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|
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module mod_clock_master(
input in_clk_12_mhz,
output out_clk_25_175_mhz,
output out_clk_166_mhz
);
// VGA has a pixel clock which defines the time between
// each consecutive pixel. For a given video mode, which is
// 640 x 480 @ 60 fps here, you need a specific pixel clock
// speed. In this case, 25.175 MHz. 'icepll -o 25.175' will
// determine the best coefficients in the PLL equation to
// get as close to this as possible (monitor is pretty
// tolerant to be slightly off).
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVF(7'b1000010),
.DIVQ(3'b101),
.DIVR(4'b0000),
.FILTER_RANGE(3'b001)
) uut (
.REFERENCECLK(in_clk_12_mhz),
.PLLOUTCORE(out_clk_25_175_mhz),
.RESETB(1'b1),
.BYPASS(1'b0)
);
// SDRAM clock 166 Mhz
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b0110110), // DIVF = 54
.DIVQ(3'b010), // DIVQ = 2
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) sdram (
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(in_clk_12_mhz),
.PLLOUTCORE(out_clk_166_mhz)
);
// TODO : Any other clocks needed elsewhere in the system..
// (PPU Clock, APU Clock, CPU Clock, RS-232)
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_BLACKBOX_V
/**
* udp_isolatchhv_pp$PLG$S: Power isolating latch (for HV). Includes
* VPWR, LVPWR, and VGND power pins with
* active high sleep pin (SLEEP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S (
UDP_OUT,
UDP_IN ,
VPWR ,
LVPWR ,
VGND ,
SLEEP
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
input LVPWR ;
input VGND ;
input SLEEP ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDLCLKP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDLCLKP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDLCLKP_BLACKBOX_V
|
module lc3_pipeline_stage4(
input reset,
input clk,
input stall,
input [5:0] state,
input [19:0] I_DR,
input [1:0] I_WBtype,
input [2:0] I_Memtype,
input [15:0] I_Res,
output [19:0] O_DR,
output reg [1:0] O_WBtype,
output [15:0] O_Res,
input [15:0] memdata,
output [15:0] memaddr,
output memtype,
output [15:0] memdatawr,
output memapply,
output reg [2:0] CC,
output inst_ld
);
reg [15:0] Res;
reg [19:0] DR;
reg [2:0] Memtype;
assign memdatawr=DR[15:0];
assign memaddr=Res;
assign memapply=Memtype[2]&state[4];
assign memtype=Memtype[0];
assign O_Res=( (memapply&~memtype)?memdata:Res );
assign O_DR=DR;
always@(negedge clk or posedge reset) begin
if(reset) begin
//nothing to do
end else begin
if(~stall) begin
DR<=I_DR;
Res<=I_Res;
Memtype<=I_Memtype;
O_WBtype<=I_WBtype;
end
end
end
always@(*) begin
if(memdata==16'b0)
CC=3'b010;
else if(memdata[15]==1)
CC=3'b100;
else
CC=3'b001;
end
assign inst_ld=Memtype[2]&~Memtype[0];
endmodule
|
// mi_nios.v
// Generated using ACDS version 14.1 186 at 2015.05.20.08:54:44
`timescale 1 ps / 1 ps
module mi_nios (
input wire clk_clk, // clk.clk
output wire flash_dclk, // flash.dclk
output wire flash_sce, // .sce
output wire flash_sdo, // .sdo
input wire flash_data0, // .data0
output wire [7:0] led_export, // led.export
input wire reset_reset_n, // reset.reset_n
output wire [11:0] sdram_addr, // sdram.addr
output wire [1:0] sdram_ba, // .ba
output wire sdram_cas_n, // .cas_n
output wire sdram_cke, // .cke
output wire sdram_cs_n, // .cs_n
inout wire [15:0] sdram_dq, // .dq
output wire [1:0] sdram_dqm, // .dqm
output wire sdram_ras_n, // .ras_n
output wire sdram_we_n, // .we_n
output wire sdram_clk_clk, // sdram_clk.clk
input wire [3:0] sw_export // sw.export
);
wire pll_c0_clk; // pll:c0 -> [cpu:clk, flash:clk, irq_mapper:clk, irq_synchronizer:sender_clk, irq_synchronizer_001:sender_clk, mm_interconnect_0:pll_c0_clk, rst_controller_001:clk, rst_controller_002:clk, sdram:clk, sysid:clock]
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
wire cpu_data_master_debugaccess; // cpu:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
wire [24:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
wire [24:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
wire mm_interconnect_0_jtag_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_avalon_jtag_slave_chipselect -> jtag:av_chipselect
wire [31:0] mm_interconnect_0_jtag_avalon_jtag_slave_readdata; // jtag:av_readdata -> mm_interconnect_0:jtag_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_avalon_jtag_slave_waitrequest; // jtag:av_waitrequest -> mm_interconnect_0:jtag_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_avalon_jtag_slave_address; // mm_interconnect_0:jtag_avalon_jtag_slave_address -> jtag:av_address
wire mm_interconnect_0_jtag_avalon_jtag_slave_read; // mm_interconnect_0:jtag_avalon_jtag_slave_read -> jtag:av_read_n
wire mm_interconnect_0_jtag_avalon_jtag_slave_write; // mm_interconnect_0:jtag_avalon_jtag_slave_write -> jtag:av_write_n
wire [31:0] mm_interconnect_0_jtag_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_avalon_jtag_slave_writedata -> jtag:av_writedata
wire [31:0] mm_interconnect_0_sysid_control_slave_readdata; // sysid:readdata -> mm_interconnect_0:sysid_control_slave_readdata
wire [0:0] mm_interconnect_0_sysid_control_slave_address; // mm_interconnect_0:sysid_control_slave_address -> sysid:address
wire mm_interconnect_0_flash_epcs_control_port_chipselect; // mm_interconnect_0:flash_epcs_control_port_chipselect -> flash:chipselect
wire [31:0] mm_interconnect_0_flash_epcs_control_port_readdata; // flash:readdata -> mm_interconnect_0:flash_epcs_control_port_readdata
wire [8:0] mm_interconnect_0_flash_epcs_control_port_address; // mm_interconnect_0:flash_epcs_control_port_address -> flash:address
wire mm_interconnect_0_flash_epcs_control_port_read; // mm_interconnect_0:flash_epcs_control_port_read -> flash:read_n
wire mm_interconnect_0_flash_epcs_control_port_write; // mm_interconnect_0:flash_epcs_control_port_write -> flash:write_n
wire [31:0] mm_interconnect_0_flash_epcs_control_port_writedata; // mm_interconnect_0:flash_epcs_control_port_writedata -> flash:writedata
wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_readdata; // cpu:jtag_debug_module_readdata -> mm_interconnect_0:cpu_jtag_debug_module_readdata
wire mm_interconnect_0_cpu_jtag_debug_module_waitrequest; // cpu:jtag_debug_module_waitrequest -> mm_interconnect_0:cpu_jtag_debug_module_waitrequest
wire mm_interconnect_0_cpu_jtag_debug_module_debugaccess; // mm_interconnect_0:cpu_jtag_debug_module_debugaccess -> cpu:jtag_debug_module_debugaccess
wire [8:0] mm_interconnect_0_cpu_jtag_debug_module_address; // mm_interconnect_0:cpu_jtag_debug_module_address -> cpu:jtag_debug_module_address
wire mm_interconnect_0_cpu_jtag_debug_module_read; // mm_interconnect_0:cpu_jtag_debug_module_read -> cpu:jtag_debug_module_read
wire [3:0] mm_interconnect_0_cpu_jtag_debug_module_byteenable; // mm_interconnect_0:cpu_jtag_debug_module_byteenable -> cpu:jtag_debug_module_byteenable
wire mm_interconnect_0_cpu_jtag_debug_module_write; // mm_interconnect_0:cpu_jtag_debug_module_write -> cpu:jtag_debug_module_write
wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_writedata; // mm_interconnect_0:cpu_jtag_debug_module_writedata -> cpu:jtag_debug_module_writedata
wire mm_interconnect_0_timer_s1_chipselect; // mm_interconnect_0:timer_s1_chipselect -> timer:chipselect
wire [15:0] mm_interconnect_0_timer_s1_readdata; // timer:readdata -> mm_interconnect_0:timer_s1_readdata
wire [2:0] mm_interconnect_0_timer_s1_address; // mm_interconnect_0:timer_s1_address -> timer:address
wire mm_interconnect_0_timer_s1_write; // mm_interconnect_0:timer_s1_write -> timer:write_n
wire [15:0] mm_interconnect_0_timer_s1_writedata; // mm_interconnect_0:timer_s1_writedata -> timer:writedata
wire [31:0] mm_interconnect_0_sw_s1_readdata; // SW:readdata -> mm_interconnect_0:SW_s1_readdata
wire [1:0] mm_interconnect_0_sw_s1_address; // mm_interconnect_0:SW_s1_address -> SW:address
wire mm_interconnect_0_led_s1_chipselect; // mm_interconnect_0:LED_s1_chipselect -> LED:chipselect
wire [31:0] mm_interconnect_0_led_s1_readdata; // LED:readdata -> mm_interconnect_0:LED_s1_readdata
wire [1:0] mm_interconnect_0_led_s1_address; // mm_interconnect_0:LED_s1_address -> LED:address
wire mm_interconnect_0_led_s1_write; // mm_interconnect_0:LED_s1_write -> LED:write_n
wire [31:0] mm_interconnect_0_led_s1_writedata; // mm_interconnect_0:LED_s1_writedata -> LED:writedata
wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:sdram_s1_chipselect -> sdram:az_cs
wire [15:0] mm_interconnect_0_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_0:sdram_s1_readdata
wire mm_interconnect_0_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_0:sdram_s1_waitrequest
wire [21:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:sdram_s1_address -> sdram:az_addr
wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:sdram_s1_read -> sdram:az_rd_n
wire [1:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:sdram_s1_byteenable -> sdram:az_be_n
wire mm_interconnect_0_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_0:sdram_s1_readdatavalid
wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:sdram_s1_write -> sdram:az_wr_n
wire [15:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:sdram_s1_writedata -> sdram:az_data
wire irq_mapper_receiver2_irq; // flash:irq -> irq_mapper:receiver2_irq
wire [31:0] cpu_d_irq_irq; // irq_mapper:sender_irq -> cpu:d_irq
wire irq_mapper_receiver0_irq; // irq_synchronizer:sender_irq -> irq_mapper:receiver0_irq
wire [0:0] irq_synchronizer_receiver_irq; // jtag:av_irq -> irq_synchronizer:receiver_irq
wire irq_mapper_receiver1_irq; // irq_synchronizer_001:sender_irq -> irq_mapper:receiver1_irq
wire [0:0] irq_synchronizer_001_receiver_irq; // timer:irq -> irq_synchronizer_001:receiver_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LED:reset_n, SW:reset_n, irq_synchronizer:receiver_reset, irq_synchronizer_001:receiver_reset, jtag:rst_n, mm_interconnect_0:jtag_reset_reset_bridge_in_reset_reset, pll:reset, timer:reset_n]
wire cpu_jtag_debug_module_reset_reset; // cpu:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_002:reset_in1]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [cpu:reset_n, irq_mapper:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, mm_interconnect_0:cpu_reset_n_reset_bridge_in_reset_reset, rst_translator:in_reset, sysid:reset_n]
wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [cpu:reset_req, rst_translator:reset_req_in]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [flash:reset_n, mm_interconnect_0:flash_reset_reset_bridge_in_reset_reset, sdram:reset_n]
wire rst_controller_002_reset_out_reset_req; // rst_controller_002:reset_req -> [flash:reset_req, rst_translator_001:reset_req_in]
mi_nios_LED led (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_led_s1_address), // s1.address
.write_n (~mm_interconnect_0_led_s1_write), // .write_n
.writedata (mm_interconnect_0_led_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_led_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_led_s1_readdata), // .readdata
.out_port (led_export) // external_connection.export
);
mi_nios_SW sw (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sw_s1_address), // s1.address
.readdata (mm_interconnect_0_sw_s1_readdata), // .readdata
.in_port (sw_export) // external_connection.export
);
mi_nios_cpu cpu (
.clk (pll_c0_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset_n.reset_n
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.d_address (cpu_data_master_address), // data_master.address
.d_byteenable (cpu_data_master_byteenable), // .byteenable
.d_read (cpu_data_master_read), // .read
.d_readdata (cpu_data_master_readdata), // .readdata
.d_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.d_write (cpu_data_master_write), // .write
.d_writedata (cpu_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess
.i_address (cpu_instruction_master_address), // instruction_master.address
.i_read (cpu_instruction_master_read), // .read
.i_readdata (cpu_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (cpu_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
.jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable
.jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess
.jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read
.jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata
.jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest
.jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write
.jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
mi_nios_flash flash (
.clk (pll_c0_clk), // clk.clk
.reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_002_reset_out_reset_req), // .reset_req
.address (mm_interconnect_0_flash_epcs_control_port_address), // epcs_control_port.address
.chipselect (mm_interconnect_0_flash_epcs_control_port_chipselect), // .chipselect
.read_n (~mm_interconnect_0_flash_epcs_control_port_read), // .read_n
.readdata (mm_interconnect_0_flash_epcs_control_port_readdata), // .readdata
.write_n (~mm_interconnect_0_flash_epcs_control_port_write), // .write_n
.writedata (mm_interconnect_0_flash_epcs_control_port_writedata), // .writedata
.irq (irq_mapper_receiver2_irq), // irq.irq
.dclk (flash_dclk), // external.export
.sce (flash_sce), // .export
.sdo (flash_sdo), // .export
.data0 (flash_data0) // .export
);
mi_nios_jtag jtag (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_synchronizer_receiver_irq) // irq.irq
);
mi_nios_pll pll (
.clk (clk_clk), // inclk_interface.clk
.reset (rst_controller_reset_out_reset), // inclk_interface_reset.reset
.read (), // pll_slave.read
.write (), // .write
.address (), // .address
.readdata (), // .readdata
.writedata (), // .writedata
.c0 (pll_c0_clk), // c0.clk
.c1 (sdram_clk_clk), // c1.clk
.areset (), // areset_conduit.export
.locked (), // locked_conduit.export
.phasedone () // phasedone_conduit.export
);
mi_nios_sdram sdram (
.clk (pll_c0_clk), // clk.clk
.reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.zs_addr (sdram_addr), // wire.export
.zs_ba (sdram_ba), // .export
.zs_cas_n (sdram_cas_n), // .export
.zs_cke (sdram_cke), // .export
.zs_cs_n (sdram_cs_n), // .export
.zs_dq (sdram_dq), // .export
.zs_dqm (sdram_dqm), // .export
.zs_ras_n (sdram_ras_n), // .export
.zs_we_n (sdram_we_n) // .export
);
mi_nios_sysid sysid (
.clock (pll_c0_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_0_sysid_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_0_sysid_control_slave_address) // .address
);
mi_nios_timer timer (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_timer_s1_address), // s1.address
.writedata (mm_interconnect_0_timer_s1_writedata), // .writedata
.readdata (mm_interconnect_0_timer_s1_readdata), // .readdata
.chipselect (mm_interconnect_0_timer_s1_chipselect), // .chipselect
.write_n (~mm_interconnect_0_timer_s1_write), // .write_n
.irq (irq_synchronizer_001_receiver_irq) // irq.irq
);
mi_nios_mm_interconnect_0 mm_interconnect_0 (
.clk_50_clk_clk (clk_clk), // clk_50_clk.clk
.pll_c0_clk (pll_c0_clk), // pll_c0.clk
.cpu_reset_n_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // cpu_reset_n_reset_bridge_in_reset.reset
.flash_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // flash_reset_reset_bridge_in_reset.reset
.jtag_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // jtag_reset_reset_bridge_in_reset.reset
.cpu_data_master_address (cpu_data_master_address), // cpu_data_master.address
.cpu_data_master_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.cpu_data_master_byteenable (cpu_data_master_byteenable), // .byteenable
.cpu_data_master_read (cpu_data_master_read), // .read
.cpu_data_master_readdata (cpu_data_master_readdata), // .readdata
.cpu_data_master_write (cpu_data_master_write), // .write
.cpu_data_master_writedata (cpu_data_master_writedata), // .writedata
.cpu_data_master_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.cpu_instruction_master_address (cpu_instruction_master_address), // cpu_instruction_master.address
.cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.cpu_instruction_master_read (cpu_instruction_master_read), // .read
.cpu_instruction_master_readdata (cpu_instruction_master_readdata), // .readdata
.cpu_jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // cpu_jtag_debug_module.address
.cpu_jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write
.cpu_jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read
.cpu_jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata
.cpu_jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata
.cpu_jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable
.cpu_jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest
.cpu_jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess
.flash_epcs_control_port_address (mm_interconnect_0_flash_epcs_control_port_address), // flash_epcs_control_port.address
.flash_epcs_control_port_write (mm_interconnect_0_flash_epcs_control_port_write), // .write
.flash_epcs_control_port_read (mm_interconnect_0_flash_epcs_control_port_read), // .read
.flash_epcs_control_port_readdata (mm_interconnect_0_flash_epcs_control_port_readdata), // .readdata
.flash_epcs_control_port_writedata (mm_interconnect_0_flash_epcs_control_port_writedata), // .writedata
.flash_epcs_control_port_chipselect (mm_interconnect_0_flash_epcs_control_port_chipselect), // .chipselect
.jtag_avalon_jtag_slave_address (mm_interconnect_0_jtag_avalon_jtag_slave_address), // jtag_avalon_jtag_slave.address
.jtag_avalon_jtag_slave_write (mm_interconnect_0_jtag_avalon_jtag_slave_write), // .write
.jtag_avalon_jtag_slave_read (mm_interconnect_0_jtag_avalon_jtag_slave_read), // .read
.jtag_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_avalon_jtag_slave_readdata), // .readdata
.jtag_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_avalon_jtag_slave_writedata), // .writedata
.jtag_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_avalon_jtag_slave_chipselect), // .chipselect
.LED_s1_address (mm_interconnect_0_led_s1_address), // LED_s1.address
.LED_s1_write (mm_interconnect_0_led_s1_write), // .write
.LED_s1_readdata (mm_interconnect_0_led_s1_readdata), // .readdata
.LED_s1_writedata (mm_interconnect_0_led_s1_writedata), // .writedata
.LED_s1_chipselect (mm_interconnect_0_led_s1_chipselect), // .chipselect
.sdram_s1_address (mm_interconnect_0_sdram_s1_address), // sdram_s1.address
.sdram_s1_write (mm_interconnect_0_sdram_s1_write), // .write
.sdram_s1_read (mm_interconnect_0_sdram_s1_read), // .read
.sdram_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata
.sdram_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata
.sdram_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable
.sdram_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.sdram_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.sdram_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.SW_s1_address (mm_interconnect_0_sw_s1_address), // SW_s1.address
.SW_s1_readdata (mm_interconnect_0_sw_s1_readdata), // .readdata
.sysid_control_slave_address (mm_interconnect_0_sysid_control_slave_address), // sysid_control_slave.address
.sysid_control_slave_readdata (mm_interconnect_0_sysid_control_slave_readdata), // .readdata
.timer_s1_address (mm_interconnect_0_timer_s1_address), // timer_s1.address
.timer_s1_write (mm_interconnect_0_timer_s1_write), // .write
.timer_s1_readdata (mm_interconnect_0_timer_s1_readdata), // .readdata
.timer_s1_writedata (mm_interconnect_0_timer_s1_writedata), // .writedata
.timer_s1_chipselect (mm_interconnect_0_timer_s1_chipselect) // .chipselect
);
mi_nios_irq_mapper irq_mapper (
.clk (pll_c0_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.sender_irq (cpu_d_irq_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer (
.receiver_clk (clk_clk), // receiver_clk.clk
.sender_clk (pll_c0_clk), // sender_clk.clk
.receiver_reset (rst_controller_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_001_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver0_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_001 (
.receiver_clk (clk_clk), // receiver_clk.clk
.sender_clk (pll_c0_clk), // sender_clk.clk
.receiver_reset (rst_controller_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_001_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_001_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver1_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (pll_c0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (pll_c0_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_002_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4B_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NAND4B_BEHAVIORAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4B_BEHAVIORAL_V |
//----------------------------------------------------------------------------
// Wishbone Tube controller
//----------------------------------------------------------------------------
module wb_tube #(
parameter latency = 0 // 0 .. 7
) (
input clk,
input reset,
// Wishbone interface
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
input wb_we_i,
input [2:0] wb_adr_i,
input [3:0] wb_sel_i,
input [31:0] wb_dat_i,
output reg [31:0] wb_dat_o,
// TUBE connection
output reg [2:0] tube_adr,
inout [7:0] tube_dat,
output reg tube_cs_n, // Chip Select
output reg tube_rd_n, // Read
output reg tube_wr_n // Write
);
//----------------------------------------------------------------------------
//
//----------------------------------------------------------------------------
// Wishbone handling
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i & ~wb_ack_o;
// Tri-State-Driver
reg [7:0] wdat;
reg wdat_oe;
assign tube_dat = wdat_oe ? wdat : 8'bz;
// Latency countdown
reg [2:0] lcount;
//----------------------------------------------------------------------------
// State Machine
//----------------------------------------------------------------------------
parameter s_idle = 0;
parameter s_read = 1;
parameter s_write = 2;
reg [2:0] state;
always @(posedge clk)
begin
if (reset) begin
state <= s_idle;
lcount <= 0;
wb_ack_o <= 0;
end else begin
case (state)
s_idle: begin
wb_ack_o <= 0;
if (wb_rd) begin
tube_cs_n <= 0;
tube_rd_n <= 0;
tube_wr_n <= 1;
tube_adr <= wb_adr_i;
wdat_oe <= 0;
lcount <= latency;
state <= s_read;
end else if (wb_wr) begin
tube_cs_n <= 0;
tube_rd_n <= 1;
tube_wr_n <= 0;
tube_adr <= wb_adr_i;
wdat <= wb_dat_i[7:0];
wdat_oe <= 1;
lcount <= latency;
state <= s_write;
end else begin
tube_cs_n <= 1;
tube_rd_n <= 1;
tube_wr_n <= 1;
wdat_oe <= 0;
end
end
s_read: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
tube_cs_n <= 1;
tube_rd_n <= 1;
tube_wr_n <= 1;
wb_dat_o <= tube_dat;
wb_ack_o <= 1;
state <= s_idle;
end
end
s_write: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
tube_cs_n <= 1;
tube_rd_n <= 1;
tube_wr_n <= 1;
wb_ack_o <= 1; // XXX We could acknoledge write XXX
state <= s_idle; // XXX requests 1 cycle ahead XXX
end
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__AND4_BEHAVIORAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211OI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A211OI_BLACKBOX_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a211oi (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211OI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_2_V
`define SKY130_FD_SC_LP__NOR2B_2_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2b_2 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2b_2 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_2_V
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2011 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Extraction to Ocaml : use of basic Ocaml types *)
Scheme Equality for nat.
Extract Inductive bool => bool [ true false ].
Extract Inductive option => option [ Some None ].
Extract Inductive unit => unit [ "()" ].
Extract Inductive list => list [ "[]" "( :: )" ].
Extract Inductive prod => "( * )" [ "" ].
(** NB: The "" above is a hack, but produce nicer code than "(,)" *)
(** Mapping sumbool to bool and sumor to option is not always nicer,
but it helps when realizing stuff like [lt_eq_lt_dec] *)
Extract Inductive sumbool => bool [ true false ].
Extract Inductive sumor => option [ Some None ].
(** Restore lazyness of andb, orb.
NB: without these Extract Constant, andb/orb would be inlined
by extraction in order to have lazyness, producing inelegant
(if ... then ... else false) and (if ... then true else ...).
*)
Extract Inlined Constant andb => "(&&)".
Extract Inlined Constant orb => "(||)".
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpll0.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 153 11/29/2010 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpll0 (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
wire [5:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 4,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 31250,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "160.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "32.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "31250"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//==========================================
// Function : Code Gray counter.
// Coder : Alex Claros F.
// Date : 15/May/2005.
//=======================================
`timescale 1ns/1ps
module GrayCounter
#(parameter COUNTER_WIDTH = 4)
(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire Clear_in, //Count reset.
input wire Clk);
/////////Internal connections & variables///////
reg [COUNTER_WIDTH-1:0] BinaryCount;
/////////Code///////////////////////
always @ (posedge Clk)
if (Clear_in) begin
BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'.
end
else if (Enable_in) begin
BinaryCount <= BinaryCount + 1;
GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
end
endmodule
|
(****************************************************************************)
(* Copyright 2021 The Project Oak Authors *)
(* *)
(* Licensed under the Apache License, Version 2.0 (the "License") *)
(* you may not use this file except in compliance with the License. *)
(* You may obtain a copy of the License at *)
(* *)
(* http://www.apache.org/licenses/LICENSE-2.0 *)
(* *)
(* Unless required by applicable law or agreed to in writing, software *)
(* distributed under the License is distributed on an "AS IS" BASIS, *)
(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *)
(* See the License for the specific language governing permissions and *)
(* limitations under the License. *)
(****************************************************************************)
Require Import Coq.Lists.List.
Require Import Coq.NArith.NArith.
Require Import Coq.ZArith.ZArith.
Require Import Cava.Types.
Require Import Cava.Expr.
Require Import Cava.Semantics.
Local Open Scope N_scope.
Require Import Coq.micromega.Lia.
Require Import coqutil.Tactics.Tactics.
Require Import Cava.Util.List.
Require Import Cava.Util.Nat.
Require Import Cava.Util.Tactics.
Require Import Cava.ExprProperties.
Definition invariant_for {s i o} (c : Circuit (var:=denote_type) s i o)
(repr : Type) : Type := denote_type s -> repr -> Prop.
Existing Class invariant_for.
Class specification_for {s i o} (c : Circuit (var:=denote_type) s i o)
(repr : Type) :=
{ reset_repr : repr;
update_repr : denote_type i -> repr -> repr;
precondition : denote_type i -> repr -> Prop;
postcondition : denote_type i -> repr -> denote_type o -> Prop;
}.
Global Arguments precondition {_ _ _} _ {_ _}.
Global Arguments postcondition {_ _ _} _ {_ _}.
Definition invariant_at_reset {s i o} (c : Circuit s i o)
{repr} {invariant : invariant_for c repr}
{spec : specification_for c repr} : Prop :=
invariant (reset_state c) reset_repr.
Existing Class invariant_at_reset.
Definition invariant_preserved {s i o} (c : Circuit s i o)
{repr} {invariant : invariant_for c repr}
{spec : specification_for c repr} : Prop :=
forall input state r new_r,
new_r = update_repr input r ->
invariant state r ->
precondition c input r ->
invariant (fst (step c state input)) new_r.
Existing Class invariant_preserved.
Definition output_correct {s i o} (c : Circuit s i o)
{repr} {invariant : invariant_for c repr}
{spec : specification_for c repr} : Prop :=
forall input state r,
invariant state r ->
precondition c input r ->
postcondition c input r (snd (step c state input)).
Existing Class output_correct.
Class correctness_for {s i o} (c : Circuit s i o)
{repr} {invariant : invariant_for c repr}
{spec : specification_for c repr} : Prop :=
{ invariant_at_reset_pf : invariant_at_reset c;
invariant_preserved_pf : invariant_preserved c;
output_correct_pf : output_correct c }.
(* Switch between higher-level representations *)
Definition invariant_by_isomorphism {s i o} {c : Circuit s i o}
{s1 s2} (phi : s1 -> s2) (inv : s2 -> s1)
{invariant : invariant_for c s1}
: invariant_for c s2 :=
fun (state : denote_type s) x => invariant state (inv x).
Definition specification_by_isomorphism {s i o} {c : Circuit s i o}
{s1 s2} (phi : s1 -> s2) (inv : s2 -> s1)
{spec : specification_for c s1}
: specification_for c s2 :=
{| reset_repr := phi (reset_repr);
update_repr := fun i x => phi (update_repr i (inv x));
precondition := fun i x => precondition c i (inv x);
postcondition := fun i x => postcondition c i (inv x);
|}.
(* Succeeds if an instance is found for circuit correctness *)
Ltac find_correctness c :=
let x := constr:(_:correctness_for c) in
idtac.
Ltac simplify_invariant c :=
cbv [invariant_at_reset invariant_preserved output_correct];
let x := constr:(_:invariant_for c _) in
let x := app_head x in
match x with
| ?x => cbv [x] in *
end.
Ltac simplify_spec c :=
let x := constr:(_:specification_for c _) in
let x := app_head x in
match x with
| ?x => cbn [x update_repr precondition postcondition] in *
end.
Ltac simplify_postcondition c :=
let x := constr:((_ : specification_for c _)) in
let x := app_head x in
match x with
| ?x => cbn[x postcondition] in *
end.
(* if a subcircuit is found that has an invariant-based correctness proof, use
the correctness proof to replace the circuit step function with the
spec. Uses [eauto] to solve the side conditions of the output-correctness
proof. *)
Ltac use_correctness' c :=
lazymatch goal with
| |- context [ @snd ?A ?B (@step ?i ?s ?o c ?state ?input) ] =>
find_correctness c;
pose proof (@output_correct_pf
s i o c _ _ _ _
input state _ ltac:(eassumption) ltac:(eassumption));
generalize dependent (@snd A B (@step i s o c state input)); intros;
try simplify_postcondition c; logical_simplify; subst
end.
Ltac use_correctness :=
match goal with
| |- context [match @step ?i ?s ?o ?c ?state ?input with pair _ _ => _ end] =>
find_correctness c;
rewrite (surjective_pairing (@step i s o c state input));
use_correctness' c
end.
Section StateLogicProofs.
Context {s i o} (c : Circuit (var:=denote_type) s i o).
Context {repr} {invariant : invariant_for c repr}
{spec : specification_for c repr}
{correctness : correctness_for c}.
(* the representation after processing the given input *)
Definition repeat_update_repr
(start : repr) (input : list (denote_type i)) : repr :=
fold_left (fun s i => update_repr i s) input start.
(* states that the precondition holds for each cycle *)
Definition precondition_holds_big_step start input : Prop :=
(forall n,
(n < length input)%nat ->
precondition c (nth n input default)
(repeat_update_repr start (firstn n input))).
Lemma invariant_holds_big_step' start_repr start_state input :
precondition_holds_big_step start_repr input ->
invariant start_state start_repr ->
invariant (snd (simulate' c input start_state))
(repeat_update_repr start_repr input).
Proof.
intros. cbv [simulate' repeat_update_repr].
induction input using rev_ind; [ assumption | ].
rewrite fold_left_accumulate'_is_splittable.
repeat destruct_pair_let; cbn [fst snd].
rewrite fold_left_accumulate'_cons_snd.
cbn [app fold_left_accumulate' fold_left fst snd].
lazymatch goal with H : precondition_holds_big_step _ _ |- _ =>
rename H into Hpre end.
eapply invariant_preserved_pf.
{ pull_snoc. reflexivity. }
{ apply IHinput; [ ].
cbv [precondition_holds_big_step] in *.
intro n; intros; specialize (Hpre n ltac:(length_hammer)).
rewrite app_nth1 in Hpre by length_hammer.
autorewrite with push_firstn in Hpre.
replace (n - length input)%nat with 0%nat in * by lia.
autorewrite with push_firstn listsimpl in Hpre.
auto. }
{ cbv [precondition_holds_big_step] in *.
specialize (Hpre (length input) ltac:(length_hammer)).
rewrite app_nth2 in Hpre by length_hammer.
autorewrite with push_firstn natsimpl push_nth listsimpl in Hpre.
apply Hpre. }
Qed.
Lemma invariant_holds_big_step input :
precondition_holds_big_step reset_repr input ->
invariant (snd (simulate' c input (reset_state c)))
(repeat_update_repr reset_repr input).
Proof.
intros; apply invariant_holds_big_step'; auto; [ ].
apply invariant_at_reset_pf.
Qed.
Lemma postcondition_holds_big_step input last_input :
precondition_holds_big_step reset_repr input ->
precondition c last_input (repeat_update_repr reset_repr input) ->
postcondition c last_input (repeat_update_repr reset_repr input)
(snd (step c (snd (simulate' c input (reset_state c)))
last_input)).
Proof.
intros. apply output_correct_pf; [ | assumption ].
apply invariant_holds_big_step. auto.
Qed.
Lemma simulate_invariant_logic input output_func :
(* precondition holds for each cycle *)
precondition_holds_big_step reset_repr input ->
(* the postcondition fully specifies the output *)
(forall i s x, postcondition c i s x -> x = output_func i s) ->
simulate c input = fold_left_accumulate
(fun s i => (update_repr i s, output_func i s))
input reset_repr.
Proof.
intros. cbv [precondition_holds_big_step] in *.
change (simulate c input) with
(fold_left_accumulate (step c) input (reset_state c)).
rewrite !fold_left_accumulate_to_seq with (default:=default).
eapply fold_left_accumulate_double_invariant_seq
with (I:=fun i s1 s2 acc1 acc2 =>
s2 = repeat_update_repr reset_repr (firstn i input)
/\ invariant s1 s2
/\ acc1 = acc2).
{ ssplit; subst; [ reflexivity | | reflexivity ].
apply invariant_at_reset_pf. }
{ intros; logical_simplify; subst.
cbn [fst snd] in *. ssplit.
{ cbv [repeat_update_repr].
rewrite firstn_succ_snoc with (d:=default) by lia.
pull_snoc. reflexivity. }
{ eauto using invariant_preserved_pf. }
{ lazymatch goal with H : context [_ = output_func _ _] |- _ =>
erewrite <-H; [ reflexivity | ] end.
apply output_correct_pf; auto. } }
{ intros; logical_simplify; subst. reflexivity. }
Qed.
(* if there's an isomorphism between two higher-level states, then invariant
logic and correctness proofs can be ported between them. *)
Lemma invariant_logic_isomorphism_correct
(repr' : Type) (phi : repr -> repr') (inv : repr' -> repr) :
(forall x, inv (phi x) = x) ->
correctness_for (invariant:=invariant_by_isomorphism phi inv)
(spec:=specification_by_isomorphism phi inv) c.
Proof.
intros Hphi.
constructor; cbv [invariant_at_reset invariant_preserved output_correct
specification_by_isomorphism
invariant_by_isomorphism].
all:cbn [reset_repr precondition postcondition].
all:rewrite ?Hphi; intros; subst.
all:eauto using invariant_preserved_pf, output_correct_pf.
all:eapply invariant_at_reset_pf.
Qed.
End StateLogicProofs.
(**** Example usage of invariant logic for counters ****)
Module DoubleCounterExample.
Section CircuitDefinitions.
Context {var : tvar}.
Import ExprNotations.
Import PrimitiveNotations.
(* Circuit which takes a bit indicating whether to increment or not, and if
the bit is true increments an 8-bit counter by 1 each cycle. The counter
truncates on overflow and returns the counter value along with a bit
indicating whether the counter overflowed. *)
Definition counter : Circuit (BitVec 8 ** Bit) [Bit] (BitVec 8 ** Bit) :=
{{ fun enable =>
let/delay '(data; overflow) :=
(if !enable
then (data,`Zero`)
else
let new_overflow := data == `K (N.ones 8)` in
let new_data := data + `K 1` in
(new_data, new_overflow))
initially
((0,false) : denote_type (BitVec 8 ** Bit)) in
(data,overflow)
}}.
(* Creates a 16-bit counter out of two 8-bit counters *)
Definition double_counter : Circuit _ [Bit] (BitVec 16 ** Bit) :=
{{ fun enable =>
let '(low; low_overflow) := `counter` enable in
let '(high; high_overflow) := `counter` low_overflow in
(`bvresize 16` (`bvconcat` high low), high_overflow) }}.
End CircuitDefinitions.
Section Specifications.
Global Instance counter_specification
: specification_for counter N :=
{| reset_repr := 0;
update_repr :=
fun (input : denote_type [Bit]) value =>
let '(enable,_) := input in
(* if enabled, add 1 mod 2^n, else do nothing *)
if enable
then ((value + 1) mod (2 ^ 8))%N
else value;
precondition := fun _ _ => True;
postcondition :=
fun input value (output : denote_type (BitVec 8 ** Bit)) =>
let '(enable,_) := input in
let new_val := if enable then (value + 1)%N else value in
output = (new_val mod (2 ^ 8), 2 ^ 8 <=? new_val)
|}.
Global Instance counter_invariant : invariant_for counter N :=
fun (state : denote_type (BitVec 8 ** _)) value =>
let '(data,_) := state in
(* value is exactly equivalent to [data] *)
data = value
(* ...and value < 2 ^ 8 *)
/\ value < 2 ^ 8.
(* Almost identical to the counter specification *)
Global Instance double_counter_specification
: specification_for double_counter N :=
{| reset_repr := 0;
update_repr :=
fun (input : denote_type [Bit]) value =>
let '(enable,_) := input in
(* if enabled, add 1 mod 2^n, else do nothing *)
if enable
then ((value + 1) mod (2 ^ 16))%N
else value;
precondition := fun _ _ => True;
postcondition :=
fun input value (output : denote_type (BitVec 16 ** Bit)) =>
let '(enable,_) := input in
let new_val := if enable then (value + 1)%N else value in
output = (new_val mod (2 ^ 16), 2 ^ 16 <=? new_val)
|}.
Global Instance double_counter_invariant_logic
: invariant_for double_counter N :=
fun (state : denote_type (state_of counter
** state_of counter)) value =>
let '(counter1_state, counter2_state) := state in
(* counter1_state matches the low part of the counter value *)
counter_invariant counter1_state (value mod 2 ^ 8)%N
(* ...and counter2_state matches the high part of the counter value *)
/\ counter_invariant counter2_state (value / 2 ^ 8)%N
(* ...and the value is < 2 ^ 16 (this is implied by the other two but
convenient to have without unfolding [counter_invariant]) *)
/\ value < 2 ^ 16.
End Specifications.
Section Proofs.
Lemma counter_invariant_at_reset : invariant_at_reset counter.
Proof.
simplify_invariant counter.
cbv [counter]. cbn [reset_state]; stepsimpl.
simplify_invariant counter.
ssplit; [ reflexivity | ]. cbn; lia.
Qed.
Lemma counter_invariant_preserved : invariant_preserved counter.
Proof.
intros (enable,[]) (data, ?) value. intros; subst.
simplify_invariant counter. simplify_spec counter.
cbv [counter]. stepsimpl. logical_simplify; subst.
destruct enable; cbn [negb fst snd].
all:ssplit; first [ lia | reflexivity
| apply N.mod_bound_pos; lia ].
Qed.
Lemma counter_output_correct : output_correct counter.
Proof.
intros (enable,[]) (data, ?) value.
simplify_invariant counter.
intros; logical_simplify; subst.
simplify_spec counter.
cbv [counter]. stepsimpl. compute_expr (N.of_nat 8).
change (2 ^ 8) with 256 in *.
change (N.ones 8) with 255 in *.
destruct enable; cbn [negb fst snd].
all:repeat lazymatch goal with
| |- context [N.eqb ?x ?y] => destr (N.eqb x y); subst
| |- context [N.leb ?x ?y] => destr (N.leb x y)
| _ => lia || reflexivity
end.
all:rewrite N.mod_small by lia; reflexivity.
Qed.
Existing Instances counter_invariant_at_reset counter_invariant_preserved
counter_output_correct.
Global Instance counter_correctness : correctness_for counter.
Proof. constructor; typeclasses eauto. Defined.
Lemma double_counter_invariant_at_reset : invariant_at_reset double_counter.
Proof.
simplify_invariant double_counter.
cbn [double_counter reset_state].
stepsimpl. rewrite N.mod_0_l, N.div_0_l by (cbn; lia).
ssplit; [ eapply counter_invariant_at_reset .. | ].
cbn; lia.
Qed.
Lemma double_counter_invariant_preserved : invariant_preserved double_counter.
Proof.
cbv [invariant_preserved]. intros (enable,[]) (data,?) value.
intros; subst. simplify_invariant double_counter.
cbv [double_counter]. stepsimpl. logical_simplify; subst.
repeat use_correctness. stepsimpl.
simplify_spec double_counter.
ssplit.
{ eapply (invariant_preserved_pf (c:=counter));
[ | solve [eauto] .. ].
simplify_spec counter.
destruct enable; [ | reflexivity ].
change (2 ^ 8) with 256 in *. change (2 ^ 16) with 65536 in *.
Zify.zify. Z.to_euclidean_division_equations. lia. }
{ eapply (invariant_preserved_pf (c:=counter));
[ | solve [eauto] .. ].
simplify_spec counter.
change (2 ^ 8) with 256 in *. change (2 ^ 16) with 65536 in *.
repeat (destruct_one_match; try lia).
(* extra step to help lia out, otherwise hangs *)
all:try rewrite N.mod_mul_div_r with (b:=256) (c:=256) by lia.
all:Zify.zify; Z.to_euclidean_division_equations; lia. }
{ destruct enable; [ | lia ].
apply N.mod_bound_pos; lia. }
Qed.
Lemma double_counter_output_correct : output_correct double_counter.
Proof.
cbv [output_correct]. intros (enable,[]) (data, ?) value.
simplify_invariant double_counter.
simplify_spec double_counter.
intros; logical_simplify; subst.
cbv [double_counter]. stepsimpl.
repeat use_correctness. stepsimpl.
f_equal.
{ (* counter values match *)
compute_expr (N.of_nat 8). compute_expr (8 + 8)%nat.
compute_expr (N.of_nat 16).
rewrite !N.shiftl_mul_pow2, !N.land_ones.
change (2 ^ 8) with 256 in *. change (2 ^ 16) with 65536 in *.
rewrite !(N.mod_small (_ mod 256) 65536)
by (eapply N.lt_le_trans; [ apply N.mod_bound_pos | ]; lia).
rewrite N.lor_high_low_add with (b:=8). change (2 ^ 8) with 256 in *.
repeat destruct_one_match.
(* the below rewrite improves performance of lia *)
all:rewrite ?N.mod_mod by lia.
all:Zify.zify; Z.to_euclidean_division_equations; lia. }
{ change (2 ^ 8) with 256 in *. change (2 ^ 16) with 65536 in *.
repeat destruct_one_match.
all:repeat lazymatch goal with |- context [N.leb ?x ?y] =>
destr (N.leb x y) end.
all:try reflexivity.
all:Zify.zify; Z.to_euclidean_division_equations; lia. }
Qed.
Existing Instances double_counter_invariant_at_reset double_counter_invariant_preserved
double_counter_output_correct.
Global Instance double_counter_correctness : correctness_for double_counter.
Proof. constructor; typeclasses eauto. Defined.
End Proofs.
End DoubleCounterExample.
(**** Example usage of invariant logic for circuit with abstract subcircuit ****)
Module AbstractSubcircuitExample.
Section CircuitDefinitions.
Context {var : tvar}.
Import ExprNotations.
Import PrimitiveNotations.
(* Somewhat contrived circuit that takes in two streams of inputs of some
type, and always returns the smallest input seen so far.
* The [cmp] subcircuit returns true if the first argument is <= the
second, and false otherwise.
* The [minimum] subcircuit has the same idea but with a single stream of
inputs; its output is the smallest input seen so far.
*)
Definition double_minimum
{T minimum_state} (cmp : Circuit [] [T;T] Bit)
(minimum : Circuit minimum_state [T] T)
: Circuit _ [T;T] T :=
{{ fun input1 input2 =>
let min1 := `minimum` input1 in
let min2 := `minimum` input2 in
let min1_le_min2 := `cmp` min1 min2 in
if min1_le_min2 then min1 else min2
}}.
End CircuitDefinitions.
Section SpecificationsAndProofs.
Context {T : type}
(* some order exists on type T *)
(rankT : denote_type T -> N).
Context (cmp : Circuit [] [T;T] Bit)
{minimum_state} (minimum : Circuit minimum_state [T] T)
{minimum_invariant : invariant_for minimum (list (denote_type T))}.
(* high-level representation here is also the list of inputs so far *)
Global Instance minimum_specification
: specification_for minimum (list (denote_type T)) :=
{| reset_repr := List.nil;
update_repr :=
fun (input : denote_type [T]) (acc : list (denote_type T)) =>
let '(x,_) := input in
x :: acc;
precondition := fun _ _ => True;
postcondition :=
fun input acc out =>
let '(x,_) := input in
Forall (fun y => rankT out <= rankT y) (x :: acc);
|}.
(* Almost the same as minimum_specification *)
Instance double_minimum_specification
: specification_for (double_minimum cmp minimum) (list (denote_type T)) :=
{| reset_repr := List.nil;
update_repr :=
fun (input : denote_type [T;T]) (acc : list (denote_type T)) =>
let '(x,(y,_)) := input in
x :: y :: acc;
precondition := fun _ _ => True;
postcondition :=
fun input acc out =>
let '(x,(y,_)) := input in
Forall (fun y => rankT out <= rankT y) (x :: y :: acc);
|}.
Instance double_minimum_invariant
: invariant_for (double_minimum cmp minimum) (list (denote_type T)) :=
fun (state : denote_type (minimum_state ++ minimum_state ++ []))
(acc : list (denote_type T)) =>
let '(state1, state) := split_absorbed_denotation state in
let '(state2, _) := split_absorbed_denotation state in
exists acc1 acc2,
minimum_invariant state1 acc1
/\ minimum_invariant state2 acc2
(* acc1 ++ acc2 is a permutation of acc *)
/\ (forall x, In x (acc1 ++ acc2) -> In x acc)
/\ (forall x, In x acc -> In x (acc1 ++ acc2)).
Section Proofs.
Context (cmp_correct :
forall x y, step cmp tt (x,(y,tt)) = (tt, rankT x <=? rankT y))
(minimum_correctness : correctness_for minimum).
Hint Rewrite cmp_correct : stepsimpl.
Lemma split_combine_denotation
{t1 t2} (x : denote_type t1) (y : denote_type t2) :
split_absorbed_denotation (combine_absorbed_denotation x y) = (x,y).
Proof.
induction t1; destruct t2.
all:cbn [split_absorbed_denotation combine_absorbed_denotation denote_type] in *.
all:logical_simplify; subst.
all:repeat lazymatch goal with x : unit |- _ => destruct x end.
all:reflexivity.
Qed.
Lemma combine_split_denotation
{t1 t2} (xy : denote_type (t1 ++ t2)) :
combine_absorbed_denotation
(fst (split_absorbed_denotation xy))
(snd (split_absorbed_denotation xy)) = xy.
Proof.
induction t1; destruct t2.
all:cbn [split_absorbed_denotation combine_absorbed_denotation
denote_type absorb_any fst snd] in *.
all:logical_simplify; subst.
all:repeat lazymatch goal with x : unit |- _ => destruct x end.
all:rewrite <-?surjective_pairing.
all:reflexivity.
Qed.
Lemma double_minimum_invariant_at_reset
: invariant_at_reset (double_minimum cmp minimum).
Proof.
simplify_invariant (double_minimum cmp minimum).
cbn [double_minimum reset_state]. stepsimpl.
rewrite !split_combine_denotation.
exists nil, nil.
ssplit.
{ exact (invariant_at_reset_pf (c:=minimum)). }
{ exact (invariant_at_reset_pf (c:=minimum)). }
{ cbn [app In]; tauto. }
{ cbn [reset_repr double_minimum_specification app In].
tauto. }
Qed.
Lemma double_minimum_invariant_preserved : invariant_preserved (double_minimum cmp minimum).
Proof.
cbv [invariant_preserved]. cbn [absorb_any].
intros [i1 [i2 []]].
intros; subst. simplify_invariant (double_minimum cmp minimum).
repeat destruct_pair_let.
repeat lazymatch goal with
| H : context [match ?p with pair _ _ => _ end] |- _ =>
rewrite (surjective_pairing p) in H
end.
cbv [double_minimum]. stepsimpl. logical_simplify; subst.
repeat (destruct_pair_let; cbn [fst snd]). stepsimpl.
repeat (rewrite split_combine_denotation; cbn [fst snd]).
simplify_spec (double_minimum cmp minimum).
do 2 eexists. ssplit.
{ eapply (invariant_preserved_pf (c:=minimum));
[ | solve [eauto] .. ].
simplify_spec minimum. reflexivity. }
{ eapply (invariant_preserved_pf (c:=minimum));
[ | solve [eauto] .. ].
simplify_spec minimum. reflexivity. }
{ cbn [app In]. intros.
repeat match goal with
| _ => progress cbn [In] in *
| H : _ \/ _ |- _ => destruct H; subst
| H : In _ (_ ++ _) |- _ => eapply in_app_or in H
| H1 : (forall x, In x (_ ++ _) -> ?P), H2 : In ?x _ |- _ =>
assert ((fun x => P) x) by (apply H1; apply in_app_iff; tauto);
tauto
| _ => tauto
end. }
{ cbn [app In]. intros.
rewrite in_app_iff. cbn [In].
repeat match goal with
| _ => progress cbn [In] in *
| H : _ \/ _ |- _ => destruct H; subst
| H : In _ (_ ++ _) |- _ => eapply in_app_or in H
| H1 : (forall x, In x ?l -> ?P), H2 : In ?x ?l |- _ =>
specialize (H1 x H2)
| _ => tauto
end. }
Qed.
Lemma double_minimum_output_correct : output_correct (double_minimum cmp minimum).
Proof.
cbv [output_correct]. cbn [absorb_any].
intros (i1,(i2,[])). intros.
simplify_invariant (double_minimum cmp minimum).
simplify_spec (double_minimum cmp minimum).
repeat lazymatch goal with
| H : context [match ?p with pair _ _ => _ end] |- _ =>
rewrite (surjective_pairing p) in H
end.
cbv [double_minimum]. stepsimpl. logical_simplify; subst.
repeat (destruct_pair_let; cbn [fst snd]). stepsimpl.
repeat use_correctness' minimum.
rewrite !Forall_forall in *. intros.
repeat match goal with
| _ => progress cbn [In] in *
| H : _ \/ _ |- _ => destruct H; subst
| H : In _ (_ ++ _) |- _ => eapply in_app_or in H
| H : forall x, ?y = x \/ _ -> _ |- _ <= rankT ?y =>
specialize (H y ltac:(eauto))
| H : (forall x, (_ \/ In x ?l) -> _), H2 : In ?x ?l |- _ =>
specialize (H x ltac:(eauto))
| H1 : (forall x, In x ?l -> ?P), H2 : In ?x ?l |- _ =>
specialize (H1 x H2)
| _ => tauto
| _ => lia
| _ => solve [eauto using N.le_trans]
| _ => destruct_one_match
end.
Qed.
Existing Instances double_minimum_invariant_at_reset double_minimum_invariant_preserved
double_minimum_output_correct.
Global Instance double_minimum_correctness : correctness_for (double_minimum cmp minimum).
Proof. constructor; typeclasses eauto. Defined.
End Proofs.
End SpecificationsAndProofs.
Section Instantiations.
Section CircuitDefinitions.
Context {var : tvar}.
Import ExprNotations.
Import PrimitiveNotations.
Definition minimum {T} (cmp : Circuit [] [T;T] Bit)
: Circuit _ [T] T :=
{{ fun input =>
let/delay min :=
(let input_le_min := `cmp` input min in
if input_le_min then input else min)
initially default in
min
}}.
Definition cmp_bit : Circuit [] [Bit;Bit] Bit :=
{{ fun x y => let out := (y || !x) in out }}.
Definition cmp_bv {n} : Circuit [] [BitVec n;BitVec n] Bit :=
{{ fun x y => let b := x <= y in b }}.
(* Instantiate [minimum] and [double_minimum] for different types *)
Definition minimum_bit : Circuit _ [Bit] Bit := minimum cmp_bit.
Definition minimum_byte : Circuit _ [BitVec 8] (BitVec 8)
:= minimum cmp_bv.
Definition double_minimum_bit : Circuit _ [Bit;Bit] Bit :=
double_minimum cmp_bit minimum_bit.
Definition double_minimum_byte : Circuit _ [BitVec 8;BitVec 8] (BitVec 8) :=
double_minimum cmp_bv minimum_byte.
End CircuitDefinitions.
(* Parameterized proofs for [minimum] *)
Section GeneralizedMinimum.
Context {T} (rankT : denote_type T -> N)
(rankT_default : rankT default = 0)
(cmp : Circuit [] [T;T] Bit)
(cmp_correct :
forall x y : denote_type T,
step cmp tt (x,(y,tt)) = (tt, rankT x <=? rankT y)).
Hint Rewrite cmp_correct : stepsimpl.
(* Generalized invariant for [minimum] *)
Instance minimum_invariant
: invariant_for (minimum cmp) (list (denote_type T)) :=
fun (state : denote_type (T ++ [])) (acc : list (denote_type T)) =>
let (min,_) := split_absorbed_denotation state in
min = fold_right (fun x min =>
if rankT x <=? rankT min then x else min)
default acc.
Lemma minimum_invariant_at_reset :
invariant_at_reset (spec:=minimum_specification rankT (minimum cmp))
(minimum cmp).
Proof.
simplify_invariant (minimum cmp).
cbn [minimum reset_state]. stepsimpl.
rewrite !split_combine_denotation.
reflexivity.
Qed.
Lemma minimum_invariant_preserved :
invariant_preserved (spec:=minimum_specification rankT (minimum cmp))
(minimum cmp).
Proof.
simplify_invariant (minimum cmp). cbn [absorb_any].
intros [input []].
intros; subst. simplify_invariant (minimum cmp).
repeat destruct_pair_let.
repeat lazymatch goal with
| H : context [match ?p with pair _ _ => _ end] |- _ =>
rewrite (surjective_pairing p) in H
end.
cbv [minimum]. stepsimpl. logical_simplify; subst.
repeat (destruct_pair_let; cbn [fst snd]). stepsimpl.
repeat (rewrite split_combine_denotation; cbn [fst snd]).
cbn [update_repr minimum_specification].
cbn [fold_right].
lazymatch goal with H : _ = fold_right _ _ _ |- _ => rewrite <-H end.
reflexivity.
Qed.
(* helper lemma for minimum_output_correct *)
Lemma Forall_rankT_min min ls :
min = fold_right (fun x min => if rankT x <=? rankT min then x else min) default ls ->
Forall (fun y => rankT min <= rankT y) ls.
Proof.
revert min; induction ls; intros; [ solve [constructor] | ].
subst. cbn [fold_right]. constructor; [ destruct_one_match; lia | ].
destruct_one_match; [ | solve [eauto] ].
specialize (IHls _ ltac:(reflexivity)).
rewrite Forall_forall in IHls. apply Forall_forall; intros.
specialize (IHls _ ltac:(eassumption)). lia.
Qed.
Lemma minimum_output_correct :
output_correct (spec:=minimum_specification rankT (minimum cmp))
(minimum cmp).
Proof.
simplify_invariant (minimum cmp). cbn [absorb_any].
intros [input []].
intros; subst. cbn [postcondition precondition minimum_specification] in *.
repeat destruct_pair_let.
repeat lazymatch goal with
| H : context [match ?p with pair _ _ => _ end] |- _ =>
rewrite (surjective_pairing p) in H
end.
cbv [minimum]. stepsimpl. logical_simplify; subst.
repeat (destruct_pair_let; cbn [fst snd]). stepsimpl.
apply Forall_rankT_min. cbn [fold_right].
lazymatch goal with H : _ = fold_right _ _ _ |- _ => rewrite <-H end.
reflexivity.
Qed.
Existing Instances minimum_invariant_at_reset minimum_invariant_preserved
minimum_output_correct.
Instance minimum_correctness :
correctness_for (spec:=minimum_specification rankT (minimum cmp))
(minimum cmp).
Proof. constructor; typeclasses eauto. Defined.
End GeneralizedMinimum.
Lemma cmp_bit_correct (x y : denote_type Bit) :
step cmp_bit tt (x, (y, tt)) = (tt, N.b2n x <=? N.b2n y).
Proof. destruct x, y; reflexivity. Qed.
Lemma cmp_bv_correct n (x y : denote_type (BitVec n)) :
step (cmp_bv (n:=n)) tt (x, (y, tt)) = (tt, x <=? y).
Proof. reflexivity. Qed.
(* Derive correctness for [minimum_bit] *)
Global Instance minimum_bit_specification
: specification_for minimum_bit (list bool) :=
minimum_specification (T:=Bit) N.b2n minimum_bit.
Global Instance minimum_bit_invariant : invariant_for minimum_bit (list bool) :=
minimum_invariant (T:=Bit) N.b2n cmp_bit.
Global Instance minimum_bit_correctness : correctness_for minimum_bit.
Proof.
apply @minimum_correctness; [ exact eq_refl | ].
exact cmp_bit_correct.
Qed.
(* Derive correctness for [minimum_byte] *)
Global Instance minimum_byte_specification
: specification_for minimum_byte (list N) :=
minimum_specification (T:=BitVec 8) (fun x => x) minimum_byte.
Global Instance minimum_byte_invariant : invariant_for minimum_byte (list N) :=
minimum_invariant (T:=BitVec 8) (fun x => x) cmp_bv.
Global Instance minimum_byte_correctness : correctness_for minimum_byte.
Proof.
apply @minimum_correctness; [ exact eq_refl | ].
exact (cmp_bv_correct 8).
Defined.
(* Derive correctness for [double_minimum_bit] *)
Global Instance double_minimum_bit_specification
: specification_for double_minimum_bit (list bool) :=
double_minimum_specification (T:=Bit) N.b2n cmp_bit minimum_bit.
Global Instance double_minimum_bit_invariant
: invariant_for double_minimum_bit (list bool) :=
double_minimum_invariant (T:=Bit) cmp_bit minimum_bit.
Global Instance double_minimum_bit_correctness : correctness_for double_minimum_bit.
Proof.
apply @double_minimum_correctness; try typeclasses eauto.
exact cmp_bit_correct.
Defined.
(* Derive correctness for [double_minimum_byte] *)
Global Instance double_minimum_byte_specification
: specification_for double_minimum_byte (list N) :=
double_minimum_specification (T:=BitVec 8) (fun x => x) cmp_bv minimum_byte.
Global Instance double_minimum_byte_invariant
: invariant_for double_minimum_byte (list N) :=
double_minimum_invariant (T:=BitVec 8) cmp_bv minimum_byte.
Global Instance double_minimum_byte_correctness : correctness_for double_minimum_byte.
Proof.
apply @double_minimum_correctness; try typeclasses eauto.
exact (cmp_bv_correct 8).
Defined.
End Instantiations.
End AbstractSubcircuitExample.
|
/****************************************************************************************
*
* File Name: mobile_ddr.v
* Version: 3.50
* Model: BUS Functional
*
* Dependencies: mobile_ddr_parameters.vh
*
* Description: Micron MOBILE DDR SDRAM
*
* Limitation: - Doesn't check for 8K-cycle refresh
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
* - Model assume Clk and Clk# crossing at both edge
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2004 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* --- ------ ---------- ---------------------------------------
* 1.0 NMB 03/19/02 - Initial Release of Mobile DDR model
* based off of version 5.0 of DDR model
* 1.1 ritz 12/03/04 - New feature: 1/8th strength driver in Drive Strength (Ext Mode Reg).
* Bugfix - ba[0] ba[1] were swapped for determening ext_mode_enable
* thus ext_mode_reg wasnt being programmed.
* 1.2 ritz 12/07/04 - Logging transactions in transcript for automated testing
* 1.3 ritz 01/31/05 - updated to SMG DDR model version 5.2 (dqs edge checking errors fix)
* 1.4 ritz 02/15/05 - Fixed display.*WRITE to use hex for "data".
* 1.5 ritz 03/22/05 - Fixed read latency (#0.5 and 2*Read_latency-1) for MMG latency
* 2.0 bas 07/19/06 - Added PASR support and clk_n checking
* 3.0 bas 08/07/06 - Added tXP check, tCke check, Power-down/Deep power down enter/exit messages
FULL_MEM fix
* 3.11 bas 10/18/06 - Added clk spd chk, added RP support, added T48M part, added SRR functionality, changed tMRD checker to measure in tck pos edge, DPD optimization for FULL_MEM mode
* 3.12 bas 10/19/06 - Fixed PASR in FULL_MEM mode
* 3.20 bas 10/23/06 - changed tXP check to tPDX check for T25L, Initial release to web
* 3.30 bas 01/15/07 - Updated T48M Parameters (updated as of 12/06)
* 3.35 bas 02/28/07 - Model uses tAC correctly to calculate strobe/data launch
* 3.36 bas 03/05/07 - fixed error messages for different banks interrupting
reads/writes w/autoprecharge
* 3.37 bas 03/21/07 - Added T47M Part to 512Mb parameter file
* 3.40 bas 06/25/07 - Removed RP options from 1024Mb
Updated 128Mb, 256Mb, and 512Mb parts to 05/07 datasheet
Updated 1024Mb part to 02/07
Added illegal Cas Latency check per speed grade
* 3.40 jwm 08/02/07 - Support for 512Mb T47M
****************************************************************************************/
// Modified to use GRLIB ramback backend instead of internal array
// magnus@gaisler, March 2012
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ns / 1ps
module mobile_ddr_fe (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm,
BEaddr, BEwr, BEdin, BEdout, BEclear, BEclrpart, BEsynco, BEsynci);
// `include "mobile_ddr_parameters.vh"
/****************************************************************************************
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2005 Micron Technology, Inc. All rights reserved.
*
*
* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK. Fixed.
* Added ROW_BITS & BA_BITS for compatibility w/our system.
* Removed part size parameter.
*
****************************************************************************************/
// Parameters current with T47M datasheet rev M (07/07)
// Timing parameters based on Speed Grade
`define sg5
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef sg5 // Timing Parameters for -5 (CL = 3)
parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
parameter tCK3_min = 5.0; // tCK ns Nominal Clock Cycle Time
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.40; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
parameter tRP = 15.0; // tRP ns Precharge command period
parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
parameter tXP = 10.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
`else `ifdef sg6 // Timing Parameters for -6 (CL = 3)
parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
parameter tRP = 18.0; // tRP ns Precharge command period
parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
`else
`define sg75 // Timing Parameters for -75 (CL = 3)
parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
parameter tRC = 75.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
parameter tRP = 22.5; // tRP ns Precharge command period
parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
parameter tXP = 7.5; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
`endif `endif
parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
parameter tRFC = 97.5; // tRFC ns Refresh to Refresh Command interval time
parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command (Not Applicable for 128Mb, 256Mb, and 512Mb Parts)
parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command (Not Applicable for 128Mb, 256Mb, and 512Mb Parts)
parameter tWR = 14.99; // tWR ns Write recovery time
// Size Parameters based on Part Width
`define x16
`ifdef x16
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter BA_BITS = 2; // Bank bits
`else
`define x32
`ifdef RP
parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
parameter COL_BITS = 8; // Set this parameter to control how many Column bits are used
parameter BA_BITS = 2; // Bank bits
`else
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
parameter BA_BITS = 2; // Bank bits
`endif
`endif
parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
parameter part_size = 512; // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb)
parameter tCH_MAX = 0.55; // Clk high level width
parameter tCH_MIN = 0.45; // Clk high level width
parameter tCL_MAX = 0.55; // Clk low level width
parameter tCL_MIN = 0.45; // Clk low level width
parameter tCKE = 2.0; // Minimum tCKE High/Low time (in tCK's)
parameter CL_MAX = 3.0; // Maximum CAS Latency
// Port Declarations
inout [DQ_BITS - 1 : 0] Dq;
inout [DQS_BITS - 1 : 0] Dqs;
input [ADDR_BITS - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Clk_n;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [DM_BITS - 1 : 0] Dm;
output reg [full_mem_bits-1 : 0] BEaddr;
output reg [DQ_BITS/8-1 : 0] BEwr;
output reg [DQ_BITS-1 : 0] BEdin;
input [DQ_BITS-1 : 0] BEdout;
output reg BEclear;
output reg BEclrpart;
output reg BEsynco;
input BEsynci;
//time variables
realtime tXP_chk ;
reg enter_DPD ;
reg enter_PD ;
reg enter_APD ;
//integer clk checks
// Internal Wires (fixed width)
wire [31 : 0] Dq_in;
wire [3 : 0] Dqs_in;
wire [3 : 0] Dm_in;
assign Dq_in [DQ_BITS - 1 : 0] = Dq;
assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;
assign Dm_in [DM_BITS - 1 : 0] = Dm;
// Data pair
reg [31 : 0] dq_rise;
reg [3 : 0] dm_rise;
reg [31 : 0] dq_fall;
reg [3 : 0] dm_fall;
reg [7 : 0] dm_pair;
reg [31 : 0] Dq_buf;
// Power-down cycle counter
reg [03:00] PD_cntr ;
// prev cmd value
reg prev_Cs_n ;
reg prev_Ras_n ;
reg prev_Cas_n ;
reg prev_We_n ;
reg [01:00] prev_Ba ;
reg prev_cke ;
wire prev_nop = ~prev_Cs_n & prev_Ras_n & prev_Cas_n & prev_We_n ;
wire prev_des = prev_Cs_n ;
wire prev_bt = ~prev_Cs_n & prev_Ras_n & prev_Cas_n & ~prev_We_n ;
//differential clk
reg diff_ck;
always @(posedge Clk) diff_ck <= Clk;
always @(posedge Clk_n) diff_ck <= ~Clk_n;
//measure clock period
realtime clk_period ;
realtime pos_clk_edge ;
integer clk_pos_edge_cnt ;
always @(posedge diff_ck) begin
clk_period = $realtime - pos_clk_edge ;
pos_clk_edge = $realtime ;
if ((Cke == 1'b1) && (clk_pos_edge_cnt < 2)) begin
clk_pos_edge_cnt = clk_pos_edge_cnt + 1 ;
end else if (Cke == 1'b0) begin
clk_pos_edge_cnt = 2'b00 ;
end
end
//measure duty cycle
realtime neg_clk_edge ;
always @(negedge diff_ck) begin
neg_clk_edge = $realtime ;
end
realtime pos_clk_time ;
realtime neg_clk_time ;
always @(diff_ck) begin
if (diff_ck) begin
neg_clk_time = $realtime - neg_clk_edge ;
end
if (~diff_ck) begin
pos_clk_time = $realtime - pos_clk_edge ;
end
if (Cke) begin
if ((pos_clk_time/clk_period)<tCH_MIN) begin
$display ("%m: at time %t ERROR: tCH minimum violation on CLK by %t", $time, tCH_MIN*clk_period - pos_clk_time);
end
if ((pos_clk_time/clk_period)>tCH_MAX) begin
$display ("%m: at time %t ERROR: tCH maximum violation on CLK by %t", $time, pos_clk_time - tCH_MAX*clk_period);
end
if ((neg_clk_time/clk_period)<tCL_MIN) begin
$display ("%m: at time %t ERROR: tCH minimum violation on CLK by %t", $time, tCL_MIN*clk_period - pos_clk_time);
end
if ((neg_clk_time/clk_period)>tCL_MAX) begin
$display ("%m: at time %t ERROR: tCH minimum violation on CLK by %t", $time, pos_clk_time - tCL_MAX*clk_period);
end
end
end
// Mode Register
reg [ADDR_BITS - 1 : 0] Mode_reg;
reg [ADDR_BITS - 1 : 0] Ext_Mode_reg;
reg [2*DQ_BITS - 1 : 0] Srr_reg;
// SRR Registers
reg SRR_read;
// Internal System Clock
reg CkeZ, Sys_clk;
// Internal Dqs initialize
reg Dqs_int;
// Dqs buffer
reg [DQS_BITS - 1 : 0] Dqs_out;
reg [DQS_BITS - 1 : 0] Dqs_gen;
// Dq buffer
reg [DQ_BITS - 1 : 0] Dq_out;
// Read pipeline variables
reg Read_cmnd [0 : 6];
reg [1 : 0] Read_bank [0 : 6];
reg [COL_BITS - 1 : 0] Read_cols [0 : 6];
// Write pipeline variables
reg Write_cmnd [0 : 3];
reg [1 : 0] Write_bank [0 : 3];
reg [COL_BITS - 1 : 0] Write_cols [0 : 3];
// Auto precharge variables
reg Read_precharge [0 : 3];
reg Write_precharge [0 : 3];
integer Count_precharge [0 : 3];
reg SelfRefresh;
reg [3:0] Read_precharge_count [3:0] ;
reg [3:0] Write_precharge_count [3:0];
reg wr_ap_display_msg ;
reg rd_ap_display_msg ;
// Manual precharge variables
reg A10_precharge [0 : 6];
reg [1 : 0] Bank_precharge [0 : 6];
reg Cmnd_precharge [0 : 6];
// Burst terminate variables
reg Cmnd_bst [0 : 6];
// tMRD counter
integer MRD_cntr ;
integer SRR_cntr ;
integer SRC_cntr ;
// Dqs edge checking
integer i;
reg [3:0] expect_pos_dqs;
reg [3:0] expect_neg_dqs;
// Burst counter
reg [COL_BITS - 1 : 0] Burst_counter;
// Burst counter delay
reg [COL_BITS - 1 : 0] Burst_counter_dly;
always@* begin
if (Mode_reg[6:4] == 3'b010) begin
Burst_counter_dly = #tAC2_max Burst_counter;
end else if (Mode_reg[6:4] == 3'b011) begin
Burst_counter_dly = #tAC3_max Burst_counter;
end
end
// Precharge variables
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3;
// Activate variables
reg Act_b0, Act_b1, Act_b2, Act_b3;
// Data IO variables
reg Data_in_enable;
reg Data_out_enable;
// Data Out Enable delay
reg Data_out_enable_dly;
always@* begin
if (Mode_reg[6:4] == 3'b010) begin
Data_out_enable_dly <= #tAC2_max Data_out_enable;
end else if (Mode_reg[6:4] == 3'b011) begin
Data_out_enable_dly <= #tAC3_max Data_out_enable;
end
end
// Internal address mux variables
reg [1 : 0] Prev_bank;
reg [1 : 0] Bank_addr;
reg [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp;
reg [ADDR_BITS - 1 : 0] Rows_addr;
reg [ADDR_BITS - 1 : 0] B0_row_addr;
reg [ADDR_BITS - 1 : 0] B1_row_addr;
reg [ADDR_BITS - 1 : 0] B2_row_addr;
reg [ADDR_BITS - 1 : 0] B3_row_addr;
integer aref_count;
reg ext_mode_load_done;
reg mode_load_done;
reg power_up_done;
reg file_load_done;
// Write DQS for tDSS , tDSH, tDQSH, tDQSL checks
wire wdqs_valid = Write_cmnd[1] || Write_cmnd[2] || Data_in_enable;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n & Cke;
wire Sref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n & ~Cke;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & Ba[1] & ~Ba[0];
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[1] & ~Ba[0];
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
wire DPD_enable = ~Cs_n & Ras_n & Cas_n & ~We_n & ~Cke;
wire PD_enable = ((~Cs_n & Ras_n & Cas_n & We_n) | Cs_n) & ~Cke;
wire nop_enable = ~Cs_n & Ras_n & Cas_n & We_n ;
wire des_enable = Cs_n ;
wire srr_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[1] & Ba[0] ; //& (part_size==1024) ; // ****
// Burst Length Decode
// reg [4:0] burst_length = 1 << (Mode_reg[2:0]);
reg [4:0] burst_length ;
reg read_precharge_truncation;
// CAS Latency Decode
wire [2:0] cas_latency_x2 = ((2*Mode_reg[6:4])-1);
// DQS Buffer
reg [DQS_BITS - 1 : 0] dqs_delayed ;
// always@* begin
// dqs_delayed <= Dqs_out ;
// end
assign Dqs = Dqs_out;
// DQ Buffer
reg [DQ_BITS - 1 : 0] dq_delayed ;
always@* begin
if (Mode_reg[6:4] == 3'b010) begin
dq_delayed <= #tAC2_max Dq_out ;
end else if (Mode_reg[6:4] == 3'b011) begin
dq_delayed <= #tAC3_max Dq_out ;
end else begin
dq_delayed <= #tAC3_max {DQ_BITS{1'bz}} ;
end
end
assign Dq = dq_delayed;
// Debug message
wire Debug = 1'b0;
// Timing Check
// realtime MRD_chk;
realtime RFC_chk;
realtime RRD_chk;
realtime RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
realtime RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3;
realtime RC_chk0, RC_chk1, RC_chk2, RC_chk3;
realtime RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
realtime RP_chk0, RP_chk1, RP_chk2, RP_chk3;
realtime WR_chk0, WR_chk1, WR_chk2, WR_chk3;
realtime SRR_chk;
//
reg [2:0] current_init_state ;
parameter [2:0] begin_init = 3'b000 ;
parameter [2:0] cke_init = 3'b001 ;
parameter [2:0] prech_init = 3'b010 ;
parameter [2:0] begin_mode_init = 3'b011 ;
parameter [2:0] mode_init = 3'b100 ;
parameter [2:0] ext_mode_init = 3'b101 ;
parameter [2:0] mode_done_init = 3'b110 ;
initial begin
CkeZ = 1'b0;
Sys_clk = 1'b0;
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;
Dqs_int = 1'b0;
Dqs_out = {DQS_BITS{1'bz}};
Dqs_gen = {DQS_BITS{1'bz}};
Dq_out = {DQ_BITS{1'bz}};
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
aref_count = 0;
SelfRefresh = 1'b0;
power_up_done = 0;
ext_mode_load_done = 0;
mode_load_done = 0;
// MRD_chk = 0;
RFC_chk = 0;
RRD_chk = 0;
RAS_chk0 = 0;
RAS_chk1 = 0;
RAS_chk2 = 0;
RAS_chk3 = 0;
RAP_chk0 = 0;
RAP_chk1 = 0;
RAP_chk2 = 0;
RAP_chk3 = 0;
RC_chk0 = 0;
RC_chk1 = 0;
RC_chk2 = 0;
RC_chk3 = 0;
RCD_chk0 = 0;
RCD_chk1 = 0;
RCD_chk2 = 0;
RCD_chk3 = 0;
RP_chk0 = 0;
RP_chk1 = 0;
RP_chk2 = 0;
RP_chk3 = 0;
WR_chk0 = 0;
WR_chk1 = 0;
WR_chk2 = 0;
WR_chk3 = 0;
SRR_chk = 0;
$timeformat (-9, 3, " ns", 12);
pos_clk_time = 0;
neg_clk_time = 0;
enter_DPD = 0;
enter_PD = 0;
enter_APD = 0;
current_init_state = begin_init ;
SRR_read = 1'b0;
MRD_cntr = 8;
SRR_cntr = 8;
SRC_cntr = 8;
Read_precharge[0] = 1'b0 ;
Read_precharge[1] = 1'b0 ;
Read_precharge[2] = 1'b0 ;
Read_precharge[3] = 1'b0 ;
Write_precharge[0] = 1'b0 ;
Write_precharge[1] = 1'b0 ;
Write_precharge[2] = 1'b0 ;
Write_precharge[3] = 1'b0 ;
wr_ap_display_msg = 1'b0 ;
rd_ap_display_msg = 1'b0 ;
Read_precharge_count[0] = 4'hf;
Read_precharge_count[1] = 4'hf;
Read_precharge_count[2] = 4'hf;
Read_precharge_count[3] = 4'hf;
Write_precharge_count[0] = 4'hf;
Write_precharge_count[1] = 4'hf;
Write_precharge_count[2] = 4'hf;
Write_precharge_count[3] = 4'hf;
BEaddr = {full_mem_bits{1'b0}};
BEwr = {(DQ_BITS/8){1'b0}};
BEdin = {DQ_BITS{1'b0}};
BEclear = 1'b0;
BEclrpart = 1'b0;
BEsynco = 0'b0;
end
//clock Frequency Check
always @(posedge diff_ck) begin
if (clk_pos_edge_cnt > 1) begin
if (Mode_reg[6:4] == 3'b011) begin
if (clk_period < (tCK3_min-0.001)) begin
$display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 3", $realtime);
$display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period);
end
end
if (Mode_reg[6:4] == 3'b010) begin
if (clk_period < (tCK2_min-0.001)) begin
$display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 2", $realtime);
$display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period);
end
end
end
end
//SRR reg settings
always @(posedge power_up_done) begin
Srr_reg = 'b0 ;
Srr_reg[3:0] = 4'b1111 ; //Manufacturer(Micron)
Srr_reg[7:4] = 4'b0000 ; //Revision ID(Default to 0 in model)
Srr_reg[10:8] = 3'b100 ; //Refresh Rate(based on temp sensor - will default to 1x in model)
Srr_reg[11] = (DQ_BITS == 32)? 1'b1 : 1'b0 ; //Part width(x32 or x16)
Srr_reg[12] = 1'b0 ; //Device Type (LP DDR)
Srr_reg[15:13] = (part_size == 1024)? 3'b011 :
(part_size == 512 )? 3'b010 :
(part_size == 256 )? 3'b001 :
3'b000 ; //Density(1024Mb, 512Mb, 256Mb, 128Mb)
end
// System Clock
always begin
@ (posedge diff_ck) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge diff_ck) begin
Sys_clk = 1'b0;
end
end
task store_prev_cmd;
begin
prev_Cs_n <= Cs_n ;
prev_Ras_n <= Ras_n ;
prev_Cas_n <= Cas_n ;
prev_We_n <= We_n ;
prev_Ba[1] <= Ba[1] ;
prev_Ba[0] <= Ba[0] ;
prev_cke <= Cke ;
end
endtask
task MRD_counter;
begin
if (Cke) begin
if (MRD_cntr < tMRD) begin
MRD_cntr = MRD_cntr + 1'b1;
end
end
end
endtask
task SRR_counter;
begin
if (Cke) begin
if (SRR_cntr < tSRR) begin
SRR_cntr = SRR_cntr + 1'b1;
end
end
end
endtask
task SRC_counter;
begin
if (Cke) begin
if (SRC_cntr < ((Mode_reg[6:4])+1)) begin
SRC_cntr = SRC_cntr + 1'b1;
end
end
end
endtask
task command_counter;
begin
if (Cke) begin
for (i=0; i<4;i=i+1) begin
if (Read_precharge_count[i] < 4'hf) begin
Read_precharge_count[i] = Read_precharge_count[i] + 1'b1;
end
end
for (i=0; i<4;i=i+1) begin
if (Write_precharge_count[i] < 4'hf) begin
Write_precharge_count[i] = Write_precharge_count[i] + 1'b1;
end
end
end
end
endtask
task PD_counter;
begin
if (~Cke) begin
if (PD_cntr < tCKE) begin
PD_cntr = PD_cntr + (enter_DPD | enter_PD | DPD_enable | PD_enable);
end
end else begin
PD_cntr = 4'h0 ;
end
end
endtask
task tXP_check;
begin
if (Cke == 1'b1 && prev_cke == 1'b0) begin
tXP_chk = $realtime ;
end
if (Cke) begin
if (~nop_enable && ~des_enable) begin
if ($realtime-tXP_chk < tXP) begin
`ifdef T25L
$display ("%m: At time %t ERROR: tPDX violation", $realtime);
`else
$display ("%m: At time %t ERROR: tXP violation", $realtime);
`endif
end
end
end
end
endtask
// DPD pos edge clk cntr
always begin
@ (posedge diff_ck) begin
tXP_check ;
Power_down_chk ;
PD_counter ;
store_prev_cmd ;
end
end
// Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high
always @(Cke) begin
if (Cke === 1'b1) begin
if (SelfRefresh === 1'b1) begin
SelfRefresh = 1'b0;
end
if (!((Cs_n) || (~Cs_n & Ras_n & Cas_n & We_n))) begin
$display ("%m: At time %t MEMORY ERROR: You must have a Deselect or NOP command applied", $realtime);
$display ("%m: when the Clock Enable is brought High.");
end
end
end
//BL Mode Reg settings
always@(Mode_reg[2:0] or mode_load_done) begin
if (mode_load_done) begin
case (Mode_reg[2:0])
3'b001 : burst_length = 5'b00010;
3'b010 : burst_length = 5'b00100;
3'b011 : burst_length = 5'b01000;
default : burst_length = 5'bxxxxx;
endcase
end
end
// Init sequence
always @* begin
if (current_init_state == begin_init) begin
if (Cke) begin
current_init_state = cke_init ;
power_up_done = 1'b0 ;
end
end
if (current_init_state == cke_init) begin
if (Prech_enable) begin
current_init_state = prech_init ;
aref_count = 0 ;
end
end
if (current_init_state == prech_init) begin
if (~Prech_enable) begin
current_init_state = begin_mode_init ;
end
end
if (current_init_state == begin_mode_init) begin
if (ext_mode_load_done) begin
current_init_state = ext_mode_init ;
end
if (mode_load_done) begin
current_init_state = mode_init ;
end
end
if (current_init_state == mode_init) begin
if (ext_mode_load_done) begin
current_init_state = mode_done_init ;
end
end
if (current_init_state == ext_mode_init) begin
if (mode_load_done) begin
current_init_state = mode_done_init ;
end
end
if (current_init_state == mode_done_init && aref_count >= 2) begin
power_up_done = 1'b1;
end
end
task backend_sync;
begin
BEsynco = 1'b1;
wait (BEsynci) BEsynco = 1'b0;
wait (!BEsynci) ;
end
endtask
// this task will erase the contents of 0 or more banks
task erase_mem;
input [BA_BITS+1:0] bank_MSB_row; //bank bits + 2 row MSB
input DPD_mode ; //erase all memory locations
integer i,j;
begin
if (DPD_mode) begin
BEclear = 1'b1;
backend_sync;
BEclear = 1'b0;
backend_sync;
end else begin
for (i={1'b0,bank_MSB_row}+1; i<5'b10000; i=i+1) begin
BEaddr = { i[3:0], {(full_mem_bits-BA_BITS-2){1'b0}} };
j = full_mem_bits-BA_BITS-2;
BEdin = j[DQ_BITS-1:0];
BEclrpart = 1'b1;
backend_sync;
BEclrpart = 1'b0;
backend_sync;
end
end // else: !if(DPD_mode)
end
endtask // erase_mem
// Write Memory
task write_mem;
input [full_mem_bits - 1 : 0] addr;
input [DQ_BITS - 1 : 0] data;
begin
BEaddr = addr;
BEdin = data;
backend_sync;
BEwr = 2'b11;
backend_sync;
BEwr = 2'b00;
backend_sync;
end
endtask // write_mem
// Read Memory
task read_mem;
input [full_mem_bits - 1 : 0] addr;
output [DQ_BITS - 1 : 0] data;
begin
BEaddr = addr;
backend_sync;
data = BEdout;
end
endtask
// Burst Decode
task Burst_Decode;
begin
// Advance Burst Counter
if (Burst_counter < burst_length) begin
Burst_counter = Burst_counter + 1;
end
// Burst Type
if (Mode_reg[3] === 1'b0) begin // Sequential Burst
Cols_temp = Cols_addr + 1;
end else if (Mode_reg[3] === 1'b1) begin // Interleaved Burst
Cols_temp[2] = Burst_counter[2] ^ Cols_brst[2];
Cols_temp[1] = Burst_counter[1] ^ Cols_brst[1];
Cols_temp[0] = Burst_counter[0] ^ Cols_brst[0];
end
// Burst Length
if (burst_length === 2) begin
Cols_addr [0] = Cols_temp [0];
end else if (burst_length === 4) begin
Cols_addr [1 : 0] = Cols_temp [1 : 0];
end else if (burst_length === 8) begin
Cols_addr [2 : 0] = Cols_temp [2 : 0];
end else if (burst_length === 16) begin
Cols_addr [3 : 0] = Cols_temp [3 : 0];
end else begin
Cols_addr = Cols_temp;
end
// Data Counter
if (Burst_counter >= burst_length) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
read_precharge_truncation = 1'b0;
//if (SRC_cntr == 2) begin // ****
if (((SRC_cntr == 2) & (Mode_reg[6:4] == 3'b010)) | ((SRC_cntr == 3) & (Mode_reg[6:4] == 3'b011))) begin
SRR_read = 1'b0;
end
end
end
endtask
// // Burst Decode
// task Burst_Decode;
// begin
//
// // Advance Burst Counter
// if (Burst_counter < burst_length) begin
// Burst_counter = Burst_counter + 1;
// end
//
// // Burst Type
// if (Mode_reg[3] === 1'b0) begin // Sequential Burst
// Cols_temp = Cols_addr + 1;
// end else if (Mode_reg[3] === 1'b1) begin // Interleaved Burst
// Cols_temp[2] = Burst_counter[2] ^ Cols_brst[2];
// Cols_temp[1] = Burst_counter[1] ^ Cols_brst[1];
// Cols_temp[0] = Burst_counter[0] ^ Cols_brst[0];
// end
//
// // Burst Length
// if (burst_length === 2) begin
// Cols_addr [0] = Cols_temp [0];
// end else if (burst_length === 4) begin
// Cols_addr [1 : 0] = Cols_temp [1 : 0];
// end else if (burst_length === 8) begin
// Cols_addr [2 : 0] = Cols_temp [2 : 0];
// end else if (burst_length === 16) begin
// Cols_addr [3 : 0] = Cols_temp [3 : 0];
// end else begin
// Cols_addr = Cols_temp;
// end
//
// // Data Counter
// if (Burst_counter >= burst_length) begin
// Data_in_enable = 1'b0;
// Data_out_enable = 1'b0;
// read_precharge_truncation = 1'b0;
// SRR_read = 1'b0;
// end
// end
// endtask
// SRC check
task Timing_chk_SRC;
begin
if (Active_enable || Aref_enable || Sref_enable || Burst_term ||
Ext_mode_enable || Mode_reg_enable || Prech_enable || Read_enable ||
Write_enable || DPD_enable || PD_enable || srr_enable) begin
if (part_size == 1024) begin
if (SRC_cntr < ((Mode_reg[6:4])+tSRC)) begin
$display ("%m: At time %t ERROR: tSRC Violation", $realtime);
end
end
end
end
endtask
// Manual Precharge Pipeline
task Manual_Precharge_Pipeline;
begin
// A10 Precharge Pipeline
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = A10_precharge[4];
A10_precharge[4] = A10_precharge[5];
A10_precharge[5] = A10_precharge[6];
A10_precharge[6] = 1'b0;
// Bank Precharge Pipeline
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = Bank_precharge[4];
Bank_precharge[4] = Bank_precharge[5];
Bank_precharge[5] = Bank_precharge[6];
Bank_precharge[6] = 2'b0;
// Command Precharge Pipeline
Cmnd_precharge[0] = Cmnd_precharge[1];
Cmnd_precharge[1] = Cmnd_precharge[2];
Cmnd_precharge[2] = Cmnd_precharge[3];
Cmnd_precharge[3] = Cmnd_precharge[4];
Cmnd_precharge[4] = Cmnd_precharge[5];
Cmnd_precharge[5] = Cmnd_precharge[6];
Cmnd_precharge[6] = 1'b0;
// Terminate a Read if same bank or all banks
if (Cmnd_precharge[0] === 1'b1) begin
if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin
if (Data_out_enable === 1'b1) begin
Data_out_enable = 1'b0;
read_precharge_truncation = 1'b1;
end
end
end
end
endtask
// Burst Terminate Pipeline
task Burst_Terminate_Pipeline;
begin
// Command Precharge Pipeline
Cmnd_bst[0] = Cmnd_bst[1];
Cmnd_bst[1] = Cmnd_bst[2];
Cmnd_bst[2] = Cmnd_bst[3];
Cmnd_bst[3] = Cmnd_bst[4];
Cmnd_bst[4] = Cmnd_bst[5];
Cmnd_bst[5] = Cmnd_bst[6];
Cmnd_bst[6] = 1'b0;
// Terminate a Read regardless of banks
if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin
Data_out_enable = 1'b0;
end
end
endtask
// Dq and Dqs Drivers
task Dq_Dqs_Drivers;
begin
// read command pipeline
Read_cmnd [0] = Read_cmnd [1];
Read_cmnd [1] = Read_cmnd [2];
Read_cmnd [2] = Read_cmnd [3];
Read_cmnd [3] = Read_cmnd [4];
Read_cmnd [4] = Read_cmnd [5];
Read_cmnd [5] = Read_cmnd [6];
Read_cmnd [6] = 1'b0;
// read bank pipeline
Read_bank [0] = Read_bank [1];
Read_bank [1] = Read_bank [2];
Read_bank [2] = Read_bank [3];
Read_bank [3] = Read_bank [4];
Read_bank [4] = Read_bank [5];
Read_bank [5] = Read_bank [6];
Read_bank [6] = 2'b0;
// read column pipeline
Read_cols [0] = Read_cols [1];
Read_cols [1] = Read_cols [2];
Read_cols [2] = Read_cols [3];
Read_cols [3] = Read_cols [4];
Read_cols [4] = Read_cols [5];
Read_cols [5] = Read_cols [6];
Read_cols [6] = 0;
// Initialize Read command
if (Read_cmnd [1] === 1'b1) begin
Data_out_enable = 1'b1;
Bank_addr = Read_bank [1];
Cols_addr = Read_cols [1];
Cols_brst = Cols_addr [2 : 0];
if (SRR_read == 1'b1) begin
Burst_counter = burst_length - 2;
end else begin
Burst_counter = 0;
end
// Row Address Mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("%m: At time %t ERROR: Invalid Bank Address", $realtime);
endcase
end
// Toggle Dqs during Read command
if (Data_out_enable === 1'b1) begin
Dqs_int = 1'b0;
if (Dqs_gen === {DQS_BITS{1'b0}}) begin
Dqs_gen = {DQS_BITS{1'b1}};
end else if (Dqs_gen === {DQS_BITS{1'b1}}) begin
Dqs_gen = {DQS_BITS{1'b0}};
end else if (Dqs_gen === {DQS_BITS{1'b0}}) begin
Dqs_gen = {DQS_BITS{1'b0}};
end
if (Mode_reg[6:4] == 3'b010) begin
Dqs_out <= #tAC2_max Dqs_gen;
end else if (Mode_reg[6:4] == 3'b011) begin
Dqs_out <= #tAC3_max Dqs_gen;
end
end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0 && (Dqs_gen !== {DQS_BITS{1'bz}})) begin
Dqs_gen = {DQS_BITS{1'bz}} ;
if (Mode_reg[6:4] == 3'b010) begin
Dqs_out <= #tHZ2_max Dqs_gen;
end else if (Mode_reg[6:4] == 3'b011) begin
Dqs_out <= #tHZ3_max Dqs_gen;
end
end
// Initialize dqs for Read command
if (Mode_reg[6:4] == 3'b010) begin
if ((Read_enable === 1'b1) && (Sys_clk == 1'b1)) begin
if (Data_out_enable === 1'b0) begin
Dqs_int = 1'b1;
Dqs_gen = {DQS_BITS{1'b0}};
// Dqs_out <= #2.0 Dqs_gen; // used in place of tLZ for a one clock preamble
Dqs_out <= #tAC2_max Dqs_gen; // used in place of tLZ for a one clock preamble // ****
end
end
end else if (Mode_reg[6:4] == 3'b011) begin
if (Read_cmnd [3] === 1'b1) begin
if (Data_out_enable === 1'b0) begin
Dqs_int = 1'b1;
Dqs_gen = {DQS_BITS{1'b0}};
Dqs_out <= #tAC3_max Dqs_gen; // used in place of tLZ for a one clock preamble
end
end
end
// Read latch
if (Data_out_enable === 1'b1) begin
// output data
if (SRR_read == 1'b1) begin
if (Burst_counter == (burst_length-2)) begin
Dq_out <= Srr_reg[DQ_BITS-1:0];
end else if (Burst_counter == (burst_length-1)) begin
Dq_out <= Srr_reg[2*DQ_BITS-1:DQ_BITS];
end
end else begin
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out);
end
if (Debug) begin
$display ("At time %t %m:READ: Bank = %d, Row = %d, Col = %d, Data = %d", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_out);
end
end else begin
Dq_out = {DQ_BITS{1'bz}};
end
end
endtask
// Write FIFO and DM Mask Logic
task Write_FIFO_DM_Mask_Logic;
begin
// Write command pipeline
Write_cmnd [0] = Write_cmnd [1];
Write_cmnd [1] = Write_cmnd [2];
Write_cmnd [2] = Write_cmnd [3];
Write_cmnd [3] = 1'b0;
// Write command pipeline
Write_bank [0] = Write_bank [1];
Write_bank [1] = Write_bank [2];
Write_bank [2] = Write_bank [3];
Write_bank [3] = 2'b0;
// Write column pipeline
Write_cols [0] = Write_cols [1];
Write_cols [1] = Write_cols [2];
Write_cols [2] = Write_cols [3];
Write_cols [3] = {COL_BITS{1'b0}};
// Initialize Write command
if (Write_cmnd [0] === 1'b1) begin
Data_in_enable = 1'b1;
Bank_addr = Write_bank [0];
Cols_addr = Write_cols [0];
Cols_brst = Cols_addr [2 : 0];
Burst_counter = 0;
// Row address mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("%m: At time %t ERROR: Invalid Row Address", $realtime);
endcase
end
// Write data
if (Data_in_enable === 1'b1) begin
// Data Buffer
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// write negedge Dqs on posedge Sys_clk
if (Sys_clk) begin
if (!dm_fall[0]) begin
Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];
end
if (!dm_fall[1]) begin
Dq_buf [15 : 8] = dq_fall [15 : 8];
end
if (!dm_fall[2]) begin
Dq_buf [23 : 16] = dq_fall [23 : 16];
end
if (!dm_fall[3]) begin
Dq_buf [31 : 24] = dq_fall [31 : 24];
end
if (~&dm_fall) begin
if (Debug) begin
$display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
// write posedge Dqs on negedge Sys_clk
end else begin
if (!dm_rise[0]) begin
Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];
end
if (!dm_rise[1]) begin
Dq_buf [15 : 8] = dq_rise [15 : 8];
end
if (!dm_rise[2]) begin
Dq_buf [23 : 16] = dq_rise [23 : 16];
end
if (!dm_rise[3]) begin
Dq_buf [31 : 24] = dq_rise [31 : 24];
end
if (~&dm_rise) begin
if (Debug) begin
$display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
end
// Write Data
write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// tWR start and tWTR check
if (Sys_clk && &dm_pair === 1'b0) begin
case (Bank_addr)
2'd0 : WR_chk0 = $realtime;
2'd1 : WR_chk1 = $realtime;
2'd2 : WR_chk2 = $realtime;
2'd3 : WR_chk3 = $realtime;
default : $display ("%m: At time %t ERROR: Invalid Bank Address (tWR)", $realtime);
endcase
// tWTR check
if (Read_enable === 1'b1) begin
$display ("%m: At time %t ERROR: tWTR violation during Read", $realtime);
end
end
end
end
endtask
// Auto Precharge Calculation
task Auto_Precharge_Calculation;
begin
// Precharge counter
if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin
Count_precharge [0] = Count_precharge [0] + 1;
end
if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin
Count_precharge [1] = Count_precharge [1] + 1;
end
if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin
Count_precharge [2] = Count_precharge [2] + 1;
end
if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin
Count_precharge [3] = Count_precharge [3] + 1;
end
// Read with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. Meet tRAS requirement
// 2. BL/2 cycles after command
if ((Read_precharge[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS)) begin
if (Count_precharge[0] >= burst_length/2) begin
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $realtime;
Read_precharge[0] = 1'b0;
end
end
if ((Read_precharge[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS)) begin
if (Count_precharge[1] >= burst_length/2) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $realtime;
Read_precharge[1] = 1'b0;
end
end
if ((Read_precharge[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS)) begin
if (Count_precharge[2] >= burst_length/2) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $realtime;
Read_precharge[2] = 1'b0;
end
end
if ((Read_precharge[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS)) begin
if (Count_precharge[3] >= burst_length/2) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $realtime;
Read_precharge[3] = 1'b0;
end
end
// Write with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. Meet tRAS requirement
// 2. Two clock after last burst
// Since tWR is time base, the model will compensate tRP
if ((Write_precharge[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS)) begin
if (Count_precharge[0] >= burst_length/2+3) begin
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
if (Mode_reg[6:4] == 3'b011) begin
RP_chk0 = $realtime - ((2 * tCK3_min) - tWR);
end
if (Mode_reg[6:4] == 3'b010) begin
RP_chk0 = $realtime - ((2 * tCK2_min) - tWR);
end
Write_precharge[0] = 1'b0;
end
end
if ((Write_precharge[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS)) begin
if (Count_precharge[1] >= burst_length/2+3) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
if (Mode_reg[6:4] == 3'b011) begin
RP_chk1 = $realtime - ((2 * tCK3_min) - tWR);
end
if (Mode_reg[6:4] == 3'b010) begin
RP_chk1 = $realtime - ((2 * tCK2_min) - tWR);
end
Write_precharge[1] = 1'b0;
end
end
if ((Write_precharge[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS)) begin
if (Count_precharge[2] >= burst_length/2+3) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
if (Mode_reg[6:4] == 3'b011) begin
RP_chk2 = $realtime - ((2 * tCK3_min) - tWR);
end
if (Mode_reg[6:4] == 3'b010) begin
RP_chk2 = $realtime - ((2 * tCK2_min) - tWR);
end
Write_precharge[2] = 1'b0;
end
end
if ((Write_precharge[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS)) begin
if (Count_precharge[3] >= burst_length/2+3) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
if (Mode_reg[6:4] == 3'b011) begin
RP_chk3 = $realtime - ((2 * tCK3_min) - tWR);
end
if (Mode_reg[6:4] == 3'b010) begin
RP_chk3 = $realtime - ((2 * tCK2_min) - tWR);
end
Write_precharge[3] = 1'b0;
end
end
end
endtask
task Power_down_chk;
begin
if (DPD_enable == 1'b1 && enter_DPD == 1'b0) begin
if (prev_cke & Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin
erase_mem(4'b0000, 1'b1);
current_init_state = begin_init ;
ext_mode_load_done = 1'b0 ;
mode_load_done = 1'b0 ;
enter_DPD = 1'b1;
$display ("%m: at time %t Entering Deep Power-Down Mode", $realtime);
end
end
if (enter_DPD == 1'b1) begin
if (Cke == 1'b1 && prev_cke == 1'b0) begin
if (PD_cntr < tCKE) begin
$display ("%m: At time %t ERROR: tCKE violation during exiting of Deep Power-Down Mode", $realtime);
end
$display ("%m: at time %t Exiting Deep Power-Down Mode - A 200 us delay is required with either DESELECT or NOP commands present before the initialization sequence may begin", $realtime);
enter_DPD = 1'b0;
end
end
if (PD_enable == 1'b1 && enter_PD == 1'b0) begin
if (prev_cke) begin
if (Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin
$display ("%m: at time %t Entering Power-Down Mode", $realtime);
enter_PD = 1'b1;
end else if (~Pc_b0 | ~Pc_b1 | ~Pc_b2 | ~Pc_b3) begin
$display ("%m: at time %t Entering Active Power-Down Mode", $realtime);
enter_APD = 1'b1;
end
end
end
if (enter_PD == 1'b1 || enter_APD == 1'b1) begin
if (Cke == 1'b1 && prev_cke == 1'b0) begin
if (PD_cntr < tCKE) begin
if (enter_PD == 1'b1) begin
$display ("%m: At time %t ERROR: tCKE violation during exiting of Power-Down Mode", $realtime);
end else if (enter_APD == 1'b1) begin
$display ("%m: At time %t ERROR: tCKE violation during exiting of Active Power-Down Mode", $realtime);
end
end
if (enter_PD == 1'b1) begin
$display ("%m: at time %t Exiting Power-Down Mode", $realtime);
enter_PD = 1'b0 ;
end else if (enter_APD == 1'b1) begin
$display ("%m: at time %t Exiting Active Power-Down Mode", $realtime);
enter_APD = 1'b0 ;
end
end
end
end
endtask
// Control Logic
task Control_Logic;
begin
// Self Refresh
if (Sref_enable === 1'b1) begin
// Partial Array Self Refresh
if (part_size == 128) begin
case (Ext_Mode_reg[2:0])
3'b000 : ;//keep Bank 0-7
3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0111, 1'b0); end
3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0011, 1'b0); end
3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
3'b101 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
3'b110 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
endcase
end else begin
case (Ext_Mode_reg[2:0])
3'b000 : ;//keep Bank 0-7
3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0111, 1'b0); end
3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0011, 1'b0); end
3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
3'b101 : begin $display("%m: at time %t INFO: Banks 1-3 and 1/2 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0001, 1'b0); end
3'b110 : begin $display("%m: at time %t INFO: Banks 1-3 and 3/4 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0000, 1'b0); end
endcase
end
SelfRefresh = 1'b1;
end
if (Aref_enable === 1'b1) begin
if (Debug) begin
$display ("Debug: At time %t %m:AUTOREFRESH: Auto Refresh", $realtime);
end
// aref_count is to make sure we have met part of the initialization sequence
if (~power_up_done) begin
aref_count = aref_count + 1;
end
// Auto Refresh to Auto Refresh
if ($realtime - RFC_chk < tRFC) begin
$display ("%m: At time %t ERROR: tRFC violation during Auto Refresh", $realtime);
end
// Precharge to Auto Refresh
if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
$display ("%m: At time %t ERROR: tRP violation during Auto Refresh", $realtime);
end
// Precharge to Auto Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m: At time %t ERROR: All banks must be Precharged before Auto Refresh", $realtime);
end
// Record Current tRFC time
RFC_chk = $realtime;
end
// SRR Register
if (srr_enable == 1'b1) begin
if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1 &&
Data_out_enable === 1'b0 && Data_in_enable === 1'b0) begin
SRR_read = 1'b1;
SRR_chk = $realtime;
SRR_cntr = 0;
end
end
// Extended Mode Register
if (Ext_mode_enable == 1'b1) begin
if (Debug) begin
$display ("Debug: At time %t %m:EMR : Extended Mode Register", $realtime);
end
// Register Mode
Ext_Mode_reg = Addr;
if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin
// ensure that power sequence is met properly
if (~power_up_done) begin
ext_mode_load_done = 1'b1;
end
$display ("At time %t %m:ELMR : Extended Load Mode Register", $realtime);
if (part_size == 128) begin
// Self Refresh Coverage
case (Addr[2 : 0])
3'b000 : $display ("%m : Self Refresh Cov = 4 banks");
3'b001 : $display ("%m : Self Refresh Cov = 2 banks");
3'b010 : $display ("%m : Self Refresh Cov = 1 bank");
3'b101 : $display ("%m : PASR = Reserved");
3'b110 : $display ("%m : PASR = Reserved");
default : $display ("%m : PASR = Reserved");
endcase
end else begin
// Self Refresh Coverage
case (Addr[2 : 0])
3'b000 : $display ("%m : Self Refresh Cov = 4 banks");
3'b001 : $display ("%m : Self Refresh Cov = 2 banks");
3'b010 : $display ("%m : Self Refresh Cov = 1 bank");
3'b101 : $display ("%m : Self Refresh Cov = 1/2 bank");
3'b110 : $display ("%m : Self Refresh Cov = 1/4 bank");
default : $display ("%m : PASR = Reserved");
endcase
end
// Maximum Case Temp
case (Addr[4 : 3])
2'b11 : $display ("%m : Maximum Case Temp = 85C");
2'b00 : $display ("%m : Maximum Case Temp = 70C");
2'b01 : $display ("%m : Maximum Case Temp = 45C");
2'b10 : $display ("%m : Maximum Case Temp = 15C");
endcase
// Drive Strength
case (Addr[6 : 5])
2'b00 : $display ("%m : Drive Strength = Full Strength");
2'b01 : $display ("%m : Drive Strength = Half Strength");
2'b10 : $display ("%m : Drive Strength = Quarter Strength");
2'b11 : $display ("%m : Drive Strength = One Eight Strength");
endcase
end else begin
$display ("%m: At time %t ERROR: all banks must be Precharged before Extended Mode Register", $realtime);
end
// Precharge to EMR
if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
$display ("%m: At time %t ERROR: tRP violation during Extended Mode Register", $realtime);
end
// LMR/EMR to LMR/EMR
// if ($realtime - MRD_chk < tMRD) begin
// $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime);
// end
if (MRD_cntr < tMRD) begin
$display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime);
end
// Record current tMRD time
// MRD_chk = $realtime;
MRD_cntr = 0;
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
if (Debug) begin
$display ("Debug: At time %t %m:LMR : Load Mode Register", $realtime);
end
// Register Mode
Mode_reg = Addr;
if (Mode_reg[6:4] == 3'b010) begin
if (tCK2_min == 0) begin
$display ("%m : at time %t ERROR : Illegal CAS Latency of 2 set for current speed grade", $realtime);
end
end
// Precharge to LMR
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m: At time %t ERROR: all banks must be Precharged before Load Mode Register", $realtime);
end
// Precharge to LMR
if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
$display ("%m: At time %t ERROR: tRP violation during Load Mode Register", $realtime);
end
// LMR/EMR to LMR/EMR
// if ($realtime - MRD_chk < tMRD) begin
// $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime);
// end
if (MRD_cntr < tMRD) begin
$display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime);
end
if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin
// ensure that power sequence is met properly
if (~power_up_done) begin
mode_load_done = 1'b1;
end
// Burst Length
case (Addr [2 : 0])
3'b001 : $display ("At time %t %m:LMR : Burst Length = 2", $realtime);
3'b010 : $display ("At time %t %m:LMR : Burst Length = 4", $realtime);
3'b011 : $display ("At time %t %m:LMR : Burst Length = 8", $realtime);
default :
begin
$display ("%m: At time %t ERROR: Undefined burst length selection", $realtime);
$stop;
end
endcase
// CAS Latency
case (Addr [6 : 4])
3'b010 : $display ("At time %t %m:LMR : CAS Latency = 2", $realtime);
3'b011 : $display ("At time %t %m:LMR : CAS Latency = 3", $realtime);
default : begin
$display ("%m: At time %t ERROR: CAS Latency not supported", $realtime);
$stop;
end
endcase
end
// Record current tMRD time
// MRD_chk = $realtime;
MRD_cntr = 0;
end
// Activate Block
if (Active_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $realtime);
end
// Display Debug Message
if (Debug) begin
$display ("Debug: At time %t %m:ACTIVATE: Bank = %d, Row = %d", $realtime, Ba, Addr);
end
// Activating an open bank can cause corruption.
if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) ||
(Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin
$display ("%m: At time %t ERROR: Bank = %d is already activated - data can be corrupted", $realtime, Ba);
end
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// Activate to Activate (same bank)
if ($realtime - RC_chk0 < tRC) begin
$display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
end
// Precharge to Activate
if ($realtime - RP_chk0 < tRP) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
end
// Record variables for checking violation
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr;
RC_chk0 = $realtime;
RCD_chk0 = $realtime;
RAS_chk0 = $realtime;
RAP_chk0 = $realtime;
end
// Activate Bank 1
if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
// Activate to Activate (same bank)
if ($realtime - RC_chk1 < tRC) begin
$display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
end
// Precharge to Activate
if ($realtime - RP_chk1 < tRP) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
end
// Record variables for checking violation
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr;
RC_chk1 = $realtime;
RCD_chk1 = $realtime;
RAS_chk1 = $realtime;
RAP_chk1 = $realtime;
end
// Activate Bank 2
if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
// Activate to Activate (same bank)
if ($realtime - RC_chk2 < tRC) begin
$display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
end
// Precharge to Activate
if ($realtime - RP_chk2 < tRP) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
end
// Record variables for checking violation
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr;
RC_chk2 = $realtime;
RCD_chk2 = $realtime;
RAS_chk2 = $realtime;
RAP_chk2 = $realtime;
end
// Activate Bank 3
if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
// Activate to Activate (same bank)
if ($realtime - RC_chk3 < tRC) begin
$display ("%m: t time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
end
// Precharge to Activate
if ($realtime - RP_chk3 < tRP) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
end
// Record variables for checking violation
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr;
RC_chk3 = $realtime;
RCD_chk3 = $realtime;
RAS_chk3 = $realtime;
RAP_chk3 = $realtime;
end
// Activate to Activate (different bank)
if ((Prev_bank != Ba) && ($realtime - RRD_chk < tRRD)) begin
$display ("%m: At time %t ERROR: tRRD violation during Activate bank = %d", $realtime, Ba);
end
// AutoRefresh to Activate
if ($realtime - RFC_chk < tRFC) begin
$display ("%m: At time %t ERROR: tRFC violation during Activate bank %d", $realtime, Ba);
end
// Record variable for checking violation
RRD_chk = $realtime;
Prev_bank = Ba;
end
// Precharge Block - consider NOP if bank already precharged or in process of precharging
if (Prech_enable === 1'b1) begin
// Display Debug Message
if (Debug) begin
$display ("Debug: At time %t %m:PRE: Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
end
// EMR or LMR to Precharge
// if ($realtime - MRD_chk < tMRD) begin
// $display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime);
// end
if (MRD_cntr < tMRD) begin
$display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime);
end
// Precharge bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $realtime;
// Activate to Precharge Bank
if ($realtime - RAS_chk0 < tRAS) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
end
// tWR violation check for Write
if ($realtime - WR_chk0 < tWR) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
end
end
// Precharge bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $realtime;
// Activate to Precharge Bank 1
if ($realtime - RAS_chk1 < tRAS) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
end
// tWR violation check for Write
if ($realtime - WR_chk1 < tWR) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
end
end
// Precharge bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $realtime;
// Activate to Precharge Bank 2
if ($realtime - RAS_chk2 < tRAS) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
end
// tWR violation check for Write
if ($realtime - WR_chk2 < tWR) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
end
end
// Precharge bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $realtime;
// Activate to Precharge Bank 3
if ($realtime - RAS_chk3 < tRAS) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
end
// tWR violation check for Write
if ($realtime - WR_chk3 < tWR) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
end
end
// Pipeline for READ
A10_precharge [cas_latency_x2] = Addr[10];
Bank_precharge[cas_latency_x2] = Ba;
Cmnd_precharge[cas_latency_x2] = 1'b1;
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Display Debug Message
if (Debug) begin
$display ("Debug: %m: At time %t BURST_TERMINATE): Burst Terminate",$realtime);
end
// Burst Terminate Command Pipeline for Read
Cmnd_bst[cas_latency_x2-1] = 1'b1;
// Illegal to burst terminate a Write
if (Data_in_enable === 1'b1) begin
$display ("%m: At time %t ERROR: It's illegal to burst terminate a Write", $realtime);
end
// Illegal to burst terminate a Read with Auto Precharge
if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 ||
Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin
$display ("%m: At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $realtime);
end
end
// Read Command
if (Read_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $realtime);
end
// Display Debug Message
if (Debug) begin
$display ("Debug: At time %t %m:READ: Bank = %d, Col = %d", $realtime, Ba, {Addr [11], Addr [9 : 0]});
end
if (part_size == 1024) begin
if (SRR_read == 1'b1) begin
if (SRR_cntr < tSRR) begin
$display ("%m: At time %t ERROR: tSRR Violation", $realtime);
end
SRC_cntr = 0 ;
end
end else begin
if (SRR_read == 1'b1) begin
if ($realtime - SRR_chk < tSRR-0.01) begin
$display ("%m: At time %t ERROR: tSRR Violation", $realtime);
end
SRC_cntr = 0;
end
end
// CAS Latency pipeline
Read_cmnd[cas_latency_x2] = 1'b1;
Read_bank[cas_latency_x2] = Ba;
Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
// Terminate a Write
if (Data_in_enable === 1'b1) begin
Data_in_enable = 1'b0;
end
// Interrupt a Read with Auto Precharge
if (Read_precharge [Ba] === 1'b1) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime);
end else if ((Read_precharge [0] === 1'b1) |
(Read_precharge [1] === 1'b1) |
(Read_precharge [2] === 1'b1) |
(Read_precharge [3] === 1'b1) ) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (different banks)", $realtime);
end
// Interrupt a Write with Auto Precharge
if (Write_precharge [Ba] === 1'b1) begin
// $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same banks)", $realtime);
end else if ((Write_precharge_count [0] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
(Write_precharge_count [1] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
(Write_precharge_count [2] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
(Write_precharge_count [3] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
(Write_precharge_count [0] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
(Write_precharge_count [1] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
(Write_precharge_count [2] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
(Write_precharge_count [3] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) ) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Write with Auto Precharge (different banks)", $realtime);
end
// Activate to Read
if (((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) &&
(SRR_read == 1'b0)) begin
$display("%m: At time %t ERROR: Bank is not Activated for Read", $realtime);
end
// Activate to Read without Auto Precharge
if ((Addr [10] === 1'b0 && Ba === 2'b00 && $realtime - RCD_chk0 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b01 && $realtime - RCD_chk1 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b10 && $realtime - RCD_chk2 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b11 && $realtime - RCD_chk3 < tRCD)) begin
$display("%m: At time %t ERROR: tRCD violation during Read", $realtime);
end
// Auto Precharge
if (Addr[10] === 1'b1) begin
Read_precharge [Ba]= 1'b1;
Count_precharge [Ba]= 0;
Read_precharge_count[Ba] = 4'h0;
end
end
// Write Command
if (Write_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $realtime);
end
// display debug message
if (Debug) begin
$display ("Debug: At time %t %m:WRITE: Bank = %d, Col = %d", $realtime, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});
end
// Pipeline for Write
Write_cmnd [3] = 1'b1;
Write_bank [3] = Ba;
Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
// Interrupt a Write with Auto Precharge (same bank only)
if (Write_precharge [Ba] === 1'b1) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge", $realtime);
end
// Activate to Write
if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
$display("%m: At time %t ERROR: Bank is not Activated for Write", $realtime);
end
// Activate to Write
if ((Ba === 2'b00 && $realtime - RCD_chk0 < tRCD) ||
(Ba === 2'b01 && $realtime - RCD_chk1 < tRCD) ||
(Ba === 2'b10 && $realtime - RCD_chk2 < tRCD) ||
(Ba === 2'b11 && $realtime - RCD_chk3 < tRCD)) begin
$display("%m: At time %t ERROR: tRCD violation during Write to Bank %d", $realtime, Ba);
end
// Read to Write
if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] ||
Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter_dly < burst_length)) begin
if (Data_out_enable_dly || read_precharge_truncation) begin
$display("%m: At time %t ERROR: Read to Write violation", $realtime);
end
end
// Interrupt a Write with Auto Precharge
if (Write_precharge [Ba] === 1'b1) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same bank)", $realtime);
end else if (((Write_precharge [0] === 1'b1) & (Count_precharge[0] < (burst_length/2))) |
((Write_precharge [1] === 1'b1) & (Count_precharge[1] < (burst_length/2))) |
((Write_precharge [2] === 1'b1) & (Count_precharge[2] < (burst_length/2))) |
((Write_precharge [3] === 1'b1) & (Count_precharge[3] < (burst_length/2))) ) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (different bank)", $realtime);
end
// Interrupt a Read with Auto Precharge
if (((Read_precharge_count [Ba] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
((Read_precharge_count [Ba] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin
// $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime);
end else if (((Read_precharge_count [0] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
((Read_precharge_count [1] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
((Read_precharge_count [2] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
((Read_precharge_count [3] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
((Read_precharge_count [0] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
((Read_precharge_count [1] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
((Read_precharge_count [2] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
((Read_precharge_count [3] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Read with Auto Precharge (different bank)", $realtime);
end
// Auto Precharge
if (Addr[10] === 1'b1) begin
Write_precharge [Ba]= 1'b1;
Count_precharge [Ba]= 0;
Write_precharge_count[Ba] = 4'h0;
end
end
end
endtask
// Main Logic
always @ (posedge Sys_clk) begin
Manual_Precharge_Pipeline;
Burst_Terminate_Pipeline;
Dq_Dqs_Drivers;
Write_FIFO_DM_Mask_Logic;
Burst_Decode;
Auto_Precharge_Calculation;
Timing_chk_SRC;
Control_Logic;
MRD_counter;
SRR_counter;
SRC_counter;
command_counter;
end
always @ (negedge Sys_clk) begin
Manual_Precharge_Pipeline;
Burst_Terminate_Pipeline;
Dq_Dqs_Drivers;
Write_FIFO_DM_Mask_Logic;
Burst_Decode;
end
// Dqs Receiver
always @ (posedge Dqs_in[0]) begin
// Latch data at posedge Dqs
dq_rise[7 : 0] = Dq_in[7 : 0];
dm_rise[0] = Dm_in[0];
expect_pos_dqs[0] = 0;
end
always @ (posedge Dqs_in[1]) begin
// Latch data at posedge Dqs
dq_rise[15 : 8] = Dq_in[15 : 8];
dm_rise[1] = Dm_in [1];
expect_pos_dqs[1] = 0;
end
`ifdef x32
always @ (posedge Dqs_in[2]) begin
// Latch data at posedge Dqs
dq_rise[23 : 16] = Dq_in[23 : 16];
dm_rise[2] = Dm_in [2];
expect_pos_dqs[2] = 0;
end
always @ (posedge Dqs_in[3]) begin
// Latch data at posedge Dqs
dq_rise[31 : 24] = Dq_in[31 : 24];
dm_rise[3] = Dm_in [3];
expect_pos_dqs[3] = 0;
end
`endif
always @ (negedge Dqs_in[0]) begin
// Latch data at negedge Dqs
dq_fall[7 : 0] = Dq_in[7 : 0];
dm_fall[0] = Dm_in[0];
dm_pair[1:0] = {dm_rise[0], dm_fall[0]};
expect_neg_dqs[0] = 0;
end
always @ (negedge Dqs_in[1]) begin
// Latch data at negedge Dqs
dq_fall[15: 8] = Dq_in[15 : 8];
dm_fall[1] = Dm_in[1];
dm_pair[3:2] = {dm_rise[1], dm_fall[1]};
expect_neg_dqs[1] = 0;
end
`ifdef x32
always @ (negedge Dqs_in[2]) begin
// Latch data at negedge Dqs
dq_fall[23: 16] = Dq_in[23 : 16];
dm_fall[2] = Dm_in[2];
dm_pair[5:4] = {dm_rise[2], dm_fall[2]};
expect_neg_dqs[2] = 0;
end
always @ (negedge Dqs_in[3]) begin
// Latch data at negedge Dqs
dq_fall[31: 24] = Dq_in[31 : 24];
dm_fall[3] = Dm_in[3];
dm_pair[7:6] = {dm_rise[3], dm_fall[3]};
expect_neg_dqs[3] = 0;
end
`endif
// Dqs edge checking
always @ (posedge Sys_clk) begin
if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if (expect_neg_dqs[i]) begin
$display ("%m: At time %t ERROR: Negative DQS[%1d] transition required.", $realtime, i);
end
expect_neg_dqs[i] = 1'b1;
end
end else begin
expect_neg_dqs = 0;
expect_pos_dqs = 0;
end
end
always @ (negedge Sys_clk) begin
if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if (expect_pos_dqs[i]) begin
$display ("%m: At time %t ERROR: Positive DQS[%1d] transition required.", $realtime, i);
end
expect_pos_dqs[i] = 1'b1;
end
end else begin
expect_neg_dqs = 0;
expect_pos_dqs = 0;
end
end
specify
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef sg5 // specparams for -6 (CL = 3)
specparam tCLK_MIN = 5.0 ; // tCLK ns minimum clk cycle time
specparam tDSS = 1.0 ; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.0 ; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.0 ; // tIH ns Input Hold Time (fast)
specparam tIS = 1.0 ; // tIS ns Input Setup Time (fast)
specparam tDQSH = 1.75; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 1.75; // tDQSL ns DQS input Low Pulse Width
`else `ifdef sg6 // specparams for -6 (CL = 3)
specparam tCLK_MIN = 6.0; // tCLK ns minimum clk cycle time
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.1; // tIH ns Input Hold Time (fast)
specparam tIS = 1.1; // tIS ns Input Setup Time (fast)
specparam tDQSH = 2.1; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 2.1; // tDQSL ns DQS input Low Pulse Width
`else `ifdef sg75 // specparams for -75 (CL = 3)
specparam tCLK_MIN = 7.5; // tCLK ns minimum clk cycle time
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.3; // tIH ns Input Hold Time (fast)
specparam tIS = 1.3; // tIS ns Input Setup Time (fast)
specparam tDQSH = 3.0; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 3.0; // tDQSL ns DQS input Low Pulse Width
`else`ifdef sg5v18 // specparams for -6 (CL = 3)
specparam tCLK_MIN = 5.0 ; // tCLK ns minimum clk cycle time
specparam tDSS = 1.0 ; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.0 ; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 0.9 ; // tIH ns Input Hold Time (fast)
specparam tIS = 0.9 ; // tIS ns Input Setup Time (fast)
specparam tDQSH = 2.0 ; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 2.0 ; // tDQSL ns DQS input Low Pulse Width
`else `ifdef sg6v18 // specparams for -6 (CL = 3)
specparam tCLK_MIN = 6.0; // tCLK ns minimum clk cycle time
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.1; // tIH ns Input Hold Time (fast)
specparam tIS = 1.1; // tIS ns Input Setup Time (fast)
specparam tDQSH = 2.4; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 2.4; // tDQSL ns DQS input Low Pulse Width
`else `ifdef sg75v18 // specparams for -75 (CL = 3)
specparam tCLK_MIN = 7.5; // tCLK ns minimum clk cycle time
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.3; // tIH ns Input Hold Time (fast)
specparam tIS = 1.3; // tIS ns Input Setup Time (fast)
specparam tDQSH = 3.0; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 3.0; // tDQSL ns DQS input Low Pulse Width
`else `ifdef sg6v12 // specparams for -6 (CL = 3)
specparam tCLK_MIN = 6.0; // tCLK ns minimum clk cycle time
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.1; // tIH ns Input Hold Time (fast)
specparam tIS = 1.1; // tIS ns Input Setup Time (fast)
specparam tDQSH = 2.1; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 2.1; // tDQSL ns DQS input Low Pulse Width
`else `ifdef sg75v12 // specparams for -75 (CL = 3)
specparam tCLK_MIN = 7.5; // tCLK ns minimum clk cycle time
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.3; // tIH ns Input Hold Time (fast)
specparam tIS = 1.3; // tIS ns Input Setup Time (fast)
specparam tDQSH = 3.0; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 3.0; // tDQSL ns DQS input Low Pulse Width
`else `ifdef sg10v12 // specparams for -10 (CL = 3)
specparam tCLK_MIN = 9.6; // tCLK ns minimum clk cycle time
specparam tDSS = 1.92; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.92; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.7; // tIH ns Input Hold Time (fast)
specparam tIS = 1.7; // tIS ns Input Setup Time (fast)
specparam tDQSH = 3.84; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 3.84; // tDQSL ns DQS input Low Pulse Width
`else `ifdef sg10 // specparams for -10 (CL = 3)
specparam tCLK_MIN = 9.6; // tCLK ns minimum clk cycle time
specparam tDSS = 1.92; // tDSS ns DQS falling edge to CLK rising (setup time)
specparam tDSH = 1.92; // tDSH ns DQS falling edge from CLK rising (hold time)
specparam tIH = 1.5; // tIH ns Input Hold Time (fast)
specparam tIS = 1.5; // tIS ns Input Setup Time (fast)
specparam tDQSH = 3.84; // tDQSH ns DQS input High Pulse Width
specparam tDQSL = 3.84; // tDQSL ns DQS input Low Pulse Width
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
$period (posedge Clk, tCLK_MIN);
$width (posedge Dqs_in[0] &&& wdqs_valid, tDQSH);
$width (posedge Dqs_in[1] &&& wdqs_valid, tDQSH);
$width (negedge Dqs_in[0] &&& wdqs_valid, tDQSL);
$width (negedge Dqs_in[1] &&& wdqs_valid, tDQSL);
$setuphold(posedge Clk, Cke, tIS, tIH);
$setuphold(posedge Clk, Cs_n, tIS, tIH);
$setuphold(posedge Clk, Cas_n, tIS, tIH);
$setuphold(posedge Clk, Ras_n, tIS, tIH);
$setuphold(posedge Clk, We_n, tIS, tIH);
$setuphold(posedge Clk, Addr, tIS, tIH);
$setuphold(posedge Clk, Ba, tIS, tIH);
$setuphold(posedge Clk, negedge Dqs &&& wdqs_valid, tDSS , tDSH);
endspecify
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O221AI_BEHAVIORAL_PP_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221AI_BEHAVIORAL_PP_V |
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: tb_openMSP430_fpga.v
//
// *Module Description:
// openMSP430 FPGA testbench
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`include "timescale.v"
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module tb_openMSP430_fpga;
//
// Wire & Register definition
//------------------------------
// Clock & Reset
reg CLK_50MHz;
reg RESET;
// Slide Switches
reg SW7;
reg SW6;
reg SW5;
reg SW4;
reg SW3;
reg SW2;
reg SW1;
reg SW0;
// Push Button Switches
reg BTN2;
reg BTN1;
reg BTN0;
// LEDs
wire LED7;
wire LED6;
wire LED5;
wire LED4;
wire LED3;
wire LED2;
wire LED1;
wire LED0;
// Four-Sigit, Seven-Segment LED Display
wire SEG_A;
wire SEG_B;
wire SEG_C;
wire SEG_D;
wire SEG_E;
wire SEG_F;
wire SEG_G;
wire SEG_DP;
wire SEG_AN0;
wire SEG_AN1;
wire SEG_AN2;
wire SEG_AN3;
// UART
reg UART_RXD;
wire UART_TXD;
// Core debug signals
wire [8*32-1:0] i_state;
wire [8*32-1:0] e_state;
wire [31:0] inst_cycle;
wire [8*32-1:0] inst_full;
wire [31:0] inst_number;
wire [15:0] inst_pc;
wire [8*32-1:0] inst_short;
// Testbench variables
integer i;
integer error;
reg stimulus_done;
//
// Include files
//------------------------------
// CPU & Memory registers
`include "registers.v"
// Verilog stimulus
`include "stimulus.v"
//
// Initialize Program Memory
//------------------------------
initial
begin
// Read memory file
#10 $readmemh("./pmem.mem", pmem);
// Update Xilinx memory banks
for (i=0; i<2048; i=i+1)
begin
dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];
dut.rom_8x2k_lo_0.inst.mem[i] = pmem[i][7:0];
end
end
//
// Generate Clock & Reset
//------------------------------
initial
begin
CLK_50MHz = 1'b0;
forever #10 CLK_50MHz <= ~CLK_50MHz; // 50 MHz
end
initial
begin
RESET = 1'b0;
#100 RESET = 1'b1;
#600 RESET = 1'b0;
end
//
// Global initialization
//------------------------------
initial
begin
error = 0;
stimulus_done = 1;
SW7 = 1'b0; // Slide Switches
SW6 = 1'b0;
SW5 = 1'b0;
SW4 = 1'b0;
SW3 = 1'b0;
SW2 = 1'b0;
SW1 = 1'b0;
SW0 = 1'b0;
BTN2 = 1'b0; // Push Button Switches
BTN1 = 1'b0;
BTN0 = 1'b0;
UART_RXD = 1'b0; // UART
end
//
// openMSP430 FPGA Instance
//----------------------------------
openMSP430_fpga dut (
// Clock Sources
.CLK_50MHz (CLK_50MHz),
.CLK_SOCKET (1'b0),
// Slide Switches
.SW7 (SW7),
.SW6 (SW6),
.SW5 (SW5),
.SW4 (SW4),
.SW3 (SW3),
.SW2 (SW2),
.SW1 (SW1),
.SW0 (SW0),
// Push Button Switches
.BTN3 (RESET),
.BTN2 (BTN2),
.BTN1 (BTN1),
.BTN0 (BTN0),
// LEDs
.LED7 (LED7),
.LED6 (LED6),
.LED5 (LED5),
.LED4 (LED4),
.LED3 (LED3),
.LED2 (LED2),
.LED1 (LED1),
.LED0 (LED0),
// Four-Sigit, Seven-Segment LED Display
.SEG_A (SEG_A),
.SEG_B (SEG_B),
.SEG_C (SEG_C),
.SEG_D (SEG_D),
.SEG_E (SEG_E),
.SEG_F (SEG_F),
.SEG_G (SEG_G),
.SEG_DP (SEG_DP),
.SEG_AN0 (SEG_AN0),
.SEG_AN1 (SEG_AN1),
.SEG_AN2 (SEG_AN2),
.SEG_AN3 (SEG_AN3),
// RS-232 Port
.UART_RXD (UART_RXD),
.UART_TXD (UART_TXD),
.UART_RXD_A (1'b0),
.UART_TXD_A (UART_TXD_A),
// PS/2 Mouse/Keyboard Port
.PS2_D (PS2_D),
.PS2_C (PS2_C),
// Fast, Asynchronous SRAM
.SRAM_A17 (SRAM_A17), // Address Bus Connections
.SRAM_A16 (SRAM_A16),
.SRAM_A15 (SRAM_A15),
.SRAM_A14 (SRAM_A14),
.SRAM_A13 (SRAM_A13),
.SRAM_A12 (SRAM_A12),
.SRAM_A11 (SRAM_A11),
.SRAM_A10 (SRAM_A10),
.SRAM_A9 (SRAM_A9),
.SRAM_A8 (SRAM_A8),
.SRAM_A7 (SRAM_A7),
.SRAM_A6 (SRAM_A6),
.SRAM_A5 (SRAM_A5),
.SRAM_A4 (SRAM_A4),
.SRAM_A3 (SRAM_A3),
.SRAM_A2 (SRAM_A2),
.SRAM_A1 (SRAM_A1),
.SRAM_A0 (SRAM_A0),
.SRAM_OE (SRAM_OE), // Write enable and output enable control signals
.SRAM_WE (SRAM_WE),
.SRAM0_IO15 (SRAM0_IO15), // SRAM Data signals, chip enables, and byte enables
.SRAM0_IO14 (SRAM0_IO14),
.SRAM0_IO13 (SRAM0_IO13),
.SRAM0_IO12 (SRAM0_IO12),
.SRAM0_IO11 (SRAM0_IO11),
.SRAM0_IO10 (SRAM0_IO10),
.SRAM0_IO9 (SRAM0_IO9),
.SRAM0_IO8 (SRAM0_IO8),
.SRAM0_IO7 (SRAM0_IO7),
.SRAM0_IO6 (SRAM0_IO6),
.SRAM0_IO5 (SRAM0_IO5),
.SRAM0_IO4 (SRAM0_IO4),
.SRAM0_IO3 (SRAM0_IO3),
.SRAM0_IO2 (SRAM0_IO2),
.SRAM0_IO1 (SRAM0_IO1),
.SRAM0_IO0 (SRAM0_IO0),
.SRAM0_CE1 (SRAM0_CE1),
.SRAM0_UB1 (SRAM0_UB1),
.SRAM0_LB1 (SRAM0_LB1),
.SRAM1_IO15 (SRAM1_IO15),
.SRAM1_IO14 (SRAM1_IO14),
.SRAM1_IO13 (SRAM1_IO13),
.SRAM1_IO12 (SRAM1_IO12),
.SRAM1_IO11 (SRAM1_IO11),
.SRAM1_IO10 (SRAM1_IO10),
.SRAM1_IO9 (SRAM1_IO9),
.SRAM1_IO8 (SRAM1_IO8),
.SRAM1_IO7 (SRAM1_IO7),
.SRAM1_IO6 (SRAM1_IO6),
.SRAM1_IO5 (SRAM1_IO5),
.SRAM1_IO4 (SRAM1_IO4),
.SRAM1_IO3 (SRAM1_IO3),
.SRAM1_IO2 (SRAM1_IO2),
.SRAM1_IO1 (SRAM1_IO1),
.SRAM1_IO0 (SRAM1_IO0),
.SRAM1_CE2 (SRAM1_CE2),
.SRAM1_UB2 (SRAM1_UB2),
.SRAM1_LB2 (SRAM1_LB2),
// VGA Port
.VGA_R (VGA_R),
.VGA_G (VGA_G),
.VGA_B (VGA_B),
.VGA_HS (VGA_HS),
.VGA_VS (VGA_VS)
);
//
// Debug utility signals
//----------------------------------------
msp_debug msp_debug_0 (
// OUTPUTs
.e_state (e_state), // Execution state
.i_state (i_state), // Instruction fetch state
.inst_cycle (inst_cycle), // Cycle number within current instruction
.inst_full (inst_full), // Currently executed instruction (full version)
.inst_number (inst_number), // Instruction number since last system reset
.inst_pc (inst_pc), // Instruction Program counter
.inst_short (inst_short), // Currently executed instruction (short version)
// INPUTs
.mclk (mclk), // Main system clock
.puc_rst (puc_rst) // Main system reset
);
//
// Generate Waveform
//----------------------------------------
initial
begin
`ifdef VPD_FILE
$vcdplusfile("tb_openMSP430_fpga.vpd");
$vcdpluson();
`else
`ifdef TRN_FILE
$recordfile ("tb_openMSP430_fpga.trn");
$recordvars;
`else
$dumpfile("tb_openMSP430_fpga.vcd");
$dumpvars(0, tb_openMSP430_fpga);
`endif
`endif
end
//
// End of simulation
//----------------------------------------
initial // Timeout
begin
`ifdef NO_TIMEOUT
`else
`ifdef VERY_LONG_TIMEOUT
#500000000;
`else
`ifdef LONG_TIMEOUT
#5000000;
`else
#500000;
`endif
`endif
$display(" ===============================================");
$display("| SIMULATION FAILED |");
$display("| (simulation Timeout) |");
$display(" ===============================================");
$finish;
`endif
end
initial // Normal end of test
begin
@(inst_pc===16'hffff)
$display(" ===============================================");
if (error!=0)
begin
$display("| SIMULATION FAILED |");
$display("| (some verilog stimulus checks failed) |");
end
else if (~stimulus_done)
begin
$display("| SIMULATION FAILED |");
$display("| (the verilog stimulus didn't complete) |");
end
else
begin
$display("| SIMULATION PASSED |");
end
$display(" ===============================================");
$finish;
end
//
// Tasks Definition
//------------------------------
task tb_error;
input [65*8:0] error_string;
begin
$display("ERROR: %s %t", error_string, $time);
error = error+1;
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_PP_SYMBOL_V
`define SKY130_FD_SC_HD__TAPVPWRVGND_PP_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvpwrvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21AI_2_V
`define SKY130_FD_SC_HDLL__O21AI_2_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ai_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21AI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311O_2_V
`define SKY130_FD_SC_LS__A311O_2_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311o_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311O_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O41A_FUNCTIONAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_FUNCTIONAL_PP_V |
module mult_wrap (
input ck,
input [63:0] i_a, i_b,
input [8:0] i_htId,
input i_vld,
output [63:0] o_res,
output [8:0] o_htId,
output o_vld
);
// Wires & Registers
wire [63:0] c_t19_res;
wire [8:0] c_t1_htId;
wire c_t1_vld;
reg [8:0] r_t2_htId, r_t3_htId, r_t4_htId, r_t5_htId, r_t6_htId, r_t7_htId, r_t8_htId, r_t9_htId, r_t10_htId, r_t11_htId, r_t12_htId, r_t13_htId, r_t14_htId, r_t15_htId, r_t16_htId, r_t17_htId, r_t18_htId, r_t19_htId;
reg r_t2_vld, r_t3_vld, r_t4_vld, r_t5_vld, r_t6_vld, r_t7_vld, r_t8_vld, r_t9_vld, r_t10_vld, r_t11_vld, r_t12_vld, r_t13_vld, r_t14_vld, r_t15_vld, r_t16_vld, r_t17_vld, r_t18_vld, r_t19_vld;
// The following example uses a fixed-length pipeline,
// but could be used with any length or a variable length pipeline.
always @(posedge ck) begin
r_t2_htId <= c_t1_htId;
r_t2_vld <= c_t1_vld;
r_t3_htId <= r_t2_htId;
r_t3_vld <= r_t2_vld;
r_t4_htId <= r_t3_htId;
r_t4_vld <= r_t3_vld;
r_t5_htId <= r_t4_htId;
r_t5_vld <= r_t4_vld;
r_t6_htId <= r_t5_htId;
r_t6_vld <= r_t5_vld;
r_t7_htId <= r_t6_htId;
r_t7_vld <= r_t6_vld;
r_t8_htId <= r_t7_htId;
r_t8_vld <= r_t7_vld;
r_t9_htId <= r_t8_htId;
r_t9_vld <= r_t8_vld;
r_t10_htId <= r_t9_htId;
r_t10_vld <= r_t9_vld;
r_t11_htId <= r_t10_htId;
r_t11_vld <= r_t10_vld;
r_t12_htId <= r_t11_htId;
r_t12_vld <= r_t11_vld;
r_t13_htId <= r_t12_htId;
r_t13_vld <= r_t12_vld;
r_t14_htId <= r_t13_htId;
r_t14_vld <= r_t13_vld;
r_t15_htId <= r_t14_htId;
r_t15_vld <= r_t14_vld;
r_t16_htId <= r_t15_htId;
r_t16_vld <= r_t15_vld;
r_t17_htId <= r_t16_htId;
r_t17_vld <= r_t16_vld;
r_t18_htId <= r_t17_htId;
r_t18_vld <= r_t17_vld;
r_t19_htId <= r_t18_htId;
r_t19_vld <= r_t18_vld;
end
// Black box instantiation
mul_64b_int multiplier (.clk(ck), .a(i_a), .b(i_b), .p(c_t19_res));
// Inputs
assign c_t1_htId = i_htId;
assign c_t1_vld = i_vld;
// Outputs
assign o_res = c_t19_res;
assign o_htId = r_t19_htId;
assign o_vld = r_t19_vld;
endmodule |
// soc_system_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_system_hps_0 #(
parameter F2S_Width = 3,
parameter S2F_Width = 3
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire f2h_cold_rst_req_n, // f2h_cold_reset_req.reset_n
input wire f2h_dbg_rst_req_n, // f2h_debug_reset_req.reset_n
input wire f2h_warm_rst_req_n, // f2h_warm_reset_req.reset_n
input wire [27:0] f2h_stm_hwevents, // f2h_stm_hw_events.stm_hwevents
input wire f2h_axi_clk, // f2h_axi_clock.clk
input wire [7:0] f2h_AWID, // f2h_axi_slave.awid
input wire [31:0] f2h_AWADDR, // .awaddr
input wire [3:0] f2h_AWLEN, // .awlen
input wire [2:0] f2h_AWSIZE, // .awsize
input wire [1:0] f2h_AWBURST, // .awburst
input wire [1:0] f2h_AWLOCK, // .awlock
input wire [3:0] f2h_AWCACHE, // .awcache
input wire [2:0] f2h_AWPROT, // .awprot
input wire f2h_AWVALID, // .awvalid
output wire f2h_AWREADY, // .awready
input wire [4:0] f2h_AWUSER, // .awuser
input wire [7:0] f2h_WID, // .wid
input wire [127:0] f2h_WDATA, // .wdata
input wire [15:0] f2h_WSTRB, // .wstrb
input wire f2h_WLAST, // .wlast
input wire f2h_WVALID, // .wvalid
output wire f2h_WREADY, // .wready
output wire [7:0] f2h_BID, // .bid
output wire [1:0] f2h_BRESP, // .bresp
output wire f2h_BVALID, // .bvalid
input wire f2h_BREADY, // .bready
input wire [7:0] f2h_ARID, // .arid
input wire [31:0] f2h_ARADDR, // .araddr
input wire [3:0] f2h_ARLEN, // .arlen
input wire [2:0] f2h_ARSIZE, // .arsize
input wire [1:0] f2h_ARBURST, // .arburst
input wire [1:0] f2h_ARLOCK, // .arlock
input wire [3:0] f2h_ARCACHE, // .arcache
input wire [2:0] f2h_ARPROT, // .arprot
input wire f2h_ARVALID, // .arvalid
output wire f2h_ARREADY, // .arready
input wire [4:0] f2h_ARUSER, // .aruser
output wire [7:0] f2h_RID, // .rid
output wire [127:0] f2h_RDATA, // .rdata
output wire [1:0] f2h_RRESP, // .rresp
output wire f2h_RLAST, // .rlast
output wire f2h_RVALID, // .rvalid
input wire f2h_RREADY, // .rready
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [127:0] h2f_WDATA, // .wdata
output wire [15:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [127:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
input wire [31:0] f2h_irq_p0, // f2h_irq0.irq
input wire [31:0] f2h_irq_p1, // f2h_irq1.irq
output wire spim0_txd, // spim0.txd
input wire spim0_rxd, // .rxd
input wire spim0_ss_in_n, // .ss_in_n
output wire spim0_ssi_oe_n, // .ssi_oe_n
output wire spim0_ss_0_n, // .ss_0_n
output wire spim0_ss_1_n, // .ss_1_n
output wire spim0_ss_2_n, // .ss_2_n
output wire spim0_ss_3_n, // .ss_3_n
output wire spim0_sclk_out, // spim0_sclk_out.clk
input wire uart1_cts, // uart1.cts
input wire uart1_dsr, // .dsr
input wire uart1_dcd, // .dcd
input wire uart1_ri, // .ri
output wire uart1_dtr, // .dtr
output wire uart1_rts, // .rts
output wire uart1_out1_n, // .out1_n
output wire uart1_out2_n, // .out2_n
input wire uart1_rxd, // .rxd
output wire uart1_txd, // .txd
input wire i2c_emac0_scl, // i2c2_scl_in.clk
output wire i2c_emac0_out_clk, // i2c2_clk.clk
output wire i2c_emac0_out_data, // i2c2.out_data
input wire i2c_emac0_sda, // .sda
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 3)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 3)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
soc_system_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.f2h_cold_rst_req_n (f2h_cold_rst_req_n), // f2h_cold_reset_req.reset_n
.f2h_dbg_rst_req_n (f2h_dbg_rst_req_n), // f2h_debug_reset_req.reset_n
.f2h_warm_rst_req_n (f2h_warm_rst_req_n), // f2h_warm_reset_req.reset_n
.f2h_stm_hwevents (f2h_stm_hwevents), // f2h_stm_hw_events.stm_hwevents
.f2h_axi_clk (f2h_axi_clk), // f2h_axi_clock.clk
.f2h_AWID (f2h_AWID), // f2h_axi_slave.awid
.f2h_AWADDR (f2h_AWADDR), // .awaddr
.f2h_AWLEN (f2h_AWLEN), // .awlen
.f2h_AWSIZE (f2h_AWSIZE), // .awsize
.f2h_AWBURST (f2h_AWBURST), // .awburst
.f2h_AWLOCK (f2h_AWLOCK), // .awlock
.f2h_AWCACHE (f2h_AWCACHE), // .awcache
.f2h_AWPROT (f2h_AWPROT), // .awprot
.f2h_AWVALID (f2h_AWVALID), // .awvalid
.f2h_AWREADY (f2h_AWREADY), // .awready
.f2h_AWUSER (f2h_AWUSER), // .awuser
.f2h_WID (f2h_WID), // .wid
.f2h_WDATA (f2h_WDATA), // .wdata
.f2h_WSTRB (f2h_WSTRB), // .wstrb
.f2h_WLAST (f2h_WLAST), // .wlast
.f2h_WVALID (f2h_WVALID), // .wvalid
.f2h_WREADY (f2h_WREADY), // .wready
.f2h_BID (f2h_BID), // .bid
.f2h_BRESP (f2h_BRESP), // .bresp
.f2h_BVALID (f2h_BVALID), // .bvalid
.f2h_BREADY (f2h_BREADY), // .bready
.f2h_ARID (f2h_ARID), // .arid
.f2h_ARADDR (f2h_ARADDR), // .araddr
.f2h_ARLEN (f2h_ARLEN), // .arlen
.f2h_ARSIZE (f2h_ARSIZE), // .arsize
.f2h_ARBURST (f2h_ARBURST), // .arburst
.f2h_ARLOCK (f2h_ARLOCK), // .arlock
.f2h_ARCACHE (f2h_ARCACHE), // .arcache
.f2h_ARPROT (f2h_ARPROT), // .arprot
.f2h_ARVALID (f2h_ARVALID), // .arvalid
.f2h_ARREADY (f2h_ARREADY), // .arready
.f2h_ARUSER (f2h_ARUSER), // .aruser
.f2h_RID (f2h_RID), // .rid
.f2h_RDATA (f2h_RDATA), // .rdata
.f2h_RRESP (f2h_RRESP), // .rresp
.f2h_RLAST (f2h_RLAST), // .rlast
.f2h_RVALID (f2h_RVALID), // .rvalid
.f2h_RREADY (f2h_RREADY), // .rready
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY), // .rready
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY), // .rready
.f2h_irq_p0 (f2h_irq_p0), // f2h_irq0.irq
.f2h_irq_p1 (f2h_irq_p1), // f2h_irq1.irq
.spim0_txd (spim0_txd), // spim0.txd
.spim0_rxd (spim0_rxd), // .rxd
.spim0_ss_in_n (spim0_ss_in_n), // .ss_in_n
.spim0_ssi_oe_n (spim0_ssi_oe_n), // .ssi_oe_n
.spim0_ss_0_n (spim0_ss_0_n), // .ss_0_n
.spim0_ss_1_n (spim0_ss_1_n), // .ss_1_n
.spim0_ss_2_n (spim0_ss_2_n), // .ss_2_n
.spim0_ss_3_n (spim0_ss_3_n), // .ss_3_n
.spim0_sclk_out (spim0_sclk_out), // spim0_sclk_out.clk
.uart1_cts (uart1_cts), // uart1.cts
.uart1_dsr (uart1_dsr), // .dsr
.uart1_dcd (uart1_dcd), // .dcd
.uart1_ri (uart1_ri), // .ri
.uart1_dtr (uart1_dtr), // .dtr
.uart1_rts (uart1_rts), // .rts
.uart1_out1_n (uart1_out1_n), // .out1_n
.uart1_out2_n (uart1_out2_n), // .out2_n
.uart1_rxd (uart1_rxd), // .rxd
.uart1_txd (uart1_txd), // .txd
.i2c_emac0_scl (i2c_emac0_scl), // i2c2_scl_in.clk
.i2c_emac0_out_clk (i2c_emac0_out_clk), // i2c2_clk.clk
.i2c_emac0_out_data (i2c_emac0_out_data), // i2c2.out_data
.i2c_emac0_sda (i2c_emac0_sda) // .sda
);
soc_system_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:30:37 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_rgb888_to_g8_1_0 -prefix
// system_rgb888_to_g8_1_0_ system_rgb888_to_g8_1_0_sim_netlist.v
// Design : system_rgb888_to_g8_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_rgb888_to_g8_1_0_rgb888_to_g8
(g8,
clk,
rgb888);
output [7:0]g8;
input clk;
input [23:0]rgb888;
wire _carry__0_i_1_n_0;
wire _carry__0_i_2_n_0;
wire _carry__0_i_3_n_0;
wire _carry__0_i_4_n_0;
wire _carry__0_n_0;
wire _carry__0_n_1;
wire _carry__0_n_2;
wire _carry__0_n_3;
wire _carry__1_i_1_n_0;
wire _carry__1_n_2;
wire _carry_i_1_n_0;
wire _carry_i_2_n_0;
wire _carry_i_3_n_0;
wire _carry_i_4_n_0;
wire _carry_i_5_n_0;
wire _carry_n_0;
wire _carry_n_1;
wire _carry_n_2;
wire _carry_n_3;
wire clk;
wire [7:0]g8;
wire [7:0]g810_in;
wire g81__120_carry__0_i_1_n_0;
wire g81__120_carry__0_i_2_n_0;
wire g81__120_carry__0_i_3_n_0;
wire g81__120_carry__0_i_4_n_0;
wire g81__120_carry__0_n_0;
wire g81__120_carry__0_n_1;
wire g81__120_carry__0_n_2;
wire g81__120_carry__0_n_3;
wire g81__120_carry__0_n_4;
wire g81__120_carry__0_n_5;
wire g81__120_carry__0_n_6;
wire g81__120_carry__0_n_7;
wire g81__120_carry__1_i_1_n_0;
wire g81__120_carry__1_i_2_n_0;
wire g81__120_carry__1_i_3_n_0;
wire g81__120_carry__1_i_4_n_0;
wire g81__120_carry__1_n_0;
wire g81__120_carry__1_n_1;
wire g81__120_carry__1_n_2;
wire g81__120_carry__1_n_3;
wire g81__120_carry__1_n_4;
wire g81__120_carry__1_n_5;
wire g81__120_carry__1_n_6;
wire g81__120_carry__1_n_7;
wire g81__120_carry__2_i_1_n_0;
wire g81__120_carry__2_i_2_n_0;
wire g81__120_carry__2_n_1;
wire g81__120_carry__2_n_3;
wire g81__120_carry__2_n_6;
wire g81__120_carry__2_n_7;
wire g81__120_carry_i_1_n_0;
wire g81__120_carry_i_2_n_0;
wire g81__120_carry_i_3_n_0;
wire g81__120_carry_i_4_n_0;
wire g81__120_carry_i_5_n_0;
wire g81__120_carry_i_6_n_0;
wire g81__120_carry_n_0;
wire g81__120_carry_n_1;
wire g81__120_carry_n_2;
wire g81__120_carry_n_3;
wire g81__120_carry_n_4;
wire g81__120_carry_n_5;
wire g81__120_carry_n_6;
wire g81__149_carry__0_i_1_n_0;
wire g81__149_carry__0_i_2_n_0;
wire g81__149_carry__0_i_3_n_0;
wire g81__149_carry__0_i_4_n_0;
wire g81__149_carry__0_i_5_n_0;
wire g81__149_carry__0_i_6_n_0;
wire g81__149_carry__0_i_7_n_0;
wire g81__149_carry__0_i_8_n_0;
wire g81__149_carry__0_n_0;
wire g81__149_carry__0_n_1;
wire g81__149_carry__0_n_2;
wire g81__149_carry__0_n_3;
wire g81__149_carry__1_i_1_n_0;
wire g81__149_carry__1_i_2_n_0;
wire g81__149_carry__1_i_3_n_0;
wire g81__149_carry__1_i_4_n_0;
wire g81__149_carry__1_i_5_n_0;
wire g81__149_carry__1_i_6_n_0;
wire g81__149_carry__1_i_7_n_0;
wire g81__149_carry__1_i_8_n_0;
wire g81__149_carry__1_n_0;
wire g81__149_carry__1_n_1;
wire g81__149_carry__1_n_2;
wire g81__149_carry__1_n_3;
wire g81__149_carry__2_i_1_n_0;
wire g81__149_carry__2_i_2_n_0;
wire g81__149_carry__2_i_3_n_0;
wire g81__149_carry__2_i_4_n_0;
wire g81__149_carry__2_i_5_n_0;
wire g81__149_carry__2_i_6_n_0;
wire g81__149_carry__2_i_7_n_0;
wire g81__149_carry__2_i_8_n_0;
wire g81__149_carry__2_n_0;
wire g81__149_carry__2_n_1;
wire g81__149_carry__2_n_2;
wire g81__149_carry__2_n_3;
wire g81__149_carry__2_n_4;
wire g81__149_carry__2_n_5;
wire g81__149_carry__2_n_6;
wire g81__149_carry__2_n_7;
wire g81__149_carry__3_i_1_n_0;
wire g81__149_carry__3_i_2_n_0;
wire g81__149_carry__3_i_3_n_0;
wire g81__149_carry__3_i_4_n_0;
wire g81__149_carry__3_i_5_n_0;
wire g81__149_carry__3_n_0;
wire g81__149_carry__3_n_1;
wire g81__149_carry__3_n_2;
wire g81__149_carry__3_n_3;
wire g81__149_carry__3_n_4;
wire g81__149_carry__3_n_5;
wire g81__149_carry__3_n_6;
wire g81__149_carry__3_n_7;
wire g81__149_carry__4_i_1_n_0;
wire g81__149_carry__4_i_2_n_0;
wire g81__149_carry__4_i_3_n_0;
wire g81__149_carry__4_n_0;
wire g81__149_carry__4_n_2;
wire g81__149_carry__4_n_3;
wire g81__149_carry__4_n_5;
wire g81__149_carry__4_n_6;
wire g81__149_carry__4_n_7;
wire g81__149_carry_i_1_n_0;
wire g81__149_carry_i_2_n_0;
wire g81__149_carry_i_3_n_0;
wire g81__149_carry_i_4_n_0;
wire g81__149_carry_i_5_n_0;
wire g81__149_carry_i_6_n_0;
wire g81__149_carry_i_7_n_0;
wire g81__149_carry_n_0;
wire g81__149_carry_n_1;
wire g81__149_carry_n_2;
wire g81__149_carry_n_3;
wire g81__206_carry__0_i_1_n_0;
wire g81__206_carry__0_i_2_n_0;
wire g81__206_carry__0_i_3_n_0;
wire g81__206_carry__0_i_4_n_0;
wire g81__206_carry__0_i_5_n_0;
wire g81__206_carry__0_i_6_n_0;
wire g81__206_carry__0_i_7_n_0;
wire g81__206_carry__0_i_8_n_0;
wire g81__206_carry__0_n_0;
wire g81__206_carry__0_n_1;
wire g81__206_carry__0_n_2;
wire g81__206_carry__0_n_3;
wire g81__206_carry__1_i_1_n_0;
wire g81__206_carry__1_i_2_n_0;
wire g81__206_carry__1_i_3_n_0;
wire g81__206_carry__1_i_4_n_0;
wire g81__206_carry__1_i_5_n_0;
wire g81__206_carry__1_i_6_n_0;
wire g81__206_carry__1_i_7_n_0;
wire g81__206_carry__1_i_8_n_0;
wire g81__206_carry__1_n_0;
wire g81__206_carry__1_n_1;
wire g81__206_carry__1_n_2;
wire g81__206_carry__1_n_3;
wire g81__206_carry__2_i_1_n_0;
wire g81__206_carry__2_i_2_n_0;
wire g81__206_carry__2_i_3_n_0;
wire g81__206_carry__2_i_4_n_0;
wire g81__206_carry__2_i_5_n_0;
wire g81__206_carry__2_i_6_n_0;
wire g81__206_carry__2_i_7_n_0;
wire g81__206_carry__2_i_8_n_0;
wire g81__206_carry__2_n_0;
wire g81__206_carry__2_n_1;
wire g81__206_carry__2_n_2;
wire g81__206_carry__2_n_3;
wire g81__206_carry__2_n_4;
wire g81__206_carry__2_n_5;
wire g81__206_carry__2_n_6;
wire g81__206_carry__2_n_7;
wire g81__206_carry__3_i_1_n_0;
wire g81__206_carry__3_i_2_n_0;
wire g81__206_carry__3_i_3_n_0;
wire g81__206_carry__3_i_4_n_0;
wire g81__206_carry__3_i_5_n_0;
wire g81__206_carry__3_i_6_n_0;
wire g81__206_carry__3_i_7_n_0;
wire g81__206_carry__3_i_8_n_0;
wire g81__206_carry__3_n_0;
wire g81__206_carry__3_n_1;
wire g81__206_carry__3_n_2;
wire g81__206_carry__3_n_3;
wire g81__206_carry__3_n_4;
wire g81__206_carry__3_n_5;
wire g81__206_carry__3_n_6;
wire g81__206_carry__3_n_7;
wire g81__206_carry__4_i_1_n_0;
wire g81__206_carry__4_i_2_n_0;
wire g81__206_carry__4_i_3_n_0;
wire g81__206_carry__4_i_4_n_0;
wire g81__206_carry__4_i_5_n_0;
wire g81__206_carry__4_i_6_n_0;
wire g81__206_carry__4_n_0;
wire g81__206_carry__4_n_2;
wire g81__206_carry__4_n_3;
wire g81__206_carry__4_n_5;
wire g81__206_carry__4_n_6;
wire g81__206_carry__4_n_7;
wire g81__206_carry_i_1_n_0;
wire g81__206_carry_i_2_n_0;
wire g81__206_carry_i_3_n_0;
wire g81__206_carry_i_4_n_0;
wire g81__206_carry_i_5_n_0;
wire g81__206_carry_i_6_n_0;
wire g81__206_carry_i_7_n_0;
wire g81__206_carry_n_0;
wire g81__206_carry_n_1;
wire g81__206_carry_n_2;
wire g81__206_carry_n_3;
wire g81__22_carry__0_i_1_n_0;
wire g81__22_carry__0_i_2_n_0;
wire g81__22_carry__0_i_3_n_0;
wire g81__22_carry__0_i_4_n_0;
wire g81__22_carry__0_n_0;
wire g81__22_carry__0_n_1;
wire g81__22_carry__0_n_2;
wire g81__22_carry__0_n_3;
wire g81__22_carry__0_n_4;
wire g81__22_carry__0_n_5;
wire g81__22_carry__0_n_6;
wire g81__22_carry__0_n_7;
wire g81__22_carry__1_i_1_n_0;
wire g81__22_carry__1_i_2_n_0;
wire g81__22_carry__1_i_3_n_0;
wire g81__22_carry__1_i_4_n_0;
wire g81__22_carry__1_n_0;
wire g81__22_carry__1_n_1;
wire g81__22_carry__1_n_2;
wire g81__22_carry__1_n_3;
wire g81__22_carry__1_n_4;
wire g81__22_carry__1_n_5;
wire g81__22_carry__1_n_6;
wire g81__22_carry__1_n_7;
wire g81__22_carry__2_i_1_n_0;
wire g81__22_carry__2_i_2_n_0;
wire g81__22_carry__2_n_1;
wire g81__22_carry__2_n_3;
wire g81__22_carry__2_n_6;
wire g81__22_carry__2_n_7;
wire g81__22_carry_i_1_n_0;
wire g81__22_carry_i_2_n_0;
wire g81__22_carry_i_3_n_0;
wire g81__22_carry_i_4_n_0;
wire g81__22_carry_i_5_n_0;
wire g81__22_carry_i_6_n_0;
wire g81__22_carry_n_0;
wire g81__22_carry_n_1;
wire g81__22_carry_n_2;
wire g81__22_carry_n_3;
wire g81__22_carry_n_4;
wire g81__22_carry_n_5;
wire g81__22_carry_n_6;
wire g81__261_carry__0_i_1_n_0;
wire g81__261_carry__0_i_2_n_0;
wire g81__261_carry__0_i_3_n_0;
wire g81__261_carry__0_i_4_n_0;
wire g81__261_carry__0_n_0;
wire g81__261_carry__0_n_1;
wire g81__261_carry__0_n_2;
wire g81__261_carry__0_n_3;
wire g81__261_carry__0_n_4;
wire g81__261_carry__0_n_5;
wire g81__261_carry__0_n_6;
wire g81__261_carry__0_n_7;
wire g81__261_carry__1_i_1_n_0;
wire g81__261_carry__1_i_2_n_0;
wire g81__261_carry__1_i_3_n_0;
wire g81__261_carry__1_i_4_n_0;
wire g81__261_carry__1_n_0;
wire g81__261_carry__1_n_1;
wire g81__261_carry__1_n_2;
wire g81__261_carry__1_n_3;
wire g81__261_carry__1_n_4;
wire g81__261_carry__1_n_5;
wire g81__261_carry__1_n_6;
wire g81__261_carry__1_n_7;
wire g81__261_carry__2_i_1_n_0;
wire g81__261_carry__2_i_2_n_0;
wire g81__261_carry__2_n_1;
wire g81__261_carry__2_n_3;
wire g81__261_carry__2_n_6;
wire g81__261_carry__2_n_7;
wire g81__261_carry_i_1_n_0;
wire g81__261_carry_i_2_n_0;
wire g81__261_carry_i_3_n_0;
wire g81__261_carry_i_4_n_0;
wire g81__261_carry_n_0;
wire g81__261_carry_n_1;
wire g81__261_carry_n_2;
wire g81__261_carry_n_3;
wire g81__261_carry_n_4;
wire g81__261_carry_n_5;
wire g81__261_carry_n_6;
wire g81__261_carry_n_7;
wire g81__301_carry__0_i_1_n_0;
wire g81__301_carry__0_i_2_n_0;
wire g81__301_carry__0_i_3_n_0;
wire g81__301_carry__0_i_4_n_0;
wire g81__301_carry__0_i_5_n_0;
wire g81__301_carry__0_i_6_n_0;
wire g81__301_carry__0_i_7_n_0;
wire g81__301_carry__0_i_8_n_0;
wire g81__301_carry__0_n_0;
wire g81__301_carry__0_n_1;
wire g81__301_carry__0_n_2;
wire g81__301_carry__0_n_3;
wire g81__301_carry__1_i_1_n_0;
wire g81__301_carry__1_i_2_n_0;
wire g81__301_carry__1_i_3_n_0;
wire g81__301_carry__1_i_4_n_0;
wire g81__301_carry__1_i_5_n_0;
wire g81__301_carry__1_i_6_n_0;
wire g81__301_carry__1_i_7_n_0;
wire g81__301_carry__1_i_8_n_0;
wire g81__301_carry__1_i_9_n_0;
wire g81__301_carry__1_n_0;
wire g81__301_carry__1_n_1;
wire g81__301_carry__1_n_2;
wire g81__301_carry__1_n_3;
wire g81__301_carry__2_i_1_n_0;
wire g81__301_carry__2_i_2_n_0;
wire g81__301_carry__2_i_3_n_0;
wire g81__301_carry__2_i_4_n_0;
wire g81__301_carry__2_i_5_n_0;
wire g81__301_carry__2_i_6_n_0;
wire g81__301_carry__2_i_7_n_0;
wire g81__301_carry__2_i_8_n_0;
wire g81__301_carry__2_n_0;
wire g81__301_carry__2_n_1;
wire g81__301_carry__2_n_2;
wire g81__301_carry__2_n_3;
wire g81__301_carry__3_i_1_n_0;
wire g81__301_carry__3_i_2_n_0;
wire g81__301_carry__3_i_3_n_0;
wire g81__301_carry__3_i_4_n_0;
wire g81__301_carry__3_i_5_n_0;
wire g81__301_carry__3_i_6_n_0;
wire g81__301_carry__3_i_7_n_0;
wire g81__301_carry__3_i_8_n_0;
wire g81__301_carry__3_n_0;
wire g81__301_carry__3_n_1;
wire g81__301_carry__3_n_2;
wire g81__301_carry__3_n_3;
wire g81__301_carry__4_i_1_n_0;
wire g81__301_carry__4_i_2_n_0;
wire g81__301_carry__4_i_3_n_0;
wire g81__301_carry__4_i_4_n_0;
wire g81__301_carry__4_i_5_n_0;
wire g81__301_carry__4_i_6_n_0;
wire g81__301_carry__4_i_7_n_0;
wire g81__301_carry__4_i_8_n_0;
wire g81__301_carry__4_n_0;
wire g81__301_carry__4_n_1;
wire g81__301_carry__4_n_2;
wire g81__301_carry__4_n_3;
wire g81__301_carry__5_i_1_n_0;
wire g81__301_carry__5_i_2_n_0;
wire g81__301_carry__5_i_3_n_0;
wire g81__301_carry__5_i_4_n_0;
wire g81__301_carry__5_i_5_n_0;
wire g81__301_carry__5_i_6_n_0;
wire g81__301_carry__5_i_7_n_0;
wire g81__301_carry__5_i_8_n_0;
wire g81__301_carry__5_n_0;
wire g81__301_carry__5_n_1;
wire g81__301_carry__5_n_2;
wire g81__301_carry__5_n_3;
wire g81__301_carry__6_i_1_n_0;
wire g81__301_carry__6_i_2_n_0;
wire g81__301_carry__6_i_3_n_0;
wire g81__301_carry__6_i_4_n_0;
wire g81__301_carry__6_i_5_n_0;
wire g81__301_carry__6_i_6_n_0;
wire g81__301_carry__6_n_1;
wire g81__301_carry__6_n_2;
wire g81__301_carry__6_n_3;
wire g81__301_carry_i_1_n_0;
wire g81__301_carry_i_2_n_0;
wire g81__301_carry_i_3_n_0;
wire g81__301_carry_i_4_n_0;
wire g81__301_carry_i_5_n_0;
wire g81__301_carry_i_6_n_0;
wire g81__301_carry_i_7_n_0;
wire g81__301_carry_n_0;
wire g81__301_carry_n_1;
wire g81__301_carry_n_2;
wire g81__301_carry_n_3;
wire g81__347_carry__0_i_1_n_0;
wire g81__347_carry__0_i_2_n_0;
wire g81__347_carry__0_i_3_n_0;
wire g81__347_carry__0_i_4_n_0;
wire g81__347_carry__0_n_1;
wire g81__347_carry__0_n_2;
wire g81__347_carry__0_n_3;
wire g81__347_carry__0_n_4;
wire g81__347_carry__0_n_5;
wire g81__347_carry__0_n_6;
wire g81__347_carry__0_n_7;
wire g81__347_carry_i_1_n_0;
wire g81__347_carry_i_2_n_0;
wire g81__347_carry_i_3_n_0;
wire g81__347_carry_i_4_n_0;
wire g81__347_carry_n_0;
wire g81__347_carry_n_1;
wire g81__347_carry_n_2;
wire g81__347_carry_n_3;
wire g81__347_carry_n_4;
wire g81__347_carry_n_5;
wire g81__347_carry_n_6;
wire g81__347_carry_n_7;
wire g81__53_carry__0_i_1_n_0;
wire g81__53_carry__0_i_2_n_0;
wire g81__53_carry__0_i_3_n_0;
wire g81__53_carry__0_i_4_n_0;
wire g81__53_carry__0_n_0;
wire g81__53_carry__0_n_1;
wire g81__53_carry__0_n_2;
wire g81__53_carry__0_n_3;
wire g81__53_carry__0_n_4;
wire g81__53_carry__0_n_5;
wire g81__53_carry__0_n_6;
wire g81__53_carry__0_n_7;
wire g81__53_carry__1_i_1_n_0;
wire g81__53_carry__1_i_2_n_0;
wire g81__53_carry__1_i_3_n_0;
wire g81__53_carry__1_i_4_n_0;
wire g81__53_carry__1_n_0;
wire g81__53_carry__1_n_1;
wire g81__53_carry__1_n_2;
wire g81__53_carry__1_n_3;
wire g81__53_carry__1_n_4;
wire g81__53_carry__1_n_5;
wire g81__53_carry__1_n_6;
wire g81__53_carry__1_n_7;
wire g81__53_carry__2_i_1_n_0;
wire g81__53_carry__2_i_2_n_0;
wire g81__53_carry__2_n_1;
wire g81__53_carry__2_n_3;
wire g81__53_carry__2_n_6;
wire g81__53_carry__2_n_7;
wire g81__53_carry_i_1_n_0;
wire g81__53_carry_i_2_n_0;
wire g81__53_carry_i_3_n_0;
wire g81__53_carry_i_4_n_0;
wire g81__53_carry_i_5_n_0;
wire g81__53_carry_i_6_n_0;
wire g81__53_carry_n_0;
wire g81__53_carry_n_1;
wire g81__53_carry_n_2;
wire g81__53_carry_n_3;
wire g81__53_carry_n_4;
wire g81__53_carry_n_5;
wire g81__53_carry_n_6;
wire g81__92_carry__0_i_1_n_0;
wire g81__92_carry__0_i_2_n_0;
wire g81__92_carry__0_i_3_n_0;
wire g81__92_carry__0_i_4_n_0;
wire g81__92_carry__0_n_0;
wire g81__92_carry__0_n_1;
wire g81__92_carry__0_n_2;
wire g81__92_carry__0_n_3;
wire g81__92_carry__0_n_4;
wire g81__92_carry__0_n_5;
wire g81__92_carry__0_n_6;
wire g81__92_carry__0_n_7;
wire g81__92_carry__1_i_1_n_0;
wire g81__92_carry__1_i_2_n_0;
wire g81__92_carry__1_i_3_n_0;
wire g81__92_carry__1_i_4_n_0;
wire g81__92_carry__1_n_0;
wire g81__92_carry__1_n_1;
wire g81__92_carry__1_n_2;
wire g81__92_carry__1_n_3;
wire g81__92_carry__1_n_4;
wire g81__92_carry__1_n_5;
wire g81__92_carry__1_n_6;
wire g81__92_carry__1_n_7;
wire g81__92_carry__2_i_1_n_0;
wire g81__92_carry__2_i_2_n_0;
wire g81__92_carry__2_n_1;
wire g81__92_carry__2_n_3;
wire g81__92_carry__2_n_6;
wire g81__92_carry__2_n_7;
wire g81__92_carry_i_1_n_0;
wire g81__92_carry_i_2_n_0;
wire g81__92_carry_i_3_n_0;
wire g81__92_carry_i_4_n_0;
wire g81__92_carry_i_5_n_0;
wire g81__92_carry_i_6_n_0;
wire g81__92_carry_n_0;
wire g81__92_carry_n_1;
wire g81__92_carry_n_2;
wire g81__92_carry_n_3;
wire g81__92_carry_n_4;
wire g81__92_carry_n_5;
wire g81__92_carry_n_6;
wire g81_carry__0_i_10_n_0;
wire g81_carry__0_i_11_n_0;
wire g81_carry__0_i_12_n_0;
wire g81_carry__0_i_13_n_0;
wire g81_carry__0_i_14_n_0;
wire g81_carry__0_i_15_n_0;
wire g81_carry__0_i_1_n_0;
wire g81_carry__0_i_2_n_0;
wire g81_carry__0_i_3_n_0;
wire g81_carry__0_i_4_n_0;
wire g81_carry__0_i_5_n_0;
wire g81_carry__0_i_6_n_0;
wire g81_carry__0_i_7_n_0;
wire g81_carry__0_i_8_n_0;
wire g81_carry__0_i_9_n_0;
wire g81_carry__0_n_0;
wire g81_carry__0_n_1;
wire g81_carry__0_n_2;
wire g81_carry__0_n_3;
wire g81_carry__0_n_4;
wire g81_carry__0_n_5;
wire g81_carry__0_n_6;
wire g81_carry__1_i_1_n_0;
wire g81_carry__1_i_2_n_0;
wire g81_carry__1_i_3_n_0;
wire g81_carry__1_i_4_n_0;
wire g81_carry__1_i_5_n_0;
wire g81_carry__1_i_6_n_0;
wire g81_carry__1_i_7_n_0;
wire g81_carry__1_i_8_n_0;
wire g81_carry__1_i_9_n_0;
wire g81_carry__1_n_0;
wire g81_carry__1_n_1;
wire g81_carry__1_n_2;
wire g81_carry__1_n_3;
wire g81_carry__1_n_4;
wire g81_carry__1_n_5;
wire g81_carry__1_n_6;
wire g81_carry__1_n_7;
wire g81_carry__2_i_1_n_0;
wire g81_carry__2_i_2_n_0;
wire g81_carry__2_i_3_n_0;
wire g81_carry__2_n_1;
wire g81_carry__2_n_3;
wire g81_carry__2_n_6;
wire g81_carry__2_n_7;
wire g81_carry_i_1_n_0;
wire g81_carry_i_2_n_0;
wire g81_carry_i_3_n_0;
wire g81_carry_i_4_n_0;
wire g81_carry_i_5_n_0;
wire g81_carry_i_6_n_0;
wire g81_carry_i_7_n_0;
wire g81_carry_n_0;
wire g81_carry_n_1;
wire g81_carry_n_2;
wire g81_carry_n_3;
wire g81_carry_n_7;
wire [9:1]g83;
wire g83__0_carry__0_i_1_n_0;
wire g83__0_carry__0_i_2_n_0;
wire g83__0_carry__0_i_3_n_0;
wire g83__0_carry__0_i_4_n_0;
wire g83__0_carry__0_i_5_n_0;
wire g83__0_carry__0_i_6_n_0;
wire g83__0_carry__0_i_7_n_0;
wire g83__0_carry__0_i_8_n_0;
wire g83__0_carry__0_n_0;
wire g83__0_carry__0_n_1;
wire g83__0_carry__0_n_2;
wire g83__0_carry__0_n_3;
wire g83__0_carry__0_n_4;
wire g83__0_carry__0_n_5;
wire g83__0_carry__0_n_6;
wire g83__0_carry__0_n_7;
wire g83__0_carry__1_i_1_n_0;
wire g83__0_carry__1_n_2;
wire g83__0_carry__1_n_7;
wire g83__0_carry_i_1_n_0;
wire g83__0_carry_i_2_n_0;
wire g83__0_carry_i_3_n_0;
wire g83__0_carry_i_4_n_0;
wire g83__0_carry_i_5_n_0;
wire g83__0_carry_i_6_n_0;
wire g83__0_carry_i_7_n_0;
wire g83__0_carry_n_0;
wire g83__0_carry_n_1;
wire g83__0_carry_n_2;
wire g83__0_carry_n_3;
wire g83__0_carry_n_4;
wire g83__0_carry_n_5;
wire g83__0_carry_n_6;
wire g83__0_carry_n_7;
wire g84;
wire g84_carry__0_i_1_n_0;
wire g84_carry__0_i_2_n_0;
wire g84_carry_i_1_n_0;
wire g84_carry_i_2_n_0;
wire g84_carry_i_3_n_0;
wire g84_carry_i_4_n_0;
wire g84_carry_i_5_n_0;
wire g84_carry_i_6_n_0;
wire g84_carry_i_7_n_0;
wire g84_carry_i_8_n_0;
wire g84_carry_n_0;
wire g84_carry_n_1;
wire g84_carry_n_2;
wire g84_carry_n_3;
wire [23:0]rgb888;
wire [3:0]NLW__carry__1_CO_UNCONNECTED;
wire [3:1]NLW__carry__1_O_UNCONNECTED;
wire [0:0]NLW_g81__120_carry_O_UNCONNECTED;
wire [3:1]NLW_g81__120_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81__120_carry__2_O_UNCONNECTED;
wire [3:0]NLW_g81__149_carry_O_UNCONNECTED;
wire [3:0]NLW_g81__149_carry__0_O_UNCONNECTED;
wire [3:0]NLW_g81__149_carry__1_O_UNCONNECTED;
wire [2:2]NLW_g81__149_carry__4_CO_UNCONNECTED;
wire [3:3]NLW_g81__149_carry__4_O_UNCONNECTED;
wire [3:0]NLW_g81__206_carry_O_UNCONNECTED;
wire [3:0]NLW_g81__206_carry__0_O_UNCONNECTED;
wire [3:0]NLW_g81__206_carry__1_O_UNCONNECTED;
wire [2:2]NLW_g81__206_carry__4_CO_UNCONNECTED;
wire [3:3]NLW_g81__206_carry__4_O_UNCONNECTED;
wire [0:0]NLW_g81__22_carry_O_UNCONNECTED;
wire [3:1]NLW_g81__22_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81__22_carry__2_O_UNCONNECTED;
wire [3:1]NLW_g81__261_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81__261_carry__2_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__0_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__1_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__2_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__3_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__4_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__5_O_UNCONNECTED;
wire [3:3]NLW_g81__301_carry__6_CO_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__6_O_UNCONNECTED;
wire [3:3]NLW_g81__347_carry__0_CO_UNCONNECTED;
wire [0:0]NLW_g81__53_carry_O_UNCONNECTED;
wire [3:1]NLW_g81__53_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81__53_carry__2_O_UNCONNECTED;
wire [0:0]NLW_g81__92_carry_O_UNCONNECTED;
wire [3:1]NLW_g81__92_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81__92_carry__2_O_UNCONNECTED;
wire [3:1]NLW_g81_carry_O_UNCONNECTED;
wire [0:0]NLW_g81_carry__0_O_UNCONNECTED;
wire [3:1]NLW_g81_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81_carry__2_O_UNCONNECTED;
wire [3:0]NLW_g83__0_carry__1_CO_UNCONNECTED;
wire [3:1]NLW_g83__0_carry__1_O_UNCONNECTED;
wire [3:0]NLW_g84_carry_O_UNCONNECTED;
wire [3:1]NLW_g84_carry__0_CO_UNCONNECTED;
wire [3:0]NLW_g84_carry__0_O_UNCONNECTED;
CARRY4 _carry
(.CI(1'b0),
.CO({_carry_n_0,_carry_n_1,_carry_n_2,_carry_n_3}),
.CYINIT(_carry_i_1_n_0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(g83[4:1]),
.S({_carry_i_2_n_0,_carry_i_3_n_0,_carry_i_4_n_0,_carry_i_5_n_0}));
CARRY4 _carry__0
(.CI(_carry_n_0),
.CO({_carry__0_n_0,_carry__0_n_1,_carry__0_n_2,_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(g83[8:5]),
.S({_carry__0_i_1_n_0,_carry__0_i_2_n_0,_carry__0_i_3_n_0,_carry__0_i_4_n_0}));
LUT1 #(
.INIT(2'h1))
_carry__0_i_1
(.I0(g83__0_carry__1_n_7),
.O(_carry__0_i_1_n_0));
LUT1 #(
.INIT(2'h1))
_carry__0_i_2
(.I0(g83__0_carry__0_n_4),
.O(_carry__0_i_2_n_0));
LUT1 #(
.INIT(2'h1))
_carry__0_i_3
(.I0(g83__0_carry__0_n_5),
.O(_carry__0_i_3_n_0));
LUT1 #(
.INIT(2'h1))
_carry__0_i_4
(.I0(g83__0_carry__0_n_6),
.O(_carry__0_i_4_n_0));
CARRY4 _carry__1
(.CI(_carry__0_n_0),
.CO({NLW__carry__1_CO_UNCONNECTED[3:2],_carry__1_n_2,NLW__carry__1_CO_UNCONNECTED[0]}),
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.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW__carry__1_O_UNCONNECTED[3:1],g83[9]}),
.S({1'b0,1'b0,1'b1,_carry__1_i_1_n_0}));
LUT1 #(
.INIT(2'h1))
_carry__1_i_1
(.I0(g83__0_carry__1_n_2),
.O(_carry__1_i_1_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_1
(.I0(g83__0_carry_n_7),
.O(_carry_i_1_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_2
(.I0(g83__0_carry__0_n_7),
.O(_carry_i_2_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_3
(.I0(g83__0_carry_n_4),
.O(_carry_i_3_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_4
(.I0(g83__0_carry_n_5),
.O(_carry_i_4_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_5
(.I0(g83__0_carry_n_6),
.O(_carry_i_5_n_0));
CARRY4 g81__120_carry
(.CI(1'b0),
.CO({g81__120_carry_n_0,g81__120_carry_n_1,g81__120_carry_n_2,g81__120_carry_n_3}),
.CYINIT(1'b0),
.DI({g81_carry_i_1_n_0,g81__120_carry_i_1_n_0,g81__120_carry_i_2_n_0,1'b0}),
.O({g81__120_carry_n_4,g81__120_carry_n_5,g81__120_carry_n_6,NLW_g81__120_carry_O_UNCONNECTED[0]}),
.S({g81__120_carry_i_3_n_0,g81__120_carry_i_4_n_0,g81__120_carry_i_5_n_0,g81__120_carry_i_6_n_0}));
CARRY4 g81__120_carry__0
(.CI(g81__120_carry_n_0),
.CO({g81__120_carry__0_n_0,g81__120_carry__0_n_1,g81__120_carry__0_n_2,g81__120_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__0_i_1_n_0,g81_carry__0_i_2_n_0,g81_carry__0_i_3_n_0,g81_carry__0_i_4_n_0}),
.O({g81__120_carry__0_n_4,g81__120_carry__0_n_5,g81__120_carry__0_n_6,g81__120_carry__0_n_7}),
.S({g81__120_carry__0_i_1_n_0,g81__120_carry__0_i_2_n_0,g81__120_carry__0_i_3_n_0,g81__120_carry__0_i_4_n_0}));
LUT6 #(
.INIT(64'h6996699669699696))
g81__120_carry__0_i_1
(.I0(g81_carry__0_i_1_n_0),
.I1(g81_carry__0_i_12_n_0),
.I2(g81_carry__0_i_13_n_0),
.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81__120_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__120_carry__0_i_2
(.I0(g81_carry__0_i_2_n_0),
.I1(g81_carry__0_i_14_n_0),
.I2(g81_carry__0_i_9_n_0),
.I3(g83__0_carry__0_n_4),
.I4(g83[7]),
.I5(g84),
.O(g81__120_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'h569AA965A965569A))
g81__120_carry__0_i_3
(.I0(g81_carry__0_i_3_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g81_carry__0_i_10_n_0),
.I5(g81_carry__0_i_12_n_0),
.O(g81__120_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h99666666A55A5A5A))
g81__120_carry__0_i_4
(.I0(g81_carry__0_i_15_n_0),
.I1(g83__0_carry__0_n_6),
.I2(g83[5]),
.I3(g81_carry__0_i_10_n_0),
.I4(g83__0_carry_n_7),
.I5(g84),
.O(g81__120_carry__0_i_4_n_0));
CARRY4 g81__120_carry__1
(.CI(g81__120_carry__0_n_0),
.CO({g81__120_carry__1_n_0,g81__120_carry__1_n_1,g81__120_carry__1_n_2,g81__120_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__1_i_1_n_0,g81_carry__1_i_2_n_0,g81_carry__1_i_3_n_0,g81_carry__1_i_4_n_0}),
.O({g81__120_carry__1_n_4,g81__120_carry__1_n_5,g81__120_carry__1_n_6,g81__120_carry__1_n_7}),
.S({g81__120_carry__1_i_1_n_0,g81__120_carry__1_i_2_n_0,g81__120_carry__1_i_3_n_0,g81__120_carry__1_i_4_n_0}));
(* HLUTNM = "lutpair7" *)
LUT4 #(
.INIT(16'h369C))
g81__120_carry__1_i_1
(.I0(g84),
.I1(g81_carry__1_i_1_n_0),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81__120_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__120_carry__1_i_2
(.I0(g81_carry__1_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.I4(g81_carry__1_i_9_n_0),
.I5(_carry__1_n_2),
.O(g81__120_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__120_carry__1_i_3
(.I0(g81_carry__1_i_3_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.I4(g81_carry__0_i_12_n_0),
.I5(_carry__1_n_2),
.O(g81__120_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__120_carry__1_i_4
(.I0(g81_carry__1_i_4_n_0),
.I1(g81_carry__1_i_9_n_0),
.I2(g81_carry__0_i_14_n_0),
.I3(g83__0_carry__1_n_2),
.I4(g83[9]),
.I5(g84),
.O(g81__120_carry__1_i_4_n_0));
CARRY4 g81__120_carry__2
(.CI(g81__120_carry__1_n_0),
.CO({NLW_g81__120_carry__2_CO_UNCONNECTED[3],g81__120_carry__2_n_1,NLW_g81__120_carry__2_CO_UNCONNECTED[1],g81__120_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81__120_carry__2_i_1_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81__120_carry__2_O_UNCONNECTED[3:2],g81__120_carry__2_n_6,g81__120_carry__2_n_7}),
.S({1'b0,1'b1,1'b0,g81__120_carry__2_i_2_n_0}));
LUT2 #(
.INIT(4'h1))
g81__120_carry__2_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81__120_carry__2_i_1_n_0));
LUT4 #(
.INIT(16'h569A))
g81__120_carry__2_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81__120_carry__2_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
g81__120_carry_i_1
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81__120_carry_i_1_n_0));
LUT3 #(
.INIT(8'hAC))
g81__120_carry_i_2
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81__120_carry_i_2_n_0));
LUT6 #(
.INIT(64'h99A5995A66A5665A))
g81__120_carry_i_3
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_5),
.I2(g83[2]),
.I3(g84),
.I4(g83[4]),
.I5(g83__0_carry__0_n_7),
.O(g81__120_carry_i_3_n_0));
LUT5 #(
.INIT(32'h353AC5CA))
g81__120_carry_i_4
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81__120_carry_i_4_n_0));
LUT4 #(
.INIT(16'h35CA))
g81__120_carry_i_5
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81__120_carry_i_5_n_0));
LUT3 #(
.INIT(8'hAC))
g81__120_carry_i_6
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81__120_carry_i_6_n_0));
CARRY4 g81__149_carry
(.CI(1'b0),
.CO({g81__149_carry_n_0,g81__149_carry_n_1,g81__149_carry_n_2,g81__149_carry_n_3}),
.CYINIT(1'b0),
.DI({g81__149_carry_i_1_n_0,g81__149_carry_i_2_n_0,g81__149_carry_i_3_n_0,1'b0}),
.O(NLW_g81__149_carry_O_UNCONNECTED[3:0]),
.S({g81__149_carry_i_4_n_0,g81__149_carry_i_5_n_0,g81__149_carry_i_6_n_0,g81__149_carry_i_7_n_0}));
CARRY4 g81__149_carry__0
(.CI(g81__149_carry_n_0),
.CO({g81__149_carry__0_n_0,g81__149_carry__0_n_1,g81__149_carry__0_n_2,g81__149_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81__149_carry__0_i_1_n_0,g81__149_carry__0_i_2_n_0,g81__149_carry__0_i_3_n_0,g81__149_carry__0_i_4_n_0}),
.O(NLW_g81__149_carry__0_O_UNCONNECTED[3:0]),
.S({g81__149_carry__0_i_5_n_0,g81__149_carry__0_i_6_n_0,g81__149_carry__0_i_7_n_0,g81__149_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair8" *)
LUT3 #(
.INIT(8'hE8))
g81__149_carry__0_i_1
(.I0(g83__0_carry_n_7),
.I1(g81__22_carry__0_n_6),
.I2(g81_carry__1_n_4),
.O(g81__149_carry__0_i_1_n_0));
(* HLUTNM = "lutpair27" *)
LUT2 #(
.INIT(4'h8))
g81__149_carry__0_i_2
(.I0(g81__22_carry__0_n_7),
.I1(g81_carry__1_n_5),
.O(g81__149_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h8))
g81__149_carry__0_i_3
(.I0(g81_carry__1_n_6),
.I1(g81__22_carry_n_4),
.O(g81__149_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h8))
g81__149_carry__0_i_4
(.I0(g81_carry__1_n_7),
.I1(g81__22_carry_n_5),
.O(g81__149_carry__0_i_4_n_0));
(* HLUTNM = "lutpair9" *)
LUT4 #(
.INIT(16'h6996))
g81__149_carry__0_i_5
(.I0(g81_carry__0_i_11_n_0),
.I1(g81__22_carry__0_n_5),
.I2(g81_carry__2_n_7),
.I3(g81__149_carry__0_i_1_n_0),
.O(g81__149_carry__0_i_5_n_0));
(* HLUTNM = "lutpair8" *)
LUT4 #(
.INIT(16'h6996))
g81__149_carry__0_i_6
(.I0(g83__0_carry_n_7),
.I1(g81__22_carry__0_n_6),
.I2(g81_carry__1_n_4),
.I3(g81__149_carry__0_i_2_n_0),
.O(g81__149_carry__0_i_6_n_0));
(* HLUTNM = "lutpair27" *)
LUT4 #(
.INIT(16'h9666))
g81__149_carry__0_i_7
(.I0(g81__22_carry__0_n_7),
.I1(g81_carry__1_n_5),
.I2(g81_carry__1_n_6),
.I3(g81__22_carry_n_4),
.O(g81__149_carry__0_i_7_n_0));
LUT4 #(
.INIT(16'h8778))
g81__149_carry__0_i_8
(.I0(g81_carry__1_n_7),
.I1(g81__22_carry_n_5),
.I2(g81__22_carry_n_4),
.I3(g81_carry__1_n_6),
.O(g81__149_carry__0_i_8_n_0));
CARRY4 g81__149_carry__1
(.CI(g81__149_carry__0_n_0),
.CO({g81__149_carry__1_n_0,g81__149_carry__1_n_1,g81__149_carry__1_n_2,g81__149_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81__149_carry__1_i_1_n_0,g81__149_carry__1_i_2_n_0,g81__149_carry__1_i_3_n_0,g81__149_carry__1_i_4_n_0}),
.O(NLW_g81__149_carry__1_O_UNCONNECTED[3:0]),
.S({g81__149_carry__1_i_5_n_0,g81__149_carry__1_i_6_n_0,g81__149_carry__1_i_7_n_0,g81__149_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair12" *)
LUT4 #(
.INIT(16'h888E))
g81__149_carry__1_i_1
(.I0(g81__53_carry_n_4),
.I1(g81__22_carry__1_n_6),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__1_i_1_n_0));
(* HLUTNM = "lutpair11" *)
LUT3 #(
.INIT(8'hE8))
g81__149_carry__1_i_2
(.I0(g81__53_carry_n_5),
.I1(g81__22_carry__1_n_7),
.I2(g81_carry__2_n_1),
.O(g81__149_carry__1_i_2_n_0));
(* HLUTNM = "lutpair10" *)
LUT3 #(
.INIT(8'hE8))
g81__149_carry__1_i_3
(.I0(g81__53_carry_n_6),
.I1(g81__22_carry__0_n_4),
.I2(g81_carry__2_n_6),
.O(g81__149_carry__1_i_3_n_0));
(* HLUTNM = "lutpair9" *)
LUT3 #(
.INIT(8'hE8))
g81__149_carry__1_i_4
(.I0(g81_carry__0_i_11_n_0),
.I1(g81__22_carry__0_n_5),
.I2(g81_carry__2_n_7),
.O(g81__149_carry__1_i_4_n_0));
(* HLUTNM = "lutpair13" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__1_i_5
(.I0(g81__53_carry__0_n_7),
.I1(g81__22_carry__1_n_5),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__1_i_1_n_0),
.O(g81__149_carry__1_i_5_n_0));
(* HLUTNM = "lutpair12" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__1_i_6
(.I0(g81__53_carry_n_4),
.I1(g81__22_carry__1_n_6),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__1_i_2_n_0),
.O(g81__149_carry__1_i_6_n_0));
(* HLUTNM = "lutpair11" *)
LUT4 #(
.INIT(16'h6996))
g81__149_carry__1_i_7
(.I0(g81__53_carry_n_5),
.I1(g81__22_carry__1_n_7),
.I2(g81_carry__2_n_1),
.I3(g81__149_carry__1_i_3_n_0),
.O(g81__149_carry__1_i_7_n_0));
(* HLUTNM = "lutpair10" *)
LUT4 #(
.INIT(16'h6996))
g81__149_carry__1_i_8
(.I0(g81__53_carry_n_6),
.I1(g81__22_carry__0_n_4),
.I2(g81_carry__2_n_6),
.I3(g81__149_carry__1_i_4_n_0),
.O(g81__149_carry__1_i_8_n_0));
CARRY4 g81__149_carry__2
(.CI(g81__149_carry__1_n_0),
.CO({g81__149_carry__2_n_0,g81__149_carry__2_n_1,g81__149_carry__2_n_2,g81__149_carry__2_n_3}),
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.DI({g81__149_carry__2_i_1_n_0,g81__149_carry__2_i_2_n_0,g81__149_carry__2_i_3_n_0,g81__149_carry__2_i_4_n_0}),
.O({g81__149_carry__2_n_4,g81__149_carry__2_n_5,g81__149_carry__2_n_6,g81__149_carry__2_n_7}),
.S({g81__149_carry__2_i_5_n_0,g81__149_carry__2_i_6_n_0,g81__149_carry__2_i_7_n_0,g81__149_carry__2_i_8_n_0}));
(* HLUTNM = "lutpair16" *)
LUT4 #(
.INIT(16'h888E))
g81__149_carry__2_i_1
(.I0(g81__53_carry__0_n_4),
.I1(g81__22_carry__2_n_6),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__2_i_1_n_0));
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LUT4 #(
.INIT(16'h888E))
g81__149_carry__2_i_2
(.I0(g81__53_carry__0_n_5),
.I1(g81__22_carry__2_n_7),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__2_i_2_n_0));
(* HLUTNM = "lutpair14" *)
LUT4 #(
.INIT(16'h888E))
g81__149_carry__2_i_3
(.I0(g81__53_carry__0_n_6),
.I1(g81__22_carry__1_n_4),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__2_i_3_n_0));
(* HLUTNM = "lutpair13" *)
LUT4 #(
.INIT(16'h888E))
g81__149_carry__2_i_4
(.I0(g81__53_carry__0_n_7),
.I1(g81__22_carry__1_n_5),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__2_i_4_n_0));
(* HLUTNM = "lutpair17" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__2_i_5
(.I0(g81__53_carry__1_n_7),
.I1(g81__22_carry__2_n_1),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__2_i_1_n_0),
.O(g81__149_carry__2_i_5_n_0));
(* HLUTNM = "lutpair16" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__2_i_6
(.I0(g81__53_carry__0_n_4),
.I1(g81__22_carry__2_n_6),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__2_i_2_n_0),
.O(g81__149_carry__2_i_6_n_0));
(* HLUTNM = "lutpair15" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__2_i_7
(.I0(g81__53_carry__0_n_5),
.I1(g81__22_carry__2_n_7),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__2_i_3_n_0),
.O(g81__149_carry__2_i_7_n_0));
(* HLUTNM = "lutpair14" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__2_i_8
(.I0(g81__53_carry__0_n_6),
.I1(g81__22_carry__1_n_4),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__2_i_4_n_0),
.O(g81__149_carry__2_i_8_n_0));
CARRY4 g81__149_carry__3
(.CI(g81__149_carry__2_n_0),
.CO({g81__149_carry__3_n_0,g81__149_carry__3_n_1,g81__149_carry__3_n_2,g81__149_carry__3_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__2_i_2_n_0,g81_carry__2_i_2_n_0,g81_carry__2_i_2_n_0,g81__149_carry__3_i_1_n_0}),
.O({g81__149_carry__3_n_4,g81__149_carry__3_n_5,g81__149_carry__3_n_6,g81__149_carry__3_n_7}),
.S({g81__149_carry__3_i_2_n_0,g81__149_carry__3_i_3_n_0,g81__149_carry__3_i_4_n_0,g81__149_carry__3_i_5_n_0}));
(* HLUTNM = "lutpair17" *)
LUT4 #(
.INIT(16'h888E))
g81__149_carry__3_i_1
(.I0(g81__53_carry__1_n_7),
.I1(g81__22_carry__2_n_1),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__3_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g81__53_carry__2_n_7),
.O(g81__149_carry__3_i_2_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__3_i_3
(.I0(g81_carry__2_i_2_n_0),
.I1(g81__53_carry__1_n_4),
.O(g81__149_carry__3_i_3_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__3_i_4
(.I0(g81_carry__2_i_2_n_0),
.I1(g81__53_carry__1_n_5),
.O(g81__149_carry__3_i_4_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__3_i_5
(.I0(g81__149_carry__3_i_1_n_0),
.I1(g81__53_carry__1_n_6),
.O(g81__149_carry__3_i_5_n_0));
CARRY4 g81__149_carry__4
(.CI(g81__149_carry__3_n_0),
.CO({g81__149_carry__4_n_0,NLW_g81__149_carry__4_CO_UNCONNECTED[2],g81__149_carry__4_n_2,g81__149_carry__4_n_3}),
.CYINIT(1'b0),
.DI({1'b0,g81__149_carry__4_i_1_n_0,g81_carry__2_i_2_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81__149_carry__4_O_UNCONNECTED[3],g81__149_carry__4_n_5,g81__149_carry__4_n_6,g81__149_carry__4_n_7}),
.S({1'b1,1'b0,g81__149_carry__4_i_2_n_0,g81__149_carry__4_i_3_n_0}));
LUT2 #(
.INIT(4'h1))
g81__149_carry__4_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81__149_carry__4_i_1_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__4_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g81__53_carry__2_n_1),
.O(g81__149_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__4_i_3
(.I0(g81_carry__2_i_2_n_0),
.I1(g81__53_carry__2_n_6),
.O(g81__149_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h8))
g81__149_carry_i_1
(.I0(g81_carry__0_n_4),
.I1(g81__22_carry_n_6),
.O(g81__149_carry_i_1_n_0));
LUT2 #(
.INIT(4'h8))
g81__149_carry_i_2
(.I0(g81_carry__0_n_5),
.I1(g81_carry__0_i_11_n_0),
.O(g81__149_carry_i_2_n_0));
LUT2 #(
.INIT(4'h8))
g81__149_carry_i_3
(.I0(g81_carry__0_n_6),
.I1(g83__0_carry_n_7),
.O(g81__149_carry_i_3_n_0));
LUT4 #(
.INIT(16'h8778))
g81__149_carry_i_4
(.I0(g81_carry__0_n_4),
.I1(g81__22_carry_n_6),
.I2(g81__22_carry_n_5),
.I3(g81_carry__1_n_7),
.O(g81__149_carry_i_4_n_0));
LUT4 #(
.INIT(16'h8778))
g81__149_carry_i_5
(.I0(g81_carry__0_n_5),
.I1(g81_carry__0_i_11_n_0),
.I2(g81__22_carry_n_6),
.I3(g81_carry__0_n_4),
.O(g81__149_carry_i_5_n_0));
LUT4 #(
.INIT(16'h8778))
g81__149_carry_i_6
(.I0(g81_carry__0_n_6),
.I1(g83__0_carry_n_7),
.I2(g81_carry__0_i_11_n_0),
.I3(g81_carry__0_n_5),
.O(g81__149_carry_i_6_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry_i_7
(.I0(g81_carry__0_n_6),
.I1(g83__0_carry_n_7),
.O(g81__149_carry_i_7_n_0));
CARRY4 g81__206_carry
(.CI(1'b0),
.CO({g81__206_carry_n_0,g81__206_carry_n_1,g81__206_carry_n_2,g81__206_carry_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry_i_1_n_0,g81__206_carry_i_2_n_0,g81__206_carry_i_3_n_0,1'b0}),
.O(NLW_g81__206_carry_O_UNCONNECTED[3:0]),
.S({g81__206_carry_i_4_n_0,g81__206_carry_i_5_n_0,g81__206_carry_i_6_n_0,g81__206_carry_i_7_n_0}));
CARRY4 g81__206_carry__0
(.CI(g81__206_carry_n_0),
.CO({g81__206_carry__0_n_0,g81__206_carry__0_n_1,g81__206_carry__0_n_2,g81__206_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__0_i_1_n_0,g81__206_carry__0_i_2_n_0,g81__206_carry__0_i_3_n_0,g81__206_carry__0_i_4_n_0}),
.O(NLW_g81__206_carry__0_O_UNCONNECTED[3:0]),
.S({g81__206_carry__0_i_5_n_0,g81__206_carry__0_i_6_n_0,g81__206_carry__0_i_7_n_0,g81__206_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair18" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__0_i_1
(.I0(g81__149_carry__3_n_5),
.I1(g83__0_carry_n_7),
.I2(g81__92_carry__0_n_6),
.O(g81__206_carry__0_i_1_n_0));
(* HLUTNM = "lutpair28" *)
LUT2 #(
.INIT(4'h8))
g81__206_carry__0_i_2
(.I0(g81__149_carry__3_n_6),
.I1(g81__92_carry__0_n_7),
.O(g81__206_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry__0_i_3
(.I0(g81__92_carry_n_4),
.I1(g81__149_carry__3_n_7),
.O(g81__206_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry__0_i_4
(.I0(g81__92_carry_n_5),
.I1(g81__149_carry__2_n_4),
.O(g81__206_carry__0_i_4_n_0));
(* HLUTNM = "lutpair19" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__0_i_5
(.I0(g81__149_carry__3_n_4),
.I1(g81_carry__0_i_11_n_0),
.I2(g81__92_carry__0_n_5),
.I3(g81__206_carry__0_i_1_n_0),
.O(g81__206_carry__0_i_5_n_0));
(* HLUTNM = "lutpair18" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__0_i_6
(.I0(g81__149_carry__3_n_5),
.I1(g83__0_carry_n_7),
.I2(g81__92_carry__0_n_6),
.I3(g81__206_carry__0_i_2_n_0),
.O(g81__206_carry__0_i_6_n_0));
(* HLUTNM = "lutpair28" *)
LUT4 #(
.INIT(16'h9666))
g81__206_carry__0_i_7
(.I0(g81__149_carry__3_n_6),
.I1(g81__92_carry__0_n_7),
.I2(g81__92_carry_n_4),
.I3(g81__149_carry__3_n_7),
.O(g81__206_carry__0_i_7_n_0));
LUT4 #(
.INIT(16'h8778))
g81__206_carry__0_i_8
(.I0(g81__92_carry_n_5),
.I1(g81__149_carry__2_n_4),
.I2(g81__149_carry__3_n_7),
.I3(g81__92_carry_n_4),
.O(g81__206_carry__0_i_8_n_0));
CARRY4 g81__206_carry__1
(.CI(g81__206_carry__0_n_0),
.CO({g81__206_carry__1_n_0,g81__206_carry__1_n_1,g81__206_carry__1_n_2,g81__206_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__1_i_1_n_0,g81__206_carry__1_i_2_n_0,g81__206_carry__1_i_3_n_0,g81__206_carry__1_i_4_n_0}),
.O(NLW_g81__206_carry__1_O_UNCONNECTED[3:0]),
.S({g81__206_carry__1_i_5_n_0,g81__206_carry__1_i_6_n_0,g81__206_carry__1_i_7_n_0,g81__206_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair22" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__1_i_1
(.I0(g81__149_carry__4_n_5),
.I1(g81__120_carry_n_4),
.I2(g81__92_carry__1_n_6),
.O(g81__206_carry__1_i_1_n_0));
(* HLUTNM = "lutpair21" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__1_i_2
(.I0(g81__149_carry__4_n_6),
.I1(g81__120_carry_n_5),
.I2(g81__92_carry__1_n_7),
.O(g81__206_carry__1_i_2_n_0));
(* HLUTNM = "lutpair20" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__1_i_3
(.I0(g81__149_carry__4_n_7),
.I1(g81__120_carry_n_6),
.I2(g81__92_carry__0_n_4),
.O(g81__206_carry__1_i_3_n_0));
(* HLUTNM = "lutpair19" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__1_i_4
(.I0(g81__149_carry__3_n_4),
.I1(g81_carry__0_i_11_n_0),
.I2(g81__92_carry__0_n_5),
.O(g81__206_carry__1_i_4_n_0));
(* HLUTNM = "lutpair23" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__1_i_5
(.I0(g81__149_carry__4_n_0),
.I1(g81__120_carry__0_n_7),
.I2(g81__92_carry__1_n_5),
.I3(g81__206_carry__1_i_1_n_0),
.O(g81__206_carry__1_i_5_n_0));
(* HLUTNM = "lutpair22" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__1_i_6
(.I0(g81__149_carry__4_n_5),
.I1(g81__120_carry_n_4),
.I2(g81__92_carry__1_n_6),
.I3(g81__206_carry__1_i_2_n_0),
.O(g81__206_carry__1_i_6_n_0));
(* HLUTNM = "lutpair21" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__1_i_7
(.I0(g81__149_carry__4_n_6),
.I1(g81__120_carry_n_5),
.I2(g81__92_carry__1_n_7),
.I3(g81__206_carry__1_i_3_n_0),
.O(g81__206_carry__1_i_7_n_0));
(* HLUTNM = "lutpair20" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__1_i_8
(.I0(g81__149_carry__4_n_7),
.I1(g81__120_carry_n_6),
.I2(g81__92_carry__0_n_4),
.I3(g81__206_carry__1_i_4_n_0),
.O(g81__206_carry__1_i_8_n_0));
CARRY4 g81__206_carry__2
(.CI(g81__206_carry__1_n_0),
.CO({g81__206_carry__2_n_0,g81__206_carry__2_n_1,g81__206_carry__2_n_2,g81__206_carry__2_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__2_i_1_n_0,g81__206_carry__2_i_2_n_0,g81__206_carry__2_i_3_n_0,g81__206_carry__2_i_4_n_0}),
.O({g81__206_carry__2_n_4,g81__206_carry__2_n_5,g81__206_carry__2_n_6,g81__206_carry__2_n_7}),
.S({g81__206_carry__2_i_5_n_0,g81__206_carry__2_i_6_n_0,g81__206_carry__2_i_7_n_0,g81__206_carry__2_i_8_n_0}));
(* HLUTNM = "lutpair29" *)
LUT2 #(
.INIT(4'h8))
g81__206_carry__2_i_1
(.I0(g81__120_carry__0_n_4),
.I1(g81__92_carry__2_n_6),
.O(g81__206_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry__2_i_2
(.I0(g81__92_carry__2_n_7),
.I1(g81__120_carry__0_n_5),
.O(g81__206_carry__2_i_2_n_0));
LUT4 #(
.INIT(16'hF110))
g81__206_carry__2_i_3
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__120_carry__0_n_6),
.I3(g81__92_carry__1_n_4),
.O(g81__206_carry__2_i_3_n_0));
(* HLUTNM = "lutpair23" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__2_i_4
(.I0(g81__149_carry__4_n_0),
.I1(g81__120_carry__0_n_7),
.I2(g81__92_carry__1_n_5),
.O(g81__206_carry__2_i_4_n_0));
LUT5 #(
.INIT(32'h99966669))
g81__206_carry__2_i_5
(.I0(g81__206_carry__2_i_1_n_0),
.I1(g81__120_carry__1_n_7),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__92_carry__2_n_1),
.O(g81__206_carry__2_i_5_n_0));
(* HLUTNM = "lutpair29" *)
LUT4 #(
.INIT(16'h9666))
g81__206_carry__2_i_6
(.I0(g81__120_carry__0_n_4),
.I1(g81__92_carry__2_n_6),
.I2(g81__92_carry__2_n_7),
.I3(g81__120_carry__0_n_5),
.O(g81__206_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h888E77717771888E))
g81__206_carry__2_i_7
(.I0(g81__92_carry__1_n_4),
.I1(g81__120_carry__0_n_6),
.I2(g84),
.I3(_carry__1_n_2),
.I4(g81__120_carry__0_n_5),
.I5(g81__92_carry__2_n_7),
.O(g81__206_carry__2_i_7_n_0));
LUT5 #(
.INIT(32'h99966669))
g81__206_carry__2_i_8
(.I0(g81__206_carry__2_i_4_n_0),
.I1(g81__120_carry__0_n_6),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__92_carry__1_n_4),
.O(g81__206_carry__2_i_8_n_0));
CARRY4 g81__206_carry__3
(.CI(g81__206_carry__2_n_0),
.CO({g81__206_carry__3_n_0,g81__206_carry__3_n_1,g81__206_carry__3_n_2,g81__206_carry__3_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__3_i_1_n_0,g81__206_carry__3_i_2_n_0,g81__206_carry__3_i_3_n_0,g81__206_carry__3_i_4_n_0}),
.O({g81__206_carry__3_n_4,g81__206_carry__3_n_5,g81__206_carry__3_n_6,g81__206_carry__3_n_7}),
.S({g81__206_carry__3_i_5_n_0,g81__206_carry__3_i_6_n_0,g81__206_carry__3_i_7_n_0,g81__206_carry__3_i_8_n_0}));
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'h02))
g81__206_carry__3_i_1
(.I0(g81__120_carry__1_n_4),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__206_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h1))
g81__206_carry__3_i_2
(.I0(_carry__1_n_2),
.I1(g84),
.O(g81__206_carry__3_i_2_n_0));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'h02))
g81__206_carry__3_i_3
(.I0(g81__120_carry__1_n_6),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__206_carry__3_i_3_n_0));
LUT4 #(
.INIT(16'hF110))
g81__206_carry__3_i_4
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__120_carry__1_n_7),
.I3(g81__92_carry__2_n_1),
.O(g81__206_carry__3_i_4_n_0));
LUT2 #(
.INIT(4'h6))
g81__206_carry__3_i_5
(.I0(g81__206_carry__3_i_1_n_0),
.I1(g81__120_carry__2_n_7),
.O(g81__206_carry__3_i_5_n_0));
(* HLUTNM = "lutpair25" *)
LUT1 #(
.INIT(2'h2))
g81__206_carry__3_i_6
(.I0(g81__120_carry__1_n_4),
.O(g81__206_carry__3_i_6_n_0));
LUT2 #(
.INIT(4'h6))
g81__206_carry__3_i_7
(.I0(g81__206_carry__3_i_3_n_0),
.I1(g81__120_carry__1_n_5),
.O(g81__206_carry__3_i_7_n_0));
(* HLUTNM = "lutpair24" *)
LUT5 #(
.INIT(32'h56AAAAA9))
g81__206_carry__3_i_8
(.I0(g81__120_carry__1_n_6),
.I1(_carry__1_n_2),
.I2(g84),
.I3(g81__92_carry__2_n_1),
.I4(g81__120_carry__1_n_7),
.O(g81__206_carry__3_i_8_n_0));
CARRY4 g81__206_carry__4
(.CI(g81__206_carry__3_n_0),
.CO({g81__206_carry__4_n_0,NLW_g81__206_carry__4_CO_UNCONNECTED[2],g81__206_carry__4_n_2,g81__206_carry__4_n_3}),
.CYINIT(1'b0),
.DI({1'b0,g81__206_carry__4_i_1_n_0,g81__206_carry__4_i_2_n_0,g81__206_carry__4_i_3_n_0}),
.O({NLW_g81__206_carry__4_O_UNCONNECTED[3],g81__206_carry__4_n_5,g81__206_carry__4_n_6,g81__206_carry__4_n_7}),
.S({1'b1,g81__206_carry__4_i_4_n_0,g81__206_carry__4_i_5_n_0,g81__206_carry__4_i_6_n_0}));
LUT2 #(
.INIT(4'h1))
g81__206_carry__4_i_1
(.I0(_carry__1_n_2),
.I1(g84),
.O(g81__206_carry__4_i_1_n_0));
(* HLUTNM = "lutpair26" *)
LUT3 #(
.INIT(8'h02))
g81__206_carry__4_i_2
(.I0(g81__120_carry__2_n_6),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__206_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h1))
g81__206_carry__4_i_3
(.I0(_carry__1_n_2),
.I1(g84),
.O(g81__206_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h1))
g81__206_carry__4_i_4
(.I0(_carry__1_n_2),
.I1(g84),
.O(g81__206_carry__4_i_4_n_0));
LUT2 #(
.INIT(4'h6))
g81__206_carry__4_i_5
(.I0(g81__206_carry__4_i_2_n_0),
.I1(g81__120_carry__2_n_1),
.O(g81__206_carry__4_i_5_n_0));
(* HLUTNM = "lutpair26" *)
LUT1 #(
.INIT(2'h2))
g81__206_carry__4_i_6
(.I0(g81__120_carry__2_n_6),
.O(g81__206_carry__4_i_6_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry_i_1
(.I0(g81__92_carry_n_6),
.I1(g81__149_carry__2_n_5),
.O(g81__206_carry_i_1_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry_i_2
(.I0(g81_carry_n_7),
.I1(g81__149_carry__2_n_6),
.O(g81__206_carry_i_2_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry_i_3
(.I0(g83__0_carry_n_7),
.I1(g81__149_carry__2_n_7),
.O(g81__206_carry_i_3_n_0));
LUT4 #(
.INIT(16'h8778))
g81__206_carry_i_4
(.I0(g81__92_carry_n_6),
.I1(g81__149_carry__2_n_5),
.I2(g81__149_carry__2_n_4),
.I3(g81__92_carry_n_5),
.O(g81__206_carry_i_4_n_0));
LUT4 #(
.INIT(16'h8778))
g81__206_carry_i_5
(.I0(g81_carry_n_7),
.I1(g81__149_carry__2_n_6),
.I2(g81__149_carry__2_n_5),
.I3(g81__92_carry_n_6),
.O(g81__206_carry_i_5_n_0));
LUT4 #(
.INIT(16'h8778))
g81__206_carry_i_6
(.I0(g83__0_carry_n_7),
.I1(g81__149_carry__2_n_7),
.I2(g81__149_carry__2_n_6),
.I3(g81_carry_n_7),
.O(g81__206_carry_i_6_n_0));
LUT2 #(
.INIT(4'h6))
g81__206_carry_i_7
(.I0(g83__0_carry_n_7),
.I1(g81__149_carry__2_n_7),
.O(g81__206_carry_i_7_n_0));
CARRY4 g81__22_carry
(.CI(1'b0),
.CO({g81__22_carry_n_0,g81__22_carry_n_1,g81__22_carry_n_2,g81__22_carry_n_3}),
.CYINIT(1'b0),
.DI({g81_carry_i_1_n_0,g81__22_carry_i_1_n_0,g81__22_carry_i_2_n_0,1'b0}),
.O({g81__22_carry_n_4,g81__22_carry_n_5,g81__22_carry_n_6,NLW_g81__22_carry_O_UNCONNECTED[0]}),
.S({g81__22_carry_i_3_n_0,g81__22_carry_i_4_n_0,g81__22_carry_i_5_n_0,g81__22_carry_i_6_n_0}));
CARRY4 g81__22_carry__0
(.CI(g81__22_carry_n_0),
.CO({g81__22_carry__0_n_0,g81__22_carry__0_n_1,g81__22_carry__0_n_2,g81__22_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__0_i_1_n_0,g81_carry__0_i_2_n_0,g81_carry__0_i_3_n_0,g81_carry__0_i_4_n_0}),
.O({g81__22_carry__0_n_4,g81__22_carry__0_n_5,g81__22_carry__0_n_6,g81__22_carry__0_n_7}),
.S({g81__22_carry__0_i_1_n_0,g81__22_carry__0_i_2_n_0,g81__22_carry__0_i_3_n_0,g81__22_carry__0_i_4_n_0}));
LUT6 #(
.INIT(64'h6996699669699696))
g81__22_carry__0_i_1
(.I0(g81_carry__0_i_1_n_0),
.I1(g81_carry__0_i_12_n_0),
.I2(g81_carry__0_i_13_n_0),
.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81__22_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__22_carry__0_i_2
(.I0(g81_carry__0_i_2_n_0),
.I1(g81_carry__0_i_14_n_0),
.I2(g81_carry__0_i_9_n_0),
.I3(g83__0_carry__0_n_4),
.I4(g83[7]),
.I5(g84),
.O(g81__22_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'h569AA965A965569A))
g81__22_carry__0_i_3
(.I0(g81_carry__0_i_3_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g81_carry__0_i_10_n_0),
.I5(g81_carry__0_i_12_n_0),
.O(g81__22_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h99666666A55A5A5A))
g81__22_carry__0_i_4
(.I0(g81_carry__0_i_15_n_0),
.I1(g83__0_carry__0_n_6),
.I2(g83[5]),
.I3(g81_carry__0_i_10_n_0),
.I4(g83__0_carry_n_7),
.I5(g84),
.O(g81__22_carry__0_i_4_n_0));
CARRY4 g81__22_carry__1
(.CI(g81__22_carry__0_n_0),
.CO({g81__22_carry__1_n_0,g81__22_carry__1_n_1,g81__22_carry__1_n_2,g81__22_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__1_i_1_n_0,g81_carry__1_i_2_n_0,g81_carry__1_i_3_n_0,g81_carry__1_i_4_n_0}),
.O({g81__22_carry__1_n_4,g81__22_carry__1_n_5,g81__22_carry__1_n_6,g81__22_carry__1_n_7}),
.S({g81__22_carry__1_i_1_n_0,g81__22_carry__1_i_2_n_0,g81__22_carry__1_i_3_n_0,g81__22_carry__1_i_4_n_0}));
LUT4 #(
.INIT(16'h569A))
g81__22_carry__1_i_1
(.I0(g81_carry__1_i_1_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81__22_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__22_carry__1_i_2
(.I0(g81_carry__1_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.I4(g81_carry__1_i_9_n_0),
.I5(_carry__1_n_2),
.O(g81__22_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__22_carry__1_i_3
(.I0(g81_carry__1_i_3_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.I4(g81_carry__0_i_12_n_0),
.I5(_carry__1_n_2),
.O(g81__22_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__22_carry__1_i_4
(.I0(g81_carry__1_i_4_n_0),
.I1(g81_carry__1_i_9_n_0),
.I2(g81_carry__0_i_14_n_0),
.I3(g83__0_carry__1_n_2),
.I4(g83[9]),
.I5(g84),
.O(g81__22_carry__1_i_4_n_0));
CARRY4 g81__22_carry__2
(.CI(g81__22_carry__1_n_0),
.CO({NLW_g81__22_carry__2_CO_UNCONNECTED[3],g81__22_carry__2_n_1,NLW_g81__22_carry__2_CO_UNCONNECTED[1],g81__22_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81__22_carry__2_i_1_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81__22_carry__2_O_UNCONNECTED[3:2],g81__22_carry__2_n_6,g81__22_carry__2_n_7}),
.S({1'b0,1'b1,1'b0,g81__22_carry__2_i_2_n_0}));
LUT2 #(
.INIT(4'h1))
g81__22_carry__2_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81__22_carry__2_i_1_n_0));
LUT4 #(
.INIT(16'h569A))
g81__22_carry__2_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81__22_carry__2_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
g81__22_carry_i_1
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81__22_carry_i_1_n_0));
LUT3 #(
.INIT(8'hAC))
g81__22_carry_i_2
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81__22_carry_i_2_n_0));
LUT6 #(
.INIT(64'h99A5995A66A5665A))
g81__22_carry_i_3
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_5),
.I2(g83[2]),
.I3(g84),
.I4(g83[4]),
.I5(g83__0_carry__0_n_7),
.O(g81__22_carry_i_3_n_0));
LUT5 #(
.INIT(32'h353AC5CA))
g81__22_carry_i_4
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81__22_carry_i_4_n_0));
LUT4 #(
.INIT(16'h35CA))
g81__22_carry_i_5
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81__22_carry_i_5_n_0));
LUT3 #(
.INIT(8'hAC))
g81__22_carry_i_6
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81__22_carry_i_6_n_0));
CARRY4 g81__261_carry
(.CI(1'b0),
.CO({g81__261_carry_n_0,g81__261_carry_n_1,g81__261_carry_n_2,g81__261_carry_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__2_n_6,g81__206_carry__2_n_7,1'b0,1'b1}),
.O({g81__261_carry_n_4,g81__261_carry_n_5,g81__261_carry_n_6,g81__261_carry_n_7}),
.S({g81__261_carry_i_1_n_0,g81__261_carry_i_2_n_0,g81__261_carry_i_3_n_0,g81__261_carry_i_4_n_0}));
CARRY4 g81__261_carry__0
(.CI(g81__261_carry_n_0),
.CO({g81__261_carry__0_n_0,g81__261_carry__0_n_1,g81__261_carry__0_n_2,g81__261_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__3_n_6,g81__206_carry__3_n_7,g81__206_carry__2_n_4,g81__206_carry__2_n_5}),
.O({g81__261_carry__0_n_4,g81__261_carry__0_n_5,g81__261_carry__0_n_6,g81__261_carry__0_n_7}),
.S({g81__261_carry__0_i_1_n_0,g81__261_carry__0_i_2_n_0,g81__261_carry__0_i_3_n_0,g81__261_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
g81__261_carry__0_i_1
(.I0(g81__206_carry__3_n_6),
.I1(g81__206_carry__3_n_4),
.O(g81__261_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__0_i_2
(.I0(g81__206_carry__3_n_7),
.I1(g81__206_carry__3_n_5),
.O(g81__261_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__0_i_3
(.I0(g81__206_carry__2_n_4),
.I1(g81__206_carry__3_n_6),
.O(g81__261_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__0_i_4
(.I0(g81__206_carry__2_n_5),
.I1(g81__206_carry__3_n_7),
.O(g81__261_carry__0_i_4_n_0));
CARRY4 g81__261_carry__1
(.CI(g81__261_carry__0_n_0),
.CO({g81__261_carry__1_n_0,g81__261_carry__1_n_1,g81__261_carry__1_n_2,g81__261_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__4_n_6,g81__206_carry__4_n_7,g81__206_carry__3_n_4,g81__206_carry__3_n_5}),
.O({g81__261_carry__1_n_4,g81__261_carry__1_n_5,g81__261_carry__1_n_6,g81__261_carry__1_n_7}),
.S({g81__261_carry__1_i_1_n_0,g81__261_carry__1_i_2_n_0,g81__261_carry__1_i_3_n_0,g81__261_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
g81__261_carry__1_i_1
(.I0(g81__206_carry__4_n_6),
.I1(g81__206_carry__4_n_0),
.O(g81__261_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__1_i_2
(.I0(g81__206_carry__4_n_7),
.I1(g81__206_carry__4_n_5),
.O(g81__261_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__1_i_3
(.I0(g81__206_carry__3_n_4),
.I1(g81__206_carry__4_n_6),
.O(g81__261_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__1_i_4
(.I0(g81__206_carry__3_n_5),
.I1(g81__206_carry__4_n_7),
.O(g81__261_carry__1_i_4_n_0));
CARRY4 g81__261_carry__2
(.CI(g81__261_carry__1_n_0),
.CO({NLW_g81__261_carry__2_CO_UNCONNECTED[3],g81__261_carry__2_n_1,NLW_g81__261_carry__2_CO_UNCONNECTED[1],g81__261_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81__206_carry__4_n_0,g81__206_carry__4_n_5}),
.O({NLW_g81__261_carry__2_O_UNCONNECTED[3:2],g81__261_carry__2_n_6,g81__261_carry__2_n_7}),
.S({1'b0,1'b1,g81__261_carry__2_i_1_n_0,g81__261_carry__2_i_2_n_0}));
LUT3 #(
.INIT(8'h56))
g81__261_carry__2_i_1
(.I0(g81__206_carry__4_n_0),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__261_carry__2_i_1_n_0));
LUT1 #(
.INIT(2'h1))
g81__261_carry__2_i_2
(.I0(g81__206_carry__4_n_5),
.O(g81__261_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry_i_1
(.I0(g81__206_carry__2_n_6),
.I1(g81__206_carry__2_n_4),
.O(g81__261_carry_i_1_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry_i_2
(.I0(g81__206_carry__2_n_7),
.I1(g81__206_carry__2_n_5),
.O(g81__261_carry_i_2_n_0));
LUT1 #(
.INIT(2'h1))
g81__261_carry_i_3
(.I0(g81__206_carry__2_n_6),
.O(g81__261_carry_i_3_n_0));
LUT1 #(
.INIT(2'h2))
g81__261_carry_i_4
(.I0(g81__206_carry__2_n_7),
.O(g81__261_carry_i_4_n_0));
CARRY4 g81__301_carry
(.CI(1'b0),
.CO({g81__301_carry_n_0,g81__301_carry_n_1,g81__301_carry_n_2,g81__301_carry_n_3}),
.CYINIT(1'b0),
.DI({g81__301_carry_i_1_n_0,g81__301_carry_i_2_n_0,g81__301_carry_i_3_n_0,1'b0}),
.O(NLW_g81__301_carry_O_UNCONNECTED[3:0]),
.S({g81__301_carry_i_4_n_0,g81__301_carry_i_5_n_0,g81__301_carry_i_6_n_0,g81__301_carry_i_7_n_0}));
CARRY4 g81__301_carry__0
(.CI(g81__301_carry_n_0),
.CO({g81__301_carry__0_n_0,g81__301_carry__0_n_1,g81__301_carry__0_n_2,g81__301_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81__301_carry__0_i_1_n_0,g81__301_carry__0_i_2_n_0,g81__301_carry__0_i_3_n_0,g81__301_carry__0_i_4_n_0}),
.O(NLW_g81__301_carry__0_O_UNCONNECTED[3:0]),
.S({g81__301_carry__0_i_5_n_0,g81__301_carry__0_i_6_n_0,g81__301_carry__0_i_7_n_0,g81__301_carry__0_i_8_n_0}));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__0_i_1
(.I0(g81__261_carry__0_n_5),
.I1(g84),
.I2(g83[6]),
.I3(g83__0_carry__0_n_5),
.O(g81__301_carry__0_i_1_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__0_i_2
(.I0(g81__261_carry__0_n_6),
.I1(g84),
.I2(g83[5]),
.I3(g83__0_carry__0_n_6),
.O(g81__301_carry__0_i_2_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__0_i_3
(.I0(g81__261_carry__0_n_7),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.O(g81__301_carry__0_i_3_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__0_i_4
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.I2(g83[3]),
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LUT6 #(
.INIT(64'hACFF53005300ACFF))
g81__301_carry__0_i_5
(.I0(g83__0_carry__0_n_5),
.I1(g83[6]),
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.I4(g81__261_carry__0_n_4),
.I5(g81_carry__1_i_9_n_0),
.O(g81__301_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'hACFF53005300ACFF))
g81__301_carry__0_i_6
(.I0(g83__0_carry__0_n_6),
.I1(g83[5]),
.I2(g84),
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.I4(g81__261_carry__0_n_5),
.I5(g81_carry__0_i_12_n_0),
.O(g81__301_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'hACFF53005300ACFF))
g81__301_carry__0_i_7
(.I0(g83__0_carry__0_n_7),
.I1(g83[4]),
.I2(g84),
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.I4(g81__261_carry__0_n_6),
.I5(g81_carry__0_i_14_n_0),
.O(g81__301_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'hB44BB44BB4B44B4B))
g81__301_carry__0_i_8
(.I0(g81_carry__0_i_9_n_0),
.I1(g81__261_carry_n_4),
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.I3(g83__0_carry__0_n_7),
.I4(g83[4]),
.I5(g84),
.O(g81__301_carry__0_i_8_n_0));
CARRY4 g81__301_carry__1
(.CI(g81__301_carry__0_n_0),
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LUT3 #(
.INIT(8'hA8))
g81__301_carry__1_i_1
(.I0(g81__261_carry__1_n_5),
.I1(_carry__1_n_2),
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.O(g81__301_carry__1_i_1_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__1_i_2
(.I0(g81__261_carry__1_n_6),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81__301_carry__1_i_2_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__1_i_3
(.I0(g81__261_carry__1_n_7),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81__301_carry__1_i_3_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__1_i_4
(.I0(g81__261_carry__0_n_4),
.I1(g84),
.I2(g83[7]),
.I3(g83__0_carry__0_n_4),
.O(g81__301_carry__1_i_4_n_0));
LUT4 #(
.INIT(16'h999C))
g81__301_carry__1_i_5
(.I0(g81__261_carry__1_n_5),
.I1(g81__261_carry__1_n_4),
.I2(g84),
.I3(_carry__1_n_2),
.O(g81__301_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h50AF30CF50AFCF30))
g81__301_carry__1_i_6
(.I0(g83__0_carry__1_n_2),
.I1(g83[9]),
.I2(g81__261_carry__1_n_6),
.I3(g81__261_carry__1_n_5),
.I4(g84),
.I5(_carry__1_n_2),
.O(g81__301_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'hACFF53005300ACFF))
g81__301_carry__1_i_7
(.I0(g83__0_carry__1_n_7),
.I1(g83[8]),
.I2(g84),
.I3(g81__261_carry__1_n_7),
.I4(g81__261_carry__1_n_6),
.I5(g81__301_carry__1_i_9_n_0),
.O(g81__301_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'hB44BB44BB4B44B4B))
g81__301_carry__1_i_8
(.I0(g81_carry__1_i_9_n_0),
.I1(g81__261_carry__0_n_4),
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.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81__301_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'hAC))
g81__301_carry__1_i_9
(.I0(g83__0_carry__1_n_2),
.I1(g83[9]),
.I2(g84),
.O(g81__301_carry__1_i_9_n_0));
CARRY4 g81__301_carry__2
(.CI(g81__301_carry__1_n_0),
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LUT3 #(
.INIT(8'h0E))
g81__301_carry__2_i_1
(.I0(_carry__1_n_2),
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.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__2_i_1_n_0));
LUT3 #(
.INIT(8'hA8))
g81__301_carry__2_i_2
(.I0(g81__261_carry__2_n_6),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__301_carry__2_i_2_n_0));
LUT3 #(
.INIT(8'hA8))
g81__301_carry__2_i_3
(.I0(g81__261_carry__2_n_7),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__301_carry__2_i_3_n_0));
LUT3 #(
.INIT(8'hA8))
g81__301_carry__2_i_4
(.I0(g81__261_carry__1_n_4),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__301_carry__2_i_4_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__2_i_5
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__2_i_5_n_0));
LUT4 #(
.INIT(16'h6663))
g81__301_carry__2_i_6
(.I0(g81__261_carry__2_n_6),
.I1(g81__261_carry__2_n_1),
.I2(g84),
.I3(_carry__1_n_2),
.O(g81__301_carry__2_i_6_n_0));
LUT4 #(
.INIT(16'h999C))
g81__301_carry__2_i_7
(.I0(g81__261_carry__2_n_7),
.I1(g81__261_carry__2_n_6),
.I2(g84),
.I3(_carry__1_n_2),
.O(g81__301_carry__2_i_7_n_0));
LUT4 #(
.INIT(16'h999C))
g81__301_carry__2_i_8
(.I0(g81__261_carry__1_n_4),
.I1(g81__261_carry__2_n_7),
.I2(g84),
.I3(_carry__1_n_2),
.O(g81__301_carry__2_i_8_n_0));
CARRY4 g81__301_carry__3
(.CI(g81__301_carry__2_n_0),
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LUT3 #(
.INIT(8'h0E))
g81__301_carry__3_i_1
(.I0(_carry__1_n_2),
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.O(g81__301_carry__3_i_1_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__3_i_2
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__3_i_2_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__3_i_3
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__3_i_3_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__3_i_4
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__3_i_4_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__3_i_5
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__3_i_5_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__3_i_6
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__3_i_6_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__3_i_7
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__3_i_7_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__3_i_8
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__3_i_8_n_0));
CARRY4 g81__301_carry__4
(.CI(g81__301_carry__3_n_0),
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LUT3 #(
.INIT(8'h0E))
g81__301_carry__4_i_1
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.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__4_i_1_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__4_i_2
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__4_i_2_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__4_i_3
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__4_i_3_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__4_i_4
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__4_i_4_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__4_i_5
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__4_i_5_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__4_i_6
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__4_i_6_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__4_i_7
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__4_i_7_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__4_i_8
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__4_i_8_n_0));
CARRY4 g81__301_carry__5
(.CI(g81__301_carry__4_n_0),
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LUT3 #(
.INIT(8'h0E))
g81__301_carry__5_i_1
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LUT3 #(
.INIT(8'h0E))
g81__301_carry__5_i_2
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.I1(g84),
.I2(g81__261_carry__2_n_1),
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LUT3 #(
.INIT(8'h0E))
g81__301_carry__5_i_3
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__5_i_3_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__5_i_4
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__5_i_4_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__5_i_5
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__5_i_5_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__5_i_6
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__5_i_6_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__5_i_7
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.I2(_carry__1_n_2),
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LUT3 #(
.INIT(8'hFD))
g81__301_carry__5_i_8
(.I0(g81__261_carry__2_n_1),
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.I2(_carry__1_n_2),
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CARRY4 g81__301_carry__6
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LUT3 #(
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g81__301_carry__6_i_1
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LUT3 #(
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g81__301_carry__6_i_2
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LUT3 #(
.INIT(8'h0E))
g81__301_carry__6_i_3
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LUT3 #(
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g81__301_carry__6_i_4
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LUT3 #(
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g81__301_carry__6_i_5
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LUT3 #(
.INIT(8'hFD))
g81__301_carry__6_i_6
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.I2(_carry__1_n_2),
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LUT4 #(
.INIT(16'h028A))
g81__301_carry_i_1
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.I1(g84),
.I2(g83[2]),
.I3(g83__0_carry_n_5),
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LUT4 #(
.INIT(16'hABEF))
g81__301_carry_i_2
(.I0(g81__261_carry_n_6),
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.I2(g83[1]),
.I3(g83__0_carry_n_6),
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LUT2 #(
.INIT(4'hB))
g81__301_carry_i_3
(.I0(g81__261_carry_n_7),
.I1(g83__0_carry_n_7),
.O(g81__301_carry_i_3_n_0));
LUT6 #(
.INIT(64'hACFF53005300ACFF))
g81__301_carry_i_4
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.I4(g81__261_carry_n_4),
.I5(g81_carry__0_i_9_n_0),
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LUT6 #(
.INIT(64'h2DD22DD22D2DD2D2))
g81__301_carry_i_5
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.I3(g83__0_carry_n_5),
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.I5(g84),
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LUT6 #(
.INIT(64'hD22DD22DD2D22D2D))
g81__301_carry_i_6
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.I1(g81__261_carry_n_7),
.I2(g81__261_carry_n_6),
.I3(g83__0_carry_n_6),
.I4(g83[1]),
.I5(g84),
.O(g81__301_carry_i_6_n_0));
LUT2 #(
.INIT(4'h6))
g81__301_carry_i_7
(.I0(g83__0_carry_n_7),
.I1(g81__261_carry_n_7),
.O(g81__301_carry_i_7_n_0));
CARRY4 g81__347_carry
(.CI(1'b0),
.CO({g81__347_carry_n_0,g81__347_carry_n_1,g81__347_carry_n_2,g81__347_carry_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({g81__347_carry_n_4,g81__347_carry_n_5,g81__347_carry_n_6,g81__347_carry_n_7}),
.S({g81__347_carry_i_1_n_0,g81__347_carry_i_2_n_0,g81__347_carry_i_3_n_0,g81__347_carry_i_4_n_0}));
CARRY4 g81__347_carry__0
(.CI(g81__347_carry_n_0),
.CO({NLW_g81__347_carry__0_CO_UNCONNECTED[3],g81__347_carry__0_n_1,g81__347_carry__0_n_2,g81__347_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({g81__347_carry__0_n_4,g81__347_carry__0_n_5,g81__347_carry__0_n_6,g81__347_carry__0_n_7}),
.S({g81__347_carry__0_i_1_n_0,g81__347_carry__0_i_2_n_0,g81__347_carry__0_i_3_n_0,g81__347_carry__0_i_4_n_0}));
LUT1 #(
.INIT(2'h2))
g81__347_carry__0_i_1
(.I0(g81__206_carry__3_n_4),
.O(g81__347_carry__0_i_1_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry__0_i_2
(.I0(g81__206_carry__3_n_5),
.O(g81__347_carry__0_i_2_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry__0_i_3
(.I0(g81__206_carry__3_n_6),
.O(g81__347_carry__0_i_3_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry__0_i_4
(.I0(g81__206_carry__3_n_7),
.O(g81__347_carry__0_i_4_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry_i_1
(.I0(g81__206_carry__2_n_4),
.O(g81__347_carry_i_1_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry_i_2
(.I0(g81__206_carry__2_n_5),
.O(g81__347_carry_i_2_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry_i_3
(.I0(g81__206_carry__2_n_6),
.O(g81__347_carry_i_3_n_0));
LUT1 #(
.INIT(2'h1))
g81__347_carry_i_4
(.I0(g81__206_carry__2_n_7),
.O(g81__347_carry_i_4_n_0));
CARRY4 g81__53_carry
(.CI(1'b0),
.CO({g81__53_carry_n_0,g81__53_carry_n_1,g81__53_carry_n_2,g81__53_carry_n_3}),
.CYINIT(1'b0),
.DI({g81_carry_i_1_n_0,g81__53_carry_i_1_n_0,g81__53_carry_i_2_n_0,1'b0}),
.O({g81__53_carry_n_4,g81__53_carry_n_5,g81__53_carry_n_6,NLW_g81__53_carry_O_UNCONNECTED[0]}),
.S({g81__53_carry_i_3_n_0,g81__53_carry_i_4_n_0,g81__53_carry_i_5_n_0,g81__53_carry_i_6_n_0}));
CARRY4 g81__53_carry__0
(.CI(g81__53_carry_n_0),
.CO({g81__53_carry__0_n_0,g81__53_carry__0_n_1,g81__53_carry__0_n_2,g81__53_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__0_i_1_n_0,g81_carry__0_i_2_n_0,g81_carry__0_i_3_n_0,g81_carry__0_i_4_n_0}),
.O({g81__53_carry__0_n_4,g81__53_carry__0_n_5,g81__53_carry__0_n_6,g81__53_carry__0_n_7}),
.S({g81__53_carry__0_i_1_n_0,g81__53_carry__0_i_2_n_0,g81__53_carry__0_i_3_n_0,g81__53_carry__0_i_4_n_0}));
LUT6 #(
.INIT(64'h6996699669699696))
g81__53_carry__0_i_1
(.I0(g81_carry__0_i_1_n_0),
.I1(g81_carry__0_i_12_n_0),
.I2(g81_carry__0_i_13_n_0),
.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81__53_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__53_carry__0_i_2
(.I0(g81_carry__0_i_2_n_0),
.I1(g81_carry__0_i_14_n_0),
.I2(g81_carry__0_i_9_n_0),
.I3(g83__0_carry__0_n_4),
.I4(g83[7]),
.I5(g84),
.O(g81__53_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'h569AA965A965569A))
g81__53_carry__0_i_3
(.I0(g81_carry__0_i_3_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g81_carry__0_i_10_n_0),
.I5(g81_carry__0_i_12_n_0),
.O(g81__53_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h99666666A55A5A5A))
g81__53_carry__0_i_4
(.I0(g81_carry__0_i_15_n_0),
.I1(g83__0_carry__0_n_6),
.I2(g83[5]),
.I3(g81_carry__0_i_10_n_0),
.I4(g83__0_carry_n_7),
.I5(g84),
.O(g81__53_carry__0_i_4_n_0));
CARRY4 g81__53_carry__1
(.CI(g81__53_carry__0_n_0),
.CO({g81__53_carry__1_n_0,g81__53_carry__1_n_1,g81__53_carry__1_n_2,g81__53_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__1_i_1_n_0,g81_carry__1_i_2_n_0,g81_carry__1_i_3_n_0,g81_carry__1_i_4_n_0}),
.O({g81__53_carry__1_n_4,g81__53_carry__1_n_5,g81__53_carry__1_n_6,g81__53_carry__1_n_7}),
.S({g81__53_carry__1_i_1_n_0,g81__53_carry__1_i_2_n_0,g81__53_carry__1_i_3_n_0,g81__53_carry__1_i_4_n_0}));
LUT4 #(
.INIT(16'h569A))
g81__53_carry__1_i_1
(.I0(g81_carry__1_i_1_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81__53_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__53_carry__1_i_2
(.I0(g81_carry__1_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.I4(g81_carry__1_i_9_n_0),
.I5(_carry__1_n_2),
.O(g81__53_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__53_carry__1_i_3
(.I0(g81_carry__1_i_3_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.I4(g81_carry__0_i_12_n_0),
.I5(_carry__1_n_2),
.O(g81__53_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__53_carry__1_i_4
(.I0(g81_carry__1_i_4_n_0),
.I1(g81_carry__1_i_9_n_0),
.I2(g81_carry__0_i_14_n_0),
.I3(g83__0_carry__1_n_2),
.I4(g83[9]),
.I5(g84),
.O(g81__53_carry__1_i_4_n_0));
CARRY4 g81__53_carry__2
(.CI(g81__53_carry__1_n_0),
.CO({NLW_g81__53_carry__2_CO_UNCONNECTED[3],g81__53_carry__2_n_1,NLW_g81__53_carry__2_CO_UNCONNECTED[1],g81__53_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81__53_carry__2_i_1_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81__53_carry__2_O_UNCONNECTED[3:2],g81__53_carry__2_n_6,g81__53_carry__2_n_7}),
.S({1'b0,1'b1,1'b0,g81__53_carry__2_i_2_n_0}));
LUT2 #(
.INIT(4'h1))
g81__53_carry__2_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81__53_carry__2_i_1_n_0));
LUT4 #(
.INIT(16'h569A))
g81__53_carry__2_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81__53_carry__2_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
g81__53_carry_i_1
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81__53_carry_i_1_n_0));
LUT3 #(
.INIT(8'hAC))
g81__53_carry_i_2
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81__53_carry_i_2_n_0));
LUT6 #(
.INIT(64'h99A5995A66A5665A))
g81__53_carry_i_3
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_5),
.I2(g83[2]),
.I3(g84),
.I4(g83[4]),
.I5(g83__0_carry__0_n_7),
.O(g81__53_carry_i_3_n_0));
LUT5 #(
.INIT(32'h353AC5CA))
g81__53_carry_i_4
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81__53_carry_i_4_n_0));
LUT4 #(
.INIT(16'h35CA))
g81__53_carry_i_5
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81__53_carry_i_5_n_0));
LUT3 #(
.INIT(8'hAC))
g81__53_carry_i_6
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81__53_carry_i_6_n_0));
CARRY4 g81__92_carry
(.CI(1'b0),
.CO({g81__92_carry_n_0,g81__92_carry_n_1,g81__92_carry_n_2,g81__92_carry_n_3}),
.CYINIT(1'b0),
.DI({g81_carry_i_1_n_0,g81__92_carry_i_1_n_0,g81__92_carry_i_2_n_0,1'b0}),
.O({g81__92_carry_n_4,g81__92_carry_n_5,g81__92_carry_n_6,NLW_g81__92_carry_O_UNCONNECTED[0]}),
.S({g81__92_carry_i_3_n_0,g81__92_carry_i_4_n_0,g81__92_carry_i_5_n_0,g81__92_carry_i_6_n_0}));
CARRY4 g81__92_carry__0
(.CI(g81__92_carry_n_0),
.CO({g81__92_carry__0_n_0,g81__92_carry__0_n_1,g81__92_carry__0_n_2,g81__92_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__0_i_1_n_0,g81_carry__0_i_2_n_0,g81_carry__0_i_3_n_0,g81_carry__0_i_4_n_0}),
.O({g81__92_carry__0_n_4,g81__92_carry__0_n_5,g81__92_carry__0_n_6,g81__92_carry__0_n_7}),
.S({g81__92_carry__0_i_1_n_0,g81__92_carry__0_i_2_n_0,g81__92_carry__0_i_3_n_0,g81__92_carry__0_i_4_n_0}));
LUT6 #(
.INIT(64'h6996699669699696))
g81__92_carry__0_i_1
(.I0(g81_carry__0_i_1_n_0),
.I1(g81_carry__0_i_12_n_0),
.I2(g81_carry__0_i_13_n_0),
.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81__92_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__92_carry__0_i_2
(.I0(g81_carry__0_i_2_n_0),
.I1(g81_carry__0_i_14_n_0),
.I2(g81_carry__0_i_9_n_0),
.I3(g83__0_carry__0_n_4),
.I4(g83[7]),
.I5(g84),
.O(g81__92_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'h569AA965A965569A))
g81__92_carry__0_i_3
(.I0(g81_carry__0_i_3_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g81_carry__0_i_10_n_0),
.I5(g81_carry__0_i_12_n_0),
.O(g81__92_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h99666666A55A5A5A))
g81__92_carry__0_i_4
(.I0(g81_carry__0_i_15_n_0),
.I1(g83__0_carry__0_n_6),
.I2(g83[5]),
.I3(g81_carry__0_i_10_n_0),
.I4(g83__0_carry_n_7),
.I5(g84),
.O(g81__92_carry__0_i_4_n_0));
CARRY4 g81__92_carry__1
(.CI(g81__92_carry__0_n_0),
.CO({g81__92_carry__1_n_0,g81__92_carry__1_n_1,g81__92_carry__1_n_2,g81__92_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__1_i_1_n_0,g81_carry__1_i_2_n_0,g81_carry__1_i_3_n_0,g81_carry__1_i_4_n_0}),
.O({g81__92_carry__1_n_4,g81__92_carry__1_n_5,g81__92_carry__1_n_6,g81__92_carry__1_n_7}),
.S({g81__92_carry__1_i_1_n_0,g81__92_carry__1_i_2_n_0,g81__92_carry__1_i_3_n_0,g81__92_carry__1_i_4_n_0}));
LUT4 #(
.INIT(16'h569A))
g81__92_carry__1_i_1
(.I0(g81_carry__1_i_1_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81__92_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__92_carry__1_i_2
(.I0(g81_carry__1_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.I4(g81_carry__1_i_9_n_0),
.I5(_carry__1_n_2),
.O(g81__92_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__92_carry__1_i_3
(.I0(g81_carry__1_i_3_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.I4(g81_carry__0_i_12_n_0),
.I5(_carry__1_n_2),
.O(g81__92_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__92_carry__1_i_4
(.I0(g81_carry__1_i_4_n_0),
.I1(g81_carry__1_i_9_n_0),
.I2(g81_carry__0_i_14_n_0),
.I3(g83__0_carry__1_n_2),
.I4(g83[9]),
.I5(g84),
.O(g81__92_carry__1_i_4_n_0));
CARRY4 g81__92_carry__2
(.CI(g81__92_carry__1_n_0),
.CO({NLW_g81__92_carry__2_CO_UNCONNECTED[3],g81__92_carry__2_n_1,NLW_g81__92_carry__2_CO_UNCONNECTED[1],g81__92_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81__92_carry__2_i_1_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81__92_carry__2_O_UNCONNECTED[3:2],g81__92_carry__2_n_6,g81__92_carry__2_n_7}),
.S({1'b0,1'b1,1'b0,g81__92_carry__2_i_2_n_0}));
LUT2 #(
.INIT(4'h1))
g81__92_carry__2_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81__92_carry__2_i_1_n_0));
LUT4 #(
.INIT(16'h569A))
g81__92_carry__2_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81__92_carry__2_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
g81__92_carry_i_1
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81__92_carry_i_1_n_0));
LUT3 #(
.INIT(8'hAC))
g81__92_carry_i_2
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81__92_carry_i_2_n_0));
LUT6 #(
.INIT(64'h99A5995A66A5665A))
g81__92_carry_i_3
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_5),
.I2(g83[2]),
.I3(g84),
.I4(g83[4]),
.I5(g83__0_carry__0_n_7),
.O(g81__92_carry_i_3_n_0));
LUT5 #(
.INIT(32'h353AC5CA))
g81__92_carry_i_4
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81__92_carry_i_4_n_0));
LUT4 #(
.INIT(16'h35CA))
g81__92_carry_i_5
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81__92_carry_i_5_n_0));
LUT3 #(
.INIT(8'hAC))
g81__92_carry_i_6
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81__92_carry_i_6_n_0));
CARRY4 g81_carry
(.CI(1'b0),
.CO({g81_carry_n_0,g81_carry_n_1,g81_carry_n_2,g81_carry_n_3}),
.CYINIT(1'b0),
.DI({g81_carry_i_1_n_0,g81_carry_i_2_n_0,g81_carry_i_3_n_0,1'b0}),
.O({NLW_g81_carry_O_UNCONNECTED[3:1],g81_carry_n_7}),
.S({g81_carry_i_4_n_0,g81_carry_i_5_n_0,g81_carry_i_6_n_0,g81_carry_i_7_n_0}));
CARRY4 g81_carry__0
(.CI(g81_carry_n_0),
.CO({g81_carry__0_n_0,g81_carry__0_n_1,g81_carry__0_n_2,g81_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__0_i_1_n_0,g81_carry__0_i_2_n_0,g81_carry__0_i_3_n_0,g81_carry__0_i_4_n_0}),
.O({g81_carry__0_n_4,g81_carry__0_n_5,g81_carry__0_n_6,NLW_g81_carry__0_O_UNCONNECTED[0]}),
.S({g81_carry__0_i_5_n_0,g81_carry__0_i_6_n_0,g81_carry__0_i_7_n_0,g81_carry__0_i_8_n_0}));
LUT6 #(
.INIT(64'hFEBAECA8BA32A820))
g81_carry__0_i_1
(.I0(g81_carry__0_i_9_n_0),
.I1(g84),
.I2(g83[5]),
.I3(g83__0_carry__0_n_6),
.I4(g83[7]),
.I5(g83__0_carry__0_n_4),
.O(g81_carry__0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_10
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81_carry__0_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_11
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81_carry__0_i_11_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_12
(.I0(g83__0_carry__0_n_5),
.I1(g83[6]),
.I2(g84),
.O(g81_carry__0_i_12_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_13
(.I0(g83__0_carry__0_n_7),
.I1(g83[4]),
.I2(g84),
.O(g81_carry__0_i_13_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_14
(.I0(g83__0_carry__0_n_6),
.I1(g83[5]),
.I2(g84),
.O(g81_carry__0_i_14_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h353AC5CA))
g81_carry__0_i_15
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81_carry__0_i_15_n_0));
LUT6 #(
.INIT(64'hFEBAECA8BA32A820))
g81_carry__0_i_2
(.I0(g81_carry__0_i_10_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g83[6]),
.I5(g83__0_carry__0_n_5),
.O(g81_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'hFEBAECA8BA32A820))
g81_carry__0_i_3
(.I0(g81_carry__0_i_11_n_0),
.I1(g84),
.I2(g83[3]),
.I3(g83__0_carry_n_4),
.I4(g83[5]),
.I5(g83__0_carry__0_n_6),
.O(g81_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'hC33CC33CA5A55A5A))
g81_carry__0_i_4
(.I0(g83[5]),
.I1(g83__0_carry__0_n_6),
.I2(g81_carry__0_i_11_n_0),
.I3(g83__0_carry_n_4),
.I4(g83[3]),
.I5(g84),
.O(g81_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81_carry__0_i_5
(.I0(g81_carry__0_i_1_n_0),
.I1(g81_carry__0_i_12_n_0),
.I2(g81_carry__0_i_13_n_0),
.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81_carry__0_i_6
(.I0(g81_carry__0_i_2_n_0),
.I1(g81_carry__0_i_14_n_0),
.I2(g81_carry__0_i_9_n_0),
.I3(g83__0_carry__0_n_4),
.I4(g83[7]),
.I5(g84),
.O(g81_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h569AA965A965569A))
g81_carry__0_i_7
(.I0(g81_carry__0_i_3_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g81_carry__0_i_10_n_0),
.I5(g81_carry__0_i_12_n_0),
.O(g81_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h99666666A55A5A5A))
g81_carry__0_i_8
(.I0(g81_carry__0_i_15_n_0),
.I1(g83__0_carry__0_n_6),
.I2(g83[5]),
.I3(g81_carry__0_i_10_n_0),
.I4(g83__0_carry_n_7),
.I5(g84),
.O(g81_carry__0_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_9
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81_carry__0_i_9_n_0));
CARRY4 g81_carry__1
(.CI(g81_carry__0_n_0),
.CO({g81_carry__1_n_0,g81_carry__1_n_1,g81_carry__1_n_2,g81_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__1_i_1_n_0,g81_carry__1_i_2_n_0,g81_carry__1_i_3_n_0,g81_carry__1_i_4_n_0}),
.O({g81_carry__1_n_4,g81_carry__1_n_5,g81_carry__1_n_6,g81_carry__1_n_7}),
.S({g81_carry__1_i_5_n_0,g81_carry__1_i_6_n_0,g81_carry__1_i_7_n_0,g81_carry__1_i_8_n_0}));
LUT6 #(
.INIT(64'hCAC00A00CFCA0F0A))
g81_carry__1_i_1
(.I0(g83[7]),
.I1(g83__0_carry__0_n_4),
.I2(g84),
.I3(g83[9]),
.I4(g83__0_carry__1_n_2),
.I5(_carry__1_n_2),
.O(g81_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hCAC00A00CFCA0F0A))
g81_carry__1_i_2
(.I0(g83[6]),
.I1(g83__0_carry__0_n_5),
.I2(g84),
.I3(g83[8]),
.I4(g83__0_carry__1_n_7),
.I5(_carry__1_n_2),
.O(g81_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hFFE4EEA0F544E400))
g81_carry__1_i_3
(.I0(g84),
.I1(g83[5]),
.I2(g83__0_carry__0_n_6),
.I3(g81_carry__1_i_9_n_0),
.I4(g83[9]),
.I5(g83__0_carry__1_n_2),
.O(g81_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'hFFE4EEA0F544E400))
g81_carry__1_i_4
(.I0(g84),
.I1(g83[4]),
.I2(g83__0_carry__0_n_7),
.I3(g81_carry__0_i_12_n_0),
.I4(g83[8]),
.I5(g83__0_carry__1_n_7),
.O(g81_carry__1_i_4_n_0));
LUT4 #(
.INIT(16'h569A))
g81_carry__1_i_5
(.I0(g81_carry__1_i_1_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81_carry__1_i_6
(.I0(g81_carry__1_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.I4(g81_carry__1_i_9_n_0),
.I5(_carry__1_n_2),
.O(g81_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81_carry__1_i_7
(.I0(g81_carry__1_i_3_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.I4(g81_carry__0_i_12_n_0),
.I5(_carry__1_n_2),
.O(g81_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81_carry__1_i_8
(.I0(g81_carry__1_i_4_n_0),
.I1(g81_carry__1_i_9_n_0),
.I2(g81_carry__0_i_14_n_0),
.I3(g83__0_carry__1_n_2),
.I4(g83[9]),
.I5(g84),
.O(g81_carry__1_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__1_i_9
(.I0(g83__0_carry__0_n_4),
.I1(g83[7]),
.I2(g84),
.O(g81_carry__1_i_9_n_0));
CARRY4 g81_carry__2
(.CI(g81_carry__1_n_0),
.CO({NLW_g81_carry__2_CO_UNCONNECTED[3],g81_carry__2_n_1,NLW_g81_carry__2_CO_UNCONNECTED[1],g81_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81_carry__2_i_1_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81_carry__2_O_UNCONNECTED[3:2],g81_carry__2_n_6,g81_carry__2_n_7}),
.S({1'b0,1'b1,1'b0,g81_carry__2_i_3_n_0}));
LUT2 #(
.INIT(4'h1))
g81_carry__2_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81_carry__2_i_1_n_0));
(* HLUTNM = "lutpair7" *)
LUT2 #(
.INIT(4'h1))
g81_carry__2_i_2
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81_carry__2_i_2_n_0));
LUT4 #(
.INIT(16'h569A))
g81_carry__2_i_3
(.I0(g81_carry__2_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81_carry__2_i_3_n_0));
LUT4 #(
.INIT(16'h35CA))
g81_carry_i_1
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81_carry_i_1_n_0));
LUT3 #(
.INIT(8'hAC))
g81_carry_i_2
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81_carry_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
g81_carry_i_3
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81_carry_i_3_n_0));
LUT6 #(
.INIT(64'h99A5995A66A5665A))
g81_carry_i_4
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_5),
.I2(g83[2]),
.I3(g84),
.I4(g83[4]),
.I5(g83__0_carry__0_n_7),
.O(g81_carry_i_4_n_0));
LUT5 #(
.INIT(32'h353AC5CA))
g81_carry_i_5
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81_carry_i_5_n_0));
LUT4 #(
.INIT(16'h35CA))
g81_carry_i_6
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81_carry_i_6_n_0));
LUT3 #(
.INIT(8'hAC))
g81_carry_i_7
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81_carry_i_7_n_0));
CARRY4 g83__0_carry
(.CI(1'b0),
.CO({g83__0_carry_n_0,g83__0_carry_n_1,g83__0_carry_n_2,g83__0_carry_n_3}),
.CYINIT(1'b0),
.DI({g83__0_carry_i_1_n_0,g83__0_carry_i_2_n_0,g83__0_carry_i_3_n_0,1'b0}),
.O({g83__0_carry_n_4,g83__0_carry_n_5,g83__0_carry_n_6,g83__0_carry_n_7}),
.S({g83__0_carry_i_4_n_0,g83__0_carry_i_5_n_0,g83__0_carry_i_6_n_0,g83__0_carry_i_7_n_0}));
CARRY4 g83__0_carry__0
(.CI(g83__0_carry_n_0),
.CO({g83__0_carry__0_n_0,g83__0_carry__0_n_1,g83__0_carry__0_n_2,g83__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g83__0_carry__0_i_1_n_0,g83__0_carry__0_i_2_n_0,g83__0_carry__0_i_3_n_0,g83__0_carry__0_i_4_n_0}),
.O({g83__0_carry__0_n_4,g83__0_carry__0_n_5,g83__0_carry__0_n_6,g83__0_carry__0_n_7}),
.S({g83__0_carry__0_i_5_n_0,g83__0_carry__0_i_6_n_0,g83__0_carry__0_i_7_n_0,g83__0_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair6" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry__0_i_1
(.I0(rgb888[14]),
.I1(rgb888[6]),
.I2(rgb888[22]),
.O(g83__0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair5" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry__0_i_2
(.I0(rgb888[13]),
.I1(rgb888[5]),
.I2(rgb888[21]),
.O(g83__0_carry__0_i_2_n_0));
(* HLUTNM = "lutpair4" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry__0_i_3
(.I0(rgb888[12]),
.I1(rgb888[4]),
.I2(rgb888[20]),
.O(g83__0_carry__0_i_3_n_0));
(* HLUTNM = "lutpair3" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry__0_i_4
(.I0(rgb888[11]),
.I1(rgb888[3]),
.I2(rgb888[19]),
.O(g83__0_carry__0_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
g83__0_carry__0_i_5
(.I0(g83__0_carry__0_i_1_n_0),
.I1(rgb888[7]),
.I2(rgb888[15]),
.I3(rgb888[23]),
.O(g83__0_carry__0_i_5_n_0));
(* HLUTNM = "lutpair6" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry__0_i_6
(.I0(rgb888[14]),
.I1(rgb888[6]),
.I2(rgb888[22]),
.I3(g83__0_carry__0_i_2_n_0),
.O(g83__0_carry__0_i_6_n_0));
(* HLUTNM = "lutpair5" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry__0_i_7
(.I0(rgb888[13]),
.I1(rgb888[5]),
.I2(rgb888[21]),
.I3(g83__0_carry__0_i_3_n_0),
.O(g83__0_carry__0_i_7_n_0));
(* HLUTNM = "lutpair4" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry__0_i_8
(.I0(rgb888[12]),
.I1(rgb888[4]),
.I2(rgb888[20]),
.I3(g83__0_carry__0_i_4_n_0),
.O(g83__0_carry__0_i_8_n_0));
CARRY4 g83__0_carry__1
(.CI(g83__0_carry__0_n_0),
.CO({NLW_g83__0_carry__1_CO_UNCONNECTED[3:2],g83__0_carry__1_n_2,NLW_g83__0_carry__1_CO_UNCONNECTED[0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW_g83__0_carry__1_O_UNCONNECTED[3:1],g83__0_carry__1_n_7}),
.S({1'b0,1'b0,1'b1,g83__0_carry__1_i_1_n_0}));
LUT3 #(
.INIT(8'hE8))
g83__0_carry__1_i_1
(.I0(rgb888[15]),
.I1(rgb888[7]),
.I2(rgb888[23]),
.O(g83__0_carry__1_i_1_n_0));
(* HLUTNM = "lutpair2" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry_i_1
(.I0(rgb888[10]),
.I1(rgb888[2]),
.I2(rgb888[18]),
.O(g83__0_carry_i_1_n_0));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry_i_2
(.I0(rgb888[9]),
.I1(rgb888[1]),
.I2(rgb888[17]),
.O(g83__0_carry_i_2_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry_i_3
(.I0(rgb888[8]),
.I1(rgb888[0]),
.I2(rgb888[16]),
.O(g83__0_carry_i_3_n_0));
(* HLUTNM = "lutpair3" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry_i_4
(.I0(rgb888[11]),
.I1(rgb888[3]),
.I2(rgb888[19]),
.I3(g83__0_carry_i_1_n_0),
.O(g83__0_carry_i_4_n_0));
(* HLUTNM = "lutpair2" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry_i_5
(.I0(rgb888[10]),
.I1(rgb888[2]),
.I2(rgb888[18]),
.I3(g83__0_carry_i_2_n_0),
.O(g83__0_carry_i_5_n_0));
(* HLUTNM = "lutpair1" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry_i_6
(.I0(rgb888[9]),
.I1(rgb888[1]),
.I2(rgb888[17]),
.I3(g83__0_carry_i_3_n_0),
.O(g83__0_carry_i_6_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'h96))
g83__0_carry_i_7
(.I0(rgb888[8]),
.I1(rgb888[0]),
.I2(rgb888[16]),
.O(g83__0_carry_i_7_n_0));
CARRY4 g84_carry
(.CI(1'b0),
.CO({g84_carry_n_0,g84_carry_n_1,g84_carry_n_2,g84_carry_n_3}),
.CYINIT(1'b1),
.DI({g84_carry_i_1_n_0,g84_carry_i_2_n_0,g84_carry_i_3_n_0,g84_carry_i_4_n_0}),
.O(NLW_g84_carry_O_UNCONNECTED[3:0]),
.S({g84_carry_i_5_n_0,g84_carry_i_6_n_0,g84_carry_i_7_n_0,g84_carry_i_8_n_0}));
CARRY4 g84_carry__0
(.CI(g84_carry_n_0),
.CO({NLW_g84_carry__0_CO_UNCONNECTED[3:1],g84}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,g84_carry__0_i_1_n_0}),
.O(NLW_g84_carry__0_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,g84_carry__0_i_2_n_0}));
LUT2 #(
.INIT(4'hE))
g84_carry__0_i_1
(.I0(g83__0_carry__1_n_7),
.I1(g83__0_carry__1_n_2),
.O(g84_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h1))
g84_carry__0_i_2
(.I0(g83__0_carry__1_n_7),
.I1(g83__0_carry__1_n_2),
.O(g84_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'hE))
g84_carry_i_1
(.I0(g83__0_carry__0_n_5),
.I1(g83__0_carry__0_n_4),
.O(g84_carry_i_1_n_0));
LUT2 #(
.INIT(4'hE))
g84_carry_i_2
(.I0(g83__0_carry__0_n_7),
.I1(g83__0_carry__0_n_6),
.O(g84_carry_i_2_n_0));
LUT2 #(
.INIT(4'hE))
g84_carry_i_3
(.I0(g83__0_carry_n_5),
.I1(g83__0_carry_n_4),
.O(g84_carry_i_3_n_0));
LUT2 #(
.INIT(4'hE))
g84_carry_i_4
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_6),
.O(g84_carry_i_4_n_0));
LUT2 #(
.INIT(4'h1))
g84_carry_i_5
(.I0(g83__0_carry__0_n_5),
.I1(g83__0_carry__0_n_4),
.O(g84_carry_i_5_n_0));
LUT2 #(
.INIT(4'h1))
g84_carry_i_6
(.I0(g83__0_carry__0_n_7),
.I1(g83__0_carry__0_n_6),
.O(g84_carry_i_6_n_0));
LUT2 #(
.INIT(4'h1))
g84_carry_i_7
(.I0(g83__0_carry_n_5),
.I1(g83__0_carry_n_4),
.O(g84_carry_i_7_n_0));
LUT2 #(
.INIT(4'h1))
g84_carry_i_8
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_6),
.O(g84_carry_i_8_n_0));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[0]_i_1
(.I0(g81__206_carry__2_n_7),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry_n_7),
.O(g810_in[0]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[1]_i_1
(.I0(g81__206_carry__2_n_6),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry_n_6),
.O(g810_in[1]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[2]_i_1
(.I0(g81__206_carry__2_n_5),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry_n_5),
.O(g810_in[2]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[3]_i_1
(.I0(g81__206_carry__2_n_4),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry_n_4),
.O(g810_in[3]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[4]_i_1
(.I0(g81__206_carry__3_n_7),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry__0_n_7),
.O(g810_in[4]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[5]_i_1
(.I0(g81__206_carry__3_n_6),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry__0_n_6),
.O(g810_in[5]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[6]_i_1
(.I0(g81__206_carry__3_n_5),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry__0_n_5),
.O(g810_in[6]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[7]_i_1
(.I0(g81__206_carry__3_n_4),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry__0_n_4),
.O(g810_in[7]));
FDRE \g8_reg[0]
(.C(clk),
.CE(1'b1),
.D(g810_in[0]),
.Q(g8[0]),
.R(1'b0));
FDRE \g8_reg[1]
(.C(clk),
.CE(1'b1),
.D(g810_in[1]),
.Q(g8[1]),
.R(1'b0));
FDRE \g8_reg[2]
(.C(clk),
.CE(1'b1),
.D(g810_in[2]),
.Q(g8[2]),
.R(1'b0));
FDRE \g8_reg[3]
(.C(clk),
.CE(1'b1),
.D(g810_in[3]),
.Q(g8[3]),
.R(1'b0));
FDRE \g8_reg[4]
(.C(clk),
.CE(1'b1),
.D(g810_in[4]),
.Q(g8[4]),
.R(1'b0));
FDRE \g8_reg[5]
(.C(clk),
.CE(1'b1),
.D(g810_in[5]),
.Q(g8[5]),
.R(1'b0));
FDRE \g8_reg[6]
(.C(clk),
.CE(1'b1),
.D(g810_in[6]),
.Q(g8[6]),
.R(1'b0));
FDRE \g8_reg[7]
(.C(clk),
.CE(1'b1),
.D(g810_in[7]),
.Q(g8[7]),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "system_rgb888_to_g8_1_0,rgb888_to_g8,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "rgb888_to_g8,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rgb888_to_g8_1_0
(clk,
rgb888,
g8);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [23:0]rgb888;
output [7:0]g8;
wire clk;
wire [7:0]g8;
wire [23:0]rgb888;
system_rgb888_to_g8_1_0_rgb888_to_g8 U0
(.clk(clk),
.g8(g8),
.rgb888(rgb888));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
`define intN 27
`include "primitives.v"
`include "tests_collatz.v"
module top(
input clk,
input [15:0] in,
output [15:0] out
);
reg `intT a = 0;
wire `intT a_in = {12'h0, in[14:0]};
wire `intT b;
reg [26:0] div = 0;
reg [14:0] out_reg = 0;
reg in_valid;
reg out_ready;
wire collatz_in_ready;
localparam nrst = `true;
`inst_sync(tests_collatz, collatz, #())(`sync(in_valid, out_ready), .in0(a), .out0(b));
assign out = {~collatz_in_ready, out_reg};
initial out_ready = `true;
initial in_valid = `false;
always @(posedge clk) begin
if(collatz_out_valid) begin
out_reg <= b[14:0];
end
else if(collatz_in_ready) begin
if(in[15]) begin
div <= div + 1;
if(div[26:12] == in[14:0]) begin
a <= a + 1;
div <= 0;
`set(in_valid);
end
end
else if(a != a_in) begin
a <= a_in;
`set(in_valid);
end
end
if(in_valid) begin
`reset(in_valid);
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:25:12 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire operation_reg_0_, NaN_reg, ready_add_subt, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_fmtted_Result_31_, FPSENCOS_enab_d_ff4_Xn,
FPSENCOS_enab_d_ff4_Yn, FPSENCOS_d_ff3_sign_out,
FPSENCOS_d_ff1_operation_out, FPSENCOS_enab_d_ff5_data_out,
FPSENCOS_enab_RB3, FPSENCOS_enab_d_ff_RB1, FPSENCOS_enab_d_ff4_Zn,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_barrel_shifter_load, FPMULT_FSM_final_result_load,
FPMULT_FSM_adder_round_norm_load, FPMULT_FSM_load_second_step,
FPMULT_FSM_exp_operation_load_result, FPMULT_FSM_first_phase_load,
FPADDSUB_N60, FPADDSUB_N59, FPADDSUB_OP_FLAG_SFG,
FPADDSUB_SIGN_FLAG_SFG, FPADDSUB__19_net_, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2, FPADDSUB__6_net_,
FPADDSUB_OP_FLAG_SHT1, FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP,
FPADDSUB_SIGN_FLAG_EXP, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPADDSUB_enable_Pipeline_input,
FPSENCOS_ITER_CONT_net8022904, FPSENCOS_ITER_CONT_N5,
FPSENCOS_ITER_CONT_N4, FPSENCOS_ITER_CONT_N3,
FPMULT_FS_Module_net8022850, FPMULT_Exp_module_Overflow_flag_A,
FPMULT_Exp_module_Overflow_A,
FPMULT_final_result_ieee_Module_Sign_S_mux,
FPADDSUB_inst_ShiftRegister_net8022742,
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652,
FPSENCOS_d_ff5_data_out_net8022868,
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580,
FPADDSUB_SGF_STAGE_DMP_net8022634,
FPADDSUB_NRM_STAGE_Raw_mant_net8022616, FPSENCOS_reg_Z0_net8022868,
FPSENCOS_reg_val_muxZ_2stage_net8022868,
FPSENCOS_reg_shift_y_net8022868, FPSENCOS_d_ff4_Xn_net8022868,
FPSENCOS_d_ff4_Yn_net8022868, FPSENCOS_d_ff4_Zn_net8022868,
FPADDSUB_INPUT_STAGE_OPERANDY_net8022580,
FPADDSUB_EXP_STAGE_DMP_net8022634, FPADDSUB_SHT1_STAGE_DMP_net8022634,
FPADDSUB_SHT2_STAGE_DMP_net8022634,
FPADDSUB_SHT2_SHIFT_DATA_net8022616,
FPMULT_Exp_module_exp_result_m_net8022814,
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796,
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778,
FPMULT_Adder_M_Add_Subt_Result_net8022760,
FPMULT_Operands_load_reg_XMRegister_net8022832,
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580, n30,
n106, n107, n810, n813, n816, n819, n824, n829, n830, n834, n842,
n843, n844, n846, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n859, n860, n861, n862, n863, n864, n865, n874, n875,
DP_OP_26J307_123_9022_n18, DP_OP_26J307_123_9022_n17,
DP_OP_26J307_123_9022_n16, DP_OP_26J307_123_9022_n15,
DP_OP_26J307_123_9022_n14, DP_OP_26J307_123_9022_n8,
DP_OP_26J307_123_9022_n7, DP_OP_26J307_123_9022_n6,
DP_OP_26J307_123_9022_n5, DP_OP_26J307_123_9022_n4,
DP_OP_26J307_123_9022_n3, DP_OP_26J307_123_9022_n2,
DP_OP_26J307_123_9022_n1, DP_OP_234J307_126_8543_n22,
DP_OP_234J307_126_8543_n21, DP_OP_234J307_126_8543_n20,
DP_OP_234J307_126_8543_n19, DP_OP_234J307_126_8543_n18,
DP_OP_234J307_126_8543_n17, DP_OP_234J307_126_8543_n16,
DP_OP_234J307_126_8543_n15, DP_OP_234J307_126_8543_n9,
DP_OP_234J307_126_8543_n8, DP_OP_234J307_126_8543_n7,
DP_OP_234J307_126_8543_n6, DP_OP_234J307_126_8543_n5,
DP_OP_234J307_126_8543_n4, DP_OP_234J307_126_8543_n3,
DP_OP_234J307_126_8543_n2, DP_OP_234J307_126_8543_n1, intadd_1033_CI,
intadd_1033_n3, intadd_1033_n2, intadd_1033_n1, intadd_1034_CI,
intadd_1034_n3, intadd_1034_n2, intadd_1034_n1, intadd_1035_CI,
intadd_1035_SUM_2_, intadd_1035_SUM_1_, intadd_1035_SUM_0_,
intadd_1035_n3, intadd_1035_n2, intadd_1035_n1, add_x_69_n161,
add_x_69_n150, add_x_69_n141, add_x_69_n134, add_x_69_n122,
add_x_69_n113, add_x_69_n106, add_x_69_n97, add_x_69_n96,
add_x_69_n91, add_x_69_n90, add_x_69_n83, add_x_69_n82, add_x_69_n77,
add_x_69_n67, add_x_69_n66, add_x_69_n61, add_x_69_n53, add_x_69_n52,
add_x_69_n47, add_x_69_n37, add_x_69_n31, add_x_69_n12, add_x_69_n10,
add_x_69_n9, add_x_69_n8, add_x_69_n7, add_x_69_n6, add_x_69_n5,
add_x_69_n4, n910, n911, n912, n913, n914, n915, n916, n917, n920,
n921, n922, n928, n929, n930, n931, n932, n933, n935, n936, n937,
n938, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999,
n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009,
n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019,
n1020, n1021, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1118, n1119, n1120, n1121, n1122, n1123,
n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133,
n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143,
n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153,
n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163,
n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173,
n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183,
n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193,
n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203,
n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213,
n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223,
n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233,
n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243,
n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253,
n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263,
n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273,
n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283,
n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293,
n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303,
n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313,
n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323,
n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333,
n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343,
n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353,
n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363,
n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373,
n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383,
n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393,
n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403,
n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413,
n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423,
n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433,
n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443,
n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453,
n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463,
n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473,
n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483,
n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493,
n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503,
n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513,
n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523,
n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533,
n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543,
n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553,
n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563,
n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573,
n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583,
n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593,
n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603,
n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613,
n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623,
n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633,
n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643,
n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653,
n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663,
n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673,
n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683,
n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693,
n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703,
n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713,
n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723,
n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733,
n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743,
n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753,
n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763,
n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773,
n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783,
n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793,
n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803,
n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813,
n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823,
n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833,
n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843,
n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853,
n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863,
n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873,
n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883,
n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893,
n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903,
n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913,
n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923,
n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933,
n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943,
n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953,
n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963,
n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973,
n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983,
n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993,
n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003,
n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013,
n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023,
n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033,
n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043,
n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053,
n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063,
n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073,
n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083,
n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093,
n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103,
n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113,
n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123,
n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133,
n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143,
n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153,
n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163,
n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173,
n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183,
n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193,
n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203,
n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213,
n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223,
n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233,
n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243,
n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253,
n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263,
n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273,
n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283,
n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293,
n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303,
n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313,
n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323,
n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333,
n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343,
n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353,
n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363,
n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373,
n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433,
n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443,
n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453,
n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463,
n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473,
n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513,
n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523,
n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533,
n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543,
n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583,
n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593,
n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603,
n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613,
n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623,
n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633,
n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643,
n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653,
n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663,
n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673,
n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683,
n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693,
n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703,
n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713,
n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723,
n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733,
n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743,
n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753,
n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763,
n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773,
n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783,
n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793,
n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803,
n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813,
n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823,
n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833,
n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843,
n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853,
n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863,
n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873,
n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883,
n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893,
n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903,
n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913,
n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923,
n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933,
n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943,
n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953,
n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963,
n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993,
n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003,
n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013,
n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023,
n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033,
n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043,
n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053,
n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063,
n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073,
n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083,
n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093,
n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103,
n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113,
n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123,
n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253,
n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263,
n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273,
n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283,
n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293,
n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303,
n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313,
n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323,
n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333,
n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343,
n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353,
n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363,
n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373,
n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383,
n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393,
n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403,
n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413,
n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423,
n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433,
n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443,
n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453,
n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463,
n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473,
n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483,
n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493,
n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503,
n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513,
n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523,
n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533,
n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543,
n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553,
n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563,
n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573,
n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583,
n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593,
n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603,
n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613,
n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623,
n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633,
n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643,
n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653,
n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663,
n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673,
n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683,
n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693,
n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703,
n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713,
n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723,
n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733,
n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743,
n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753,
n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763,
n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773,
n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783,
n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793,
n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803,
n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813,
n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823,
n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833,
n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843,
n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853,
n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863,
n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873,
n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883,
n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893,
n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903,
n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913,
n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923,
n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933,
n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943,
n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953,
n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963,
n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973,
n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983,
n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993,
n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003,
n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013,
n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023,
n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033,
n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043,
n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053,
n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063,
n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073,
n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083,
n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093,
n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103,
n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113,
n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123,
n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133,
n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143,
n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153,
n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163,
n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173,
n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183,
n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193,
n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203,
n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213,
n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223,
n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233,
n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243,
n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253,
n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263,
n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273,
n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283,
n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293,
n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303,
n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313,
n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323,
n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333,
n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343,
n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353,
n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363,
n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373,
n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383,
n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393,
n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403,
n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413,
n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423,
n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433,
n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443,
n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453,
n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463,
n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473,
n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483,
n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493,
n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503,
n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513,
n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523,
n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533,
n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543,
n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553,
n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563,
n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573,
n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583,
n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593,
n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603,
n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613,
n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623,
n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633,
n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643,
n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653,
n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663,
n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673,
n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683,
n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693,
n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703,
n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713,
n4714, n4715, n4716, n4717, n4719, n4720, n4721, n4722, n4723, n4724,
n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734,
n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744,
n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754,
n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764,
n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774,
n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784,
n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794,
n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804,
n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814,
n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824,
n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834,
n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844,
n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854,
n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864,
n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874,
n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884,
n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894,
n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904,
n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914,
n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924,
n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934,
n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944,
n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954,
n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964,
n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974,
n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984,
n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994,
n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004,
n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014,
n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024,
n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034,
n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044,
n5045, n5046, n5047, n5048, n5049, n5051, n5052, n5053, n5054, n5055,
n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065,
n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075,
n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085,
n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095,
n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5105, n5106,
n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115, n5116,
n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125, n5126,
n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135, n5136,
n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145, n5146,
n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155, n5156,
n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165, n5166,
n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175, n5176,
n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185, n5186,
n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195, n5196,
n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205, n5206,
n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215, n5216,
n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225, n5226,
n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235, n5236,
n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245, n5246,
n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255, n5256,
n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265, n5266,
n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275, n5276,
n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285, n5286,
n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295, n5296,
n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305, n5306,
n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315, n5316,
n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325, n5326,
n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335, n5336,
n5337, n5338, n5339, n5341, n5342, n5344, n5345, n5346, n5347, n5348,
n5349, n5350, n5351, n5352, n5353, n5354, n5355, n5356, n5357, n5358,
n5359, n5360, n5361, n5362, n5363, n5364, n5365, n5366, n5367, n5368,
n5369;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] add_subt_data1;
wire [30:0] add_subt_data2;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [30:0] FPSENCOS_mux_sal;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [25:4] FPSENCOS_data_out_LUT;
wire [7:0] FPSENCOS_sh_exp_y;
wire [7:0] FPSENCOS_sh_exp_x;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_first_mux_Z;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_first_mux_Y;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_first_mux_X;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [20:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [30:0] FPMULT_Op_MY;
wire [30:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [25:23] FPMULT_P_Sgf;
wire [31:0] FPADDSUB_formatted_number_W;
wire [25:1] FPADDSUB_Raw_mant_SGF;
wire [25:2] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [25:0] FPADDSUB_sftr_odat_SHT2_SWR;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [49:0] FPADDSUB_Data_array_SWR;
wire [24:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:2] FPADDSUB_shft_value_mux_o_EWR;
wire [4:0] FPADDSUB_LZD_raw_out_EWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [4:0] FPADDSUB_Shift_amount_EXP_EW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [27:0] FPADDSUB_DmP_INIT_EWSW;
wire [30:0] FPADDSUB_DMP_INIT_EWSW;
wire [30:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_next;
wire [3:1] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [30:23] FPMULT_Sgf_operation_Result;
wire [24:1] FPMULT_Adder_M_result_A_adder;
wire [22:0] FPMULT_final_result_ieee_Module_Sgf_S_mux;
wire [7:0] FPMULT_final_result_ieee_Module_Exp_S_mux;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 FPSENCOS_ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(n5281), .ENCLK(FPSENCOS_ITER_CONT_net8022904), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function FPMULT_FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n846), .ENCLK(FPMULT_FS_Module_net8022850), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 FPADDSUB_inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n875), .ENCLK(FPADDSUB_inst_ShiftRegister_net8022742),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 FPADDSUB_SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[1]), .ENCLK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 FPSENCOS_d_ff5_data_out_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff5_data_out), .ENCLK(
FPSENCOS_d_ff5_data_out_net8022868), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 FPADDSUB_FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[0]), .ENCLK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 FPADDSUB_SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__19_net_), .ENCLK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 FPADDSUB_NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[2]), .ENCLK(
FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 FPSENCOS_reg_Z0_clk_gate_Q_reg ( .CLK(
clk), .EN(FPSENCOS_enab_d_ff_RB1), .ENCLK(FPSENCOS_reg_Z0_net8022868),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 FPSENCOS_reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
FPSENCOS_reg_val_muxZ_2stage_net8022868), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 FPSENCOS_reg_shift_y_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_RB3), .ENCLK(
FPSENCOS_reg_shift_y_net8022868), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 FPSENCOS_d_ff4_Xn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Xn), .ENCLK(
FPSENCOS_d_ff4_Xn_net8022868), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 FPSENCOS_d_ff4_Yn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Yn), .ENCLK(
FPSENCOS_d_ff4_Yn_net8022868), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 FPSENCOS_d_ff4_Zn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Zn), .ENCLK(
FPSENCOS_d_ff4_Zn_net8022868), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 FPADDSUB_INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_enable_Pipeline_input), .ENCLK(
FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 FPADDSUB_EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_6), .ENCLK(
FPADDSUB_EXP_STAGE_DMP_net8022634), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 FPADDSUB_SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_5), .ENCLK(
FPADDSUB_SHT1_STAGE_DMP_net8022634), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 FPADDSUB_SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 FPADDSUB_SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__6_net_), .ENCLK(
FPADDSUB_SHT2_SHIFT_DATA_net8022616), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 FPMULT_Exp_module_exp_result_m_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_exp_operation_load_result), .ENCLK(
FPMULT_Exp_module_exp_result_m_net8022814), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 FPMULT_Sgf_operation_EVEN1_finalreg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_load_second_step), .ENCLK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 FPMULT_Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_barrel_shifter_load), .ENCLK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 FPMULT_Adder_M_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_adder_round_norm_load), .ENCLK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 FPMULT_Operands_load_reg_XMRegister_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_first_phase_load), .ENCLK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 FPMULT_final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_final_result_load), .ENCLK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .TE(
1'b0) );
DFFRXLTS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n5322),
.QN(n1104) );
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n5327), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n824), .QN(
n1093) );
DFFRXLTS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n824), .QN(
n1094) );
DFFRXLTS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n824), .QN(
n1046) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n5327), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n5316), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n5316), .Q(
dataB[31]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n5345), .CK(
FPADDSUB_inst_ShiftRegister_net8022742), .RN(n5225), .Q(
FPADDSUB_Shift_reg_FLAGS_7_6) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_6), .CK(
FPADDSUB_inst_ShiftRegister_net8022742), .RN(n5225), .Q(
FPADDSUB_Shift_reg_FLAGS_7_5) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
FPADDSUB_inst_ShiftRegister_net8022742), .RN(n5225), .Q(
FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[3]), .CK(
FPADDSUB_inst_ShiftRegister_net8022742), .RN(n5225), .Q(
FPADDSUB_Shift_reg_FLAGS_7[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[4]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5226), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[3]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5226), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[2]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5226), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[1]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5226), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[0]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5226), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(region_flag[0]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5314), .Q(
FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n1692) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n852), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5314), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n862), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5314), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n856), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5314), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n864), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5314), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(FPSENCOS_data_out_LUT[4]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5314), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n853), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5313), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n855), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5313), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n859), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5313), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n5096), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5313), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n861), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5313), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n854), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5313), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n860), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5313), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n851), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5313), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n863), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5313), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n865), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5313), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n850), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5312), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n849), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5312), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n848), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5312), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(FPSENCOS_data_out_LUT[25]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5312), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n857), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5312), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5312), .Q(FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5312), .Q(FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5312), .Q(FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5312), .Q(FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5311), .Q(FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5311), .Q(FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5311), .Q(FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5311), .Q(FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5311), .Q(FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5311), .Q(FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(Data_1[10]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5311), .Q(FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(Data_1[11]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5311), .Q(FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(Data_1[12]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5311), .Q(FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(Data_1[13]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5311), .Q(FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(Data_1[14]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5300), .Q(FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(Data_1[15]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5310), .Q(FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(Data_1[16]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5300), .Q(FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(Data_1[17]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5321), .Q(FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(Data_1[18]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5310), .Q(FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(Data_1[19]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5300), .Q(FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(Data_1[20]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5321), .Q(FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(Data_1[21]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5310), .Q(FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(Data_1[22]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5300), .Q(FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(Data_1[23]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5321), .Q(FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(Data_1[24]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5309), .Q(FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(Data_1[25]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5309), .Q(FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(Data_1[26]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5309), .Q(FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(Data_1[27]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5309), .Q(FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(Data_1[28]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5309), .Q(FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(Data_1[29]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5309), .Q(FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(Data_1[30]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5309), .Q(FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(Data_1[31]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5309), .Q(FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(FPSENCOS_sh_exp_x[0]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5309), .Q(
FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(FPSENCOS_sh_exp_x[1]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5309), .Q(
FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(FPSENCOS_sh_exp_x[2]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5308), .Q(
FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(FPSENCOS_sh_exp_x[3]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5308), .Q(
FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(FPSENCOS_sh_exp_x[4]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5308), .Q(
FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(FPSENCOS_sh_exp_x[5]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5308), .Q(
FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(FPSENCOS_sh_exp_x[6]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5308), .Q(
FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(FPSENCOS_sh_exp_x[7]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5308), .Q(
FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(FPSENCOS_sh_exp_y[0]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5308), .Q(
FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(FPSENCOS_sh_exp_y[1]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5308), .Q(
FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(FPSENCOS_sh_exp_y[2]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5308), .Q(
FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(FPSENCOS_sh_exp_y[3]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5308), .Q(
FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(FPSENCOS_sh_exp_y[4]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5321), .Q(
FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(FPSENCOS_sh_exp_y[5]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5323), .Q(
FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(FPSENCOS_sh_exp_y[6]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5323), .Q(
FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(FPSENCOS_sh_exp_y[7]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5326), .Q(
FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5326), .Q(FPSENCOS_d_ff_Xn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_X[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5326), .Q(FPSENCOS_d_ff2_X[23]), .QN(n5143) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5323), .Q(FPSENCOS_d_ff_Xn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n824), .Q(FPSENCOS_d_ff_Xn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5307), .Q(FPSENCOS_d_ff_Xn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5307), .Q(FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5307), .Q(FPSENCOS_d_ff_Xn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5307), .Q(FPSENCOS_d_ff_Xn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5307), .Q(FPSENCOS_d_ff_Xn[30]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5306), .Q(FPSENCOS_d_ff_Yn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Y[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5306), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n5142) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(FPSENCOS_mux_sal[23]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5306), .Q(cordic_result[23])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5306), .Q(FPSENCOS_d_ff_Yn[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(FPSENCOS_mux_sal[24]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5306), .Q(cordic_result[24])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5306), .Q(FPSENCOS_d_ff_Yn[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(FPSENCOS_mux_sal[25]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5306), .Q(cordic_result[25])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5306), .Q(FPSENCOS_d_ff_Yn[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(FPSENCOS_mux_sal[26]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5305), .Q(cordic_result[26])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5305), .Q(FPSENCOS_d_ff_Yn[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(FPSENCOS_mux_sal[27]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5305), .Q(cordic_result[27])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5305), .Q(FPSENCOS_d_ff_Yn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Y[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5305), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n5205) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(FPSENCOS_mux_sal[28]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5305), .Q(cordic_result[28])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5305), .Q(FPSENCOS_d_ff_Yn[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(FPSENCOS_mux_sal[29]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5304), .Q(cordic_result[29])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5304), .Q(FPSENCOS_d_ff_Yn[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(FPSENCOS_mux_sal[30]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5304), .Q(cordic_result[30])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5304), .Q(FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Z[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5304), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5304), .Q(FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Z[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5304), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5304), .Q(FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Z[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5304), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5303), .Q(FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Z[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5303), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5303), .Q(FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Z[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5303), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5303), .Q(FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Z[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5303), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5303), .Q(FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Z[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5303), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5303), .Q(FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Z[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5303), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(FPADDSUB_DmP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5227), .Q(
FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(FPADDSUB_DmP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5227), .Q(
FPADDSUB_DmP_EXP_EWSW[24]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(FPADDSUB_DmP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5227), .Q(
FPADDSUB_DmP_EXP_EWSW[25]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(FPADDSUB_DmP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5228), .Q(
FPADDSUB_DmP_EXP_EWSW[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(FPADDSUB_DmP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5228), .Q(
FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(add_subt_data2[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5228), .Q(
FPADDSUB_intDY_EWSW[29]), .QN(n5111) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(add_subt_data2[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5228), .Q(
FPADDSUB_intDY_EWSW[30]), .QN(n5158) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5228), .Q(
FPADDSUB_DMP_EXP_EWSW[23]), .QN(n5159) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5228), .Q(
FPADDSUB_DMP_EXP_EWSW[24]), .QN(n5177) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5228), .Q(
FPADDSUB_DMP_EXP_EWSW[25]), .QN(n5202) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5228), .Q(
FPADDSUB_DMP_EXP_EWSW[26]), .QN(n5201) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5229), .Q(
FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_INIT_EWSW[28]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5229), .Q(
FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_INIT_EWSW[29]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5229), .Q(
FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_INIT_EWSW[30]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5229), .Q(
FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_EXP_EWSW[23]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5229), .Q(
FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_EXP_EWSW[24]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5229), .Q(
FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_EXP_EWSW[25]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5229), .Q(
FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_EXP_EWSW[26]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5229), .Q(
FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_EXP_EWSW[27]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5229), .Q(
FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_EXP_EWSW[28]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5229), .Q(
FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_EXP_EWSW[29]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5230), .Q(
FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_EXP_EWSW[30]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5230), .Q(
FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT1_EWSW[23]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5230), .Q(
FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT2_EWSW[23]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5247), .Q(
FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(FPADDSUB_DMP_SFG[23]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5247), .Q(
FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5247), .Q(
FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT1_EWSW[24]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5230), .Q(
FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT2_EWSW[24]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5247), .Q(
FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(FPADDSUB_DMP_SFG[24]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5247), .Q(
FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5247), .Q(
FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT1_EWSW[25]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5230), .Q(
FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT2_EWSW[25]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5248), .Q(
FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(FPADDSUB_DMP_SFG[25]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5248), .Q(
FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5247), .Q(
FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT1_EWSW[26]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5230), .Q(
FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT2_EWSW[26]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5248), .Q(
FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(FPADDSUB_DMP_SFG[26]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5248), .Q(
FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5248), .Q(
FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT1_EWSW[27]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5230), .Q(
FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT2_EWSW[27]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5248), .Q(
FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(FPADDSUB_DMP_SFG[27]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5248), .Q(
FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5248), .Q(
FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT1_EWSW[28]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5230), .Q(
FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT2_EWSW[28]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5249), .Q(
FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(FPADDSUB_DMP_SFG[28]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5248), .Q(
FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[5]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5248), .Q(
FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT1_EWSW[29]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5230), .Q(
FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT2_EWSW[29]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5249), .Q(
FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(FPADDSUB_DMP_SFG[29]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5249), .Q(
FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[6]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5249), .Q(
FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT1_EWSW[30]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5230), .Q(
FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT2_EWSW[30]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5249), .Q(
FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(FPADDSUB_DMP_SFG[30]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5249), .Q(
FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[7]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5249), .Q(
FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(
FPADDSUB_formatted_number_W[22]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5231), .Q(
result_add_subt[22]), .QN(n1230) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n1231), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5302), .Q(FPSENCOS_d_ff_Xn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_X[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5302), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(FPSENCOS_d_ff2_X[22]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5302), .Q(
FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n1231), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5302), .Q(FPSENCOS_d_ff_Yn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Y[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5302), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(FPSENCOS_d_ff2_Y[22]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5302), .Q(
FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(FPSENCOS_mux_sal[22]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5302), .Q(cordic_result[22])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5302), .Q(FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Z[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5302), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(FPADDSUB_DmP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5231), .Q(
FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_DmP_EXP_EWSW[22]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5251), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(
FPADDSUB_formatted_number_W[19]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5231), .Q(
result_add_subt[19]), .QN(n1232) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n1233), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5302), .Q(FPSENCOS_d_ff_Xn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_X[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5301), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(FPSENCOS_d_ff2_X[19]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5301), .Q(
FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n1233), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5301), .Q(FPSENCOS_d_ff_Yn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Y[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5301), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(FPSENCOS_d_ff2_Y[19]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5301), .Q(
FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(FPSENCOS_mux_sal[19]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5301), .Q(cordic_result[19])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5301), .Q(FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Z[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5301), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(FPADDSUB_DmP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5231), .Q(
FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_DmP_EXP_EWSW[19]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5250), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(FPADDSUB_Data_array_SWR[2]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5231), .Q(
FPADDSUB_Data_array_SWR[28]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(
FPADDSUB_formatted_number_W[21]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5231), .Q(
result_add_subt[21]), .QN(n1234) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n1235), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5301), .Q(FPSENCOS_d_ff_Xn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_X[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5301), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(FPSENCOS_d_ff2_X[21]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5317), .Q(
FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n1235), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5321), .Q(FPSENCOS_d_ff_Yn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Y[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5321), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(FPSENCOS_d_ff2_Y[21]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5300), .Q(
FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(FPSENCOS_mux_sal[21]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5310), .Q(cordic_result[21])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5310), .Q(FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Z[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5300), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(FPADDSUB_DmP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5232), .Q(
FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_DmP_EXP_EWSW[21]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5250), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(
FPADDSUB_formatted_number_W[2]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5232), .Q(
result_add_subt[2]), .QN(n1236) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n1237), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5310), .Q(FPSENCOS_d_ff_Xn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_X[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5300), .Q(
FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(FPSENCOS_d_ff2_X[2]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5310), .Q(
FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n1237), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5299), .Q(FPSENCOS_d_ff_Yn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Y[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5299), .Q(
FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(FPSENCOS_d_ff2_Y[2]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5299), .Q(
FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(FPSENCOS_mux_sal[2]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5299), .Q(cordic_result[2])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5299), .Q(FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Z[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5299), .Q(
FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(FPADDSUB_DmP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5232), .Q(
FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(FPADDSUB_DmP_EXP_EWSW[2]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5249), .Q(
FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(
FPADDSUB_formatted_number_W[16]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5232), .Q(
result_add_subt[16]), .QN(n1238) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n1239), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5299), .Q(FPSENCOS_d_ff_Xn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_X[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5299), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(FPSENCOS_d_ff2_X[16]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5299), .Q(
FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n1239), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5299), .Q(FPSENCOS_d_ff_Yn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Y[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5298), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(FPSENCOS_d_ff2_Y[16]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5298), .Q(
FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(FPSENCOS_mux_sal[16]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5298), .Q(cordic_result[16])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5298), .Q(FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Z[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5298), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(FPADDSUB_DmP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5233), .Q(
FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_DmP_EXP_EWSW[16]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5255), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(
FPADDSUB_formatted_number_W[18]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5257), .Q(
result_add_subt[18]), .QN(n1240) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n1241), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5298), .Q(FPSENCOS_d_ff_Xn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_X[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5298), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(FPSENCOS_d_ff2_X[18]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5298), .Q(
FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n1241), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5298), .Q(FPSENCOS_d_ff_Yn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Y[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5298), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(FPSENCOS_d_ff2_Y[18]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5297), .Q(
FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(FPSENCOS_mux_sal[18]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5297), .Q(cordic_result[18])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5297), .Q(FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Z[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5297), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(FPADDSUB_DmP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5254), .Q(
FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_DmP_EXP_EWSW[18]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5250), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(FPADDSUB_Data_array_SWR[3]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5259), .Q(
FPADDSUB_Data_array_SWR[29]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(
FPADDSUB_formatted_number_W[20]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5235), .Q(
result_add_subt[20]), .QN(n1242) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n1243), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5297), .Q(FPSENCOS_d_ff_Xn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_X[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5297), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(FPSENCOS_d_ff2_X[20]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5297), .Q(
FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n1243), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5297), .Q(FPSENCOS_d_ff_Yn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Y[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5297), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(FPSENCOS_d_ff2_Y[20]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5297), .Q(
FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(FPSENCOS_mux_sal[20]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5320), .Q(cordic_result[20])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5320), .Q(FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Z[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5324), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(FPADDSUB_DmP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5234), .Q(
FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_DmP_EXP_EWSW[20]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5250), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(
FPADDSUB_formatted_number_W[17]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5234), .Q(
result_add_subt[17]), .QN(n1244) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n1245), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5324), .Q(FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_X[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n1132), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(FPSENCOS_d_ff2_X[17]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n1132), .Q(
FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n1245), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5320), .Q(FPSENCOS_d_ff_Yn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Y[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5320), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(FPSENCOS_d_ff2_Y[17]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5320), .Q(
FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(FPSENCOS_mux_sal[17]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5320), .Q(cordic_result[17])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5296), .Q(FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Z[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5296), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(FPADDSUB_DmP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5234), .Q(
FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_DmP_EXP_EWSW[17]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5250), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(
FPADDSUB_formatted_number_W[4]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5234), .Q(
result_add_subt[4]), .QN(n1246) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n1247), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5296), .Q(FPSENCOS_d_ff_Xn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_X[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5296), .Q(
FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(FPSENCOS_d_ff2_X[4]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5296), .Q(
FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n1247), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5296), .Q(FPSENCOS_d_ff_Yn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Y[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5296), .Q(
FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(FPSENCOS_d_ff2_Y[4]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5296), .Q(
FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(FPSENCOS_mux_sal[4]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5296), .Q(cordic_result[4])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5296), .Q(FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Z[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5295), .Q(
FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(FPADDSUB_DmP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5257), .Q(
FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(FPADDSUB_DmP_EXP_EWSW[4]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5250), .Q(
FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(
FPADDSUB_formatted_number_W[15]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5258), .Q(
result_add_subt[15]), .QN(n1248) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n1249), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5295), .Q(FPSENCOS_d_ff_Xn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_X[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5295), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(FPSENCOS_d_ff2_X[15]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5295), .Q(
FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n1249), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5295), .Q(FPSENCOS_d_ff_Yn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Y[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5295), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(FPSENCOS_d_ff2_Y[15]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5295), .Q(
FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(FPSENCOS_mux_sal[15]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5295), .Q(cordic_result[15])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5295), .Q(FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Z[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5295), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(FPADDSUB_DmP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5235), .Q(
FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_DmP_EXP_EWSW[15]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5250), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(
FPADDSUB_formatted_number_W[5]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5239), .Q(
result_add_subt[5]), .QN(n1250) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n1251), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5317), .Q(FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_X[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5317), .Q(
FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(FPSENCOS_d_ff2_X[5]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5317), .Q(
FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n1251), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5317), .Q(FPSENCOS_d_ff_Yn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Y[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5317), .Q(
FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(FPSENCOS_d_ff2_Y[5]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n1132), .Q(
FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(FPSENCOS_mux_sal[5]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5317), .Q(cordic_result[5])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n1132), .Q(FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Z[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n1133), .Q(
FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(add_subt_data1[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5256), .Q(
FPADDSUB_intDX_EWSW[5]), .QN(n5109) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(FPADDSUB_DmP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5259), .Q(
FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(FPADDSUB_DmP_EXP_EWSW[5]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5250), .Q(
FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(FPADDSUB_Data_array_SWR[15]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5236), .QN(n1113) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(
FPADDSUB_formatted_number_W[13]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5236), .Q(
result_add_subt[13]), .QN(n1252) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n1253), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5322), .Q(FPSENCOS_d_ff_Xn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_X[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5294), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(FPSENCOS_d_ff2_X[13]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5294), .Q(
FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n1253), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5294), .Q(FPSENCOS_d_ff_Yn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Y[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5294), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(FPSENCOS_d_ff2_Y[13]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5294), .Q(
FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(FPSENCOS_mux_sal[13]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5294), .Q(cordic_result[13])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5294), .Q(FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Z[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5294), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(FPADDSUB_DmP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5236), .Q(
FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_DmP_EXP_EWSW[13]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5236), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(
FPADDSUB_formatted_number_W[14]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5236), .Q(
result_add_subt[14]), .QN(n1254) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n1255), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5294), .Q(FPSENCOS_d_ff_Xn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_X[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5294), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(FPSENCOS_d_ff2_X[14]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5293), .Q(
FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n1255), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5293), .Q(FPSENCOS_d_ff_Yn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Y[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5293), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(FPSENCOS_d_ff2_Y[14]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5293), .Q(
FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(FPSENCOS_mux_sal[14]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5293), .Q(cordic_result[14])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5293), .Q(FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Z[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5293), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(FPADDSUB_DmP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5237), .Q(
FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_DmP_EXP_EWSW[14]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5237), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(
FPADDSUB_formatted_number_W[11]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5237), .Q(
result_add_subt[11]), .QN(n1256) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n1257), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5293), .Q(FPSENCOS_d_ff_Xn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_X[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5293), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(FPSENCOS_d_ff2_X[11]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5293), .Q(
FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n1257), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5317), .Q(FPSENCOS_d_ff_Yn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Y[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n1132), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(FPSENCOS_d_ff2_Y[11]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n929), .Q(
FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(FPSENCOS_mux_sal[11]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n1133), .Q(cordic_result[11])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n1229), .Q(FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Z[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5322), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(FPADDSUB_DmP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5237), .Q(
FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_DmP_EXP_EWSW[11]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5237), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(
FPADDSUB_formatted_number_W[8]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5237), .Q(
result_add_subt[8]), .QN(n1258) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n1259), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5321), .Q(FPSENCOS_d_ff_Xn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_X[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5317), .Q(
FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(FPSENCOS_d_ff2_X[8]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n930), .Q(
FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n1259), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n1228), .Q(FPSENCOS_d_ff_Yn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Y[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5292), .Q(
FPSENCOS_d_ff2_Y[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(FPSENCOS_d_ff2_Y[8]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5292), .Q(
FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(FPSENCOS_mux_sal[8]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5292), .Q(cordic_result[8])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5292), .Q(FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Z[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5292), .Q(
FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(FPADDSUB_DmP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5238), .Q(
FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(FPADDSUB_DmP_EXP_EWSW[8]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5238), .Q(
FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(
FPADDSUB_formatted_number_W[10]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5238), .Q(
result_add_subt[10]), .QN(n1260) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n1261), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5292), .Q(FPSENCOS_d_ff_Xn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_X[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5292), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(FPSENCOS_d_ff2_X[10]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5292), .Q(
FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n1261), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5292), .Q(FPSENCOS_d_ff_Yn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Y[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5292), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(FPSENCOS_d_ff2_Y[10]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5291), .Q(
FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(FPSENCOS_mux_sal[10]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5291), .Q(cordic_result[10])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5291), .Q(FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Z[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5291), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(FPADDSUB_DmP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5238), .Q(
FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_DmP_EXP_EWSW[10]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5238), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(
FPADDSUB_formatted_number_W[12]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5255), .Q(
result_add_subt[12]), .QN(n1262) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n1263), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5291), .Q(FPSENCOS_d_ff_Xn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_X[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5291), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(FPSENCOS_d_ff2_X[12]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5291), .Q(
FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n1263), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5291), .Q(FPSENCOS_d_ff_Yn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Y[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5291), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(FPSENCOS_d_ff2_Y[12]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5291), .Q(
FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(FPSENCOS_mux_sal[12]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5290), .Q(cordic_result[12])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5290), .Q(FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Z[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5290), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(FPADDSUB_DmP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5258), .Q(
FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_DmP_EXP_EWSW[12]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634),
.RN(n5254), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(
FPADDSUB_formatted_number_W[9]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5233), .Q(
result_add_subt[9]), .QN(n1264) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n1265), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5290), .Q(FPSENCOS_d_ff_Xn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_X[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5290), .Q(
FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(FPSENCOS_d_ff2_X[9]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5290), .Q(
FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n1265), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5290), .Q(FPSENCOS_d_ff_Yn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Y[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5290), .Q(
FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(FPSENCOS_d_ff2_Y[9]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5290), .Q(
FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(FPSENCOS_mux_sal[9]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5290), .Q(cordic_result[9])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5289), .Q(FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Z[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5289), .Q(
FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5289), .Q(FPSENCOS_d_ff_Xn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_X[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5289), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(FPSENCOS_d_ff2_X[31]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5289), .Q(
FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5289), .Q(FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(FPSENCOS_fmtted_Result_31_),
.CK(FPSENCOS_d_ff5_data_out_net8022868), .RN(n5289), .Q(
cordic_result[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Y[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5289), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(FPSENCOS_d_ff2_Y[31]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5289), .Q(
FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5289), .Q(FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Z[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5288), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(add_subt_data1[31]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5240), .Q(
FPADDSUB_intDX_EWSW[31]) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Z[31]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5288), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(
FPADDSUB_Raw_mant_SGF[15]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n922), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(
FPADDSUB_Raw_mant_SGF[18]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n922), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
FPADDSUB_LZD_raw_out_EWR[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5247), .Q(
FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(
FPADDSUB_LZD_raw_out_EWR[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5246), .Q(
FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
FPADDSUB_LZD_raw_out_EWR[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5246), .Q(
FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(
FPADDSUB_LZD_raw_out_EWR[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5246), .Q(
FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
FPADDSUB_LZD_raw_out_EWR[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8022652), .RN(n5247), .Q(
FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(
FPADDSUB_formatted_number_W[0]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5240), .Q(
result_add_subt[0]), .QN(n1266) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n1267), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5288), .Q(FPSENCOS_d_ff_Xn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_X[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5288), .Q(
FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(FPSENCOS_d_ff2_X[0]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5288), .Q(
FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n1267), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5288), .Q(FPSENCOS_d_ff_Yn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Y[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5288), .Q(
FPSENCOS_d_ff2_Y[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Y[0]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5288), .Q(
FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(FPSENCOS_mux_sal[0]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5288), .Q(cordic_result[0])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5288), .Q(FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Z[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5319), .Q(
FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(FPADDSUB_DmP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5241), .Q(
FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(FPADDSUB_DmP_EXP_EWSW[0]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5249), .Q(
FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5257), .Q(
FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_EXP_EWSW[0]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5254), .Q(
FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT1_EWSW[0]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5255), .Q(
FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(
FPADDSUB_formatted_number_W[1]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5241), .Q(
result_add_subt[1]), .QN(n1268) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n1269), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5319), .Q(FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_X[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n930), .Q(
FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(FPSENCOS_d_ff2_X[1]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5325), .Q(
FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n1269), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5319), .Q(FPSENCOS_d_ff_Yn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Y[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n1132), .Q(
FPSENCOS_d_ff2_Y[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(FPSENCOS_d_ff2_Y[1]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n930), .Q(
FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(FPSENCOS_mux_sal[1]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5319), .Q(cordic_result[1])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n1132), .Q(FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Z[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n930), .Q(
FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(FPADDSUB_DmP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5241), .Q(
FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(FPADDSUB_DmP_EXP_EWSW[1]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5249), .Q(
FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5256), .Q(
FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_EXP_EWSW[1]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5259), .Q(
FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT1_EWSW[1]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5235), .Q(
FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(
FPADDSUB_formatted_number_W[3]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5241), .Q(
result_add_subt[3]), .QN(n1270) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n1271), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5287), .Q(FPSENCOS_d_ff_Xn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_X[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5287), .Q(
FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(FPSENCOS_d_ff2_X[3]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5287), .Q(
FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n1271), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5287), .Q(FPSENCOS_d_ff_Yn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Y[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5287), .Q(
FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(FPSENCOS_d_ff2_Y[3]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5287), .Q(
FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(FPSENCOS_mux_sal[3]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5287), .Q(cordic_result[3])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5287), .Q(FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Z[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5287), .Q(
FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(FPADDSUB_DmP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5241), .Q(
FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(FPADDSUB_DmP_EXP_EWSW[3]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5250), .Q(
FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5256), .Q(
FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_EXP_EWSW[3]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5259), .Q(
FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT1_EWSW[3]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5235), .Q(
FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(
FPADDSUB_formatted_number_W[6]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5241), .Q(
result_add_subt[6]), .QN(n1272) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n1273), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5287), .Q(FPSENCOS_d_ff_Xn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_X[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5286), .Q(
FPSENCOS_d_ff2_X[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(FPSENCOS_d_ff2_X[6]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5286), .Q(
FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n1273), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5286), .Q(FPSENCOS_d_ff_Yn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Y[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5286), .Q(
FPSENCOS_d_ff2_Y[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(FPSENCOS_d_ff2_Y[6]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5286), .Q(
FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(FPSENCOS_mux_sal[6]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n5286), .Q(cordic_result[6])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n5286), .Q(FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Z[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5286), .Q(
FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(FPADDSUB_DmP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5242), .Q(
FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(FPADDSUB_DmP_EXP_EWSW[6]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5250), .Q(
FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5260), .Q(
FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_EXP_EWSW[6]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5260), .Q(
FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT1_EWSW[6]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5260), .Q(
FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(
FPADDSUB_formatted_number_W[7]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5242), .Q(
result_add_subt[7]), .QN(n1274) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n1275), .CK(
FPSENCOS_d_ff4_Xn_net8022868), .RN(n5286), .Q(FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_X[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5286), .Q(
FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(FPSENCOS_d_ff2_X[7]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n916), .Q(
FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n1275), .CK(
FPSENCOS_d_ff4_Yn_net8022868), .RN(n5285), .Q(FPSENCOS_d_ff_Yn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Y[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n932), .Q(
FPSENCOS_d_ff2_Y[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(FPSENCOS_d_ff2_Y[7]), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n5284), .Q(
FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(FPSENCOS_mux_sal[7]), .CK(
FPSENCOS_d_ff5_data_out_net8022868), .RN(n917), .Q(cordic_result[7])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Zn_net8022868), .RN(n1229), .Q(FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Z[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n932), .Q(
FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(add_subt_data1[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5242), .Q(
FPADDSUB_intDX_EWSW[7]), .QN(n5108) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(FPADDSUB_DmP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5242), .Q(
FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(FPADDSUB_DmP_EXP_EWSW[7]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5242), .Q(
FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5261), .Q(
FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_EXP_EWSW[7]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5260), .Q(
FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT1_EWSW[7]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5260), .Q(
FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(FPADDSUB_DmP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5242), .Q(
FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(FPADDSUB_DmP_EXP_EWSW[9]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5242), .Q(
FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5243), .Q(
FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_EXP_EWSW[9]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5261), .Q(
FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT1_EWSW[9]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5261), .Q(
FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5243), .Q(
FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_EXP_EWSW[12]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5262), .Q(
FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT1_EWSW[12]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5262), .Q(
FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5243), .Q(
FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_EXP_EWSW[10]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5261), .Q(
FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT1_EWSW[10]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5261), .Q(
FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5243), .Q(
FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_EXP_EWSW[8]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5261), .Q(
FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT1_EWSW[8]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5261), .Q(
FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5243), .Q(
FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_EXP_EWSW[11]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5262), .Q(
FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT1_EWSW[11]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5262), .Q(
FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5243), .Q(
FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_EXP_EWSW[14]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5263), .Q(
FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT1_EWSW[14]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5263), .Q(
FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5243), .Q(
FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_EXP_EWSW[13]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5262), .Q(
FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT1_EWSW[13]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5262), .Q(
FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5260), .Q(
FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_EXP_EWSW[5]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5260), .Q(
FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT1_EWSW[5]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5260), .Q(
FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5243), .Q(
FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_EXP_EWSW[15]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5263), .Q(
FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT1_EWSW[15]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5263), .Q(
FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5233), .Q(
FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_EXP_EWSW[4]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5258), .Q(
FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT1_EWSW[4]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5239), .Q(
FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5243), .Q(
FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_EXP_EWSW[17]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5264), .Q(
FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT1_EWSW[17]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5263), .Q(
FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5244), .Q(
FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_EXP_EWSW[20]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5264), .Q(
FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT1_EWSW[20]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5264), .Q(
FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5244), .Q(
FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_EXP_EWSW[18]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5264), .Q(
FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT1_EWSW[18]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5264), .Q(
FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5244), .Q(
FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_EXP_EWSW[16]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5263), .Q(
FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT1_EWSW[16]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5263), .Q(
FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5257), .Q(
FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_EXP_EWSW[2]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5258), .Q(
FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT1_EWSW[2]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5239), .Q(
FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5244), .Q(
FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_EXP_EWSW[21]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n3959), .Q(
FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT1_EWSW[21]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n3963), .Q(
FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5244), .Q(
FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_EXP_EWSW[19]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5264), .Q(
FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT1_EWSW[19]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5264), .Q(
FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(FPADDSUB_Data_array_SWR[1]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5244), .Q(
FPADDSUB_Data_array_SWR[27]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(FPADDSUB_Data_array_SWR[0]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5244), .Q(
FPADDSUB_Data_array_SWR[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5244), .Q(
FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_EXP_EWSW[22]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5240), .Q(
FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT1_EWSW[22]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8022634), .RN(n5255), .Q(
FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n5137), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n937), .Q(
FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n5102) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n5135), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5259), .Q(
FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n5101) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n5134), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5235), .Q(
FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n5106) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n5133), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5257), .Q(
FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n5105) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[16]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5256), .Q(
FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n5132) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[17]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5254), .Q(
FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n5146) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[18]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5233), .Q(
FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n5147) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[19]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5255), .Q(
FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n5164) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[20]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5258), .Q(
FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n5166) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[21]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5239), .Q(
FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n5163) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[22]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5239), .Q(
FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n5175) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[23]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5256), .Q(
FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n5173) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[24]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5233), .Q(
FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n5174) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[25]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5258), .Q(
FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n5207) );
DFFRXLTS FPMULT_FS_Module_state_reg_reg_2_ ( .D(
FPMULT_FS_Module_state_next[2]), .CK(FPMULT_FS_Module_net8022850),
.RN(n5285), .Q(FPMULT_FS_Module_state_reg[2]), .QN(n1665) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(Data_2[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5267), .Q(
FPMULT_Op_MY[30]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(Data_2[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5282), .Q(
FPMULT_Op_MY[29]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(Data_2[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5278), .Q(
FPMULT_Op_MY[28]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(Data_2[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1140), .Q(
FPMULT_Op_MY[27]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(Data_2[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5277), .Q(
FPMULT_Op_MY[26]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(Data_2[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5278), .Q(
FPMULT_Op_MY[24]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(Data_2[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1140), .Q(
FPMULT_Op_MY[23]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(Data_2[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5278), .Q(
FPMULT_Op_MY[22]), .QN(n1689) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(Data_2[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5277), .Q(
FPMULT_Op_MY[21]), .QN(n5221) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(Data_2[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5279), .Q(
FPMULT_Op_MY[20]), .QN(n1655) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(Data_2[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5278), .Q(
FPMULT_Op_MY[19]), .QN(n5222) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(Data_2[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5277), .Q(
FPMULT_Op_MY[18]), .QN(n1669) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(Data_2[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5279), .Q(
FPMULT_Op_MY[17]), .QN(n5220) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(Data_2[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5278), .Q(
FPMULT_Op_MY[16]), .QN(n1673) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(Data_2[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1139), .Q(
FPMULT_Op_MY[15]), .QN(n5217) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(Data_2[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1139), .Q(
FPMULT_Op_MY[14]), .QN(n1072) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(Data_2[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5277), .Q(
FPMULT_Op_MY[13]), .QN(n1675) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(Data_2[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5279), .Q(
FPMULT_Op_MY[11]), .QN(n1216) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(Data_2[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5278), .Q(
FPMULT_Op_MY[10]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(Data_2[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1139), .Q(
FPMULT_Op_MY[9]), .QN(n1641) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(Data_2[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5276), .Q(
FPMULT_Op_MY[8]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(Data_2[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5276), .Q(
FPMULT_Op_MY[7]), .QN(n5219) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(Data_2[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5276), .Q(
FPMULT_Op_MY[6]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(Data_2[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5276), .Q(
FPMULT_Op_MY[5]), .QN(n1666) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(Data_2[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5276), .Q(
FPMULT_Op_MY[4]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(Data_2[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5276), .Q(
FPMULT_Op_MY[3]), .QN(n1658) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(Data_2[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1139), .Q(
FPMULT_Op_MY[2]), .QN(n1042) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(Data_1[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5278), .Q(
FPMULT_Op_MX[24]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(Data_1[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1139), .Q(
FPMULT_Op_MX[22]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(Data_1[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5279), .Q(
FPMULT_Op_MX[19]), .QN(n1662) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(Data_1[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5278), .Q(
FPMULT_Op_MX[18]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(Data_1[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5277), .Q(
FPMULT_Op_MX[17]), .QN(n1667) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(Data_1[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1140), .Q(
FPMULT_Op_MX[15]), .QN(n1664) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(Data_1[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5277), .Q(
FPMULT_Op_MX[14]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(Data_1[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5279), .Q(
FPMULT_Op_MX[13]), .QN(n1676) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(Data_1[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5278), .Q(
FPMULT_Op_MX[12]), .QN(n1040) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(Data_1[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1140), .Q(
FPMULT_Op_MX[11]), .QN(n1635) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(Data_1[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5275), .Q(
FPMULT_Op_MX[10]), .QN(n1636) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5275), .Q(
FPMULT_Op_MX[9]), .QN(n1659) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5275), .Q(
FPMULT_Op_MX[8]), .QN(n1638) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5275), .Q(
FPMULT_Op_MX[7]), .QN(n1643) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5275), .Q(
FPMULT_Op_MX[6]), .QN(n1644) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5275), .Q(
FPMULT_Op_MX[5]), .QN(n1649) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5275), .Q(
FPMULT_Op_MX[4]), .QN(n1650) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5275), .Q(
FPMULT_Op_MX[3]), .QN(n1651) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n912), .Q(
FPMULT_Op_MX[2]), .QN(n1652) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5275), .Q(
FPMULT_Op_MX[1]), .QN(n5218) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5271), .Q(
FPMULT_Op_MX[0]) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n106), .CK(
n5342), .RN(n5272), .QN(n1671) );
DFFRXLTS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n5341), .CK(n5342),
.RN(n5274), .Q(underflow_flag_mult), .QN(n5203) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(
FPMULT_Adder_M_result_A_adder[10]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5272), .QN(n1115) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1690), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5272), .Q(
FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(
FPMULT_Sgf_operation_Result[23]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n1132), .Q(
FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(
FPMULT_Exp_module_Data_S[8]), .CK(
FPMULT_Exp_module_exp_result_m_net8022814), .RN(n5271), .Q(
FPMULT_exp_oper_result[8]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(
FPMULT_Exp_module_Data_S[7]), .CK(
FPMULT_Exp_module_exp_result_m_net8022814), .RN(n5270), .Q(
FPMULT_exp_oper_result[7]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(
FPMULT_Exp_module_Data_S[6]), .CK(
FPMULT_Exp_module_exp_result_m_net8022814), .RN(n5274), .Q(
FPMULT_exp_oper_result[6]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(
FPMULT_Exp_module_Data_S[5]), .CK(
FPMULT_Exp_module_exp_result_m_net8022814), .RN(n913), .Q(
FPMULT_exp_oper_result[5]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(
FPMULT_Exp_module_Data_S[4]), .CK(
FPMULT_Exp_module_exp_result_m_net8022814), .RN(n5272), .Q(
FPMULT_exp_oper_result[4]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(
FPMULT_Exp_module_Data_S[3]), .CK(
FPMULT_Exp_module_exp_result_m_net8022814), .RN(n5270), .Q(
FPMULT_exp_oper_result[3]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(
FPMULT_Exp_module_Data_S[2]), .CK(
FPMULT_Exp_module_exp_result_m_net8022814), .RN(n5271), .Q(
FPMULT_exp_oper_result[2]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(
FPMULT_Exp_module_Data_S[1]), .CK(
FPMULT_Exp_module_exp_result_m_net8022814), .RN(n5274), .Q(
FPMULT_exp_oper_result[1]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Data_S[0]), .CK(
FPMULT_Exp_module_exp_result_m_net8022814), .RN(n5272), .Q(
FPMULT_exp_oper_result[0]) );
DFFRXLTS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Overflow_A), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n913), .Q(
FPMULT_Exp_module_Overflow_flag_A) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n5369), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5270), .Q(
FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n5367), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5274), .Q(
FPMULT_Sgf_normalized_result[21]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n5365), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5272), .Q(
FPMULT_Sgf_normalized_result[19]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n5363), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5271), .Q(
FPMULT_Sgf_normalized_result[17]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n5361), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5267), .Q(
FPMULT_Sgf_normalized_result[15]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n5359), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5265), .Q(
FPMULT_Sgf_normalized_result[13]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n5357), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5267), .Q(
FPMULT_Sgf_normalized_result[11]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n5355), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5265), .Q(
FPMULT_Sgf_normalized_result[9]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n5354), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5269), .Q(
FPMULT_Sgf_normalized_result[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n5350), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5268), .Q(
FPMULT_Sgf_normalized_result[4]), .QN(n1118) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5268), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5268), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5268), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5266), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5265), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5269), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5267), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5266), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5265), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5269), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5267), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5266), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5265), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5269), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5267), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5266), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5265), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5266), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5265), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5269), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5267), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5266), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5265), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5269), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5267), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5266), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5265), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5269), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5267), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5266), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5265), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
FPMULT_final_result_ieee_Module_Sign_S_mux), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8022580), .RN(
n5269), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n5337), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5246), .Q(
underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n5338), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5246), .Q(
overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n5336), .CK(
FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5244), .Q(
FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_EXP),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5245), .Q(
FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n819), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5245), .Q(
FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_SHT2),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5245), .Q(
FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_SIGN_FLAG_SFG),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5245), .Q(
FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n816), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5245), .Q(
FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n30), .CK(
FPADDSUB_EXP_STAGE_DMP_net8022634), .RN(n5245), .Q(
FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_EXP), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8022634), .RN(n5245), .Q(
FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n813), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5254), .Q(
FPADDSUB_OP_FLAG_SHT2) );
SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 clk_gate_FPMULT_Exp_module_Underflow_m_Q_reg (
.CLK(clk), .EN(n107), .ENCLK(n5342), .TE(1'b0) );
CMPR32X2TS DP_OP_26J307_123_9022_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n1120), .C(DP_OP_26J307_123_9022_n18), .CO(DP_OP_26J307_123_9022_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_234J307_126_8543_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n1127), .C(DP_OP_234J307_126_8543_n22), .CO(DP_OP_234J307_126_8543_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_234J307_126_8543_U9 ( .A(DP_OP_234J307_126_8543_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J307_126_8543_n9), .CO(
DP_OP_234J307_126_8543_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J307_126_8543_U8 ( .A(DP_OP_234J307_126_8543_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J307_126_8543_n8), .CO(
DP_OP_234J307_126_8543_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J307_126_8543_U7 ( .A(DP_OP_234J307_126_8543_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J307_126_8543_n7), .CO(
DP_OP_234J307_126_8543_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J307_126_8543_U6 ( .A(DP_OP_234J307_126_8543_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J307_126_8543_n6), .CO(
DP_OP_234J307_126_8543_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J307_126_8543_U5 ( .A(DP_OP_234J307_126_8543_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J307_126_8543_n5), .CO(
DP_OP_234J307_126_8543_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J307_126_8543_U4 ( .A(DP_OP_234J307_126_8543_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J307_126_8543_n4), .CO(
DP_OP_234J307_126_8543_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J307_126_8543_U3 ( .A(DP_OP_234J307_126_8543_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J307_126_8543_n3), .CO(
DP_OP_234J307_126_8543_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_234J307_126_8543_U2 ( .A(n1128), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_234J307_126_8543_n2), .CO(DP_OP_234J307_126_8543_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_1033_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n5096), .C(
intadd_1033_n3), .CO(intadd_1033_n2), .S(FPSENCOS_sh_exp_x[2]) );
CMPR32X2TS intadd_1033_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n5097), .C(
intadd_1033_n2), .CO(intadd_1033_n1), .S(FPSENCOS_sh_exp_x[3]) );
CMPR32X2TS intadd_1035_U4 ( .A(FPADDSUB_DmP_EXP_EWSW[24]), .B(n5177), .C(
intadd_1035_CI), .CO(intadd_1035_n3), .S(intadd_1035_SUM_0_) );
CMPR32X2TS intadd_1035_U3 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n5202), .C(
intadd_1035_n3), .CO(intadd_1035_n2), .S(intadd_1035_SUM_1_) );
CMPR32X2TS intadd_1035_U2 ( .A(FPADDSUB_DmP_EXP_EWSW[26]), .B(n5201), .C(
intadd_1035_n2), .CO(intadd_1035_n1), .S(intadd_1035_SUM_2_) );
DFFSX2TS R_47 ( .D(n5214), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .SN(n1140), .Q(n5334),
.QN(n5200) );
DFFSX2TS R_48 ( .D(n5213), .CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580),
.SN(n5240), .Q(n5335) );
DFFSX2TS R_56 ( .D(n5209), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n1133), .Q(n5332)
);
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(
FPSENCOS_reg_shift_y_net8022868), .RN(n1133), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_X[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5307), .Q(FPSENCOS_d_ff2_X[28]), .QN(n5206) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(FPADDSUB_Data_array_SWR[23]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5259), .Q(
FPADDSUB_Data_array_SWR[47]), .QN(n5165) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n5315), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n5161) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n834), .CK(FPMULT_FS_Module_net8022850),
.RN(n5274), .Q(FPMULT_FSM_selector_C), .QN(n5152) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(
FPADDSUB_Raw_mant_SGF[12]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5253), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n5150) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(
FPMULT_FS_Module_state_next[3]), .CK(FPMULT_FS_Module_net8022850),
.RN(n932), .Q(FPMULT_FS_Module_state_reg[3]), .QN(n5144) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n829), .CK(FPMULT_FS_Module_net8022850),
.RN(n5270), .Q(FPMULT_FSM_selector_B[1]), .QN(n5119) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n843), .CK(clk), .RN(n5315), .Q(
FPSENCOS_cont_var_out[0]), .QN(n5117) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(
FPMULT_FS_Module_state_next[1]), .CK(FPMULT_FS_Module_net8022850),
.RN(n5285), .Q(FPMULT_FS_Module_state_reg[1]), .QN(n5107) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n5098), .CK(
FPSENCOS_ITER_CONT_net8022904), .RN(n5315), .Q(
FPSENCOS_cont_iter_out[0]), .QN(n5098) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(FPSENCOS_ITER_CONT_N5), .CK(
FPSENCOS_ITER_CONT_net8022904), .RN(n5315), .Q(
FPSENCOS_cont_iter_out[3]), .QN(n5097) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(FPSENCOS_ITER_CONT_N4), .CK(
FPSENCOS_ITER_CONT_net8022904), .RN(n5315), .Q(
FPSENCOS_cont_iter_out[2]), .QN(n5096) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n5316), .Q(NaN_flag)
);
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_5), .CK(
FPADDSUB_inst_ShiftRegister_net8022742), .RN(n5225), .Q(busy), .QN(
n5208) );
CMPR32X2TS DP_OP_26J307_123_9022_U3 ( .A(n1034), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J307_123_9022_n3), .CO(
DP_OP_26J307_123_9022_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J307_123_9022_U4 ( .A(n1034), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J307_123_9022_n4), .CO(
DP_OP_26J307_123_9022_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J307_123_9022_U5 ( .A(DP_OP_26J307_123_9022_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J307_123_9022_n5), .CO(
DP_OP_26J307_123_9022_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J307_123_9022_U6 ( .A(DP_OP_26J307_123_9022_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J307_123_9022_n6), .CO(
DP_OP_26J307_123_9022_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J307_123_9022_U7 ( .A(DP_OP_26J307_123_9022_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J307_123_9022_n7), .CO(
DP_OP_26J307_123_9022_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J307_123_9022_U8 ( .A(DP_OP_26J307_123_9022_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J307_123_9022_n8), .CO(
DP_OP_26J307_123_9022_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
DFFRHQX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(Data_1[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5282), .Q(
FPMULT_Op_MX[21]) );
DFFSX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n951), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n824), .QN(
FPMULT_P_Sgf[24]) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n842), .CK(clk), .RN(n5315), .Q(
FPSENCOS_cont_var_out[1]) );
DFFRX4TS FPMULT_Sel_A_Q_reg_0_ ( .D(1'b1), .CK(n5342), .RN(n5272), .Q(
FPMULT_FSM_selector_A) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[2]), .CK(
FPADDSUB_inst_ShiftRegister_net8022742), .RN(n5239), .Q(
FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n5169) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[1]), .CK(
FPADDSUB_inst_ShiftRegister_net8022742), .RN(n5225), .Q(
FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[3]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5240), .Q(
FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(FPADDSUB_Raw_mant_SGF[5]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5251), .Q(
FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n5170) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(
FPADDSUB_Raw_mant_SGF[10]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5251), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n5315), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[4]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n937), .Q(
FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n1095) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(add_subt_data1[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5227), .Q(
FPADDSUB_intDX_EWSW[29]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n844), .CK(clk), .RN(n5225), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(add_subt_data1[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5227), .Q(
FPADDSUB_intDX_EWSW[30]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(FPADDSUB_Raw_mant_SGF[2]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5251), .Q(
FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(add_subt_data2[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5259), .Q(
FPADDSUB_intDY_EWSW[5]), .QN(n5172) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(add_subt_data2[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5242), .Q(
FPADDSUB_intDY_EWSW[7]), .QN(n5171) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(FPADDSUB_Raw_mant_SGF[7]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5251), .Q(
FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(FPADDSUB_Raw_mant_SGF[4]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5251), .Q(
FPADDSUB_Raw_mant_NRM_SWR[4]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(FPADDSUB_Data_array_SWR[17]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5257), .Q(
FPADDSUB_Data_array_SWR[41]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(FPADDSUB_Data_array_SWR[16]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5235), .Q(
FPADDSUB_Data_array_SWR[40]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(FPADDSUB_Raw_mant_SGF[9]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5253), .Q(
FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT2_EWSW[10]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5261), .Q(
FPADDSUB_DMP_SFG[10]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT2_EWSW[11]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5262), .Q(
FPADDSUB_DMP_SFG[11]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(add_subt_data1[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5241), .Q(
FPADDSUB_intDX_EWSW[3]), .QN(n1047) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(FPADDSUB_Raw_mant_SGF[8]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5253), .Q(
FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(add_subt_data1[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5233), .Q(
FPADDSUB_intDX_EWSW[15]), .QN(n1100) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT2_EWSW[19]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5264), .Q(
FPADDSUB_DMP_SFG[19]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT2_EWSW[21]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5253), .Q(
FPADDSUB_DMP_SFG[21]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT2_EWSW[2]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5255), .Q(
FPADDSUB_DMP_SFG[2]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT2_EWSW[17]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5263), .Q(
FPADDSUB_DMP_SFG[17]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT2_EWSW[15]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5263), .Q(
FPADDSUB_DMP_SFG[15]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT2_EWSW[13]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5262), .Q(
FPADDSUB_DMP_SFG[13]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(FPADDSUB_Data_array_SWR[18]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5239), .Q(
FPADDSUB_Data_array_SWR[42]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(add_subt_data2[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5238), .Q(
FPADDSUB_intDY_EWSW[10]), .QN(n5179) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(FPADDSUB_Data_array_SWR[19]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5259), .Q(
FPADDSUB_Data_array_SWR[43]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(add_subt_data1[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5236), .Q(
FPADDSUB_intDX_EWSW[13]), .QN(n1049) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(add_subt_data1[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5232), .Q(
FPADDSUB_intDX_EWSW[21]), .QN(n1101) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(add_subt_data2[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5227), .Q(
FPADDSUB_intDY_EWSW[24]), .QN(n5185) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(add_subt_data2[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5232), .Q(
FPADDSUB_intDY_EWSW[16]), .QN(n5181) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT2_EWSW[9]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5261), .Q(
FPADDSUB_DMP_SFG[9]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n5314), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Y[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5305), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_X[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5307), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT2_EWSW[12]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5262), .Q(
FPADDSUB_DMP_SFG[12]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT2_EWSW[16]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5263), .Q(
FPADDSUB_DMP_SFG[16]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT2_EWSW[18]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5264), .Q(
FPADDSUB_DMP_SFG[18]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT2_EWSW[14]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5262), .Q(
FPADDSUB_DMP_SFG[14]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(add_subt_data2[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5228), .Q(
FPADDSUB_intDY_EWSW[27]), .QN(n5187) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT2_EWSW[22]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n3962), .Q(
FPADDSUB_DMP_SFG[22]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT2_EWSW[20]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5264), .Q(
FPADDSUB_DMP_SFG[20]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(
FPADDSUB_formatted_number_W[31]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5240), .Q(
result_add_subt[31]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(
FPADDSUB_formatted_number_W[30]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5246), .Q(
result_add_subt[30]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(
FPADDSUB_formatted_number_W[29]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5246), .Q(
result_add_subt[29]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(
FPADDSUB_formatted_number_W[28]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5246), .Q(
result_add_subt[28]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(
FPADDSUB_formatted_number_W[27]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5246), .Q(
result_add_subt[27]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(
FPADDSUB_formatted_number_W[26]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5246), .Q(
result_add_subt[26]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(
FPADDSUB_formatted_number_W[25]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5245), .Q(
result_add_subt[25]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(
FPADDSUB_formatted_number_W[24]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5245), .Q(
result_add_subt[24]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(
FPADDSUB_formatted_number_W[23]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8022580), .RN(n5245), .Q(
result_add_subt[23]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(Data_1[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5277), .Q(
FPMULT_Op_MX[20]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(add_subt_data2[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5255), .Q(
FPADDSUB_intDY_EWSW[15]), .QN(n5191) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(add_subt_data1[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5238), .Q(
FPADDSUB_intDX_EWSW[8]), .QN(n954) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(add_subt_data1[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5254), .Q(
FPADDSUB_intDX_EWSW[18]), .QN(n1109) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(add_subt_data1[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5237), .Q(
FPADDSUB_intDX_EWSW[11]), .QN(n1096) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(add_subt_data1[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5234), .Q(
FPADDSUB_intDX_EWSW[17]), .QN(n1107) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(add_subt_data1[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5226), .Q(
FPADDSUB_intDX_EWSW[25]), .QN(n1050) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(add_subt_data1[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5226), .Q(
FPADDSUB_intDX_EWSW[26]), .QN(n1108) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n5315), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(add_subt_data2[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5241), .Q(
FPADDSUB_intDY_EWSW[1]), .QN(n5196) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(add_subt_data2[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5227), .Q(
FPADDSUB_intDY_EWSW[26]), .QN(n5197) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(add_subt_data1[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5234), .Q(
FPADDSUB_intDX_EWSW[20]), .QN(n1112) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(add_subt_data2[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5238), .Q(
FPADDSUB_intDY_EWSW[8]), .QN(n5194) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(FPADDSUB_Data_array_SWR[9]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5236), .Q(
FPADDSUB_Data_array_SWR[35]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_X[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5307), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(add_subt_data1[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5231), .Q(
FPADDSUB_intDX_EWSW[19]), .QN(n1099) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(add_subt_data1[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5241), .Q(
FPADDSUB_intDX_EWSW[1]), .QN(n1051) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(FPADDSUB_Data_array_SWR[8]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5243), .Q(
FPADDSUB_Data_array_SWR[34]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(FPADDSUB_Data_array_SWR[10]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5237), .Q(
FPADDSUB_Data_array_SWR[36]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(add_subt_data1[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5232), .Q(
FPADDSUB_intDX_EWSW[2]), .QN(n1097) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(n1181), .CK(clk), .RN(n1228), .Q(
operation_reg_0_) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(add_subt_data1[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5259), .Q(
FPADDSUB_intDX_EWSW[9]), .QN(n1098) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(add_subt_data1[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5226), .Q(
FPADDSUB_intDX_EWSW[23]), .QN(n5155) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Y[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5305), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_SHT2), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5233), .Q(
FPADDSUB_OP_FLAG_SFG) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(add_subt_data1[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5236), .Q(
FPADDSUB_intDX_EWSW[14]), .QN(n5156) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n5344), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5312), .Q(
FPSENCOS_d_ff1_operation_out) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(add_subt_data2[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5228), .Q(
FPADDSUB_intDY_EWSW[28]), .QN(n5157) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(add_subt_data1[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5227), .Q(
FPADDSUB_intDX_EWSW[28]), .QN(n5130) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n830), .CK(FPMULT_FS_Module_net8022850),
.RN(n5271), .Q(FPMULT_FSM_selector_B[0]), .QN(n5116) );
DFFSXLTS add_x_69_R_31 ( .D(add_x_69_n8), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n1228), .Q(n5092)
);
DFFSXLTS add_x_69_R_34 ( .D(add_x_69_n161), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n1228), .Q(n5094)
);
DFFRXLTS add_x_69_R_35 ( .D(add_x_69_n12), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n1228), .Q(n5095)
);
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Y[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5306), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_X[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5317), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Y[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5305), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Y[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5306), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_X[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5307), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_X[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5322), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(add_subt_data1[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5240), .Q(
FPADDSUB_intDX_EWSW[0]), .QN(n1111) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(add_subt_data2[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5227), .Q(
FPADDSUB_intDY_EWSW[23]), .QN(n5204) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n5316), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n824), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n824), .Q(
dataA[29]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Y[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5304), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_X[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8022868), .RN(n5307), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n5316), .Q(
dataB[25]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[1]), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5253), .Q(FPADDSUB_N60), .QN(n5129) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(
FPMULT_Sgf_operation_Result[25]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n5325), .Q(
FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(
FPMULT_Adder_M_result_A_adder[1]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5270), .Q(
FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(
FPMULT_Adder_M_result_A_adder[3]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5272), .Q(
FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(
FPMULT_Adder_M_result_A_adder[5]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n913), .Q(
FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(
FPMULT_Adder_M_result_A_adder[7]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5274), .Q(
FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(
FPMULT_Adder_M_result_A_adder[9]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5271), .Q(
FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(
FPMULT_Adder_M_result_A_adder[11]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5270), .Q(
FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(
FPMULT_Adder_M_result_A_adder[13]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5272), .Q(
FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(
FPMULT_Adder_M_result_A_adder[15]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n913), .Q(
FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(
FPMULT_Adder_M_result_A_adder[17]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5274), .Q(
FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(
FPMULT_Adder_M_result_A_adder[19]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n913), .Q(
FPMULT_Add_result[19]) );
DFFRX1TS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n5316), .Q(
dataB[27]) );
DFFRHQX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(Data_2[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5282), .Q(
FPMULT_Op_MY[12]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1138), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5255), .Q(
FPADDSUB_left_right_SHT2), .QN(n1114) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(FPADDSUB_Raw_mant_SGF[3]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5251), .Q(
FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n5160) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n5345), .CK(
clk), .RN(n5225), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]),
.QN(n1106) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(FPADDSUB_Data_array_SWR[13]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5237), .Q(
FPADDSUB_Data_array_SWR[38]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(FPADDSUB_Data_array_SWR[12]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5238), .Q(
FPADDSUB_Data_array_SWR[37]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(add_subt_data2[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5242), .Q(
FPADDSUB_intDY_EWSW[6]), .QN(n5180) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(add_subt_data2[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5234), .Q(
FPADDSUB_intDY_EWSW[4]), .QN(n5182) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(FPADDSUB_Data_array_SWR[14]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5256), .Q(
FPADDSUB_Data_array_SWR[39]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(add_subt_data2[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5232), .Q(
FPADDSUB_intDY_EWSW[21]), .QN(n5188) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(add_subt_data2[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5236), .Q(
FPADDSUB_intDY_EWSW[13]), .QN(n5183) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(add_subt_data2[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5232), .Q(
FPADDSUB_intDY_EWSW[2]), .QN(n5184) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(add_subt_data2[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5239), .Q(
FPADDSUB_intDY_EWSW[9]), .QN(n5186) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n5315), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n810), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5247), .Q(
FPADDSUB_ADD_OVRFLW_NRM2), .QN(n1034) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(
FPADDSUB_Raw_mant_SGF[11]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5253), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(
FPADDSUB_Raw_mant_SGF[13]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5253), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[2]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5240), .Q(
FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n5145) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(
FPMULT_Adder_M_result_A_adder[8]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5275), .Q(
FPMULT_Add_result[8]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n4219), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5240), .Q(
FPADDSUB_bit_shift_SHT2) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(FPADDSUB_N59), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5251), .Q(
FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[0]), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5253), .Q(FPADDSUB_N59), .QN(n5103) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(add_subt_data2[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5227), .Q(
FPADDSUB_intDY_EWSW[25]), .QN(n5193) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(add_subt_data2[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5234), .Q(
FPADDSUB_intDY_EWSW[17]), .QN(n5192) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(add_subt_data2[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5237), .Q(
FPADDSUB_intDY_EWSW[11]), .QN(n5190) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(add_subt_data2[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5257), .Q(
FPADDSUB_intDY_EWSW[18]), .QN(n5195) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(add_subt_data2[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5241), .Q(
FPADDSUB_intDY_EWSW[3]), .QN(n5198) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(add_subt_data1[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5226), .Q(
FPADDSUB_intDX_EWSW[24]), .QN(n1110) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(add_subt_data2[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5236), .Q(
FPADDSUB_intDY_EWSW[14]), .QN(n5110) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(add_subt_data1[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5226), .Q(
FPADDSUB_intDX_EWSW[27]), .QN(n1048) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(add_subt_data1[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5231), .Q(
FPADDSUB_intDX_EWSW[22]), .QN(n1695) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(add_subt_data2[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5231), .Q(
FPADDSUB_intDY_EWSW[19]), .QN(n5113) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(add_subt_data2[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5235), .Q(
FPADDSUB_intDY_EWSW[20]), .QN(n5189) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(FPADDSUB_Raw_mant_SGF[6]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5251), .Q(
FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n5115) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(add_subt_data2[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5231), .Q(
FPADDSUB_intDY_EWSW[22]), .QN(n5114) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(add_subt_data2[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5240), .Q(
FPADDSUB_intDY_EWSW[0]), .QN(n5199) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(region_flag[1]), .CK(
FPSENCOS_reg_Z0_net8022868), .RN(n5314), .Q(
FPSENCOS_d_ff1_shift_region_flag_out[1]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n874), .CK(clk), .RN(n5225), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(Data_2[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5279), .Q(
FPMULT_Op_MY[25]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(Data_1[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5279), .Q(
FPMULT_Op_MX[29]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(Data_1[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5279), .Q(
FPMULT_Op_MX[25]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(Data_1[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5279), .Q(
FPMULT_Op_MX[16]) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(clk), .RN(n5225), .Q(ready_add_subt), .QN(n1105) );
DFFRX1TS R_55 ( .D(n5210), .CK(clk), .RN(n5322), .Q(n5328) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n5314), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .QN(n1693) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[4]), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n936), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n5122) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n5136), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5254), .Q(
FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n5100) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(add_subt_data1[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5232), .Q(
FPADDSUB_intDX_EWSW[16]), .QN(n5149) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(add_subt_data1[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5238), .Q(
FPADDSUB_intDX_EWSW[10]), .QN(n5140) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n5314), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(Data_1[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5278), .Q(
FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(Data_1[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1140), .Q(
FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(Data_1[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5277), .Q(
FPMULT_Op_MX[26]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(add_subt_data1[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5234), .Q(
FPADDSUB_intDX_EWSW[4]), .QN(n5153) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(add_subt_data1[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5242), .Q(
FPADDSUB_intDX_EWSW[6]), .QN(n5154) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(add_subt_data2[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5257), .Q(
FPADDSUB_intDY_EWSW[12]), .QN(n5141) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n5316), .Q(
dataB[28]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(FPADDSUB_Data_array_SWR[25]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5256), .Q(
FPADDSUB_Data_array_SWR[49]), .QN(n1103) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(FPADDSUB_Data_array_SWR[24]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5258), .Q(
FPADDSUB_Data_array_SWR[48]), .QN(n1102) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(Data_1[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n5277), .Q(
FPMULT_Op_MX[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(Data_1[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1140), .Q(
FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(
FPMULT_Adder_M_result_A_adder[14]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5274), .Q(
FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(
FPMULT_Adder_M_result_A_adder[12]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n912), .Q(
FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(
FPMULT_Adder_M_result_A_adder[6]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5270), .Q(
FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(
FPMULT_Adder_M_result_A_adder[4]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5274), .Q(
FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(
FPMULT_Adder_M_result_A_adder[2]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n912), .Q(
FPMULT_Add_result[2]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(FPADDSUB_Raw_mant_SGF[1]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5251), .Q(
FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n5127) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n5316), .Q(
dataB[23]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n5316), .Q(
dataB[26]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n5327), .Q(
dataA[23]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n5316), .Q(
dataB[24]) );
DFFRX1TS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n824), .Q(
dataA[26]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n5368), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5271), .Q(
FPMULT_Sgf_normalized_result[22]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(Data_2[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1139), .Q(
FPMULT_Op_MY[0]), .QN(n1038) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(FPSENCOS_ITER_CONT_N3), .CK(
FPSENCOS_ITER_CONT_net8022904), .RN(n5315), .Q(
FPSENCOS_cont_iter_out[1]), .QN(n5118) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(
FPADDSUB_Raw_mant_SGF[16]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n922), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(
FPADDSUB_Raw_mant_SGF[17]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n922), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n1228), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFSX1TS R_39 ( .D(n5216), .CK(clk), .SN(n5319), .Q(n5330) );
DFFSXLTS R_49 ( .D(n5212), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n5325), .Q(n5333)
);
DFFSX1TS R_54 ( .D(n5211), .CK(clk), .SN(n5327), .Q(n5329) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(
FPADDSUB_Raw_mant_SGF[14]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n921), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n5131) );
DFFSXLTS add_x_69_R_33 ( .D(add_x_69_n10), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n916), .Q(n5093)
);
DFFSXLTS add_x_69_R_27 ( .D(add_x_69_n9), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n1229), .Q(n5091)
);
DFFSXLTS add_x_69_R_23 ( .D(n1678), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n933), .Q(n5090)
);
DFFSXLTS add_x_69_R_21 ( .D(n1679), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n5284), .Q(n5089)
);
DFFSXLTS add_x_69_R_19 ( .D(n1681), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n5285), .Q(n5088)
);
DFFSXLTS add_x_69_R_17 ( .D(add_x_69_n52), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n1228), .Q(n5087)
);
DFFSXLTS add_x_69_R_15 ( .D(n1680), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n5284), .Q(n5086)
);
DFFSXLTS add_x_69_R_13 ( .D(add_x_69_n66), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n917), .Q(n5085)
);
DFFSXLTS add_x_69_R_11 ( .D(n1065), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n933), .Q(n5084)
);
DFFSXLTS add_x_69_R_9 ( .D(add_x_69_n90), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n932), .Q(n5083)
);
DFFSXLTS add_x_69_R_7 ( .D(add_x_69_n82), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n916), .Q(n5082)
);
DFFSXLTS add_x_69_R_5 ( .D(add_x_69_n5), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n917), .Q(n5081)
);
DFFSXLTS add_x_69_R_3 ( .D(add_x_69_n4), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n5285), .Q(n5080)
);
DFFSXLTS add_x_69_R_1 ( .D(add_x_69_n6), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n916), .Q(n5079)
);
DFFSX1TS R_40 ( .D(n5215), .CK(clk), .SN(n5327), .Q(n5331) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(add_subt_data1[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8022580), .RN(n5235), .Q(
FPADDSUB_intDX_EWSW[12]), .QN(n5178) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(FPADDSUB_Data_array_SWR[5]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5239), .Q(
FPADDSUB_Data_array_SWR[31]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(
FPMULT_Adder_M_result_A_adder[18]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5271), .Q(
FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(
FPMULT_Adder_M_result_A_adder[16]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5270), .Q(
FPMULT_Add_result[16]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n5352), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5268), .Q(
FPMULT_Sgf_normalized_result[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[2]), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5253), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n5128) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT2_EWSW[0]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5256), .Q(
FPADDSUB_DMP_SFG[0]) );
DFFRX2TS R_57 ( .D(FPMULT_Sgf_normalized_result[23]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n912), .Q(n1032) );
DFFSX2TS R_60 ( .D(FPMULT_Sgf_normalized_result[22]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .SN(n5272), .Q(n1031) );
DFFRX2TS R_94 ( .D(n1028), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n938),
.Q(n4376) );
DFFRX1TS R_93 ( .D(FPADDSUB_DMP_SHT2_EWSW[8]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5261), .Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS R_96 ( .D(FPMULT_Sgf_normalized_result[22]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n912), .Q(n1027) );
DFFRX2TS R_103 ( .D(n1024), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n937), .Q(n4343) );
DFFRX1TS R_102 ( .D(FPADDSUB_DMP_SHT2_EWSW[4]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5256), .Q(FPADDSUB_DMP_SFG[4]) );
DFFRX2TS R_115 ( .D(n3822), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n5284), .Q(n1019)
);
DFFSX2TS R_118 ( .D(n1017), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .SN(n937), .Q(n4538) );
DFFRX1TS R_116 ( .D(FPADDSUB_sftr_odat_SHT2_SWR[9]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n936), .Q(
FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n1018) );
DFFRX1TS R_117 ( .D(FPADDSUB_DMP_SHT2_EWSW[7]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5260), .Q(FPADDSUB_DMP_SFG[7]) );
DFFSX2TS R_119 ( .D(n3819), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n933), .Q(n1016)
);
DFFSX2TS R_120 ( .D(n3818), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n933), .Q(n1015)
);
DFFSX2TS R_121 ( .D(n3817), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n933), .Q(n1014)
);
DFFSX2TS R_124 ( .D(n1012), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .SN(n938), .Q(n4361) );
DFFRX1TS R_122 ( .D(FPADDSUB_sftr_odat_SHT2_SWR[7]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n936), .Q(
FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n1013) );
DFFRX1TS R_123 ( .D(FPADDSUB_DMP_SHT2_EWSW[5]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5258), .Q(FPADDSUB_DMP_SFG[5]) );
DFFSX2TS R_132 ( .D(n1010), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .SN(n937), .Q(n4562), .QN(n953) );
DFFRX1TS R_130 ( .D(FPADDSUB_sftr_odat_SHT2_SWR[5]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n936), .Q(
FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n1011) );
DFFRX1TS R_131 ( .D(FPADDSUB_DMP_SHT2_EWSW[3]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5233), .Q(FPADDSUB_DMP_SFG[3]) );
DFFSX2TS R_133 ( .D(n3831), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n933), .Q(n1009)
);
DFFSX2TS R_135 ( .D(n3829), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n933), .Q(n1008)
);
DFFRX2TS R_138 ( .D(n1006), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n938), .Q(n4345) );
DFFRX1TS R_136 ( .D(FPADDSUB_sftr_odat_SHT2_SWR[8]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n936), .Q(
FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n1007) );
DFFRX1TS R_137 ( .D(FPADDSUB_DMP_SHT2_EWSW[6]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5260), .Q(FPADDSUB_DMP_SFG[6]) );
DFFSX2TS R_154 ( .D(n3753), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n916), .QN(n982)
);
DFFSX2TS R_159 ( .D(n1003), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .SN(n938), .Q(n4584) );
DFFRX1TS R_158 ( .D(FPADDSUB_DMP_SHT2_EWSW[1]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n5254), .Q(FPADDSUB_DMP_SFG[1]) );
DFFRX2TS R_161 ( .D(n3843), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n5283), .Q(n1002)
);
DFFSX2TS R_165 ( .D(n3850), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n930), .Q(n998)
);
DFFRX2TS R_166 ( .D(n3849), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n929), .Q(n997)
);
DFFSX2TS R_167 ( .D(FPMULT_Sgf_normalized_result[21]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .SN(n913), .Q(n996) );
DFFSX2TS R_170 ( .D(n3856), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n930), .Q(n993)
);
DFFSX2TS R_169 ( .D(n3857), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n930), .Q(n994)
);
DFFRX1TS R_173 ( .D(n3828), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n5283), .Q(n991)
);
DFFRX1TS R_172 ( .D(n3826), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n5283), .Q(n992)
);
DFFRX2TS R_175 ( .D(n3842), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n5283), .Q(n990)
);
DFFRX2TS R_176 ( .D(n3840), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n5283), .Q(n989)
);
DFFSX2TS R_178 ( .D(n4462), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616),
.SN(n5233), .Q(n987) );
DFFSX2TS R_177 ( .D(n3896), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616),
.SN(n5255), .Q(n988) );
DFFSX1TS R_179 ( .D(n1337), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n917), .Q(n986)
);
DFFRXLTS R_180 ( .D(n1335), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n915), .Q(n985)
);
DFFRX4TS R_151_RW_0 ( .D(n3685), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n915), .Q(n1005)
);
DFFSX2TS R_202 ( .D(n3852), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n930), .Q(n979)
);
DFFSX2TS R_201 ( .D(n3853), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n930), .Q(n980)
);
DFFSX2TS R_203 ( .D(n3827), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n933), .Q(n978)
);
DFFSX2TS R_206 ( .D(n4262), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .SN(
n5255), .Q(n977) );
DFFSX2TS R_208 ( .D(n4225), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .SN(
n5254), .Q(n975) );
DFFSX2TS R_209 ( .D(n3774), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n933), .Q(n974)
);
DFFRX2TS R_210 ( .D(n3683), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n932), .Q(n973)
);
DFFRX2TS R_211 ( .D(n3682), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n932), .Q(n972)
);
DFFSX2TS R_212 ( .D(n3663), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n917), .Q(n971)
);
DFFSX2TS R_213 ( .D(n3844), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n1228), .Q(n970)
);
DFFSX2TS R_214 ( .D(add_x_69_n96), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n916), .Q(n969)
);
DFFSX2TS R_215 ( .D(n3754), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n917), .Q(n968),
.QN(n967) );
DFFSX2TS R_216 ( .D(n3756), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n916), .Q(n966)
);
DFFSX2TS R_217 ( .D(n3830), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n933), .Q(n965)
);
DFFSX2TS R_218 ( .D(n3761), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n917), .Q(n964)
);
DFFSX2TS R_219 ( .D(n3770), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n916), .Q(n963)
);
DFFSX2TS R_220 ( .D(n3766), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n917), .Q(n962),
.QN(n961) );
DFFSX2TS R_221 ( .D(n3763), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n916), .Q(n960)
);
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(Data_2[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8022832), .RN(n1139), .Q(
FPMULT_Op_MY[1]), .QN(n1639) );
DFFRXLTS R_111_RW_1 ( .D(n3815), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n915), .QN(n952)
);
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n5351), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5268), .Q(
FPMULT_Sgf_normalized_result[5]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n5349), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5268), .Q(
FPMULT_Sgf_normalized_result[3]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n5346), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5268), .Q(
FPMULT_Sgf_normalized_result[0]), .QN(n1690) );
DFFRXLTS R_108_RW_1 ( .D(n3825), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n915), .QN(n948)
);
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(
FPADDSUB_Raw_mant_SGF[24]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n921), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]), .QN(n5151) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n5347), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5268), .Q(
FPMULT_Sgf_normalized_result[1]) );
DFFRXLTS R_112 ( .D(n3774), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n1228), .Q(n1021)
);
DFFSXLTS R_168 ( .D(n3782), .CK(FPMULT_Adder_M_Add_Subt_Result_net8022760),
.SN(n913), .Q(n995) );
DFFRXLTS add_x_69_R_29 ( .D(add_x_69_n7), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n5283), .QN(n981)
);
DFFRXLTS R_114_RW_1 ( .D(n3823), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n915), .Q(n1020)
);
DFFRXLTS R_97_RW_0 ( .D(n3750), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n915), .Q(n1026)
);
DFFRXLTS R_90_RW_1 ( .D(n3821), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .RN(n915), .Q(n1030)
);
DFFSXLTS R_207 ( .D(n4097), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .SN(
n5233), .Q(n976) );
DFFRX1TS R_92 ( .D(n5138), .CK(FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n938),
.Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n1029) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n5364), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5270), .Q(
FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n5362), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5269), .Q(
FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n5360), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5266), .Q(
FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n5358), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5269), .Q(
FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n5356), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5266), .Q(
FPMULT_Sgf_normalized_result[10]) );
DFFRX1TS R_101 ( .D(FPADDSUB_sftr_odat_SHT2_SWR[6]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n937), .Q(
FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n1025) );
DFFRX1TS R_157 ( .D(FPADDSUB_sftr_odat_SHT2_SWR[3]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8022634), .RN(n938), .Q(
FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n1004) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n5366), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n912), .Q(
FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n5353), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5267), .Q(
FPMULT_Sgf_normalized_result[7]) );
DFFSX1TS R_164 ( .D(n4555), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616),
.SN(n922), .Q(n999) );
DFFSX1TS R_162 ( .D(n4492), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616),
.SN(n922), .Q(n1001) );
DFFRXLTS R_163 ( .D(n4491), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616),
.RN(n921), .Q(n1000) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(
FPADDSUB_Raw_mant_SGF[22]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n921), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(
FPADDSUB_Raw_mant_SGF[23]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n921), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRHQX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(
FPADDSUB_Raw_mant_SGF[21]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5280), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(
FPADDSUB_Raw_mant_SGF[19]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n921), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]), .QN(n5168) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(
FPADDSUB_Raw_mant_SGF[20]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8022616), .RN(n5253), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n5348), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8022778), .RN(n5268), .Q(
FPMULT_Sgf_normalized_result[2]) );
DFFRX4TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(
FPMULT_FS_Module_state_next[0]), .CK(FPMULT_FS_Module_net8022850),
.RN(n1229), .Q(n910) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(FPADDSUB_Data_array_SWR[22]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n3961), .Q(
FPADDSUB_Data_array_SWR[46]), .QN(n5162) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(FPADDSUB_Data_array_SWR[21]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5235), .Q(
FPADDSUB_Data_array_SWR[45]), .QN(n5167) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(FPADDSUB_Data_array_SWR[6]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5234), .Q(
FPADDSUB_Data_array_SWR[32]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(FPADDSUB_Data_array_SWR[7]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5257), .Q(
FPADDSUB_Data_array_SWR[33]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(FPADDSUB_Data_array_SWR[20]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5258), .Q(
FPADDSUB_Data_array_SWR[44]), .QN(n5176) );
CMPR32X2TS DP_OP_26J307_123_9022_U2 ( .A(n1034), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J307_123_9022_n2), .CO(
DP_OP_26J307_123_9022_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFSX1TS R_100 ( .D(n1052), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8022796), .SN(n1229), .QN(n984)
);
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(FPADDSUB_Data_array_SWR[4]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8022616), .RN(n5244), .Q(
FPADDSUB_Data_array_SWR[30]) );
CMPR32X2TS intadd_1033_U4 ( .A(n1134), .B(FPSENCOS_d_ff2_X[24]), .C(
intadd_1033_CI), .CO(intadd_1033_n3), .S(FPSENCOS_sh_exp_x[1]) );
CMPR32X2TS intadd_1034_U4 ( .A(n1134), .B(FPSENCOS_d_ff2_Y[24]), .C(
intadd_1034_CI), .CO(intadd_1034_n3), .S(FPSENCOS_sh_exp_y[1]) );
CMPR32X2TS intadd_1034_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n5096), .C(
intadd_1034_n3), .CO(intadd_1034_n2), .S(FPSENCOS_sh_exp_y[2]) );
CMPR32X2TS intadd_1034_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n5097), .C(
intadd_1034_n2), .CO(intadd_1034_n1), .S(FPSENCOS_sh_exp_y[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(
FPMULT_Adder_M_result_A_adder[20]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8022760), .RN(n5274), .Q(
FPMULT_Add_result[20]) );
NAND2X1TS U1399 ( .A(n3848), .B(n3847), .Y(n3849) );
NAND2X1TS U1400 ( .A(n3791), .B(n3829), .Y(add_x_69_n9) );
NAND2X1TS U1401 ( .A(n3813), .B(n3823), .Y(add_x_69_n7) );
NAND2X1TS U1402 ( .A(n3790), .B(n3789), .Y(add_x_69_n4) );
NAND2X1TS U1403 ( .A(n3803), .B(n3802), .Y(add_x_69_n12) );
NAND2X1TS U1404 ( .A(n3798), .B(n3797), .Y(add_x_69_n8) );
NAND2X1TS U1405 ( .A(n3792), .B(n3817), .Y(add_x_69_n5) );
OAI21X2TS U1406 ( .A0(n3853), .A1(n3787), .B0(n3786), .Y(add_x_69_n161) );
NOR2X2TS U1407 ( .A(n3816), .B(n3818), .Y(n3821) );
INVX2TS U1408 ( .A(n3663), .Y(n3825) );
NOR2X4TS U1409 ( .A(n3663), .B(n1052), .Y(n3750) );
CLKBUFX2TS U1410 ( .A(n1133), .Y(n5285) );
INVX2TS U1411 ( .A(n4856), .Y(n4848) );
INVX2TS U1412 ( .A(n4861), .Y(n4860) );
INVX2TS U1413 ( .A(n4861), .Y(n4863) );
INVX2TS U1414 ( .A(n1691), .Y(n4850) );
INVX3TS U1415 ( .A(n4831), .Y(n4835) );
INVX3TS U1416 ( .A(n4825), .Y(n4819) );
INVX2TS U1417 ( .A(n4856), .Y(n4857) );
INVX2TS U1418 ( .A(n4856), .Y(n4846) );
INVX2TS U1419 ( .A(n4856), .Y(n4855) );
INVX2TS U1420 ( .A(n4856), .Y(n4854) );
CLKINVX6TS U1421 ( .A(n1177), .Y(n1178) );
INVX2TS U1422 ( .A(n1691), .Y(n3976) );
CLKINVX6TS U1423 ( .A(n1177), .Y(n1179) );
INVX2TS U1424 ( .A(n3839), .Y(n3842) );
INVX2TS U1425 ( .A(n3814), .Y(n3823) );
INVX3TS U1426 ( .A(n4825), .Y(n4821) );
INVX3TS U1427 ( .A(n4825), .Y(n4834) );
INVX3TS U1428 ( .A(n4825), .Y(n4830) );
INVX4TS U1429 ( .A(n3785), .Y(n3853) );
NAND2X1TS U1430 ( .A(n3859), .B(n3858), .Y(n3860) );
NAND2X1TS U1431 ( .A(n4877), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n4073) );
INVX2TS U1432 ( .A(n3815), .Y(n3816) );
CLKINVX6TS U1433 ( .A(n1129), .Y(n1131) );
CLKINVX6TS U1434 ( .A(n1129), .Y(n1130) );
BUFX3TS U1435 ( .A(n4825), .Y(n4818) );
OR2X2TS U1436 ( .A(n1346), .B(n2867), .Y(n1063) );
NAND2X1TS U1437 ( .A(n2755), .B(n2865), .Y(n2756) );
BUFX3TS U1438 ( .A(n4833), .Y(n4832) );
BUFX3TS U1439 ( .A(n4833), .Y(n4826) );
NAND2X2TS U1440 ( .A(n3679), .B(n3678), .Y(n3817) );
NAND2X2TS U1441 ( .A(n3681), .B(n3680), .Y(n3789) );
XNOR2X1TS U1442 ( .A(n4489), .B(n4483), .Y(n4484) );
OAI21X1TS U1443 ( .A0(n3838), .A1(n3834), .B0(n3835), .Y(n2757) );
BUFX3TS U1444 ( .A(n3981), .Y(n4943) );
BUFX3TS U1445 ( .A(n4922), .Y(n4944) );
BUFX3TS U1446 ( .A(n4608), .Y(n4972) );
BUFX3TS U1447 ( .A(n4922), .Y(n4967) );
BUFX3TS U1448 ( .A(n4608), .Y(n4878) );
BUFX3TS U1449 ( .A(n4078), .Y(n4072) );
OR3X1TS U1450 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_1033_n1), .Y(n5076) );
OAI2BB1X1TS U1451 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1N(n5223), .B0(
n4201), .Y(n4265) );
INVX2TS U1452 ( .A(n3769), .Y(n3753) );
BUFX3TS U1453 ( .A(n3949), .Y(n4877) );
CLKINVX3TS U1454 ( .A(n1175), .Y(n4273) );
BUFX3TS U1455 ( .A(n4864), .Y(n4861) );
BUFX3TS U1456 ( .A(n1691), .Y(n4851) );
BUFX3TS U1457 ( .A(n4825), .Y(n4831) );
INVX3TS U1458 ( .A(n4097), .Y(n1177) );
NAND2X2TS U1459 ( .A(n1545), .B(n3675), .Y(n3813) );
INVX2TS U1460 ( .A(n4862), .Y(n4858) );
NAND2X2TS U1461 ( .A(n3464), .B(n3463), .Y(n3797) );
NAND2X2TS U1462 ( .A(n3677), .B(n3676), .Y(n3794) );
CLKBUFX2TS U1463 ( .A(n3961), .Y(n5252) );
INVX1TS U1464 ( .A(n3960), .Y(n5273) );
BUFX3TS U1465 ( .A(n1691), .Y(n4856) );
OAI22X1TS U1466 ( .A0(n4262), .A1(n1164), .B0(n4267), .B1(n1176), .Y(n4207)
);
OAI22X1TS U1467 ( .A0(n4268), .A1(n1164), .B0(n4275), .B1(n1176), .Y(n4220)
);
OAI22X1TS U1468 ( .A0(n4246), .A1(n1164), .B0(n4251), .B1(n1175), .Y(n4169)
);
OAI22X1TS U1469 ( .A0(n4267), .A1(n1166), .B0(n4243), .B1(n1176), .Y(n4205)
);
BUFX3TS U1470 ( .A(n4825), .Y(n4833) );
BUFX3TS U1471 ( .A(n5017), .Y(n4987) );
BUFX3TS U1472 ( .A(n4978), .Y(n5016) );
INVX6TS U1473 ( .A(n4221), .Y(n1166) );
BUFX3TS U1474 ( .A(n3930), .Y(n5019) );
INVX6TS U1475 ( .A(n4168), .Y(n1175) );
INVX6TS U1476 ( .A(n4168), .Y(n1176) );
INVX6TS U1477 ( .A(n4221), .Y(n1165) );
INVX2TS U1478 ( .A(n1161), .Y(n1163) );
NAND2X1TS U1479 ( .A(n865), .B(FPSENCOS_cont_iter_out[0]), .Y(n5025) );
NOR2X6TS U1480 ( .A(n3464), .B(n3463), .Y(n3796) );
NOR2X6TS U1481 ( .A(n3462), .B(n3461), .Y(n3830) );
BUFX3TS U1482 ( .A(n4864), .Y(n4862) );
NOR2X2TS U1483 ( .A(n2839), .B(n2803), .Y(n2806) );
NAND2X1TS U1484 ( .A(n947), .B(n4101), .Y(n4097) );
CLKBUFX2TS U1485 ( .A(n5325), .Y(n5318) );
NOR3X1TS U1486 ( .A(FPADDSUB_Raw_mant_NRM_SWR[2]), .B(n4036), .C(n5127), .Y(
n4277) );
BUFX3TS U1487 ( .A(n3949), .Y(n4922) );
NOR2X4TS U1488 ( .A(n5337), .B(n5338), .Y(n1036) );
NOR2X2TS U1489 ( .A(n1431), .B(n1423), .Y(n1421) );
BUFX3TS U1490 ( .A(n4961), .Y(n4964) );
OR2X2TS U1491 ( .A(FPSENCOS_cont_iter_out[2]), .B(n4788), .Y(n1691) );
BUFX4TS U1492 ( .A(n4999), .Y(n5017) );
BUFX4TS U1493 ( .A(n4978), .Y(n4989) );
NAND2X1TS U1494 ( .A(n5096), .B(FPSENCOS_cont_iter_out[3]), .Y(n3925) );
INVX2TS U1495 ( .A(n1427), .Y(n1426) );
INVX8TS U1496 ( .A(n4224), .Y(n1164) );
INVX2TS U1497 ( .A(n1670), .Y(n1138) );
NOR3X6TS U1498 ( .A(n4163), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n4083),
.Y(n5337) );
NAND3X2TS U1499 ( .A(n5097), .B(n5098), .C(n1134), .Y(n4788) );
NOR2X6TS U1500 ( .A(n4167), .B(n947), .Y(n4221) );
NOR2X4TS U1501 ( .A(n1181), .B(operation[2]), .Y(n3930) );
AND3X2TS U1502 ( .A(n4163), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n4162),
.Y(n5338) );
NOR2X1TS U1503 ( .A(n1427), .B(n3460), .Y(n1425) );
INVX2TS U1504 ( .A(n4813), .Y(n4864) );
NOR2X4TS U1505 ( .A(n4970), .B(n4872), .Y(n3949) );
NAND2X1TS U1506 ( .A(n3812), .B(n3772), .Y(n3763) );
BUFX3TS U1507 ( .A(n4608), .Y(n4961) );
NOR2X2TS U1508 ( .A(n4306), .B(n3997), .Y(n4136) );
INVX2TS U1509 ( .A(n5027), .Y(n4978) );
NOR2X4TS U1510 ( .A(n4970), .B(operation[2]), .Y(n4999) );
NAND2X1TS U1511 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n4872) );
AND4X1TS U1512 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n4161), .Y(n4162) );
INVX2TS U1513 ( .A(n910), .Y(n4719) );
NAND2X1TS U1514 ( .A(n1686), .B(n3588), .Y(n3578) );
NAND2X1TS U1515 ( .A(n1684), .B(n3624), .Y(n3617) );
NAND2X1TS U1516 ( .A(n3433), .B(n3432), .Y(n3434) );
NAND2X1TS U1517 ( .A(n1606), .B(n3545), .Y(n3407) );
NAND2X1TS U1518 ( .A(n3537), .B(n3543), .Y(n3538) );
CLKINVX3TS U1519 ( .A(n4101), .Y(n4167) );
INVX2TS U1520 ( .A(n1433), .Y(n1432) );
AOI21X2TS U1521 ( .A0(n1370), .A1(n1488), .B0(n1300), .Y(n3408) );
INVX4TS U1522 ( .A(n1332), .Y(n1593) );
XNOR2X2TS U1523 ( .A(DP_OP_26J307_123_9022_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n4163) );
OR4X2TS U1524 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n4082), .Y(n4083) );
NAND4BBX1TS U1525 ( .AN(n4674), .BN(n4673), .C(n4672), .D(n4671), .Y(n4675)
);
OR2X4TS U1526 ( .A(n3225), .B(n3224), .Y(n3851) );
NAND2X1TS U1527 ( .A(n1395), .B(n1477), .Y(n1434) );
NAND3BXLTS U1528 ( .AN(n4659), .B(n4657), .C(n4656), .Y(n4677) );
NAND2X2TS U1529 ( .A(n3227), .B(n3226), .Y(n3847) );
NAND2X2TS U1530 ( .A(n1482), .B(n1481), .Y(n1435) );
AOI211X1TS U1531 ( .A0(n4689), .A1(n4670), .B0(n4669), .C0(n4668), .Y(n4676)
);
NOR2X1TS U1532 ( .A(n3448), .B(n3452), .Y(n1430) );
CLKXOR2X2TS U1533 ( .A(n3670), .B(n3669), .Y(n3812) );
BUFX3TS U1534 ( .A(n4004), .Y(n4608) );
INVX2TS U1535 ( .A(n1162), .Y(n4306) );
AOI2BB2X1TS U1536 ( .B0(n4621), .B1(n4672), .A0N(n4620), .A1N(n4619), .Y(
n4678) );
NAND2X2TS U1537 ( .A(n4929), .B(operation[2]), .Y(n5027) );
NAND2X1TS U1538 ( .A(n986), .B(n985), .Y(n3465) );
INVX2TS U1539 ( .A(n1087), .Y(n1154) );
NAND2XLTS U1540 ( .A(FPSENCOS_cont_var_out[1]), .B(n5117), .Y(n3937) );
INVX2TS U1541 ( .A(n1088), .Y(n1152) );
INVX2TS U1542 ( .A(n1087), .Y(n1155) );
XOR2X1TS U1543 ( .A(n3493), .B(n3492), .Y(n3764) );
INVX2TS U1544 ( .A(n1156), .Y(n1157) );
INVX2TS U1545 ( .A(n1156), .Y(n1158) );
AOI211X2TS U1546 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n5130), .B0(n4619),
.C0(n4617), .Y(n4672) );
NAND2X1TS U1547 ( .A(n3441), .B(n3439), .Y(n3217) );
INVX2TS U1548 ( .A(n3539), .Y(n3656) );
NOR2X4TS U1549 ( .A(n3025), .B(n3024), .Y(n1332) );
NAND2X4TS U1550 ( .A(n1370), .B(n3449), .Y(n1433) );
NOR2X1TS U1551 ( .A(n3440), .B(n3441), .Y(n1480) );
NOR2X1TS U1552 ( .A(n3730), .B(n3734), .Y(n3737) );
CLKINVX2TS U1553 ( .A(n1395), .Y(n1482) );
NAND2X1TS U1554 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n3997) );
CLKAND2X2TS U1555 ( .A(n3444), .B(n3441), .Y(n1477) );
NAND2X2TS U1556 ( .A(n3023), .B(n1661), .Y(n3858) );
AOI21X2TS U1557 ( .A0(n1300), .A1(n1606), .B0(n1605), .Y(n1603) );
NAND2X2TS U1558 ( .A(n3025), .B(n3024), .Y(n3855) );
NOR2X2TS U1559 ( .A(n3623), .B(n3547), .Y(n3549) );
OAI211X1TS U1560 ( .A0(n4616), .A1(n4674), .B0(n4615), .C0(n4614), .Y(n4621)
);
OAI31X1TS U1561 ( .A0(n4654), .A1(n4653), .A2(n4652), .B0(n4651), .Y(n4657)
);
NOR2X1TS U1562 ( .A(n3444), .B(n3440), .Y(n1481) );
INVX2TS U1563 ( .A(n1161), .Y(n1162) );
BUFX4TS U1564 ( .A(n4883), .Y(n4929) );
NAND2X1TS U1565 ( .A(FPSENCOS_d_ff1_operation_out), .B(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(n4814) );
BUFX3TS U1566 ( .A(n5169), .Y(n4217) );
BUFX8TS U1567 ( .A(n1447), .Y(n1370) );
INVX2TS U1568 ( .A(FPADDSUB_left_right_SHT2), .Y(n1161) );
INVX6TS U1569 ( .A(n1300), .Y(n3628) );
INVX2TS U1570 ( .A(n3542), .Y(n1606) );
INVX2TS U1571 ( .A(n3439), .Y(n3440) );
NOR2XLTS U1572 ( .A(n3732), .B(n3708), .Y(n3710) );
NOR2X1TS U1573 ( .A(n4838), .B(FPADDSUB_intDX_EWSW[30]), .Y(n4619) );
INVX2TS U1574 ( .A(n1670), .Y(n5224) );
NAND2X2TS U1575 ( .A(n1440), .B(n1357), .Y(n1439) );
NAND2X2TS U1576 ( .A(n3451), .B(n3450), .Y(n3452) );
AOI21X1TS U1577 ( .A0(n3744), .A1(n3724), .B0(n3723), .Y(n3729) );
BUFX3TS U1578 ( .A(n4883), .Y(n4970) );
OA22X1TS U1579 ( .A0(n5114), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n4666), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n4689) );
OAI2BB2XLTS U1580 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n4636), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n5183), .Y(n4649) );
OAI2BB2XLTS U1581 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n4646), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n4645), .Y(n4647) );
AND2X6TS U1582 ( .A(n1686), .B(n1684), .Y(n1646) );
OAI2BB2XLTS U1583 ( .B0(n4644), .B1(n4652), .A0N(n4643), .A1N(n4642), .Y(
n4648) );
NAND2X4TS U1584 ( .A(n3449), .B(n3372), .Y(n3623) );
NAND2X1TS U1585 ( .A(n3731), .B(n3706), .Y(n3708) );
NAND2BX1TS U1586 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n4613) );
NAND2X2TS U1587 ( .A(n1546), .B(n3158), .Y(n1357) );
NOR2X1TS U1588 ( .A(n4836), .B(FPADDSUB_intDX_EWSW[29]), .Y(n4617) );
BUFX4TS U1589 ( .A(n3428), .Y(n3448) );
BUFX3TS U1590 ( .A(n3366), .Y(n3439) );
OR2X2TS U1591 ( .A(n4228), .B(n5339), .Y(n1670) );
BUFX4TS U1592 ( .A(n1180), .Y(n4883) );
NOR2X1TS U1593 ( .A(n5193), .B(FPADDSUB_intDX_EWSW[25]), .Y(n4673) );
NOR2X6TS U1594 ( .A(n3406), .B(n3405), .Y(n3542) );
NOR2X1TS U1595 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n4283), .Y(n4041) );
NOR2X6TS U1596 ( .A(n3536), .B(n3535), .Y(n3544) );
NAND2X1TS U1597 ( .A(n2750), .B(n2871), .Y(n2751) );
INVX2TS U1598 ( .A(FPADDSUB_intDY_EWSW[29]), .Y(n4836) );
NOR2X1TS U1599 ( .A(n5192), .B(FPADDSUB_intDX_EWSW[17]), .Y(n4659) );
NAND2X2TS U1600 ( .A(n3536), .B(n3535), .Y(n3543) );
NOR2BX2TS U1601 ( .AN(n988), .B(n987), .Y(n5339) );
OR2X4TS U1602 ( .A(n3616), .B(n3615), .Y(n1684) );
NAND2X2TS U1603 ( .A(n3577), .B(n3576), .Y(n3588) );
NAND2X2TS U1604 ( .A(n3616), .B(n3615), .Y(n3624) );
NOR2X6TS U1605 ( .A(n3367), .B(n3281), .Y(n3449) );
OAI2BB1X1TS U1606 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[18]), .A1N(n4091), .B0(
n4281), .Y(n4040) );
AOI21X1TS U1607 ( .A0(n2675), .A1(n2674), .B0(n2673), .Y(n2682) );
NOR2X2TS U1608 ( .A(n5131), .B(n3909), .Y(n4278) );
INVX4TS U1609 ( .A(operation[1]), .Y(n1180) );
NAND2X1TS U1610 ( .A(n3702), .B(n3701), .Y(n3735) );
NOR2X1TS U1611 ( .A(n3702), .B(n3701), .Y(n3730) );
INVX2TS U1612 ( .A(n1523), .Y(n2685) );
INVX2TS U1613 ( .A(n3092), .Y(n1573) );
NOR2X4TS U1614 ( .A(n3216), .B(n3215), .Y(n3281) );
NAND2BX1TS U1615 ( .AN(n4048), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n4038)
);
NAND2BX1TS U1616 ( .AN(n3908), .B(FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n4281)
);
OAI21X1TS U1617 ( .A0(n3476), .A1(n3475), .B0(n3474), .Y(n3477) );
NOR2X2TS U1618 ( .A(n3725), .B(n3718), .Y(n3731) );
NAND2X1TS U1619 ( .A(n3490), .B(n3489), .Y(n3690) );
NAND2X1TS U1620 ( .A(n3695), .B(n3688), .Y(n3726) );
NAND2X1TS U1621 ( .A(n3422), .B(n3421), .Y(n3474) );
NAND2X1TS U1622 ( .A(n3499), .B(n3498), .Y(n3689) );
NAND2X1TS U1623 ( .A(n3696), .B(n3359), .Y(n3719) );
NAND2X1TS U1624 ( .A(n3470), .B(n3471), .Y(n3584) );
NAND2X1TS U1625 ( .A(n3466), .B(n3467), .Y(n3659) );
CMPR32X2TS U1626 ( .A(n3642), .B(n3641), .C(n3640), .CO(n3643), .S(n3630) );
NAND2X1TS U1627 ( .A(n3487), .B(n3488), .Y(n3667) );
NOR2X4TS U1628 ( .A(n2939), .B(n2940), .Y(n3026) );
NOR2X6TS U1629 ( .A(n3147), .B(n3148), .Y(n3160) );
NOR2X2TS U1630 ( .A(n3696), .B(n3359), .Y(n3718) );
NOR2X2TS U1631 ( .A(n3499), .B(n3498), .Y(n3691) );
NOR2X2TS U1632 ( .A(n3688), .B(n3695), .Y(n3725) );
NAND2X1TS U1633 ( .A(n1451), .B(n1453), .Y(n2326) );
NAND2X1TS U1634 ( .A(n2572), .B(n2571), .Y(n2575) );
NOR2X2TS U1635 ( .A(n3487), .B(n3488), .Y(n3666) );
NAND2XLTS U1636 ( .A(n1076), .B(n2325), .Y(n2327) );
OA22X1TS U1637 ( .A0(n5110), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n4645), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n4650) );
INVX2TS U1638 ( .A(n1080), .Y(n1127) );
AOI21X2TS U1639 ( .A0(n2675), .A1(n2308), .B0(n2547), .Y(n2324) );
AOI21X2TS U1640 ( .A0(n4529), .A1(n4528), .B0(n3890), .Y(n4521) );
AOI21X1TS U1641 ( .A0(n2675), .A1(n2335), .B0(n2334), .Y(n2340) );
CMPR32X2TS U1642 ( .A(n3555), .B(n3554), .C(n3553), .CO(n3595), .S(n3573) );
OR2X2TS U1643 ( .A(FPMULT_FSM_selector_B[1]), .B(n5116), .Y(n4318) );
NOR2X1TS U1644 ( .A(n2329), .B(n2332), .Y(n2335) );
NOR2X1TS U1645 ( .A(n2665), .B(n2664), .Y(n2566) );
NOR2X1TS U1646 ( .A(n2665), .B(n2552), .Y(n2554) );
INVX3TS U1647 ( .A(n1448), .Y(n2573) );
NAND2X1TS U1648 ( .A(n1625), .B(n1624), .Y(n2670) );
OAI21X2TS U1649 ( .A0(n2672), .A1(n2664), .B0(n2671), .Y(n2565) );
OAI21X2TS U1650 ( .A0(n2672), .A1(n2577), .B0(n2576), .Y(n2578) );
ADDFHX1TS U1651 ( .A(n3611), .B(n3610), .CI(n3609), .CO(n3640), .S(n3614) );
OAI21X2TS U1652 ( .A0(n4387), .A1(n4384), .B0(n4385), .Y(n4529) );
OAI21X1TS U1653 ( .A0(n2333), .A1(n2332), .B0(n2331), .Y(n2334) );
NAND2X1TS U1654 ( .A(n3415), .B(n3414), .Y(n3455) );
NAND2X1TS U1655 ( .A(n3222), .B(n3221), .Y(n3409) );
CMPR32X2TS U1656 ( .A(n1084), .B(n3634), .C(n3633), .CO(n3635), .S(n3638) );
NOR2X1TS U1657 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n910), .Y(n3956) );
NOR2X6TS U1658 ( .A(n2661), .B(n2660), .Y(n2870) );
NAND2X1TS U1659 ( .A(n1458), .B(n1456), .Y(n2184) );
NAND2X1TS U1660 ( .A(n2010), .B(n1995), .Y(n2011) );
NAND2X1TS U1661 ( .A(n2001), .B(n2000), .Y(n2002) );
NAND2XLTS U1662 ( .A(n1541), .B(n2128), .Y(n2075) );
NAND2X1TS U1663 ( .A(n2020), .B(n2019), .Y(n2021) );
AOI21X2TS U1664 ( .A0(n2675), .A1(n2328), .B0(n2330), .Y(n2127) );
AOI21X2TS U1665 ( .A0(n2761), .A1(n1998), .B0(n1997), .Y(n2003) );
AOI21X2TS U1666 ( .A0(n2103), .A1(n2077), .B0(n2076), .Y(n2101) );
NAND2X1TS U1667 ( .A(n2183), .B(n1683), .Y(n2174) );
AOI21X1TS U1668 ( .A0(n1682), .A1(n2074), .B0(n2073), .Y(n2130) );
CMPR32X2TS U1669 ( .A(n3807), .B(n3608), .C(n3607), .CO(n3637), .S(n3610) );
OAI21X1TS U1670 ( .A0(n3328), .A1(n3327), .B0(n3326), .Y(n1512) );
BUFX8TS U1671 ( .A(n2103), .Y(n2675) );
XNOR2X2TS U1672 ( .A(n3142), .B(n3141), .Y(n1392) );
INVX4TS U1673 ( .A(n1468), .Y(n2592) );
OAI21X2TS U1674 ( .A0(n1996), .A1(n2009), .B0(n1995), .Y(n1997) );
OAI22X1TS U1675 ( .A0(n3397), .A1(n3516), .B0(n3515), .B1(n3514), .Y(n3530)
);
ADDFHX2TS U1676 ( .A(n3378), .B(n3377), .CI(n3376), .CO(n3506), .S(n3404) );
NOR2X2TS U1677 ( .A(n2104), .B(n2107), .Y(n2328) );
XNOR2X1TS U1678 ( .A(n3571), .B(n3526), .Y(n3528) );
XNOR2X1TS U1679 ( .A(n3527), .B(n3526), .Y(n3567) );
OAI21X1TS U1680 ( .A0(n4391), .A1(n4390), .B0(n4389), .Y(n4392) );
NAND2X1TS U1681 ( .A(n3067), .B(n3068), .Y(n1492) );
OAI21X2TS U1682 ( .A0(n3080), .A1(n3079), .B0(n3077), .Y(n3078) );
NAND2X1TS U1683 ( .A(n3016), .B(n3015), .Y(n3088) );
NAND2X1TS U1684 ( .A(n3022), .B(n3021), .Y(n3089) );
CMPR32X2TS U1685 ( .A(n3605), .B(n3604), .C(n3603), .CO(n3606), .S(n3560) );
NOR2X2TS U1686 ( .A(n3067), .B(n3068), .Y(n1493) );
OAI22X2TS U1687 ( .A0(n3265), .A1(n3264), .B0(n1396), .B1(n3263), .Y(n3284)
);
NOR2X1TS U1688 ( .A(n3016), .B(n3015), .Y(n3090) );
ADDFX2TS U1689 ( .A(n3513), .B(n3512), .CI(n3511), .CO(n3746), .S(n3711) );
AOI21X1TS U1690 ( .A0(n4583), .A1(n4341), .B0(n4340), .Y(n4358) );
NAND2X2TS U1691 ( .A(n2537), .B(n1626), .Y(n2664) );
CMPR32X2TS U1692 ( .A(n1689), .B(n2957), .C(n3559), .CO(n3808), .S(n3745) );
AOI21X1TS U1693 ( .A0(n4569), .A1(n3881), .B0(n3880), .Y(n4329) );
XNOR2X2TS U1694 ( .A(n3602), .B(n1126), .Y(n3807) );
CLKINVX2TS U1695 ( .A(n3695), .Y(n3293) );
CLKINVX2TS U1696 ( .A(n3696), .Y(n3334) );
INVX2TS U1697 ( .A(n3688), .Y(n3295) );
INVX2TS U1698 ( .A(n3291), .Y(n3333) );
CLKINVX2TS U1699 ( .A(n3335), .Y(n3401) );
AO21XLTS U1700 ( .A0(n1209), .A1(n3380), .B0(n1211), .Y(n3513) );
INVX3TS U1701 ( .A(n3498), .Y(n3294) );
INVX2TS U1702 ( .A(n1570), .Y(n2721) );
NAND2X2TS U1703 ( .A(n3165), .B(n1575), .Y(n3234) );
NAND2X1TS U1704 ( .A(n3265), .B(n3208), .Y(n2331) );
XOR2X2TS U1705 ( .A(n3080), .B(n3079), .Y(n2977) );
NOR2X4TS U1706 ( .A(n2400), .B(n2570), .Y(n2403) );
NOR2X2TS U1707 ( .A(n2332), .B(n2336), .Y(n2306) );
CMPR32X2TS U1708 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[20]), .C(n3510),
.CO(n3559), .S(n3512) );
NAND2X2TS U1709 ( .A(n2466), .B(n2465), .Y(n2468) );
CMPR32X2TS U1710 ( .A(n3275), .B(n3274), .C(n3273), .CO(n3314), .S(n3277) );
INVX2TS U1711 ( .A(n3257), .Y(n3318) );
INVX2TS U1712 ( .A(n3256), .Y(n3319) );
CMPR32X2TS U1713 ( .A(n2561), .B(n2560), .C(n2559), .CO(n2676), .S(n2556) );
NAND2X1TS U1714 ( .A(n2464), .B(n2460), .Y(n2465) );
NOR2X1TS U1715 ( .A(n3558), .B(n1126), .Y(n3510) );
NAND2X2TS U1716 ( .A(n3055), .B(n3054), .Y(n2106) );
NOR2X4TS U1717 ( .A(n3265), .B(n3208), .Y(n2332) );
NOR2X1TS U1718 ( .A(n1310), .B(n1636), .Y(n3605) );
NAND2X4TS U1719 ( .A(n1517), .B(n1516), .Y(n2725) );
INVX3TS U1720 ( .A(n1444), .Y(n1445) );
NOR2X2TS U1721 ( .A(n3292), .B(n3291), .Y(n2577) );
NAND2X2TS U1722 ( .A(n3099), .B(n3164), .Y(n2105) );
NOR2X4TS U1723 ( .A(n3099), .B(n3164), .Y(n2107) );
NAND2X1TS U1724 ( .A(n3163), .B(n1574), .Y(n1575) );
NAND2X2TS U1725 ( .A(n2235), .B(n2234), .Y(n2325) );
OAI21X2TS U1726 ( .A0(n1999), .A1(n1995), .B0(n2000), .Y(n1810) );
NOR2X6TS U1727 ( .A(n2288), .B(n2289), .Y(n2400) );
ADDFX2TS U1728 ( .A(n3385), .B(n3384), .CI(n3383), .CO(n3712), .S(n3701) );
ADDFHX2TS U1729 ( .A(n2922), .B(n2921), .CI(n2920), .CO(n2983), .S(n2918) );
XNOR2X1TS U1730 ( .A(n3184), .B(n3526), .Y(n3352) );
XOR2X2TS U1731 ( .A(n3355), .B(n3353), .Y(n3313) );
XNOR2X1TS U1732 ( .A(n3571), .B(n1145), .Y(n3337) );
INVX2TS U1733 ( .A(n3499), .Y(n3255) );
CLKAND2X2TS U1734 ( .A(n3470), .B(n3471), .Y(n1082) );
INVX3TS U1735 ( .A(n3468), .Y(n2921) );
OAI22X2TS U1736 ( .A0(n3480), .A1(n2651), .B0(n2650), .B1(n2649), .Y(n2728)
);
OAI22X1TS U1737 ( .A0(n2734), .A1(n3310), .B0(n2882), .B1(n3339), .Y(n2922)
);
XOR2X2TS U1738 ( .A(n2504), .B(n2501), .Y(n2414) );
NOR2X6TS U1739 ( .A(n2018), .B(n2016), .Y(n1992) );
XOR2X2TS U1740 ( .A(n2733), .B(n2653), .Y(n2727) );
NAND2X2TS U1741 ( .A(n2658), .B(n1515), .Y(n1516) );
XNOR2X1TS U1742 ( .A(n3524), .B(n1145), .Y(n3300) );
OAI22X1TS U1743 ( .A0(n3244), .A1(n3243), .B0(n3242), .B1(n3241), .Y(n3290)
);
CMPR32X2TS U1744 ( .A(n1655), .B(n3382), .C(n3381), .CO(n3511), .S(n3384) );
CLKINVX6TS U1745 ( .A(n2926), .Y(n2985) );
INVX2TS U1746 ( .A(n2961), .Y(n3074) );
INVX2TS U1747 ( .A(n3469), .Y(n2933) );
CMPR32X2TS U1748 ( .A(n2545), .B(n2544), .C(n2543), .CO(n2555), .S(n2539) );
CMPR32X2TS U1749 ( .A(FPMULT_Op_MY[19]), .B(n5045), .C(n3341), .CO(n3385),
.S(n3342) );
CMPR32X2TS U1750 ( .A(n1669), .B(n3302), .C(n3301), .CO(n3358), .S(n3307) );
OAI2BB1X2TS U1751 ( .A0N(n2233), .A1N(n2230), .B0(n2232), .Y(n2235) );
OR2X6TS U1752 ( .A(n1455), .B(n1454), .Y(n2183) );
CMPR32X2TS U1753 ( .A(n2536), .B(n2535), .C(n2534), .CO(n2538), .S(n2526) );
NOR2X1TS U1754 ( .A(n2647), .B(n2648), .Y(n2651) );
NAND2X2TS U1755 ( .A(n2434), .B(n2404), .Y(n4018) );
NAND2X2TS U1756 ( .A(n2491), .B(n2494), .Y(n4022) );
INVX2TS U1757 ( .A(n1553), .Y(n1219) );
OAI2BB1X2TS U1758 ( .A0N(n2442), .A1N(n2441), .B0(n2440), .Y(n2500) );
NOR2X4TS U1759 ( .A(n2976), .B(n2961), .Y(n1999) );
OAI21X2TS U1760 ( .A0(n2886), .A1(n2887), .B0(n2885), .Y(n1381) );
INVX3TS U1761 ( .A(n1683), .Y(n1452) );
OAI22X1TS U1762 ( .A0(n3130), .A1(n3310), .B0(n3183), .B1(n1225), .Y(n3188)
);
XNOR2X2TS U1763 ( .A(n2884), .B(n2714), .Y(n2720) );
CLKINVX2TS U1764 ( .A(n1569), .Y(n1495) );
OAI22X2TS U1765 ( .A0(n3258), .A1(n1221), .B0(n3185), .B1(n1039), .Y(n3262)
);
XOR2X2TS U1766 ( .A(n2989), .B(n1287), .Y(n2984) );
XOR2X1TS U1767 ( .A(n3632), .B(n1514), .Y(n3311) );
XNOR2X2TS U1768 ( .A(n3312), .B(n3526), .Y(n3272) );
XNOR2X2TS U1769 ( .A(n2968), .B(n3526), .Y(n3299) );
CLKXOR2X2TS U1770 ( .A(n3485), .B(n3069), .Y(n1498) );
NAND2X2TS U1771 ( .A(n1367), .B(n2599), .Y(n1363) );
OAI22X2TS U1772 ( .A0(n3345), .A1(n1144), .B0(n3398), .B1(n1292), .Y(n3387)
);
XNOR2X1TS U1773 ( .A(n5040), .B(FPMULT_Op_MX[11]), .Y(n2558) );
XNOR2X1TS U1774 ( .A(n3270), .B(n3526), .Y(n3174) );
CMPR32X2TS U1775 ( .A(n2967), .B(n2966), .C(n2965), .CO(n3053), .S(n2963) );
INVX2TS U1776 ( .A(n2976), .Y(n3051) );
BUFX3TS U1777 ( .A(n2926), .Y(n1809) );
NAND2X1TS U1778 ( .A(n2398), .B(n2397), .Y(n2399) );
INVX4TS U1779 ( .A(n3055), .Y(n3097) );
INVX1TS U1780 ( .A(n3312), .Y(n3345) );
OAI21X1TS U1781 ( .A0(n2230), .A1(n2233), .B0(n2231), .Y(n2232) );
NOR2X1TS U1782 ( .A(n2769), .B(n2824), .Y(n1843) );
NAND2X4TS U1783 ( .A(n2348), .B(n1616), .Y(n2464) );
OR2X4TS U1784 ( .A(n1989), .B(n1988), .Y(n1682) );
OAI22X1TS U1785 ( .A0(n3134), .A1(n3516), .B0(n3185), .B1(n3515), .Y(n3169)
);
OAI22X1TS U1786 ( .A0(n2679), .A1(n2294), .B0(n1149), .B1(n2318), .Y(n2317)
);
INVX2TS U1787 ( .A(n3526), .Y(n3599) );
OAI21X2TS U1788 ( .A0(n2769), .A1(n2825), .B0(n2770), .Y(n1842) );
XNOR2X1TS U1789 ( .A(n3524), .B(n2878), .Y(n2604) );
CMPR32X2TS U1790 ( .A(n5039), .B(n5038), .C(n3245), .CO(n3308), .S(n3250) );
NAND2X4TS U1791 ( .A(n2994), .B(n2993), .Y(n1569) );
CLKXOR2X2TS U1792 ( .A(n3467), .B(n2998), .Y(n2912) );
ADDFHX2TS U1793 ( .A(n2410), .B(n2409), .CI(n2408), .CO(n2501), .S(n2416) );
CLKXOR2X2TS U1794 ( .A(n2991), .B(n2988), .Y(n1287) );
NAND2X1TS U1795 ( .A(n2154), .B(n2131), .Y(n2825) );
INVX2TS U1796 ( .A(n2389), .Y(n2410) );
INVX2TS U1797 ( .A(n2491), .Y(n2599) );
NAND2X1TS U1798 ( .A(n2062), .B(n2056), .Y(n2846) );
OAI2BB1X2TS U1799 ( .A0N(n2691), .A1N(n2690), .B0(n1618), .Y(n2924) );
NOR2X1TS U1800 ( .A(n1216), .B(n1638), .Y(n2561) );
NOR2X2TS U1801 ( .A(n2154), .B(n2131), .Y(n2824) );
CLKAND2X2TS U1802 ( .A(n1524), .B(n1548), .Y(n2607) );
NOR2X1TS U1803 ( .A(n1437), .B(n3340), .Y(n1436) );
INVX2TS U1804 ( .A(n1367), .Y(n1366) );
OAI21X2TS U1805 ( .A0(n2413), .A1(n2412), .B0(n2411), .Y(n1522) );
OAI22X1TS U1806 ( .A0(n2322), .A1(n2298), .B0(n958), .B1(n2321), .Y(n2313)
);
XNOR2X1TS U1807 ( .A(n5040), .B(FPMULT_Op_MX[8]), .Y(n2318) );
XNOR2X1TS U1808 ( .A(n5040), .B(FPMULT_Op_MX[10]), .Y(n2542) );
XNOR2X1TS U1809 ( .A(n3524), .B(n3128), .Y(n3032) );
ADDFHX1TS U1810 ( .A(n2293), .B(n2292), .CI(n2291), .CO(n2311), .S(n2300) );
OAI22X2TS U1811 ( .A0(n2713), .A1(n1142), .B0(n2880), .B1(n1213), .Y(n2887)
);
NAND2X2TS U1812 ( .A(n1327), .B(n1326), .Y(n1325) );
NAND2X2TS U1813 ( .A(n1615), .B(n1614), .Y(n1613) );
XNOR2X1TS U1814 ( .A(n5040), .B(FPMULT_Op_MX[9]), .Y(n2533) );
CLKXOR2X2TS U1815 ( .A(n3571), .B(n3338), .Y(n3266) );
AO21XLTS U1816 ( .A0(n1911), .A1(n2124), .B0(n1666), .Y(n2291) );
INVX4TS U1817 ( .A(n3419), .Y(n2412) );
NAND2X1TS U1818 ( .A(n2456), .B(n2506), .Y(n2457) );
OR2X2TS U1819 ( .A(n1959), .B(n1983), .Y(n1629) );
NAND2X2TS U1820 ( .A(n2434), .B(n1328), .Y(n1327) );
OAI22X2TS U1821 ( .A0(n2717), .A1(n3269), .B0(n2877), .B1(n1222), .Y(n2909)
);
NAND2X2TS U1822 ( .A(n3060), .B(n3059), .Y(n3061) );
OAI22X1TS U1823 ( .A0(n3558), .A1(FPMULT_Op_MY[17]), .B0(n3557), .B1(n5045),
.Y(n3194) );
OAI22X2TS U1824 ( .A0(n1039), .A1(n2521), .B0(n2643), .B1(n3515), .Y(n2645)
);
OAI21X2TS U1825 ( .A0(n3115), .A1(n3114), .B0(n3113), .Y(n3190) );
OAI22X1TS U1826 ( .A0(n1225), .A1(n1437), .B0(n1592), .B1(n3340), .Y(n2644)
);
XOR2X2TS U1827 ( .A(n2892), .B(n2895), .Y(n2703) );
OAI22X1TS U1828 ( .A0(n1209), .A1(n3107), .B0(n3380), .B1(n3196), .Y(n3193)
);
AND2X2TS U1829 ( .A(n1554), .B(n1208), .Y(n1555) );
OAI22X1TS U1830 ( .A0(n2679), .A1(n2123), .B0(n1149), .B1(n2294), .Y(n2292)
);
OAI22X2TS U1831 ( .A0(n2384), .A1(n1142), .B0(n2459), .B1(n1213), .Y(n2411)
);
OAI22X2TS U1832 ( .A0(n1060), .A1(n3195), .B0(n1214), .B1(n1160), .Y(n3239)
);
XNOR2X2TS U1833 ( .A(n1172), .B(FPMULT_Op_MX[10]), .Y(n2321) );
XNOR2X2TS U1834 ( .A(n1172), .B(FPMULT_Op_MX[11]), .Y(n2532) );
XNOR2X2TS U1835 ( .A(n1469), .B(n1514), .Y(n2882) );
CMPR32X2TS U1836 ( .A(n1732), .B(n1731), .C(n1730), .CO(n1798), .S(n1761) );
NAND2X1TS U1837 ( .A(n1924), .B(n1923), .Y(n1925) );
OAI2BB1X2TS U1838 ( .A0N(n1748), .A1N(n1749), .B0(n1705), .Y(n1745) );
INVX3TS U1839 ( .A(n3420), .Y(n2442) );
NOR2X1TS U1840 ( .A(n1279), .B(n3247), .Y(n3197) );
NAND2X1TS U1841 ( .A(n2480), .B(n1322), .Y(n1317) );
OAI21X2TS U1842 ( .A0(n2895), .A1(n2894), .B0(n2892), .Y(n2893) );
OAI2BB1X2TS U1843 ( .A0N(n1922), .A1N(n1921), .B0(n1920), .Y(n1926) );
INVX4TS U1844 ( .A(n3632), .Y(n3527) );
XOR2X1TS U1845 ( .A(n1750), .B(n1749), .Y(n1890) );
OAI22X2TS U1846 ( .A0(n3200), .A1(n2477), .B0(n3199), .B1(n2624), .Y(n2613)
);
NAND2BX2TS U1847 ( .AN(n3070), .B(n1533), .Y(n1587) );
ADDFHX2TS U1848 ( .A(n2168), .B(n2167), .CI(n2166), .CO(n2233), .S(n2170) );
XNOR2X2TS U1849 ( .A(n1172), .B(FPMULT_Op_MX[9]), .Y(n2298) );
XNOR2X2TS U1850 ( .A(n3172), .B(n3526), .Y(n3103) );
ADDFHX2TS U1851 ( .A(n3038), .B(n3037), .CI(n3036), .CO(n3139), .S(n3058) );
XNOR2X2TS U1852 ( .A(n3312), .B(n3336), .Y(n3134) );
XNOR2X2TS U1853 ( .A(n1514), .B(n3131), .Y(n1437) );
XOR2X2TS U1854 ( .A(n2405), .B(n2406), .Y(n1581) );
BUFX3TS U1855 ( .A(n2972), .Y(n3526) );
CLKINVX6TS U1856 ( .A(n3421), .Y(n2492) );
INVX6TS U1857 ( .A(n1399), .Y(n3571) );
OAI21X2TS U1858 ( .A0(n2271), .A1(n2272), .B0(n2270), .Y(n1355) );
XOR2X1TS U1859 ( .A(n5048), .B(n1211), .Y(n3196) );
CLKAND2X2TS U1860 ( .A(n1725), .B(n1724), .Y(n1780) );
NAND2X4TS U1861 ( .A(n1566), .B(n1567), .Y(n1565) );
OAI21X2TS U1862 ( .A0(n2093), .A1(n2092), .B0(n2091), .Y(n2111) );
BUFX8TS U1863 ( .A(n3340), .Y(n3310) );
OR2X2TS U1864 ( .A(n2929), .B(n1041), .Y(n1288) );
AO21X1TS U1865 ( .A0(n3045), .A1(n1125), .B0(n1664), .Y(n3108) );
OAI22X2TS U1866 ( .A0(n1209), .A1(n3042), .B0(n3380), .B1(n3107), .Y(n3110)
);
OAI22X1TS U1867 ( .A0(n2122), .A1(n2088), .B0(n1148), .B1(n2123), .Y(n2112)
);
OAI22X2TS U1868 ( .A0(n2418), .A1(n1598), .B0(n2474), .B1(n1220), .Y(n2490)
);
OAI22X2TS U1869 ( .A0(n3306), .A1(n2475), .B0(n3305), .B1(n2625), .Y(n2611)
);
OR2X2TS U1870 ( .A(n2974), .B(n3600), .Y(n1289) );
OAI22X1TS U1871 ( .A0(n1206), .A1(n2888), .B0(n3199), .B1(n2953), .Y(n2950)
);
OAI22X1TS U1872 ( .A0(n1204), .A1(n2098), .B0(n2124), .B1(n1666), .Y(n2118)
);
ADDFHX1TS U1873 ( .A(n3035), .B(n3034), .CI(n3033), .CO(n3140), .S(n3036) );
OAI21X1TS U1874 ( .A0(n1748), .A1(n1749), .B0(n1747), .Y(n1705) );
OAI22X1TS U1875 ( .A0(n1911), .A1(n1723), .B0(n2124), .B1(n1722), .Y(n1731)
);
CMPR32X2TS U1876 ( .A(n1743), .B(n1742), .C(n1741), .CO(n1746), .S(n1756) );
XOR2X1TS U1877 ( .A(n1748), .B(n1747), .Y(n1750) );
XOR2X1TS U1878 ( .A(n1717), .B(n1714), .Y(n1712) );
XNOR2X1TS U1879 ( .A(n2618), .B(n2620), .Y(n2489) );
XOR2X2TS U1880 ( .A(n3312), .B(n3338), .Y(n2969) );
ADDFX2TS U1881 ( .A(n1881), .B(n1880), .CI(n1879), .CO(n1757), .S(n1893) );
CMPR32X2TS U1882 ( .A(n1970), .B(n1969), .C(n1968), .CO(n2069), .S(n1957) );
CLKXOR2X2TS U1883 ( .A(n1775), .B(n1773), .Y(n1729) );
CMPR32X2TS U1884 ( .A(n1907), .B(n1906), .C(n1905), .CO(n2086), .S(n1923) );
INVX2TS U1885 ( .A(n2264), .Y(n2358) );
CMPR32X2TS U1886 ( .A(n1962), .B(n1961), .C(n1960), .CO(n2058), .S(n1987) );
NOR2X1TS U1887 ( .A(n1216), .B(n1650), .Y(n2297) );
INVX2TS U1888 ( .A(n3414), .Y(n2390) );
OAI2BB1X2TS U1889 ( .A0N(n2192), .A1N(n2191), .B0(n2190), .Y(n2269) );
AO21X2TS U1890 ( .A0(n1205), .A1(n1122), .B0(n1658), .Y(n2094) );
OAI2BB2X1TS U1891 ( .B0(n2541), .B1(n1641), .A0N(n1621), .A1N(n1740), .Y(
n1879) );
OAI2BB2X1TS U1892 ( .B0(n2320), .B1(n1736), .A0N(n1703), .A1N(n1702), .Y(
n1741) );
NAND2X1TS U1893 ( .A(n1716), .B(n1713), .Y(n1715) );
OAI2BB2X1TS U1894 ( .B0(n1911), .B1(n1855), .A0N(n1696), .A1N(n1738), .Y(
n1880) );
OAI22X1TS U1895 ( .A0(n1136), .A1(n1733), .B0(n1701), .B1(n1038), .Y(n1742)
);
NAND2X4TS U1896 ( .A(n1561), .B(n1526), .Y(n1566) );
OAI22X1TS U1897 ( .A0(n2898), .A1(n2621), .B0(n1125), .B1(n2693), .Y(n2699)
);
NOR2BX2TS U1898 ( .AN(n1227), .B(n3557), .Y(n2620) );
OAI22X1TS U1899 ( .A0(n1854), .A1(n1852), .B0(n1122), .B1(n1751), .Y(n1887)
);
OAI22X1TS U1900 ( .A0(n1975), .A1(n1213), .B0(n1141), .B1(n1938), .Y(n1986)
);
OAI22X2TS U1901 ( .A0(n1209), .A1(n2486), .B0(n3380), .B1(n2630), .Y(n2619)
);
XNOR2X1TS U1902 ( .A(n1212), .B(FPMULT_Op_MX[10]), .Y(n2117) );
XNOR2X1TS U1903 ( .A(n1223), .B(FPMULT_Op_MX[7]), .Y(n1722) );
XNOR2X2TS U1904 ( .A(n2930), .B(n2972), .Y(n2719) );
OAI22X2TS U1905 ( .A0(n1304), .A1(n1302), .B0(n2711), .B1(n2601), .Y(n1305)
);
ADDFHX1TS U1906 ( .A(n1846), .B(n1845), .CI(n1844), .CO(n1885), .S(n1896) );
OAI22X2TS U1907 ( .A0(n1136), .A1(n1701), .B0(n1700), .B1(n1038), .Y(n1724)
);
XOR2X2TS U1908 ( .A(n2093), .B(n1919), .Y(n2081) );
NAND2X2TS U1909 ( .A(n1955), .B(n1954), .Y(n2013) );
CMPR32X2TS U1910 ( .A(n5037), .B(n1675), .C(n3047), .CO(n3105), .S(n3034) );
XNOR2X2TS U1911 ( .A(n3131), .B(n2972), .Y(n3056) );
CMPR32X2TS U1912 ( .A(n1783), .B(n1782), .C(n1639), .CO(n1924), .S(n1801) );
ADDFHX2TS U1913 ( .A(n2902), .B(n2901), .CI(n2900), .CO(n2944), .S(n2892) );
CMPR32X2TS U1914 ( .A(n1764), .B(n1763), .C(n1762), .CO(n1794), .S(n1779) );
INVX2TS U1915 ( .A(n2193), .Y(n2254) );
INVX2TS U1916 ( .A(n2216), .Y(n2286) );
INVX2TS U1917 ( .A(n3413), .Y(n2287) );
CLKINVX1TS U1918 ( .A(n2089), .Y(n1915) );
INVX4TS U1919 ( .A(n2281), .Y(n2391) );
BUFX6TS U1920 ( .A(n1037), .Y(n2320) );
CLKINVX2TS U1921 ( .A(n2930), .Y(n2971) );
OAI2BB2X1TS U1922 ( .B0(n2898), .B1(n2693), .A0N(n1976), .A1N(n2692), .Y(
n2902) );
OAI2BB2X1TS U1923 ( .B0(n2898), .B1(n2897), .A0N(n1976), .A1N(n1664), .Y(
n2956) );
OAI2BB2X1TS U1924 ( .B0(n3246), .B1(n3112), .A0N(n2957), .A1N(n1673), .Y(
n3047) );
OAI22X1TS U1925 ( .A0(n2251), .A1(n3133), .B0(n2196), .B1(n1057), .Y(n2252)
);
NOR2X4TS U1926 ( .A(n1711), .B(n1710), .Y(n1716) );
OAI22X1TS U1927 ( .A0(n1136), .A1(n1859), .B0(n1754), .B1(n1038), .Y(n1845)
);
OAI22X2TS U1928 ( .A0(n2280), .A1(n3340), .B0(n1225), .B1(n2387), .Y(n1387)
);
OAI22X1TS U1929 ( .A0(n1037), .A1(n1766), .B0(n2319), .B1(n1789), .Y(n1791)
);
XNOR2X1TS U1930 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MX[7]), .Y(n2087) );
OAI22X1TS U1931 ( .A0(n1135), .A1(n1700), .B0(n1146), .B1(n1639), .Y(n1763)
);
XNOR2X2TS U1932 ( .A(n1218), .B(FPMULT_Op_MX[10]), .Y(n1701) );
CMPR22X2TS U1933 ( .A(n2195), .B(n2194), .CO(n2253), .S(n2209) );
OAI22X1TS U1934 ( .A0(n1136), .A1(n1754), .B0(n1733), .B1(n1146), .Y(n1753)
);
XNOR2X1TS U1935 ( .A(n1224), .B(FPMULT_Op_MX[10]), .Y(n1910) );
XNOR2X1TS U1936 ( .A(n1212), .B(FPMULT_Op_MX[3]), .Y(n1736) );
XNOR2X2TS U1937 ( .A(n1171), .B(FPMULT_Op_MX[7]), .Y(n1751) );
XNOR2X2TS U1938 ( .A(n1172), .B(FPMULT_Op_MX[4]), .Y(n1765) );
XNOR2X2TS U1939 ( .A(n1169), .B(FPMULT_Op_MY[17]), .Y(n2477) );
XNOR2X2TS U1940 ( .A(n1160), .B(n5048), .Y(n3044) );
CMPR32X2TS U1941 ( .A(n2433), .B(n2432), .C(n2431), .CO(n2479), .S(n2453) );
XNOR2X1TS U1942 ( .A(n1169), .B(n1126), .Y(n3046) );
XNOR2X1TS U1943 ( .A(n2638), .B(n5040), .Y(n1073) );
XNOR2X2TS U1944 ( .A(n1169), .B(n5045), .Y(n2624) );
XNOR2X1TS U1945 ( .A(n1171), .B(FPMULT_Op_MX[9]), .Y(n1726) );
XNOR2X1TS U1946 ( .A(n1171), .B(FPMULT_Op_MX[8]), .Y(n1721) );
XNOR2X1TS U1947 ( .A(n1170), .B(FPMULT_Op_MX[6]), .Y(n1852) );
INVX2TS U1948 ( .A(n2131), .Y(n2195) );
XOR2X1TS U1949 ( .A(FPMULT_Op_MY[17]), .B(n1211), .Y(n2952) );
INVX4TS U1950 ( .A(n1697), .Y(n1149) );
NAND2X1TS U1951 ( .A(n2629), .B(n2628), .Y(n2695) );
BUFX4TS U1952 ( .A(n1057), .Y(n1598) );
NAND2X1TS U1953 ( .A(n2277), .B(n2377), .Y(n2278) );
NAND2BX1TS U1954 ( .AN(n2488), .B(n1976), .Y(n1323) );
NOR2X2TS U1955 ( .A(n1216), .B(n5218), .Y(n2089) );
XNOR2X1TS U1956 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[2]), .Y(n1778) );
INVX4TS U1957 ( .A(n1532), .Y(n1225) );
NAND2BXLTS U1958 ( .AN(n1173), .B(n1514), .Y(n2263) );
OR2X2TS U1959 ( .A(n3045), .B(n2427), .Y(n1324) );
XNOR2X2TS U1960 ( .A(n3071), .B(n1514), .Y(n1592) );
BUFX8TS U1961 ( .A(n1039), .Y(n3516) );
XNOR2X2TS U1962 ( .A(n5047), .B(FPMULT_Op_MX[11]), .Y(n1700) );
NOR2X2TS U1963 ( .A(n2541), .B(n1709), .Y(n1711) );
OAI22X2TS U1964 ( .A0(n1037), .A1(n1707), .B0(n2319), .B1(n1706), .Y(n1717)
);
XNOR2X1TS U1965 ( .A(n1212), .B(FPMULT_Op_MX[6]), .Y(n1766) );
XOR2X2TS U1966 ( .A(n3071), .B(n3267), .Y(n2386) );
OAI22X2TS U1967 ( .A0(n1136), .A1(n1829), .B0(n1831), .B1(n1146), .Y(n1931)
);
XNOR2X2TS U1968 ( .A(n1172), .B(FPMULT_Op_MX[6]), .Y(n1913) );
OAI22X1TS U1969 ( .A0(n1677), .A1(n1211), .B0(n3380), .B1(n2428), .Y(n2482)
);
XNOR2X1TS U1970 ( .A(n1224), .B(FPMULT_Op_MX[8]), .Y(n1777) );
XNOR2X1TS U1971 ( .A(n1223), .B(FPMULT_Op_MX[9]), .Y(n1787) );
XNOR2X2TS U1972 ( .A(n1172), .B(FPMULT_Op_MX[5]), .Y(n1785) );
ADDFHX2TS U1973 ( .A(n1867), .B(n1866), .CI(n1865), .CO(n1895), .S(n1868) );
XNOR2X1TS U1974 ( .A(n5060), .B(n5046), .Y(n2954) );
XOR2X2TS U1975 ( .A(n2041), .B(n2042), .Y(n1984) );
XNOR2X1TS U1976 ( .A(n1171), .B(FPMULT_Op_MX[10]), .Y(n1768) );
ADDFHX2TS U1977 ( .A(n2353), .B(n2352), .CI(n2351), .CO(n3420), .S(n3415) );
XNOR2X1TS U1978 ( .A(n1169), .B(FPMULT_Op_MY[19]), .Y(n2687) );
BUFX6TS U1979 ( .A(n1060), .Y(n3306) );
CLKINVX6TS U1980 ( .A(n1514), .Y(n3338) );
CLKINVX6TS U1981 ( .A(n957), .Y(n1217) );
BUFX6TS U1982 ( .A(n2322), .Y(n2541) );
INVX2TS U1983 ( .A(n5221), .Y(n5049) );
INVX6TS U1984 ( .A(n1697), .Y(n1148) );
NAND2X1TS U1985 ( .A(n2201), .B(n2378), .Y(n2202) );
INVX4TS U1986 ( .A(n1621), .Y(n958) );
NAND2X1TS U1987 ( .A(n2627), .B(n2626), .Y(n2629) );
INVX8TS U1988 ( .A(n2627), .Y(n3246) );
AND2X2TS U1989 ( .A(n1174), .B(n1533), .Y(n1071) );
INVX4TS U1990 ( .A(n3412), .Y(n2266) );
NAND2X2TS U1991 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .Y(n2708) );
INVX2TS U1992 ( .A(n2602), .Y(n2710) );
OAI2BB2X2TS U1993 ( .B0(n1037), .B1(n1849), .A0N(n1703), .A1N(n1848), .Y(
n1867) );
XNOR2X1TS U1994 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MX[3]), .Y(n1728) );
AOI2BB1X2TS U1995 ( .A0N(n1908), .A1N(n1858), .B0(n1857), .Y(n1861) );
XNOR2X2TS U1996 ( .A(n1172), .B(FPMULT_Op_MX[2]), .Y(n1709) );
NAND2X2TS U1997 ( .A(n1472), .B(n2274), .Y(n1471) );
CLKAND2X2TS U1998 ( .A(n2631), .B(n3303), .Y(n1508) );
NOR2X2TS U1999 ( .A(n1677), .B(n2630), .Y(n1509) );
XNOR2X1TS U2000 ( .A(n1151), .B(n5048), .Y(n2422) );
NOR2X2TS U2001 ( .A(n2505), .B(n2508), .Y(n2601) );
CLKXOR2X2TS U2002 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n2636) );
XNOR2X1TS U2003 ( .A(n1159), .B(n5045), .Y(n2427) );
XNOR2X1TS U2004 ( .A(n2220), .B(n2221), .Y(n2147) );
INVX2TS U2005 ( .A(n1215), .Y(n1703) );
INVX6TS U2006 ( .A(n1527), .Y(n3515) );
OAI21X2TS U2007 ( .A0(FPMULT_Op_MY[22]), .A1(FPMULT_Op_MY[10]), .B0(
FPMULT_Op_MY[21]), .Y(n2640) );
INVX4TS U2008 ( .A(n2931), .Y(n1174) );
NOR2X2TS U2009 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .Y(n2602) );
OAI22X1TS U2010 ( .A0(n2898), .A1(n2060), .B0(n1125), .B1(n2141), .Y(n2133)
);
NOR2X2TS U2011 ( .A(FPMULT_Op_MX[8]), .B(n5061), .Y(n2505) );
NAND2X1TS U2012 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n2639) );
NAND2X2TS U2013 ( .A(n1413), .B(n2375), .Y(n1472) );
OAI21X2TS U2014 ( .A0(n2379), .A1(n2378), .B0(n2377), .Y(n2380) );
CLKXOR2X2TS U2015 ( .A(n3071), .B(n1974), .Y(n2051) );
NAND2X2TS U2016 ( .A(n1377), .B(n1935), .Y(n1607) );
INVX4TS U2017 ( .A(n2931), .Y(n1173) );
OAI22X1TS U2018 ( .A0(n1136), .A1(n1831), .B0(n1830), .B1(n1146), .Y(n1838)
);
OAI22X1TS U2019 ( .A0(n1060), .A1(n1662), .B0(n3305), .B1(n2248), .Y(n2368)
);
XNOR2X1TS U2020 ( .A(n5047), .B(FPMULT_Op_MX[7]), .Y(n1859) );
XNOR2X1TS U2021 ( .A(n1171), .B(FPMULT_Op_MX[5]), .Y(n1853) );
XOR2X1TS U2022 ( .A(n5038), .B(n1210), .Y(n2889) );
CLKINVX6TS U2023 ( .A(n1441), .Y(n3131) );
BUFX6TS U2024 ( .A(FPMULT_Op_MY[7]), .Y(n1212) );
INVX2TS U2025 ( .A(n1620), .Y(n1214) );
NAND2X1TS U2026 ( .A(n949), .B(n2063), .Y(n2064) );
INVX4TS U2027 ( .A(n1547), .Y(n3336) );
NOR2X4TS U2028 ( .A(FPMULT_Op_MX[9]), .B(n3379), .Y(n2508) );
NOR2X1TS U2029 ( .A(n2136), .B(n2135), .Y(n2137) );
BUFX3TS U2030 ( .A(n1908), .Y(n2124) );
NAND2X1TS U2031 ( .A(n2222), .B(n2221), .Y(n2223) );
NAND2X2TS U2032 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[6]), .Y(n2378) );
OR2X4TS U2033 ( .A(n1663), .B(n1620), .Y(n1060) );
BUFX3TS U2034 ( .A(n1911), .Y(n1204) );
NAND2X2TS U2035 ( .A(FPMULT_Op_MX[9]), .B(n3379), .Y(n2506) );
NAND2X2TS U2036 ( .A(n5060), .B(FPMULT_Op_MX[7]), .Y(n2377) );
XNOR2X1TS U2037 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[7]), .Y(n1645) );
NAND2X2TS U2038 ( .A(n2219), .B(n2218), .Y(n2224) );
XNOR2X1TS U2039 ( .A(n5047), .B(FPMULT_Op_MX[6]), .Y(n1860) );
CLKAND2X2TS U2040 ( .A(n1934), .B(n2879), .Y(n1068) );
XNOR2X1TS U2041 ( .A(FPMULT_Op_MX[13]), .B(n5046), .Y(n2366) );
XNOR2X1TS U2042 ( .A(n5060), .B(FPMULT_Op_MY[13]), .Y(n2371) );
NAND2X2TS U2043 ( .A(n1657), .B(n1937), .Y(n2931) );
XOR2X1TS U2044 ( .A(n2135), .B(n1672), .Y(n2065) );
XNOR2X1TS U2045 ( .A(n1169), .B(n5037), .Y(n2250) );
XOR2X1TS U2046 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n2135) );
OR2X6TS U2047 ( .A(n1059), .B(n1696), .Y(n1911) );
OR2X1TS U2048 ( .A(n1170), .B(FPMULT_Op_MY[15]), .Y(n1672) );
INVX4TS U2049 ( .A(n1279), .Y(n1600) );
NAND2X2TS U2050 ( .A(n1168), .B(FPMULT_Op_MX[5]), .Y(n2198) );
BUFX6TS U2051 ( .A(FPMULT_Op_MY[5]), .Y(n1223) );
XNOR2X1TS U2052 ( .A(n5047), .B(FPMULT_Op_MX[4]), .Y(n1825) );
XNOR2X1TS U2053 ( .A(n5047), .B(FPMULT_Op_MX[5]), .Y(n1815) );
ADDHX1TS U2054 ( .A(n2055), .B(n2054), .CO(n2159), .S(n2040) );
XNOR2X1TS U2055 ( .A(n1171), .B(FPMULT_Op_MX[4]), .Y(n1851) );
CLKXOR2X4TS U2056 ( .A(n1413), .B(n2050), .Y(n1441) );
XNOR2X2TS U2057 ( .A(n1159), .B(n5038), .Y(n2241) );
CLKXOR2X2TS U2058 ( .A(n2930), .B(n957), .Y(n2038) );
XNOR2X1TS U2059 ( .A(n1169), .B(n3112), .Y(n2370) );
INVX4TS U2060 ( .A(n1167), .Y(n1169) );
BUFX6TS U2061 ( .A(FPMULT_Op_MX[20]), .Y(n5061) );
NAND2XLTS U2062 ( .A(n1584), .B(n2225), .Y(n1536) );
NAND2X1TS U2063 ( .A(n2149), .B(n2199), .Y(n2050) );
NAND2X1TS U2064 ( .A(n2385), .B(n1417), .Y(n1530) );
INVX2TS U2065 ( .A(n1227), .Y(n2626) );
NOR2X6TS U2066 ( .A(n5060), .B(FPMULT_Op_MX[7]), .Y(n2379) );
BUFX6TS U2067 ( .A(FPMULT_Op_MY[18]), .Y(n5045) );
XNOR2X2TS U2068 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[21]), .Y(n2518) );
AOI21X2TS U2069 ( .A0(n1610), .A1(n1405), .B0(n1404), .Y(n1403) );
NAND2X1TS U2070 ( .A(n5048), .B(FPMULT_Op_MY[8]), .Y(n2447) );
NAND2X1TS U2071 ( .A(n1935), .B(n1394), .Y(n1393) );
BUFX4TS U2072 ( .A(n2898), .Y(n3045) );
NOR2X1TS U2073 ( .A(n1964), .B(n1963), .Y(n1965) );
OAI21X1TS U2074 ( .A0(FPMULT_Op_MY[20]), .A1(FPMULT_Op_MY[8]), .B0(
FPMULT_Op_MY[7]), .Y(n2448) );
NOR2X2TS U2075 ( .A(n1402), .B(n1610), .Y(n1972) );
NAND2BX1TS U2076 ( .AN(n1945), .B(n1067), .Y(n1948) );
NAND2X1TS U2077 ( .A(n1405), .B(n2047), .Y(n1932) );
NOR2X2TS U2078 ( .A(n2143), .B(n1594), .Y(n2145) );
XNOR2X2TS U2079 ( .A(n1159), .B(n5037), .Y(n2141) );
CLKXOR2X2TS U2080 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[18]), .Y(n2257) );
XNOR2X1TS U2081 ( .A(n1168), .B(n1202), .Y(n2210) );
OR2X6TS U2082 ( .A(n1035), .B(n1976), .Y(n2898) );
XOR2X1TS U2083 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n1963) );
BUFX6TS U2084 ( .A(FPMULT_Op_MY[20]), .Y(n5048) );
NAND2X1TS U2085 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n2261) );
OAI21X2TS U2086 ( .A0(FPMULT_Op_MY[18]), .A1(FPMULT_Op_MY[6]), .B0(
FPMULT_Op_MY[17]), .Y(n2262) );
INVX2TS U2087 ( .A(n1374), .Y(n1394) );
OAI21X2TS U2088 ( .A0(FPMULT_Op_MY[16]), .A1(FPMULT_Op_MY[4]), .B0(n3112),
.Y(n2139) );
INVX4TS U2089 ( .A(n1538), .Y(n1854) );
NAND2X4TS U2090 ( .A(n1151), .B(n1147), .Y(n2623) );
BUFX6TS U2091 ( .A(FPMULT_Op_MY[5]), .Y(n1224) );
INVX6TS U2092 ( .A(n1976), .Y(n1125) );
BUFX4TS U2093 ( .A(FPMULT_Op_MY[16]), .Y(n5038) );
INVX4TS U2094 ( .A(n1675), .Y(n1202) );
INVX8TS U2095 ( .A(n1676), .Y(n1151) );
BUFX4TS U2096 ( .A(FPMULT_Op_MY[12]), .Y(n1227) );
INVX2TS U2097 ( .A(n2046), .Y(n1306) );
INVX4TS U2098 ( .A(FPMULT_Op_MX[12]), .Y(n1147) );
BUFX6TS U2099 ( .A(FPMULT_Op_MY[15]), .Y(n3112) );
BUFX4TS U2100 ( .A(FPMULT_Op_MY[3]), .Y(n1171) );
NAND2X1TS U2101 ( .A(n1072), .B(n1042), .Y(n1578) );
INVX6TS U2102 ( .A(n1373), .Y(n3199) );
NOR2X4TS U2103 ( .A(n2048), .B(n2045), .Y(n2049) );
INVX2TS U2104 ( .A(n1070), .Y(n1121) );
BUFX4TS U2105 ( .A(FPMULT_Op_MY[1]), .Y(n5047) );
INVX8TS U2106 ( .A(n1167), .Y(n1168) );
CLKINVX6TS U2107 ( .A(FPMULT_Op_MX[17]), .Y(n1167) );
BUFX8TS U2108 ( .A(FPMULT_Op_MX[15]), .Y(n5055) );
CLKBUFX2TS U2109 ( .A(n1133), .Y(n5283) );
CLKBUFX2TS U2110 ( .A(n1133), .Y(n1229) );
BUFX3TS U2111 ( .A(n1133), .Y(n1228) );
CLKBUFX2TS U2112 ( .A(n1133), .Y(n5284) );
INVX2TS U2113 ( .A(n5273), .Y(n911) );
INVX2TS U2114 ( .A(n911), .Y(n912) );
INVX2TS U2115 ( .A(n911), .Y(n913) );
INVX2TS U2116 ( .A(n5284), .Y(n914) );
INVX2TS U2117 ( .A(n914), .Y(n915) );
INVX2TS U2118 ( .A(n914), .Y(n916) );
INVX2TS U2119 ( .A(n914), .Y(n917) );
OAI211XLTS U2120 ( .A0(n1182), .A1(n4071), .B0(n4070), .C0(n4073), .Y(
add_subt_data2[29]) );
OAI211XLTS U2121 ( .A0(n1182), .A1(n3986), .B0(n3985), .C0(n3984), .Y(
add_subt_data2[7]) );
CLKINVX1TS U2122 ( .A(n1784), .Y(n1767) );
OAI21X2TS U2123 ( .A0(n4155), .A1(n4291), .B0(n4120), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[3]) );
INVX2TS U2124 ( .A(n5252), .Y(n920) );
INVX2TS U2125 ( .A(n920), .Y(n921) );
INVX2TS U2126 ( .A(n920), .Y(n922) );
OAI211X4TS U2127 ( .A0(n4287), .A1(n4291), .B0(n4286), .C0(n4289), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[5]) );
OAI211X4TS U2128 ( .A0(n4128), .A1(n4291), .B0(n4109), .C0(n4289), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[6]) );
OAI211X4TS U2129 ( .A0(n4115), .A1(n4291), .B0(n4114), .C0(n4289), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[8]) );
OAI211X4TS U2130 ( .A0(n4152), .A1(n4291), .B0(n4140), .C0(n4289), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[7]) );
OAI211X4TS U2131 ( .A0(n4146), .A1(n4291), .B0(n4145), .C0(n4289), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[9]) );
ADDHX1TS U2132 ( .A(n996), .B(n995), .CO(n3783), .S(
FPMULT_Adder_M_result_A_adder[21]) );
MXI2X2TS U2133 ( .A(n4310), .B(n4309), .S0(n1163), .Y(n5138) );
INVX2TS U2134 ( .A(n5318), .Y(n928) );
INVX2TS U2135 ( .A(n928), .Y(n929) );
INVX2TS U2136 ( .A(n928), .Y(n930) );
INVX2TS U2137 ( .A(n1228), .Y(n931) );
INVX2TS U2138 ( .A(n931), .Y(n932) );
CLKINVX3TS U2139 ( .A(n931), .Y(n933) );
OAI21X2TS U2140 ( .A0(n977), .A1(n976), .B0(n975), .Y(
FPADDSUB_Data_array_SWR[11]) );
INVX2TS U2141 ( .A(n5254), .Y(n935) );
INVX2TS U2142 ( .A(n935), .Y(n936) );
INVX2TS U2143 ( .A(n935), .Y(n937) );
INVX2TS U2144 ( .A(n935), .Y(n938) );
NAND2X1TS U2145 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n1966) );
OAI22X2TS U2146 ( .A0(n3340), .A1(n2387), .B0(n2450), .B1(n3339), .Y(n1583)
);
NAND2X1TS U2147 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n2138) );
INVX2TS U2148 ( .A(n2062), .Y(n2162) );
OAI21X2TS U2149 ( .A0(n2266), .A1(n1071), .B0(n1356), .Y(n2265) );
CLKXOR2X2TS U2150 ( .A(n3336), .B(n1441), .Y(n2881) );
NAND2X1TS U2151 ( .A(n1389), .B(n1303), .Y(n1302) );
ADDFHX2TS U2152 ( .A(n2163), .B(n2162), .CI(n2161), .CO(n2205), .S(n2166) );
OAI21X2TS U2153 ( .A0(n2441), .A1(n2442), .B0(n2439), .Y(n2440) );
XNOR2X2TS U2154 ( .A(n2607), .B(n2606), .Y(n1591) );
CLKXOR2X2TS U2155 ( .A(n2730), .B(n1685), .Y(n2653) );
NAND2X1TS U2156 ( .A(n2886), .B(n2887), .Y(n1380) );
NAND2X2TS U2157 ( .A(n1588), .B(n1587), .Y(n1586) );
OAI2BB1X1TS U2158 ( .A0N(n2957), .A1N(n2626), .B0(n3246), .Y(n2696) );
NAND2X1TS U2159 ( .A(n1950), .B(n1949), .Y(n1939) );
NAND2X1TS U2160 ( .A(n1794), .B(n1793), .Y(n1771) );
NAND2X4TS U2161 ( .A(n1361), .B(n1360), .Y(n1367) );
OAI2BB1X2TS U2162 ( .A0N(n3069), .A1N(n1569), .B0(n1568), .Y(n3124) );
INVX2TS U2163 ( .A(n3208), .Y(n3254) );
OAI21X1TS U2164 ( .A0(n3271), .A1(n1143), .B0(n1293), .Y(n3286) );
INVX2TS U2165 ( .A(n3099), .Y(n3168) );
AND2X6TS U2166 ( .A(FPMULT_Op_MX[12]), .B(n1277), .Y(n1062) );
BUFX12TS U2167 ( .A(n2122), .Y(n2679) );
XNOR2X2TS U2168 ( .A(n1331), .B(n3422), .Y(n2497) );
OAI2BB1X2TS U2169 ( .A0N(n3080), .A1N(n3079), .B0(n3078), .Y(n3119) );
XNOR2X1TS U2170 ( .A(n1159), .B(FPMULT_Op_MY[17]), .Y(n2365) );
OAI22X1TS U2171 ( .A0(n3300), .A1(n3516), .B0(n3337), .B1(n3515), .Y(n3347)
);
OAI22X1TS U2172 ( .A0(n2623), .A1(n2622), .B0(n1147), .B1(n1151), .Y(n2698)
);
INVX2TS U2173 ( .A(n3517), .Y(n3569) );
BUFX3TS U2174 ( .A(n1041), .Y(n3601) );
OAI22X1TS U2175 ( .A0(n3246), .A1(n5037), .B0(n3557), .B1(n3112), .Y(n2959)
);
NAND2X1TS U2176 ( .A(n2217), .B(n2220), .Y(n2218) );
OR2X4TS U2177 ( .A(n2234), .B(n2235), .Y(n1076) );
XNOR2X1TS U2178 ( .A(n1171), .B(FPMULT_Op_MX[3]), .Y(n1817) );
INVX2TS U2179 ( .A(n2072), .Y(n2073) );
INVX2TS U2180 ( .A(n1122), .Y(n1704) );
AOI21X2TS U2181 ( .A0(n1626), .A1(n2549), .B0(n2548), .Y(n2671) );
OR2X1TS U2182 ( .A(n3518), .B(n3517), .Y(n1624) );
OAI22X1TS U2183 ( .A0(n2898), .A1(n2365), .B0(n1125), .B1(n2427), .Y(n2432)
);
NAND2X2TS U2184 ( .A(n1318), .B(n1317), .Y(n2609) );
OAI2BB2X1TS U2185 ( .B0(n1209), .B1(n2952), .A0N(n3303), .A1N(n2951), .Y(
n3041) );
INVX6TS U2186 ( .A(n2957), .Y(n3557) );
ADDHX1TS U2187 ( .A(n1753), .B(n1752), .CO(n1758), .S(n1886) );
NAND2X2TS U2188 ( .A(n2976), .B(n2961), .Y(n2000) );
XNOR2X1TS U2189 ( .A(n1223), .B(FPMULT_Op_MX[2]), .Y(n1856) );
NOR2X2TS U2190 ( .A(n2031), .B(n2030), .Y(n2786) );
OAI2BB1X1TS U2191 ( .A0N(n2246), .A1N(n2245), .B0(n2244), .Y(n2352) );
INVX2TS U2192 ( .A(n3651), .Y(n3654) );
XOR2X1TS U2193 ( .A(n3115), .B(n3050), .Y(n3104) );
AO21X1TS U2194 ( .A0(n3306), .A1(n3305), .B0(n1662), .Y(n3343) );
BUFX4TS U2195 ( .A(FPMULT_Op_MX[0]), .Y(n1277) );
AOI21X2TS U2196 ( .A0(n1674), .A1(n2014), .B0(n1956), .Y(n2007) );
CLKXOR2X2TS U2197 ( .A(n2582), .B(n2581), .Y(n2584) );
NOR2XLTS U2198 ( .A(n2665), .B(n1043), .Y(n2674) );
NOR2XLTS U2199 ( .A(n4659), .B(FPADDSUB_intDY_EWSW[16]), .Y(n4660) );
CLKXOR2X4TS U2200 ( .A(n2960), .B(n3058), .Y(n3486) );
INVX2TS U2201 ( .A(n3026), .Y(n3019) );
NAND2X1TS U2202 ( .A(n3444), .B(n3439), .Y(n1479) );
NAND2X4TS U2203 ( .A(n3368), .B(n3369), .Y(n3450) );
OAI21XLTS U2204 ( .A0(n3654), .A1(n3653), .B0(n3652), .Y(n3655) );
NOR2X2TS U2205 ( .A(n3686), .B(n3691), .Y(n3693) );
INVX2TS U2206 ( .A(n3281), .Y(n3441) );
NOR2X1TS U2207 ( .A(n1931), .B(n1941), .Y(n4026) );
OAI21XLTS U2208 ( .A0(n1009), .A1(n965), .B0(n1008), .Y(n3832) );
INVX2TS U2209 ( .A(n3684), .Y(n3824) );
BUFX6TS U2210 ( .A(FPMULT_Op_MX[19]), .Y(n5060) );
OAI21XLTS U2211 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n5188), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n4658) );
NAND2X1TS U2212 ( .A(n3013), .B(n3027), .Y(n3014) );
NAND2X1TS U2213 ( .A(n3420), .B(n3419), .Y(n3475) );
NOR2X2TS U2214 ( .A(n3623), .B(n3590), .Y(n3592) );
NOR2X2TS U2215 ( .A(n3664), .B(n3666), .Y(n3687) );
NAND2X1TS U2216 ( .A(n3731), .B(n3737), .Y(n3740) );
NOR2XLTS U2217 ( .A(n5105), .B(FPADDSUB_DMP_SFG[13]), .Y(n4422) );
NOR2XLTS U2218 ( .A(n4370), .B(n4371), .Y(n3889) );
OAI21XLTS U2219 ( .A0(n3438), .A1(n3473), .B0(n3475), .Y(n3425) );
NOR2X4TS U2220 ( .A(n2754), .B(n2753), .Y(n2866) );
NOR2X2TS U2221 ( .A(n2264), .B(n2281), .Y(n1874) );
BUFX3TS U2222 ( .A(FPMULT_Op_MX[0]), .Y(n1278) );
BUFX4TS U2223 ( .A(FPMULT_Op_MY[3]), .Y(n1170) );
NAND2X1TS U2224 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n5145), .Y(n3992)
);
NOR2X1TS U2225 ( .A(n3869), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(n4276) );
OR2X1TS U2226 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]),
.Y(n4455) );
OR2X1TS U2227 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]),
.Y(n4494) );
INVX2TS U2228 ( .A(n5030), .Y(n5026) );
NOR2X1TS U2229 ( .A(add_x_69_n52), .B(n1681), .Y(n3749) );
NOR2XLTS U2230 ( .A(n3494), .B(n3686), .Y(n3497) );
NOR2XLTS U2231 ( .A(n3732), .B(n3740), .Y(n3743) );
NAND2X1TS U2232 ( .A(n2851), .B(n2850), .Y(n4029) );
OAI21X2TS U2233 ( .A0(n4521), .A1(n4518), .B0(n4519), .Y(n4512) );
NOR3X2TS U2234 ( .A(FPSENCOS_cont_var_out[1]), .B(n4970), .C(n5117), .Y(
n4004) );
OAI21XLTS U2235 ( .A0(n4540), .A1(n4406), .B0(n4405), .Y(n4409) );
BUFX3TS U2236 ( .A(n5169), .Y(n4228) );
OAI22X1TS U2237 ( .A0(n4263), .A1(n4269), .B0(n4262), .B1(n1165), .Y(n4264)
);
BUFX3TS U2238 ( .A(n4922), .Y(n4898) );
OAI21XLTS U2239 ( .A0(n4357), .A1(n4354), .B0(n4355), .Y(n4335) );
OAI21XLTS U2240 ( .A0(n4582), .A1(n4579), .B0(n4580), .Y(n4573) );
NOR2X4TS U2241 ( .A(n1162), .B(n3997), .Y(n3998) );
NOR2X2TS U2242 ( .A(n4048), .B(n1525), .Y(n4046) );
INVX2TS U2243 ( .A(n1036), .Y(n1129) );
BUFX3TS U2244 ( .A(n5017), .Y(n5013) );
AND2X2TS U2245 ( .A(n3749), .B(n3751), .Y(n1058) );
NAND3X4TS U2246 ( .A(n1341), .B(n1340), .C(n1339), .Y(n3785) );
NAND2X4TS U2247 ( .A(n3157), .B(n3156), .Y(n3848) );
AND3X1TS U2248 ( .A(n4190), .B(n4189), .C(n4188), .Y(n4247) );
XOR2X1TS U2249 ( .A(n3704), .B(n3703), .Y(n3759) );
AND3X1TS U2250 ( .A(n4187), .B(n4186), .C(n4185), .Y(n4242) );
INVX2TS U2251 ( .A(n4136), .Y(n4289) );
AND3X1TS U2252 ( .A(n4181), .B(n4180), .C(n4179), .Y(n4255) );
AND3X1TS U2253 ( .A(n4174), .B(n4173), .C(n4172), .Y(n4257) );
OR2X2TS U2254 ( .A(n4228), .B(n5139), .Y(n4293) );
NAND2X1TS U2255 ( .A(n3231), .B(n3230), .Y(n3802) );
NAND2X1TS U2256 ( .A(n4877), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n4079) );
AND3X1TS U2257 ( .A(n4198), .B(n4197), .C(n4196), .Y(n4256) );
OAI21XLTS U2258 ( .A0(n5035), .A1(n5117), .B0(FPSENCOS_cont_var_out[1]), .Y(
n4295) );
NOR4X1TS U2259 ( .A(n2854), .B(n2853), .C(n2852), .D(n1628), .Y(n2855) );
AND2X2TS U2260 ( .A(n5203), .B(n4787), .Y(n4843) );
INVX2TS U2261 ( .A(n3934), .Y(n4717) );
INVX2TS U2262 ( .A(FPADDSUB_intDY_EWSW[30]), .Y(n4838) );
BUFX3TS U2263 ( .A(n4833), .Y(n4820) );
INVX2TS U2264 ( .A(FPSENCOS_cont_iter_out[1]), .Y(n1134) );
BUFX3TS U2265 ( .A(n3930), .Y(n5009) );
BUFX3TS U2266 ( .A(n3930), .Y(n4995) );
INVX2TS U2267 ( .A(n4787), .Y(n4892) );
OR2X1TS U2268 ( .A(n107), .B(FPMULT_FSM_load_second_step), .Y(
FPMULT_FSM_exp_operation_load_result) );
NOR2X4TS U2269 ( .A(n3663), .B(n3753), .Y(n3685) );
NAND2X1TS U2270 ( .A(n1593), .B(n3855), .Y(n3856) );
OAI21XLTS U2271 ( .A0(n3979), .A1(n3978), .B0(n3977), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
OAI211XLTS U2272 ( .A0(operation[1]), .A1(n4061), .B0(n4060), .C0(n4059),
.Y(add_subt_data2[14]) );
OR2X1TS U2273 ( .A(FPSENCOS_d_ff_Xn[25]), .B(n3976), .Y(
FPSENCOS_first_mux_X[25]) );
OAI21XLTS U2274 ( .A0(n4262), .A1(n1176), .B0(n4241), .Y(
FPADDSUB_Data_array_SWR[10]) );
OR2X1TS U2275 ( .A(n5337), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(
FPADDSUB_formatted_number_W[29]) );
OAI211XLTS U2276 ( .A0(n4251), .A1(n1166), .B0(n4171), .C0(n4105), .Y(
FPADDSUB_Data_array_SWR[0]) );
OR2X1TS U2277 ( .A(FPSENCOS_d_ff_Xn[17]), .B(n3976), .Y(
FPSENCOS_first_mux_X[17]) );
OAI21XLTS U2278 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n865), .B0(n5025), .Y(
n849) );
CLKXOR2X4TS U2279 ( .A(n1524), .B(n1475), .Y(n946) );
AOI22X4TS U2280 ( .A0(n5224), .A1(FPADDSUB_LZD_raw_out_EWR[1]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .B1(n4217), .Y(n947) );
CLKXOR2X2TS U2281 ( .A(n5217), .B(FPMULT_Op_MY[3]), .Y(n949) );
XNOR2X4TS U2282 ( .A(n2063), .B(n949), .Y(n950) );
INVX2TS U2283 ( .A(n1080), .Y(n1128) );
NAND2X2TS U2284 ( .A(n3964), .B(n3956), .Y(n1080) );
INVX2TS U2285 ( .A(n5220), .Y(n5039) );
CLKXOR2X4TS U2286 ( .A(n3480), .B(n1476), .Y(n1515) );
BUFX3TS U2287 ( .A(n3981), .Y(n4078) );
NOR2X4TS U2288 ( .A(n4970), .B(n3937), .Y(n3981) );
XOR2X1TS U2289 ( .A(n2757), .B(n2756), .Y(n951) );
INVX4TS U2290 ( .A(n4679), .Y(n4825) );
CLKINVX3TS U2291 ( .A(n4825), .Y(n4837) );
AOI32X1TS U2292 ( .A0(n4678), .A1(n4677), .A2(n4676), .B0(n4675), .B1(n4678),
.Y(n4679) );
NAND2X2TS U2293 ( .A(n1081), .B(n3844), .Y(n1337) );
OR2X4TS U2294 ( .A(n3786), .B(n3801), .Y(n1342) );
NAND2X4TS U2295 ( .A(n1432), .B(n3452), .Y(n1431) );
NAND2X1TS U2296 ( .A(n3846), .B(n3851), .Y(n3852) );
NOR2X4TS U2297 ( .A(n3231), .B(n3230), .Y(n3801) );
INVX2TS U2298 ( .A(n3855), .Y(n1344) );
NOR2X4TS U2299 ( .A(n956), .B(n1428), .Y(n1427) );
NAND2X4TS U2300 ( .A(n1286), .B(n1596), .Y(n1371) );
BUFX8TS U2301 ( .A(n1164), .Y(n4269) );
INVX3TS U2302 ( .A(n2594), .Y(n1315) );
NAND2X4TS U2303 ( .A(n3085), .B(n3084), .Y(n1388) );
INVX2TS U2304 ( .A(n3622), .Y(n3547) );
INVX2TS U2305 ( .A(n2400), .Y(n2290) );
INVX2TS U2306 ( .A(n3432), .Y(n1513) );
INVX2TS U2307 ( .A(n3759), .Y(add_x_69_n52) );
XOR2X2TS U2308 ( .A(n2563), .B(n2562), .Y(n2587) );
NAND4X4TS U2309 ( .A(n4095), .B(n4094), .C(n4093), .D(n4092), .Y(
FPADDSUB_LZD_raw_out_EWR[0]) );
OAI21X1TS U2310 ( .A0(n3741), .A1(n3698), .B0(n3697), .Y(n3699) );
INVX2TS U2311 ( .A(n3741), .Y(n3723) );
INVX4TS U2312 ( .A(n3876), .Y(n4036) );
NAND2X2TS U2313 ( .A(n3000), .B(n2999), .Y(n3004) );
OR2X4TS U2314 ( .A(n1899), .B(n1991), .Y(n1900) );
NAND2X2TS U2315 ( .A(n2413), .B(n2412), .Y(n1521) );
NAND2X2TS U2316 ( .A(n1330), .B(n2490), .Y(n1329) );
NAND2X2TS U2317 ( .A(n1464), .B(n1462), .Y(n2204) );
NAND2XLTS U2318 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(n4086), .Y(n3877) );
OR2X4TS U2319 ( .A(n946), .B(n1369), .Y(n1361) );
INVX4TS U2320 ( .A(n3489), .Y(n3176) );
INVX3TS U2321 ( .A(n3466), .Y(n2986) );
NAND2X6TS U2322 ( .A(n3062), .B(n3061), .Y(n3487) );
INVX2TS U2323 ( .A(n2165), .Y(n1461) );
NAND2X4TS U2324 ( .A(n3871), .B(n3870), .Y(n3872) );
OR2X1TS U2325 ( .A(n3808), .B(n3807), .Y(n1668) );
INVX2TS U2326 ( .A(n3746), .Y(n3562) );
INVX2TS U2327 ( .A(n2493), .Y(n1369) );
INVX2TS U2328 ( .A(n3292), .Y(n3332) );
INVX2TS U2329 ( .A(n3518), .Y(n3568) );
NAND2X4TS U2330 ( .A(n4280), .B(n4276), .Y(n3909) );
OR2X4TS U2331 ( .A(n1073), .B(n1553), .Y(n1041) );
CLKMX2X2TS U2332 ( .A(n4590), .B(n4589), .S0(n4604), .Y(
FPADDSUB_Raw_mant_SGF[4]) );
ADDHX1TS U2333 ( .A(n2373), .B(n2372), .CO(n2424), .S(n2353) );
INVX2TS U2334 ( .A(n1410), .Y(n1409) );
OAI21X2TS U2335 ( .A0(n2619), .A1(n2620), .B0(n2618), .Y(n1511) );
BUFX4TS U2336 ( .A(n4964), .Y(n4919) );
ADDFHX2TS U2337 ( .A(n1916), .B(n1915), .CI(n1914), .CO(n2082), .S(n1903) );
NAND2XLTS U2338 ( .A(n4219), .B(FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n4187) );
BUFX8TS U2339 ( .A(n4989), .Y(n5001) );
NAND2XLTS U2340 ( .A(n5224), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n4211) );
NAND2XLTS U2341 ( .A(n1137), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n4186) );
INVX2TS U2342 ( .A(n4866), .Y(n3933) );
XNOR2X2TS U2343 ( .A(n1169), .B(n5048), .Y(n2888) );
NAND2X2TS U2344 ( .A(n1119), .B(n1118), .Y(n959) );
BUFX3TS U2345 ( .A(n3981), .Y(n4918) );
INVX2TS U2346 ( .A(n3824), .Y(n955) );
NAND2BX1TS U2347 ( .AN(n1277), .B(n1224), .Y(n1819) );
NAND2X4TS U2348 ( .A(FPMULT_Op_MX[8]), .B(n5061), .Y(n2507) );
NAND2BXLTS U2349 ( .AN(FPADDSUB_intDX_EWSW[30]), .B(n4838), .Y(
FPADDSUB_DMP_INIT_EWSW[30]) );
INVX1TS U2350 ( .A(n4412), .Y(n4414) );
NAND2X2TS U2351 ( .A(n3862), .B(FPMULT_Sgf_normalized_result[3]), .Y(n1119)
);
NAND2X2TS U2352 ( .A(n5047), .B(n1578), .Y(n1577) );
NAND2X2TS U2353 ( .A(n2262), .B(n2261), .Y(n2385) );
BUFX4TS U2354 ( .A(n5060), .Y(n1160) );
INVX2TS U2355 ( .A(n1067), .Y(n1580) );
AND2X2TS U2356 ( .A(n5132), .B(FPADDSUB_DMP_SFG[14]), .Y(n4423) );
AND2X2TS U2357 ( .A(n5147), .B(FPADDSUB_DMP_SFG[16]), .Y(n4427) );
OR2X2TS U2358 ( .A(n5175), .B(FPADDSUB_DMP_SFG[20]), .Y(n4470) );
NOR2X1TS U2359 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n4319) );
CLKMX2X2TS U2360 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
INVX2TS U2361 ( .A(n3774), .Y(n3819) );
NOR2X4TS U2362 ( .A(n1422), .B(n1421), .Y(n1420) );
NAND2X4TS U2363 ( .A(n3459), .B(n3458), .Y(n3841) );
NOR2X4TS U2364 ( .A(n3459), .B(n3458), .Y(n3839) );
NOR2X4TS U2365 ( .A(n3787), .B(n3801), .Y(n1338) );
NAND3X4TS U2366 ( .A(n1435), .B(n1434), .C(n1478), .Y(n3459) );
NAND2X4TS U2367 ( .A(n3851), .B(n3848), .Y(n3787) );
INVX2TS U2368 ( .A(n3846), .Y(n3229) );
INVX2TS U2369 ( .A(n3847), .Y(n3228) );
NOR2X4TS U2370 ( .A(n1344), .B(n1345), .Y(n1341) );
NAND2X4TS U2371 ( .A(n1433), .B(n1430), .Y(n1429) );
NAND2X4TS U2372 ( .A(n1604), .B(n1603), .Y(n1602) );
INVX4TS U2373 ( .A(n3227), .Y(n3157) );
NAND2X4TS U2374 ( .A(n3225), .B(n3224), .Y(n3846) );
OAI21X2TS U2375 ( .A0(n3444), .A1(n1480), .B0(n1479), .Y(n1478) );
INVX6TS U2376 ( .A(n3448), .Y(n956) );
INVX2TS U2377 ( .A(n3449), .Y(n3427) );
INVX2TS U2378 ( .A(n2873), .Y(n2750) );
NOR2X6TS U2379 ( .A(n2873), .B(n2870), .Y(n1416) );
INVX2TS U2380 ( .A(n2870), .Y(n2662) );
NAND2X2TS U2381 ( .A(n1573), .B(n1388), .Y(n3086) );
OR2X4TS U2382 ( .A(n3756), .B(n1679), .Y(n1052) );
INVX2TS U2383 ( .A(n3452), .Y(n1428) );
NOR2X4TS U2384 ( .A(n1301), .B(n1513), .Y(n1290) );
NOR2X4TS U2385 ( .A(n1316), .B(n1315), .Y(n1314) );
NAND2X2TS U2386 ( .A(n1687), .B(n2593), .Y(n2564) );
NOR2X4TS U2387 ( .A(n1468), .B(n2593), .Y(n1316) );
AND2X4TS U2388 ( .A(n947), .B(n4167), .Y(n4168) );
INVX2TS U2389 ( .A(n3426), .Y(n3451) );
NAND2X4TS U2390 ( .A(n2342), .B(n2341), .Y(n2841) );
NAND2X4TS U2391 ( .A(n2467), .B(n2468), .Y(n2593) );
INVX2TS U2392 ( .A(n2468), .Y(n1312) );
NAND2X2TS U2393 ( .A(n2781), .B(n1056), .Y(n2182) );
NAND2X4TS U2394 ( .A(n2523), .B(n2522), .Y(n2594) );
NOR2X4TS U2395 ( .A(n3674), .B(n3763), .Y(n3769) );
NAND2X4TS U2396 ( .A(n3406), .B(n3405), .Y(n3545) );
INVX4TS U2397 ( .A(n3588), .Y(n3626) );
NAND2X4TS U2398 ( .A(n1612), .B(n2399), .Y(n2401) );
NAND2X2TS U2399 ( .A(n2176), .B(n2175), .Y(n2782) );
AND2X2TS U2400 ( .A(n4017), .B(n4016), .Y(n4033) );
NOR2X4TS U2401 ( .A(n2175), .B(n2176), .Y(n2102) );
INVX2TS U2402 ( .A(n1497), .Y(n1494) );
NAND2X2TS U2403 ( .A(n2938), .B(n2937), .Y(n2978) );
AOI21X2TS U2404 ( .A0(n2675), .A1(n2566), .B0(n2565), .Y(n2569) );
AOI21X2TS U2405 ( .A0(n2675), .A1(n2579), .B0(n2578), .Y(n2582) );
OAI21X1TS U2406 ( .A0(n3495), .A1(n3686), .B0(n3690), .Y(n3496) );
NAND2X4TS U2407 ( .A(n3004), .B(n3003), .Y(n3067) );
INVX2TS U2408 ( .A(n3007), .Y(n1379) );
NAND2X4TS U2409 ( .A(n1329), .B(n1325), .Y(n2658) );
OAI21X1TS U2410 ( .A0(n3741), .A1(n3740), .B0(n3739), .Y(n3742) );
NAND2X4TS U2411 ( .A(n3162), .B(n3161), .Y(n3165) );
ADDFHX2TS U2412 ( .A(n3595), .B(n3594), .CI(n3593), .CO(n3616), .S(n3576) );
INVX2TS U2413 ( .A(n1515), .Y(n1518) );
NAND2X4TS U2414 ( .A(n1381), .B(n1380), .Y(n3005) );
NAND2X4TS U2415 ( .A(n3687), .B(n3693), .Y(n3732) );
INVX2TS U2416 ( .A(n3163), .Y(n1611) );
INVX2TS U2417 ( .A(n2665), .Y(n2308) );
NAND2X4TS U2418 ( .A(n1522), .B(n1521), .Y(n2503) );
NAND2X4TS U2419 ( .A(n2307), .B(n1630), .Y(n2547) );
AND2X2TS U2420 ( .A(n3263), .B(n1396), .Y(n3264) );
OAI21X2TS U2421 ( .A0(n3691), .A1(n3690), .B0(n3689), .Y(n3692) );
INVX2TS U2422 ( .A(n3001), .Y(n2998) );
ADDFHX2TS U2423 ( .A(n3177), .B(n3176), .CI(n3175), .CO(n3276), .S(n3166) );
NAND2X4TS U2424 ( .A(n2328), .B(n2306), .Y(n2665) );
INVX2TS U2425 ( .A(n3738), .Y(n3697) );
NOR2X4TS U2426 ( .A(n1438), .B(n1436), .Y(n1685) );
NAND2X2TS U2427 ( .A(n2330), .B(n2306), .Y(n2307) );
OAI2BB1X2TS U2428 ( .A0N(n1071), .A1N(n2266), .B0(n2265), .Y(n2357) );
ADDFHX2TS U2429 ( .A(n2500), .B(n2499), .CI(n2498), .CO(n2635), .S(n2495) );
INVX2TS U2430 ( .A(n2104), .Y(n2077) );
INVX2TS U2431 ( .A(n1470), .Y(n3271) );
NAND2X2TS U2432 ( .A(n2165), .B(n1463), .Y(n1462) );
INVX4TS U2433 ( .A(n3054), .Y(n3098) );
INVX2TS U2434 ( .A(n2884), .Y(n2885) );
NAND2X4TS U2435 ( .A(n2224), .B(n2223), .Y(n3412) );
ADDFHX2TS U2436 ( .A(n3204), .B(n3203), .CI(n3202), .CO(n3251), .S(n3206) );
INVX2TS U2437 ( .A(n3712), .Y(n3520) );
INVX2TS U2438 ( .A(n3711), .Y(n3561) );
INVX2TS U2439 ( .A(n3745), .Y(n3563) );
NAND2X4TS U2440 ( .A(n1502), .B(n1499), .Y(n2894) );
ADDHX2TS U2441 ( .A(n2716), .B(n2715), .CO(n2910), .S(n2739) );
INVX2TS U2442 ( .A(n1548), .Y(n1475) );
NAND2X2TS U2443 ( .A(n1500), .B(n2700), .Y(n1499) );
NAND2X2TS U2444 ( .A(n1503), .B(n2701), .Y(n1502) );
INVX2TS U2445 ( .A(n1375), .Y(n1304) );
INVX2TS U2446 ( .A(n3556), .Y(n3611) );
INVX2TS U2447 ( .A(n3386), .Y(n3519) );
ADDFHX2TS U2448 ( .A(n2311), .B(n2310), .CI(n2309), .CO(n3292), .S(n3256) );
INVX2TS U2449 ( .A(n2702), .Y(n1503) );
INVX2TS U2450 ( .A(n2110), .Y(n1309) );
NAND2X2TS U2451 ( .A(n2042), .B(n2041), .Y(n2043) );
NAND2X4TS U2452 ( .A(n1511), .B(n1510), .Y(n2691) );
INVX2TS U2453 ( .A(n3560), .Y(n3607) );
NOR2X4TS U2454 ( .A(n2145), .B(n2144), .Y(n2220) );
BUFX12TS U2455 ( .A(n1064), .Y(n3269) );
NAND2X2TS U2456 ( .A(n2619), .B(n2620), .Y(n1510) );
INVX2TS U2457 ( .A(n1979), .Y(n2041) );
ADDHX2TS U2458 ( .A(n2696), .B(n2695), .CO(n2900), .S(n2700) );
INVX4TS U2459 ( .A(n1144), .Y(n1292) );
ADDFHX2TS U2460 ( .A(n2083), .B(n2082), .CI(n2081), .CO(n2110), .S(n2084) );
NAND2X4TS U2461 ( .A(n1324), .B(n1323), .Y(n1322) );
BUFX6TS U2462 ( .A(n1377), .Y(n1410) );
INVX4TS U2463 ( .A(n4851), .Y(n4847) );
AOI32X1TS U2464 ( .A0(n4719), .A1(n3934), .A2(n5112), .B0(n910), .B1(n4717),
.Y(n4721) );
BUFX12TS U2465 ( .A(n3246), .Y(n3558) );
INVX4TS U2466 ( .A(n4851), .Y(n4849) );
ADDHX2TS U2467 ( .A(FPMULT_Sgf_normalized_result[6]), .B(n1033), .CO(n3781),
.S(FPMULT_Adder_M_result_A_adder[6]) );
INVX2TS U2468 ( .A(n1793), .Y(n1769) );
CLKINVX1TS U2469 ( .A(n4276), .Y(n4279) );
AND2X2TS U2470 ( .A(n959), .B(FPMULT_Sgf_normalized_result[5]), .Y(n1033) );
INVX1TS U2471 ( .A(n5281), .Y(n3978) );
NAND2X4TS U2472 ( .A(n1966), .B(n1577), .Y(n2063) );
NAND2X4TS U2473 ( .A(n2139), .B(n2138), .Y(n1584) );
INVX6TS U2474 ( .A(n1062), .Y(n1937) );
XOR2X1TS U2475 ( .A(n2626), .B(n1067), .Y(n1934) );
BUFX4TS U2476 ( .A(n3199), .Y(n1594) );
INVX2TS U2477 ( .A(n2505), .Y(n2455) );
INVX6TS U2478 ( .A(n3379), .Y(n1210) );
NAND2X1TS U2479 ( .A(n4228), .B(FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n4098) );
NOR2X4TS U2480 ( .A(FPADDSUB_Raw_mant_SGF[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n3912) );
INVX4TS U2481 ( .A(n1622), .Y(n1215) );
OAI21X1TS U2482 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n4628), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n4627) );
INVX2TS U2483 ( .A(n2297), .Y(n2120) );
INVX2TS U2484 ( .A(n2047), .Y(n1404) );
AND2X2TS U2485 ( .A(n5166), .B(FPADDSUB_DMP_SFG[18]), .Y(n4431) );
INVX1TS U2486 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n4088) );
CLKMX2X2TS U2487 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
XOR2X2TS U2488 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[15]), .Y(n1373) );
OR3X4TS U2489 ( .A(FPMULT_Sgf_normalized_result[1]), .B(
FPMULT_Sgf_normalized_result[0]), .C(FPMULT_Sgf_normalized_result[2]),
.Y(n3862) );
NOR3X1TS U2490 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n4791) );
AND2X4TS U2491 ( .A(n1347), .B(n3826), .Y(n1081) );
NAND3X4TS U2492 ( .A(n1343), .B(n3802), .C(n1342), .Y(n3844) );
NOR2X6TS U2493 ( .A(n1424), .B(n3839), .Y(n3826) );
NAND2X4TS U2494 ( .A(n3785), .B(n1338), .Y(n1343) );
AND3X8TS U2495 ( .A(n1431), .B(n1429), .C(n1425), .Y(n1424) );
NAND3X4TS U2496 ( .A(n1346), .B(n3859), .C(n1593), .Y(n1340) );
NAND3X4TS U2497 ( .A(n2867), .B(n3859), .C(n1593), .Y(n1339) );
AND2X4TS U2498 ( .A(n2868), .B(n2869), .Y(n1346) );
AND4X4TS U2499 ( .A(n2858), .B(n2857), .C(n2856), .D(n2855), .Y(n5209) );
NAND2X1TS U2500 ( .A(n3836), .B(n3835), .Y(n3837) );
XOR2X2TS U2501 ( .A(n2806), .B(n2805), .Y(n2814) );
INVX2TS U2502 ( .A(n2804), .Y(n2589) );
OAI21X1TS U2503 ( .A0(n4263), .A1(n1179), .B0(n4222), .Y(
FPADDSUB_Data_array_SWR[12]) );
OAI21X1TS U2504 ( .A0(n4275), .A1(n1178), .B0(n4274), .Y(
FPADDSUB_Data_array_SWR[13]) );
OAI21X1TS U2505 ( .A0(n4267), .A1(n1178), .B0(n4266), .Y(
FPADDSUB_Data_array_SWR[9]) );
OAI21X1TS U2506 ( .A0(n4246), .A1(n1178), .B0(n4192), .Y(
FPADDSUB_Data_array_SWR[4]) );
OAI21X1TS U2507 ( .A0(n4247), .A1(n1178), .B0(n4245), .Y(
FPADDSUB_Data_array_SWR[5]) );
AOI21X1TS U2508 ( .A0(n4224), .A1(n4253), .B0(n4199), .Y(n4200) );
NAND2X6TS U2509 ( .A(n1384), .B(n3027), .Y(n1286) );
NAND2X4TS U2510 ( .A(n1537), .B(n2584), .Y(n2836) );
NAND2X2TS U2511 ( .A(n3019), .B(n3028), .Y(n3020) );
NAND3X6TS U2512 ( .A(n2592), .B(n1334), .C(n1687), .Y(n1311) );
INVX2TS U2513 ( .A(n3367), .Y(n3443) );
NAND2X6TS U2514 ( .A(n1075), .B(n1313), .Y(n1334) );
NAND2X4TS U2515 ( .A(n2871), .B(n2872), .Y(n1359) );
INVX2TS U2516 ( .A(n3028), .Y(n2941) );
NOR2X6TS U2517 ( .A(n2344), .B(n2343), .Y(n2808) );
NAND2X6TS U2518 ( .A(n2940), .B(n2939), .Y(n3028) );
NAND2X6TS U2519 ( .A(n2403), .B(n1448), .Y(n1313) );
NAND2X2TS U2520 ( .A(n2594), .B(n2592), .Y(n2524) );
NAND2X6TS U2521 ( .A(n2661), .B(n2660), .Y(n2872) );
INVX2TS U2522 ( .A(n2593), .Y(n2469) );
NAND2X4TS U2523 ( .A(n1445), .B(n2401), .Y(n2571) );
INVX2TS U2524 ( .A(n3545), .Y(n1605) );
XOR2X2TS U2525 ( .A(n2327), .B(n2326), .Y(n2342) );
INVX2TS U2526 ( .A(n2401), .Y(n1443) );
NAND2X6TS U2527 ( .A(n1449), .B(n2325), .Y(n1448) );
INVX2TS U2528 ( .A(n3431), .Y(n3433) );
NAND3X4TS U2529 ( .A(n1076), .B(n1453), .C(n1451), .Y(n1449) );
AO22X1TS U2530 ( .A0(n1138), .A1(FPADDSUB_LZD_raw_out_EWR[2]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n5071), .Y(
FPADDSUB_shft_value_mux_o_EWR[2]) );
XOR2X1TS U2531 ( .A(n3811), .B(n3810), .Y(n1678) );
NAND2X4TS U2532 ( .A(n3371), .B(n3370), .Y(n3432) );
AO22X1TS U2533 ( .A0(n1138), .A1(FPADDSUB_LZD_raw_out_EWR[3]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .B1(n5169), .Y(
FPADDSUB_shft_value_mux_o_EWR[3]) );
AO22X1TS U2534 ( .A0(n1138), .A1(FPADDSUB_LZD_raw_out_EWR[4]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n5071), .Y(
FPADDSUB_shft_value_mux_o_EWR[4]) );
NAND2X6TS U2535 ( .A(n1452), .B(n2183), .Y(n1451) );
OAI211X1TS U2536 ( .A0(n4048), .A1(n5170), .B0(n4095), .C0(n4047), .Y(
FPADDSUB_LZD_raw_out_EWR[2]) );
ADDFHX2TS U2537 ( .A(n3506), .B(n3505), .CI(n3504), .CO(n3536), .S(n3405) );
XOR2X2TS U2538 ( .A(n2340), .B(n2339), .Y(n2341) );
XOR2X2TS U2539 ( .A(n2682), .B(n2681), .Y(n2683) );
NAND2X6TS U2540 ( .A(n1364), .B(n1363), .Y(n2744) );
OAI21X1TS U2541 ( .A0(n3806), .A1(n3805), .B0(n3804), .Y(n3811) );
XOR2X2TS U2542 ( .A(n2569), .B(n2568), .Y(n2585) );
AOI21X2TS U2543 ( .A0(n2675), .A1(n2554), .B0(n2553), .Y(n2563) );
NAND2X4TS U2544 ( .A(n1285), .B(n1284), .Y(n1283) );
OAI2BB1X2TS U2545 ( .A0N(n3327), .A1N(n3328), .B0(n1512), .Y(n3375) );
XOR2X2TS U2546 ( .A(n2075), .B(n2130), .Y(n2175) );
ADDFHX2TS U2547 ( .A(n3322), .B(n3321), .CI(n3320), .CO(n3361), .S(n3323) );
ADDFHX2TS U2548 ( .A(n3552), .B(n3551), .CI(n3550), .CO(n3577), .S(n3535) );
XOR2X2TS U2549 ( .A(n2101), .B(n2100), .Y(n2176) );
MX2X2TS U2550 ( .A(n4485), .B(n4484), .S0(n4555), .Y(
FPADDSUB_Raw_mant_SGF[24]) );
ADDFHX2TS U2551 ( .A(n2635), .B(n2634), .CI(n2633), .CO(n2746), .S(n2595) );
NAND3X6TS U2552 ( .A(n2183), .B(n1456), .C(n1458), .Y(n1453) );
AOI211X1TS U2553 ( .A0(n4280), .A1(n4279), .B0(n4278), .C0(n4277), .Y(n4282)
);
AOI211X1TS U2554 ( .A0(n3876), .A1(FPADDSUB_Raw_mant_NRM_SWR[0]), .B0(n3917),
.C0(n4277), .Y(n3878) );
ADDFHX2TS U2555 ( .A(n3534), .B(n3533), .CI(n3532), .CO(n3550), .S(n3505) );
NOR2X1TS U2556 ( .A(n3732), .B(n3698), .Y(n3700) );
ADDFHX2TS U2557 ( .A(n3284), .B(n3283), .CI(n3282), .CO(n3363), .S(n3320) );
OAI21X1TS U2558 ( .A0(n3741), .A1(n3708), .B0(n3707), .Y(n3709) );
ADDFHX2TS U2559 ( .A(n2729), .B(n2728), .CI(n2727), .CO(n2916), .S(n2723) );
OR2X2TS U2560 ( .A(n3647), .B(n3646), .Y(n1637) );
NOR2X1TS U2561 ( .A(n3732), .B(n3725), .Y(n3717) );
CLKMX2X2TS U2562 ( .A(n4475), .B(n4474), .S0(n4555), .Y(
FPADDSUB_Raw_mant_SGF[23]) );
AND2X2TS U2563 ( .A(n1130), .B(FPADDSUB_sftr_odat_SHT2_SWR[20]), .Y(
FPADDSUB_formatted_number_W[18]) );
INVX2TS U2564 ( .A(n2128), .Y(n1457) );
AND2X2TS U2565 ( .A(n1131), .B(n5135), .Y(FPADDSUB_formatted_number_W[11])
);
NOR2X4TS U2566 ( .A(n2129), .B(n1540), .Y(n1539) );
NAND2X4TS U2567 ( .A(n1355), .B(n1354), .Y(n2398) );
NAND2X6TS U2568 ( .A(n1901), .B(n1900), .Y(n2103) );
CLKMX2X2TS U2569 ( .A(n4464), .B(n4463), .S0(n4462), .Y(
FPADDSUB_Raw_mant_SGF[22]) );
AND2X2TS U2570 ( .A(n1131), .B(FPADDSUB_sftr_odat_SHT2_SWR[22]), .Y(
FPADDSUB_formatted_number_W[20]) );
ADDFHX2TS U2571 ( .A(n3392), .B(n3391), .CI(n3390), .CO(n3533), .S(n3402) );
ADDFHX2TS U2572 ( .A(n2417), .B(n2416), .CI(n2415), .CO(n2471), .S(n2461) );
AND2X2TS U2573 ( .A(n1130), .B(FPADDSUB_sftr_odat_SHT2_SWR[16]), .Y(
FPADDSUB_formatted_number_W[14]) );
AND2X2TS U2574 ( .A(n1131), .B(FPADDSUB_sftr_odat_SHT2_SWR[2]), .Y(
FPADDSUB_formatted_number_W[0]) );
ADDFHX2TS U2575 ( .A(n3348), .B(n3347), .CI(n3346), .CO(n3376), .S(n3328) );
ADDFHX2TS U2576 ( .A(n3575), .B(n3574), .CI(n3573), .CO(n3593), .S(n3551) );
AND2X2TS U2577 ( .A(n1130), .B(FPADDSUB_sftr_odat_SHT2_SWR[19]), .Y(
FPADDSUB_formatted_number_W[17]) );
INVX2TS U2578 ( .A(n3694), .Y(n3495) );
AND2X2TS U2579 ( .A(n1130), .B(FPADDSUB_sftr_odat_SHT2_SWR[17]), .Y(
FPADDSUB_formatted_number_W[15]) );
INVX6TS U2580 ( .A(n2547), .Y(n2672) );
ADDFHX2TS U2581 ( .A(n2983), .B(n2982), .CI(n2981), .CO(n3066), .S(n2979) );
AND2X2TS U2582 ( .A(n1131), .B(FPADDSUB_sftr_odat_SHT2_SWR[23]), .Y(
FPADDSUB_formatted_number_W[21]) );
AND2X2TS U2583 ( .A(n1131), .B(n5136), .Y(FPADDSUB_formatted_number_W[10])
);
AND2X2TS U2584 ( .A(n1130), .B(n5133), .Y(FPADDSUB_formatted_number_W[13])
);
ADDFHX2TS U2585 ( .A(n3509), .B(n3508), .CI(n3507), .CO(n3552), .S(n3532) );
AND2X2TS U2586 ( .A(n1130), .B(FPADDSUB_sftr_odat_SHT2_SWR[18]), .Y(
FPADDSUB_formatted_number_W[16]) );
AND2X2TS U2587 ( .A(n1130), .B(FPADDSUB_sftr_odat_SHT2_SWR[24]), .Y(
FPADDSUB_formatted_number_W[22]) );
AND2X2TS U2588 ( .A(n1131), .B(FPADDSUB_sftr_odat_SHT2_SWR[21]), .Y(
FPADDSUB_formatted_number_W[19]) );
AOI21X2TS U2589 ( .A0(n3482), .A1(n3651), .B0(n3481), .Y(n3483) );
NAND2X2TS U2590 ( .A(n3482), .B(n3649), .Y(n3484) );
OAI31X1TS U2591 ( .A0(n3871), .A1(FPADDSUB_Raw_mant_NRM_SWR[10]), .A2(n3908),
.B0(n4038), .Y(n3879) );
CLKMX2X2TS U2592 ( .A(n4436), .B(n4435), .S0(n4462), .Y(
FPADDSUB_Raw_mant_SGF[21]) );
OAI2BB1X2TS U2593 ( .A0N(n3031), .A1N(n1586), .B0(n1585), .Y(n3095) );
ADDFHX2TS U2594 ( .A(n2707), .B(n2706), .CI(n2705), .CO(n2935), .S(n2743) );
INVX4TS U2595 ( .A(n2231), .Y(n1450) );
INVX6TS U2596 ( .A(n1991), .Y(n2761) );
AND2X4TS U2597 ( .A(n4046), .B(n5160), .Y(n3876) );
OA21X2TS U2598 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B0(n4046), .Y(n3875) );
ADDFHX2TS U2599 ( .A(n3278), .B(n3277), .CI(n3276), .CO(n3282), .S(n3232) );
OAI21X1TS U2600 ( .A0(n4020), .A1(n4019), .B0(n4018), .Y(n4025) );
AND2X2TS U2601 ( .A(n1036), .B(n5134), .Y(FPADDSUB_formatted_number_W[12])
);
ADDFHX2TS U2602 ( .A(n3189), .B(n3188), .CI(n3187), .CO(n3260), .S(n3181) );
ADDFHX2TS U2603 ( .A(n3523), .B(n3522), .CI(n3521), .CO(n3574), .S(n3534) );
ADDFHX2TS U2604 ( .A(n3531), .B(n3530), .CI(n3529), .CO(n3553), .S(n3508) );
AND2X2TS U2605 ( .A(n1036), .B(FPADDSUB_sftr_odat_SHT2_SWR[4]), .Y(
FPADDSUB_formatted_number_W[2]) );
ADDFHX2TS U2606 ( .A(n3137), .B(n3136), .CI(n3135), .CO(n3163), .S(n3125) );
NAND2X4TS U2607 ( .A(n1368), .B(n2492), .Y(n1360) );
CLKMX2X2TS U2608 ( .A(n4444), .B(n4443), .S0(n4462), .Y(
FPADDSUB_Raw_mant_SGF[20]) );
ADDFHX2TS U2609 ( .A(n2172), .B(n2171), .CI(n2170), .CO(n2173), .S(n2071) );
OAI21X2TS U2610 ( .A0(n3445), .A1(n3418), .B0(n3417), .Y(n3479) );
ADDFHX2TS U2611 ( .A(n3287), .B(n3286), .CI(n3285), .CO(n3351), .S(n3315) );
INVX2TS U2612 ( .A(n2887), .Y(n2714) );
AND2X2TS U2613 ( .A(n1036), .B(n5137), .Y(FPADDSUB_formatted_number_W[9]) );
OR2X2TS U2614 ( .A(n5337), .B(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
FPADDSUB_formatted_number_W[25]) );
INVX2TS U2615 ( .A(n3487), .Y(n3175) );
XOR3X2TS U2616 ( .A(n3645), .B(n3644), .C(n3643), .Y(n3646) );
OR2X2TS U2617 ( .A(n5337), .B(FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(
FPADDSUB_formatted_number_W[24]) );
OR2X2TS U2618 ( .A(n5337), .B(FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
FPADDSUB_formatted_number_W[23]) );
XOR2X2TS U2619 ( .A(n2361), .B(n2360), .Y(n2255) );
XNOR2X2TS U2620 ( .A(n3102), .B(n3101), .Y(n3063) );
CLKMX2X2TS U2621 ( .A(n4453), .B(n4452), .S0(n4462), .Y(
FPADDSUB_Raw_mant_SGF[19]) );
XOR2X2TS U2622 ( .A(n3030), .B(n1586), .Y(n2975) );
ADDFHX2TS U2623 ( .A(n2740), .B(n2739), .CI(n2738), .CO(n2920), .S(n2729) );
AOI2BB1X1TS U2624 ( .A0N(n5337), .A1N(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(
n5338), .Y(FPADDSUB_formatted_number_W[31]) );
OR2X2TS U2625 ( .A(n5337), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(
FPADDSUB_formatted_number_W[28]) );
OR2X2TS U2626 ( .A(n5337), .B(FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(
FPADDSUB_formatted_number_W[27]) );
OR2X2TS U2627 ( .A(n5337), .B(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
FPADDSUB_formatted_number_W[26]) );
NOR2X4TS U2628 ( .A(n3489), .B(n3490), .Y(n3686) );
OR2X2TS U2629 ( .A(n2664), .B(n2670), .Y(n1043) );
INVX2TS U2630 ( .A(n3872), .Y(n3873) );
ADDFHX2TS U2631 ( .A(n2646), .B(n2645), .CI(n2644), .CO(n2738), .S(n2605) );
CLKMX2X2TS U2632 ( .A(n4500), .B(n4499), .S0(n4555), .Y(
FPADDSUB_Raw_mant_SGF[18]) );
ADDFHX2TS U2633 ( .A(n3171), .B(n3170), .CI(n3169), .CO(n3278), .S(n3187) );
NAND2X2TS U2634 ( .A(n3480), .B(n3472), .Y(n3580) );
INVX3TS U2635 ( .A(n2686), .Y(n2934) );
NOR2X1TS U2636 ( .A(n3632), .B(n1143), .Y(n3636) );
INVX4TS U2637 ( .A(n2883), .Y(n2962) );
OAI2BB1X2TS U2638 ( .A0N(n2037), .A1N(n2036), .B0(n2035), .Y(n2172) );
OAI21X1TS U2639 ( .A0(n3735), .A1(n3734), .B0(n3733), .Y(n3736) );
CLKMX2X2TS U2640 ( .A(n4509), .B(n4508), .S0(n4555), .Y(
FPADDSUB_Raw_mant_SGF[17]) );
XOR2X2TS U2641 ( .A(n2068), .B(n2069), .Y(n1544) );
ADDFHX2TS U2642 ( .A(n3639), .B(n3638), .CI(n3637), .CO(n3644), .S(n3641) );
ADDFHX2TS U2643 ( .A(n3711), .B(n3520), .CI(n3519), .CO(n3564), .S(n3523) );
NAND2X6TS U2644 ( .A(n2947), .B(n2946), .Y(n3060) );
INVX2TS U2645 ( .A(n1874), .Y(n2799) );
CLKMX2X2TS U2646 ( .A(n4517), .B(n4516), .S0(n4555), .Y(
FPADDSUB_Raw_mant_SGF[16]) );
NAND2X4TS U2647 ( .A(n2044), .B(n2043), .Y(n2165) );
OR2X2TS U2648 ( .A(n3221), .B(n3222), .Y(n1656) );
INVX6TS U2649 ( .A(n3472), .Y(n2606) );
ADDFHX2TS U2650 ( .A(n3563), .B(n3562), .CI(n3561), .CO(n3609), .S(n3566) );
ADDFHX2TS U2651 ( .A(n3118), .B(n3117), .CI(n3116), .CO(n3205), .S(n3138) );
NAND2X2TS U2652 ( .A(n1926), .B(n1925), .Y(n2078) );
NAND2X2TS U2653 ( .A(n1772), .B(n1771), .Y(n1929) );
XOR2X2TS U2654 ( .A(n2034), .B(n1543), .Y(n1542) );
AOI31X1TS U2655 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n4091), .A2(n3910),
.B0(n4278), .Y(n3915) );
ADDFHX2TS U2656 ( .A(n1987), .B(n1986), .CI(n1985), .CO(n1988), .S(n1958) );
INVX4TS U2657 ( .A(n2494), .Y(n2598) );
OAI21X1TS U2658 ( .A0(n4160), .A1(n1199), .B0(n4000), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[25]) );
INVX2TS U2659 ( .A(n3907), .Y(n4283) );
ADDFHX2TS U2660 ( .A(n3570), .B(n3569), .CI(n3568), .CO(n3597), .S(n3565) );
NAND2X1TS U2661 ( .A(n1623), .B(n2680), .Y(n2681) );
NAND2X1TS U2662 ( .A(n1624), .B(n2666), .Y(n2562) );
INVX2TS U2663 ( .A(n3808), .Y(n3608) );
OAI21X1TS U2664 ( .A0(n1044), .A1(n4291), .B0(n3991), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[1]) );
NAND2X4TS U2665 ( .A(n1289), .B(n1288), .Y(n2991) );
ADDFHX2TS U2666 ( .A(n1799), .B(n1798), .CI(n1797), .CO(n1804), .S(n1806) );
OAI21X1TS U2667 ( .A0(n1199), .A1(n4291), .B0(n3996), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[0]) );
NAND2X1TS U2668 ( .A(n1625), .B(n2567), .Y(n2568) );
ADDFHX2TS U2669 ( .A(n2617), .B(n2616), .CI(n2615), .CO(n2736), .S(n2608) );
ADDFHX2TS U2670 ( .A(n2160), .B(n2159), .CI(n2158), .CO(n2206), .S(n2168) );
CLKMX2X2TS U2671 ( .A(n4526), .B(n4525), .S0(n4555), .Y(
FPADDSUB_Raw_mant_SGF[15]) );
AO22X1TS U2672 ( .A0(n4860), .A1(FPSENCOS_d_ff_Yn[10]), .B0(n4859), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(FPSENCOS_mux_sal[10]) );
AO22X1TS U2673 ( .A0(n4863), .A1(FPSENCOS_d_ff_Yn[23]), .B0(n4861), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(FPSENCOS_mux_sal[23]) );
NAND2X2TS U2674 ( .A(n1720), .B(n1719), .Y(n1799) );
AO22X1TS U2675 ( .A0(n4860), .A1(FPSENCOS_d_ff_Yn[16]), .B0(n4859), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(FPSENCOS_mux_sal[16]) );
AO22X1TS U2676 ( .A0(n4863), .A1(FPSENCOS_d_ff_Yn[21]), .B0(n4862), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(FPSENCOS_mux_sal[21]) );
AO22X1TS U2677 ( .A0(n4860), .A1(FPSENCOS_d_ff_Yn[13]), .B0(n4859), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(FPSENCOS_mux_sal[13]) );
AO22X1TS U2678 ( .A0(n4860), .A1(FPSENCOS_d_ff_Yn[11]), .B0(n4859), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(FPSENCOS_mux_sal[11]) );
ADDFHX2TS U2679 ( .A(n3344), .B(n3343), .CI(n3342), .CO(n3383), .S(n3357) );
ADDFHX2TS U2680 ( .A(n2528), .B(n2527), .CI(n2526), .CO(n3335), .S(n3291) );
AO22X1TS U2681 ( .A0(n4863), .A1(FPSENCOS_d_ff_Yn[22]), .B0(n4861), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(FPSENCOS_mux_sal[22]) );
OR2X2TS U2682 ( .A(n3556), .B(n3560), .Y(n1623) );
CLKMX2X2TS U2683 ( .A(n4534), .B(n4533), .S0(n4555), .Y(
FPADDSUB_Raw_mant_SGF[14]) );
AO22X1TS U2684 ( .A0(n4860), .A1(FPSENCOS_d_ff_Yn[14]), .B0(n4859), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(FPSENCOS_mux_sal[14]) );
OAI21X1TS U2685 ( .A0(n910), .A1(n4717), .B0(n3919), .Y(
FPMULT_FS_Module_state_next[0]) );
AO22X1TS U2686 ( .A0(n4863), .A1(FPSENCOS_d_ff_Yn[19]), .B0(n4861), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(FPSENCOS_mux_sal[19]) );
AO22X1TS U2687 ( .A0(n4860), .A1(FPSENCOS_d_ff_Yn[17]), .B0(n4861), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(FPSENCOS_mux_sal[17]) );
NAND2X6TS U2688 ( .A(n1375), .B(n1389), .Y(n2712) );
ADDFHX2TS U2689 ( .A(n2905), .B(n2904), .CI(n2903), .CO(n2943), .S(n2925) );
CLKMX2X2TS U2690 ( .A(n4367), .B(n4366), .S0(n4462), .Y(
FPADDSUB_Raw_mant_SGF[8]) );
CLKMX2X2TS U2691 ( .A(n4353), .B(n4352), .S0(n4462), .Y(
FPADDSUB_Raw_mant_SGF[9]) );
AO22X1TS U2692 ( .A0(n4863), .A1(FPSENCOS_d_ff_Yn[20]), .B0(n4864), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(FPSENCOS_mux_sal[20]) );
CLKMX2X2TS U2693 ( .A(n4545), .B(n4544), .S0(n4555), .Y(
FPADDSUB_Raw_mant_SGF[10]) );
AO22X1TS U2694 ( .A0(n4860), .A1(FPSENCOS_d_ff_Yn[15]), .B0(n4859), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(FPSENCOS_mux_sal[15]) );
ADDFHX2TS U2695 ( .A(n2284), .B(n2283), .CI(n2282), .CO(n3414), .S(n3413) );
AO22X1TS U2696 ( .A0(n4865), .A1(FPSENCOS_d_ff_Yn[30]), .B0(n4864), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(FPSENCOS_mux_sal[30]) );
AO22X1TS U2697 ( .A0(n4860), .A1(FPSENCOS_d_ff_Yn[9]), .B0(n4859), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(FPSENCOS_mux_sal[9]) );
CLKMX2X2TS U2698 ( .A(n4383), .B(n4382), .S0(n4462), .Y(
FPADDSUB_Raw_mant_SGF[12]) );
AO22X1TS U2699 ( .A0(n4865), .A1(FPSENCOS_d_ff_Yn[29]), .B0(n4864), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(FPSENCOS_mux_sal[29]) );
AO22X1TS U2700 ( .A0(n4860), .A1(FPSENCOS_d_ff_Yn[18]), .B0(n4861), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(FPSENCOS_mux_sal[18]) );
ADDFHX2TS U2701 ( .A(n2950), .B(n2949), .CI(n2948), .CO(n3059), .S(n2997) );
AO22X1TS U2702 ( .A0(n4863), .A1(FPSENCOS_d_ff_Yn[28]), .B0(n4864), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(FPSENCOS_mux_sal[28]) );
ADDFHX2TS U2703 ( .A(n2485), .B(n2484), .CI(n2483), .CO(n2616), .S(n2516) );
AO22X1TS U2704 ( .A0(n4863), .A1(FPSENCOS_d_ff_Yn[25]), .B0(n4864), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(FPSENCOS_mux_sal[25]) );
AO22X1TS U2705 ( .A0(n4863), .A1(FPSENCOS_d_ff_Yn[26]), .B0(n4864), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(FPSENCOS_mux_sal[26]) );
AO22X1TS U2706 ( .A0(n4860), .A1(FPSENCOS_d_ff_Yn[12]), .B0(n4859), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(FPSENCOS_mux_sal[12]) );
CLKMX2X2TS U2707 ( .A(n4411), .B(n4410), .S0(n4462), .Y(
FPADDSUB_Raw_mant_SGF[11]) );
ADDFHX2TS U2708 ( .A(n1904), .B(n1903), .CI(n1902), .CO(n2080), .S(n1920) );
NOR2X4TS U2709 ( .A(n1409), .B(n1408), .Y(n1407) );
AO22X1TS U2710 ( .A0(n4863), .A1(FPSENCOS_d_ff_Yn[27]), .B0(n4864), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(FPSENCOS_mux_sal[27]) );
AO22X1TS U2711 ( .A0(n4863), .A1(FPSENCOS_d_ff_Yn[24]), .B0(n4862), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(FPSENCOS_mux_sal[24]) );
AO22X1TS U2712 ( .A0(n4858), .A1(FPSENCOS_d_ff_Yn[4]), .B0(n4862), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(FPSENCOS_mux_sal[4]) );
ADDFHX2TS U2713 ( .A(n1887), .B(n1886), .CI(n1885), .CO(n1889), .S(n1891) );
INVX3TS U2714 ( .A(n1459), .Y(n3072) );
ADDFHX2TS U2715 ( .A(n2557), .B(n2556), .CI(n2555), .CO(n3518), .S(n3386) );
ADDFHX2TS U2716 ( .A(n1673), .B(n3194), .CI(n3193), .CO(n3249), .S(n3204) );
ADDFHX2TS U2717 ( .A(n2540), .B(n2539), .CI(n2538), .CO(n3396), .S(n3360) );
CLKMX2X2TS U2718 ( .A(n4557), .B(n4556), .S0(n4555), .Y(
FPADDSUB_Raw_mant_SGF[7]) );
XNOR2X2TS U2719 ( .A(n1712), .B(n1716), .Y(n1744) );
AO22X1TS U2720 ( .A0(n4858), .A1(FPSENCOS_d_ff_Yn[2]), .B0(n4862), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(FPSENCOS_mux_sal[2]) );
OR2X2TS U2721 ( .A(FPMULT_FSM_selector_C), .B(n4721), .Y(n1092) );
ADDFHX2TS U2722 ( .A(n1781), .B(n1780), .CI(n1779), .CO(n1800), .S(n1808) );
NOR2X1TS U2723 ( .A(n3602), .B(n1126), .Y(n1084) );
ADDFHX2TS U2724 ( .A(n1841), .B(n1840), .CI(n1839), .CO(n2131), .S(n2062) );
ADDFHX2TS U2725 ( .A(n2317), .B(n2316), .CI(n2315), .CO(n2527), .S(n2310) );
ADDFHX2TS U2726 ( .A(n1758), .B(n1757), .CI(n1756), .CO(n1760), .S(n1888) );
ADDFHX2TS U2727 ( .A(n2302), .B(n2301), .CI(n2300), .CO(n2309), .S(n2303) );
OR2X2TS U2728 ( .A(n4721), .B(n5152), .Y(n1090) );
CLKMX2X2TS U2729 ( .A(n4398), .B(n4397), .S0(n4462), .Y(
FPADDSUB_Raw_mant_SGF[13]) );
OAI21X1TS U2730 ( .A0(n4301), .A1(n1102), .B0(n3901), .Y(n3902) );
AO22X1TS U2731 ( .A0(n4858), .A1(FPSENCOS_d_ff_Yn[5]), .B0(n4862), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(FPSENCOS_mux_sal[5]) );
AO22X1TS U2732 ( .A0(n4858), .A1(FPSENCOS_d_ff_Yn[1]), .B0(n4862), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(FPSENCOS_mux_sal[1]) );
XOR2X1TS U2733 ( .A(FPSENCOS_d_ff2_X[30]), .B(n5075), .Y(
FPSENCOS_sh_exp_x[7]) );
OAI21X1TS U2734 ( .A0(n4301), .A1(n5165), .B0(n4300), .Y(n4302) );
OAI31X1TS U2735 ( .A0(n910), .A1(n4717), .A2(n5107), .B0(n3924), .Y(
FPMULT_FS_Module_state_next[1]) );
NAND2X2TS U2736 ( .A(n1411), .B(n2199), .Y(n1408) );
OAI21X1TS U2737 ( .A0(n5162), .A1(n4301), .B0(n4296), .Y(n4297) );
OAI21X1TS U2738 ( .A0(n4301), .A1(n1103), .B0(n3899), .Y(n3900) );
AO22X1TS U2739 ( .A0(n4858), .A1(FPSENCOS_d_ff_Yn[7]), .B0(n4859), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(FPSENCOS_mux_sal[7]) );
CLKMX2X2TS U2740 ( .A(n4568), .B(n4567), .S0(n4604), .Y(
FPADDSUB_Raw_mant_SGF[6]) );
XOR2X2TS U2741 ( .A(n2478), .B(n2613), .Y(n2610) );
AO22X1TS U2742 ( .A0(n4858), .A1(FPSENCOS_d_ff_Yn[3]), .B0(n4862), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(FPSENCOS_mux_sal[3]) );
AO22X1TS U2743 ( .A0(n4858), .A1(FPSENCOS_d_ff_Yn[6]), .B0(n4862), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(FPSENCOS_mux_sal[6]) );
CMPR22X2TS U2744 ( .A(n2212), .B(n2211), .CO(n2283), .S(n2219) );
AO22X1TS U2745 ( .A0(n4858), .A1(FPSENCOS_d_ff_Yn[0]), .B0(n4861), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(FPSENCOS_mux_sal[0]) );
XOR2X1TS U2746 ( .A(FPSENCOS_d_ff2_Y[30]), .B(n5072), .Y(
FPSENCOS_sh_exp_y[7]) );
AO22X1TS U2747 ( .A0(n4858), .A1(FPSENCOS_d_ff_Yn[8]), .B0(n4859), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(FPSENCOS_mux_sal[8]) );
ADDFHX2TS U2748 ( .A(n2699), .B(n2698), .CI(n2697), .CO(n2895), .S(n2690) );
OAI211X1TS U2749 ( .A0(operation[1]), .A1(n4081), .B0(n4080), .C0(n4079),
.Y(add_subt_data2[17]) );
OAI211X1TS U2750 ( .A0(operation[1]), .A1(n4055), .B0(n4054), .C0(n4062),
.Y(add_subt_data2[18]) );
AO22X1TS U2751 ( .A0(n4854), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n4853), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(FPSENCOS_first_mux_Z[29]) );
AO22X1TS U2752 ( .A0(n4848), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n4856), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(FPSENCOS_first_mux_Z[30]) );
CLKMX2X2TS U2753 ( .A(n4578), .B(n4577), .S0(n4604), .Y(
FPADDSUB_Raw_mant_SGF[5]) );
AO22X1TS U2754 ( .A0(n4855), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n4853), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(FPSENCOS_first_mux_Z[28]) );
OAI21X1TS U2755 ( .A0(n5077), .A1(n5206), .B0(n5076), .Y(
FPSENCOS_sh_exp_x[5]) );
AO21X1TS U2756 ( .A0(intadd_1033_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n5077),
.Y(FPSENCOS_sh_exp_x[4]) );
AO22X1TS U2757 ( .A0(n4848), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n4852), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(FPSENCOS_first_mux_Z[19]) );
XNOR2X2TS U2758 ( .A(n2619), .B(n2489), .Y(n2615) );
OAI21X1TS U2759 ( .A0(n5021), .A1(n5118), .B0(n5023), .Y(n854) );
NOR2X1TS U2760 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n5073), .Y(n5072) );
OAI21X1TS U2761 ( .A0(n5074), .A1(n5205), .B0(n5073), .Y(
FPSENCOS_sh_exp_y[5]) );
ADDFHX2TS U2762 ( .A(n3022), .B(n1943), .CI(n1942), .CO(n1969), .S(n1950) );
OR2X6TS U2763 ( .A(n1053), .B(n1597), .Y(n1057) );
AO22X1TS U2764 ( .A0(n4857), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n4853), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(FPSENCOS_first_mux_Z[22]) );
AO21X1TS U2765 ( .A0(intadd_1034_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n5074),
.Y(FPSENCOS_sh_exp_y[4]) );
ADDFHX2TS U2766 ( .A(n3110), .B(n3109), .CI(n3108), .CO(n3203), .S(n3117) );
CMPR22X2TS U2767 ( .A(n2482), .B(n2481), .CO(n2617), .S(n2480) );
XOR2X2TS U2768 ( .A(n1725), .B(n1724), .Y(n1730) );
OR2X2TS U2769 ( .A(FPMULT_FSM_selector_C), .B(n4722), .Y(n1091) );
OR2X2TS U2770 ( .A(n5152), .B(n4722), .Y(n4720) );
XOR2X1TS U2771 ( .A(intadd_1035_n1), .B(n4606), .Y(
FPADDSUB_Shift_amount_EXP_EW[4]) );
NOR2X1TS U2772 ( .A(FPSENCOS_d_ff2_X[29]), .B(n5076), .Y(n5075) );
AOI211X1TS U2773 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n5034), .B0(n5031), .C0(n4003), .Y(FPADDSUB_enable_Pipeline_input) );
AO22X1TS U2774 ( .A0(n4846), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n4853), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(FPSENCOS_first_mux_Z[23]) );
AO22X1TS U2775 ( .A0(n4854), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n4853), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(FPSENCOS_first_mux_Z[24]) );
AO22X1TS U2776 ( .A0(n4848), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n4853), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(FPSENCOS_first_mux_Z[25]) );
NOR2X6TS U2777 ( .A(n1509), .B(n1508), .Y(n2702) );
AO22X1TS U2778 ( .A0(n4857), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n4853), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(FPSENCOS_first_mux_Z[26]) );
AO22X1TS U2779 ( .A0(n4848), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n4853), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(FPSENCOS_first_mux_Z[27]) );
OR2X4TS U2780 ( .A(n1981), .B(n1980), .Y(n2042) );
NOR2X2TS U2781 ( .A(n3868), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n4280) );
AO22X1TS U2782 ( .A0(FPADDSUB_Data_array_SWR[42]), .A1(n1154), .B0(n1157),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n4304) );
AO22X1TS U2783 ( .A0(n4855), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n4856), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(FPSENCOS_first_mux_Z[31]) );
OAI21X1TS U2784 ( .A0(n4537), .A1(n4370), .B0(n4369), .Y(n4374) );
AO22X1TS U2785 ( .A0(n4846), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n4851), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(FPSENCOS_first_mux_Z[7]) );
AO22X1TS U2786 ( .A0(n4848), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n4852), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(FPSENCOS_first_mux_Z[15]) );
OAI21X1TS U2787 ( .A0(n4540), .A1(n4539), .B0(n4538), .Y(n4543) );
AO22X1TS U2788 ( .A0(n4848), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n4852), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(FPSENCOS_first_mux_Z[11]) );
AO22X1TS U2789 ( .A0(n4848), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n4852), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(FPSENCOS_first_mux_Z[17]) );
ADDFHX2TS U2790 ( .A(n2314), .B(n2313), .CI(n2312), .CO(n2528), .S(n2315) );
AND3X2TS U2791 ( .A(n4212), .B(n4211), .C(n4210), .Y(n4261) );
AO22X1TS U2792 ( .A0(n4848), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n4852), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(FPSENCOS_first_mux_Z[16]) );
AO22X1TS U2793 ( .A0(n4854), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n4851), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(FPSENCOS_first_mux_Z[9]) );
ADDFHX2TS U2794 ( .A(n2113), .B(n2112), .CI(n2111), .CO(n2305), .S(n2116) );
AO22X1TS U2795 ( .A0(n4846), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n4852), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(FPSENCOS_first_mux_Z[14]) );
OAI21X1TS U2796 ( .A0(n4554), .A1(n4362), .B0(n4361), .Y(n4365) );
AND3X2TS U2797 ( .A(n4100), .B(n4099), .C(n4098), .Y(n4251) );
ADDFHX2TS U2798 ( .A(n2120), .B(n2119), .CI(n2118), .CO(n2301), .S(n2114) );
AO22X1TS U2799 ( .A0(n4857), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n4851), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(FPSENCOS_first_mux_Z[6]) );
AO22X1TS U2800 ( .A0(n4846), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n4852), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(FPSENCOS_first_mux_Z[12]) );
AO22X1TS U2801 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1106), .B1(n5031),
.Y(n5033) );
AO22X1TS U2802 ( .A0(n4854), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n4853), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(FPSENCOS_first_mux_Z[20]) );
OAI21X1TS U2803 ( .A0(n4537), .A1(n4399), .B0(n4535), .Y(n4402) );
AO22X1TS U2804 ( .A0(n4848), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n4852), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(FPSENCOS_first_mux_Z[18]) );
AND3X2TS U2805 ( .A(n4231), .B(n4230), .C(n4229), .Y(n4839) );
AO22X1TS U2806 ( .A0(n4855), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n4853), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(FPSENCOS_first_mux_Z[21]) );
AO22X1TS U2807 ( .A0(n4855), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n4851), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(FPSENCOS_first_mux_Z[8]) );
AND3X2TS U2808 ( .A(n4178), .B(n4177), .C(n4176), .Y(n4840) );
AO22X1TS U2809 ( .A0(n1154), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n1157),
.B1(n1201), .Y(n4299) );
AO22X1TS U2810 ( .A0(n4848), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n4852), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(FPSENCOS_first_mux_Z[13]) );
NAND4X1TS U2811 ( .A(n5331), .B(n5330), .C(n5329), .D(n4808), .Y(n4810) );
NAND3X1TS U2812 ( .A(n4868), .B(n4874), .C(n4867), .Y(n4869) );
AO22X1TS U2813 ( .A0(n4857), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n4852), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(FPSENCOS_first_mux_Z[10]) );
OAI21X1TS U2814 ( .A0(n4540), .A1(n4388), .B0(n4391), .Y(n4381) );
OAI211X1TS U2815 ( .A0(operation[1]), .A1(n4068), .B0(n4067), .C0(n4079),
.Y(add_subt_data2[20]) );
OAI211X1TS U2816 ( .A0(operation[1]), .A1(n3983), .B0(n3982), .C0(n3984),
.Y(add_subt_data2[11]) );
OAI211X1TS U2817 ( .A0(operation[1]), .A1(n4075), .B0(n4074), .C0(n4073),
.Y(add_subt_data2[27]) );
BUFX4TS U2818 ( .A(n4964), .Y(n4945) );
OAI211X1TS U2819 ( .A0(operation[1]), .A1(n4008), .B0(n4007), .C0(n4059),
.Y(add_subt_data2[5]) );
OR2X2TS U2820 ( .A(FPSENCOS_d_ff_Xn[13]), .B(n3976), .Y(
FPSENCOS_first_mux_X[13]) );
AO22X1TS U2821 ( .A0(n4850), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n1691), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(FPSENCOS_first_mux_Z[0]) );
AO22X1TS U2822 ( .A0(n4850), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n4856), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(FPSENCOS_first_mux_Z[1]) );
XOR2X2TS U2823 ( .A(n2611), .B(n2614), .Y(n2478) );
OR2X2TS U2824 ( .A(n863), .B(n5024), .Y(n850) );
OR2X2TS U2825 ( .A(FPSENCOS_d_ff_Xn[1]), .B(n3975), .Y(
FPSENCOS_first_mux_X[1]) );
INVX6TS U2826 ( .A(n1527), .Y(n1221) );
OAI21X1TS U2827 ( .A0(n3936), .A1(n3935), .B0(n5152), .Y(n834) );
INVX2TS U2828 ( .A(n3015), .Y(n1980) );
OR2X2TS U2829 ( .A(FPSENCOS_d_ff_Xn[26]), .B(n4850), .Y(
FPSENCOS_first_mux_X[26]) );
AO22X1TS U2830 ( .A0(n4850), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n4851), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(FPSENCOS_first_mux_Z[5]) );
OR2X2TS U2831 ( .A(FPSENCOS_d_ff_Xn[10]), .B(n3976), .Y(
FPSENCOS_first_mux_X[10]) );
NOR2X1TS U2832 ( .A(n3973), .B(n3966), .Y(FPMULT_FSM_first_phase_load) );
OR2X2TS U2833 ( .A(FPSENCOS_d_ff_Xn[7]), .B(n3975), .Y(
FPSENCOS_first_mux_X[7]) );
NAND2X1TS U2834 ( .A(n2150), .B(n2198), .Y(n2151) );
NOR3X1TS U2835 ( .A(n5107), .B(n4719), .C(n3974), .Y(
FPMULT_FSM_final_result_load) );
INVX6TS U2836 ( .A(n950), .Y(n957) );
OR2X2TS U2837 ( .A(FPSENCOS_d_ff_Xn[12]), .B(n3976), .Y(
FPSENCOS_first_mux_X[12]) );
OAI2BB2X2TS U2838 ( .B0(n1209), .B1(n2421), .A0N(n3303), .A1N(n2420), .Y(
n2485) );
OR2X2TS U2839 ( .A(FPSENCOS_d_ff_Xn[6]), .B(n3975), .Y(
FPSENCOS_first_mux_X[6]) );
OR2X2TS U2840 ( .A(FPSENCOS_d_ff_Xn[14]), .B(n3976), .Y(
FPSENCOS_first_mux_X[14]) );
AO21X1TS U2841 ( .A0(n4294), .A1(n4872), .B0(FPSENCOS_enab_RB3), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
AO22X1TS U2842 ( .A0(n4850), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n4851), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(FPSENCOS_first_mux_Z[3]) );
OR2X2TS U2843 ( .A(FPSENCOS_d_ff_Xn[3]), .B(n3975), .Y(
FPSENCOS_first_mux_X[3]) );
CMPR22X2TS U2844 ( .A(n2053), .B(n2052), .CO(n3149), .S(n1979) );
XNOR2X2TS U2845 ( .A(n2245), .B(n2215), .Y(n2282) );
NAND2BX1TS U2846 ( .AN(n4876), .B(n4875), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
AND2X2TS U2847 ( .A(n1660), .B(n3089), .Y(n1661) );
OR2X2TS U2848 ( .A(FPSENCOS_d_ff_Xn[27]), .B(n4850), .Y(
FPSENCOS_first_mux_X[27]) );
OR2X2TS U2849 ( .A(FPSENCOS_d_ff_Xn[20]), .B(n3976), .Y(
FPSENCOS_first_mux_X[20]) );
OR2X2TS U2850 ( .A(FPSENCOS_d_ff_Xn[19]), .B(n3976), .Y(
FPSENCOS_first_mux_X[19]) );
OR2X2TS U2851 ( .A(FPSENCOS_d_ff_Xn[29]), .B(n4850), .Y(
FPSENCOS_first_mux_X[29]) );
OR2X2TS U2852 ( .A(FPSENCOS_d_ff_Xn[2]), .B(n3975), .Y(
FPSENCOS_first_mux_X[2]) );
AO22X1TS U2853 ( .A0(n4850), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n1691), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(FPSENCOS_first_mux_Z[2]) );
OR2X2TS U2854 ( .A(FPSENCOS_d_ff_Xn[5]), .B(n3975), .Y(
FPSENCOS_first_mux_X[5]) );
OAI21X2TS U2855 ( .A0(n4130), .A1(FPADDSUB_Data_array_SWR[48]), .B0(n4129),
.Y(n1044) );
OR2X2TS U2856 ( .A(FPSENCOS_d_ff_Xn[24]), .B(n3976), .Y(
FPSENCOS_first_mux_X[24]) );
INVX2TS U2857 ( .A(n4091), .Y(n3868) );
INVX12TS U2858 ( .A(n1595), .Y(n3200) );
AO22X1TS U2859 ( .A0(n4850), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n4851), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(FPSENCOS_first_mux_Z[4]) );
INVX2TS U2860 ( .A(n3239), .Y(n3243) );
ADDFHX2TS U2861 ( .A(n2956), .B(n2955), .CI(n1676), .CO(n3037), .S(n2945) );
OR2X2TS U2862 ( .A(FPSENCOS_d_ff_Xn[28]), .B(n4850), .Y(
FPSENCOS_first_mux_X[28]) );
OR2X2TS U2863 ( .A(FPSENCOS_d_ff_Xn[16]), .B(n3976), .Y(
FPSENCOS_first_mux_X[16]) );
OAI211X1TS U2864 ( .A0(operation[1]), .A1(n4006), .B0(n4005), .C0(n4056),
.Y(add_subt_data2[3]) );
NAND2X4TS U2865 ( .A(n2049), .B(n1609), .Y(n1295) );
OAI21X1TS U2866 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n5022), .B0(n3980),
.Y(n862) );
OAI21X1TS U2867 ( .A0(n5020), .A1(n5118), .B0(n5022), .Y(n859) );
INVX2TS U2868 ( .A(n5025), .Y(n5024) );
OAI21X1TS U2869 ( .A0(n4369), .A1(n4371), .B0(n4372), .Y(n3888) );
AND2X6TS U2870 ( .A(n1066), .B(n3199), .Y(n1595) );
XNOR2X2TS U2871 ( .A(n1963), .B(n1946), .Y(n1947) );
AND2X6TS U2872 ( .A(n1061), .B(n1121), .Y(n1538) );
OAI21X1TS U2873 ( .A0(n5118), .A1(n5022), .B0(n3925), .Y(n860) );
NAND2BX1TS U2874 ( .AN(FPMULT_exp_oper_result[1]), .B(n4845), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]) );
NAND2BX1TS U2875 ( .AN(FPMULT_exp_oper_result[0]), .B(n4845), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]) );
AOI31X1TS U2876 ( .A0(n4800), .A1(n4799), .A2(n4798), .B0(dataB[27]), .Y(
n4811) );
OR2X2TS U2877 ( .A(n3022), .B(n3021), .Y(n1660) );
NAND3X1TS U2878 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n3968), .C(n4719),
.Y(n3971) );
NOR2X1TS U2879 ( .A(n3979), .B(n857), .Y(FPSENCOS_ITER_CONT_N5) );
XNOR2X4TS U2880 ( .A(n1078), .B(n2518), .Y(n1547) );
XOR2X1TS U2881 ( .A(n959), .B(FPMULT_Sgf_normalized_result[5]), .Y(
FPMULT_Adder_M_result_A_adder[5]) );
NAND2BX1TS U2882 ( .AN(FPMULT_exp_oper_result[7]), .B(n4845), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]) );
NAND2BX1TS U2883 ( .AN(FPMULT_exp_oper_result[6]), .B(n4845), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]) );
NAND2BX1TS U2884 ( .AN(FPMULT_exp_oper_result[5]), .B(n4845), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]) );
NAND2BX1TS U2885 ( .AN(FPMULT_exp_oper_result[4]), .B(n4845), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]) );
NAND2BX1TS U2886 ( .AN(FPMULT_exp_oper_result[3]), .B(n4845), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]) );
NAND2BX1TS U2887 ( .AN(FPMULT_exp_oper_result[2]), .B(n4845), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]) );
INVX4TS U2888 ( .A(n1599), .Y(n1677) );
OAI21X1TS U2889 ( .A0(n4596), .A1(n4585), .B0(n4584), .Y(n4588) );
NAND3X1TS U2890 ( .A(n5107), .B(n4719), .C(n3968), .Y(n3935) );
XNOR2X2TS U2891 ( .A(n2246), .B(n2243), .Y(n2215) );
BUFX3TS U2892 ( .A(n4078), .Y(n4069) );
OAI21X1TS U2893 ( .A0(n4089), .A1(FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(n5151),
.Y(n4090) );
NAND3BX1TS U2894 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n3948), .Y(n3977) );
AND2X4TS U2895 ( .A(n2448), .B(n2447), .Y(n1078) );
XOR2X1TS U2896 ( .A(FPMULT_Op_MY[2]), .B(n1170), .Y(n1061) );
NOR2X4TS U2897 ( .A(n1218), .B(FPMULT_Op_MY[13]), .Y(n1946) );
OAI31XLTS U2898 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(
FPSENCOS_cont_iter_out[1]), .A2(n5096), .B0(n3920), .Y(n856) );
NAND3X1TS U2899 ( .A(n5281), .B(n5020), .C(n4976), .Y(n4875) );
INVX4TS U2900 ( .A(n4301), .Y(n3988) );
AND2X2TS U2901 ( .A(n3783), .B(n1027), .Y(n3784) );
XOR2X2TS U2902 ( .A(n1535), .B(n2257), .Y(n1534) );
OAI2BB2X1TS U2903 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n4667), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n4666), .Y(n4668) );
AO22XLTS U2904 ( .A0(operation[2]), .A1(n4892), .B0(n4893), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
OAI211X2TS U2905 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n4828), .B0(n4650),
.C0(n4635), .Y(n4652) );
OAI211X1TS U2906 ( .A0(n4628), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n4626), .C0(
n4625), .Y(n4630) );
OAI211X1TS U2907 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n5194), .B0(n4639), .C0(
n4642), .Y(n4654) );
OR2X2TS U2908 ( .A(n4298), .B(n4303), .Y(n4305) );
XOR2X1TS U2909 ( .A(FPMULT_Sgf_normalized_result[4]), .B(n1119), .Y(
FPMULT_Adder_M_result_A_adder[4]) );
AOI2BB1X1TS U2910 ( .A0N(n5200), .A1N(underflow_flag_mult), .B0(n4892), .Y(
FPMULT_final_result_ieee_Module_Sign_S_mux) );
AO22X1TS U2911 ( .A0(n1182), .A1(n4607), .B0(n4929), .B1(operation[0]), .Y(
n4611) );
CLKINVX2TS U2912 ( .A(n3964), .Y(n3972) );
AO22X1TS U2913 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n5071), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n816) );
NOR2X1TS U2914 ( .A(n4976), .B(n3967), .Y(FPSENCOS_ITER_CONT_N3) );
BUFX3TS U2915 ( .A(n3465), .Y(n5078) );
INVX2TS U2916 ( .A(n4501), .Y(n4503) );
OAI21X1TS U2917 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n4645), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n4646) );
OAI21X1TS U2918 ( .A0(n4332), .A1(n4355), .B0(n4333), .Y(n3882) );
INVX2TS U2919 ( .A(FPADDSUB_Raw_mant_SGF[25]), .Y(n5148) );
INVX2TS U2920 ( .A(n4518), .Y(n4520) );
OAI21X1TS U2921 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n4666), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n4667) );
OAI2BB2X1TS U2922 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n4658), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n5188), .Y(n4670) );
OAI21X1TS U2923 ( .A0(n4345), .A1(n4361), .B0(n4344), .Y(n4346) );
OR2X2TS U2924 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n3992), .Y(n1088)
);
OR2X2TS U2925 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n4132), .Y(n1087)
);
OAI21X1TS U2926 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n5143), .B0(
intadd_1033_CI), .Y(FPSENCOS_sh_exp_x[0]) );
OAI21X1TS U2927 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n5142), .B0(
intadd_1034_CI), .Y(FPSENCOS_sh_exp_y[0]) );
OAI21X1TS U2928 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .B0(n4814), .Y(n4812) );
XOR2X1TS U2929 ( .A(FPMULT_Sgf_normalized_result[3]), .B(n3862), .Y(
FPMULT_Adder_M_result_A_adder[3]) );
NAND3X1TS U2930 ( .A(n5197), .B(n4613), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n4615) );
NOR2X1TS U2931 ( .A(n4673), .B(FPADDSUB_intDY_EWSW[24]), .Y(n4612) );
NAND3X1TS U2932 ( .A(n5194), .B(n4639), .C(FPADDSUB_intDX_EWSW[8]), .Y(n4640) );
NOR2X1TS U2933 ( .A(n4637), .B(FPADDSUB_intDY_EWSW[10]), .Y(n4638) );
XNOR2X2TS U2934 ( .A(n2636), .B(n2517), .Y(n2520) );
BUFX8TS U2935 ( .A(n5047), .Y(n1218) );
OAI21X1TS U2936 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n4319), .B0(n4318), .Y(
n4320) );
OR2X2TS U2937 ( .A(FPMULT_Op_MX[12]), .B(n1277), .Y(n1657) );
INVX2TS U2938 ( .A(n2197), .Y(n2149) );
AND2X2TS U2939 ( .A(n5175), .B(FPADDSUB_DMP_SFG[20]), .Y(n4469) );
AOI2BB2X1TS U2940 ( .B0(FPMULT_Sgf_normalized_result[1]), .B1(n1690), .A0N(
n1690), .A1N(FPMULT_Sgf_normalized_result[1]), .Y(
FPMULT_Adder_M_result_A_adder[1]) );
OR2X2TS U2941 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(
FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n1525) );
NAND2BX1TS U2942 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n4639) );
CLKMX2X2TS U2943 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
NOR2X1TS U2944 ( .A(n5173), .B(FPADDSUB_DMP_SFG[21]), .Y(n4480) );
NOR2X1TS U2945 ( .A(n5163), .B(FPADDSUB_DMP_SFG[19]), .Y(n4458) );
CLKMX2X2TS U2946 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
OR2X2TS U2947 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n4477) );
MX2X4TS U2948 ( .A(n1001), .B(n1000), .S0(n999), .Y(
FPADDSUB_Raw_mant_SGF[25]) );
AO22XLTS U2949 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n4893),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
NAND2BX1TS U2950 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n4614) );
CLKMX2X2TS U2951 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
NOR2X1TS U2952 ( .A(n971), .B(n960), .Y(n3758) );
NOR2X2TS U2953 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n3871) );
NOR2X1TS U2954 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n4042) );
NAND2BX1TS U2955 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n4635) );
CLKMX2X2TS U2956 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
NAND2X6TS U2957 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[1]), .Y(n1935) );
AO22X1TS U2958 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n5208), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n819) );
NOR2X1TS U2959 ( .A(n971), .B(n962), .Y(n3767) );
NAND2BX1TS U2960 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n4661) );
NAND2BX1TS U2961 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n4655) );
OAI21X1TS U2962 ( .A0(n1016), .A1(n1015), .B0(n1014), .Y(n3820) );
OR2X2TS U2963 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]),
.Y(n4528) );
BUFX3TS U2964 ( .A(FPMULT_Op_MY[12]), .Y(n1226) );
NAND2BX1TS U2965 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n4625) );
OR2X2TS U2966 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n4401) );
OAI21X1TS U2967 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n5183), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n4636) );
NOR2X1TS U2968 ( .A(n5146), .B(FPADDSUB_DMP_SFG[15]), .Y(n4426) );
NOR2X2TS U2969 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n3910) );
NOR2X1TS U2970 ( .A(n971), .B(n969), .Y(n3773) );
OR2X2TS U2971 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]),
.Y(n4511) );
NOR2X1TS U2972 ( .A(n5101), .B(FPADDSUB_DMP_SFG[11]), .Y(n4417) );
CLKMX2X2TS U2973 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
NOR2X1TS U2974 ( .A(n5164), .B(FPADDSUB_DMP_SFG[17]), .Y(n4430) );
NAND2BX1TS U2975 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n4671) );
OR2X2TS U2976 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]),
.Y(n4438) );
NAND2BX1TS U2977 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n4641) );
NOR2X1TS U2978 ( .A(n971), .B(n968), .Y(n3755) );
NOR2X4TS U2979 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n3897) );
NOR2X1TS U2980 ( .A(n978), .B(n965), .Y(n3833) );
NOR2X1TS U2981 ( .A(n971), .B(n964), .Y(n3762) );
NOR2X1TS U2982 ( .A(n971), .B(n966), .Y(n3757) );
NOR2X1TS U2983 ( .A(n971), .B(n963), .Y(n3771) );
OR2X2TS U2984 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n1694) );
NAND3X1TS U2985 ( .A(n4795), .B(n4794), .C(n4793), .Y(n5210) );
NAND3X1TS U2986 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n4806) );
OR2X2TS U2987 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n3905) );
NOR2X1TS U2988 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n3927) );
INVX2TS U2989 ( .A(n1180), .Y(n1182) );
NAND3X1TS U2990 ( .A(n3866), .B(n3865), .C(n3864), .Y(n3867) );
BUFX20TS U2991 ( .A(n1447), .Y(n1395) );
XNOR2X2TS U2992 ( .A(n3172), .B(n950), .Y(n2392) );
BUFX6TS U2993 ( .A(n2349), .Y(n1351) );
INVX6TS U2994 ( .A(n1295), .Y(n1608) );
NOR2X6TS U2995 ( .A(n3679), .B(n3678), .Y(n3818) );
OAI2BB2X2TS U2996 ( .B0(n1854), .B1(n1784), .A0N(n1704), .A1N(n1171), .Y(
n1907) );
AOI21X2TS U2997 ( .A0(n3430), .A1(n1370), .B0(n3429), .Y(n3435) );
OAI21X2TS U2998 ( .A0(n3220), .A1(n3219), .B0(n3218), .Y(n3411) );
OAI21X4TS U2999 ( .A0(n2362), .A1(n2361), .B0(n2360), .Y(n2364) );
AOI21X2TS U3000 ( .A0(n1546), .A1(n3019), .B0(n2941), .Y(n1333) );
CMPR22X2TS U3001 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n2859), .CO(
n3863), .S(FPMULT_Adder_M_result_A_adder[18]) );
CMPR22X2TS U3002 ( .A(FPMULT_Sgf_normalized_result[16]), .B(n2864), .CO(
n3775), .S(FPMULT_Adder_M_result_A_adder[16]) );
CMPR22X2TS U3003 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n2863), .CO(
n3776), .S(FPMULT_Adder_M_result_A_adder[14]) );
CMPR22X2TS U3004 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n2860), .CO(
n3778), .S(FPMULT_Adder_M_result_A_adder[12]) );
CMPR22X2TS U3005 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n2861), .CO(
n3779), .S(FPMULT_Adder_M_result_A_adder[10]) );
ADDHX1TS U3006 ( .A(FPMULT_Sgf_normalized_result[7]), .B(n3781), .CO(n2862),
.S(FPMULT_Adder_M_result_A_adder[7]) );
ADDHX1TS U3007 ( .A(FPMULT_Sgf_normalized_result[20]), .B(n3777), .CO(n3782),
.S(FPMULT_Adder_M_result_A_adder[20]) );
NAND3X6TS U3008 ( .A(n1488), .B(n1489), .C(n1395), .Y(n1487) );
OAI2BB2X2TS U3009 ( .B0(n2122), .B1(n1699), .A0N(n1697), .A1N(n1698), .Y(
n1725) );
AOI21X2TS U3010 ( .A0(n4478), .A1(n4477), .B0(n3895), .Y(n4486) );
OAI21X4TS U3011 ( .A0(n4468), .A1(n4465), .B0(n4466), .Y(n4478) );
OAI21X2TS U3012 ( .A0(n4504), .A1(n4501), .B0(n4502), .Y(n4495) );
AO21X2TS U3013 ( .A0(n3626), .A1(n1684), .B0(n3625), .Y(n1648) );
OAI22X1TS U3014 ( .A0(n2122), .A1(n1778), .B0(n1149), .B1(n1786), .Y(n1782)
);
OAI22X1TS U3015 ( .A0(n2122), .A1(n1912), .B0(n1148), .B1(n2088), .Y(n2095)
);
XNOR2X1TS U3016 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[3]), .Y(n1786) );
CLKINVX6TS U3017 ( .A(FPMULT_Op_MY[11]), .Y(n1310) );
AOI21X2TS U3018 ( .A0(n4442), .A1(n4432), .B0(n4431), .Y(n4459) );
OAI21X2TS U3019 ( .A0(n4451), .A1(n4430), .B0(n4429), .Y(n4442) );
NAND3X6TS U3020 ( .A(n1487), .B(n1486), .C(n1485), .Y(n1484) );
NOR2X1TS U3021 ( .A(n2258), .B(n2257), .Y(n2259) );
XNOR2X4TS U3022 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[1]), .Y(n1067) );
OAI22X2TS U3023 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n4038), .B0(n4037),
.B1(n4036), .Y(n4039) );
AOI21X2TS U3024 ( .A0(n1334), .A1(n1687), .B0(n2469), .Y(n2525) );
AO21X1TS U3025 ( .A0(n974), .A1(n973), .B0(n972), .Y(n3684) );
XNOR2X1TS U3026 ( .A(n983), .B(n981), .Y(n4759) );
AOI22X1TS U3027 ( .A0(n3755), .A1(n3465), .B0(n955), .B1(n967), .Y(
add_x_69_n53) );
AOI22X1TS U3028 ( .A0(n3767), .A1(n3465), .B0(n955), .B1(n961), .Y(
add_x_69_n77) );
INVX2TS U3029 ( .A(n5078), .Y(n983) );
AOI22X1TS U3030 ( .A0(n1005), .A1(n3465), .B0(n955), .B1(n982), .Y(
add_x_69_n67) );
AOI2BB1X1TS U3031 ( .A0N(n983), .A1N(n952), .B0(n1021), .Y(add_x_69_n113) );
AOI2BB1X1TS U3032 ( .A0N(n983), .A1N(n948), .B0(n3684), .Y(add_x_69_n97) );
AOI22X1TS U3033 ( .A0(n1026), .A1(n5078), .B0(n955), .B1(n984), .Y(
add_x_69_n31) );
INVX2TS U3034 ( .A(n5339), .Y(n5139) );
XNOR2X1TS U3035 ( .A(n998), .B(n997), .Y(FPMULT_Sgf_operation_Result[28]) );
XNOR2X1TS U3036 ( .A(n970), .B(n1002), .Y(FPMULT_Sgf_operation_Result[30])
);
NOR2X1TS U3037 ( .A(n1004), .B(FPADDSUB_DMP_SFG[1]), .Y(n4585) );
NOR2X1TS U3038 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n4591) );
OAI21X1TS U3039 ( .A0(n4339), .A1(n4584), .B0(n4338), .Y(n4340) );
INVX2TS U3040 ( .A(FPADDSUB_sftr_odat_SHT2_SWR[3]), .Y(n5126) );
NAND2X1TS U3041 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n4355) );
NOR2X1TS U3042 ( .A(n4362), .B(n4345), .Y(n4347) );
INVX2TS U3043 ( .A(FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(n5120) );
NOR2X1TS U3044 ( .A(n1011), .B(FPADDSUB_DMP_SFG[3]), .Y(n4561) );
NOR2X2TS U3045 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n4570) );
OAI21X1TS U3046 ( .A0(n4343), .A1(n4562), .B0(n4342), .Y(n4359) );
INVX2TS U3047 ( .A(FPADDSUB_sftr_odat_SHT2_SWR[5]), .Y(n5125) );
NAND2X1TS U3048 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n4549) );
INVX2TS U3049 ( .A(FPADDSUB_sftr_odat_SHT2_SWR[7]), .Y(n5124) );
NOR2X1TS U3050 ( .A(n1018), .B(FPADDSUB_DMP_SFG[7]), .Y(n4539) );
NOR2X2TS U3051 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n4332) );
OAI21X1TS U3052 ( .A0(n4376), .A1(n4538), .B0(n4375), .Y(n4404) );
INVX2TS U3053 ( .A(FPADDSUB_sftr_odat_SHT2_SWR[9]), .Y(n5123) );
NAND2X1TS U3054 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n4558) );
NOR2X1TS U3055 ( .A(n4561), .B(n4343), .Y(n4360) );
INVX2TS U3056 ( .A(FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(n5121) );
NOR2X1TS U3057 ( .A(n4539), .B(n4376), .Y(n4403) );
INVX2TS U3058 ( .A(n5138), .Y(n5099) );
ADDHX1TS U3059 ( .A(n1032), .B(n3784), .CO(FPMULT_Adder_M_result_A_adder[24]), .S(FPMULT_Adder_M_result_A_adder[23]) );
INVX2TS U3060 ( .A(FPMULT_Adder_M_result_A_adder[24]), .Y(n5112) );
OAI21X1TS U3061 ( .A0(n3788), .A1(n3817), .B0(n3789), .Y(n3682) );
NOR2X8TS U3062 ( .A(n3818), .B(n3788), .Y(n3683) );
XNOR2X4TS U3063 ( .A(n1334), .B(n2564), .Y(n2586) );
XNOR2X2TS U3064 ( .A(n1469), .B(n950), .Y(n2418) );
XNOR2X2TS U3065 ( .A(n3071), .B(n950), .Y(n2196) );
XNOR2X4TS U3066 ( .A(n1546), .B(n3020), .Y(n3023) );
OAI21X4TS U3067 ( .A0(n3666), .A1(n3671), .B0(n3667), .Y(n3694) );
NAND2X1TS U3068 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n4599) );
NOR2X1TS U3069 ( .A(n5128), .B(FPADDSUB_DMP_SFG[0]), .Y(n4337) );
AOI21X2TS U3070 ( .A0(n4495), .A1(n4494), .B0(n3892), .Y(n4448) );
OAI21X2TS U3071 ( .A0(n4481), .A1(n4480), .B0(n4479), .Y(n4489) );
AOI21X4TS U3072 ( .A0(n4471), .A1(n4470), .B0(n4469), .Y(n4481) );
OAI21X2TS U3073 ( .A0(n4459), .A1(n4458), .B0(n4457), .Y(n4471) );
OAI21X2TS U3074 ( .A0(n4601), .A1(n4337), .B0(n4336), .Y(n4583) );
OAI21X2TS U3075 ( .A0(n4415), .A1(n4412), .B0(n4413), .Y(n4456) );
AOI21X4TS U3076 ( .A0(n4439), .A1(n4438), .B0(n3893), .Y(n4415) );
XNOR2X1TS U3077 ( .A(n2972), .B(n1174), .Y(n2642) );
INVX2TS U3078 ( .A(n1418), .Y(n1417) );
INVX2TS U3079 ( .A(n2508), .Y(n2456) );
NAND2X1TS U3080 ( .A(n2710), .B(n2708), .Y(n2509) );
XOR2X1TS U3081 ( .A(n1126), .B(FPMULT_Op_MY[9]), .Y(n2637) );
XNOR2X1TS U3082 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[9]), .Y(n1647) );
NAND2X4TS U3083 ( .A(n3428), .B(n3372), .Y(n1280) );
NOR2X1TS U3084 ( .A(n3476), .B(n3473), .Y(n3478) );
NAND2X2TS U3085 ( .A(n3467), .B(n2998), .Y(n3000) );
INVX2TS U3086 ( .A(n2968), .Y(n3398) );
NOR2X4TS U3087 ( .A(n1391), .B(n1390), .Y(n1554) );
NOR2X2TS U3088 ( .A(n2971), .B(n1143), .Y(n1391) );
NOR2X1TS U3089 ( .A(n1216), .B(n1644), .Y(n2531) );
NOR2X4TS U3090 ( .A(n1467), .B(n1466), .Y(n1465) );
OR2X4TS U3091 ( .A(n1174), .B(n1550), .Y(n1549) );
OAI22X2TS U3092 ( .A0(n1082), .A1(n2632), .B0(n3470), .B1(n3471), .Y(n2917)
);
OAI22X2TS U3093 ( .A0(n2733), .A1(n2732), .B0(n1685), .B1(n2731), .Y(n2919)
);
NOR2X2TS U3094 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[21]), .Y(n2517) );
INVX2TS U3095 ( .A(n3485), .Y(n3127) );
OAI21X1TS U3096 ( .A0(n3101), .A1(n3102), .B0(n3487), .Y(n3100) );
INVX4TS U3097 ( .A(n3486), .Y(n3075) );
NAND2X4TS U3098 ( .A(n1366), .B(n2491), .Y(n1365) );
NOR2X4TS U3099 ( .A(n1332), .B(n3858), .Y(n1345) );
INVX2TS U3100 ( .A(n3540), .Y(n3582) );
INVX2TS U3101 ( .A(n3242), .Y(n3238) );
NAND3X4TS U3102 ( .A(n1383), .B(n1388), .C(n1382), .Y(n1572) );
OR2X4TS U3103 ( .A(n1440), .B(n3092), .Y(n1383) );
CLKXOR2X2TS U3104 ( .A(n3155), .B(n3220), .Y(n3226) );
NAND2X1TS U3105 ( .A(n3151), .B(n3218), .Y(n3155) );
NAND2X1TS U3106 ( .A(n3647), .B(n3646), .Y(n3648) );
CLKXOR2X2TS U3107 ( .A(n3662), .B(n3661), .Y(n3680) );
NAND2X1TS U3108 ( .A(n3660), .B(n3659), .Y(n3661) );
AOI21X1TS U3109 ( .A0(n3657), .A1(n3656), .B0(n3655), .Y(n3662) );
INVX2TS U3110 ( .A(n3658), .Y(n3660) );
CLKXOR2X2TS U3111 ( .A(n3621), .B(n3620), .Y(n3678) );
NAND2X1TS U3112 ( .A(n3619), .B(n3652), .Y(n3620) );
AOI21X1TS U3113 ( .A0(n3656), .A1(n3649), .B0(n3651), .Y(n3621) );
INVX2TS U3114 ( .A(n3653), .Y(n3619) );
INVX2TS U3115 ( .A(n3730), .Y(n3706) );
NOR2X6TS U3116 ( .A(n3677), .B(n3676), .Y(n3793) );
OAI21X1TS U3117 ( .A0(n3658), .A1(n3652), .B0(n3659), .Y(n3481) );
NOR2X1TS U3118 ( .A(n3746), .B(n3745), .Y(n3805) );
NAND2X1TS U3119 ( .A(n3746), .B(n3745), .Y(n3804) );
CLKXOR2X2TS U3120 ( .A(n3457), .B(n3456), .Y(n3460) );
NAND2X1TS U3121 ( .A(n1633), .B(n3455), .Y(n3456) );
AOI21X1TS U3122 ( .A0(n3454), .A1(n1632), .B0(n3453), .Y(n3457) );
AOI21X2TS U3123 ( .A0(n4498), .A1(n4428), .B0(n4427), .Y(n4451) );
MX2X1TS U3124 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
NAND2X4TS U3125 ( .A(n5055), .B(FPMULT_Op_MX[3]), .Y(n2046) );
NAND2X4TS U3126 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .Y(n2047) );
INVX2TS U3127 ( .A(n3221), .Y(n2194) );
NAND2X4TS U3128 ( .A(n1563), .B(n1562), .Y(n2989) );
NAND2X2TS U3129 ( .A(n2927), .B(n1560), .Y(n1563) );
NAND3X4TS U3130 ( .A(n1566), .B(n1567), .C(n1564), .Y(n1560) );
INVX2TS U3131 ( .A(n1924), .Y(n1921) );
XOR2X1TS U3132 ( .A(n2445), .B(n2518), .Y(n2446) );
NOR2X2TS U3133 ( .A(n2444), .B(n2443), .Y(n2445) );
XOR2X1TS U3134 ( .A(n5048), .B(n5046), .Y(n2444) );
OAI21X2TS U3135 ( .A0(n3031), .A1(n1586), .B0(n3030), .Y(n1585) );
NAND2X2TS U3136 ( .A(n3002), .B(n3001), .Y(n3003) );
INVX2TS U3137 ( .A(n3467), .Y(n3002) );
INVX2TS U3138 ( .A(n3184), .Y(n3525) );
ACHCINX2TS U3139 ( .CIN(n3701), .A(n3387), .B(n3388), .CO(n3522) );
INVX12TS U3140 ( .A(n1532), .Y(n3339) );
INVX4TS U3141 ( .A(n2347), .Y(n1350) );
ADDFHX2TS U3142 ( .A(n2531), .B(n2530), .CI(n2529), .CO(n2540), .S(n2534) );
NOR2X1TS U3143 ( .A(n1216), .B(n1643), .Y(n2530) );
OAI2BB1X2TS U3144 ( .A0N(n1776), .A1N(n1775), .B0(n1774), .Y(n1802) );
OAI21X1TS U3145 ( .A0(n1569), .A1(n3069), .B0(n3485), .Y(n1568) );
INVX2TS U3146 ( .A(n3524), .Y(n3572) );
OAI21X2TS U3147 ( .A0(n1303), .A1(n2602), .B0(n2708), .Y(n2603) );
OAI2BB2X2TS U3148 ( .B0(n3306), .B1(n2430), .A0N(n1620), .A1N(n2429), .Y(
n2481) );
ADDFHX2TS U3149 ( .A(n1675), .B(n2959), .CI(n2958), .CO(n3033), .S(n2949) );
ADDFHX2TS U3150 ( .A(n2426), .B(n2425), .CI(n2424), .CO(n2515), .S(n2451) );
OAI22X2TS U3151 ( .A0(n3306), .A1(n2371), .B0(n1214), .B1(n2430), .Y(n2425)
);
INVX2TS U3152 ( .A(n2106), .Y(n2076) );
NAND2X1TS U3153 ( .A(n1718), .B(n1717), .Y(n1719) );
NAND2X2TS U3154 ( .A(n2546), .B(n1625), .Y(n2552) );
NAND2X4TS U3155 ( .A(n1395), .B(n3503), .Y(n1604) );
NOR2X4TS U3156 ( .A(n3542), .B(n3623), .Y(n3503) );
NOR2X2TS U3157 ( .A(n3049), .B(n3048), .Y(n3115) );
NOR2X1TS U3158 ( .A(n3558), .B(n5038), .Y(n3049) );
XOR2X1TS U3159 ( .A(n5049), .B(n1211), .Y(n3247) );
NAND2X4TS U3160 ( .A(n3365), .B(n3364), .Y(n3442) );
NAND2X1TS U3161 ( .A(n3396), .B(n3386), .Y(n2567) );
OR2X2TS U3162 ( .A(n3335), .B(n3360), .Y(n1626) );
NAND2X2TS U3163 ( .A(n2402), .B(n2290), .Y(n1531) );
NAND2X1TS U3164 ( .A(n2537), .B(n2576), .Y(n2323) );
NOR2X4TS U3165 ( .A(n1958), .B(n1957), .Y(n2004) );
NAND2X1TS U3166 ( .A(n3518), .B(n3517), .Y(n2666) );
INVX2TS U3167 ( .A(n2567), .Y(n2668) );
AOI2BB2XLTS U3168 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n4628), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n4627), .Y(n4629) );
NAND2X2TS U3169 ( .A(n1979), .B(n3087), .Y(n3152) );
CMPR22X2TS U3170 ( .A(n1838), .B(n1837), .CO(n2056), .S(n1959) );
NOR2X4TS U3171 ( .A(n2733), .B(n2632), .Y(n2016) );
NOR2X2TS U3172 ( .A(n2786), .B(n4009), .Y(n2033) );
OAI21X2TS U3173 ( .A0(n4358), .A1(n4349), .B0(n4348), .Y(n4394) );
OAI21X1TS U3174 ( .A0(n4329), .A1(n3885), .B0(n3884), .Y(n4368) );
CLKXOR2X2TS U3175 ( .A(n3587), .B(n3586), .Y(n3676) );
NAND2X1TS U3176 ( .A(n3585), .B(n3584), .Y(n3586) );
NOR2X2TS U3177 ( .A(n3238), .B(n3240), .Y(n3244) );
CLKXOR2X2TS U3178 ( .A(n3438), .B(n3437), .Y(n3461) );
NAND2X1TS U3179 ( .A(n3436), .B(n3475), .Y(n3437) );
INVX2TS U3180 ( .A(n3473), .Y(n3436) );
AOI21X1TS U3181 ( .A0(n4404), .A1(n4378), .B0(n4377), .Y(n4391) );
CLKAND2X2TS U3182 ( .A(n5102), .B(FPADDSUB_DMP_SFG[9]), .Y(n4377) );
NAND2X1TS U3183 ( .A(n4403), .B(n4378), .Y(n4388) );
NOR2X2TS U3184 ( .A(n2056), .B(n2062), .Y(n2845) );
NAND2X1TS U3185 ( .A(n1688), .B(n2800), .Y(n2801) );
NAND2X1TS U3186 ( .A(n1931), .B(n1941), .Y(n4027) );
NAND2X1TS U3187 ( .A(n2662), .B(n2872), .Y(n2663) );
INVX2TS U3188 ( .A(n3226), .Y(n3156) );
INVX2TS U3189 ( .A(n4561), .Y(n4563) );
AOI21X1TS U3190 ( .A0(n4368), .A1(n3889), .B0(n3888), .Y(n4387) );
INVX2TS U3191 ( .A(n4384), .Y(n4386) );
INVX2TS U3192 ( .A(n4403), .Y(n4406) );
INVX2TS U3193 ( .A(n4404), .Y(n4405) );
INVX2TS U3194 ( .A(n4591), .Y(n4593) );
NAND2X1TS U3195 ( .A(n5223), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n4204) );
NAND2X1TS U3196 ( .A(n3668), .B(n3667), .Y(n3669) );
INVX2TS U3197 ( .A(n3666), .Y(n3668) );
INVX2TS U3198 ( .A(n3686), .Y(n3491) );
NOR2X2TS U3199 ( .A(n3712), .B(n3711), .Y(n3734) );
AOI21X1TS U3200 ( .A0(n3738), .A1(n3706), .B0(n3705), .Y(n3707) );
NAND2X1TS U3201 ( .A(n3712), .B(n3711), .Y(n3733) );
NAND2X1TS U3202 ( .A(n3672), .B(n3671), .Y(n3673) );
OR2X2TS U3203 ( .A(n4015), .B(n4014), .Y(n4017) );
NAND2X1TS U3204 ( .A(n4023), .B(n4022), .Y(n4024) );
OAI221XLTS U3205 ( .A0(n5155), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n1695),
.B1(FPADDSUB_intDY_EWSW[22]), .C0(n4689), .Y(n4694) );
OAI221X1TS U3206 ( .A0(n4838), .A1(FPADDSUB_intDX_EWSW[30]), .B0(n1112),
.B1(FPADDSUB_intDY_EWSW[20]), .C0(n4696), .Y(n4711) );
INVX2TS U3207 ( .A(n2869), .Y(n3838) );
NAND2X4TS U3208 ( .A(n4086), .B(n5115), .Y(n4048) );
OAI21X1TS U3209 ( .A0(n4507), .A1(n4426), .B0(n4425), .Y(n4498) );
AOI21X1TS U3210 ( .A0(n4532), .A1(n4420), .B0(n4419), .Y(n4524) );
CLKAND2X2TS U3211 ( .A(n5106), .B(FPADDSUB_DMP_SFG[12]), .Y(n4419) );
NAND2X1TS U3212 ( .A(n3747), .B(n3804), .Y(n3748) );
NAND3BX1TS U3213 ( .AN(FPADDSUB_Raw_mant_NRM_SWR[17]), .B(n4091), .C(
FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n4092) );
NAND2X6TS U3214 ( .A(n1062), .B(n1608), .Y(n1412) );
INVX2TS U3215 ( .A(n2928), .Y(n1564) );
INVX2TS U3216 ( .A(n1039), .Y(n1561) );
NOR2X6TS U3217 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[6]), .Y(n2374) );
NOR2X1TS U3218 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[19]), .Y(n1529) );
XNOR2X2TS U3219 ( .A(n3071), .B(n2972), .Y(n2974) );
INVX2TS U3220 ( .A(n2507), .Y(n2454) );
NOR2BX1TS U3221 ( .AN(n1685), .B(n2730), .Y(n2732) );
INVX2TS U3222 ( .A(n3387), .Y(n1491) );
NOR2X4TS U3223 ( .A(n2048), .B(n2047), .Y(n1307) );
NOR2X6TS U3224 ( .A(n2374), .B(n2379), .Y(n2381) );
NAND2X1TS U3225 ( .A(n1469), .B(n1144), .Y(n1293) );
NAND2X1TS U3226 ( .A(n2455), .B(n2507), .Y(n2383) );
XNOR2X1TS U3227 ( .A(n3524), .B(n3526), .Y(n3389) );
XNOR2X2TS U3228 ( .A(n3184), .B(n1276), .Y(n3130) );
INVX2TS U3229 ( .A(n3071), .Y(n3132) );
OAI22X2TS U3230 ( .A0(n1064), .A1(n2140), .B0(n3268), .B1(n2226), .Y(n2208)
);
INVX2TS U3231 ( .A(n1465), .Y(n1463) );
NOR2X1TS U3232 ( .A(n2090), .B(n2089), .Y(n2092) );
NAND2X1TS U3233 ( .A(n2090), .B(n2089), .Y(n2091) );
ADDFHX2TS U3234 ( .A(n2096), .B(n2095), .CI(n2094), .CO(n2115), .S(n2085) );
XNOR2X1TS U3235 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MX[8]), .Y(n2121) );
XNOR2X2TS U3236 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[6]), .Y(n2123) );
XNOR2X2TS U3237 ( .A(n1124), .B(FPMULT_Op_MX[7]), .Y(n2294) );
ADDFHX2TS U3238 ( .A(n2297), .B(n2296), .CI(n2295), .CO(n2316), .S(n2302) );
NOR2X1TS U3239 ( .A(n1216), .B(n1649), .Y(n2296) );
XNOR2X1TS U3240 ( .A(n2090), .B(n2089), .Y(n1919) );
XNOR2X1TS U3241 ( .A(n1514), .B(n1174), .Y(n2280) );
CMPR22X2TS U3242 ( .A(n2355), .B(n2354), .CO(n2441), .S(n2359) );
OAI21X1TS U3243 ( .A0(n2406), .A1(n2405), .B0(n1583), .Y(n1582) );
NAND2BX1TS U3244 ( .AN(n2992), .B(n2991), .Y(n2993) );
INVX2TS U3245 ( .A(n2988), .Y(n2992) );
ADDFHX2TS U3246 ( .A(n3395), .B(n3394), .CI(n3393), .CO(n3509), .S(n3390) );
INVX2TS U3247 ( .A(n3360), .Y(n3393) );
INVX2TS U3248 ( .A(n3702), .Y(n3395) );
INVX2TS U3249 ( .A(n3359), .Y(n3394) );
NAND2X4TS U3250 ( .A(n2640), .B(n2639), .Y(n2718) );
XNOR2X2TS U3251 ( .A(n1159), .B(n5046), .Y(n2488) );
NAND2X1TS U3252 ( .A(n2626), .B(n3379), .Y(n2428) );
INVX2TS U3253 ( .A(n3490), .Y(n3162) );
NOR2X4TS U3254 ( .A(n1398), .B(n1397), .Y(n3263) );
NOR2X1TS U3255 ( .A(n3183), .B(n3340), .Y(n1397) );
INVX2TS U3256 ( .A(n2398), .Y(n1615) );
INVX2TS U3257 ( .A(n2397), .Y(n1614) );
OAI22X1TS U3258 ( .A0(n2679), .A1(n2318), .B0(n1149), .B1(n2533), .Y(n2536)
);
INVX2TS U3259 ( .A(n2531), .Y(n2314) );
OAI21X2TS U3260 ( .A0(n2191), .A1(n2192), .B0(n2189), .Y(n2190) );
XNOR2X2TS U3261 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[1]), .Y(n1727) );
OAI21X2TS U3262 ( .A0(n2037), .A1(n2036), .B0(n2034), .Y(n2035) );
INVX2TS U3263 ( .A(n1716), .Y(n1718) );
NAND2X2TS U3264 ( .A(n1715), .B(n1714), .Y(n1720) );
INVX2TS U3265 ( .A(n1717), .Y(n1713) );
XNOR2X2TS U3266 ( .A(n1218), .B(FPMULT_Op_MX[9]), .Y(n1733) );
ADDFHX2TS U3267 ( .A(n1915), .B(n1791), .CI(n1790), .CO(n1902), .S(n1796) );
OAI2BB2X1TS U3268 ( .B0(n1854), .B1(n1768), .A0N(n1704), .A1N(n1767), .Y(
n1790) );
INVX2TS U3269 ( .A(n3422), .Y(n1326) );
INVX2TS U3270 ( .A(n2658), .Y(n1519) );
INVX2TS U3271 ( .A(n2561), .Y(n2545) );
OAI22X1TS U3272 ( .A0(n2541), .A1(n2532), .B0(n1150), .B1(n1641), .Y(n2544)
);
INVX2TS U3273 ( .A(n3488), .Y(n3093) );
ADDFHX2TS U3274 ( .A(n3566), .B(n3565), .CI(n3564), .CO(n3613), .S(n3575) );
OAI22X1TS U3275 ( .A0(n3528), .A1(n3601), .B0(n3567), .B1(n1219), .Y(n3554)
);
INVX2TS U3276 ( .A(n1322), .Y(n1320) );
INVX2TS U3277 ( .A(n2480), .Y(n1319) );
XNOR2X2TS U3278 ( .A(n1159), .B(n1126), .Y(n2897) );
NAND2X2TS U3279 ( .A(n2702), .B(n1501), .Y(n1500) );
INVX2TS U3280 ( .A(n2701), .Y(n1501) );
XNOR2X2TS U3281 ( .A(n1159), .B(n5049), .Y(n2693) );
INVX8TS U3282 ( .A(n1296), .Y(n3216) );
CLKINVX6TS U3283 ( .A(n1348), .Y(n2289) );
INVX2TS U3284 ( .A(n2577), .Y(n2537) );
INVX2TS U3285 ( .A(n2074), .Y(n1540) );
XNOR2X2TS U3286 ( .A(n1218), .B(FPMULT_Op_MX[8]), .Y(n1754) );
XNOR2X1TS U3287 ( .A(n1981), .B(n1980), .Y(n1970) );
OAI21X2TS U3288 ( .A0(n2672), .A1(n2552), .B0(n2551), .Y(n2553) );
AOI21X1TS U3289 ( .A0(n2550), .A1(n1625), .B0(n2668), .Y(n2551) );
NAND2X2TS U3290 ( .A(n3292), .B(n3291), .Y(n2576) );
XNOR2X1TS U3291 ( .A(n5055), .B(n1227), .Y(n1978) );
ADDFHX2TS U3292 ( .A(n2134), .B(n2133), .CI(n2132), .CO(n3221), .S(n3150) );
NOR2X4TS U3293 ( .A(n3431), .B(n3450), .Y(n1301) );
ADDFX2TS U3294 ( .A(n3598), .B(n3597), .CI(n3596), .CO(n3631), .S(n3612) );
ADDFX2TS U3295 ( .A(n3614), .B(n3613), .CI(n3612), .CO(n3629), .S(n3594) );
INVX2TS U3296 ( .A(n3807), .Y(n3634) );
INVX2TS U3297 ( .A(n3606), .Y(n3633) );
AND2X2TS U3298 ( .A(n3622), .B(n1646), .Y(n1489) );
OAI22X1TS U3299 ( .A0(n3045), .A1(n1159), .B0(n1125), .B1(n1664), .Y(n3035)
);
ADDFHX2TS U3300 ( .A(n3041), .B(n3040), .CI(n3039), .CO(n3118), .S(n3038) );
OAI22X1TS U3301 ( .A0(n3306), .A1(n2954), .B0(n3305), .B1(n3044), .Y(n3039)
);
ADDFHX2TS U3302 ( .A(n3192), .B(n3191), .CI(n3190), .CO(n3253), .S(n3202) );
OAI22X2TS U3303 ( .A0(n3306), .A1(n3111), .B0(n3305), .B1(n3195), .Y(n3191)
);
XNOR2X2TS U3304 ( .A(n1160), .B(n1126), .Y(n3195) );
XOR2X1TS U3305 ( .A(n1126), .B(n1211), .Y(n3304) );
NAND2X2TS U3306 ( .A(n2944), .B(n2945), .Y(n2946) );
OAI22X1TS U3307 ( .A0(n1060), .A1(n2242), .B0(n1214), .B1(n2371), .Y(n2372)
);
ADDFHX2TS U3308 ( .A(n2369), .B(n2368), .CI(n2367), .CO(n2452), .S(n2351) );
NAND2X1TS U3309 ( .A(n3335), .B(n3360), .Y(n2580) );
NOR2X2TS U3310 ( .A(n3256), .B(n3257), .Y(n2336) );
NAND2X1TS U3311 ( .A(n3257), .B(n3256), .Y(n2337) );
XNOR2X2TS U3312 ( .A(n5047), .B(FPMULT_Op_MX[3]), .Y(n1830) );
AND2X2TS U3313 ( .A(n2077), .B(n2106), .Y(n1653) );
NAND2X1TS U3314 ( .A(n2125), .B(n2331), .Y(n2126) );
NAND2X1TS U3315 ( .A(n2099), .B(n2105), .Y(n2100) );
INVX2TS U3316 ( .A(n2107), .Y(n2099) );
INVX2TS U3317 ( .A(n2009), .Y(n2010) );
XNOR2X1TS U3318 ( .A(n2015), .B(n2014), .Y(n2026) );
NAND2X1TS U3319 ( .A(n2013), .B(n1674), .Y(n2015) );
CMPR22X2TS U3320 ( .A(n1821), .B(n1820), .CO(n1872), .S(n1822) );
OAI22X1TS U3321 ( .A0(n1135), .A1(n1825), .B0(n1815), .B1(n1038), .Y(n1821)
);
ADDFHX2TS U3322 ( .A(n1864), .B(n1863), .CI(n1862), .CO(n1869), .S(n1871) );
ADDFHX2TS U3323 ( .A(n1884), .B(n1883), .CI(n1882), .CO(n1892), .S(n1894) );
XNOR2X2TS U3324 ( .A(n1218), .B(FPMULT_Op_MX[2]), .Y(n1831) );
INVX2TS U3325 ( .A(n1994), .Y(n1996) );
NOR2X2TS U3326 ( .A(n1993), .B(n2009), .Y(n1998) );
INVX2TS U3327 ( .A(n1992), .Y(n1993) );
NOR2X1TS U3328 ( .A(n1310), .B(n1659), .Y(n2560) );
NAND3X4TS U3329 ( .A(n1573), .B(n3158), .C(n1546), .Y(n1382) );
AOI21X1TS U3330 ( .A0(n3154), .A1(n1627), .B0(n3153), .Y(n3220) );
INVX2TS U3331 ( .A(n3152), .Y(n3153) );
NAND2X1TS U3332 ( .A(n3150), .B(n3149), .Y(n3218) );
NOR2X1TS U3333 ( .A(n3150), .B(n3149), .Y(n3219) );
INVX6TS U3334 ( .A(n1286), .Y(n1440) );
INVX2TS U3335 ( .A(n3580), .Y(n3581) );
ADDFX2TS U3336 ( .A(n3631), .B(n3630), .CI(n3629), .CO(n3647), .S(n3615) );
XNOR2X1TS U3337 ( .A(n3636), .B(n3635), .Y(n3645) );
NAND2X4TS U3338 ( .A(n1489), .B(n1300), .Y(n1485) );
INVX2TS U3339 ( .A(n3624), .Y(n3625) );
NOR2X1TS U3340 ( .A(n3650), .B(n3653), .Y(n3657) );
INVX2TS U3341 ( .A(n3544), .Y(n3537) );
XNOR2X2TS U3342 ( .A(n3656), .B(n3541), .Y(n3675) );
NAND2X4TS U3343 ( .A(n3622), .B(n1686), .Y(n3590) );
ADDFHX2TS U3344 ( .A(n3106), .B(n3105), .CI(n3104), .CO(n3207), .S(n3116) );
OAI22X1TS U3345 ( .A0(n3246), .A1(FPMULT_Op_MY[19]), .B0(n3557), .B1(n5048),
.Y(n3302) );
OAI22X1TS U3346 ( .A0(n1209), .A1(n3247), .B0(n3380), .B1(n3304), .Y(n3301)
);
ADDFHX2TS U3347 ( .A(n3309), .B(n3308), .CI(n3307), .CO(n3356), .S(n3289) );
OAI22X1TS U3348 ( .A0(n1160), .A1(n3306), .B0(n1214), .B1(n1662), .Y(n3309)
);
NOR2X2TS U3349 ( .A(n3422), .B(n3421), .Y(n3476) );
AOI21X1TS U3350 ( .A0(n1633), .A1(n3453), .B0(n3416), .Y(n3417) );
NAND2X1TS U3351 ( .A(n1633), .B(n1632), .Y(n3418) );
INVX2TS U3352 ( .A(n3455), .Y(n3416) );
OAI2BB1X1TS U3353 ( .A0N(n2614), .A1N(n2613), .B0(n2612), .Y(n2737) );
NOR2X2TS U3354 ( .A(n3472), .B(n3480), .Y(n3540) );
NOR2X4TS U3355 ( .A(n3468), .B(n3469), .Y(n3653) );
NOR2X2TS U3356 ( .A(n3470), .B(n3471), .Y(n3583) );
OAI22X1TS U3357 ( .A0(n3558), .A1(FPMULT_Op_MY[21]), .B0(n3557), .B1(n1126),
.Y(n3382) );
NOR2X2TS U3358 ( .A(n3485), .B(n3486), .Y(n3664) );
INVX2TS U3359 ( .A(n3479), .Y(n3438) );
OAI22X1TS U3360 ( .A0(n1206), .A1(n2210), .B0(n3199), .B1(n2250), .Y(n2284)
);
NAND2X1TS U3361 ( .A(n3413), .B(n3412), .Y(n3446) );
AOI21X2TS U3362 ( .A0(n3411), .A1(n1656), .B0(n3410), .Y(n3445) );
INVX2TS U3363 ( .A(n3409), .Y(n3410) );
INVX2TS U3364 ( .A(n2758), .Y(n2017) );
XNOR2X2TS U3365 ( .A(n1218), .B(FPMULT_Op_MX[1]), .Y(n1829) );
INVX6TS U3366 ( .A(n1069), .Y(n1135) );
CLKXOR2X2TS U3367 ( .A(n2008), .B(n2007), .Y(n2028) );
NAND2X1TS U3368 ( .A(n2006), .B(n2005), .Y(n2008) );
NOR2X4TS U3369 ( .A(n2808), .B(n2840), .Y(n2346) );
NOR2X1TS U3370 ( .A(n1310), .B(n1635), .Y(n3604) );
AO21XLTS U3371 ( .A0(n2679), .A1(n1149), .B0(n1310), .Y(n3603) );
ADDFX2TS U3372 ( .A(n2678), .B(n2677), .CI(n2676), .CO(n3556), .S(n3517) );
INVX2TS U3373 ( .A(n3605), .Y(n2678) );
OAI22X1TS U3374 ( .A0(n2679), .A1(n2558), .B0(n1149), .B1(n1310), .Y(n2677)
);
OAI21X1TS U3375 ( .A0(n2672), .A1(n1043), .B0(n1085), .Y(n2673) );
AOI21X1TS U3376 ( .A0(n2668), .A1(n1624), .B0(n2667), .Y(n2669) );
INVX2TS U3377 ( .A(n2666), .Y(n2667) );
AOI32X1TS U3378 ( .A0(n5195), .A1(n4661), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n5113), .Y(n4662) );
INVX2TS U3379 ( .A(n3029), .Y(n3013) );
CLKXOR2X2TS U3380 ( .A(n3018), .B(n3089), .Y(n3024) );
NAND2X1TS U3381 ( .A(n3017), .B(n3088), .Y(n3018) );
XNOR2X2TS U3382 ( .A(n3091), .B(n3154), .Y(n3224) );
XNOR2X2TS U3383 ( .A(n3411), .B(n3223), .Y(n3230) );
NAND2X1TS U3384 ( .A(n1656), .B(n3409), .Y(n3223) );
XNOR2X2TS U3385 ( .A(n3425), .B(n3424), .Y(n3463) );
NAND2X1TS U3386 ( .A(n3423), .B(n3474), .Y(n3424) );
INVX2TS U3387 ( .A(n3476), .Y(n3423) );
INVX2TS U3388 ( .A(n3671), .Y(n3665) );
NOR2X2TS U3389 ( .A(n3466), .B(n3467), .Y(n3658) );
NAND2X2TS U3390 ( .A(n3468), .B(n3469), .Y(n3652) );
NOR2X2TS U3391 ( .A(n3583), .B(n3540), .Y(n3649) );
NOR2X2TS U3392 ( .A(n3658), .B(n3653), .Y(n3482) );
OAI21X2TS U3393 ( .A0(n3583), .A1(n3580), .B0(n3584), .Y(n3651) );
OAI21X2TS U3394 ( .A0(n3726), .A1(n3718), .B0(n3719), .Y(n3738) );
AOI21X1TS U3395 ( .A0(n3738), .A1(n3737), .B0(n3736), .Y(n3739) );
NAND2X2TS U3396 ( .A(n3485), .B(n3486), .Y(n3671) );
INVX2TS U3397 ( .A(n3664), .Y(n3672) );
INVX2TS U3398 ( .A(n3460), .Y(n1423) );
XNOR2X2TS U3399 ( .A(n3454), .B(n3447), .Y(n3458) );
NAND2X1TS U3400 ( .A(n1632), .B(n3446), .Y(n3447) );
OR2X2TS U3401 ( .A(n3412), .B(n3413), .Y(n1632) );
OR2X2TS U3402 ( .A(n3414), .B(n3415), .Y(n1633) );
INVX2TS U3403 ( .A(n3446), .Y(n3453) );
INVX2TS U3404 ( .A(n3445), .Y(n3454) );
NOR2X4TS U3405 ( .A(n1537), .B(n2584), .Y(n2835) );
NAND2X4TS U3406 ( .A(n2733), .B(n2632), .Y(n2758) );
AOI221X1TS U3407 ( .A0(n1100), .A1(FPADDSUB_intDY_EWSW[15]), .B0(
FPADDSUB_intDY_EWSW[13]), .B1(n1049), .C0(n4703), .Y(n4704) );
BUFX4TS U3408 ( .A(FPMULT_Op_MY[14]), .Y(n5037) );
INVX2TS U3409 ( .A(n4354), .Y(n4356) );
INVX2TS U3410 ( .A(n4332), .Y(n4334) );
INVX2TS U3411 ( .A(n4579), .Y(n4581) );
INVX2TS U3412 ( .A(n4558), .Y(n4547) );
INVX2TS U3413 ( .A(n4570), .Y(n4572) );
CLKBUFX2TS U3414 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n4604) );
XOR2X1TS U3415 ( .A(n3729), .B(n3728), .Y(n3768) );
NAND2X1TS U3416 ( .A(n3727), .B(n3726), .Y(n3728) );
INVX2TS U3417 ( .A(n3725), .Y(n3727) );
NAND2X1TS U3418 ( .A(n3706), .B(n3735), .Y(n3703) );
INVX2TS U3419 ( .A(n4371), .Y(n4373) );
XOR2X1TS U3420 ( .A(n2827), .B(n2826), .Y(n2833) );
NAND2X1TS U3421 ( .A(n2773), .B(n2825), .Y(n2826) );
NAND2X1TS U3422 ( .A(n1629), .B(n2828), .Y(n2830) );
XOR2X1TS U3423 ( .A(n2849), .B(n2848), .Y(n2852) );
NAND2X1TS U3424 ( .A(n2847), .B(n2846), .Y(n2849) );
XOR2X1TS U3425 ( .A(n4020), .B(n2764), .Y(n2776) );
NAND2X1TS U3426 ( .A(n2763), .B(n4018), .Y(n2764) );
XNOR2X1TS U3427 ( .A(n2761), .B(n2760), .Y(n2777) );
NAND2X1TS U3428 ( .A(n2759), .B(n2758), .Y(n2760) );
NAND2X1TS U3429 ( .A(n2799), .B(n2766), .Y(n2767) );
INVX2TS U3430 ( .A(n2769), .Y(n2771) );
XOR2X1TS U3431 ( .A(n1874), .B(n2801), .Y(n2815) );
CLKAND2X2TS U3432 ( .A(n3922), .B(n3964), .Y(n4326) );
AOI211X1TS U3433 ( .A0(n1153), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n4303),
.C0(n3902), .Y(n3904) );
CLKAND2X2TS U3434 ( .A(n5174), .B(FPADDSUB_DMP_SFG[22]), .Y(n4487) );
BUFX3TS U3435 ( .A(n3981), .Y(n4971) );
OAI211XLTS U3436 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n1106), .B0(n5032), .C0(n4786), .Y(n875) );
MX2X1TS U3437 ( .A(FPADDSUB_N60), .B(n4605), .S0(n4604), .Y(
FPADDSUB_Raw_mant_SGF[1]) );
INVX2TS U3438 ( .A(n3851), .Y(n3845) );
XOR2X1TS U3439 ( .A(FPMULT_Sgf_normalized_result[2]), .B(n3861), .Y(
FPMULT_Adder_M_result_A_adder[2]) );
NOR2X1TS U3440 ( .A(FPMULT_Sgf_normalized_result[1]), .B(
FPMULT_Sgf_normalized_result[0]), .Y(n3861) );
OAI21X1TS U3441 ( .A0(n4242), .A1(n1176), .B0(n4237), .Y(
FPADDSUB_Data_array_SWR[6]) );
MXI2X1TS U3442 ( .A(n3904), .B(n3903), .S0(n1163), .Y(n5136) );
OAI211XLTS U3443 ( .A0(n1182), .A1(n4050), .B0(n4049), .C0(n4051), .Y(
add_subt_data2[19]) );
OAI21X1TS U3444 ( .A0(n4268), .A1(n1176), .B0(n4239), .Y(
FPADDSUB_Data_array_SWR[14]) );
MX2X1TS U3445 ( .A(n4598), .B(n4597), .S0(n4604), .Y(
FPADDSUB_Raw_mant_SGF[3]) );
OAI211XLTS U3446 ( .A0(n1182), .A1(n4066), .B0(n4065), .C0(n4073), .Y(
add_subt_data2[28]) );
OAI211XLTS U3447 ( .A0(n1182), .A1(n4077), .B0(n4076), .C0(n4079), .Y(
add_subt_data2[15]) );
OAI211XLTS U3448 ( .A0(n1182), .A1(n4058), .B0(n4057), .C0(n4056), .Y(
add_subt_data2[16]) );
MX2X1TS U3449 ( .A(n4603), .B(n4602), .S0(n4604), .Y(
FPADDSUB_Raw_mant_SGF[2]) );
CLKAND2X2TS U3450 ( .A(n4600), .B(n4599), .Y(n4603) );
OAI31X1TS U3451 ( .A0(n5035), .A1(FPSENCOS_cont_var_out[1]), .A2(n5117),
.B0(n4295), .Y(n842) );
NOR2X4TS U3452 ( .A(n5281), .B(rst), .Y(n5280) );
AOI21X1TS U3453 ( .A0(n5078), .A1(n1020), .B0(n1019), .Y(add_x_69_n122) );
NAND2X1TS U3454 ( .A(n3795), .B(n3794), .Y(add_x_69_n6) );
AOI21X1TS U3455 ( .A0(n5078), .A1(n1030), .B0(n3820), .Y(add_x_69_n106) );
AOI2BB2X1TS U3456 ( .B0(n3758), .B1(n5078), .A0N(n3824), .A1N(n960), .Y(
add_x_69_n83) );
INVX2TS U3457 ( .A(n3764), .Y(add_x_69_n82) );
AOI2BB2X1TS U3458 ( .B0(n3773), .B1(n5078), .A0N(n3824), .A1N(n969), .Y(
add_x_69_n91) );
NAND2X1TS U3459 ( .A(n3765), .B(n3764), .Y(n3766) );
NAND2X1TS U3460 ( .A(n3500), .B(n3689), .Y(n3501) );
INVX2TS U3461 ( .A(n3691), .Y(n3500) );
INVX2TS U3462 ( .A(n3768), .Y(add_x_69_n66) );
AOI2BB2X1TS U3463 ( .B0(n3771), .B1(n5078), .A0N(n3824), .A1N(n963), .Y(
add_x_69_n61) );
NAND2X1TS U3464 ( .A(n3769), .B(n3768), .Y(n3770) );
XNOR2X2TS U3465 ( .A(n3722), .B(n3721), .Y(n1680) );
NAND2X1TS U3466 ( .A(n3720), .B(n3719), .Y(n3721) );
AOI2BB2X1TS U3467 ( .B0(n3762), .B1(n5078), .A0N(n3824), .A1N(n964), .Y(
add_x_69_n47) );
NAND2X1TS U3468 ( .A(n3760), .B(n3759), .Y(n3761) );
XNOR2X1TS U3469 ( .A(n3715), .B(n3714), .Y(n1681) );
NAND2X1TS U3470 ( .A(n3713), .B(n3733), .Y(n3714) );
AOI2BB2X1TS U3471 ( .B0(n3757), .B1(n5078), .A0N(n3824), .A1N(n966), .Y(
add_x_69_n37) );
INVX2TS U3472 ( .A(n3772), .Y(add_x_69_n96) );
AOI21X1TS U3473 ( .A0(n970), .A1(n992), .B0(n991), .Y(add_x_69_n141) );
AOI21X1TS U3474 ( .A0(n970), .A1(n990), .B0(n989), .Y(add_x_69_n150) );
INVX2TS U3475 ( .A(n3841), .Y(n3840) );
NAND2X1TS U3476 ( .A(n3800), .B(n3799), .Y(add_x_69_n10) );
NAND2X1TS U3477 ( .A(n1419), .B(n3460), .Y(n3799) );
NAND3X1TS U3478 ( .A(n1431), .B(n1429), .C(n1426), .Y(n1419) );
XNOR2X1TS U3479 ( .A(n4025), .B(n4024), .Y(n4032) );
AOI2BB2X1TS U3480 ( .B0(n4831), .B1(n5335), .A0N(FPADDSUB_intDX_EWSW[31]),
.A1N(n4715), .Y(n5336) );
AOI31X1TS U3481 ( .A0(n4714), .A1(n4713), .A2(n4712), .B0(n4837), .Y(n4715)
);
CLKAND2X2TS U3482 ( .A(FPMULT_FSM_selector_A), .B(FPMULT_exp_oper_result[8]),
.Y(FPMULT_S_Oper_A_exp[8]) );
XOR2X1TS U3483 ( .A(n3838), .B(n3837), .Y(FPMULT_Sgf_operation_Result[23])
);
CLKAND2X2TS U3484 ( .A(n1131), .B(FPADDSUB_sftr_odat_SHT2_SWR[9]), .Y(
FPADDSUB_formatted_number_W[7]) );
CLKAND2X2TS U3485 ( .A(n1036), .B(FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(
FPADDSUB_formatted_number_W[6]) );
CLKAND2X2TS U3486 ( .A(n1130), .B(FPADDSUB_sftr_odat_SHT2_SWR[5]), .Y(
FPADDSUB_formatted_number_W[3]) );
CLKAND2X2TS U3487 ( .A(n1131), .B(FPADDSUB_sftr_odat_SHT2_SWR[3]), .Y(
FPADDSUB_formatted_number_W[1]) );
NAND3BX1TS U3488 ( .AN(n3879), .B(n3878), .C(n3877), .Y(
FPADDSUB_LZD_raw_out_EWR[4]) );
OAI211X1TS U3489 ( .A0(n4284), .A1(n4283), .B0(n4282), .C0(n4281), .Y(
FPADDSUB_LZD_raw_out_EWR[3]) );
CLKAND2X2TS U3490 ( .A(n1036), .B(n5138), .Y(FPADDSUB_formatted_number_W[8])
);
CLKAND2X2TS U3491 ( .A(n1036), .B(FPADDSUB_sftr_odat_SHT2_SWR[7]), .Y(
FPADDSUB_formatted_number_W[5]) );
CLKAND2X2TS U3492 ( .A(n1036), .B(FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(
FPADDSUB_formatted_number_W[4]) );
CLKAND2X2TS U3493 ( .A(n4975), .B(n5097), .Y(n857) );
XNOR2X1TS U3494 ( .A(n5055), .B(FPMULT_Op_MX[14]), .Y(n1035) );
INVX2TS U3495 ( .A(n3471), .Y(n2741) );
CLKXOR2X4TS U3496 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[8]), .Y(n1621) );
NAND2X4TS U3497 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[4]), .Y(n2199) );
OR2X8TS U3498 ( .A(n1645), .B(n1622), .Y(n1037) );
NAND2X4TS U3499 ( .A(n2446), .B(n3515), .Y(n1039) );
INVX4TS U3500 ( .A(n1689), .Y(n1126) );
INVX6TS U3501 ( .A(n1070), .Y(n1122) );
INVX4TS U3502 ( .A(n3623), .Y(n1488) );
OA21XLTS U3503 ( .A0(n4130), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n4129),
.Y(n1045) );
INVX6TS U3504 ( .A(n1538), .Y(n1205) );
XNOR2X1TS U3505 ( .A(n1965), .B(n949), .Y(n1053) );
XNOR2X1TS U3506 ( .A(n2137), .B(n2225), .Y(n1054) );
OR2X4TS U3507 ( .A(n2588), .B(n2587), .Y(n1055) );
OR2X4TS U3508 ( .A(n2178), .B(n2177), .Y(n1056) );
INVX4TS U3509 ( .A(n1620), .Y(n3305) );
CLKXOR2X4TS U3510 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[17]), .Y(n1620) );
NAND2X4TS U3511 ( .A(n2288), .B(n2289), .Y(n2402) );
INVX2TS U3512 ( .A(n3262), .Y(n1396) );
OAI22X4TS U3513 ( .A0(n1854), .A1(n1658), .B0(n1121), .B1(n1835), .Y(n1983)
);
INVX2TS U3514 ( .A(n3339), .Y(n1533) );
INVX6TS U3515 ( .A(n1574), .Y(n3164) );
XNOR2X1TS U3516 ( .A(FPMULT_Op_MY[4]), .B(n1224), .Y(n1059) );
INVX2TS U3517 ( .A(n1908), .Y(n1696) );
CLKXOR2X2TS U3518 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .Y(n2443) );
INVX4TS U3519 ( .A(n1622), .Y(n2319) );
CLKXOR2X2TS U3520 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[5]), .Y(n1622) );
OR2X6TS U3521 ( .A(n1054), .B(n1617), .Y(n1064) );
XNOR2X1TS U3522 ( .A(n3502), .B(n3501), .Y(n1065) );
XOR2X1TS U3523 ( .A(n1168), .B(FPMULT_Op_MX[16]), .Y(n1066) );
INVX2TS U3524 ( .A(n2382), .Y(n2274) );
INVX8TS U3525 ( .A(n1483), .Y(n2957) );
INVX4TS U3526 ( .A(n1935), .Y(n1610) );
AND2X2TS U3527 ( .A(n5047), .B(n1146), .Y(n1069) );
CLKXOR2X4TS U3528 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[2]), .Y(n1070) );
BUFX8TS U3529 ( .A(FPMULT_Op_MX[21]), .Y(n3379) );
INVX2TS U3530 ( .A(n5040), .Y(n1123) );
CLKINVX6TS U3531 ( .A(n1123), .Y(n1124) );
BUFX6TS U3532 ( .A(FPMULT_Op_MY[11]), .Y(n5040) );
INVX2TS U3533 ( .A(n2045), .Y(n1405) );
NOR2X6TS U3534 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .Y(n2045) );
INVX12TS U3535 ( .A(n1600), .Y(n3380) );
OA21X4TS U3536 ( .A0(n3160), .A1(n1388), .B0(n3159), .Y(n1074) );
OA21X4TS U3537 ( .A0(n2570), .A1(n2402), .B0(n2571), .Y(n1075) );
AND2X2TS U3538 ( .A(n2718), .B(FPMULT_Op_MY[11]), .Y(n1077) );
INVX4TS U3539 ( .A(n2129), .Y(n1541) );
INVX2TS U3540 ( .A(n2173), .Y(n1454) );
AND2X2TS U3541 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .Y(n1944) );
XNOR2X1TS U3542 ( .A(n1168), .B(n5038), .Y(n2423) );
AND2X4TS U3543 ( .A(n2712), .B(n1640), .Y(n1079) );
INVX2TS U3544 ( .A(n1401), .Y(n1526) );
XNOR2X2TS U3545 ( .A(n3071), .B(n1145), .Y(n1401) );
AND2X2TS U3546 ( .A(n1973), .B(n2046), .Y(n1083) );
INVX2TS U3547 ( .A(n2199), .Y(n2148) );
NOR2X6TS U3548 ( .A(n3085), .B(n3084), .Y(n3092) );
OA21XLTS U3549 ( .A0(n2671), .A1(n2670), .B0(n2669), .Y(n1085) );
AND2X2TS U3550 ( .A(n1637), .B(n3648), .Y(n1086) );
OAI21X2TS U3551 ( .A0(n5115), .A1(n4293), .B0(n4184), .Y(n1089) );
INVX2TS U3552 ( .A(n1670), .Y(n4227) );
INVX2TS U3553 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n4158) );
BUFX3TS U3554 ( .A(n929), .Y(n5317) );
INVX2TS U3555 ( .A(n3958), .Y(n5276) );
INVX2TS U3556 ( .A(n5282), .Y(n3960) );
XOR2X1TS U3557 ( .A(n3783), .B(n1031), .Y(FPMULT_Adder_M_result_A_adder[22])
);
INVX2TS U3558 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1120) );
OAI22X2TS U3559 ( .A0(n1057), .A1(n1967), .B0(n2038), .B1(n3133), .Y(n2057)
);
NOR2X4TS U3560 ( .A(n1057), .B(n2038), .Y(n1467) );
INVX2TS U3561 ( .A(rst), .Y(n1132) );
INVX2TS U3562 ( .A(rst), .Y(n1133) );
INVX4TS U3563 ( .A(n1069), .Y(n1136) );
INVX2TS U3564 ( .A(n1670), .Y(n1137) );
INVX2TS U3565 ( .A(n3960), .Y(n1139) );
INVX2TS U3566 ( .A(n3960), .Y(n1140) );
INVX2TS U3567 ( .A(n1068), .Y(n1141) );
INVX4TS U3568 ( .A(n1068), .Y(n1142) );
INVX2TS U3569 ( .A(n1077), .Y(n1143) );
INVX2TS U3570 ( .A(n1077), .Y(n1144) );
INVX4TS U3571 ( .A(n1547), .Y(n1145) );
XNOR2X2TS U3572 ( .A(n3527), .B(n1145), .Y(n3397) );
XNOR2X2TS U3573 ( .A(n3184), .B(n1145), .Y(n3258) );
XNOR2X2TS U3574 ( .A(n2968), .B(n1145), .Y(n3185) );
XNOR2X2TS U3575 ( .A(n3172), .B(n3336), .Y(n2970) );
INVX2TS U3576 ( .A(n3336), .Y(n3514) );
XNOR2X1TS U3577 ( .A(n3336), .B(n1174), .Y(n2449) );
XNOR2X2TS U3578 ( .A(n3336), .B(n2930), .Y(n2521) );
XNOR2X2TS U3579 ( .A(n3270), .B(n3336), .Y(n3057) );
XNOR2X2TS U3580 ( .A(n1459), .B(n3336), .Y(n2643) );
INVX8TS U3581 ( .A(FPMULT_Op_MY[0]), .Y(n1146) );
INVX2TS U3582 ( .A(n1621), .Y(n1150) );
NAND2BX1TS U3583 ( .AN(FPMULT_Op_MY[12]), .B(n1151), .Y(n1930) );
XNOR2X2TS U3584 ( .A(n1151), .B(n5049), .Y(n2476) );
XNOR2X2TS U3585 ( .A(n1151), .B(n5038), .Y(n2146) );
XNOR2X2TS U3586 ( .A(n1151), .B(n1126), .Y(n2622) );
XNOR2X2TS U3587 ( .A(n1151), .B(FPMULT_Op_MY[17]), .Y(n2214) );
XNOR2X1TS U3588 ( .A(FPMULT_Op_MX[13]), .B(n3112), .Y(n2061) );
XNOR2X1TS U3589 ( .A(n1151), .B(n5045), .Y(n2247) );
XNOR2X2TS U3590 ( .A(FPMULT_Op_MX[13]), .B(n5037), .Y(n1982) );
INVX2TS U3591 ( .A(n1088), .Y(n1153) );
INVX2TS U3592 ( .A(n3898), .Y(n1156) );
BUFX4TS U3593 ( .A(FPMULT_Op_MX[15]), .Y(n1159) );
XNOR2X2TS U3594 ( .A(n5055), .B(n5048), .Y(n2621) );
XNOR2X2TS U3595 ( .A(n5060), .B(FPMULT_Op_MY[17]), .Y(n2694) );
XNOR2X2TS U3596 ( .A(n5060), .B(n5038), .Y(n2625) );
XNOR2X2TS U3597 ( .A(n5060), .B(n5045), .Y(n2899) );
OAI22X2TS U3598 ( .A0(n4275), .A1(n4269), .B0(n4263), .B1(n1165), .Y(n4240)
);
NOR2X8TS U3599 ( .A(n4101), .B(n947), .Y(n4224) );
XOR2X1TS U3600 ( .A(n5038), .B(n1170), .Y(n2136) );
NAND2BX1TS U3601 ( .AN(n1278), .B(n1171), .Y(n1835) );
XNOR2X1TS U3602 ( .A(n1170), .B(FPMULT_Op_MX[1]), .Y(n1832) );
XNOR2X1TS U3603 ( .A(n1170), .B(FPMULT_Op_MX[11]), .Y(n1784) );
BUFX4TS U3604 ( .A(FPMULT_Op_MY[9]), .Y(n1172) );
INVX2TS U3605 ( .A(n1180), .Y(n1181) );
INVX2TS U3606 ( .A(n1090), .Y(n1183) );
INVX2TS U3607 ( .A(n1090), .Y(n1184) );
INVX2TS U3608 ( .A(n1090), .Y(n1185) );
INVX2TS U3609 ( .A(n4720), .Y(n1186) );
INVX2TS U3610 ( .A(n4720), .Y(n1187) );
INVX2TS U3611 ( .A(n4720), .Y(n1188) );
INVX2TS U3612 ( .A(n1092), .Y(n1189) );
INVX2TS U3613 ( .A(n1092), .Y(n1190) );
INVX2TS U3614 ( .A(n1092), .Y(n1191) );
INVX2TS U3615 ( .A(n1091), .Y(n1192) );
INVX2TS U3616 ( .A(n1091), .Y(n1193) );
INVX2TS U3617 ( .A(n1091), .Y(n1194) );
CLKINVX3TS U3618 ( .A(rst), .Y(n824) );
INVX2TS U3619 ( .A(n1094), .Y(n1195) );
INVX2TS U3620 ( .A(n1046), .Y(n1196) );
INVX2TS U3621 ( .A(n1093), .Y(n1197) );
NAND3BX2TS U3622 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .C(n4001), .Y(n4874) );
INVX2TS U3623 ( .A(n1115), .Y(n1198) );
OAI32X1TS U3624 ( .A0(n5107), .A1(n4717), .A2(n4719), .B0(
FPMULT_FS_Module_state_reg[1]), .B1(n3972), .Y(
FPMULT_FS_Module_state_next[2]) );
OAI21X1TS U3625 ( .A0(n4841), .A1(n4097), .B0(n4293), .Y(
FPADDSUB_Data_array_SWR[25]) );
NOR4X2TS U3626 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n3928) );
NAND2X1TS U3627 ( .A(n4486), .B(n5207), .Y(n3896) );
BUFX3TS U3628 ( .A(n5327), .Y(n5322) );
INVX2TS U3629 ( .A(n1045), .Y(n1199) );
OAI22X1TS U3630 ( .A0(n1164), .A1(n4243), .B0(n4242), .B1(n1165), .Y(n4244)
);
OAI21X1TS U3631 ( .A0(n4243), .A1(n1179), .B0(n4208), .Y(
FPADDSUB_Data_array_SWR[8]) );
AND3X2TS U3632 ( .A(n4204), .B(n4203), .C(n4202), .Y(n4243) );
OAI21X2TS U3633 ( .A0(n4130), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n4129),
.Y(n4155) );
BUFX3TS U3634 ( .A(n5323), .Y(n5321) );
NOR2X4TS U3635 ( .A(n5096), .B(n5097), .Y(n5020) );
NAND2X4TS U3636 ( .A(n1095), .B(n1162), .Y(n4291) );
CLKINVX3TS U3637 ( .A(n3958), .Y(n5279) );
NAND2BX1TS U3638 ( .AN(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n4786) );
NAND2X1TS U3639 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1106),
.Y(n5032) );
OAI221X1TS U3640 ( .A0(n1051), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n1111), .B1(
FPADDSUB_intDY_EWSW[0]), .C0(n4682), .Y(n4685) );
INVX2TS U3641 ( .A(n1104), .Y(n1200) );
OAI211XLTS U3642 ( .A0(n1182), .A1(n4053), .B0(n4052), .C0(n4051), .Y(
add_subt_data2[22]) );
OAI21X1TS U3643 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n3873), .Y(n3874) );
AOI221X1TS U3644 ( .A0(n1099), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[27]), .B1(n1048), .C0(n4698), .Y(n4699) );
AOI211X1TS U3645 ( .A0(n1153), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n4303),
.C0(n3900), .Y(n3903) );
AOI21X2TS U3646 ( .A0(n3897), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n4122),
.Y(n4292) );
OAI221X1TS U3647 ( .A0(FPADDSUB_intDX_EWSW[14]), .A1(n5110), .B0(n5156),
.B1(FPADDSUB_intDY_EWSW[14]), .C0(n4699), .Y(n4709) );
OAI221XLTS U3648 ( .A0(n1108), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n1047),
.B1(FPADDSUB_intDY_EWSW[3]), .C0(n4683), .Y(n4684) );
OAI221X1TS U3649 ( .A0(n4836), .A1(FPADDSUB_intDX_EWSW[29]), .B0(n1109),
.B1(FPADDSUB_intDY_EWSW[18]), .C0(n4680), .Y(n4687) );
AOI221X1TS U3650 ( .A0(n4817), .A1(FPADDSUB_intDY_EWSW[10]), .B0(
FPADDSUB_intDY_EWSW[11]), .B1(n1096), .C0(n4702), .Y(n4705) );
OAI221X1TS U3651 ( .A0(n1107), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n4829),
.B1(FPADDSUB_intDY_EWSW[16]), .C0(n4690), .Y(n4693) );
OAI221XLTS U3652 ( .A0(n1050), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n1110),
.B1(FPADDSUB_intDY_EWSW[24]), .C0(n4697), .Y(n4710) );
CLKINVX3TS U3653 ( .A(n5029), .Y(n5269) );
INVX2TS U3654 ( .A(n3960), .Y(n5271) );
CLKINVX3TS U3655 ( .A(n3960), .Y(n5272) );
INVX3TS U3656 ( .A(n5029), .Y(n5268) );
CLKINVX3TS U3657 ( .A(n5029), .Y(n5265) );
CLKINVX3TS U3658 ( .A(n5029), .Y(n5266) );
CLKINVX3TS U3659 ( .A(n5029), .Y(n5267) );
CLKINVX3TS U3660 ( .A(n3958), .Y(n5277) );
INVX3TS U3661 ( .A(n3958), .Y(n5278) );
NOR4X2TS U3662 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3906) );
AOI31X1TS U3663 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n4041), .A2(n5150),
.B0(n4040), .Y(n3916) );
INVX3TS U3664 ( .A(n3960), .Y(n5275) );
INVX3TS U3665 ( .A(n3960), .Y(n5274) );
CLKINVX3TS U3666 ( .A(n3960), .Y(n5270) );
NOR2X4TS U3667 ( .A(n5098), .B(n5118), .Y(n4976) );
AOI221X1TS U3668 ( .A0(n4827), .A1(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDY_EWSW[9]), .B1(n1098), .C0(n4701), .Y(n4706) );
AOI221X1TS U3669 ( .A0(n4828), .A1(FPADDSUB_intDX_EWSW[12]), .B0(
FPADDSUB_intDY_EWSW[2]), .B1(n1097), .C0(n4700), .Y(n4707) );
OAI211XLTS U3670 ( .A0(n1182), .A1(n4064), .B0(n4063), .C0(n4062), .Y(
add_subt_data2[13]) );
INVX2TS U3671 ( .A(n1113), .Y(n1201) );
AOI222X1TS U3672 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4822), .B0(n4630), .B1(
n4629), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n4823), .Y(n4632) );
OAI221X1TS U3673 ( .A0(n4823), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n4822), .B1(
FPADDSUB_intDY_EWSW[4]), .C0(n4688), .Y(n4695) );
OAI221XLTS U3674 ( .A0(n5157), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n4824),
.B1(FPADDSUB_intDY_EWSW[6]), .C0(n4681), .Y(n4686) );
XNOR2X2TS U3675 ( .A(n5055), .B(n1202), .Y(n2060) );
XNOR2X2TS U3676 ( .A(FPMULT_Op_MX[13]), .B(n1202), .Y(n1936) );
NAND2X1TS U3677 ( .A(n1202), .B(n3112), .Y(n3113) );
NOR2BX1TS U3678 ( .AN(n5217), .B(FPMULT_Op_MY[13]), .Y(n3114) );
XOR2X1TS U3679 ( .A(FPMULT_Op_MY[13]), .B(n5217), .Y(n3050) );
XOR2X1TS U3680 ( .A(n5037), .B(n1202), .Y(n1964) );
OAI22X1TS U3681 ( .A0(n3246), .A1(n1202), .B0(n3557), .B1(n5037), .Y(n2891)
);
AND2X2TS U3682 ( .A(n3558), .B(n1483), .Y(n3602) );
OAI22X1TS U3683 ( .A0(n3558), .A1(n5045), .B0(n3557), .B1(FPMULT_Op_MY[19]),
.Y(n3245) );
NOR2X1TS U3684 ( .A(n3557), .B(FPMULT_Op_MY[17]), .Y(n3048) );
NAND2BX1TS U3685 ( .AN(n3557), .B(n1675), .Y(n2628) );
CLKBUFX2TS U3686 ( .A(n2623), .Y(n1203) );
OAI22X2TS U3687 ( .A0(n1203), .A1(n2476), .B0(n2622), .B1(n1040), .Y(n2614)
);
OAI22X1TS U3688 ( .A0(n1203), .A1(n2061), .B0(n2146), .B1(n1040), .Y(n2132)
);
OAI22X2TS U3689 ( .A0(n1203), .A1(n2422), .B0(n2476), .B1(n1147), .Y(n2484)
);
OAI22X1TS U3690 ( .A0(n2623), .A1(n2247), .B0(n2366), .B1(n1040), .Y(n2369)
);
OAI22X2TS U3691 ( .A0(n2623), .A1(n2146), .B0(n2214), .B1(n1040), .Y(n2221)
);
OAI22X2TS U3692 ( .A0(n2623), .A1(n1982), .B0(n2061), .B1(n1040), .Y(n3087)
);
OAI22X2TS U3693 ( .A0(n2623), .A1(n2214), .B0(n2247), .B1(n1040), .Y(n2243)
);
NAND2X2TS U3694 ( .A(n1930), .B(n2623), .Y(n3022) );
OAI22X2TS U3695 ( .A0(n2623), .A1(n1936), .B0(n1982), .B1(n1040), .Y(n3016)
);
OAI22X1TS U3696 ( .A0(n1204), .A1(n1722), .B0(n2124), .B1(n1777), .Y(n1781)
);
OAI22X1TS U3697 ( .A0(n1911), .A1(n1812), .B0(n2124), .B1(n1856), .Y(n1873)
);
OAI22X2TS U3698 ( .A0(n1204), .A1(n1858), .B0(n2124), .B1(n1855), .Y(n1883)
);
OAI22X1TS U3699 ( .A0(n1911), .A1(n1777), .B0(n2124), .B1(n1787), .Y(n1783)
);
OAI22X2TS U3700 ( .A0(n1204), .A1(n1666), .B0(n2124), .B1(n1819), .Y(n1823)
);
OAI2BB2X1TS U3701 ( .B0(n1911), .B1(n1814), .A0N(n1696), .A1N(n1813), .Y(
n1820) );
OAI22X2TS U3702 ( .A0(n1911), .A1(n1737), .B0(n2124), .B1(n1723), .Y(n1748)
);
OAI2BB2X1TS U3703 ( .B0(n1911), .B1(n1910), .A0N(n1696), .A1N(n1909), .Y(
n2096) );
NOR2X1TS U3704 ( .A(n1911), .B(n1856), .Y(n1857) );
OAI22X1TS U3705 ( .A0(n1205), .A1(n1851), .B0(n1122), .B1(n1853), .Y(n1865)
);
OAI22X1TS U3706 ( .A0(n1205), .A1(n1853), .B0(n1122), .B1(n1852), .Y(n1884)
);
OAI2BB2X1TS U3707 ( .B0(n1205), .B1(n1834), .A0N(n1704), .A1N(n1833), .Y(
n1837) );
OAI2BB2X1TS U3708 ( .B0(n1205), .B1(n1826), .A0N(n1704), .A1N(n1818), .Y(
n1824) );
OAI2BB2X1TS U3709 ( .B0(n1205), .B1(n1832), .A0N(n1704), .A1N(n1827), .Y(
n1839) );
OAI2BB2X1TS U3710 ( .B0(n1205), .B1(n1817), .A0N(n1704), .A1N(n1816), .Y(
n1862) );
OAI22X1TS U3711 ( .A0(n1205), .A1(n1721), .B0(n1122), .B1(n1726), .Y(n1732)
);
OAI22X2TS U3712 ( .A0(n1205), .A1(n1726), .B0(n1122), .B1(n1768), .Y(n1775)
);
OAI22X2TS U3713 ( .A0(n1205), .A1(n1751), .B0(n1122), .B1(n1721), .Y(n1749)
);
OAI22X2TS U3714 ( .A0(n3045), .A1(n2141), .B0(n1125), .B1(n2213), .Y(n2212)
);
OAI22X1TS U3715 ( .A0(n2898), .A1(n1978), .B0(n1125), .B1(n2060), .Y(n2052)
);
OAI22X2TS U3716 ( .A0(n2898), .A1(n2213), .B0(n1125), .B1(n2241), .Y(n2245)
);
OAI2BB2X2TS U3717 ( .B0(n3045), .B1(n2241), .A0N(n1976), .A1N(n2240), .Y(
n2373) );
OAI22X2TS U3718 ( .A0(n2898), .A1(n1664), .B0(n1125), .B1(n1977), .Y(n2053)
);
OAI2BB2X2TS U3719 ( .B0(n2898), .B1(n2488), .A0N(n1976), .A1N(n2487), .Y(
n2618) );
BUFX3TS U3720 ( .A(n3200), .Y(n1206) );
OAI22X1TS U3721 ( .A0(n1206), .A1(n2423), .B0(n1594), .B1(n2477), .Y(n2483)
);
OAI2BB2X1TS U3722 ( .B0(n1206), .B1(n2250), .A0N(n1373), .A1N(n2249), .Y(
n2367) );
OAI22X1TS U3723 ( .A0(n3200), .A1(n3046), .B0(n3199), .B1(n1169), .Y(n3106)
);
OAI22X1TS U3724 ( .A0(n3200), .A1(n2142), .B0(n1594), .B1(n2210), .Y(n2211)
);
OAI22X2TS U3725 ( .A0(n1206), .A1(n2687), .B0(n1594), .B1(n2888), .Y(n2904)
);
AO21X2TS U3726 ( .A0(n3200), .A1(n1594), .B0(n1667), .Y(n3240) );
OAI22X1TS U3727 ( .A0(n3200), .A1(n1169), .B0(n1594), .B1(n1667), .Y(n3192)
);
OAI22X1TS U3728 ( .A0(n3200), .A1(n2370), .B0(n1594), .B1(n2423), .Y(n2426)
);
NOR2X1TS U3729 ( .A(n3200), .B(n1667), .Y(n2144) );
OAI22X1TS U3730 ( .A0(n3200), .A1(n2624), .B0(n2687), .B1(n1594), .Y(n2697)
);
OAI22X2TS U3731 ( .A0(n3200), .A1(n2953), .B0(n1594), .B1(n3046), .Y(n3040)
);
BUFX6TS U3732 ( .A(n3128), .Y(n1207) );
NAND2BX1TS U3733 ( .AN(n1173), .B(n1207), .Y(n2153) );
XNOR2X2TS U3734 ( .A(n3527), .B(n3128), .Y(n3173) );
XNOR2X1TS U3735 ( .A(n3571), .B(n1207), .Y(n3129) );
XNOR2X1TS U3736 ( .A(n3184), .B(n1207), .Y(n2942) );
XNOR2X2TS U3737 ( .A(n3172), .B(n3128), .Y(n2473) );
XNOR2X2TS U3738 ( .A(n3270), .B(n3128), .Y(n2652) );
XNOR2X2TS U3739 ( .A(n3312), .B(n3128), .Y(n2717) );
XNOR2X2TS U3740 ( .A(n2968), .B(n3128), .Y(n2877) );
XNOR2X1TS U3741 ( .A(n3128), .B(n1173), .Y(n2140) );
XNOR2X2TS U3742 ( .A(n2930), .B(n3128), .Y(n2226) );
XNOR2X2TS U3743 ( .A(n3131), .B(n3128), .Y(n2407) );
INVX4TS U3744 ( .A(n3267), .Y(n3128) );
OAI22X1TS U3745 ( .A0(n1399), .A1(n1144), .B0(n3632), .B1(n1292), .Y(n3642)
);
OAI22X1TS U3746 ( .A0(n3572), .A1(n1144), .B0(n1399), .B1(n1292), .Y(n3596)
);
OAI22X1TS U3747 ( .A0(n3525), .A1(n1143), .B0(n3572), .B1(n1292), .Y(n3555)
);
OAI22X1TS U3748 ( .A0(n3525), .A1(n1292), .B0(n3398), .B1(n1144), .Y(n3529)
);
OAI22X1TS U3749 ( .A0(n3271), .A1(n1292), .B0(n1441), .B1(n1144), .Y(n3275)
);
OAI22X1TS U3750 ( .A0(n3132), .A1(n1292), .B0(n3072), .B1(n1144), .Y(n3137)
);
OAI21X2TS U3751 ( .A0(n1292), .A1(n3345), .B0(n1291), .Y(n3355) );
OAI22X1TS U3752 ( .A0(n1441), .A1(n1077), .B0(n3132), .B1(n1143), .Y(n3171)
);
OAI22X2TS U3753 ( .A0(n2971), .A1(n1077), .B0(n1143), .B1(n2931), .Y(n2988)
);
NOR2BX2TS U3754 ( .AN(n1174), .B(n1077), .Y(n2928) );
NOR2X2TS U3755 ( .A(n3072), .B(n1077), .Y(n1390) );
INVX2TS U3756 ( .A(n1579), .Y(n1208) );
XNOR2X2TS U3757 ( .A(n2878), .B(n2930), .Y(n1938) );
XNOR2X1TS U3758 ( .A(n3184), .B(n1208), .Y(n2510) );
XNOR2X1TS U3759 ( .A(n3270), .B(n1208), .Y(n2279) );
XNOR2X1TS U3760 ( .A(n3172), .B(n1208), .Y(n2203) );
XNOR2X2TS U3761 ( .A(n3131), .B(n2878), .Y(n2152) );
XNOR2X2TS U3762 ( .A(n3571), .B(n2878), .Y(n2713) );
CLKXOR2X2TS U3763 ( .A(n3632), .B(n2878), .Y(n2880) );
XNOR2X2TS U3764 ( .A(n3312), .B(n2878), .Y(n2384) );
XNOR2X2TS U3765 ( .A(n2968), .B(n2878), .Y(n2459) );
NAND2BX1TS U3766 ( .AN(n1173), .B(n2878), .Y(n1953) );
INVX2TS U3767 ( .A(n2878), .Y(n1974) );
INVX4TS U3768 ( .A(n1579), .Y(n2878) );
NAND2X4TS U3769 ( .A(n4306), .B(n4158), .Y(n4160) );
INVX6TS U3770 ( .A(n1599), .Y(n1209) );
NOR2X2TS U3771 ( .A(n1677), .B(n3196), .Y(n3198) );
OAI22X1TS U3772 ( .A0(n1677), .A1(n2889), .B0(n3380), .B1(n2952), .Y(n2958)
);
INVX6TS U3773 ( .A(n3379), .Y(n1211) );
MXI2X1TS U3774 ( .A(n3380), .B(n1209), .S0(n1211), .Y(n3381) );
OAI2BB2X1TS U3775 ( .B0(n1209), .B1(n3304), .A0N(n3303), .A1N(n1211), .Y(
n3344) );
CLKXOR2X2TS U3776 ( .A(n5046), .B(n1211), .Y(n3107) );
CLKXOR2X2TS U3777 ( .A(n1202), .B(n1210), .Y(n2486) );
CLKXOR2X2TS U3778 ( .A(n5045), .B(n1210), .Y(n3042) );
CLKXOR2X2TS U3779 ( .A(n5037), .B(n1210), .Y(n2630) );
CLKXOR2X2TS U3780 ( .A(n3112), .B(n1210), .Y(n2689) );
XNOR2X1TS U3781 ( .A(n1212), .B(FPMULT_Op_MX[11]), .Y(n2299) );
XNOR2X1TS U3782 ( .A(n1212), .B(FPMULT_Op_MX[2]), .Y(n1755) );
XNOR2X2TS U3783 ( .A(n1212), .B(FPMULT_Op_MX[7]), .Y(n1789) );
XNOR2X1TS U3784 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MX[1]), .Y(n1847) );
XNOR2X2TS U3785 ( .A(n1212), .B(FPMULT_Op_MX[4]), .Y(n1707) );
XNOR2X2TS U3786 ( .A(n1212), .B(FPMULT_Op_MX[8]), .Y(n1917) );
XNOR2X2TS U3787 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MX[9]), .Y(n2097) );
INVX4TS U3788 ( .A(n1933), .Y(n1213) );
OAI22X1TS U3789 ( .A0(n2510), .A1(n1213), .B0(n2459), .B1(n1142), .Y(n2498)
);
OAI22X1TS U3790 ( .A0(n2510), .A1(n1142), .B0(n2604), .B1(n1213), .Y(n2656)
);
OAI22X2TS U3791 ( .A0(n2604), .A1(n1142), .B0(n2713), .B1(n1213), .Y(n2706)
);
OAI22X1TS U3792 ( .A0(n2279), .A1(n1142), .B0(n2384), .B1(n1213), .Y(n2395)
);
OAI22X1TS U3793 ( .A0(n2203), .A1(n1142), .B0(n2279), .B1(n1213), .Y(n2267)
);
OAI22X2TS U3794 ( .A0(n2203), .A1(n1213), .B0(n2152), .B1(n1142), .Y(n2185)
);
OAI22X1TS U3795 ( .A0(n2880), .A1(n1142), .B0(n1974), .B1(n1213), .Y(n2967)
);
OAI22X2TS U3796 ( .A0(n2051), .A1(n2879), .B0(n1975), .B1(n1142), .Y(n2034)
);
NOR2BX1TS U3797 ( .AN(n1174), .B(n2879), .Y(n2023) );
OAI22X2TS U3798 ( .A0(n2152), .A1(n2879), .B0(n2051), .B1(n1141), .Y(n2164)
);
OAI22X2TS U3799 ( .A0(n1141), .A1(n1174), .B0(n1938), .B1(n2879), .Y(n1952)
);
INVX2TS U3800 ( .A(n1933), .Y(n2879) );
CLKXOR2X2TS U3801 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .Y(n1933) );
OAI22X2TS U3802 ( .A0(n1060), .A1(n2694), .B0(n3305), .B1(n2899), .Y(n2901)
);
OAI22X2TS U3803 ( .A0(n1060), .A1(n2899), .B0(n1214), .B1(n2954), .Y(n2955)
);
AO21X1TS U3804 ( .A0(n2320), .A1(n1215), .B0(n5219), .Y(n2535) );
OAI22X1TS U3805 ( .A0(n2320), .A1(n2299), .B0(n1215), .B1(n5219), .Y(n2312)
);
OAI22X1TS U3806 ( .A0(n2320), .A1(n2117), .B0(n1215), .B1(n2299), .Y(n2295)
);
OAI22X2TS U3807 ( .A0(n2320), .A1(n2097), .B0(n1215), .B1(n2117), .Y(n2119)
);
OAI22X1TS U3808 ( .A0(n1037), .A1(n1847), .B0(n2319), .B1(n1755), .Y(n1844)
);
OAI22X1TS U3809 ( .A0(n1037), .A1(n1706), .B0(n2319), .B1(n1766), .Y(n1762)
);
OAI22X2TS U3810 ( .A0(n1037), .A1(n5219), .B0(n2319), .B1(n1850), .Y(n1866)
);
OAI22X1TS U3811 ( .A0(n1037), .A1(n1755), .B0(n2319), .B1(n1736), .Y(n1881)
);
OAI22X2TS U3812 ( .A0(n1216), .A1(n2122), .B0(n1708), .B1(n1148), .Y(n1714)
);
NOR2X1TS U3813 ( .A(n1216), .B(n1652), .Y(n1916) );
NOR2X2TS U3814 ( .A(n1216), .B(n1651), .Y(n2090) );
XNOR2X1TS U3815 ( .A(n1217), .B(n1173), .Y(n1967) );
XNOR2X1TS U3816 ( .A(n3527), .B(n1217), .Y(n3073) );
XNOR2X2TS U3817 ( .A(n3571), .B(n1217), .Y(n2987) );
XNOR2X2TS U3818 ( .A(n3524), .B(n1217), .Y(n2907) );
XNOR2X1TS U3819 ( .A(n3184), .B(n1217), .Y(n2704) );
XNOR2X2TS U3820 ( .A(n3312), .B(n950), .Y(n2474) );
NAND2BX1TS U3821 ( .AN(n1173), .B(n950), .Y(n1971) );
OAI22X1TS U3822 ( .A0(n3567), .A1(n3601), .B0(n1219), .B1(n3599), .Y(n3598)
);
AO21X1TS U3823 ( .A0(n3601), .A1(n1219), .B0(n3599), .Y(n3639) );
OAI22X1TS U3824 ( .A0(n3352), .A1(n1219), .B0(n3299), .B1(n3601), .Y(n3348)
);
OAI22X1TS U3825 ( .A0(n3103), .A1(n3601), .B0(n3174), .B1(n1219), .Y(n3177)
);
OAI22X1TS U3826 ( .A0(n3174), .A1(n3601), .B0(n3272), .B1(n1219), .Y(n3273)
);
OAI22X2TS U3827 ( .A0(n3103), .A1(n3600), .B0(n3056), .B1(n3601), .Y(n3102)
);
OAI22X2TS U3828 ( .A0(n3272), .A1(n3601), .B0(n3299), .B1(n3600), .Y(n3285)
);
OAI22X1TS U3829 ( .A0(n1041), .A1(n3599), .B0(n3600), .B1(n2641), .Y(n2740)
);
OAI22X2TS U3830 ( .A0(n1041), .A1(n2719), .B0(n2929), .B1(n3600), .Y(n2927)
);
NOR2BX1TS U3831 ( .AN(n1173), .B(n3600), .Y(n2646) );
OAI22X2TS U3832 ( .A0(n1041), .A1(n2642), .B0(n3600), .B1(n2719), .Y(n2716)
);
INVX2TS U3833 ( .A(n1553), .Y(n3600) );
INVX2TS U3834 ( .A(n1597), .Y(n1220) );
OAI22X1TS U3835 ( .A0(n2704), .A1(n1598), .B0(n2907), .B1(n1220), .Y(n2932)
);
OAI22X1TS U3836 ( .A0(n2704), .A1(n1220), .B0(n1057), .B1(n2600), .Y(n2707)
);
OAI22X1TS U3837 ( .A0(n3073), .A1(n1057), .B0(n1220), .B1(n957), .Y(n3135)
);
OAI22X2TS U3838 ( .A0(n2907), .A1(n1598), .B0(n2987), .B1(n1220), .Y(n3001)
);
OAI22X2TS U3839 ( .A0(n2987), .A1(n1598), .B0(n3073), .B1(n3133), .Y(n3069)
);
AO21X1TS U3840 ( .A0(n1057), .A1(n3133), .B0(n957), .Y(n3170) );
NOR2BX1TS U3841 ( .AN(n1174), .B(n3133), .Y(n1968) );
OAI22X2TS U3842 ( .A0(n1598), .A1(n2251), .B0(n2392), .B1(n3133), .Y(n2360)
);
NOR2X2TS U3843 ( .A(n2155), .B(n3133), .Y(n1466) );
INVX4TS U3844 ( .A(n1597), .Y(n3133) );
OAI22X1TS U3845 ( .A0(n3258), .A1(n3516), .B0(n3300), .B1(n1221), .Y(n3317)
);
AO21X1TS U3846 ( .A0(n3516), .A1(n1221), .B0(n3514), .Y(n3570) );
OAI22X2TS U3847 ( .A0(n2970), .A1(n3516), .B0(n3057), .B1(n1221), .Y(n3030)
);
OAI22X2TS U3848 ( .A0(n3057), .A1(n3516), .B0(n3134), .B1(n3515), .Y(n3101)
);
OR2X4TS U3849 ( .A(n2881), .B(n3515), .Y(n1567) );
NOR2BX2TS U3850 ( .AN(n1174), .B(n1221), .Y(n2406) );
NAND2BX1TS U3851 ( .AN(n1221), .B(n3336), .Y(n1550) );
INVX2TS U3852 ( .A(n1617), .Y(n1222) );
OAI22X1TS U3853 ( .A0(n2942), .A1(n1222), .B0(n2877), .B1(n3269), .Y(n2964)
);
OAI22X2TS U3854 ( .A0(n3032), .A1(n3269), .B0(n3129), .B1(n1222), .Y(n3094)
);
OAI22X1TS U3855 ( .A0(n2942), .A1(n3269), .B0(n3032), .B1(n1222), .Y(n3076)
);
OAI22X1TS U3856 ( .A0(n3129), .A1(n3269), .B0(n3173), .B1(n1222), .Y(n3189)
);
OAI22X1TS U3857 ( .A0(n2473), .A1(n1222), .B0(n2407), .B1(n3269), .Y(n2511)
);
OAI22X1TS U3858 ( .A0(n3173), .A1(n3269), .B0(n3268), .B1(n3267), .Y(n3274)
);
OAI22X2TS U3859 ( .A0(n2652), .A1(n3269), .B0(n2717), .B1(n3268), .Y(n2730)
);
OAI22X2TS U3860 ( .A0(n3269), .A1(n2473), .B0(n3268), .B1(n2652), .Y(n2648)
);
AO21X1TS U3861 ( .A0(n3269), .A1(n3268), .B0(n3267), .Y(n3287) );
OAI22X2TS U3862 ( .A0(n2256), .A1(n3268), .B0(n1064), .B1(n2226), .Y(n1356)
);
OAI22X2TS U3863 ( .A0(n2256), .A1(n1064), .B0(n3268), .B1(n2386), .Y(n2355)
);
NOR2BX1TS U3864 ( .AN(n1173), .B(n3268), .Y(n2161) );
OAI22X2TS U3865 ( .A0(n1064), .A1(n3267), .B0(n3268), .B1(n2153), .Y(n2191)
);
INVX4TS U3866 ( .A(n1617), .Y(n3268) );
XNOR2X2TS U3867 ( .A(n1223), .B(FPMULT_Op_MX[6]), .Y(n1723) );
XNOR2X2TS U3868 ( .A(n1224), .B(FPMULT_Op_MX[4]), .Y(n1855) );
XNOR2X2TS U3869 ( .A(n1223), .B(FPMULT_Op_MX[3]), .Y(n1858) );
XNOR2X1TS U3870 ( .A(n1224), .B(FPMULT_Op_MX[1]), .Y(n1812) );
NOR2X1TS U3871 ( .A(n1224), .B(n5039), .Y(n1535) );
XNOR2X2TS U3872 ( .A(n1224), .B(FPMULT_Op_MX[11]), .Y(n2098) );
XNOR2X2TS U3873 ( .A(n1223), .B(FPMULT_Op_MX[5]), .Y(n1737) );
XOR2X1TS U3874 ( .A(n5045), .B(n1223), .Y(n2258) );
NOR2X1TS U3875 ( .A(n3266), .B(n3339), .Y(n1398) );
OAI22X1TS U3876 ( .A0(n3266), .A1(n3310), .B0(n3311), .B1(n3339), .Y(n3316)
);
OAI22X1TS U3877 ( .A0(n2882), .A1(n3310), .B0(n2969), .B1(n1225), .Y(n2965)
);
NOR2X2TS U3878 ( .A(n2734), .B(n1225), .Y(n1438) );
OAI22X2TS U3879 ( .A0(n3311), .A1(n3310), .B0(n1225), .B1(n3338), .Y(n3353)
);
AO21X1TS U3880 ( .A0(n3340), .A1(n1225), .B0(n3338), .Y(n3388) );
OAI22X1TS U3881 ( .A0(n3340), .A1(n3338), .B0(n1225), .B1(n2263), .Y(n2354)
);
NAND2X4TS U3882 ( .A(n2260), .B(n3339), .Y(n3340) );
NOR2BX2TS U3883 ( .AN(n1227), .B(n1147), .Y(n2753) );
ADDFX2TS U3884 ( .A(n1226), .B(n2891), .CI(n2890), .CO(n2948), .S(n2903) );
OAI22X2TS U3885 ( .A0(n2623), .A1(n1226), .B0(n1936), .B1(n1040), .Y(n3021)
);
XNOR2X1TS U3886 ( .A(n1168), .B(n1227), .Y(n2142) );
NOR2BX1TS U3887 ( .AN(n1226), .B(n3199), .Y(n2134) );
NOR2BX2TS U3888 ( .AN(n1227), .B(n3305), .Y(n2246) );
NAND2BX1TS U3889 ( .AN(n1227), .B(n1168), .Y(n2143) );
NAND2BX1TS U3890 ( .AN(n1227), .B(n1160), .Y(n2248) );
NOR2BX1TS U3891 ( .AN(n1226), .B(n3380), .Y(n2433) );
XNOR2X1TS U3892 ( .A(n1227), .B(n3379), .Y(n2421) );
NAND2BX1TS U3893 ( .AN(n1226), .B(n5055), .Y(n1977) );
NOR2BX2TS U3894 ( .AN(n1227), .B(n1125), .Y(n3015) );
OAI211XLTS U3895 ( .A0(n1080), .A1(n1671), .B0(n3974), .C0(n3970), .Y(
FPMULT_FS_Module_state_next[3]) );
XOR2X1TS U3896 ( .A(n980), .B(n979), .Y(FPMULT_Sgf_operation_Result[27]) );
XNOR2X2TS U3897 ( .A(n1063), .B(n3860), .Y(FPMULT_Sgf_operation_Result[25])
);
MXI2X1TS U3898 ( .A(n3903), .B(n3904), .S0(n1163), .Y(n5135) );
NAND3X2TS U3899 ( .A(n4104), .B(n4103), .C(n4102), .Y(n4249) );
NOR2X2TS U3900 ( .A(n5144), .B(n4717), .Y(n3968) );
AOI21X2TS U3901 ( .A0(n3897), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n4121),
.Y(n4287) );
OAI21X2TS U3902 ( .A0(n4130), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n4129),
.Y(n4149) );
ADDHXLTS U3903 ( .A(FPMULT_Sgf_normalized_result[17]), .B(n3775), .CO(n2859),
.S(FPMULT_Adder_M_result_A_adder[17]) );
ADDHXLTS U3904 ( .A(FPMULT_Sgf_normalized_result[15]), .B(n3776), .CO(n2864),
.S(FPMULT_Adder_M_result_A_adder[15]) );
ADDHXLTS U3905 ( .A(FPMULT_Sgf_normalized_result[13]), .B(n3778), .CO(n2863),
.S(FPMULT_Adder_M_result_A_adder[13]) );
ADDHXLTS U3906 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n3780), .CO(n2861),
.S(FPMULT_Adder_M_result_A_adder[9]) );
ADDHXLTS U3907 ( .A(FPMULT_Sgf_normalized_result[8]), .B(n2862), .CO(n3780),
.S(FPMULT_Adder_M_result_A_adder[8]) );
OAI32X4TS U3908 ( .A0(n1692), .A1(FPSENCOS_d_ff1_operation_out), .A2(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .B0(
FPSENCOS_d_ff1_shift_region_flag_out[0]), .B1(n4814), .Y(n4815) );
OAI21XLTS U3909 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n5196), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n4624) );
NOR4X4TS U3910 ( .A(n3929), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .D(n5161), .Y(n5281) );
AOI21X1TS U3911 ( .A0(n3744), .A1(n3743), .B0(n3742), .Y(n3806) );
XNOR2X2TS U3912 ( .A(n3744), .B(n3673), .Y(n3772) );
AOI21X1TS U3913 ( .A0(n3744), .A1(n3717), .B0(n3716), .Y(n3722) );
AOI21X1TS U3914 ( .A0(n3744), .A1(n3710), .B0(n3709), .Y(n3715) );
AOI21X1TS U3915 ( .A0(n3744), .A1(n3672), .B0(n3665), .Y(n3670) );
AOI21X1TS U3916 ( .A0(n3744), .A1(n3497), .B0(n3496), .Y(n3502) );
AOI21X1TS U3917 ( .A0(n3744), .A1(n3687), .B0(n3694), .Y(n3493) );
AOI21X1TS U3918 ( .A0(n3744), .A1(n3700), .B0(n3699), .Y(n3704) );
OAI21XLTS U3919 ( .A0(n5020), .A1(FPSENCOS_cont_iter_out[1]), .B0(n3980),
.Y(n864) );
AOI21X2TS U3920 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n5097), .B0(n3965),
.Y(n3980) );
OAI21X2TS U3921 ( .A0(n5131), .A1(n4293), .B0(n4218), .Y(n4272) );
OAI21X2TS U3922 ( .A0(n1670), .A1(n5160), .B0(n4175), .Y(n4253) );
AOI21X2TS U3923 ( .A0(n1138), .A1(FPADDSUB_Raw_mant_NRM_SWR[0]), .B0(n4096),
.Y(n4841) );
OAI21X1TS U3924 ( .A0(n1137), .A1(n5148), .B0(FPADDSUB_Shift_reg_FLAGS_7[1]),
.Y(n4096) );
INVX2TS U3925 ( .A(n1230), .Y(n1231) );
INVX2TS U3926 ( .A(n1232), .Y(n1233) );
INVX2TS U3927 ( .A(n1234), .Y(n1235) );
INVX2TS U3928 ( .A(n1236), .Y(n1237) );
INVX2TS U3929 ( .A(n1238), .Y(n1239) );
INVX2TS U3930 ( .A(n1240), .Y(n1241) );
INVX2TS U3931 ( .A(n1242), .Y(n1243) );
INVX2TS U3932 ( .A(n1244), .Y(n1245) );
INVX2TS U3933 ( .A(n1246), .Y(n1247) );
INVX2TS U3934 ( .A(n1248), .Y(n1249) );
INVX2TS U3935 ( .A(n1250), .Y(n1251) );
INVX2TS U3936 ( .A(n1252), .Y(n1253) );
INVX2TS U3937 ( .A(n1254), .Y(n1255) );
INVX2TS U3938 ( .A(n1256), .Y(n1257) );
INVX2TS U3939 ( .A(n1258), .Y(n1259) );
INVX2TS U3940 ( .A(n1260), .Y(n1261) );
INVX2TS U3941 ( .A(n1262), .Y(n1263) );
INVX2TS U3942 ( .A(n1264), .Y(n1265) );
INVX2TS U3943 ( .A(n1266), .Y(n1267) );
INVX2TS U3944 ( .A(n1268), .Y(n1269) );
INVX2TS U3945 ( .A(n1270), .Y(n1271) );
INVX2TS U3946 ( .A(n1272), .Y(n1273) );
INVX2TS U3947 ( .A(n1274), .Y(n1275) );
OR2X1TS U3948 ( .A(n5106), .B(FPADDSUB_DMP_SFG[12]), .Y(n4420) );
OR2X1TS U3949 ( .A(n5102), .B(FPADDSUB_DMP_SFG[9]), .Y(n4378) );
AOI21X2TS U3950 ( .A0(n3897), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n4106),
.Y(n4128) );
AOI21X2TS U3951 ( .A0(n3897), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n4133),
.Y(n4152) );
NOR2X2TS U3952 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4579) );
NOR3BX2TS U3953 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n3905),
.C(n3926), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]) );
NOR4BX2TS U3954 ( .AN(n3906), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]),
.C(n3905), .D(n1693), .Y(FPSENCOS_enab_RB3) );
NAND2X1TS U3955 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n4385) );
NOR2X1TS U3956 ( .A(n5099), .B(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1028) );
NOR2X2TS U3957 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n3872), .Y(n4086) );
INVX2TS U3958 ( .A(n3338), .Y(n1276) );
CLKXOR2X4TS U3959 ( .A(n2385), .B(n1418), .Y(n1514) );
NOR2BX1TS U3960 ( .AN(FPMULT_Op_MX[0]), .B(n1038), .Y(n2831) );
OAI22X2TS U3961 ( .A0(n1135), .A1(n1278), .B0(n1829), .B1(n1038), .Y(n2850)
);
NAND2BX1TS U3962 ( .AN(n1278), .B(n1212), .Y(n1850) );
NOR2BX1TS U3963 ( .AN(FPMULT_Op_MX[0]), .B(n1216), .Y(n1764) );
NOR2BX1TS U3964 ( .AN(n1278), .B(n2319), .Y(n1864) );
NAND2BX1TS U3965 ( .AN(n1278), .B(n1172), .Y(n1739) );
NOR2BX1TS U3966 ( .AN(FPMULT_Op_MX[0]), .B(n1908), .Y(n1841) );
NAND2BX1TS U3967 ( .AN(n1277), .B(n1124), .Y(n1708) );
XNOR2X1TS U3968 ( .A(n1212), .B(n1278), .Y(n1849) );
XNOR2X1TS U3969 ( .A(n1224), .B(n1278), .Y(n1814) );
XNOR2X1TS U3970 ( .A(n1124), .B(n1277), .Y(n1699) );
NOR2BX2TS U3971 ( .AN(FPMULT_Op_MX[0]), .B(n1121), .Y(n1941) );
NAND2BX1TS U3972 ( .AN(n1277), .B(n5047), .Y(n1828) );
AOI221X1TS U3973 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n4838), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n4836), .C0(n4618), .Y(n4620) );
OAI21XLTS U3974 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n5032), .B0(n4786), .Y(n874) );
NOR2X2TS U3975 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n3908), .Y(n3870) );
CLKBUFX3TS U3976 ( .A(n5280), .Y(n3961) );
OAI22X4TS U3977 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(FPADDSUB_LZD_raw_out_EWR[0]),
.B1(n1670), .Y(n4101) );
XNOR2X4TS U3978 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[19]), .Y(n1279) );
OAI2BB1X4TS U3979 ( .A0N(n3622), .A1N(n1300), .B0(n3546), .Y(n3548) );
NAND2X8TS U3980 ( .A(n1280), .B(n1290), .Y(n1300) );
OAI2BB1X4TS U3981 ( .A0N(n3179), .A1N(n3178), .B0(n1281), .Y(n3279) );
OAI21X4TS U3982 ( .A0(n3178), .A1(n3179), .B0(n1283), .Y(n1281) );
XOR2X4TS U3983 ( .A(n1282), .B(n3178), .Y(n3212) );
XOR2X4TS U3984 ( .A(n3179), .B(n1283), .Y(n1282) );
NAND2X4TS U3985 ( .A(n3143), .B(n3142), .Y(n1284) );
OAI21X4TS U3986 ( .A0(n3143), .A1(n3142), .B0(n3141), .Y(n1285) );
XNOR2X4TS U3987 ( .A(n1459), .B(n2972), .Y(n2929) );
NAND2X2TS U3988 ( .A(n1469), .B(n1292), .Y(n1291) );
XOR2X4TS U3989 ( .A(n1294), .B(n3328), .Y(n3329) );
XOR2X4TS U3990 ( .A(n3326), .B(n3327), .Y(n1294) );
NAND3X8TS U3991 ( .A(n1412), .B(n1410), .C(n1411), .Y(n1413) );
NAND2X6TS U3992 ( .A(n1608), .B(n1610), .Y(n1411) );
OAI2BB1X4TS U3993 ( .A0N(n3280), .A1N(n3279), .B0(n1297), .Y(n3365) );
OAI21X2TS U3994 ( .A0(n3279), .A1(n3280), .B0(n1298), .Y(n1297) );
XNOR2X4TS U3995 ( .A(n1299), .B(n1298), .Y(n1296) );
XOR2X4TS U3996 ( .A(n1552), .B(n3235), .Y(n1298) );
XOR2X4TS U3997 ( .A(n3279), .B(n3280), .Y(n1299) );
NOR2X6TS U3998 ( .A(n3426), .B(n3431), .Y(n3372) );
OAI21X4TS U3999 ( .A0(n3366), .A1(n3367), .B0(n3442), .Y(n3428) );
INVX2TS U4000 ( .A(n2711), .Y(n1303) );
XOR2X4TS U4001 ( .A(n3338), .B(n3524), .Y(n3183) );
XOR2X4TS U4002 ( .A(n1305), .B(n2509), .Y(n3524) );
NOR2X8TS U4003 ( .A(n1307), .B(n1306), .Y(n1377) );
XOR2X4TS U4004 ( .A(n3237), .B(n3236), .Y(n1552) );
XOR2X4TS U4005 ( .A(n1308), .B(n2108), .Y(n1574) );
XOR2X4TS U4006 ( .A(n2109), .B(n1309), .Y(n1308) );
XOR2X4TS U4007 ( .A(FPMULT_Op_MY[10]), .B(n1310), .Y(n1631) );
NAND2X8TS U4008 ( .A(n1314), .B(n1311), .Y(n1523) );
NAND2BX4TS U4009 ( .AN(n2467), .B(n1312), .Y(n1687) );
OAI2BB1X4TS U4010 ( .A0N(n1320), .A1N(n1319), .B0(n2479), .Y(n1318) );
XOR2X4TS U4011 ( .A(n2479), .B(n1321), .Y(n2514) );
XOR2X4TS U4012 ( .A(n2480), .B(n1322), .Y(n1321) );
INVX2TS U4013 ( .A(n2490), .Y(n1328) );
INVX2TS U4014 ( .A(n2434), .Y(n1330) );
XNOR2X4TS U4015 ( .A(n2434), .B(n2490), .Y(n1331) );
XOR2X4TS U4016 ( .A(n1333), .B(n3014), .Y(n3025) );
NOR2X8TS U4017 ( .A(n3830), .B(n3796), .Y(n1347) );
AOI21X4TS U4018 ( .A0(n3828), .A1(n1347), .B0(n1336), .Y(n1335) );
OAI21X4TS U4019 ( .A0(n3829), .A1(n3796), .B0(n3797), .Y(n1336) );
OAI21X4TS U4020 ( .A0(n1424), .A1(n3841), .B0(n1420), .Y(n3828) );
INVX6TS U4021 ( .A(n1349), .Y(n2396) );
XNOR2X4TS U4022 ( .A(n1353), .B(n2396), .Y(n1348) );
XNOR2X4TS U4023 ( .A(n1352), .B(n1350), .Y(n1349) );
XNOR2X4TS U4024 ( .A(n2349), .B(n2350), .Y(n1352) );
XOR2X4TS U4025 ( .A(n2255), .B(n2362), .Y(n2349) );
XOR2X4TS U4026 ( .A(n2397), .B(n2398), .Y(n1353) );
NAND2X2TS U4027 ( .A(n2271), .B(n2272), .Y(n1354) );
XOR2X4TS U4028 ( .A(n1459), .B(n957), .Y(n2155) );
XOR2X2TS U4029 ( .A(n1459), .B(n1579), .Y(n1975) );
XOR2X4TS U4030 ( .A(n1972), .B(n1932), .Y(n1459) );
XOR2X4TS U4031 ( .A(n2227), .B(n1356), .Y(n2285) );
NAND2X8TS U4032 ( .A(n1415), .B(n1414), .Y(n1546) );
OAI22X4TS U4033 ( .A0(n1598), .A1(n2474), .B0(n3133), .B1(n2600), .Y(n2647)
);
XNOR2X2TS U4034 ( .A(n2968), .B(n950), .Y(n2600) );
XNOR2X4TS U4035 ( .A(n2712), .B(n2383), .Y(n2968) );
XOR2X4TS U4036 ( .A(n1358), .B(n2278), .Y(n3312) );
AOI21X4TS U4037 ( .A0(n2276), .A1(n1413), .B0(n2275), .Y(n1358) );
NAND2BX4TS U4038 ( .AN(n2873), .B(n1359), .Y(n1414) );
NAND2X4TS U4039 ( .A(n2748), .B(n2749), .Y(n2871) );
NOR2X8TS U4040 ( .A(n2748), .B(n2749), .Y(n2873) );
XOR2X4TS U4041 ( .A(n1367), .B(n1362), .Y(n2657) );
XOR2X4TS U4042 ( .A(n2598), .B(n2599), .Y(n1362) );
NAND2X4TS U4043 ( .A(n2598), .B(n1365), .Y(n1364) );
NAND2X4TS U4044 ( .A(n946), .B(n1369), .Y(n1368) );
OAI22X4TS U4045 ( .A0(n2449), .A1(n3516), .B0(n1221), .B1(n2521), .Y(n2493)
);
OAI22X4TS U4046 ( .A0(n3340), .A1(n2450), .B0(n1592), .B1(n3339), .Y(n1524)
);
NAND3X8TS U4047 ( .A(n1074), .B(n1372), .C(n1371), .Y(n1447) );
NAND3X8TS U4048 ( .A(n1596), .B(n1546), .C(n3158), .Y(n1372) );
NAND2X4TS U4049 ( .A(n1935), .B(n1374), .Y(n1609) );
NAND2X2TS U4050 ( .A(n1405), .B(n1394), .Y(n1406) );
NOR2X2TS U4051 ( .A(n1937), .B(n1374), .Y(n1402) );
NOR2X8TS U4052 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[1]), .Y(n1374) );
OAI21X4TS U4053 ( .A0(n1607), .A1(n1062), .B0(n1376), .Y(n1375) );
AOI21X2TS U4054 ( .A0(n1295), .A1(n1377), .B0(n2376), .Y(n1376) );
OAI2BB1X4TS U4055 ( .A0N(n3006), .A1N(n3005), .B0(n1378), .Y(n3064) );
OAI21X4TS U4056 ( .A0(n3006), .A1(n3005), .B0(n1379), .Y(n1378) );
NOR2X8TS U4057 ( .A(n1079), .B(n1634), .Y(n3632) );
OR2X8TS U4058 ( .A(n3029), .B(n3028), .Y(n1384) );
OAI2BB1X4TS U4059 ( .A0N(n2391), .A1N(n1387), .B0(n1385), .Y(n2409) );
OAI21X2TS U4060 ( .A0(n1387), .A1(n2391), .B0(n2390), .Y(n1385) );
XNOR2X4TS U4061 ( .A(n1386), .B(n2390), .Y(n2394) );
XNOR2X4TS U4062 ( .A(n1387), .B(n2391), .Y(n1386) );
XOR2X4TS U4063 ( .A(n2968), .B(n3338), .Y(n3070) );
XNOR2X4TS U4064 ( .A(n1470), .B(n1514), .Y(n2734) );
AOI21X4TS U4065 ( .A0(n2382), .A1(n2381), .B0(n2380), .Y(n1389) );
XNOR2X4TS U4066 ( .A(n1554), .B(n1974), .Y(n1556) );
XNOR2X4TS U4067 ( .A(n1392), .B(n3143), .Y(n3146) );
CLKXOR2X4TS U4068 ( .A(n1393), .B(n1937), .Y(n2930) );
XNOR2X4TS U4069 ( .A(n1395), .B(n3217), .Y(n3231) );
XOR2X4TS U4070 ( .A(n3263), .B(n3262), .Y(n3186) );
XNOR2X4TS U4071 ( .A(n1400), .B(FPMULT_Op_MX[11]), .Y(n1399) );
AOI21X4TS U4072 ( .A0(n2712), .A1(n1640), .B0(n2603), .Y(n1400) );
XNOR2X4TS U4073 ( .A(n3006), .B(n3005), .Y(n2913) );
XNOR2X4TS U4074 ( .A(n2720), .B(n2886), .Y(n1570) );
OAI21X4TS U4075 ( .A0(n1937), .A1(n1406), .B0(n1403), .Y(n1442) );
AOI2BB2X4TS U4076 ( .B0(n1407), .B1(n1412), .A0N(n2149), .A1N(n2148), .Y(
n1473) );
NAND2X8TS U4077 ( .A(n1523), .B(n1416), .Y(n1415) );
XNOR2X1TS U4078 ( .A(n2259), .B(n1418), .Y(n2260) );
XNOR2X4TS U4079 ( .A(n5222), .B(FPMULT_Op_MY[7]), .Y(n1418) );
AOI21X4TS U4080 ( .A0(n1429), .A1(n1426), .B0(n1423), .Y(n1422) );
XNOR2X4TS U4081 ( .A(n1439), .B(n3086), .Y(n3225) );
OAI22X4TS U4082 ( .A0(n1064), .A1(n2386), .B0(n2407), .B1(n3268), .Y(n2405)
);
XOR2X4TS U4083 ( .A(n1442), .B(n1083), .Y(n3071) );
AND2X8TS U4084 ( .A(n1444), .B(n1443), .Y(n2570) );
XOR2X4TS U4085 ( .A(n1446), .B(n2461), .Y(n1444) );
XNOR2X4TS U4086 ( .A(n2464), .B(n2460), .Y(n1446) );
XOR2X4TS U4087 ( .A(n2169), .B(n1450), .Y(n1455) );
NAND2X4TS U4088 ( .A(n1455), .B(n1454), .Y(n1683) );
NAND2X6TS U4089 ( .A(n1539), .B(n1682), .Y(n1458) );
AOI21X4TS U4090 ( .A0(n1541), .A1(n2073), .B0(n1457), .Y(n1456) );
XOR2X4TS U4091 ( .A(n1460), .B(n1465), .Y(n2171) );
XOR2X4TS U4092 ( .A(n2164), .B(n1461), .Y(n1460) );
OAI2BB1X4TS U4093 ( .A0N(n1465), .A1N(n1461), .B0(n2164), .Y(n1464) );
NOR2X8TS U4094 ( .A(n2523), .B(n2522), .Y(n1468) );
BUFX6TS U4095 ( .A(n3270), .Y(n1469) );
BUFX6TS U4096 ( .A(n3172), .Y(n1470) );
XNOR2X4TS U4097 ( .A(n1471), .B(n2202), .Y(n3270) );
XNOR2X4TS U4098 ( .A(n1473), .B(n2151), .Y(n3172) );
XNOR2X4TS U4099 ( .A(n946), .B(n1474), .Y(n2499) );
XOR2X4TS U4100 ( .A(n2492), .B(n2493), .Y(n1474) );
NOR2X8TS U4101 ( .A(n3092), .B(n3160), .Y(n1596) );
INVX2TS U4102 ( .A(n2647), .Y(n2650) );
XNOR2X4TS U4103 ( .A(n2647), .B(n2648), .Y(n1476) );
XNOR2X4TS U4104 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[21]), .Y(n1483) );
NOR2X8TS U4105 ( .A(n3368), .B(n3369), .Y(n3426) );
NOR2X8TS U4106 ( .A(n3370), .B(n3371), .Y(n3431) );
XOR2X4TS U4107 ( .A(n1484), .B(n1086), .Y(n3681) );
AOI21X4TS U4108 ( .A0(n3627), .A1(n1646), .B0(n1648), .Y(n1486) );
XOR2X4TS U4109 ( .A(n3701), .B(n1490), .Y(n3399) );
XOR2X4TS U4110 ( .A(n3388), .B(n1491), .Y(n1490) );
NOR2X8TS U4111 ( .A(n2957), .B(FPMULT_Op_MX[22]), .Y(n2627) );
OAI21X4TS U4112 ( .A0(n1493), .A1(n1497), .B0(n1492), .Y(n3121) );
XOR2X4TS U4113 ( .A(n1498), .B(n1495), .Y(n1497) );
XOR2X4TS U4114 ( .A(n1496), .B(n1494), .Y(n3065) );
XOR2X4TS U4115 ( .A(n3067), .B(n3068), .Y(n1496) );
XOR2X4TS U4116 ( .A(n5061), .B(FPMULT_Op_MX[21]), .Y(n2419) );
XOR2X4TS U4117 ( .A(n1504), .B(n2744), .Y(n2747) );
XOR2X4TS U4118 ( .A(n2743), .B(n2742), .Y(n1504) );
XOR2X4TS U4119 ( .A(n1505), .B(n3470), .Y(n2742) );
XOR2X4TS U4120 ( .A(n2741), .B(n2632), .Y(n1505) );
XNOR2X4TS U4121 ( .A(n1506), .B(n2700), .Y(n1619) );
XOR2X4TS U4122 ( .A(n2702), .B(n2701), .Y(n1506) );
XOR2X4TS U4123 ( .A(n1507), .B(n2690), .Y(n2735) );
XOR2X4TS U4124 ( .A(n2691), .B(n1619), .Y(n1507) );
NAND2X8TS U4125 ( .A(n3216), .B(n3215), .Y(n3366) );
NOR2X8TS U4126 ( .A(n3364), .B(n3365), .Y(n3367) );
OAI2BB1X4TS U4127 ( .A0N(n1519), .A1N(n1518), .B0(n2657), .Y(n1517) );
XOR2X4TS U4128 ( .A(n2657), .B(n1520), .Y(n2597) );
XOR2X4TS U4129 ( .A(n2658), .B(n1515), .Y(n1520) );
OAI21X4TS U4130 ( .A0(n2504), .A1(n2503), .B0(n2501), .Y(n2502) );
XOR2X4TS U4131 ( .A(n1581), .B(n1583), .Y(n2413) );
XNOR2X2TS U4132 ( .A(n3131), .B(n1217), .Y(n2251) );
XOR2X4TS U4133 ( .A(n1530), .B(n1528), .Y(n1527) );
XOR2X4TS U4134 ( .A(n1529), .B(n2443), .Y(n1528) );
XOR2X4TS U4135 ( .A(n1531), .B(n2573), .Y(n2344) );
XOR2X4TS U4136 ( .A(n1536), .B(n1534), .Y(n1532) );
XNOR2X4TS U4137 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[5]), .Y(n2225) );
XNOR2X4TS U4138 ( .A(n2574), .B(n2575), .Y(n1537) );
XOR2X4TS U4139 ( .A(n1544), .B(n2066), .Y(n1989) );
XOR2X4TS U4140 ( .A(n1542), .B(n1576), .Y(n2066) );
INVX2TS U4141 ( .A(n2037), .Y(n1543) );
NOR2X4TS U4142 ( .A(n1545), .B(n3675), .Y(n3814) );
XNOR2X4TS U4143 ( .A(n1602), .B(n3538), .Y(n1545) );
NOR2X8TS U4144 ( .A(n3029), .B(n3026), .Y(n3158) );
OAI21X4TS U4145 ( .A0(n3514), .A1(n1039), .B0(n1549), .Y(n1548) );
OAI2BB1X4TS U4146 ( .A0N(n3237), .A1N(n3236), .B0(n1551), .Y(n3324) );
OAI21X4TS U4147 ( .A0(n3236), .A1(n3237), .B0(n3235), .Y(n1551) );
XNOR2X4TS U4148 ( .A(n2519), .B(n2520), .Y(n1553) );
OAI22X4TS U4149 ( .A0(n1557), .A1(n1555), .B0(n1554), .B1(n1208), .Y(n3136)
);
XNOR2X4TS U4150 ( .A(n1557), .B(n1556), .Y(n3031) );
AOI2BB2X4TS U4151 ( .B0(n2973), .B1(n1553), .A0N(n2974), .A1N(n1041), .Y(
n1557) );
XOR2X4TS U4152 ( .A(n3163), .B(n1558), .Y(n3180) );
XOR2X4TS U4153 ( .A(n3164), .B(n3490), .Y(n1558) );
XNOR2X4TS U4154 ( .A(n1559), .B(n2927), .Y(n2908) );
XNOR2X4TS U4155 ( .A(n1565), .B(n2928), .Y(n1559) );
NAND2X2TS U4156 ( .A(n1565), .B(n2928), .Y(n1562) );
OAI21X4TS U4157 ( .A0(n2935), .A1(n2936), .B0(n1570), .Y(n2938) );
XOR2X4TS U4158 ( .A(n1572), .B(n1571), .Y(n3227) );
NOR2BX1TS U4159 ( .AN(n3159), .B(n3160), .Y(n1571) );
NAND2BX4TS U4160 ( .AN(n1631), .B(n1148), .Y(n2122) );
XOR2X4TS U4161 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[10]), .Y(n1697) );
INVX2TS U4162 ( .A(n2036), .Y(n1576) );
XNOR2X4TS U4163 ( .A(n1944), .B(n1580), .Y(n1579) );
XOR2X4TS U4164 ( .A(n3338), .B(n1459), .Y(n2450) );
XOR2X4TS U4165 ( .A(n3338), .B(n2930), .Y(n2387) );
OAI2BB1X4TS U4166 ( .A0N(n2406), .A1N(n2405), .B0(n1582), .Y(n2512) );
XOR2X4TS U4167 ( .A(n1584), .B(n2225), .Y(n3267) );
OR2X4TS U4168 ( .A(n3310), .B(n2969), .Y(n1588) );
OAI2BB1X4TS U4169 ( .A0N(n2744), .A1N(n2743), .B0(n1589), .Y(n2914) );
OAI21X4TS U4170 ( .A0(n2743), .A1(n2744), .B0(n2742), .Y(n1589) );
OAI2BB1X4TS U4171 ( .A0N(n2607), .A1N(n2606), .B0(n1590), .Y(n2705) );
OAI21X4TS U4172 ( .A0(n2606), .A1(n2607), .B0(n2605), .Y(n1590) );
XNOR2X4TS U4173 ( .A(n1591), .B(n2605), .Y(n2654) );
XNOR2X4TS U4174 ( .A(n1947), .B(n1948), .Y(n1597) );
NOR2BX4TS U4175 ( .AN(n2419), .B(n1600), .Y(n1599) );
NAND2X4TS U4176 ( .A(n3147), .B(n3148), .Y(n3159) );
OAI2BB1X4TS U4177 ( .A0N(n2110), .A1N(n2108), .B0(n1601), .Y(n3265) );
OAI21X2TS U4178 ( .A0(n2108), .A1(n2110), .B0(n2109), .Y(n1601) );
NAND2X4TS U4179 ( .A(n1611), .B(n3164), .Y(n3161) );
NAND2X4TS U4180 ( .A(n2396), .B(n1613), .Y(n1612) );
NAND2X4TS U4181 ( .A(n2350), .B(n1351), .Y(n1616) );
XNOR2X4TS U4182 ( .A(n2065), .B(n2064), .Y(n1617) );
XOR2X4TS U4183 ( .A(n1459), .B(n3267), .Y(n2256) );
OAI21X2TS U4184 ( .A0(n2690), .A1(n2691), .B0(n1619), .Y(n1618) );
NOR2X1TS U4185 ( .A(n1728), .B(n958), .Y(n1710) );
AOI21X1TS U4186 ( .A0(n970), .A1(n3833), .B0(n3832), .Y(add_x_69_n134) );
OAI22X2TS U4187 ( .A0(n3130), .A1(n3339), .B0(n3070), .B1(n3310), .Y(n3126)
);
AO21X1TS U4188 ( .A0(n2541), .A1(n1150), .B0(n1641), .Y(n2557) );
OAI22X1TS U4189 ( .A0(n2322), .A1(n2321), .B0(n1150), .B1(n2532), .Y(n2529)
);
OAI22X1TS U4190 ( .A0(n2541), .A1(n2121), .B0(n1150), .B1(n2298), .Y(n2293)
);
OAI22X1TS U4191 ( .A0(n2322), .A1(n2087), .B0(n958), .B1(n2121), .Y(n2113)
);
OAI22X1TS U4192 ( .A0(n2322), .A1(n1913), .B0(n1150), .B1(n2087), .Y(n2083)
);
OAI22X2TS U4193 ( .A0(n2322), .A1(n1785), .B0(n1150), .B1(n1913), .Y(n1906)
);
OAI22X2TS U4194 ( .A0(n2322), .A1(n1765), .B0(n958), .B1(n1785), .Y(n1793)
);
NOR2BX1TS U4195 ( .AN(n1278), .B(n958), .Y(n1846) );
OAI22X1TS U4196 ( .A0(n2322), .A1(n1735), .B0(n958), .B1(n1734), .Y(n1752)
);
OAI22X2TS U4197 ( .A0(n2322), .A1(n1728), .B0(n958), .B1(n1765), .Y(n1776)
);
OAI22X2TS U4198 ( .A0(n2322), .A1(n1734), .B0(n958), .B1(n1709), .Y(n1747)
);
OAI22X2TS U4199 ( .A0(n3337), .A1(n3516), .B0(n3397), .B1(n1221), .Y(n3400)
);
OAI22X2TS U4200 ( .A0(n2970), .A1(n3515), .B0(n2881), .B1(n3516), .Y(n2966)
);
OAI22X2TS U4201 ( .A0(n1401), .A1(n3515), .B0(n1039), .B1(n2643), .Y(n2715)
);
OAI22X1TS U4202 ( .A0(n2679), .A1(n2542), .B0(n1149), .B1(n2558), .Y(n2559)
);
OAI22X1TS U4203 ( .A0(n2679), .A1(n2533), .B0(n1149), .B1(n2542), .Y(n2543)
);
OAI22X1TS U4204 ( .A0(n2122), .A1(n1786), .B0(n1149), .B1(n1912), .Y(n1905)
);
OAI22X2TS U4205 ( .A0(n2122), .A1(n1727), .B0(n1149), .B1(n1778), .Y(n1773)
);
NOR2BX1TS U4206 ( .AN(n1278), .B(n1148), .Y(n1743) );
ADDFHX4TS U4207 ( .A(n3098), .B(n3097), .CI(n3096), .CO(n3210), .S(n3141) );
OR2X2TS U4208 ( .A(n3396), .B(n3386), .Y(n1625) );
OR2X2TS U4209 ( .A(n1979), .B(n3087), .Y(n1627) );
CLKAND2X2TS U4210 ( .A(n1642), .B(n4029), .Y(n1628) );
OA21X4TS U4211 ( .A0(n2331), .A1(n2336), .B0(n2337), .Y(n1630) );
AO21X1TS U4212 ( .A0(n2711), .A1(n2710), .B0(n2709), .Y(n1634) );
INVX2TS U4213 ( .A(n2850), .Y(n1949) );
AND2X2TS U4214 ( .A(n2601), .B(n2710), .Y(n1640) );
OR2X1TS U4215 ( .A(n2851), .B(n2850), .Y(n1642) );
OA22X2TS U4216 ( .A0(n1135), .A1(n1860), .B0(n1859), .B1(n1146), .Y(n1654)
);
XNOR2X1TS U4217 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[19]), .Y(n1663) );
INVX2TS U4218 ( .A(FPMULT_FS_Module_state_reg[2]), .Y(n3934) );
INVX2TS U4219 ( .A(n2154), .Y(n2189) );
INVX6TS U4220 ( .A(n2896), .Y(n1976) );
OR2X4TS U4221 ( .A(n1955), .B(n1954), .Y(n1674) );
XNOR2X1TS U4222 ( .A(n3806), .B(n3748), .Y(n1679) );
OR2X8TS U4223 ( .A(n3577), .B(n3576), .Y(n1686) );
OR2X4TS U4224 ( .A(n2389), .B(n2438), .Y(n1688) );
NOR2X4TS U4225 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[4]), .Y(n2197) );
NOR2X1TS U4226 ( .A(n2273), .B(n2374), .Y(n2276) );
NAND2X2TS U4227 ( .A(n2040), .B(n2039), .Y(n2044) );
NAND2X1TS U4228 ( .A(n1635), .B(n2708), .Y(n2709) );
XNOR2X2TS U4229 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MX[5]), .Y(n1706) );
OAI22X1TS U4230 ( .A0(n2392), .A1(n1057), .B0(n2418), .B1(n1220), .Y(n2408)
);
NAND2BX1TS U4231 ( .AN(n1173), .B(n2972), .Y(n2641) );
OAI22X1TS U4232 ( .A0(n1204), .A1(n1787), .B0(n2124), .B1(n1910), .Y(n1904)
);
INVX2TS U4233 ( .A(n2404), .Y(n2513) );
INVX2TS U4234 ( .A(n3016), .Y(n1962) );
XNOR2X2TS U4235 ( .A(n1160), .B(n5037), .Y(n2430) );
INVX2TS U4236 ( .A(n3396), .Y(n3531) );
XNOR2X2TS U4237 ( .A(n1169), .B(n5049), .Y(n2953) );
XNOR2X1TS U4238 ( .A(n5060), .B(FPMULT_Op_MY[12]), .Y(n2242) );
XNOR2X2TS U4239 ( .A(n1159), .B(n3112), .Y(n2213) );
INVX2TS U4240 ( .A(n2332), .Y(n2125) );
XNOR2X1TS U4241 ( .A(FPMULT_Op_MY[9]), .B(n1277), .Y(n1735) );
OAI22X1TS U4242 ( .A0(n2623), .A1(n2366), .B0(n2422), .B1(n1040), .Y(n2431)
);
XNOR2X1TS U4243 ( .A(n1170), .B(n1277), .Y(n1834) );
INVX2TS U4244 ( .A(n2336), .Y(n2338) );
NOR2X4TS U4245 ( .A(n3198), .B(n3197), .Y(n3242) );
NAND2X1TS U4246 ( .A(n2338), .B(n2337), .Y(n2339) );
INVX2TS U4247 ( .A(n3735), .Y(n3705) );
CLKXOR2X2TS U4248 ( .A(n2324), .B(n2323), .Y(n2343) );
NOR2X2TS U4249 ( .A(n4021), .B(n4019), .Y(n1898) );
INVX2TS U4250 ( .A(n2018), .Y(n2020) );
NAND2X4TS U4251 ( .A(n3012), .B(n3011), .Y(n3027) );
NAND2X1TS U4252 ( .A(n1627), .B(n3152), .Y(n3091) );
INVX2TS U4253 ( .A(n3583), .Y(n3585) );
NAND2X1TS U4254 ( .A(n3582), .B(n3580), .Y(n3541) );
INVX2TS U4255 ( .A(n3731), .Y(n3698) );
NOR2X2TS U4256 ( .A(n3427), .B(n3426), .Y(n3430) );
NOR2X1TS U4257 ( .A(n5100), .B(FPADDSUB_DMP_SFG[10]), .Y(n4390) );
AOI21X1TS U4258 ( .A0(n3656), .A1(n3582), .B0(n3581), .Y(n3587) );
OAI21X1TS U4259 ( .A0(n3741), .A1(n3725), .B0(n3726), .Y(n3716) );
AOI31XLTS U4260 ( .A0(n4804), .A1(n4803), .A2(n4802), .B0(n4809), .Y(n4807)
);
INVX2TS U4261 ( .A(n4026), .Y(n4028) );
NAND2X1TS U4262 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n4535) );
INVX2TS U4263 ( .A(n4548), .Y(n4550) );
NAND2X1TS U4264 ( .A(n3491), .B(n3690), .Y(n3492) );
OAI21X2TS U4265 ( .A0(n4418), .A1(n4417), .B0(n4416), .Y(n4532) );
XNOR2X1TS U4266 ( .A(n2768), .B(n2767), .Y(n2775) );
INVX2TS U4267 ( .A(n3858), .Y(n3854) );
OAI21X2TS U4268 ( .A0(n4448), .A1(n4445), .B0(n4446), .Y(n4439) );
OAI21X2TS U4269 ( .A0(n4524), .A1(n4422), .B0(n4421), .Y(n4515) );
XOR2X1TS U4270 ( .A(n4030), .B(n4029), .Y(n4031) );
AOI21X1TS U4271 ( .A0(n1063), .A1(n3859), .B0(n3854), .Y(n3857) );
ADDHXLTS U4272 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n3779), .CO(n2860),
.S(FPMULT_Adder_M_result_A_adder[11]) );
OAI211XLTS U4273 ( .A0(n3967), .A1(n3925), .B0(n3920), .C0(n4788), .Y(n855)
);
XNOR2X4TS U4274 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[3]), .Y(n1908) );
INVX2TS U4275 ( .A(n1727), .Y(n1698) );
INVX2TS U4276 ( .A(n1707), .Y(n1702) );
OR2X8TS U4277 ( .A(n1647), .B(n1621), .Y(n2322) );
XNOR2X2TS U4278 ( .A(n1172), .B(FPMULT_Op_MX[1]), .Y(n1734) );
XOR2X4TS U4279 ( .A(n1729), .B(n1776), .Y(n1797) );
INVX2TS U4280 ( .A(n1737), .Y(n1738) );
INVX2TS U4281 ( .A(n1739), .Y(n1740) );
ADDFHX4TS U4282 ( .A(n1746), .B(n1745), .CI(n1744), .CO(n1807), .S(n1759) );
NOR2X6TS U4283 ( .A(n2884), .B(n2686), .Y(n2018) );
ADDFHX4TS U4284 ( .A(n1761), .B(n1760), .CI(n1759), .CO(n2686), .S(n2632) );
NAND2X2TS U4285 ( .A(n2686), .B(n2884), .Y(n2019) );
OAI21X4TS U4286 ( .A0(n2018), .A1(n2758), .B0(n2019), .Y(n1994) );
INVX2TS U4287 ( .A(n1794), .Y(n1770) );
OAI2BB1X4TS U4288 ( .A0N(n1770), .A1N(n1769), .B0(n1796), .Y(n1772) );
OAI21X1TS U4289 ( .A0(n1776), .A1(n1775), .B0(n1773), .Y(n1774) );
XNOR2X4TS U4290 ( .A(n1124), .B(FPMULT_Op_MX[4]), .Y(n1912) );
XOR2X4TS U4291 ( .A(n1924), .B(n1923), .Y(n1792) );
INVX2TS U4292 ( .A(n1917), .Y(n1788) );
OAI2BB2X4TS U4293 ( .B0(n1037), .B1(n1789), .A0N(n1703), .A1N(n1788), .Y(
n1914) );
XOR2X4TS U4294 ( .A(n1792), .B(n1920), .Y(n1927) );
XOR2X4TS U4295 ( .A(n1794), .B(n1793), .Y(n1795) );
XOR2X4TS U4296 ( .A(n1796), .B(n1795), .Y(n1805) );
ADDFHX4TS U4297 ( .A(n1802), .B(n1801), .CI(n1800), .CO(n1928), .S(n1803) );
ADDFHX4TS U4298 ( .A(n1805), .B(n1804), .CI(n1803), .CO(n2961), .S(n2883) );
ADDFHX4TS U4299 ( .A(n1808), .B(n1807), .CI(n1806), .CO(n2926), .S(n2884) );
NOR2X8TS U4300 ( .A(n2883), .B(n1809), .Y(n2009) );
NOR2X8TS U4301 ( .A(n1999), .B(n2009), .Y(n1811) );
NAND2X4TS U4302 ( .A(n2883), .B(n1809), .Y(n1995) );
AOI21X4TS U4303 ( .A0(n1994), .A1(n1811), .B0(n1810), .Y(n1901) );
NAND2X4TS U4304 ( .A(n1811), .B(n1992), .Y(n1899) );
INVX2TS U4305 ( .A(n1812), .Y(n1813) );
OAI22X2TS U4306 ( .A0(n1136), .A1(n1815), .B0(n1860), .B1(n1038), .Y(n1863)
);
INVX2TS U4307 ( .A(n1851), .Y(n1816) );
XNOR2X2TS U4308 ( .A(n1171), .B(FPMULT_Op_MX[2]), .Y(n1826) );
INVX2TS U4309 ( .A(n1817), .Y(n1818) );
NOR2X4TS U4310 ( .A(n2216), .B(n2193), .Y(n2769) );
ADDFHX4TS U4311 ( .A(n1824), .B(n1823), .CI(n1822), .CO(n2193), .S(n2154) );
OAI22X2TS U4312 ( .A0(n1135), .A1(n1830), .B0(n1825), .B1(n1146), .Y(n1840)
);
INVX2TS U4313 ( .A(n1826), .Y(n1827) );
NAND2X1TS U4314 ( .A(n1828), .B(n1135), .Y(n2851) );
OAI21X4TS U4315 ( .A0(n4026), .A1(n4029), .B0(n4027), .Y(n2829) );
INVX2TS U4316 ( .A(n1832), .Y(n1833) );
NAND2X2TS U4317 ( .A(n1959), .B(n1983), .Y(n2828) );
INVX2TS U4318 ( .A(n2828), .Y(n1836) );
AOI21X4TS U4319 ( .A0(n2829), .A1(n1629), .B0(n1836), .Y(n2848) );
OAI21X4TS U4320 ( .A0(n2848), .A1(n2845), .B0(n2846), .Y(n2823) );
NAND2X2TS U4321 ( .A(n2216), .B(n2193), .Y(n2770) );
AOI21X4TS U4322 ( .A0(n1843), .A1(n2823), .B0(n1842), .Y(n2765) );
INVX2TS U4323 ( .A(n1847), .Y(n1848) );
NOR2X2TS U4324 ( .A(n1861), .B(n1654), .Y(n1882) );
XOR2X4TS U4325 ( .A(n1861), .B(n1654), .Y(n1870) );
ADDFHX4TS U4326 ( .A(n1870), .B(n1869), .CI(n1868), .CO(n2438), .S(n2264) );
ADDFHX4TS U4327 ( .A(n1873), .B(n1872), .CI(n1871), .CO(n2281), .S(n2216) );
NAND2X2TS U4328 ( .A(n1688), .B(n2799), .Y(n1878) );
NAND2X2TS U4329 ( .A(n2264), .B(n2281), .Y(n2766) );
INVX2TS U4330 ( .A(n2766), .Y(n1876) );
NAND2X2TS U4331 ( .A(n2389), .B(n2438), .Y(n2800) );
INVX2TS U4332 ( .A(n2800), .Y(n1875) );
AOI21X4TS U4333 ( .A0(n1688), .A1(n1876), .B0(n1875), .Y(n1877) );
OAI21X4TS U4334 ( .A0(n2765), .A1(n1878), .B0(n1877), .Y(n2762) );
ADDFHX4TS U4335 ( .A(n1890), .B(n1889), .CI(n1888), .CO(n2733), .S(n2494) );
NOR2X8TS U4336 ( .A(n2491), .B(n2494), .Y(n4021) );
ADDFHX4TS U4337 ( .A(n1893), .B(n1892), .CI(n1891), .CO(n2491), .S(n2434) );
ADDFHX4TS U4338 ( .A(n1896), .B(n1895), .CI(n1894), .CO(n2404), .S(n2389) );
NOR2X4TS U4339 ( .A(n2434), .B(n2404), .Y(n4019) );
OAI21X4TS U4340 ( .A0(n4021), .A1(n4018), .B0(n4022), .Y(n1897) );
AOI21X4TS U4341 ( .A0(n2762), .A1(n1898), .B0(n1897), .Y(n1991) );
INVX2TS U4342 ( .A(n2098), .Y(n1909) );
XNOR2X4TS U4343 ( .A(n1124), .B(FPMULT_Op_MX[5]), .Y(n2088) );
INVX2TS U4344 ( .A(n2097), .Y(n1918) );
AOI2BB2X4TS U4345 ( .B0(n1918), .B1(n1703), .A0N(n1037), .A1N(n1917), .Y(
n2093) );
INVX2TS U4346 ( .A(n1923), .Y(n1922) );
ADDFHX4TS U4347 ( .A(n1929), .B(n1928), .CI(n1927), .CO(n3054), .S(n2976) );
NOR2X4TS U4348 ( .A(n3055), .B(n3054), .Y(n2104) );
XOR2X4TS U4349 ( .A(n2103), .B(n1653), .Y(n2031) );
INVX2TS U4350 ( .A(n3022), .Y(n1961) );
INVX2TS U4351 ( .A(n1931), .Y(n1960) );
INVX2TS U4352 ( .A(n3021), .Y(n1943) );
INVX2TS U4353 ( .A(n2851), .Y(n1942) );
OAI21X2TS U4354 ( .A0(n1950), .A1(n1949), .B0(n1952), .Y(n1940) );
NAND2X2TS U4355 ( .A(n1940), .B(n1939), .Y(n1985) );
INVX2TS U4356 ( .A(n1941), .Y(n1981) );
XNOR2X4TS U4357 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[14]), .Y(n2896) );
INVX2TS U4358 ( .A(n1944), .Y(n1945) );
XOR2X4TS U4359 ( .A(n1950), .B(n2850), .Y(n1951) );
XNOR2X4TS U4360 ( .A(n1952), .B(n1951), .Y(n1955) );
NAND2X1TS U4361 ( .A(n1953), .B(n1141), .Y(n1954) );
INVX2TS U4362 ( .A(n2831), .Y(n2025) );
INVX2TS U4363 ( .A(n2753), .Y(n2024) );
INVX2TS U4364 ( .A(n2013), .Y(n1956) );
NAND2X4TS U4365 ( .A(n1958), .B(n1957), .Y(n2005) );
OAI21X4TS U4366 ( .A0(n2004), .A1(n2007), .B0(n2005), .Y(n2074) );
INVX2TS U4367 ( .A(n1959), .Y(n2059) );
OAI22X2TS U4368 ( .A0(n1057), .A1(n957), .B0(n3133), .B1(n1971), .Y(n2037)
);
NOR2X8TS U4369 ( .A(n5055), .B(FPMULT_Op_MX[3]), .Y(n2048) );
INVX2TS U4370 ( .A(n2048), .Y(n1973) );
INVX2TS U4371 ( .A(n3087), .Y(n2055) );
INVX2TS U4372 ( .A(n1983), .Y(n2054) );
XOR2X4TS U4373 ( .A(n1984), .B(n2040), .Y(n2036) );
NAND2X4TS U4374 ( .A(n1989), .B(n1988), .Y(n2072) );
NAND2X2TS U4375 ( .A(n2072), .B(n1682), .Y(n1990) );
XNOR2X4TS U4376 ( .A(n2074), .B(n1990), .Y(n2030) );
INVX2TS U4377 ( .A(n1999), .Y(n2001) );
XOR2X4TS U4378 ( .A(n2003), .B(n2002), .Y(n2029) );
INVX2TS U4379 ( .A(n2004), .Y(n2006) );
NOR2X4TS U4380 ( .A(n2029), .B(n2028), .Y(n4009) );
AOI21X4TS U4381 ( .A0(n2761), .A1(n1992), .B0(n1994), .Y(n2012) );
XOR2X4TS U4382 ( .A(n2012), .B(n2011), .Y(n2027) );
NOR2X2TS U4383 ( .A(n2027), .B(n2026), .Y(n2791) );
INVX2TS U4384 ( .A(n2016), .Y(n2759) );
AOI21X4TS U4385 ( .A0(n2761), .A1(n2759), .B0(n2017), .Y(n2022) );
CLKXOR2X4TS U4386 ( .A(n2022), .B(n2021), .Y(n4015) );
CMPR32X2TS U4387 ( .A(n2025), .B(n2024), .C(n2023), .CO(n2014), .S(n4014) );
NAND2X2TS U4388 ( .A(n4015), .B(n4014), .Y(n4016) );
NAND2X1TS U4389 ( .A(n2027), .B(n2026), .Y(n2792) );
OAI21X2TS U4390 ( .A0(n2791), .A1(n4016), .B0(n2792), .Y(n2785) );
NAND2X2TS U4391 ( .A(n2029), .B(n2028), .Y(n4010) );
NAND2X1TS U4392 ( .A(n2031), .B(n2030), .Y(n2787) );
OAI21X2TS U4393 ( .A0(n2786), .A1(n4010), .B0(n2787), .Y(n2032) );
AOI21X4TS U4394 ( .A0(n2033), .A1(n2785), .B0(n2032), .Y(n2780) );
NAND2BX4TS U4395 ( .AN(n2042), .B(n1979), .Y(n2039) );
INVX2TS U4396 ( .A(n3149), .Y(n2160) );
INVX2TS U4397 ( .A(n2056), .Y(n2158) );
ADDFHX4TS U4398 ( .A(n2059), .B(n2058), .CI(n2057), .CO(n2167), .S(n2068) );
INVX2TS U4399 ( .A(n3150), .Y(n2163) );
OAI21X2TS U4400 ( .A0(n2068), .A1(n2069), .B0(n2066), .Y(n2067) );
OAI2BB1X4TS U4401 ( .A0N(n2069), .A1N(n2068), .B0(n2067), .Y(n2070) );
NOR2X6TS U4402 ( .A(n2071), .B(n2070), .Y(n2129) );
NAND2X4TS U4403 ( .A(n2071), .B(n2070), .Y(n2128) );
ADDFHX4TS U4404 ( .A(n2080), .B(n2079), .CI(n2078), .CO(n3099), .S(n3055) );
ADDFHX4TS U4405 ( .A(n2086), .B(n2085), .CI(n2084), .CO(n2109), .S(n2079) );
INVX2TS U4406 ( .A(n2102), .Y(n2781) );
OAI21X4TS U4407 ( .A0(n2107), .A1(n2106), .B0(n2105), .Y(n2330) );
ADDFHX4TS U4408 ( .A(n2116), .B(n2115), .CI(n2114), .CO(n2304), .S(n2108) );
XOR2X4TS U4409 ( .A(n2127), .B(n2126), .Y(n2178) );
XOR2X4TS U4410 ( .A(n2219), .B(n2147), .Y(n3222) );
INVX2TS U4411 ( .A(n3222), .Y(n2207) );
NOR2X8TS U4412 ( .A(n1168), .B(FPMULT_Op_MX[5]), .Y(n2200) );
INVX2TS U4413 ( .A(n2200), .Y(n2150) );
XNOR2X4TS U4414 ( .A(n2187), .B(n2185), .Y(n2157) );
XOR2X4TS U4415 ( .A(n2154), .B(n2191), .Y(n2156) );
OAI22X4TS U4416 ( .A0(n2196), .A1(n3133), .B0(n1057), .B1(n2155), .Y(n2192)
);
XNOR2X4TS U4417 ( .A(n2156), .B(n2192), .Y(n2188) );
XNOR2X4TS U4418 ( .A(n2157), .B(n2188), .Y(n2231) );
XOR2X2TS U4419 ( .A(n2230), .B(n2233), .Y(n2169) );
XNOR2X4TS U4420 ( .A(n2184), .B(n2174), .Y(n2177) );
INVX2TS U4421 ( .A(n2782), .Y(n2180) );
NAND2X2TS U4422 ( .A(n2178), .B(n2177), .Y(n2778) );
INVX2TS U4423 ( .A(n2778), .Y(n2179) );
AOI21X4TS U4424 ( .A0(n2180), .A1(n1056), .B0(n2179), .Y(n2181) );
OAI21X4TS U4425 ( .A0(n2780), .A1(n2182), .B0(n2181), .Y(n2807) );
OAI21X2TS U4426 ( .A0(n2188), .A1(n2187), .B0(n2185), .Y(n2186) );
OAI2BB1X4TS U4427 ( .A0N(n2188), .A1N(n2187), .B0(n2186), .Y(n2239) );
NOR2X8TS U4428 ( .A(n2197), .B(n2200), .Y(n2375) );
OAI21X4TS U4429 ( .A0(n2200), .A1(n2199), .B0(n2198), .Y(n2382) );
INVX2TS U4430 ( .A(n2374), .Y(n2201) );
XOR2X4TS U4431 ( .A(n2239), .B(n2238), .Y(n2229) );
ADDFHX4TS U4432 ( .A(n2206), .B(n2205), .CI(n2204), .CO(n2270), .S(n2230) );
ADDFHX4TS U4433 ( .A(n2209), .B(n2208), .CI(n2207), .CO(n2272), .S(n2187) );
XOR2X4TS U4434 ( .A(n2270), .B(n2272), .Y(n2228) );
INVX2TS U4435 ( .A(n2221), .Y(n2217) );
INVX2TS U4436 ( .A(n2220), .Y(n2222) );
XOR2X4TS U4437 ( .A(n2266), .B(n1071), .Y(n2227) );
XOR2X4TS U4438 ( .A(n2228), .B(n2271), .Y(n2236) );
XOR2X4TS U4439 ( .A(n2229), .B(n2236), .Y(n2234) );
OAI21X1TS U4440 ( .A0(n2238), .A1(n2239), .B0(n2236), .Y(n2237) );
OAI2BB1X4TS U4441 ( .A0N(n2239), .A1N(n2238), .B0(n2237), .Y(n2288) );
INVX2TS U4442 ( .A(n2365), .Y(n2240) );
OAI21X2TS U4443 ( .A0(n2245), .A1(n2246), .B0(n2243), .Y(n2244) );
INVX2TS U4444 ( .A(n2370), .Y(n2249) );
INVX6TS U4445 ( .A(n3415), .Y(n2361) );
ADDFHX4TS U4446 ( .A(n2254), .B(n2253), .CI(n2252), .CO(n2362), .S(n2268) );
ADDFHX4TS U4447 ( .A(n2269), .B(n2268), .CI(n2267), .CO(n2347), .S(n2238) );
INVX2TS U4448 ( .A(n2375), .Y(n2273) );
OAI21X4TS U4449 ( .A0(n2274), .A1(n2374), .B0(n2378), .Y(n2275) );
INVX2TS U4450 ( .A(n2379), .Y(n2277) );
ADDFHX4TS U4451 ( .A(n2287), .B(n2286), .CI(n2285), .CO(n2393), .S(n2271) );
ADDFHX4TS U4452 ( .A(n2305), .B(n2304), .CI(n2303), .CO(n3257), .S(n3208) );
INVX2TS U4453 ( .A(n2328), .Y(n2329) );
INVX2TS U4454 ( .A(n2330), .Y(n2333) );
NOR2X4TS U4455 ( .A(n2342), .B(n2341), .Y(n2840) );
NAND2X2TS U4456 ( .A(n2344), .B(n2343), .Y(n2809) );
OAI21X4TS U4457 ( .A0(n2808), .A1(n2841), .B0(n2809), .Y(n2345) );
AOI21X4TS U4458 ( .A0(n2807), .A1(n2346), .B0(n2345), .Y(n2802) );
OAI21X4TS U4459 ( .A0(n1351), .A1(n2350), .B0(n2347), .Y(n2348) );
XOR2X4TS U4460 ( .A(n2442), .B(n2438), .Y(n2356) );
XNOR2X4TS U4461 ( .A(n2356), .B(n2441), .Y(n2437) );
ADDFHX4TS U4462 ( .A(n2359), .B(n2358), .CI(n2357), .CO(n2436), .S(n2350) );
NAND2X2TS U4463 ( .A(n2362), .B(n2361), .Y(n2363) );
NAND2X4TS U4464 ( .A(n2364), .B(n2363), .Y(n2435) );
NAND2X4TS U4465 ( .A(n2381), .B(n2375), .Y(n2376) );
XOR2X4TS U4466 ( .A(n2412), .B(n2411), .Y(n2388) );
XOR2X4TS U4467 ( .A(n2388), .B(n2413), .Y(n2417) );
ADDFHX4TS U4468 ( .A(n2395), .B(n2394), .CI(n2393), .CO(n2415), .S(n2397) );
XOR2X4TS U4469 ( .A(n2414), .B(n2503), .Y(n2472) );
INVX2TS U4470 ( .A(n2486), .Y(n2420) );
XNOR2X4TS U4471 ( .A(n1160), .B(n3112), .Y(n2475) );
INVX2TS U4472 ( .A(n2475), .Y(n2429) );
ADDFHX4TS U4473 ( .A(n2437), .B(n2436), .CI(n2435), .CO(n2496), .S(n2460) );
INVX2TS U4474 ( .A(n2438), .Y(n2439) );
ADDFHX4TS U4475 ( .A(n2453), .B(n2452), .CI(n2451), .CO(n3421), .S(n3419) );
AOI21X4TS U4476 ( .A0(n2712), .A1(n2455), .B0(n2454), .Y(n2458) );
XOR2X4TS U4477 ( .A(n2458), .B(n2457), .Y(n3184) );
INVX2TS U4478 ( .A(n2464), .Y(n2463) );
INVX2TS U4479 ( .A(n2460), .Y(n2462) );
OAI2BB1X2TS U4480 ( .A0N(n2463), .A1N(n2462), .B0(n2461), .Y(n2466) );
ADDFHX4TS U4481 ( .A(n2472), .B(n2471), .CI(n2470), .CO(n2522), .S(n2467) );
INVX2TS U4482 ( .A(n2621), .Y(n2487) );
ADDFHX4TS U4483 ( .A(n2497), .B(n2496), .CI(n2495), .CO(n2596), .S(n2470) );
OAI2BB1X4TS U4484 ( .A0N(n2504), .A1N(n2503), .B0(n2502), .Y(n2634) );
OAI21X4TS U4485 ( .A0(n2508), .A1(n2507), .B0(n2506), .Y(n2711) );
ADDFHX4TS U4486 ( .A(n2513), .B(n2512), .CI(n2511), .CO(n2655), .S(n2504) );
ADDFHX4TS U4487 ( .A(n2516), .B(n2515), .CI(n2514), .CO(n3472), .S(n3422) );
NAND2BX4TS U4488 ( .AN(n1078), .B(n2518), .Y(n2519) );
XOR2X4TS U4489 ( .A(n2525), .B(n2524), .Y(n2588) );
INVX2TS U4490 ( .A(n2664), .Y(n2546) );
INVX2TS U4491 ( .A(n2576), .Y(n2549) );
INVX2TS U4492 ( .A(n2580), .Y(n2548) );
INVX2TS U4493 ( .A(n2671), .Y(n2550) );
NOR2X4TS U4494 ( .A(n2586), .B(n2585), .Y(n2818) );
INVX2TS U4495 ( .A(n2570), .Y(n2572) );
OAI21X2TS U4496 ( .A0(n2573), .A1(n2400), .B0(n2402), .Y(n2574) );
NOR2X2TS U4497 ( .A(n2665), .B(n2577), .Y(n2579) );
NAND2X1TS U4498 ( .A(n1626), .B(n2580), .Y(n2581) );
NOR2X4TS U4499 ( .A(n2818), .B(n2835), .Y(n2583) );
NAND2X4TS U4500 ( .A(n1055), .B(n2583), .Y(n2591) );
NAND2X2TS U4501 ( .A(n2586), .B(n2585), .Y(n2819) );
OAI21X4TS U4502 ( .A0(n2818), .A1(n2836), .B0(n2819), .Y(n2803) );
NAND2X2TS U4503 ( .A(n2588), .B(n2587), .Y(n2804) );
AOI21X4TS U4504 ( .A0(n2803), .A1(n1055), .B0(n2589), .Y(n2590) );
OAI21X4TS U4505 ( .A0(n2802), .A1(n2591), .B0(n2590), .Y(n2869) );
ADDFHX4TS U4506 ( .A(n2597), .B(n2596), .CI(n2595), .CO(n2660), .S(n2523) );
ADDFHX4TS U4507 ( .A(n2610), .B(n2609), .CI(n2608), .CO(n3471), .S(n3480) );
OAI21X1TS U4508 ( .A0(n2613), .A1(n2614), .B0(n2611), .Y(n2612) );
OAI22X4TS U4509 ( .A0(n1060), .A1(n2625), .B0(n1214), .B1(n2694), .Y(n2701)
);
INVX2TS U4510 ( .A(n2689), .Y(n2631) );
NOR2X2TS U4511 ( .A(n2637), .B(n2636), .Y(n2638) );
XNOR2X4TS U4512 ( .A(n2718), .B(FPMULT_Op_MY[11]), .Y(n2972) );
INVX2TS U4513 ( .A(n2648), .Y(n2649) );
ADDFHX4TS U4514 ( .A(n2656), .B(n2655), .CI(n2654), .CO(n2726), .S(n2633) );
XOR2X4TS U4515 ( .A(n2723), .B(n2726), .Y(n2659) );
XOR2X4TS U4516 ( .A(n2659), .B(n2725), .Y(n2745) );
XOR2X4TS U4517 ( .A(n2685), .B(n2663), .Y(n2684) );
NAND2X1TS U4518 ( .A(n3556), .B(n3560), .Y(n2680) );
NOR2X6TS U4519 ( .A(n2684), .B(n2683), .Y(n3834) );
NAND2X4TS U4520 ( .A(n2684), .B(n2683), .Y(n3835) );
OAI21X4TS U4521 ( .A0(n2685), .A1(n2870), .B0(n2872), .Y(n2752) );
NOR2X1TS U4522 ( .A(n1676), .B(n1040), .Y(n2905) );
INVX2TS U4523 ( .A(n2889), .Y(n2688) );
OAI2BB2X4TS U4524 ( .B0(n1209), .B1(n2689), .A0N(n3303), .A1N(n2688), .Y(
n2890) );
INVX2TS U4525 ( .A(n2897), .Y(n2692) );
XOR2X4TS U4526 ( .A(n2703), .B(n2894), .Y(n2923) );
XNOR2X4TS U4527 ( .A(n2936), .B(n2935), .Y(n2722) );
XOR2X4TS U4528 ( .A(n2722), .B(n2721), .Y(n2876) );
OAI21X4TS U4529 ( .A0(n2725), .A1(n2726), .B0(n2723), .Y(n2724) );
OAI2BB1X4TS U4530 ( .A0N(n2726), .A1N(n2725), .B0(n2724), .Y(n2875) );
INVX2TS U4531 ( .A(n2730), .Y(n2731) );
ADDFHX4TS U4532 ( .A(n2737), .B(n2736), .CI(n2735), .CO(n3468), .S(n3470) );
ADDFHX4TS U4533 ( .A(n2747), .B(n2746), .CI(n2745), .CO(n2749), .S(n2661) );
XNOR2X4TS U4534 ( .A(n2752), .B(n2751), .Y(n2754) );
INVX2TS U4535 ( .A(n2866), .Y(n2755) );
NAND2X2TS U4536 ( .A(n2754), .B(n2753), .Y(n2865) );
INVX2TS U4537 ( .A(n2762), .Y(n4020) );
INVX2TS U4538 ( .A(n4019), .Y(n2763) );
INVX2TS U4539 ( .A(n2765), .Y(n2768) );
INVX2TS U4540 ( .A(n2824), .Y(n2773) );
NAND2X1TS U4541 ( .A(n2771), .B(n2770), .Y(n2772) );
XNOR2X1TS U4542 ( .A(n2773), .B(n2772), .Y(n2774) );
NOR4X1TS U4543 ( .A(n2777), .B(n2776), .C(n2775), .D(n2774), .Y(n2858) );
NAND2X1TS U4544 ( .A(n1056), .B(n2778), .Y(n2779) );
XOR2X1TS U4545 ( .A(n2102), .B(n2779), .Y(n2798) );
INVX2TS U4546 ( .A(n2780), .Y(n2784) );
NAND2X1TS U4547 ( .A(n2782), .B(n2781), .Y(n2783) );
XNOR2X1TS U4548 ( .A(n2784), .B(n2783), .Y(n2797) );
INVX2TS U4549 ( .A(n2785), .Y(n4013) );
OAI21X1TS U4550 ( .A0(n4013), .A1(n4009), .B0(n4010), .Y(n2790) );
INVX2TS U4551 ( .A(n2786), .Y(n2788) );
NAND2X1TS U4552 ( .A(n2788), .B(n2787), .Y(n2789) );
XNOR2X1TS U4553 ( .A(n2790), .B(n2789), .Y(n2796) );
INVX2TS U4554 ( .A(n2791), .Y(n2793) );
NAND2X1TS U4555 ( .A(n2793), .B(n2792), .Y(n2794) );
XOR2X1TS U4556 ( .A(n2794), .B(n4016), .Y(n2795) );
NOR4X2TS U4557 ( .A(n2798), .B(n2797), .C(n2796), .D(n2795), .Y(n2816) );
INVX6TS U4558 ( .A(n2802), .Y(n2839) );
NAND2X1TS U4559 ( .A(n1055), .B(n2804), .Y(n2805) );
INVX2TS U4560 ( .A(n2807), .Y(n2844) );
NAND2X1TS U4561 ( .A(n2841), .B(n2844), .Y(n2812) );
INVX2TS U4562 ( .A(n2808), .Y(n2810) );
NAND2X1TS U4563 ( .A(n2810), .B(n2809), .Y(n2811) );
XNOR2X1TS U4564 ( .A(n2812), .B(n2811), .Y(n2813) );
NOR4BX4TS U4565 ( .AN(n2816), .B(n2815), .C(n2814), .D(n2813), .Y(n2857) );
INVX2TS U4566 ( .A(n2836), .Y(n2817) );
NOR2X2TS U4567 ( .A(n2839), .B(n2817), .Y(n2822) );
INVX2TS U4568 ( .A(n2818), .Y(n2820) );
NAND2X1TS U4569 ( .A(n2820), .B(n2819), .Y(n2821) );
XOR2X1TS U4570 ( .A(n2822), .B(n2821), .Y(n2834) );
INVX2TS U4571 ( .A(n2823), .Y(n2827) );
XNOR2X1TS U4572 ( .A(n2830), .B(n2829), .Y(n2832) );
NOR4X2TS U4573 ( .A(n2834), .B(n2833), .C(n2832), .D(n2831), .Y(n2856) );
INVX2TS U4574 ( .A(n2835), .Y(n2837) );
NAND2X1TS U4575 ( .A(n2837), .B(n2836), .Y(n2838) );
XNOR2X1TS U4576 ( .A(n2839), .B(n2838), .Y(n2854) );
INVX2TS U4577 ( .A(n2840), .Y(n2842) );
NAND2X1TS U4578 ( .A(n2842), .B(n2841), .Y(n2843) );
XOR2X1TS U4579 ( .A(n2844), .B(n2843), .Y(n2853) );
INVX2TS U4580 ( .A(n2845), .Y(n2847) );
NOR2X4TS U4581 ( .A(n3834), .B(n2866), .Y(n2868) );
OAI21X4TS U4582 ( .A0(n2866), .A1(n3835), .B0(n2865), .Y(n2867) );
ADDFHX4TS U4583 ( .A(n2876), .B(n2875), .CI(n2874), .CO(n2939), .S(n2748) );
OAI2BB1X4TS U4584 ( .A0N(n2895), .A1N(n2894), .B0(n2893), .Y(n2996) );
XOR2X4TS U4585 ( .A(n2945), .B(n2944), .Y(n2906) );
XOR2X4TS U4586 ( .A(n2906), .B(n2943), .Y(n2995) );
ADDFHX4TS U4587 ( .A(n2910), .B(n2909), .CI(n2908), .CO(n2999), .S(n2886) );
INVX2TS U4588 ( .A(n2999), .Y(n2911) );
XOR2X4TS U4589 ( .A(n2912), .B(n2911), .Y(n3007) );
XOR2X4TS U4590 ( .A(n2913), .B(n3007), .Y(n3010) );
ADDFHX4TS U4591 ( .A(n2916), .B(n2915), .CI(n2914), .CO(n3009), .S(n2874) );
ADDFHX4TS U4592 ( .A(n2919), .B(n2918), .CI(n2917), .CO(n2980), .S(n2915) );
ADDFHX4TS U4593 ( .A(n2925), .B(n2924), .CI(n2923), .CO(n3466), .S(n3469) );
ADDFHX4TS U4594 ( .A(n2934), .B(n2933), .CI(n2932), .CO(n2981), .S(n2936) );
NAND2X2TS U4595 ( .A(n2936), .B(n2935), .Y(n2937) );
OAI21X4TS U4596 ( .A0(n2945), .A1(n2944), .B0(n2943), .Y(n2947) );
XOR2X4TS U4597 ( .A(n3060), .B(n3059), .Y(n2960) );
INVX2TS U4598 ( .A(n3042), .Y(n2951) );
ADDFHX4TS U4599 ( .A(n2964), .B(n2963), .CI(n2962), .CO(n3079), .S(n3006) );
INVX2TS U4600 ( .A(n3056), .Y(n2973) );
XOR2X4TS U4601 ( .A(n2975), .B(n3031), .Y(n3052) );
XOR2X4TS U4602 ( .A(n2977), .B(n3077), .Y(n3083) );
ADDFHX4TS U4603 ( .A(n2980), .B(n2979), .CI(n2978), .CO(n3082), .S(n3008) );
ADDFHX4TS U4604 ( .A(n2986), .B(n2985), .CI(n2984), .CO(n3068), .S(n2982) );
INVX2TS U4605 ( .A(n2991), .Y(n2990) );
OAI2BB1X4TS U4606 ( .A0N(n2990), .A1N(n2992), .B0(n2989), .Y(n2994) );
ADDFHX4TS U4607 ( .A(n2997), .B(n2996), .CI(n2995), .CO(n3485), .S(n3467) );
ADDFHX4TS U4608 ( .A(n3010), .B(n3009), .CI(n3008), .CO(n3012), .S(n2940) );
NOR2X8TS U4609 ( .A(n3011), .B(n3012), .Y(n3029) );
INVX2TS U4610 ( .A(n3090), .Y(n3017) );
OR2X4TS U4611 ( .A(n3023), .B(n1661), .Y(n3859) );
XNOR2X2TS U4612 ( .A(n5060), .B(n5049), .Y(n3111) );
INVX2TS U4613 ( .A(n3111), .Y(n3043) );
OAI2BB2X4TS U4614 ( .B0(n3306), .B1(n3044), .A0N(n1620), .A1N(n3043), .Y(
n3109) );
ADDFHX4TS U4615 ( .A(n3053), .B(n3052), .CI(n3051), .CO(n3142), .S(n3077) );
OAI21X4TS U4616 ( .A0(n3060), .A1(n3059), .B0(n3058), .Y(n3062) );
XNOR2X4TS U4617 ( .A(n3063), .B(n3487), .Y(n3096) );
ADDFHX4TS U4618 ( .A(n3066), .B(n3065), .CI(n3064), .CO(n3145), .S(n3081) );
ADDFHX4TS U4619 ( .A(n3076), .B(n3075), .CI(n3074), .CO(n3122), .S(n3080) );
ADDFHX4TS U4620 ( .A(n3083), .B(n3082), .CI(n3081), .CO(n3084), .S(n3011) );
OAI21X4TS U4621 ( .A0(n3090), .A1(n3089), .B0(n3088), .Y(n3154) );
ADDFHX4TS U4622 ( .A(n3095), .B(n3094), .CI(n3093), .CO(n3211), .S(n3143) );
OAI2BB1X4TS U4623 ( .A0N(n3102), .A1N(n3101), .B0(n3100), .Y(n3167) );
ADDFHX4TS U4624 ( .A(n3121), .B(n3120), .CI(n3119), .CO(n3213), .S(n3144) );
ADDFHX4TS U4625 ( .A(n3124), .B(n3123), .CI(n3122), .CO(n3179), .S(n3120) );
ADDFHX4TS U4626 ( .A(n3127), .B(n3126), .CI(n3125), .CO(n3182), .S(n3123) );
ADDFHX4TS U4627 ( .A(n3140), .B(n3139), .CI(n3138), .CO(n3490), .S(n3488) );
ADDFHX4TS U4628 ( .A(n3146), .B(n3145), .CI(n3144), .CO(n3148), .S(n3085) );
INVX2TS U4629 ( .A(n3219), .Y(n3151) );
ADDFHX4TS U4630 ( .A(n3168), .B(n3167), .CI(n3166), .CO(n3233), .S(n3209) );
ADDFHX4TS U4631 ( .A(n3182), .B(n3181), .CI(n3180), .CO(n3237), .S(n3178) );
XOR2X4TS U4632 ( .A(n3186), .B(n3265), .Y(n3261) );
XOR2X4TS U4633 ( .A(n3239), .B(n3242), .Y(n3201) );
XNOR2X4TS U4634 ( .A(n3201), .B(n3240), .Y(n3248) );
ADDFHX4TS U4635 ( .A(n3207), .B(n3206), .CI(n3205), .CO(n3499), .S(n3489) );
ADDFHX4TS U4636 ( .A(n3211), .B(n3210), .CI(n3209), .CO(n3235), .S(n3214) );
ADDFHX4TS U4637 ( .A(n3214), .B(n3213), .CI(n3212), .CO(n3215), .S(n3147) );
AOI21X4TS U4638 ( .A0(n3848), .A1(n3229), .B0(n3228), .Y(n3786) );
ADDFHX4TS U4639 ( .A(n3234), .B(n3233), .CI(n3232), .CO(n3325), .S(n3280) );
INVX2TS U4640 ( .A(n3240), .Y(n3241) );
ADDFHX4TS U4641 ( .A(n3250), .B(n3249), .CI(n3248), .CO(n3288), .S(n3252) );
ADDFHX4TS U4642 ( .A(n3253), .B(n3252), .CI(n3251), .CO(n3695), .S(n3498) );
ADDFHX4TS U4643 ( .A(n3498), .B(n3255), .CI(n3254), .CO(n3297), .S(n3259) );
ADDFHX4TS U4644 ( .A(n3261), .B(n3260), .CI(n3259), .CO(n3321), .S(n3236) );
ADDFHX4TS U4645 ( .A(n3290), .B(n3289), .CI(n3288), .CO(n3696), .S(n3688) );
ADDFHX4TS U4646 ( .A(n3295), .B(n3294), .CI(n3293), .CO(n3349), .S(n3298) );
ADDFHX4TS U4647 ( .A(n3298), .B(n3297), .CI(n3296), .CO(n3330), .S(n3322) );
INVX2TS U4648 ( .A(n3380), .Y(n3303) );
OAI22X1TS U4649 ( .A0(n3558), .A1(n5048), .B0(n3557), .B1(FPMULT_Op_MY[21]),
.Y(n3341) );
XOR2X4TS U4650 ( .A(n3359), .B(n3313), .Y(n3346) );
ADDFHX4TS U4651 ( .A(n3316), .B(n3315), .CI(n3314), .CO(n3327), .S(n3283) );
ADDFHX4TS U4652 ( .A(n3319), .B(n3318), .CI(n3317), .CO(n3326), .S(n3296) );
ADDFHX4TS U4653 ( .A(n3325), .B(n3324), .CI(n3323), .CO(n3369), .S(n3364) );
ADDFHX4TS U4654 ( .A(n3331), .B(n3330), .CI(n3329), .CO(n3374), .S(n3362) );
ADDFHX4TS U4655 ( .A(n3334), .B(n3333), .CI(n3332), .CO(n3378), .S(n3350) );
ADDFHX4TS U4656 ( .A(n3351), .B(n3350), .CI(n3349), .CO(n3403), .S(n3331) );
OAI22X1TS U4657 ( .A0(n3352), .A1(n3601), .B0(n3389), .B1(n1219), .Y(n3392)
);
OAI21X1TS U4658 ( .A0(n3359), .A1(n3355), .B0(n3353), .Y(n3354) );
OAI2BB1X2TS U4659 ( .A0N(n3355), .A1N(n3359), .B0(n3354), .Y(n3391) );
ADDFHX4TS U4660 ( .A(n3358), .B(n3357), .CI(n3356), .CO(n3702), .S(n3359) );
ADDFHX4TS U4661 ( .A(n3363), .B(n3362), .CI(n3361), .CO(n3371), .S(n3368) );
ADDFHX4TS U4662 ( .A(n3375), .B(n3374), .CI(n3373), .CO(n3406), .S(n3370) );
OAI22X1TS U4663 ( .A0(n3389), .A1(n3601), .B0(n3528), .B1(n1219), .Y(n3521)
);
ADDFHX4TS U4664 ( .A(n3401), .B(n3400), .CI(n3399), .CO(n3507), .S(n3377) );
ADDFHX4TS U4665 ( .A(n3404), .B(n3403), .CI(n3402), .CO(n3504), .S(n3373) );
XOR2X4TS U4666 ( .A(n3408), .B(n3407), .Y(n3464) );
NOR2X2TS U4667 ( .A(n3420), .B(n3419), .Y(n3473) );
OAI21X1TS U4668 ( .A0(n956), .A1(n3426), .B0(n3450), .Y(n3429) );
XOR2X4TS U4669 ( .A(n3435), .B(n3434), .Y(n3462) );
NAND2X4TS U4670 ( .A(n3443), .B(n3442), .Y(n3444) );
NAND2X4TS U4671 ( .A(n3462), .B(n3461), .Y(n3829) );
AOI21X4TS U4672 ( .A0(n3479), .A1(n3478), .B0(n3477), .Y(n3539) );
OAI21X4TS U4673 ( .A0(n3484), .A1(n3539), .B0(n3483), .Y(n3744) );
INVX2TS U4674 ( .A(n3687), .Y(n3494) );
NOR2X8TS U4675 ( .A(n3542), .B(n3544), .Y(n3622) );
OAI21X4TS U4676 ( .A0(n3545), .A1(n3544), .B0(n3543), .Y(n3627) );
INVX2TS U4677 ( .A(n3627), .Y(n3546) );
AOI21X4TS U4678 ( .A0(n1370), .A1(n3549), .B0(n3548), .Y(n3579) );
XOR2X4TS U4679 ( .A(n3579), .B(n3578), .Y(n3677) );
NOR2X8TS U4680 ( .A(n3814), .B(n3793), .Y(n3815) );
AOI21X4TS U4681 ( .A0(n3627), .A1(n1686), .B0(n3626), .Y(n3589) );
OAI21X4TS U4682 ( .A0(n3590), .A1(n3628), .B0(n3589), .Y(n3591) );
AOI21X4TS U4683 ( .A0(n1395), .A1(n3592), .B0(n3591), .Y(n3618) );
XOR2X4TS U4684 ( .A(n3618), .B(n3617), .Y(n3679) );
INVX2TS U4685 ( .A(n3649), .Y(n3650) );
NOR2X6TS U4686 ( .A(n3681), .B(n3680), .Y(n3788) );
NAND2X6TS U4687 ( .A(n3815), .B(n3683), .Y(n3663) );
OR2X4TS U4688 ( .A(add_x_69_n82), .B(n1065), .Y(n3674) );
OAI21X4TS U4689 ( .A0(n3793), .A1(n3813), .B0(n3794), .Y(n3774) );
AOI21X4TS U4690 ( .A0(n3694), .A1(n3693), .B0(n3692), .Y(n3741) );
INVX2TS U4691 ( .A(n3734), .Y(n3713) );
INVX2TS U4692 ( .A(n3718), .Y(n3720) );
INVX2TS U4693 ( .A(n3732), .Y(n3724) );
INVX2TS U4694 ( .A(n3805), .Y(n3747) );
NOR2X4TS U4695 ( .A(n1680), .B(add_x_69_n66), .Y(n3751) );
NAND2X4TS U4696 ( .A(n1058), .B(n3769), .Y(n3756) );
INVX2TS U4697 ( .A(n3751), .Y(n3752) );
NOR2X4TS U4698 ( .A(n3753), .B(n3752), .Y(n3760) );
INVX2TS U4699 ( .A(n3760), .Y(n3754) );
INVX2TS U4700 ( .A(n3763), .Y(n3765) );
INVX2TS U4701 ( .A(n3788), .Y(n3790) );
INVX2TS U4702 ( .A(n3830), .Y(n3791) );
INVX2TS U4703 ( .A(n3818), .Y(n3792) );
INVX2TS U4704 ( .A(n3793), .Y(n3795) );
INVX2TS U4705 ( .A(n3796), .Y(n3798) );
INVX2TS U4706 ( .A(n1424), .Y(n3800) );
INVX2TS U4707 ( .A(n3801), .Y(n3803) );
NAND2X1TS U4708 ( .A(n3808), .B(n3807), .Y(n3809) );
NAND2X1TS U4709 ( .A(n1668), .B(n3809), .Y(n3810) );
INVX2TS U4710 ( .A(n3812), .Y(add_x_69_n90) );
INVX2TS U4711 ( .A(n3813), .Y(n3822) );
INVX2TS U4712 ( .A(n3826), .Y(n3827) );
INVX2TS U4713 ( .A(n3828), .Y(n3831) );
INVX2TS U4714 ( .A(n3834), .Y(n3836) );
NAND2X2TS U4715 ( .A(n3842), .B(n3841), .Y(n3843) );
OAI21X2TS U4716 ( .A0(n3853), .A1(n3845), .B0(n3846), .Y(n3850) );
XOR2X1TS U4717 ( .A(n994), .B(n993), .Y(FPMULT_Sgf_operation_Result[26]) );
ADDHXLTS U4718 ( .A(FPMULT_Sgf_normalized_result[19]), .B(n3863), .CO(n3777),
.S(FPMULT_Adder_M_result_A_adder[19]) );
NOR4X1TS U4719 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n5216) );
NOR4X1TS U4720 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n5215) );
NOR2X1TS U4721 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n4717), .Y(n3957) );
INVX2TS U4722 ( .A(n3957), .Y(n3966) );
NOR3X2TS U4723 ( .A(n5107), .B(n4719), .C(n3966), .Y(n107) );
NOR4X1TS U4724 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n3866) );
NOR4X1TS U4725 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n3865) );
NOR4X1TS U4726 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n3864) );
NOR4X1TS U4727 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n3867),
.Y(n5211) );
NOR3BX2TS U4728 ( .AN(FPSENCOS_cont_var_out[1]), .B(n1105), .C(
FPSENCOS_cont_var_out[0]), .Y(FPSENCOS_enab_d_ff4_Zn) );
NOR3X2TS U4729 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(
n4284) );
NOR3X2TS U4730 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[19]), .C(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(
n4044) );
NOR2X2TS U4731 ( .A(FPADDSUB_Raw_mant_NRM_SWR[22]), .B(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3911) );
NAND2X2TS U4732 ( .A(n3912), .B(n3911), .Y(n4043) );
NOR2BX4TS U4733 ( .AN(n4044), .B(n4043), .Y(n4091) );
INVX2TS U4734 ( .A(n3910), .Y(n3869) );
NOR2X4TS U4735 ( .A(FPADDSUB_Raw_mant_NRM_SWR[14]), .B(n3909), .Y(n3907) );
NAND2X4TS U4736 ( .A(n4284), .B(n3907), .Y(n3908) );
NAND2BX2TS U4737 ( .AN(n3875), .B(n3874), .Y(n3917) );
NAND2BX1TS U4738 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n3928),
.Y(n3929) );
NAND2X1TS U4739 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n4592) );
OAI21X1TS U4740 ( .A0(n4591), .A1(n4599), .B0(n4592), .Y(n4569) );
NOR2X1TS U4741 ( .A(n4579), .B(n4570), .Y(n3881) );
NAND2X1TS U4742 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4580) );
NAND2X1TS U4743 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n4571) );
OAI21X1TS U4744 ( .A0(n4570), .A1(n4580), .B0(n4571), .Y(n3880) );
NOR2X1TS U4745 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n4546) );
NOR2X2TS U4746 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n4548) );
NOR2X1TS U4747 ( .A(n4546), .B(n4548), .Y(n4331) );
NOR2X2TS U4748 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n4354) );
NOR2X1TS U4749 ( .A(n4354), .B(n4332), .Y(n3883) );
NAND2X1TS U4750 ( .A(n4331), .B(n3883), .Y(n3885) );
OAI21X1TS U4751 ( .A0(n4548), .A1(n4558), .B0(n4549), .Y(n4330) );
NAND2X1TS U4752 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n4333) );
AOI21X1TS U4753 ( .A0(n4330), .A1(n3883), .B0(n3882), .Y(n3884) );
NOR2X1TS U4754 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n4399) );
INVX2TS U4755 ( .A(n4399), .Y(n4536) );
NAND2X1TS U4756 ( .A(n4536), .B(n4401), .Y(n4370) );
NOR2X2TS U4757 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]),
.Y(n4371) );
INVX2TS U4758 ( .A(n4535), .Y(n3887) );
NAND2X1TS U4759 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n4400) );
INVX2TS U4760 ( .A(n4400), .Y(n3886) );
AOI21X1TS U4761 ( .A0(n4401), .A1(n3887), .B0(n3886), .Y(n4369) );
NAND2X1TS U4762 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n4372) );
NOR2X1TS U4763 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]),
.Y(n4384) );
NAND2X1TS U4764 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n4527) );
INVX2TS U4765 ( .A(n4527), .Y(n3890) );
NOR2X1TS U4766 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]),
.Y(n4518) );
NAND2X1TS U4767 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n4519) );
NAND2X1TS U4768 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n4510) );
INVX2TS U4769 ( .A(n4510), .Y(n3891) );
AOI21X4TS U4770 ( .A0(n4512), .A1(n4511), .B0(n3891), .Y(n4504) );
NOR2X1TS U4771 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]),
.Y(n4501) );
NAND2X1TS U4772 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n4502) );
NAND2X1TS U4773 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n4493) );
INVX2TS U4774 ( .A(n4493), .Y(n3892) );
NOR2X1TS U4775 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]),
.Y(n4445) );
NAND2X1TS U4776 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n4446) );
NAND2X1TS U4777 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n4437) );
INVX2TS U4778 ( .A(n4437), .Y(n3893) );
NOR2X1TS U4779 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]),
.Y(n4412) );
NAND2X1TS U4780 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n4413) );
NAND2X1TS U4781 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n4454) );
INVX2TS U4782 ( .A(n4454), .Y(n3894) );
AOI21X4TS U4783 ( .A0(n4456), .A1(n4455), .B0(n3894), .Y(n4468) );
NOR2X1TS U4784 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]),
.Y(n4465) );
NAND2X1TS U4785 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n4466) );
NAND2X1TS U4786 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n4476) );
INVX2TS U4787 ( .A(n4476), .Y(n3895) );
BUFX3TS U4788 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n4462) );
INVX2TS U4789 ( .A(n3997), .Y(n4303) );
NAND3X2TS U4790 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .C(n4158), .Y(n4301) );
NAND2BX2TS U4791 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n4132) );
NOR2BX1TS U4792 ( .AN(n3897), .B(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n3898) );
AOI22X1TS U4793 ( .A0(n1154), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n1157),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n3899) );
AOI22X1TS U4794 ( .A0(n1155), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n1158),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n3901) );
XOR2X1TS U4795 ( .A(n1120), .B(n1694), .Y(DP_OP_26J307_123_9022_n18) );
NAND2X1TS U4796 ( .A(n3906), .B(n1693), .Y(n3926) );
OAI31X1TS U4797 ( .A0(n5168), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(
FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n3911), .Y(n3913) );
NAND2X1TS U4798 ( .A(n3913), .B(n3912), .Y(n3914) );
NAND4BX2TS U4799 ( .AN(n3917), .B(n3916), .C(n3915), .D(n3914), .Y(
FPADDSUB_LZD_raw_out_EWR[1]) );
NOR2X1TS U4800 ( .A(FPSENCOS_cont_iter_out[0]), .B(FPSENCOS_cont_iter_out[1]), .Y(n3967) );
NAND2X1TS U4801 ( .A(n4976), .B(n5096), .Y(n3920) );
INVX2TS U4802 ( .A(n5020), .Y(n865) );
INVX2TS U4803 ( .A(n3925), .Y(n3965) );
NOR2X1TS U4804 ( .A(n3965), .B(n5024), .Y(n5021) );
OAI211X1TS U4805 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n5098), .B0(n5096),
.C0(n5118), .Y(n5023) );
NOR2X2TS U4806 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n1665), .Y(n3964) );
NAND2X1TS U4807 ( .A(n5107), .B(n910), .Y(n3973) );
INVX2TS U4808 ( .A(n3973), .Y(n3922) );
XOR2X1TS U4809 ( .A(add_x_69_n31), .B(n5090), .Y(n4325) );
INVX2TS U4810 ( .A(n4325), .Y(n3918) );
AOI22X1TS U4811 ( .A0(n4326), .A1(n3918), .B0(n1128), .B1(n1671), .Y(n3919)
);
INVX2TS U4812 ( .A(n3935), .Y(n3923) );
AOI22X1TS U4813 ( .A0(n5333), .A1(n5332), .B0(r_mode[0]), .B1(r_mode[1]),
.Y(n3921) );
OAI221X1TS U4814 ( .A0(n5200), .A1(r_mode[1]), .B0(n5334), .B1(r_mode[0]),
.C0(n3921), .Y(n3936) );
NAND2X1TS U4815 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n4717), .Y(n3931) );
AOI22X1TS U4816 ( .A0(n3923), .A1(n3936), .B0(n3922), .B1(n3931), .Y(n3924)
);
OAI31X4TS U4817 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(
FPSENCOS_cont_iter_out[3]), .A2(n5098), .B0(n865), .Y(n5022) );
NOR2X1TS U4818 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n3926),
.Y(n3948) );
NAND4X1TS U4819 ( .A(n3928), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]),
.C(n3927), .D(n5161), .Y(n4870) );
NAND2X1TS U4820 ( .A(n3977), .B(n4870), .Y(FPSENCOS_enab_d_ff_RB1) );
NOR2X1TS U4821 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n3929),
.Y(n4001) );
NAND3BX1TS U4822 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n4001), .Y(n4866) );
NOR3X2TS U4823 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n910), .C(n3931), .Y(
n5030) );
AOI22X1TS U4824 ( .A0(n5019), .A1(ready_add_subt), .B0(n5030), .B1(n5016),
.Y(n3932) );
OAI2BB1X1TS U4825 ( .A0N(n3933), .A1N(n5017), .B0(n3932), .Y(operation_ready) );
NAND2X1TS U4826 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n5159), .Y(n3969) );
OAI21XLTS U4827 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n5159), .B0(n3969),
.Y(FPADDSUB_Shift_amount_EXP_EW[0]) );
AOI22X1TS U4828 ( .A0(FPSENCOS_d_ff3_sh_x_out[4]), .A1(n4072), .B0(Data_2[4]), .B1(n4883), .Y(n3939) );
AOI22X1TS U4829 ( .A0(n4878), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n4877),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n3938) );
NAND2X1TS U4830 ( .A(n3939), .B(n3938), .Y(add_subt_data2[4]) );
AOI22X1TS U4831 ( .A0(FPSENCOS_d_ff3_sh_x_out[8]), .A1(n4072), .B0(Data_2[8]), .B1(n1180), .Y(n3941) );
AOI22X1TS U4832 ( .A0(n4878), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n4877),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n3940) );
NAND2X1TS U4833 ( .A(n3941), .B(n3940), .Y(add_subt_data2[8]) );
AOI22X1TS U4834 ( .A0(FPSENCOS_d_ff3_sh_x_out[6]), .A1(n4072), .B0(Data_2[6]), .B1(n4883), .Y(n3943) );
AOI22X1TS U4835 ( .A0(n4878), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n4877),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n3942) );
NAND2X1TS U4836 ( .A(n3943), .B(n3942), .Y(add_subt_data2[6]) );
AOI22X1TS U4837 ( .A0(FPSENCOS_d_ff3_sh_x_out[2]), .A1(n4072), .B0(Data_2[2]), .B1(n4883), .Y(n3945) );
AOI22X1TS U4838 ( .A0(n4608), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n4877),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n3944) );
NAND2X1TS U4839 ( .A(n3945), .B(n3944), .Y(add_subt_data2[2]) );
AOI22X1TS U4840 ( .A0(FPSENCOS_d_ff3_sh_x_out[10]), .A1(n4072), .B0(
Data_2[10]), .B1(n4883), .Y(n3947) );
AOI22X1TS U4841 ( .A0(n4878), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n4877),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n3946) );
NAND2X1TS U4842 ( .A(n3947), .B(n3946), .Y(add_subt_data2[10]) );
NAND3BX1TS U4843 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n3948),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n4873) );
INVX2TS U4844 ( .A(n4873), .Y(n4294) );
AOI22X1TS U4845 ( .A0(FPSENCOS_d_ff3_sh_x_out[12]), .A1(n4072), .B0(
Data_2[12]), .B1(n1180), .Y(n3951) );
AOI22X1TS U4846 ( .A0(n4878), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n4898),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n3950) );
NAND2X1TS U4847 ( .A(n3951), .B(n3950), .Y(add_subt_data2[12]) );
AOI22X1TS U4848 ( .A0(FPSENCOS_d_ff3_sh_x_out[1]), .A1(n4971), .B0(Data_2[1]), .B1(n4883), .Y(n3953) );
AOI22X1TS U4849 ( .A0(n4878), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n4898),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n3952) );
NAND2X1TS U4850 ( .A(n3953), .B(n3952), .Y(add_subt_data2[1]) );
AOI22X1TS U4851 ( .A0(FPSENCOS_d_ff3_sh_x_out[0]), .A1(n4069), .B0(Data_2[0]), .B1(n4929), .Y(n3955) );
AOI22X1TS U4852 ( .A0(n4964), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n4967),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n3954) );
NAND2X1TS U4853 ( .A(n3955), .B(n3954), .Y(add_subt_data2[0]) );
CLKBUFX2TS U4854 ( .A(n824), .Y(n5326) );
CLKBUFX2TS U4855 ( .A(n5326), .Y(n5324) );
BUFX3TS U4856 ( .A(n5285), .Y(n5293) );
BUFX3TS U4857 ( .A(n5324), .Y(n5294) );
CLKBUFX3TS U4858 ( .A(n5280), .Y(n3962) );
BUFX3TS U4859 ( .A(n3962), .Y(n5235) );
CLKBUFX3TS U4860 ( .A(n5280), .Y(n3963) );
BUFX3TS U4861 ( .A(n3963), .Y(n5234) );
BUFX3TS U4862 ( .A(n3962), .Y(n5233) );
BUFX3TS U4863 ( .A(n5324), .Y(n5320) );
CLKBUFX2TS U4864 ( .A(n5326), .Y(n5325) );
CLKBUFX3TS U4865 ( .A(n5325), .Y(n5319) );
BUFX3TS U4866 ( .A(n5319), .Y(n5288) );
CLKBUFX3TS U4867 ( .A(n5280), .Y(n3959) );
BUFX3TS U4868 ( .A(n3959), .Y(n5240) );
BUFX3TS U4869 ( .A(n5319), .Y(n5289) );
BUFX3TS U4870 ( .A(n5325), .Y(n5290) );
BUFX3TS U4871 ( .A(n3962), .Y(n5239) );
BUFX3TS U4872 ( .A(n5324), .Y(n5291) );
BUFX3TS U4873 ( .A(n3963), .Y(n5238) );
BUFX3TS U4874 ( .A(n5319), .Y(n5292) );
CLKBUFX2TS U4875 ( .A(n5326), .Y(n5323) );
BUFX3TS U4876 ( .A(n5310), .Y(n5306) );
BUFX3TS U4877 ( .A(n5300), .Y(n5308) );
BUFX3TS U4878 ( .A(n5321), .Y(n5309) );
BUFX3TS U4879 ( .A(n5323), .Y(n5310) );
CLKBUFX2TS U4880 ( .A(n824), .Y(n5327) );
BUFX3TS U4881 ( .A(n1229), .Y(n5311) );
BUFX3TS U4882 ( .A(n5324), .Y(n5299) );
BUFX3TS U4883 ( .A(n5323), .Y(n5300) );
BUFX3TS U4884 ( .A(n5300), .Y(n5301) );
BUFX3TS U4885 ( .A(n3961), .Y(n5251) );
BUFX3TS U4886 ( .A(n3959), .Y(n5231) );
BUFX3TS U4887 ( .A(n3961), .Y(n5249) );
BUFX3TS U4888 ( .A(n3961), .Y(n5232) );
BUFX3TS U4889 ( .A(n3961), .Y(n5248) );
BUFX3TS U4890 ( .A(n3959), .Y(n5230) );
BUFX3TS U4891 ( .A(n3959), .Y(n5229) );
BUFX3TS U4892 ( .A(n3959), .Y(n5228) );
BUFX3TS U4893 ( .A(n3959), .Y(n5227) );
BUFX3TS U4894 ( .A(n3959), .Y(n5226) );
BUFX3TS U4895 ( .A(n5321), .Y(n5303) );
BUFX3TS U4896 ( .A(n5310), .Y(n5304) );
BUFX3TS U4897 ( .A(n5300), .Y(n5305) );
NAND2X2TS U4898 ( .A(n3957), .B(n3956), .Y(n5282) );
INVX2TS U4899 ( .A(n5282), .Y(n3958) );
BUFX3TS U4900 ( .A(n3962), .Y(n5254) );
BUFX3TS U4901 ( .A(n3961), .Y(n5253) );
BUFX3TS U4902 ( .A(n3962), .Y(n5257) );
BUFX3TS U4903 ( .A(n5310), .Y(n5307) );
BUFX3TS U4904 ( .A(n3959), .Y(n5247) );
BUFX3TS U4905 ( .A(n3962), .Y(n5255) );
BUFX3TS U4906 ( .A(n3961), .Y(n5245) );
INVX2TS U4907 ( .A(n5282), .Y(n5029) );
BUFX3TS U4908 ( .A(n3959), .Y(n5225) );
BUFX3TS U4909 ( .A(n5321), .Y(n5302) );
BUFX3TS U4910 ( .A(n3962), .Y(n5256) );
BUFX3TS U4911 ( .A(n5319), .Y(n5286) );
BUFX3TS U4912 ( .A(n5319), .Y(n5287) );
BUFX3TS U4913 ( .A(n3963), .Y(n5264) );
BUFX3TS U4914 ( .A(n3961), .Y(n5250) );
BUFX3TS U4915 ( .A(n3963), .Y(n5263) );
BUFX3TS U4916 ( .A(n3963), .Y(n5262) );
BUFX3TS U4917 ( .A(n3963), .Y(n5260) );
BUFX3TS U4918 ( .A(n3962), .Y(n5259) );
BUFX3TS U4919 ( .A(n3963), .Y(n5243) );
BUFX3TS U4920 ( .A(n3962), .Y(n5258) );
BUFX3TS U4921 ( .A(n3963), .Y(n5261) );
BUFX3TS U4922 ( .A(n5169), .Y(n5071) );
NAND2X1TS U4923 ( .A(n5071), .B(n5208), .Y(FPADDSUB__6_net_) );
NAND2X1TS U4924 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n3964), .Y(n3970) );
NAND2X1TS U4925 ( .A(n3971), .B(n3970), .Y(FPMULT_FSM_barrel_shifter_load)
);
NAND2X1TS U4926 ( .A(n3980), .B(n5025), .Y(n851) );
BUFX3TS U4927 ( .A(n5280), .Y(n5236) );
BUFX3TS U4928 ( .A(n5320), .Y(n5295) );
BUFX3TS U4929 ( .A(n5320), .Y(n5296) );
BUFX3TS U4930 ( .A(n5320), .Y(n5297) );
BUFX3TS U4931 ( .A(n5320), .Y(n5298) );
BUFX3TS U4932 ( .A(n5280), .Y(n5237) );
BUFX3TS U4933 ( .A(n5322), .Y(n5312) );
BUFX3TS U4934 ( .A(n5322), .Y(n5313) );
BUFX3TS U4935 ( .A(n5322), .Y(n5314) );
BUFX3TS U4936 ( .A(n5322), .Y(n5316) );
BUFX3TS U4937 ( .A(n5322), .Y(n5315) );
BUFX3TS U4938 ( .A(n3963), .Y(n5246) );
BUFX3TS U4939 ( .A(n5280), .Y(n5241) );
BUFX3TS U4940 ( .A(n5280), .Y(n5244) );
BUFX3TS U4941 ( .A(n5280), .Y(n5242) );
NAND2X1TS U4942 ( .A(n5143), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1033_CI) );
NAND2X1TS U4943 ( .A(n5142), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1034_CI) );
INVX2TS U4944 ( .A(intadd_1035_SUM_0_), .Y(FPADDSUB_Shift_amount_EXP_EW[1])
);
INVX2TS U4945 ( .A(intadd_1035_SUM_1_), .Y(FPADDSUB_Shift_amount_EXP_EW[2])
);
INVX2TS U4946 ( .A(n3968), .Y(n3974) );
INVX2TS U4947 ( .A(intadd_1035_SUM_2_), .Y(FPADDSUB_Shift_amount_EXP_EW[3])
);
INVX2TS U4948 ( .A(n3969), .Y(intadd_1035_CI) );
OAI22X1TS U4949 ( .A0(n910), .A1(n3972), .B0(n3971), .B1(n5112), .Y(
FPMULT_FSM_load_second_step) );
NOR2X1TS U4950 ( .A(n3974), .B(n3973), .Y(FPMULT_FSM_adder_round_norm_load)
);
NOR2X1TS U4951 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_1034_n1), .Y(n5074) );
OR3X1TS U4952 ( .A(FPSENCOS_d_ff2_Y[27]), .B(FPSENCOS_d_ff2_Y[28]), .C(
intadd_1034_n1), .Y(n5073) );
NOR2X1TS U4953 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_1033_n1), .Y(n5077) );
NAND2X1TS U4954 ( .A(FPSENCOS_cont_iter_out[2]), .B(n4976), .Y(n4975) );
NOR2X1TS U4955 ( .A(n5097), .B(n4975), .Y(n3979) );
INVX2TS U4956 ( .A(n1691), .Y(n3975) );
OAI21X1TS U4957 ( .A0(n5020), .A1(n5118), .B0(n3980), .Y(n863) );
INVX2TS U4958 ( .A(Data_2[11]), .Y(n3983) );
AOI22X1TS U4959 ( .A0(n4878), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n4078),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n3982) );
NAND2X1TS U4960 ( .A(n4877), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n3984) );
INVX2TS U4961 ( .A(Data_2[7]), .Y(n3986) );
AOI22X1TS U4962 ( .A0(n4878), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n4078),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n3985) );
NOR2BX2TS U4963 ( .AN(FPADDSUB_bit_shift_SHT2), .B(n3897), .Y(n4130) );
OR2X2TS U4964 ( .A(n4130), .B(n3897), .Y(n4129) );
NAND2X2TS U4965 ( .A(FPADDSUB_bit_shift_SHT2), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4131) );
NOR2X2TS U4966 ( .A(n4131), .B(n5145), .Y(n4298) );
OAI22X1TS U4967 ( .A0(n4132), .A1(n5167), .B0(n3992), .B1(n1103), .Y(n3987)
);
AOI211X2TS U4968 ( .A0(n3897), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n4298),
.C0(n3987), .Y(n4115) );
AOI22X1TS U4969 ( .A0(n3988), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n1152),
.B1(FPADDSUB_Data_array_SWR[35]), .Y(n3990) );
AOI22X1TS U4970 ( .A0(n1155), .A1(FPADDSUB_Data_array_SWR[31]), .B0(n1158),
.B1(FPADDSUB_Data_array_SWR[27]), .Y(n3989) );
OAI211X1TS U4971 ( .A0(n4115), .A1(n4158), .B0(n3990), .C0(n3989), .Y(n4116)
);
AOI21X1TS U4972 ( .A0(n4116), .A1(n1161), .B0(n4136), .Y(n3991) );
OAI22X1TS U4973 ( .A0(n4132), .A1(n5176), .B0(n3992), .B1(n1102), .Y(n3993)
);
AOI211X2TS U4974 ( .A0(n3897), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n4298),
.C0(n3993), .Y(n4146) );
AOI22X1TS U4975 ( .A0(n1158), .A1(FPADDSUB_Data_array_SWR[26]), .B0(n3988),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n3995) );
AOI22X1TS U4976 ( .A0(n1155), .A1(FPADDSUB_Data_array_SWR[30]), .B0(n1153),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n3994) );
OAI211X1TS U4977 ( .A0(n4146), .A1(n1095), .B0(n3995), .C0(n3994), .Y(n3999)
);
AOI21X1TS U4978 ( .A0(n3999), .A1(n1161), .B0(n4136), .Y(n3996) );
AOI21X1TS U4979 ( .A0(FPADDSUB_left_right_SHT2), .A1(n3999), .B0(n3998), .Y(
n4000) );
INVX2TS U4980 ( .A(n4786), .Y(n5034) );
NAND2X1TS U4981 ( .A(n4874), .B(n4873), .Y(n4002) );
AOI22X1TS U4982 ( .A0(n1182), .A1(n4002), .B0(begin_operation), .B1(n5019),
.Y(n5031) );
INVX2TS U4983 ( .A(n5032), .Y(n4003) );
INVX2TS U4984 ( .A(Data_2[3]), .Y(n4006) );
AOI22X1TS U4985 ( .A0(n4004), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n4078),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n4005) );
NAND2X1TS U4986 ( .A(n4922), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n4056) );
INVX2TS U4987 ( .A(Data_2[5]), .Y(n4008) );
AOI22X1TS U4988 ( .A0(n4878), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n3981),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n4007) );
NAND2X1TS U4989 ( .A(n3949), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n4059) );
INVX2TS U4990 ( .A(n4009), .Y(n4011) );
NAND2X1TS U4991 ( .A(n4011), .B(n4010), .Y(n4012) );
XOR2X1TS U4992 ( .A(n4013), .B(n4012), .Y(n4034) );
INVX2TS U4993 ( .A(n4021), .Y(n4023) );
NAND2X1TS U4994 ( .A(n4028), .B(n4027), .Y(n4030) );
NOR4X1TS U4995 ( .A(n4034), .B(n4033), .C(n4032), .D(n4031), .Y(n5212) );
AOI222X1TS U4996 ( .A0(n4929), .A1(Data_2[30]), .B0(n4069), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .C0(FPSENCOS_d_ff3_sh_y_out[30]), .C1(
n4608), .Y(n4035) );
INVX2TS U4997 ( .A(n4035), .Y(add_subt_data2[30]) );
AOI21X1TS U4998 ( .A0(n5127), .A1(FPADDSUB_Raw_mant_NRM_SWR[0]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4037) );
AOI211X2TS U4999 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n4041), .B0(n4040), .C0(n4039), .Y(n4095) );
OAI22X1TS U5000 ( .A0(n4044), .A1(n4043), .B0(n4042), .B1(n4283), .Y(n4045)
);
AOI21X1TS U5001 ( .A0(n4046), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n4045),
.Y(n4047) );
INVX2TS U5002 ( .A(Data_2[19]), .Y(n4050) );
AOI22X1TS U5003 ( .A0(n4972), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n4069),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n4049) );
NAND2X1TS U5004 ( .A(n4877), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n4051) );
INVX2TS U5005 ( .A(Data_2[22]), .Y(n4053) );
AOI22X1TS U5006 ( .A0(n4964), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n4072),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n4052) );
INVX2TS U5007 ( .A(Data_2[18]), .Y(n4055) );
AOI22X1TS U5008 ( .A0(n4964), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n4069),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n4054) );
NAND2X1TS U5009 ( .A(n4922), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n4062) );
INVX2TS U5010 ( .A(Data_2[16]), .Y(n4058) );
AOI22X1TS U5011 ( .A0(n4964), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n4078),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n4057) );
INVX2TS U5012 ( .A(Data_2[14]), .Y(n4061) );
AOI22X1TS U5013 ( .A0(n4961), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n4078),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n4060) );
INVX2TS U5014 ( .A(Data_2[13]), .Y(n4064) );
AOI22X1TS U5015 ( .A0(n4961), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n4078),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n4063) );
INVX2TS U5016 ( .A(Data_2[28]), .Y(n4066) );
AOI22X1TS U5017 ( .A0(n4972), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n4072),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n4065) );
INVX2TS U5018 ( .A(Data_2[20]), .Y(n4068) );
AOI22X1TS U5019 ( .A0(n4961), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n4072),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n4067) );
INVX2TS U5020 ( .A(Data_2[29]), .Y(n4071) );
AOI22X1TS U5021 ( .A0(n4972), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n4069),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n4070) );
INVX2TS U5022 ( .A(Data_2[27]), .Y(n4075) );
AOI22X1TS U5023 ( .A0(n4972), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n4072),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n4074) );
INVX2TS U5024 ( .A(Data_2[15]), .Y(n4077) );
AOI22X1TS U5025 ( .A0(n4608), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n4069),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n4076) );
INVX2TS U5026 ( .A(Data_2[17]), .Y(n4081) );
AOI22X1TS U5027 ( .A0(n4964), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n4078),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n4080) );
OR4X2TS U5028 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n4082) );
AND4X1TS U5029 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[0]), .D(
FPMULT_Exp_module_Data_S[1]), .Y(n4084) );
AND4X1TS U5030 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[5]), .C(FPMULT_Exp_module_Data_S[4]), .D(
n4084), .Y(n4085) );
NOR3X1TS U5031 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_Exp_module_Data_S[7]), .C(n4085), .Y(n5341) );
NOR4X1TS U5032 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .D(
n4283), .Y(n4087) );
AOI22X1TS U5033 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(n4087), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n4086), .Y(n4094) );
AOI21X1TS U5034 ( .A0(n4088), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n4089) );
AOI21X1TS U5035 ( .A0(n4090), .A1(n5148), .B0(n4278), .Y(n4093) );
INVX2TS U5036 ( .A(n4293), .Y(n4226) );
NAND2X1TS U5037 ( .A(n4219), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4100) );
NAND2X1TS U5038 ( .A(n5224), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n4099) );
INVX2TS U5039 ( .A(n4293), .Y(n4219) );
AOI22X1TS U5040 ( .A0(n4226), .A1(FPADDSUB_Raw_mant_NRM_SWR[1]), .B0(n1138),
.B1(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n4171) );
NAND2X1TS U5041 ( .A(n4219), .B(FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n4104) );
NAND2X1TS U5042 ( .A(n1137), .B(FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n4103) );
NAND2X1TS U5043 ( .A(n4217), .B(FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n4102) );
AOI22X1TS U5044 ( .A0(n4224), .A1(n4249), .B0(n1138), .B1(
FPADDSUB_Raw_mant_SGF[25]), .Y(n4105) );
OAI21X1TS U5045 ( .A0(n4132), .A1(n5165), .B0(n4131), .Y(n4106) );
AOI22X1TS U5046 ( .A0(n1155), .A1(FPADDSUB_Data_array_SWR[36]), .B0(
FPADDSUB_Data_array_SWR[32]), .B1(n1158), .Y(n4108) );
AOI22X1TS U5047 ( .A0(FPADDSUB_Data_array_SWR[42]), .A1(n3988), .B0(
FPADDSUB_Data_array_SWR[39]), .B1(n1152), .Y(n4107) );
OAI211X1TS U5048 ( .A0(n4155), .A1(n1095), .B0(n4108), .C0(n4107), .Y(n4126)
);
NAND2X1TS U5049 ( .A(n4126), .B(n4306), .Y(n4109) );
AOI22X1TS U5050 ( .A0(n1155), .A1(FPADDSUB_Data_array_SWR[37]), .B0(n1158),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n4111) );
AOI22X1TS U5051 ( .A0(n3988), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n1152),
.B1(FPADDSUB_Data_array_SWR[40]), .Y(n4110) );
OAI211X1TS U5052 ( .A0(n1044), .A1(n1095), .B0(n4111), .C0(n4110), .Y(n4113)
);
AOI21X1TS U5053 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4113), .B0(n3998), .Y(
n4112) );
OAI21X1TS U5054 ( .A0(n4160), .A1(n4115), .B0(n4112), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[17]) );
NAND2X1TS U5055 ( .A(n4113), .B(n4306), .Y(n4114) );
AOI21X1TS U5056 ( .A0(n1163), .A1(n4116), .B0(n3998), .Y(n4117) );
OAI21X1TS U5057 ( .A0(n4160), .A1(n1044), .B0(n4117), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[24]) );
AOI22X1TS U5058 ( .A0(n3988), .A1(n1201), .B0(n1152), .B1(
FPADDSUB_Data_array_SWR[11]), .Y(n4119) );
AOI22X1TS U5059 ( .A0(n1154), .A1(FPADDSUB_Data_array_SWR[33]), .B0(n1157),
.B1(FPADDSUB_Data_array_SWR[29]), .Y(n4118) );
OAI211X1TS U5060 ( .A0(n4128), .A1(n1095), .B0(n4119), .C0(n4118), .Y(n4153)
);
AOI21X1TS U5061 ( .A0(n4153), .A1(n4306), .B0(n4136), .Y(n4120) );
OAI21X1TS U5062 ( .A0(n4132), .A1(n1102), .B0(n4131), .Y(n4121) );
OAI21X1TS U5063 ( .A0(n4132), .A1(n1103), .B0(n4131), .Y(n4122) );
AOI22X1TS U5064 ( .A0(n3988), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n1152),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n4124) );
AOI22X1TS U5065 ( .A0(n1155), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n1158),
.B1(FPADDSUB_Data_array_SWR[31]), .Y(n4123) );
OAI211X1TS U5066 ( .A0(n4292), .A1(n1095), .B0(n4124), .C0(n4123), .Y(n4285)
);
AOI21X1TS U5067 ( .A0(n1163), .A1(n4285), .B0(n3998), .Y(n4125) );
OAI21X1TS U5068 ( .A0(n4160), .A1(n4287), .B0(n4125), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[20]) );
AOI21X1TS U5069 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4126), .B0(n3998), .Y(
n4127) );
OAI21X1TS U5070 ( .A0(n4128), .A1(n4160), .B0(n4127), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[19]) );
OAI21X1TS U5071 ( .A0(n4132), .A1(n5162), .B0(n4131), .Y(n4133) );
AOI22X1TS U5072 ( .A0(n3988), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n1152),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n4135) );
AOI22X1TS U5073 ( .A0(n1154), .A1(FPADDSUB_Data_array_SWR[32]), .B0(n1157),
.B1(FPADDSUB_Data_array_SWR[28]), .Y(n4134) );
OAI211X1TS U5074 ( .A0(n4152), .A1(n4158), .B0(n4135), .C0(n4134), .Y(n4147)
);
AOI21X1TS U5075 ( .A0(n4147), .A1(n1114), .B0(n4136), .Y(n4137) );
OAI21X1TS U5076 ( .A0(n4149), .A1(n4291), .B0(n4137), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[2]) );
AOI22X1TS U5077 ( .A0(n1155), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n1158),
.B1(FPADDSUB_Data_array_SWR[33]), .Y(n4139) );
AOI22X1TS U5078 ( .A0(n3988), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n1152),
.B1(n1201), .Y(n4138) );
OAI211X1TS U5079 ( .A0(n4149), .A1(n1095), .B0(n4139), .C0(n4138), .Y(n4150)
);
NAND2X1TS U5080 ( .A(n4150), .B(n4306), .Y(n4140) );
AOI22X1TS U5081 ( .A0(n1157), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n3988),
.B1(FPADDSUB_Data_array_SWR[45]), .Y(n4142) );
AOI22X1TS U5082 ( .A0(n1154), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n1152),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n4141) );
OAI211X1TS U5083 ( .A0(n1199), .A1(n1095), .B0(n4142), .C0(n4141), .Y(n4144)
);
AOI21X1TS U5084 ( .A0(n1163), .A1(n4144), .B0(n3998), .Y(n4143) );
OAI21X1TS U5085 ( .A0(n4160), .A1(n4146), .B0(n4143), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[16]) );
NAND2X1TS U5086 ( .A(n4144), .B(n4306), .Y(n4145) );
AOI21X1TS U5087 ( .A0(n1163), .A1(n4147), .B0(n3998), .Y(n4148) );
OAI21X1TS U5088 ( .A0(n4160), .A1(n4149), .B0(n4148), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[23]) );
AOI21X1TS U5089 ( .A0(n1163), .A1(n4150), .B0(n3998), .Y(n4151) );
OAI21X1TS U5090 ( .A0(n4160), .A1(n4152), .B0(n4151), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[18]) );
AOI21X1TS U5091 ( .A0(n1162), .A1(n4153), .B0(n3998), .Y(n4154) );
OAI21X1TS U5092 ( .A0(n4160), .A1(n4155), .B0(n4154), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[22]) );
AOI22X1TS U5093 ( .A0(n3988), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n1153),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n4157) );
AOI22X1TS U5094 ( .A0(n1155), .A1(FPADDSUB_Data_array_SWR[34]), .B0(n1158),
.B1(FPADDSUB_Data_array_SWR[30]), .Y(n4156) );
OAI211X1TS U5095 ( .A0(n4287), .A1(n1095), .B0(n4157), .C0(n4156), .Y(n4288)
);
AOI21X1TS U5096 ( .A0(n1162), .A1(n4288), .B0(n3998), .Y(n4159) );
OAI21X1TS U5097 ( .A0(n4160), .A1(n4292), .B0(n4159), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[21]) );
AND4X1TS U5098 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n4161) );
NAND2X1TS U5099 ( .A(n4226), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n4166) );
NAND2X1TS U5100 ( .A(n5224), .B(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n4165) );
NAND2X1TS U5101 ( .A(n4217), .B(FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n4164) );
AND3X2TS U5102 ( .A(n4166), .B(n4165), .C(n4164), .Y(n4246) );
AOI21X1TS U5103 ( .A0(n4221), .A1(n4249), .B0(n4169), .Y(n4170) );
OAI21X1TS U5104 ( .A0(n4171), .A1(n1179), .B0(n4170), .Y(
FPADDSUB_Data_array_SWR[1]) );
NAND2X1TS U5105 ( .A(n4226), .B(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n4174) );
NAND2X1TS U5106 ( .A(n5224), .B(FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n4173) );
NAND2X1TS U5107 ( .A(n4228), .B(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n4172) );
AOI22X1TS U5108 ( .A0(n5223), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n4217), .Y(n4175) );
NAND2X1TS U5109 ( .A(n4219), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n4178) );
NAND2X1TS U5110 ( .A(n4227), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4177) );
NAND2X1TS U5111 ( .A(n4228), .B(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n4176) );
NAND2X1TS U5112 ( .A(n5223), .B(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n4181) );
NAND2X1TS U5113 ( .A(n5224), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n4180) );
NAND2X1TS U5114 ( .A(n4228), .B(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n4179) );
OAI22X1TS U5115 ( .A0(n4840), .A1(n4269), .B0(n4255), .B1(n1175), .Y(n4182)
);
AOI21X1TS U5116 ( .A0(n4221), .A1(n4253), .B0(n4182), .Y(n4183) );
OAI21X1TS U5117 ( .A0(n4257), .A1(n1179), .B0(n4183), .Y(
FPADDSUB_Data_array_SWR[20]) );
AOI22X1TS U5118 ( .A0(n1137), .A1(FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n4217), .Y(n4184) );
NAND2X1TS U5119 ( .A(n4217), .B(FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n4185) );
NAND2X1TS U5120 ( .A(n4226), .B(FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n4190) );
NAND2X1TS U5121 ( .A(n5224), .B(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n4189) );
NAND2X1TS U5122 ( .A(n4217), .B(FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n4188) );
OAI22X1TS U5123 ( .A0(n4242), .A1(n1164), .B0(n4247), .B1(n1175), .Y(n4191)
);
AOI21X1TS U5124 ( .A0(n4221), .A1(n1089), .B0(n4191), .Y(n4192) );
INVX2TS U5125 ( .A(n4249), .Y(n4195) );
OAI22X1TS U5126 ( .A0(n4247), .A1(n1166), .B0(n4246), .B1(n1175), .Y(n4193)
);
AOI21X1TS U5127 ( .A0(n4224), .A1(n1089), .B0(n4193), .Y(n4194) );
OAI21X1TS U5128 ( .A0(n4195), .A1(n1178), .B0(n4194), .Y(
FPADDSUB_Data_array_SWR[3]) );
NAND2X1TS U5129 ( .A(n5223), .B(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n4198) );
NAND2X1TS U5130 ( .A(n5224), .B(FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n4197) );
NAND2X1TS U5131 ( .A(n4228), .B(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n4196) );
OAI22X1TS U5132 ( .A0(n4255), .A1(n1166), .B0(n4257), .B1(n1176), .Y(n4199)
);
OAI21X1TS U5133 ( .A0(n4256), .A1(n1178), .B0(n4200), .Y(
FPADDSUB_Data_array_SWR[19]) );
INVX2TS U5134 ( .A(n4293), .Y(n5223) );
AOI22X1TS U5135 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n1138), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n4217), .Y(n4201) );
AOI222X4TS U5136 ( .A0(n5071), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n4219), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n4227), .Y(n4267) );
NAND2X1TS U5137 ( .A(n5224), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n4203) );
NAND2X1TS U5138 ( .A(n4228), .B(FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n4202) );
AOI21X1TS U5139 ( .A0(n4224), .A1(n4265), .B0(n4205), .Y(n4206) );
OAI21X1TS U5140 ( .A0(n4242), .A1(n1179), .B0(n4206), .Y(
FPADDSUB_Data_array_SWR[7]) );
AOI222X4TS U5141 ( .A0(n5071), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n5223), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n4227), .Y(n4262) );
AOI21X1TS U5142 ( .A0(n4221), .A1(n4265), .B0(n4207), .Y(n4208) );
AOI222X4TS U5143 ( .A0(n5071), .A1(FPADDSUB_DmP_mant_SHT1_SW[14]), .B0(n4227), .B1(FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(
n4226), .Y(n4270) );
AOI22X1TS U5144 ( .A0(n4226), .A1(FPADDSUB_Raw_mant_NRM_SWR[18]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n4217), .Y(n4209) );
OAI2BB1X1TS U5145 ( .A0N(n4227), .A1N(FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(
n4209), .Y(n4259) );
NAND2X1TS U5146 ( .A(n4219), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n4212) );
NAND2X1TS U5147 ( .A(n4228), .B(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n4210) );
OAI22X1TS U5148 ( .A0(n4256), .A1(n4269), .B0(n4261), .B1(n1175), .Y(n4213)
);
AOI21X1TS U5149 ( .A0(n4221), .A1(n4259), .B0(n4213), .Y(n4214) );
OAI21X1TS U5150 ( .A0(n4270), .A1(n1178), .B0(n4214), .Y(
FPADDSUB_Data_array_SWR[16]) );
AOI222X4TS U5151 ( .A0(n5071), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n4227), .B1(FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(
n4226), .Y(n4268) );
OAI22X1TS U5152 ( .A0(n4261), .A1(n1166), .B0(n4270), .B1(n1175), .Y(n4215)
);
AOI21X1TS U5153 ( .A0(n4224), .A1(n4259), .B0(n4215), .Y(n4216) );
OAI21X1TS U5154 ( .A0(n4268), .A1(n1179), .B0(n4216), .Y(
FPADDSUB_Data_array_SWR[15]) );
AOI222X4TS U5155 ( .A0(n5071), .A1(FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n4219), .C0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n1137), .Y(n4263) );
AOI22X1TS U5156 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n1138), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n4217), .Y(n4218) );
AOI222X4TS U5157 ( .A0(n5071), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n4227), .B1(FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(
n4226), .Y(n4275) );
AOI21X1TS U5158 ( .A0(n4221), .A1(n4272), .B0(n4220), .Y(n4222) );
OAI22X1TS U5159 ( .A0(n4275), .A1(n1165), .B0(n4263), .B1(n1175), .Y(n4223)
);
AOI21X1TS U5160 ( .A0(n4224), .A1(n4272), .B0(n4223), .Y(n4225) );
NAND2X1TS U5161 ( .A(n5223), .B(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n4231) );
NAND2X1TS U5162 ( .A(n4227), .B(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n4230) );
NAND2X1TS U5163 ( .A(n4228), .B(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n4229) );
OAI22X1TS U5164 ( .A0(n4839), .A1(n1166), .B0(n4840), .B1(n1175), .Y(n4232)
);
AOI21X1TS U5165 ( .A0(n1177), .A1(n4253), .B0(n4232), .Y(n4233) );
OAI21X1TS U5166 ( .A0(n4841), .A1(n1164), .B0(n4233), .Y(
FPADDSUB_Data_array_SWR[22]) );
OAI22X1TS U5167 ( .A0(n4255), .A1(n4269), .B0(n4257), .B1(n1166), .Y(n4234)
);
AOI21X1TS U5168 ( .A0(n1177), .A1(n4259), .B0(n4234), .Y(n4235) );
OAI21X1TS U5169 ( .A0(n4256), .A1(n1176), .B0(n4235), .Y(
FPADDSUB_Data_array_SWR[18]) );
OAI22X1TS U5170 ( .A0(n4267), .A1(n4269), .B0(n4243), .B1(n1165), .Y(n4236)
);
AOI21X1TS U5171 ( .A0(n1177), .A1(n1089), .B0(n4236), .Y(n4237) );
OAI22X1TS U5172 ( .A0(n4261), .A1(n1164), .B0(n4270), .B1(n1165), .Y(n4238)
);
AOI21X1TS U5173 ( .A0(n1177), .A1(n4272), .B0(n4238), .Y(n4239) );
AOI21X1TS U5174 ( .A0(n1177), .A1(n4265), .B0(n4240), .Y(n4241) );
AOI21X1TS U5175 ( .A0(n4273), .A1(n1089), .B0(n4244), .Y(n4245) );
OAI22X1TS U5176 ( .A0(n4247), .A1(n1164), .B0(n4246), .B1(n1166), .Y(n4248)
);
AOI21X1TS U5177 ( .A0(n4273), .A1(n4249), .B0(n4248), .Y(n4250) );
OAI21X1TS U5178 ( .A0(n4251), .A1(n1178), .B0(n4250), .Y(
FPADDSUB_Data_array_SWR[2]) );
OAI22X1TS U5179 ( .A0(n4839), .A1(n4269), .B0(n4840), .B1(n1165), .Y(n4252)
);
AOI21X1TS U5180 ( .A0(n4273), .A1(n4253), .B0(n4252), .Y(n4254) );
OAI21X1TS U5181 ( .A0(n4255), .A1(n1178), .B0(n4254), .Y(
FPADDSUB_Data_array_SWR[21]) );
OAI22X1TS U5182 ( .A0(n4257), .A1(n4269), .B0(n4256), .B1(n1166), .Y(n4258)
);
AOI21X1TS U5183 ( .A0(n4273), .A1(n4259), .B0(n4258), .Y(n4260) );
OAI21X1TS U5184 ( .A0(n4261), .A1(n1179), .B0(n4260), .Y(
FPADDSUB_Data_array_SWR[17]) );
AOI21X1TS U5185 ( .A0(n4273), .A1(n4265), .B0(n4264), .Y(n4266) );
OAI22X1TS U5186 ( .A0(n4270), .A1(n1164), .B0(n4268), .B1(n1166), .Y(n4271)
);
AOI21X1TS U5187 ( .A0(n4273), .A1(n4272), .B0(n4271), .Y(n4274) );
NAND2X1TS U5188 ( .A(n4285), .B(n1114), .Y(n4286) );
NAND2X1TS U5189 ( .A(n4288), .B(n4306), .Y(n4290) );
OAI211X1TS U5190 ( .A0(n4292), .A1(n4291), .B0(n4290), .C0(n4289), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[4]) );
OAI21XLTS U5191 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n1034), .B0(n4293),
.Y(n810) );
NOR3XLTS U5192 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n1105), .Y(FPSENCOS_enab_d_ff4_Xn) );
NOR3XLTS U5193 ( .A(FPSENCOS_cont_var_out[1]), .B(n5117), .C(n1105), .Y(
FPSENCOS_enab_d_ff4_Yn) );
NOR2X1TS U5194 ( .A(n5281), .B(n4294), .Y(n4868) );
NAND2X1TS U5195 ( .A(n4868), .B(n1105), .Y(n5036) );
INVX2TS U5196 ( .A(n5036), .Y(n5035) );
AOI22X1TS U5197 ( .A0(n1154), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n1157),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n4296) );
AOI211X1TS U5198 ( .A0(FPADDSUB_Data_array_SWR[42]), .A1(n1153), .B0(n4303),
.C0(n4297), .Y(n4310) );
AOI211X1TS U5199 ( .A0(n1153), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n4305),
.C0(n4299), .Y(n4309) );
MXI2X1TS U5200 ( .A(n4310), .B(n4309), .S0(n1114), .Y(n5133) );
AOI22X1TS U5201 ( .A0(n1154), .A1(n1201), .B0(n1157), .B1(
FPADDSUB_Data_array_SWR[11]), .Y(n4300) );
AOI211X1TS U5202 ( .A0(n1153), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n4303),
.C0(n4302), .Y(n4308) );
AOI211X1TS U5203 ( .A0(FPADDSUB_Data_array_SWR[46]), .A1(n1153), .B0(n4305),
.C0(n4304), .Y(n4307) );
MXI2X1TS U5204 ( .A(n4308), .B(n4307), .S0(n1114), .Y(n5134) );
MXI2X1TS U5205 ( .A(n4308), .B(n4307), .S0(n1162), .Y(n5137) );
XNOR2X1TS U5206 ( .A(DP_OP_234J307_126_8543_n1), .B(n1080), .Y(
FPMULT_Exp_module_Overflow_A) );
NOR3BX1TS U5207 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n4311) );
XOR2X1TS U5208 ( .A(n1128), .B(n4311), .Y(DP_OP_234J307_126_8543_n15) );
OAI2BB1X1TS U5209 ( .A0N(FPMULT_Op_MY[29]), .A1N(n5119), .B0(n4318), .Y(
n4312) );
XOR2X1TS U5210 ( .A(n1128), .B(n4312), .Y(DP_OP_234J307_126_8543_n16) );
OAI2BB1X1TS U5211 ( .A0N(FPMULT_Op_MY[28]), .A1N(n5119), .B0(n4318), .Y(
n4313) );
XOR2X1TS U5212 ( .A(n1128), .B(n4313), .Y(DP_OP_234J307_126_8543_n17) );
OAI2BB1X1TS U5213 ( .A0N(FPMULT_Op_MY[27]), .A1N(n5119), .B0(n4318), .Y(
n4314) );
XOR2X1TS U5214 ( .A(n1128), .B(n4314), .Y(DP_OP_234J307_126_8543_n18) );
OAI2BB1X1TS U5215 ( .A0N(FPMULT_Op_MY[26]), .A1N(n5119), .B0(n4318), .Y(
n4315) );
XOR2X1TS U5216 ( .A(n1128), .B(n4315), .Y(DP_OP_234J307_126_8543_n19) );
OAI2BB1X1TS U5217 ( .A0N(FPMULT_Op_MY[25]), .A1N(n5119), .B0(n4318), .Y(
n4316) );
XOR2X1TS U5218 ( .A(n1128), .B(n4316), .Y(DP_OP_234J307_126_8543_n20) );
OAI2BB1X1TS U5219 ( .A0N(FPMULT_Op_MY[24]), .A1N(n5119), .B0(n4318), .Y(
n4317) );
XOR2X1TS U5220 ( .A(n1127), .B(n4317), .Y(DP_OP_234J307_126_8543_n21) );
XOR2X1TS U5221 ( .A(n1127), .B(n4320), .Y(DP_OP_234J307_126_8543_n22) );
NOR2BX1TS U5222 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4321) );
XOR2X1TS U5223 ( .A(n1034), .B(n4321), .Y(DP_OP_26J307_123_9022_n14) );
NOR2BX1TS U5224 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4322) );
XOR2X1TS U5225 ( .A(n1034), .B(n4322), .Y(DP_OP_26J307_123_9022_n15) );
NOR2BX1TS U5226 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4323) );
XOR2X1TS U5227 ( .A(n1034), .B(n4323), .Y(DP_OP_26J307_123_9022_n16) );
NOR2BX1TS U5228 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4324) );
XOR2X1TS U5229 ( .A(n1120), .B(n4324), .Y(DP_OP_26J307_123_9022_n17) );
NOR2X1TS U5230 ( .A(n107), .B(FPMULT_FSM_adder_round_norm_load), .Y(n4327)
);
NAND2X1TS U5231 ( .A(n4326), .B(n4325), .Y(n4328) );
OAI2BB1X1TS U5232 ( .A0N(FPMULT_FSM_selector_B[1]), .A1N(n4327), .B0(n4328),
.Y(n829) );
OAI2BB1X1TS U5233 ( .A0N(FPMULT_FSM_selector_B[0]), .A1N(n4328), .B0(n4327),
.Y(n830) );
MX2X1TS U5234 ( .A(FPADDSUB_OP_FLAG_SHT2), .B(FPADDSUB_OP_FLAG_SHT1), .S0(
busy), .Y(n813) );
INVX2TS U5235 ( .A(n4329), .Y(n4560) );
AOI21X1TS U5236 ( .A0(n4560), .A1(n4331), .B0(n4330), .Y(n4357) );
NAND2X1TS U5237 ( .A(n4334), .B(n4333), .Y(n4350) );
XNOR2X1TS U5238 ( .A(n4335), .B(n4350), .Y(n4353) );
NAND2X1TS U5239 ( .A(n5129), .B(n5103), .Y(n4601) );
NAND2X1TS U5240 ( .A(n5128), .B(FPADDSUB_DMP_SFG[0]), .Y(n4336) );
NOR2X1TS U5241 ( .A(n5122), .B(FPADDSUB_DMP_SFG[2]), .Y(n4339) );
NOR2X1TS U5242 ( .A(n4585), .B(n4339), .Y(n4341) );
NAND2X1TS U5243 ( .A(n5126), .B(FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1003) );
NAND2X1TS U5244 ( .A(n5122), .B(FPADDSUB_DMP_SFG[2]), .Y(n4338) );
NOR2X1TS U5245 ( .A(n5121), .B(FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1024) );
NOR2X1TS U5246 ( .A(n1013), .B(FPADDSUB_DMP_SFG[5]), .Y(n4362) );
NOR2X1TS U5247 ( .A(n5120), .B(FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1006) );
NAND2X1TS U5248 ( .A(n4360), .B(n4347), .Y(n4349) );
NAND2X1TS U5249 ( .A(n5125), .B(FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1010) );
NAND2X1TS U5250 ( .A(n1025), .B(FPADDSUB_DMP_SFG[4]), .Y(n4342) );
NAND2X1TS U5251 ( .A(n5124), .B(FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1012) );
NAND2X1TS U5252 ( .A(n1007), .B(FPADDSUB_DMP_SFG[6]), .Y(n4344) );
AOI21X1TS U5253 ( .A0(n4359), .A1(n4347), .B0(n4346), .Y(n4348) );
INVX2TS U5254 ( .A(n4394), .Y(n4540) );
INVX2TS U5255 ( .A(n4350), .Y(n4351) );
XOR2X1TS U5256 ( .A(n4540), .B(n4351), .Y(n4352) );
NAND2X1TS U5257 ( .A(n4356), .B(n4355), .Y(n4363) );
XOR2X1TS U5258 ( .A(n4357), .B(n4363), .Y(n4367) );
INVX2TS U5259 ( .A(n4358), .Y(n4576) );
AOI21X1TS U5260 ( .A0(n4576), .A1(n4360), .B0(n4359), .Y(n4554) );
INVX2TS U5261 ( .A(n4363), .Y(n4364) );
XNOR2X1TS U5262 ( .A(n4365), .B(n4364), .Y(n4366) );
INVX2TS U5263 ( .A(n4368), .Y(n4537) );
NAND2X1TS U5264 ( .A(n4373), .B(n4372), .Y(n4379) );
XNOR2X1TS U5265 ( .A(n4374), .B(n4379), .Y(n4383) );
NAND2X1TS U5266 ( .A(n5123), .B(FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1017) );
NAND2X1TS U5267 ( .A(n1029), .B(FPADDSUB_DMP_SFG[8]), .Y(n4375) );
INVX2TS U5268 ( .A(n4379), .Y(n4380) );
XNOR2X1TS U5269 ( .A(n4381), .B(n4380), .Y(n4382) );
NAND2X1TS U5270 ( .A(n4386), .B(n4385), .Y(n4395) );
XOR2X1TS U5271 ( .A(n4387), .B(n4395), .Y(n4398) );
NOR2X2TS U5272 ( .A(n4388), .B(n4390), .Y(n4393) );
NAND2X1TS U5273 ( .A(n5100), .B(FPADDSUB_DMP_SFG[10]), .Y(n4389) );
AOI21X4TS U5274 ( .A0(n4394), .A1(n4393), .B0(n4392), .Y(n4418) );
INVX2TS U5275 ( .A(n4395), .Y(n4396) );
XOR2X1TS U5276 ( .A(n4418), .B(n4396), .Y(n4397) );
NAND2X1TS U5277 ( .A(n4401), .B(n4400), .Y(n4407) );
XNOR2X1TS U5278 ( .A(n4402), .B(n4407), .Y(n4411) );
INVX2TS U5279 ( .A(n4407), .Y(n4408) );
XNOR2X1TS U5280 ( .A(n4409), .B(n4408), .Y(n4410) );
NAND2X1TS U5281 ( .A(n4414), .B(n4413), .Y(n4433) );
XOR2X1TS U5282 ( .A(n4415), .B(n4433), .Y(n4436) );
NAND2X1TS U5283 ( .A(n5101), .B(FPADDSUB_DMP_SFG[11]), .Y(n4416) );
NAND2X1TS U5284 ( .A(n5105), .B(FPADDSUB_DMP_SFG[13]), .Y(n4421) );
OR2X1TS U5285 ( .A(n5132), .B(FPADDSUB_DMP_SFG[14]), .Y(n4424) );
AOI21X4TS U5286 ( .A0(n4515), .A1(n4424), .B0(n4423), .Y(n4507) );
NAND2X1TS U5287 ( .A(n5146), .B(FPADDSUB_DMP_SFG[15]), .Y(n4425) );
OR2X1TS U5288 ( .A(n5147), .B(FPADDSUB_DMP_SFG[16]), .Y(n4428) );
NAND2X1TS U5289 ( .A(n5164), .B(FPADDSUB_DMP_SFG[17]), .Y(n4429) );
OR2X1TS U5290 ( .A(n5166), .B(FPADDSUB_DMP_SFG[18]), .Y(n4432) );
INVX2TS U5291 ( .A(n4433), .Y(n4434) );
XOR2X1TS U5292 ( .A(n4459), .B(n4434), .Y(n4435) );
NAND2X1TS U5293 ( .A(n4438), .B(n4437), .Y(n4440) );
XNOR2X1TS U5294 ( .A(n4439), .B(n4440), .Y(n4444) );
INVX2TS U5295 ( .A(n4440), .Y(n4441) );
XNOR2X1TS U5296 ( .A(n4442), .B(n4441), .Y(n4443) );
INVX2TS U5297 ( .A(n4445), .Y(n4447) );
NAND2X1TS U5298 ( .A(n4447), .B(n4446), .Y(n4449) );
XOR2X1TS U5299 ( .A(n4448), .B(n4449), .Y(n4453) );
INVX2TS U5300 ( .A(n4449), .Y(n4450) );
XOR2X1TS U5301 ( .A(n4451), .B(n4450), .Y(n4452) );
NAND2X1TS U5302 ( .A(n4455), .B(n4454), .Y(n4460) );
XNOR2X1TS U5303 ( .A(n4456), .B(n4460), .Y(n4464) );
NAND2X1TS U5304 ( .A(n5163), .B(FPADDSUB_DMP_SFG[19]), .Y(n4457) );
INVX2TS U5305 ( .A(n4460), .Y(n4461) );
XNOR2X1TS U5306 ( .A(n4471), .B(n4461), .Y(n4463) );
INVX2TS U5307 ( .A(n4465), .Y(n4467) );
NAND2X1TS U5308 ( .A(n4467), .B(n4466), .Y(n4472) );
XOR2X1TS U5309 ( .A(n4468), .B(n4472), .Y(n4475) );
INVX2TS U5310 ( .A(n4472), .Y(n4473) );
XOR2X1TS U5311 ( .A(n4481), .B(n4473), .Y(n4474) );
BUFX3TS U5312 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n4555) );
NAND2X1TS U5313 ( .A(n4477), .B(n4476), .Y(n4482) );
XNOR2X1TS U5314 ( .A(n4478), .B(n4482), .Y(n4485) );
NAND2X1TS U5315 ( .A(n5173), .B(FPADDSUB_DMP_SFG[21]), .Y(n4479) );
INVX2TS U5316 ( .A(n4482), .Y(n4483) );
XOR2X1TS U5317 ( .A(n4486), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n4492) );
OR2X1TS U5318 ( .A(n5174), .B(FPADDSUB_DMP_SFG[22]), .Y(n4488) );
AOI21X1TS U5319 ( .A0(n4489), .A1(n4488), .B0(n4487), .Y(n4490) );
XOR2X1TS U5320 ( .A(n4490), .B(n5207), .Y(n4491) );
NAND2X1TS U5321 ( .A(n4494), .B(n4493), .Y(n4496) );
XNOR2X1TS U5322 ( .A(n4495), .B(n4496), .Y(n4500) );
INVX2TS U5323 ( .A(n4496), .Y(n4497) );
XNOR2X1TS U5324 ( .A(n4498), .B(n4497), .Y(n4499) );
NAND2X1TS U5325 ( .A(n4503), .B(n4502), .Y(n4505) );
XOR2X1TS U5326 ( .A(n4504), .B(n4505), .Y(n4509) );
INVX2TS U5327 ( .A(n4505), .Y(n4506) );
XOR2X1TS U5328 ( .A(n4507), .B(n4506), .Y(n4508) );
NAND2X1TS U5329 ( .A(n4511), .B(n4510), .Y(n4513) );
XNOR2X1TS U5330 ( .A(n4512), .B(n4513), .Y(n4517) );
INVX2TS U5331 ( .A(n4513), .Y(n4514) );
XNOR2X1TS U5332 ( .A(n4515), .B(n4514), .Y(n4516) );
NAND2X1TS U5333 ( .A(n4520), .B(n4519), .Y(n4522) );
XOR2X1TS U5334 ( .A(n4521), .B(n4522), .Y(n4526) );
INVX2TS U5335 ( .A(n4522), .Y(n4523) );
XOR2X1TS U5336 ( .A(n4524), .B(n4523), .Y(n4525) );
NAND2X1TS U5337 ( .A(n4528), .B(n4527), .Y(n4530) );
XNOR2X1TS U5338 ( .A(n4529), .B(n4530), .Y(n4534) );
INVX2TS U5339 ( .A(n4530), .Y(n4531) );
XNOR2X1TS U5340 ( .A(n4532), .B(n4531), .Y(n4533) );
NAND2X1TS U5341 ( .A(n4536), .B(n4535), .Y(n4541) );
XOR2X1TS U5342 ( .A(n4537), .B(n4541), .Y(n4545) );
INVX2TS U5343 ( .A(n4541), .Y(n4542) );
XNOR2X1TS U5344 ( .A(n4543), .B(n4542), .Y(n4544) );
INVX2TS U5345 ( .A(n4546), .Y(n4559) );
AOI21X1TS U5346 ( .A0(n4560), .A1(n4559), .B0(n4547), .Y(n4551) );
NAND2X1TS U5347 ( .A(n4550), .B(n4549), .Y(n4552) );
XOR2X1TS U5348 ( .A(n4551), .B(n4552), .Y(n4557) );
INVX2TS U5349 ( .A(n4552), .Y(n4553) );
XOR2X1TS U5350 ( .A(n4554), .B(n4553), .Y(n4556) );
NAND2X1TS U5351 ( .A(n4559), .B(n4558), .Y(n4564) );
XNOR2X1TS U5352 ( .A(n4560), .B(n4564), .Y(n4568) );
AOI21X1TS U5353 ( .A0(n4576), .A1(n4563), .B0(n953), .Y(n4566) );
INVX2TS U5354 ( .A(n4564), .Y(n4565) );
XOR2X1TS U5355 ( .A(n4566), .B(n4565), .Y(n4567) );
INVX2TS U5356 ( .A(n4569), .Y(n4582) );
NAND2X1TS U5357 ( .A(n4572), .B(n4571), .Y(n4574) );
XNOR2X1TS U5358 ( .A(n4573), .B(n4574), .Y(n4578) );
INVX2TS U5359 ( .A(n4574), .Y(n4575) );
XNOR2X1TS U5360 ( .A(n4576), .B(n4575), .Y(n4577) );
NAND2X1TS U5361 ( .A(n4581), .B(n4580), .Y(n4586) );
XOR2X1TS U5362 ( .A(n4582), .B(n4586), .Y(n4590) );
INVX2TS U5363 ( .A(n4583), .Y(n4596) );
INVX2TS U5364 ( .A(n4586), .Y(n4587) );
XNOR2X1TS U5365 ( .A(n4588), .B(n4587), .Y(n4589) );
NAND2X1TS U5366 ( .A(n4593), .B(n4592), .Y(n4594) );
XOR2X1TS U5367 ( .A(n4594), .B(n4599), .Y(n4598) );
INVX2TS U5368 ( .A(n4594), .Y(n4595) );
XOR2X1TS U5369 ( .A(n4596), .B(n4595), .Y(n4597) );
OR2X1TS U5370 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n4600) );
XOR2X1TS U5371 ( .A(n4603), .B(n4601), .Y(n4602) );
XNOR2X1TS U5372 ( .A(FPADDSUB_N60), .B(n5103), .Y(n4605) );
NOR2BX1TS U5373 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n5338), .Y(
FPADDSUB_formatted_number_W[30]) );
NOR2X1TS U5374 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .Y(n4787) );
BUFX3TS U5375 ( .A(n4843), .Y(n4845) );
XOR2X1TS U5376 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(FPADDSUB_DmP_EXP_EWSW[27]), .Y(n4606) );
NOR2BX1TS U5377 ( .AN(operation[0]), .B(n4929), .Y(n5344) );
AOI2BB2XLTS U5378 ( .B0(FPSENCOS_cont_var_out[0]), .B1(
FPSENCOS_d_ff3_sign_out), .A0N(FPSENCOS_d_ff3_sign_out), .A1N(
FPSENCOS_cont_var_out[0]), .Y(n4607) );
AOI222X1TS U5379 ( .A0(n4929), .A1(Data_2[31]), .B0(n4069), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .C0(FPSENCOS_d_ff3_sh_y_out[31]), .C1(
n4608), .Y(n4609) );
INVX2TS U5380 ( .A(n4609), .Y(n4610) );
XNOR2X1TS U5381 ( .A(n4611), .B(n4610), .Y(n5213) );
AOI22X1TS U5382 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n5193), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n4612), .Y(n4616) );
OAI21X1TS U5383 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n5197), .B0(n4613), .Y(
n4674) );
NOR3X1TS U5384 ( .A(n5130), .B(n4617), .C(FPADDSUB_intDY_EWSW[28]), .Y(n4618) );
INVX2TS U5385 ( .A(FPADDSUB_intDX_EWSW[10]), .Y(n4817) );
NOR2X1TS U5386 ( .A(n5190), .B(FPADDSUB_intDX_EWSW[11]), .Y(n4637) );
AOI21X1TS U5387 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n4817), .B0(n4637), .Y(
n4642) );
INVX2TS U5388 ( .A(FPADDSUB_intDX_EWSW[5]), .Y(n4823) );
OAI2BB1X1TS U5389 ( .A0N(n4823), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n4622) );
OAI22X1TS U5390 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4622), .B0(n4823), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n4634) );
INVX2TS U5391 ( .A(FPADDSUB_intDX_EWSW[7]), .Y(n4827) );
OAI2BB1X1TS U5392 ( .A0N(n4827), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n4623) );
OAI22X1TS U5393 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n4623), .B0(n4827), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n4633) );
INVX2TS U5394 ( .A(FPADDSUB_intDX_EWSW[4]), .Y(n4822) );
INVX2TS U5395 ( .A(FPADDSUB_intDY_EWSW[3]), .Y(n4628) );
OAI2BB2XLTS U5396 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n4624), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n5196), .Y(n4626) );
INVX2TS U5397 ( .A(FPADDSUB_intDX_EWSW[6]), .Y(n4824) );
AOI22X1TS U5398 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n4827), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n4824), .Y(n4631) );
OAI32X1TS U5399 ( .A0(n4634), .A1(n4633), .A2(n4632), .B0(n4631), .B1(n4633),
.Y(n4653) );
INVX2TS U5400 ( .A(FPADDSUB_intDY_EWSW[12]), .Y(n4828) );
INVX2TS U5401 ( .A(FPADDSUB_intDY_EWSW[15]), .Y(n4645) );
AOI22X1TS U5402 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n5190), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n4638), .Y(n4644) );
AOI21X1TS U5403 ( .A0(n4641), .A1(n4640), .B0(n4652), .Y(n4643) );
AOI211X1TS U5404 ( .A0(n4650), .A1(n4649), .B0(n4648), .C0(n4647), .Y(n4651)
);
INVX2TS U5405 ( .A(FPADDSUB_intDX_EWSW[16]), .Y(n4829) );
INVX2TS U5406 ( .A(FPADDSUB_intDY_EWSW[23]), .Y(n4666) );
OAI211X4TS U5407 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n5189), .B0(n4689),
.C0(n4655), .Y(n4664) );
OAI21X1TS U5408 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n5195), .B0(n4661), .Y(
n4665) );
AOI211X1TS U5409 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n4829), .B0(n4664),
.C0(n4665), .Y(n4656) );
AOI22X1TS U5410 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n5192), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n4660), .Y(n4663) );
OAI32X1TS U5411 ( .A0(n4665), .A1(n4664), .A2(n4663), .B0(n4662), .B1(n4664),
.Y(n4669) );
AOI22X1TS U5412 ( .A0(n5111), .A1(FPADDSUB_intDX_EWSW[29]), .B0(n1109), .B1(
FPADDSUB_intDY_EWSW[18]), .Y(n4680) );
AOI22X1TS U5413 ( .A0(n5157), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n5154), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n4681) );
AOI22X1TS U5414 ( .A0(n1051), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n1111), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n4682) );
AOI22X1TS U5415 ( .A0(n1108), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n1047), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n4683) );
NOR4X1TS U5416 ( .A(n4687), .B(n4686), .C(n4685), .D(n4684), .Y(n4714) );
AOI22X1TS U5417 ( .A0(n5109), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n5153), .B1(
FPADDSUB_intDY_EWSW[4]), .Y(n4688) );
AOI22X1TS U5418 ( .A0(n1107), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n5149), .B1(
FPADDSUB_intDY_EWSW[16]), .Y(n4690) );
AOI22X1TS U5419 ( .A0(n1101), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n954), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n4691) );
OAI221XLTS U5420 ( .A0(n1101), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n954), .B1(
FPADDSUB_intDY_EWSW[8]), .C0(n4691), .Y(n4692) );
NOR4X1TS U5421 ( .A(n4695), .B(n4694), .C(n4693), .D(n4692), .Y(n4713) );
AOI22X1TS U5422 ( .A0(n5158), .A1(FPADDSUB_intDX_EWSW[30]), .B0(n1112), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n4696) );
AOI22X1TS U5423 ( .A0(n1050), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n1110), .B1(
FPADDSUB_intDY_EWSW[24]), .Y(n4697) );
OAI22X1TS U5424 ( .A0(n1099), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n1048), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n4698) );
OAI22X1TS U5425 ( .A0(n5141), .A1(FPADDSUB_intDX_EWSW[12]), .B0(n1097), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n4700) );
OAI22X1TS U5426 ( .A0(n5108), .A1(FPADDSUB_intDY_EWSW[7]), .B0(n1098), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n4701) );
OAI22X1TS U5427 ( .A0(n5140), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n1096), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n4702) );
OAI22X1TS U5428 ( .A0(n1100), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n1049), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n4703) );
NAND4XLTS U5429 ( .A(n4707), .B(n4706), .C(n4705), .D(n4704), .Y(n4708) );
NOR4X1TS U5430 ( .A(n4711), .B(n4710), .C(n4709), .D(n4708), .Y(n4712) );
OAI21X2TS U5433 ( .A0(n4717), .A1(FPMULT_Adder_M_result_A_adder[24]), .B0(
n4719), .Y(n4722) );
XOR2X1TS U5434 ( .A(add_x_69_n37), .B(n5089), .Y(n4723) );
AOI22X1TS U5435 ( .A0(FPMULT_FSM_selector_C), .A1(
FPMULT_Adder_M_result_A_adder[23]), .B0(n4723), .B1(n5152), .Y(n4716)
);
AOI22X1TS U5436 ( .A0(n3934), .A1(n910), .B0(n4722), .B1(n4716), .Y(n5369)
);
AOI22X1TS U5437 ( .A0(n1185), .A1(FPMULT_Adder_M_result_A_adder[22]), .B0(
n1186), .B1(FPMULT_Adder_M_result_A_adder[23]), .Y(n4725) );
XOR2X1TS U5438 ( .A(add_x_69_n47), .B(n5088), .Y(n4726) );
AOI22X1TS U5439 ( .A0(n1189), .A1(n4726), .B0(n1192), .B1(n4723), .Y(n4724)
);
NAND2X1TS U5440 ( .A(n4725), .B(n4724), .Y(n5368) );
AOI22X1TS U5441 ( .A0(n1183), .A1(FPMULT_Adder_M_result_A_adder[21]), .B0(
FPMULT_Adder_M_result_A_adder[22]), .B1(n1187), .Y(n4728) );
XOR2X1TS U5442 ( .A(add_x_69_n53), .B(n5087), .Y(n4729) );
AOI22X1TS U5443 ( .A0(n1189), .A1(n4729), .B0(n4726), .B1(n1193), .Y(n4727)
);
NAND2X1TS U5444 ( .A(n4728), .B(n4727), .Y(n5367) );
AOI22X1TS U5445 ( .A0(n1185), .A1(FPMULT_Add_result[20]), .B0(n1186), .B1(
FPMULT_Adder_M_result_A_adder[21]), .Y(n4731) );
XOR2X1TS U5446 ( .A(add_x_69_n61), .B(n5086), .Y(n4732) );
AOI22X1TS U5447 ( .A0(n1190), .A1(n4732), .B0(n1192), .B1(n4729), .Y(n4730)
);
NAND2X1TS U5448 ( .A(n4731), .B(n4730), .Y(n5366) );
AOI22X1TS U5449 ( .A0(n1184), .A1(FPMULT_Add_result[19]), .B0(n1186), .B1(
FPMULT_Add_result[20]), .Y(n4734) );
XOR2X1TS U5450 ( .A(add_x_69_n67), .B(n5085), .Y(n4735) );
AOI22X1TS U5451 ( .A0(n1191), .A1(n4735), .B0(n1192), .B1(n4732), .Y(n4733)
);
NAND2X1TS U5452 ( .A(n4734), .B(n4733), .Y(n5365) );
AOI22X1TS U5453 ( .A0(n1183), .A1(FPMULT_Add_result[18]), .B0(n1186), .B1(
FPMULT_Add_result[19]), .Y(n4737) );
XOR2X1TS U5454 ( .A(add_x_69_n77), .B(n5084), .Y(n4738) );
AOI22X1TS U5455 ( .A0(n1190), .A1(n4738), .B0(n1194), .B1(n4735), .Y(n4736)
);
NAND2X1TS U5456 ( .A(n4737), .B(n4736), .Y(n5364) );
AOI22X1TS U5457 ( .A0(n1185), .A1(FPMULT_Add_result[17]), .B0(n1186), .B1(
FPMULT_Add_result[18]), .Y(n4740) );
XOR2X1TS U5458 ( .A(add_x_69_n83), .B(n5082), .Y(n4741) );
AOI22X1TS U5459 ( .A0(n1191), .A1(n4741), .B0(n1193), .B1(n4738), .Y(n4739)
);
NAND2X1TS U5460 ( .A(n4740), .B(n4739), .Y(n5363) );
AOI22X1TS U5461 ( .A0(n1183), .A1(FPMULT_Add_result[16]), .B0(n1188), .B1(
FPMULT_Add_result[17]), .Y(n4743) );
XOR2X1TS U5462 ( .A(add_x_69_n91), .B(n5083), .Y(n4744) );
AOI22X1TS U5463 ( .A0(n1190), .A1(n4744), .B0(n1194), .B1(n4741), .Y(n4742)
);
NAND2X1TS U5464 ( .A(n4743), .B(n4742), .Y(n5362) );
AOI22X1TS U5465 ( .A0(n1184), .A1(FPMULT_Add_result[15]), .B0(n1187), .B1(
FPMULT_Add_result[16]), .Y(n4746) );
XOR2X1TS U5466 ( .A(add_x_69_n97), .B(n969), .Y(n4747) );
AOI22X1TS U5467 ( .A0(n1191), .A1(n4747), .B0(n1193), .B1(n4744), .Y(n4745)
);
NAND2X1TS U5468 ( .A(n4746), .B(n4745), .Y(n5361) );
AOI22X1TS U5469 ( .A0(n1183), .A1(FPMULT_Add_result[14]), .B0(n1188), .B1(
FPMULT_Add_result[15]), .Y(n4749) );
XOR2X1TS U5470 ( .A(add_x_69_n106), .B(n5080), .Y(n4750) );
AOI22X1TS U5471 ( .A0(n1190), .A1(n4750), .B0(n1194), .B1(n4747), .Y(n4748)
);
NAND2X1TS U5472 ( .A(n4749), .B(n4748), .Y(n5360) );
AOI22X1TS U5473 ( .A0(n1185), .A1(FPMULT_Add_result[13]), .B0(n1187), .B1(
FPMULT_Add_result[14]), .Y(n4752) );
XOR2X1TS U5474 ( .A(add_x_69_n113), .B(n5081), .Y(n4753) );
AOI22X1TS U5475 ( .A0(n1191), .A1(n4753), .B0(n1193), .B1(n4750), .Y(n4751)
);
NAND2X1TS U5476 ( .A(n4752), .B(n4751), .Y(n5359) );
AOI22X1TS U5477 ( .A0(n1184), .A1(FPMULT_Add_result[12]), .B0(n1188), .B1(
FPMULT_Add_result[13]), .Y(n4755) );
XOR2X1TS U5478 ( .A(add_x_69_n122), .B(n5079), .Y(n4756) );
AOI22X1TS U5479 ( .A0(n1190), .A1(n4756), .B0(n1194), .B1(n4753), .Y(n4754)
);
NAND2X1TS U5480 ( .A(n4755), .B(n4754), .Y(n5358) );
AOI22X1TS U5481 ( .A0(n1185), .A1(FPMULT_Add_result[11]), .B0(n1187), .B1(
FPMULT_Add_result[12]), .Y(n4758) );
AOI22X1TS U5482 ( .A0(n1191), .A1(n4759), .B0(n1193), .B1(n4756), .Y(n4757)
);
NAND2X1TS U5483 ( .A(n4758), .B(n4757), .Y(n5357) );
AOI22X1TS U5484 ( .A0(n1184), .A1(n1198), .B0(n1188), .B1(
FPMULT_Add_result[11]), .Y(n4761) );
XOR2X1TS U5485 ( .A(add_x_69_n134), .B(n5092), .Y(n4762) );
AOI22X1TS U5486 ( .A0(n1189), .A1(n4762), .B0(n1192), .B1(n4759), .Y(n4760)
);
NAND2X1TS U5487 ( .A(n4761), .B(n4760), .Y(n5356) );
AOI22X1TS U5488 ( .A0(n1184), .A1(FPMULT_Add_result[9]), .B0(n1187), .B1(
n1198), .Y(n4764) );
XOR2X1TS U5489 ( .A(add_x_69_n141), .B(n5091), .Y(n4765) );
AOI22X1TS U5490 ( .A0(n1190), .A1(n4765), .B0(n1194), .B1(n4762), .Y(n4763)
);
NAND2X1TS U5491 ( .A(n4764), .B(n4763), .Y(n5355) );
AOI22X1TS U5492 ( .A0(n1185), .A1(FPMULT_Add_result[8]), .B0(n1188), .B1(
FPMULT_Add_result[9]), .Y(n4767) );
XOR2X1TS U5493 ( .A(add_x_69_n150), .B(n5093), .Y(n4768) );
AOI22X1TS U5494 ( .A0(n1190), .A1(n4768), .B0(n1193), .B1(n4765), .Y(n4766)
);
NAND2X1TS U5495 ( .A(n4767), .B(n4766), .Y(n5354) );
AOI22X1TS U5496 ( .A0(n1184), .A1(FPMULT_Add_result[7]), .B0(n1187), .B1(
FPMULT_Add_result[8]), .Y(n4770) );
AOI22X1TS U5497 ( .A0(n1191), .A1(FPMULT_Sgf_operation_Result[30]), .B0(
n1194), .B1(n4768), .Y(n4769) );
NAND2X1TS U5498 ( .A(n4770), .B(n4769), .Y(n5353) );
AOI22X1TS U5499 ( .A0(n1185), .A1(FPMULT_Add_result[6]), .B0(n1188), .B1(
FPMULT_Add_result[7]), .Y(n4772) );
XNOR2X1TS U5500 ( .A(n5094), .B(n5095), .Y(n4773) );
AOI22X1TS U5501 ( .A0(n1189), .A1(n4773), .B0(n1193), .B1(
FPMULT_Sgf_operation_Result[30]), .Y(n4771) );
NAND2X1TS U5502 ( .A(n4772), .B(n4771), .Y(n5352) );
AOI22X1TS U5503 ( .A0(n1184), .A1(FPMULT_Add_result[5]), .B0(n1187), .B1(
FPMULT_Add_result[6]), .Y(n4775) );
AOI22X1TS U5504 ( .A0(n1191), .A1(FPMULT_Sgf_operation_Result[28]), .B0(
n1192), .B1(n4773), .Y(n4774) );
NAND2X1TS U5505 ( .A(n4775), .B(n4774), .Y(n5351) );
AOI22X1TS U5506 ( .A0(n1185), .A1(FPMULT_Add_result[4]), .B0(n1188), .B1(
FPMULT_Add_result[5]), .Y(n4777) );
AOI22X1TS U5507 ( .A0(n1190), .A1(FPMULT_Sgf_operation_Result[27]), .B0(
n1194), .B1(FPMULT_Sgf_operation_Result[28]), .Y(n4776) );
NAND2X1TS U5508 ( .A(n4777), .B(n4776), .Y(n5350) );
AOI22X1TS U5509 ( .A0(n1183), .A1(FPMULT_Add_result[3]), .B0(n1186), .B1(
FPMULT_Add_result[4]), .Y(n4779) );
AOI22X1TS U5510 ( .A0(n1189), .A1(FPMULT_Sgf_operation_Result[26]), .B0(
n1192), .B1(FPMULT_Sgf_operation_Result[27]), .Y(n4778) );
NAND2X1TS U5511 ( .A(n4779), .B(n4778), .Y(n5349) );
AOI22X1TS U5512 ( .A0(n1183), .A1(FPMULT_Add_result[2]), .B0(n1186), .B1(
FPMULT_Add_result[3]), .Y(n4781) );
AOI22X1TS U5513 ( .A0(n1189), .A1(FPMULT_P_Sgf[25]), .B0(n1192), .B1(
FPMULT_Sgf_operation_Result[26]), .Y(n4780) );
NAND2X1TS U5514 ( .A(n4781), .B(n4780), .Y(n5348) );
AOI22X1TS U5515 ( .A0(n1183), .A1(FPMULT_Add_result[1]), .B0(n1186), .B1(
FPMULT_Add_result[2]), .Y(n4783) );
AOI22X1TS U5516 ( .A0(n1189), .A1(FPMULT_P_Sgf[24]), .B0(n1192), .B1(
FPMULT_P_Sgf[25]), .Y(n4782) );
NAND2X1TS U5517 ( .A(n4783), .B(n4782), .Y(n5347) );
AOI22X1TS U5518 ( .A0(n1184), .A1(FPMULT_Add_result[0]), .B0(n1188), .B1(
FPMULT_Add_result[1]), .Y(n4785) );
AOI22X1TS U5519 ( .A0(n1191), .A1(FPMULT_P_Sgf[23]), .B0(n1194), .B1(
FPMULT_P_Sgf[24]), .Y(n4784) );
NAND2X1TS U5520 ( .A(n4785), .B(n4784), .Y(n5346) );
AOI22X1TS U5521 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n4786), .B1(n1106),
.Y(n5345) );
XNOR2X1TS U5522 ( .A(Data_2[31]), .B(Data_1[31]), .Y(n5214) );
AOI32X1TS U5523 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n4788), .A2(n5118),
.B0(FPSENCOS_cont_iter_out[2]), .B1(n4788), .Y(
FPSENCOS_data_out_LUT[4]) );
OAI22X1TS U5524 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n4975), .B0(
FPSENCOS_cont_iter_out[2]), .B1(n4976), .Y(FPSENCOS_data_out_LUT[25])
);
NOR4X1TS U5525 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n4795) );
NOR4X1TS U5526 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n4794) );
NOR4X1TS U5527 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n4792) );
NOR4X1TS U5528 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n4790) );
NOR4X1TS U5529 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n4789) );
AND4X1TS U5530 ( .A(n4792), .B(n4791), .C(n4790), .D(n4789), .Y(n4793) );
NOR4BX1TS U5531 ( .AN(n1200), .B(dataB[28]), .C(operation_reg_0_), .D(
dataB[23]), .Y(n4800) );
NOR4X1TS U5532 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n4799) );
NAND4XLTS U5533 ( .A(dataA[30]), .B(n1195), .C(n1196), .D(dataA[26]), .Y(
n4797) );
NAND4XLTS U5534 ( .A(dataA[29]), .B(dataA[23]), .C(n1197), .D(dataA[24]),
.Y(n4796) );
OR3X1TS U5535 ( .A(n5328), .B(n4797), .C(n4796), .Y(n4801) );
NOR3X1TS U5536 ( .A(dataB[25]), .B(dataB[31]), .C(n4801), .Y(n4798) );
NOR4X1TS U5537 ( .A(dataA[30]), .B(n1195), .C(n1196), .D(dataA[26]), .Y(
n4804) );
NOR4X1TS U5538 ( .A(dataA[29]), .B(dataA[23]), .C(n1197), .D(dataA[24]), .Y(
n4803) );
NOR4BX1TS U5539 ( .AN(n1200), .B(dataA[31]), .C(operation_reg_0_), .D(n5328),
.Y(n4802) );
NOR2X1TS U5540 ( .A(n1200), .B(n4801), .Y(n4809) );
NAND4XLTS U5541 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n4805) );
OAI31X1TS U5542 ( .A0(n4807), .A1(n4806), .A2(n4805), .B0(dataB[27]), .Y(
n4808) );
OAI2BB2XLTS U5543 ( .B0(n4811), .B1(n4810), .A0N(n4809), .A1N(
operation_reg_0_), .Y(NaN_reg) );
XOR2X1TS U5544 ( .A(n1692), .B(n4812), .Y(n4813) );
AOI22X1TS U5545 ( .A0(n4858), .A1(FPSENCOS_d_ff_Yn[31]), .B0(
FPSENCOS_d_ff_Xn[31]), .B1(n4862), .Y(n4816) );
XNOR2X1TS U5546 ( .A(n4816), .B(n4815), .Y(FPSENCOS_fmtted_Result_31_) );
AOI22X1TS U5547 ( .A0(n4837), .A1(n5199), .B0(n1111), .B1(n4831), .Y(
FPADDSUB_DmP_INIT_EWSW[0]) );
AOI22X1TS U5548 ( .A0(n4837), .A1(n5196), .B0(n1051), .B1(n4831), .Y(
FPADDSUB_DmP_INIT_EWSW[1]) );
AOI22X1TS U5549 ( .A0(n4837), .A1(n5184), .B0(n1097), .B1(n4831), .Y(
FPADDSUB_DmP_INIT_EWSW[2]) );
AOI22X1TS U5550 ( .A0(n4837), .A1(n5198), .B0(n1047), .B1(n4831), .Y(
FPADDSUB_DmP_INIT_EWSW[3]) );
AOI22X1TS U5551 ( .A0(n4837), .A1(n5182), .B0(n4822), .B1(n4831), .Y(
FPADDSUB_DmP_INIT_EWSW[4]) );
AOI22X1TS U5552 ( .A0(n4837), .A1(n5172), .B0(n4823), .B1(n4831), .Y(
FPADDSUB_DmP_INIT_EWSW[5]) );
AOI22X1TS U5553 ( .A0(n4819), .A1(n5180), .B0(n4824), .B1(n4818), .Y(
FPADDSUB_DmP_INIT_EWSW[6]) );
AOI22X1TS U5554 ( .A0(n4819), .A1(n5171), .B0(n4827), .B1(n4818), .Y(
FPADDSUB_DmP_INIT_EWSW[7]) );
AOI22X1TS U5555 ( .A0(n4819), .A1(n5194), .B0(n954), .B1(n4818), .Y(
FPADDSUB_DmP_INIT_EWSW[8]) );
AOI22X1TS U5556 ( .A0(n4819), .A1(n5186), .B0(n1098), .B1(n4818), .Y(
FPADDSUB_DmP_INIT_EWSW[9]) );
AOI22X1TS U5557 ( .A0(n4819), .A1(n5179), .B0(n4817), .B1(n4818), .Y(
FPADDSUB_DmP_INIT_EWSW[10]) );
AOI22X1TS U5558 ( .A0(n4819), .A1(n5190), .B0(n1096), .B1(n4818), .Y(
FPADDSUB_DmP_INIT_EWSW[11]) );
AOI22X1TS U5559 ( .A0(n4819), .A1(n5141), .B0(n5178), .B1(n4818), .Y(
FPADDSUB_DmP_INIT_EWSW[12]) );
AOI22X1TS U5560 ( .A0(n4819), .A1(n5183), .B0(n1049), .B1(n4818), .Y(
FPADDSUB_DmP_INIT_EWSW[13]) );
AOI22X1TS U5561 ( .A0(n4819), .A1(n5110), .B0(n5156), .B1(n4818), .Y(
FPADDSUB_DmP_INIT_EWSW[14]) );
AOI22X1TS U5562 ( .A0(n4819), .A1(n5191), .B0(n1100), .B1(n4818), .Y(
FPADDSUB_DmP_INIT_EWSW[15]) );
AOI22X1TS U5563 ( .A0(n4821), .A1(n5181), .B0(n4829), .B1(n4820), .Y(
FPADDSUB_DmP_INIT_EWSW[16]) );
AOI22X1TS U5564 ( .A0(n4821), .A1(n5192), .B0(n1107), .B1(n4820), .Y(
FPADDSUB_DmP_INIT_EWSW[17]) );
AOI22X1TS U5565 ( .A0(n4821), .A1(n5195), .B0(n1109), .B1(n4820), .Y(
FPADDSUB_DmP_INIT_EWSW[18]) );
AOI22X1TS U5566 ( .A0(n4821), .A1(n5113), .B0(n1099), .B1(n4820), .Y(
FPADDSUB_DmP_INIT_EWSW[19]) );
AOI22X1TS U5567 ( .A0(n4821), .A1(n5189), .B0(n1112), .B1(n4820), .Y(
FPADDSUB_DmP_INIT_EWSW[20]) );
AOI22X1TS U5568 ( .A0(n4821), .A1(n5188), .B0(n1101), .B1(n4820), .Y(
FPADDSUB_DmP_INIT_EWSW[21]) );
AOI22X1TS U5569 ( .A0(n4821), .A1(n5114), .B0(n1695), .B1(n4820), .Y(
FPADDSUB_DmP_INIT_EWSW[22]) );
AOI22X1TS U5570 ( .A0(n4821), .A1(n5204), .B0(n5155), .B1(n4820), .Y(
FPADDSUB_DmP_INIT_EWSW[23]) );
AOI22X1TS U5571 ( .A0(n4821), .A1(n5185), .B0(n1110), .B1(n4820), .Y(
FPADDSUB_DmP_INIT_EWSW[24]) );
AOI22X1TS U5572 ( .A0(n4821), .A1(n5193), .B0(n1050), .B1(n4820), .Y(
FPADDSUB_DmP_INIT_EWSW[25]) );
AOI22X1TS U5573 ( .A0(n4834), .A1(n5197), .B0(n1108), .B1(n4826), .Y(
FPADDSUB_DmP_INIT_EWSW[26]) );
AOI22X1TS U5574 ( .A0(n4834), .A1(n5187), .B0(n1048), .B1(n4826), .Y(
FPADDSUB_DmP_INIT_EWSW[27]) );
AOI22X1TS U5575 ( .A0(n4834), .A1(n1111), .B0(n5199), .B1(n4826), .Y(
FPADDSUB_DMP_INIT_EWSW[0]) );
AOI22X1TS U5576 ( .A0(n4834), .A1(n1051), .B0(n5196), .B1(n4826), .Y(
FPADDSUB_DMP_INIT_EWSW[1]) );
AOI22X1TS U5577 ( .A0(n4834), .A1(n1097), .B0(n5184), .B1(n4826), .Y(
FPADDSUB_DMP_INIT_EWSW[2]) );
AOI22X1TS U5578 ( .A0(n4834), .A1(n1047), .B0(n5198), .B1(n4826), .Y(
FPADDSUB_DMP_INIT_EWSW[3]) );
AOI22X1TS U5579 ( .A0(n4834), .A1(n4822), .B0(n5182), .B1(n4826), .Y(
FPADDSUB_DMP_INIT_EWSW[4]) );
AOI22X1TS U5580 ( .A0(n4834), .A1(n4823), .B0(n5172), .B1(n4826), .Y(
FPADDSUB_DMP_INIT_EWSW[5]) );
AOI22X1TS U5581 ( .A0(n4834), .A1(n4824), .B0(n5180), .B1(n4826), .Y(
FPADDSUB_DMP_INIT_EWSW[6]) );
AOI22X1TS U5582 ( .A0(n4830), .A1(n4827), .B0(n5171), .B1(n4826), .Y(
FPADDSUB_DMP_INIT_EWSW[7]) );
AOI22X1TS U5583 ( .A0(n4830), .A1(n954), .B0(n5194), .B1(n4832), .Y(
FPADDSUB_DMP_INIT_EWSW[8]) );
AOI22X1TS U5584 ( .A0(n4830), .A1(n1098), .B0(n5186), .B1(n4832), .Y(
FPADDSUB_DMP_INIT_EWSW[9]) );
AOI22X1TS U5585 ( .A0(n4830), .A1(n5140), .B0(n5179), .B1(n4832), .Y(
FPADDSUB_DMP_INIT_EWSW[10]) );
AOI22X1TS U5586 ( .A0(n4830), .A1(n1096), .B0(n5190), .B1(n4832), .Y(
FPADDSUB_DMP_INIT_EWSW[11]) );
AOI22X1TS U5587 ( .A0(n4830), .A1(n5178), .B0(n4828), .B1(n4832), .Y(
FPADDSUB_DMP_INIT_EWSW[12]) );
AOI22X1TS U5588 ( .A0(n4830), .A1(n1049), .B0(n5183), .B1(n4832), .Y(
FPADDSUB_DMP_INIT_EWSW[13]) );
AOI22X1TS U5589 ( .A0(n4830), .A1(n5156), .B0(n5110), .B1(n4832), .Y(
FPADDSUB_DMP_INIT_EWSW[14]) );
AOI22X1TS U5590 ( .A0(n4830), .A1(n1100), .B0(n5191), .B1(n4832), .Y(
FPADDSUB_DMP_INIT_EWSW[15]) );
AOI22X1TS U5591 ( .A0(n4830), .A1(n4829), .B0(n5181), .B1(n4832), .Y(
FPADDSUB_DMP_INIT_EWSW[16]) );
AOI22X1TS U5592 ( .A0(n4835), .A1(n1107), .B0(n5192), .B1(n4832), .Y(
FPADDSUB_DMP_INIT_EWSW[17]) );
AOI22X1TS U5593 ( .A0(n4835), .A1(n1109), .B0(n5195), .B1(n4833), .Y(
FPADDSUB_DMP_INIT_EWSW[18]) );
AOI22X1TS U5594 ( .A0(n4834), .A1(n1099), .B0(n5113), .B1(n4831), .Y(
FPADDSUB_DMP_INIT_EWSW[19]) );
AOI22X1TS U5595 ( .A0(n4835), .A1(n1112), .B0(n5189), .B1(n4833), .Y(
FPADDSUB_DMP_INIT_EWSW[20]) );
AOI22X1TS U5596 ( .A0(n4835), .A1(n1101), .B0(n5188), .B1(n4833), .Y(
FPADDSUB_DMP_INIT_EWSW[21]) );
AOI22X1TS U5597 ( .A0(n4835), .A1(n1695), .B0(n5114), .B1(n4833), .Y(
FPADDSUB_DMP_INIT_EWSW[22]) );
AOI22X1TS U5598 ( .A0(n4835), .A1(n5155), .B0(n5204), .B1(n4831), .Y(
FPADDSUB_DMP_INIT_EWSW[23]) );
AOI22X1TS U5599 ( .A0(n4835), .A1(n1110), .B0(n5185), .B1(n4833), .Y(
FPADDSUB_DMP_INIT_EWSW[24]) );
AOI22X1TS U5600 ( .A0(n4835), .A1(n1050), .B0(n5193), .B1(n4833), .Y(
FPADDSUB_DMP_INIT_EWSW[25]) );
AOI22X1TS U5601 ( .A0(n4835), .A1(n1108), .B0(n5197), .B1(n4833), .Y(
FPADDSUB_DMP_INIT_EWSW[26]) );
AOI22X1TS U5602 ( .A0(n4835), .A1(n1048), .B0(n5187), .B1(n4825), .Y(
FPADDSUB_DMP_INIT_EWSW[27]) );
OAI2BB2XLTS U5603 ( .B0(n4837), .B1(n5157), .A0N(n4837), .A1N(
FPADDSUB_intDX_EWSW[28]), .Y(FPADDSUB_DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U5604 ( .B0(n4837), .B1(n4836), .A0N(n4679), .A1N(
FPADDSUB_intDX_EWSW[29]), .Y(FPADDSUB_DMP_INIT_EWSW[29]) );
OAI22X1TS U5605 ( .A0(n4839), .A1(n1178), .B0(n4841), .B1(n1176), .Y(
FPADDSUB_Data_array_SWR[24]) );
OAI222X1TS U5606 ( .A0(n1165), .A1(n4841), .B0(n1179), .B1(n4840), .C0(n1176), .C1(n4839), .Y(FPADDSUB_Data_array_SWR[23]) );
NAND2X1TS U5607 ( .A(n4866), .B(n4875), .Y(FPSENCOS_enab_d_ff5_data_out) );
CLKAND2X2TS U5608 ( .A(n4843), .B(FPMULT_Sgf_normalized_result[0]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]) );
BUFX3TS U5609 ( .A(n4843), .Y(n4842) );
CLKAND2X2TS U5610 ( .A(n4842), .B(FPMULT_Sgf_normalized_result[1]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]) );
CLKAND2X2TS U5611 ( .A(n4842), .B(FPMULT_Sgf_normalized_result[2]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]) );
CLKAND2X2TS U5612 ( .A(n4842), .B(FPMULT_Sgf_normalized_result[3]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]) );
CLKAND2X2TS U5613 ( .A(n4842), .B(FPMULT_Sgf_normalized_result[4]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]) );
CLKAND2X2TS U5614 ( .A(FPMULT_Sgf_normalized_result[5]), .B(n4842), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]) );
CLKAND2X2TS U5615 ( .A(n4842), .B(FPMULT_Sgf_normalized_result[6]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]) );
CLKAND2X2TS U5616 ( .A(n4842), .B(FPMULT_Sgf_normalized_result[7]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]) );
CLKAND2X2TS U5617 ( .A(n4842), .B(FPMULT_Sgf_normalized_result[8]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]) );
CLKAND2X2TS U5618 ( .A(n4842), .B(FPMULT_Sgf_normalized_result[9]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]) );
CLKAND2X2TS U5619 ( .A(n4842), .B(FPMULT_Sgf_normalized_result[10]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]) );
BUFX3TS U5620 ( .A(n4843), .Y(n4844) );
CLKAND2X2TS U5621 ( .A(n4844), .B(FPMULT_Sgf_normalized_result[11]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]) );
CLKAND2X2TS U5622 ( .A(n4844), .B(FPMULT_Sgf_normalized_result[12]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]) );
CLKAND2X2TS U5623 ( .A(n4844), .B(FPMULT_Sgf_normalized_result[13]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]) );
CLKAND2X2TS U5624 ( .A(n4844), .B(FPMULT_Sgf_normalized_result[14]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]) );
CLKAND2X2TS U5625 ( .A(n4844), .B(FPMULT_Sgf_normalized_result[15]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]) );
CLKAND2X2TS U5626 ( .A(n4844), .B(FPMULT_Sgf_normalized_result[16]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]) );
CLKAND2X2TS U5627 ( .A(n4844), .B(FPMULT_Sgf_normalized_result[17]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]) );
CLKAND2X2TS U5628 ( .A(n4844), .B(FPMULT_Sgf_normalized_result[18]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]) );
CLKAND2X2TS U5629 ( .A(n4844), .B(FPMULT_Sgf_normalized_result[19]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]) );
CLKAND2X2TS U5630 ( .A(n4844), .B(FPMULT_Sgf_normalized_result[20]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]) );
CLKAND2X2TS U5631 ( .A(n4845), .B(FPMULT_Sgf_normalized_result[21]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]) );
CLKAND2X2TS U5632 ( .A(n4845), .B(FPMULT_Sgf_normalized_result[22]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]) );
NOR2BX1TS U5633 ( .AN(FPSENCOS_d_ff_Xn[0]), .B(n4847), .Y(
FPSENCOS_first_mux_X[0]) );
NOR2BX1TS U5634 ( .AN(FPSENCOS_d_ff_Xn[4]), .B(n4847), .Y(
FPSENCOS_first_mux_X[4]) );
NOR2BX1TS U5635 ( .AN(FPSENCOS_d_ff_Xn[8]), .B(n4847), .Y(
FPSENCOS_first_mux_X[8]) );
NOR2BX1TS U5636 ( .AN(FPSENCOS_d_ff_Xn[9]), .B(n4847), .Y(
FPSENCOS_first_mux_X[9]) );
NOR2BX1TS U5637 ( .AN(FPSENCOS_d_ff_Xn[11]), .B(n4847), .Y(
FPSENCOS_first_mux_X[11]) );
NOR2BX1TS U5638 ( .AN(FPSENCOS_d_ff_Xn[15]), .B(n4846), .Y(
FPSENCOS_first_mux_X[15]) );
NOR2BX1TS U5639 ( .AN(FPSENCOS_d_ff_Xn[18]), .B(n4854), .Y(
FPSENCOS_first_mux_X[18]) );
NOR2BX1TS U5640 ( .AN(FPSENCOS_d_ff_Xn[21]), .B(n4857), .Y(
FPSENCOS_first_mux_X[21]) );
NOR2BX1TS U5641 ( .AN(FPSENCOS_d_ff_Xn[22]), .B(n4847), .Y(
FPSENCOS_first_mux_X[22]) );
NOR2BX1TS U5642 ( .AN(FPSENCOS_d_ff_Xn[23]), .B(n4847), .Y(
FPSENCOS_first_mux_X[23]) );
NOR2BX1TS U5643 ( .AN(FPSENCOS_d_ff_Xn[30]), .B(n4854), .Y(
FPSENCOS_first_mux_X[30]) );
NOR2BX1TS U5644 ( .AN(FPSENCOS_d_ff_Xn[31]), .B(n4857), .Y(
FPSENCOS_first_mux_X[31]) );
NOR2BX1TS U5645 ( .AN(FPSENCOS_d_ff_Yn[0]), .B(n4855), .Y(
FPSENCOS_first_mux_Y[0]) );
NOR2BX1TS U5646 ( .AN(FPSENCOS_d_ff_Yn[1]), .B(n4846), .Y(
FPSENCOS_first_mux_Y[1]) );
NOR2BX1TS U5647 ( .AN(FPSENCOS_d_ff_Yn[2]), .B(n4854), .Y(
FPSENCOS_first_mux_Y[2]) );
NOR2BX1TS U5648 ( .AN(FPSENCOS_d_ff_Yn[3]), .B(n4855), .Y(
FPSENCOS_first_mux_Y[3]) );
NOR2BX1TS U5649 ( .AN(FPSENCOS_d_ff_Yn[4]), .B(n4857), .Y(
FPSENCOS_first_mux_Y[4]) );
NOR2BX1TS U5650 ( .AN(FPSENCOS_d_ff_Yn[5]), .B(n4846), .Y(
FPSENCOS_first_mux_Y[5]) );
NOR2BX1TS U5651 ( .AN(FPSENCOS_d_ff_Yn[6]), .B(n4847), .Y(
FPSENCOS_first_mux_Y[6]) );
NOR2BX1TS U5652 ( .AN(FPSENCOS_d_ff_Yn[7]), .B(n4849), .Y(
FPSENCOS_first_mux_Y[7]) );
NOR2BX1TS U5653 ( .AN(FPSENCOS_d_ff_Yn[8]), .B(n4855), .Y(
FPSENCOS_first_mux_Y[8]) );
NOR2BX1TS U5654 ( .AN(FPSENCOS_d_ff_Yn[9]), .B(n4849), .Y(
FPSENCOS_first_mux_Y[9]) );
NOR2BX1TS U5655 ( .AN(FPSENCOS_d_ff_Yn[10]), .B(n4847), .Y(
FPSENCOS_first_mux_Y[10]) );
NOR2BX1TS U5656 ( .AN(FPSENCOS_d_ff_Yn[11]), .B(n4854), .Y(
FPSENCOS_first_mux_Y[11]) );
NOR2BX1TS U5657 ( .AN(FPSENCOS_d_ff_Yn[12]), .B(n4857), .Y(
FPSENCOS_first_mux_Y[12]) );
NOR2BX1TS U5658 ( .AN(FPSENCOS_d_ff_Yn[13]), .B(n4849), .Y(
FPSENCOS_first_mux_Y[13]) );
NOR2BX1TS U5659 ( .AN(FPSENCOS_d_ff_Yn[14]), .B(n4855), .Y(
FPSENCOS_first_mux_Y[14]) );
NOR2BX1TS U5660 ( .AN(FPSENCOS_d_ff_Yn[15]), .B(n4849), .Y(
FPSENCOS_first_mux_Y[15]) );
NOR2BX1TS U5661 ( .AN(FPSENCOS_d_ff_Yn[16]), .B(n4846), .Y(
FPSENCOS_first_mux_Y[16]) );
NOR2BX1TS U5662 ( .AN(FPSENCOS_d_ff_Yn[17]), .B(n4849), .Y(
FPSENCOS_first_mux_Y[17]) );
NOR2BX1TS U5663 ( .AN(FPSENCOS_d_ff_Yn[18]), .B(n4854), .Y(
FPSENCOS_first_mux_Y[18]) );
NOR2BX1TS U5664 ( .AN(FPSENCOS_d_ff_Yn[19]), .B(n4849), .Y(
FPSENCOS_first_mux_Y[19]) );
NOR2BX1TS U5665 ( .AN(FPSENCOS_d_ff_Yn[20]), .B(n4857), .Y(
FPSENCOS_first_mux_Y[20]) );
NOR2BX1TS U5666 ( .AN(FPSENCOS_d_ff_Yn[21]), .B(n4849), .Y(
FPSENCOS_first_mux_Y[21]) );
NOR2BX1TS U5667 ( .AN(FPSENCOS_d_ff_Yn[22]), .B(n4855), .Y(
FPSENCOS_first_mux_Y[22]) );
NOR2BX1TS U5668 ( .AN(FPSENCOS_d_ff_Yn[23]), .B(n4847), .Y(
FPSENCOS_first_mux_Y[23]) );
NOR2BX1TS U5669 ( .AN(FPSENCOS_d_ff_Yn[24]), .B(n4849), .Y(
FPSENCOS_first_mux_Y[24]) );
NOR2BX1TS U5670 ( .AN(FPSENCOS_d_ff_Yn[25]), .B(n4854), .Y(
FPSENCOS_first_mux_Y[25]) );
NOR2BX1TS U5671 ( .AN(FPSENCOS_d_ff_Yn[26]), .B(n4846), .Y(
FPSENCOS_first_mux_Y[26]) );
NOR2BX1TS U5672 ( .AN(FPSENCOS_d_ff_Yn[27]), .B(n4857), .Y(
FPSENCOS_first_mux_Y[27]) );
NOR2BX1TS U5673 ( .AN(FPSENCOS_d_ff_Yn[28]), .B(n4849), .Y(
FPSENCOS_first_mux_Y[28]) );
NOR2BX1TS U5674 ( .AN(FPSENCOS_d_ff_Yn[29]), .B(n4855), .Y(
FPSENCOS_first_mux_Y[29]) );
NOR2BX1TS U5675 ( .AN(FPSENCOS_d_ff_Yn[30]), .B(n4849), .Y(
FPSENCOS_first_mux_Y[30]) );
NOR2BX1TS U5676 ( .AN(FPSENCOS_d_ff_Yn[31]), .B(n4846), .Y(
FPSENCOS_first_mux_Y[31]) );
BUFX3TS U5677 ( .A(n4856), .Y(n4852) );
BUFX3TS U5678 ( .A(n4856), .Y(n4853) );
BUFX3TS U5679 ( .A(n4864), .Y(n4859) );
INVX2TS U5680 ( .A(n4861), .Y(n4865) );
AOI21X1TS U5681 ( .A0(operation[1]), .A1(ack_operation), .B0(n4866), .Y(
n4876) );
NOR3X1TS U5682 ( .A(FPSENCOS_enab_RB3), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .C(FPSENCOS_enab_d_ff_RB1),
.Y(n4867) );
NOR2BX1TS U5683 ( .AN(begin_operation), .B(n4929), .Y(n4871) );
OAI22X1TS U5684 ( .A0(n4876), .A1(n4869), .B0(n4871), .B1(n4870), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U5685 ( .AN(n4871), .B(n4870), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U5686 ( .A0(FPSENCOS_enab_d_ff4_Zn), .A1(n4874), .B0(n4873), .B1(
n4872), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U5687 ( .AN(FPSENCOS_enab_d_ff4_Zn), .B(n4874), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
AOI22X1TS U5688 ( .A0(FPSENCOS_d_ff3_sh_x_out[9]), .A1(n4971), .B0(Data_2[9]), .B1(n4883), .Y(n4880) );
AOI22X1TS U5689 ( .A0(n4878), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n4877),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n4879) );
NAND2X1TS U5690 ( .A(n4880), .B(n4879), .Y(add_subt_data2[9]) );
BUFX3TS U5691 ( .A(n4883), .Y(n4905) );
AOI22X1TS U5692 ( .A0(FPSENCOS_d_ff3_sh_x_out[21]), .A1(n4971), .B0(
Data_2[21]), .B1(n4905), .Y(n4882) );
AOI22X1TS U5693 ( .A0(n4964), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n4898),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n4881) );
NAND2X1TS U5694 ( .A(n4882), .B(n4881), .Y(add_subt_data2[21]) );
AOI22X1TS U5695 ( .A0(FPSENCOS_d_ff3_sh_x_out[23]), .A1(n4971), .B0(
Data_2[23]), .B1(n4883), .Y(n4885) );
AOI22X1TS U5696 ( .A0(n4608), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n4898),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n4884) );
NAND2X1TS U5697 ( .A(n4885), .B(n4884), .Y(add_subt_data2[23]) );
AOI22X1TS U5698 ( .A0(FPSENCOS_d_ff3_sh_x_out[24]), .A1(n4971), .B0(
Data_2[24]), .B1(n4905), .Y(n4887) );
AOI22X1TS U5699 ( .A0(n4972), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n4898),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n4886) );
NAND2X1TS U5700 ( .A(n4887), .B(n4886), .Y(add_subt_data2[24]) );
AOI22X1TS U5701 ( .A0(FPSENCOS_d_ff3_sh_x_out[25]), .A1(n4971), .B0(
Data_2[25]), .B1(n4905), .Y(n4889) );
AOI22X1TS U5702 ( .A0(n4972), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n4898),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n4888) );
NAND2X1TS U5703 ( .A(n4889), .B(n4888), .Y(add_subt_data2[25]) );
AOI22X1TS U5704 ( .A0(FPSENCOS_d_ff3_sh_x_out[26]), .A1(n4971), .B0(
Data_2[26]), .B1(n4905), .Y(n4891) );
AOI22X1TS U5705 ( .A0(n4972), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n4898),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n4890) );
NAND2X1TS U5706 ( .A(n4891), .B(n4890), .Y(add_subt_data2[26]) );
INVX2TS U5707 ( .A(operation[2]), .Y(n4893) );
AOI22X1TS U5708 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n4971), .B0(Data_1[0]), .B1(
n4905), .Y(n4895) );
AOI22X1TS U5709 ( .A0(n4972), .A1(FPSENCOS_d_ff2_X[0]), .B0(n4898), .B1(
FPSENCOS_d_ff2_Z[0]), .Y(n4894) );
NAND2X1TS U5710 ( .A(n4895), .B(n4894), .Y(add_subt_data1[0]) );
AOI22X1TS U5711 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n4971), .B0(Data_1[1]), .B1(
n4905), .Y(n4897) );
AOI22X1TS U5712 ( .A0(n4972), .A1(FPSENCOS_d_ff2_X[1]), .B0(n4898), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n4896) );
NAND2X1TS U5713 ( .A(n4897), .B(n4896), .Y(add_subt_data1[1]) );
AOI22X1TS U5714 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n4918), .B0(Data_1[2]), .B1(
n4905), .Y(n4900) );
AOI22X1TS U5715 ( .A0(n4919), .A1(FPSENCOS_d_ff2_X[2]), .B0(n4898), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n4899) );
NAND2X1TS U5716 ( .A(n4900), .B(n4899), .Y(add_subt_data1[2]) );
AOI22X1TS U5717 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n4918), .B0(Data_1[3]), .B1(
n4905), .Y(n4902) );
AOI22X1TS U5718 ( .A0(n4919), .A1(FPSENCOS_d_ff2_X[3]), .B0(n4922), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n4901) );
NAND2X1TS U5719 ( .A(n4902), .B(n4901), .Y(add_subt_data1[3]) );
AOI22X1TS U5720 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n4918), .B0(Data_1[4]), .B1(
n4905), .Y(n4904) );
AOI22X1TS U5721 ( .A0(n4919), .A1(FPSENCOS_d_ff2_X[4]), .B0(n4922), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n4903) );
NAND2X1TS U5722 ( .A(n4904), .B(n4903), .Y(add_subt_data1[4]) );
AOI22X1TS U5723 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n4918), .B0(Data_1[5]), .B1(
n4905), .Y(n4907) );
AOI22X1TS U5724 ( .A0(n4919), .A1(FPSENCOS_d_ff2_X[5]), .B0(n4922), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n4906) );
NAND2X1TS U5725 ( .A(n4907), .B(n4906), .Y(add_subt_data1[5]) );
BUFX3TS U5726 ( .A(n4929), .Y(n4938) );
AOI22X1TS U5727 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n4918), .B0(Data_1[6]), .B1(
n4938), .Y(n4909) );
AOI22X1TS U5728 ( .A0(n4919), .A1(FPSENCOS_d_ff2_X[6]), .B0(n3949), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n4908) );
NAND2X1TS U5729 ( .A(n4909), .B(n4908), .Y(add_subt_data1[6]) );
AOI22X1TS U5730 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n4918), .B0(Data_1[7]), .B1(
n4938), .Y(n4911) );
AOI22X1TS U5731 ( .A0(n4919), .A1(FPSENCOS_d_ff2_X[7]), .B0(n3949), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n4910) );
NAND2X1TS U5732 ( .A(n4911), .B(n4910), .Y(add_subt_data1[7]) );
AOI22X1TS U5733 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n4918), .B0(Data_1[8]), .B1(
n4938), .Y(n4913) );
AOI22X1TS U5734 ( .A0(n4919), .A1(FPSENCOS_d_ff2_X[8]), .B0(n3949), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n4912) );
NAND2X1TS U5735 ( .A(n4913), .B(n4912), .Y(add_subt_data1[8]) );
AOI22X1TS U5736 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n4918), .B0(Data_1[9]), .B1(
n4938), .Y(n4915) );
AOI22X1TS U5737 ( .A0(n4919), .A1(FPSENCOS_d_ff2_X[9]), .B0(n3949), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n4914) );
NAND2X1TS U5738 ( .A(n4915), .B(n4914), .Y(add_subt_data1[9]) );
AOI22X1TS U5739 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n4918), .B0(Data_1[10]),
.B1(n4938), .Y(n4917) );
AOI22X1TS U5740 ( .A0(n4919), .A1(FPSENCOS_d_ff2_X[10]), .B0(n3949), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n4916) );
NAND2X1TS U5741 ( .A(n4917), .B(n4916), .Y(add_subt_data1[10]) );
AOI22X1TS U5742 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n4918), .B0(Data_1[11]),
.B1(n4938), .Y(n4921) );
AOI22X1TS U5743 ( .A0(n4919), .A1(FPSENCOS_d_ff2_X[11]), .B0(n3949), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n4920) );
NAND2X1TS U5744 ( .A(n4921), .B(n4920), .Y(add_subt_data1[11]) );
AOI22X1TS U5745 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n4943), .B0(Data_1[12]),
.B1(n4938), .Y(n4924) );
AOI22X1TS U5746 ( .A0(n4945), .A1(FPSENCOS_d_ff2_X[12]), .B0(n4944), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n4923) );
NAND2X1TS U5747 ( .A(n4924), .B(n4923), .Y(add_subt_data1[12]) );
AOI22X1TS U5748 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n4943), .B0(Data_1[13]),
.B1(n4938), .Y(n4926) );
AOI22X1TS U5749 ( .A0(n4945), .A1(FPSENCOS_d_ff2_X[13]), .B0(n4944), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n4925) );
NAND2X1TS U5750 ( .A(n4926), .B(n4925), .Y(add_subt_data1[13]) );
AOI22X1TS U5751 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n4943), .B0(Data_1[14]),
.B1(n4938), .Y(n4928) );
AOI22X1TS U5752 ( .A0(n4945), .A1(FPSENCOS_d_ff2_X[14]), .B0(n4944), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n4927) );
NAND2X1TS U5753 ( .A(n4928), .B(n4927), .Y(add_subt_data1[14]) );
BUFX3TS U5754 ( .A(n4929), .Y(n4954) );
AOI22X1TS U5755 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n4943), .B0(Data_1[15]),
.B1(n4954), .Y(n4931) );
AOI22X1TS U5756 ( .A0(n4945), .A1(FPSENCOS_d_ff2_X[15]), .B0(n4944), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n4930) );
NAND2X1TS U5757 ( .A(n4931), .B(n4930), .Y(add_subt_data1[15]) );
AOI22X1TS U5758 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n4943), .B0(Data_1[16]),
.B1(n4954), .Y(n4933) );
AOI22X1TS U5759 ( .A0(n4945), .A1(FPSENCOS_d_ff2_X[16]), .B0(n4944), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n4932) );
NAND2X1TS U5760 ( .A(n4933), .B(n4932), .Y(add_subt_data1[16]) );
AOI22X1TS U5761 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n4943), .B0(Data_1[17]),
.B1(n4954), .Y(n4935) );
AOI22X1TS U5762 ( .A0(n4945), .A1(FPSENCOS_d_ff2_X[17]), .B0(n4944), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n4934) );
NAND2X1TS U5763 ( .A(n4935), .B(n4934), .Y(add_subt_data1[17]) );
AOI22X1TS U5764 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n4943), .B0(Data_1[18]),
.B1(n4954), .Y(n4937) );
AOI22X1TS U5765 ( .A0(n4945), .A1(FPSENCOS_d_ff2_X[18]), .B0(n4944), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n4936) );
NAND2X1TS U5766 ( .A(n4937), .B(n4936), .Y(add_subt_data1[18]) );
AOI22X1TS U5767 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n4943), .B0(Data_1[19]),
.B1(n4938), .Y(n4940) );
AOI22X1TS U5768 ( .A0(n4945), .A1(FPSENCOS_d_ff2_X[19]), .B0(n4944), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n4939) );
NAND2X1TS U5769 ( .A(n4940), .B(n4939), .Y(add_subt_data1[19]) );
AOI22X1TS U5770 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n4943), .B0(Data_1[20]),
.B1(n4954), .Y(n4942) );
AOI22X1TS U5771 ( .A0(n4945), .A1(FPSENCOS_d_ff2_X[20]), .B0(n4944), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n4941) );
NAND2X1TS U5772 ( .A(n4942), .B(n4941), .Y(add_subt_data1[20]) );
AOI22X1TS U5773 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n4943), .B0(Data_1[21]),
.B1(n4954), .Y(n4947) );
AOI22X1TS U5774 ( .A0(n4945), .A1(FPSENCOS_d_ff2_X[21]), .B0(n4944), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n4946) );
NAND2X1TS U5775 ( .A(n4947), .B(n4946), .Y(add_subt_data1[21]) );
AOI22X1TS U5776 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n3981), .B0(Data_1[22]),
.B1(n4954), .Y(n4949) );
AOI22X1TS U5777 ( .A0(n4961), .A1(FPSENCOS_d_ff2_X[22]), .B0(n4967), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n4948) );
NAND2X1TS U5778 ( .A(n4949), .B(n4948), .Y(add_subt_data1[22]) );
AOI22X1TS U5779 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n3981), .B0(Data_1[23]),
.B1(n4954), .Y(n4951) );
AOI22X1TS U5780 ( .A0(n4608), .A1(FPSENCOS_d_ff2_X[23]), .B0(n4967), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n4950) );
NAND2X1TS U5781 ( .A(n4951), .B(n4950), .Y(add_subt_data1[23]) );
AOI22X1TS U5782 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n3981), .B0(Data_1[24]),
.B1(n4954), .Y(n4953) );
AOI22X1TS U5783 ( .A0(n4961), .A1(FPSENCOS_d_ff2_X[24]), .B0(n4967), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n4952) );
NAND2X1TS U5784 ( .A(n4953), .B(n4952), .Y(add_subt_data1[24]) );
AOI22X1TS U5785 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n3981), .B0(Data_1[25]),
.B1(n4954), .Y(n4956) );
AOI22X1TS U5786 ( .A0(n4961), .A1(FPSENCOS_d_ff2_X[25]), .B0(n4967), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n4955) );
NAND2X1TS U5787 ( .A(n4956), .B(n4955), .Y(add_subt_data1[25]) );
AOI22X1TS U5788 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n4069), .B0(Data_1[26]),
.B1(n4970), .Y(n4958) );
AOI22X1TS U5789 ( .A0(n4961), .A1(FPSENCOS_d_ff2_X[26]), .B0(n4967), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n4957) );
NAND2X1TS U5790 ( .A(n4958), .B(n4957), .Y(add_subt_data1[26]) );
AOI22X1TS U5791 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n3981), .B0(Data_1[27]),
.B1(n4970), .Y(n4960) );
AOI22X1TS U5792 ( .A0(n4964), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4967), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n4959) );
NAND2X1TS U5793 ( .A(n4960), .B(n4959), .Y(add_subt_data1[27]) );
AOI22X1TS U5794 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n4078), .B0(Data_1[28]),
.B1(n4970), .Y(n4963) );
AOI22X1TS U5795 ( .A0(n4961), .A1(FPSENCOS_d_ff2_X[28]), .B0(n4967), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n4962) );
NAND2X1TS U5796 ( .A(n4963), .B(n4962), .Y(add_subt_data1[28]) );
AOI22X1TS U5797 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4069), .B0(Data_1[29]),
.B1(n4970), .Y(n4966) );
AOI22X1TS U5798 ( .A0(n4964), .A1(FPSENCOS_d_ff2_X[29]), .B0(n4967), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n4965) );
NAND2X1TS U5799 ( .A(n4966), .B(n4965), .Y(add_subt_data1[29]) );
AOI22X1TS U5800 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n4069), .B0(Data_1[30]),
.B1(n4970), .Y(n4969) );
AOI22X1TS U5801 ( .A0(n4608), .A1(FPSENCOS_d_ff2_X[30]), .B0(n4967), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n4968) );
NAND2X1TS U5802 ( .A(n4969), .B(n4968), .Y(add_subt_data1[30]) );
AOI22X1TS U5803 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n4971), .B0(Data_1[31]),
.B1(n4970), .Y(n4974) );
AOI22X1TS U5804 ( .A0(n4972), .A1(FPSENCOS_d_ff2_X[31]), .B0(n3949), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n4973) );
NAND2X1TS U5805 ( .A(n4974), .B(n4973), .Y(add_subt_data1[31]) );
OA21XLTS U5806 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n4976), .B0(n4975), .Y(
FPSENCOS_ITER_CONT_N4) );
AOI22X1TS U5807 ( .A0(n4987), .A1(cordic_result[31]), .B0(n4978), .B1(
mult_result[31]), .Y(n4977) );
OAI2BB1X1TS U5808 ( .A0N(n5019), .A1N(result_add_subt[31]), .B0(n4977), .Y(
op_result[31]) );
AOI22X1TS U5809 ( .A0(n4987), .A1(cordic_result[30]), .B0(n4989), .B1(
mult_result[30]), .Y(n4979) );
OAI2BB1X1TS U5810 ( .A0N(n3930), .A1N(result_add_subt[30]), .B0(n4979), .Y(
op_result[30]) );
AOI22X1TS U5811 ( .A0(n4987), .A1(cordic_result[29]), .B0(n4989), .B1(
mult_result[29]), .Y(n4980) );
OAI2BB1X1TS U5812 ( .A0N(n3930), .A1N(result_add_subt[29]), .B0(n4980), .Y(
op_result[29]) );
AOI22X1TS U5813 ( .A0(n4987), .A1(cordic_result[28]), .B0(n4989), .B1(
mult_result[28]), .Y(n4981) );
OAI2BB1X1TS U5814 ( .A0N(n3930), .A1N(result_add_subt[28]), .B0(n4981), .Y(
op_result[28]) );
AOI22X1TS U5815 ( .A0(n4987), .A1(cordic_result[27]), .B0(n4989), .B1(
mult_result[27]), .Y(n4982) );
OAI2BB1X1TS U5816 ( .A0N(n3930), .A1N(result_add_subt[27]), .B0(n4982), .Y(
op_result[27]) );
AOI22X1TS U5817 ( .A0(n4987), .A1(cordic_result[26]), .B0(n4989), .B1(
mult_result[26]), .Y(n4983) );
OAI2BB1X1TS U5818 ( .A0N(n4995), .A1N(result_add_subt[26]), .B0(n4983), .Y(
op_result[26]) );
AOI22X1TS U5819 ( .A0(n4987), .A1(cordic_result[25]), .B0(n4989), .B1(
mult_result[25]), .Y(n4984) );
OAI2BB1X1TS U5820 ( .A0N(n4995), .A1N(result_add_subt[25]), .B0(n4984), .Y(
op_result[25]) );
AOI22X1TS U5821 ( .A0(n4987), .A1(cordic_result[24]), .B0(n4989), .B1(
mult_result[24]), .Y(n4985) );
OAI2BB1X1TS U5822 ( .A0N(n4995), .A1N(result_add_subt[24]), .B0(n4985), .Y(
op_result[24]) );
AOI22X1TS U5823 ( .A0(n4987), .A1(cordic_result[23]), .B0(n4989), .B1(
mult_result[23]), .Y(n4986) );
OAI2BB1X1TS U5824 ( .A0N(n4995), .A1N(result_add_subt[23]), .B0(n4986), .Y(
op_result[23]) );
AOI22X1TS U5825 ( .A0(n4987), .A1(cordic_result[22]), .B0(n4989), .B1(
mult_result[22]), .Y(n4988) );
OAI2BB1X1TS U5826 ( .A0N(n4995), .A1N(result_add_subt[22]), .B0(n4988), .Y(
op_result[22]) );
AOI22X1TS U5827 ( .A0(n4999), .A1(cordic_result[21]), .B0(n5001), .B1(
mult_result[21]), .Y(n4990) );
OAI2BB1X1TS U5828 ( .A0N(n4995), .A1N(result_add_subt[21]), .B0(n4990), .Y(
op_result[21]) );
AOI22X1TS U5829 ( .A0(n4999), .A1(cordic_result[20]), .B0(n5001), .B1(
mult_result[20]), .Y(n4991) );
OAI2BB1X1TS U5830 ( .A0N(n4995), .A1N(result_add_subt[20]), .B0(n4991), .Y(
op_result[20]) );
AOI22X1TS U5831 ( .A0(n4999), .A1(cordic_result[19]), .B0(n5001), .B1(
mult_result[19]), .Y(n4992) );
OAI2BB1X1TS U5832 ( .A0N(n4995), .A1N(result_add_subt[19]), .B0(n4992), .Y(
op_result[19]) );
AOI22X1TS U5833 ( .A0(n4999), .A1(cordic_result[18]), .B0(n5001), .B1(
mult_result[18]), .Y(n4993) );
OAI2BB1X1TS U5834 ( .A0N(n4995), .A1N(result_add_subt[18]), .B0(n4993), .Y(
op_result[18]) );
AOI22X1TS U5835 ( .A0(n4999), .A1(cordic_result[17]), .B0(n5001), .B1(
mult_result[17]), .Y(n4994) );
OAI2BB1X1TS U5836 ( .A0N(n4995), .A1N(result_add_subt[17]), .B0(n4994), .Y(
op_result[17]) );
AOI22X1TS U5837 ( .A0(n4999), .A1(cordic_result[16]), .B0(n5001), .B1(
mult_result[16]), .Y(n4996) );
OAI2BB1X1TS U5838 ( .A0N(n5009), .A1N(result_add_subt[16]), .B0(n4996), .Y(
op_result[16]) );
AOI22X1TS U5839 ( .A0(n4999), .A1(cordic_result[15]), .B0(n5001), .B1(
mult_result[15]), .Y(n4997) );
OAI2BB1X1TS U5840 ( .A0N(n5009), .A1N(result_add_subt[15]), .B0(n4997), .Y(
op_result[15]) );
AOI22X1TS U5841 ( .A0(n4999), .A1(cordic_result[14]), .B0(n5001), .B1(
mult_result[14]), .Y(n4998) );
OAI2BB1X1TS U5842 ( .A0N(n5009), .A1N(result_add_subt[14]), .B0(n4998), .Y(
op_result[14]) );
AOI22X1TS U5843 ( .A0(n4999), .A1(cordic_result[13]), .B0(n5001), .B1(
mult_result[13]), .Y(n5000) );
OAI2BB1X1TS U5844 ( .A0N(n5009), .A1N(result_add_subt[13]), .B0(n5000), .Y(
op_result[13]) );
AOI22X1TS U5845 ( .A0(n5017), .A1(cordic_result[12]), .B0(n5001), .B1(
mult_result[12]), .Y(n5002) );
OAI2BB1X1TS U5846 ( .A0N(n5009), .A1N(result_add_subt[12]), .B0(n5002), .Y(
op_result[12]) );
AOI22X1TS U5847 ( .A0(n5013), .A1(cordic_result[11]), .B0(n5016), .B1(
mult_result[11]), .Y(n5003) );
OAI2BB1X1TS U5848 ( .A0N(n5009), .A1N(result_add_subt[11]), .B0(n5003), .Y(
op_result[11]) );
AOI22X1TS U5849 ( .A0(n5013), .A1(cordic_result[10]), .B0(n5016), .B1(
mult_result[10]), .Y(n5004) );
OAI2BB1X1TS U5850 ( .A0N(n5009), .A1N(result_add_subt[10]), .B0(n5004), .Y(
op_result[10]) );
AOI22X1TS U5851 ( .A0(n5013), .A1(cordic_result[9]), .B0(n5016), .B1(
mult_result[9]), .Y(n5005) );
OAI2BB1X1TS U5852 ( .A0N(n5009), .A1N(result_add_subt[9]), .B0(n5005), .Y(
op_result[9]) );
AOI22X1TS U5853 ( .A0(n5013), .A1(cordic_result[8]), .B0(n5016), .B1(
mult_result[8]), .Y(n5006) );
OAI2BB1X1TS U5854 ( .A0N(n5009), .A1N(result_add_subt[8]), .B0(n5006), .Y(
op_result[8]) );
AOI22X1TS U5855 ( .A0(n5013), .A1(cordic_result[7]), .B0(n5016), .B1(
mult_result[7]), .Y(n5007) );
OAI2BB1X1TS U5856 ( .A0N(n5019), .A1N(result_add_subt[7]), .B0(n5007), .Y(
op_result[7]) );
AOI22X1TS U5857 ( .A0(n5013), .A1(cordic_result[6]), .B0(n5016), .B1(
mult_result[6]), .Y(n5008) );
OAI2BB1X1TS U5858 ( .A0N(n5009), .A1N(result_add_subt[6]), .B0(n5008), .Y(
op_result[6]) );
AOI22X1TS U5859 ( .A0(n5013), .A1(cordic_result[5]), .B0(n5016), .B1(
mult_result[5]), .Y(n5010) );
OAI2BB1X1TS U5860 ( .A0N(n5019), .A1N(result_add_subt[5]), .B0(n5010), .Y(
op_result[5]) );
AOI22X1TS U5861 ( .A0(n5013), .A1(cordic_result[4]), .B0(n4978), .B1(
mult_result[4]), .Y(n5011) );
OAI2BB1X1TS U5862 ( .A0N(n5019), .A1N(result_add_subt[4]), .B0(n5011), .Y(
op_result[4]) );
AOI22X1TS U5863 ( .A0(n5013), .A1(cordic_result[3]), .B0(n4978), .B1(
mult_result[3]), .Y(n5012) );
OAI2BB1X1TS U5864 ( .A0N(n5019), .A1N(result_add_subt[3]), .B0(n5012), .Y(
op_result[3]) );
AOI22X1TS U5865 ( .A0(n5013), .A1(cordic_result[2]), .B0(n4978), .B1(
mult_result[2]), .Y(n5014) );
OAI2BB1X1TS U5866 ( .A0N(n5019), .A1N(result_add_subt[2]), .B0(n5014), .Y(
op_result[2]) );
AOI22X1TS U5867 ( .A0(n5017), .A1(cordic_result[1]), .B0(n5016), .B1(
mult_result[1]), .Y(n5015) );
OAI2BB1X1TS U5868 ( .A0N(n5019), .A1N(result_add_subt[1]), .B0(n5015), .Y(
op_result[1]) );
AOI22X1TS U5869 ( .A0(n5017), .A1(cordic_result[0]), .B0(n5016), .B1(
mult_result[0]), .Y(n5018) );
OAI2BB1X1TS U5870 ( .A0N(n5019), .A1N(result_add_subt[0]), .B0(n5018), .Y(
op_result[0]) );
AOI22X1TS U5871 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n5022), .B0(n5020),
.B1(n5118), .Y(n861) );
AOI22X1TS U5872 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n5022), .B0(n5021),
.B1(n1134), .Y(n853) );
OAI2BB1X1TS U5873 ( .A0N(FPSENCOS_cont_iter_out[1]), .A1N(n851), .B0(n5023),
.Y(n852) );
AOI22X1TS U5874 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n5025), .B0(n5024),
.B1(n5118), .Y(n848) );
AOI22X1TS U5875 ( .A0(ack_operation), .A1(n5282), .B0(begin_operation), .B1(
n5026), .Y(n5028) );
OAI22X1TS U5876 ( .A0(n5030), .A1(n5029), .B0(n5028), .B1(n5027), .Y(n846)
);
OAI22X1TS U5877 ( .A0(n5034), .A1(n5033), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n5032), .Y(n844) );
AOI22X1TS U5878 ( .A0(FPSENCOS_cont_var_out[0]), .A1(n5036), .B0(n5035),
.B1(n5117), .Y(n843) );
NOR4X1TS U5879 ( .A(FPMULT_Op_MY[7]), .B(n1170), .C(FPMULT_Op_MY[2]), .D(
n5037), .Y(n5044) );
NOR4X1TS U5880 ( .A(n5039), .B(n5038), .C(n3112), .D(FPMULT_Op_MY[0]), .Y(
n5043) );
NOR4X1TS U5881 ( .A(FPMULT_Op_MY[24]), .B(FPMULT_Op_MY[25]), .C(
FPMULT_Op_MY[26]), .D(FPMULT_Op_MY[27]), .Y(n5042) );
NOR4X1TS U5882 ( .A(FPMULT_Op_MY[28]), .B(FPMULT_Op_MY[29]), .C(n5040), .D(
FPMULT_Op_MY[30]), .Y(n5041) );
NAND4XLTS U5883 ( .A(n5044), .B(n5043), .C(n5042), .D(n5041), .Y(n5070) );
INVX2TS U5884 ( .A(n5222), .Y(n5046) );
NOR4X1TS U5885 ( .A(FPMULT_Op_MY[13]), .B(n5046), .C(n5045), .D(
FPMULT_Op_MY[22]), .Y(n5054) );
NOR4X1TS U5886 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[4]), .C(
FPMULT_Op_MY[6]), .D(n1218), .Y(n5053) );
NOR4X1TS U5887 ( .A(n5049), .B(n5048), .C(n1172), .D(n1223), .Y(n5052) );
NOR3XLTS U5888 ( .A(FPMULT_Op_MY[10]), .B(n1226), .C(FPMULT_Op_MY[23]), .Y(
n5051) );
NAND4XLTS U5889 ( .A(n5054), .B(n5053), .C(n5052), .D(n5051), .Y(n5069) );
NOR4X1TS U5890 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[11]), .C(
FPMULT_Op_MX[2]), .D(n1278), .Y(n5059) );
NOR4X1TS U5891 ( .A(n1168), .B(n1159), .C(FPMULT_Op_MX[16]), .D(
FPMULT_Op_MX[14]), .Y(n5058) );
NOR4X1TS U5892 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_Op_MX[25]), .C(
FPMULT_Op_MX[26]), .D(FPMULT_Op_MX[27]), .Y(n5057) );
NOR4X1TS U5893 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_Op_MX[3]), .C(
FPMULT_Op_MX[29]), .D(FPMULT_Op_MX[30]), .Y(n5056) );
NAND4XLTS U5894 ( .A(n5059), .B(n5058), .C(n5057), .D(n5056), .Y(n5068) );
NOR4X1TS U5895 ( .A(n1160), .B(n1151), .C(FPMULT_Op_MX[21]), .D(
FPMULT_Op_MX[12]), .Y(n5066) );
NOR4X1TS U5896 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[4]), .C(
FPMULT_Op_MX[8]), .D(n5061), .Y(n5065) );
INVX2TS U5897 ( .A(n5218), .Y(n5062) );
NOR4X1TS U5898 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[5]), .C(
FPMULT_Op_MX[9]), .D(n5062), .Y(n5064) );
NOR3XLTS U5899 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .C(
FPMULT_Op_MX[24]), .Y(n5063) );
NAND4XLTS U5900 ( .A(n5066), .B(n5065), .C(n5064), .D(n5063), .Y(n5067) );
OAI22X1TS U5901 ( .A0(n5070), .A1(n5069), .B0(n5068), .B1(n5067), .Y(n106)
);
XNOR2X1TS U5902 ( .A(FPADDSUB_intDX_EWSW[31]), .B(n5335), .Y(n30) );
NOR2BX1TS U5903 ( .AN(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(FPADDSUB__19_net_) );
XNOR2X1TS U5904 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n5073), .Y(
FPSENCOS_sh_exp_y[6]) );
XNOR2X1TS U5905 ( .A(FPSENCOS_d_ff2_X[29]), .B(n5076), .Y(
FPSENCOS_sh_exp_x[6]) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// XTEA IP Core ////
//// ////
//// This file is part of the xtea project ////
//// http://www.opencores.org/projects.cgi/web/xtea/overview ////
//// ////
//// Test-bench for the XTEA encryption algorithm. ////
//// ////
//// TODO: ////
//// * Update for new combined encipher/decipher module ////
//// * Tidy ////
//// * Add interconnections ////
//// ////
//// Author: David Johnson, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006 David Johnson ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, write to the ////
//// Free Software Foundation, Inc., 51 Franklin Street, Fifth ////
//// Floor, Boston, MA 02110-1301 USA ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
module cipher_testbench (clock, reset, all_done_encipher, all_done_decipher, data_out_encipher1, data_out_encipher2, data_out_decipher1, data_out_decipher2, data_in_encipher1, data_in_encipher2, data_in_decipher1, data_in_decipher2, key_out, result, reset_out);
input clock, reset, all_done_encipher, all_done_decipher;
input[31:0] data_in_encipher1, data_in_encipher2, data_in_decipher1, data_in_decipher2;
output result, reset_out;
output[31:0] data_out_encipher1, data_out_encipher2, data_out_decipher1, data_out_decipher2;
output[127:0] key_out;
reg result, reset_out, test_ciphertext, test_plaintext;
reg[7:0] state;
reg[31:0] data_out_encipher1, data_out_encipher2, data_out_decipher1, data_out_decipher2, tempdata1, tempdata2;
reg[127:0] key_out;
parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4, s5 = 5, s6 = 6, s7 = 7, s8 = 8, s9 = 9,
s10 = 10, s11 = 11, s12 = 12, s13 = 13, s14 = 14, s15 = 15, s16 = 16, s17 = 17, s18 = 18, s19 = 19,
s20 = 20, s21 = 21, s22 = 22, s23 = 23, s24 = 24, s25 = 25, s26 = 26, s27 = 27, s28 = 28, s29 = 29,
s30 = 30, s31 = 31, s32 = 32, s33 = 33, s34 = 34, s35 = 35, s36 = 36, s37 = 37, s38 = 38, s39 = 39,
s40 = 40, s41 = 41, s42 = 42, s43 = 43, s44 = 44, s45 = 45, s46 = 46, s47 = 47, s48 = 48, s49 = 49;
always @(posedge clock or posedge reset)
begin
if (reset)
state = s0;
else
begin
case (state)
s0: state = s1;
s1: state = s2;
s2: state = all_done_encipher ? s3 : s2;
s3: state = s4;
s4: state = s5;
s5: state = all_done_decipher ? s6 : s5;
s6: state = s7;
s7: state = s8;
s8: state = s9;
s9: state = all_done_encipher ? s10 : s9;
s10: state = s11;
s11: state = s12;
s12: state = all_done_decipher ? s13 : s12;
s13: state = s14;
s14: state = s15;
s15: state = s16;
s16: state = all_done_encipher ? s17 : s16;
s17: state = s18;
s18: state = s19;
s19: state = all_done_decipher ? s20 : s19;
s20: state = s21;
s21: state = s22;
s22: state = s23;
s23: state = all_done_encipher ? s24 : s23;
s24: state = s25;
s25: state = s26;
s26: state = all_done_decipher ? s27 : s26;
s27: state = s28;
s28: state = s29;
s29: state = s30;
s30: state = all_done_encipher ? s31 : s30;
s31: state = s32;
s32: state = s33;
s33: state = all_done_decipher ? s34 : s33;
s34: state = s35;
s35: state = s36;
s36: state = s37;
s37: state = all_done_encipher ? s38 : s37;
s38: state = s39;
s39: state = s40;
s40: state = all_done_decipher ? s41 : s40;
s41: state = s42;
s42: state = s43;
s43: state = s44;
s44: state = all_done_encipher ? s45 : s44;
s45: state = s46;
s46: state = s47;
s47: state = all_done_decipher ? s48 : s47;
s48: state = s49;
s49: state = s49;
default: state = 1'bz;
endcase
end
end
always @(posedge clock or posedge reset)
begin
if (reset)
begin
result = 1'b0;
reset_out = 1'b0;
test_ciphertext = 1'b0;
test_plaintext = 1'b0;
data_out_encipher1 = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
data_out_encipher2 = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
data_out_decipher1 = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
data_out_decipher2 = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
key_out = 128'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
end
else begin
case (state)
//Test 1
s1: begin
reset_out = 1'b1;
data_out_encipher1 = 32'h00000000;
data_out_encipher2 = 32'h00000000;
key_out = 128'h00000000000000000000000000000000;
end
s2: reset_out = 1'b0;
s3: begin
test_ciphertext = ((data_in_encipher1 == 32'hdee9d4d8) && (data_in_encipher2 == 32'hf7131ed9));
tempdata1 = data_in_encipher1;
tempdata2 = data_in_encipher2;
end
s4: begin
reset_out = 1'b1;
data_out_decipher1 = tempdata1;
data_out_decipher2 = tempdata2;
end
s5: reset_out = 1'b0;
s6: test_plaintext = ((data_in_decipher1 == 32'h00000000) && (data_in_decipher2 == 32'h00000000));
s7: result = (test_ciphertext && test_plaintext);
//Test 2
s8: begin
result = 1'b0;
reset_out = 1'b1;
data_out_encipher1 = 32'h00000000;
data_out_encipher2 = 32'h00000000;
key_out = 128'h11111111222222223333333344444444;
end
s9: reset_out = 1'b0;
s10: begin
test_ciphertext = ((data_in_encipher1 == 32'hf07ac290) && (data_in_encipher2 == 32'h23c92672));
tempdata1 = data_in_encipher1;
tempdata2 = data_in_encipher2;
end
s11: begin
reset_out = 1'b1;
data_out_decipher1 = tempdata1;
data_out_decipher2 = tempdata2;
end
s12: reset_out = 1'b0;
s13: test_plaintext = ((data_in_decipher1 == 32'h00000000) && (data_in_decipher2 == 32'h00000000));
s14: result = (test_ciphertext && test_plaintext);
//Test 3
s15: begin
result = 1'b0;
reset_out = 1'b1;
data_out_encipher1 = 32'h12345678;
data_out_encipher2 = 32'h9abcdeff;
key_out = 128'h6a1d78c88c86d67f2a65bfbeb4bd6e46;
end
s16: reset_out = 1'b0;
s17: begin
test_ciphertext = ((data_in_encipher1 == 32'h99bbb92b) && (data_in_encipher2 == 32'h3ebd1644));
tempdata1 = data_in_encipher1;
tempdata2 = data_in_encipher2;
end
s18: begin
reset_out = 1'b1;
data_out_decipher1 = tempdata1;
data_out_decipher2 = tempdata2;
end
s19: reset_out = 1'b0;
s20: test_plaintext = ((data_in_decipher1 == 32'h12345678) && (data_in_decipher2 == 32'h9abcdeff));
s21: result = (test_ciphertext && test_plaintext);
//Test 4
s22: begin
result = 1'b0;
reset_out = 1'b1;
data_out_encipher1 = 32'h00000001;
data_out_encipher2 = 32'h00000001;
key_out = 128'h62ee209f69b7afce376a8936cdc9e923;
end
s23: reset_out = 1'b0;
s24: begin
test_ciphertext = ((data_in_encipher1 == 32'he57220dd) && (data_in_encipher2 == 32'h2622745b));
tempdata1 = data_in_encipher1;
tempdata2 = data_in_encipher2;
end
s25: begin
reset_out = 1'b1;
data_out_decipher1 = tempdata1;
data_out_decipher2 = tempdata2;
end
s26: reset_out = 1'b0;
s27: test_plaintext = ((data_in_decipher1 == 32'h00000001) && (data_in_decipher2 == 32'h00000001));
s28: result = (test_ciphertext && test_plaintext);
//Test 5
s29: begin
result = 1'b0;
reset_out = 1'b1;
data_out_encipher1 = 32'h77777777;
data_out_encipher2 = 32'h98765432;
key_out = 128'hbc3a7de2845846cf2794a1276b8ea8b8;
end
s30: reset_out = 1'b0;
s31: begin
test_ciphertext = ((data_in_encipher1 == 32'hda6b0b0a) && (data_in_encipher2 == 32'ha15e9758));
tempdata1 = data_in_encipher1;
tempdata2 = data_in_encipher2;
end
s32: begin
reset_out = 1'b1;
data_out_decipher1 = tempdata1;
data_out_decipher2 = tempdata2;
end
s33: reset_out = 1'b0;
s34: test_plaintext = ((data_in_decipher1 == 32'h77777777) && (data_in_decipher2 == 32'h98765432));
s35: result = (test_ciphertext && test_plaintext);
//Test 6
s36: begin
result = 1'b0;
reset_out = 1'b1;
data_out_encipher1 = 32'hffffffff;
data_out_encipher2 = 32'hffffffff;
key_out = 128'h6a1d78c88c86d6712a65bfbeb4bd6e46;
end
s37: reset_out = 1'b0;
s38: begin
test_ciphertext = ((data_in_encipher1 == 32'h674e0539) && (data_in_encipher2 == 32'h5ad31ab8));
tempdata1 = data_in_encipher1;
tempdata2 = data_in_encipher2;
end
s39: begin
reset_out = 1'b1;
data_out_decipher1 = tempdata1;
data_out_decipher2 = tempdata2;
end
s40: reset_out = 1'b0;
s41: test_plaintext = ((data_in_decipher1 == 32'hffffffff) && (data_in_decipher2 == 32'hffffffff));
s42: result = (test_ciphertext && test_plaintext);
//Test 7
s43: begin
result = 1'b0;
reset_out = 1'b1;
data_out_encipher1 = 32'hffffffff;
data_out_encipher2 = 32'hffffffff;
key_out = 128'hffffffffffffffffffffffffffffffff;
end
s44: reset_out = 1'b0;
s45: begin
test_ciphertext = ((data_in_encipher1 == 32'h28fc2891) && (data_in_encipher2 == 32'he623566a));
tempdata1 = data_in_encipher1;
tempdata2 = data_in_encipher2;
end
s46: begin
reset_out = 1'b1;
data_out_decipher1 = tempdata1;
data_out_decipher2 = tempdata2;
end
s47: reset_out = 1'b0;
s48: test_plaintext = ((data_in_decipher1 == 32'hffffffff) && (data_in_decipher2 == 32'hffffffff));
s49: result = (test_ciphertext && test_plaintext);
//End tests
default: begin
reset_out = 1'b1;
data_out_encipher1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
data_out_encipher2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
data_out_decipher1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
data_out_decipher2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
key_out = 128'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
result = 1'bz;
end
endcase
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_SYMBOL_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_SYMBOL_V
|
module ForwardingJudgment(
input [1:0] twobeforeop1,
input [2:0] twobeforeop2,twobeforecond,
input [3:0] twobeforeop3,
input [1:0] beforeop1,
input [2:0] beforeop2,beforecond,
input [3:0] beforeop3,
input [1:0] op1,
input [2:0] op2,cond,
input [3:0] op3,
output one_A, one_B, two_A, two_B, MW_One, MW_Two);
reg oA, oB, tA, tB, mwo, mwt;
//one_A
always @ (op1 or op2 or cond or op3 or beforeop1 or beforeop2 or beforecond or beforeop3) begin
if (((beforeop1 == 2'b11
&& beforeop3 >= 4'b0000
&& beforeop3 <= 4'b1100
&& beforeop3 != 4'b0101
&& beforeop3 != 4'b0111)
|| (beforeop1 == 2'b10 && beforeop2 == 3'b001))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0110)
|| op3 == 4'b1101)))
&& op2 == beforecond)
oA <= 1'b1;
else
oA <= 1'b0;
end
//two_A
always @ (op1 or op2 or cond or op3 or twobeforeop1 or twobeforeop2 or twobeforecond or twobeforeop3) begin
if (((twobeforeop1 == 2'b11
&& twobeforeop3 >= 4'b0000
&& twobeforeop3 <= 4'b1100
&& twobeforeop3 != 4'b0101
&& twobeforeop3 != 4'b0111)
|| (twobeforeop1 == 2'b10 && twobeforeop2 == 3'b001))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0110)
|| op3 == 4'b1101)))
&& op2 == twobeforecond)
tA <= 1'b1;
else
tA <= 1'b0;
end
//one_B
always @ (op1 or op2 or cond or op3 or beforeop1 or beforeop2 or beforecond or beforeop3) begin
if (((beforeop1 == 2'b11
&& beforeop3 >= 4'b0000
&& beforeop3 <= 4'b1100
&& beforeop3 != 4'b0101
&& beforeop3 != 4'b0111)
|| (beforeop1 == 2'b10 && (beforeop2 == 3'b001 || beforeop2 == 3'b000)))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0101)
|| (op3 >= 4'b1000
&& op3 <= 4'b1011)))
|| (op1 == 2'b01)
|| (op1 == 2'b00)
|| (op1 == 2'b10 && (op2 == 3'b001
|| op2 == 3'b010
|| op2 == 3'b110)))
&& cond == beforecond)
oB <= 1'b1;
else
oB <= 1'b0;
end
//two_B
always @ (op1 or op2 or cond or op3 or twobeforeop1 or twobeforeop2 or twobeforecond or twobeforeop3) begin
if (((twobeforeop1 == 2'b11
&& twobeforeop3 >= 4'b0000
&& twobeforeop3 <= 4'b1100
&& twobeforeop3 != 4'b0101
&& twobeforeop3 != 4'b0111)
|| (twobeforeop1 == 2'b10 && (twobeforeop2 == 3'b001 || twobeforeop2 == 3'b000)))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0101)
|| (op3 >= 4'b1000
&& op3 <= 4'b1011)))
|| (op1 == 2'b01)
|| (op1 == 2'b00)
|| (op1 == 2'b10 && (op2 == 3'b001
|| op2 == 3'b010
|| op2 == 3'b110)))
&& cond == twobeforecond)
tB <= 1'b1;
else
tB <= 1'b0;
end
//MW_One
always @ (op1 or op2 or cond or op3 or beforeop1 or beforeop2 or beforecond or beforeop3) begin
if (((beforeop1 == 2'b11
&& beforeop3 >= 4'b0000
&& beforeop3 <= 4'b1100
&& beforeop3 != 4'b0101
&& beforeop3 != 4'b0111)
|| (beforeop1 == 2'b10 && (beforeop2 == 3'b001 || beforeop2 == 3'b000)))
&& (op1 == 2'b01 && op2 == beforecond)
|| (((op1 == 2'b10 && op2 == 3'b010)
|| (op1 == 2'b10 && op2 == 3'b110))
&& cond == beforecond))
mwo <= 1'b1;
else
mwo <= 1'b0;
end
//MW_Two
always @ (op1 or op2 or cond or op3 or twobeforeop1 or twobeforeop2 or twobeforecond or twobeforeop3) begin
if (((twobeforeop1 == 2'b11
&& twobeforeop3 >= 4'b0000
&& twobeforeop3 <= 4'b1100
&& twobeforeop3 != 4'b0101
&& twobeforeop3 != 4'b0111)
|| (twobeforeop1 == 2'b10 && (twobeforeop2 == 3'b001 || twobeforeop2 == 3'b000)))
&& (op1 == 2'b01 && op2 == twobeforecond)
|| (((op1 == 2'b10 && op2 == 3'b010)
|| (op1 == 2'b10 && op2 == 3'b110))
&& cond == twobeforecond))
mwt <= 1'b1;
else
mwt <= 1'b0;
end
assign one_A = oA;
assign one_B = oB;
assign two_A = tA;
assign two_B = tB;
assign MW_One = mwo;
assign MW_Two = mwt;
endmodule // ForwardingJudgement
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_1_V
`define SKY130_FD_SC_LP__DFXTP_1_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_1 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_1 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLCLKP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLCLKP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlclkp (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLCLKP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD3_SYMBOL_V
`define SKY130_FD_SC_HS__DLYGATE4SD3_SYMBOL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlygate4sd3 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD3_SYMBOL_V
|
// *****************************************************************************
// Cadence C-to-Silicon Compiler
// Version 14.10-p100 (32 bit), build 50398 Tue, 27 May 2014
//
// File created on Sat Oct 11 22:26:53 2014
//
// The code contained herein is generated for Cadences customer and third
// parties authorized by customer. It may be used in accordance with a
// previously executed license agreement between Cadence and that customer.
// Absolutely no disassembling, decompiling, reverse-translations or
// reverse-engineering of the generated code is allowed.
//
//*****************************************************************************
module dflipflop_post_build(din, clk, reset, dout);
input din;
input clk;
input reset;
output reg dout;
always begin : dflipflop_behaviour
reg state_dflipflop;
reg joins_dflipflop;
reg read_dflipflop_din_ln8;
joins_dflipflop = 1'b0;
if (reset) begin
dout <= 1'b0;
joins_dflipflop = 1'b1;
end
else begin
read_dflipflop_din_ln8 = din;
dout <= read_dflipflop_din_ln8;
joins_dflipflop = 1'b1;
end
// proc_ln4
if (joins_dflipflop == 1'b1) begin
joins_dflipflop = 1'b0;
state_dflipflop <= 1'b0;
end
@(posedge clk);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 19:07:10
// Design Name:
// Module Name: can_qsampler
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module can_qsampler
(
input wire GCLK, // Main clock
input wire RES, // Reset module
inout wire CAN, // CAN bus inout
input wire din, // Bit to transmit
output reg dout, // Received bit
output reg cntmn, // Contamination detector
output reg cntmn_ready, // See if cntmn is valid
output reg sync // Timeslot start flag
);
parameter QUANTA = 20; // Level hold time
parameter SP = 15; // Sample point
reg din_latch = 1'b0; // Latch din at timeslot start
reg [63:0] qcnt = 64'd0; // Timeslot counter
// CAN Read with resync
reg can_sample;
always @(posedge GCLK) begin
can_sample <= CAN;
// Sample data
if (qcnt == SP) begin
dout <= CAN;
cntmn_ready <= 1'b1;
// Contamination flag:
if (din_latch != CAN) begin
cntmn <= 1'b1;
end
else begin
cntmn <= 1'b0;
end
end
else if (qcnt < SP) begin
cntmn_ready <= 1'b0;
end
// Reset circuit
else if (RES == 1'b1) begin
dout <= 1'b0;
cntmn <= 1'b0;
end
// Reset circuit
if (RES == 1'b1) begin
qcnt <= 64'd0;
sync <= 1'b0;
end
// Reset counter
else if (qcnt == QUANTA) begin
qcnt <= 64'd0;
sync <= 1'b1; // Hold for 1 tact
cntmn <= 1'b0;
cntmn_ready <= 1'b0;
end
// Resync circuit
else if ((qcnt > SP) & (can_sample != dout)) begin
qcnt <= 64'd0;
sync <= 1'b1; // Hold for 1 tact
cntmn <= 1'b0;
cntmn_ready <= 1'b0;
end
// Counter
else begin
qcnt <= qcnt + 64'd1;
sync <= 1'b0;
end
end
// CAN Write
assign CAN = (din_latch == 1'b0) ? 1'b0 : 1'bZ;
always @(negedge GCLK) begin
if (qcnt == 64'd0) begin
din_latch <= din; // CAN Write
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_TB_V
`define SKY130_FD_SC_LS__DLYMETAL6S2S_TB_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlymetal6s2s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__dlymetal6s2s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S2S_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFRTP_PP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_PP_BLACKBOX_V
|
//-----------------------------------------------------------------------------
// File : avalon_st_gen.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Copyright 2008 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera
// turn off bogus verilog processor warnings
// altera message_off 10034 10035 10036 10037 10230
module avalon_st_gen
(
input clk // TX FIFO Interface clock
,input reset // Reset signal
,input [7:0] address // Register Address
,input write // Register Write Strobe
,input read // Register Read Strobe
,output wire waitrequest
,input [31:0] writedata // Register Write Data
,output reg [31:0] readdata // Register Read Data
,input tx_ready // Avalon-ST Ready Input
,output reg [63:0] tx_data // Avalon-ST TX Data
,output reg tx_valid // Avalon-ST TX Valid
,output reg tx_sop // Avalon-ST TX StartOfPacket
,output reg tx_eop // Avalon-ST TX EndOfPacket
,output reg [2:0] tx_empty // Avalon-ST TX Empty
,output wire tx_error // Avalon-ST TX Error
);
// ___________________________________________________________
// address parameters
// ___________________________________________________________
parameter ADDR_NUMPKTS = 8'h0;
parameter ADDR_RANDOMLENGTH = 8'h1;
parameter ADDR_RANDOMPAYLOAD = 8'h2;
parameter ADDR_START = 8'h3;
parameter ADDR_STOP = 8'h4;
parameter ADDR_MACSA0 = 8'h5;
parameter ADDR_MACSA1 = 8'h6;
parameter ADDR_MACDA0 = 8'h7;
parameter ADDR_MACDA1 = 8'h8;
parameter ADDR_TXPKTCNT = 8'h9;
parameter ADDR_RNDSEED0 = 8'ha;
parameter ADDR_RNDSEED1 = 8'hb;
parameter ADDR_RNDSEED2 = 8'hc;
parameter ADDR_PKTLENGTH = 8'hd;
parameter ADDR_CNTDASA = 8'hf0;
parameter ADDR_CNTSATLEN = 8'hf1;
parameter ADDR_CNTDATA = 8'hf2;
parameter ADDR_CNTTRNSTN = 8'hf3;
// 10G Ethernet Control Registers
reg start_reg;
wire start; // Start operation of packet generator
reg stop; // Stop operation of packet generator
reg [31:0] number_packet; // Register to store number of packets to be transmitted
reg [31:0] config_setting; // Register to configure settings: data pattern type, length
reg [31:0] source_addr0; // Register to program the MAC source address [31:0]
reg [31:0] source_addr1; // Register to program the MAC source address [47:32]
reg [31:0] destination_addr0; // Register to program the MAC destination address [31:0]
reg [31:0] destination_addr1; // Register to program the MAC destination address [47:32]
reg [31:0] packet_tx_count; // Register to count the number of succesfully transmitted packets
reg [31:0] rand_seed0; // Register to program seed number for prbs generator [31:0]
reg [31:0] rand_seed1; // Register to program seed number for prbs generator [63:32]
reg [31:0] rand_seed2; // Register to program seed number for prbs generator [91:64]
reg random_payload; // Select what type of data pattern:0=incremental, 1=random
reg random_length; // Select what type of packet length:0=fixed, 1=random
reg [13:0] pkt_length; // Fixed payload length for every packet
wire [7:0] DA5,DA4,DA3,DA2,DA1,DA0;
wire [7:0] SA5,SA4,SA3,SA2,SA1,SA0;
wire [91:0] random_seed; // Random seed number for PRBS generator
wire S_IDLE;
wire S_DEST_SRC;
wire S_SRC_LEN_SEQ;
wire S_DATA;
wire S_TRANSITION;
reg[31:0] cnt_dasa, cnt_satlen, cnt_data, cnt_trnstn;
reg [2:0] ns;
reg [2:0] ps;
// State machine parameters
// --------------------------
localparam state_idle = 3'b000; // Idle State
localparam state_dest_src = 3'b001; // Dest(47:0) & Src(47:32) State
localparam state_src_len_seq = 3'b010; // Src(31:0) & Length(15:0) & SeqNr(15:0) State
localparam state_data = 3'b011; // Data Pattern State
localparam state_transition = 3'b100; // Transition State
wire [91:0] tx_prbs;
reg [15:0] byte_count;
reg [63:0] data_pattern;
reg [15:0] length;
reg [15:0] seq_num;
// Avalon-ST signals to CRC generator
// -----------------------------------
wire [3:0] empty;
reg [63:0] tx_data_reg;
reg tx_valid_reg;
reg tx_sop_reg;
reg tx_eop_reg;
reg [2:0] tx_empty_reg;
wire crc_valid;
wire [31:0] crc;
reg [31:0] crc_l1;
reg [31:0] crc_l2;
reg [31:0] crc_l3;
reg [31:0] crc_l4;
reg [2:0] crc_valid_count;
wire [31:0] checksum;
wire [63:0] tx_data_out;
wire [5:0] tx_ctrl_out;
reg add_extra_qword;
reg valid_extended;
reg eop_extended;
reg [2:0] empty_extended;
// ____________________________________________________________________________
// number packet register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) number_packet <= 32'h0;
else if (write & address == ADDR_NUMPKTS) number_packet <= writedata;
end
// ____________________________________________________________________________
// packet length setting register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) pkt_length <= 14'd0;
else if (write & address == ADDR_PKTLENGTH) pkt_length[13:0] <= writedata[13:0];
end
// ____________________________________________________________________________
// payload pattern setting register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) random_payload <= 1'h0;
else if (write & address == ADDR_RANDOMPAYLOAD) random_payload <= writedata[0];
end
// ____________________________________________________________________________
// packet length type (fixed or random) setting register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) random_length <= 1'h0;
else if (write & address == ADDR_RANDOMLENGTH) random_length <= writedata[0];
end
// ____________________________________________________________________________
// start register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) start_reg <= 1'h0;
else if (write & address == ADDR_START) start_reg <= writedata[0];
else if (start_reg) start_reg <= 1'b0; // clear itself
end
// used for edge detection because start_reg[0] assertion maybe > 1 clk long
reg start_d;
always @ (posedge reset or posedge clk)
begin
if (reset) start_d<= 1'd0;
else start_d<= start_reg;
end
assign start = start_reg & ~start_d;
// ____________________________________________________________________________
// stop register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) stop <= 1'h0;
else if (write & address == ADDR_STOP) stop <= writedata[0];
end
// ____________________________________________________________________________
// MAC source_addr0 register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) source_addr0 <= 32'h0;
else if (write & address == ADDR_MACSA0) source_addr0 <= writedata;
end
// ____________________________________________________________________________
// MAC dest_addr1 register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) source_addr1 <= 32'h0;
else if (write & address == ADDR_MACSA1) source_addr1[15:0] <= writedata[15:0];
end
// ____________________________________________________________________________
// MAC dest_addr0 register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) destination_addr0 <= 32'h0;
else if (write & address == ADDR_MACDA0) destination_addr0 <= writedata;
end
// ____________________________________________________________________________
// MAC dest_addr1 register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) destination_addr1 <= 32'h0;
else if (write & address == ADDR_MACDA1) destination_addr1[15:0] <= writedata[15:0];
end
assign {DA5,DA4,DA3,DA2,DA1,DA0} = {destination_addr1[15:0], destination_addr0[31:0]};
assign {SA5,SA4,SA3,SA2,SA1,SA0} = {source_addr1[15:0], source_addr0[31:0]};
// ____________________________________________________________________________
// packet_tx_count register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) begin
packet_tx_count <= 32'h0;
end else begin
if (start) begin
packet_tx_count <= 32'h0;
end else if (tx_ready & S_SRC_LEN_SEQ) begin
packet_tx_count <= packet_tx_count + 32'h1;
end
end
end
// ____________________________________________________________________________
// rand_seed0 register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) begin
// rand_seed0 <= 32'h0;
// initialize with non zero seed so that
// prbs works even when no random seed is
// provided by the user - ajay dubey
rand_seed0 <= 32'h5EED_0000;
end else begin
if (write & address == ADDR_RNDSEED0) begin
rand_seed0 <= writedata;
end
end
end
// ____________________________________________________________________________
// rand_seed1 register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) begin
// rand_seed1 <= 32'h0;
// initialize with non zero seed so that
// prbs works even when no random seed is
// provided by the user - ajay dubey
rand_seed1 <= 32'h5EED_0001;
end else begin
if (write & address == ADDR_RNDSEED1) begin
rand_seed1 <= writedata;
end
end
end
// ____________________________________________________________________________
// rand_seed2 register
// ____________________________________________________________________________
always @ (posedge reset or posedge clk)
begin
if (reset) begin
//rand_seed2 <= 32'h0;
// initialize with non zero seed so that
// prbs works even when no random seed is
// provided by the user - ajay dubey
rand_seed2 <= 32'h0002_5EED;
end else begin
if (write & address == ADDR_RNDSEED2) begin
rand_seed2[27:0] <= {5'd0,writedata[27:0]};
end
end
end
assign random_seed = {rand_seed2[27:0], rand_seed1[31:0], rand_seed0[31:0]};
// Output MUX of registers into readdata bus
always@(posedge clk or posedge reset)
begin
if(reset) readdata <= 32'h0;
else if (read) begin
case (address)
ADDR_NUMPKTS: readdata <= number_packet;
ADDR_RANDOMLENGTH: readdata <= random_length;
ADDR_RANDOMPAYLOAD: readdata <= random_payload;
ADDR_START: readdata <= start;
ADDR_STOP: readdata <= stop;
ADDR_MACSA0: readdata <= source_addr0;
ADDR_MACSA1: readdata <= source_addr1;
ADDR_MACDA0: readdata <= destination_addr0;
ADDR_MACDA1: readdata <= destination_addr1;
ADDR_TXPKTCNT: readdata <= packet_tx_count;
ADDR_RNDSEED0: readdata <= rand_seed0;
ADDR_RNDSEED1: readdata <= rand_seed1;
ADDR_RNDSEED2: readdata <= rand_seed2;
ADDR_CNTDASA: readdata <= cnt_dasa;
ADDR_CNTSATLEN: readdata <= cnt_satlen;
ADDR_CNTDATA: readdata <= cnt_data;
ADDR_CNTTRNSTN: readdata <= cnt_trnstn;
default: readdata <=32'h0;
endcase
end
end
// ____________________________________________________________
//
reg rddly, wrdly;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
wrdly <= 1'b0;
rddly <= 1'b0;
end
else
begin
wrdly <= write;
rddly <= read;
end
end
wire wredge = write& ~wrdly;
wire rdedge = read & ~rddly;
assign waitrequest = (wredge|rdedge); // your design is done with transaction when this goes down
// __________________________________________________________________________________
// PRBS Pattern Generator
// --------------------------------
prbs23 prbs_tx0
(
.clk (clk),
.rst_n (~reset),
.load (S_IDLE),
.enable (tx_ready & (S_SRC_LEN_SEQ | S_DATA)),
.seed (random_seed[22:0]),
.d (tx_prbs[22:0]),
.m (tx_prbs[22:0])
);
prbs23 prbs_tx1
(
.clk (clk),
.rst_n (~reset),
.load (S_IDLE),
.enable (tx_ready & (S_SRC_LEN_SEQ | S_DATA)),
.seed (random_seed[45:23]),
.d (tx_prbs[45:23]),
.m (tx_prbs[45:23])
);
prbs23 prbs_tx2
(
.clk (clk),
.rst_n (~reset),
.load (S_IDLE),
.enable (tx_ready & (S_SRC_LEN_SEQ | S_DATA)),
.seed (random_seed[68:46]),
.d (tx_prbs[68:46]),
.m (tx_prbs[68:46])
);
prbs23 prbs_tx3
(
.clk (clk),
.rst_n (~reset),
.load (S_IDLE),
.enable (tx_ready & (S_SRC_LEN_SEQ | S_DATA)),
.seed (random_seed[91:69]),
.d (tx_prbs[91:69]),
.m (tx_prbs[91:69])
);
// FSM State Machine for Generator
// --------------------------------
always @ (posedge reset or posedge clk)
begin
if (reset) begin
ps <= state_idle;
end else begin
if (start) begin
ps <= state_dest_src;
end else begin
ps <= ns;
end
end
end
always @ (*)
begin
ns = ps;
case (ps)
state_idle:begin
if (start) begin
ns = state_dest_src;
end
end
state_dest_src:begin
if (tx_ready) begin
ns = state_src_len_seq;
end
end
state_src_len_seq:begin
if (tx_ready & (length == 16'h0)) begin
ns = state_transition;
end else if (tx_ready) begin
ns = state_data;
end
end
state_data:begin
if (tx_ready & (byte_count[15] | byte_count == 16'h0)) begin
ns = state_transition;
end
end
state_transition:begin
if (stop | packet_tx_count == number_packet) begin
ns = state_idle;
end else if (tx_ready) begin
ns = state_dest_src;
end
end
default: ns = state_idle;
endcase
end
assign S_IDLE = (ns == state_idle) ? 1'b1 : 1'b0;
assign S_DEST_SRC = (ns == state_dest_src) ? 1'b1 : 1'b0;
assign S_SRC_LEN_SEQ = (ns == state_src_len_seq) ? 1'b1 : 1'b0;
assign S_DATA = (ns == state_data) ? 1'b1 : 1'b0;
assign S_TRANSITION = (ns == state_transition) ? 1'b1 : 1'b0;
// Length is used to store the payload length size. Payload length smaller than 46 will have zeros data padded
// Allowable fixed payload length: 6 -> 9582
// Allowable random payload length: 6 -> 1500
// --------------------------------------------------
always @ (posedge reset or posedge clk)
begin
if (reset) begin
length <= 16'h0;
end else begin
if (S_IDLE | S_TRANSITION) begin
if (~random_length & (pkt_length < 14'h0018)) begin
length <= 16'h0;
end else if (~random_length & (pkt_length > 14'h2580)) begin
length <= 16'h2568;
end else if (~random_length) begin
length <= {2'b00, pkt_length - 14'h18};
end else if (random_length) begin
length <= (tx_prbs[74:64] % 16'h05D7);
end
end
end
end
// Byte_count is used to keep track of how many bytes of data payload being generated out
// --------------------------------------------------------------------------------------
always @ (posedge reset or posedge clk)
begin
if (reset) begin
byte_count <= 16'h0;
end else begin
if (S_DEST_SRC) begin
byte_count <= length;
end else if (S_DATA & tx_ready) begin
byte_count <= byte_count - 16'h8;
end
end
end
// Seq_num is inserted into the first 2 bytes of data payload of every packet
// ---------------------------------------------------------------------------
always @ (posedge reset or posedge clk)
begin
if (reset) begin
seq_num <= 16'h0;
end else begin
if (start) begin
seq_num <= 16'h0;
end else if (S_TRANSITION & tx_ready) begin
seq_num <= seq_num + 16'h1;
end
end
end
// Generation of incremental data or pseudo random data
// -----------------------------------------------------
always @ (posedge reset or posedge clk)
begin
if (reset) begin
data_pattern <= 64'h0;
end else begin
if (S_IDLE & ~random_payload) begin
data_pattern <= 64'h0001020304050607;
end else if (S_DATA & ~random_payload & tx_ready & data_pattern == 64'hF8F9FAFBFCFDFEFF) begin
data_pattern <= 64'h0001020304050607;
end else if (S_DATA & ~random_payload & tx_ready) begin
data_pattern <= data_pattern + 64'h0808080808080808;
end else if ((S_SRC_LEN_SEQ | S_DATA) & random_payload & tx_ready) begin
data_pattern <= tx_prbs[63:0];
end
end
end
// Avalon-ST tx_data interface to CRC generator
// ---------------------------------------------
always @ (posedge reset or posedge clk)
begin
if (reset) begin
tx_data_reg <= 64'h0;
end else begin
if (S_DEST_SRC) begin
tx_data_reg[63:32] <= {DA5,DA4,DA3,DA2};
tx_data_reg[31: 0] <= {DA1,DA0,SA5,SA4};
end else if (S_SRC_LEN_SEQ) begin
tx_data_reg[63:32] <= {SA3,SA2,SA1,SA0};
tx_data_reg[31: 0] <= {length + 16'h6, seq_num};
end else if (S_DATA & tx_ready) begin
tx_data_reg <= data_pattern;
end
end
end
// Avalon-ST tx_valid interface to CRC generator
// ----------------------------------------------
always @ (posedge reset or posedge clk)
begin
if (reset) begin
tx_valid_reg <= 1'b0;
end else begin
if (S_IDLE | S_TRANSITION) begin
tx_valid_reg <= 1'b0;
end else begin
tx_valid_reg <= 1'b1;
end
end
end
// Avalon-ST tx_sop interface to CRC generator
// --------------------------------------------
always @ (posedge reset or posedge clk)
begin
if (reset) begin
tx_sop_reg <= 1'b0;
end else begin
if (S_DEST_SRC) begin
tx_sop_reg <= 1'b1;
end else begin
tx_sop_reg <= 1'b0;
end
end
end
// Avalon-ST tx_eop interface to CRC generator
// --------------------------------------------
always @ (posedge reset or posedge clk)
begin
if (reset) begin
tx_eop_reg <= 1'b0;
end else begin
if (S_SRC_LEN_SEQ & (length == 0)) begin
tx_eop_reg <= 1'b1;
end else if (S_DATA & tx_ready & (byte_count <= 8)) begin
tx_eop_reg <= 1'b1;
end else if (S_TRANSITION) begin
tx_eop_reg <= 1'b0;
end
end
end
// Avalon-ST tx_empty interface to CRC generator
// ----------------------------------------------
assign empty = 4'h8 - length[2:0];
always @ (posedge reset or posedge clk)
begin
if (reset) begin
tx_empty_reg <= 3'b000;
end else begin
if (S_DATA & tx_ready & (byte_count <= 8)) begin
tx_empty_reg <= empty[2:0];
end else if (S_TRANSITION) begin
tx_empty_reg <= 3'b000;
end
end
end
// Using CRC Compiler to generate checksum and append it to EOP
// -------------------------------------------------------------
/*
crcgen crcgen_inst
(
.clk (clk),
.data (tx_data_reg),
.datavalid (tx_valid_reg & tx_ready),
.empty (tx_empty_reg),
.endofpacket (tx_eop_reg),
.reset_n (~reset),
.startofpacket (tx_sop_reg),
.checksum (crc),
.crcvalid (crc_valid)
);
*/
// Using RAM based shift register to delay packet payload sending to TSE TX FIFO
// interface for CRC checksum merging at EOP
// -------------------------------------------------------------------------------
shiftreg_data shiftreg_data_inst
(
.aclr (reset),
.clken (tx_ready),
.clock (clk),
.shiftin (tx_data_reg),
.shiftout (tx_data_out),
.taps ()
);
// Using RAM based shift register to store and delay control signals
// ------------------------------------------------------------------
shiftreg_ctrl shiftreg_ctrl_inst
(
.aclr (reset),
.clken (tx_ready),
.clock (clk),
.shiftin ({tx_valid_reg, tx_sop_reg, tx_eop_reg, tx_empty_reg}),
.shiftout (tx_ctrl_out),
.taps ()
);
always @ (posedge reset or posedge clk)
begin
if (reset) begin
crc_valid_count <= 2'b00;
end else begin
crc_valid_count <= crc_valid_count + (crc_valid) - (tx_ready & tx_eop);
end
end
always @ (posedge reset or posedge clk)
begin
if (reset) begin
crc_l1 <= 32'h0;
crc_l2 <= 32'h0;
end else begin
if (crc_valid) begin
crc_l1 <= crc;
crc_l2 <= crc_l1;
crc_l3 <= crc_l2;
crc_l4 <= crc_l3;
end
end
end
assign checksum = (crc_valid_count == 3'b001) ? crc_l1 :
(crc_valid_count == 3'b010) ? crc_l2 :
(crc_valid_count == 3'b011) ? crc_l3 :
(crc_valid_count == 3'b100) ? crc_l4 :
32'h0;
// Extend packet by one cycle when not enough
// space in last word to add in checksum
// -------------------------------------------
always @ (*)
begin
add_extra_qword <= 1'b0;
if (tx_ctrl_out[5] & tx_ctrl_out[3]) begin // valid eop
if (tx_ctrl_out[2] == 1'b0) begin // Less than 4 empty bytes
add_extra_qword <= 1'b1;
end
end
end
always @ (posedge reset or posedge clk)
begin
if (reset) begin
valid_extended <= 1'b0;
eop_extended <= 1'b0;
empty_extended <= 3'b000;
end else begin
if (tx_ready) begin
if (add_extra_qword) begin
valid_extended <= 1'b1;
eop_extended <= 1'b1;
empty_extended[2] <= 1'b1;
empty_extended[1:0] <= tx_ctrl_out[1:0];
end else begin
valid_extended <= 1'b0;
eop_extended <= 1'b0;
empty_extended[2] <= 1'b0;
empty_extended[1:0] <= 3'b000;
end
end
end
end
always @ (posedge reset or posedge clk)
begin
if (reset) begin
tx_valid <= 1'b0;
tx_sop <= 1'b0;
tx_eop <= 1'b0;
tx_empty <= 1'b0;
end else begin
if (tx_ready) begin
tx_valid <= tx_ctrl_out[5] | valid_extended;
end else begin
//tx_valid <= 1'b0 ;
tx_valid <= tx_valid ; // ajay: remain unchanged
end
if (tx_ready) begin
//tx_valid <= tx_ctrl_out[5] | valid_extended; // ajay: unnecessary: already defined above
tx_sop <= tx_ctrl_out[4];
if (tx_ctrl_out[5] & tx_ctrl_out[3]) begin // valid eop
tx_eop <= !add_extra_qword; // keep original
end else begin
tx_eop <= eop_extended;
end
if (tx_ctrl_out[5] & tx_ctrl_out[3]) begin // valid eop
if (add_extra_qword) begin
tx_empty <= 3'b000;
end else begin
tx_empty <= tx_ctrl_out[2:0] - 3'h4;
end
end else begin
tx_empty <= empty_extended[2:0];
end
end
end
end
always @ (posedge reset or posedge clk)
begin
if (reset) begin
tx_data <= 64'h0;
end else begin
if (tx_ready) begin
tx_data <= tx_data_out; // By default
if (tx_ctrl_out[3]) begin // Normal EOP field
case (tx_ctrl_out[2:0])
3'b000: tx_data <= tx_data_out[63:0];
3'b001: tx_data <= {tx_data_out[63:8], checksum[31:24]};
3'b010: tx_data <= {tx_data_out[63:16], checksum[31:16]};
3'b011: tx_data <= {tx_data_out[63:24], checksum[31: 8]};
3'b100: tx_data <= {tx_data_out[63:32], checksum[31: 0]};
3'b101: tx_data <= {tx_data_out[63:40], checksum[31: 0], 8'h0};
3'b110: tx_data <= {tx_data_out[63:48], checksum[31: 0], 16'h0};
3'b111: tx_data <= {tx_data_out[63:56], checksum[31: 0], 24'h0};
default: tx_data <= tx_data_out;
endcase
end else if (eop_extended) begin
case (empty_extended)
3'b100: tx_data <= {checksum[31:0], 32'h0};
3'b101: tx_data <= {checksum[23:0], 40'h0};
3'b110: tx_data <= {checksum[15:0], 48'h0};
3'b111: tx_data <= {checksum[ 7:0], 56'h0};
default: tx_data <= 64'h0;
endcase
end
end
end
end
assign tx_error = 1'b0;
// ___________________________________________________________________________________________
// Debug Logic
// ___________________________________________________________________________________________
reg ppln_dasa, ppln_satlen, ppln_data, ppln_trnstn;
always @ (posedge reset or posedge clk)
begin
if (reset)
begin
ppln_dasa <= 1'b0;
ppln_satlen <= 1'b0;
ppln_data <= 1'b0;
ppln_trnstn <= 1'b0;
end
else
begin
ppln_dasa <= S_DEST_SRC;
ppln_satlen <= S_SRC_LEN_SEQ;
ppln_data <= S_DATA;
ppln_trnstn <= S_TRANSITION;
end
end
wire ena_dasa = S_DEST_SRC & ~ppln_dasa;
wire ena_satlen = S_SRC_LEN_SEQ & ~ppln_satlen;
wire ena_data = S_DATA & ~ppln_data;
wire ena_trnstn = S_TRANSITION & ~ppln_trnstn;
always @ (posedge reset or posedge clk)
begin
if (reset)
begin
cnt_dasa <= 32'd0;
cnt_satlen <= 32'd0;
cnt_data <= 32'd0;
cnt_trnstn <= 32'd0;
end
else
begin
if (ena_dasa) cnt_dasa <= cnt_dasa + 32'd1;
if (ena_satlen) cnt_satlen <= cnt_satlen + 32'd1;
if (ena_data) cnt_data <= cnt_data + 32'd1;
if (ena_trnstn) cnt_trnstn <= cnt_trnstn + 32'd1;
end
end
endmodule
// ___________________________________________________________________________________________________
// PRBS23 GENERATOR
// ___________________________________________________________________________________________________
//-----------------------------------------------------------------------------
// Functional Description:
// This module is the Pseudo-Random Bit Sequence 23 Block
// where g(x) = x^23 + x^18 + x^0
//
// use lsb of m 1st first
// k can be > N, but part of the sequence will be skipped
//
//-------------------------------------------------------------------------------
//
// Copyright 2007 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera
// turn off bogus verilog processor warnings
// altera message_off 10034 10035 10036 10037 10230
module prbs23 ( clk, rst_n, load, enable, seed, d, m);
parameter k = 23; //step value = a^k
parameter N = 23;
input clk;
input rst_n;
input load;
input enable;
input [N-1:0] seed;
input [N-1:0] d;
output [N-1:0] m;
reg [N-1:0] m;
reg [N-1:0] tmpa;
reg [N-1:0] tmpb;
integer i,j;
always @ (d)
begin
tmpa = d;
for (i=0; i<k; i=i+1)
begin
for (j=0; j<(N-1); j=j+1) begin tmpb[j] = tmpa[j+1]; end
tmpb[N-1] = tmpa[18] ^ tmpa[0]; //x^23 + x[18] + x[0]
tmpa = tmpb;
end
end
always @(posedge clk or negedge rst_n)
begin
begin
if (!rst_n) m <= 0;
else if (load) m <= seed;
else if (enable) m <= tmpb;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_SYMBOL_V
`define SKY130_FD_SC_HDLL__CLKBUF_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_SYMBOL_V
|
`timescale 1ns/1ps
`include "definitions.v"
`include "decodificador.v"
`include "Module_ROM.v"
`include "WB.v"
`include "ALU.v"
`include "Mux.v"
`include "memory.v"
`include "FFD.v"
`include "pc_decider.v"
`include "generator.v"
module BancoPruebas;
wire Clock,Reset;
wire [9:0] wAddress;
wire [15:0] wInstruction;
wire [9:0] wBranchAddress;
wire [7:0] rConstant;
wire [7:0] wAreg;
wire [7:0] wBreg;
generator g1(Clock,Reset);
ROM r1(
.iAddress(wAddress),
.oInstruction(wInstruction)
);
wire wBranchTaken;
wire wJumpTaken;
wire wCa;
wire wCb;
pc_Decider pc1(
.Clock(Clock),
.Reset(Reset),
.wIP(wAddress),
.wBranchTaken(wBranchTaken),
.wJumpTaken(wJumpTaken),
.wBranchAddress(wBranchAddress)
);
wire a_sel;
wire b_sel;
decodificador dec1(
.Clock(Clock),
.wInstruction(wInstruction),
.wZa(wAreg==6'b0),
.wZb(wBreg==6'b0),
.wNa(wAreg[7]),
.wNb(wBreg[7]),
.wCa(wCa),
.wCb(wCb),
.rBranch_taken(wBranchTaken),
.rJumpTaken(wJumpTaken),
.rBranch_dir(wBranchAddress),
.rC(rConstant),
.rMux_a_sel(a_sel),
.rMux_b_sel(b_sel)
);
wire [7:0] wOut_Mux_A;
Mux2 #(8) muxa(
.wSelect(a_sel),
.wA(wAreg),
.wB(rConstant),
.rOut(wOut_Mux_A)
);
wire[15:0] wInstructionToAlu;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16) FFDInstruciton(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction),
.Q(wInstructionToAlu)
);
wire [7:0] wOut_Mux_B;
Mux2 #(8) muxb(
.wSelect(b_sel),
.wA(wBreg),
.wB(rConstant),
.rOut(wOut_Mux_B)
);
wire [7:0] outAlu;
wire [7:0] outAlutoRam;
wire [9:0]wRamAddress;
wire [9:0] oRamAddress;
wire wWriteA;
wire wWriteB;
wire ReadA;
wire ReadB;
wire wRamEnable;
ALU alu(
.wInstruction(wInstructionToAlu),
.iA(wOut_Mux_A),
.iB(wOut_Mux_B),
.oRamEnableWrite(wRamEnable),
.oData(outAlu),
.oWriteA(wWriteA),
.oWriteB(wWriteB),
.wCa(wCa),
.wCb(wCb),
.oRamAddress(wRamAddress),
.oReadA(ReadA),
.oReadB(ReadB)
);
///FFD de la alu a la ram y leugo al wb
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8) FFDalutoram
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(outAlu),
.Q(outAlutoRam)
);
wire [7:0] outAlutoWB;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8) FFDalutowb
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(outAlutoRam),
.Q(outAlutoWB)
);
//ReadA
wire ReadAtoRam;
wire ReadAtoWB;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1) FFDReadAtoram
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(ReadA),
.Q(ReadAtoRam)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1) FFDReadAtowb
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(ReadAtoRam),
.Q(ReadAtoWB)
);
//READB
wire ReadBtoRam;
wire ReadBtoWB;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1) FFDReadBtoram
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(ReadB),
.Q(ReadBtoRam)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1) FFDReadBtowb
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(ReadBtoRam),
.Q(ReadBtoWB)
);
//WRITEA
wire wWriteABUF;
wire wWriteAtoWB;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1) FFDWriteAtoram
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wWriteA),
.Q(wWriteABUF)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1) FFDWriteAtowb
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wWriteABUF),
.Q(wWriteAtoWB)
);
//WRITEB
wire wWriteBBUF;
wire wWriteBtoWB;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1) FFDWriteBtoram
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wWriteB),
.Q(wWriteBBUF)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1) FFDWriteBtowb
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wWriteBBUF),
.Q(wWriteBtoWB)
);
wire oRamEnableWrite;
///ram enable
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1) FFDramenable
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wRamEnable),
.Q(oRamEnableWrite)
);
///ram address
FFD_POSEDGE_SYNCRONOUS_RESET # ( 10) FFDRamaddress
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wRamAddress),
.Q(oRamAddress)
);
wire [7:0] ramA;
wire [7:0] ramB;
MEMORY #( 8 ,10 ,1024 ) ram_memory(
.Clock(Clock),
.iWriteEnable(oRamEnableWrite),
.iAddress(oRamAddress),
.iReadtoa(ReadAtoRam),
.iReadtob(ReadBtoRam),
.iDataIn(outAlutoRam),
.oDataOuta(ramA),
.oDataOutb(ramB)
);
wire [7:0] A;
WBX WBA(
.iRead(ReadAtoWB),
.iWrite(wWriteAtoWB),
.iDataRAM(ramA),
.iDataALU(outAlutoWB),
.iRegister(A),
.oRegister(A)
);
wire [7:0] B;
WBX WBB(
.iRead(ReadBtoWB),
.iWrite(wWriteBtoWB),
.iDataRAM(ramB),
.iDataALU(outAlutoWB),
.iRegister(B),
.oRegister(B)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8) FFDA(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(A),
.Q(wAreg)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8) FFDB(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(B),
.Q(wBreg)
);
initial
begin
$dumpfile("signals.vcd");
$dumpvars;
#70000 ;
$display ("Test finished");
$finish;
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Slave Model ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_slv_model.v,v 1.2 2002-02-01 01:55:44 rudi Exp $
//
// $Date: 2002-02-01 01:55:44 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.1.1.1 2001/03/19 13:11:29 rudi
// Initial Release
//
//
//
`include "wb_model_defines.v"
module wb_slv(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
input clk, rst;
input [31:0] adr, din;
output [31:0] dout;
input cyc, stb;
input [3:0] sel;
input we;
output ack, err, rty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
parameter mem_size = 13;
parameter sz = (1<<mem_size)-1;
reg [31:0] mem[sz:0];
wire mem_re, mem_we;
wire [31:0] tmp;
reg [31:0] dout, tmp2;
reg err, rty;
reg [31:0] del_ack;
reg [5:0] delay;
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
initial
begin
delay = 0;
err = 0;
rty = 0;
#2;
$display("\nINFO: WISHBONE MEMORY MODEL INSTANTIATED (%m)");
$display(" Memory Size %0d address lines %0d words\n",
mem_size, sz+1);
end
assign mem_re = cyc & stb & !we;
assign mem_we = cyc & stb & we;
assign tmp = mem[adr[mem_size+1:2]];
always @(sel or tmp or mem_re or ack)
if(mem_re & ack)
begin
dout[31:24] <= #1 sel[3] ? tmp[31:24] : 8'hxx;
dout[23:16] <= #1 sel[2] ? tmp[23:16] : 8'hxx;
dout[15:08] <= #1 sel[1] ? tmp[15:08] : 8'hxx;
dout[07:00] <= #1 sel[0] ? tmp[07:00] : 8'hxx;
end
else dout <= #1 32'hzzzz_zzzz;
always @(sel or tmp or din)
begin
tmp2[31:24] = !sel[3] ? tmp[31:24] : din[31:24];
tmp2[23:16] = !sel[2] ? tmp[23:16] : din[23:16];
tmp2[15:08] = !sel[1] ? tmp[15:08] : din[15:08];
tmp2[07:00] = !sel[0] ? tmp[07:00] : din[07:00];
end
always @(posedge clk)
if(mem_we) mem[adr[mem_size+1:2]] <= #1 tmp2;
always @(posedge clk)
del_ack = ack ? 0 : {del_ack[30:0], (mem_re | mem_we)};
assign #3 ack = cyc & ((delay==0) ? (mem_re | mem_we) : del_ack[delay-1]);
task fill_mem;
input mode;
integer n, mode;
begin
for(n=0;n<(sz+1);n=n+1)
begin
case(mode)
0: mem[n] = { ~n[15:0], n[15:0] };
1: mem[n] = $random;
endcase
end
end
endtask
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: alu_mul.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alu_mul (
dataa,
datab,
result);
input [7:0] dataa;
input [7:0] datab;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 8,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "8"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "16"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "16"
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: TU Darmstadt
// Engineer: Mahdi Enan
//
// Create Date: 10:05:08 01/18/2017
// Design Name: lCounter
// Module Name: tb_lCounter.v
// Project Name: spongent
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: lCounter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lCounter;
// Inputs
reg [15:0] lfsr;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
lCounter uut (
.lfsr(lfsr),
.out(out)
);
initial begin
// Initialize Inputs
lfsr = 16'b0000000000000000;
// Wait 100 ns for global reset to finish
#100;
while (lfsr < 16'b1111111111111111)
begin
$display ("lfsr=%d, (hex): %h", lfsr, out);
#1;
lfsr = lfsr + 1;
#1;
end
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file data_ram.v when simulating
// the core, data_ram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module data_ram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [3 : 0] wea;
input [7 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
input clkb;
input [3 : 0] web;
input [7 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(4),
.C_WEB_WIDTH(4),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_P_PP_PG_N_TB_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_P_PP_PG_N_TB_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_dlatch_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_P_PP_PG_N_TB_V
|
/*
******************************************************************************
* File Name : tb_ada_id_stage.v
* Project : NR1K processor
* Version : 0.1
* Date : Aug 28th, 2014
* Author : Angel Terrones <[email protected]>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Testbench for the Instruction decode Stage
******************************************************************************
*/
`timescale 1ns / 1ns
`include "ada_defines.v"
`define cycle 10
module tb_ada_id_stage;
reg clk;
reg rst;
reg [31:0] instruction;
reg [31:0] pc_current;
reg [31:0] pc_next;
reg [1:0] forward_port_a_select;
reg [1:0] forward_port_b_select;
reg [31:0] exu_fwd_data;
reg [31:0] mem_fwd_data;
reg [31:0] wb_fwd_data;
reg [4:0] wb_gpr_wa;
reg [31:0] wb_gpr_wd;
reg wb_gpr_we;
reg [31:0] sr_data_input;
reg sr_sm;
wire haz_take_branch;
wire exc_op_reset;
wire exc_op_shutdown;
wire exc_op_syscall;
wire exc_op_break;
wire exc_op_invalid;
wire exc_op_rfe;
wire exc_op_rfb;
wire exc_bad_branch_addr;
wire [31:0] pc_branch_address;
wire [4:0] id_gpr_port_a;
wire [4:0] id_gpr_port_b;
wire [4:0] exu_operation;
wire [31:0] exu_port_a;
wire [31:0] exu_port_b;
wire [31:0] mem_store_data;
wire [4:0] exu_gpr_wa;
wire exu_gpr_we;
wire [4:0] sr_ra;
wire [4:0] sr_wa;
wire [31:0] sr_wd;
wire sr_we;
wire mem_write;
wire mem_read;
wire mem_byte;
wire mem_halfword;
wire mem_sign_ext;
wire mem_exu_mem_select;
//--------------------------------------------------------------------------
// UUT
//--------------------------------------------------------------------------
ada_id_stage uut(
.clk(clk),
.instruction(instruction),
.pc_current(pc_current),
.pc_next(pc_next),
.forward_port_a_select(forward_port_a_select),
.forward_port_b_select(forward_port_b_select),
.exu_fwd_data(exu_fwd_data),
.mem_fwd_data(mem_fwd_data),
.wb_fwd_data(wb_fwd_data),
.wb_gpr_wa(wb_gpr_wa),
.wb_gpr_wd(wb_gpr_wd),
.wb_gpr_we(wb_gpr_we),
.sr_data_input(sr_data_input),
.sr_sm(sr_sm),
.haz_take_branch(haz_take_branch),
.exc_op_reset(exc_op_reset),
.exc_op_shutdown(exc_op_shutdown),
.exc_op_syscall(exc_op_syscall),
.exc_op_break(exc_op_break),
.exc_op_invalid(exc_op_invalid),
.exc_op_rfe(exc_op_rfe),
.exc_op_rfb(exc_op_rfb),
.exc_bad_branch_addr(exc_bad_branch_addr),
.pc_branch_address(pc_branch_address),
.id_gpr_port_a(id_gpr_port_a),
.id_gpr_port_b(id_gpr_port_b),
.exu_operation(exu_operation),
.exu_port_a(exu_port_a),
.exu_port_b(exu_port_b),
.mem_store_data(mem_store_data),
.exu_gpr_wa(exu_gpr_wa),
.exu_gpr_we(exu_gpr_we),
.sr_ra(sr_ra),
.sr_wa(sr_wa),
.sr_wd(sr_wd),
.sr_we(sr_we),
.mem_write(mem_write),
.mem_read(mem_read),
.mem_byte(mem_byte),
.mem_halfword(mem_halfword),
.mem_sign_ext(mem_sign_ext),
.mem_exu_mem_select(mem_exu_mem_select)
);
//--------------------------------------------------------------------------
// Setup
//--------------------------------------------------------------------------
initial begin
// Initialize Inputs
clk = 1;
rst = 1;
instruction = 32'h0000_0000;
pc_current = 32'hDEAD_BEEF;
pc_next = 32'hDEAD_C0DE;
forward_port_a_select = 2'b00;
forward_port_b_select = 2'b00;
exu_fwd_data = 32'hA0A0_B0B0;
mem_fwd_data = 32'hA1A1_B1B1;
wb_fwd_data = 32'hA2A2_B2B2;
wb_gpr_wa = 5'b00000;
wb_gpr_wd = 32'h0101_0404;
wb_gpr_we = 0;
sr_data_input = 32'h0BAD_F00D;
sr_sm = 0;
// dump the wave file
$dumpfile("tb_id_stage.vcd");
$dumpvars;
end
//--------------------------------------------------------------------------
// clock
//--------------------------------------------------------------------------
always begin
#(`cycle/2) clk = !clk;
end
//--------------------------------------------------------------------------
// simulation
//--------------------------------------------------------------------------
initial begin
rst = #(5*`cycle)0;
$display("Testing the ID stage.");
@(posedge clk)
wb_gpr_wa = 5'b00000;
wb_gpr_we = 1;
@(posedge clk)
wb_gpr_wa = 5'b00001;
@(posedge clk)
wb_gpr_wa = 5'b00010;
@(posedge clk)
wb_gpr_wa = 5'b00011;
@(posedge clk)
wb_gpr_wa = 5'b00100;
@(posedge clk)
wb_gpr_wa = 5'b00101;
@(posedge clk)
wb_gpr_wa = 5'b00110;
@(posedge clk)
wb_gpr_we = 0;
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_ADD, 5'b01000, 5'b0001, 5'b00010, 5'b00000, `EXT_OP_ADD}; // R8 <= R1 + R2
forward_port_a_select = 2'b00;
forward_port_b_select = 2'b00;
@(posedge clk)
forward_port_a_select = 2'b01;
forward_port_b_select = 2'b00;
@(posedge clk)
forward_port_a_select = 2'b10;
forward_port_b_select = 2'b00;
@(posedge clk)
forward_port_a_select = 2'b11;
forward_port_b_select = 2'b00;
@(posedge clk)
forward_port_a_select = 2'b00;
forward_port_b_select = 2'b01;
@(posedge clk)
forward_port_a_select = 2'b00;
forward_port_b_select = 2'b10;
@(posedge clk)
forward_port_a_select = 2'b00;
forward_port_b_select = 2'b11;
@(posedge clk)
forward_port_a_select = 2'b00;
forward_port_b_select = 2'b00;
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_ADDI, 5'b01001, 5'b00100, 16'h0100}; // R9 <= R4 + 0x0100
forward_port_a_select = 2'b00;
forward_port_b_select = 2'b00;
@(posedge clk)
forward_port_a_select = 2'b01;
forward_port_b_select = 2'b00;
@(posedge clk)
forward_port_a_select = 2'b10;
forward_port_b_select = 2'b00;
@(posedge clk)
forward_port_a_select = 2'b11;
forward_port_b_select = 2'b00;
@(posedge clk)
forward_port_a_select = 2'b00;
forward_port_b_select = 2'b01;
@(posedge clk)
forward_port_a_select = 2'b00;
forward_port_b_select = 2'b10;
@(posedge clk)
forward_port_a_select = 2'b00;
forward_port_b_select = 2'b11;
@(posedge clk)
forward_port_a_select = 2'b00;
forward_port_b_select = 2'b00;
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_B, 5'b11111, 21'h00_0001};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_B, 5'b11111, 21'h00_AA00};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_BE, 5'b11111, 5'b0001, 16'h0010};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_BE, 5'b00011, 5'b00001, 16'h0100};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_BG, 5'b11111, 5'b00000, 16'h0101};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_BG, 5'b11111, 5'b00010, 16'h0110};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_CALL, 5'b11111, 21'h00_CA77}; //
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_CALLR, 5'b11111, 5'b0000, 5'b00001, 5'b00000, `EXT_OP_CALLR};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_LDSB, 5'b00010, 5'b00000, 16'h0001};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_LDSH, 5'b0011, 5'b00000, 16'h002};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_LDUB, 5'b00100, 5'b00000, 16'h0003};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_LDUH, 5'b00101, 5'b00000, 16'h0004};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_LDUI, 5'b00110, 5'b00000, 16'h2345};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_LDW, 5'b00111, 5'b00000, 16'h0020};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_RESET, 5'b00000, 5'b00000, 5'b00000, 5'b00000, `EXT_OP_RESET};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_RFE, 5'b00000, 5'b00000, 5'b00000, 5'b00000, `EXT_OP_RFE};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_RFB, 5'b00000, 5'b00000, 5'b00000, 5'b00000, `EXT_OP_RFB};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_RSCR, 5'b11111, 5'b0000, 5'b00001, 5'b00000, `EXT_OP_RSCR};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_RESET, 5'b00000, 5'b00000, 5'b00000, 5'b00000, `EXT_OP_RESET};
sr_sm = 1;
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_RFE, 5'b00000, 5'b00000, 5'b00000, 5'b00000, `EXT_OP_RFE};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_RFB, 5'b00000, 5'b00000, 5'b00000, 5'b00000, `EXT_OP_RFB};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_RSCR, 5'b11111, 5'b0000, 5'b00001, 5'b00000, `EXT_OP_RSCR};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = {`OP_WSCR, 5'b00101, 5'b0011, 5'b00000, 5'b00000, `EXT_OP_WSCR};
//---------------------------------------------------------------------------------------------
@(posedge clk)
instruction = 32'h0000_0000;
sr_sm = 0;
//---------------------------------------------------------------------------------------------
@(posedge clk)
//---------------------------------------------------------------------------------------------
$display("Test finished");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_BLACKBOX_V
`define SKY130_FD_SC_LP__AND3B_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3b (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_BLACKBOX_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:sem:4.1
// IP Revision: 7
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module sem_0 (
status_heartbeat,
status_initialization,
status_observation,
status_correction,
status_classification,
status_injection,
status_essential,
status_uncorrectable,
monitor_txdata,
monitor_txwrite,
monitor_txfull,
monitor_rxdata,
monitor_rxread,
monitor_rxempty,
icap_o,
icap_csib,
icap_rdwrb,
icap_i,
icap_clk,
icap_request,
icap_grant,
fecc_crcerr,
fecc_eccerr,
fecc_eccerrsingle,
fecc_syndromevalid,
fecc_syndrome,
fecc_far,
fecc_synbit,
fecc_synword
);
output wire status_heartbeat;
output wire status_initialization;
output wire status_observation;
output wire status_correction;
output wire status_classification;
output wire status_injection;
output wire status_essential;
output wire status_uncorrectable;
output wire [7 : 0] monitor_txdata;
output wire monitor_txwrite;
input wire monitor_txfull;
input wire [7 : 0] monitor_rxdata;
output wire monitor_rxread;
input wire monitor_rxempty;
input wire [31 : 0] icap_o;
output wire icap_csib;
output wire icap_rdwrb;
output wire [31 : 0] icap_i;
input wire icap_clk;
output wire icap_request;
input wire icap_grant;
input wire fecc_crcerr;
input wire fecc_eccerr;
input wire fecc_eccerrsingle;
input wire fecc_syndromevalid;
input wire [12 : 0] fecc_syndrome;
input wire [25 : 0] fecc_far;
input wire [4 : 0] fecc_synbit;
input wire [6 : 0] fecc_synword;
sem_v4_1_7_x7_sem_controller #(
.c_xdevice("kintex7"),
.c_xpackage("ffg676"),
.c_xspeedgrade("-2"),
.c_xdevicefamily("kintex7"),
.c_family("kintex7"),
.c_device_array(33554435),
.c_icapwidth(32),
.c_eipwidth(40),
.c_farwidth(26),
.c_component_name("sem_0"),
.c_clock_per(10000),
.c_feature_set(16),
.c_hardware_cfg(6),
.c_software_cfg(9),
.b_debug(0),
.b_cosim(0),
.b_dfset(0),
.b_gen_user_app(0)
) inst (
.status_heartbeat(status_heartbeat),
.status_initialization(status_initialization),
.status_observation(status_observation),
.status_correction(status_correction),
.status_classification(status_classification),
.status_injection(status_injection),
.status_essential(status_essential),
.status_uncorrectable(status_uncorrectable),
.fetch_txdata(),
.fetch_txwrite(),
.fetch_txfull(1'B0),
.fetch_rxdata(8'B0),
.fetch_rxread(),
.fetch_rxempty(1'B1),
.fetch_tbladdr(32'B0),
.monitor_txdata(monitor_txdata),
.monitor_txwrite(monitor_txwrite),
.monitor_txfull(monitor_txfull),
.monitor_rxdata(monitor_rxdata),
.monitor_rxread(monitor_rxread),
.monitor_rxempty(monitor_rxempty),
.inject_strobe(1'B0),
.inject_address(40'B0),
.icap_o(icap_o),
.icap_csib(icap_csib),
.icap_rdwrb(icap_rdwrb),
.icap_i(icap_i),
.icap_clk(icap_clk),
.icap_request(icap_request),
.icap_grant(icap_grant),
.fecc_crcerr(fecc_crcerr),
.fecc_eccerr(fecc_eccerr),
.fecc_eccerrsingle(fecc_eccerrsingle),
.fecc_syndromevalid(fecc_syndromevalid),
.fecc_syndrome(fecc_syndrome),
.fecc_far(fecc_far),
.fecc_synbit(fecc_synbit),
.fecc_synword(fecc_synword)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module HLS_accel_fcmp_32ns_32ns_1_1
#(parameter
ID = 4,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 1
)(
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
input wire [4:0] opcode,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Parameter----------------------
// AutoESL opcode
localparam [4:0]
AP_OEQ = 5'b00001,
AP_OGT = 5'b00010,
AP_OGE = 5'b00011,
AP_OLT = 5'b00100,
AP_OLE = 5'b00101,
AP_ONE = 5'b00110,
AP_UNO = 5'b01000;
// FPV6 opcode
localparam [7:0]
OP_EQ = 8'b00010100,
OP_GT = 8'b00100100,
OP_GE = 8'b00110100,
OP_LT = 8'b00001100,
OP_LE = 8'b00011100,
OP_NE = 8'b00101100,
OP_UO = 8'b00000100;
//------------------------Local signal-------------------
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire op_tvalid;
reg [7:0] op_tdata;
wire r_tvalid;
wire [7:0] r_tdata;
//------------------------Instantiation------------------
HLS_accel_ap_fcmp_0_no_dsp_32 HLS_accel_ap_fcmp_0_no_dsp_32_u (
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.s_axis_operation_tvalid ( op_tvalid ),
.s_axis_operation_tdata ( op_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata = din0==='bx ? 'b0 : din0;
assign b_tvalid = 1'b1;
assign b_tdata = din1==='bx ? 'b0 : din1;
assign op_tvalid = 1'b1;
assign dout = r_tdata[0];
always @(*) begin
case (opcode)
AP_OEQ : op_tdata = OP_EQ;
AP_OGT : op_tdata = OP_GT;
AP_OGE : op_tdata = OP_GE;
AP_OLT : op_tdata = OP_LT;
AP_OLE : op_tdata = OP_LE;
AP_ONE : op_tdata = OP_NE;
AP_UNO : op_tdata = OP_UO;
default : op_tdata = OP_EQ;
endcase
end
endmodule
|
// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_sample_cycle_ratio
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_clock_converter_v2_1_8_axic_sample_cycle_ratio # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SLOW_ACLK,
input wire FAST_ACLK,
output wire SAMPLE_CYCLE_EARLY,
output wire SAMPLE_CYCLE
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg slow_aclk_div2 = 0;
reg posedge_finder_first;
reg posedge_finder_second;
wire first_edge;
wire second_edge;
reg [P_DELAY-1:0] sample_cycle_d;
(* shreg_extract = "no" *) reg sample_cycle_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_RATIO == 1) begin : gen_always_sample
assign SAMPLE_CYCLE_EARLY = 1'b1;
assign SAMPLE_CYCLE = 1'b1;
end
else begin : gen_sample_cycle
genvar i;
always @(posedge SLOW_ACLK) begin
slow_aclk_div2 <= ~slow_aclk_div2;
end
// Find matching rising edges by clocking slow_aclk_div2 onto faster clock
always @(posedge FAST_ACLK) begin
posedge_finder_first <= slow_aclk_div2;
end
always @(posedge FAST_ACLK) begin
posedge_finder_second <= ~slow_aclk_div2;
end
assign first_edge = slow_aclk_div2 & ~posedge_finder_first;
assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;
always @(*) begin
sample_cycle_d[P_DELAY-1] = first_edge | second_edge;
end
// delay the posedge alignment by C_RATIO - 1 to set the sample cycle as
// the clock one cycle before the posedge.
for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay
always @(posedge FAST_ACLK) begin
sample_cycle_d[i-1] <= sample_cycle_d[i];
end
end
always @(posedge FAST_ACLK) begin
sample_cycle_r <= sample_cycle_d[0];
end
assign SAMPLE_CYCLE_EARLY = sample_cycle_d[0];
assign SAMPLE_CYCLE = sample_cycle_r;
end
endgenerate
endmodule // axisc_sample_cycle_ratio
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCON_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__FAHCON_PP_BLACKBOX_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCON_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_SYMBOL_V
`define SKY130_FD_SC_LS__OR3B_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAH_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__FAH_FUNCTIONAL_PP_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAH_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_BEHAVIORAL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd2 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_NSR_PP_PG_N_TB_V
`define SKY130_FD_SC_MS__UDP_DFF_NSR_PP_PG_N_TB_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 SET = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 NOTIFIER = 1'b1;
#180 RESET = 1'b1;
#200 SET = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 NOTIFIER = 1'b0;
#300 RESET = 1'b0;
#320 SET = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SET = 1'b1;
#440 RESET = 1'b1;
#460 NOTIFIER = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SET = 1'bx;
#560 RESET = 1'bx;
#580 NOTIFIER = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N dut (.SET(SET), .RESET(RESET), .D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_NSR_PP_PG_N_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__XOR2_PP_SYMBOL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_PP_BLACKBOX_V
/**
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer,
* vpb/vnb taps, double-row-height
* cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_PP_BLACKBOX_V
|
`include "bsg_defines.v"
`include "config_defs.v"
// fixme: label all signals with clock prefix, and use bsg_ip_cores macros to hardplace CDC regions
// and rNandMeta
module config_node
#(parameter // node specific parameters
id_p = -1, // unique ID of this node
data_bits_p = -1, // number of bits of configurable register associated with this node
default_p = -1 // default/reset value of configurable register associated with this node
)
(
// this includes the config clock and a single config data line
input config_s config_i, // from IO pads
// all of these signals are relative to the destination clock domain
input clk, // destination side clock from pins
input reset, // destination side reset from pins
// whether data_o is new
output logic data_new_r_o,
output [data_bits_p - 1 : 0] data_r_o
);
localparam debug_lp = 0;
localparam data_rx_len_lp = (data_bits_p + (data_bits_p / data_frame_len_lp) + frame_bit_size_lp);
// + frame_bit_size_lp means the end, or msb of received data is always framing bits
// if data_bits_p is a multiple of data_frame_len_lp, "00" is expected at the end of received data
localparam shift_width_lp = (data_rx_len_lp + frame_bit_size_lp +
id_width_lp + frame_bit_size_lp +
len_width_lp + frame_bit_size_lp +
valid_bit_size_lp);
// shift register width of this node
/* The communication packet is defined as follows:
* msb lsb
* | data_rx | frame bits | node id | frame bits | packet length | frame bits | valid bits |
*
* valid bit is defined as "10".
* packet length equals the number of bits in one complete packet, i.e. msb - lsb + 1.
* frame bits are certain patterns to separate packet content, defined as '0'.
* node id is an unique integer to identify current node.
* data_rx contains the data payload and framing bits inserted every data_frame_len_lp bits.
*
* Before use, reset the configuration node is mandatory by sending continuous '1's, and the
* minimum length of the reset sequence is (frame_bit_size_lp * 2 + len_width_lp), or the
* indicated field above.
*
* Each node contains a shift register that represents the same structure of a complete packet,
* and the node begins interpret received packet once it sees a '0' in the lsb of the shift
* register. The node determines if it is the target according to the node id bits. If so, the
* node captures received data, remove framing bits and write the data to its internal register.
* Otherwise, the node simply passes every bit to its subsequent node.
*/
typedef struct packed {
logic [data_rx_len_lp - 1 : 0] rx; // data_rx
logic f2; // frame bit 2
logic [id_width_lp - 1 : 0] id; // node id
logic [frame_bit_size_lp - 1 : 0] f1; // frame bit 1
logic [len_width_lp - 1 : 0] len; // packet length
logic [frame_bit_size_lp - 1 : 0] f0; // frame bit 0
logic [valid_bit_size_lp - 1 : 0] valid; // valid bits
} node_packet_s;
node_packet_s shift_n, shift_r; // shift register
logic [id_width_lp - 1 : 0] node_id;
logic cfg_reset; // configuration network reset signal
logic valid; // begin of packet signal
logic match; // node id match signal
logic data_en; // data_r write enable
logic ready_n, ready_r; // data_r ready and corresponding registers for clock domain crossing
// no combinational logic between ready_r and its destination side receiver,
// to reduce the change to go metastable
logic ready_synced; // ready signal which is passed through the bsg_launch_sync_sync to
// cross clock domains
logic [len_width_lp - 1 : 0] packet_len;
logic [$bits(integer) - 1 : 0] count_n_int; // to avoid type casting warnings from Lint
logic [len_width_lp - 1 : 0] count_n, count_r; // bypass counter
logic count_non_zero; // bypass counter is zero signal
logic [data_rx_len_lp - 1 : 0] data_rx;
logic [data_bits_p - 1 : 0] data_n, data_r; // data payload register
logic [1 : 0] sync_shift_n, sync_shift_r; // edge detection registers
// The following two signals are used to detect the reset posedge.
// Suppose that apart from this configuration network the remaining part of
// the chip resets on 1 of the reset_input, now if the configuration
// registers are made to reset on posedge of the reset_input, it is possible
// to configure those registers while the rest of chip is being reset,
// reducing the chance for the chip to go metastable. The reset_input is
// pulled down when it's safe to believe all configuration registers are
// properly loaded and stable.
// Here it is not necessary to reset configuration registers strictly on the
// posedge of reset_input, therefore the following two signals are used to
// detect a delayed posedge of reset_input.
logic r_e_s_e_t_r; // registered reset, to be used with reset input to detect posedge of reset
logic default_en; // derived reset-to-default in destination clock domain
logic data_dst_en; // data_dst_r write enable
logic [data_bits_p - 1 : 0] data_dst_n, data_dst_r; // destination side data payload register
assign count_n_int = (valid) ? (packet_len - 1) : ((count_non_zero) ? (count_r - 1) : count_r);
assign count_n = count_n_int[0 +: len_width_lp];
// Load packet length to counter at the beginning of a packet, and
// decrease its value while it's non-zero. The node does not care
// about content in its shift register when the counter is not zero.
assign shift_n = {config_i.cfg_bit, shift_r[1 +: shift_width_lp - 1]};
// synopsys translate_off
// non-synthesizeable helper message
always @(negedge config_i.cfg_clk)
begin
if (cfg_reset)
$display("## I: CONFIG NODE (id=%-d,default=%-d'b%-b,packet_size=%-d) received reset packet (%m)",id_p,data_bits_p,default_p,$bits(node_packet_s));
end
// synopsys translate_on
// we break up the config register into three parts because it is too tall
// receive register for config net's data portion
// this is separated out so because it aligns with the data synchronization registers
bsg_dff_gatestack #(.width_p(data_rx_len_lp)
,.harden_p(1)
) shift_reg_data
(
.i0 (shift_n.rx) // D
,.i1({ data_rx_len_lp {config_i.cfg_clk}}) // CLK
,.o (shift_r.rx) // Q
);
// receive register for config net's len portion
// this is separated out so because it aligns with the data synchronization registers
bsg_dff_gatestack #(.width_p(len_width_lp)
,.harden_p(1)
) shift_reg_len
(
.i0 (shift_n.len )
,.i1({ len_width_lp {config_i.cfg_clk}})
,.o (shift_r.len)
);
bsg_dff_gatestack #(.width_p(id_width_lp)
,.harden_p(1)
) shift_reg_id
(
.i0 (shift_n.id )
,.i1({ id_width_lp {config_i.cfg_clk}})
,.o (shift_r.id)
);
initial assert (data_rx_len_lp+1+id_width_lp+frame_bit_size_lp+len_width_lp+frame_bit_size_lp+valid_bit_size_lp == $bits(node_packet_s))
else
$error("%m likely missing component in config_node flops");
localparam remainder_lp = $bits(node_packet_s)-id_width_lp-data_rx_len_lp-len_width_lp;
// receive register for config net
bsg_dff_gatestack #(.width_p(remainder_lp)
,.harden_p(1)
) shift_reg_remain
(
.i0 ({shift_n.f2, shift_n.f1, shift_n.f0, shift_n.valid})
,.i1({ remainder_lp {config_i.cfg_clk}})
,.o ({shift_r.f2, shift_r.f1, shift_r.f0, shift_r.valid})
);
bsg_dff_reset #(.width_p(len_width_lp)
,.harden_p(1)
) count_reg
(.clk_i(config_i.cfg_clk)
,.data_i(count_n)
,.data_o(count_r)
,.reset_i(cfg_reset)
);
always_ff @ (posedge config_i.cfg_clk) begin
if (cfg_reset) begin
ready_r <= 0;
end else begin
if (data_en) begin
ready_r <= ready_n;
end
end
end
assign ready_n = ready_r ^ data_en; // xor, invert ready signal when data_en is 1
assign default_en = reset & (~ r_e_s_e_t_r); // (reset == 1) & (r_e_s_e_t_r == 0)
// This bsg_launch_sync_sync module is used to cross the clock domains for
// the ready signal
bsg_launch_sync_sync #( .width_p(1)
, .use_negedge_for_launch_p(0)
) synchronizer
( .iclk_i(config_i.cfg_clk)
, .iclk_reset_i(1'b0) // mbt: was incorrectly set to reset; which is wrong clock domain
, .oclk_i(clk)
, .iclk_data_i(ready_r ^ cfg_reset)
, .iclk_data_o()
, .oclk_data_o(ready_synced)
);
if (default_p==0)
begin: def
bsg_dff_reset_en #(.width_p(data_bits_p),.harden_p(1'b1))
data_r_reg
(.clk_i(config_i.cfg_clk)
,.reset_i(cfg_reset)
,.en_i(data_en)
,.data_i(data_n)
,.data_o(data_r)
);
bsg_dff_reset_en #(.width_p(data_bits_p),.harden_p(1'b1))
data_dst_reg
(.clk_i(clk)
,.data_i(data_r)
,.en_i(data_dst_en)
,.reset_i(default_en)
,.data_o(data_dst_r)
);
end
else
begin: def
// source register for crossing clock domains
bsg_dff_en #(.width_p(data_bits_p),.harden_p(1'b1))
data_r_reg
(.clock_i(config_i.cfg_clk)
,.en_i(cfg_reset | data_en)
,.data_i(cfg_reset ? default_p : data_n)
,.data_o(data_r)
);
bsg_mux #(.width_p(data_bits_p)
,.harden_p(1)
,.els_p(2)
) data_dst_mux
(
.sel_i(default_en)
,.data_i( { data_bits_p '(default_p), data_r})
,.data_o(data_dst_n)
);
bsg_dff_en #(.width_p(data_bits_p)
,.harden_p(1)
) data_dst_reg
(.clock_i(clk)
,.data_i(data_dst_n)
,.en_i(default_en | data_dst_en)
,.data_o(data_dst_r)
);
end
// Register for edge detection
assign sync_shift_n = {ready_synced, sync_shift_r[1]};
always_ff @ (posedge clk) begin
if (reset) begin
r_e_s_e_t_r <= 1;
end else begin
r_e_s_e_t_r <= 0;
end
data_new_r_o <= data_dst_en | default_en;
sync_shift_r <= sync_shift_n;
end
if (debug_lp)
always @(negedge clk)
begin
if (default_en)
$display("## I: CONFIG NODE (id=%-d) dest_clk setting default: %x (%m)",id_p, default_p);
if (data_new_r_o)
$display("## I: CONFIG NODE (id=%-d) dest_clk received data: %x (%m)",id_p, data_dst_r);
end
// An inverted ready_r from config domain indicates a valid data_r word is ready to be captured.
// If an edge occurs in ready_r, sooner or later the sync line detects it by having different bits in the least significant 2 positions.
// This implementation depends on that the least significant 2 bits in sync line are *NOT* metastable. When they also go metastable,
// the circuit may fail. Extend the length of sync_len_lp could increase mean time between failures.
assign data_dst_en = sync_shift_r[0] ^ sync_shift_r[1];
assign cfg_reset = & shift_r[0 +: reset_len_lp]; // reset sequence is an all '1' string of reset_len_lp length
assign valid = (~count_non_zero) ? (shift_r.valid == 2'b10) : 1'b0; // shift_r.valid == "10" means a valid packet arrives
assign packet_len = shift_r.len;
assign node_id = shift_r.id;
assign data_rx = shift_r.rx;
// This generate block is to remove framing bits and wire only data payload
// bits to the config data register of this node.
genvar i;
generate
for(i = 0; i < data_rx_len_lp - frame_bit_size_lp; i++) begin // the end, or msb of a transferred data is always '0' which is discarded
if((i + 1) % (data_frame_len_lp + frame_bit_size_lp)) begin // bit is payload when % returns non-zero
assign data_n[i - i / (data_frame_len_lp + frame_bit_size_lp)] = data_rx[i];
end
end
endgenerate
assign match = node_id == id_p;
assign data_en = valid & match;
assign count_non_zero = | count_r;
// Output signals
assign data_r_o = data_dst_r; // data_dst_r is the inverted data_r
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_PP_SYMBOL_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb16to1 (
//# {{data|Data Signals}}
input [15:0] D ,
output Z ,
//# {{control|Control Signals}}
input [15:0] S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_PP_SYMBOL_V
|
// ======================================================================
// cadeau_marraine.v generated from TopDesign.cysch
// 11/08/2014 at 11:42
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 2
`define CYDEV_CHIP_REV_EXPECT 17
`define CYDEV_CHIP_DIE_ACTUAL 2
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4D 3
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4D_ES0 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 4
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 5
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 2
`define CYDEV_CHIP_REVISION_USED 17
// CharLCD_v2_0(ConversionRoutines=true, CUSTOM0=0,E,8,8,8,E,0, CUSTOM1=0,A,A,4,4,4,0, CUSTOM2=0,E,A,E,8,8,0, CUSTOM3=0,E,A,C,A,A,0, CUSTOM4=0,E,8,C,8,E,0, CUSTOM5=0,E,8,E,2,E,0, CUSTOM6=0,E,8,E,2,E,0, CUSTOM7=0,4,4,4,0,4,0, CustomCharacterSet=0, TypeReplacementString=uint32, CY_COMPONENT_NAME=CharLCD_v2_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=LCD_Char_1, CY_INSTANCE_SHORT_NAME=LCD_Char_1, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=LCD_Char_1, )
module CharLCD_v2_0_0 ;
wire [6:0] tmpOE__LCDPort_net;
wire [6:0] tmpFB_6__LCDPort_net;
wire [6:0] tmpIO_6__LCDPort_net;
wire [0:0] tmpINTERRUPT_0__LCDPort_net;
electrical [0:0] tmpSIOVREF__LCDPort_net;
cy_psoc3_pins_v1_10
#(.id("5d7669ae-5f32-40b5-9c5a-1eda1fc21044/ed092b9b-d398-4703-be89-cebf998501f6"),
.drive_mode(21'b110_110_110_110_110_110_110),
.ibuf_enabled(7'b1_1_1_1_1_1_1),
.init_dr_st(7'b0_0_0_0_0_0_0),
.input_clk_en(0),
.input_sync(7'b1_1_1_1_1_1_1),
.input_sync_mode(7'b0_0_0_0_0_0_0),
.intr_mode(14'b00_00_00_00_00_00_00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(",,,,,,"),
.layout_mode("CONTIGUOUS"),
.oe_conn(7'b0_0_0_0_0_0_0),
.oe_reset(0),
.oe_sync(7'b0_0_0_0_0_0_0),
.output_clk_en(0),
.output_clock_mode(7'b0_0_0_0_0_0_0),
.output_conn(7'b0_0_0_0_0_0_0),
.output_mode(7'b0_0_0_0_0_0_0),
.output_reset(0),
.output_sync(7'b0_0_0_0_0_0_0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(",,,,,,"),
.pin_mode("OOOOOOO"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(7'b0_0_0_0_0_0_0),
.sio_ibuf(""),
.sio_info(14'b00_00_00_00_00_00_00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(7'b0_0_0_0_0_0_0),
.spanning(0),
.use_annotation(7'b0_0_0_0_0_0_0),
.vtrip(14'b10_10_10_10_10_10_10),
.width(7))
LCDPort
(.oe(tmpOE__LCDPort_net),
.y({7'b0}),
.fb({tmpFB_6__LCDPort_net[6:0]}),
.io({tmpIO_6__LCDPort_net[6:0]}),
.siovref(tmpSIOVREF__LCDPort_net),
.interrupt({tmpINTERRUPT_0__LCDPort_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LCDPort_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{7'b1111111} : {7'b1111111};
endmodule
// TCPWM_P4_v1_10(PWMCompare=0, PWMCompareBuf=65535, PWMCompareSwap=0, PWMCountMode=3, PWMCountPresent=false, PWMDeadTimeCycle=0, PWMInterruptMask=1, PWMKillEvent=0, PWMLinenSignal=0, PWMLineSignal=0, PWMMode=4, PWMPeriod=10000, PWMPeriodBuf=65535, PWMPeriodSwap=0, PWMPrescaler=0, PWMReloadMode=0, PWMReloadPresent=false, PWMRunMode=0, PWMSetAlign=0, PWMStartMode=0, PWMStartPresent=false, PWMStopEvent=0, PWMStopMode=0, PWMStopPresent=false, PWMSwitchMode=0, PWMSwitchPresent=false, QuadEncodingModes=0, QuadIndexMode=0, QuadIndexPresent=false, QuadInterruptMask=1, QuadPhiAMode=3, QuadPhiBMode=3, QuadStopMode=0, QuadStopPresent=false, TCCaptureMode=0, TCCapturePresent=false, TCCompare=65535, TCCompareBuf=65535, TCCompareSwap=0, TCCompCapMode=2, TCCountingModes=0, TCCountMode=3, TCCountPresent=false, TCInterruptMask=1, TCPeriod=65535, TCPrescaler=0, TCPWMCapturePresent=false, TCPWMConfig=7, TCPWMCountPresent=false, TCPWMReloadPresent=false, TCPWMStartPresent=false, TCPWMStopPresent=false, TCReloadMode=0, TCReloadPresent=false, TCRunMode=0, TCStartMode=0, TCStartPresent=false, TCStopMode=0, TCStopPresent=false, CY_COMPONENT_NAME=TCPWM_P4_v1_10, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=PWM_1, CY_INSTANCE_SHORT_NAME=PWM_1, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=PWM_1, )
module TCPWM_P4_v1_10_1 (
stop,
count,
reload,
start,
capture,
interrupt,
ov,
un,
cc,
clock,
line,
line_n);
input stop;
input count;
input reload;
input start;
input capture;
output interrupt;
output ov;
output un;
output cc;
input clock;
output line;
output line_n;
parameter PWMCountMode = 3;
parameter PWMReloadMode = 0;
parameter PWMReloadPresent = 0;
parameter PWMStartMode = 0;
parameter PWMStopMode = 0;
parameter PWMSwitchMode = 0;
parameter QuadIndexMode = 0;
parameter QuadPhiAMode = 3;
parameter QuadPhiBMode = 3;
parameter QuadStopMode = 0;
parameter TCCaptureMode = 0;
parameter TCCountMode = 3;
parameter TCReloadMode = 0;
parameter TCStartMode = 0;
parameter TCStopMode = 0;
cy_m0s8_tcpwm_v1_0 cy_m0s8_tcpwm_1 (
.capture(capture),
.underflow(un),
.overflow(ov),
.line_out_compl(line_n),
.line_out(line),
.compare_match(cc),
.interrupt(interrupt),
.count(count),
.reload(reload),
.stop(stop),
.start(start),
.clock(clock));
endmodule
// TCPWM_P4_v1_10(PWMCompare=0, PWMCompareBuf=65535, PWMCompareSwap=0, PWMCountMode=3, PWMCountPresent=false, PWMDeadTimeCycle=0, PWMInterruptMask=1, PWMKillEvent=0, PWMLinenSignal=0, PWMLineSignal=0, PWMMode=4, PWMPeriod=10000, PWMPeriodBuf=65535, PWMPeriodSwap=0, PWMPrescaler=0, PWMReloadMode=0, PWMReloadPresent=false, PWMRunMode=0, PWMSetAlign=0, PWMStartMode=0, PWMStartPresent=false, PWMStopEvent=0, PWMStopMode=0, PWMStopPresent=false, PWMSwitchMode=0, PWMSwitchPresent=false, QuadEncodingModes=0, QuadIndexMode=0, QuadIndexPresent=false, QuadInterruptMask=1, QuadPhiAMode=3, QuadPhiBMode=3, QuadStopMode=0, QuadStopPresent=false, TCCaptureMode=0, TCCapturePresent=false, TCCompare=65535, TCCompareBuf=65535, TCCompareSwap=0, TCCompCapMode=2, TCCountingModes=0, TCCountMode=3, TCCountPresent=false, TCInterruptMask=1, TCPeriod=65535, TCPrescaler=0, TCPWMCapturePresent=false, TCPWMConfig=7, TCPWMCountPresent=false, TCPWMReloadPresent=false, TCPWMStartPresent=false, TCPWMStopPresent=false, TCReloadMode=0, TCReloadPresent=false, TCRunMode=0, TCStartMode=0, TCStartPresent=false, TCStopMode=0, TCStopPresent=false, CY_COMPONENT_NAME=TCPWM_P4_v1_10, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=PWM_2, CY_INSTANCE_SHORT_NAME=PWM_2, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=PWM_2, )
module TCPWM_P4_v1_10_2 (
stop,
count,
reload,
start,
capture,
interrupt,
ov,
un,
cc,
clock,
line,
line_n);
input stop;
input count;
input reload;
input start;
input capture;
output interrupt;
output ov;
output un;
output cc;
input clock;
output line;
output line_n;
parameter PWMCountMode = 3;
parameter PWMReloadMode = 0;
parameter PWMReloadPresent = 0;
parameter PWMStartMode = 0;
parameter PWMStopMode = 0;
parameter PWMSwitchMode = 0;
parameter QuadIndexMode = 0;
parameter QuadPhiAMode = 3;
parameter QuadPhiBMode = 3;
parameter QuadStopMode = 0;
parameter TCCaptureMode = 0;
parameter TCCountMode = 3;
parameter TCReloadMode = 0;
parameter TCStartMode = 0;
parameter TCStopMode = 0;
cy_m0s8_tcpwm_v1_0 cy_m0s8_tcpwm_1 (
.capture(capture),
.underflow(un),
.overflow(ov),
.line_out_compl(line_n),
.line_out(line),
.compare_match(cc),
.interrupt(interrupt),
.count(count),
.reload(reload),
.stop(stop),
.start(start),
.clock(clock));
endmodule
// TCPWM_P4_v1_10(PWMCompare=0, PWMCompareBuf=65535, PWMCompareSwap=0, PWMCountMode=3, PWMCountPresent=false, PWMDeadTimeCycle=0, PWMInterruptMask=1, PWMKillEvent=0, PWMLinenSignal=0, PWMLineSignal=0, PWMMode=4, PWMPeriod=10000, PWMPeriodBuf=65535, PWMPeriodSwap=0, PWMPrescaler=0, PWMReloadMode=0, PWMReloadPresent=false, PWMRunMode=0, PWMSetAlign=0, PWMStartMode=0, PWMStartPresent=false, PWMStopEvent=0, PWMStopMode=0, PWMStopPresent=false, PWMSwitchMode=0, PWMSwitchPresent=false, QuadEncodingModes=0, QuadIndexMode=0, QuadIndexPresent=false, QuadInterruptMask=1, QuadPhiAMode=3, QuadPhiBMode=3, QuadStopMode=0, QuadStopPresent=false, TCCaptureMode=0, TCCapturePresent=false, TCCompare=65535, TCCompareBuf=65535, TCCompareSwap=0, TCCompCapMode=2, TCCountingModes=0, TCCountMode=3, TCCountPresent=false, TCInterruptMask=1, TCPeriod=65535, TCPrescaler=0, TCPWMCapturePresent=false, TCPWMConfig=7, TCPWMCountPresent=false, TCPWMReloadPresent=false, TCPWMStartPresent=false, TCPWMStopPresent=false, TCReloadMode=0, TCReloadPresent=false, TCRunMode=0, TCStartMode=0, TCStartPresent=false, TCStopMode=0, TCStopPresent=false, CY_COMPONENT_NAME=TCPWM_P4_v1_10, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=PWM_3, CY_INSTANCE_SHORT_NAME=PWM_3, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=PWM_3, )
module TCPWM_P4_v1_10_3 (
stop,
count,
reload,
start,
capture,
interrupt,
ov,
un,
cc,
clock,
line,
line_n);
input stop;
input count;
input reload;
input start;
input capture;
output interrupt;
output ov;
output un;
output cc;
input clock;
output line;
output line_n;
parameter PWMCountMode = 3;
parameter PWMReloadMode = 0;
parameter PWMReloadPresent = 0;
parameter PWMStartMode = 0;
parameter PWMStopMode = 0;
parameter PWMSwitchMode = 0;
parameter QuadIndexMode = 0;
parameter QuadPhiAMode = 3;
parameter QuadPhiBMode = 3;
parameter QuadStopMode = 0;
parameter TCCaptureMode = 0;
parameter TCCountMode = 3;
parameter TCReloadMode = 0;
parameter TCStartMode = 0;
parameter TCStopMode = 0;
cy_m0s8_tcpwm_v1_0 cy_m0s8_tcpwm_1 (
.capture(capture),
.underflow(un),
.overflow(ov),
.line_out_compl(line_n),
.line_out(line),
.compare_match(cc),
.interrupt(interrupt),
.count(count),
.reload(reload),
.stop(stop),
.start(start),
.clock(clock));
endmodule
// TCPWM_P4_v1_10(PWMCompare=0, PWMCompareBuf=65535, PWMCompareSwap=0, PWMCountMode=3, PWMCountPresent=false, PWMDeadTimeCycle=0, PWMInterruptMask=1, PWMKillEvent=0, PWMLinenSignal=0, PWMLineSignal=0, PWMMode=4, PWMPeriod=10000, PWMPeriodBuf=65535, PWMPeriodSwap=0, PWMPrescaler=0, PWMReloadMode=0, PWMReloadPresent=false, PWMRunMode=0, PWMSetAlign=0, PWMStartMode=0, PWMStartPresent=false, PWMStopEvent=0, PWMStopMode=0, PWMStopPresent=false, PWMSwitchMode=0, PWMSwitchPresent=false, QuadEncodingModes=0, QuadIndexMode=0, QuadIndexPresent=false, QuadInterruptMask=1, QuadPhiAMode=3, QuadPhiBMode=3, QuadStopMode=0, QuadStopPresent=false, TCCaptureMode=0, TCCapturePresent=false, TCCompare=65535, TCCompareBuf=65535, TCCompareSwap=0, TCCompCapMode=2, TCCountingModes=0, TCCountMode=3, TCCountPresent=false, TCInterruptMask=1, TCPeriod=60000, TCPrescaler=0, TCPWMCapturePresent=false, TCPWMConfig=1, TCPWMCountPresent=false, TCPWMReloadPresent=false, TCPWMStartPresent=false, TCPWMStopPresent=false, TCReloadMode=0, TCReloadPresent=false, TCRunMode=0, TCStartMode=0, TCStartPresent=false, TCStopMode=0, TCStopPresent=false, CY_COMPONENT_NAME=TCPWM_P4_v1_10, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=TIM_4, CY_INSTANCE_SHORT_NAME=TIM_4, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=TIM_4, )
module TCPWM_P4_v1_10_4 (
stop,
count,
reload,
start,
capture,
interrupt,
ov,
un,
cc,
clock,
line,
line_n);
input stop;
input count;
input reload;
input start;
input capture;
output interrupt;
output ov;
output un;
output cc;
input clock;
output line;
output line_n;
parameter PWMCountMode = 3;
parameter PWMReloadMode = 0;
parameter PWMReloadPresent = 0;
parameter PWMStartMode = 0;
parameter PWMStopMode = 0;
parameter PWMSwitchMode = 0;
parameter QuadIndexMode = 0;
parameter QuadPhiAMode = 3;
parameter QuadPhiBMode = 3;
parameter QuadStopMode = 0;
parameter TCCaptureMode = 0;
parameter TCCountMode = 3;
parameter TCReloadMode = 0;
parameter TCStartMode = 0;
parameter TCStopMode = 0;
cy_m0s8_tcpwm_v1_0 cy_m0s8_tcpwm_1 (
.capture(capture),
.underflow(un),
.overflow(ov),
.line_out_compl(line_n),
.line_out(line),
.compare_match(cc),
.interrupt(interrupt),
.count(count),
.reload(reload),
.stop(stop),
.start(start),
.clock(clock));
endmodule
// top
module top ;
wire Net_41;
wire Net_40;
wire Net_39;
wire Net_38;
wire Net_37;
wire Net_36;
wire Net_35;
wire Net_34;
wire Net_33;
wire Net_32;
wire Net_31;
wire Net_30;
wire Net_29;
wire Net_28;
wire Net_27;
wire Net_26;
wire Net_25;
wire Net_24;
wire Net_23;
wire Net_22;
wire Net_21;
wire Net_20;
wire Net_19;
wire Net_18;
wire Net_17;
wire Net_16;
wire Net_15;
wire Net_14;
wire Net_13;
wire Net_12;
wire Net_11;
wire Net_10;
wire Net_9;
wire Net_8;
wire Net_7;
wire Net_6;
wire Net_5;
wire Net_4;
wire Net_3;
wire Net_2;
wire Net_1;
wire Net_331;
wire Net_337;
wire Net_129;
wire Net_117;
wire Net_68;
wire Net_74;
wire Net_72;
wire Net_121;
wire Net_133;
wire Net_108;
wire Net_95;
CharLCD_v2_0_0 LCD_Char_1 ();
TCPWM_P4_v1_10_1 PWM_1 (
.stop(1'b0),
.reload(1'b0),
.start(1'b0),
.count(1'b1),
.capture(1'b0),
.interrupt(Net_68),
.ov(Net_6),
.un(Net_7),
.cc(Net_8),
.line(Net_72),
.line_n(Net_9),
.clock(Net_74));
defparam PWM_1.PWMCountMode = 3;
defparam PWM_1.PWMReloadMode = 0;
defparam PWM_1.PWMReloadPresent = 0;
defparam PWM_1.PWMStartMode = 0;
defparam PWM_1.PWMStopMode = 0;
defparam PWM_1.PWMSwitchMode = 0;
defparam PWM_1.QuadIndexMode = 0;
defparam PWM_1.QuadPhiAMode = 3;
defparam PWM_1.QuadPhiBMode = 3;
defparam PWM_1.QuadStopMode = 0;
defparam PWM_1.TCCaptureMode = 0;
defparam PWM_1.TCCountMode = 3;
defparam PWM_1.TCReloadMode = 0;
defparam PWM_1.TCStartMode = 0;
defparam PWM_1.TCStopMode = 0;
TCPWM_P4_v1_10_2 PWM_2 (
.stop(1'b0),
.reload(1'b0),
.start(1'b0),
.count(1'b1),
.capture(1'b0),
.interrupt(Net_117),
.ov(Net_15),
.un(Net_16),
.cc(Net_17),
.line(Net_121),
.line_n(Net_18),
.clock(Net_95));
defparam PWM_2.PWMCountMode = 3;
defparam PWM_2.PWMReloadMode = 0;
defparam PWM_2.PWMReloadPresent = 0;
defparam PWM_2.PWMStartMode = 0;
defparam PWM_2.PWMStopMode = 0;
defparam PWM_2.PWMSwitchMode = 0;
defparam PWM_2.QuadIndexMode = 0;
defparam PWM_2.QuadPhiAMode = 3;
defparam PWM_2.QuadPhiBMode = 3;
defparam PWM_2.QuadStopMode = 0;
defparam PWM_2.TCCaptureMode = 0;
defparam PWM_2.TCCountMode = 3;
defparam PWM_2.TCReloadMode = 0;
defparam PWM_2.TCStartMode = 0;
defparam PWM_2.TCStopMode = 0;
cy_clock_v1_0
#(.id("2372d904-f599-4e94-a937-cbf30710aca1"),
.source_clock_id(""),
.divisor(0),
.period("100000000"),
.is_direct(0),
.is_digital(0))
Clock_2
(.clock_out(Net_95));
TCPWM_P4_v1_10_3 PWM_3 (
.stop(1'b0),
.reload(1'b0),
.start(1'b0),
.count(1'b1),
.capture(1'b0),
.interrupt(Net_129),
.ov(Net_25),
.un(Net_26),
.cc(Net_27),
.line(Net_133),
.line_n(Net_28),
.clock(Net_108));
defparam PWM_3.PWMCountMode = 3;
defparam PWM_3.PWMReloadMode = 0;
defparam PWM_3.PWMReloadPresent = 0;
defparam PWM_3.PWMStartMode = 0;
defparam PWM_3.PWMStopMode = 0;
defparam PWM_3.PWMSwitchMode = 0;
defparam PWM_3.QuadIndexMode = 0;
defparam PWM_3.QuadPhiAMode = 3;
defparam PWM_3.QuadPhiBMode = 3;
defparam PWM_3.QuadStopMode = 0;
defparam PWM_3.TCCaptureMode = 0;
defparam PWM_3.TCCountMode = 3;
defparam PWM_3.TCReloadMode = 0;
defparam PWM_3.TCStartMode = 0;
defparam PWM_3.TCStopMode = 0;
cy_clock_v1_0
#(.id("30443c36-6964-4ee1-9efe-af42ce2dde68"),
.source_clock_id(""),
.divisor(0),
.period("100000000"),
.is_direct(0),
.is_digital(0))
Clock_3
(.clock_out(Net_108));
wire [0:0] tmpOE__PWM1_net;
wire [0:0] tmpFB_0__PWM1_net;
wire [0:0] tmpIO_0__PWM1_net;
wire [0:0] tmpINTERRUPT_0__PWM1_net;
electrical [0:0] tmpSIOVREF__PWM1_net;
cy_psoc3_pins_v1_10
#(.id("e219e390-1ce5-49ce-ad3e-702089585d25"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
PWM1
(.oe(tmpOE__PWM1_net),
.y({Net_72}),
.fb({tmpFB_0__PWM1_net[0:0]}),
.io({tmpIO_0__PWM1_net[0:0]}),
.siovref(tmpSIOVREF__PWM1_net),
.interrupt({tmpINTERRUPT_0__PWM1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__PWM1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__PWM2_net;
wire [0:0] tmpFB_0__PWM2_net;
wire [0:0] tmpIO_0__PWM2_net;
wire [0:0] tmpINTERRUPT_0__PWM2_net;
electrical [0:0] tmpSIOVREF__PWM2_net;
cy_psoc3_pins_v1_10
#(.id("fdc5f587-2927-4fc4-acc0-945b16c97a74"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
PWM2
(.oe(tmpOE__PWM2_net),
.y({Net_121}),
.fb({tmpFB_0__PWM2_net[0:0]}),
.io({tmpIO_0__PWM2_net[0:0]}),
.siovref(tmpSIOVREF__PWM2_net),
.interrupt({tmpINTERRUPT_0__PWM2_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__PWM2_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__PWM3_net;
wire [0:0] tmpFB_0__PWM3_net;
wire [0:0] tmpIO_0__PWM3_net;
wire [0:0] tmpINTERRUPT_0__PWM3_net;
electrical [0:0] tmpSIOVREF__PWM3_net;
cy_psoc3_pins_v1_10
#(.id("c4749d34-f08a-4d33-bb22-fa567c5a7292"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
PWM3
(.oe(tmpOE__PWM3_net),
.y({Net_133}),
.fb({tmpFB_0__PWM3_net[0:0]}),
.io({tmpIO_0__PWM3_net[0:0]}),
.siovref(tmpSIOVREF__PWM3_net),
.interrupt({tmpINTERRUPT_0__PWM3_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__PWM3_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b10))
TC1_ISR
(.int_signal(Net_68));
cy_isr_v1_0
#(.int_type(2'b10))
TC2_ISR
(.int_signal(Net_117));
cy_isr_v1_0
#(.int_type(2'b10))
TC3_ISR
(.int_signal(Net_129));
TCPWM_P4_v1_10_4 TIM_4 (
.stop(1'b0),
.reload(1'b0),
.start(1'b0),
.count(1'b1),
.capture(1'b0),
.interrupt(Net_331),
.ov(Net_35),
.un(Net_36),
.cc(Net_37),
.line(Net_38),
.line_n(Net_39),
.clock(Net_337));
defparam TIM_4.PWMCountMode = 3;
defparam TIM_4.PWMReloadMode = 0;
defparam TIM_4.PWMReloadPresent = 0;
defparam TIM_4.PWMStartMode = 0;
defparam TIM_4.PWMStopMode = 0;
defparam TIM_4.PWMSwitchMode = 0;
defparam TIM_4.QuadIndexMode = 0;
defparam TIM_4.QuadPhiAMode = 3;
defparam TIM_4.QuadPhiBMode = 3;
defparam TIM_4.QuadStopMode = 0;
defparam TIM_4.TCCaptureMode = 0;
defparam TIM_4.TCCountMode = 3;
defparam TIM_4.TCReloadMode = 0;
defparam TIM_4.TCStartMode = 0;
defparam TIM_4.TCStopMode = 0;
cy_clock_v1_0
#(.id("72f73c91-d285-4113-8eaf-6cc5d31dcc2a"),
.source_clock_id(""),
.divisor(0),
.period("100000000000"),
.is_direct(0),
.is_digital(0))
Clock_4
(.clock_out(Net_337));
cy_isr_v1_0
#(.int_type(2'b10))
TC4_ISR
(.int_signal(Net_331));
cy_clock_v1_0
#(.id("782d7a58-9327-432e-9d9e-efa2d29fdf99"),
.source_clock_id("413DE2EF-D9F2-4233-A808-DFAF137FD877"),
.divisor(0),
.period("100000000"),
.is_direct(0),
.is_digital(0))
Clock_1
(.clock_out(Net_74));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXTP_TB_V
`define SKY130_FD_SC_HS__SDFXTP_TB_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfxtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 SCD = 1'b1;
#160 SCE = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 SCD = 1'b0;
#260 SCE = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SCE = 1'b1;
#380 SCD = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SCE = 1'bx;
#480 SCD = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sdfxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXTP_TB_V
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// This module to implement the CSR instructions
//
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_alu_csrctrl(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Handshake Interface
//
input csr_i_valid, // Handshake valid
output csr_i_ready, // Handshake ready
input [`E203_XLEN-1:0] csr_i_rs1,
input [`E203_DECINFO_CSR_WIDTH-1:0] csr_i_info,
input csr_i_rdwen,
output csr_ena,
output csr_wr_en,
output csr_rd_en,
output [12-1:0] csr_idx,
input csr_access_ilgl,
input [`E203_XLEN-1:0] read_csr_dat,
output [`E203_XLEN-1:0] wbck_csr_dat,
`ifdef E203_HAS_CSR_EAI//{
output csr_sel_eai,
input eai_xs_off,
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The CSR Write-back/Commit Interface
output csr_o_valid, // Handshake valid
input csr_o_ready, // Handshake ready
// The Write-Back Interface for Special (unaligned ldst and AMO instructions)
output [`E203_XLEN-1:0] csr_o_wbck_wdat,
output csr_o_wbck_err,
input clk,
input rst_n
);
`ifdef E203_HAS_CSR_EAI//{
// If accessed the EAI CSR range then we need to check if the EAI CSR is ready
assign csr_sel_eai = (csr_idx[11:8] == 4'hE);
wire sel_eai = csr_sel_eai & (~eai_xs_off);
wire addi_condi = sel_eai ? eai_csr_ready : 1'b1;
assign csr_o_valid = csr_i_valid
& addi_condi; // Need to make sure the eai_csr-ready is ready to make sure
// it can be sent to EAI and O interface same cycle
assign eai_csr_valid = sel_eai & csr_i_valid &
csr_o_ready;// Need to make sure the o-ready is ready to make sure
// it can be sent to EAI and O interface same cycle
assign csr_i_ready = sel_eai ? (eai_csr_ready & csr_o_ready) : csr_o_ready;
assign csr_o_wbck_err = csr_access_ilgl;
assign csr_o_wbck_wdat = sel_eai ? eai_csr_rdata : read_csr_dat;
assign eai_csr_addr = csr_idx;
assign eai_csr_wr = csr_wr_en;
assign eai_csr_wdata = wbck_csr_dat;
`else//}{
assign sel_eai = 1'b0;
assign csr_o_valid = csr_i_valid;
assign csr_i_ready = csr_o_ready;
assign csr_o_wbck_err = csr_access_ilgl;
assign csr_o_wbck_wdat = read_csr_dat;
`endif//}
wire csrrw = csr_i_info[`E203_DECINFO_CSR_CSRRW ];
wire csrrs = csr_i_info[`E203_DECINFO_CSR_CSRRS ];
wire csrrc = csr_i_info[`E203_DECINFO_CSR_CSRRC ];
wire rs1imm = csr_i_info[`E203_DECINFO_CSR_RS1IMM];
wire rs1is0 = csr_i_info[`E203_DECINFO_CSR_RS1IS0];
wire [4:0] zimm = csr_i_info[`E203_DECINFO_CSR_ZIMMM ];
wire [11:0] csridx = csr_i_info[`E203_DECINFO_CSR_CSRIDX];
wire [`E203_XLEN-1:0] csr_op1 = rs1imm ? {27'b0,zimm} : csr_i_rs1;
assign csr_rd_en = csr_i_valid &
(
(csrrw ? csr_i_rdwen : 1'b0) // the CSRRW only read when the destination reg need to be writen
| csrrs | csrrc // The set and clear operation always need to read CSR
);
assign csr_wr_en = csr_i_valid & (
csrrw // CSRRW always write the original RS1 value into the CSR
| ((csrrs | csrrc) & (~rs1is0)) // for CSRRS/RC, if the RS is x0, then should not really write
);
assign csr_idx = csridx;
assign csr_ena = csr_o_valid & csr_o_ready & (~sel_eai);
assign wbck_csr_dat =
({`E203_XLEN{csrrw}} & csr_op1)
| ({`E203_XLEN{csrrs}} & ( csr_op1 | read_csr_dat))
| ({`E203_XLEN{csrrc}} & ((~csr_op1) & read_csr_dat));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_8_V
`define SKY130_FD_SC_HDLL__NOR4_8_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_8 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_8 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_8_V
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* CLOCK MODULE */
/*---------------------------------------------------------------------------*/
/* Test the clock module: */
/* - Check the SMCLK clock generation. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
`define LONG_TIMEOUT
integer smclk_counter;
always @ (negedge smclk)
smclk_counter <= smclk_counter+1;
integer dco_clk_counter;
always @ (negedge dco_clk)
dco_clk_counter <= dco_clk_counter+1;
integer lfxt_clk_counter;
always @ (negedge lfxt_clk)
lfxt_clk_counter <= lfxt_clk_counter+1;
reg [15:0] reg_val;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge smclk);
stimulus_done = 0;
`ifdef ASIC_CLOCKING
//--------------------------------------------------------
// SMCLK GENERATION - LFXT_CLK INPUT
//--------------------------------------------------------
// ------- Divider /1 ----------
@(r15 === 16'h0001);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
`endif
$display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - DONE =====");
// ------- Divider /2 ----------
@(r15 === 16'h0002);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
`else
if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
`endif
`else
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
`endif
`endif
$display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - DONE =====");
// ------- Divider /4 ----------
@(r15 === 16'h0003);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
`else
if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
`endif
`else
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
`endif
`endif
$display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - DONE =====");
// ------- Divider /8 ----------
@(r15 === 16'h0004);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
`else
if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
`endif
`else
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
`endif
`endif
$display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - DONE =====");
//--------------------------------------------------------
// SSMCLK GENERATION - DCO_CLK INPUT
//--------------------------------------------------------
// ------- Divider /1 ----------
@(r15 === 16'h1001);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
$display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - DONE =====");
// ------- Divider /2 ----------
@(r15 === 16'h1002);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
`endif
$display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - DONE =====");
// ------- Divider /4 ----------
@(r15 === 16'h1003);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
`endif
$display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - DONE =====");
// ------- Divider /8 ----------
@(r15 === 16'h1004);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
`endif
$display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
//--------------------------------------------------------
// SMCLK GENERATION - LFXT_CLK INPUT
//--------------------------------------------------------
// ------- Divider /1 ----------
@(r15 === 16'h2001);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
`endif
$display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - DONE =====");
// ------- Divider /2 ----------
@(r15 === 16'h2002);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
`else
if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
`endif
`else
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
`endif
`endif
$display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - DONE =====");
// ------- Divider /4 ----------
@(r15 === 16'h2003);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
`else
if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
`endif
`else
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
`endif
`endif
$display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - DONE =====");
// ------- Divider /8 ----------
@(r15 === 16'h2004);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
`else
if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
`endif
`else
`ifdef SMCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
`endif
`endif
$display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - DONE =====");
//--------------------------------------------------------
// SSMCLK GENERATION - DCO_CLK INPUT
//--------------------------------------------------------
// ------- Divider /1 ----------
@(r15 === 16'h3001);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
$display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - DONE =====");
// ------- Divider /2 ----------
@(r15 === 16'h3002);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
`endif
$display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - DONE =====");
// ------- Divider /4 ----------
@(r15 === 16'h3003);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
`endif
$display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - DONE =====");
// ------- Divider /8 ----------
@(r15 === 16'h3004);
repeat(2) @(posedge smclk);
smclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge smclk);
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
`ifdef SMCLK_DIVIDER
if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
`endif
$display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
`else
tb_skip_finish("| (this test is not supported in FPGA mode) |");
`endif
stimulus_done = 1;
end
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_TB_V
`define SKY130_FD_SC_HD__TAPVGND2_TB_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__tapvgnd2.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hd__tapvgnd2 dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_TB_V
|
module testbench ();
parameter START_ADDR = 32'h8001_fffc; // h80020000
reg clk;
reg [31:0] addr_write;
reg [31:0] din;
reg enable;
reg rw_write;
reg [2:0] access_size;
reg stall;
reg test_mode;
wire [31:0] dout;
wire busy;
wire [31:0] addr;
wire [31:0] pc;
wire rw;
wire rw_fetch;
wire [2:0] access_size_fetch;
wire [2:0] access_size_mem;
wire enable_fetch;
wire enable_mem;
wire [5:0] instbits;
wire [1:0] op; // r = 00, j = 01, i = 10
wire [4:0] src1;
wire [4:0] src2;
wire [4:0] dst;
wire [31:0] pc_mem;
mips_memory2 test_memory(.clk(clk),
.addr(addr),
.din(din),
.dout(dout),
.access_size(access_size_mem),
.pc(pc_mem),
.rw(rw),
.busy(busy),
.enable(enable_mem));
fetch fetch_unit(.clk(clk),
.busy(busy),
.stall(stall),
.pc(pc),
.rw(rw_fetch),
.access_size(access_size_fetch),
.enable(enable_fetch));
decode decode_unit(.clk(clk),
.insn(dout),
.pc(pc_mem));
reg [7:0] mem[0:512];
assign addr = (test_mode == 0) ? addr_write : pc;
assign access_size_mem = (test_mode == 0) ? access_size : access_size_fetch;
assign rw = (test_mode == 0) ? rw_write : rw_fetch;
assign enable_mem = (test_mode == 0) ? enable : enable_fetch;
initial
begin
clk = 1'b0;
enable = 1'b1;
addr_write = 32'h8001_fffc;
din = 32'b0000_0000;
rw_write = 1'b1;
access_size = 3'b000;
test_mode = 0;
stall = 1'b1;
$readmemh("BubbleSort.x", mem);
end
always @(negedge clk)
begin
if (test_mode == 0)
begin
din[31:24] = mem[addr_write - START_ADDR];
din[23:16] = mem[addr_write + 1 - START_ADDR];
din[15:8] = mem[addr_write + 2 - START_ADDR];
din[7:0] = mem[addr_write + 3 - START_ADDR];
addr_write = addr_write + 32'h0000_0004;
end
else
begin
addr_write = addr_write + 32'h0000_0004;
end
if (addr_write > 32'h8002_01a4 & test_mode == 0)
begin
test_mode = 1;
addr_write = 32'h8002_0000;
rw_write = 1'b0;
stall = 1'b0;
end
end
always
#5 clk = !clk;
endmodule
|
//
// Seven-segment LED display controller
//
// Copyright (C) 2015 Andrzej <[email protected]>
//
// Redistribution and use in source and non-source forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in non-source form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
module sseg_ctrl
#(
parameter n_digits = 8,
parameter n_segs = 8
)
(
input clk_i,
input rst_i,
input async_rst_i,
// config registers
input enable_i,
input [15:0] clk_div_i,
input [7:0] brightness_i,
input [n_digits*n_segs-1:0] segments_i,
// display i/f
output [n_segs-1:0] seg_o,
output [n_digits-1:0] seg_sel_o,
// sync irq (end of the sweep)
output sync_o
);
// time-base strobe generator
reg [15:0] cnt_strobe_reg;
wire strobe = (enable_i & cnt_strobe_reg == 16'b0);
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
cnt_strobe_reg <= 16'b0;
else if (rst_i | ~enable_i)
cnt_strobe_reg <= 16'b0;
else if (strobe)
cnt_strobe_reg <= clk_div_i;
else
cnt_strobe_reg <= cnt_strobe_reg - 16'd1;
// digit strobe generator
reg [7:0] cnt_strobe_dig_reg;
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
cnt_strobe_dig_reg <= 8'b0;
else if (rst_i | ~enable_i)
cnt_strobe_dig_reg <= 8'b0;
else if (strobe)
cnt_strobe_dig_reg <= cnt_strobe_dig_reg - 8'd1;
wire strobe_dig = (strobe & cnt_strobe_dig_reg == 8'hff);
// pwm reg
reg pwm_reg;
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
pwm_reg <= 1'b0;
else if (rst_i | ~enable_i)
pwm_reg <= 1'b0;
else if (strobe)
pwm_reg <= (cnt_strobe_dig_reg <= brightness_i);
// frame strobe generator
reg [4:0] cnt_strobe_frame_reg;
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
cnt_strobe_frame_reg <= 5'b0;
else if (rst_i | ~enable_i)
cnt_strobe_frame_reg <= 5'b0;
else if (strobe_dig &cnt_strobe_frame_reg == 5'b0)
cnt_strobe_frame_reg <= n_digits - 1;
else if (strobe_dig)
cnt_strobe_frame_reg <= cnt_strobe_frame_reg - 5'd1;
wire strobe_frame = (strobe_dig & cnt_strobe_frame_reg == 5'b0);
// multiplex digits
wire [n_digits-1:0] seg_sel_reg_new;
assign seg_sel_reg_new = {strobe_frame, seg_sel_reg[n_digits-1:1]};
reg [n_digits-1:0] seg_sel_reg;
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
seg_sel_reg <= 0;
else if (rst_i | ~enable_i)
seg_sel_reg <= 0;
else if (strobe_dig)
seg_sel_reg <= seg_sel_reg_new;
// output seg_sel
assign seg_sel_o = seg_sel_reg; // & {n_digits{pwm_reg}};
// segment value
integer i;
reg [n_segs-1:0] seg_reg;
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
seg_reg <= 0;
else if (rst_i | ~enable_i)
seg_reg <= 0;
else if (strobe_dig)
for (i = 0; i < n_digits; i = i + 1)
if (seg_sel_reg_new[i])
seg_reg <= segments_i[n_segs*(n_digits-i)-1 -: n_segs];
//seg_o <= segments_i[n_segs*(i+1)-1 -: n_segs];
// output seg
assign seg_o = seg_reg & {n_segs{pwm_reg}};
assign sync_o = strobe_frame;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD1_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLYGATE4SD1_BEHAVIORAL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD1_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// Elbert V2 Library
// Copyright (c) 2015 J.B. Langston
//
// (subsequently tweaked by MLT)
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//////////////////////////////////////////////////////////////////////////////////
module vga_noise_demo(clkin, dips, segments, anodes, hsync, vsync, red, green, blue, audio_l, audio_r, gpio_P1);
input clkin;
// DIP switch
input [8:1] dips;
// 7-SEG
output [7:0] segments;
output [3:1] anodes;
// VGA
output hsync, vsync;
output [2:0] red, green;
output [1:0] blue;
wire [7:0] color;
wire [9:0] x, y;
//
// AUDIO
output audio_l, audio_r;
// GPIO
output [7:0] gpio_P1;
wire [11:0] bcd;
wire clk;
reg [15:0] cnt;
// Use the DCM to multiply the incoming 12MHz clock to a 192MHz clock
clock_mgr dcm (
.CLKIN_IN(clkin),
.CLKFX_OUT(clk),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT()
);
// Convert binary input from DIP switches into BCD
binary_to_bcd conv (
.binary({4'b0, ~dips}),
.bcd(bcd)
);
// Increment a counter for each clock cycle which can be used to divide the clock as needed
always @(posedge clk) cnt <= cnt + 1;
// route the divided clock to GPIO
// so we can see it on the scope
// /1024 so MHz are now ~= kHz
assign gpio_P1[0] = cnt[9];// main clock / 1024
assign gpio_P1[1] = cnt[3];// pixel clock / 2
assign gpio_P1[2] = dips[1]&vsync; // LFSR reset signal
// assign remaining GPIOs to something
assign gpio_P1[7:3] = 5'b00000;
// Generate sync pulses and x/y coordinates
// pixel clock is 25.5MHz, should be 25.175MHz
vga_driver vga (
.clk(cnt[2]),
.color(color),
.hsync(hsync),
.vsync(vsync),
.red(red),
.green(green),
.blue(blue),
.x(x),
.y(y)
);
// generate VGA output:
//
// DIP switch 1 pauses/unpauses the noise display
// DIP switch 2 switches between colour/monochrome output
// DIP switch 3 switches between noise mode and test mode
vga_noise vga_noise(
.clk(clk),
.color(color),
.pause(dips[1]),
.vsync(vsync),
.hsync(hsync),
.style(dips[2]),
.test(dips[3]),
.audio_l(audio_l),
.audio_r(audio_r)
);
// Multiplex BCD value across seven segment display (no decimal points)
seven_segment_mux mux (
.clk(cnt[15]),
.value({4'b0, bcd}),
.dp(3'b000),
.segments(segments),
.anodes(anodes)
);
endmodule
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`include "globalDefines.vh"
/*function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction*/
module logicBlock(
stateA, maskA, stateB, maskB, constant, opBMux,
prevConfigInvalid,
resultMux, out,
configInvalid
);
input [31:0] stateA;
input [31:0] stateB;
input [31:0] maskA; // Configuration
input [31:0] maskB; // Configuration
input [31:0] constant; // Configuration
input opBMux; // Configuration, 1 = stateB, 0 = constant
input [2:0] resultMux; // Configuration, 0 = ==, 1 = !=, 2 = >,
// 3 = >=, 4 = <, 5 = <=
input prevConfigInvalid;
output out;
output configInvalid;
reg out;
wire configInvalid;
// Create both operands
wire [31:0] maskedA = stateA & maskA;
wire [31:0] operandA = maskedA;
wire [31:0] maskedB = stateB & maskB;
wire [31:0] operandB = opBMux ? maskedB : constant;
// Perform the operations in parallel
wire eq = operandA == operandB;
wire neq = operandA != operandB;
wire gt = operandA > operandB;
wire gteq = operandA >= operandB;
wire lt = operandA < operandB;
wire lteq = operandA `LTEQ operandB;
// Check for valid configurations
assign configInvalid = prevConfigInvalid | (resultMux > 3'd5);
// Send the correct result to the output
always @(resultMux or eq or neq or gt or gteq or lt or lteq) begin
case(resultMux)
0: out = eq;
1: out = neq;
2: out = gt;
3: out = gteq;
4: out = lt;
5: out = lteq;
default : out = 0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4B_SYMBOL_V
`define SKY130_FD_SC_HS__NOR4B_SYMBOL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4B_SYMBOL_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file write_data_fifo.v when simulating
// the core, write_data_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module write_data_fifo(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count,
prog_full
);
input rst;
input wr_clk;
input rd_clk;
input [255 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
output [12 : 0] rd_data_count;
output [9 : 0] wr_data_count;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(256),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(510),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(13),
.C_RD_DEPTH(8192),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(13),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06:43:33 11/30/2014
// Design Name:
// Module Name: FSMNeuronalNetwork
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSMNeuralNetwork(CLK, reset,Start,Read,Address,ResetInterfaz,ResetStart,ResetCoeffALUandInput,
EnableCoeffALUandInput,EnableMulX,SELCoeffX,EnableRegOutMultCoeffX,EnableFuctAct,EnableRegActFunc,
EnableMulY,EnableRegDesplazamiento,EnableSum,SELCoeffY,SELOffset,EnableAcumulador,ResetAcumulador,
Listo);
input CLK;
input reset;
input Start;
input Read;
input [8:0] Address;
output reg ResetInterfaz =0;
output reg ResetStart=0;
output reg ResetCoeffALUandInput=0;
output reg EnableCoeffALUandInput=0;
output reg EnableMulX=0;
output reg [3:0] SELCoeffX=0;
output reg EnableRegOutMultCoeffX=0;
output reg EnableFuctAct=0;
output reg EnableRegActFunc=0;
output reg EnableMulY=0;
output reg EnableRegDesplazamiento=0;
output reg EnableSum=0;
output reg [3:0] SELCoeffY=0;
output reg SELOffset=0;
output reg EnableAcumulador=0;
output reg ResetAcumulador=0;
output reg Listo=0;
//** Registros de la Maquina de Estados***********************************************************************************
reg[5:0] State = 0;
reg [5:0] NextState = 0;
parameter S1=5'd1, S2=5'd2, S3=5'd3, S4=5'd4, S5=5'd5, S6=5'd6, S7=5'd7, S8=5'd8, S9=5'd9, S10=5'd10,
S11=5'd11, S12=5'd12, S13=5'd13, S14=5'd14, S15=5'd15, S16=5'd16, S17=5'd17, S18=5'd18, S19=5'd19, S20=5'd20,
S21=5'd21, S22=5'd22, S23=5'd23, S24=5'd24, S25=5'd25, S26=5'd26, S27=5'd27, S28=5'd28, S29=5'd29, S30=5'd30,
S31=5'd31, RESETEADOR=5'd00;
//******************************** FIN DE DECLARACI�N DE REGISTROS Y PAMAMETROS MAQUIINA DE ESTADOS***********************************
// *********************Registro de estado *********************************************************
always @(posedge CLK) begin //or posedge reset) begin
begin
if(reset)
State<=RESETEADOR;
else
State<=NextState;
end
end
// L�gica combinacional de estado siguiente ************************************
always @*
begin
case(State)
RESETEADOR: begin //***********ESTADO DE RESET DEL SISTEMA
if (reset) NextState <= RESETEADOR;
else NextState <= S1;
end
S1: begin //***********ESTADO DE ESPERA INICIO
if (Start) NextState <= S2;
else NextState <= S1;
end
S2: begin // ****************ESTADO DE HABILITA EnableCoeffALUandInput
NextState <= S3;
end
S3: begin // **********EnableMultX = 01 and EnableRegOutMultCoeffX = 01 SELCoeffX= 00
NextState <= S4;
end
S4: begin // **********EnableMultX = 01 and EnableRegOutMultCoeffX = 01 SELCoeffX= 01, EnableFuctAct=1, EnableRegFuctAct=1,
NextState <= S5;
end
S5: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 02, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =00, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
NextState <= S6;
end
S6: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 03, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =01, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
NextState <= S7;
end
S7: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 04, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =02, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
NextState <= S8;
end
S8: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 05, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =03, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
NextState <= S9;
end
S9: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 06, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =04, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
NextState <= S10;
end
S10: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 07, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =05, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
NextState <= S11;
end
S11: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 08, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =06, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
NextState <= S12;
end
S12: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 09, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =07, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
NextState <= S13;
end
S13: begin // **********EnableMultX = 0 and EnableRegOutMultCoeffX = 0 SELCoeffX= 00, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =08, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
NextState <= S14;
end
S14: begin // **********EnableMultX = 0 and EnableRegOutMultCoeffX = 0 SELCoeffX= 00, EnableFuctAct=0, EnableRegFuctAct=0, SELCoeffY =09, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
NextState <= S15;
end
S15: begin // **********EnableMultX = 0 and EnableRegOutMultCoeffX = 0 SELCoeffX= 00, EnableFuctAct=0, EnableRegFuctAct=0, SELCoeffY =00, EnableMultY=0,EnableSum=1,EnableRegDesplazamientro=0,SELOffset =1, Enable Acum=1
NextState <= S16;
end
S16: begin // **********EnableMultX = 0 and EnableRegOutMultCoeffX = 0 SELCoeffX= 00, EnableFuctAct=0, EnableRegFuctAct=0, SELCoeffY =00, EnableMultY=0,EnableSum=0,EnableRegDesplazamientro=0,SELOffset =0, Enable Acum=0, Listo = 1
if(Address==9'h000 && Read == 1'b1) NextState <= S17; // Direccion de memoria donde se hace la ultima lectura
else NextState <= S16;
end
S17: begin // **********EnableMultX = 0 and EnableRegOutMultCoeffX = 0 SELCoeffX= 00, EnableFuctAct=0, EnableRegFuctAct=0, SELCoeffY =00, EnableMultY=0,EnableSum=0,EnableRegDesplazamientro=0,SELOffset =0, Enable Acum=0, Listo = 1
if(Address==9'h000 && Read == 1'b1) NextState <= S17; // Direccion de memoria donde se hace la ultima lectura
else NextState <= S18;
end
S18: begin // Estado de resetea todos los registros excepto el resetInterfaz
NextState <= S1;
end
default: begin // Salidas por defecto iguales a la del reset
NextState <= RESETEADOR;
end
endcase
end
//********************************************LOGICA DE SALIDA COMBINACIONAL*********************************************
always @*
begin
case(State)
RESETEADOR: begin //***********ESTADO DE RESET DEL SISTEMA
ResetInterfaz <=1;
ResetStart<=1;
ResetCoeffALUandInput<=1;
EnableCoeffALUandInput<=0;
EnableMulX<=0;
SELCoeffX<=0;
EnableRegOutMultCoeffX<=0;
EnableFuctAct<=0;
EnableRegActFunc<=0;
EnableMulY<=0;
EnableRegDesplazamiento<=0;
EnableSum<=0;
SELCoeffY<=0;
SELOffset<=0;
EnableAcumulador<=0;
ResetAcumulador<=1;
Listo<=0;
end
S1: begin //***********ESTADO DE ESPERA INICIO
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=0;
SELCoeffX<=0;
EnableRegOutMultCoeffX<=0;
EnableFuctAct<=0;
EnableRegActFunc<=0;
EnableMulY<=0;
EnableRegDesplazamiento<=0;
EnableSum<=0;
SELCoeffY<=0;
SELOffset<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
Listo<=0;
end
S2: begin // ****************ESTADO DE HABILITA EnableCoeffALUandInput
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=1;
EnableMulX<=0;
SELCoeffX<=0;
EnableRegOutMultCoeffX<=0;
EnableFuctAct<=0;
EnableRegActFunc<=0;
EnableMulY<=0;
EnableRegDesplazamiento<=0;
EnableSum<=0;
SELCoeffY<=0;
SELOffset<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
Listo<=0;
end
S3: begin // **********EnableMultX = 01 and EnableRegOutMultCoeffX = 01 SELCoeffX= 00
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=1;
SELCoeffX<=0;
EnableRegOutMultCoeffX<=1;
EnableFuctAct<=0;
EnableRegActFunc<=0;
EnableMulY<=0;
EnableRegDesplazamiento<=0;
EnableSum<=0;
SELCoeffY<=0;
SELOffset<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
Listo<=0;
end
S4: begin // **********EnableMultX = 01 and EnableRegOutMultCoeffX = 01 SELCoeffX= 01, EnableFuctAct=1, EnableRegFuctAct=1,
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=1;
SELCoeffX<=1;
EnableRegOutMultCoeffX<=1;
EnableFuctAct<=1;
EnableRegActFunc<=1;
EnableMulY<=0;
EnableRegDesplazamiento<=0;
EnableSum<=0;
SELCoeffY<=0;
SELOffset<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
Listo<=0;
end
S5: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 02, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =00, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=1;
SELCoeffX<=2;
EnableRegOutMultCoeffX<=1;
EnableFuctAct<=1;
EnableRegActFunc<=1;
EnableMulY<=1;
EnableRegDesplazamiento<=1;
EnableSum<=1;
SELCoeffY<=0;
SELOffset<=0;
EnableAcumulador<=1;
ResetAcumulador<=0;
Listo<=0;
end
S6: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 03, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =01, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=1;
SELCoeffX<=3;
EnableRegOutMultCoeffX<=1;
EnableFuctAct<=1;
EnableRegActFunc<=1;
EnableMulY<=1;
EnableRegDesplazamiento<=1;
EnableSum<=1;
SELCoeffY<=1;
SELOffset<=0;
EnableAcumulador<=1;
ResetAcumulador<=0;
Listo<=0;
end
S7: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 04, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =02, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=1;
SELCoeffX<=4;
EnableRegOutMultCoeffX<=1;
EnableFuctAct<=1;
EnableRegActFunc<=1;
EnableMulY<=1;
EnableRegDesplazamiento<=1;
EnableSum<=1;
SELCoeffY<=2;
SELOffset<=0;
EnableAcumulador<=1;
ResetAcumulador<=0;
Listo<=0;
end
S8: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 05, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =03, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=1;
SELCoeffX<=5;
EnableRegOutMultCoeffX<=1;
EnableFuctAct<=1;
EnableRegActFunc<=1;
EnableMulY<=1;
EnableRegDesplazamiento<=1;
EnableSum<=1;
SELCoeffY<=3;
SELOffset<=0;
EnableAcumulador<=1;
ResetAcumulador<=0;
Listo<=0;
end
S9: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 06, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =04, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=1;
SELCoeffX<=6;
EnableRegOutMultCoeffX<=1;
EnableFuctAct<=1;
EnableRegActFunc<=1;
EnableMulY<=1;
EnableRegDesplazamiento<=1;
EnableSum<=1;
SELCoeffY<=4;
SELOffset<=0;
EnableAcumulador<=1;
ResetAcumulador<=0;
Listo<=0;
end
S10: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 07, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =05, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=1;
SELCoeffX<=7;
EnableRegOutMultCoeffX<=1;
EnableFuctAct<=1;
EnableRegActFunc<=1;
EnableMulY<=1;
EnableRegDesplazamiento<=1;
EnableSum<=1;
SELCoeffY<=5;
SELOffset<=0;
EnableAcumulador<=1;
ResetAcumulador<=0;
Listo<=0;
end
S11: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 08, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =06, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=1;
SELCoeffX<=8;
EnableRegOutMultCoeffX<=1;
EnableFuctAct<=1;
EnableRegActFunc<=1;
EnableMulY<=1;
EnableRegDesplazamiento<=1;
EnableSum<=1;
SELCoeffY<=6;
SELOffset<=0;
EnableAcumulador<=1;
ResetAcumulador<=0;
Listo<=0;
end
S12: begin // **********EnableMultX = 1 and EnableRegOutMultCoeffX = 1 SELCoeffX= 09, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =07, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=1;
SELCoeffX<=9;
EnableRegOutMultCoeffX<=1;
EnableFuctAct<=1;
EnableRegActFunc<=1;
EnableMulY<=1;
EnableRegDesplazamiento<=1;
EnableSum<=1;
SELCoeffY<=7;
SELOffset<=0;
EnableAcumulador<=1;
ResetAcumulador<=0;
Listo<=0;
end
S13: begin // **********EnableMultX = 0 and EnableRegOutMultCoeffX = 0 SELCoeffX= 00, EnableFuctAct=1, EnableRegFuctAct=1, SELCoeffY =08, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=0;
SELCoeffX<=0;
EnableRegOutMultCoeffX<=0;
EnableFuctAct<=1;
EnableRegActFunc<=1;
EnableMulY<=1;
EnableRegDesplazamiento<=1;
EnableSum<=1;
SELCoeffY<=8;
SELOffset<=0;
EnableAcumulador<=1;
ResetAcumulador<=0;
Listo<=0;
end
S14: begin // **********EnableMultX = 0 and EnableRegOutMultCoeffX = 0 SELCoeffX= 00, EnableFuctAct=0, EnableRegFuctAct=0, SELCoeffY =09, EnableMultY=1,EnableSum=1,EnableRegDesplazamientro=1,SELOffset =0, Enable Acum=1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=0;
SELCoeffX<=0;
EnableRegOutMultCoeffX<=0;
EnableFuctAct<=0;
EnableRegActFunc<=0;
EnableMulY<=1;
EnableRegDesplazamiento<=1;
EnableSum<=1;
SELCoeffY<=9;
SELOffset<=0;
EnableAcumulador<=1;
ResetAcumulador<=0;
Listo<=0;
end
S15: begin // **********EnableMultX = 0 and EnableRegOutMultCoeffX = 0 SELCoeffX= 00, EnableFuctAct=0, EnableRegFuctAct=0, SELCoeffY =00, EnableMultY=0,EnableSum=1,EnableRegDesplazamientro=0,SELOffset =1, Enable Acum=1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=0;
SELCoeffX<=0;
EnableRegOutMultCoeffX<=0;
EnableFuctAct<=0;
EnableRegActFunc<=0;
EnableMulY<=0;
EnableRegDesplazamiento<=0;
EnableSum<=1;
SELCoeffY<=0;
SELOffset<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
Listo<=0;
end
S16: begin // **********EnableMultX = 0 and EnableRegOutMultCoeffX = 0 SELCoeffX= 00, EnableFuctAct=0, EnableRegFuctAct=0, SELCoeffY =00, EnableMultY=0,EnableSum=0,EnableRegDesplazamientro=0,SELOffset =0, Enable Acum=0, Listo = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=0;
SELCoeffX<=0;
EnableRegOutMultCoeffX<=0;
EnableFuctAct<=0;
EnableRegActFunc<=0;
EnableMulY<=0;
EnableRegDesplazamiento<=0;
EnableSum<=0;
SELCoeffY<=0;
SELOffset<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
Listo<=1;
end
S17: begin // **********EnableMultX = 0 and EnableRegOutMultCoeffX = 0 SELCoeffX= 00, EnableFuctAct=0, EnableRegFuctAct=0, SELCoeffY =00, EnableMultY=0,EnableSum=0,EnableRegDesplazamientro=0,SELOffset =0, Enable Acum=0, Listo = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
EnableMulX<=0;
SELCoeffX<=0;
EnableRegOutMultCoeffX<=0;
EnableFuctAct<=0;
EnableRegActFunc<=0;
EnableMulY<=0;
EnableRegDesplazamiento<=0;
EnableSum<=0;
SELCoeffY<=0;
SELOffset<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
Listo<=1;
end
S18: begin // Estado de resetea todos los registros excepto el resetInterfaz
ResetInterfaz <=0;
ResetStart<=1;
ResetCoeffALUandInput<=1;
EnableCoeffALUandInput<=0;
EnableMulX<=0;
SELCoeffX<=0;
EnableRegOutMultCoeffX<=0;
EnableFuctAct<=0;
EnableRegActFunc<=0;
EnableMulY<=0;
EnableRegDesplazamiento<=0;
EnableSum<=0;
SELCoeffY<=0;
SELOffset<=0;
EnableAcumulador<=0;
ResetAcumulador<=1;
Listo<=0;
end
default: begin // Salidas por defecto iguales a la del reset
ResetInterfaz <=1;
ResetStart<=1;
ResetCoeffALUandInput<=1;
EnableCoeffALUandInput<=0;
EnableMulX<=0;
SELCoeffX<=0;
EnableRegOutMultCoeffX<=0;
EnableFuctAct<=0;
EnableRegActFunc<=0;
EnableMulY<=0;
EnableRegDesplazamiento<=0;
EnableSum<=0;
SELCoeffY<=0;
SELOffset<=0;
EnableAcumulador<=0;
ResetAcumulador<=1;
Listo<=0;
end
endcase
end
endmodule
|
// -*- Mode: Verilog -*-
// Filename : test_tools.v
// Description : Tools to help with test cases
// Author : Philip Tracton
// Created On : Wed May 27 21:11:18 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed May 27 21:11:18 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module test_tools (/*AUTOARG*/ ) ;
//
// Registers
//
reg test_passed = 1'b0;
reg test_failed = 1'b0;
reg test_done = 1'b0;
reg [31:0] test_fail_count = 32'h0000_0000;
//
// A test case can assert test_passed to signal a succesful
// end to the test. This will terminate the test.
//
always @(posedge test_passed) begin
$display("Test Passed @ %d", $time);
#100 $finish;
end
//
// A test case can assert test_failed to signal a failing
// end to the test. This will terminate the test.
//
always @(posedge test_failed) begin
$display("Test Failed @ %d", $time);
#100 $finish;
end
//
// A test case can assert test_done to signal to figure out
// if the test case passed or failed and then terminate the simulation
//
always @(posedge test_done) begin
if (test_fail_count) begin
test_failed <= 1'b1;
end else begin
test_passed <= 1'b1;
end
end
//
// Task: test_case
//
// dstring -- String to $display to user
// value -- the measured data
// expected -- the expected data, if matches value then we passed, else fail
//
task test_case;
input [32*8-1:0] dstring;
input [31:0] value;
input [31:0] expected;
begin
if (value !== expected) begin
test_fail_count <= test_fail_count + 1;
end
$display("%s\t\t0x%h\t\t0x%h\t\t", dstring, value,expected );
end
endtask // if
endmodule // test_tools
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:19:56 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_ScratchRam_0_0/RAT_ScratchRam_0_0_sim_netlist.v
// Design : RAT_ScratchRam_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_ScratchRam_0_0,ScratchRam,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ScratchRam,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_ScratchRam_0_0
(DATA_IN,
DATA_OUT,
ADDR,
WE,
CLK);
input [9:0]DATA_IN;
output [9:0]DATA_OUT;
input [7:0]ADDR;
input WE;
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;
wire [7:0]ADDR;
wire CLK;
wire [9:0]DATA_IN;
wire [9:0]DATA_OUT;
wire WE;
RAT_ScratchRam_0_0_ScratchRam U0
(.ADDR(ADDR),
.CLK(CLK),
.DATA_IN(DATA_IN),
.DATA_OUT(DATA_OUT),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "ScratchRam" *)
module RAT_ScratchRam_0_0_ScratchRam
(DATA_OUT,
CLK,
DATA_IN,
WE,
ADDR);
output [9:0]DATA_OUT;
input CLK;
input [9:0]DATA_IN;
input WE;
input [7:0]ADDR;
wire [7:0]ADDR;
wire CLK;
wire [9:0]DATA_IN;
wire [9:0]DATA_OUT;
wire WE;
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_0_0
(.A(ADDR),
.D(DATA_IN[0]),
.O(DATA_OUT[0]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_1_1
(.A(ADDR),
.D(DATA_IN[1]),
.O(DATA_OUT[1]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_2_2
(.A(ADDR),
.D(DATA_IN[2]),
.O(DATA_OUT[2]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_3_3
(.A(ADDR),
.D(DATA_IN[3]),
.O(DATA_OUT[3]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_4_4
(.A(ADDR),
.D(DATA_IN[4]),
.O(DATA_OUT[4]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_5_5
(.A(ADDR),
.D(DATA_IN[5]),
.O(DATA_OUT[5]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_6_6
(.A(ADDR),
.D(DATA_IN[6]),
.O(DATA_OUT[6]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_7_7
(.A(ADDR),
.D(DATA_IN[7]),
.O(DATA_OUT[7]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_8_8
(.A(ADDR),
.D(DATA_IN[8]),
.O(DATA_OUT[8]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_9_9
(.A(ADDR),
.D(DATA_IN[9]),
.O(DATA_OUT[9]),
.WCLK(CLK),
.WE(WE));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NAND4_PP_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__AND3_BEHAVIORAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:43:33 09/07/2013
// Design Name: synchronizer
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab2/laboratorio2/test_synchronizer.v
// Project Name: laboratorio2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: synchronizer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_synchronizer;
// Inputs
reg clk;
reg rst;
reg sensor;
reg reprogram;
reg walk_btn;
// Outputs
wire rst_out;
wire sensor_out;
wire walk_register;
wire reprogram_out;
// Instantiate the Unit Under Test (UUT)
synchronizer uut (
.clk(clk),
.rst(rst),
.sensor(sensor),
.reprogram(reprogram),
.walk_btn(walk_btn),
.rst_out(rst_out),
.sensor_out(sensor_out),
.walk_register(walk_register),
.reprogram_out(reprogram_out)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
sensor = 0;
reprogram = 0;
walk_btn = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_1_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_1_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog wrapper for dlygate4sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlygate4sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlygate4sd1_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlygate4sd1_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A2BB2OI_FUNCTIONAL_PP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2OI_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3_1_V
`define SKY130_FD_SC_HDLL__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3_1_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2011 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_fpga.v
//
// *Module Description:
// openMSP430 FPGA Top-level for the Avnet LX9 Microboard
//
// *Author(s):
// - Ricardo Ribalda, [email protected]
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
`include "openmsp430/openMSP430_defines.v"
module openMSP430_fpga (
//----------------------------------------------
// User Reset Push Button
//----------------------------------------------
USER_RESET,
//----------------------------------------------
// Micron N25Q128 SPI Flash
// This is a Multi-I/O Flash. Several pins
// have dual purposes depending on the mode.
//----------------------------------------------
SPI_SCK,
SPI_CS_n,
SPI_MOSI_MISO0,
SPI_MISO_MISO1,
SPI_Wn_MISO2,
SPI_HOLDn_MISO3,
//----------------------------------------------
// TI CDCE913 Triple-Output PLL Clock Chip
// Y1: 40 MHz, USER_CLOCK can be used as
// external configuration clock
// Y2: 66.667 MHz
// Y3: 100 MHz
//----------------------------------------------
USER_CLOCK,
CLOCK_Y2,
CLOCK_Y3,
//----------------------------------------------
// The following oscillator is not populated
// in production but the footprint is compatible
// with the Maxim DS1088LU
//----------------------------------------------
BACKUP_CLK,
//----------------------------------------------
// User DIP Switch x4
//----------------------------------------------
GPIO_DIP1,
GPIO_DIP2,
GPIO_DIP3,
GPIO_DIP4,
//----------------------------------------------
// User LEDs
//----------------------------------------------
GPIO_LED1,
GPIO_LED2,
GPIO_LED3,
GPIO_LED4,
//----------------------------------------------
// Silicon Labs CP2102 USB-to-UART Bridge Chip
//----------------------------------------------
USB_RS232_RXD,
USB_RS232_TXD,
//----------------------------------------------
// Texas Instruments CDCE913 programming port
//----------------------------------------------
SCL,
SDA,
//----------------------------------------------
// Micron MT46H32M16LFBF-5 LPDDR
//----------------------------------------------
// Addresses
LPDDR_A0,
LPDDR_A1,
LPDDR_A2,
LPDDR_A3,
LPDDR_A4,
LPDDR_A5,
LPDDR_A6,
LPDDR_A7,
LPDDR_A8,
LPDDR_A9,
LPDDR_A10,
LPDDR_A11,
LPDDR_A12,
LPDDR_BA0,
LPDDR_BA1,
// Data
LPDDR_DQ0,
LPDDR_DQ1,
LPDDR_DQ2,
LPDDR_DQ3,
LPDDR_DQ4,
LPDDR_DQ5,
LPDDR_DQ6,
LPDDR_DQ7,
LPDDR_DQ8,
LPDDR_DQ9,
LPDDR_DQ10,
LPDDR_DQ11,
LPDDR_DQ12,
LPDDR_DQ13,
LPDDR_DQ14,
LPDDR_DQ15,
LPDDR_LDM,
LPDDR_UDM,
LPDDR_LDQS,
LPDDR_UDQS,
// Clock
LPDDR_CK_N,
LPDDR_CK_P,
LPDDR_CKE,
// Control
LPDDR_CAS_n,
LPDDR_RAS_n,
LPDDR_WE_n,
LPDDR_RZQ,
//----------------------------------------------
// National Semiconductor DP83848J 10/100 Ethernet PHY
// Pull-ups on RXD are necessary to set the PHY AD to 11110b.
// Must keep the PHY from defaulting to PHY AD = 00000b
// because this is Isolate Mode
//----------------------------------------------
ETH_COL,
ETH_CRS,
ETH_MDC,
ETH_MDIO,
ETH_RESET_n,
ETH_RX_CLK,
ETH_RX_D0,
ETH_RX_D1,
ETH_RX_D2,
ETH_RX_D3,
ETH_RX_DV,
ETH_RX_ER,
ETH_TX_CLK,
ETH_TX_D0,
ETH_TX_D1,
ETH_TX_D2,
ETH_TX_D3,
ETH_TX_EN,
//----------------------------------------------
// Peripheral Modules (PMODs) and GPIO
// https://www.digilentinc.com/PMODs
//----------------------------------------------
// Connector J5
PMOD1_P1,
PMOD1_P2,
PMOD1_P3,
PMOD1_P4,
PMOD1_P7,
PMOD1_P8,
PMOD1_P9,
PMOD1_P10,
// Connector J4
PMOD2_P1,
PMOD2_P2,
PMOD2_P3,
PMOD2_P4,
PMOD2_P7,
PMOD2_P8,
PMOD2_P9,
PMOD2_P10
);
//----------------------------------------------
// User Reset Push Button
//----------------------------------------------
input USER_RESET;
//----------------------------------------------
// Micron N25Q128 SPI Flash
// This is a Multi-I/O Flash. Several pins
// have dual purposes depending on the mode.
//----------------------------------------------
output SPI_SCK;
output SPI_CS_n;
inout SPI_MOSI_MISO0;
inout SPI_MISO_MISO1;
output SPI_Wn_MISO2;
output SPI_HOLDn_MISO3;
//----------------------------------------------
// TI CDCE913 Triple-Output PLL Clock Chip
// Y1: 40 MHz; USER_CLOCK can be used as
// external configuration clock
// Y2: 66.667 MHz
// Y3: 100 MHz
//----------------------------------------------
input USER_CLOCK;
input CLOCK_Y2;
input CLOCK_Y3;
//----------------------------------------------
// The following oscillator is not populated
// in production but the footprint is compatible
// with the Maxim DS1088LU
//----------------------------------------------
input BACKUP_CLK;
//----------------------------------------------
// User DIP Switch x4
//----------------------------------------------
input GPIO_DIP1;
input GPIO_DIP2;
input GPIO_DIP3;
input GPIO_DIP4;
//----------------------------------------------
// User LEDs
//----------------------------------------------
output GPIO_LED1;
output GPIO_LED2;
output GPIO_LED3;
output GPIO_LED4;
//----------------------------------------------
// Silicon Labs CP2102 USB-to-UART Bridge Chip
//----------------------------------------------
input USB_RS232_RXD;
output USB_RS232_TXD;
//----------------------------------------------
// Texas Instruments CDCE913 programming port
//----------------------------------------------
output SCL;
inout SDA;
//----------------------------------------------
// Micron MT46H32M16LFBF-5 LPDDR
//----------------------------------------------
// Addresses
output LPDDR_A0;
output LPDDR_A1;
output LPDDR_A2;
output LPDDR_A3;
output LPDDR_A4;
output LPDDR_A5;
output LPDDR_A6;
output LPDDR_A7;
output LPDDR_A8;
output LPDDR_A9;
output LPDDR_A10;
output LPDDR_A11;
output LPDDR_A12;
output LPDDR_BA0;
output LPDDR_BA1;
// Data
inout LPDDR_DQ0;
inout LPDDR_DQ1;
inout LPDDR_DQ2;
inout LPDDR_DQ3;
inout LPDDR_DQ4;
inout LPDDR_DQ5;
inout LPDDR_DQ6;
inout LPDDR_DQ7;
inout LPDDR_DQ8;
inout LPDDR_DQ9;
inout LPDDR_DQ10;
inout LPDDR_DQ11;
inout LPDDR_DQ12;
inout LPDDR_DQ13;
inout LPDDR_DQ14;
inout LPDDR_DQ15;
output LPDDR_LDM;
output LPDDR_UDM;
inout LPDDR_LDQS;
inout LPDDR_UDQS;
// Clock
output LPDDR_CK_N;
output LPDDR_CK_P;
output LPDDR_CKE;
// Control
output LPDDR_CAS_n;
output LPDDR_RAS_n;
output LPDDR_WE_n;
inout LPDDR_RZQ;
//----------------------------------------------
// National Semiconductor DP83848J 10/100 Ethernet PHY
// Pull-ups on RXD are necessary to set the PHY AD to 11110b.
// Must keep the PHY from defaulting to PHY AD = 00000b
// because this is Isolate Mode
//----------------------------------------------
input ETH_COL;
input ETH_CRS;
output ETH_MDC;
inout ETH_MDIO;
output ETH_RESET_n;
input ETH_RX_CLK;
input ETH_RX_D0;
input ETH_RX_D1;
input ETH_RX_D2;
input ETH_RX_D3;
input ETH_RX_DV;
input ETH_RX_ER;
input ETH_TX_CLK;
output ETH_TX_D0;
output ETH_TX_D1;
output ETH_TX_D2;
output ETH_TX_D3;
output ETH_TX_EN;
//----------------------------------------------
// Peripheral Modules (PMODs) and GPIO
// https://www.digilentinc.com/PMODs
//----------------------------------------------
// Connector J5
inout PMOD1_P1;
inout PMOD1_P2;
inout PMOD1_P3;
input PMOD1_P4;
inout PMOD1_P7;
inout PMOD1_P8;
inout PMOD1_P9;
inout PMOD1_P10;
// Connector J4
inout PMOD2_P1;
inout PMOD2_P2;
inout PMOD2_P3;
inout PMOD2_P4;
inout PMOD2_P7;
inout PMOD2_P8;
inout PMOD2_P9;
inout PMOD2_P10;
//=============================================================================
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
//=============================================================================
// Clock generation
wire clk_40mhz;
wire dcm_locked;
wire dcm_clkfx;
wire dcm_clk0;
wire dcm_clkfb;
wire dco_clk;
// Reset generation
wire reset_pin;
wire reset_pin_n;
wire reset_n;
// Debug interface
wire omsp_dbg_i2c_scl;
wire omsp_dbg_i2c_sda_in;
wire omsp_dbg_i2c_sda_out;
wire omsp0_dbg_i2c_sda_out;
wire omsp1_dbg_i2c_sda_out;
wire [23:0] chipscope_trigger;
// Data memory
wire [`DMEM_MSB:0] omsp0_dmem_addr;
wire omsp0_dmem_cen;
wire omsp0_dmem_cen_sp;
wire omsp0_dmem_cen_dp;
wire [15:0] omsp0_dmem_din;
wire [1:0] omsp0_dmem_wen;
wire [15:0] omsp0_dmem_dout;
wire [15:0] omsp0_dmem_dout_sp;
wire [15:0] omsp0_dmem_dout_dp;
reg omsp0_dmem_dout_sel;
wire [`DMEM_MSB:0] omsp1_dmem_addr;
wire omsp1_dmem_cen;
wire omsp1_dmem_cen_sp;
wire omsp1_dmem_cen_dp;
wire [15:0] omsp1_dmem_din;
wire [1:0] omsp1_dmem_wen;
wire [15:0] omsp1_dmem_dout;
wire [15:0] omsp1_dmem_dout_sp;
wire [15:0] omsp1_dmem_dout_dp;
reg omsp1_dmem_dout_sel;
// Program memory
wire [`PMEM_MSB:0] omsp0_pmem_addr;
wire omsp0_pmem_cen;
wire [15:0] omsp0_pmem_din;
wire [1:0] omsp0_pmem_wen;
wire [15:0] omsp0_pmem_dout;
wire [`PMEM_MSB:0] omsp1_pmem_addr;
wire omsp1_pmem_cen;
wire [15:0] omsp1_pmem_din;
wire [1:0] omsp1_pmem_wen;
wire [15:0] omsp1_pmem_dout;
// UART
wire omsp0_uart_rxd;
wire omsp0_uart_txd;
// LEDs & Switches
wire [3:0] omsp_switch;
wire [1:0] omsp0_led;
wire [1:0] omsp1_led;
//=============================================================================
// 2) RESET GENERATION & FPGA STARTUP
//=============================================================================
// Reset input buffer
IBUF ibuf_reset_n (.O(reset_pin), .I(USER_RESET));
assign reset_pin_n = ~reset_pin;
// Release the reset only, if the DCM is locked
assign reset_n = reset_pin_n & dcm_locked;
// Top level reset generation
wire dco_rst;
omsp_sync_reset sync_reset_dco (.rst_s (dco_rst), .clk(dco_clk), .rst_a(!reset_n));
//=============================================================================
// 3) CLOCK GENERATION
//=============================================================================
// Input buffers
//------------------------
IBUFG ibuf_clk_main (.O(clk_40mhz), .I(USER_CLOCK));
IBUFG ibuf_clk_y2 (.O(), .I(CLOCK_Y2));
IBUFG ibuf_clk_y3 (.O(), .I(CLOCK_Y3));
IBUFG ibuf_clk_bkup (.O(), .I(BACKUP_CLK));
// Digital Clock Manager
//------------------------
DCM_SP #(.CLKFX_MULTIPLY(7),
.CLKFX_DIVIDE(10),
.CLKIN_PERIOD(25.000)) dcm_inst (
// OUTPUTs
.CLKDV (),
.CLKFX (dcm_clkfx),
.CLKFX180 (),
.LOCKED (dcm_locked),
.PSDONE (),
.STATUS (),
.CLK0 (dcm_clk0),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLK90 (),
// INPUTs
.CLKFB (dcm_clkfb),
.CLKIN (clk_40mhz),
.DSSEN (1'b0),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.RST (reset_pin)
);
BUFG CLK0_BUFG_INST (
.I(dcm_clk0),
.O(dcm_clkfb)
);
//synthesis translate_off
defparam dcm_inst.CLKFX_MULTIPLY = 7;
defparam dcm_inst.CLKFX_DIVIDE = 10;
defparam dcm_inst.CLKIN_PERIOD = 25.000;
//synthesis translate_on
// Clock buffers
//------------------------
BUFG buf_sys_clock (.O(dco_clk), .I(dcm_clkfx));
//=============================================================================
// 4) OPENMSP430 SYSTEM 0
//=============================================================================
omsp_system_0 omsp_system_0_inst (
// Clock & Reset
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
// Serial Debug Interface (I2C)
.dbg_i2c_addr (7'd50), // Debug interface: I2C Address
.dbg_i2c_broadcast (7'd49), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (omsp_dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (omsp_dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_i2c_sda_out (omsp0_dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
// Data Memory
.dmem_addr (omsp0_dmem_addr), // Data Memory address
.dmem_cen (omsp0_dmem_cen), // Data Memory chip enable (low active)
.dmem_din (omsp0_dmem_din), // Data Memory data input
.dmem_wen (omsp0_dmem_wen), // Data Memory write enable (low active)
.dmem_dout (omsp0_dmem_dout), // Data Memory data output
// Program Memory
.pmem_addr (omsp0_pmem_addr), // Program Memory address
.pmem_cen (omsp0_pmem_cen), // Program Memory chip enable (low active)
.pmem_din (omsp0_pmem_din), // Program Memory data input (optional)
.pmem_wen (omsp0_pmem_wen), // Program Memory write enable (low active) (optional)
.pmem_dout (omsp0_pmem_dout), // Program Memory data output
// UART
.uart_rxd (omsp0_uart_rxd), // UART Data Receive (RXD)
.uart_txd (omsp0_uart_txd), // UART Data Transmit (TXD)
// Switches & LEDs
.switch (omsp_switch), // Input switches
.led (omsp0_led) // LEDs
);
//=============================================================================
// 5) OPENMSP430 SYSTEM 1
//=============================================================================
omsp_system_1 omsp_system_1_inst (
// Clock & Reset
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
// Serial Debug Interface (I2C)
.dbg_i2c_addr (7'd51), // Debug interface: I2C Address
.dbg_i2c_broadcast (7'd49), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (omsp_dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (omsp_dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_i2c_sda_out (omsp1_dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
// Data Memory
.dmem_addr (omsp1_dmem_addr), // Data Memory address
.dmem_cen (omsp1_dmem_cen), // Data Memory chip enable (low active)
.dmem_din (omsp1_dmem_din), // Data Memory data input
.dmem_wen (omsp1_dmem_wen), // Data Memory write enable (low active)
.dmem_dout (omsp1_dmem_dout), // Data Memory data output
// Program Memory
.pmem_addr (omsp1_pmem_addr), // Program Memory address
.pmem_cen (omsp1_pmem_cen), // Program Memory chip enable (low active)
.pmem_din (omsp1_pmem_din), // Program Memory data input (optional)
.pmem_wen (omsp1_pmem_wen), // Program Memory write enable (low active) (optional)
.pmem_dout (omsp1_pmem_dout), // Program Memory data output
// Switches & LEDs
.switch (omsp_switch), // Input switches
.led (omsp1_led) // LEDs
);
//=============================================================================
// 6) PROGRAM AND DATA MEMORIES
//=============================================================================
// Memory muxing (CPU 0)
assign omsp0_dmem_cen_sp = omsp0_dmem_addr[`DMEM_MSB] | omsp0_dmem_cen;
assign omsp0_dmem_cen_dp = ~omsp0_dmem_addr[`DMEM_MSB] | omsp0_dmem_cen;
assign omsp0_dmem_dout = omsp0_dmem_dout_sel ? omsp0_dmem_dout_sp : omsp0_dmem_dout_dp;
always @ (posedge dco_clk or posedge dco_rst)
if (dco_rst) omsp0_dmem_dout_sel <= 1'b1;
else if (~omsp0_dmem_cen_sp) omsp0_dmem_dout_sel <= 1'b1;
else if (~omsp0_dmem_cen_dp) omsp0_dmem_dout_sel <= 1'b0;
// Memory muxing (CPU 1)
assign omsp1_dmem_cen_sp = omsp1_dmem_addr[`DMEM_MSB] | omsp1_dmem_cen;
assign omsp1_dmem_cen_dp = ~omsp1_dmem_addr[`DMEM_MSB] | omsp1_dmem_cen;
assign omsp1_dmem_dout = omsp1_dmem_dout_sel ? omsp1_dmem_dout_sp : omsp1_dmem_dout_dp;
always @ (posedge dco_clk or posedge dco_rst)
if (dco_rst) omsp1_dmem_dout_sel <= 1'b1;
else if (~omsp1_dmem_cen_sp) omsp1_dmem_dout_sel <= 1'b1;
else if (~omsp1_dmem_cen_dp) omsp1_dmem_dout_sel <= 1'b0;
// Data Memory (CPU 0)
ram_16x1k_sp ram_16x1k_sp_dmem_omsp0 (
.clka ( dco_clk),
.ena (~omsp0_dmem_cen_sp),
.wea (~omsp0_dmem_wen),
.addra ( omsp0_dmem_addr[`DMEM_MSB-1:0]),
.dina ( omsp0_dmem_din),
.douta ( omsp0_dmem_dout_sp)
);
// Data Memory (CPU 1)
ram_16x1k_sp ram_16x1k_sp_dmem_omsp1 (
.clka ( dco_clk),
.ena (~omsp1_dmem_cen_sp),
.wea (~omsp1_dmem_wen),
.addra ( omsp1_dmem_addr[`DMEM_MSB-1:0]),
.dina ( omsp1_dmem_din),
.douta ( omsp1_dmem_dout_sp)
);
// Shared Data Memory
ram_16x1k_dp ram_16x1k_dp_dmem_shared (
.clka ( dco_clk),
.ena (~omsp0_dmem_cen_dp),
.wea (~omsp0_dmem_wen),
.addra ( omsp0_dmem_addr[`DMEM_MSB-1:0]),
.dina ( omsp0_dmem_din),
.douta ( omsp0_dmem_dout_dp),
.clkb ( dco_clk),
.enb (~omsp1_dmem_cen_dp),
.web (~omsp1_dmem_wen),
.addrb ( omsp1_dmem_addr[`DMEM_MSB-1:0]),
.dinb ( omsp1_dmem_din),
.doutb ( omsp1_dmem_dout_dp)
);
// Shared Program Memory
ram_16x8k_dp ram_16x8k_dp_pmem_shared (
.clka ( dco_clk),
.ena (~omsp0_pmem_cen),
.wea (~omsp0_pmem_wen),
.addra ( omsp0_pmem_addr),
.dina ( omsp0_pmem_din),
.douta ( omsp0_pmem_dout),
.clkb ( dco_clk),
.enb (~omsp1_pmem_cen),
.web (~omsp1_pmem_wen),
.addrb ( omsp1_pmem_addr),
.dinb ( omsp1_pmem_din),
.doutb ( omsp1_pmem_dout)
);
//=============================================================================
// 7) I/O CELLS
//=============================================================================
//----------------------------------------------
// Micron N25Q128 SPI Flash
// This is a Multi-I/O Flash. Several pins
// have dual purposes depending on the mode.
//----------------------------------------------
OBUF SPI_CLK_PIN (.I(1'b0), .O(SPI_SCK));
OBUF SPI_CSN_PIN (.I(1'b1), .O(SPI_CS_n));
IOBUF SPI_MOSI_MISO0_PIN (.T(1'b0), .I(1'b0), .O(), .IO(SPI_MOSI_MISO0));
IOBUF SPI_MISO_MISO1_PIN (.T(1'b0), .I(1'b0), .O(), .IO(SPI_MISO_MISO1));
OBUF SPI_WN_PIN (.I(1'b1), .O(SPI_Wn_MISO2));
OBUF SPI_HOLD_PIN (.I(1'b1), .O(SPI_HOLDn_MISO3));
//----------------------------------------------
// User DIP Switch x4
//----------------------------------------------
IBUF SW3_PIN (.O(omsp_switch[3]), .I(GPIO_DIP4));
IBUF SW2_PIN (.O(omsp_switch[2]), .I(GPIO_DIP3));
IBUF SW1_PIN (.O(omsp_switch[1]), .I(GPIO_DIP2));
IBUF SW0_PIN (.O(omsp_switch[0]), .I(GPIO_DIP1));
//----------------------------------------------
// User LEDs
//----------------------------------------------
OBUF LED3_PIN (.I(omsp1_led[1]), .O(GPIO_LED4));
OBUF LED2_PIN (.I(omsp1_led[0]), .O(GPIO_LED3));
OBUF LED1_PIN (.I(omsp0_led[1]), .O(GPIO_LED2));
OBUF LED0_PIN (.I(omsp0_led[0]), .O(GPIO_LED1));
//----------------------------------------------
// Silicon Labs CP2102 USB-to-UART Bridge Chip
//----------------------------------------------
IBUF UART_RXD_PIN (.O(omsp0_uart_rxd), .I(USB_RS232_RXD));
OBUF UART_TXD_PIN (.I(omsp0_uart_txd), .O(USB_RS232_TXD));
//----------------------------------------------
// Texas Instruments CDCE913 programming port
//----------------------------------------------
IOBUF SCL_PIN (.T(1'b0), .I(1'b1), .O(), .IO(SCL));
IOBUF SDA_PIN (.T(1'b0), .I(1'b1), .O(), .IO(SDA));
//----------------------------------------------
// Micron MT46H32M16LFBF-5 LPDDR
//----------------------------------------------
// Addresses
OBUF LPDDR_A0_PIN (.I(1'b0), .O(LPDDR_A0));
OBUF LPDDR_A1_PIN (.I(1'b0), .O(LPDDR_A1));
OBUF LPDDR_A2_PIN (.I(1'b0), .O(LPDDR_A2));
OBUF LPDDR_A3_PIN (.I(1'b0), .O(LPDDR_A3));
OBUF LPDDR_A4_PIN (.I(1'b0), .O(LPDDR_A4));
OBUF LPDDR_A5_PIN (.I(1'b0), .O(LPDDR_A5));
OBUF LPDDR_A6_PIN (.I(1'b0), .O(LPDDR_A6));
OBUF LPDDR_A7_PIN (.I(1'b0), .O(LPDDR_A7));
OBUF LPDDR_A8_PIN (.I(1'b0), .O(LPDDR_A8));
OBUF LPDDR_A9_PIN (.I(1'b0), .O(LPDDR_A9));
OBUF LPDDR_A10_PIN (.I(1'b0), .O(LPDDR_A10));
OBUF LPDDR_A11_PIN (.I(1'b0), .O(LPDDR_A11));
OBUF LPDDR_A12_PIN (.I(1'b0), .O(LPDDR_A12));
OBUF LPDDR_BA0_PIN (.I(1'b0), .O(LPDDR_BA0));
OBUF LPDDR_BA1_PIN (.I(1'b0), .O(LPDDR_BA1));
// Data
IOBUF LPDDR_DQ0_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ0));
IOBUF LPDDR_DQ1_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ1));
IOBUF LPDDR_DQ2_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ2));
IOBUF LPDDR_DQ3_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ3));
IOBUF LPDDR_DQ4_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ4));
IOBUF LPDDR_DQ5_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ5));
IOBUF LPDDR_DQ6_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ6));
IOBUF LPDDR_DQ7_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ7));
IOBUF LPDDR_DQ8_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ8));
IOBUF LPDDR_DQ9_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ9));
IOBUF LPDDR_DQ10_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ10));
IOBUF LPDDR_DQ11_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ11));
IOBUF LPDDR_DQ12_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ12));
IOBUF LPDDR_DQ13_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ13));
IOBUF LPDDR_DQ14_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ14));
IOBUF LPDDR_DQ15_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_DQ15));
OBUF LPDDR_LDM_PIN (.I(1'b0), .O(LPDDR_LDM));
OBUF LPDDR_UDM_PIN (.I(1'b0), .O(LPDDR_UDM));
IOBUF LPDDR_LDQS_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_LDQS));
IOBUF LPDDR_UDQS_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_UDQS));
// Clock
IOBUF LPDDR_CK_N_PIN (.T(1'b1), .I(1'b0), .O(), .IO(LPDDR_CK_N));
IOBUF LPDDR_CK_P_PIN (.T(1'b1), .I(1'b1), .O(), .IO(LPDDR_CK_P));
OBUF LPDDR_CKE_PIN (.I(1'b0), .O(LPDDR_CKE));
// Control
OBUF LPDDR_CAS_N_PIN (.I(1'b1), .O(LPDDR_CAS_n));
OBUF LPDDR_RAS_N_PIN (.I(1'b1), .O(LPDDR_RAS_n));
OBUF LPDDR_WE_N_PIN (.I(1'b1), .O(LPDDR_WE_n));
IOBUF LPDDR_RZQ_PIN (.T(1'b0), .I(1'b0), .O(), .IO(LPDDR_RZQ));
//----------------------------------------------
// National Semiconductor DP83848J 10/100 Ethernet PHY
// Pull-ups on RXD are necessary to set the PHY AD to 11110b.
// Must keep the PHY from defaulting to PHY AD = 00000b
// because this is Isolate Mode
//----------------------------------------------
IBUF ETH_COL_PIN (.O(), .I(ETH_COL));
IBUF ETH_CRS_PIN (.O(), .I(ETH_CRS));
OBUF ETH_MDC_PIN (.I(1'b0), .O(ETH_MDC));
IOBUF ETH_MDIO_PIN (.T(1'b0), .I(1'b0), .O(), .IO(ETH_MDIO));
OBUF ETH_RESET_N_PIN (.I(1'b1), .O(ETH_RESET_n));
IBUF ETH_RX_CLK_PIN (.O(), .I(ETH_RX_CLK));
IBUF ETH_RX_D0_PIN (.O(), .I(ETH_RX_D0));
IBUF ETH_RX_D1_PIN (.O(), .I(ETH_RX_D1));
IBUF ETH_RX_D2_PIN (.O(), .I(ETH_RX_D2));
IBUF ETH_RX_D3_PIN (.O(), .I(ETH_RX_D3));
IBUF ETH_RX_DV_PIN (.O(), .I(ETH_RX_DV));
IBUF ETH_RX_ER_PIN (.O(), .I(ETH_RX_ER));
IBUF ETH_TX_CLK_PIN (.O(), .I(ETH_TX_CLK));
OBUF ETH_TX_D0_PIN (.I(1'b0), .O(ETH_TX_D0));
OBUF ETH_TX_D1_PIN (.I(1'b0), .O(ETH_TX_D1));
OBUF ETH_TX_D2_PIN (.I(1'b0), .O(ETH_TX_D2));
OBUF ETH_TX_D3_PIN (.I(1'b0), .O(ETH_TX_D3));
OBUF ETH_TX_EN_PIN (.I(1'b0), .O(ETH_TX_EN));
//----------------------------------------------
// Peripheral Modules (PMODs) and GPIO
// https://www.digilentinc.com/PMODs
//----------------------------------------------
assign omsp_dbg_i2c_sda_out = omsp0_dbg_i2c_sda_out & omsp1_dbg_i2c_sda_out;
// Connector J5
IOBUF PMOD1_P1_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD1_P1));
IOBUF PMOD1_P2_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD1_P2));
IOBUF PMOD1_P3_PIN (.T(omsp_dbg_i2c_sda_out), .I(1'b0), .O(omsp_dbg_i2c_sda_in), .IO(PMOD1_P3));
IBUF PMOD1_P4_PIN ( .O(omsp_dbg_i2c_scl), .I (PMOD1_P4));
IOBUF PMOD1_P7_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD1_P7));
IBUF PMOD1_P8_PIN ( .O(), .I (PMOD1_P8));
IOBUF PMOD1_P9_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD1_P9));
IOBUF PMOD1_P10_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD1_P10));
// Connector J4
IOBUF PMOD2_P1_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD2_P1));
IOBUF PMOD2_P2_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD2_P2));
IOBUF PMOD2_P3_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD2_P3));
IOBUF PMOD2_P4_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD2_P4));
IOBUF PMOD2_P7_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD2_P7));
IOBUF PMOD2_P8_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD2_P8));
IOBUF PMOD2_P9_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD2_P9));
IOBUF PMOD2_P10_PIN (.T(1'b0), .I(1'b0), .O(), .IO(PMOD2_P10));
//=============================================================================
//8) CHIPSCOPE
//=============================================================================
//`define WITH_CHIPSCOPE
`ifdef WITH_CHIPSCOPE
// Sampling clock
reg [7:0] div_cnt;
always @ (posedge dco_clk or posedge dco_rst)
if (dco_rst) div_cnt <= 8'h00;
else if (div_cnt > 10) div_cnt <= 8'h00;
else div_cnt <= div_cnt+8'h01;
reg clk_sample;
always @ (posedge dco_clk or posedge dco_rst)
if (dco_rst) clk_sample <= 1'b0;
else clk_sample <= (div_cnt==8'h00);
// ChipScope instance
wire [35:0] chipscope_control;
chipscope_ila chipscope_ila (
.CONTROL (chipscope_control),
.CLK (clk_sample),
.TRIG0 (chipscope_trigger)
);
chipscope_icon chipscope_icon (
.CONTROL0 (chipscope_control)
);
assign chipscope_trigger[0] = 1'b0;
assign chipscope_trigger[1] = 1'b0;
assign chipscope_trigger[2] = 1'b0;
assign chipscope_trigger[23:3] = 21'h00_0000;
`endif
endmodule // openMSP430_fpga
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:38:16 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire n5245, NaN_reg, ready_add_subt, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_d_ff3_sign_out, FPSENCOS_d_ff1_operation_out,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag, FPADDSUB_OP_FLAG_SFG,
FPADDSUB_SIGN_FLAG_SFG, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_intAS, FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1483, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697,
n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737,
n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747,
n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757,
n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767,
n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777,
n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2193, DP_OP_26J216_122_5882_n18,
DP_OP_26J216_122_5882_n17, DP_OP_26J216_122_5882_n16,
DP_OP_26J216_122_5882_n15, DP_OP_26J216_122_5882_n14,
DP_OP_26J216_122_5882_n8, DP_OP_26J216_122_5882_n7,
DP_OP_26J216_122_5882_n6, DP_OP_26J216_122_5882_n5,
DP_OP_26J216_122_5882_n4, DP_OP_26J216_122_5882_n3,
DP_OP_26J216_122_5882_n2, DP_OP_26J216_122_5882_n1,
DP_OP_230J216_125_7006_n22, DP_OP_230J216_125_7006_n21,
DP_OP_230J216_125_7006_n20, DP_OP_230J216_125_7006_n19,
DP_OP_230J216_125_7006_n18, DP_OP_230J216_125_7006_n17,
DP_OP_230J216_125_7006_n16, DP_OP_230J216_125_7006_n15,
DP_OP_230J216_125_7006_n9, DP_OP_230J216_125_7006_n8,
DP_OP_230J216_125_7006_n7, DP_OP_230J216_125_7006_n6,
DP_OP_230J216_125_7006_n5, DP_OP_230J216_125_7006_n4,
DP_OP_230J216_125_7006_n3, DP_OP_230J216_125_7006_n2,
DP_OP_230J216_125_7006_n1, intadd_489_CI, intadd_489_SUM_2_,
intadd_489_SUM_1_, intadd_489_SUM_0_, intadd_489_n3, intadd_489_n2,
intadd_489_n1, intadd_490_CI, intadd_490_SUM_2_, intadd_490_SUM_1_,
intadd_490_SUM_0_, intadd_490_n3, intadd_490_n2, intadd_490_n1,
mult_x_69_n1224, mult_x_69_n1223, mult_x_69_n1222, mult_x_69_n1221,
mult_x_69_n1220, mult_x_69_n1219, mult_x_69_n1218, mult_x_69_n1217,
mult_x_69_n1216, mult_x_69_n1215, mult_x_69_n1214, mult_x_69_n1213,
mult_x_69_n1212, mult_x_69_n1211, mult_x_69_n1210, mult_x_69_n1209,
mult_x_69_n1208, mult_x_69_n1200, mult_x_69_n1199, mult_x_69_n1198,
mult_x_69_n1197, mult_x_69_n1196, mult_x_69_n1195, mult_x_69_n1194,
mult_x_69_n1193, mult_x_69_n1192, mult_x_69_n1191, mult_x_69_n1190,
mult_x_69_n1189, mult_x_69_n1188, mult_x_69_n1187, mult_x_69_n1186,
mult_x_69_n1185, mult_x_69_n1184, mult_x_69_n1183, mult_x_69_n1182,
mult_x_69_n1181, mult_x_69_n1176, mult_x_69_n1175, mult_x_69_n1174,
mult_x_69_n1173, mult_x_69_n1172, mult_x_69_n1170, mult_x_69_n1169,
mult_x_69_n1168, mult_x_69_n1167, mult_x_69_n1166, mult_x_69_n1165,
mult_x_69_n1164, mult_x_69_n1163, mult_x_69_n1162, mult_x_69_n1161,
mult_x_69_n1160, mult_x_69_n1159, mult_x_69_n1158, mult_x_69_n1157,
mult_x_69_n1156, mult_x_69_n1155, mult_x_69_n1154, mult_x_69_n1146,
mult_x_69_n1145, mult_x_69_n1144, mult_x_69_n1143, mult_x_69_n1142,
mult_x_69_n1141, mult_x_69_n1140, mult_x_69_n1139, mult_x_69_n1138,
mult_x_69_n1137, mult_x_69_n1136, mult_x_69_n1135, mult_x_69_n1134,
mult_x_69_n1133, mult_x_69_n1132, mult_x_69_n1131, mult_x_69_n1130,
mult_x_69_n1129, mult_x_69_n1128, mult_x_69_n1127, mult_x_69_n1122,
mult_x_69_n1121, mult_x_69_n1120, mult_x_69_n1119, mult_x_69_n1118,
mult_x_69_n1116, mult_x_69_n1115, mult_x_69_n1114, mult_x_69_n1113,
mult_x_69_n1112, mult_x_69_n1111, mult_x_69_n1110, mult_x_69_n1109,
mult_x_69_n1108, mult_x_69_n1107, mult_x_69_n1106, mult_x_69_n1105,
mult_x_69_n1104, mult_x_69_n1103, mult_x_69_n1102, mult_x_69_n1101,
mult_x_69_n1100, mult_x_69_n1092, mult_x_69_n1091, mult_x_69_n1090,
mult_x_69_n1089, mult_x_69_n1088, mult_x_69_n1087, mult_x_69_n1086,
mult_x_69_n1085, mult_x_69_n1084, mult_x_69_n1083, mult_x_69_n1082,
mult_x_69_n1081, mult_x_69_n1080, mult_x_69_n1079, mult_x_69_n1078,
mult_x_69_n1077, mult_x_69_n1076, mult_x_69_n1075, mult_x_69_n1074,
mult_x_69_n1068, mult_x_69_n1067, mult_x_69_n1066, mult_x_69_n1065,
mult_x_69_n1064, mult_x_69_n1063, mult_x_69_n1062, mult_x_69_n1061,
mult_x_69_n1060, mult_x_69_n1059, mult_x_69_n1058, mult_x_69_n1057,
mult_x_69_n1056, mult_x_69_n1055, mult_x_69_n1054, mult_x_69_n1053,
mult_x_69_n1052, mult_x_69_n1051, mult_x_69_n1050, mult_x_69_n1049,
mult_x_69_n1048, mult_x_69_n1047, mult_x_69_n1046, mult_x_69_n767,
mult_x_69_n764, mult_x_69_n762, mult_x_69_n761, mult_x_69_n760,
mult_x_69_n759, mult_x_69_n757, mult_x_69_n756, mult_x_69_n755,
mult_x_69_n754, mult_x_69_n752, mult_x_69_n751, mult_x_69_n750,
mult_x_69_n747, mult_x_69_n745, mult_x_69_n744, mult_x_69_n743,
mult_x_69_n740, mult_x_69_n739, mult_x_69_n738, mult_x_69_n737,
mult_x_69_n736, mult_x_69_n734, mult_x_69_n733, mult_x_69_n732,
mult_x_69_n731, mult_x_69_n730, mult_x_69_n729, mult_x_69_n728,
mult_x_69_n726, mult_x_69_n725, mult_x_69_n724, mult_x_69_n723,
mult_x_69_n722, mult_x_69_n721, mult_x_69_n720, mult_x_69_n718,
mult_x_69_n717, mult_x_69_n716, mult_x_69_n715, mult_x_69_n714,
mult_x_69_n713, mult_x_69_n712, mult_x_69_n710, mult_x_69_n709,
mult_x_69_n708, mult_x_69_n707, mult_x_69_n706, mult_x_69_n705,
mult_x_69_n702, mult_x_69_n700, mult_x_69_n699, mult_x_69_n698,
mult_x_69_n697, mult_x_69_n696, mult_x_69_n695, mult_x_69_n692,
mult_x_69_n691, mult_x_69_n690, mult_x_69_n689, mult_x_69_n688,
mult_x_69_n687, mult_x_69_n686, mult_x_69_n685, mult_x_69_n683,
mult_x_69_n682, mult_x_69_n681, mult_x_69_n680, mult_x_69_n679,
mult_x_69_n678, mult_x_69_n677, mult_x_69_n676, mult_x_69_n675,
mult_x_69_n674, mult_x_69_n672, mult_x_69_n671, mult_x_69_n670,
mult_x_69_n669, mult_x_69_n668, mult_x_69_n667, mult_x_69_n666,
mult_x_69_n665, mult_x_69_n664, mult_x_69_n663, mult_x_69_n661,
mult_x_69_n660, mult_x_69_n659, mult_x_69_n658, mult_x_69_n657,
mult_x_69_n656, mult_x_69_n655, mult_x_69_n654, mult_x_69_n653,
mult_x_69_n652, mult_x_69_n650, mult_x_69_n649, mult_x_69_n648,
mult_x_69_n647, mult_x_69_n646, mult_x_69_n645, mult_x_69_n644,
mult_x_69_n643, mult_x_69_n642, mult_x_69_n641, mult_x_69_n639,
mult_x_69_n638, mult_x_69_n637, mult_x_69_n636, mult_x_69_n635,
mult_x_69_n634, mult_x_69_n633, mult_x_69_n632, mult_x_69_n631,
mult_x_69_n630, mult_x_69_n629, mult_x_69_n628, mult_x_69_n627,
mult_x_69_n626, mult_x_69_n625, mult_x_69_n624, mult_x_69_n623,
mult_x_69_n622, mult_x_69_n621, mult_x_69_n620, mult_x_69_n619,
mult_x_69_n618, mult_x_69_n617, mult_x_69_n616, mult_x_69_n615,
mult_x_69_n614, mult_x_69_n613, mult_x_69_n612, mult_x_69_n611,
mult_x_69_n610, mult_x_69_n609, mult_x_69_n608, mult_x_69_n607,
mult_x_69_n606, mult_x_69_n605, mult_x_69_n604, mult_x_69_n603,
mult_x_69_n602, mult_x_69_n601, mult_x_69_n600, mult_x_69_n599,
mult_x_69_n598, mult_x_69_n597, mult_x_69_n596, mult_x_69_n595,
mult_x_69_n594, mult_x_69_n593, mult_x_69_n592, mult_x_69_n591,
mult_x_69_n590, mult_x_69_n589, mult_x_69_n588, mult_x_69_n587,
mult_x_69_n586, mult_x_69_n585, mult_x_69_n584, mult_x_69_n583,
mult_x_69_n582, mult_x_69_n581, mult_x_69_n580, mult_x_69_n579,
mult_x_69_n578, mult_x_69_n577, mult_x_69_n576, mult_x_69_n574,
mult_x_69_n573, mult_x_69_n572, mult_x_69_n571, mult_x_69_n570,
mult_x_69_n569, mult_x_69_n568, mult_x_69_n567, mult_x_69_n566,
mult_x_69_n564, mult_x_69_n563, mult_x_69_n562, mult_x_69_n561,
mult_x_69_n560, mult_x_69_n559, mult_x_69_n558, mult_x_69_n557,
mult_x_69_n556, mult_x_69_n555, mult_x_69_n554, mult_x_69_n553,
mult_x_69_n552, mult_x_69_n551, mult_x_69_n550, mult_x_69_n549,
mult_x_69_n548, mult_x_69_n547, mult_x_69_n545, mult_x_69_n543,
mult_x_69_n542, mult_x_69_n541, mult_x_69_n540, mult_x_69_n539,
mult_x_69_n538, mult_x_69_n536, mult_x_69_n535, mult_x_69_n534,
mult_x_69_n533, mult_x_69_n532, mult_x_69_n531, mult_x_69_n530,
mult_x_69_n529, mult_x_69_n528, mult_x_69_n527, mult_x_69_n526,
mult_x_69_n525, mult_x_69_n524, mult_x_69_n523, mult_x_69_n522,
mult_x_69_n521, mult_x_69_n519, mult_x_69_n518, mult_x_69_n517,
mult_x_69_n516, mult_x_69_n515, mult_x_69_n514, mult_x_69_n512,
mult_x_69_n511, mult_x_69_n510, mult_x_69_n509, mult_x_69_n508,
mult_x_69_n507, mult_x_69_n506, mult_x_69_n505, mult_x_69_n504,
mult_x_69_n503, mult_x_69_n502, mult_x_69_n501, mult_x_69_n499,
mult_x_69_n498, mult_x_69_n497, mult_x_69_n496, mult_x_69_n495,
mult_x_69_n493, mult_x_69_n492, mult_x_69_n491, mult_x_69_n490,
mult_x_69_n489, mult_x_69_n488, mult_x_69_n487, mult_x_69_n486,
mult_x_69_n485, mult_x_69_n484, mult_x_69_n482, mult_x_69_n481,
mult_x_69_n480, mult_x_69_n478, mult_x_69_n477, mult_x_69_n476,
mult_x_69_n475, mult_x_69_n474, mult_x_69_n473, n2196, n2197, n2198,
n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209,
n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219,
n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229,
n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239,
n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249,
n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259,
n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290,
n2291, n2292, n2293, n2295, n2296, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482,
n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492,
n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542,
n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552,
n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694,
n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704,
n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714,
n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724,
n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944,
n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954,
n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964,
n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974,
n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984,
n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994,
n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004,
n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014,
n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024,
n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034,
n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044,
n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054,
n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064,
n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074,
n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084,
n3085, n3086, n3087, n3088, n3089, n3091, n3092, n3093, n3094, n3095,
n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105,
n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115,
n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125,
n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3134, n3135, n3136,
n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146,
n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156,
n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166,
n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176,
n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186,
n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196,
n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206,
n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215, n3216,
n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225, n3226,
n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236,
n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246,
n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256,
n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266,
n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276,
n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286,
n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296,
n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306,
n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316,
n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326,
n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336,
n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3345, n3346, n3347,
n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357,
n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367,
n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377,
n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387,
n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397,
n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407,
n3409, n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418,
n3419, n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428,
n3429, n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438,
n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449,
n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459,
n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469,
n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479,
n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489,
n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499,
n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509,
n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519,
n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529,
n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539,
n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549,
n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559,
n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569,
n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579,
n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589,
n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599,
n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609,
n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620,
n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630,
n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640,
n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650,
n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660,
n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670,
n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680,
n3681, n3682, n3683, n3684, n3685, n3687, n3688, n3689, n3690, n3691,
n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701,
n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711,
n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3721, n3722,
n3723, n3724, n3725, n3726, n3728, n3729, n3730, n3731, n3732, n3733,
n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743,
n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753,
n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763,
n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773,
n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783,
n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793,
n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803,
n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813,
n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823,
n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833,
n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843,
n3844, n3845, n3846, n3847, n3848, n3849, n3851, n3852, n3853, n3854,
n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864,
n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874,
n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884,
n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894,
n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904,
n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914,
n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924,
n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934,
n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944,
n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954,
n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964,
n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974,
n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984,
n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994,
n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004,
n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014,
n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024,
n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034,
n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044,
n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054,
n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064,
n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074,
n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084,
n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094,
n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104,
n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114,
n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124,
n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134,
n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144,
n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154,
n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164,
n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174,
n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184,
n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194,
n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204,
n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214,
n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224,
n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234,
n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244,
n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254,
n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264,
n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274,
n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284,
n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294,
n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304,
n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314,
n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324,
n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334,
n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344,
n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354,
n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364,
n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374,
n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384,
n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394,
n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404,
n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414,
n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424,
n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434,
n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444,
n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454,
n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464,
n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474,
n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484,
n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494,
n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504,
n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514,
n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524,
n4525, n4526, n4527, n4528, n4529, n4530, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4636,
n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646,
n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656,
n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666,
n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676,
n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686,
n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696,
n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706,
n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716,
n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725, n4726,
n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735, n4736,
n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745, n4746,
n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756,
n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766,
n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775, n4776,
n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785, n4786,
n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795, n4796,
n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805, n4806,
n4807, n4808, n4809, n4810, n4813, n4814, n4815, n4816, n4817, n4818,
n4819, n4820, n4821, n4822, n4823, n4825, n4826, n4827, n4828, n4829,
n4830, n4831, n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839,
n4840, n4841, n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849,
n4850, n4851, n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859,
n4860, n4861, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870,
n4871, n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880,
n4881, n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890,
n4891, n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900,
n4901, n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910,
n4911, n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920,
n4921, n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930,
n4931, n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940,
n4941, n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950,
n4951, n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960,
n4961, n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970,
n4971, n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980,
n4981, n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990,
n4991, n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000,
n5001, n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010,
n5011, n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020,
n5021, n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030,
n5031, n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040,
n5041, n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050,
n5051, n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060,
n5061, n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070,
n5071, n5072, n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080,
n5081, n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090,
n5091, n5092, n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100,
n5101, n5102, n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110,
n5111, n5112, n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120,
n5121, n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130,
n5131, n5132, n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140,
n5141, n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150,
n5151, n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160,
n5161, n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170,
n5171, n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180,
n5181, n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190,
n5191, n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200,
n5201, n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210,
n5211, n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220,
n5221, n5222, n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230,
n5231, n5232, n5233, n5234, n5235, n5237, n5238, n5239, n5240, n5241,
n5242, n5243, n5244;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [30:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:1] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:0] FPMULT_P_Sgf;
wire [25:1] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [22:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n5212), .Q(
dataA[25]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n2379), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n5213), .Q(
dataA[27]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n5212), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n5212), .Q(
dataB[23]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n5211), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n2382), .Q(
dataB[26]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n5205), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n5211), .Q(
dataB[28]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n5202), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n5190), .Q(
dataB[31]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2132), .CK(clk), .RN(n5207), .Q(
FPSENCOS_d_ff3_LUT_out[3]), .QN(n5135) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2129), .CK(clk), .RN(n5192), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2127), .CK(clk), .RN(n5206), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2126), .CK(clk), .RN(n2266), .Q(
FPSENCOS_d_ff3_LUT_out[9]), .QN(n5134) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2124), .CK(clk), .RN(n5195), .Q(
FPSENCOS_d_ff3_LUT_out[12]), .QN(n5130) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2123), .CK(clk), .RN(n2266), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2122), .CK(clk), .RN(n5195), .Q(
FPSENCOS_d_ff3_LUT_out[15]), .QN(n5136) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2121), .CK(clk), .RN(n5192), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2120), .CK(clk), .RN(n5210), .Q(
FPSENCOS_d_ff3_LUT_out[21]), .QN(n5131) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2115), .CK(clk), .RN(n2266), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1854), .CK(clk), .RN(n5195),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1853), .CK(clk), .RN(n5208),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1852), .CK(clk), .RN(n5218),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1851), .CK(clk), .RN(n5210),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1850), .CK(clk), .RN(n5206),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1849), .CK(clk), .RN(n2266),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1848), .CK(clk), .RN(n5195),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1953), .CK(clk), .RN(n5208),
.Q(FPSENCOS_d_ff3_sh_x_out[23]), .QN(n5133) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1952), .CK(clk), .RN(n5207),
.Q(FPSENCOS_d_ff3_sh_x_out[24]), .QN(n5147) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1951), .CK(clk), .RN(n5209),
.Q(FPSENCOS_d_ff3_sh_x_out[25]), .QN(n5148) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1950), .CK(clk), .RN(n5190),
.Q(FPSENCOS_d_ff3_sh_x_out[26]), .QN(n5149) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1949), .CK(clk), .RN(n5210),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1948), .CK(clk), .RN(n5206),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1947), .CK(clk), .RN(n2266),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1946), .CK(clk), .RN(n5208),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2114), .CK(clk), .RN(n5190), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2113), .CK(clk), .RN(n5194), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2112), .CK(clk), .RN(n2380), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2111), .CK(clk), .RN(n5198), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2110), .CK(clk), .RN(n5206), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2109), .CK(clk), .RN(n2381), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2108), .CK(clk), .RN(n5198), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2107), .CK(clk), .RN(n5191), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2106), .CK(clk), .RN(n5220), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2105), .CK(clk), .RN(n5221), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2104), .CK(clk), .RN(n2265), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2103), .CK(clk), .RN(n5220), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2102), .CK(clk), .RN(n5209), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2101), .CK(clk), .RN(n2382), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2100), .CK(clk), .RN(n5194), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2099), .CK(clk), .RN(n5191), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2098), .CK(clk), .RN(n2379), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2097), .CK(clk), .RN(n5221), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2096), .CK(clk), .RN(n2265), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2095), .CK(clk), .RN(n5198), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2094), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2093), .CK(clk), .RN(n5221), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2092), .CK(clk), .RN(n5194), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2091), .CK(clk), .RN(n5194), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2090), .CK(clk), .RN(n5191), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2089), .CK(clk), .RN(n5220), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2088), .CK(clk), .RN(n5194), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2087), .CK(clk), .RN(n2265), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2086), .CK(clk), .RN(n5198), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2085), .CK(clk), .RN(n5216), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2084), .CK(clk), .RN(n5212), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2083), .CK(clk), .RN(n5220), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1788), .CK(clk), .RN(n5191), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1743), .CK(clk), .RN(
n5220), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1705), .CK(clk), .RN(n2265),
.Q(cordic_result[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1785), .CK(clk), .RN(n5198), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1742), .CK(clk), .RN(
n5204), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1704), .CK(clk), .RN(n5216),
.Q(cordic_result[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1782), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1741), .CK(clk), .RN(
n2264), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1703), .CK(clk), .RN(n5217),
.Q(cordic_result[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1779), .CK(clk), .RN(n5215), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1740), .CK(clk), .RN(
n5214), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1702), .CK(clk), .RN(n5215),
.Q(cordic_result[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1776), .CK(clk), .RN(n5214), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1739), .CK(clk), .RN(
n5216), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1701), .CK(clk), .RN(n5199),
.Q(cordic_result[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1773), .CK(clk), .RN(n2264), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1738), .CK(clk), .RN(
n5218), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1858), .CK(clk), .RN(
n5217), .Q(FPSENCOS_d_ff2_Y[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1700), .CK(clk), .RN(n5215),
.Q(cordic_result[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1770), .CK(clk), .RN(n5214), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1699), .CK(clk), .RN(n5216),
.Q(cordic_result[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1767), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1736), .CK(clk), .RN(
n5199), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1698), .CK(clk), .RN(n5217),
.Q(cordic_result[30]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2010), .CK(clk), .RN(n5215), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1744), .CK(clk), .RN(
n5214), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1865), .CK(clk), .RN(
n5216), .Q(FPSENCOS_d_ff2_Y[22]), .QN(n5121) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1864), .CK(clk), .RN(n5199),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1962), .CK(clk), .RN(n5217),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2031), .CK(clk), .RN(n5215), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1751), .CK(clk), .RN(
n5214), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1879), .CK(clk), .RN(
n5219), .Q(FPSENCOS_d_ff2_Y[15]), .QN(n5114) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1878), .CK(clk), .RN(n5199),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1976), .CK(clk), .RN(n2264),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2022), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1748), .CK(clk), .RN(
n5199), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1873), .CK(clk), .RN(
n5218), .Q(FPSENCOS_d_ff2_Y[18]), .QN(n5117) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1872), .CK(clk), .RN(n5218),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1970), .CK(clk), .RN(n5215),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2013), .CK(clk), .RN(n5214), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1745), .CK(clk), .RN(
n5216), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1867), .CK(clk), .RN(
n5219), .Q(FPSENCOS_d_ff2_Y[21]), .QN(n5120) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1866), .CK(clk), .RN(n5202),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1964), .CK(clk), .RN(n5196),
.Q(FPSENCOS_d_ff3_sh_x_out[21]), .QN(n5146) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2019), .CK(clk), .RN(n5197), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1747), .CK(clk), .RN(
n5202), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1871), .CK(clk), .RN(
n2382), .Q(FPSENCOS_d_ff2_Y[19]), .QN(n5118) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1870), .CK(clk), .RN(n2379),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1968), .CK(clk), .RN(n2380),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2016), .CK(clk), .RN(n5196), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1746), .CK(clk), .RN(
n5205), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1869), .CK(clk), .RN(
n2382), .Q(FPSENCOS_d_ff2_Y[20]), .QN(n5119) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1868), .CK(clk), .RN(n5202),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1966), .CK(clk), .RN(n2381),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2025), .CK(clk), .RN(n5196), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1749), .CK(clk), .RN(
n5205), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1875), .CK(clk), .RN(
n5204), .Q(FPSENCOS_d_ff2_Y[17]), .QN(n5116) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1874), .CK(clk), .RN(n2380),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1972), .CK(clk), .RN(n5211),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2064), .CK(clk), .RN(n5197), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1762), .CK(clk), .RN(
n5190), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1901), .CK(clk), .RN(
n5211), .Q(FPSENCOS_d_ff2_Y[4]), .QN(n5103) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1900), .CK(clk), .RN(n2381),
.Q(FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1998), .CK(clk), .RN(n5190),
.Q(FPSENCOS_d_ff3_sh_x_out[4]), .QN(n5140) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2058), .CK(clk), .RN(n5211), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1760), .CK(clk), .RN(
n2380), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1897), .CK(clk), .RN(
n5207), .Q(FPSENCOS_d_ff2_Y[6]), .QN(n5105) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1896), .CK(clk), .RN(n5209),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1994), .CK(clk), .RN(n5203),
.Q(FPSENCOS_d_ff3_sh_x_out[6]), .QN(n5141) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2037), .CK(clk), .RN(n5210), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1753), .CK(clk), .RN(
n5206), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1883), .CK(clk), .RN(
n5195), .Q(FPSENCOS_d_ff2_Y[13]), .QN(n5112) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1882), .CK(clk), .RN(n5208),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1980), .CK(clk), .RN(n5198),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2028), .CK(clk), .RN(n5191), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1750), .CK(clk), .RN(
n5210), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1877), .CK(clk), .RN(
n5191), .Q(FPSENCOS_d_ff2_Y[16]), .QN(n5115) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1876), .CK(clk), .RN(n5220),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1974), .CK(clk), .RN(n2265),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1804), .CK(clk), .RN(n5165), .QN(n2225) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2052), .CK(clk), .RN(n5198), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1758), .CK(clk), .RN(
n5199), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1893), .CK(clk), .RN(
n5193), .Q(FPSENCOS_d_ff2_Y[8]), .QN(n5107) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1892), .CK(clk), .RN(n5193),
.Q(FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1990), .CK(clk), .RN(n5190),
.Q(FPSENCOS_d_ff3_sh_x_out[8]), .QN(n5142) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2043), .CK(clk), .RN(n5203), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1755), .CK(clk), .RN(
n5211), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1887), .CK(clk), .RN(
n5190), .Q(FPSENCOS_d_ff2_Y[11]), .QN(n5110) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1886), .CK(clk), .RN(n5204),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1984), .CK(clk), .RN(n5193),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1798), .CK(clk), .RN(n2268),
.QN(n2226) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2034), .CK(clk), .RN(n5193), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1752), .CK(clk), .RN(
n5193), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1881), .CK(clk), .RN(
n5193), .Q(FPSENCOS_d_ff2_Y[14]), .QN(n5113) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1880), .CK(clk), .RN(n5193),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1978), .CK(clk), .RN(n5193),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2046), .CK(clk), .RN(n5193), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1756), .CK(clk), .RN(
n5193), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1889), .CK(clk), .RN(
n5192), .Q(FPSENCOS_d_ff2_Y[10]), .QN(n5109) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1888), .CK(clk), .RN(n5192),
.Q(FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1986), .CK(clk), .RN(n5192),
.Q(FPSENCOS_d_ff3_sh_x_out[10]), .QN(n5144) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1800), .CK(clk), .RN(n5185), .QN(n2227) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2040), .CK(clk), .RN(n5192), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1754), .CK(clk), .RN(
n5192), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1885), .CK(clk), .RN(
n5192), .Q(FPSENCOS_d_ff2_Y[12]), .QN(n5111) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1884), .CK(clk), .RN(n5192),
.Q(FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1982), .CK(clk), .RN(n2265),
.Q(FPSENCOS_d_ff3_sh_x_out[12]), .QN(n5145) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1911), .CK(clk), .RN(n5198), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1847), .CK(clk), .RN(
n2264), .Q(FPSENCOS_d_ff2_Y[31]), .QN(n2230) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1846), .CK(clk), .RN(n5194),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1729), .CK(clk), .RN(n5191), .Q(
FPSENCOS_d_ff_Xn[31]), .QN(n5097) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1945), .CK(clk), .RN(
n5220), .QN(n2234) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1944), .CK(clk), .RN(n5221),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2067), .CK(clk), .RN(n2265), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1763), .CK(clk), .RN(
n5192), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1903), .CK(clk), .RN(
n5197), .Q(FPSENCOS_d_ff2_Y[3]), .QN(n5102) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1902), .CK(clk), .RN(n5190),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n2000), .CK(clk), .RN(n5211),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1725), .CK(clk), .RN(n2380),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2070), .CK(clk), .RN(n5190), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1764), .CK(clk), .RN(
n5190), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1905), .CK(clk), .RN(
n5193), .Q(FPSENCOS_d_ff2_Y[2]), .QN(n5101) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1904), .CK(clk), .RN(n5209),
.Q(FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2002), .CK(clk), .RN(n5210),
.Q(FPSENCOS_d_ff3_sh_x_out[2]), .QN(n5139) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1726), .CK(clk), .RN(n5206),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2055), .CK(clk), .RN(n2266), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1759), .CK(clk), .RN(
n5195), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1895), .CK(clk), .RN(
n5207), .Q(FPSENCOS_d_ff2_Y[7]), .QN(n5106) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1894), .CK(clk), .RN(n5209),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1992), .CK(clk), .RN(n5208),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2076), .CK(clk), .RN(n5209), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1766), .CK(clk), .RN(
n5202), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1909), .CK(clk), .RN(
n5206), .Q(FPSENCOS_d_ff2_Y[0]), .QN(n5099) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1908), .CK(clk), .RN(n5195),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2006), .CK(clk), .RN(n5208),
.Q(FPSENCOS_d_ff3_sh_x_out[0]), .QN(n5137) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1728), .CK(clk), .RN(n5204),
.Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2073), .CK(clk), .RN(n2380), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1765), .CK(clk), .RN(
n5197), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1907), .CK(clk), .RN(
n2379), .Q(FPSENCOS_d_ff2_Y[1]), .QN(n5100) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1906), .CK(clk), .RN(n2381),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2004), .CK(clk), .RN(n5196),
.Q(FPSENCOS_d_ff3_sh_x_out[1]), .QN(n5138) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1727), .CK(clk), .RN(n5205),
.Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2049), .CK(clk), .RN(n5203), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1757), .CK(clk), .RN(
n5204), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1891), .CK(clk), .RN(
n2380), .Q(FPSENCOS_d_ff2_Y[9]), .QN(n5108) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1890), .CK(clk), .RN(n5204),
.Q(FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1989), .CK(clk), .RN(
n5197), .QN(n2233) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1988), .CK(clk), .RN(n5202),
.Q(FPSENCOS_d_ff3_sh_x_out[9]), .QN(n5143) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2061), .CK(clk), .RN(n2381), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1761), .CK(clk), .RN(
n2382), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1899), .CK(clk), .RN(
n5205), .Q(FPSENCOS_d_ff2_Y[5]), .QN(n5104) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1898), .CK(clk), .RN(n5203),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1996), .CK(clk), .RN(n2379),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1723), .CK(clk), .RN(n2381),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1724), .CK(clk), .RN(n5196),
.Q(cordic_result[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1708), .CK(clk), .RN(n5203),
.Q(cordic_result[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1709), .CK(clk), .RN(n5204),
.Q(cordic_result[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1707), .CK(clk), .RN(n5196),
.Q(cordic_result[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1706), .CK(clk), .RN(n5204),
.Q(cordic_result[22]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1696), .CK(clk),
.RN(n5222), .Q(FPMULT_Op_MY[31]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1685), .CK(clk),
.RN(n2386), .QN(n2221) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1684), .CK(clk),
.RN(n5232), .QN(n2205) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1677), .CK(clk),
.RN(n5230), .QN(n2210) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n1662), .CK(clk),
.RN(n5228), .QN(n2211) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1658), .CK(clk),
.RN(n5230), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1602), .CK(clk),
.RN(n2386), .QN(n2232) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1624), .CK(clk), .RN(
n2386), .Q(FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1601), .CK(clk),
.RN(n5232), .Q(FPMULT_Add_result[23]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_22_ ( .D(n1575), .CK(clk), .RN(
n5218), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_1_ ( .D(n1554), .CK(clk), .RN(
n5199), .Q(FPMULT_P_Sgf[1]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_0_ ( .D(n1553), .CK(clk), .RN(
n2264), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1519), .CK(
clk), .RN(n5224), .QN(n2214) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1518), .CK(
clk), .RN(n5226), .QN(n2203) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1515), .CK(clk), .RN(n5223), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1514), .CK(clk), .RN(n5233), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1513), .CK(clk), .RN(n5227), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1512), .CK(clk), .RN(n5222), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1511), .CK(clk), .RN(n5229), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1510), .CK(clk), .RN(n5225), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1509), .CK(clk), .RN(n5224), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1508), .CK(clk), .RN(n2386), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1507), .CK(clk), .RN(n5231), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1506), .CK(clk), .RN(n5231), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1505), .CK(clk), .RN(n5231), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1504), .CK(clk), .RN(n5231), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1503), .CK(clk), .RN(n5231), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1502), .CK(clk), .RN(n5231), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1501), .CK(clk), .RN(n5231), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1500), .CK(clk), .RN(n5231), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1499), .CK(clk), .RN(n5231), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1498), .CK(clk), .RN(n5231), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1497), .CK(clk), .RN(n5223), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1496), .CK(clk), .RN(n5233), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1495), .CK(clk), .RN(n5229), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1494), .CK(clk), .RN(n5229), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1493), .CK(clk), .RN(n5229), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1492), .CK(clk), .RN(n5229), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1491), .CK(clk), .RN(n5227), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1490), .CK(clk), .RN(n5233), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1489), .CK(clk), .RN(n5227), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1488), .CK(clk), .RN(n5233), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1487), .CK(clk), .RN(n5227), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1486), .CK(clk), .RN(n5233), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1485), .CK(clk), .RN(n5223), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1483), .CK(clk), .RN(n5222), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1480), .CK(clk), .RN(
n5169), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1479), .CK(clk), .RN(
n5169), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1478), .CK(clk), .RN(
n5169), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1477), .CK(clk), .RN(
n5181), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1476), .CK(clk), .RN(
n5186), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1462), .CK(clk), .RN(n5166),
.Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1461), .CK(clk), .RN(n5170),
.Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1460), .CK(clk), .RN(n5184),
.Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1459), .CK(clk), .RN(n5183),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1458), .CK(clk), .RN(n5181),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1456), .CK(clk), .RN(
n5165), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1454), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1453), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1451), .CK(clk), .RN(
n5172), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1449), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1448), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1446), .CK(clk), .RN(
n5189), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1444), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1441), .CK(clk), .RN(
n5163), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1439), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n5171),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n5188),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1436), .CK(clk), .RN(
n5188), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1434), .CK(clk), .RN(n5165),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1433), .CK(clk), .RN(n5172),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n2378),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1431), .CK(clk), .RN(
n5165), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1429), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1428), .CK(clk), .RN(n5162),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n5188),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1426), .CK(clk), .RN(
n5172), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1424), .CK(clk), .RN(n5165),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1423), .CK(clk), .RN(n5172),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1421), .CK(clk), .RN(
n5189), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1414), .CK(clk), .RN(n5186), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1413), .CK(clk), .RN(n5162), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1411), .CK(clk), .RN(
n5162), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1409), .CK(clk), .RN(n5186),
.Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n5174), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1406), .CK(clk), .RN(n5174),
.Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n5167), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1403), .CK(clk), .RN(n2377),
.Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n5173), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1400), .CK(clk), .RN(n5173),
.Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n5186), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1397), .CK(clk), .RN(n5174),
.Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n5181), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1394), .CK(clk), .RN(n5173),
.Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n5173), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1391), .CK(clk), .RN(n5168),
.Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n2378), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1388), .CK(clk), .RN(n5182),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n5165), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(n5174),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n5183), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1382), .CK(clk), .RN(n5166),
.Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n5173), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1379), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n5181), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1376), .CK(clk), .RN(n5174),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n5165), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1373), .CK(clk), .RN(n2376),
.Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n5173), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1370), .CK(clk), .RN(n5183),
.Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n5183), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1367), .CK(clk), .RN(n5174),
.Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n5165), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1364), .CK(clk), .RN(n5170),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1363), .CK(clk), .RN(n5188), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n2268), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n5173),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1360), .CK(clk), .RN(n5181),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1359), .CK(clk), .RN(
n5169), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(n5189),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n5174), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n5189), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n2377),
.Q(FPADDSUB_OP_FLAG_SFG), .QN(n5084) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1332), .CK(clk), .RN(
n5188), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1330), .CK(clk), .RN(n2267),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n5180), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1328), .CK(clk), .RN(n5179),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(n5175),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n5177),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1324), .CK(clk), .RN(
n5187), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1320), .CK(clk), .RN(
n5163), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1319), .CK(clk), .RN(
n5176), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n2215) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1316), .CK(clk), .RN(
n5163), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1314), .CK(clk), .RN(n5164),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n5180), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1312), .CK(clk), .RN(n5179),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(n5175),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n5177),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1307), .CK(clk), .RN(n5176),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n5164), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1305), .CK(clk), .RN(n2267),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n5180),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n5179),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1300), .CK(clk), .RN(n5178),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n2267), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1298), .CK(clk), .RN(n5180),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n5179),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n5175),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1293), .CK(clk), .RN(n5177),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n5176), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1291), .CK(clk), .RN(n5164),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(n5178),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n2267),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1286), .CK(clk), .RN(n5180),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n5179), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1284), .CK(clk), .RN(n5175),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(n5177),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n5176),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1279), .CK(clk), .RN(n5164),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n5178), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1277), .CK(clk), .RN(n5178),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(n2267),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n5180),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1273), .CK(clk), .RN(n5179),
.Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1272), .CK(clk), .RN(
n5175), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1271), .CK(clk), .RN(n5177),
.Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(n5176),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n5164),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1267), .CK(clk), .RN(n5178),
.Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1266), .CK(clk), .RN(n2267),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n5170),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1263), .CK(clk), .RN(n5181),
.Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1262), .CK(clk), .RN(n5183),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n5166),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1259), .CK(clk), .RN(n5186),
.Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n5184),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n5182),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1255), .CK(clk), .RN(n2268),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1254), .CK(clk), .RN(n5185),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n5182),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1251), .CK(clk), .RN(n5184),
.Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1250), .CK(clk), .RN(n2268),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n5185),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1247), .CK(clk), .RN(n5183),
.Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1246), .CK(clk), .RN(n5181),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n5186),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1243), .CK(clk), .RN(n5182),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1242), .CK(clk), .RN(n5166),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n5182),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1239), .CK(clk), .RN(n5184),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1238), .CK(clk), .RN(n2268),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n5185),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1235), .CK(clk), .RN(n5181),
.Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1234), .CK(clk), .RN(n5183),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n5186),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1231), .CK(clk), .RN(n5166),
.Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1230), .CK(clk), .RN(n5170),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n5170),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1227), .CK(clk), .RN(n5183),
.Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1226), .CK(clk), .RN(n5181),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n5186),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1223), .CK(clk), .RN(n5182),
.Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1222), .CK(clk), .RN(n5184),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n2268),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1219), .CK(clk), .RN(n5185),
.Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1218), .CK(clk), .RN(n5183),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n5186),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1215), .CK(clk), .RN(n2268),
.Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1214), .CK(clk), .RN(n5185),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n5182),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1211), .CK(clk), .RN(n5166),
.Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1210), .CK(clk), .RN(n5170),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n5183),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
CMPR32X2TS DP_OP_26J216_122_5882_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n2198), .C(DP_OP_26J216_122_5882_n18), .CO(DP_OP_26J216_122_5882_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_230J216_125_7006_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n2358), .C(DP_OP_230J216_125_7006_n22), .CO(DP_OP_230J216_125_7006_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_230J216_125_7006_U9 ( .A(DP_OP_230J216_125_7006_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_230J216_125_7006_n9), .CO(
DP_OP_230J216_125_7006_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_230J216_125_7006_U8 ( .A(DP_OP_230J216_125_7006_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_230J216_125_7006_n8), .CO(
DP_OP_230J216_125_7006_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_230J216_125_7006_U7 ( .A(DP_OP_230J216_125_7006_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_230J216_125_7006_n7), .CO(
DP_OP_230J216_125_7006_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_230J216_125_7006_U6 ( .A(DP_OP_230J216_125_7006_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_230J216_125_7006_n6), .CO(
DP_OP_230J216_125_7006_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_230J216_125_7006_U5 ( .A(DP_OP_230J216_125_7006_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_230J216_125_7006_n5), .CO(
DP_OP_230J216_125_7006_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_230J216_125_7006_U4 ( .A(DP_OP_230J216_125_7006_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_230J216_125_7006_n4), .CO(
DP_OP_230J216_125_7006_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_230J216_125_7006_U3 ( .A(DP_OP_230J216_125_7006_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_230J216_125_7006_n3), .CO(
DP_OP_230J216_125_7006_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_230J216_125_7006_U2 ( .A(n2358), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_230J216_125_7006_n2), .CO(DP_OP_230J216_125_7006_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_489_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n4994), .C(
intadd_489_CI), .CO(intadd_489_n3), .S(intadd_489_SUM_0_) );
CMPR32X2TS intadd_489_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n4260), .C(
intadd_489_n3), .CO(intadd_489_n2), .S(intadd_489_SUM_1_) );
CMPR42X1TS mult_x_69_U632 ( .A(mult_x_69_n764), .B(mult_x_69_n1176), .C(
mult_x_69_n767), .D(mult_x_69_n1200), .ICI(mult_x_69_n1224), .S(
mult_x_69_n762), .ICO(mult_x_69_n760), .CO(mult_x_69_n761) );
CMPR42X1TS mult_x_69_U630 ( .A(mult_x_69_n759), .B(mult_x_69_n1175), .C(
mult_x_69_n760), .D(mult_x_69_n1223), .ICI(mult_x_69_n1199), .S(
mult_x_69_n757), .ICO(mult_x_69_n755), .CO(mult_x_69_n756) );
CMPR42X1TS mult_x_69_U628 ( .A(mult_x_69_n754), .B(mult_x_69_n1198), .C(
mult_x_69_n1174), .D(mult_x_69_n755), .ICI(mult_x_69_n1222), .S(
mult_x_69_n752), .ICO(mult_x_69_n750), .CO(mult_x_69_n751) );
CMPR42X1TS mult_x_69_U625 ( .A(mult_x_69_n747), .B(mult_x_69_n1173), .C(
mult_x_69_n1197), .D(mult_x_69_n1221), .ICI(mult_x_69_n750), .S(
mult_x_69_n745), .ICO(mult_x_69_n743), .CO(mult_x_69_n744) );
CMPR42X1TS mult_x_69_U622 ( .A(mult_x_69_n1196), .B(mult_x_69_n1172), .C(
mult_x_69_n740), .D(mult_x_69_n743), .ICI(mult_x_69_n1220), .S(
mult_x_69_n738), .ICO(mult_x_69_n736), .CO(mult_x_69_n737) );
CMPR42X1TS mult_x_69_U619 ( .A(mult_x_69_n1219), .B(mult_x_69_n739), .C(
mult_x_69_n733), .D(mult_x_69_n1195), .ICI(mult_x_69_n736), .S(
mult_x_69_n731), .ICO(mult_x_69_n729), .CO(mult_x_69_n730) );
CMPR42X1TS mult_x_69_U617 ( .A(mult_x_69_n728), .B(mult_x_69_n1122), .C(
mult_x_69_n734), .D(mult_x_69_n1146), .ICI(mult_x_69_n1194), .S(
mult_x_69_n726), .ICO(mult_x_69_n724), .CO(mult_x_69_n725) );
CMPR42X1TS mult_x_69_U616 ( .A(mult_x_69_n1170), .B(mult_x_69_n732), .C(
mult_x_69_n1218), .D(mult_x_69_n729), .ICI(mult_x_69_n726), .S(
mult_x_69_n723), .ICO(mult_x_69_n721), .CO(mult_x_69_n722) );
CMPR42X1TS mult_x_69_U614 ( .A(mult_x_69_n720), .B(mult_x_69_n1121), .C(
mult_x_69_n724), .D(mult_x_69_n1169), .ICI(mult_x_69_n1217), .S(
mult_x_69_n718), .ICO(mult_x_69_n716), .CO(mult_x_69_n717) );
CMPR42X1TS mult_x_69_U613 ( .A(mult_x_69_n1145), .B(mult_x_69_n1193), .C(
mult_x_69_n725), .D(mult_x_69_n721), .ICI(mult_x_69_n718), .S(
mult_x_69_n715), .ICO(mult_x_69_n713), .CO(mult_x_69_n714) );
CMPR42X1TS mult_x_69_U610 ( .A(mult_x_69_n1168), .B(mult_x_69_n1216), .C(
mult_x_69_n717), .D(mult_x_69_n713), .ICI(mult_x_69_n710), .S(
mult_x_69_n707), .ICO(mult_x_69_n705), .CO(mult_x_69_n706) );
CMPR42X1TS mult_x_69_U607 ( .A(mult_x_69_n702), .B(mult_x_69_n1119), .C(
mult_x_69_n1167), .D(mult_x_69_n1143), .ICI(mult_x_69_n1191), .S(
mult_x_69_n700), .ICO(mult_x_69_n698), .CO(mult_x_69_n699) );
CMPR42X1TS mult_x_69_U606 ( .A(mult_x_69_n708), .B(mult_x_69_n1215), .C(
mult_x_69_n709), .D(mult_x_69_n700), .ICI(mult_x_69_n705), .S(
mult_x_69_n697), .ICO(mult_x_69_n695), .CO(mult_x_69_n696) );
CMPR42X1TS mult_x_69_U603 ( .A(mult_x_69_n1142), .B(mult_x_69_n1118), .C(
mult_x_69_n1190), .D(mult_x_69_n692), .ICI(mult_x_69_n1166), .S(
mult_x_69_n690), .ICO(mult_x_69_n688), .CO(mult_x_69_n689) );
CMPR42X1TS mult_x_69_U599 ( .A(mult_x_69_n1165), .B(mult_x_69_n691), .C(
mult_x_69_n1213), .D(mult_x_69_n682), .ICI(mult_x_69_n1189), .S(
mult_x_69_n680), .ICO(mult_x_69_n678), .CO(mult_x_69_n679) );
CMPR42X1TS mult_x_69_U598 ( .A(mult_x_69_n688), .B(mult_x_69_n1141), .C(
mult_x_69_n689), .D(mult_x_69_n680), .ICI(mult_x_69_n685), .S(
mult_x_69_n677), .ICO(mult_x_69_n675), .CO(mult_x_69_n676) );
CMPR42X1TS mult_x_69_U596 ( .A(mult_x_69_n674), .B(mult_x_69_n1068), .C(
mult_x_69_n683), .D(mult_x_69_n1092), .ICI(mult_x_69_n1116), .S(
mult_x_69_n672), .ICO(mult_x_69_n670), .CO(mult_x_69_n671) );
CMPR42X1TS mult_x_69_U595 ( .A(mult_x_69_n1140), .B(mult_x_69_n681), .C(
mult_x_69_n1188), .D(mult_x_69_n1164), .ICI(mult_x_69_n678), .S(
mult_x_69_n669), .ICO(mult_x_69_n667), .CO(mult_x_69_n668) );
CMPR42X1TS mult_x_69_U594 ( .A(mult_x_69_n1212), .B(mult_x_69_n672), .C(
mult_x_69_n679), .D(mult_x_69_n669), .ICI(mult_x_69_n675), .S(
mult_x_69_n666), .ICO(mult_x_69_n664), .CO(mult_x_69_n665) );
CMPR42X1TS mult_x_69_U592 ( .A(mult_x_69_n663), .B(mult_x_69_n1067), .C(
mult_x_69_n670), .D(mult_x_69_n1115), .ICI(mult_x_69_n1163), .S(
mult_x_69_n661), .ICO(mult_x_69_n659), .CO(mult_x_69_n660) );
CMPR42X1TS mult_x_69_U591 ( .A(mult_x_69_n1091), .B(mult_x_69_n1139), .C(
mult_x_69_n671), .D(mult_x_69_n667), .ICI(mult_x_69_n1211), .S(
mult_x_69_n658), .ICO(mult_x_69_n656), .CO(mult_x_69_n657) );
CMPR42X1TS mult_x_69_U590 ( .A(mult_x_69_n1187), .B(mult_x_69_n661), .C(
mult_x_69_n668), .D(mult_x_69_n664), .ICI(mult_x_69_n658), .S(
mult_x_69_n655), .ICO(mult_x_69_n653), .CO(mult_x_69_n654) );
CMPR42X1TS mult_x_69_U588 ( .A(mult_x_69_n652), .B(mult_x_69_n1090), .C(
mult_x_69_n1066), .D(mult_x_69_n1138), .ICI(mult_x_69_n659), .S(
mult_x_69_n650), .ICO(mult_x_69_n648), .CO(mult_x_69_n649) );
CMPR42X1TS mult_x_69_U587 ( .A(mult_x_69_n1186), .B(mult_x_69_n1114), .C(
mult_x_69_n1210), .D(mult_x_69_n1162), .ICI(mult_x_69_n650), .S(
mult_x_69_n647), .ICO(mult_x_69_n645), .CO(mult_x_69_n646) );
CMPR42X1TS mult_x_69_U586 ( .A(mult_x_69_n660), .B(mult_x_69_n656), .C(
mult_x_69_n657), .D(mult_x_69_n647), .ICI(mult_x_69_n653), .S(
mult_x_69_n644), .ICO(mult_x_69_n642), .CO(mult_x_69_n643) );
CMPR42X1TS mult_x_69_U584 ( .A(mult_x_69_n641), .B(mult_x_69_n1065), .C(
mult_x_69_n1089), .D(mult_x_69_n1113), .ICI(mult_x_69_n1209), .S(
mult_x_69_n639), .ICO(mult_x_69_n637), .CO(mult_x_69_n638) );
CMPR42X1TS mult_x_69_U583 ( .A(mult_x_69_n648), .B(mult_x_69_n1161), .C(
mult_x_69_n1137), .D(mult_x_69_n1185), .ICI(mult_x_69_n639), .S(
mult_x_69_n636), .ICO(mult_x_69_n634), .CO(mult_x_69_n635) );
CMPR42X1TS mult_x_69_U582 ( .A(mult_x_69_n645), .B(mult_x_69_n649), .C(
mult_x_69_n646), .D(mult_x_69_n636), .ICI(mult_x_69_n642), .S(
mult_x_69_n633), .ICO(mult_x_69_n631), .CO(mult_x_69_n632) );
CMPR42X1TS mult_x_69_U580 ( .A(mult_x_69_n630), .B(mult_x_69_n1088), .C(
mult_x_69_n1064), .D(mult_x_69_n1136), .ICI(mult_x_69_n1112), .S(
mult_x_69_n628), .ICO(mult_x_69_n626), .CO(mult_x_69_n627) );
CMPR42X1TS mult_x_69_U578 ( .A(mult_x_69_n634), .B(mult_x_69_n628), .C(
mult_x_69_n635), .D(mult_x_69_n625), .ICI(mult_x_69_n631), .S(
mult_x_69_n622), .ICO(mult_x_69_n620), .CO(mult_x_69_n621) );
CMPR42X1TS mult_x_69_U576 ( .A(mult_x_69_n629), .B(mult_x_69_n1063), .C(
mult_x_69_n619), .D(mult_x_69_n1111), .ICI(mult_x_69_n626), .S(
mult_x_69_n617), .ICO(mult_x_69_n615), .CO(mult_x_69_n616) );
CMPR42X1TS mult_x_69_U575 ( .A(mult_x_69_n1159), .B(mult_x_69_n1087), .C(
mult_x_69_n1183), .D(mult_x_69_n1135), .ICI(mult_x_69_n627), .S(
mult_x_69_n614), .ICO(mult_x_69_n612), .CO(mult_x_69_n613) );
CMPR42X1TS mult_x_69_U574 ( .A(mult_x_69_n617), .B(mult_x_69_n623), .C(
mult_x_69_n614), .D(mult_x_69_n624), .ICI(mult_x_69_n620), .S(
mult_x_69_n611), .ICO(mult_x_69_n609), .CO(mult_x_69_n610) );
CMPR42X1TS mult_x_69_U572 ( .A(mult_x_69_n618), .B(mult_x_69_n608), .C(
mult_x_69_n1086), .D(mult_x_69_n1062), .ICI(mult_x_69_n1110), .S(
mult_x_69_n606), .ICO(mult_x_69_n604), .CO(mult_x_69_n605) );
CMPR42X1TS mult_x_69_U571 ( .A(mult_x_69_n1182), .B(mult_x_69_n1134), .C(
mult_x_69_n615), .D(mult_x_69_n1158), .ICI(mult_x_69_n612), .S(
mult_x_69_n603), .ICO(mult_x_69_n601), .CO(mult_x_69_n602) );
CMPR42X1TS mult_x_69_U570 ( .A(mult_x_69_n616), .B(mult_x_69_n606), .C(
mult_x_69_n613), .D(mult_x_69_n603), .ICI(mult_x_69_n609), .S(
mult_x_69_n600), .ICO(mult_x_69_n598), .CO(mult_x_69_n599) );
CMPR42X1TS mult_x_69_U568 ( .A(mult_x_69_n607), .B(mult_x_69_n1061), .C(
mult_x_69_n1109), .D(mult_x_69_n597), .ICI(mult_x_69_n1085), .S(
mult_x_69_n595), .ICO(mult_x_69_n593), .CO(mult_x_69_n594) );
CMPR42X1TS mult_x_69_U567 ( .A(mult_x_69_n1181), .B(mult_x_69_n604), .C(
mult_x_69_n601), .D(mult_x_69_n1157), .ICI(mult_x_69_n1133), .S(
mult_x_69_n592), .ICO(mult_x_69_n590), .CO(mult_x_69_n591) );
CMPR42X1TS mult_x_69_U566 ( .A(mult_x_69_n605), .B(mult_x_69_n595), .C(
mult_x_69_n602), .D(mult_x_69_n592), .ICI(mult_x_69_n598), .S(
mult_x_69_n589), .ICO(mult_x_69_n587), .CO(mult_x_69_n588) );
CMPR42X1TS mult_x_69_U564 ( .A(mult_x_69_n586), .B(n4958), .C(
mult_x_69_n1084), .D(mult_x_69_n596), .ICI(mult_x_69_n1132), .S(
mult_x_69_n584), .ICO(mult_x_69_n582), .CO(mult_x_69_n583) );
CMPR42X1TS mult_x_69_U563 ( .A(mult_x_69_n593), .B(mult_x_69_n1060), .C(
mult_x_69_n1156), .D(mult_x_69_n1108), .ICI(mult_x_69_n590), .S(
mult_x_69_n581), .ICO(mult_x_69_n579), .CO(mult_x_69_n580) );
CMPR42X1TS mult_x_69_U560 ( .A(n4889), .B(mult_x_69_n585), .C(n4952), .D(
mult_x_69_n1059), .ICI(mult_x_69_n1155), .S(mult_x_69_n574), .ICO(
mult_x_69_n572), .CO(mult_x_69_n573) );
CMPR42X1TS mult_x_69_U559 ( .A(mult_x_69_n1107), .B(mult_x_69_n582), .C(
mult_x_69_n1083), .D(mult_x_69_n1131), .ICI(mult_x_69_n574), .S(
mult_x_69_n571), .ICO(mult_x_69_n569), .CO(mult_x_69_n570) );
CMPR42X1TS mult_x_69_U558 ( .A(mult_x_69_n579), .B(mult_x_69_n583), .C(
mult_x_69_n580), .D(mult_x_69_n571), .ICI(mult_x_69_n576), .S(
mult_x_69_n568), .ICO(mult_x_69_n566), .CO(mult_x_69_n567) );
CMPR42X1TS mult_x_69_U556 ( .A(FPMULT_Op_MY[6]), .B(n4886), .C(n4951), .D(
mult_x_69_n1082), .ICI(mult_x_69_n572), .S(mult_x_69_n564), .ICO(
mult_x_69_n562), .CO(mult_x_69_n563) );
CMPR42X1TS mult_x_69_U553 ( .A(n4948), .B(n2241), .C(n5158), .D(
mult_x_69_n1057), .ICI(mult_x_69_n562), .S(mult_x_69_n555), .ICO(
mult_x_69_n553), .CO(mult_x_69_n554) );
CMPR42X1TS mult_x_69_U552 ( .A(n4950), .B(mult_x_69_n1105), .C(
mult_x_69_n1081), .D(mult_x_69_n1129), .ICI(mult_x_69_n563), .S(
mult_x_69_n552), .ICO(mult_x_69_n550), .CO(mult_x_69_n551) );
CMPR42X1TS mult_x_69_U551 ( .A(mult_x_69_n555), .B(mult_x_69_n559), .C(
mult_x_69_n552), .D(mult_x_69_n560), .ICI(mult_x_69_n556), .S(
mult_x_69_n549), .ICO(mult_x_69_n547), .CO(mult_x_69_n548) );
CMPR42X1TS mult_x_69_U548 ( .A(mult_x_69_n545), .B(mult_x_69_n1128), .C(
mult_x_69_n1080), .D(mult_x_69_n1056), .ICI(mult_x_69_n1104), .S(
mult_x_69_n543), .ICO(mult_x_69_n541), .CO(mult_x_69_n542) );
CMPR42X1TS mult_x_69_U547 ( .A(mult_x_69_n554), .B(mult_x_69_n550), .C(
mult_x_69_n551), .D(mult_x_69_n543), .ICI(mult_x_69_n547), .S(
mult_x_69_n540), .ICO(mult_x_69_n538), .CO(mult_x_69_n539) );
CMPR42X1TS mult_x_69_U538 ( .A(n4888), .B(mult_x_69_n527), .C(
mult_x_69_n1101), .D(n4963), .ICI(mult_x_69_n1053), .S(mult_x_69_n519),
.ICO(mult_x_69_n517), .CO(mult_x_69_n518) );
CMPR42X1TS mult_x_69_U535 ( .A(FPMULT_Op_MY[12]), .B(n4885), .C(n4962), .D(
mult_x_69_n1100), .ICI(mult_x_69_n517), .S(mult_x_69_n512), .ICO(
mult_x_69_n510), .CO(mult_x_69_n511) );
CMPR42X1TS mult_x_69_U533 ( .A(n4887), .B(FPMULT_Op_MY[13]), .C(n5159), .D(
mult_x_69_n510), .ICI(n4965), .S(mult_x_69_n506), .ICO(mult_x_69_n504),
.CO(mult_x_69_n505) );
CMPR42X1TS mult_x_69_U529 ( .A(mult_x_69_n1074), .B(mult_x_69_n499), .C(
mult_x_69_n505), .D(mult_x_69_n1050), .ICI(mult_x_69_n501), .S(
mult_x_69_n497), .ICO(mult_x_69_n495), .CO(mult_x_69_n496) );
CMPR42X1TS mult_x_69_U524 ( .A(mult_x_69_n488), .B(n4973), .C(
mult_x_69_n1048), .D(mult_x_69_n492), .ICI(mult_x_69_n489), .S(
mult_x_69_n486), .ICO(mult_x_69_n484), .CO(mult_x_69_n485) );
DFFSX2TS R_3 ( .D(n5153), .CK(clk), .SN(n5220), .Q(n5238) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_29_ ( .D(n1582), .CK(clk), .RN(
n5200), .Q(FPMULT_P_Sgf[29]), .QN(n5129) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_30_ ( .D(n1583), .CK(clk), .RN(
n5200), .Q(FPMULT_P_Sgf[30]), .QN(n5128) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_31_ ( .D(n1584), .CK(clk), .RN(
n5200), .Q(FPMULT_P_Sgf[31]), .QN(n5127) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_24_ ( .D(n1577), .CK(clk), .RN(
n5201), .Q(FPMULT_P_Sgf[24]), .QN(n5126) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_25_ ( .D(n1578), .CK(clk), .RN(
n5200), .Q(FPMULT_P_Sgf[25]), .QN(n5125) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_26_ ( .D(n1579), .CK(clk), .RN(
n5200), .Q(FPMULT_P_Sgf[26]), .QN(n5124) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_27_ ( .D(n1580), .CK(clk), .RN(
n5200), .Q(FPMULT_P_Sgf[27]), .QN(n5123) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_28_ ( .D(n1581), .CK(clk), .RN(
n5200), .Q(FPMULT_P_Sgf[28]), .QN(n5122) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1625), .CK(
clk), .RN(n5222), .Q(FPMULT_Sgf_normalized_result[23]), .QN(n5096) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1622), .CK(clk), .RN(
n5232), .Q(FPMULT_Add_result[2]), .QN(n5095) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1860), .CK(clk), .RN(
n5219), .Q(FPSENCOS_d_ff2_Y[26]), .QN(n5094) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1861), .CK(clk), .RN(
n5218), .Q(FPSENCOS_d_ff2_Y[25]), .QN(n5093) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1862), .CK(clk), .RN(
n5214), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n5092) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1516), .CK(clk), .RN(
n5223), .Q(underflow_flag_mult), .QN(n5091) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1856), .CK(clk), .RN(
n5215), .Q(FPSENCOS_d_ff2_Y[30]), .QN(n5089) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1859), .CK(clk), .RN(
n5199), .Q(FPSENCOS_d_ff2_Y[27]), .QN(n5088) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1857), .CK(clk), .RN(
n5214), .Q(FPSENCOS_d_ff2_Y[29]), .QN(n5087) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1182), .CK(clk), .RN(
n2377), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n5086) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(n5221), .Q(
FPSENCOS_d_ff_Yn[31]), .QN(n5085) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1956), .CK(clk), .RN(
n2264), .Q(FPSENCOS_d_ff2_X[28]), .QN(n5082) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1820), .CK(clk), .RN(
n5172), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n5080) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1819), .CK(clk), .RN(
n5189), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n5079) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1539), .CK(
clk), .RN(n5225), .Q(FPMULT_Sgf_normalized_result[22]), .QN(n5078) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n5170),
.Q(FPADDSUB_DMP_SFG[22]), .QN(n5076) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2137), .CK(clk), .RN(n5207),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n5074) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1467), .CK(clk), .RN(n5181),
.Q(FPADDSUB_DMP_EXP_EWSW[23]), .QN(n5073) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1537), .CK(
clk), .RN(n5224), .Q(FPMULT_Sgf_normalized_result[20]), .QN(n5072) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1809), .CK(clk), .RN(n5188), .Q(FPADDSUB_Data_array_SWR[17]), .QN(n5071) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1810), .CK(clk), .RN(n5180), .Q(FPADDSUB_Data_array_SWR[18]), .QN(n5070) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1351), .CK(clk), .RN(
n2586), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n5068) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1913), .CK(clk), .RN(
n2586), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n5066) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1812), .CK(clk), .RN(n5168), .Q(FPADDSUB_Data_array_SWR[20]), .QN(n5065) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1811), .CK(clk), .RN(n5168), .Q(FPADDSUB_Data_array_SWR[19]), .QN(n5064) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n5185),
.Q(FPADDSUB_DMP_SFG[21]), .QN(n5063) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1185), .CK(clk), .RN(
n5163), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n5062) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1943), .CK(clk), .RN(
n5168), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n5061) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1535), .CK(
clk), .RN(n5226), .Q(FPMULT_Sgf_normalized_result[18]), .QN(n5058) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n2268),
.Q(FPADDSUB_DMP_SFG[19]), .QN(n5056) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1928), .CK(clk), .RN(
n5179), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n5055) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1922), .CK(clk), .RN(
n5174), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n5054) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1930), .CK(clk), .RN(
n5187), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n5053) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1926), .CK(clk), .RN(
n5171), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n5052) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1932), .CK(clk), .RN(
n5182), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n5051) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1934), .CK(clk), .RN(
n5169), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n5050) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1942), .CK(clk), .RN(
n5168), .Q(FPADDSUB_intDX_EWSW[1]), .QN(n5049) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1916), .CK(clk), .RN(
n5163), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n5048) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1187), .CK(clk), .RN(
n5189), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n5047) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1924), .CK(clk), .RN(
n5169), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n5044) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1941), .CK(clk), .RN(
n5168), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n5043) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1935), .CK(clk), .RN(
n5184), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n5042) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1472), .CK(clk), .RN(
n5163), .Q(result_add_subt[26]), .QN(n5041) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1474), .CK(clk), .RN(
n5187), .Q(result_add_subt[24]), .QN(n5040) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1471), .CK(clk), .RN(
n5162), .Q(result_add_subt[27]), .QN(n5039) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1470), .CK(clk), .RN(
n5171), .Q(result_add_subt[28]), .QN(n5038) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1280), .CK(clk), .RN(
n5176), .Q(result_add_subt[5]), .QN(n5037) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1287), .CK(clk), .RN(
n2267), .Q(result_add_subt[9]), .QN(n5036) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1294), .CK(clk), .RN(
n5177), .Q(result_add_subt[1]), .QN(n5035) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1301), .CK(clk), .RN(
n5175), .Q(result_add_subt[0]), .QN(n5034) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1308), .CK(clk), .RN(
n5178), .Q(result_add_subt[7]), .QN(n5033) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1315), .CK(clk), .RN(
n5164), .Q(result_add_subt[2]), .QN(n5032) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1331), .CK(clk), .RN(
n5176), .Q(result_add_subt[3]), .QN(n5031) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1365), .CK(clk), .RN(
n5174), .Q(result_add_subt[12]), .QN(n5030) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1368), .CK(clk), .RN(
n5173), .Q(result_add_subt[10]), .QN(n5029) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1371), .CK(clk), .RN(
n5171), .Q(result_add_subt[14]), .QN(n5028) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1374), .CK(clk), .RN(
n5174), .Q(result_add_subt[11]), .QN(n5027) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1377), .CK(clk), .RN(
n2268), .Q(result_add_subt[8]), .QN(n5026) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1380), .CK(clk), .RN(
n2586), .Q(result_add_subt[16]), .QN(n5025) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1383), .CK(clk), .RN(
n5174), .Q(result_add_subt[13]), .QN(n5024) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(
n5176), .Q(result_add_subt[6]), .QN(n5023) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1389), .CK(clk), .RN(
n5174), .Q(result_add_subt[4]), .QN(n5022) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1392), .CK(clk), .RN(
n2376), .Q(result_add_subt[17]), .QN(n5021) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1395), .CK(clk), .RN(
n5163), .Q(result_add_subt[20]), .QN(n5020) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1398), .CK(clk), .RN(
n5173), .Q(result_add_subt[19]), .QN(n5019) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1401), .CK(clk), .RN(
n5188), .Q(result_add_subt[21]), .QN(n5018) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1404), .CK(clk), .RN(
n5169), .Q(result_add_subt[18]), .QN(n5017) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1407), .CK(clk), .RN(
n5173), .Q(result_add_subt[15]), .QN(n5016) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1410), .CK(clk), .RN(
n5172), .Q(result_add_subt[22]), .QN(n5015) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2079), .CK(clk), .RN(
n5167), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n5014) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2081), .CK(clk), .RN(
n5167), .Q(FPADDSUB_bit_shift_SHT2), .QN(n5012) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n5186),
.Q(FPADDSUB_DMP_SFG[17]), .QN(n5011) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1189), .CK(clk), .RN(
n5187), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n5010) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1533), .CK(
clk), .RN(n5223), .Q(FPMULT_Sgf_normalized_result[16]), .QN(n5008) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1337), .CK(clk), .RN(
n5177), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n5006) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1191), .CK(clk), .RN(
n5165), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n5005) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n5186),
.Q(FPADDSUB_DMP_SFG[15]), .QN(n5004) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1551), .CK(clk), .RN(n5229), .Q(
FPMULT_FSM_selector_B[0]), .QN(n5003) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1816), .CK(clk), .RN(
n5187), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n5002) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1531), .CK(
clk), .RN(n5233), .Q(FPMULT_Sgf_normalized_result[14]), .QN(n4999) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n5209), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .QN(n4998) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1322), .CK(clk), .RN(
n5178), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n4996) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1333), .CK(clk), .RN(
n5179), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n4995) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1193), .CK(clk), .RN(
n5188), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n4985) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n5182),
.Q(FPADDSUB_DMP_SFG[13]), .QN(n4984) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1529), .CK(
clk), .RN(n5227), .Q(FPMULT_Sgf_normalized_result[12]), .QN(n4981) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2193), .CK(
clk), .RN(n5163), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n4980) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1195), .CK(clk), .RN(
n5185), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n4976) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n5184),
.Q(FPADDSUB_DMP_SFG[11]), .QN(n4975) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n5164),
.Q(FPADDSUB_DMP_SFG[9]), .QN(n4972) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1527), .CK(
clk), .RN(n5222), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n4968) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1197), .CK(clk), .RN(
n5166), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n4967) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1198), .CK(clk), .RN(
n5181), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n4966) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1525), .CK(
clk), .RN(n2386), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n4964) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1523), .CK(
clk), .RN(n5225), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n4961) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1199), .CK(clk), .RN(
n5183), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n4960) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1200), .CK(clk), .RN(
n5182), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n4959) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1521), .CK(
clk), .RN(n5229), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n4956) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1336), .CK(clk), .RN(
n5175), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n4955) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1201), .CK(clk), .RN(
n5186), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n4954) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1202), .CK(clk), .RN(
n5184), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n4953) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1681), .CK(clk),
.RN(n5230), .Q(FPMULT_Op_MX[22]), .QN(n4945) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n1659), .CK(clk),
.RN(n5228), .Q(FPMULT_Op_MX[0]), .QN(n4941) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1203), .CK(clk), .RN(
n2268), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n4940) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n5178),
.Q(FPADDSUB_DMP_SFG[0]), .QN(n4938) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1417), .CK(clk), .RN(n5174),
.Q(FPADDSUB_DmP_EXP_EWSW[25]), .QN(n4937) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1464), .CK(clk), .RN(n5166),
.Q(FPADDSUB_DMP_EXP_EWSW[26]), .QN(n4936) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1416), .CK(clk), .RN(n2586),
.Q(FPADDSUB_DmP_EXP_EWSW[26]), .QN(n4934) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1541), .CK(clk), .RN(
n5229), .Q(FPMULT_exp_oper_result[8]), .QN(n4933) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1338), .CK(clk), .RN(
n5164), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]), .QN(n4931) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1341), .CK(clk), .RN(
n5179), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n4930) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1465), .CK(clk), .RN(n5182),
.Q(FPADDSUB_DMP_EXP_EWSW[25]), .QN(n4929) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2136), .CK(clk), .RN(n2266),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n4928) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1813), .CK(clk), .RN(n5168), .Q(FPADDSUB_Data_array_SWR[21]), .QN(n4927) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1814), .CK(clk), .RN(n5167), .Q(FPADDSUB_Data_array_SWR[22]), .QN(n4926) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1914), .CK(clk), .RN(
n2586), .Q(FPADDSUB_intDX_EWSW[29]), .QN(n4924) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1921), .CK(clk), .RN(
n2267), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n4923) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1925), .CK(clk), .RN(
n5178), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n4922) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1929), .CK(clk), .RN(
n5182), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n4921) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1931), .CK(clk), .RN(
n5167), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n4920) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1940), .CK(clk), .RN(
n5167), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n4917) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1923), .CK(clk), .RN(
n5182), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n4916) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1863), .CK(clk), .RN(
n5194), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n4914) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1358), .CK(clk), .RN(
n5177), .Q(result_add_subt[31]), .QN(n4913) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1344), .CK(clk), .RN(
n5173), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n4911) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n5208), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .QN(n4909) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1339), .CK(clk), .RN(
n2267), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n4908) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1815), .CK(clk), .RN(
n5180), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n4907) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1321), .CK(clk), .RN(
n5175), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n4906) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1350), .CK(clk), .RN(
n5184), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n4904) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n5195), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n4903) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1346), .CK(clk), .RN(
n5173), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n4902) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1194), .CK(clk), .RN(
n5183), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n4898) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1196), .CK(clk), .RN(
n5170), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n4896) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1342), .CK(clk), .RN(
n5173), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n4895) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n5179),
.Q(FPADDSUB_DMP_SFG[7]), .QN(n4893) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n5180),
.Q(FPADDSUB_DMP_SFG[5]), .QN(n4891) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1334), .CK(clk), .RN(
n5178), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n4890) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n1661), .CK(clk),
.RN(n5230), .Q(FPMULT_Op_MX[2]), .QN(n4970) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1636), .CK(clk),
.RN(n5223), .Q(FPMULT_Op_MY[9]), .QN(n4971) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n1642), .CK(clk),
.RN(n5229), .Q(FPMULT_Op_MY[15]), .QN(n5009) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1648), .CK(clk),
.RN(n5222), .Q(FPMULT_Op_MY[21]), .QN(n5075) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n5176),
.Q(FPADDSUB_DMP_SFG[3]), .QN(n4883) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2149), .CK(clk), .RN(
n5189), .Q(n2229), .QN(n5083) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2082), .CK(clk), .RN(n5191),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n4881) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1466), .CK(clk), .RN(n5186),
.Q(FPADDSUB_DMP_EXP_EWSW[24]), .QN(n4880) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1418), .CK(clk), .RN(n5188),
.Q(FPADDSUB_DmP_EXP_EWSW[24]), .QN(n4879) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1340), .CK(clk), .RN(
n5180), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n4878) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1918), .CK(clk), .RN(
n5172), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n4877) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1917), .CK(clk), .RN(
n5162), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n4876) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1345), .CK(clk), .RN(
n5168), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n4874) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1343), .CK(clk), .RN(
n5172), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n4871) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1919), .CK(clk), .RN(
n5187), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n4867) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n5196), .Q(NaN_flag)
);
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1318), .CK(clk), .RN(
n5177), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]), .QN(n4882) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1207), .CK(clk), .RN(
n5166), .QN(n4868) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1205), .CK(clk), .RN(
n5186), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2150), .CK(clk), .RN(
n5162), .Q(n5156), .QN(n5244) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1663), .CK(clk),
.RN(n2386), .Q(FPMULT_Op_MX[4]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n2586),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n4870) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1691), .CK(clk), .RN(n5229), .Q(
FPMULT_FSM_selector_A), .QN(n5081) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1348), .CK(clk), .RN(
n2378), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n4873) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1550), .CK(clk), .RN(n5233), .Q(
FPMULT_FSM_selector_B[1]), .QN(n5007) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2142), .CK(clk), .RN(n5212),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n4994) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2140), .CK(clk), .RN(n5206),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n4894) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2139), .CK(clk), .RN(n5210),
.Q(FPSENCOS_cont_var_out[0]), .QN(n5077) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1184), .CK(clk), .RN(
n5187), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n4925) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1186), .CK(clk), .RN(
n5162), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n4915) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1188), .CK(clk), .RN(
n2377), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n4912) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1694), .CK(clk), .RN(n5198),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n4989) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1695), .CK(clk), .RN(n5204),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n4901) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1692), .CK(clk), .RN(n5198),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n4872) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1842), .CK(clk), .RN(
n5167), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n4986) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1844), .CK(clk), .RN(
n5168), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n4979) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1915), .CK(clk), .RN(
n5165), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n5067) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1823), .CK(clk), .RN(
n5175), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n4987) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1825), .CK(clk), .RN(
n5164), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n4988) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1821), .CK(clk), .RN(
n5172), .Q(FPADDSUB_intDY_EWSW[24]), .QN(n4935) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1822), .CK(clk), .RN(
n5189), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n4900) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1824), .CK(clk), .RN(
n5177), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n4997) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1826), .CK(clk), .RN(
n2376), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n4905) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1827), .CK(clk), .RN(
n5164), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n5000) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1831), .CK(clk), .RN(
n5183), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n4977) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1832), .CK(clk), .RN(
n5165), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n4990) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1834), .CK(clk), .RN(
n5170), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n4992) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1838), .CK(clk), .RN(
n5168), .Q(FPADDSUB_intDY_EWSW[7]), .QN(n5057) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1828), .CK(clk), .RN(
n5184), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n4993) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1830), .CK(clk), .RN(
n5176), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n4897) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1927), .CK(clk), .RN(
n5172), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n5046) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1833), .CK(clk), .RN(
n5166), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n4978) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1837), .CK(clk), .RN(
n5189), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n4991) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1933), .CK(clk), .RN(
n5170), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n5045) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1936), .CK(clk), .RN(
n5168), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n5069) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1938), .CK(clk), .RN(
n5169), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n5060) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1937), .CK(clk), .RN(
n5187), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n4918) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1939), .CK(clk), .RN(
n5163), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n4919) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1920), .CK(clk), .RN(
n5188), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n5013) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1335), .CK(clk), .RN(
n5175), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n4869) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n5194), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .QN(n5001) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2143), .CK(clk), .RN(n2379),
.Q(n5157), .QN(n2206) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1840), .CK(clk), .RN(
n5169), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2138), .CK(clk), .RN(n5202),
.Q(FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1839), .CK(clk), .RN(
n2376), .Q(FPADDSUB_intDY_EWSW[6]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1835), .CK(clk), .RN(
n5186), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1829), .CK(clk), .RN(
n5188), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1843), .CK(clk), .RN(
n5168), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1818), .CK(clk), .RN(
n5187), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1517), .CK(
clk), .RN(n5222), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1667), .CK(clk),
.RN(n5222), .Q(FPMULT_Op_MX[8]), .QN(n4948) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n1673), .CK(clk),
.RN(n5227), .Q(FPMULT_Op_MX[14]), .QN(n4887) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1183), .CK(clk), .RN(
n5188), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1845), .CK(clk), .RN(
n5168), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2078), .CK(clk), .RN(
n5167), .Q(FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1323), .CK(clk), .RN(
n5177), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n5170),
.Q(FPADDSUB_DMP_SFG[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n5183),
.Q(FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n5183),
.Q(FPADDSUB_DMP_SFG[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n5181),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n5182),
.Q(FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n5184),
.Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n2268),
.Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n5185),
.Q(FPADDSUB_DMP_SFG[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n5164),
.Q(FPADDSUB_DMP_SFG[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n5176),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1676), .CK(clk),
.RN(n5228), .Q(FPMULT_Op_MX[17]), .QN(n4942) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1806), .CK(clk), .RN(n5169), .Q(FPADDSUB_Data_array_SWR[14]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1805), .CK(clk), .RN(n5162), .Q(FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1807), .CK(clk), .RN(n5168), .Q(FPADDSUB_Data_array_SWR[15]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1808), .CK(clk), .RN(n5163), .Q(FPADDSUB_Data_array_SWR[16]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1802), .CK(clk), .RN(n5181), .Q(FPADDSUB_Data_array_SWR[11]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1801), .CK(clk), .RN(n5166), .Q(FPADDSUB_Data_array_SWR[10]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1349), .CK(clk), .RN(
n5185), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1957), .CK(clk), .RN(
n2264), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1469), .CK(clk), .RN(
n5165), .Q(result_add_subt[29]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1473), .CK(clk), .RN(
n5172), .Q(result_add_subt[25]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1475), .CK(clk), .RN(
n5189), .Q(result_add_subt[23]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1468), .CK(clk), .RN(
n5163), .Q(result_add_subt[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n1671), .CK(clk),
.RN(n5233), .Q(FPMULT_Op_MX[12]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1630), .CK(clk),
.RN(n5222), .Q(FPMULT_Op_MY[3]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1637), .CK(clk),
.RN(n5233), .Q(FPMULT_Op_MY[10]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1638), .CK(clk),
.RN(n5227), .Q(FPMULT_Op_MY[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1520), .CK(
clk), .RN(n5223), .Q(FPMULT_Sgf_normalized_result[3]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1522), .CK(
clk), .RN(n5226), .Q(FPMULT_Sgf_normalized_result[5]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1526), .CK(
clk), .RN(n2386), .Q(FPMULT_Sgf_normalized_result[9]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1528), .CK(
clk), .RN(n5224), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1530), .CK(
clk), .RN(n5225), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1532), .CK(
clk), .RN(n5227), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n2374), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1647), .CK(clk),
.RN(n5233), .Q(FPMULT_Op_MY[20]) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1540), .CK(clk), .RN(
n5222), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1955), .CK(clk), .RN(
n5215), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1536), .CK(
clk), .RN(n5233), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n1660), .CK(clk),
.RN(n5232), .Q(FPMULT_Op_MX[1]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1317), .CK(clk), .RN(
n2267), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]), .QN(n4944) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1961), .CK(clk), .RN(
n5198), .Q(FPSENCOS_d_ff2_X[23]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1524), .CK(
clk), .RN(n5229), .Q(FPMULT_Sgf_normalized_result[7]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1534), .CK(
clk), .RN(n5223), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1538), .CK(
clk), .RN(n5226), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1912), .CK(clk), .RN(
n5167), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n5180),
.Q(FPADDSUB_DMP_SFG[1]), .QN(n2208) );
DFFRX2TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1353), .CK(clk), .RN(n5167),
.Q(FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1958), .CK(clk), .RN(
n5214), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1959), .CK(clk), .RN(
n5216), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1960), .CK(clk), .RN(
n5221), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1796), .CK(clk), .RN(n5163),
.Q(FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1795), .CK(clk), .RN(n5185),
.Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1419), .CK(clk), .RN(n5165),
.Q(FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1686), .CK(clk),
.RN(n2386), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1954), .CK(clk), .RN(
n5217), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2151), .CK(
clk), .RN(n5172), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n4899) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1735), .CK(clk), .RN(
n5220), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n5212),
.Q(operation_reg[0]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1617), .CK(clk), .RN(
n5227), .Q(FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1621), .CK(clk), .RN(
n2386), .Q(FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1619), .CK(clk), .RN(
n5233), .Q(FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1542), .CK(clk), .RN(
n5224), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1543), .CK(clk), .RN(
n5227), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1544), .CK(clk), .RN(
n5233), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n5203),
.Q(operation_reg[1]) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1600), .CK(clk),
.RN(n5230), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n2382), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n2381), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n5206), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n5205), .Q(
FPSENCOS_d_ff_Xn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n5213), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n5192), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n5192), .Q(
FPSENCOS_d_ff_Xn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n5213), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n2265), .Q(
FPSENCOS_d_ff_Xn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n5209), .Q(
FPSENCOS_d_ff_Xn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n5207), .Q(
FPSENCOS_d_ff_Xn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n5197), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n5203), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n5203), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n5217), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_47_ ( .D(n1552), .CK(clk), .RN(
n5220), .Q(FPMULT_P_Sgf[47]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n5210), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n2379), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n2374), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n5212), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n5213), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n5190), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n5199), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2015), .CK(clk), .RN(n5204), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2012), .CK(clk), .RN(n5214), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2009), .CK(clk), .RN(n5218), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1772), .CK(clk), .RN(n5218), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1775), .CK(clk), .RN(n5215), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1778), .CK(clk), .RN(n5199), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1784), .CK(clk), .RN(n2265), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1546), .CK(clk), .RN(
n5223), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1547), .CK(clk), .RN(
n5226), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1548), .CK(clk), .RN(
n5224), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1549), .CK(clk), .RN(
n5225), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2018), .CK(clk), .RN(n5205), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1631), .CK(clk),
.RN(n5226), .Q(FPMULT_Op_MY[4]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1641), .CK(clk),
.RN(n5227), .Q(FPMULT_Op_MY[14]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1643), .CK(clk),
.RN(n5223), .Q(FPMULT_Op_MY[16]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1688), .CK(clk),
.RN(n5222), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1689), .CK(clk),
.RN(n5229), .Q(FPMULT_Op_MX[30]) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1626), .CK(
clk), .RN(n5227), .Q(FPMULT_zero_flag), .QN(n5132) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1649), .CK(clk),
.RN(n5226), .Q(FPMULT_Op_MY[22]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_5_ ( .D(n1558), .CK(clk), .RN(
n2264), .Q(FPMULT_P_Sgf[5]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1730), .CK(clk), .RN(
n5167), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1420), .CK(clk), .RN(
n5163), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1425), .CK(clk), .RN(
n5187), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1430), .CK(clk), .RN(
n2376), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1435), .CK(clk), .RN(
n5162), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1440), .CK(clk), .RN(
n5188), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1445), .CK(clk), .RN(
n5165), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1450), .CK(clk), .RN(
n5172), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1455), .CK(clk), .RN(
n5189), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_14_ ( .D(n1567), .CK(clk), .RN(
n5191), .Q(FPMULT_P_Sgf[14]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_18_ ( .D(n1571), .CK(clk), .RN(
n5194), .Q(FPMULT_P_Sgf[18]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1665), .CK(clk),
.RN(n5226), .Q(FPMULT_Op_MX[6]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1666), .CK(clk),
.RN(n5233), .Q(FPMULT_Op_MX[7]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n1674), .CK(clk),
.RN(n5229), .Q(FPMULT_Op_MX[15]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1675), .CK(clk),
.RN(n5223), .Q(FPMULT_Op_MX[16]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n5202),
.Q(cordic_result[31]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_23_ ( .D(n1576), .CK(clk), .RN(
n5201), .Q(FPMULT_P_Sgf[23]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n5212), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n5213), .Q(
dataA[29]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_46_ ( .D(n1599), .CK(clk), .RN(
n5212), .Q(FPMULT_P_Sgf[46]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1792), .CK(clk), .RN(n5174),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1791), .CK(clk), .RN(n5179),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1790), .CK(clk), .RN(n5178),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRX1TS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1855), .CK(clk), .RN(n5206),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2117), .CK(clk), .RN(n5210), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2118), .CK(clk), .RN(n5196), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2125), .CK(clk), .RN(n5195), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2131), .CK(clk), .RN(n5209), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n5207), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1789), .CK(clk), .RN(n5169),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2116), .CK(clk), .RN(n5195), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2133), .CK(clk), .RN(n2266), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n5208), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n1640), .CK(clk),
.RN(n5224), .Q(FPMULT_Op_MY[13]), .QN(n4885) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1634), .CK(clk),
.RN(n5225), .Q(FPMULT_Op_MY[7]), .QN(n4886) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n1639), .CK(clk),
.RN(n5222), .Q(FPMULT_Op_MY[12]), .QN(n4888) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1679), .CK(clk),
.RN(n2386), .Q(FPMULT_Op_MX[20]), .QN(n4884) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1670), .CK(clk),
.RN(n5226), .Q(FPMULT_Op_MX[11]), .QN(n4943) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1664), .CK(clk),
.RN(n2375), .Q(FPMULT_Op_MX[5]), .QN(n4949) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1841), .CK(clk), .RN(
n5173), .Q(FPADDSUB_intDY_EWSW[4]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1836), .CK(clk), .RN(
n5169), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1817), .CK(clk), .RN(
n5163), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1803), .CK(clk), .RN(n5165), .Q(FPADDSUB_Data_array_SWR[12]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1668), .CK(clk),
.RN(n5222), .Q(FPMULT_Op_MX[9]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1635), .CK(clk),
.RN(n5224), .Q(FPMULT_Op_MY[8]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1629), .CK(clk),
.RN(n5225), .Q(FPMULT_Op_MY[2]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1628), .CK(clk),
.RN(n2375), .Q(FPMULT_Op_MY[1]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1799), .CK(clk), .RN(n5169), .Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1797), .CK(clk), .RN(n5169),
.Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1646), .CK(clk),
.RN(n5224), .Q(FPMULT_Op_MY[19]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1644), .CK(clk),
.RN(n5225), .Q(FPMULT_Op_MY[17]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1632), .CK(clk),
.RN(n2375), .Q(FPMULT_Op_MY[5]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n1672), .CK(clk),
.RN(n5224), .Q(FPMULT_Op_MX[13]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1678), .CK(clk),
.RN(n5230), .Q(FPMULT_Op_MX[19]) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2148), .CK(clk), .RN(
n5162), .Q(n5245), .QN(n5237) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_33_ ( .D(n1586), .CK(clk), .RN(
n2374), .Q(FPMULT_P_Sgf[33]) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n5235), .CK(clk), .RN(n5189), .Q(
ready_add_subt), .QN(n4932) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1192), .CK(clk), .RN(
n5162), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n2217) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1656), .CK(clk),
.RN(n5228), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1650), .CK(clk),
.RN(n2375), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1653), .CK(clk),
.RN(n5232), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1651), .CK(clk),
.RN(n5223), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1687), .CK(clk),
.RN(n5228), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1683), .CK(clk),
.RN(n5232), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1977), .CK(clk), .RN(
n5216), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1995), .CK(clk), .RN(
n5208), .Q(FPSENCOS_d_ff2_X[6]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1794), .CK(clk), .RN(n2267),
.Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2141), .CK(clk), .RN(n2266),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n2308) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n5207), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n5234), .CK(clk),
.RN(n5209), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1190), .CK(clk), .RN(
n5172), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n4910) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2147), .CK(clk), .RN(
n5168), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1669), .CK(clk),
.RN(n5223), .Q(FPMULT_Op_MX[10]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_2_ ( .D(n1555), .CK(clk), .RN(
n5221), .Q(FPMULT_P_Sgf[2]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_21_ ( .D(n1574), .CK(clk), .RN(
n2265), .Q(FPMULT_P_Sgf[21]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_20_ ( .D(n1573), .CK(clk), .RN(
n5217), .Q(FPMULT_P_Sgf[20]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_19_ ( .D(n1572), .CK(clk), .RN(
n5194), .Q(FPMULT_P_Sgf[19]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_17_ ( .D(n1570), .CK(clk), .RN(
n5191), .Q(FPMULT_P_Sgf[17]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_16_ ( .D(n1569), .CK(clk), .RN(
n5220), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_15_ ( .D(n1568), .CK(clk), .RN(
n5221), .Q(FPMULT_P_Sgf[15]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_45_ ( .D(n1598), .CK(clk), .RN(
n5200), .Q(FPMULT_P_Sgf[45]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_8_ ( .D(n1561), .CK(clk), .RN(
n5200), .Q(FPMULT_P_Sgf[8]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1965), .CK(clk), .RN(
n5218), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n5217), .Q(
FPSENCOS_d_ff_Xn[26]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1737), .CK(clk), .RN(
n5199), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1769), .CK(clk), .RN(n5216), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff_Xn[29]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_42_ ( .D(n1595), .CK(clk), .RN(
n5201), .Q(FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_41_ ( .D(n1594), .CK(clk), .RN(
n5201), .Q(FPMULT_P_Sgf[41]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_40_ ( .D(n1593), .CK(clk), .RN(
n5201), .Q(FPMULT_P_Sgf[40]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_39_ ( .D(n1592), .CK(clk), .RN(
n5201), .Q(FPMULT_P_Sgf[39]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_38_ ( .D(n1591), .CK(clk), .RN(
n5201), .Q(FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_37_ ( .D(n1590), .CK(clk), .RN(
n5201), .Q(FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_36_ ( .D(n1589), .CK(clk), .RN(
n5201), .Q(FPMULT_P_Sgf[36]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_35_ ( .D(n1588), .CK(clk), .RN(
n5201), .Q(FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_34_ ( .D(n1587), .CK(clk), .RN(
n5201), .Q(FPMULT_P_Sgf[34]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1987), .CK(clk), .RN(
n5192), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2045), .CK(clk), .RN(n5192), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_7_ ( .D(n1560), .CK(clk), .RN(
n5218), .Q(FPMULT_P_Sgf[7]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1347), .CK(clk), .RN(
n5174), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n4875) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2146), .CK(clk), .RN(
n5188), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n5098) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_6_ ( .D(n1559), .CK(clk), .RN(
n5217), .Q(FPMULT_P_Sgf[6]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_4_ ( .D(n1557), .CK(clk), .RN(
n5218), .Q(FPMULT_P_Sgf[4]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1680), .CK(clk),
.RN(n5232), .QN(n2202) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_3_ ( .D(n1556), .CK(clk), .RN(
n5217), .Q(FPMULT_P_Sgf[3]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1733), .CK(clk), .RN(
n5167), .Q(FPADDSUB_intAS) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_10_ ( .D(n1563), .CK(clk), .RN(
n5219), .Q(FPMULT_P_Sgf[10]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_12_ ( .D(n1565), .CK(clk), .RN(
n5214), .Q(FPMULT_P_Sgf[12]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n2374), .Q(
dataA[30]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_11_ ( .D(n1564), .CK(clk), .RN(
n5216), .Q(FPMULT_P_Sgf[11]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2119), .CK(clk), .RN(n5206), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2130), .CK(clk), .RN(n5209), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1415), .CK(clk), .RN(n5173),
.Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_13_ ( .D(n1566), .CK(clk), .RN(
n5215), .Q(FPMULT_P_Sgf[13]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n5212), .Q(
dataA[28]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n2374), .Q(
dataA[23]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n5212), .Q(
dataB[24]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n5208), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2128), .CK(clk), .RN(n5210), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRX1TS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n5213), .Q(
dataA[24]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1412), .CK(clk), .RN(
n5175), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n2204) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1793), .CK(clk), .RN(n5169),
.Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n5203),
.Q(cordic_result[15]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1710), .CK(clk), .RN(n5205),
.Q(cordic_result[18]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1711), .CK(clk), .RN(n5205),
.Q(cordic_result[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1722), .CK(clk), .RN(n2380),
.Q(cordic_result[6]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n5205),
.Q(cordic_result[13]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1712), .CK(clk), .RN(n5196),
.Q(cordic_result[16]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1720), .CK(clk), .RN(n5204),
.Q(cordic_result[8]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1717), .CK(clk), .RN(n5203),
.Q(cordic_result[11]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1714), .CK(clk), .RN(n5205),
.Q(cordic_result[14]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n5196),
.Q(cordic_result[10]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1716), .CK(clk), .RN(n2382),
.Q(cordic_result[12]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1719), .CK(clk), .RN(n2379),
.Q(cordic_result[9]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1721), .CK(clk), .RN(n5207),
.Q(cordic_result[7]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1682), .CK(clk),
.RN(n5228), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1618), .CK(clk), .RN(
n5226), .Q(FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1616), .CK(clk), .RN(
n5224), .Q(FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1623), .CK(clk), .RN(
n5230), .Q(FPMULT_Add_result[1]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1463), .CK(clk), .RN(n5182),
.Q(FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1657), .CK(clk),
.RN(n5228), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1620), .CK(clk), .RN(
n5228), .Q(FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_43_ ( .D(n1596), .CK(clk), .RN(
n5197), .Q(FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_44_ ( .D(n1597), .CK(clk), .RN(
n2380), .Q(FPMULT_P_Sgf[44]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1654), .CK(clk),
.RN(n2386), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1652), .CK(clk),
.RN(n5223), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1655), .CK(clk),
.RN(n5230), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1967), .CK(clk), .RN(
n2379), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1997), .CK(clk), .RN(
n5202), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1993), .CK(clk), .RN(
n5195), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n2001), .CK(clk), .RN(
n5204), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1979), .CK(clk), .RN(
n5193), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1975), .CK(clk), .RN(
n5221), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1981), .CK(clk), .RN(
n5207), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1973), .CK(clk), .RN(
n5197), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1969), .CK(clk), .RN(
n2381), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1985), .CK(clk), .RN(
n5193), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1971), .CK(clk), .RN(
n5217), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1963), .CK(clk), .RN(
n5218), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1983), .CK(clk), .RN(
n5221), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2003), .CK(clk), .RN(
n5202), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2005), .CK(clk), .RN(
n2382), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1991), .CK(clk), .RN(
n2381), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2007), .CK(clk), .RN(
n2266), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1999), .CK(clk), .RN(
n5190), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1545), .CK(clk), .RN(
n5225), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n2379), .Q(
FPSENCOS_d_ff_Xn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n5218), .Q(
FPSENCOS_d_ff_Xn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1615), .CK(clk), .RN(
n5225), .Q(FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1604), .CK(clk),
.RN(n5228), .Q(FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1606), .CK(clk),
.RN(n2386), .Q(FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1608), .CK(clk),
.RN(n5226), .Q(FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1610), .CK(clk),
.RN(n5233), .Q(FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1612), .CK(clk),
.RN(n5222), .Q(FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1614), .CK(clk),
.RN(n5222), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1787), .CK(clk), .RN(n5191), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1781), .CK(clk), .RN(n5218), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1732), .CK(clk), .RN(n2264), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2042), .CK(clk), .RN(n2382), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2039), .CK(clk), .RN(n5192), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2030), .CK(clk), .RN(n5216), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2021), .CK(clk), .RN(n2264), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2024), .CK(clk), .RN(n5203), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2063), .CK(clk), .RN(n5197), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2057), .CK(clk), .RN(n5190), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2036), .CK(clk), .RN(n2266), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2027), .CK(clk), .RN(n5194), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2051), .CK(clk), .RN(n2379), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2033), .CK(clk), .RN(n5193), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2066), .CK(clk), .RN(n5211), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2069), .CK(clk), .RN(n5211), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2054), .CK(clk), .RN(n5208), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2075), .CK(clk), .RN(n5210), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2072), .CK(clk), .RN(n5202), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2048), .CK(clk), .RN(n5203), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2060), .CK(clk), .RN(n5196), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n5221), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1731), .CK(clk), .RN(n5218), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n2264), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1603), .CK(clk),
.RN(n5232), .Q(FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1605), .CK(clk),
.RN(n5230), .Q(FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1607), .CK(clk),
.RN(n5232), .Q(FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1609), .CK(clk),
.RN(n5223), .Q(FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1611), .CK(clk),
.RN(n5227), .Q(FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1613), .CK(clk),
.RN(n5229), .Q(FPMULT_Add_result[11]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1734), .CK(clk), .RN(n5215), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_32_ ( .D(n1585), .CK(clk), .RN(
n5200), .Q(FPMULT_P_Sgf[32]), .QN(n2231) );
DFFSX1TS R_1 ( .D(n5155), .CK(clk), .SN(n5211), .Q(n5242) );
DFFSX1TS R_2 ( .D(n5154), .CK(clk), .SN(n5190), .Q(n5243) );
DFFSX1TS R_11 ( .D(n5151), .CK(clk), .SN(n5193), .Q(n5241) );
DFFRX1TS R_12 ( .D(n5150), .CK(clk), .RN(n5211), .Q(n5240) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1690), .CK(clk), .RN(n5227), .Q(
FPMULT_FSM_selector_C), .QN(n5059) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1204), .CK(clk), .RN(
n5181), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n4939) );
DFFSX1TS R_4 ( .D(n5152), .CK(clk), .SN(n5211), .Q(n5239) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1206), .CK(clk), .RN(
n5181), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n2200) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_9_ ( .D(n1562), .CK(clk), .RN(
n5200), .Q(FPMULT_P_Sgf[9]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1627), .CK(clk),
.RN(n5225), .Q(FPMULT_Op_MY[0]), .QN(n4957) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1645), .CK(clk),
.RN(n5227), .Q(FPMULT_Op_MY[18]), .QN(n4892) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1633), .CK(clk),
.RN(n5229), .Q(FPMULT_Op_MY[6]), .QN(n4889) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1352), .CK(clk), .RN(
n5188), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n2198) );
DFFRX4TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1693), .CK(clk), .RN(n5207),
.Q(FPMULT_FS_Module_state_reg[1]) );
CMPR32X2TS DP_OP_26J216_122_5882_U8 ( .A(DP_OP_26J216_122_5882_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J216_122_5882_n8), .CO(
DP_OP_26J216_122_5882_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J216_122_5882_U7 ( .A(DP_OP_26J216_122_5882_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J216_122_5882_n7), .CO(
DP_OP_26J216_122_5882_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2145), .CK(clk), .RN(
n5167), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n2197) );
CMPR32X2TS DP_OP_26J216_122_5882_U6 ( .A(DP_OP_26J216_122_5882_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J216_122_5882_n6), .CO(
DP_OP_26J216_122_5882_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J216_122_5882_U5 ( .A(DP_OP_26J216_122_5882_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J216_122_5882_n5), .CO(
DP_OP_26J216_122_5882_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J216_122_5882_U4 ( .A(n2198), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J216_122_5882_n4), .CO(
DP_OP_26J216_122_5882_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2080), .CK(clk), .RN(
n5167), .Q(FPADDSUB_left_right_SHT2), .QN(n2207) );
CMPR32X2TS DP_OP_26J216_122_5882_U3 ( .A(n2198), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J216_122_5882_n3), .CO(
DP_OP_26J216_122_5882_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS intadd_490_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n4994), .C(
intadd_490_CI), .CO(intadd_490_n3), .S(intadd_490_SUM_0_) );
CMPR32X2TS DP_OP_26J216_122_5882_U2 ( .A(n2198), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J216_122_5882_n2), .CO(
DP_OP_26J216_122_5882_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2144), .CK(clk), .RN(
n5187), .Q(FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n5090) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2077), .CK(clk), .RN(
n5167), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2196) );
CMPR32X2TS intadd_490_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n4260), .C(
intadd_490_n3), .CO(intadd_490_n2), .S(intadd_490_SUM_1_) );
CMPR32X2TS intadd_489_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n4894), .C(
intadd_489_n2), .CO(intadd_489_n1), .S(intadd_489_SUM_2_) );
CMPR32X2TS intadd_490_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n4894), .C(
intadd_490_n2), .CO(intadd_490_n1), .S(intadd_490_SUM_2_) );
NAND2X4TS U2219 ( .A(n4529), .B(n4528), .Y(n4530) );
AOI222X1TS U2220 ( .A0(n2823), .A1(cordic_result[23]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[23]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[23]), .Y(n2857) );
AOI222X1TS U2221 ( .A0(n2885), .A1(cordic_result[4]), .B0(n2825), .B1(
FPSENCOS_d_ff_Yn[4]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[4]), .Y(n2828)
);
AOI222X1TS U2222 ( .A0(n2885), .A1(cordic_result[3]), .B0(n2825), .B1(
FPSENCOS_d_ff_Yn[3]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[3]), .Y(n2829)
);
AOI222X1TS U2223 ( .A0(n2885), .A1(cordic_result[5]), .B0(n2825), .B1(
FPSENCOS_d_ff_Yn[5]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[5]), .Y(n2827)
);
AOI222X1TS U2224 ( .A0(n2866), .A1(cordic_result[24]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[24]), .C0(n2855), .C1(FPSENCOS_d_ff_Xn[24]), .Y(n2856) );
AOI222X1TS U2225 ( .A0(n2885), .A1(cordic_result[1]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[1]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[1]), .Y(n2861)
);
AOI222X1TS U2226 ( .A0(n2866), .A1(cordic_result[25]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[25]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[25]), .Y(n2858) );
AOI222X1TS U2227 ( .A0(n2866), .A1(cordic_result[29]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[29]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[29]), .Y(n2859) );
AOI222X1TS U2228 ( .A0(n2866), .A1(cordic_result[30]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[30]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[30]), .Y(n2864) );
AOI222X1TS U2229 ( .A0(n2866), .A1(cordic_result[26]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[26]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[26]), .Y(n2854) );
AOI222X1TS U2230 ( .A0(n2866), .A1(cordic_result[27]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[27]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[27]), .Y(n2862) );
AOI222X1TS U2231 ( .A0(n2866), .A1(cordic_result[22]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[22]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[22]), .Y(n2867) );
AOI222X1TS U2232 ( .A0(n2866), .A1(cordic_result[21]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[21]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[21]), .Y(n2853) );
AOI222X1TS U2233 ( .A0(n2866), .A1(cordic_result[28]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[28]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[28]), .Y(n2863) );
AOI222X1TS U2234 ( .A0(n2866), .A1(cordic_result[19]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[19]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[19]), .Y(n2852) );
AOI222X1TS U2235 ( .A0(n2866), .A1(cordic_result[20]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[20]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[20]), .Y(n2860) );
AOI222X1TS U2236 ( .A0(n4320), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n4319), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n2668), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n2669)
);
AOI222X1TS U2237 ( .A0(n4320), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n2749), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n4319), .Y(n2675)
);
AOI222X1TS U2238 ( .A0(n4320), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4319), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n2749), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n2664)
);
AOI222X1TS U2239 ( .A0(n4320), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n4319), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n2749), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n2665)
);
AOI222X1TS U2240 ( .A0(n4320), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4319), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n2749), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n2666)
);
AOI222X1TS U2241 ( .A0(n4320), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n4319), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n2749), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n2667)
);
AOI222X1TS U2242 ( .A0(n2885), .A1(cordic_result[0]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[0]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[0]), .Y(n2874)
);
AOI222X1TS U2243 ( .A0(n2885), .A1(cordic_result[2]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[2]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[2]), .Y(n2872)
);
AOI222X1TS U2244 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n2780)
);
AOI222X1TS U2245 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n2775) );
AOI222X1TS U2246 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n2778) );
AOI222X1TS U2247 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n2789) );
AOI222X1TS U2248 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n2749), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n2748)
);
AOI222X1TS U2249 ( .A0(n4320), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n2749), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n2750)
);
AOI222X1TS U2250 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n2769) );
AOI222X1TS U2251 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n2749), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n2768) );
AOI222X1TS U2252 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n2668), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n2764) );
AOI222X1TS U2253 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n2668), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n2763) );
AOI222X1TS U2254 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n2668), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n2760) );
AOI222X1TS U2255 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n2668), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n2759) );
AOI222X1TS U2256 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n2787), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n2749), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n2758)
);
AOI222X1TS U2257 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n2782) );
AOI222X1TS U2258 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n2781) );
AOI222X1TS U2259 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n2785) );
AOI222X1TS U2260 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n2777) );
AOI222X1TS U2261 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n2771) );
AOI222X1TS U2262 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n2749), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n2770) );
AOI222X1TS U2263 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n2749), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n2767) );
AOI222X1TS U2264 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n2749), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n2766) );
AOI222X1TS U2265 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n2668), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n2765) );
AOI222X1TS U2266 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n2668), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n2762) );
AOI222X1TS U2267 ( .A0(n2788), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n2668), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n2761) );
CLKINVX6TS U2268 ( .A(n4386), .Y(n3116) );
INVX4TS U2269 ( .A(n2893), .Y(n4336) );
NAND2X1TS U2270 ( .A(n3088), .B(n4386), .Y(n3195) );
INVX4TS U2271 ( .A(n2662), .Y(n2249) );
NAND2X1TS U2272 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n4479), .Y(n4481)
);
AOI211X2TS U2273 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[0]), .A1(n4256), .B0(
n3860), .C0(n3067), .Y(n3188) );
AO22X1TS U2274 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[1]), .A1(n2197), .B0(
n3164), .B1(n3859), .Y(n3088) );
NAND2X1TS U2275 ( .A(FPMULT_Sgf_normalized_result[19]), .B(n4473), .Y(n4476)
);
NOR2X1TS U2276 ( .A(n3008), .B(n2311), .Y(n2312) );
NAND2X1TS U2277 ( .A(n4253), .B(n2658), .Y(n2311) );
AO22X1TS U2278 ( .A0(operation[1]), .A1(n2310), .B0(begin_operation), .B1(
n4250), .Y(n2658) );
NAND2X1TS U2279 ( .A(FPMULT_Sgf_normalized_result[17]), .B(n4469), .Y(n4471)
);
NAND2X1TS U2280 ( .A(FPMULT_Sgf_normalized_result[15]), .B(n4465), .Y(n4467)
);
NAND2X1TS U2281 ( .A(FPMULT_Sgf_normalized_result[13]), .B(n4461), .Y(n4463)
);
NAND2X1TS U2282 ( .A(n3083), .B(n4874), .Y(n3001) );
NAND2X1TS U2283 ( .A(n4086), .B(n3818), .Y(n3820) );
NAND2X1TS U2284 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n4457), .Y(n4459)
);
NOR3BX1TS U2285 ( .AN(n3084), .B(FPADDSUB_Raw_mant_NRM_SWR[12]), .C(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n3058) );
NAND2X1TS U2286 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n4453), .Y(n4455)
);
ADDHXLTS U2287 ( .A(n3290), .B(n3289), .CO(n3263), .S(n3300) );
NOR2BX4TS U2288 ( .AN(n4941), .B(n2455), .Y(n2497) );
NOR2BX4TS U2289 ( .AN(n3215), .B(n3214), .Y(n3255) );
NOR2BX4TS U2290 ( .AN(n3237), .B(n3236), .Y(n3422) );
NOR2BX4TS U2291 ( .AN(n3565), .B(n3561), .Y(n3572) );
AOI222X4TS U2292 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n4938), .B0(
FPADDSUB_DmP_mant_SFG_SWR[2]), .B1(n4643), .C0(n4938), .C1(n4643), .Y(
n4649) );
NAND2X1TS U2293 ( .A(n2200), .B(n4868), .Y(n4643) );
NOR2X4TS U2294 ( .A(n2329), .B(n4945), .Y(n2327) );
NOR2X4TS U2295 ( .A(n3209), .B(n3208), .Y(n3266) );
NOR2X4TS U2296 ( .A(n3246), .B(n3245), .Y(n3516) );
NOR2XLTS U2297 ( .A(n2429), .B(n2393), .Y(n2395) );
INVX2TS U2298 ( .A(n2396), .Y(n2548) );
OAI21X1TS U2299 ( .A0(n2364), .A1(n2363), .B0(n2362), .Y(n2396) );
AOI21X1TS U2300 ( .A0(n2302), .A1(n2333), .B0(n2332), .Y(n2364) );
NOR2X1TS U2301 ( .A(n2531), .B(n2465), .Y(n2361) );
BUFX4TS U2302 ( .A(n3623), .Y(n3702) );
NAND2X1TS U2303 ( .A(n3732), .B(n3759), .Y(n2519) );
OA21XLTS U2304 ( .A0(n3616), .A1(n2317), .B0(n3198), .Y(n3284) );
OAI21XLTS U2305 ( .A0(n3579), .A1(n3515), .B0(n3524), .Y(n3525) );
OAI21XLTS U2306 ( .A0(n3650), .A1(n2348), .B0(n3472), .Y(n3473) );
OAI21XLTS U2307 ( .A0(n3616), .A1(n3410), .B0(n3393), .Y(n3394) );
OAI21XLTS U2308 ( .A0(n3612), .A1(n2348), .B0(n3491), .Y(n3492) );
OAI21XLTS U2309 ( .A0(n3621), .A1(n3774), .B0(n2498), .Y(n2499) );
OAI21XLTS U2310 ( .A0(n3579), .A1(n3254), .B0(n3334), .Y(n3335) );
INVX2TS U2311 ( .A(n3833), .Y(n3837) );
NOR2XLTS U2312 ( .A(n2648), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n2649) );
NOR2XLTS U2313 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4520) );
OAI21XLTS U2314 ( .A0(n3938), .A1(n3914), .B0(n3913), .Y(n3917) );
CLKINVX3TS U2315 ( .A(n2216), .Y(n2256) );
OAI21XLTS U2316 ( .A0(n2656), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n4529),
.Y(n2657) );
OAI211XLTS U2317 ( .A0(n3113), .A1(n3189), .B0(n3112), .C0(n3111), .Y(n1793)
);
OAI211XLTS U2318 ( .A0(n3113), .A1(n3191), .B0(n3103), .C0(n3102), .Y(n1794)
);
OAI211XLTS U2319 ( .A0(n3126), .A1(n3189), .B0(n3106), .C0(n3105), .Y(n1797)
);
OAI211XLTS U2320 ( .A0(n4394), .A1(n3191), .B0(n3099), .C0(n3098), .Y(n1790)
);
OAI211XLTS U2321 ( .A0(n3131), .A1(n3189), .B0(n3130), .C0(n3129), .Y(n1795)
);
OAI21XLTS U2322 ( .A0(n3066), .A1(n3063), .B0(n3064), .Y(n2077) );
OAI211XLTS U2323 ( .A0(n3163), .A1(n3189), .B0(n3162), .C0(n3161), .Y(n1801)
);
OAI211XLTS U2324 ( .A0(n2988), .A1(n5092), .B0(n2959), .C0(n2958), .Y(n1919)
);
OAI211XLTS U2325 ( .A0(n2996), .A1(n5119), .B0(n2939), .C0(n2938), .Y(n1923)
);
OAI21XLTS U2326 ( .A0(n3190), .A1(n3191), .B0(n3097), .Y(n1813) );
OAI21XLTS U2327 ( .A0(n3006), .A1(n3063), .B0(n3004), .Y(n2079) );
OAI211XLTS U2328 ( .A0(n2985), .A1(n5107), .B0(n2925), .C0(n2924), .Y(n1935)
);
OAI211XLTS U2329 ( .A0(n2996), .A1(n5118), .B0(n2947), .C0(n2946), .Y(n1924)
);
OAI211XLTS U2330 ( .A0(n3192), .A1(n3189), .B0(n3185), .C0(n3184), .Y(n1811)
);
CLKMX2X2TS U2331 ( .A(FPMULT_P_Sgf[42]), .B(n4176), .S0(n4185), .Y(n1595) );
CLKMX2X2TS U2332 ( .A(FPMULT_P_Sgf[41]), .B(n4168), .S0(n4185), .Y(n1594) );
CLKMX2X2TS U2333 ( .A(FPMULT_P_Sgf[40]), .B(n4159), .S0(n4185), .Y(n1593) );
CLKMX2X2TS U2334 ( .A(FPMULT_P_Sgf[30]), .B(n4040), .S0(n4194), .Y(n1583) );
CLKMX2X2TS U2335 ( .A(FPMULT_P_Sgf[39]), .B(n4151), .S0(n4185), .Y(n1592) );
CLKMX2X2TS U2336 ( .A(FPMULT_P_Sgf[31]), .B(n4018), .S0(n4194), .Y(n1584) );
CLKMX2X2TS U2337 ( .A(FPMULT_P_Sgf[32]), .B(n4028), .S0(n4194), .Y(n1585) );
CLKMX2X2TS U2338 ( .A(FPMULT_P_Sgf[37]), .B(n4134), .S0(n4185), .Y(n1590) );
CLKMX2X2TS U2339 ( .A(FPMULT_P_Sgf[36]), .B(n4123), .S0(n4185), .Y(n1589) );
CLKMX2X2TS U2340 ( .A(FPMULT_P_Sgf[38]), .B(n4142), .S0(n4185), .Y(n1591) );
CLKMX2X2TS U2341 ( .A(FPMULT_P_Sgf[29]), .B(n4045), .S0(n4194), .Y(n1582) );
CLKMX2X2TS U2342 ( .A(FPMULT_P_Sgf[26]), .B(n4066), .S0(n4194), .Y(n1579) );
CLKMX2X2TS U2343 ( .A(FPMULT_P_Sgf[28]), .B(n4051), .S0(n4194), .Y(n1581) );
CLKMX2X2TS U2344 ( .A(FPMULT_P_Sgf[25]), .B(n4072), .S0(n4194), .Y(n1578) );
AO21X1TS U2345 ( .A0(n2258), .A1(n4483), .B0(n4482), .Y(n1602) );
OAI21X2TS U2346 ( .A0(n4058), .A1(n3810), .B0(n3809), .Y(n4013) );
INVX4TS U2347 ( .A(n3089), .Y(n2254) );
INVX4TS U2348 ( .A(n3096), .Y(n3189) );
AO22X1TS U2349 ( .A0(n4488), .A1(n4472), .B0(n4483), .B1(
FPMULT_Add_result[18]), .Y(n1606) );
AOI22X1TS U2350 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(n4912), .B0(n4750), .B1(
n4749), .Y(n4757) );
NOR2X1TS U2351 ( .A(n4067), .B(n4061), .Y(n3808) );
OR2X2TS U2352 ( .A(mult_x_69_n516), .B(mult_x_69_n522), .Y(n4128) );
OR2X2TS U2353 ( .A(mult_x_69_n523), .B(mult_x_69_n530), .Y(n4113) );
OR2X2TS U2354 ( .A(mult_x_69_n503), .B(mult_x_69_n508), .Y(n4139) );
OR2X2TS U2355 ( .A(mult_x_69_n666), .B(mult_x_69_n676), .Y(n2307) );
OR2X2TS U2356 ( .A(mult_x_69_n687), .B(mult_x_69_n696), .Y(n3905) );
OR2X2TS U2357 ( .A(mult_x_69_n491), .B(mult_x_69_n496), .Y(n4156) );
OR2X2TS U2358 ( .A(mult_x_69_n477), .B(mult_x_69_n475), .Y(n4191) );
OAI21X1TS U2359 ( .A0(n3978), .A1(n3977), .B0(n3976), .Y(n3983) );
OAI21X1TS U2360 ( .A0(n3602), .A1(n3515), .B0(n3534), .Y(n3535) );
OAI21X1TS U2361 ( .A0(n3645), .A1(n3441), .B0(n3418), .Y(n3419) );
OAI21X1TS U2362 ( .A0(n3612), .A1(n2496), .B0(n2515), .Y(n2516) );
OAI21X1TS U2363 ( .A0(n3602), .A1(n3704), .B0(n3601), .Y(n3603) );
OAI21X1TS U2364 ( .A0(n3612), .A1(n3515), .B0(n3538), .Y(n3539) );
OAI21X1TS U2365 ( .A0(n3592), .A1(n3515), .B0(n3530), .Y(n3531) );
OAI21X1TS U2366 ( .A0(n3592), .A1(n3704), .B0(n3591), .Y(n3593) );
OAI21X1TS U2367 ( .A0(n3575), .A1(n3704), .B0(n3574), .Y(n3576) );
OAI21X1TS U2368 ( .A0(n3650), .A1(n2496), .B0(n3649), .Y(n3651) );
OAI21X1TS U2369 ( .A0(n3612), .A1(n2352), .B0(n3391), .Y(n3392) );
OAI21X1TS U2370 ( .A0(n3650), .A1(n3515), .B0(n3520), .Y(n3521) );
OAI21X1TS U2371 ( .A0(n3583), .A1(n2348), .B0(n3478), .Y(n3479) );
OAI21X1TS U2372 ( .A0(n3575), .A1(n3515), .B0(n3522), .Y(n3523) );
OAI21X1TS U2373 ( .A0(n3592), .A1(n2348), .B0(n3482), .Y(n3483) );
OAI21X1TS U2374 ( .A0(n3612), .A1(n3441), .B0(n3440), .Y(n3443) );
OAI21X1TS U2375 ( .A0(n3650), .A1(n3704), .B0(n3570), .Y(n3571) );
INVX2TS U2376 ( .A(n2444), .Y(n3602) );
OAI21X1TS U2377 ( .A0(n3597), .A1(n2348), .B0(n3484), .Y(n3485) );
OAI21X1TS U2378 ( .A0(n3606), .A1(n3704), .B0(n3605), .Y(n3607) );
OAI21X1TS U2379 ( .A0(n3579), .A1(n2352), .B0(n3377), .Y(n3378) );
OAI21X1TS U2380 ( .A0(n3616), .A1(n3774), .B0(n2544), .Y(n2545) );
OAI21X1TS U2381 ( .A0(n3627), .A1(n3774), .B0(n2584), .Y(n2585) );
OAI21X1TS U2382 ( .A0(n3606), .A1(n2348), .B0(n3489), .Y(n3490) );
OAI21X1TS U2383 ( .A0(n3632), .A1(n3232), .B0(n3451), .Y(n3452) );
OAI21X1TS U2384 ( .A0(n3627), .A1(n3232), .B0(n3449), .Y(n3450) );
OAI21X1TS U2385 ( .A0(n3597), .A1(n3515), .B0(n3532), .Y(n3533) );
OAI21X1TS U2386 ( .A0(n3597), .A1(n2352), .B0(n3383), .Y(n3384) );
AOI222X1TS U2387 ( .A0(n2823), .A1(cordic_result[14]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[14]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[14]), .Y(n2876) );
OAI21X1TS U2388 ( .A0(n3699), .A1(n3232), .B0(n3457), .Y(n3458) );
INVX2TS U2389 ( .A(n2560), .Y(n3627) );
OAI21X1TS U2390 ( .A0(n3710), .A1(n3232), .B0(n3455), .Y(n3456) );
AOI222X1TS U2391 ( .A0(n2823), .A1(cordic_result[11]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[11]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[11]), .Y(n2889) );
OAI21X1TS U2392 ( .A0(n3693), .A1(n3232), .B0(n3264), .Y(n3265) );
INVX2TS U2393 ( .A(n2569), .Y(n3606) );
AOI222X1TS U2394 ( .A0(n2823), .A1(cordic_result[10]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[10]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[10]), .Y(n2882) );
AOI222X1TS U2395 ( .A0(n2823), .A1(cordic_result[12]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[12]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[12]), .Y(n2880) );
INVX2TS U2396 ( .A(n2470), .Y(n3775) );
OAI21X1TS U2397 ( .A0(n3693), .A1(n3774), .B0(n3692), .Y(n3694) );
INVX2TS U2398 ( .A(n2511), .Y(n3204) );
OA21XLTS U2399 ( .A0(n3718), .A1(n2317), .B0(n2331), .Y(n2344) );
NAND2XLTS U2400 ( .A(n3068), .B(n4908), .Y(n3077) );
AOI21X2TS U2401 ( .A0(n2396), .A1(n2395), .B0(n2394), .Y(n2511) );
OAI21X1TS U2402 ( .A0(n3718), .A1(n3232), .B0(n3240), .Y(n3241) );
OAI21X1TS U2403 ( .A0(n4957), .A1(n3441), .B0(n3233), .Y(n3234) );
OAI21X1TS U2404 ( .A0(n4957), .A1(n2348), .B0(n2319), .Y(n2320) );
INVX2TS U2405 ( .A(n2342), .Y(n3734) );
OAI21X1TS U2406 ( .A0(n4957), .A1(n3254), .B0(n3257), .Y(n3258) );
NAND2X1TS U2407 ( .A(n2433), .B(n2391), .Y(n2393) );
NOR2X6TS U2408 ( .A(n4252), .B(n2822), .Y(n2823) );
INVX4TS U2409 ( .A(n4492), .Y(n4489) );
INVX4TS U2410 ( .A(n3063), .Y(n3164) );
NAND2X2TS U2411 ( .A(n3853), .B(n3852), .Y(n3984) );
OAI21XLTS U2412 ( .A0(n3041), .A1(n5040), .B0(n3011), .Y(op_result[24]) );
NAND2BX4TS U2413 ( .AN(n2329), .B(n4945), .Y(n2317) );
INVX4TS U2414 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n4760) );
BUFX3TS U2415 ( .A(FPMULT_Op_MX[5]), .Y(n2287) );
CLKMX2X2TS U2416 ( .A(FPMULT_P_Sgf[47]), .B(n3854), .S0(n4185), .Y(n1552) );
CLKMX2X2TS U2417 ( .A(FPMULT_P_Sgf[46]), .B(n4006), .S0(n4194), .Y(n1599) );
CLKMX2X2TS U2418 ( .A(FPMULT_P_Sgf[45]), .B(n4012), .S0(n4194), .Y(n1598) );
CLKMX2X2TS U2419 ( .A(FPMULT_P_Sgf[44]), .B(n4195), .S0(n4194), .Y(n1597) );
CLKMX2X2TS U2420 ( .A(FPMULT_P_Sgf[43]), .B(n4186), .S0(n4185), .Y(n1596) );
CLKMX2X2TS U2421 ( .A(FPMULT_P_Sgf[35]), .B(n4116), .S0(n4185), .Y(n1588) );
CLKMX2X2TS U2422 ( .A(FPMULT_P_Sgf[34]), .B(n4105), .S0(n4185), .Y(n1587) );
CLKMX2X2TS U2423 ( .A(FPMULT_P_Sgf[33]), .B(n4093), .S0(n4185), .Y(n1586) );
OAI21X1TS U2424 ( .A0(n4111), .A1(n4110), .B0(n4109), .Y(n4115) );
AO22X1TS U2425 ( .A0(n4782), .A1(n4640), .B0(n4760), .B1(
FPADDSUB_ADD_OVRFLW_NRM), .Y(n1353) );
OAI21X2TS U2426 ( .A0(n4120), .A1(n3825), .B0(n3824), .Y(n4141) );
OAI21X1TS U2427 ( .A0(n4056), .A1(n4052), .B0(n4053), .Y(n4050) );
OAI21X1TS U2428 ( .A0(n4071), .A1(n4067), .B0(n4068), .Y(n4065) );
AOI22X2TS U2429 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(n4925), .B0(n4778), .B1(
n4776), .Y(n4786) );
OAI211X1TS U2430 ( .A0(n3131), .A1(n3191), .B0(n3115), .C0(n3114), .Y(n1796)
);
OAI211X1TS U2431 ( .A0(n3126), .A1(n3191), .B0(n3125), .C0(n3124), .Y(n1798)
);
OAI211X1TS U2432 ( .A0(n3180), .A1(n3191), .B0(n3174), .C0(n3173), .Y(n1806)
);
OAI211X1TS U2433 ( .A0(n3155), .A1(n3189), .B0(n3148), .C0(n3147), .Y(n1803)
);
AOI2BB1X1TS U2434 ( .A0N(n4488), .A1N(FPMULT_FSM_add_overflow_flag), .B0(
n4487), .Y(n1600) );
OAI211X1TS U2435 ( .A0(n3121), .A1(n3189), .B0(n3109), .C0(n3108), .Y(n1799)
);
OAI211X1TS U2436 ( .A0(n3155), .A1(n3191), .B0(n3154), .C0(n3153), .Y(n1804)
);
OAI211X1TS U2437 ( .A0(n3121), .A1(n3191), .B0(n3120), .C0(n3119), .Y(n1800)
);
OAI211X1TS U2438 ( .A0(n3138), .A1(n3191), .B0(n3137), .C0(n3136), .Y(n1792)
);
OAI21X1TS U2439 ( .A0(n4484), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
n4487), .Y(n4485) );
OAI211X1TS U2440 ( .A0(n3171), .A1(n3191), .B0(n3170), .C0(n3169), .Y(n1808)
);
OAI21X1TS U2441 ( .A0(n4388), .A1(n3195), .B0(n3194), .Y(n1812) );
NAND3X1TS U2442 ( .A(n4394), .B(n4393), .C(n4392), .Y(n1789) );
OAI211X1TS U2443 ( .A0(n3165), .A1(n3189), .B0(n3145), .C0(n3144), .Y(n1809)
);
OAI211X1TS U2444 ( .A0(n3180), .A1(n3189), .B0(n3179), .C0(n3178), .Y(n1805)
);
OAI211X1TS U2445 ( .A0(n3165), .A1(n3191), .B0(n3141), .C0(n3140), .Y(n1810)
);
OAI211X1TS U2446 ( .A0(n3138), .A1(n3189), .B0(n3095), .C0(n3094), .Y(n1791)
);
OAI211X1TS U2447 ( .A0(n3171), .A1(n3189), .B0(n3167), .C0(n3166), .Y(n1807)
);
OAI211X1TS U2448 ( .A0(n3163), .A1(n3191), .B0(n3157), .C0(n3156), .Y(n1802)
);
OAI2BB2X1TS U2449 ( .B0(n4768), .B1(n4770), .A0N(n5062), .A1N(
FPADDSUB_DMP_SFG[20]), .Y(n4776) );
OAI21X1TS U2450 ( .A0(n3938), .A1(n3937), .B0(n3936), .Y(n3943) );
AOI2BB2X1TS U2451 ( .B0(n4792), .B1(n4754), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[19]), .A1N(n4782), .Y(n1323) );
AO22X1TS U2452 ( .A0(n4488), .A1(n4477), .B0(n4483), .B1(
FPMULT_Add_result[20]), .Y(n1604) );
NOR2X1TS U2453 ( .A(n4015), .B(n3820), .Y(n3822) );
OAI211X1TS U2454 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n4479), .B0(
n4478), .C0(n4481), .Y(n4480) );
OAI21X1TS U2455 ( .A0(n3881), .A1(n3880), .B0(n3879), .Y(n3886) );
NOR2X1TS U2456 ( .A(n3937), .B(n3939), .Y(n3806) );
OAI21X1TS U2457 ( .A0(n3816), .A1(n4099), .B0(n3815), .Y(n3817) );
OR2X2TS U2458 ( .A(n3188), .B(n3195), .Y(n2216) );
OR2X2TS U2459 ( .A(n3092), .B(n3195), .Y(n3089) );
NAND2X1TS U2460 ( .A(n3808), .B(n4060), .Y(n3810) );
OAI21X1TS U2461 ( .A0(n3963), .A1(n3962), .B0(n3961), .Y(n3968) );
OAI21X1TS U2462 ( .A0(n4035), .A1(n4041), .B0(n4036), .Y(n3811) );
OAI2BB2X1TS U2463 ( .B0(n4739), .B1(n4741), .A0N(n5010), .A1N(
FPADDSUB_DMP_SFG[16]), .Y(n4749) );
INVX1TS U2464 ( .A(n4109), .Y(n3814) );
OAI21X1TS U2465 ( .A0(n4068), .A1(n4061), .B0(n4062), .Y(n3807) );
OR2X2TS U2466 ( .A(mult_x_69_n509), .B(mult_x_69_n515), .Y(n4131) );
OAI21X1TS U2467 ( .A0(n3066), .A1(n4256), .B0(n3065), .Y(n1332) );
OAI21X1TS U2468 ( .A0(n3053), .A1(n4256), .B0(n3052), .Y(n1324) );
OAI21X1TS U2469 ( .A0(n4256), .A1(n3006), .B0(n3005), .Y(n1320) );
OAI21X1TS U2470 ( .A0(n3053), .A1(n3063), .B0(n3051), .Y(n2078) );
OR2X2TS U2471 ( .A(mult_x_69_n482), .B(mult_x_69_n485), .Y(n4173) );
OAI21X1TS U2472 ( .A0(n3964), .A1(n3961), .B0(n3965), .Y(n3793) );
NOR2X1TS U2473 ( .A(n3962), .B(n3964), .Y(n3794) );
INVX1TS U2474 ( .A(n3059), .Y(n3050) );
OAI211X1TS U2475 ( .A0(n2988), .A1(n5093), .B0(n2957), .C0(n2956), .Y(n1918)
);
OAI211X1TS U2476 ( .A0(n2988), .A1(n5138), .B0(n2903), .C0(n2902), .Y(n1844)
);
OAI211X1TS U2477 ( .A0(n2988), .A1(n5094), .B0(n2909), .C0(n2908), .Y(n1917)
);
OAI211X1TS U2478 ( .A0(n2996), .A1(n5147), .B0(n2995), .C0(n2994), .Y(n1821)
);
OAI211X1TS U2479 ( .A0(n2988), .A1(n4323), .B0(n2907), .C0(n2906), .Y(n1915)
);
OAI211X1TS U2480 ( .A0(n2996), .A1(n5111), .B0(n2945), .C0(n2944), .Y(n1931)
);
OAI211X1TS U2481 ( .A0(n2996), .A1(n5113), .B0(n2949), .C0(n2948), .Y(n1929)
);
OAI211X1TS U2482 ( .A0(n2996), .A1(n5133), .B0(n2992), .C0(n2991), .Y(n1822)
);
OAI211X1TS U2483 ( .A0(n2996), .A1(n5146), .B0(n2990), .C0(n2989), .Y(n1824)
);
OAI211X1TS U2484 ( .A0(n2996), .A1(n5117), .B0(n2933), .C0(n2932), .Y(n1925)
);
NAND3X1TS U2485 ( .A(n4364), .B(n4363), .C(n4370), .Y(n1826) );
OAI211X1TS U2486 ( .A0(n2996), .A1(n5121), .B0(n2951), .C0(n2950), .Y(n1921)
);
NAND3X1TS U2487 ( .A(n4372), .B(n4371), .C(n4370), .Y(n1823) );
NAND3X1TS U2488 ( .A(n4360), .B(n4359), .C(n4358), .Y(n1827) );
NAND3X1TS U2489 ( .A(n4347), .B(n4346), .C(n4358), .Y(n1832) );
NAND3X1TS U2490 ( .A(n4369), .B(n4368), .C(n4367), .Y(n1825) );
NAND3X1TS U2491 ( .A(n4350), .B(n4349), .C(n4348), .Y(n1831) );
OAI211X1TS U2492 ( .A0(n2985), .A1(n5102), .B0(n2955), .C0(n2954), .Y(n1940)
);
OAI211X1TS U2493 ( .A0(n2988), .A1(n5087), .B0(n2911), .C0(n2910), .Y(n1914)
);
NAND3X1TS U2494 ( .A(n4345), .B(n4344), .C(n4343), .Y(n1834) );
NAND3X1TS U2495 ( .A(n4342), .B(n4341), .C(n4343), .Y(n1838) );
NAND3X1TS U2496 ( .A(n4357), .B(n4356), .C(n4367), .Y(n1828) );
NAND3X1TS U2497 ( .A(n4352), .B(n4351), .C(n4367), .Y(n1830) );
OAI211X1TS U2498 ( .A0(n2996), .A1(n5115), .B0(n2969), .C0(n2968), .Y(n1927)
);
OAI211X1TS U2499 ( .A0(n2985), .A1(n5145), .B0(n2920), .C0(n2919), .Y(n1833)
);
OAI211X1TS U2500 ( .A0(n2988), .A1(n5142), .B0(n2953), .C0(n2952), .Y(n1837)
);
OAI211X1TS U2501 ( .A0(n2985), .A1(n5109), .B0(n2965), .C0(n2964), .Y(n1933)
);
OAI211X1TS U2502 ( .A0(n2985), .A1(n5106), .B0(n2976), .C0(n2975), .Y(n1936)
);
OAI211X1TS U2503 ( .A0(n2985), .A1(n5104), .B0(n2971), .C0(n2970), .Y(n1938)
);
OAI211X1TS U2504 ( .A0(n2985), .A1(n5105), .B0(n2963), .C0(n2962), .Y(n1937)
);
OAI211X1TS U2505 ( .A0(n2985), .A1(n5103), .B0(n2967), .C0(n2966), .Y(n1939)
);
NAND3X1TS U2506 ( .A(n4383), .B(n4382), .C(n4381), .Y(n1816) );
OAI211X1TS U2507 ( .A0(n2996), .A1(n4914), .B0(n2981), .C0(n2980), .Y(n1920)
);
OAI211X1TS U2508 ( .A0(n2985), .A1(n5101), .B0(n2937), .C0(n2936), .Y(n1941)
);
OAI211X1TS U2509 ( .A0(n2988), .A1(n5088), .B0(n2913), .C0(n2912), .Y(n1916)
);
OAI211X1TS U2510 ( .A0(n2985), .A1(n5100), .B0(n2935), .C0(n2934), .Y(n1942)
);
OAI211X1TS U2511 ( .A0(n2985), .A1(n5108), .B0(n2927), .C0(n2926), .Y(n1934)
);
OAI211X1TS U2512 ( .A0(n2985), .A1(n5110), .B0(n2929), .C0(n2928), .Y(n1932)
);
OAI211X1TS U2513 ( .A0(n2996), .A1(n5116), .B0(n2931), .C0(n2930), .Y(n1926)
);
OAI211X1TS U2514 ( .A0(n2996), .A1(n5112), .B0(n2941), .C0(n2940), .Y(n1930)
);
OAI211X1TS U2515 ( .A0(n2996), .A1(n5120), .B0(n2922), .C0(n2921), .Y(n1922)
);
OAI211X1TS U2516 ( .A0(n2996), .A1(n5114), .B0(n2943), .C0(n2942), .Y(n1928)
);
OAI211X1TS U2517 ( .A0(n2985), .A1(n5099), .B0(n2961), .C0(n2960), .Y(n1943)
);
OAI211X1TS U2518 ( .A0(n2988), .A1(n5089), .B0(n2905), .C0(n2904), .Y(n1913)
);
OAI211X1TS U2519 ( .A0(n2985), .A1(n5149), .B0(n2984), .C0(n2983), .Y(n1819)
);
OAI211X1TS U2520 ( .A0(n2988), .A1(n5148), .B0(n2987), .C0(n2986), .Y(n1820)
);
OAI211X1TS U2521 ( .A0(n2988), .A1(n5139), .B0(n2895), .C0(n2894), .Y(n1843)
);
NAND3X1TS U2522 ( .A(n4379), .B(n4378), .C(n4381), .Y(n1817) );
NAND3X1TS U2523 ( .A(n4355), .B(n4354), .C(n4353), .Y(n1829) );
OAI211X1TS U2524 ( .A0(n2985), .A1(n5144), .B0(n2918), .C0(n2917), .Y(n1835)
);
NAND3X1TS U2525 ( .A(n4376), .B(n4375), .C(n4381), .Y(n1818) );
OAI211X1TS U2526 ( .A0(n2988), .A1(n5140), .B0(n2899), .C0(n2898), .Y(n1841)
);
OAI211X1TS U2527 ( .A0(n2988), .A1(n5143), .B0(n2916), .C0(n2915), .Y(n1836)
);
OAI211X1TS U2528 ( .A0(n2988), .A1(n5137), .B0(n2897), .C0(n2896), .Y(n1845)
);
INVX1TS U2529 ( .A(n4528), .Y(n2656) );
NAND3X1TS U2530 ( .A(n4339), .B(n4338), .C(n4348), .Y(n1840) );
NAND3X1TS U2531 ( .A(n4335), .B(n4334), .C(n4353), .Y(n1842) );
OAI21X1TS U2532 ( .A0(n3592), .A1(n2496), .B0(n2482), .Y(n2483) );
OAI21X1TS U2533 ( .A0(n3612), .A1(n3704), .B0(n3611), .Y(n3613) );
OAI21X1TS U2534 ( .A0(n3602), .A1(n3254), .B0(n3342), .Y(n3343) );
OAI21X1TS U2535 ( .A0(n3602), .A1(n2496), .B0(n2563), .Y(n2564) );
OAI21X1TS U2536 ( .A0(n3575), .A1(n3441), .B0(n3423), .Y(n3424) );
OAI21X1TS U2537 ( .A0(n3575), .A1(n2496), .B0(n2517), .Y(n2518) );
OAI21X1TS U2538 ( .A0(n3645), .A1(n3254), .B0(n3328), .Y(n3329) );
OAI21X1TS U2539 ( .A0(n3575), .A1(n3254), .B0(n3332), .Y(n3333) );
OAI21X1TS U2540 ( .A0(n3583), .A1(n2496), .B0(n2459), .Y(n2460) );
OAI21X1TS U2541 ( .A0(n3645), .A1(n2352), .B0(n3212), .Y(n3213) );
OAI21X1TS U2542 ( .A0(n3583), .A1(n2352), .B0(n3221), .Y(n3222) );
OAI21X1TS U2543 ( .A0(n3645), .A1(n2348), .B0(n3470), .Y(n3471) );
OAI21X1TS U2544 ( .A0(n3602), .A1(n3441), .B0(n3435), .Y(n3436) );
OAI21X1TS U2545 ( .A0(n3592), .A1(n2352), .B0(n3381), .Y(n3382) );
OAI21X1TS U2546 ( .A0(n3650), .A1(n2352), .B0(n3375), .Y(n3376) );
OAI21X1TS U2547 ( .A0(n3583), .A1(n3254), .B0(n3217), .Y(n3218) );
OAI21X1TS U2548 ( .A0(n3583), .A1(n3704), .B0(n3582), .Y(n3584) );
OAI21X1TS U2549 ( .A0(n3645), .A1(n3704), .B0(n3568), .Y(n3569) );
OAI21X1TS U2550 ( .A0(n3621), .A1(n3232), .B0(n3447), .Y(n3448) );
OAI21X1TS U2551 ( .A0(n3645), .A1(n2496), .B0(n3644), .Y(n3646) );
OAI21X1TS U2552 ( .A0(n3575), .A1(n2348), .B0(n3474), .Y(n3475) );
OAI21X1TS U2553 ( .A0(n3602), .A1(n2352), .B0(n3385), .Y(n3386) );
OAI21X1TS U2554 ( .A0(n3592), .A1(n3254), .B0(n3338), .Y(n3339) );
OAI21X1TS U2555 ( .A0(n3583), .A1(n3515), .B0(n3526), .Y(n3527) );
OAI21X1TS U2556 ( .A0(n3602), .A1(n2348), .B0(n3486), .Y(n3487) );
OAI21X1TS U2557 ( .A0(n3575), .A1(n2352), .B0(n3219), .Y(n3220) );
OAI21X1TS U2558 ( .A0(n3645), .A1(n3515), .B0(n3518), .Y(n3519) );
OAI21X1TS U2559 ( .A0(n3592), .A1(n3441), .B0(n3431), .Y(n3432) );
OAI21X1TS U2560 ( .A0(n3650), .A1(n3441), .B0(n3420), .Y(n3421) );
INVX3TS U2561 ( .A(n2833), .Y(n2812) );
OAI21X1TS U2562 ( .A0(n3612), .A1(n3254), .B0(n3223), .Y(n3224) );
OAI21X1TS U2563 ( .A0(n3583), .A1(n3441), .B0(n3427), .Y(n3428) );
OAI21X1TS U2564 ( .A0(n3650), .A1(n3254), .B0(n3330), .Y(n3331) );
OAI21X1TS U2565 ( .A0(n3597), .A1(n3441), .B0(n3433), .Y(n3434) );
OAI21X1TS U2566 ( .A0(n3837), .A1(n3232), .B0(n3413), .Y(n3414) );
BUFX4TS U2567 ( .A(n2914), .Y(n2982) );
OAI21X1TS U2568 ( .A0(n3587), .A1(n3254), .B0(n3336), .Y(n3337) );
INVX3TS U2569 ( .A(n2813), .Y(n2845) );
OAI21X1TS U2570 ( .A0(n3579), .A1(n3441), .B0(n3425), .Y(n3426) );
OAI21X1TS U2571 ( .A0(n3606), .A1(n2496), .B0(n2579), .Y(n2580) );
OAI21X1TS U2572 ( .A0(n3606), .A1(n3254), .B0(n3345), .Y(n3347) );
INVX3TS U2573 ( .A(n2813), .Y(n4515) );
INVX2TS U2574 ( .A(n2423), .Y(n3583) );
OAI21X1TS U2575 ( .A0(n3837), .A1(n3761), .B0(n3608), .Y(n3560) );
OAI21X1TS U2576 ( .A0(n3616), .A1(n3688), .B0(n3540), .Y(n3541) );
OAI21X1TS U2577 ( .A0(n3587), .A1(n2352), .B0(n3379), .Y(n3380) );
AO21X1TS U2578 ( .A0(n4874), .A1(n4911), .B0(n3054), .Y(n3055) );
OAI21X1TS U2579 ( .A0(n3627), .A1(n3508), .B0(n3499), .Y(n3500) );
OAI21X1TS U2580 ( .A0(n3627), .A1(n3761), .B0(n3626), .Y(n3628) );
OAI21X1TS U2581 ( .A0(n3606), .A1(n2352), .B0(n3388), .Y(n3389) );
OAI21X1TS U2582 ( .A0(n3775), .A1(n3688), .B0(n3548), .Y(n3549) );
OAI21X1TS U2583 ( .A0(n3775), .A1(n3232), .B0(n3453), .Y(n3454) );
OAI21X1TS U2584 ( .A0(n3632), .A1(n3761), .B0(n3631), .Y(n3633) );
OAI21X1TS U2585 ( .A0(n3579), .A1(n2348), .B0(n3476), .Y(n3477) );
OAI21X1TS U2586 ( .A0(n3597), .A1(n3704), .B0(n3596), .Y(n3598) );
OAI21X1TS U2587 ( .A0(n3606), .A1(n3515), .B0(n3536), .Y(n3537) );
OAI21X1TS U2588 ( .A0(n3606), .A1(n3441), .B0(n3437), .Y(n3438) );
OAI21X1TS U2589 ( .A0(n3579), .A1(n2496), .B0(n2576), .Y(n2577) );
OAI21X1TS U2590 ( .A0(n3587), .A1(n3704), .B0(n3586), .Y(n3588) );
OAI21X1TS U2591 ( .A0(n3587), .A1(n2496), .B0(n2457), .Y(n2458) );
OAI21X1TS U2592 ( .A0(n3837), .A1(n2496), .B0(n2513), .Y(n2514) );
BUFX4TS U2593 ( .A(n2772), .Y(n2833) );
INVX3TS U2594 ( .A(n2772), .Y(n4514) );
OAI21X1TS U2595 ( .A0(n3587), .A1(n3515), .B0(n3528), .Y(n3529) );
OAI21X1TS U2596 ( .A0(n3837), .A1(n3410), .B0(n3390), .Y(n3277) );
OAI21X1TS U2597 ( .A0(n3587), .A1(n2348), .B0(n3480), .Y(n3481) );
OAI21X1TS U2598 ( .A0(n3587), .A1(n3441), .B0(n3429), .Y(n3430) );
OAI21X1TS U2599 ( .A0(n3775), .A1(n3508), .B0(n3503), .Y(n3504) );
OAI21X1TS U2600 ( .A0(n3597), .A1(n3254), .B0(n3340), .Y(n3341) );
INVX2TS U2601 ( .A(n2401), .Y(n3650) );
OAI21X1TS U2602 ( .A0(n3579), .A1(n3704), .B0(n3578), .Y(n3580) );
OAI21X1TS U2603 ( .A0(n3775), .A1(n3410), .B0(n3405), .Y(n3406) );
OAI21X1TS U2604 ( .A0(n3632), .A1(n3688), .B0(n3546), .Y(n3547) );
OAI21X1TS U2605 ( .A0(n3833), .A1(n3371), .B0(n3325), .Y(n3326) );
OAI21X1TS U2606 ( .A0(n3833), .A1(n3761), .B0(n3562), .Y(n3563) );
OAI21X1TS U2607 ( .A0(n3693), .A1(n3371), .B0(n3357), .Y(n3358) );
NAND3X1TS U2608 ( .A(n3058), .B(n4895), .C(n4871), .Y(n3054) );
OAI21X1TS U2609 ( .A0(n3699), .A1(n3371), .B0(n3364), .Y(n3365) );
NOR2X2TS U2610 ( .A(n2892), .B(n4239), .Y(n2923) );
OAI21X1TS U2611 ( .A0(n3833), .A1(n3410), .B0(n3373), .Y(n3374) );
OAI21X1TS U2612 ( .A0(n3833), .A1(n3508), .B0(n3467), .Y(n3468) );
OAI21X1TS U2613 ( .A0(n3833), .A1(n3232), .B0(n3415), .Y(n3416) );
NAND3X1TS U2614 ( .A(FPSENCOS_cont_var_out[1]), .B(n2312), .C(n5077), .Y(
n2893) );
NAND3X1TS U2615 ( .A(n3084), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n4895),
.Y(n3085) );
BUFX3TS U2616 ( .A(n2972), .Y(n4340) );
NOR2BX2TS U2617 ( .AN(n2826), .B(n2885), .Y(n2825) );
NOR2X4TS U2618 ( .A(n4254), .B(n4631), .Y(n2772) );
OAI21X1TS U2619 ( .A0(n2548), .A1(n2547), .B0(n2546), .Y(n2553) );
OAI21X1TS U2620 ( .A0(n2548), .A1(n2429), .B0(n2431), .Y(n2542) );
NOR2X6TS U2621 ( .A(operation[1]), .B(n2311), .Y(n4366) );
INVX3TS U2622 ( .A(n2244), .Y(n2246) );
OAI21X1TS U2623 ( .A0(n2511), .A1(n2510), .B0(n2509), .Y(n2512) );
OAI21X1TS U2624 ( .A0(n4872), .A1(n3669), .B0(FPMULT_FS_Module_state_reg[3]),
.Y(n2678) );
OAI31X1TS U2625 ( .A0(n4264), .A1(FPSENCOS_cont_var_out[1]), .A2(n5077),
.B0(n3201), .Y(n2138) );
NOR2X1TS U2626 ( .A(n3669), .B(n2674), .Y(n1694) );
OAI221X2TS U2627 ( .A0(n4390), .A1(n2204), .B0(n3063), .B1(n5068), .C0(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n3187) );
NOR2X1TS U2628 ( .A(n3202), .B(n3843), .Y(n2509) );
NAND3BX1TS U2629 ( .AN(n2724), .B(n2722), .C(n2721), .Y(n2742) );
INVX3TS U2630 ( .A(n4333), .Y(n4332) );
INVX3TS U2631 ( .A(n4333), .Y(n4306) );
INVX3TS U2632 ( .A(n4331), .Y(n2784) );
OAI21X2TS U2633 ( .A0(n4882), .A1(n3063), .B0(n3093), .Y(n2220) );
CLKINVX3TS U2634 ( .A(n4863), .Y(n4816) );
OAI21X1TS U2635 ( .A0(n2431), .A1(n2393), .B0(n2392), .Y(n2394) );
INVX3TS U2636 ( .A(n3063), .Y(n4390) );
NOR2X4TS U2637 ( .A(n4185), .B(n4434), .Y(n3855) );
NOR2X4TS U2638 ( .A(FPMULT_FSM_selector_C), .B(n2593), .Y(n2612) );
BUFX3TS U2639 ( .A(n4271), .Y(n4322) );
OR2X2TS U2640 ( .A(n3042), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n2999) );
NAND2X4TS U2641 ( .A(n2196), .B(n4829), .Y(n4526) );
NOR2X6TS U2642 ( .A(rst), .B(n4259), .Y(n2586) );
INVX3TS U2643 ( .A(n4486), .Y(n4478) );
AOI222X1TS U2644 ( .A0(n3772), .A1(n2296), .B0(n3771), .B1(n3708), .C0(n3769), .C1(n3759), .Y(n3709) );
BUFX3TS U2645 ( .A(n3254), .Y(n3371) );
NAND2X4TS U2646 ( .A(n2248), .B(n2196), .Y(n4556) );
BUFX3TS U2647 ( .A(n3515), .Y(n3688) );
AOI21X1TS U2648 ( .A0(n2463), .A1(n2361), .B0(n2360), .Y(n2362) );
NAND2X1TS U2649 ( .A(n2464), .B(n2361), .Y(n2363) );
BUFX3TS U2650 ( .A(n2348), .Y(n3508) );
OR2X4TS U2651 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n2197), .Y(n3063) );
INVX3TS U2652 ( .A(n2248), .Y(n4829) );
OAI211X1TS U2653 ( .A0(n2683), .A1(n2739), .B0(n2682), .C0(n2681), .Y(n2688)
);
BUFX3TS U2654 ( .A(n2352), .Y(n3410) );
OAI21XLTS U2655 ( .A0(n3041), .A1(n5034), .B0(n3027), .Y(op_result[0]) );
OAI21XLTS U2656 ( .A0(n3041), .A1(n5032), .B0(n3017), .Y(op_result[2]) );
INVX3TS U2657 ( .A(n4760), .Y(n4753) );
OA21X2TS U2658 ( .A0(n3851), .A1(n2591), .B0(FPMULT_FS_Module_state_reg[1]),
.Y(n2592) );
NOR2X4TS U2659 ( .A(n3852), .B(FPMULT_FS_Module_state_reg[1]), .Y(n2358) );
NAND2X2TS U2660 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(n5090), .Y(n4851) );
INVX4TS U2661 ( .A(n2385), .Y(n4271) );
NAND2BX4TS U2662 ( .AN(n3227), .B(n3228), .Y(n2348) );
OR2X2TS U2663 ( .A(n3843), .B(n3643), .Y(n2504) );
NOR2X1TS U2664 ( .A(n4989), .B(n3667), .Y(n2587) );
INVX3TS U2665 ( .A(n4591), .Y(n4522) );
INVX3TS U2666 ( .A(n4760), .Y(n4792) );
OAI211XLTS U2667 ( .A0(n4986), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n2693), .C0(
n2692), .Y(n2696) );
OAI211XLTS U2668 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n4991), .B0(n2705), .C0(
n2708), .Y(n2719) );
NAND2BX4TS U2669 ( .AN(n3208), .B(n3209), .Y(n2352) );
NAND2BX4TS U2670 ( .AN(n3215), .B(n3216), .Y(n3254) );
NOR2X4TS U2671 ( .A(n3216), .B(n3215), .Y(n3259) );
OAI21X1TS U2672 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n3078), .B0(n2204),
.Y(n3079) );
AND2X2TS U2673 ( .A(n3673), .B(n3672), .Y(n3674) );
NAND2BX4TS U2674 ( .AN(n4941), .B(n2456), .Y(n2496) );
NOR2X1TS U2675 ( .A(n3600), .B(n3595), .Y(n2425) );
NOR2X4TS U2676 ( .A(n3238), .B(n3237), .Y(n3235) );
NAND2BX4TS U2677 ( .AN(n3237), .B(n3238), .Y(n3232) );
NOR2X4TS U2678 ( .A(n3228), .B(n3227), .Y(n3225) );
NOR2X4TS U2679 ( .A(n3566), .B(n3565), .Y(n3623) );
NAND2BX4TS U2680 ( .AN(n3245), .B(n3246), .Y(n3515) );
NAND3X1TS U2681 ( .A(n3851), .B(FPMULT_FS_Module_state_reg[1]), .C(
FPMULT_FSM_add_overflow_flag), .Y(n3853) );
BUFX3TS U2682 ( .A(n3012), .Y(n4247) );
NAND3X1TS U2683 ( .A(n5079), .B(n2680), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n2682) );
NAND3X1TS U2684 ( .A(FPSENCOS_cont_iter_out[1]), .B(n5157), .C(n2634), .Y(
n4238) );
OAI211X1TS U2685 ( .A0(n3071), .A1(n3070), .B0(n4882), .C0(n2272), .Y(n3073)
);
OAI211X2TS U2686 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n4978), .B0(n2715),
.C0(n2701), .Y(n2717) );
NOR2X1TS U2687 ( .A(n3732), .B(n3759), .Y(n2359) );
OAI211X2TS U2688 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n4988), .B0(n2735),
.C0(n2720), .Y(n2729) );
INVX3TS U2689 ( .A(n4695), .Y(n4777) );
NOR2X1TS U2690 ( .A(n4989), .B(FPMULT_FS_Module_state_reg[1]), .Y(n3672) );
NAND3BX1TS U2691 ( .AN(n2384), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]),
.C(n2383), .Y(n2385) );
NOR2X1TS U2692 ( .A(n3595), .B(n3590), .Y(n2476) );
INVX3TS U2693 ( .A(n3844), .Y(n3647) );
INVX3TS U2694 ( .A(n4695), .Y(n4787) );
NAND2BX1TS U2695 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n2736) );
BUFX3TS U2696 ( .A(n4297), .Y(n2201) );
NAND2BX1TS U2697 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n2726) );
NOR2XLTS U2698 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n3074) );
BUFX4TS U2699 ( .A(FPMULT_Op_MY[4]), .Y(n3759) );
NAND4X1TS U2700 ( .A(n2204), .B(n4944), .C(n4882), .D(n2215), .Y(n3000) );
NOR4X1TS U2701 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n2322) );
OAI32X1TS U2702 ( .A0(n4242), .A1(FPMULT_exp_oper_result[8]), .A2(
FPMULT_Exp_module_Overflow_flag_A), .B0(overflow_flag_addsubt), .B1(
operation[2]), .Y(n2868) );
INVX1TS U2703 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n4695) );
NAND2BX1TS U2704 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n2680) );
NAND2BX1TS U2705 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n2681) );
BUFX4TS U2706 ( .A(FPMULT_Op_MX[11]), .Y(n2237) );
OR3X2TS U2707 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n4932), .Y(n4396) );
INVX4TS U2708 ( .A(n4250), .Y(n3007) );
NOR2X4TS U2709 ( .A(n3008), .B(operation[2]), .Y(n3012) );
NOR2X4TS U2710 ( .A(operation[1]), .B(n4242), .Y(n3013) );
AOI21X4TS U2711 ( .A0(n4141), .A1(n4139), .B0(n3826), .Y(n4150) );
OAI21X1TS U2712 ( .A0(n3837), .A1(n3508), .B0(n3465), .Y(n3466) );
OAI21X2TS U2713 ( .A0(n4184), .A1(n4180), .B0(n4181), .Y(n4193) );
AOI21X2TS U2714 ( .A0(n4013), .A1(n3822), .B0(n3821), .Y(n4120) );
OAI21X4TS U2715 ( .A0(n4167), .A1(n4163), .B0(n4164), .Y(n4175) );
AOI21X4TS U2716 ( .A0(n4158), .A1(n4156), .B0(n3827), .Y(n4167) );
OAI21XLTS U2717 ( .A0(n3734), .A1(n3410), .B0(n3294), .Y(n3295) );
OA21XLTS U2718 ( .A0(n3762), .A1(n2317), .B0(n2336), .Y(n2347) );
OAI21XLTS U2719 ( .A0(n3718), .A1(n3508), .B0(n3306), .Y(n3307) );
OAI21XLTS U2720 ( .A0(n3722), .A1(n3410), .B0(n2212), .Y(n2351) );
AOI222X1TS U2721 ( .A0(n2327), .A1(n3731), .B0(n3280), .B1(n3730), .C0(n3831), .C1(FPMULT_Op_MY[0]), .Y(n2331) );
OAI21XLTS U2722 ( .A0(n3722), .A1(n3508), .B0(n2300), .Y(n2349) );
OAI21XLTS U2723 ( .A0(n3722), .A1(n3688), .B0(n2301), .Y(n3679) );
INVX2TS U2724 ( .A(n2448), .Y(n3693) );
AOI21X2TS U2725 ( .A0(n4193), .A1(n4191), .B0(n3829), .Y(n4011) );
NOR2X1TS U2726 ( .A(n2488), .B(n2490), .Y(n2366) );
NOR2X1TS U2727 ( .A(n3630), .B(n3625), .Y(n2488) );
NOR2X1TS U2728 ( .A(n3625), .B(n3619), .Y(n2490) );
NOR2X1TS U2729 ( .A(n2547), .B(n2549), .Y(n2484) );
NAND2X1TS U2730 ( .A(n3630), .B(n3625), .Y(n2556) );
NOR2X1TS U2731 ( .A(n3759), .B(n3768), .Y(n2523) );
OAI21XLTS U2732 ( .A0(n3632), .A1(n3410), .B0(n3400), .Y(n3401) );
AOI222X1TS U2733 ( .A0(n3266), .A1(n3624), .B0(n3404), .B1(n3629), .C0(n3210), .C1(n2241), .Y(n3400) );
OA21XLTS U2734 ( .A0(n3734), .A1(n2317), .B0(n2343), .Y(n3197) );
AOI222X1TS U2735 ( .A0(n3235), .A1(n3629), .B0(n3462), .B1(n2241), .C0(n3239), .C1(n2296), .Y(n3264) );
OAI21XLTS U2736 ( .A0(n3699), .A1(n3410), .B0(n3267), .Y(n3268) );
INVX2TS U2737 ( .A(n2427), .Y(n3597) );
BUFX4TS U2738 ( .A(FPMULT_Op_MY[14]), .Y(n5159) );
OAI21XLTS U2739 ( .A0(n3632), .A1(n3508), .B0(n3501), .Y(n3502) );
OAI21XLTS U2740 ( .A0(n3718), .A1(n3410), .B0(n3287), .Y(n3288) );
INVX2TS U2741 ( .A(n2543), .Y(n3616) );
INVX2TS U2742 ( .A(n2490), .Y(n2492) );
OAI21XLTS U2743 ( .A0(n3699), .A1(n3508), .B0(n3249), .Y(n3250) );
OAI21XLTS U2744 ( .A0(n3722), .A1(n3232), .B0(n2299), .Y(n3231) );
INVX2TS U2745 ( .A(n2523), .Y(n2525) );
OAI21XLTS U2746 ( .A0(n3627), .A1(n3410), .B0(n3398), .Y(n3399) );
OAI21XLTS U2747 ( .A0(n3621), .A1(n3371), .B0(n3351), .Y(n3352) );
OAI21XLTS U2748 ( .A0(n3632), .A1(n3371), .B0(n3355), .Y(n3356) );
OA21XLTS U2749 ( .A0(n3722), .A1(n2317), .B0(n2318), .Y(n2323) );
OAI21X1TS U2750 ( .A0(n2511), .A1(n2415), .B0(n2414), .Y(n2453) );
OAI21XLTS U2751 ( .A0(n3718), .A1(n3371), .B0(n3260), .Y(n3261) );
OAI21XLTS U2752 ( .A0(n3699), .A1(n3688), .B0(n3553), .Y(n3554) );
INVX2TS U2753 ( .A(n2536), .Y(n3710) );
NOR2X1TS U2754 ( .A(n3816), .B(n4091), .Y(n3818) );
INVX2TS U2755 ( .A(n2575), .Y(n3579) );
INVX2TS U2756 ( .A(n2335), .Y(n3762) );
OAI21XLTS U2757 ( .A0(n3632), .A1(n3774), .B0(n2582), .Y(n2583) );
INVX2TS U2758 ( .A(n3206), .Y(n3645) );
NAND2X1TS U2759 ( .A(n3721), .B(n3755), .Y(n2338) );
OAI21XLTS U2760 ( .A0(n3734), .A1(n3508), .B0(n3313), .Y(n3314) );
BUFX3TS U2761 ( .A(n2512), .Y(n3833) );
OAI21XLTS U2762 ( .A0(n3734), .A1(n3774), .B0(n3733), .Y(n3735) );
OAI21XLTS U2763 ( .A0(n3775), .A1(n3774), .B0(n3773), .Y(n3777) );
AOI21X1TS U2764 ( .A0(n3995), .A1(n3993), .B0(n3788), .Y(n3950) );
OAI21XLTS U2765 ( .A0(n3621), .A1(n3688), .B0(n3542), .Y(n3543) );
AOI21X1TS U2766 ( .A0(n3957), .A1(n3794), .B0(n3793), .Y(n3868) );
NOR2X1TS U2767 ( .A(n4075), .B(n4073), .Y(n4060) );
OAI21X2TS U2768 ( .A0(n3802), .A1(n3888), .B0(n3801), .Y(n3909) );
OAI21X1TS U2769 ( .A0(n4056), .A1(n4015), .B0(n4014), .Y(n4022) );
OR2X1TS U2770 ( .A(mult_x_69_n757), .B(mult_x_69_n761), .Y(n3953) );
OR2X1TS U2771 ( .A(n3738), .B(n3737), .Y(n3922) );
NOR2XLTS U2772 ( .A(n3977), .B(n3979), .Y(n3752) );
OR2X1TS U2773 ( .A(n3787), .B(n3786), .Y(n3993) );
OR2X1TS U2774 ( .A(mult_x_69_n762), .B(n3789), .Y(n3998) );
OAI21XLTS U2775 ( .A0(n3718), .A1(n3774), .B0(n3717), .Y(n3719) );
AOI222X1TS U2776 ( .A0(n3772), .A1(n3755), .B0(n3771), .B1(n3730), .C0(n3740), .C1(FPMULT_Op_MY[0]), .Y(n3717) );
OR2X1TS U2777 ( .A(mult_x_69_n738), .B(mult_x_69_n744), .Y(n3971) );
OR2X1TS U2778 ( .A(mult_x_69_n731), .B(mult_x_69_n737), .Y(n3871) );
NAND2X1TS U2779 ( .A(n4956), .B(n4443), .Y(n4445) );
AOI22X1TS U2780 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n4910), .B0(n4735), .B1(
n4734), .Y(n4741) );
INVX2TS U2781 ( .A(n4013), .Y(n4056) );
AOI22X1TS U2782 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(n4915), .B0(n4764), .B1(
n4763), .Y(n4770) );
OAI21XLTS U2783 ( .A0(n3722), .A1(n3774), .B0(n2209), .Y(n3723) );
NAND2X1TS U2784 ( .A(n2307), .B(n3910), .Y(n3937) );
OAI32X1TS U2785 ( .A0(n4774), .A1(n4783), .A2(n4517), .B0(n4639), .B1(n4787),
.Y(n4518) );
AOI21X1TS U2786 ( .A0(n4005), .A1(n4003), .B0(n3841), .Y(n3849) );
NOR2X1TS U2787 ( .A(n2359), .B(n2523), .Y(n2464) );
OAI21X1TS U2788 ( .A0(n2548), .A1(n2436), .B0(n2435), .Y(n2568) );
NAND2X1TS U2789 ( .A(n2500), .B(n2504), .Y(n2507) );
NOR2X1TS U2790 ( .A(n2437), .B(n2439), .Y(n2391) );
AOI21X2TS U2791 ( .A0(n2485), .A1(n2366), .B0(n2365), .Y(n2431) );
NAND2X1TS U2792 ( .A(n2484), .B(n2366), .Y(n2429) );
OAI21XLTS U2793 ( .A0(n3710), .A1(n3371), .B0(n3362), .Y(n3363) );
OAI21XLTS U2794 ( .A0(n3616), .A1(n3232), .B0(n3444), .Y(n3445) );
OAI21XLTS U2795 ( .A0(n3833), .A1(n3688), .B0(n3513), .Y(n3514) );
AOI222X1TS U2796 ( .A0(n2327), .A1(n3624), .B0(n3830), .B1(n3629), .C0(n2330), .C1(n2241), .Y(n2555) );
NOR2X1TS U2797 ( .A(n2425), .B(n2476), .Y(n2412) );
NOR2X1TS U2798 ( .A(n5160), .B(n5161), .Y(n2403) );
NOR2X1TS U2799 ( .A(n5161), .B(n3643), .Y(n2405) );
NAND2X1TS U2800 ( .A(n2412), .B(n2398), .Y(n2501) );
NAND2X1TS U2801 ( .A(n3755), .B(n3732), .Y(n2339) );
NOR2X1TS U2802 ( .A(n2403), .B(n2405), .Y(n2500) );
AO21XLTS U2803 ( .A0(n3462), .A1(n3648), .B0(n3446), .Y(n3417) );
NAND2X1TS U2804 ( .A(n5160), .B(n5161), .Y(n2571) );
OAI21XLTS U2805 ( .A0(n3710), .A1(n3508), .B0(n3507), .Y(n3510) );
OAI21XLTS U2806 ( .A0(n4957), .A1(n2352), .B0(n2353), .Y(n2354) );
AOI21X1TS U2807 ( .A0(n2522), .A1(n2464), .B0(n2463), .Y(n2535) );
AO21XLTS U2808 ( .A0(n3506), .A1(n3843), .B0(n3495), .Y(n3469) );
OAI21XLTS U2809 ( .A0(n3627), .A1(n3688), .B0(n3544), .Y(n3545) );
OAI21XLTS U2810 ( .A0(n3762), .A1(n3232), .B0(n3459), .Y(n3460) );
OAI21XLTS U2811 ( .A0(n3693), .A1(n3508), .B0(n3229), .Y(n3230) );
NOR2X1TS U2812 ( .A(n2501), .B(n2507), .Y(n3203) );
AO21XLTS U2813 ( .A0(n3758), .A1(n3648), .B0(n3702), .Y(n3567) );
AOI222X1TS U2814 ( .A0(n3680), .A1(n3573), .B0(n3685), .B1(n3577), .C0(n3684), .C1(FPMULT_Op_MY[18]), .Y(n3524) );
OAI21XLTS U2815 ( .A0(n3775), .A1(n3371), .B0(n3359), .Y(n3360) );
OAI21XLTS U2816 ( .A0(n3693), .A1(n3410), .B0(n3402), .Y(n3403) );
AO21XLTS U2817 ( .A0(n3771), .A1(n3648), .B0(n3725), .Y(n3642) );
OAI21XLTS U2818 ( .A0(n3837), .A1(n3688), .B0(n3512), .Y(n3511) );
AO21XLTS U2819 ( .A0(n3678), .A1(n3648), .B0(n3680), .Y(n3517) );
OAI21XLTS U2820 ( .A0(n3627), .A1(n3371), .B0(n3353), .Y(n3354) );
NAND2BXLTS U2821 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n2707) );
NAND3XLTS U2822 ( .A(n4991), .B(n2705), .C(FPADDSUB_intDX_EWSW[8]), .Y(n2706) );
NOR2XLTS U2823 ( .A(n2703), .B(FPADDSUB_intDY_EWSW[10]), .Y(n2704) );
OAI21XLTS U2824 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n4990), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n2702) );
OAI21XLTS U2825 ( .A0(n3762), .A1(n3371), .B0(n3366), .Y(n3367) );
OAI21XLTS U2826 ( .A0(n3734), .A1(n3371), .B0(n3370), .Y(n3372) );
OAI21XLTS U2827 ( .A0(n3710), .A1(n3410), .B0(n3409), .Y(n3412) );
OAI21XLTS U2828 ( .A0(n3616), .A1(n3508), .B0(n3493), .Y(n3494) );
OAI21X2TS U2829 ( .A0(n2511), .A1(n2501), .B0(n2508), .Y(n2574) );
AOI222X1TS U2830 ( .A0(n3725), .A1(n3573), .B0(n2497), .B1(n3577), .C0(n3740), .C1(FPMULT_Op_MY[18]), .Y(n2576) );
OAI21XLTS U2831 ( .A0(n3762), .A1(n3410), .B0(n3291), .Y(n3292) );
NOR2X1TS U2832 ( .A(n4035), .B(n4033), .Y(n3812) );
OAI21XLTS U2833 ( .A0(n3837), .A1(n3371), .B0(n3323), .Y(n3324) );
OAI21XLTS U2834 ( .A0(n3762), .A1(n3688), .B0(n3555), .Y(n3556) );
OAI21XLTS U2835 ( .A0(n4957), .A1(n3515), .B0(n3681), .Y(n3683) );
INVX2TS U2836 ( .A(n2481), .Y(n3592) );
AO21XLTS U2837 ( .A0(n3404), .A1(n3648), .B0(n3395), .Y(n3211) );
AO21XLTS U2838 ( .A0(n3369), .A1(n3648), .B0(n3350), .Y(n3327) );
OAI21XLTS U2839 ( .A0(n3734), .A1(n3688), .B0(n3557), .Y(n3558) );
INVX2TS U2840 ( .A(n2554), .Y(n3632) );
AND3X2TS U2841 ( .A(n3228), .B(n3227), .C(n3226), .Y(n3505) );
INVX2TS U2842 ( .A(n2454), .Y(n3587) );
OAI21XLTS U2843 ( .A0(n3710), .A1(n3688), .B0(n3551), .Y(n3552) );
INVX2TS U2844 ( .A(n2495), .Y(n3621) );
OAI21XLTS U2845 ( .A0(n3693), .A1(n3688), .B0(n3247), .Y(n3248) );
OAI21XLTS U2846 ( .A0(n3762), .A1(n3508), .B0(n3310), .Y(n3311) );
INVX2TS U2847 ( .A(n2528), .Y(n3699) );
NAND2BXLTS U2848 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n2705) );
NAND2BXLTS U2849 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n2701) );
NAND2BXLTS U2850 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n2720) );
OAI21XLTS U2851 ( .A0(n4957), .A1(n3704), .B0(n3703), .Y(n3705) );
AO21XLTS U2852 ( .A0(n3830), .A1(n3843), .B0(n3281), .Y(n3275) );
INVX2TS U2853 ( .A(n2326), .Y(n3718) );
NOR2X1TS U2854 ( .A(n4016), .B(n4023), .Y(n4086) );
NAND3XLTS U2855 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(n2321),
.C(n2322), .Y(n2821) );
AOI211X2TS U2856 ( .A0(n4583), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n4582),
.C0(n4581), .Y(n4825) );
NOR2X1TS U2857 ( .A(n4052), .B(n4046), .Y(n4029) );
AOI211X2TS U2858 ( .A0(n4583), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n4582),
.C0(n4521), .Y(n4560) );
AOI211X1TS U2859 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n3068), .B0(n3069), .C0(n2998), .Y(n3086) );
NOR2X1TS U2860 ( .A(n3080), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n3045) );
OAI21XLTS U2861 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n4997), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n2723) );
OAI21XLTS U2862 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n4900), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n2731) );
NAND4BXLTS U2863 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n2647), .C(n3865),
.D(n2646), .Y(n2648) );
NOR2XLTS U2864 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n2647) );
OR2X1TS U2865 ( .A(n3721), .B(n3724), .Y(n2316) );
OAI21XLTS U2866 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n2624), .Y(n2625) );
NAND2X1TS U2867 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n3152) );
OR2X1TS U2868 ( .A(n3840), .B(n3839), .Y(n4003) );
OR2X1TS U2869 ( .A(n3845), .B(n3844), .Y(n3847) );
AO21XLTS U2870 ( .A0(n4246), .A1(begin_operation), .B0(n5231), .Y(n2671) );
NAND2X1TS U2871 ( .A(FPADDSUB_DmP_mant_SFG_SWR[2]), .B(FPADDSUB_DMP_SFG[0]),
.Y(n4648) );
NAND3XLTS U2872 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4870),
.C(n4899), .Y(n2659) );
NOR2XLTS U2873 ( .A(n4799), .B(n4526), .Y(n4543) );
NOR2XLTS U2874 ( .A(n4793), .B(n4526), .Y(n4546) );
NOR2XLTS U2875 ( .A(n4557), .B(n4526), .Y(n4555) );
NOR2XLTS U2876 ( .A(n4557), .B(n4556), .Y(n4558) );
NOR2XLTS U2877 ( .A(n4807), .B(n4526), .Y(n4568) );
NOR2XLTS U2878 ( .A(n4825), .B(n4526), .Y(n4584) );
NOR2XLTS U2879 ( .A(n4745), .B(n4556), .Y(n4746) );
NOR2XLTS U2880 ( .A(n4793), .B(n4556), .Y(n4794) );
NOR2XLTS U2881 ( .A(n4825), .B(n4556), .Y(n4796) );
NOR2XLTS U2882 ( .A(n4799), .B(n4556), .Y(n4800) );
NOR2XLTS U2883 ( .A(n4802), .B(n4556), .Y(n4803) );
NOR2XLTS U2884 ( .A(n4807), .B(n4556), .Y(n4809) );
NOR2XLTS U2885 ( .A(n4745), .B(n4526), .Y(n4539) );
NOR2XLTS U2886 ( .A(n4802), .B(n4526), .Y(n4552) );
OAI21XLTS U2887 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n3660), .B0(n3659), .Y(
n3661) );
CLKAND2X2TS U2888 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n2653), .Y(n2655)
);
INVX4TS U2889 ( .A(n4333), .Y(n4401) );
OAI211XLTS U2890 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4457), .B0(
n4478), .C0(n4459), .Y(n4458) );
OAI211XLTS U2891 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4461), .B0(
n4478), .C0(n4463), .Y(n4462) );
OAI211XLTS U2892 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4465), .B0(
n4478), .C0(n4467), .Y(n4466) );
OAI211XLTS U2893 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4469), .B0(
n4478), .C0(n4471), .Y(n4470) );
OAI211XLTS U2894 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4473), .B0(
n4478), .C0(n4476), .Y(n4474) );
AO22XLTS U2895 ( .A0(n4410), .A1(result_add_subt[22]), .B0(n4409), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(n2008) );
AO22XLTS U2896 ( .A0(n4295), .A1(result_add_subt[5]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[5]), .Y(n2060) );
AO22XLTS U2897 ( .A0(n4295), .A1(result_add_subt[9]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[9]), .Y(n2048) );
AO22XLTS U2898 ( .A0(n4295), .A1(result_add_subt[1]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[1]), .Y(n2072) );
AO22XLTS U2899 ( .A0(n4295), .A1(result_add_subt[0]), .B0(n4299), .B1(
FPSENCOS_d_ff_Yn[0]), .Y(n2075) );
AO22XLTS U2900 ( .A0(n4295), .A1(result_add_subt[7]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[7]), .Y(n2054) );
AO22XLTS U2901 ( .A0(n4404), .A1(result_add_subt[2]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[2]), .Y(n2069) );
AO22XLTS U2902 ( .A0(n4295), .A1(result_add_subt[3]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[3]), .Y(n2066) );
AO22XLTS U2903 ( .A0(n4295), .A1(result_add_subt[14]), .B0(n4299), .B1(
FPSENCOS_d_ff_Yn[14]), .Y(n2033) );
AO22XLTS U2904 ( .A0(n4404), .A1(result_add_subt[8]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[8]), .Y(n2051) );
AO22XLTS U2905 ( .A0(n4295), .A1(result_add_subt[16]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[16]), .Y(n2027) );
AO22XLTS U2906 ( .A0(n4404), .A1(result_add_subt[13]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[13]), .Y(n2036) );
AO22XLTS U2907 ( .A0(n4404), .A1(result_add_subt[6]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[6]), .Y(n2057) );
AO22XLTS U2908 ( .A0(n4404), .A1(result_add_subt[4]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[4]), .Y(n2063) );
AO22XLTS U2909 ( .A0(n4295), .A1(result_add_subt[17]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[17]), .Y(n2024) );
AO22XLTS U2910 ( .A0(n4404), .A1(result_add_subt[18]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[18]), .Y(n2021) );
AO22XLTS U2911 ( .A0(n4404), .A1(result_add_subt[15]), .B0(n4299), .B1(
FPSENCOS_d_ff_Yn[15]), .Y(n2030) );
AO22XLTS U2912 ( .A0(n4488), .A1(n4456), .B0(n4483), .B1(
FPMULT_Add_result[10]), .Y(n1614) );
AO22XLTS U2913 ( .A0(n4488), .A1(n4460), .B0(n4483), .B1(
FPMULT_Add_result[12]), .Y(n1612) );
AO22XLTS U2914 ( .A0(n4488), .A1(n4464), .B0(n4483), .B1(
FPMULT_Add_result[14]), .Y(n1610) );
AO22XLTS U2915 ( .A0(n4488), .A1(n4468), .B0(n4483), .B1(
FPMULT_Add_result[16]), .Y(n1608) );
OAI211XLTS U2916 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4453), .B0(
n4478), .C0(n4455), .Y(n4454) );
AO22XLTS U2917 ( .A0(n4294), .A1(result_add_subt[27]), .B0(n4396), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(n1774) );
AO22XLTS U2918 ( .A0(n4410), .A1(result_add_subt[25]), .B0(n4409), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(n1780) );
AO22XLTS U2919 ( .A0(n4300), .A1(result_add_subt[24]), .B0(n4396), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(n1783) );
AO22XLTS U2920 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n4320), .B0(
FPSENCOS_d_ff_Xn[4]), .B1(n4319), .Y(n1999) );
AO22XLTS U2921 ( .A0(FPSENCOS_d_ff2_X[0]), .A1(n4320), .B0(
FPSENCOS_d_ff_Xn[0]), .B1(n4319), .Y(n2007) );
AO22XLTS U2922 ( .A0(FPSENCOS_d_ff2_X[8]), .A1(n4312), .B0(
FPSENCOS_d_ff_Xn[8]), .B1(n2249), .Y(n1991) );
AO22XLTS U2923 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n4313), .B0(
FPSENCOS_d_ff_Xn[22]), .B1(n2249), .Y(n1963) );
AO22XLTS U2924 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n4312), .B0(
FPSENCOS_d_ff_Xn[18]), .B1(n2249), .Y(n1971) );
AO22XLTS U2925 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n4312), .B0(
FPSENCOS_d_ff_Xn[11]), .B1(n2249), .Y(n1985) );
AO22XLTS U2926 ( .A0(n4488), .A1(n4444), .B0(n4483), .B1(
FPMULT_Add_result[4]), .Y(n1620) );
AO22XLTS U2927 ( .A0(n4488), .A1(n4452), .B0(n4483), .B1(
FPMULT_Add_result[8]), .Y(n1616) );
AO22XLTS U2928 ( .A0(n4488), .A1(n4448), .B0(n4483), .B1(
FPMULT_Add_result[6]), .Y(n1618) );
AOI222X1TS U2929 ( .A0(n2885), .A1(cordic_result[7]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[7]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[7]), .Y(n2873)
);
AOI222X1TS U2930 ( .A0(n2885), .A1(cordic_result[9]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[9]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[9]), .Y(n2886)
);
AOI222X1TS U2931 ( .A0(n2885), .A1(cordic_result[8]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[8]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[8]), .Y(n2878)
);
AOI222X1TS U2932 ( .A0(n2823), .A1(cordic_result[16]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[16]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[16]), .Y(n2875) );
AOI222X1TS U2933 ( .A0(n2885), .A1(cordic_result[6]), .B0(n2865), .B1(
FPSENCOS_d_ff_Yn[6]), .C0(n2887), .C1(FPSENCOS_d_ff_Xn[6]), .Y(n2871)
);
AOI222X1TS U2934 ( .A0(n2823), .A1(cordic_result[17]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[17]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[17]), .Y(n2879) );
AOI222X1TS U2935 ( .A0(n2823), .A1(cordic_result[18]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[18]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[18]), .Y(n2877) );
AOI222X1TS U2936 ( .A0(n2823), .A1(cordic_result[15]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[15]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[15]), .Y(n2884) );
MX2X1TS U2937 ( .A(FPMULT_P_Sgf[13]), .B(n3975), .S0(n3974), .Y(n1566) );
MX2X1TS U2938 ( .A(FPMULT_P_Sgf[11]), .B(n3960), .S0(n3974), .Y(n1564) );
MX2X1TS U2939 ( .A(FPMULT_P_Sgf[12]), .B(n3969), .S0(n3974), .Y(n1565) );
MX2X1TS U2940 ( .A(FPMULT_P_Sgf[10]), .B(n3956), .S0(n3974), .Y(n1563) );
MX2X1TS U2941 ( .A(FPMULT_P_Sgf[3]), .B(n3925), .S0(n3974), .Y(n1556) );
MX2X1TS U2942 ( .A(FPMULT_P_Sgf[4]), .B(n3931), .S0(n3974), .Y(n1557) );
MX2X1TS U2943 ( .A(FPMULT_P_Sgf[6]), .B(n3985), .S0(n4194), .Y(n1559) );
AO22XLTS U2944 ( .A0(n4255), .A1(n4753), .B0(n4257), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2146) );
MX2X1TS U2945 ( .A(FPMULT_P_Sgf[7]), .B(n3991), .S0(n4194), .Y(n1560) );
AO22XLTS U2946 ( .A0(n4294), .A1(result_add_subt[26]), .B0(n4396), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(n1777) );
AO22XLTS U2947 ( .A0(FPSENCOS_d_ff2_X[21]), .A1(n4312), .B0(
FPSENCOS_d_ff_Xn[21]), .B1(n2249), .Y(n1965) );
MX2X1TS U2948 ( .A(FPMULT_P_Sgf[8]), .B(n3996), .S0(n4194), .Y(n1561) );
MX2X1TS U2949 ( .A(FPMULT_P_Sgf[9]), .B(n4001), .S0(n4194), .Y(n1562) );
MX2X1TS U2950 ( .A(FPMULT_P_Sgf[15]), .B(n3878), .S0(n3984), .Y(n1568) );
MX2X1TS U2951 ( .A(FPMULT_P_Sgf[16]), .B(n3887), .S0(n3984), .Y(n1569) );
MX2X1TS U2952 ( .A(FPMULT_P_Sgf[17]), .B(n3891), .S0(n3984), .Y(n1570) );
MX2X1TS U2953 ( .A(FPMULT_P_Sgf[19]), .B(n3908), .S0(n3974), .Y(n1572) );
MX2X1TS U2954 ( .A(FPMULT_P_Sgf[20]), .B(n3912), .S0(n3974), .Y(n1573) );
MX2X1TS U2955 ( .A(FPMULT_P_Sgf[21]), .B(n3918), .S0(n3974), .Y(n1574) );
MX2X1TS U2956 ( .A(FPMULT_P_Sgf[2]), .B(n3920), .S0(n3974), .Y(n1555) );
AO22XLTS U2957 ( .A0(n4257), .A1(busy), .B0(n4255), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2147) );
AO22XLTS U2958 ( .A0(FPSENCOS_d_ff2_X[15]), .A1(n4312), .B0(
FPSENCOS_d_ff_Xn[15]), .B1(n2249), .Y(n1977) );
NAND2BXLTS U2959 ( .AN(n4276), .B(n4275), .Y(n2125) );
NOR2XLTS U2960 ( .A(n2206), .B(n4280), .Y(n4282) );
MX2X1TS U2961 ( .A(FPMULT_P_Sgf[23]), .B(n4085), .S0(n4185), .Y(n1576) );
MX2X1TS U2962 ( .A(FPMULT_P_Sgf[18]), .B(n3900), .S0(n3974), .Y(n1571) );
MX2X1TS U2963 ( .A(FPMULT_P_Sgf[14]), .B(n3874), .S0(n3984), .Y(n1567) );
MX2X1TS U2964 ( .A(FPMULT_P_Sgf[5]), .B(n3935), .S0(n3974), .Y(n1558) );
AO22XLTS U2965 ( .A0(n4404), .A1(result_add_subt[19]), .B0(n4301), .B1(
FPSENCOS_d_ff_Yn[19]), .Y(n2018) );
AO22XLTS U2966 ( .A0(n4294), .A1(result_add_subt[15]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(n2029) );
AO22XLTS U2967 ( .A0(n4410), .A1(result_add_subt[18]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(n2020) );
AO22XLTS U2968 ( .A0(n4410), .A1(result_add_subt[21]), .B0(n4396), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(n2011) );
AO22XLTS U2969 ( .A0(n4300), .A1(result_add_subt[4]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(n2062) );
AO22XLTS U2970 ( .A0(n4300), .A1(result_add_subt[8]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(n2050) );
AO22XLTS U2971 ( .A0(n4294), .A1(result_add_subt[11]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(n2041) );
AO22XLTS U2972 ( .A0(n4294), .A1(result_add_subt[9]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(n2047) );
AO22XLTS U2973 ( .A0(n4410), .A1(result_add_subt[28]), .B0(n4396), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(n1771) );
AO22XLTS U2974 ( .A0(n4410), .A1(result_add_subt[19]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(n2017) );
AO22XLTS U2975 ( .A0(n4410), .A1(result_add_subt[20]), .B0(n4396), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(n2014) );
AO22XLTS U2976 ( .A0(n4294), .A1(result_add_subt[17]), .B0(n4409), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(n2023) );
AO22XLTS U2977 ( .A0(n4300), .A1(result_add_subt[6]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(n2056) );
AO22XLTS U2978 ( .A0(n4294), .A1(result_add_subt[13]), .B0(n4409), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(n2035) );
AO22XLTS U2979 ( .A0(n4300), .A1(result_add_subt[16]), .B0(n4409), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(n2026) );
AO22XLTS U2980 ( .A0(n4300), .A1(result_add_subt[14]), .B0(n4409), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(n2032) );
AO22XLTS U2981 ( .A0(n4300), .A1(result_add_subt[10]), .B0(n4409), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(n2044) );
AO22XLTS U2982 ( .A0(n4300), .A1(result_add_subt[12]), .B0(n4409), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(n2038) );
AO22XLTS U2983 ( .A0(n4294), .A1(result_add_subt[3]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(n2065) );
AO22XLTS U2984 ( .A0(n4300), .A1(result_add_subt[2]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(n2068) );
AO22XLTS U2985 ( .A0(n4294), .A1(result_add_subt[7]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(n2053) );
AO22XLTS U2986 ( .A0(n4294), .A1(result_add_subt[1]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(n2071) );
AO22XLTS U2987 ( .A0(n4294), .A1(result_add_subt[5]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(n2059) );
MX2X1TS U2988 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_exp_oper_result[5]), .S0(n3855), .Y(n1544) );
MX2X1TS U2989 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_exp_oper_result[6]), .S0(n3855), .Y(n1543) );
MX2X1TS U2990 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_exp_oper_result[7]), .S0(n3855), .Y(n1542) );
OAI211XLTS U2991 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4445), .B0(
n4478), .C0(n4447), .Y(n4446) );
OAI211XLTS U2992 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4441), .B0(
n4478), .C0(n4443), .Y(n4442) );
OAI211XLTS U2993 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4449), .B0(
n4478), .C0(n4451), .Y(n4450) );
AO22XLTS U2994 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n4312), .B0(
FPSENCOS_d_ff_Xn[30]), .B1(n2249), .Y(n1954) );
AOI222X1TS U2995 ( .A0(n2813), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DmP_EXP_EWSW[23]), .B1(n4637), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n2869), .Y(n2870) );
AO22XLTS U2996 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n4312), .B0(
FPSENCOS_d_ff_Xn[23]), .B1(n2249), .Y(n1961) );
MX2X1TS U2997 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(n3858), .S0(n3984),
.Y(n1540) );
AO22XLTS U2998 ( .A0(n4529), .A1(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B0(n5090),
.B1(result_add_subt[30]), .Y(n1468) );
OAI21XLTS U2999 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n5011), .B0(n4750),
.Y(n4751) );
AOI2BB2XLTS U3000 ( .B0(n4865), .B1(n4859), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[24]), .A1N(n4865), .Y(n1183) );
NAND3XLTS U3001 ( .A(n4231), .B(n4283), .C(n4241), .Y(n4232) );
NAND3XLTS U3002 ( .A(n3671), .B(n3857), .C(n3670), .Y(n1692) );
AOI211XLTS U3003 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(n3669), .B0(n4434), .C0(n4492), .Y(n3671) );
AOI2BB2XLTS U3004 ( .B0(n2246), .B1(n4832), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[2]), .A1N(n4820), .Y(n1205) );
OAI21XLTS U3005 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[23]), .A1(n5063), .B0(n4778),
.Y(n4779) );
OAI32X1TS U3006 ( .A0(n4287), .A1(n2677), .A2(n3008), .B0(n4881), .B1(n4291),
.Y(n2082) );
OAI21XLTS U3007 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(n5004), .B0(n4735),
.Y(n4736) );
OAI21XLTS U3008 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n5056), .B0(n4764),
.Y(n4765) );
OAI21XLTS U3009 ( .A0(n5235), .A1(n4913), .B0(n2657), .Y(n1358) );
AO22XLTS U3010 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[23]), .B1(n4317), .Y(n1863) );
AO22XLTS U3011 ( .A0(n4287), .A1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.B0(n4291), .B1(region_flag[1]), .Y(n2136) );
MX2X1TS U3012 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_exp_oper_result[8]), .S0(n3855), .Y(n1541) );
AOI2BB2XLTS U3013 ( .B0(n5090), .B1(n5038), .A0N(n3867), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n1470) );
AOI2BB2XLTS U3014 ( .B0(n5090), .B1(n5039), .A0N(n3867), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(n1471) );
AOI2BB2XLTS U3015 ( .B0(n5090), .B1(n5040), .A0N(n3867), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n1474) );
AO22XLTS U3016 ( .A0(n4287), .A1(FPSENCOS_d_ff1_shift_region_flag_out[0]),
.B0(n4288), .B1(region_flag[0]), .Y(n2137) );
AO22XLTS U3017 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4320), .B0(
FPSENCOS_d_ff_Yn[29]), .B1(n4319), .Y(n1857) );
AO22XLTS U3018 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n4320), .B0(
FPSENCOS_d_ff_Yn[27]), .B1(n4319), .Y(n1859) );
AO22XLTS U3019 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n4320), .B0(
FPSENCOS_d_ff_Yn[30]), .B1(n4319), .Y(n1856) );
NAND3BXLTS U3020 ( .AN(FPMULT_Exp_module_Data_S[7]), .B(n4434), .C(n3863),
.Y(n3864) );
AO22XLTS U3021 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[24]), .B1(n4317), .Y(n1862) );
AO22XLTS U3022 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[25]), .B1(n4317), .Y(n1861) );
AO22XLTS U3023 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[26]), .B1(n4317), .Y(n1860) );
MX2X1TS U3024 ( .A(FPMULT_P_Sgf[27]), .B(n4057), .S0(n4194), .Y(n1580) );
MX2X1TS U3025 ( .A(FPMULT_P_Sgf[24]), .B(n4080), .S0(n4185), .Y(n1577) );
NAND3XLTS U3026 ( .A(n4211), .B(n4210), .C(n4209), .Y(n5150) );
OAI21XLTS U3027 ( .A0(n4923), .A1(n2845), .B0(n2795), .Y(n1211) );
OAI21XLTS U3028 ( .A0(n5055), .A1(n4515), .B0(n2814), .Y(n1215) );
OAI21XLTS U3029 ( .A0(n4922), .A1(n4515), .B0(n2818), .Y(n1219) );
OAI21XLTS U3030 ( .A0(n5054), .A1(n4515), .B0(n2815), .Y(n1223) );
OAI21XLTS U3031 ( .A0(n4916), .A1(n4515), .B0(n2819), .Y(n1231) );
OAI21XLTS U3032 ( .A0(n5052), .A1(n4515), .B0(n2817), .Y(n1235) );
OAI21XLTS U3033 ( .A0(n4919), .A1(n2845), .B0(n2831), .Y(n1239) );
OAI21XLTS U3034 ( .A0(n4918), .A1(n2845), .B0(n2832), .Y(n1243) );
OAI21XLTS U3035 ( .A0(n5053), .A1(n2845), .B0(n2816), .Y(n1247) );
OAI21XLTS U3036 ( .A0(n5046), .A1(n2845), .B0(n2830), .Y(n1251) );
OAI21XLTS U3037 ( .A0(n5042), .A1(n2845), .B0(n2746), .Y(n1255) );
OAI21XLTS U3038 ( .A0(n5051), .A1(n2845), .B0(n2744), .Y(n1259) );
OAI21XLTS U3039 ( .A0(n4921), .A1(n2845), .B0(n2794), .Y(n1263) );
OAI21XLTS U3040 ( .A0(n5045), .A1(n2845), .B0(n2841), .Y(n1267) );
OAI21XLTS U3041 ( .A0(n4920), .A1(n2793), .B0(n2773), .Y(n1273) );
OAI21XLTS U3042 ( .A0(n5060), .A1(n2845), .B0(n2844), .Y(n1277) );
OAI21XLTS U3043 ( .A0(n5060), .A1(n2793), .B0(n2792), .Y(n1279) );
OAI21XLTS U3044 ( .A0(n5050), .A1(n2845), .B0(n2796), .Y(n1284) );
OAI21XLTS U3045 ( .A0(n5050), .A1(n2793), .B0(n2791), .Y(n1286) );
OAI21XLTS U3046 ( .A0(n5049), .A1(n2845), .B0(n2745), .Y(n1291) );
OAI21XLTS U3047 ( .A0(n5049), .A1(n2793), .B0(n2774), .Y(n1293) );
OAI21XLTS U3048 ( .A0(n5061), .A1(n2843), .B0(n2747), .Y(n1298) );
OAI21XLTS U3049 ( .A0(n5061), .A1(n2793), .B0(n2790), .Y(n1300) );
OAI21XLTS U3050 ( .A0(n5057), .A1(n2812), .B0(n2802), .Y(n1305) );
OAI21XLTS U3051 ( .A0(n5069), .A1(n2812), .B0(n2800), .Y(n1307) );
OAI21XLTS U3052 ( .A0(n5043), .A1(n2843), .B0(n2842), .Y(n1312) );
OAI21XLTS U3053 ( .A0(n5043), .A1(n2812), .B0(n2809), .Y(n1314) );
AO21XLTS U3054 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n4256), .B0(n3860),
.Y(n1316) );
OAI21XLTS U3055 ( .A0(n4917), .A1(n2843), .B0(n2837), .Y(n1328) );
OAI21XLTS U3056 ( .A0(n4917), .A1(n2812), .B0(n2808), .Y(n1330) );
AOI2BB2XLTS U3057 ( .B0(n5156), .B1(n4633), .A0N(FPADDSUB_SIGN_FLAG_EXP),
.A1N(n5156), .Y(n1364) );
AOI31XLTS U3058 ( .A0(n4630), .A1(n4629), .A2(n4628), .B0(n4631), .Y(n4632)
);
OAI21XLTS U3059 ( .A0(n5045), .A1(n2812), .B0(n2801), .Y(n1367) );
OAI21XLTS U3060 ( .A0(n4921), .A1(n2812), .B0(n2807), .Y(n1370) );
OAI21XLTS U3061 ( .A0(n5051), .A1(n2812), .B0(n2804), .Y(n1373) );
OAI21XLTS U3062 ( .A0(n5042), .A1(n2812), .B0(n2811), .Y(n1376) );
OAI21XLTS U3063 ( .A0(n5046), .A1(n2812), .B0(n2798), .Y(n1379) );
OAI21XLTS U3064 ( .A0(n5053), .A1(n2812), .B0(n2806), .Y(n1382) );
OAI21XLTS U3065 ( .A0(n4918), .A1(n2812), .B0(n2797), .Y(n1385) );
OAI21XLTS U3066 ( .A0(n4919), .A1(n2812), .B0(n2799), .Y(n1388) );
OAI21XLTS U3067 ( .A0(n5052), .A1(n2812), .B0(n2803), .Y(n1391) );
OAI21XLTS U3068 ( .A0(n4916), .A1(n4514), .B0(n2756), .Y(n1394) );
OAI21XLTS U3069 ( .A0(n5054), .A1(n4514), .B0(n2752), .Y(n1400) );
OAI21XLTS U3070 ( .A0(n4922), .A1(n4514), .B0(n2751), .Y(n1403) );
OAI21XLTS U3071 ( .A0(n5055), .A1(n4514), .B0(n2755), .Y(n1406) );
OAI21XLTS U3072 ( .A0(n4923), .A1(n4514), .B0(n2754), .Y(n1409) );
MX2X1TS U3073 ( .A(n3859), .B(FPADDSUB_LZD_output_NRM2_EW[1]), .S0(n4256),
.Y(n1411) );
AO21XLTS U3074 ( .A0(underflow_flag_addsubt), .A1(n5090), .B0(n4516), .Y(
n1414) );
OAI21XLTS U3075 ( .A0(n4924), .A1(n2843), .B0(n2834), .Y(n1461) );
OAI21XLTS U3076 ( .A0(n5067), .A1(n2843), .B0(n2839), .Y(n1462) );
MX2X1TS U3077 ( .A(FPMULT_P_Sgf[22]), .B(n3944), .S0(n3974), .Y(n1575) );
AO22XLTS U3078 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[5]), .B1(n4315), .Y(n1899) );
AO22XLTS U3079 ( .A0(n4397), .A1(result_add_subt[5]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(n2061) );
AO22XLTS U3080 ( .A0(n2271), .A1(n4312), .B0(FPSENCOS_d_ff_Xn[9]), .B1(n2249), .Y(n1989) );
AO22XLTS U3081 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[9]), .B1(n4315), .Y(n1891) );
AO22XLTS U3082 ( .A0(n4397), .A1(result_add_subt[9]), .B0(n4296), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(n2049) );
AO22XLTS U3083 ( .A0(n4332), .A1(FPSENCOS_d_ff3_sh_x_out[1]), .B0(n4303),
.B1(FPSENCOS_d_ff2_X[1]), .Y(n2004) );
AO22XLTS U3084 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[1]), .B1(n4315), .Y(n1907) );
AO22XLTS U3085 ( .A0(n4397), .A1(result_add_subt[1]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(n2073) );
AO22XLTS U3086 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[0]), .B1(n2249), .Y(n1909) );
AO22XLTS U3087 ( .A0(n4298), .A1(result_add_subt[0]), .B0(n4296), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(n2076) );
AO22XLTS U3088 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[7]), .B1(n4315), .Y(n1895) );
AO22XLTS U3089 ( .A0(n4401), .A1(FPSENCOS_d_ff3_sh_x_out[2]), .B0(n4303),
.B1(FPSENCOS_d_ff2_X[2]), .Y(n2002) );
AO22XLTS U3090 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[2]), .B1(n4315), .Y(n1905) );
AO22XLTS U3091 ( .A0(n4298), .A1(result_add_subt[2]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(n2070) );
AO22XLTS U3092 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[3]), .B1(n4315), .Y(n1903) );
AO22XLTS U3093 ( .A0(n4397), .A1(result_add_subt[3]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(n2067) );
AO22XLTS U3094 ( .A0(FPSENCOS_d_ff_Xn[31]), .A1(n4319), .B0(n2270), .B1(
n4312), .Y(n1945) );
AO22XLTS U3095 ( .A0(n4397), .A1(result_add_subt[31]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(n1911) );
AO22XLTS U3096 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[12]), .B1(n4315), .Y(n1885) );
AO22XLTS U3097 ( .A0(n4400), .A1(result_add_subt[12]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(n2040) );
AO22XLTS U3098 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[10]), .B1(n4315), .Y(n1889) );
AO22XLTS U3099 ( .A0(n4298), .A1(result_add_subt[10]), .B0(n4296), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(n2046) );
AO22XLTS U3100 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[14]), .B1(n4317), .Y(n1881) );
AO22XLTS U3101 ( .A0(n4400), .A1(result_add_subt[14]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(n2034) );
AO22XLTS U3102 ( .A0(n4402), .A1(FPSENCOS_d_ff2_X[11]), .B0(n4306), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1984) );
AO22XLTS U3103 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[11]), .B1(n4315), .Y(n1887) );
AO22XLTS U3104 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[8]), .B1(n4315), .Y(n1893) );
AO22XLTS U3105 ( .A0(n4298), .A1(result_add_subt[8]), .B0(n4296), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(n2052) );
AO22XLTS U3106 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[16]), .B1(n4317), .Y(n1877) );
AO22XLTS U3107 ( .A0(n4400), .A1(result_add_subt[16]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(n2028) );
AO22XLTS U3108 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[13]), .B1(n4315), .Y(n1883) );
AO22XLTS U3109 ( .A0(n4400), .A1(result_add_subt[13]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(n2037) );
AO22XLTS U3110 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[6]), .B1(n4315), .Y(n1897) );
AO22XLTS U3111 ( .A0(n4298), .A1(result_add_subt[6]), .B0(n4297), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(n2058) );
AO22XLTS U3112 ( .A0(n4302), .A1(FPSENCOS_d_ff3_sh_x_out[4]), .B0(n4303),
.B1(FPSENCOS_d_ff2_X[4]), .Y(n1998) );
AO22XLTS U3113 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n4313), .B0(
FPSENCOS_d_ff_Yn[4]), .B1(n4315), .Y(n1901) );
AO22XLTS U3114 ( .A0(n4298), .A1(result_add_subt[4]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(n2064) );
AO22XLTS U3115 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[17]), .B1(n4317), .Y(n1875) );
AO22XLTS U3116 ( .A0(n4400), .A1(result_add_subt[17]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(n2025) );
AO22XLTS U3117 ( .A0(n4402), .A1(FPSENCOS_d_ff2_X[20]), .B0(n4302), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1966) );
AO22XLTS U3118 ( .A0(n4402), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n4332), .B1(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1868) );
AO22XLTS U3119 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[20]), .B1(n4317), .Y(n1869) );
AO22XLTS U3120 ( .A0(n4400), .A1(result_add_subt[20]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(n2016) );
AO22XLTS U3121 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[19]), .B1(n4317), .Y(n1871) );
AO22XLTS U3122 ( .A0(n4400), .A1(result_add_subt[19]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(n2019) );
AO22XLTS U3123 ( .A0(n4306), .A1(FPSENCOS_d_ff3_sh_x_out[21]), .B0(n4327),
.B1(FPSENCOS_d_ff2_X[21]), .Y(n1964) );
AO22XLTS U3124 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[21]), .B1(n4317), .Y(n1867) );
AO22XLTS U3125 ( .A0(n4397), .A1(result_add_subt[21]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(n2013) );
AO22XLTS U3126 ( .A0(n4402), .A1(FPSENCOS_d_ff2_X[18]), .B0(n4401), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1970) );
AO22XLTS U3127 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[18]), .B1(n4317), .Y(n1873) );
AO22XLTS U3128 ( .A0(n4400), .A1(result_add_subt[18]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(n2022) );
AO22XLTS U3129 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[15]), .B1(n4317), .Y(n1879) );
AO22XLTS U3130 ( .A0(n4400), .A1(result_add_subt[15]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(n2031) );
AO22XLTS U3131 ( .A0(n4402), .A1(FPSENCOS_d_ff2_X[22]), .B0(n4401), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1962) );
AO22XLTS U3132 ( .A0(n4333), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n4302), .B1(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1864) );
AO22XLTS U3133 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n4318), .B0(
FPSENCOS_d_ff_Yn[22]), .B1(n4317), .Y(n1865) );
AO22XLTS U3134 ( .A0(n4298), .A1(result_add_subt[22]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(n2010) );
AO22XLTS U3135 ( .A0(n4397), .A1(result_add_subt[30]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(n1767) );
AO22XLTS U3136 ( .A0(n4298), .A1(result_add_subt[29]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(n1770) );
AO22XLTS U3137 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n4320), .B0(
FPSENCOS_d_ff_Yn[28]), .B1(n4319), .Y(n1858) );
AO22XLTS U3138 ( .A0(n4400), .A1(result_add_subt[28]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(n1773) );
AO22XLTS U3139 ( .A0(n4400), .A1(result_add_subt[27]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(n1776) );
AO22XLTS U3140 ( .A0(n4397), .A1(result_add_subt[26]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(n1779) );
AO22XLTS U3141 ( .A0(n4298), .A1(result_add_subt[25]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(n1782) );
AO22XLTS U3142 ( .A0(n4397), .A1(result_add_subt[24]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(n1785) );
AO22XLTS U3143 ( .A0(n4298), .A1(result_add_subt[23]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(n1788) );
AO22XLTS U3144 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n4292), .B1(
Data_1[31]), .Y(n2083) );
AO22XLTS U3145 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n4291), .B1(
Data_1[30]), .Y(n2084) );
AO22XLTS U3146 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n4291), .B1(
Data_1[29]), .Y(n2085) );
AO22XLTS U3147 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n4290), .B1(
Data_1[28]), .Y(n2086) );
AO22XLTS U3148 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n4291), .B1(
Data_1[27]), .Y(n2087) );
AO22XLTS U3149 ( .A0(n4287), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n4288), .B1(
Data_1[19]), .Y(n2095) );
AO22XLTS U3150 ( .A0(n4287), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n4288), .B1(
Data_1[18]), .Y(n2096) );
AO22XLTS U3151 ( .A0(n4287), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n4288), .B1(
Data_1[17]), .Y(n2097) );
AO22XLTS U3152 ( .A0(n4287), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n4288), .B1(
Data_1[16]), .Y(n2098) );
AO22XLTS U3153 ( .A0(n4287), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n4288), .B1(
Data_1[15]), .Y(n2099) );
AO22XLTS U3154 ( .A0(n4287), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n4288), .B1(
Data_1[14]), .Y(n2100) );
AO22XLTS U3155 ( .A0(n4287), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n4288), .B1(
Data_1[13]), .Y(n2101) );
AO22XLTS U3156 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n4290), .B1(
Data_1[12]), .Y(n2102) );
AO22XLTS U3157 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n4290), .B1(
Data_1[11]), .Y(n2103) );
AO22XLTS U3158 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n4290), .B1(
Data_1[10]), .Y(n2104) );
AO22XLTS U3159 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n4290), .B1(
Data_1[9]), .Y(n2105) );
AO22XLTS U3160 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n4290), .B1(
Data_1[8]), .Y(n2106) );
AO22XLTS U3161 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n4290), .B1(
Data_1[7]), .Y(n2107) );
AO22XLTS U3162 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n4290), .B1(
Data_1[6]), .Y(n2108) );
AO22XLTS U3163 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n4290), .B1(
Data_1[5]), .Y(n2109) );
AO22XLTS U3164 ( .A0(n4293), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n4290), .B1(
Data_1[4]), .Y(n2110) );
AO22XLTS U3165 ( .A0(n4287), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n4290), .B1(
Data_1[3]), .Y(n2111) );
AO22XLTS U3166 ( .A0(n4287), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n4290), .B1(
Data_1[2]), .Y(n2112) );
AO22XLTS U3167 ( .A0(n4287), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n4291), .B1(
Data_1[1]), .Y(n2113) );
AO22XLTS U3168 ( .A0(n4287), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n4291), .B1(
Data_1[0]), .Y(n2114) );
AO22XLTS U3169 ( .A0(n4402), .A1(n4311), .B0(n4401), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1946) );
AOI2BB2XLTS U3170 ( .B0(n4322), .B1(n4309), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n4327), .Y(n1947) );
AO22XLTS U3171 ( .A0(n4402), .A1(n4307), .B0(n4302), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1948) );
OAI21XLTS U3172 ( .A0(n4305), .A1(n5082), .B0(n4308), .Y(n4307) );
AOI2BB2XLTS U3173 ( .B0(n4322), .B1(n4304), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n4327), .Y(n1949) );
AO22XLTS U3174 ( .A0(n4302), .A1(FPSENCOS_d_ff3_sh_x_out[26]), .B0(n4327),
.B1(intadd_490_SUM_2_), .Y(n1950) );
AO22XLTS U3175 ( .A0(n4401), .A1(FPSENCOS_d_ff3_sh_x_out[25]), .B0(n4327),
.B1(intadd_490_SUM_1_), .Y(n1951) );
AO22XLTS U3176 ( .A0(n4401), .A1(FPSENCOS_d_ff3_sh_x_out[24]), .B0(n4327),
.B1(intadd_490_SUM_0_), .Y(n1952) );
OAI21XLTS U3177 ( .A0(n4283), .A1(intadd_490_CI), .B0(n2619), .Y(n1953) );
AO22XLTS U3178 ( .A0(n4333), .A1(n4330), .B0(n4302), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1848) );
AOI2BB2XLTS U3179 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n4329), .A0N(n4329),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n4330) );
AOI2BB2XLTS U3180 ( .B0(n4271), .B1(n4328), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n4327), .Y(n1849) );
AO22XLTS U3181 ( .A0(n4333), .A1(n4325), .B0(n4332), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1850) );
OAI21XLTS U3182 ( .A0(n4324), .A1(n4323), .B0(n4326), .Y(n4325) );
AOI2BB2XLTS U3183 ( .B0(n4322), .B1(n4321), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n4327), .Y(n1851) );
AO22XLTS U3184 ( .A0(n4333), .A1(intadd_489_SUM_2_), .B0(n4306), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1852) );
NAND2BXLTS U3185 ( .AN(FPSENCOS_d_ff3_LUT_out[27]), .B(n2243), .Y(n2115) );
OAI211XLTS U3186 ( .A0(n4271), .A1(n5136), .B0(n4278), .C0(n4265), .Y(n2122)
);
AOI2BB2XLTS U3187 ( .B0(n4322), .B1(n2288), .A0N(FPSENCOS_d_ff3_LUT_out[13]),
.A1N(n4327), .Y(n2123) );
OAI211XLTS U3188 ( .A0(n4271), .A1(n5134), .B0(n4268), .C0(n2645), .Y(n2126)
);
AO22XLTS U3189 ( .A0(n4271), .A1(n4260), .B0(n4401), .B1(
FPSENCOS_d_ff3_LUT_out[8]), .Y(n2127) );
AOI211XLTS U3190 ( .A0(n4994), .A1(n2206), .B0(n4283), .C0(n2640), .Y(n2632)
);
OAI211XLTS U3191 ( .A0(n4271), .A1(n5135), .B0(n2645), .C0(n4265), .Y(n2132)
);
AOI22X1TS U3192 ( .A0(n3725), .A1(n3721), .B0(n3771), .B1(FPMULT_Op_MY[0]),
.Y(n2209) );
AOI22X1TS U3193 ( .A0(n3404), .A1(FPMULT_Op_MY[0]), .B0(n3395), .B1(n3721),
.Y(n2212) );
AOI22X1TS U3194 ( .A0(n3350), .A1(n3721), .B0(n3369), .B1(FPMULT_Op_MY[0]),
.Y(n2213) );
BUFX3TS U3195 ( .A(n2805), .Y(n2813) );
OR2X1TS U3196 ( .A(n5059), .B(n2593), .Y(n2218) );
OA21XLTS U3197 ( .A0(n4902), .A1(n3063), .B0(n3142), .Y(n2219) );
OR2X1TS U3198 ( .A(n4437), .B(n5059), .Y(n2222) );
NAND2X1TS U3199 ( .A(n4583), .B(n2196), .Y(n2223) );
OR2X1TS U3200 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n4580), .Y(n2224)
);
INVX2TS U3201 ( .A(n3152), .Y(n3067) );
INVX2TS U3202 ( .A(n4863), .Y(n4857) );
NOR4X1TS U3203 ( .A(FPMULT_P_Sgf[10]), .B(FPMULT_P_Sgf[11]), .C(
FPMULT_P_Sgf[12]), .D(FPMULT_P_Sgf[13]), .Y(n2228) );
BUFX3TS U3204 ( .A(n5083), .Y(n4817) );
INVX2TS U3205 ( .A(n5245), .Y(n2274) );
INVX4TS U3206 ( .A(rst), .Y(n2374) );
BUFX4TS U3207 ( .A(n2375), .Y(n2386) );
BUFX4TS U3208 ( .A(n4333), .Y(n4402) );
BUFX4TS U3209 ( .A(n5244), .Y(n4254) );
BUFX4TS U3210 ( .A(n4851), .Y(n4839) );
NOR2X6TS U3211 ( .A(n3092), .B(n4387), .Y(n3182) );
AOI21X2TS U3212 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n4583), .B0(n4535),
.Y(n4793) );
AOI21X2TS U3213 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n4583), .B0(n4538),
.Y(n4745) );
AOI21X2TS U3214 ( .A0(n4583), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n4576),
.Y(n4802) );
CLKBUFX3TS U3215 ( .A(n2201), .Y(n4296) );
NOR2X2TS U3216 ( .A(n4894), .B(n2308), .Y(n2634) );
NAND2X2TS U3217 ( .A(n4322), .B(FPSENCOS_cont_iter_out[1]), .Y(n4280) );
INVX2TS U3218 ( .A(n2223), .Y(n2235) );
INVX2TS U3219 ( .A(n2223), .Y(n2236) );
INVX2TS U3220 ( .A(n4884), .Y(n2238) );
INVX2TS U3221 ( .A(n4888), .Y(n2239) );
INVX2TS U3222 ( .A(n4886), .Y(n2240) );
INVX4TS U3223 ( .A(n4886), .Y(n2241) );
INVX2TS U3224 ( .A(n4885), .Y(n2242) );
INVX2TS U3225 ( .A(n4333), .Y(n2243) );
INVX2TS U3226 ( .A(n4857), .Y(n2244) );
INVX2TS U3227 ( .A(n2244), .Y(n2245) );
INVX4TS U3228 ( .A(n4760), .Y(n4782) );
INVX2TS U3229 ( .A(FPADDSUB_left_right_SHT2), .Y(n2247) );
INVX2TS U3230 ( .A(n2247), .Y(n2248) );
INVX2TS U3231 ( .A(n2249), .Y(n2250) );
INVX2TS U3232 ( .A(n2249), .Y(n2251) );
INVX2TS U3233 ( .A(n5245), .Y(n2252) );
INVX2TS U3234 ( .A(n5245), .Y(n2253) );
INVX4TS U3235 ( .A(n3089), .Y(n2255) );
INVX4TS U3236 ( .A(n2216), .Y(n2257) );
OAI21XLTS U3237 ( .A0(n5048), .A1(n4515), .B0(n2840), .Y(n1463) );
INVX2TS U3238 ( .A(n2232), .Y(n2258) );
INVX2TS U3239 ( .A(n2221), .Y(n2259) );
INVX2TS U3240 ( .A(n2205), .Y(n2260) );
BUFX4TS U3241 ( .A(n2197), .Y(n3150) );
BUFX4TS U3242 ( .A(n3116), .Y(n4389) );
BUFX4TS U3243 ( .A(n4406), .Y(n4380) );
BUFX4TS U3244 ( .A(n4406), .Y(n4361) );
BUFX4TS U3245 ( .A(n4523), .Y(n4821) );
CLKINVX3TS U3246 ( .A(n2218), .Y(n2261) );
INVX3TS U3247 ( .A(n2218), .Y(n2262) );
OAI21X1TS U3248 ( .A0(n5065), .A1(n4580), .B0(n4548), .Y(n4549) );
OAI21XLTS U3249 ( .A0(n4277), .A1(n4284), .B0(n2616), .Y(n2119) );
OAI31XLTS U3250 ( .A0(n5157), .A1(FPSENCOS_cont_iter_out[3]), .A2(n4286),
.B0(n2633), .Y(n2129) );
AOI2BB1X1TS U3251 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1N(n3070), .B0(
n3000), .Y(n3003) );
OAI32X1TS U3252 ( .A0(n4262), .A1(n4258), .A2(n2206), .B0(n4994), .B1(n4262),
.Y(n2142) );
NOR3X4TS U3253 ( .A(n4258), .B(n4994), .C(n2206), .Y(n4262) );
OAI21XLTS U3254 ( .A0(n2892), .A1(n2891), .B0(n2890), .Y(n1733) );
NOR4X2TS U3255 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .C(n4901), .D(n4872), .Y(n4249) );
NOR3X1TS U3256 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n4998),
.C(n4236), .Y(n2357) );
INVX2TS U3257 ( .A(n2202), .Y(n2263) );
BUFX4TS U3258 ( .A(n4486), .Y(n4483) );
NOR4BX2TS U3259 ( .AN(n3086), .B(n3043), .C(n3003), .D(n3002), .Y(n3006) );
OAI211XLTS U3260 ( .A0(n2636), .A1(n2638), .B0(n2629), .C0(n3670), .Y(n1693)
);
NAND3X2TS U3261 ( .A(n3667), .B(FPMULT_FS_Module_state_reg[0]), .C(n2591),
.Y(n3670) );
NAND3X2TS U3262 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n2676),
.C(n5001), .Y(n4240) );
NOR4X1TS U3263 ( .A(FPMULT_P_Sgf[6]), .B(FPMULT_P_Sgf[7]), .C(
FPMULT_P_Sgf[8]), .D(FPMULT_P_Sgf[9]), .Y(n2621) );
AOI21X2TS U3264 ( .A0(n4583), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n4576),
.Y(n4860) );
BUFX4TS U3265 ( .A(n4520), .Y(n4583) );
BUFX4TS U3266 ( .A(n2386), .Y(n5229) );
NOR2XLTS U3267 ( .A(n4528), .B(n5090), .Y(n4516) );
BUFX4TS U3268 ( .A(n2265), .Y(n5192) );
NOR2X2TS U3269 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n4326), .Y(n4329) );
AOI22X1TS U3270 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(n4896), .B0(n4698), .B1(
n4697), .Y(n4704) );
AOI22X1TS U3271 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(n4898), .B0(n4710), .B1(
n4709), .Y(n4717) );
AOI22X1TS U3272 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(n4953), .B0(n4661), .B1(
n4660), .Y(n4667) );
AOI22X1TS U3273 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(n4959), .B0(n4673), .B1(
n4672), .Y(n4679) );
AOI22X1TS U3274 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(n4966), .B0(n4685), .B1(
n4684), .Y(n4691) );
NOR4X1TS U3275 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[20]), .C(
FPMULT_Op_MX[15]), .D(n2292), .Y(n4421) );
NOR4X1TS U3276 ( .A(FPMULT_Op_MY[22]), .B(n2295), .C(FPMULT_Op_MY[14]), .D(
FPMULT_Op_MY[21]), .Y(n4414) );
BUFX3TS U3277 ( .A(n2382), .Y(n2264) );
BUFX3TS U3278 ( .A(n2374), .Y(n2379) );
BUFX4TS U3279 ( .A(n2380), .Y(n5218) );
INVX2TS U3280 ( .A(n4409), .Y(n4410) );
BUFX3TS U3281 ( .A(n4396), .Y(n4409) );
NAND2X1TS U3282 ( .A(n3673), .B(n2587), .Y(n4432) );
NAND2X2TS U3283 ( .A(n3673), .B(n2373), .Y(n2375) );
NOR2X2TS U3284 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n3673) );
BUFX3TS U3285 ( .A(n2381), .Y(n5212) );
BUFX3TS U3286 ( .A(n5203), .Y(n2265) );
BUFX3TS U3287 ( .A(n2374), .Y(n2381) );
BUFX4TS U3288 ( .A(n2374), .Y(n5196) );
BUFX4TS U3289 ( .A(n2374), .Y(n5203) );
BUFX4TS U3290 ( .A(n2374), .Y(n5204) );
BUFX4TS U3291 ( .A(n2374), .Y(n5205) );
BUFX4TS U3292 ( .A(n4817), .Y(n4547) );
BUFX4TS U3293 ( .A(n5232), .Y(n5223) );
NOR2XLTS U3294 ( .A(n4827), .B(n4526), .Y(n4527) );
AOI21X2TS U3295 ( .A0(n4583), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n4576),
.Y(n4827) );
BUFX4TS U3296 ( .A(n2376), .Y(n5172) );
BUFX3TS U3297 ( .A(n5196), .Y(n2266) );
BUFX3TS U3298 ( .A(n2374), .Y(n2380) );
BUFX4TS U3299 ( .A(n4291), .Y(n4290) );
BUFX3TS U3300 ( .A(n4292), .Y(n4291) );
BUFX4TS U3301 ( .A(n2201), .Y(n4399) );
BUFX3TS U3302 ( .A(n2377), .Y(n2267) );
BUFX3TS U3303 ( .A(n2586), .Y(n2377) );
BUFX4TS U3304 ( .A(n4322), .Y(n4303) );
BUFX4TS U3305 ( .A(n2586), .Y(n5174) );
BUFX4TS U3306 ( .A(n2586), .Y(n5173) );
BUFX3TS U3307 ( .A(n2378), .Y(n2268) );
BUFX4TS U3308 ( .A(n4299), .Y(n4403) );
BUFX4TS U3309 ( .A(n2378), .Y(n5183) );
BUFX4TS U3310 ( .A(n2378), .Y(n5182) );
BUFX4TS U3311 ( .A(n2378), .Y(n5181) );
BUFX4TS U3312 ( .A(n2378), .Y(n5186) );
BUFX4TS U3313 ( .A(n2376), .Y(n5163) );
BUFX4TS U3314 ( .A(n2376), .Y(n5165) );
BUFX4TS U3315 ( .A(n2376), .Y(n5188) );
BUFX4TS U3316 ( .A(n2376), .Y(n5189) );
BUFX4TS U3317 ( .A(n4271), .Y(n4316) );
BUFX3TS U3318 ( .A(n5196), .Y(n5211) );
BUFX4TS U3319 ( .A(n5230), .Y(n5227) );
BUFX4TS U3320 ( .A(n5228), .Y(n5233) );
BUFX4TS U3321 ( .A(n5232), .Y(n5222) );
BUFX4TS U3322 ( .A(n2612), .Y(n4203) );
BUFX4TS U3323 ( .A(n2813), .Y(n2810) );
BUFX4TS U3324 ( .A(n4695), .Y(n4774) );
INVX2TS U3325 ( .A(n2234), .Y(n2270) );
NOR2X4TS U3326 ( .A(operation[1]), .B(operation[2]), .Y(n4250) );
INVX2TS U3327 ( .A(n2233), .Y(n2271) );
BUFX4TS U3328 ( .A(n2249), .Y(n4319) );
NOR3XLTS U3329 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[2]), .C(
FPMULT_Op_MX[24]), .Y(n4425) );
NOR4X1TS U3330 ( .A(n2291), .B(FPMULT_Op_MX[30]), .C(FPMULT_Op_MX[29]), .D(
FPMULT_Op_MX[28]), .Y(n4420) );
NOR2XLTS U3331 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n3660) );
NOR3XLTS U3332 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MY[9]), .C(
FPMULT_Op_MY[23]), .Y(n4416) );
NOR2X2TS U3333 ( .A(ready_add_subt), .B(n4230), .Y(n4264) );
INVX2TS U3334 ( .A(FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n2272) );
INVX2TS U3335 ( .A(n2272), .Y(n2273) );
INVX3TS U3336 ( .A(n4813), .Y(n4569) );
INVX3TS U3337 ( .A(n4813), .Y(n4815) );
INVX3TS U3338 ( .A(n4814), .Y(n4798) );
BUFX4TS U3339 ( .A(n2311), .Y(n2972) );
BUFX4TS U3340 ( .A(n2972), .Y(n4405) );
BUFX4TS U3341 ( .A(n2972), .Y(n4365) );
BUFX4TS U3342 ( .A(n2838), .Y(n4637) );
BUFX4TS U3343 ( .A(n4254), .Y(n2838) );
INVX2TS U3344 ( .A(n2219), .Y(n2275) );
AOI221X1TS U3345 ( .A0(n2248), .A1(n4586), .B0(n4829), .B1(n4587), .C0(n4588), .Y(n4846) );
NOR2X4TS U3346 ( .A(n2196), .B(n5012), .Y(n4588) );
AO22XLTS U3347 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n4490), .B0(
mult_result[0]), .B1(n4489), .Y(n1515) );
INVX3TS U3348 ( .A(n2303), .Y(n4490) );
CLKINVX3TS U3349 ( .A(n2222), .Y(n2276) );
INVX3TS U3350 ( .A(n2222), .Y(n2277) );
INVX2TS U3351 ( .A(n2224), .Y(n2278) );
INVX2TS U3352 ( .A(n2224), .Y(n2279) );
INVX3TS U3353 ( .A(n4331), .Y(n4320) );
BUFX4TS U3354 ( .A(n2357), .Y(n4331) );
INVX3TS U3355 ( .A(n4486), .Y(n4488) );
CLKINVX3TS U3356 ( .A(n4863), .Y(n4865) );
INVX3TS U3357 ( .A(n4314), .Y(n4318) );
INVX4TS U3358 ( .A(n4333), .Y(n4302) );
INVX3TS U3359 ( .A(n4322), .Y(n4283) );
INVX4TS U3360 ( .A(n4841), .Y(n4820) );
INVX3TS U3361 ( .A(n4291), .Y(n4293) );
CLKINVX3TS U3362 ( .A(n4299), .Y(n4398) );
CLKINVX3TS U3363 ( .A(n4299), .Y(n4295) );
INVX2TS U3364 ( .A(n4299), .Y(n4404) );
CLKINVX3TS U3365 ( .A(n2592), .Y(n4435) );
INVX4TS U3366 ( .A(n2592), .Y(n4199) );
CLKINVX3TS U3367 ( .A(n4296), .Y(n4400) );
CLKINVX3TS U3368 ( .A(n4296), .Y(n4397) );
CLKINVX3TS U3369 ( .A(n4296), .Y(n4298) );
CLKINVX3TS U3370 ( .A(n4409), .Y(n4294) );
CLKINVX3TS U3371 ( .A(n4409), .Y(n4300) );
INVX2TS U3372 ( .A(n2214), .Y(n2280) );
CLKXOR2X2TS U3373 ( .A(n2238), .B(FPMULT_Op_MX[19]), .Y(n3216) );
NOR4X1TS U3374 ( .A(n2263), .B(FPMULT_Op_MX[19]), .C(FPMULT_Op_MX[16]), .D(
n2284), .Y(n4423) );
NOR4X1TS U3375 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[10]), .C(
FPMULT_Op_MX[7]), .D(FPMULT_Op_MX[4]), .Y(n4427) );
BUFX4TS U3376 ( .A(FPMULT_Op_MY[5]), .Y(n3708) );
NOR4X1TS U3377 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[8]), .C(
FPMULT_Op_MY[5]), .D(FPMULT_Op_MY[4]), .Y(n4417) );
BUFX4TS U3378 ( .A(FPMULT_Op_MY[17]), .Y(n3585) );
NOR4X1TS U3379 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[19]), .C(
FPMULT_Op_MY[17]), .D(FPMULT_Op_MY[16]), .Y(n4413) );
BUFX4TS U3380 ( .A(FPMULT_Op_MY[19]), .Y(n3577) );
INVX2TS U3381 ( .A(n2227), .Y(n2281) );
INVX2TS U3382 ( .A(n2226), .Y(n2282) );
BUFX4TS U3383 ( .A(FPMULT_Op_MY[1]), .Y(n3721) );
BUFX4TS U3384 ( .A(FPMULT_Op_MY[1]), .Y(n3730) );
NOR4X1TS U3385 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MY[2]), .C(
FPMULT_Op_MY[1]), .D(FPMULT_Op_MY[0]), .Y(n4418) );
BUFX4TS U3386 ( .A(FPMULT_Op_MY[2]), .Y(n3755) );
BUFX4TS U3387 ( .A(FPMULT_Op_MY[2]), .Y(n3731) );
BUFX4TS U3388 ( .A(FPMULT_Op_MY[8]), .Y(n5158) );
BUFX4TS U3389 ( .A(FPMULT_Op_MY[8]), .Y(n3629) );
XNOR2X2TS U3390 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[10]), .Y(n3226) );
NOR4X1TS U3391 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[9]), .C(
FPMULT_Op_MX[6]), .D(n2283), .Y(n4426) );
INVX2TS U3392 ( .A(n2211), .Y(n2283) );
INVX2TS U3393 ( .A(n2210), .Y(n2284) );
INVX2TS U3394 ( .A(n2225), .Y(n2285) );
INVX2TS U3395 ( .A(n2203), .Y(n2286) );
OAI221X1TS U3396 ( .A0(n5067), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n5048),
.B1(FPADDSUB_intDY_EWSW[27]), .C0(n4606), .Y(n4609) );
OAI221X1TS U3397 ( .A0(n5045), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n5050),
.B1(FPADDSUB_intDY_EWSW[9]), .C0(n4604), .Y(n4611) );
AOI222X1TS U3398 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4919), .B0(n2696), .B1(
n2695), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n5060), .Y(n2698) );
AOI221X1TS U3399 ( .A0(n4919), .A1(FPADDSUB_intDY_EWSW[4]), .B0(
FPADDSUB_intDY_EWSW[5]), .B1(n5060), .C0(n4618), .Y(n4621) );
XNOR2X2TS U3400 ( .A(n2238), .B(n2263), .Y(n2329) );
NOR2X1TS U3401 ( .A(n2239), .B(n2242), .Y(n2387) );
NAND2X1TS U3402 ( .A(n3619), .B(n2239), .Y(n2539) );
NOR2X1TS U3403 ( .A(n3619), .B(n2239), .Y(n2388) );
NAND2X1TS U3404 ( .A(n2240), .B(n5158), .Y(n2546) );
NOR2X1TS U3405 ( .A(n2242), .B(n5159), .Y(n2437) );
NAND2X1TS U3406 ( .A(n2242), .B(n5159), .Y(n2565) );
OAI221X1TS U3407 ( .A0(n4867), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n5013),
.B1(FPADDSUB_intDY_EWSW[23]), .C0(n4612), .Y(n4627) );
OAI221X1TS U3408 ( .A0(n4922), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n5052),
.B1(FPADDSUB_intDY_EWSW[17]), .C0(n4596), .Y(n4603) );
OAI21XLTS U3409 ( .A0(n4286), .A1(n2639), .B0(n2630), .Y(n2133) );
OAI21XLTS U3410 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n4286), .B0(n2620),
.Y(n2116) );
OAI21XLTS U3411 ( .A0(n4261), .A1(n4280), .B0(n2644), .Y(n2131) );
OAI21XLTS U3412 ( .A0(n2206), .A1(n4278), .B0(n2642), .Y(n2118) );
OAI21XLTS U3413 ( .A0(n4283), .A1(intadd_489_CI), .B0(n2617), .Y(n1855) );
OAI21XLTS U3414 ( .A0(n2850), .A1(n2851), .B0(n2849), .Y(n1697) );
XOR2XLTS U3415 ( .A(FPSENCOS_d_ff_Yn[31]), .B(n2847), .Y(n2848) );
OAI33X4TS U3416 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .A2(n5074), .B0(n4881), .B1(
n4928), .B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n2847) );
XNOR2X2TS U3417 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[16]), .Y(n3207) );
XNOR2X2TS U3418 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[7]), .Y(n3244) );
NOR4X1TS U3419 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n5152) );
NOR4X1TS U3420 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n5155) );
NOR4X1TS U3421 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n5154) );
NOR4X1TS U3422 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n5153) );
NOR4X1TS U3423 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n2315),
.Y(n5151) );
OAI32X1TS U3424 ( .A0(n2200), .A1(n4774), .A2(n4868), .B0(
FPADDSUB_DmP_mant_SFG_SWR[1]), .B1(n4641), .Y(n4642) );
NOR4X1TS U3425 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_P_Sgf[3]), .C(
FPMULT_P_Sgf[4]), .D(FPMULT_P_Sgf[5]), .Y(n2623) );
NOR2X1TS U3426 ( .A(n4281), .B(n4273), .Y(n2288) );
OAI21XLTS U3427 ( .A0(n2288), .A1(n4280), .B0(n2635), .Y(n2135) );
NOR2X2TS U3428 ( .A(FPSENCOS_cont_iter_out[3]), .B(n4260), .Y(n4281) );
NOR2XLTS U3429 ( .A(n4281), .B(n4273), .Y(n4279) );
NOR4X1TS U3430 ( .A(FPMULT_FS_Module_state_reg[2]), .B(n4901), .C(n4989),
.D(n3667), .Y(n3668) );
NOR2X2TS U3431 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_489_n1), .Y(n4324) );
BUFX4TS U3432 ( .A(FPMULT_Op_MY[22]), .Y(n3648) );
NOR2X2TS U3433 ( .A(n5014), .B(n4548), .Y(n4582) );
NOR2X2TS U3434 ( .A(n3748), .B(n3747), .Y(n3977) );
ADDHX1TS U3435 ( .A(n3716), .B(n3715), .CO(n3765), .S(n3747) );
NOR2X2TS U3436 ( .A(n5006), .B(n3042), .Y(n3082) );
AOI21X2TS U3437 ( .A0(n4583), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n4576),
.Y(n4799) );
OAI21XLTS U3438 ( .A0(n3597), .A1(n2496), .B0(n2461), .Y(n2462) );
OAI21XLTS U3439 ( .A0(n3833), .A1(n2496), .B0(n3640), .Y(n3641) );
NOR2X2TS U3440 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4899),
.Y(n2661) );
AOI211X1TS U3441 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5046), .B0(n2729),
.C0(n2730), .Y(n2721) );
OAI21XLTS U3442 ( .A0(n3621), .A1(n3761), .B0(n3620), .Y(n3622) );
OAI21XLTS U3443 ( .A0(n3775), .A1(n3761), .B0(n3636), .Y(n3637) );
OAI21XLTS U3444 ( .A0(n3699), .A1(n3761), .B0(n3695), .Y(n3696) );
OAI21XLTS U3445 ( .A0(n3693), .A1(n3761), .B0(n3634), .Y(n3635) );
OAI21XLTS U3446 ( .A0(n3616), .A1(n3761), .B0(n3615), .Y(n3617) );
OAI21XLTS U3447 ( .A0(n3710), .A1(n3761), .B0(n3638), .Y(n3639) );
OAI21XLTS U3448 ( .A0(n3762), .A1(n3761), .B0(n3760), .Y(n3764) );
OAI21XLTS U3449 ( .A0(n3734), .A1(n3761), .B0(n3713), .Y(n3714) );
OAI21XLTS U3450 ( .A0(n3718), .A1(n3761), .B0(n3706), .Y(n3707) );
OAI21XLTS U3451 ( .A0(n3722), .A1(n3761), .B0(n2304), .Y(n3701) );
BUFX4TS U3452 ( .A(n2923), .Y(n4374) );
BUFX4TS U3453 ( .A(n3013), .Y(n3036) );
OAI21X2TS U3454 ( .A0(n2634), .A1(n2206), .B0(n2640), .Y(n4273) );
NAND2X2TS U3455 ( .A(FPSENCOS_cont_iter_out[3]), .B(n4260), .Y(n2640) );
BUFX3TS U3456 ( .A(n2668), .Y(n2749) );
NOR2X4TS U3457 ( .A(n2784), .B(n2663), .Y(n2668) );
BUFX4TS U3458 ( .A(n2381), .Y(n5193) );
BUFX4TS U3459 ( .A(n5197), .Y(n5190) );
BUFX3TS U3460 ( .A(n2374), .Y(n2382) );
BUFX4TS U3461 ( .A(FPMULT_Op_MY[16]), .Y(n3589) );
BUFX4TS U3462 ( .A(FPMULT_Op_MY[14]), .Y(n3599) );
BUFX4TS U3463 ( .A(FPMULT_Op_MY[4]), .Y(n3697) );
AOI222X1TS U3464 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n2776) );
OAI21XLTS U3465 ( .A0(n2661), .A1(n2660), .B0(n2659), .Y(n2151) );
AOI32X1TS U3466 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n4386), .A2(
n4256), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n3116), .Y(n3004)
);
BUFX4TS U3467 ( .A(n2197), .Y(n4256) );
OAI21X2TS U3468 ( .A0(n4873), .A1(n3063), .B0(n3139), .Y(n3181) );
BUFX4TS U3469 ( .A(n4366), .Y(n4377) );
NAND2X2TS U3470 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n2289) );
OAI21X2TS U3471 ( .A0(n4875), .A1(n2289), .B0(n3091), .Y(n3135) );
OAI21X2TS U3472 ( .A0(n4908), .A1(n2289), .B0(n3107), .Y(n3160) );
OAI21X2TS U3473 ( .A0(n4869), .A1(n2289), .B0(n3146), .Y(n3177) );
OAI21X2TS U3474 ( .A0(n5006), .A1(n2289), .B0(n3118), .Y(n3158) );
OAI21X2TS U3475 ( .A0(n4995), .A1(n2289), .B0(n3151), .Y(n3175) );
OAI21X2TS U3476 ( .A0(n4874), .A1(n2289), .B0(n3100), .Y(n3134) );
OAI21X2TS U3477 ( .A0(n4930), .A1(n3152), .B0(n3104), .Y(n3123) );
OAI21X2TS U3478 ( .A0(n4871), .A1(n3152), .B0(n3101), .Y(n3127) );
AOI222X1TS U3479 ( .A0(n2823), .A1(cordic_result[13]), .B0(n2888), .B1(
FPSENCOS_d_ff_Yn[13]), .C0(n2883), .C1(FPSENCOS_d_ff_Xn[13]), .Y(n2881) );
BUFX4TS U3480 ( .A(n2825), .Y(n2865) );
BUFX4TS U3481 ( .A(n2825), .Y(n2888) );
AOI22X1TS U3482 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(n4939), .B0(n4649), .B1(
n4647), .Y(n4655) );
INVX3TS U3483 ( .A(n4094), .Y(n4201) );
OR2X4TS U3484 ( .A(n4437), .B(FPMULT_FSM_selector_C), .Y(n4094) );
INVX4TS U3485 ( .A(n4817), .Y(n4818) );
BUFX4TS U3486 ( .A(n2586), .Y(n5171) );
BUFX4TS U3487 ( .A(n2586), .Y(n5167) );
BUFX4TS U3488 ( .A(n2586), .Y(n5169) );
BUFX4TS U3489 ( .A(n2586), .Y(n5168) );
BUFX3TS U3490 ( .A(n2586), .Y(n2376) );
BUFX3TS U3491 ( .A(n2586), .Y(n2378) );
INVX3TS U3492 ( .A(n3674), .Y(n4411) );
OAI211XLTS U3493 ( .A0(n2988), .A1(n2230), .B0(n2901), .C0(n2900), .Y(n1912)
);
OR4X4TS U3494 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(
FPMULT_exp_oper_result[8]), .C(underflow_flag_mult), .D(n4489), .Y(
n2303) );
NOR3XLTS U3495 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n4489), .Y(n4493) );
BUFX4TS U3496 ( .A(FPMULT_Op_MY[20]), .Y(n3573) );
NOR3X1TS U3497 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n2321) );
NAND4X2TS U3498 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n2309),
.C(n4909), .D(n5001), .Y(n4241) );
NOR3X1TS U3499 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n2383) );
NAND2X1TS U3500 ( .A(FPMULT_Sgf_normalized_result[5]), .B(n4445), .Y(n4447)
);
NAND2X1TS U3501 ( .A(FPMULT_Sgf_normalized_result[3]), .B(n4441), .Y(n4443)
);
BUFX4TS U3502 ( .A(FPMULT_Op_MY[11]), .Y(n3619) );
BUFX4TS U3503 ( .A(FPMULT_Op_MY[11]), .Y(n3614) );
BUFX4TS U3504 ( .A(FPMULT_Op_MY[10]), .Y(n3625) );
BUFX4TS U3505 ( .A(FPMULT_Op_MY[10]), .Y(n3618) );
BUFX4TS U3506 ( .A(FPMULT_Op_MY[3]), .Y(n3732) );
BUFX4TS U3507 ( .A(FPMULT_Op_MY[3]), .Y(n3757) );
XNOR2X2TS U3508 ( .A(n2263), .B(FPMULT_Op_MX[22]), .Y(n2328) );
AOI32X1TS U3509 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n4386), .A2(
n4256), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n3116), .Y(n3064)
);
INVX3TS U3510 ( .A(n4314), .Y(n4313) );
BUFX4TS U3511 ( .A(n4322), .Y(n4333) );
BUFX3TS U3512 ( .A(n4530), .Y(n2290) );
INVX3TS U3513 ( .A(n4291), .Y(n4287) );
AOI21X2TS U3514 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n4583), .B0(n4549),
.Y(n4557) );
AOI21X2TS U3515 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n4583), .B0(n4540),
.Y(n4807) );
BUFX3TS U3516 ( .A(FPMULT_Op_MX[17]), .Y(n2291) );
AOI222X2TS U3517 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(
FPADDSUB_DMP_SFG[2]), .B0(FPADDSUB_DmP_mant_SFG_SWR[4]), .B1(n4654),
.C0(FPADDSUB_DMP_SFG[2]), .C1(n4654), .Y(n4659) );
AOI222X2TS U3518 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(
FPADDSUB_DMP_SFG[12]), .B0(FPADDSUB_DmP_mant_SFG_SWR[14]), .B1(n4716),
.C0(FPADDSUB_DMP_SFG[12]), .C1(n4716), .Y(n4721) );
AOI222X2TS U3519 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(
FPADDSUB_DMP_SFG[10]), .B0(FPADDSUB_DmP_mant_SFG_SWR[12]), .B1(n4703),
.C0(FPADDSUB_DMP_SFG[10]), .C1(n4703), .Y(n4708) );
AOI222X2TS U3520 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[16]), .A1(
FPADDSUB_DMP_SFG[14]), .B0(FPADDSUB_DmP_mant_SFG_SWR[16]), .B1(n4728),
.C0(FPADDSUB_DMP_SFG[14]), .C1(n4728), .Y(n4733) );
AOI222X2TS U3521 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(
FPADDSUB_DMP_SFG[8]), .B0(FPADDSUB_DmP_mant_SFG_SWR[10]), .B1(n4690),
.C0(FPADDSUB_DMP_SFG[8]), .C1(n4690), .Y(n4696) );
AOI222X2TS U3522 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(
FPADDSUB_DMP_SFG[16]), .B0(FPADDSUB_DmP_mant_SFG_SWR[18]), .B1(n4740),
.C0(FPADDSUB_DMP_SFG[16]), .C1(n4740), .Y(n4748) );
AOI222X2TS U3523 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(
FPADDSUB_DMP_SFG[6]), .B0(FPADDSUB_DmP_mant_SFG_SWR[8]), .B1(n4678),
.C0(FPADDSUB_DMP_SFG[6]), .C1(n4678), .Y(n4683) );
AOI222X2TS U3524 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(
FPADDSUB_DMP_SFG[4]), .B0(FPADDSUB_DmP_mant_SFG_SWR[6]), .B1(n4666),
.C0(FPADDSUB_DMP_SFG[4]), .C1(n4666), .Y(n4671) );
AOI222X2TS U3525 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(
FPADDSUB_DMP_SFG[20]), .B0(FPADDSUB_DmP_mant_SFG_SWR[22]), .B1(n4769),
.C0(FPADDSUB_DMP_SFG[20]), .C1(n4769), .Y(n4775) );
AOI222X2TS U3526 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(
FPADDSUB_DMP_SFG[18]), .B0(FPADDSUB_DmP_mant_SFG_SWR[20]), .B1(n4756),
.C0(FPADDSUB_DMP_SFG[18]), .C1(n4756), .Y(n4762) );
AOI31XLTS U3527 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n4890), .A2(n4869),
.B0(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n3071) );
AOI32X1TS U3528 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n4386), .A2(
n4256), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n3116), .Y(n3051)
);
NAND2X2TS U3529 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n4548) );
AOI222X2TS U3530 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(
FPADDSUB_DMP_SFG[22]), .B0(FPADDSUB_DmP_mant_SFG_SWR[24]), .B1(n4785),
.C0(FPADDSUB_DMP_SFG[22]), .C1(n4785), .Y(n4639) );
BUFX3TS U3531 ( .A(FPMULT_Op_MX[14]), .Y(n2292) );
BUFX3TS U3532 ( .A(FPMULT_Op_MX[8]), .Y(n2293) );
BUFX3TS U3533 ( .A(FPMULT_Op_MY[18]), .Y(n2295) );
NOR2X1TS U3534 ( .A(FPMULT_Op_MY[18]), .B(n5160), .Y(n2418) );
NOR2X1TS U3535 ( .A(n3590), .B(FPMULT_Op_MY[18]), .Y(n2416) );
CLKBUFX2TS U3536 ( .A(FPMULT_Op_MY[6]), .Y(n2296) );
NOR2X1TS U3537 ( .A(n2296), .B(n2240), .Y(n2465) );
NOR2X2TS U3538 ( .A(n3768), .B(n2296), .Y(n2531) );
NAND2X1TS U3539 ( .A(n3768), .B(n2296), .Y(n2532) );
NOR2XLTS U3540 ( .A(n2724), .B(FPADDSUB_intDY_EWSW[16]), .Y(n2725) );
OAI221X1TS U3541 ( .A0(n5046), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n5055),
.B1(FPADDSUB_intDY_EWSW[15]), .C0(n4597), .Y(n4602) );
OAI211XLTS U3542 ( .A0(n2893), .A1(n5141), .B0(n2314), .C0(n2313), .Y(n1839)
);
OAI211X2TS U3543 ( .A0(n5157), .A1(n4261), .B0(n2639), .C0(n2640), .Y(n4270)
);
NAND2X1TS U3544 ( .A(n3281), .B(n3724), .Y(n2298) );
AOI22X1TS U3545 ( .A0(n3462), .A1(n3724), .B0(n3446), .B1(n3721), .Y(n2299)
);
AOI22X1TS U3546 ( .A0(n3506), .A1(n3724), .B0(n3495), .B1(n3721), .Y(n2300)
);
AOI22X1TS U3547 ( .A0(n3678), .A1(n3724), .B0(n3680), .B1(n3721), .Y(n2301)
);
OR2X1TS U3548 ( .A(n3755), .B(n3732), .Y(n2302) );
AOI22X1TS U3549 ( .A0(n3758), .A1(n3724), .B0(n3702), .B1(n3721), .Y(n2304)
);
OR2X1TS U3550 ( .A(n3721), .B(n3755), .Y(n2305) );
XNOR2X1TS U3551 ( .A(n3719), .B(n3776), .Y(n2306) );
INVX2TS U3552 ( .A(FPSENCOS_cont_iter_out[2]), .Y(n4260) );
NOR2X1TS U3553 ( .A(n5158), .B(n3630), .Y(n2549) );
NOR2X1TS U3554 ( .A(n5159), .B(n3600), .Y(n2439) );
NAND2X1TS U3555 ( .A(n3600), .B(n3595), .Y(n2473) );
NOR2X1TS U3556 ( .A(n2416), .B(n2418), .Y(n2398) );
NAND2X1TS U3557 ( .A(n3759), .B(n3768), .Y(n2524) );
OAI21X1TS U3558 ( .A0(n2548), .A1(n2487), .B0(n2486), .Y(n2559) );
INVX2TS U3559 ( .A(n2364), .Y(n2522) );
AND3X2TS U3560 ( .A(n3246), .B(n3245), .C(n3244), .Y(n3550) );
OAI21XLTS U3561 ( .A0(n3616), .A1(n3371), .B0(n3348), .Y(n3349) );
OAI21XLTS U3562 ( .A0(n3621), .A1(n3410), .B0(n3396), .Y(n3397) );
OAI21XLTS U3563 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n4897), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n2711) );
BUFX4TS U3564 ( .A(FPMULT_Op_MY[5]), .Y(n3768) );
OAI21XLTS U3565 ( .A0(n3734), .A1(n3232), .B0(n3463), .Y(n3464) );
INVX2TS U3566 ( .A(n2371), .Y(n3612) );
NOR2XLTS U3567 ( .A(n2738), .B(FPADDSUB_intDY_EWSW[24]), .Y(n2679) );
OAI21XLTS U3568 ( .A0(n3621), .A1(n3508), .B0(n3496), .Y(n3497) );
INVX2TS U3569 ( .A(n2410), .Y(n3575) );
OAI21XLTS U3570 ( .A0(n3762), .A1(n3774), .B0(n3741), .Y(n3742) );
NAND2X1TS U3571 ( .A(n4029), .B(n3812), .Y(n4015) );
OR2X1TS U3572 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n3666) );
OAI21XLTS U3573 ( .A0(n3979), .A1(n3976), .B0(n3980), .Y(n3751) );
OAI21XLTS U3574 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n4972), .B0(n4698),
.Y(n4699) );
NOR2XLTS U3575 ( .A(n4560), .B(n4526), .Y(n4534) );
NOR2XLTS U3576 ( .A(n4560), .B(n4556), .Y(n4561) );
NAND2X1TS U3577 ( .A(FPMULT_Sgf_normalized_result[7]), .B(n4449), .Y(n4451)
);
OAI21XLTS U3578 ( .A0(n4494), .A1(underflow_flag_mult), .B0(n4493), .Y(n4495) );
OR2X1TS U3579 ( .A(FPSENCOS_d_ff2_X[23]), .B(n2206), .Y(intadd_490_CI) );
AOI211XLTS U3580 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n4283), .B0(n2632),
.C0(n2631), .Y(n2633) );
OAI211XLTS U3581 ( .A0(n3857), .A1(n5132), .B0(n4199), .C0(n2678), .Y(n1695)
);
OAI21XLTS U3582 ( .A0(n2615), .A1(n4240), .B0(n4306), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
OAI211XLTS U3583 ( .A0(n4094), .A1(n5122), .B0(n2605), .C0(n2604), .Y(n1521)
);
OAI21XLTS U3584 ( .A0(n4386), .A1(n5012), .B0(n2289), .Y(n2081) );
OAI21XLTS U3585 ( .A0(n5044), .A1(n4515), .B0(n2820), .Y(n1227) );
OAI21XLTS U3586 ( .A0(n4920), .A1(n2845), .B0(n2836), .Y(n1271) );
OAI21XLTS U3587 ( .A0(n5044), .A1(n4514), .B0(n2757), .Y(n1397) );
OAI21XLTS U3588 ( .A0(n5048), .A1(n4514), .B0(n2753), .Y(n1415) );
OAI21XLTS U3589 ( .A0(n5066), .A1(n2843), .B0(n2835), .Y(n1460) );
NOR2XLTS U3590 ( .A(n4241), .B(n4296), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
OAI21XLTS U3591 ( .A0(n3007), .A1(n5037), .B0(n3039), .Y(op_result[5]) );
OAI21XLTS U3592 ( .A0(n3041), .A1(n5020), .B0(n3023), .Y(op_result[20]) );
BUFX3TS U3593 ( .A(n2317), .Y(n3836) );
BUFX4TS U3594 ( .A(n2327), .Y(n3281) );
INVX4TS U3595 ( .A(n4957), .Y(n3724) );
OAI21X1TS U3596 ( .A0(n4957), .A1(n3836), .B0(n2298), .Y(mult_x_69_n674) );
INVX2TS U3597 ( .A(operation[1]), .Y(n3008) );
AOI22X1TS U3598 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n2661), .B0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n4870),
.Y(n4253) );
OR4X2TS U3599 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n2384) );
NOR2X1TS U3600 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(n2384),
.Y(n2309) );
NOR2BX1TS U3601 ( .AN(n2309), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n2676) );
NAND2X1TS U3602 ( .A(n4241), .B(n4240), .Y(n2310) );
AOI22X1TS U3603 ( .A0(Data_2[6]), .A1(n4380), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n4340), .Y(n2314) );
INVX2TS U3604 ( .A(n2312), .Y(n2892) );
NOR3X1TS U3605 ( .A(FPSENCOS_cont_var_out[1]), .B(n5077), .C(n2892), .Y(
n2914) );
BUFX3TS U3606 ( .A(n2914), .Y(n4337) );
NAND2X1TS U3607 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n4239) );
BUFX3TS U3608 ( .A(n2923), .Y(n2993) );
AOI22X1TS U3609 ( .A0(n4337), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n2313) );
BUFX4TS U3610 ( .A(FPMULT_Op_MY[19]), .Y(n5160) );
BUFX4TS U3611 ( .A(FPMULT_Op_MY[20]), .Y(n5161) );
OR4X2TS U3612 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n2315) );
INVX2TS U3613 ( .A(mult_x_69_n674), .Y(n2324) );
NAND2X2TS U3614 ( .A(n3721), .B(n3724), .Y(n2337) );
NAND2X2TS U3615 ( .A(n2316), .B(n2337), .Y(n3722) );
NOR2BX4TS U3616 ( .AN(n2329), .B(n2328), .Y(n3830) );
AOI22X1TS U3617 ( .A0(n3830), .A1(FPMULT_Op_MY[0]), .B0(n3281), .B1(n3721),
.Y(n2318) );
INVX4TS U3618 ( .A(n4943), .Y(n3509) );
XNOR2X2TS U3619 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[9]), .Y(n3227) );
CLKXOR2X2TS U3620 ( .A(n3509), .B(FPMULT_Op_MX[10]), .Y(n3228) );
BUFX4TS U3621 ( .A(n3225), .Y(n3495) );
NAND2X1TS U3622 ( .A(n3495), .B(n3724), .Y(n2319) );
XOR2X1TS U3623 ( .A(n2320), .B(FPMULT_Op_MX[11]), .Y(n2350) );
OAI21XLTS U3624 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n2198), .B0(n2289),
.Y(n1352) );
AOI21X1TS U3625 ( .A0(operation[1]), .A1(ack_operation), .B0(n2821), .Y(
n4233) );
NOR2BX1TS U3626 ( .AN(n2322), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]),
.Y(n2356) );
NAND4X2TS U3627 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n2356),
.C(n4903), .D(n4998), .Y(n4258) );
NOR2X1TS U3628 ( .A(n4258), .B(n4238), .Y(n2822) );
OR2X1TS U3629 ( .A(n4233), .B(n2822), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
ADDHXLTS U3630 ( .A(n2324), .B(n2323), .CO(n2345), .S(mult_x_69_n663) );
NAND2X1TS U3631 ( .A(n2305), .B(n2338), .Y(n2325) );
XOR2X1TS U3632 ( .A(n2325), .B(n2337), .Y(n2326) );
BUFX4TS U3633 ( .A(n3830), .Y(n3280) );
AND3X2TS U3634 ( .A(n2329), .B(n2328), .C(n4945), .Y(n2330) );
INVX2TS U3635 ( .A(n2330), .Y(n3835) );
INVX4TS U3636 ( .A(n3835), .Y(n3831) );
INVX2TS U3637 ( .A(n2337), .Y(n2333) );
NAND2X1TS U3638 ( .A(n2339), .B(n2338), .Y(n2332) );
INVX2TS U3639 ( .A(n2359), .Y(n2521) );
NAND2X1TS U3640 ( .A(n2521), .B(n2519), .Y(n2334) );
XNOR2X1TS U3641 ( .A(n2522), .B(n2334), .Y(n2335) );
AOI222X1TS U3642 ( .A0(n2327), .A1(n3697), .B0(n3280), .B1(n3757), .C0(n3831), .C1(n3755), .Y(n2336) );
NAND2X1TS U3643 ( .A(n2338), .B(n2337), .Y(n2341) );
NAND2X1TS U3644 ( .A(n2302), .B(n2339), .Y(n2340) );
XNOR2X1TS U3645 ( .A(n2341), .B(n2340), .Y(n2342) );
AOI222X1TS U3646 ( .A0(n2327), .A1(n3757), .B0(n3280), .B1(n3731), .C0(n3831), .C1(n3730), .Y(n2343) );
ADDHXLTS U3647 ( .A(n2345), .B(n2344), .CO(n3196), .S(mult_x_69_n652) );
CMPR32X2TS U3648 ( .A(n3721), .B(n2347), .C(n2346), .CO(mult_x_69_n629), .S(
mult_x_69_n630) );
NOR2BX4TS U3649 ( .AN(n3227), .B(n3226), .Y(n3506) );
XOR2X1TS U3650 ( .A(n2349), .B(FPMULT_Op_MX[11]), .Y(n3305) );
ADDHXLTS U3651 ( .A(n3509), .B(n2350), .CO(n3304), .S(mult_x_69_n764) );
XNOR2X2TS U3652 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[15]), .Y(n3208) );
INVX4TS U3653 ( .A(n4942), .Y(n3411) );
CLKXOR2X2TS U3654 ( .A(n3411), .B(FPMULT_Op_MX[16]), .Y(n3209) );
NOR2BX4TS U3655 ( .AN(n3208), .B(n3207), .Y(n3404) );
BUFX4TS U3656 ( .A(n3266), .Y(n3395) );
XOR2X1TS U3657 ( .A(n2351), .B(n2291), .Y(n3286) );
NAND2X1TS U3658 ( .A(n3395), .B(n3724), .Y(n2353) );
XOR2X1TS U3659 ( .A(n2354), .B(n2291), .Y(n2355) );
ADDHXLTS U3660 ( .A(n3411), .B(n2355), .CO(n3285), .S(mult_x_69_n728) );
NAND2X2TS U3661 ( .A(n2197), .B(n2252), .Y(n4386) );
INVX2TS U3662 ( .A(n5090), .Y(n5235) );
NAND2BX1TS U3663 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n2356),
.Y(n4236) );
CLKBUFX2TS U3664 ( .A(n4331), .Y(n4314) );
BUFX3TS U3665 ( .A(n4314), .Y(n5234) );
NOR3X1TS U3666 ( .A(n4872), .B(FPMULT_FS_Module_state_reg[3]), .C(
FPMULT_FS_Module_state_reg[0]), .Y(n2590) );
INVX2TS U3667 ( .A(n2590), .Y(n3852) );
NAND2X1TS U3668 ( .A(n2524), .B(n2519), .Y(n2463) );
NAND2X1TS U3669 ( .A(n2296), .B(n2240), .Y(n2466) );
NAND2X1TS U3670 ( .A(n2466), .B(n2532), .Y(n2360) );
NOR2X2TS U3671 ( .A(n2240), .B(n5158), .Y(n2547) );
CLKBUFX2TS U3672 ( .A(n4971), .Y(n3200) );
INVX4TS U3673 ( .A(n3200), .Y(n3630) );
NAND2X1TS U3674 ( .A(n5158), .B(n3630), .Y(n2550) );
NAND2X1TS U3675 ( .A(n2550), .B(n2546), .Y(n2485) );
NAND2X1TS U3676 ( .A(n3625), .B(n3619), .Y(n2491) );
NAND2X1TS U3677 ( .A(n2491), .B(n2556), .Y(n2365) );
INVX2TS U3678 ( .A(n2388), .Y(n2540) );
INVX2TS U3679 ( .A(n2539), .Y(n2367) );
AOI21X1TS U3680 ( .A0(n2542), .A1(n2540), .B0(n2367), .Y(n2370) );
INVX2TS U3681 ( .A(n2387), .Y(n2368) );
NAND2X1TS U3682 ( .A(n2239), .B(n2242), .Y(n2389) );
NAND2X1TS U3683 ( .A(n2368), .B(n2389), .Y(n2369) );
XOR2X1TS U3684 ( .A(n2370), .B(n2369), .Y(n2371) );
INVX4TS U3685 ( .A(n4885), .Y(n3604) );
INVX4TS U3686 ( .A(n4888), .Y(n3609) );
AOI222X1TS U3687 ( .A0(n3281), .A1(n3604), .B0(n3280), .B1(n3609), .C0(n2330), .C1(n3619), .Y(n2372) );
OA21XLTS U3688 ( .A0(n3612), .A1(n3836), .B0(n2372), .Y(n4947) );
NOR2XLTS U3689 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .Y(n2373) );
BUFX3TS U3690 ( .A(n5196), .Y(n5199) );
CLKBUFX2TS U3691 ( .A(n5205), .Y(n5213) );
BUFX3TS U3692 ( .A(n5204), .Y(n5194) );
BUFX3TS U3693 ( .A(n5205), .Y(n5195) );
BUFX3TS U3694 ( .A(n5205), .Y(n5215) );
BUFX3TS U3695 ( .A(n5203), .Y(n5214) );
BUFX3TS U3696 ( .A(n5203), .Y(n5206) );
BUFX3TS U3697 ( .A(n2374), .Y(n5197) );
BUFX3TS U3698 ( .A(n2382), .Y(n5191) );
BUFX3TS U3699 ( .A(n5204), .Y(n5216) );
BUFX3TS U3700 ( .A(n2375), .Y(n5228) );
BUFX3TS U3701 ( .A(n5190), .Y(n5201) );
BUFX3TS U3702 ( .A(n5220), .Y(n5200) );
INVX2TS U3703 ( .A(n4258), .Y(n4259) );
BUFX3TS U3704 ( .A(n5204), .Y(n5208) );
BUFX3TS U3705 ( .A(n2374), .Y(n5202) );
BUFX3TS U3706 ( .A(n2382), .Y(n5207) );
BUFX3TS U3707 ( .A(n2377), .Y(n5178) );
BUFX3TS U3708 ( .A(n2376), .Y(n5187) );
BUFX3TS U3709 ( .A(n2380), .Y(n5210) );
BUFX3TS U3710 ( .A(n2378), .Y(n5166) );
BUFX3TS U3711 ( .A(n2377), .Y(n5179) );
BUFX3TS U3712 ( .A(n2377), .Y(n5164) );
BUFX3TS U3713 ( .A(n5228), .Y(n5225) );
BUFX3TS U3714 ( .A(n5197), .Y(n5209) );
BUFX3TS U3715 ( .A(n5230), .Y(n5224) );
BUFX3TS U3716 ( .A(n2378), .Y(n5184) );
BUFX3TS U3717 ( .A(n2375), .Y(n5232) );
BUFX3TS U3718 ( .A(n2378), .Y(n5170) );
BUFX3TS U3719 ( .A(n2380), .Y(n5198) );
BUFX3TS U3720 ( .A(n2386), .Y(n5231) );
BUFX3TS U3721 ( .A(n5197), .Y(n5220) );
BUFX3TS U3722 ( .A(n5196), .Y(n5219) );
BUFX3TS U3723 ( .A(n2386), .Y(n5226) );
BUFX3TS U3724 ( .A(n2375), .Y(n5230) );
BUFX3TS U3725 ( .A(n2377), .Y(n5175) );
BUFX3TS U3726 ( .A(n2376), .Y(n5162) );
BUFX3TS U3727 ( .A(n2377), .Y(n5176) );
BUFX3TS U3728 ( .A(n2377), .Y(n5180) );
BUFX3TS U3729 ( .A(n2377), .Y(n5177) );
BUFX3TS U3730 ( .A(n2378), .Y(n5185) );
BUFX3TS U3731 ( .A(n2381), .Y(n5221) );
BUFX3TS U3732 ( .A(n5205), .Y(n5217) );
INVX2TS U3733 ( .A(n2661), .Y(n4229) );
NAND2X1TS U3734 ( .A(n4229), .B(n2659), .Y(n2193) );
BUFX3TS U3735 ( .A(n4333), .Y(n4327) );
INVX2TS U3736 ( .A(n4280), .Y(n4274) );
INVX2TS U3737 ( .A(n4281), .Y(n2639) );
NAND2X1TS U3738 ( .A(n4274), .B(n4270), .Y(n4268) );
OAI221XLTS U3739 ( .A0(n4322), .A1(n5130), .B0(n4401), .B1(n2640), .C0(n4268), .Y(n2124) );
INVX4TS U3740 ( .A(n5237), .Y(busy) );
NOR2X2TS U3741 ( .A(n2388), .B(n2387), .Y(n2433) );
CLKBUFX2TS U3742 ( .A(n5009), .Y(n3279) );
INVX4TS U3743 ( .A(n3279), .Y(n3600) );
NAND2X1TS U3744 ( .A(n2389), .B(n2539), .Y(n2432) );
NAND2X1TS U3745 ( .A(n5159), .B(n3600), .Y(n2440) );
NAND2X1TS U3746 ( .A(n2440), .B(n2565), .Y(n2390) );
AOI21X1TS U3747 ( .A0(n2432), .A1(n2391), .B0(n2390), .Y(n2392) );
BUFX4TS U3748 ( .A(FPMULT_Op_MY[16]), .Y(n3595) );
BUFX4TS U3749 ( .A(FPMULT_Op_MY[17]), .Y(n3590) );
NAND2X1TS U3750 ( .A(n3595), .B(n3590), .Y(n2477) );
NAND2X1TS U3751 ( .A(n2477), .B(n2473), .Y(n2413) );
NAND2X1TS U3752 ( .A(FPMULT_Op_MY[18]), .B(n5160), .Y(n2419) );
NAND2X1TS U3753 ( .A(n3590), .B(FPMULT_Op_MY[18]), .Y(n2450) );
NAND2X1TS U3754 ( .A(n2419), .B(n2450), .Y(n2397) );
AOI21X1TS U3755 ( .A0(n2413), .A1(n2398), .B0(n2397), .Y(n2508) );
CLKBUFX2TS U3756 ( .A(n5075), .Y(n3844) );
INVX4TS U3757 ( .A(n3844), .Y(n3643) );
NAND2X1TS U3758 ( .A(n5161), .B(n3643), .Y(n2406) );
NAND2X1TS U3759 ( .A(n2406), .B(n2571), .Y(n2505) );
AOI21X1TS U3760 ( .A0(n2574), .A1(n2500), .B0(n2505), .Y(n2400) );
BUFX4TS U3761 ( .A(FPMULT_Op_MY[22]), .Y(n3843) );
NAND2X1TS U3762 ( .A(n3843), .B(n3643), .Y(n2502) );
NAND2X1TS U3763 ( .A(n2504), .B(n2502), .Y(n2399) );
XOR2X1TS U3764 ( .A(n2400), .B(n2399), .Y(n2401) );
AOI222X1TS U3765 ( .A0(n3281), .A1(n3648), .B0(n3830), .B1(n3647), .C0(n3831), .C1(n5161), .Y(n2402) );
OA21XLTS U3766 ( .A0(n3650), .A1(n3836), .B0(n2402), .Y(n4982) );
INVX2TS U3767 ( .A(n2403), .Y(n2572) );
INVX2TS U3768 ( .A(n2571), .Y(n2404) );
AOI21X1TS U3769 ( .A0(n2574), .A1(n2572), .B0(n2404), .Y(n2409) );
INVX2TS U3770 ( .A(n2405), .Y(n2407) );
NAND2X1TS U3771 ( .A(n2407), .B(n2406), .Y(n2408) );
XOR2X1TS U3772 ( .A(n2409), .B(n2408), .Y(n2410) );
AOI222X1TS U3773 ( .A0(n3281), .A1(n3647), .B0(n3280), .B1(n3573), .C0(n3831), .C1(n5160), .Y(n2411) );
OA21XLTS U3774 ( .A0(n3575), .A1(n3836), .B0(n2411), .Y(n4974) );
INVX2TS U3775 ( .A(n2412), .Y(n2415) );
INVX2TS U3776 ( .A(n2413), .Y(n2414) );
INVX2TS U3777 ( .A(n2416), .Y(n2451) );
INVX2TS U3778 ( .A(n2450), .Y(n2417) );
AOI21X1TS U3779 ( .A0(n2453), .A1(n2451), .B0(n2417), .Y(n2422) );
INVX2TS U3780 ( .A(n2418), .Y(n2420) );
NAND2X1TS U3781 ( .A(n2420), .B(n2419), .Y(n2421) );
XOR2X1TS U3782 ( .A(n2422), .B(n2421), .Y(n2423) );
INVX4TS U3783 ( .A(n4892), .Y(n3581) );
AOI222X1TS U3784 ( .A0(n3281), .A1(n3577), .B0(n3280), .B1(n3581), .C0(n3831), .C1(n3590), .Y(n2424) );
OA21XLTS U3785 ( .A0(n3583), .A1(n3836), .B0(n2424), .Y(n4969) );
INVX2TS U3786 ( .A(n2425), .Y(n2475) );
NAND2X1TS U3787 ( .A(n2475), .B(n2473), .Y(n2426) );
XNOR2X1TS U3788 ( .A(n3204), .B(n2426), .Y(n2427) );
INVX4TS U3789 ( .A(n3279), .Y(n3594) );
AOI222X1TS U3790 ( .A0(n3281), .A1(n3589), .B0(n3280), .B1(n3594), .C0(n3831), .C1(n5159), .Y(n2428) );
OA21XLTS U3791 ( .A0(n3597), .A1(n3836), .B0(n2428), .Y(n4962) );
INVX2TS U3792 ( .A(n2429), .Y(n2430) );
NAND2X1TS U3793 ( .A(n2430), .B(n2433), .Y(n2436) );
INVX2TS U3794 ( .A(n2431), .Y(n2434) );
AOI21X1TS U3795 ( .A0(n2434), .A1(n2433), .B0(n2432), .Y(n2435) );
INVX2TS U3796 ( .A(n2437), .Y(n2566) );
INVX2TS U3797 ( .A(n2565), .Y(n2438) );
AOI21X1TS U3798 ( .A0(n2568), .A1(n2566), .B0(n2438), .Y(n2443) );
INVX2TS U3799 ( .A(n2439), .Y(n2441) );
NAND2X1TS U3800 ( .A(n2441), .B(n2440), .Y(n2442) );
XOR2X1TS U3801 ( .A(n2443), .B(n2442), .Y(n2444) );
AOI222X1TS U3802 ( .A0(n3281), .A1(n3594), .B0(n3280), .B1(n3599), .C0(n3831), .C1(FPMULT_Op_MY[13]), .Y(n2445) );
OA21XLTS U3803 ( .A0(n3602), .A1(n3836), .B0(n2445), .Y(n4963) );
INVX2TS U3804 ( .A(n2547), .Y(n2446) );
NAND2X1TS U3805 ( .A(n2446), .B(n2546), .Y(n2447) );
XOR2X1TS U3806 ( .A(n2548), .B(n2447), .Y(n2448) );
AOI222X1TS U3807 ( .A0(n2327), .A1(n3629), .B0(n3830), .B1(FPMULT_Op_MY[7]),
.C0(n2330), .C1(FPMULT_Op_MY[6]), .Y(n2449) );
OA21XLTS U3808 ( .A0(n3693), .A1(n2317), .B0(n2449), .Y(n4958) );
NAND2X1TS U3809 ( .A(n2451), .B(n2450), .Y(n2452) );
XNOR2X1TS U3810 ( .A(n2453), .B(n2452), .Y(n2454) );
INVX4TS U3811 ( .A(n4970), .Y(n3728) );
CLKXOR2X2TS U3812 ( .A(n3728), .B(FPMULT_Op_MX[1]), .Y(n2456) );
NOR2X1TS U3813 ( .A(n2456), .B(n4941), .Y(n2581) );
BUFX4TS U3814 ( .A(n2581), .Y(n3725) );
XNOR2X1TS U3815 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MX[1]), .Y(n2455) );
AND3X2TS U3816 ( .A(n2456), .B(n2455), .C(n4941), .Y(n3769) );
INVX2TS U3817 ( .A(n3769), .Y(n2513) );
INVX4TS U3818 ( .A(n2513), .Y(n3740) );
AOI222X1TS U3819 ( .A0(n3725), .A1(n3581), .B0(n2497), .B1(n3585), .C0(n3740), .C1(n3595), .Y(n2457) );
INVX4TS U3820 ( .A(n4970), .Y(n3776) );
XOR2X1TS U3821 ( .A(n2458), .B(n3776), .Y(mult_x_69_n1215) );
AOI222X1TS U3822 ( .A0(n3725), .A1(n3577), .B0(n2497), .B1(n3581), .C0(n3740), .C1(n3590), .Y(n2459) );
XOR2X1TS U3823 ( .A(n2460), .B(n3776), .Y(mult_x_69_n1214) );
AOI222X1TS U3824 ( .A0(n3725), .A1(n3589), .B0(n2497), .B1(n3594), .C0(n3740), .C1(n5159), .Y(n2461) );
XOR2X1TS U3825 ( .A(n2462), .B(n3776), .Y(mult_x_69_n1217) );
OAI21X1TS U3826 ( .A0(n2535), .A1(n2531), .B0(n2532), .Y(n2469) );
INVX2TS U3827 ( .A(n2465), .Y(n2467) );
NAND2X1TS U3828 ( .A(n2467), .B(n2466), .Y(n2468) );
XNOR2X1TS U3829 ( .A(n2469), .B(n2468), .Y(n2470) );
INVX4TS U3830 ( .A(n4889), .Y(n3770) );
AOI222X1TS U3831 ( .A0(n2327), .A1(FPMULT_Op_MY[7]), .B0(n3830), .B1(n3770),
.C0(n2330), .C1(n3768), .Y(n2471) );
OA21XLTS U3832 ( .A0(n3775), .A1(n2317), .B0(n2471), .Y(n2472) );
CMPR32X2TS U3833 ( .A(n3728), .B(n3759), .C(n2472), .CO(mult_x_69_n596), .S(
mult_x_69_n597) );
INVX2TS U3834 ( .A(n2473), .Y(n2474) );
AOI21X1TS U3835 ( .A0(n3204), .A1(n2475), .B0(n2474), .Y(n2480) );
INVX2TS U3836 ( .A(n2476), .Y(n2478) );
NAND2X1TS U3837 ( .A(n2478), .B(n2477), .Y(n2479) );
XOR2X1TS U3838 ( .A(n2480), .B(n2479), .Y(n2481) );
AOI222X1TS U3839 ( .A0(n3725), .A1(n3585), .B0(n2497), .B1(n3589), .C0(n3740), .C1(n3600), .Y(n2482) );
XOR2X1TS U3840 ( .A(n2483), .B(n3776), .Y(mult_x_69_n1216) );
INVX2TS U3841 ( .A(n2484), .Y(n2487) );
INVX2TS U3842 ( .A(n2485), .Y(n2486) );
INVX2TS U3843 ( .A(n2488), .Y(n2557) );
INVX2TS U3844 ( .A(n2556), .Y(n2489) );
AOI21X1TS U3845 ( .A0(n2559), .A1(n2557), .B0(n2489), .Y(n2494) );
NAND2X1TS U3846 ( .A(n2492), .B(n2491), .Y(n2493) );
XOR2X1TS U3847 ( .A(n2494), .B(n2493), .Y(n2495) );
BUFX3TS U3848 ( .A(n2496), .Y(n3774) );
BUFX4TS U3849 ( .A(n2497), .Y(n3771) );
AOI222X1TS U3850 ( .A0(n3725), .A1(n3614), .B0(n3771), .B1(n3618), .C0(n3769), .C1(n3630), .Y(n2498) );
XOR2X1TS U3851 ( .A(n2499), .B(n3728), .Y(mult_x_69_n1222) );
INVX2TS U3852 ( .A(n3203), .Y(n2510) );
INVX2TS U3853 ( .A(n2502), .Y(n2503) );
AOI21X1TS U3854 ( .A0(n2505), .A1(n2504), .B0(n2503), .Y(n2506) );
OAI21X1TS U3855 ( .A0(n2508), .A1(n2507), .B0(n2506), .Y(n3202) );
XOR2X1TS U3856 ( .A(n2514), .B(n3728), .Y(mult_x_69_n1208) );
AOI222X1TS U3857 ( .A0(n3725), .A1(n3604), .B0(n2497), .B1(n3609), .C0(n3769), .C1(n3619), .Y(n2515) );
XOR2X1TS U3858 ( .A(n2516), .B(n3728), .Y(mult_x_69_n1220) );
AOI222X1TS U3859 ( .A0(n3725), .A1(n3643), .B0(n2497), .B1(n3573), .C0(n3740), .C1(n5160), .Y(n2517) );
XOR2X1TS U3860 ( .A(n2518), .B(n3776), .Y(mult_x_69_n1212) );
INVX2TS U3861 ( .A(n2519), .Y(n2520) );
AOI21X1TS U3862 ( .A0(n2522), .A1(n2521), .B0(n2520), .Y(n2527) );
NAND2X1TS U3863 ( .A(n2525), .B(n2524), .Y(n2526) );
XOR2X1TS U3864 ( .A(n2527), .B(n2526), .Y(n2528) );
AOI222X1TS U3865 ( .A0(n2327), .A1(n3708), .B0(n3280), .B1(n3697), .C0(n3831), .C1(n3732), .Y(n2529) );
OA21XLTS U3866 ( .A0(n3699), .A1(n2317), .B0(n2529), .Y(n2530) );
CMPR32X2TS U3867 ( .A(n3728), .B(n3755), .C(n2530), .CO(mult_x_69_n618), .S(
mult_x_69_n619) );
INVX2TS U3868 ( .A(n2531), .Y(n2533) );
NAND2X1TS U3869 ( .A(n2533), .B(n2532), .Y(n2534) );
XOR2X1TS U3870 ( .A(n2535), .B(n2534), .Y(n2536) );
AOI222X1TS U3871 ( .A0(n2327), .A1(n3770), .B0(n3280), .B1(n3708), .C0(n2330), .C1(n3759), .Y(n2537) );
OA21XLTS U3872 ( .A0(n3710), .A1(n2317), .B0(n2537), .Y(n2538) );
CMPR32X2TS U3873 ( .A(n3728), .B(n3732), .C(n2538), .CO(mult_x_69_n607), .S(
mult_x_69_n608) );
NAND2X1TS U3874 ( .A(n2540), .B(n2539), .Y(n2541) );
XNOR2X1TS U3875 ( .A(n2542), .B(n2541), .Y(n2543) );
AOI222X1TS U3876 ( .A0(n3725), .A1(n3609), .B0(n3771), .B1(n3614), .C0(n3769), .C1(n3625), .Y(n2544) );
XOR2X1TS U3877 ( .A(n2545), .B(n3728), .Y(mult_x_69_n1221) );
INVX2TS U3878 ( .A(n2549), .Y(n2551) );
NAND2X1TS U3879 ( .A(n2551), .B(n2550), .Y(n2552) );
XNOR2X1TS U3880 ( .A(n2553), .B(n2552), .Y(n2554) );
INVX4TS U3881 ( .A(n3200), .Y(n3624) );
OA21XLTS U3882 ( .A0(n3632), .A1(n2317), .B0(n2555), .Y(n4952) );
NAND2X1TS U3883 ( .A(n2557), .B(n2556), .Y(n2558) );
XNOR2X1TS U3884 ( .A(n2559), .B(n2558), .Y(n2560) );
AOI222X1TS U3885 ( .A0(n2327), .A1(n3618), .B0(n3830), .B1(n3624), .C0(n2330), .C1(n5158), .Y(n2562) );
OA21XLTS U3886 ( .A0(n3627), .A1(n2317), .B0(n2562), .Y(n4951) );
AOI222X1TS U3887 ( .A0(n3725), .A1(n3594), .B0(n2497), .B1(n3599), .C0(n3740), .C1(FPMULT_Op_MY[13]), .Y(n2563) );
XOR2X1TS U3888 ( .A(n2564), .B(n3776), .Y(mult_x_69_n1218) );
NAND2X1TS U3889 ( .A(n2566), .B(n2565), .Y(n2567) );
XNOR2X1TS U3890 ( .A(n2568), .B(n2567), .Y(n2569) );
AOI222X1TS U3891 ( .A0(n3281), .A1(n3599), .B0(n3280), .B1(n3604), .C0(n3831), .C1(FPMULT_Op_MY[12]), .Y(n2570) );
OA21XLTS U3892 ( .A0(n3606), .A1(n3836), .B0(n2570), .Y(n4946) );
NAND2X1TS U3893 ( .A(n2572), .B(n2571), .Y(n2573) );
XNOR2X1TS U3894 ( .A(n2574), .B(n2573), .Y(n2575) );
XOR2X1TS U3895 ( .A(n2577), .B(n3776), .Y(mult_x_69_n1213) );
AOI222X1TS U3896 ( .A0(n3725), .A1(n3599), .B0(n2497), .B1(n3604), .C0(n3740), .C1(FPMULT_Op_MY[12]), .Y(n2579) );
XOR2X1TS U3897 ( .A(n2580), .B(n3728), .Y(mult_x_69_n1219) );
BUFX3TS U3898 ( .A(n2581), .Y(n3772) );
AOI222X1TS U3899 ( .A0(n3772), .A1(n3630), .B0(n3771), .B1(n3629), .C0(n3769), .C1(n2241), .Y(n2582) );
XOR2X1TS U3900 ( .A(n2583), .B(n3728), .Y(mult_x_69_n1224) );
AOI222X1TS U3901 ( .A0(n3772), .A1(n3618), .B0(n3771), .B1(n3624), .C0(n3769), .C1(n5158), .Y(n2584) );
XOR2X1TS U3902 ( .A(n2585), .B(n3728), .Y(mult_x_69_n1223) );
OAI21XLTS U3903 ( .A0(n4386), .A1(n2247), .B0(n3063), .Y(n2080) );
INVX2TS U3904 ( .A(FPMULT_FS_Module_state_reg[1]), .Y(n3667) );
NOR2X1TS U3905 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n4872), .Y(n2591) );
NOR2BX1TS U3906 ( .AN(FPMULT_P_Sgf[47]), .B(n3670), .Y(n2588) );
NAND4X1TS U3907 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[0]), .C(n4872), .D(n3667), .Y(n4475) );
BUFX3TS U3908 ( .A(n4475), .Y(n4486) );
OAI211XLTS U3909 ( .A0(n2588), .A1(n5003), .B0(n4486), .C0(n4432), .Y(n1551)
);
INVX2TS U3910 ( .A(n4432), .Y(n4434) );
INVX2TS U3911 ( .A(n2588), .Y(n2589) );
OAI31X1TS U3912 ( .A0(n4434), .A1(n4488), .A2(n5007), .B0(n2589), .Y(n1550)
);
OR2X1TS U3913 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n2672) );
NOR2X2TS U3914 ( .A(n2672), .B(n4901), .Y(n3851) );
AOI32X4TS U3915 ( .A0(FPMULT_FSM_add_overflow_flag), .A1(
FPMULT_FS_Module_state_reg[1]), .A2(n3851), .B0(n2590), .B1(
FPMULT_FS_Module_state_reg[1]), .Y(n4437) );
AOI22X1TS U3916 ( .A0(n2280), .A1(n4199), .B0(n2277), .B1(
FPMULT_Add_result[3]), .Y(n2595) );
NAND2X1TS U3917 ( .A(n2592), .B(n4437), .Y(n2593) );
AOI22X1TS U3918 ( .A0(n4203), .A1(FPMULT_P_Sgf[25]), .B0(n2261), .B1(
FPMULT_Add_result[2]), .Y(n2594) );
OAI211XLTS U3919 ( .A0(n4094), .A1(n5124), .B0(n2595), .C0(n2594), .Y(n1519)
);
AOI22X1TS U3920 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n4199), .B0(
n2277), .B1(FPMULT_Add_result[1]), .Y(n2597) );
AOI22X1TS U3921 ( .A0(n4203), .A1(FPMULT_P_Sgf[23]), .B0(n2261), .B1(
FPMULT_Add_result[0]), .Y(n2596) );
OAI211XLTS U3922 ( .A0(n4094), .A1(n5126), .B0(n2597), .C0(n2596), .Y(n1517)
);
AOI22X1TS U3923 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4199), .B0(
n2277), .B1(FPMULT_Add_result[4]), .Y(n2599) );
AOI22X1TS U3924 ( .A0(n4203), .A1(FPMULT_P_Sgf[26]), .B0(n2261), .B1(
FPMULT_Add_result[3]), .Y(n2598) );
OAI211XLTS U3925 ( .A0(n4094), .A1(n5123), .B0(n2599), .C0(n2598), .Y(n1520)
);
AOI22X1TS U3926 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4199), .B0(
FPMULT_Add_result[6]), .B1(n2277), .Y(n2601) );
AOI22X1TS U3927 ( .A0(n4203), .A1(FPMULT_P_Sgf[28]), .B0(n2261), .B1(
FPMULT_Add_result[5]), .Y(n2600) );
OAI211XLTS U3928 ( .A0(n4094), .A1(n5129), .B0(n2601), .C0(n2600), .Y(n1522)
);
AOI22X1TS U3929 ( .A0(n2286), .A1(n4199), .B0(n2277), .B1(
FPMULT_Add_result[2]), .Y(n2603) );
AOI22X1TS U3930 ( .A0(n4203), .A1(FPMULT_P_Sgf[24]), .B0(n2261), .B1(
FPMULT_Add_result[1]), .Y(n2602) );
OAI211XLTS U3931 ( .A0(n4094), .A1(n5125), .B0(n2603), .C0(n2602), .Y(n1518)
);
AOI22X1TS U3932 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n4199), .B0(
n2277), .B1(FPMULT_Add_result[5]), .Y(n2605) );
AOI22X1TS U3933 ( .A0(n4203), .A1(FPMULT_P_Sgf[27]), .B0(n2261), .B1(
FPMULT_Add_result[4]), .Y(n2604) );
AOI22X1TS U3934 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4199), .B0(
FPMULT_Add_result[8]), .B1(n2277), .Y(n2607) );
AOI22X1TS U3935 ( .A0(FPMULT_Add_result[7]), .A1(n2261), .B0(n4203), .B1(
FPMULT_P_Sgf[30]), .Y(n2606) );
OAI211XLTS U3936 ( .A0(n4094), .A1(n5127), .B0(n2607), .C0(n2606), .Y(n1524)
);
AOI22X1TS U3937 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n4199), .B0(
FPMULT_Add_result[7]), .B1(n2277), .Y(n2609) );
AOI22X1TS U3938 ( .A0(FPMULT_Add_result[6]), .A1(n2261), .B0(n4203), .B1(
FPMULT_P_Sgf[29]), .Y(n2608) );
OAI211XLTS U3939 ( .A0(n4094), .A1(n5128), .B0(n2609), .C0(n2608), .Y(n1523)
);
AOI22X1TS U3940 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n4199), .B0(
FPMULT_Add_result[9]), .B1(n2277), .Y(n2611) );
AOI22X1TS U3941 ( .A0(FPMULT_Add_result[8]), .A1(n2261), .B0(n4203), .B1(
FPMULT_P_Sgf[31]), .Y(n2610) );
OAI211XLTS U3942 ( .A0(n4094), .A1(n2231), .B0(n2611), .C0(n2610), .Y(n1525)
);
AOI22X1TS U3943 ( .A0(FPMULT_FSM_selector_C), .A1(FPMULT_Add_result[23]),
.B0(FPMULT_P_Sgf[46]), .B1(n5059), .Y(n4436) );
AOI22X1TS U3944 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n4199), .B0(
n2258), .B1(n2261), .Y(n2614) );
NAND2X1TS U3945 ( .A(n2612), .B(FPMULT_P_Sgf[45]), .Y(n2613) );
OAI211XLTS U3946 ( .A0(n4437), .A1(n4436), .B0(n2614), .C0(n2613), .Y(n1539)
);
NAND3X1TS U3947 ( .A(FPSENCOS_cont_var_out[1]), .B(ready_add_subt), .C(n5077), .Y(n4297) );
INVX2TS U3948 ( .A(n4239), .Y(n2615) );
INVX2TS U3949 ( .A(n2634), .Y(n4277) );
NAND2X1TS U3950 ( .A(n4322), .B(n2206), .Y(n4284) );
AOI32X1TS U3951 ( .A0(n5157), .A1(n4271), .A2(n4277), .B0(
FPSENCOS_d_ff3_LUT_out[23]), .B1(n4283), .Y(n2616) );
NAND2X1TS U3952 ( .A(n5157), .B(n4914), .Y(intadd_489_CI) );
INVX2TS U3953 ( .A(n4284), .Y(n2618) );
AOI22X1TS U3954 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n2618), .B0(
FPSENCOS_d_ff3_sh_y_out[23]), .B1(n2243), .Y(n2617) );
AOI22X1TS U3955 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n2618), .B0(
FPSENCOS_d_ff3_sh_x_out[23]), .B1(n2243), .Y(n2619) );
NAND2X2TS U3956 ( .A(n4322), .B(n4994), .Y(n4286) );
AOI21X1TS U3957 ( .A0(n5157), .A1(n4261), .B0(FPSENCOS_cont_iter_out[3]),
.Y(n2643) );
AOI22X1TS U3958 ( .A0(n4271), .A1(n2643), .B0(FPSENCOS_d_ff3_LUT_out[26]),
.B1(n2243), .Y(n2620) );
NOR4X1TS U3959 ( .A(FPMULT_P_Sgf[14]), .B(FPMULT_P_Sgf[15]), .C(
FPMULT_P_Sgf[16]), .D(FPMULT_P_Sgf[17]), .Y(n2628) );
NOR4X1TS U3960 ( .A(FPMULT_P_Sgf[18]), .B(FPMULT_P_Sgf[19]), .C(
FPMULT_P_Sgf[20]), .D(FPMULT_P_Sgf[21]), .Y(n2627) );
NOR3XLTS U3961 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[0]), .C(
FPMULT_P_Sgf[1]), .Y(n2622) );
AND4X1TS U3962 ( .A(n2623), .B(n2228), .C(n2622), .D(n2621), .Y(n2626) );
XOR2X1TS U3963 ( .A(FPMULT_Op_MX[31]), .B(FPMULT_Op_MY[31]), .Y(n4494) );
MXI2X1TS U3964 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n4494), .Y(n2624) );
AOI31X1TS U3965 ( .A0(n2628), .A1(n2627), .A2(n2626), .B0(n2625), .Y(n2636)
);
INVX2TS U3966 ( .A(n3851), .Y(n2638) );
OAI221XLTS U3967 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(
FPMULT_FS_Module_state_reg[1]), .B0(n4989), .B1(n3667), .C0(n4872),
.Y(n2629) );
NOR3X1TS U3968 ( .A(n4261), .B(n2206), .C(n4280), .Y(n2631) );
AOI21X1TS U3969 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n4306), .B0(n2631),
.Y(n2630) );
AOI211X1TS U3970 ( .A0(n5157), .A1(n4894), .B0(n4261), .C0(n4286), .Y(n4276)
);
AOI21X1TS U3971 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n4332), .B0(n4276),
.Y(n2635) );
INVX2TS U3972 ( .A(n2636), .Y(n2637) );
OAI31X1TS U3973 ( .A0(FPMULT_FS_Module_state_reg[1]), .A1(n2638), .A2(n2637),
.B0(n5059), .Y(n1690) );
NAND2X1TS U3974 ( .A(n4274), .B(n4277), .Y(n4278) );
OAI2BB1X1TS U3975 ( .A0N(n2640), .A1N(n2639), .B0(n4322), .Y(n4265) );
INVX2TS U3976 ( .A(n4286), .Y(n4267) );
NAND2X1TS U3977 ( .A(n5157), .B(n4277), .Y(n2641) );
AOI22X1TS U3978 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n4283), .B0(n4267),
.B1(n2641), .Y(n2642) );
AOI22X1TS U3979 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n4283), .B0(n4267),
.B1(n2643), .Y(n2644) );
NAND2X1TS U3980 ( .A(n4267), .B(n4277), .Y(n2645) );
XNOR2X1TS U3981 ( .A(DP_OP_26J216_122_5882_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n2654) );
INVX2TS U3982 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n3865) );
INVX2TS U3983 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n2646) );
NAND2BX1TS U3984 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(n2649), .Y(n2650)
);
NOR2X1TS U3985 ( .A(n2650), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n2651) );
NAND2BX1TS U3986 ( .AN(n2654), .B(n2651), .Y(n4528) );
AND4X1TS U3987 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n2652) );
AND4X1TS U3988 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n2652), .Y(n2653) );
OAI2BB1X1TS U3989 ( .A0N(n2655), .A1N(n2654), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n3861) );
INVX2TS U3990 ( .A(n3861), .Y(n4529) );
AOI22X1TS U3991 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n4980), .B0(n2658), .B1(n4870), .Y(n2660) );
NAND4X1TS U3992 ( .A(n4994), .B(n2206), .C(n4894), .D(n2308), .Y(n2663) );
NAND2X1TS U3993 ( .A(n2663), .B(n4331), .Y(n2662) );
INVX2TS U3994 ( .A(n2664), .Y(n1765) );
INVX2TS U3995 ( .A(n2665), .Y(n1764) );
INVX2TS U3996 ( .A(n2666), .Y(n1760) );
INVX2TS U3997 ( .A(n2667), .Y(n1762) );
INVX2TS U3998 ( .A(n2669), .Y(n1763) );
INVX2TS U3999 ( .A(operation[2]), .Y(n4242) );
BUFX3TS U4000 ( .A(n3013), .Y(n4246) );
OAI2BB1X1TS U4001 ( .A0N(ack_operation), .A1N(n3013), .B0(n4249), .Y(n2670)
);
NAND2X1TS U4002 ( .A(n2671), .B(n2670), .Y(n3669) );
INVX2TS U4003 ( .A(n2358), .Y(n3857) );
OAI21XLTS U4004 ( .A0(n3670), .A1(FPMULT_P_Sgf[47]), .B0(n2672), .Y(n2673)
);
AOI2BB1XLTS U4005 ( .A0N(n3857), .A1N(FPMULT_zero_flag), .B0(n2673), .Y(
n2674) );
INVX2TS U4006 ( .A(n2675), .Y(n1766) );
NAND3X1TS U4007 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n2676),
.C(n4909), .Y(n4234) );
OAI31X1TS U4008 ( .A0(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .A1(n4903),
.A2(n4236), .B0(n4234), .Y(n4292) );
BUFX3TS U4009 ( .A(n4291), .Y(n4288) );
INVX2TS U4010 ( .A(operation[0]), .Y(n2677) );
NOR2XLTS U4011 ( .A(n4933), .B(n5081), .Y(FPMULT_S_Oper_A_exp[8]) );
NOR2X1TS U4012 ( .A(n5080), .B(FPADDSUB_intDX_EWSW[25]), .Y(n2738) );
AOI22X1TS U4013 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n5080), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n2679), .Y(n2683) );
OAI21X1TS U4014 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n5079), .B0(n2680), .Y(
n2739) );
NOR2X1TS U4015 ( .A(n4907), .B(FPADDSUB_intDX_EWSW[30]), .Y(n2686) );
NOR2X1TS U4016 ( .A(n5002), .B(FPADDSUB_intDX_EWSW[29]), .Y(n2684) );
AOI211X1TS U4017 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n5067), .B0(n2686),
.C0(n2684), .Y(n2737) );
NOR3X1TS U4018 ( .A(n5067), .B(n2684), .C(FPADDSUB_intDY_EWSW[28]), .Y(n2685) );
AOI221X1TS U4019 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n4907), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n5002), .C0(n2685), .Y(n2687) );
AOI2BB2X1TS U4020 ( .B0(n2688), .B1(n2737), .A0N(n2687), .A1N(n2686), .Y(
n2743) );
NOR2X1TS U4021 ( .A(n4993), .B(FPADDSUB_intDX_EWSW[17]), .Y(n2724) );
NOR2X1TS U4022 ( .A(n4992), .B(FPADDSUB_intDX_EWSW[11]), .Y(n2703) );
AOI21X1TS U4023 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n5045), .B0(n2703), .Y(
n2708) );
OAI2BB1X1TS U4024 ( .A0N(n5060), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n2689) );
OAI22X1TS U4025 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2689), .B0(n5060), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n2700) );
OAI2BB1X1TS U4026 ( .A0N(n5069), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n2690) );
OAI22X1TS U4027 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n2690), .B0(n5069), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n2699) );
OAI21XLTS U4028 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n4979), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n2691) );
OAI2BB2XLTS U4029 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n2691), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n4979), .Y(n2693) );
NAND2BXLTS U4030 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n2692) );
OAI21XLTS U4031 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n4986), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n2694) );
AOI2BB2XLTS U4032 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n4986), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n2694), .Y(n2695) );
AOI22X1TS U4033 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n5069), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n4918), .Y(n2697) );
OAI32X1TS U4034 ( .A0(n2700), .A1(n2699), .A2(n2698), .B0(n2697), .B1(n2699),
.Y(n2718) );
OA22X1TS U4035 ( .A0(n4977), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n4897), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n2715) );
OAI2BB2XLTS U4036 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n2702), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n4990), .Y(n2714) );
AOI22X1TS U4037 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n4992), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n2704), .Y(n2710) );
AOI21X1TS U4038 ( .A0(n2707), .A1(n2706), .B0(n2717), .Y(n2709) );
OAI2BB2XLTS U4039 ( .B0(n2710), .B1(n2717), .A0N(n2709), .A1N(n2708), .Y(
n2713) );
OAI2BB2XLTS U4040 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n2711), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n4897), .Y(n2712) );
AOI211X1TS U4041 ( .A0(n2715), .A1(n2714), .B0(n2713), .C0(n2712), .Y(n2716)
);
OAI31X1TS U4042 ( .A0(n2719), .A1(n2718), .A2(n2717), .B0(n2716), .Y(n2722)
);
OA22X1TS U4043 ( .A0(n4987), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n4900), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n2735) );
OAI21X1TS U4044 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n5000), .B0(n2726), .Y(
n2730) );
OAI2BB2XLTS U4045 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n2723), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n4997), .Y(n2734) );
AOI22X1TS U4046 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n4993), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n2725), .Y(n2728) );
AOI32X1TS U4047 ( .A0(n5000), .A1(n2726), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n4905), .Y(n2727) );
OAI32X1TS U4048 ( .A0(n2730), .A1(n2729), .A2(n2728), .B0(n2727), .B1(n2729),
.Y(n2733) );
OAI2BB2XLTS U4049 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n2731), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n4900), .Y(n2732) );
AOI211X1TS U4050 ( .A0(n2735), .A1(n2734), .B0(n2733), .C0(n2732), .Y(n2741)
);
NAND4BBX1TS U4051 ( .AN(n2739), .BN(n2738), .C(n2737), .D(n2736), .Y(n2740)
);
AOI32X4TS U4052 ( .A0(n2743), .A1(n2742), .A2(n2741), .B0(n2740), .B1(n2743),
.Y(n4631) );
AND2X2TS U4053 ( .A(n5156), .B(n4631), .Y(n2805) );
AOI22X1TS U4054 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n2772), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n4637), .Y(n2744) );
AOI22X1TS U4055 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n2772), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n4637), .Y(n2745) );
AOI22X1TS U4056 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n2772), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n4254), .Y(n2746) );
INVX2TS U4057 ( .A(n2813), .Y(n2843) );
AOI22X1TS U4058 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n2772), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n4637), .Y(n2747) );
INVX3TS U4059 ( .A(n4331), .Y(n2788) );
BUFX3TS U4060 ( .A(n4319), .Y(n2787) );
INVX2TS U4061 ( .A(n2748), .Y(n1759) );
INVX2TS U4062 ( .A(n2750), .Y(n1761) );
AOI22X1TS U4063 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n2805), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n2838), .Y(n2751) );
AOI22X1TS U4064 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n2805), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n2838), .Y(n2752) );
AOI22X1TS U4065 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n2813), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n2838), .Y(n2753) );
AOI22X1TS U4066 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n2805), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n2838), .Y(n2754) );
AOI22X1TS U4067 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n2805), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n2838), .Y(n2755) );
AOI22X1TS U4068 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n2805), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n2838), .Y(n2756) );
AOI22X1TS U4069 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n2813), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n2838), .Y(n2757) );
INVX2TS U4070 ( .A(n2758), .Y(n1757) );
INVX2TS U4071 ( .A(n2759), .Y(n1747) );
INVX2TS U4072 ( .A(n2760), .Y(n1751) );
BUFX3TS U4073 ( .A(n4319), .Y(n2783) );
INVX2TS U4074 ( .A(n2761), .Y(n1749) );
INVX2TS U4075 ( .A(n2762), .Y(n1746) );
INVX2TS U4076 ( .A(n2763), .Y(n1753) );
INVX2TS U4077 ( .A(n2764), .Y(n1752) );
INVX2TS U4078 ( .A(n2765), .Y(n1745) );
INVX2TS U4079 ( .A(n2766), .Y(n1744) );
INVX2TS U4080 ( .A(n2767), .Y(n1743) );
INVX2TS U4081 ( .A(n2768), .Y(n1750) );
INVX2TS U4082 ( .A(n2769), .Y(n1748) );
INVX2TS U4083 ( .A(n2770), .Y(n1742) );
INVX2TS U4084 ( .A(n2771), .Y(n1741) );
INVX2TS U4085 ( .A(n2772), .Y(n2793) );
AOI22X1TS U4086 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n4637), .Y(n2773) );
AOI22X1TS U4087 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n4637), .Y(n2774) );
BUFX3TS U4088 ( .A(n2668), .Y(n2786) );
INVX2TS U4089 ( .A(n2775), .Y(n1755) );
INVX2TS U4090 ( .A(n2776), .Y(n1735) );
INVX2TS U4091 ( .A(n2777), .Y(n1738) );
INVX2TS U4092 ( .A(n2778), .Y(n1756) );
AOI222X1TS U4093 ( .A0(n2784), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n2783), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n2786), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n2779) );
INVX2TS U4094 ( .A(n2779), .Y(n1737) );
INVX2TS U4095 ( .A(n2780), .Y(n1758) );
INVX2TS U4096 ( .A(n2781), .Y(n1739) );
INVX2TS U4097 ( .A(n2782), .Y(n1736) );
INVX2TS U4098 ( .A(n2785), .Y(n1740) );
INVX2TS U4099 ( .A(n2789), .Y(n1754) );
AOI22X1TS U4100 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n4637), .Y(n2790) );
AOI22X1TS U4101 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n4637), .Y(n2791) );
AOI22X1TS U4102 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n4637), .Y(n2792) );
AOI22X1TS U4103 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n4637), .Y(n2794) );
AOI22X1TS U4104 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n5244), .Y(n2795) );
AOI22X1TS U4105 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n4637), .Y(n2796) );
AOI22X1TS U4106 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n2805), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n2838), .Y(n2797) );
AOI22X1TS U4107 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n2813), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n5244), .Y(n2798) );
AOI22X1TS U4108 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2813), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n2838), .Y(n2799) );
AOI22X1TS U4109 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n5244), .Y(n2800) );
AOI22X1TS U4110 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n5244), .Y(n2801) );
AOI22X1TS U4111 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n2810), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n5244), .Y(n2802) );
AOI22X1TS U4112 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n2838), .Y(n2803) );
AOI22X1TS U4113 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n5244), .Y(n2804) );
AOI22X1TS U4114 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n2805), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n5244), .Y(n2806) );
AOI22X1TS U4115 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n5244), .Y(n2807) );
AOI22X1TS U4116 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n5244), .Y(n2808) );
AOI22X1TS U4117 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n5244), .Y(n2809) );
AOI22X1TS U4118 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n2810), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n5244), .Y(n2811) );
AOI22X1TS U4119 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n4254), .Y(n2814) );
AOI22X1TS U4120 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n4254), .Y(n2815) );
AOI22X1TS U4121 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n4254), .Y(n2816) );
AOI22X1TS U4122 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n4254), .Y(n2817) );
AOI22X1TS U4123 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n4254), .Y(n2818) );
AOI22X1TS U4124 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n4254), .Y(n2819) );
AOI22X1TS U4125 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n4254), .Y(n2820) );
INVX2TS U4126 ( .A(n2821), .Y(n4252) );
BUFX3TS U4127 ( .A(n2823), .Y(n2885) );
XNOR2X1TS U4128 ( .A(FPSENCOS_d_ff1_operation_out), .B(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(n2824) );
XNOR2X1TS U4129 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .B(n2824),
.Y(n2826) );
BUFX3TS U4130 ( .A(n2823), .Y(n2866) );
NOR2X1TS U4131 ( .A(n2866), .B(n2826), .Y(n2855) );
INVX2TS U4132 ( .A(n2855), .Y(n2851) );
INVX4TS U4133 ( .A(n2851), .Y(n2887) );
INVX2TS U4134 ( .A(n2827), .Y(n1723) );
INVX2TS U4135 ( .A(n2828), .Y(n1724) );
INVX2TS U4136 ( .A(n2829), .Y(n1725) );
AOI22X1TS U4137 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n4254), .Y(n2830) );
AOI22X1TS U4138 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n4254), .Y(n2831) );
AOI22X1TS U4139 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n2833), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n4254), .Y(n2832) );
BUFX3TS U4140 ( .A(n2833), .Y(n2869) );
AOI22X1TS U4141 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n2869), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n2838), .Y(n2834) );
AOI22X1TS U4142 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n2869), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n2838), .Y(n2835) );
AOI22X1TS U4143 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n2869), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n4637), .Y(n2836) );
AOI22X1TS U4144 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n2869), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n5244), .Y(n2837) );
AOI22X1TS U4145 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n2869), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n2838), .Y(n2839) );
AOI22X1TS U4146 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n2869), .B0(
FPADDSUB_DMP_EXP_EWSW[27]), .B1(n5244), .Y(n2840) );
AOI22X1TS U4147 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n2869), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n4637), .Y(n2841) );
AOI22X1TS U4148 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n2869), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n5244), .Y(n2842) );
AOI22X1TS U4149 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n2869), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n4637), .Y(n2844) );
AOI222X1TS U4150 ( .A0(n2869), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DMP_EXP_EWSW[23]), .B1(n2838), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n2813), .Y(n2846) );
INVX2TS U4151 ( .A(n2846), .Y(n1467) );
XNOR2X1TS U4152 ( .A(n2847), .B(FPSENCOS_d_ff_Xn[31]), .Y(n2850) );
AOI22X1TS U4153 ( .A0(n2866), .A1(cordic_result[31]), .B0(n2865), .B1(n2848),
.Y(n2849) );
INVX4TS U4154 ( .A(n2851), .Y(n2883) );
INVX2TS U4155 ( .A(n2852), .Y(n1709) );
INVX2TS U4156 ( .A(n2853), .Y(n1707) );
INVX2TS U4157 ( .A(n2854), .Y(n1702) );
INVX2TS U4158 ( .A(n2856), .Y(n1704) );
INVX2TS U4159 ( .A(n2857), .Y(n1705) );
INVX2TS U4160 ( .A(n2858), .Y(n1703) );
INVX2TS U4161 ( .A(n2859), .Y(n1699) );
INVX2TS U4162 ( .A(n2860), .Y(n1708) );
INVX2TS U4163 ( .A(n2861), .Y(n1727) );
INVX2TS U4164 ( .A(n2862), .Y(n1701) );
INVX2TS U4165 ( .A(n2863), .Y(n1700) );
INVX2TS U4166 ( .A(n2864), .Y(n1698) );
INVX2TS U4167 ( .A(n2867), .Y(n1706) );
INVX2TS U4168 ( .A(n2868), .Y(overflow_flag) );
INVX2TS U4169 ( .A(n2870), .Y(n1419) );
INVX2TS U4170 ( .A(n2871), .Y(n1722) );
INVX2TS U4171 ( .A(n2872), .Y(n1726) );
INVX2TS U4172 ( .A(n2873), .Y(n1721) );
INVX2TS U4173 ( .A(n2874), .Y(n1728) );
INVX2TS U4174 ( .A(n2875), .Y(n1712) );
INVX2TS U4175 ( .A(n2876), .Y(n1714) );
INVX2TS U4176 ( .A(n2877), .Y(n1710) );
INVX2TS U4177 ( .A(n2878), .Y(n1720) );
INVX2TS U4178 ( .A(n2879), .Y(n1711) );
INVX2TS U4179 ( .A(n2880), .Y(n1716) );
INVX2TS U4180 ( .A(n2881), .Y(n1715) );
INVX2TS U4181 ( .A(n2882), .Y(n1718) );
INVX2TS U4182 ( .A(n2884), .Y(n1713) );
INVX2TS U4183 ( .A(n2886), .Y(n1719) );
INVX2TS U4184 ( .A(n2889), .Y(n1717) );
AOI2BB2XLTS U4185 ( .B0(FPSENCOS_d_ff3_sign_out), .B1(n5077), .A0N(n5077),
.A1N(FPSENCOS_d_ff3_sign_out), .Y(n2891) );
AOI22X1TS U4186 ( .A0(operation[0]), .A1(n4380), .B0(FPADDSUB_intAS), .B1(
n4405), .Y(n2890) );
INVX4TS U4187 ( .A(n4336), .Y(n2988) );
AOI22X1TS U4188 ( .A0(Data_2[2]), .A1(n4380), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n4340), .Y(n2895) );
AOI22X1TS U4189 ( .A0(n4337), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n2894) );
AOI22X1TS U4190 ( .A0(Data_2[0]), .A1(n4361), .B0(FPADDSUB_intDY_EWSW[0]),
.B1(n4340), .Y(n2897) );
BUFX3TS U4191 ( .A(n2923), .Y(n2978) );
AOI22X1TS U4192 ( .A0(n4337), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n2978),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n2896) );
AOI22X1TS U4193 ( .A0(Data_2[4]), .A1(n4380), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n4340), .Y(n2899) );
AOI22X1TS U4194 ( .A0(n4337), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n2898) );
AOI22X1TS U4195 ( .A0(Data_1[31]), .A1(n4361), .B0(FPADDSUB_intDX_EWSW[31]),
.B1(n4340), .Y(n2901) );
AOI22X1TS U4196 ( .A0(n4337), .A1(n2270), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n2900) );
AOI22X1TS U4197 ( .A0(Data_2[1]), .A1(n4380), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n4340), .Y(n2903) );
AOI22X1TS U4198 ( .A0(n4337), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n2902) );
AOI22X1TS U4199 ( .A0(Data_1[30]), .A1(n4361), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n4340), .Y(n2905) );
AOI22X1TS U4200 ( .A0(n4337), .A1(FPSENCOS_d_ff2_X[30]), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n2904) );
INVX1TS U4201 ( .A(FPSENCOS_d_ff2_Y[28]), .Y(n4323) );
BUFX3TS U4202 ( .A(n4340), .Y(n2977) );
AOI22X1TS U4203 ( .A0(Data_1[28]), .A1(n4380), .B0(FPADDSUB_intDX_EWSW[28]),
.B1(n2977), .Y(n2907) );
AOI22X1TS U4204 ( .A0(n4337), .A1(FPSENCOS_d_ff2_X[28]), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n2906) );
AOI22X1TS U4205 ( .A0(Data_1[26]), .A1(n4361), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n2977), .Y(n2909) );
AOI22X1TS U4206 ( .A0(n4337), .A1(FPSENCOS_d_ff2_X[26]), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n2908) );
AOI22X1TS U4207 ( .A0(Data_1[29]), .A1(n4380), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n4340), .Y(n2911) );
AOI22X1TS U4208 ( .A0(n4337), .A1(FPSENCOS_d_ff2_X[29]), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n2910) );
AOI22X1TS U4209 ( .A0(Data_1[27]), .A1(n4380), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n2977), .Y(n2913) );
AOI22X1TS U4210 ( .A0(n4337), .A1(FPSENCOS_d_ff2_X[27]), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n2912) );
AOI22X1TS U4211 ( .A0(Data_2[9]), .A1(n4361), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n4365), .Y(n2916) );
BUFX3TS U4212 ( .A(n2982), .Y(n4362) );
AOI22X1TS U4213 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n2915) );
INVX4TS U4214 ( .A(n4336), .Y(n2985) );
AOI22X1TS U4215 ( .A0(Data_2[10]), .A1(n4361), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n4365), .Y(n2918) );
AOI22X1TS U4216 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n2917) );
AOI22X1TS U4217 ( .A0(Data_2[12]), .A1(n4380), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n4365), .Y(n2920) );
AOI22X1TS U4218 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n2919) );
INVX4TS U4219 ( .A(n4336), .Y(n2996) );
AOI22X1TS U4220 ( .A0(Data_1[21]), .A1(n4366), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n2977), .Y(n2922) );
BUFX3TS U4221 ( .A(n2982), .Y(n2979) );
AOI22X1TS U4222 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[21]), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n2921) );
BUFX3TS U4223 ( .A(n4366), .Y(n4406) );
AOI22X1TS U4224 ( .A0(Data_1[8]), .A1(n4406), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n2972), .Y(n2925) );
BUFX3TS U4225 ( .A(n2982), .Y(n2974) );
AOI22X1TS U4226 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[8]), .B0(n4374), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n2924) );
AOI22X1TS U4227 ( .A0(Data_1[9]), .A1(n4377), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n2972), .Y(n2927) );
BUFX3TS U4228 ( .A(n2923), .Y(n2973) );
AOI22X1TS U4229 ( .A0(n2974), .A1(n2271), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n2926) );
AOI22X1TS U4230 ( .A0(Data_1[11]), .A1(n4406), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n2972), .Y(n2929) );
AOI22X1TS U4231 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[11]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n2928) );
AOI22X1TS U4232 ( .A0(Data_1[17]), .A1(n4366), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n2977), .Y(n2931) );
AOI22X1TS U4233 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[17]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n2930) );
AOI22X1TS U4234 ( .A0(Data_1[18]), .A1(n4377), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n2977), .Y(n2933) );
AOI22X1TS U4235 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[18]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n2932) );
AOI22X1TS U4236 ( .A0(Data_1[1]), .A1(n4361), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n4365), .Y(n2935) );
AOI22X1TS U4237 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[1]), .B0(n4374), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n2934) );
AOI22X1TS U4238 ( .A0(Data_1[2]), .A1(n4406), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n4405), .Y(n2937) );
AOI22X1TS U4239 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[2]), .B0(n4374), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n2936) );
AOI22X1TS U4240 ( .A0(Data_1[20]), .A1(n4377), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n2977), .Y(n2939) );
AOI22X1TS U4241 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[20]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n2938) );
AOI22X1TS U4242 ( .A0(Data_1[13]), .A1(n4377), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n2972), .Y(n2941) );
AOI22X1TS U4243 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[13]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n2940) );
AOI22X1TS U4244 ( .A0(Data_1[15]), .A1(n4377), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n2972), .Y(n2943) );
AOI22X1TS U4245 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[15]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n2942) );
AOI22X1TS U4246 ( .A0(Data_1[12]), .A1(n4377), .B0(FPADDSUB_intDX_EWSW[12]),
.B1(n2972), .Y(n2945) );
AOI22X1TS U4247 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[12]), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n2944) );
AOI22X1TS U4248 ( .A0(Data_1[19]), .A1(n4366), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n2977), .Y(n2947) );
AOI22X1TS U4249 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[19]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n2946) );
AOI22X1TS U4250 ( .A0(Data_1[14]), .A1(n4377), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n2972), .Y(n2949) );
AOI22X1TS U4251 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[14]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n2948) );
AOI22X1TS U4252 ( .A0(Data_1[22]), .A1(n4377), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n2977), .Y(n2951) );
AOI22X1TS U4253 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[22]), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n2950) );
AOI22X1TS U4254 ( .A0(Data_2[8]), .A1(n4361), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n4340), .Y(n2953) );
AOI22X1TS U4255 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n2952) );
AOI22X1TS U4256 ( .A0(Data_1[3]), .A1(n4406), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n4405), .Y(n2955) );
AOI22X1TS U4257 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[3]), .B0(n4374), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n2954) );
AOI22X1TS U4258 ( .A0(Data_1[25]), .A1(n4377), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n2977), .Y(n2957) );
AOI22X1TS U4259 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[25]), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n2956) );
AOI22X1TS U4260 ( .A0(Data_1[24]), .A1(n4377), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n2977), .Y(n2959) );
AOI22X1TS U4261 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[24]), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n2958) );
AOI22X1TS U4262 ( .A0(n4366), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n4405), .Y(n2961) );
AOI22X1TS U4263 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[0]), .B0(
FPSENCOS_d_ff2_Z[0]), .B1(n4374), .Y(n2960) );
AOI22X1TS U4264 ( .A0(Data_1[6]), .A1(n4406), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n2972), .Y(n2963) );
AOI22X1TS U4265 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[6]), .B0(n4374), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n2962) );
AOI22X1TS U4266 ( .A0(Data_1[10]), .A1(n4406), .B0(FPADDSUB_intDX_EWSW[10]),
.B1(n2972), .Y(n2965) );
AOI22X1TS U4267 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[10]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n2964) );
AOI22X1TS U4268 ( .A0(Data_1[4]), .A1(n4406), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n4365), .Y(n2967) );
AOI22X1TS U4269 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[4]), .B0(n4374), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n2966) );
AOI22X1TS U4270 ( .A0(Data_1[16]), .A1(n4366), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n2972), .Y(n2969) );
AOI22X1TS U4271 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[16]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n2968) );
AOI22X1TS U4272 ( .A0(Data_1[5]), .A1(n4406), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n2972), .Y(n2971) );
AOI22X1TS U4273 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[5]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n2970) );
AOI22X1TS U4274 ( .A0(Data_1[7]), .A1(n4406), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n2972), .Y(n2976) );
AOI22X1TS U4275 ( .A0(n2974), .A1(FPSENCOS_d_ff2_X[7]), .B0(n2973), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n2975) );
AOI22X1TS U4276 ( .A0(Data_1[23]), .A1(n4406), .B0(FPADDSUB_intDX_EWSW[23]),
.B1(n2977), .Y(n2981) );
AOI22X1TS U4277 ( .A0(n2979), .A1(FPSENCOS_d_ff2_X[23]), .B0(n2978), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n2980) );
AOI22X1TS U4278 ( .A0(Data_2[26]), .A1(n4366), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n4405), .Y(n2984) );
AOI22X1TS U4279 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n2983) );
AOI22X1TS U4280 ( .A0(Data_2[25]), .A1(n4366), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n4405), .Y(n2987) );
AOI22X1TS U4281 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n2986) );
AOI22X1TS U4282 ( .A0(Data_2[21]), .A1(n4361), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n4405), .Y(n2990) );
AOI22X1TS U4283 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n2989) );
AOI22X1TS U4284 ( .A0(Data_2[23]), .A1(n4366), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n4405), .Y(n2992) );
AOI22X1TS U4285 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n2991) );
AOI22X1TS U4286 ( .A0(Data_2[24]), .A1(n4377), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n4405), .Y(n2995) );
AOI22X1TS U4287 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n2993),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n2994) );
OR4X2TS U4288 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[19]), .D(
n3000), .Y(n3080) );
NAND4X1TS U4289 ( .A(n4890), .B(n4869), .C(n4955), .D(n3045), .Y(n3042) );
NOR2X2TS U4290 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n2999), .Y(n3068) );
INVX2TS U4291 ( .A(n3068), .Y(n3048) );
NOR2X2TS U4292 ( .A(n3048), .B(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n3084) );
NAND2X1TS U4293 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n3084), .Y(n3046) );
OAI22X1TS U4294 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n3046), .B0(n4995),
.B1(n3080), .Y(n3069) );
AOI32X1TS U4295 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n4873), .A2(n4904),
.B0(FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n4873), .Y(n2997) );
NOR2X2TS U4296 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n3054), .Y(n3083) );
AOI211X1TS U4297 ( .A0(n4875), .A1(n2997), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C0(n3001), .Y(n2998) );
AOI21X1TS U4298 ( .A0(n4931), .A1(n4878), .B0(n2999), .Y(n3043) );
NAND2X1TS U4299 ( .A(n4906), .B(n4996), .Y(n3070) );
INVX2TS U4300 ( .A(n3001), .Y(n3062) );
NAND3X2TS U4301 ( .A(n3062), .B(n4902), .C(n4875), .Y(n3059) );
OAI22X1TS U4302 ( .A0(n4902), .A1(n3001), .B0(n3059), .B1(n4873), .Y(n3002)
);
NAND2X1TS U4303 ( .A(n4256), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n3005)
);
BUFX3TS U4304 ( .A(n3007), .Y(n3041) );
AOI22X1TS U4305 ( .A0(cordic_result[31]), .A1(n4247), .B0(n4246), .B1(
mult_result[31]), .Y(n3009) );
OAI21XLTS U4306 ( .A0(n3041), .A1(n4913), .B0(n3009), .Y(op_result[31]) );
AOI22X1TS U4307 ( .A0(n4247), .A1(cordic_result[21]), .B0(n4246), .B1(
mult_result[21]), .Y(n3010) );
OAI21XLTS U4308 ( .A0(n3041), .A1(n5018), .B0(n3010), .Y(op_result[21]) );
AOI22X1TS U4309 ( .A0(n4247), .A1(cordic_result[24]), .B0(n4246), .B1(
mult_result[24]), .Y(n3011) );
BUFX3TS U4310 ( .A(n3012), .Y(n3037) );
AOI22X1TS U4311 ( .A0(cordic_result[10]), .A1(n3037), .B0(n3036), .B1(
mult_result[10]), .Y(n3014) );
OAI21XLTS U4312 ( .A0(n3007), .A1(n5029), .B0(n3014), .Y(op_result[10]) );
AOI22X1TS U4313 ( .A0(cordic_result[11]), .A1(n3037), .B0(n3036), .B1(
mult_result[11]), .Y(n3015) );
OAI21XLTS U4314 ( .A0(n3007), .A1(n5027), .B0(n3015), .Y(op_result[11]) );
AOI22X1TS U4315 ( .A0(cordic_result[12]), .A1(n3037), .B0(n3036), .B1(
mult_result[12]), .Y(n3016) );
OAI21XLTS U4316 ( .A0(n3007), .A1(n5030), .B0(n3016), .Y(op_result[12]) );
AOI22X1TS U4317 ( .A0(n3012), .A1(cordic_result[2]), .B0(n3013), .B1(
mult_result[2]), .Y(n3017) );
AOI22X1TS U4318 ( .A0(n4247), .A1(cordic_result[27]), .B0(n4246), .B1(
mult_result[27]), .Y(n3018) );
OAI21XLTS U4319 ( .A0(n3041), .A1(n5039), .B0(n3018), .Y(op_result[27]) );
AOI22X1TS U4320 ( .A0(cordic_result[13]), .A1(n3037), .B0(n3036), .B1(
mult_result[13]), .Y(n3019) );
OAI21XLTS U4321 ( .A0(n3007), .A1(n5024), .B0(n3019), .Y(op_result[13]) );
AOI22X1TS U4322 ( .A0(n4247), .A1(cordic_result[28]), .B0(n4246), .B1(
mult_result[28]), .Y(n3020) );
OAI21XLTS U4323 ( .A0(n3041), .A1(n5038), .B0(n3020), .Y(op_result[28]) );
AOI22X1TS U4324 ( .A0(cordic_result[17]), .A1(n3037), .B0(n3036), .B1(
mult_result[17]), .Y(n3021) );
OAI21XLTS U4325 ( .A0(n3041), .A1(n5021), .B0(n3021), .Y(op_result[17]) );
AOI22X1TS U4326 ( .A0(cordic_result[14]), .A1(n3037), .B0(n3036), .B1(
mult_result[14]), .Y(n3022) );
OAI21XLTS U4327 ( .A0(n3007), .A1(n5028), .B0(n3022), .Y(op_result[14]) );
AOI22X1TS U4328 ( .A0(n4247), .A1(cordic_result[20]), .B0(n4246), .B1(
mult_result[20]), .Y(n3023) );
AOI22X1TS U4329 ( .A0(cordic_result[8]), .A1(n3037), .B0(n3036), .B1(
mult_result[8]), .Y(n3024) );
OAI21XLTS U4330 ( .A0(n3007), .A1(n5026), .B0(n3024), .Y(op_result[8]) );
AOI22X1TS U4331 ( .A0(cordic_result[15]), .A1(n3037), .B0(n3036), .B1(
mult_result[15]), .Y(n3025) );
OAI21XLTS U4332 ( .A0(n3007), .A1(n5016), .B0(n3025), .Y(op_result[15]) );
AOI22X1TS U4333 ( .A0(n3012), .A1(cordic_result[4]), .B0(n3013), .B1(
mult_result[4]), .Y(n3026) );
OAI21XLTS U4334 ( .A0(n3007), .A1(n5022), .B0(n3026), .Y(op_result[4]) );
AOI22X1TS U4335 ( .A0(n3012), .A1(cordic_result[0]), .B0(n3013), .B1(
mult_result[0]), .Y(n3027) );
AOI22X1TS U4336 ( .A0(n4247), .A1(cordic_result[19]), .B0(n3036), .B1(
mult_result[19]), .Y(n3028) );
OAI21XLTS U4337 ( .A0(n3041), .A1(n5019), .B0(n3028), .Y(op_result[19]) );
AOI22X1TS U4338 ( .A0(n3012), .A1(cordic_result[1]), .B0(n3013), .B1(
mult_result[1]), .Y(n3029) );
OAI21XLTS U4339 ( .A0(n3007), .A1(n5035), .B0(n3029), .Y(op_result[1]) );
AOI22X1TS U4340 ( .A0(cordic_result[7]), .A1(n3037), .B0(n3036), .B1(
mult_result[7]), .Y(n3030) );
OAI21XLTS U4341 ( .A0(n3007), .A1(n5033), .B0(n3030), .Y(op_result[7]) );
AOI22X1TS U4342 ( .A0(cordic_result[16]), .A1(n3037), .B0(n3036), .B1(
mult_result[16]), .Y(n3031) );
OAI21XLTS U4343 ( .A0(n3041), .A1(n5025), .B0(n3031), .Y(op_result[16]) );
AOI22X1TS U4344 ( .A0(cordic_result[6]), .A1(n3037), .B0(n3036), .B1(
mult_result[6]), .Y(n3032) );
OAI21XLTS U4345 ( .A0(n3007), .A1(n5023), .B0(n3032), .Y(op_result[6]) );
AOI22X1TS U4346 ( .A0(cordic_result[9]), .A1(n3037), .B0(n3036), .B1(
mult_result[9]), .Y(n3033) );
OAI21XLTS U4347 ( .A0(n3007), .A1(n5036), .B0(n3033), .Y(op_result[9]) );
AOI22X1TS U4348 ( .A0(n4247), .A1(cordic_result[22]), .B0(n4246), .B1(
mult_result[22]), .Y(n3034) );
OAI21XLTS U4349 ( .A0(n3041), .A1(n5015), .B0(n3034), .Y(op_result[22]) );
AOI22X1TS U4350 ( .A0(n3012), .A1(cordic_result[3]), .B0(n3013), .B1(
mult_result[3]), .Y(n3035) );
OAI21XLTS U4351 ( .A0(n3007), .A1(n5031), .B0(n3035), .Y(op_result[3]) );
AOI22X1TS U4352 ( .A0(cordic_result[18]), .A1(n3037), .B0(n3036), .B1(
mult_result[18]), .Y(n3038) );
OAI21XLTS U4353 ( .A0(n3041), .A1(n5017), .B0(n3038), .Y(op_result[18]) );
AOI22X1TS U4354 ( .A0(n3012), .A1(cordic_result[5]), .B0(n3013), .B1(
mult_result[5]), .Y(n3039) );
AOI22X1TS U4355 ( .A0(n4247), .A1(cordic_result[26]), .B0(n4246), .B1(
mult_result[26]), .Y(n3040) );
OAI21XLTS U4356 ( .A0(n3041), .A1(n5041), .B0(n3040), .Y(op_result[26]) );
NOR2X1TS U4357 ( .A(FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n3056) );
NAND3XLTS U4358 ( .A(n4890), .B(n4869), .C(n4955), .Y(n3044) );
AOI211X1TS U4359 ( .A0(n3045), .A1(n3044), .B0(n3082), .C0(n3043), .Y(n3047)
);
OAI211XLTS U4360 ( .A0(n3048), .A1(n4908), .B0(n3047), .C0(n3046), .Y(n3049)
);
AOI31X1TS U4361 ( .A0(n3050), .A1(n3056), .A2(FPADDSUB_Raw_mant_NRM_SWR[1]),
.B0(n3049), .Y(n3053) );
NAND2X1TS U4362 ( .A(n4256), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n3052)
);
OAI21X1TS U4363 ( .A0(n3056), .A1(n3059), .B0(n3055), .Y(n3072) );
NAND2X1TS U4364 ( .A(n4895), .B(n4871), .Y(n3057) );
AOI22X1TS U4365 ( .A0(n3083), .A1(FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n3058),
.B1(n3057), .Y(n3060) );
AOI32X1TS U4366 ( .A0(n4904), .A1(n3060), .A2(n5068), .B0(n3059), .B1(n3060),
.Y(n3061) );
AOI211X1TS U4367 ( .A0(n3062), .A1(FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n3072),
.C0(n3061), .Y(n3066) );
NAND2X1TS U4368 ( .A(n4256), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n3065)
);
BUFX4TS U4369 ( .A(n3067), .Y(n3186) );
AOI222X4TS U4370 ( .A0(n2197), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[3]), .B1(n3186), .C0(n2273), .C1(n3164), .Y(
n3138) );
INVX2TS U4371 ( .A(n3069), .Y(n3076) );
AOI211X1TS U4372 ( .A0(n3074), .A1(n3073), .B0(n3082), .C0(n3072), .Y(n3075)
);
OAI211X1TS U4373 ( .A0(n4878), .A1(n3077), .B0(n3076), .C0(n3075), .Y(n3859)
);
NAND2BX1TS U4374 ( .AN(n3088), .B(n4386), .Y(n4387) );
OAI32X1TS U4375 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n4996), .B0(n2272), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3078) );
OAI31X1TS U4376 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n4869), .A2(n3080),
.B0(n3079), .Y(n3081) );
AOI211X1TS U4377 ( .A0(n3083), .A1(FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n3082),
.C0(n3081), .Y(n3087) );
AOI31X1TS U4378 ( .A0(n3087), .A1(n3086), .A2(n3085), .B0(n4256), .Y(n3860)
);
NOR2X1TS U4379 ( .A(n4387), .B(n3188), .Y(n3096) );
INVX2TS U4380 ( .A(n3188), .Y(n3092) );
AOI22X1TS U4381 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[21]), .A1(n4390), .B0(
FPADDSUB_DmP_mant_SHT1_SW[2]), .B1(n3150), .Y(n3091) );
AOI22X1TS U4382 ( .A0(n3116), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n2254),
.B1(n3135), .Y(n3095) );
AOI22X1TS U4383 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[2]), .A1(n3186), .B0(
FPADDSUB_DmP_mant_SHT1_SW[0]), .B1(n3150), .Y(n3093) );
AOI222X4TS U4384 ( .A0(n2197), .A1(FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .B1(n3186), .C0(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C1(n3164), .Y(n3113) );
INVX2TS U4385 ( .A(n3113), .Y(n3132) );
AOI22X1TS U4386 ( .A0(n3182), .A1(n2220), .B0(n2256), .B1(n3132), .Y(n3094)
);
AOI222X4TS U4387 ( .A0(n2197), .A1(FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(n4390), .B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .C0(FPADDSUB_Raw_mant_NRM_SWR[24]), .C1(
n3186), .Y(n3190) );
INVX4TS U4388 ( .A(n3182), .Y(n3191) );
BUFX3TS U4389 ( .A(n3096), .Y(n3172) );
AOI22X1TS U4390 ( .A0(n3116), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n3172),
.B1(n3187), .Y(n3097) );
AOI22X1TS U4391 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n4390), .B0(n3186),
.B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n4394) );
INVX2TS U4392 ( .A(n3138), .Y(n4391) );
AOI22X1TS U4393 ( .A0(n3116), .A1(FPADDSUB_Data_array_SWR[1]), .B0(n2254),
.B1(n4391), .Y(n3099) );
AOI22X1TS U4394 ( .A0(n3172), .A1(n2220), .B0(n2256), .B1(n3135), .Y(n3098)
);
AOI222X4TS U4395 ( .A0(n3150), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(n3186), .C0(
FPADDSUB_Raw_mant_NRM_SWR[18]), .C1(n3164), .Y(n3131) );
INVX2TS U4396 ( .A(n3131), .Y(n3110) );
AOI22X1TS U4397 ( .A0(n3116), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n2254),
.B1(n3110), .Y(n3103) );
AOI22X1TS U4398 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n4390), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n3150), .Y(n3100) );
AOI22X1TS U4399 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n4390), .B0(
FPADDSUB_DmP_mant_SHT1_SW[6]), .B1(n3150), .Y(n3101) );
AOI22X1TS U4400 ( .A0(n3172), .A1(n3134), .B0(n2256), .B1(n3127), .Y(n3102)
);
AOI222X4TS U4401 ( .A0(n2197), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n3186), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n3164), .Y(n3126) );
AOI22X1TS U4402 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n4390), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n3150), .Y(n3104) );
AOI22X1TS U4403 ( .A0(n3116), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n2254),
.B1(n3123), .Y(n3106) );
AOI222X4TS U4404 ( .A0(n3150), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n3186), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n3164), .Y(n3121) );
INVX2TS U4405 ( .A(n3121), .Y(n3122) );
AOI22X1TS U4406 ( .A0(n3182), .A1(n3127), .B0(n2256), .B1(n3122), .Y(n3105)
);
AOI22X1TS U4407 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[13]), .A1(n4390), .B0(
FPADDSUB_DmP_mant_SHT1_SW[10]), .B1(n3150), .Y(n3107) );
AOI22X1TS U4408 ( .A0(n3116), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n2254),
.B1(n3160), .Y(n3109) );
AOI222X4TS U4409 ( .A0(n3150), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n3164), .C0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n3186), .Y(n3163) );
INVX2TS U4410 ( .A(n3163), .Y(n3117) );
AOI22X1TS U4411 ( .A0(n3182), .A1(n3123), .B0(n2256), .B1(n3117), .Y(n3108)
);
AOI22X1TS U4412 ( .A0(n3116), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n2254),
.B1(n3134), .Y(n3112) );
AOI22X1TS U4413 ( .A0(n3182), .A1(n3135), .B0(n2256), .B1(n3110), .Y(n3111)
);
INVX2TS U4414 ( .A(n3126), .Y(n3128) );
AOI22X1TS U4415 ( .A0(n3116), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n2254),
.B1(n3128), .Y(n3115) );
AOI22X1TS U4416 ( .A0(n3172), .A1(n3127), .B0(n2256), .B1(n3123), .Y(n3114)
);
AOI22X1TS U4417 ( .A0(n4389), .A1(n2281), .B0(n2255), .B1(n3117), .Y(n3120)
);
AOI22X1TS U4418 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n4390), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n3150), .Y(n3118) );
AOI22X1TS U4419 ( .A0(n3172), .A1(n3160), .B0(n2257), .B1(n3158), .Y(n3119)
);
AOI22X1TS U4420 ( .A0(n3116), .A1(n2282), .B0(n2255), .B1(n3122), .Y(n3125)
);
AOI22X1TS U4421 ( .A0(n3172), .A1(n3123), .B0(n2257), .B1(n3160), .Y(n3124)
);
AOI22X1TS U4422 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n2255),
.B1(n3127), .Y(n3130) );
AOI22X1TS U4423 ( .A0(n3182), .A1(n3134), .B0(n2256), .B1(n3128), .Y(n3129)
);
AOI22X1TS U4424 ( .A0(n3116), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n2254),
.B1(n3132), .Y(n3137) );
AOI22X1TS U4425 ( .A0(n3172), .A1(n3135), .B0(n2257), .B1(n3134), .Y(n3136)
);
AOI222X4TS U4426 ( .A0(n2197), .A1(FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[4]), .B1(n3164), .C0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .C1(n3186), .Y(n3165) );
AOI222X4TS U4427 ( .A0(n2197), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n3164), .C0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .C1(n3186), .Y(n3192) );
INVX2TS U4428 ( .A(n3192), .Y(n3143) );
AOI22X1TS U4429 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n2255),
.B1(n3143), .Y(n3141) );
AOI22X1TS U4430 ( .A0(n2273), .A1(n3067), .B0(FPADDSUB_DmP_mant_SHT1_SW[20]),
.B1(n3150), .Y(n3139) );
INVX2TS U4431 ( .A(n3190), .Y(n3183) );
AOI22X1TS U4432 ( .A0(n3172), .A1(n3181), .B0(n2257), .B1(n3183), .Y(n3140)
);
AOI22X1TS U4433 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n2255),
.B1(n3181), .Y(n3145) );
AOI22X1TS U4434 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[20]), .A1(n3186), .B0(
FPADDSUB_DmP_mant_SHT1_SW[18]), .B1(n3150), .Y(n3142) );
AOI22X1TS U4435 ( .A0(n3182), .A1(n2275), .B0(n2257), .B1(n3143), .Y(n3144)
);
AOI222X4TS U4436 ( .A0(n3150), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n3164), .C0(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(n3186), .Y(n3155) );
AOI22X1TS U4437 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n4390), .B0(
FPADDSUB_DmP_mant_SHT1_SW[14]), .B1(n3150), .Y(n3146) );
AOI22X1TS U4438 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n2254),
.B1(n3177), .Y(n3148) );
AOI222X4TS U4439 ( .A0(n2197), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n4390), .C0(
FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(n3186), .Y(n3180) );
INVX2TS U4440 ( .A(n3180), .Y(n3149) );
AOI22X1TS U4441 ( .A0(n3182), .A1(n3158), .B0(n2256), .B1(n3149), .Y(n3147)
);
AOI22X1TS U4442 ( .A0(n4389), .A1(n2285), .B0(n2255), .B1(n3149), .Y(n3154)
);
AOI22X1TS U4443 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n4390), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n3150), .Y(n3151) );
AOI22X1TS U4444 ( .A0(n3172), .A1(n3177), .B0(n2257), .B1(n3175), .Y(n3153)
);
INVX2TS U4445 ( .A(n3155), .Y(n3159) );
AOI22X1TS U4446 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n2254),
.B1(n3159), .Y(n3157) );
AOI22X1TS U4447 ( .A0(n3172), .A1(n3158), .B0(n2256), .B1(n3177), .Y(n3156)
);
AOI22X1TS U4448 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n2254),
.B1(n3158), .Y(n3162) );
AOI22X1TS U4449 ( .A0(n3182), .A1(n3160), .B0(n2256), .B1(n3159), .Y(n3161)
);
AOI222X4TS U4450 ( .A0(n2197), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n3164), .C0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .C1(n3067), .Y(n3171) );
AOI22X1TS U4451 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n2255),
.B1(n2275), .Y(n3167) );
INVX2TS U4452 ( .A(n3165), .Y(n3168) );
AOI22X1TS U4453 ( .A0(n3182), .A1(n3175), .B0(n2257), .B1(n3168), .Y(n3166)
);
AOI22X1TS U4454 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n2255),
.B1(n3168), .Y(n3170) );
AOI22X1TS U4455 ( .A0(n3172), .A1(n2275), .B0(n2257), .B1(n3181), .Y(n3169)
);
INVX2TS U4456 ( .A(n3171), .Y(n3176) );
AOI22X1TS U4457 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n2255),
.B1(n3176), .Y(n3174) );
AOI22X1TS U4458 ( .A0(n3172), .A1(n3175), .B0(n2257), .B1(n2275), .Y(n3173)
);
AOI22X1TS U4459 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n2255),
.B1(n3175), .Y(n3179) );
AOI22X1TS U4460 ( .A0(n3182), .A1(n3177), .B0(n2257), .B1(n3176), .Y(n3178)
);
AOI22X1TS U4461 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n3182),
.B1(n3181), .Y(n3185) );
AOI22X1TS U4462 ( .A0(n2255), .A1(n3183), .B0(n2257), .B1(n3187), .Y(n3184)
);
AOI21X1TS U4463 ( .A0(n3188), .A1(n3187), .B0(n3186), .Y(n4388) );
OAI22X1TS U4464 ( .A0(n3192), .A1(n3191), .B0(n3190), .B1(n3189), .Y(n3193)
);
AOI21X1TS U4465 ( .A0(n4389), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n3193),
.Y(n3194) );
CMPR32X2TS U4466 ( .A(n3724), .B(n3197), .C(n3196), .CO(n2346), .S(
mult_x_69_n641) );
AOI222X1TS U4467 ( .A0(n3281), .A1(n3609), .B0(n3280), .B1(n3614), .C0(n2330), .C1(n3625), .Y(n3198) );
CMPR32X2TS U4468 ( .A(n3625), .B(n3200), .C(n3199), .CO(mult_x_69_n535), .S(
mult_x_69_n536) );
NAND2X1TS U4469 ( .A(n4240), .B(n4258), .Y(n4230) );
OAI21XLTS U4470 ( .A0(n4264), .A1(n5077), .B0(FPSENCOS_cont_var_out[1]), .Y(
n3201) );
CMPR32X2TS U4471 ( .A(n4949), .B(n4970), .C(n3768), .CO(mult_x_69_n585), .S(
mult_x_69_n586) );
AOI21X1TS U4472 ( .A0(n3204), .A1(n3203), .B0(n3202), .Y(n3205) );
XOR2X1TS U4473 ( .A(n3205), .B(n3843), .Y(n3206) );
AND3X2TS U4474 ( .A(n3209), .B(n3208), .C(n3207), .Y(n3210) );
INVX2TS U4475 ( .A(n3210), .Y(n3390) );
INVX4TS U4476 ( .A(n3390), .Y(n3387) );
AOI21X1TS U4477 ( .A0(n3387), .A1(n3643), .B0(n3211), .Y(n3212) );
XOR2X1TS U4478 ( .A(n3213), .B(FPMULT_Op_MX[17]), .Y(mult_x_69_n1075) );
XNOR2X2TS U4479 ( .A(n3411), .B(n2284), .Y(n3215) );
BUFX4TS U4480 ( .A(n3259), .Y(n3350) );
XNOR2X1TS U4481 ( .A(n2284), .B(FPMULT_Op_MX[19]), .Y(n3214) );
AND3X2TS U4482 ( .A(n3216), .B(n3215), .C(n3214), .Y(n3361) );
INVX2TS U4483 ( .A(n3361), .Y(n3323) );
INVX4TS U4484 ( .A(n3323), .Y(n3368) );
AOI222X1TS U4485 ( .A0(n3350), .A1(n3577), .B0(n3255), .B1(n3581), .C0(n3368), .C1(n3590), .Y(n3217) );
INVX4TS U4486 ( .A(n4884), .Y(n3346) );
XOR2X1TS U4487 ( .A(n3218), .B(n3346), .Y(mult_x_69_n1052) );
BUFX4TS U4488 ( .A(n3404), .Y(n3407) );
AOI222X1TS U4489 ( .A0(n3395), .A1(n3647), .B0(n3407), .B1(n3573), .C0(n3387), .C1(n5160), .Y(n3219) );
XOR2X1TS U4490 ( .A(n3220), .B(FPMULT_Op_MX[17]), .Y(mult_x_69_n1077) );
AOI222X1TS U4491 ( .A0(n3395), .A1(n3577), .B0(n3407), .B1(n3581), .C0(n3387), .C1(n3590), .Y(n3221) );
XOR2X1TS U4492 ( .A(n3222), .B(n2291), .Y(mult_x_69_n1079) );
AOI222X1TS U4493 ( .A0(n3350), .A1(n3604), .B0(n3255), .B1(n3609), .C0(n3361), .C1(n3619), .Y(n3223) );
XOR2X1TS U4494 ( .A(n3224), .B(n3346), .Y(mult_x_69_n1058) );
AOI222X1TS U4495 ( .A0(n3225), .A1(n3629), .B0(n3506), .B1(FPMULT_Op_MY[7]),
.C0(n3505), .C1(FPMULT_Op_MY[6]), .Y(n3229) );
XOR2X1TS U4496 ( .A(n3230), .B(n3509), .Y(mult_x_69_n1144) );
XNOR2X2TS U4497 ( .A(n3509), .B(FPMULT_Op_MX[12]), .Y(n3237) );
CLKXOR2X2TS U4498 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[13]), .Y(n3238) );
XNOR2X1TS U4499 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[13]), .Y(n3236) );
BUFX4TS U4500 ( .A(n3422), .Y(n3462) );
BUFX4TS U4501 ( .A(n3235), .Y(n3446) );
INVX4TS U4502 ( .A(n4887), .Y(n3442) );
XOR2X1TS U4503 ( .A(n3231), .B(n3442), .Y(n3309) );
BUFX3TS U4504 ( .A(n3232), .Y(n3441) );
NAND2X1TS U4505 ( .A(n3446), .B(n3724), .Y(n3233) );
XOR2X1TS U4506 ( .A(n3234), .B(n3442), .Y(n3312) );
AND3X2TS U4507 ( .A(n3238), .B(n3237), .C(n3236), .Y(n3239) );
INVX2TS U4508 ( .A(n3239), .Y(n3413) );
INVX4TS U4509 ( .A(n3413), .Y(n3461) );
AOI222X1TS U4510 ( .A0(n3235), .A1(n3731), .B0(n3462), .B1(n3730), .C0(n3461), .C1(FPMULT_Op_MY[0]), .Y(n3240) );
XOR2X1TS U4511 ( .A(n3241), .B(n2292), .Y(n3242) );
ADDHXLTS U4512 ( .A(n3243), .B(n3242), .CO(mult_x_69_n734), .S(n3253) );
INVX4TS U4513 ( .A(n4949), .Y(n3763) );
XNOR2X2TS U4514 ( .A(n3763), .B(FPMULT_Op_MX[6]), .Y(n3245) );
CLKXOR2X2TS U4515 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[7]), .Y(n3246) );
NOR2BX4TS U4516 ( .AN(n3245), .B(n3244), .Y(n3678) );
BUFX4TS U4517 ( .A(n3678), .Y(n3685) );
AOI222X1TS U4518 ( .A0(n3516), .A1(n3629), .B0(n3685), .B1(FPMULT_Op_MY[7]),
.C0(n3550), .C1(FPMULT_Op_MY[6]), .Y(n3247) );
XOR2X1TS U4519 ( .A(n3248), .B(FPMULT_Op_MX[8]), .Y(n3252) );
BUFX4TS U4520 ( .A(n3506), .Y(n3498) );
INVX2TS U4521 ( .A(n3505), .Y(n3465) );
INVX4TS U4522 ( .A(n3465), .Y(n3488) );
AOI222X1TS U4523 ( .A0(n3225), .A1(n3708), .B0(n3498), .B1(n3697), .C0(n3488), .C1(n3732), .Y(n3249) );
XOR2X1TS U4524 ( .A(n3250), .B(n3509), .Y(n3251) );
CMPR32X2TS U4525 ( .A(n3253), .B(n3252), .C(n3251), .CO(mult_x_69_n732), .S(
mult_x_69_n733) );
BUFX4TS U4526 ( .A(n3255), .Y(n3369) );
OAI21X1TS U4527 ( .A0(n3722), .A1(n3371), .B0(n2213), .Y(n3256) );
XOR2X1TS U4528 ( .A(n3256), .B(n3346), .Y(n3290) );
NAND2X1TS U4529 ( .A(n3350), .B(n3724), .Y(n3257) );
XOR2X1TS U4530 ( .A(n3258), .B(n3346), .Y(n3293) );
AOI222X1TS U4531 ( .A0(n3259), .A1(n3731), .B0(n3369), .B1(n3730), .C0(n3368), .C1(FPMULT_Op_MY[0]), .Y(n3260) );
XOR2X1TS U4532 ( .A(n3261), .B(n3346), .Y(n3262) );
ADDHXLTS U4533 ( .A(n3263), .B(n3262), .CO(mult_x_69_n683), .S(n3271) );
XOR2X1TS U4534 ( .A(n3265), .B(n3442), .Y(n3270) );
AOI222X1TS U4535 ( .A0(n3266), .A1(n3708), .B0(n3407), .B1(n3697), .C0(n3387), .C1(n3732), .Y(n3267) );
XOR2X1TS U4536 ( .A(n3268), .B(n3411), .Y(n3269) );
CMPR32X2TS U4537 ( .A(n3271), .B(n3270), .C(n3269), .CO(mult_x_69_n681), .S(
mult_x_69_n682) );
AOI222X1TS U4538 ( .A0(n3281), .A1(n3614), .B0(n3830), .B1(n3618), .C0(n2330), .C1(n3630), .Y(n3272) );
OA21XLTS U4539 ( .A0(n3621), .A1(n2317), .B0(n3272), .Y(n4950) );
AOI222X1TS U4540 ( .A0(n3281), .A1(n3585), .B0(n3280), .B1(n3589), .C0(n3831), .C1(n3600), .Y(n3273) );
OA21XLTS U4541 ( .A0(n3592), .A1(n3836), .B0(n3273), .Y(n4965) );
AOI222X1TS U4542 ( .A0(n3281), .A1(n3573), .B0(n3280), .B1(n3577), .C0(n3831), .C1(n2295), .Y(n3274) );
OA21XLTS U4543 ( .A0(n3579), .A1(n3836), .B0(n3274), .Y(n4973) );
AOI21X1TS U4544 ( .A0(n3831), .A1(n3643), .B0(n3275), .Y(n3276) );
OA21XLTS U4545 ( .A0(n3645), .A1(n3836), .B0(n3276), .Y(n4983) );
CMPR32X2TS U4546 ( .A(n4942), .B(n3600), .C(n3590), .CO(mult_x_69_n487), .S(
mult_x_69_n488) );
XOR2X1TS U4547 ( .A(n3277), .B(n3411), .Y(n3278) );
CMPR32X2TS U4548 ( .A(n3595), .B(n3279), .C(n3278), .CO(mult_x_69_n492), .S(
mult_x_69_n493) );
AOI222X1TS U4549 ( .A0(n3281), .A1(n3581), .B0(n3280), .B1(n3585), .C0(n3831), .C1(n3595), .Y(n3282) );
OA21XLTS U4550 ( .A0(n3587), .A1(n3836), .B0(n3282), .Y(n3283) );
CMPR32X2TS U4551 ( .A(n5009), .B(mult_x_69_n504), .C(n3283), .CO(
mult_x_69_n498), .S(mult_x_69_n499) );
CMPR32X2TS U4552 ( .A(n4943), .B(n3630), .C(n3619), .CO(mult_x_69_n527), .S(
mult_x_69_n528) );
CMPR32X2TS U4553 ( .A(n4971), .B(mult_x_69_n553), .C(n3284), .CO(n3199), .S(
mult_x_69_n545) );
ADDHXLTS U4554 ( .A(n3286), .B(n3285), .CO(n3297), .S(mult_x_69_n720) );
AOI222X1TS U4555 ( .A0(n3266), .A1(n3731), .B0(n3407), .B1(n3730), .C0(n3387), .C1(FPMULT_Op_MY[0]), .Y(n3287) );
XOR2X1TS U4556 ( .A(n3288), .B(n3411), .Y(n3296) );
AOI222X1TS U4557 ( .A0(n3266), .A1(n3697), .B0(n3407), .B1(n3757), .C0(n3387), .C1(n3755), .Y(n3291) );
XOR2X1TS U4558 ( .A(n3292), .B(n3411), .Y(n3299) );
ADDHXLTS U4559 ( .A(n2238), .B(n3293), .CO(n3289), .S(n3303) );
AOI222X1TS U4560 ( .A0(n3266), .A1(n3757), .B0(n3407), .B1(n3731), .C0(n3387), .C1(n3730), .Y(n3294) );
XOR2X1TS U4561 ( .A(n3295), .B(n3411), .Y(n3302) );
ADDHXLTS U4562 ( .A(n3297), .B(n3296), .CO(n3301), .S(mult_x_69_n712) );
CMPR32X2TS U4563 ( .A(n3300), .B(n3299), .C(n3298), .CO(mult_x_69_n691), .S(
mult_x_69_n692) );
CMPR32X2TS U4564 ( .A(n3303), .B(n3302), .C(n3301), .CO(n3298), .S(
mult_x_69_n702) );
ADDHXLTS U4565 ( .A(n3305), .B(n3304), .CO(n3316), .S(mult_x_69_n759) );
AOI222X1TS U4566 ( .A0(n3225), .A1(n3731), .B0(n3498), .B1(n3730), .C0(n3488), .C1(FPMULT_Op_MY[0]), .Y(n3306) );
XOR2X1TS U4567 ( .A(n3307), .B(n3509), .Y(n3315) );
ADDHXLTS U4568 ( .A(n3309), .B(n3308), .CO(n3243), .S(n3319) );
AOI222X1TS U4569 ( .A0(n3225), .A1(n3697), .B0(n3498), .B1(n3757), .C0(n3488), .C1(n3755), .Y(n3310) );
XOR2X1TS U4570 ( .A(n3311), .B(n3509), .Y(n3318) );
ADDHXLTS U4571 ( .A(n2292), .B(n3312), .CO(n3308), .S(n3322) );
AOI222X1TS U4572 ( .A0(n3225), .A1(n3757), .B0(n3498), .B1(n3731), .C0(n3488), .C1(n3721), .Y(n3313) );
XOR2X1TS U4573 ( .A(n3314), .B(n3509), .Y(n3321) );
ADDHXLTS U4574 ( .A(n3316), .B(n3315), .CO(n3320), .S(mult_x_69_n754) );
CMPR32X2TS U4575 ( .A(n3319), .B(n3318), .C(n3317), .CO(mult_x_69_n739), .S(
mult_x_69_n740) );
CMPR32X2TS U4576 ( .A(n3322), .B(n3321), .C(n3320), .CO(n3317), .S(
mult_x_69_n747) );
XOR2X1TS U4577 ( .A(n3324), .B(FPMULT_Op_MX[20]), .Y(mult_x_69_n1046) );
AOI21X1TS U4578 ( .A0(n3368), .A1(n3843), .B0(n3369), .Y(n3325) );
XOR2X1TS U4579 ( .A(n3326), .B(n3346), .Y(mult_x_69_n1047) );
AOI21X1TS U4580 ( .A0(n3368), .A1(n3643), .B0(n3327), .Y(n3328) );
XOR2X1TS U4581 ( .A(n3329), .B(n3346), .Y(mult_x_69_n1048) );
AOI222X1TS U4582 ( .A0(n3350), .A1(n3648), .B0(n3369), .B1(n3647), .C0(n3368), .C1(n5161), .Y(n3330) );
XOR2X1TS U4583 ( .A(n3331), .B(n3346), .Y(mult_x_69_n1049) );
AOI222X1TS U4584 ( .A0(n3350), .A1(n3647), .B0(n3255), .B1(n3573), .C0(n3368), .C1(n5160), .Y(n3332) );
XOR2X1TS U4585 ( .A(n3333), .B(n3346), .Y(mult_x_69_n1050) );
AOI222X1TS U4586 ( .A0(n3350), .A1(n3573), .B0(n3255), .B1(n3577), .C0(n3368), .C1(n2295), .Y(n3334) );
XOR2X1TS U4587 ( .A(n3335), .B(n3346), .Y(mult_x_69_n1051) );
AOI222X1TS U4588 ( .A0(n3350), .A1(n3581), .B0(n3255), .B1(n3585), .C0(n3368), .C1(n3595), .Y(n3336) );
XOR2X1TS U4589 ( .A(n3337), .B(n3346), .Y(mult_x_69_n1053) );
AOI222X1TS U4590 ( .A0(n3350), .A1(n3585), .B0(n3255), .B1(n3589), .C0(n3368), .C1(n3600), .Y(n3338) );
XOR2X1TS U4591 ( .A(n3339), .B(n3346), .Y(mult_x_69_n1054) );
AOI222X1TS U4592 ( .A0(n3350), .A1(n3589), .B0(n3255), .B1(n3594), .C0(n3368), .C1(n5159), .Y(n3340) );
XOR2X1TS U4593 ( .A(n3341), .B(n3346), .Y(mult_x_69_n1055) );
AOI222X1TS U4594 ( .A0(n3350), .A1(n3594), .B0(n3255), .B1(n3599), .C0(n3368), .C1(n3604), .Y(n3342) );
XOR2X1TS U4595 ( .A(n3343), .B(n3346), .Y(mult_x_69_n1056) );
AOI222X1TS U4596 ( .A0(n3350), .A1(n3599), .B0(n3255), .B1(n3604), .C0(n3368), .C1(FPMULT_Op_MY[12]), .Y(n3345) );
XOR2X1TS U4597 ( .A(n3347), .B(n3346), .Y(mult_x_69_n1057) );
AOI222X1TS U4598 ( .A0(n3350), .A1(n3609), .B0(n3369), .B1(n3614), .C0(n3361), .C1(n3625), .Y(n3348) );
XOR2X1TS U4599 ( .A(n3349), .B(FPMULT_Op_MX[20]), .Y(mult_x_69_n1059) );
AOI222X1TS U4600 ( .A0(n3350), .A1(n3614), .B0(n3369), .B1(n3618), .C0(n3361), .C1(n3630), .Y(n3351) );
XOR2X1TS U4601 ( .A(n3352), .B(FPMULT_Op_MX[20]), .Y(mult_x_69_n1060) );
AOI222X1TS U4602 ( .A0(n3259), .A1(n3625), .B0(n3369), .B1(n3624), .C0(n3361), .C1(n5158), .Y(n3353) );
XOR2X1TS U4603 ( .A(n3354), .B(FPMULT_Op_MX[20]), .Y(mult_x_69_n1061) );
AOI222X1TS U4604 ( .A0(n3259), .A1(n3624), .B0(n3369), .B1(n3629), .C0(n3361), .C1(n2241), .Y(n3355) );
XOR2X1TS U4605 ( .A(n3356), .B(FPMULT_Op_MX[20]), .Y(mult_x_69_n1062) );
AOI222X1TS U4606 ( .A0(n3259), .A1(n3629), .B0(n3369), .B1(n2241), .C0(n3361), .C1(FPMULT_Op_MY[6]), .Y(n3357) );
XOR2X1TS U4607 ( .A(n3358), .B(FPMULT_Op_MX[20]), .Y(mult_x_69_n1063) );
AOI222X1TS U4608 ( .A0(n3259), .A1(FPMULT_Op_MY[7]), .B0(n3369), .B1(n3770),
.C0(n3361), .C1(n3768), .Y(n3359) );
XOR2X1TS U4609 ( .A(n3360), .B(FPMULT_Op_MX[20]), .Y(mult_x_69_n1064) );
AOI222X1TS U4610 ( .A0(n3259), .A1(n3770), .B0(n3369), .B1(n3708), .C0(n3361), .C1(n3759), .Y(n3362) );
XOR2X1TS U4611 ( .A(n3363), .B(FPMULT_Op_MX[20]), .Y(mult_x_69_n1065) );
AOI222X1TS U4612 ( .A0(n3259), .A1(n3708), .B0(n3369), .B1(n3697), .C0(n3368), .C1(n3732), .Y(n3364) );
XOR2X1TS U4613 ( .A(n3365), .B(FPMULT_Op_MX[20]), .Y(mult_x_69_n1066) );
AOI222X1TS U4614 ( .A0(n3259), .A1(n3697), .B0(n3369), .B1(n3757), .C0(n3368), .C1(n3755), .Y(n3366) );
XOR2X1TS U4615 ( .A(n3367), .B(FPMULT_Op_MX[20]), .Y(mult_x_69_n1067) );
AOI222X1TS U4616 ( .A0(n3259), .A1(n3757), .B0(n3369), .B1(n3731), .C0(n3368), .C1(n3721), .Y(n3370) );
XOR2X1TS U4617 ( .A(n3372), .B(FPMULT_Op_MX[20]), .Y(mult_x_69_n1068) );
AOI21X1TS U4618 ( .A0(n3387), .A1(n3843), .B0(n3404), .Y(n3373) );
XOR2X1TS U4619 ( .A(n3374), .B(n2291), .Y(mult_x_69_n1074) );
AOI222X1TS U4620 ( .A0(n3395), .A1(n3648), .B0(n3404), .B1(n3647), .C0(n3387), .C1(n5161), .Y(n3375) );
XOR2X1TS U4621 ( .A(n3376), .B(FPMULT_Op_MX[17]), .Y(mult_x_69_n1076) );
AOI222X1TS U4622 ( .A0(n3395), .A1(n3573), .B0(n3407), .B1(n3577), .C0(n3387), .C1(n2295), .Y(n3377) );
XOR2X1TS U4623 ( .A(n3378), .B(n2291), .Y(mult_x_69_n1078) );
AOI222X1TS U4624 ( .A0(n3395), .A1(n3581), .B0(n3407), .B1(n3585), .C0(n3387), .C1(n3595), .Y(n3379) );
XOR2X1TS U4625 ( .A(n3380), .B(n2291), .Y(mult_x_69_n1080) );
AOI222X1TS U4626 ( .A0(n3395), .A1(n3585), .B0(n3407), .B1(n3589), .C0(n3387), .C1(n3600), .Y(n3381) );
XOR2X1TS U4627 ( .A(n3382), .B(n2291), .Y(mult_x_69_n1081) );
AOI222X1TS U4628 ( .A0(n3395), .A1(n3589), .B0(n3407), .B1(n3594), .C0(n3387), .C1(n5159), .Y(n3383) );
XOR2X1TS U4629 ( .A(n3384), .B(n2291), .Y(mult_x_69_n1082) );
AOI222X1TS U4630 ( .A0(n3395), .A1(n3594), .B0(n3407), .B1(n3599), .C0(n3387), .C1(FPMULT_Op_MY[13]), .Y(n3385) );
XOR2X1TS U4631 ( .A(n3386), .B(n2291), .Y(mult_x_69_n1083) );
AOI222X1TS U4632 ( .A0(n3395), .A1(n3599), .B0(n3407), .B1(n3604), .C0(n3387), .C1(n3609), .Y(n3388) );
XOR2X1TS U4633 ( .A(n3389), .B(n2291), .Y(mult_x_69_n1084) );
AOI222X1TS U4634 ( .A0(n3395), .A1(n3604), .B0(n3407), .B1(n3609), .C0(n3210), .C1(n3619), .Y(n3391) );
XOR2X1TS U4635 ( .A(n3392), .B(n2291), .Y(mult_x_69_n1085) );
AOI222X1TS U4636 ( .A0(n3395), .A1(n3609), .B0(n3404), .B1(n3614), .C0(n3210), .C1(n3625), .Y(n3393) );
XOR2X1TS U4637 ( .A(n3394), .B(n3411), .Y(mult_x_69_n1086) );
AOI222X1TS U4638 ( .A0(n3395), .A1(n3614), .B0(n3404), .B1(n3618), .C0(n3210), .C1(n3630), .Y(n3396) );
XOR2X1TS U4639 ( .A(n3397), .B(n3411), .Y(mult_x_69_n1087) );
AOI222X1TS U4640 ( .A0(n3266), .A1(n3618), .B0(n3404), .B1(n3624), .C0(n3210), .C1(n5158), .Y(n3398) );
XOR2X1TS U4641 ( .A(n3399), .B(n3411), .Y(mult_x_69_n1088) );
XOR2X1TS U4642 ( .A(n3401), .B(n3411), .Y(mult_x_69_n1089) );
AOI222X1TS U4643 ( .A0(n3266), .A1(n3629), .B0(n3407), .B1(FPMULT_Op_MY[7]),
.C0(n3210), .C1(FPMULT_Op_MY[6]), .Y(n3402) );
XOR2X1TS U4644 ( .A(n3403), .B(n3411), .Y(mult_x_69_n1090) );
AOI222X1TS U4645 ( .A0(n3266), .A1(FPMULT_Op_MY[7]), .B0(n3404), .B1(n3770),
.C0(n3210), .C1(n3768), .Y(n3405) );
XOR2X1TS U4646 ( .A(n3406), .B(n3411), .Y(mult_x_69_n1091) );
AOI222X1TS U4647 ( .A0(n3266), .A1(n3770), .B0(n3407), .B1(n3708), .C0(n3210), .C1(n3759), .Y(n3409) );
XOR2X1TS U4648 ( .A(n3412), .B(n3411), .Y(mult_x_69_n1092) );
XOR2X1TS U4649 ( .A(n3414), .B(n2292), .Y(mult_x_69_n1100) );
AOI21X1TS U4650 ( .A0(n3461), .A1(n3843), .B0(n3462), .Y(n3415) );
XOR2X1TS U4651 ( .A(n3416), .B(n3442), .Y(mult_x_69_n1101) );
AOI21X1TS U4652 ( .A0(n3461), .A1(n3643), .B0(n3417), .Y(n3418) );
XOR2X1TS U4653 ( .A(n3419), .B(n3442), .Y(mult_x_69_n1102) );
AOI222X1TS U4654 ( .A0(n3446), .A1(n3648), .B0(n3462), .B1(n3647), .C0(n3461), .C1(n5161), .Y(n3420) );
XOR2X1TS U4655 ( .A(n3421), .B(n3442), .Y(mult_x_69_n1103) );
AOI222X1TS U4656 ( .A0(n3446), .A1(n3643), .B0(n3422), .B1(n3573), .C0(n3461), .C1(n5160), .Y(n3423) );
XOR2X1TS U4657 ( .A(n3424), .B(n3442), .Y(mult_x_69_n1104) );
AOI222X1TS U4658 ( .A0(n3446), .A1(n3573), .B0(n3422), .B1(n3577), .C0(n3461), .C1(n2295), .Y(n3425) );
XOR2X1TS U4659 ( .A(n3426), .B(n3442), .Y(mult_x_69_n1105) );
AOI222X1TS U4660 ( .A0(n3446), .A1(n3577), .B0(n3422), .B1(n3581), .C0(n3461), .C1(n3590), .Y(n3427) );
XOR2X1TS U4661 ( .A(n3428), .B(n3442), .Y(mult_x_69_n1106) );
AOI222X1TS U4662 ( .A0(n3446), .A1(n3581), .B0(n3422), .B1(n3585), .C0(n3461), .C1(n3595), .Y(n3429) );
XOR2X1TS U4663 ( .A(n3430), .B(n3442), .Y(mult_x_69_n1107) );
AOI222X1TS U4664 ( .A0(n3446), .A1(n3585), .B0(n3422), .B1(n3589), .C0(n3461), .C1(n3600), .Y(n3431) );
XOR2X1TS U4665 ( .A(n3432), .B(n3442), .Y(mult_x_69_n1108) );
AOI222X1TS U4666 ( .A0(n3446), .A1(n3589), .B0(n3422), .B1(n3594), .C0(n3461), .C1(n5159), .Y(n3433) );
XOR2X1TS U4667 ( .A(n3434), .B(n3442), .Y(mult_x_69_n1109) );
AOI222X1TS U4668 ( .A0(n3446), .A1(n3594), .B0(n3422), .B1(n3599), .C0(n3461), .C1(FPMULT_Op_MY[13]), .Y(n3435) );
XOR2X1TS U4669 ( .A(n3436), .B(n3442), .Y(mult_x_69_n1110) );
AOI222X1TS U4670 ( .A0(n3446), .A1(n3599), .B0(n3422), .B1(n3604), .C0(n3461), .C1(FPMULT_Op_MY[12]), .Y(n3437) );
XOR2X1TS U4671 ( .A(n3438), .B(n3442), .Y(mult_x_69_n1111) );
AOI222X1TS U4672 ( .A0(n3446), .A1(n3604), .B0(n3422), .B1(n3609), .C0(n3239), .C1(n3619), .Y(n3440) );
XOR2X1TS U4673 ( .A(n3443), .B(n3442), .Y(mult_x_69_n1112) );
AOI222X1TS U4674 ( .A0(n3446), .A1(n3609), .B0(n3462), .B1(n3614), .C0(n3239), .C1(n3625), .Y(n3444) );
XOR2X1TS U4675 ( .A(n3445), .B(n2292), .Y(mult_x_69_n1113) );
AOI222X1TS U4676 ( .A0(n3446), .A1(n3614), .B0(n3462), .B1(n3618), .C0(n3239), .C1(n3630), .Y(n3447) );
XOR2X1TS U4677 ( .A(n3448), .B(n2292), .Y(mult_x_69_n1114) );
AOI222X1TS U4678 ( .A0(n3235), .A1(n3618), .B0(n3462), .B1(n3624), .C0(n3239), .C1(n5158), .Y(n3449) );
XOR2X1TS U4679 ( .A(n3450), .B(n2292), .Y(mult_x_69_n1115) );
AOI222X1TS U4680 ( .A0(n3235), .A1(n3624), .B0(n3462), .B1(n3629), .C0(n3239), .C1(n2241), .Y(n3451) );
XOR2X1TS U4681 ( .A(n3452), .B(n2292), .Y(mult_x_69_n1116) );
AOI222X1TS U4682 ( .A0(n3235), .A1(FPMULT_Op_MY[7]), .B0(n3462), .B1(n3770),
.C0(n3239), .C1(n3768), .Y(n3453) );
XOR2X1TS U4683 ( .A(n3454), .B(n2292), .Y(mult_x_69_n1118) );
AOI222X1TS U4684 ( .A0(n3235), .A1(n3770), .B0(n3462), .B1(n3708), .C0(n3239), .C1(n3759), .Y(n3455) );
XOR2X1TS U4685 ( .A(n3456), .B(n2292), .Y(mult_x_69_n1119) );
AOI222X1TS U4686 ( .A0(n3235), .A1(n3708), .B0(n3462), .B1(n3697), .C0(n3461), .C1(n3732), .Y(n3457) );
XOR2X1TS U4687 ( .A(n3458), .B(n2292), .Y(mult_x_69_n1120) );
AOI222X1TS U4688 ( .A0(n3235), .A1(n3697), .B0(n3462), .B1(n3757), .C0(n3461), .C1(n3755), .Y(n3459) );
XOR2X1TS U4689 ( .A(n3460), .B(n2292), .Y(mult_x_69_n1121) );
AOI222X1TS U4690 ( .A0(n3235), .A1(n3757), .B0(n3462), .B1(n3731), .C0(n3461), .C1(n3730), .Y(n3463) );
XOR2X1TS U4691 ( .A(n3464), .B(FPMULT_Op_MX[14]), .Y(mult_x_69_n1122) );
XOR2X1TS U4692 ( .A(n3466), .B(n3509), .Y(mult_x_69_n1127) );
AOI21X1TS U4693 ( .A0(n3488), .A1(n3843), .B0(n3506), .Y(n3467) );
XOR2X1TS U4694 ( .A(n3468), .B(n2237), .Y(mult_x_69_n1128) );
AOI21X1TS U4695 ( .A0(n3488), .A1(n3643), .B0(n3469), .Y(n3470) );
XOR2X1TS U4696 ( .A(n3471), .B(n2237), .Y(mult_x_69_n1129) );
AOI222X1TS U4697 ( .A0(n3495), .A1(n3648), .B0(n3506), .B1(n3647), .C0(n3488), .C1(n5161), .Y(n3472) );
XOR2X1TS U4698 ( .A(n3473), .B(n2237), .Y(mult_x_69_n1130) );
AOI222X1TS U4699 ( .A0(n3495), .A1(n3647), .B0(n3498), .B1(n3573), .C0(n3488), .C1(n5160), .Y(n3474) );
XOR2X1TS U4700 ( .A(n3475), .B(n2237), .Y(mult_x_69_n1131) );
AOI222X1TS U4701 ( .A0(n3495), .A1(n5161), .B0(n3498), .B1(n3577), .C0(n3488), .C1(n2295), .Y(n3476) );
XOR2X1TS U4702 ( .A(n3477), .B(n2237), .Y(mult_x_69_n1132) );
AOI222X1TS U4703 ( .A0(n3495), .A1(n5160), .B0(n3498), .B1(n3581), .C0(n3488), .C1(n3590), .Y(n3478) );
XOR2X1TS U4704 ( .A(n3479), .B(n2237), .Y(mult_x_69_n1133) );
AOI222X1TS U4705 ( .A0(n3495), .A1(FPMULT_Op_MY[18]), .B0(n3498), .B1(n3585),
.C0(n3488), .C1(n3595), .Y(n3480) );
XOR2X1TS U4706 ( .A(n3481), .B(n2237), .Y(mult_x_69_n1134) );
AOI222X1TS U4707 ( .A0(n3495), .A1(n3590), .B0(n3498), .B1(n3589), .C0(n3488), .C1(n3600), .Y(n3482) );
XOR2X1TS U4708 ( .A(n3483), .B(n2237), .Y(mult_x_69_n1135) );
AOI222X1TS U4709 ( .A0(n3495), .A1(n3595), .B0(n3498), .B1(n3594), .C0(n3488), .C1(n5159), .Y(n3484) );
XOR2X1TS U4710 ( .A(n3485), .B(n2237), .Y(mult_x_69_n1136) );
AOI222X1TS U4711 ( .A0(n3495), .A1(n3600), .B0(n3498), .B1(n3599), .C0(n3488), .C1(FPMULT_Op_MY[13]), .Y(n3486) );
XOR2X1TS U4712 ( .A(n3487), .B(n2237), .Y(mult_x_69_n1137) );
AOI222X1TS U4713 ( .A0(n3495), .A1(n5159), .B0(n3498), .B1(n3604), .C0(n3488), .C1(FPMULT_Op_MY[12]), .Y(n3489) );
XOR2X1TS U4714 ( .A(n3490), .B(n2237), .Y(mult_x_69_n1138) );
AOI222X1TS U4715 ( .A0(n3495), .A1(FPMULT_Op_MY[13]), .B0(n3498), .B1(n3609),
.C0(n3505), .C1(n3619), .Y(n3491) );
XOR2X1TS U4716 ( .A(n3492), .B(n2237), .Y(mult_x_69_n1139) );
AOI222X1TS U4717 ( .A0(n3495), .A1(FPMULT_Op_MY[12]), .B0(n3498), .B1(n3614),
.C0(n3505), .C1(n3625), .Y(n3493) );
XOR2X1TS U4718 ( .A(n3494), .B(n3509), .Y(mult_x_69_n1140) );
AOI222X1TS U4719 ( .A0(n3495), .A1(n3619), .B0(n3506), .B1(n3618), .C0(n3505), .C1(n3630), .Y(n3496) );
XOR2X1TS U4720 ( .A(n3497), .B(n3509), .Y(mult_x_69_n1141) );
AOI222X1TS U4721 ( .A0(n3225), .A1(n3618), .B0(n3498), .B1(n3624), .C0(n3505), .C1(n5158), .Y(n3499) );
XOR2X1TS U4722 ( .A(n3500), .B(n3509), .Y(mult_x_69_n1142) );
AOI222X1TS U4723 ( .A0(n3225), .A1(n3624), .B0(n3506), .B1(n3629), .C0(n3505), .C1(n2241), .Y(n3501) );
XOR2X1TS U4724 ( .A(n3502), .B(n3509), .Y(mult_x_69_n1143) );
AOI222X1TS U4725 ( .A0(n3225), .A1(FPMULT_Op_MY[7]), .B0(n3506), .B1(n3770),
.C0(n3505), .C1(n3768), .Y(n3503) );
XOR2X1TS U4726 ( .A(n3504), .B(n3509), .Y(mult_x_69_n1145) );
AOI222X1TS U4727 ( .A0(n3225), .A1(n3770), .B0(n3506), .B1(n3708), .C0(n3505), .C1(n3759), .Y(n3507) );
XOR2X1TS U4728 ( .A(n3510), .B(n3509), .Y(mult_x_69_n1146) );
INVX2TS U4729 ( .A(n3550), .Y(n3512) );
XOR2X1TS U4730 ( .A(n3511), .B(n2293), .Y(mult_x_69_n1154) );
INVX4TS U4731 ( .A(n3512), .Y(n3684) );
AOI21X1TS U4732 ( .A0(n3684), .A1(n3843), .B0(n3678), .Y(n3513) );
INVX4TS U4733 ( .A(n4948), .Y(n3682) );
XOR2X1TS U4734 ( .A(n3514), .B(n3682), .Y(mult_x_69_n1155) );
BUFX4TS U4735 ( .A(n3516), .Y(n3680) );
AOI21X1TS U4736 ( .A0(n3684), .A1(n3643), .B0(n3517), .Y(n3518) );
XOR2X1TS U4737 ( .A(n3519), .B(n3682), .Y(mult_x_69_n1156) );
AOI222X1TS U4738 ( .A0(n3680), .A1(n3648), .B0(n3678), .B1(n3647), .C0(n3684), .C1(n5161), .Y(n3520) );
XOR2X1TS U4739 ( .A(n3521), .B(n3682), .Y(mult_x_69_n1157) );
AOI222X1TS U4740 ( .A0(n3680), .A1(n3647), .B0(n3685), .B1(n3573), .C0(n3684), .C1(n5160), .Y(n3522) );
XOR2X1TS U4741 ( .A(n3523), .B(n3682), .Y(mult_x_69_n1158) );
XOR2X1TS U4742 ( .A(n3525), .B(n3682), .Y(mult_x_69_n1159) );
AOI222X1TS U4743 ( .A0(n3680), .A1(n3577), .B0(n3685), .B1(n3581), .C0(n3684), .C1(n3590), .Y(n3526) );
XOR2X1TS U4744 ( .A(n3527), .B(n3682), .Y(mult_x_69_n1160) );
AOI222X1TS U4745 ( .A0(n3680), .A1(n3581), .B0(n3685), .B1(n3585), .C0(n3684), .C1(n3595), .Y(n3528) );
XOR2X1TS U4746 ( .A(n3529), .B(n3682), .Y(mult_x_69_n1161) );
AOI222X1TS U4747 ( .A0(n3680), .A1(n3585), .B0(n3685), .B1(n3589), .C0(n3684), .C1(n3600), .Y(n3530) );
XOR2X1TS U4748 ( .A(n3531), .B(n3682), .Y(mult_x_69_n1162) );
AOI222X1TS U4749 ( .A0(n3680), .A1(n3589), .B0(n3685), .B1(n3594), .C0(n3684), .C1(n5159), .Y(n3532) );
XOR2X1TS U4750 ( .A(n3533), .B(n3682), .Y(mult_x_69_n1163) );
AOI222X1TS U4751 ( .A0(n3680), .A1(n3594), .B0(n3685), .B1(n3599), .C0(n3684), .C1(FPMULT_Op_MY[13]), .Y(n3534) );
XOR2X1TS U4752 ( .A(n3535), .B(n3682), .Y(mult_x_69_n1164) );
AOI222X1TS U4753 ( .A0(n3680), .A1(n3599), .B0(n3685), .B1(n3604), .C0(n3684), .C1(FPMULT_Op_MY[12]), .Y(n3536) );
XOR2X1TS U4754 ( .A(n3537), .B(n3682), .Y(mult_x_69_n1165) );
AOI222X1TS U4755 ( .A0(n3680), .A1(n3604), .B0(n3685), .B1(n3609), .C0(n3550), .C1(n3619), .Y(n3538) );
XOR2X1TS U4756 ( .A(n3539), .B(n3682), .Y(mult_x_69_n1166) );
AOI222X1TS U4757 ( .A0(n3680), .A1(n3609), .B0(n3685), .B1(n3614), .C0(n3550), .C1(n3625), .Y(n3540) );
XOR2X1TS U4758 ( .A(n3541), .B(n2293), .Y(mult_x_69_n1167) );
AOI222X1TS U4759 ( .A0(n3680), .A1(n3614), .B0(n3678), .B1(n3618), .C0(n3550), .C1(n3630), .Y(n3542) );
XOR2X1TS U4760 ( .A(n3543), .B(n2293), .Y(mult_x_69_n1168) );
AOI222X1TS U4761 ( .A0(n3516), .A1(n3618), .B0(n3678), .B1(n3624), .C0(n3550), .C1(n5158), .Y(n3544) );
XOR2X1TS U4762 ( .A(n3545), .B(n2293), .Y(mult_x_69_n1169) );
AOI222X1TS U4763 ( .A0(n3516), .A1(n3624), .B0(n3678), .B1(n3629), .C0(n3550), .C1(n2241), .Y(n3546) );
XOR2X1TS U4764 ( .A(n3547), .B(n2293), .Y(mult_x_69_n1170) );
AOI222X1TS U4765 ( .A0(n3516), .A1(FPMULT_Op_MY[7]), .B0(n3678), .B1(n3770),
.C0(n3550), .C1(n3768), .Y(n3548) );
XOR2X1TS U4766 ( .A(n3549), .B(n2293), .Y(mult_x_69_n1172) );
AOI222X1TS U4767 ( .A0(n3516), .A1(n3770), .B0(n3685), .B1(n3708), .C0(n3550), .C1(n3759), .Y(n3551) );
XOR2X1TS U4768 ( .A(n3552), .B(n2293), .Y(mult_x_69_n1173) );
AOI222X1TS U4769 ( .A0(n3516), .A1(n3708), .B0(n3678), .B1(n3697), .C0(n3684), .C1(n3732), .Y(n3553) );
XOR2X1TS U4770 ( .A(n3554), .B(n2293), .Y(mult_x_69_n1174) );
AOI222X1TS U4771 ( .A0(n3516), .A1(n3697), .B0(n3685), .B1(n3757), .C0(n3684), .C1(n3755), .Y(n3555) );
XOR2X1TS U4772 ( .A(n3556), .B(n2293), .Y(mult_x_69_n1175) );
AOI222X1TS U4773 ( .A0(n3516), .A1(n3757), .B0(n3685), .B1(n3731), .C0(n3684), .C1(n3730), .Y(n3557) );
XOR2X1TS U4774 ( .A(n3558), .B(n3682), .Y(mult_x_69_n1176) );
XNOR2X2TS U4775 ( .A(n3728), .B(n2283), .Y(n3565) );
CLKXOR2X2TS U4776 ( .A(n3763), .B(FPMULT_Op_MX[4]), .Y(n3566) );
NAND2BX1TS U4777 ( .AN(n3565), .B(n3566), .Y(n3564) );
BUFX3TS U4778 ( .A(n3564), .Y(n3761) );
XNOR2X1TS U4779 ( .A(n2283), .B(FPMULT_Op_MX[4]), .Y(n3561) );
AND3X2TS U4780 ( .A(n3566), .B(n3565), .C(n3561), .Y(n3559) );
INVX2TS U4781 ( .A(n3559), .Y(n3608) );
XOR2X1TS U4782 ( .A(n3560), .B(n3763), .Y(mult_x_69_n1181) );
INVX4TS U4783 ( .A(n3608), .Y(n3756) );
BUFX4TS U4784 ( .A(n3572), .Y(n3758) );
AOI21X1TS U4785 ( .A0(n3756), .A1(n3843), .B0(n3758), .Y(n3562) );
XOR2X1TS U4786 ( .A(n3563), .B(n2287), .Y(mult_x_69_n1182) );
BUFX3TS U4787 ( .A(n3564), .Y(n3704) );
AOI21X1TS U4788 ( .A0(n3756), .A1(n3643), .B0(n3567), .Y(n3568) );
XOR2X1TS U4789 ( .A(n3569), .B(n2287), .Y(mult_x_69_n1183) );
AOI222X1TS U4790 ( .A0(n3702), .A1(n3648), .B0(n3758), .B1(n3647), .C0(n3756), .C1(n5161), .Y(n3570) );
XOR2X1TS U4791 ( .A(n3571), .B(n2287), .Y(mult_x_69_n1184) );
AOI222X1TS U4792 ( .A0(n3702), .A1(n3643), .B0(n3572), .B1(n3573), .C0(n3756), .C1(n5160), .Y(n3574) );
XOR2X1TS U4793 ( .A(n3576), .B(n2287), .Y(mult_x_69_n1185) );
AOI222X1TS U4794 ( .A0(n3702), .A1(n5161), .B0(n3572), .B1(n3577), .C0(n3756), .C1(n2295), .Y(n3578) );
XOR2X1TS U4795 ( .A(n3580), .B(n2287), .Y(mult_x_69_n1186) );
AOI222X1TS U4796 ( .A0(n3702), .A1(n5160), .B0(n3572), .B1(n3581), .C0(n3756), .C1(n3590), .Y(n3582) );
XOR2X1TS U4797 ( .A(n3584), .B(FPMULT_Op_MX[5]), .Y(mult_x_69_n1187) );
AOI222X1TS U4798 ( .A0(n3702), .A1(n2295), .B0(n3572), .B1(n3585), .C0(n3756), .C1(n3595), .Y(n3586) );
XOR2X1TS U4799 ( .A(n3588), .B(n2287), .Y(mult_x_69_n1188) );
AOI222X1TS U4800 ( .A0(n3702), .A1(n3590), .B0(n3572), .B1(n3589), .C0(n3756), .C1(n3600), .Y(n3591) );
XOR2X1TS U4801 ( .A(n3593), .B(FPMULT_Op_MX[5]), .Y(mult_x_69_n1189) );
AOI222X1TS U4802 ( .A0(n3702), .A1(n3595), .B0(n3572), .B1(n3594), .C0(n3756), .C1(n5159), .Y(n3596) );
XOR2X1TS U4803 ( .A(n3598), .B(n2287), .Y(mult_x_69_n1190) );
AOI222X1TS U4804 ( .A0(n3702), .A1(n3600), .B0(n3572), .B1(n3599), .C0(n3756), .C1(FPMULT_Op_MY[13]), .Y(n3601) );
XOR2X1TS U4805 ( .A(n3603), .B(FPMULT_Op_MX[5]), .Y(mult_x_69_n1191) );
AOI222X1TS U4806 ( .A0(n3702), .A1(n5159), .B0(n3572), .B1(n3604), .C0(n3756), .C1(FPMULT_Op_MY[12]), .Y(n3605) );
XOR2X1TS U4807 ( .A(n3607), .B(n2287), .Y(mult_x_69_n1192) );
AOI222X1TS U4808 ( .A0(n3702), .A1(FPMULT_Op_MY[13]), .B0(n3572), .B1(n3609),
.C0(n3559), .C1(n3619), .Y(n3611) );
XOR2X1TS U4809 ( .A(n3613), .B(n2287), .Y(mult_x_69_n1193) );
AOI222X1TS U4810 ( .A0(n3702), .A1(FPMULT_Op_MY[12]), .B0(n3758), .B1(n3614),
.C0(n3559), .C1(n3625), .Y(n3615) );
XOR2X1TS U4811 ( .A(n3617), .B(n3763), .Y(mult_x_69_n1194) );
AOI222X1TS U4812 ( .A0(n3702), .A1(n3619), .B0(n3758), .B1(n3618), .C0(n3559), .C1(n3630), .Y(n3620) );
XOR2X1TS U4813 ( .A(n3622), .B(n3763), .Y(mult_x_69_n1195) );
AOI222X1TS U4814 ( .A0(n3623), .A1(n3625), .B0(n3758), .B1(n3624), .C0(n3559), .C1(n5158), .Y(n3626) );
XOR2X1TS U4815 ( .A(n3628), .B(n3763), .Y(mult_x_69_n1196) );
AOI222X1TS U4816 ( .A0(n3623), .A1(n3630), .B0(n3758), .B1(n3629), .C0(n3559), .C1(n2241), .Y(n3631) );
XOR2X1TS U4817 ( .A(n3633), .B(n3763), .Y(mult_x_69_n1197) );
AOI222X1TS U4818 ( .A0(n3623), .A1(n5158), .B0(n3758), .B1(FPMULT_Op_MY[7]),
.C0(n3559), .C1(FPMULT_Op_MY[6]), .Y(n3634) );
XOR2X1TS U4819 ( .A(n3635), .B(n3763), .Y(mult_x_69_n1198) );
AOI222X1TS U4820 ( .A0(n3623), .A1(n2241), .B0(n3758), .B1(n3770), .C0(n3559), .C1(n3768), .Y(n3636) );
XOR2X1TS U4821 ( .A(n3637), .B(n3763), .Y(mult_x_69_n1199) );
AOI222X1TS U4822 ( .A0(n3623), .A1(FPMULT_Op_MY[6]), .B0(n3758), .B1(n3708),
.C0(n3559), .C1(n3759), .Y(n3638) );
XOR2X1TS U4823 ( .A(n3639), .B(n3763), .Y(mult_x_69_n1200) );
AOI21X1TS U4824 ( .A0(n3740), .A1(n3843), .B0(n3771), .Y(n3640) );
XOR2X1TS U4825 ( .A(n3641), .B(FPMULT_Op_MX[2]), .Y(mult_x_69_n1209) );
AOI21X1TS U4826 ( .A0(n3740), .A1(n3643), .B0(n3642), .Y(n3644) );
XOR2X1TS U4827 ( .A(n3646), .B(FPMULT_Op_MX[2]), .Y(mult_x_69_n1210) );
AOI222X1TS U4828 ( .A0(n3725), .A1(n3648), .B0(n3771), .B1(n3647), .C0(n3740), .C1(n5161), .Y(n3649) );
XOR2X1TS U4829 ( .A(n3651), .B(n3776), .Y(mult_x_69_n1211) );
NOR3BX1TS U4830 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[0]), .C(
FPMULT_FSM_selector_B[1]), .Y(n3652) );
XOR2X1TS U4831 ( .A(n2358), .B(n3652), .Y(DP_OP_230J216_125_7006_n15) );
OR2X2TS U4832 ( .A(FPMULT_FSM_selector_B[1]), .B(n5003), .Y(n3659) );
OAI2BB1X1TS U4833 ( .A0N(FPMULT_Op_MY[29]), .A1N(n5007), .B0(n3659), .Y(
n3653) );
XOR2X1TS U4834 ( .A(n2358), .B(n3653), .Y(DP_OP_230J216_125_7006_n16) );
OAI2BB1X1TS U4835 ( .A0N(FPMULT_Op_MY[28]), .A1N(n5007), .B0(n3659), .Y(
n3654) );
XOR2X1TS U4836 ( .A(n2358), .B(n3654), .Y(DP_OP_230J216_125_7006_n17) );
OAI2BB1X1TS U4837 ( .A0N(FPMULT_Op_MY[27]), .A1N(n5007), .B0(n3659), .Y(
n3655) );
XOR2X1TS U4838 ( .A(n2358), .B(n3655), .Y(DP_OP_230J216_125_7006_n18) );
OAI2BB1X1TS U4839 ( .A0N(FPMULT_Op_MY[26]), .A1N(n5007), .B0(n3659), .Y(
n3656) );
XOR2X1TS U4840 ( .A(n2358), .B(n3656), .Y(DP_OP_230J216_125_7006_n19) );
OAI2BB1X1TS U4841 ( .A0N(FPMULT_Op_MY[25]), .A1N(n5007), .B0(n3659), .Y(
n3657) );
XOR2X1TS U4842 ( .A(n2358), .B(n3657), .Y(DP_OP_230J216_125_7006_n20) );
OAI2BB1X1TS U4843 ( .A0N(FPMULT_Op_MY[24]), .A1N(n5007), .B0(n3659), .Y(
n3658) );
XOR2X1TS U4844 ( .A(n2358), .B(n3658), .Y(DP_OP_230J216_125_7006_n21) );
XOR2X1TS U4845 ( .A(n2358), .B(n3661), .Y(DP_OP_230J216_125_7006_n22) );
NOR2BX1TS U4846 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3662) );
XOR2X1TS U4847 ( .A(n2198), .B(n3662), .Y(DP_OP_26J216_122_5882_n14) );
NOR2BX1TS U4848 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3663) );
XOR2X1TS U4849 ( .A(n2198), .B(n3663), .Y(DP_OP_26J216_122_5882_n15) );
NOR2BX1TS U4850 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3664) );
XOR2X1TS U4851 ( .A(n2198), .B(n3664), .Y(DP_OP_26J216_122_5882_n16) );
NOR2BX1TS U4852 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3665) );
XOR2X1TS U4853 ( .A(n2198), .B(n3665), .Y(DP_OP_26J216_122_5882_n17) );
XOR2X1TS U4854 ( .A(n2198), .B(n3666), .Y(DP_OP_26J216_122_5882_n18) );
BUFX3TS U4855 ( .A(n3668), .Y(n4492) );
INVX4TS U4856 ( .A(n3674), .Y(n3675) );
MX2X1TS U4857 ( .A(Data_1[22]), .B(FPMULT_Op_MX[22]), .S0(n3675), .Y(n1681)
);
MX2X1TS U4858 ( .A(Data_1[21]), .B(n2263), .S0(n3675), .Y(n1680) );
MX2X1TS U4859 ( .A(Data_1[20]), .B(FPMULT_Op_MX[20]), .S0(n3675), .Y(n1679)
);
MX2X1TS U4860 ( .A(Data_1[19]), .B(FPMULT_Op_MX[19]), .S0(n3675), .Y(n1678)
);
MX2X1TS U4861 ( .A(Data_1[18]), .B(n2284), .S0(n3675), .Y(n1677) );
MX2X1TS U4862 ( .A(Data_1[17]), .B(n2291), .S0(n3675), .Y(n1676) );
MX2X1TS U4863 ( .A(Data_1[16]), .B(FPMULT_Op_MX[16]), .S0(n3675), .Y(n1675)
);
MX2X1TS U4864 ( .A(Data_1[15]), .B(FPMULT_Op_MX[15]), .S0(n3675), .Y(n1674)
);
MX2X1TS U4865 ( .A(Data_1[14]), .B(n2292), .S0(n3675), .Y(n1673) );
MX2X1TS U4866 ( .A(Data_1[13]), .B(FPMULT_Op_MX[13]), .S0(n3675), .Y(n1672)
);
MX2X1TS U4867 ( .A(Data_1[12]), .B(FPMULT_Op_MX[12]), .S0(n3675), .Y(n1671)
);
MX2X1TS U4868 ( .A(Data_1[11]), .B(n2237), .S0(n3675), .Y(n1670) );
MX2X1TS U4869 ( .A(Data_1[10]), .B(FPMULT_Op_MX[10]), .S0(n3675), .Y(n1669)
);
INVX4TS U4870 ( .A(n3674), .Y(n3676) );
MX2X1TS U4871 ( .A(Data_1[9]), .B(FPMULT_Op_MX[9]), .S0(n3676), .Y(n1668) );
MX2X1TS U4872 ( .A(Data_1[8]), .B(n2293), .S0(n3676), .Y(n1667) );
MX2X1TS U4873 ( .A(Data_1[7]), .B(FPMULT_Op_MX[7]), .S0(n3676), .Y(n1666) );
MX2X1TS U4874 ( .A(Data_1[6]), .B(FPMULT_Op_MX[6]), .S0(n3676), .Y(n1665) );
MX2X1TS U4875 ( .A(Data_1[5]), .B(n2287), .S0(n3676), .Y(n1664) );
MX2X1TS U4876 ( .A(Data_1[4]), .B(FPMULT_Op_MX[4]), .S0(n3676), .Y(n1663) );
MX2X1TS U4877 ( .A(Data_1[3]), .B(n2283), .S0(n3676), .Y(n1662) );
MX2X1TS U4878 ( .A(Data_1[2]), .B(FPMULT_Op_MX[2]), .S0(n3676), .Y(n1661) );
MX2X1TS U4879 ( .A(Data_1[1]), .B(FPMULT_Op_MX[1]), .S0(n3676), .Y(n1660) );
MX2X1TS U4880 ( .A(Data_1[0]), .B(FPMULT_Op_MX[0]), .S0(n3676), .Y(n1659) );
MX2X1TS U4881 ( .A(Data_2[22]), .B(FPMULT_Op_MY[22]), .S0(n3676), .Y(n1649)
);
MX2X1TS U4882 ( .A(Data_2[21]), .B(FPMULT_Op_MY[21]), .S0(n3676), .Y(n1648)
);
MX2X1TS U4883 ( .A(Data_2[20]), .B(FPMULT_Op_MY[20]), .S0(n3676), .Y(n1647)
);
INVX4TS U4884 ( .A(n3674), .Y(n3677) );
MX2X1TS U4885 ( .A(Data_2[19]), .B(FPMULT_Op_MY[19]), .S0(n3677), .Y(n1646)
);
MX2X1TS U4886 ( .A(Data_2[18]), .B(n2295), .S0(n3677), .Y(n1645) );
MX2X1TS U4887 ( .A(Data_2[17]), .B(FPMULT_Op_MY[17]), .S0(n3677), .Y(n1644)
);
MX2X1TS U4888 ( .A(Data_2[16]), .B(FPMULT_Op_MY[16]), .S0(n3677), .Y(n1643)
);
MX2X1TS U4889 ( .A(Data_2[15]), .B(FPMULT_Op_MY[15]), .S0(n3677), .Y(n1642)
);
MX2X1TS U4890 ( .A(Data_2[14]), .B(FPMULT_Op_MY[14]), .S0(n3677), .Y(n1641)
);
MX2X1TS U4891 ( .A(Data_2[13]), .B(FPMULT_Op_MY[13]), .S0(n3677), .Y(n1640)
);
MX2X1TS U4892 ( .A(Data_2[12]), .B(FPMULT_Op_MY[12]), .S0(n3677), .Y(n1639)
);
MX2X1TS U4893 ( .A(Data_2[11]), .B(FPMULT_Op_MY[11]), .S0(n3677), .Y(n1638)
);
MX2X1TS U4894 ( .A(Data_2[10]), .B(FPMULT_Op_MY[10]), .S0(n3677), .Y(n1637)
);
MX2X1TS U4895 ( .A(Data_2[9]), .B(FPMULT_Op_MY[9]), .S0(n3677), .Y(n1636) );
MX2X1TS U4896 ( .A(Data_2[8]), .B(FPMULT_Op_MY[8]), .S0(n3677), .Y(n1635) );
MX2X1TS U4897 ( .A(Data_2[7]), .B(n2241), .S0(n3677), .Y(n1634) );
INVX4TS U4898 ( .A(n3674), .Y(n3856) );
MX2X1TS U4899 ( .A(Data_2[6]), .B(FPMULT_Op_MY[6]), .S0(n3856), .Y(n1633) );
MX2X1TS U4900 ( .A(Data_2[5]), .B(FPMULT_Op_MY[5]), .S0(n3856), .Y(n1632) );
MX2X1TS U4901 ( .A(Data_2[4]), .B(FPMULT_Op_MY[4]), .S0(n3856), .Y(n1631) );
MX2X1TS U4902 ( .A(Data_2[3]), .B(FPMULT_Op_MY[3]), .S0(n3856), .Y(n1630) );
MX2X1TS U4903 ( .A(Data_2[2]), .B(FPMULT_Op_MY[2]), .S0(n3856), .Y(n1629) );
MX2X1TS U4904 ( .A(Data_2[1]), .B(FPMULT_Op_MY[1]), .S0(n3856), .Y(n1628) );
MX2X1TS U4905 ( .A(Data_2[0]), .B(FPMULT_Op_MY[0]), .S0(n3856), .Y(n1627) );
XOR2X1TS U4906 ( .A(n3679), .B(n3682), .Y(n3754) );
NAND2X1TS U4907 ( .A(n3680), .B(n3724), .Y(n3681) );
XOR2X1TS U4908 ( .A(n3683), .B(n3682), .Y(n3712) );
AOI222X1TS U4909 ( .A0(n3516), .A1(n3731), .B0(n3685), .B1(n3730), .C0(n3684), .C1(FPMULT_Op_MY[0]), .Y(n3687) );
OAI21X1TS U4910 ( .A0(n3718), .A1(n3688), .B0(n3687), .Y(n3689) );
XOR2X1TS U4911 ( .A(n3689), .B(n2293), .Y(n3690) );
NOR2X1TS U4912 ( .A(mult_x_69_n677), .B(mult_x_69_n686), .Y(n3914) );
INVX2TS U4913 ( .A(n3914), .Y(n3910) );
NOR2X2TS U4914 ( .A(mult_x_69_n655), .B(mult_x_69_n665), .Y(n3939) );
NOR2X2TS U4915 ( .A(mult_x_69_n697), .B(mult_x_69_n706), .Y(n3895) );
NOR2X1TS U4916 ( .A(mult_x_69_n707), .B(mult_x_69_n714), .Y(n3889) );
NOR2X1TS U4917 ( .A(n3895), .B(n3889), .Y(n3902) );
NAND2X1TS U4918 ( .A(n3902), .B(n3905), .Y(n3802) );
ADDHXLTS U4919 ( .A(n3691), .B(n3690), .CO(mult_x_69_n767), .S(n3782) );
AOI222X1TS U4920 ( .A0(n3772), .A1(n5158), .B0(n3771), .B1(FPMULT_Op_MY[7]),
.C0(n3769), .C1(FPMULT_Op_MY[6]), .Y(n3692) );
XOR2X1TS U4921 ( .A(n3694), .B(n3728), .Y(n3781) );
AOI222X1TS U4922 ( .A0(n3623), .A1(n3768), .B0(n3758), .B1(n3697), .C0(n3756), .C1(n3732), .Y(n3695) );
XOR2X1TS U4923 ( .A(n3696), .B(n3763), .Y(n3780) );
NAND2X1TS U4924 ( .A(n3953), .B(n3998), .Y(n3792) );
AOI222X1TS U4925 ( .A0(n3772), .A1(n3768), .B0(n3771), .B1(n3697), .C0(n3740), .C1(n3732), .Y(n3698) );
OAI21X1TS U4926 ( .A0(n3699), .A1(n3774), .B0(n3698), .Y(n3700) );
XOR2X1TS U4927 ( .A(n3700), .B(n3776), .Y(n3748) );
XOR2X1TS U4928 ( .A(n3701), .B(n2287), .Y(n3744) );
NAND2X1TS U4929 ( .A(n3702), .B(n3724), .Y(n3703) );
XOR2X1TS U4930 ( .A(n3705), .B(n2287), .Y(n3736) );
AOI222X1TS U4931 ( .A0(n3623), .A1(n3755), .B0(n3758), .B1(n3730), .C0(n3756), .C1(FPMULT_Op_MY[0]), .Y(n3706) );
XOR2X1TS U4932 ( .A(n3707), .B(n3763), .Y(n3715) );
OAI21X1TS U4933 ( .A0(n3710), .A1(n3774), .B0(n3709), .Y(n3711) );
XOR2X1TS U4934 ( .A(n3711), .B(n3776), .Y(n3750) );
ADDHXLTS U4935 ( .A(n2293), .B(n3712), .CO(n3753), .S(n3767) );
AOI222X1TS U4936 ( .A0(n3623), .A1(n3732), .B0(n3758), .B1(n3731), .C0(n3756), .C1(n3730), .Y(n3713) );
XOR2X1TS U4937 ( .A(n3714), .B(n3763), .Y(n3766) );
NOR2X2TS U4938 ( .A(n3750), .B(n3749), .Y(n3979) );
XOR2X1TS U4939 ( .A(n3723), .B(n3776), .Y(n3946) );
NAND2X1TS U4940 ( .A(n3725), .B(n3724), .Y(n3726) );
OAI21X1TS U4941 ( .A0(n4957), .A1(n2496), .B0(n3726), .Y(n3945) );
INVX2TS U4942 ( .A(n3945), .Y(n3729) );
CLKAND2X2TS U4943 ( .A(n3729), .B(n3728), .Y(n3947) );
NAND2X1TS U4944 ( .A(n3946), .B(n3947), .Y(n3919) );
NOR2X1TS U4945 ( .A(n2306), .B(n3919), .Y(n3923) );
AOI222X1TS U4946 ( .A0(n3772), .A1(n3732), .B0(n3771), .B1(n3731), .C0(n3740), .C1(n3730), .Y(n3733) );
XOR2X1TS U4947 ( .A(n3735), .B(n3776), .Y(n3738) );
ADDHX1TS U4948 ( .A(n3763), .B(n3736), .CO(n3743), .S(n3737) );
NAND2X1TS U4949 ( .A(n3738), .B(n3737), .Y(n3921) );
INVX2TS U4950 ( .A(n3921), .Y(n3739) );
AOI21X1TS U4951 ( .A0(n3923), .A1(n3922), .B0(n3739), .Y(n3930) );
AOI222X1TS U4952 ( .A0(n3772), .A1(n3759), .B0(n3771), .B1(n3757), .C0(n3740), .C1(n3755), .Y(n3741) );
XOR2X1TS U4953 ( .A(n3742), .B(n3776), .Y(n3746) );
ADDHX1TS U4954 ( .A(n3744), .B(n3743), .CO(n3716), .S(n3745) );
NOR2X1TS U4955 ( .A(n3746), .B(n3745), .Y(n3926) );
NAND2X1TS U4956 ( .A(n3746), .B(n3745), .Y(n3927) );
OAI21X1TS U4957 ( .A0(n3930), .A1(n3926), .B0(n3927), .Y(n3933) );
NAND2X1TS U4958 ( .A(n3748), .B(n3747), .Y(n3976) );
NAND2X1TS U4959 ( .A(n3750), .B(n3749), .Y(n3980) );
AOI21X1TS U4960 ( .A0(n3752), .A1(n3933), .B0(n3751), .Y(n3990) );
ADDHXLTS U4961 ( .A(n3754), .B(n3753), .CO(n3691), .S(n3785) );
AOI222X1TS U4962 ( .A0(n3623), .A1(n3759), .B0(n3758), .B1(n3757), .C0(n3756), .C1(n3755), .Y(n3760) );
XOR2X1TS U4963 ( .A(n3764), .B(n3763), .Y(n3784) );
CMPR32X2TS U4964 ( .A(n3767), .B(n3766), .C(n3765), .CO(n3783), .S(n3749) );
AOI222X1TS U4965 ( .A0(n3772), .A1(n2241), .B0(n3771), .B1(n3770), .C0(n3769), .C1(n3768), .Y(n3773) );
XOR2X1TS U4966 ( .A(n3777), .B(n3776), .Y(n3778) );
NOR2X1TS U4967 ( .A(n3779), .B(n3778), .Y(n3986) );
NAND2X1TS U4968 ( .A(n3779), .B(n3778), .Y(n3987) );
OAI21X1TS U4969 ( .A0(n3990), .A1(n3986), .B0(n3987), .Y(n3995) );
CMPR32X2TS U4970 ( .A(n3782), .B(n3781), .C(n3780), .CO(n3789), .S(n3787) );
CMPR32X2TS U4971 ( .A(n3785), .B(n3784), .C(n3783), .CO(n3786), .S(n3779) );
NAND2X1TS U4972 ( .A(n3787), .B(n3786), .Y(n3992) );
INVX2TS U4973 ( .A(n3992), .Y(n3788) );
NAND2X1TS U4974 ( .A(mult_x_69_n762), .B(n3789), .Y(n3997) );
INVX2TS U4975 ( .A(n3997), .Y(n3951) );
NAND2X1TS U4976 ( .A(mult_x_69_n757), .B(mult_x_69_n761), .Y(n3952) );
INVX2TS U4977 ( .A(n3952), .Y(n3790) );
AOI21X1TS U4978 ( .A0(n3953), .A1(n3951), .B0(n3790), .Y(n3791) );
OAI21X1TS U4979 ( .A0(n3792), .A1(n3950), .B0(n3791), .Y(n3957) );
NOR2X2TS U4980 ( .A(mult_x_69_n752), .B(mult_x_69_n756), .Y(n3962) );
NOR2X2TS U4981 ( .A(mult_x_69_n745), .B(mult_x_69_n751), .Y(n3964) );
NAND2X1TS U4982 ( .A(mult_x_69_n752), .B(mult_x_69_n756), .Y(n3961) );
NAND2X1TS U4983 ( .A(mult_x_69_n745), .B(mult_x_69_n751), .Y(n3965) );
NAND2X1TS U4984 ( .A(n3871), .B(n3971), .Y(n3797) );
NAND2X1TS U4985 ( .A(mult_x_69_n738), .B(mult_x_69_n744), .Y(n3970) );
INVX2TS U4986 ( .A(n3970), .Y(n3869) );
NAND2X1TS U4987 ( .A(mult_x_69_n731), .B(mult_x_69_n737), .Y(n3870) );
INVX2TS U4988 ( .A(n3870), .Y(n3795) );
AOI21X1TS U4989 ( .A0(n3871), .A1(n3869), .B0(n3795), .Y(n3796) );
OAI21X2TS U4990 ( .A0(n3868), .A1(n3797), .B0(n3796), .Y(n3875) );
NOR2X2TS U4991 ( .A(mult_x_69_n715), .B(mult_x_69_n722), .Y(n3882) );
NOR2X2TS U4992 ( .A(mult_x_69_n723), .B(mult_x_69_n730), .Y(n3880) );
NOR2X1TS U4993 ( .A(n3882), .B(n3880), .Y(n3799) );
NAND2X1TS U4994 ( .A(mult_x_69_n723), .B(mult_x_69_n730), .Y(n3879) );
NAND2X1TS U4995 ( .A(mult_x_69_n715), .B(mult_x_69_n722), .Y(n3883) );
OAI21X1TS U4996 ( .A0(n3882), .A1(n3879), .B0(n3883), .Y(n3798) );
AOI21X4TS U4997 ( .A0(n3875), .A1(n3799), .B0(n3798), .Y(n3888) );
NAND2X1TS U4998 ( .A(mult_x_69_n707), .B(mult_x_69_n714), .Y(n3892) );
NAND2X1TS U4999 ( .A(mult_x_69_n697), .B(mult_x_69_n706), .Y(n3896) );
OAI21X1TS U5000 ( .A0(n3895), .A1(n3892), .B0(n3896), .Y(n3901) );
NAND2X1TS U5001 ( .A(mult_x_69_n687), .B(mult_x_69_n696), .Y(n3904) );
INVX2TS U5002 ( .A(n3904), .Y(n3800) );
AOI21X1TS U5003 ( .A0(n3901), .A1(n3905), .B0(n3800), .Y(n3801) );
NAND2X1TS U5004 ( .A(mult_x_69_n677), .B(mult_x_69_n686), .Y(n3913) );
INVX2TS U5005 ( .A(n3913), .Y(n3804) );
NAND2X1TS U5006 ( .A(mult_x_69_n666), .B(mult_x_69_n676), .Y(n3915) );
INVX2TS U5007 ( .A(n3915), .Y(n3803) );
AOI21X1TS U5008 ( .A0(n2307), .A1(n3804), .B0(n3803), .Y(n3936) );
NAND2X1TS U5009 ( .A(mult_x_69_n655), .B(mult_x_69_n665), .Y(n3940) );
OAI21X1TS U5010 ( .A0(n3936), .A1(n3939), .B0(n3940), .Y(n3805) );
AOI21X4TS U5011 ( .A0(n3806), .A1(n3909), .B0(n3805), .Y(n4058) );
NOR2X2TS U5012 ( .A(mult_x_69_n622), .B(mult_x_69_n632), .Y(n4067) );
NOR2X2TS U5013 ( .A(mult_x_69_n611), .B(mult_x_69_n621), .Y(n4061) );
NOR2X2TS U5014 ( .A(mult_x_69_n633), .B(mult_x_69_n643), .Y(n4075) );
NOR2X1TS U5015 ( .A(mult_x_69_n644), .B(mult_x_69_n654), .Y(n4073) );
NAND2X1TS U5016 ( .A(mult_x_69_n644), .B(mult_x_69_n654), .Y(n4081) );
NAND2X1TS U5017 ( .A(mult_x_69_n633), .B(mult_x_69_n643), .Y(n4076) );
OAI21X1TS U5018 ( .A0(n4075), .A1(n4081), .B0(n4076), .Y(n4059) );
NAND2X1TS U5019 ( .A(mult_x_69_n622), .B(mult_x_69_n632), .Y(n4068) );
NAND2X1TS U5020 ( .A(mult_x_69_n611), .B(mult_x_69_n621), .Y(n4062) );
AOI21X1TS U5021 ( .A0(n3808), .A1(n4059), .B0(n3807), .Y(n3809) );
NOR2X2TS U5022 ( .A(mult_x_69_n600), .B(mult_x_69_n610), .Y(n4052) );
NOR2X2TS U5023 ( .A(mult_x_69_n589), .B(mult_x_69_n599), .Y(n4046) );
NOR2X2TS U5024 ( .A(mult_x_69_n568), .B(mult_x_69_n577), .Y(n4035) );
NOR2X1TS U5025 ( .A(mult_x_69_n578), .B(mult_x_69_n588), .Y(n4033) );
NOR2X1TS U5026 ( .A(mult_x_69_n558), .B(mult_x_69_n567), .Y(n4016) );
NOR2X2TS U5027 ( .A(mult_x_69_n549), .B(mult_x_69_n557), .Y(n4023) );
NOR2X1TS U5028 ( .A(mult_x_69_n539), .B(mult_x_69_n531), .Y(n4110) );
INVX2TS U5029 ( .A(n4110), .Y(n4103) );
NAND2X1TS U5030 ( .A(n4103), .B(n4113), .Y(n3816) );
NOR2X1TS U5031 ( .A(mult_x_69_n540), .B(mult_x_69_n548), .Y(n4091) );
NAND2X1TS U5032 ( .A(mult_x_69_n600), .B(mult_x_69_n610), .Y(n4053) );
NAND2X1TS U5033 ( .A(mult_x_69_n589), .B(mult_x_69_n599), .Y(n4047) );
OAI21X1TS U5034 ( .A0(n4046), .A1(n4053), .B0(n4047), .Y(n4030) );
NAND2X1TS U5035 ( .A(mult_x_69_n578), .B(mult_x_69_n588), .Y(n4041) );
NAND2X1TS U5036 ( .A(mult_x_69_n568), .B(mult_x_69_n577), .Y(n4036) );
AOI21X1TS U5037 ( .A0(n4030), .A1(n3812), .B0(n3811), .Y(n4014) );
NAND2X1TS U5038 ( .A(mult_x_69_n558), .B(mult_x_69_n567), .Y(n4019) );
NAND2X1TS U5039 ( .A(mult_x_69_n549), .B(mult_x_69_n557), .Y(n4024) );
OAI21X1TS U5040 ( .A0(n4019), .A1(n4023), .B0(n4024), .Y(n4087) );
NAND2X1TS U5041 ( .A(mult_x_69_n540), .B(mult_x_69_n548), .Y(n4099) );
NAND2X1TS U5042 ( .A(mult_x_69_n539), .B(mult_x_69_n531), .Y(n4109) );
NAND2X1TS U5043 ( .A(mult_x_69_n523), .B(mult_x_69_n530), .Y(n4112) );
INVX2TS U5044 ( .A(n4112), .Y(n3813) );
AOI21X1TS U5045 ( .A0(n4113), .A1(n3814), .B0(n3813), .Y(n3815) );
AOI21X1TS U5046 ( .A0(n4087), .A1(n3818), .B0(n3817), .Y(n3819) );
OAI21X1TS U5047 ( .A0(n4014), .A1(n3820), .B0(n3819), .Y(n3821) );
NAND2X1TS U5048 ( .A(n4128), .B(n4131), .Y(n3825) );
NAND2X1TS U5049 ( .A(mult_x_69_n516), .B(mult_x_69_n522), .Y(n4121) );
INVX2TS U5050 ( .A(n4121), .Y(n4127) );
NAND2X1TS U5051 ( .A(mult_x_69_n509), .B(mult_x_69_n515), .Y(n4130) );
INVX2TS U5052 ( .A(n4130), .Y(n3823) );
AOI21X1TS U5053 ( .A0(n4131), .A1(n4127), .B0(n3823), .Y(n3824) );
NAND2X1TS U5054 ( .A(mult_x_69_n503), .B(mult_x_69_n508), .Y(n4138) );
INVX2TS U5055 ( .A(n4138), .Y(n3826) );
NOR2X1TS U5056 ( .A(mult_x_69_n502), .B(mult_x_69_n497), .Y(n4146) );
NAND2X1TS U5057 ( .A(mult_x_69_n502), .B(mult_x_69_n497), .Y(n4147) );
OAI21X4TS U5058 ( .A0(n4150), .A1(n4146), .B0(n4147), .Y(n4158) );
NAND2X1TS U5059 ( .A(mult_x_69_n491), .B(mult_x_69_n496), .Y(n4155) );
INVX2TS U5060 ( .A(n4155), .Y(n3827) );
NOR2X1TS U5061 ( .A(mult_x_69_n490), .B(mult_x_69_n486), .Y(n4163) );
NAND2X1TS U5062 ( .A(mult_x_69_n490), .B(mult_x_69_n486), .Y(n4164) );
NAND2X1TS U5063 ( .A(mult_x_69_n482), .B(mult_x_69_n485), .Y(n4172) );
INVX2TS U5064 ( .A(n4172), .Y(n3828) );
AOI21X4TS U5065 ( .A0(n4175), .A1(n4173), .B0(n3828), .Y(n4184) );
NOR2X1TS U5066 ( .A(mult_x_69_n478), .B(mult_x_69_n481), .Y(n4180) );
NAND2X1TS U5067 ( .A(mult_x_69_n478), .B(mult_x_69_n481), .Y(n4181) );
NAND2X1TS U5068 ( .A(mult_x_69_n477), .B(mult_x_69_n475), .Y(n4190) );
INVX2TS U5069 ( .A(n4190), .Y(n3829) );
AOI21X1TS U5070 ( .A0(n3831), .A1(n3843), .B0(n3830), .Y(n3832) );
OA21XLTS U5071 ( .A0(n3833), .A1(n3836), .B0(n3832), .Y(n3838) );
NOR2X1TS U5072 ( .A(mult_x_69_n474), .B(n3834), .Y(n4007) );
NAND2X1TS U5073 ( .A(mult_x_69_n474), .B(n3834), .Y(n4008) );
OAI21X2TS U5074 ( .A0(n4011), .A1(n4007), .B0(n4008), .Y(n4005) );
OA21XLTS U5075 ( .A0(n3837), .A1(n3836), .B0(n3835), .Y(n3842) );
CMPR32X2TS U5076 ( .A(n5075), .B(mult_x_69_n473), .C(n3838), .CO(n3839), .S(
n3834) );
NAND2X1TS U5077 ( .A(n3840), .B(n3839), .Y(n4002) );
INVX2TS U5078 ( .A(n4002), .Y(n3841) );
CMPR32X2TS U5079 ( .A(n3843), .B(n3844), .C(n3842), .CO(n3845), .S(n3840) );
NAND2X1TS U5080 ( .A(n3845), .B(n5075), .Y(n3846) );
NAND2X1TS U5081 ( .A(n3847), .B(n3846), .Y(n3848) );
XOR2X1TS U5082 ( .A(n3849), .B(n3848), .Y(n3854) );
BUFX4TS U5083 ( .A(n3984), .Y(n4185) );
NAND2X1TS U5084 ( .A(n4432), .B(n5081), .Y(n1691) );
MX2X1TS U5085 ( .A(Data_1[30]), .B(FPMULT_Op_MX[30]), .S0(n3856), .Y(n1689)
);
MX2X1TS U5086 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
MX2X1TS U5087 ( .A(Data_1[29]), .B(FPMULT_Op_MX[29]), .S0(n3856), .Y(n1688)
);
MX2X1TS U5088 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U5089 ( .A(Data_1[28]), .B(FPMULT_Op_MX[28]), .S0(n3856), .Y(n1687)
);
MX2X1TS U5090 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
MX2X1TS U5091 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n3856), .Y(n1686)
);
MX2X1TS U5092 ( .A(FPMULT_Exp_module_Data_S[4]), .B(
FPMULT_exp_oper_result[4]), .S0(n3855), .Y(n1545) );
MX2X1TS U5093 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
MX2X1TS U5094 ( .A(Data_1[26]), .B(n2259), .S0(n3856), .Y(n1685) );
MX2X1TS U5095 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_exp_oper_result[3]), .S0(n3855), .Y(n1546) );
MX2X1TS U5096 ( .A(n2259), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U5097 ( .A(Data_1[25]), .B(n2260), .S0(n3856), .Y(n1684) );
MX2X1TS U5098 ( .A(FPMULT_Exp_module_Data_S[2]), .B(
FPMULT_exp_oper_result[2]), .S0(n3855), .Y(n1547) );
MX2X1TS U5099 ( .A(n2260), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U5100 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n4411), .Y(n1683)
);
MX2X1TS U5101 ( .A(FPMULT_Exp_module_Data_S[1]), .B(
FPMULT_exp_oper_result[1]), .S0(n3855), .Y(n1548) );
MX2X1TS U5102 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U5103 ( .A(Data_1[23]), .B(FPMULT_Op_MX[23]), .S0(n4411), .Y(n1682)
);
MX2X1TS U5104 ( .A(FPMULT_Exp_module_Data_S[0]), .B(
FPMULT_exp_oper_result[0]), .S0(n3855), .Y(n1549) );
MX2X1TS U5105 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U5106 ( .A(Data_2[30]), .B(FPMULT_Op_MY[30]), .S0(n4411), .Y(n1657)
);
MX2X1TS U5107 ( .A(Data_2[29]), .B(FPMULT_Op_MY[29]), .S0(n4411), .Y(n1656)
);
MX2X1TS U5108 ( .A(Data_2[28]), .B(FPMULT_Op_MY[28]), .S0(n4411), .Y(n1655)
);
MX2X1TS U5109 ( .A(Data_2[27]), .B(FPMULT_Op_MY[27]), .S0(n4411), .Y(n1654)
);
MX2X1TS U5110 ( .A(Data_2[26]), .B(FPMULT_Op_MY[26]), .S0(n4411), .Y(n1653)
);
MX2X1TS U5111 ( .A(Data_2[25]), .B(FPMULT_Op_MY[25]), .S0(n4411), .Y(n1652)
);
MX2X1TS U5112 ( .A(Data_2[24]), .B(FPMULT_Op_MY[24]), .S0(n4411), .Y(n1651)
);
MX2X1TS U5113 ( .A(Data_2[23]), .B(FPMULT_Op_MY[23]), .S0(n4411), .Y(n1650)
);
XNOR2X1TS U5114 ( .A(DP_OP_230J216_125_7006_n1), .B(n3857), .Y(n3858) );
MX2X1TS U5115 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1420) );
MX2X1TS U5116 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1425) );
MX2X1TS U5117 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1430) );
MX2X1TS U5118 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1435) );
MX2X1TS U5119 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1440) );
MX2X1TS U5120 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1445) );
MX2X1TS U5121 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1450) );
MX2X1TS U5122 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1455) );
OA21XLTS U5123 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(
overflow_flag_addsubt), .B0(n3861), .Y(n1413) );
NAND4XLTS U5124 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n3862) );
NAND4BXLTS U5125 ( .AN(n3862), .B(FPMULT_Exp_module_Data_S[6]), .C(
FPMULT_Exp_module_Data_S[5]), .D(FPMULT_Exp_module_Data_S[4]), .Y(
n3863) );
OAI22X1TS U5126 ( .A0(FPMULT_Exp_module_Data_S[8]), .A1(n3864), .B0(n4434),
.B1(n5091), .Y(n1516) );
NAND2X2TS U5127 ( .A(n4528), .B(FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n3867) );
OA22X1TS U5128 ( .A0(n3867), .A1(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(result_add_subt[29]), .Y(n1469) );
INVX2TS U5129 ( .A(n3867), .Y(n3866) );
AOI22X1TS U5130 ( .A0(n3866), .A1(n3865), .B0(n5090), .B1(n5041), .Y(n1472)
);
OA22X1TS U5131 ( .A0(n3867), .A1(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(result_add_subt[25]), .Y(n1473) );
OA22X1TS U5132 ( .A0(n3867), .A1(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(result_add_subt[23]), .Y(n1475) );
INVX2TS U5133 ( .A(n3868), .Y(n3973) );
AOI21X1TS U5134 ( .A0(n3973), .A1(n3971), .B0(n3869), .Y(n3873) );
NAND2X1TS U5135 ( .A(n3871), .B(n3870), .Y(n3872) );
XOR2X1TS U5136 ( .A(n3873), .B(n3872), .Y(n3874) );
INVX2TS U5137 ( .A(n3875), .Y(n3881) );
INVX2TS U5138 ( .A(n3880), .Y(n3876) );
NAND2X1TS U5139 ( .A(n3876), .B(n3879), .Y(n3877) );
XOR2X1TS U5140 ( .A(n3881), .B(n3877), .Y(n3878) );
INVX2TS U5141 ( .A(n3882), .Y(n3884) );
NAND2X1TS U5142 ( .A(n3884), .B(n3883), .Y(n3885) );
XNOR2X1TS U5143 ( .A(n3886), .B(n3885), .Y(n3887) );
INVX2TS U5144 ( .A(n3888), .Y(n3903) );
INVX2TS U5145 ( .A(n3889), .Y(n3894) );
NAND2X1TS U5146 ( .A(n3894), .B(n3892), .Y(n3890) );
XNOR2X1TS U5147 ( .A(n3903), .B(n3890), .Y(n3891) );
INVX2TS U5148 ( .A(n3892), .Y(n3893) );
AOI21X1TS U5149 ( .A0(n3903), .A1(n3894), .B0(n3893), .Y(n3899) );
INVX2TS U5150 ( .A(n3895), .Y(n3897) );
NAND2X1TS U5151 ( .A(n3897), .B(n3896), .Y(n3898) );
XOR2X1TS U5152 ( .A(n3899), .B(n3898), .Y(n3900) );
BUFX4TS U5153 ( .A(n3984), .Y(n3974) );
AOI21X1TS U5154 ( .A0(n3903), .A1(n3902), .B0(n3901), .Y(n3907) );
NAND2X1TS U5155 ( .A(n3905), .B(n3904), .Y(n3906) );
XOR2X1TS U5156 ( .A(n3907), .B(n3906), .Y(n3908) );
INVX2TS U5157 ( .A(n3909), .Y(n3938) );
NAND2X1TS U5158 ( .A(n3910), .B(n3913), .Y(n3911) );
XOR2X1TS U5159 ( .A(n3938), .B(n3911), .Y(n3912) );
NAND2X1TS U5160 ( .A(n2307), .B(n3915), .Y(n3916) );
XNOR2X1TS U5161 ( .A(n3917), .B(n3916), .Y(n3918) );
XOR2X1TS U5162 ( .A(n2306), .B(n3919), .Y(n3920) );
NAND2X1TS U5163 ( .A(n3922), .B(n3921), .Y(n3924) );
XNOR2X1TS U5164 ( .A(n3924), .B(n3923), .Y(n3925) );
INVX2TS U5165 ( .A(n3926), .Y(n3928) );
NAND2X1TS U5166 ( .A(n3928), .B(n3927), .Y(n3929) );
XOR2X1TS U5167 ( .A(n3930), .B(n3929), .Y(n3931) );
INVX2TS U5168 ( .A(n3977), .Y(n3932) );
NAND2X1TS U5169 ( .A(n3932), .B(n3976), .Y(n3934) );
INVX2TS U5170 ( .A(n3933), .Y(n3978) );
XOR2X1TS U5171 ( .A(n3934), .B(n3978), .Y(n3935) );
INVX2TS U5172 ( .A(n3939), .Y(n3941) );
NAND2X1TS U5173 ( .A(n3941), .B(n3940), .Y(n3942) );
XNOR2X1TS U5174 ( .A(n3943), .B(n3942), .Y(n3944) );
MX2X1TS U5175 ( .A(FPMULT_P_Sgf[0]), .B(n3945), .S0(n3974), .Y(n1553) );
INVX2TS U5176 ( .A(n3946), .Y(n3948) );
XNOR2X1TS U5177 ( .A(n3948), .B(n3947), .Y(n3949) );
MX2X1TS U5178 ( .A(FPMULT_P_Sgf[1]), .B(n3949), .S0(n3974), .Y(n1554) );
INVX2TS U5179 ( .A(n3950), .Y(n4000) );
AOI21X1TS U5180 ( .A0(n4000), .A1(n3998), .B0(n3951), .Y(n3955) );
NAND2X1TS U5181 ( .A(n3953), .B(n3952), .Y(n3954) );
XOR2X1TS U5182 ( .A(n3955), .B(n3954), .Y(n3956) );
INVX2TS U5183 ( .A(n3957), .Y(n3963) );
INVX2TS U5184 ( .A(n3962), .Y(n3958) );
NAND2X1TS U5185 ( .A(n3958), .B(n3961), .Y(n3959) );
XOR2X1TS U5186 ( .A(n3963), .B(n3959), .Y(n3960) );
INVX2TS U5187 ( .A(n3964), .Y(n3966) );
NAND2X1TS U5188 ( .A(n3966), .B(n3965), .Y(n3967) );
XNOR2X1TS U5189 ( .A(n3968), .B(n3967), .Y(n3969) );
NAND2X1TS U5190 ( .A(n3971), .B(n3970), .Y(n3972) );
XNOR2X1TS U5191 ( .A(n3973), .B(n3972), .Y(n3975) );
INVX2TS U5192 ( .A(n3979), .Y(n3981) );
NAND2X1TS U5193 ( .A(n3981), .B(n3980), .Y(n3982) );
XNOR2X1TS U5194 ( .A(n3983), .B(n3982), .Y(n3985) );
BUFX4TS U5195 ( .A(n3984), .Y(n4194) );
INVX2TS U5196 ( .A(n3986), .Y(n3988) );
NAND2X1TS U5197 ( .A(n3988), .B(n3987), .Y(n3989) );
XOR2X1TS U5198 ( .A(n3990), .B(n3989), .Y(n3991) );
NAND2X1TS U5199 ( .A(n3993), .B(n3992), .Y(n3994) );
XNOR2X1TS U5200 ( .A(n3995), .B(n3994), .Y(n3996) );
NAND2X1TS U5201 ( .A(n3998), .B(n3997), .Y(n3999) );
XNOR2X1TS U5202 ( .A(n4000), .B(n3999), .Y(n4001) );
NAND2X1TS U5203 ( .A(n4003), .B(n4002), .Y(n4004) );
XNOR2X1TS U5204 ( .A(n4005), .B(n4004), .Y(n4006) );
INVX2TS U5205 ( .A(n4007), .Y(n4009) );
NAND2X1TS U5206 ( .A(n4009), .B(n4008), .Y(n4010) );
XOR2X1TS U5207 ( .A(n4011), .B(n4010), .Y(n4012) );
INVX2TS U5208 ( .A(n4022), .Y(n4090) );
INVX2TS U5209 ( .A(n4016), .Y(n4021) );
NAND2X1TS U5210 ( .A(n4021), .B(n4019), .Y(n4017) );
XOR2X1TS U5211 ( .A(n4090), .B(n4017), .Y(n4018) );
INVX2TS U5212 ( .A(n4019), .Y(n4020) );
AOI21X1TS U5213 ( .A0(n4022), .A1(n4021), .B0(n4020), .Y(n4027) );
INVX2TS U5214 ( .A(n4023), .Y(n4025) );
NAND2X1TS U5215 ( .A(n4025), .B(n4024), .Y(n4026) );
XOR2X1TS U5216 ( .A(n4027), .B(n4026), .Y(n4028) );
INVX2TS U5217 ( .A(n4029), .Y(n4032) );
INVX2TS U5218 ( .A(n4030), .Y(n4031) );
OAI21X1TS U5219 ( .A0(n4056), .A1(n4032), .B0(n4031), .Y(n4044) );
INVX2TS U5220 ( .A(n4033), .Y(n4042) );
INVX2TS U5221 ( .A(n4041), .Y(n4034) );
AOI21X1TS U5222 ( .A0(n4044), .A1(n4042), .B0(n4034), .Y(n4039) );
INVX2TS U5223 ( .A(n4035), .Y(n4037) );
NAND2X1TS U5224 ( .A(n4037), .B(n4036), .Y(n4038) );
XOR2X1TS U5225 ( .A(n4039), .B(n4038), .Y(n4040) );
NAND2X1TS U5226 ( .A(n4042), .B(n4041), .Y(n4043) );
XNOR2X1TS U5227 ( .A(n4044), .B(n4043), .Y(n4045) );
INVX2TS U5228 ( .A(n4046), .Y(n4048) );
NAND2X1TS U5229 ( .A(n4048), .B(n4047), .Y(n4049) );
XNOR2X1TS U5230 ( .A(n4050), .B(n4049), .Y(n4051) );
INVX2TS U5231 ( .A(n4052), .Y(n4054) );
NAND2X1TS U5232 ( .A(n4054), .B(n4053), .Y(n4055) );
XOR2X1TS U5233 ( .A(n4056), .B(n4055), .Y(n4057) );
INVX2TS U5234 ( .A(n4058), .Y(n4084) );
AOI21X1TS U5235 ( .A0(n4084), .A1(n4060), .B0(n4059), .Y(n4071) );
INVX2TS U5236 ( .A(n4061), .Y(n4063) );
NAND2X1TS U5237 ( .A(n4063), .B(n4062), .Y(n4064) );
XNOR2X1TS U5238 ( .A(n4065), .B(n4064), .Y(n4066) );
INVX2TS U5239 ( .A(n4067), .Y(n4069) );
NAND2X1TS U5240 ( .A(n4069), .B(n4068), .Y(n4070) );
XOR2X1TS U5241 ( .A(n4071), .B(n4070), .Y(n4072) );
INVX2TS U5242 ( .A(n4073), .Y(n4082) );
INVX2TS U5243 ( .A(n4081), .Y(n4074) );
AOI21X1TS U5244 ( .A0(n4084), .A1(n4082), .B0(n4074), .Y(n4079) );
INVX2TS U5245 ( .A(n4075), .Y(n4077) );
NAND2X1TS U5246 ( .A(n4077), .B(n4076), .Y(n4078) );
XOR2X1TS U5247 ( .A(n4079), .B(n4078), .Y(n4080) );
NAND2X1TS U5248 ( .A(n4082), .B(n4081), .Y(n4083) );
XNOR2X1TS U5249 ( .A(n4084), .B(n4083), .Y(n4085) );
INVX2TS U5250 ( .A(n4086), .Y(n4089) );
INVX2TS U5251 ( .A(n4087), .Y(n4088) );
OAI21X1TS U5252 ( .A0(n4090), .A1(n4089), .B0(n4088), .Y(n4102) );
INVX2TS U5253 ( .A(n4091), .Y(n4101) );
NAND2X1TS U5254 ( .A(n4101), .B(n4099), .Y(n4092) );
XNOR2X1TS U5255 ( .A(n4102), .B(n4092), .Y(n4093) );
INVX2TS U5256 ( .A(n2612), .Y(n4097) );
AOI22X1TS U5257 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4435), .B0(
FPMULT_Add_result[10]), .B1(n2276), .Y(n4096) );
NAND2X1TS U5258 ( .A(n4201), .B(FPMULT_P_Sgf[33]), .Y(n4095) );
OAI211XLTS U5259 ( .A0(n4097), .A1(n2231), .B0(n4096), .C0(n4095), .Y(n4098)
);
AO21XLTS U5260 ( .A0(n2262), .A1(FPMULT_Add_result[9]), .B0(n4098), .Y(n1526) );
INVX2TS U5261 ( .A(n4099), .Y(n4100) );
AOI21X1TS U5262 ( .A0(n4102), .A1(n4101), .B0(n4100), .Y(n4111) );
NAND2X1TS U5263 ( .A(n4103), .B(n4109), .Y(n4104) );
XOR2X1TS U5264 ( .A(n4111), .B(n4104), .Y(n4105) );
AOI22X1TS U5265 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n4435), .B0(
FPMULT_Add_result[11]), .B1(n2276), .Y(n4106) );
OAI2BB1X1TS U5266 ( .A0N(FPMULT_P_Sgf[34]), .A1N(n4201), .B0(n4106), .Y(
n4107) );
AOI21X1TS U5267 ( .A0(n2612), .A1(FPMULT_P_Sgf[33]), .B0(n4107), .Y(n4108)
);
OAI2BB1X1TS U5268 ( .A0N(n2262), .A1N(FPMULT_Add_result[10]), .B0(n4108),
.Y(n1527) );
NAND2X1TS U5269 ( .A(n4113), .B(n4112), .Y(n4114) );
XNOR2X1TS U5270 ( .A(n4115), .B(n4114), .Y(n4116) );
AOI22X1TS U5271 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4435), .B0(
FPMULT_Add_result[12]), .B1(n2276), .Y(n4117) );
OAI2BB1X1TS U5272 ( .A0N(FPMULT_P_Sgf[35]), .A1N(n4201), .B0(n4117), .Y(
n4118) );
AOI21X1TS U5273 ( .A0(n2612), .A1(FPMULT_P_Sgf[34]), .B0(n4118), .Y(n4119)
);
OAI2BB1X1TS U5274 ( .A0N(n2262), .A1N(FPMULT_Add_result[11]), .B0(n4119),
.Y(n1528) );
INVX2TS U5275 ( .A(n4120), .Y(n4129) );
NAND2X1TS U5276 ( .A(n4128), .B(n4121), .Y(n4122) );
XNOR2X1TS U5277 ( .A(n4129), .B(n4122), .Y(n4123) );
AOI22X1TS U5278 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n4435), .B0(
FPMULT_Add_result[13]), .B1(n2276), .Y(n4124) );
OAI2BB1X1TS U5279 ( .A0N(FPMULT_P_Sgf[36]), .A1N(n4201), .B0(n4124), .Y(
n4125) );
AOI21X1TS U5280 ( .A0(n2612), .A1(FPMULT_P_Sgf[35]), .B0(n4125), .Y(n4126)
);
OAI2BB1X1TS U5281 ( .A0N(n2262), .A1N(FPMULT_Add_result[12]), .B0(n4126),
.Y(n1529) );
AOI21X1TS U5282 ( .A0(n4129), .A1(n4128), .B0(n4127), .Y(n4133) );
NAND2X1TS U5283 ( .A(n4131), .B(n4130), .Y(n4132) );
XOR2X1TS U5284 ( .A(n4133), .B(n4132), .Y(n4134) );
AOI22X1TS U5285 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4435), .B0(
FPMULT_Add_result[14]), .B1(n2276), .Y(n4135) );
OAI2BB1X1TS U5286 ( .A0N(FPMULT_P_Sgf[37]), .A1N(n4201), .B0(n4135), .Y(
n4136) );
AOI21X1TS U5287 ( .A0(n2612), .A1(FPMULT_P_Sgf[36]), .B0(n4136), .Y(n4137)
);
OAI2BB1X1TS U5288 ( .A0N(n2262), .A1N(FPMULT_Add_result[13]), .B0(n4137),
.Y(n1530) );
NAND2X1TS U5289 ( .A(n4139), .B(n4138), .Y(n4140) );
XNOR2X1TS U5290 ( .A(n4141), .B(n4140), .Y(n4142) );
AOI22X1TS U5291 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n4435), .B0(
FPMULT_Add_result[15]), .B1(n2276), .Y(n4143) );
OAI2BB1X1TS U5292 ( .A0N(FPMULT_P_Sgf[38]), .A1N(n4201), .B0(n4143), .Y(
n4144) );
AOI21X1TS U5293 ( .A0(n2612), .A1(FPMULT_P_Sgf[37]), .B0(n4144), .Y(n4145)
);
OAI2BB1X1TS U5294 ( .A0N(n2262), .A1N(FPMULT_Add_result[14]), .B0(n4145),
.Y(n1531) );
INVX2TS U5295 ( .A(n4146), .Y(n4148) );
NAND2X1TS U5296 ( .A(n4148), .B(n4147), .Y(n4149) );
XOR2X1TS U5297 ( .A(n4150), .B(n4149), .Y(n4151) );
AOI22X1TS U5298 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4435), .B0(
FPMULT_Add_result[16]), .B1(n2276), .Y(n4152) );
OAI2BB1X1TS U5299 ( .A0N(FPMULT_P_Sgf[39]), .A1N(n4201), .B0(n4152), .Y(
n4153) );
AOI21X1TS U5300 ( .A0(n2612), .A1(FPMULT_P_Sgf[38]), .B0(n4153), .Y(n4154)
);
OAI2BB1X1TS U5301 ( .A0N(n2262), .A1N(FPMULT_Add_result[15]), .B0(n4154),
.Y(n1532) );
NAND2X1TS U5302 ( .A(n4156), .B(n4155), .Y(n4157) );
XNOR2X1TS U5303 ( .A(n4158), .B(n4157), .Y(n4159) );
AOI22X1TS U5304 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n4435), .B0(
FPMULT_Add_result[17]), .B1(n2276), .Y(n4160) );
OAI2BB1X1TS U5305 ( .A0N(FPMULT_P_Sgf[40]), .A1N(n4201), .B0(n4160), .Y(
n4161) );
AOI21X1TS U5306 ( .A0(n2612), .A1(FPMULT_P_Sgf[39]), .B0(n4161), .Y(n4162)
);
OAI2BB1X1TS U5307 ( .A0N(n2262), .A1N(FPMULT_Add_result[16]), .B0(n4162),
.Y(n1533) );
INVX2TS U5308 ( .A(n4163), .Y(n4165) );
NAND2X1TS U5309 ( .A(n4165), .B(n4164), .Y(n4166) );
XOR2X1TS U5310 ( .A(n4167), .B(n4166), .Y(n4168) );
AOI22X1TS U5311 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4435), .B0(
FPMULT_Add_result[18]), .B1(n2276), .Y(n4169) );
OAI2BB1X1TS U5312 ( .A0N(FPMULT_P_Sgf[41]), .A1N(n4201), .B0(n4169), .Y(
n4170) );
AOI21X1TS U5313 ( .A0(n4203), .A1(FPMULT_P_Sgf[40]), .B0(n4170), .Y(n4171)
);
OAI2BB1X1TS U5314 ( .A0N(n2262), .A1N(FPMULT_Add_result[17]), .B0(n4171),
.Y(n1534) );
NAND2X1TS U5315 ( .A(n4173), .B(n4172), .Y(n4174) );
XNOR2X1TS U5316 ( .A(n4175), .B(n4174), .Y(n4176) );
AOI22X1TS U5317 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n4435), .B0(
FPMULT_Add_result[19]), .B1(n2276), .Y(n4177) );
OAI2BB1X1TS U5318 ( .A0N(FPMULT_P_Sgf[42]), .A1N(n4201), .B0(n4177), .Y(
n4178) );
AOI21X1TS U5319 ( .A0(n4203), .A1(FPMULT_P_Sgf[41]), .B0(n4178), .Y(n4179)
);
OAI2BB1X1TS U5320 ( .A0N(n2262), .A1N(FPMULT_Add_result[18]), .B0(n4179),
.Y(n1535) );
INVX2TS U5321 ( .A(n4180), .Y(n4182) );
NAND2X1TS U5322 ( .A(n4182), .B(n4181), .Y(n4183) );
XOR2X1TS U5323 ( .A(n4184), .B(n4183), .Y(n4186) );
AOI22X1TS U5324 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4435), .B0(
FPMULT_Add_result[20]), .B1(n2277), .Y(n4187) );
OAI2BB1X1TS U5325 ( .A0N(FPMULT_P_Sgf[43]), .A1N(n4201), .B0(n4187), .Y(
n4188) );
AOI21X1TS U5326 ( .A0(n4203), .A1(FPMULT_P_Sgf[42]), .B0(n4188), .Y(n4189)
);
OAI2BB1X1TS U5327 ( .A0N(n2262), .A1N(FPMULT_Add_result[19]), .B0(n4189),
.Y(n1536) );
NAND2X1TS U5328 ( .A(n4191), .B(n4190), .Y(n4192) );
XNOR2X1TS U5329 ( .A(n4193), .B(n4192), .Y(n4195) );
AOI22X1TS U5330 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n4199), .B0(
FPMULT_Add_result[21]), .B1(n2277), .Y(n4196) );
OAI2BB1X1TS U5331 ( .A0N(FPMULT_P_Sgf[44]), .A1N(n4201), .B0(n4196), .Y(
n4197) );
AOI21X1TS U5332 ( .A0(n4203), .A1(FPMULT_P_Sgf[43]), .B0(n4197), .Y(n4198)
);
OAI2BB1X1TS U5333 ( .A0N(n2262), .A1N(FPMULT_Add_result[20]), .B0(n4198),
.Y(n1537) );
AOI22X1TS U5334 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n4199), .B0(
n2258), .B1(n2277), .Y(n4200) );
OAI2BB1X1TS U5335 ( .A0N(FPMULT_P_Sgf[45]), .A1N(n4201), .B0(n4200), .Y(
n4202) );
AOI21X1TS U5336 ( .A0(n4203), .A1(FPMULT_P_Sgf[44]), .B0(n4202), .Y(n4204)
);
OAI2BB1X1TS U5337 ( .A0N(n2262), .A1N(FPMULT_Add_result[21]), .B0(n4204),
.Y(n1538) );
NOR4X1TS U5338 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n4211) );
NOR4X1TS U5339 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n4210) );
NOR4X1TS U5340 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n4208) );
NOR3XLTS U5341 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n4207) );
NOR4X1TS U5342 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n4206) );
NOR4X1TS U5343 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n4205) );
AND4X1TS U5344 ( .A(n4208), .B(n4207), .C(n4206), .D(n4205), .Y(n4209) );
NAND4XLTS U5345 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n4213) );
NAND4XLTS U5346 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n4212) );
NOR3X1TS U5347 ( .A(n5240), .B(n4213), .C(n4212), .Y(n4218) );
NOR4X1TS U5348 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[28]), .D(dataB[23]),
.Y(n4215) );
NOR3XLTS U5349 ( .A(dataB[26]), .B(dataB[29]), .C(dataB[25]), .Y(n4214) );
NAND4XLTS U5350 ( .A(n4218), .B(operation_reg[1]), .C(n4215), .D(n4214), .Y(
n4216) );
NOR3XLTS U5351 ( .A(operation_reg[0]), .B(dataB[31]), .C(n4216), .Y(n4217)
);
OAI211XLTS U5352 ( .A0(dataB[27]), .A1(n4217), .B0(n5239), .C0(n5238), .Y(
n4228) );
NOR4X1TS U5353 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[28]), .D(dataA[26]),
.Y(n4221) );
NOR4BX1TS U5354 ( .AN(operation_reg[1]), .B(dataA[31]), .C(dataA[24]), .D(
dataA[25]), .Y(n4220) );
NOR4X1TS U5355 ( .A(n5240), .B(dataA[30]), .C(operation_reg[0]), .D(
dataA[27]), .Y(n4219) );
NOR2BX1TS U5356 ( .AN(n4218), .B(operation_reg[1]), .Y(n4226) );
AOI31XLTS U5357 ( .A0(n4221), .A1(n4220), .A2(n4219), .B0(n4226), .Y(n4224)
);
NAND3XLTS U5358 ( .A(dataB[23]), .B(dataB[28]), .C(dataB[25]), .Y(n4223) );
NAND4XLTS U5359 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n4222) );
OAI31X1TS U5360 ( .A0(n4224), .A1(n4223), .A2(n4222), .B0(dataB[27]), .Y(
n4225) );
NAND4XLTS U5361 ( .A(n5243), .B(n5242), .C(n5241), .D(n4225), .Y(n4227) );
OAI2BB2XLTS U5362 ( .B0(n4228), .B1(n4227), .A0N(n4226), .A1N(
operation_reg[0]), .Y(NaN_reg) );
AOI22X1TS U5363 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n4229), .B1(n4870),
.Y(FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
NOR3XLTS U5364 ( .A(n4331), .B(n4288), .C(n4230), .Y(n4231) );
CLKAND2X2TS U5365 ( .A(begin_operation), .B(operation[1]), .Y(n4235) );
OAI22X1TS U5366 ( .A0(n4233), .A1(n4232), .B0(n4235), .B1(n4234), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U5367 ( .AN(n4235), .B(n4234), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
NOR3XLTS U5368 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n4903),
.C(n4236), .Y(n4237) );
AO21XLTS U5369 ( .A0(n4259), .A1(n4238), .B0(n4237), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
OAI22X1TS U5370 ( .A0(n4298), .A1(n4241), .B0(n4240), .B1(n4239), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
AO22XLTS U5371 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n4242),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
AOI22X1TS U5372 ( .A0(n4247), .A1(cordic_result[30]), .B0(n4246), .B1(
mult_result[30]), .Y(n4243) );
OAI2BB1X1TS U5373 ( .A0N(n4250), .A1N(result_add_subt[30]), .B0(n4243), .Y(
op_result[30]) );
AOI22X1TS U5374 ( .A0(n4247), .A1(cordic_result[29]), .B0(n4246), .B1(
mult_result[29]), .Y(n4244) );
OAI2BB1X1TS U5375 ( .A0N(n4250), .A1N(result_add_subt[29]), .B0(n4244), .Y(
op_result[29]) );
AOI22X1TS U5376 ( .A0(n4247), .A1(cordic_result[25]), .B0(n4246), .B1(
mult_result[25]), .Y(n4245) );
OAI2BB1X1TS U5377 ( .A0N(n4250), .A1N(result_add_subt[25]), .B0(n4245), .Y(
op_result[25]) );
AOI22X1TS U5378 ( .A0(n4247), .A1(cordic_result[23]), .B0(n4246), .B1(
mult_result[23]), .Y(n4248) );
OAI2BB1X1TS U5379 ( .A0N(n4250), .A1N(result_add_subt[23]), .B0(n4248), .Y(
op_result[23]) );
AOI22X1TS U5380 ( .A0(n4250), .A1(ready_add_subt), .B0(n3013), .B1(n4249),
.Y(n4251) );
OAI2BB1X1TS U5381 ( .A0N(n4252), .A1N(n3012), .B0(n4251), .Y(operation_ready) );
OAI33X4TS U5382 ( .A0(n4980), .A1(n4870), .A2(n4899), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n4255) );
INVX2TS U5383 ( .A(n4255), .Y(n4257) );
AO22XLTS U5384 ( .A0(n4255), .A1(n5156), .B0(n4257), .B1(n4253), .Y(n2150)
);
BUFX3TS U5385 ( .A(n5083), .Y(n4634) );
BUFX3TS U5386 ( .A(n4634), .Y(n4814) );
AOI22X1TS U5387 ( .A0(n4257), .A1(n4254), .B0(n4814), .B1(n4255), .Y(n2149)
);
AOI22X1TS U5388 ( .A0(n4257), .A1(n4814), .B0(n2253), .B1(n4255), .Y(n2148)
);
AOI22X1TS U5389 ( .A0(n4257), .A1(n4760), .B0(n4256), .B1(n4255), .Y(n2145)
);
AOI22X1TS U5390 ( .A0(n4257), .A1(n4256), .B0(n5090), .B1(n4255), .Y(n2144)
);
AOI22X1TS U5391 ( .A0(n4259), .A1(n5157), .B0(n2206), .B1(n4258), .Y(n2143)
);
INVX2TS U5392 ( .A(n4260), .Y(n4261) );
AOI2BB2XLTS U5393 ( .B0(n4261), .B1(n4262), .A0N(n4262), .A1N(n4261), .Y(
n2141) );
NAND2X1TS U5394 ( .A(n4261), .B(n4262), .Y(n4263) );
XNOR2X1TS U5395 ( .A(FPSENCOS_cont_iter_out[3]), .B(n4263), .Y(n2140) );
AOI2BB2XLTS U5396 ( .B0(n4264), .B1(n5077), .A0N(n5077), .A1N(n4264), .Y(
n2139) );
AOI22X1TS U5397 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n4283), .B0(n4267),
.B1(n4270), .Y(n4266) );
NAND2X1TS U5398 ( .A(n4266), .B(n4265), .Y(n2134) );
AOI22X1TS U5399 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n4283), .B0(n4267),
.B1(n4273), .Y(n4269) );
NAND2X1TS U5400 ( .A(n4269), .B(n4268), .Y(n2130) );
AOI22X1TS U5401 ( .A0(n4271), .A1(n4270), .B0(FPSENCOS_d_ff3_LUT_out[7]),
.B1(n4283), .Y(n4272) );
NAND2X1TS U5402 ( .A(n4272), .B(n4278), .Y(n2128) );
AOI22X1TS U5403 ( .A0(FPSENCOS_d_ff3_LUT_out[10]), .A1(n4283), .B0(n4274),
.B1(n4273), .Y(n4275) );
AO22XLTS U5404 ( .A0(n4316), .A1(n4277), .B0(n4302), .B1(
FPSENCOS_d_ff3_LUT_out[19]), .Y(n2121) );
OAI221XLTS U5405 ( .A0(n4322), .A1(n5131), .B0(n4302), .B1(n4279), .C0(n4278), .Y(n2120) );
AOI22X1TS U5406 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n4283), .B0(n4282),
.B1(n4281), .Y(n4285) );
AOI32X1TS U5407 ( .A0(n4286), .A1(n4285), .A2(n4284), .B0(n4261), .B1(n4285),
.Y(n2117) );
INVX2TS U5408 ( .A(n4291), .Y(n4289) );
AO22XLTS U5409 ( .A0(n4289), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n4288), .B1(
Data_1[20]), .Y(n2094) );
AO22XLTS U5410 ( .A0(n4289), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n4288), .B1(
Data_1[21]), .Y(n2093) );
AO22XLTS U5411 ( .A0(n4289), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n4288), .B1(
Data_1[22]), .Y(n2092) );
AO22XLTS U5412 ( .A0(n4289), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n4290), .B1(
Data_1[23]), .Y(n2091) );
AO22XLTS U5413 ( .A0(n4289), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n4288), .B1(
Data_1[24]), .Y(n2090) );
AO22XLTS U5414 ( .A0(n4289), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n4290), .B1(
Data_1[25]), .Y(n2089) );
AO22XLTS U5415 ( .A0(n4289), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n4290), .B1(
Data_1[26]), .Y(n2088) );
OR3X2TS U5416 ( .A(FPSENCOS_cont_var_out[1]), .B(n5077), .C(n4932), .Y(n4299) );
AO22XLTS U5417 ( .A0(n4300), .A1(result_add_subt[0]), .B0(n4409), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(n2074) );
BUFX3TS U5418 ( .A(n4299), .Y(n4301) );
BUFX3TS U5419 ( .A(n4396), .Y(n4395) );
AO22XLTS U5420 ( .A0(n4397), .A1(result_add_subt[7]), .B0(n2201), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(n2055) );
AO22XLTS U5421 ( .A0(n4295), .A1(result_add_subt[10]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[10]), .Y(n2045) );
AO22XLTS U5422 ( .A0(n4397), .A1(result_add_subt[11]), .B0(n4399), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(n2043) );
AO22XLTS U5423 ( .A0(n4404), .A1(result_add_subt[11]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[11]), .Y(n2042) );
AO22XLTS U5424 ( .A0(n4295), .A1(result_add_subt[12]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[12]), .Y(n2039) );
AO22XLTS U5425 ( .A0(n4398), .A1(result_add_subt[20]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[20]), .Y(n2015) );
AO22XLTS U5426 ( .A0(n4398), .A1(result_add_subt[21]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[21]), .Y(n2012) );
AO22XLTS U5427 ( .A0(n4398), .A1(result_add_subt[22]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[22]), .Y(n2009) );
AO22XLTS U5428 ( .A0(n4332), .A1(FPSENCOS_d_ff3_sh_x_out[0]), .B0(n4303),
.B1(FPSENCOS_d_ff2_X[0]), .Y(n2006) );
OA22X1TS U5429 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n2251), .B0(
FPSENCOS_d_ff2_X[1]), .B1(n4331), .Y(n2005) );
OA22X1TS U5430 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n2250), .B0(
FPSENCOS_d_ff2_X[2]), .B1(n5234), .Y(n2003) );
OA22X1TS U5431 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n2251), .B0(
FPSENCOS_d_ff2_X[3]), .B1(n5234), .Y(n2001) );
AO22XLTS U5432 ( .A0(n4327), .A1(FPSENCOS_d_ff2_X[3]), .B0(n4401), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n2000) );
OA22X1TS U5433 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n2250), .B0(
FPSENCOS_d_ff2_X[5]), .B1(n5234), .Y(n1997) );
AO22XLTS U5434 ( .A0(n4303), .A1(FPSENCOS_d_ff2_X[5]), .B0(n4302), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1996) );
OA22X1TS U5435 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n2251), .B0(
FPSENCOS_d_ff2_X[6]), .B1(n5234), .Y(n1995) );
AO22XLTS U5436 ( .A0(n4332), .A1(FPSENCOS_d_ff3_sh_x_out[6]), .B0(n4303),
.B1(FPSENCOS_d_ff2_X[6]), .Y(n1994) );
OA22X1TS U5437 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n2251), .B0(
FPSENCOS_d_ff2_X[7]), .B1(n5234), .Y(n1993) );
AO22XLTS U5438 ( .A0(n4303), .A1(FPSENCOS_d_ff2_X[7]), .B0(n4401), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1992) );
INVX2TS U5439 ( .A(n4314), .Y(n4312) );
AO22XLTS U5440 ( .A0(n4401), .A1(FPSENCOS_d_ff3_sh_x_out[8]), .B0(n4303),
.B1(FPSENCOS_d_ff2_X[8]), .Y(n1990) );
AO22XLTS U5441 ( .A0(n2243), .A1(FPSENCOS_d_ff3_sh_x_out[9]), .B0(n4303),
.B1(n2271), .Y(n1988) );
OA22X1TS U5442 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n2250), .B0(
FPSENCOS_d_ff2_X[10]), .B1(n5234), .Y(n1987) );
AO22XLTS U5443 ( .A0(n4302), .A1(FPSENCOS_d_ff3_sh_x_out[10]), .B0(n4303),
.B1(FPSENCOS_d_ff2_X[10]), .Y(n1986) );
OA22X1TS U5444 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n2250), .B0(
FPSENCOS_d_ff2_X[12]), .B1(n5234), .Y(n1983) );
AO22XLTS U5445 ( .A0(n4306), .A1(FPSENCOS_d_ff3_sh_x_out[12]), .B0(n4303),
.B1(FPSENCOS_d_ff2_X[12]), .Y(n1982) );
OA22X1TS U5446 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n2251), .B0(
FPSENCOS_d_ff2_X[13]), .B1(n5234), .Y(n1981) );
AO22XLTS U5447 ( .A0(n4303), .A1(FPSENCOS_d_ff2_X[13]), .B0(n4306), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1980) );
OA22X1TS U5448 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n2250), .B0(
FPSENCOS_d_ff2_X[14]), .B1(n5234), .Y(n1979) );
AO22XLTS U5449 ( .A0(n4303), .A1(FPSENCOS_d_ff2_X[14]), .B0(n4332), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1978) );
AO22XLTS U5450 ( .A0(n4303), .A1(FPSENCOS_d_ff2_X[15]), .B0(n4332), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1976) );
OA22X1TS U5451 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n2251), .B0(
FPSENCOS_d_ff2_X[16]), .B1(n5234), .Y(n1975) );
AO22XLTS U5452 ( .A0(n4327), .A1(FPSENCOS_d_ff2_X[16]), .B0(n4306), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1974) );
OA22X1TS U5453 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n2250), .B0(
FPSENCOS_d_ff2_X[17]), .B1(n4331), .Y(n1973) );
AO22XLTS U5454 ( .A0(n4327), .A1(FPSENCOS_d_ff2_X[17]), .B0(n4302), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1972) );
OA22X1TS U5455 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n2251), .B0(
FPSENCOS_d_ff2_X[19]), .B1(n4331), .Y(n1969) );
AO22XLTS U5456 ( .A0(n4303), .A1(FPSENCOS_d_ff2_X[19]), .B0(n4332), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1968) );
OA22X1TS U5457 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n2251), .B0(
FPSENCOS_d_ff2_X[20]), .B1(n4331), .Y(n1967) );
OA22X1TS U5458 ( .A0(FPSENCOS_d_ff_Xn[24]), .A1(n2251), .B0(
FPSENCOS_d_ff2_X[24]), .B1(n4331), .Y(n1960) );
OA22X1TS U5459 ( .A0(FPSENCOS_d_ff_Xn[25]), .A1(n2250), .B0(
FPSENCOS_d_ff2_X[25]), .B1(n5234), .Y(n1959) );
OA22X1TS U5460 ( .A0(FPSENCOS_d_ff_Xn[26]), .A1(n2251), .B0(
FPSENCOS_d_ff2_X[26]), .B1(n4331), .Y(n1958) );
OA22X1TS U5461 ( .A0(FPSENCOS_d_ff_Xn[27]), .A1(n2662), .B0(
FPSENCOS_d_ff2_X[27]), .B1(n4331), .Y(n1957) );
OA22X1TS U5462 ( .A0(FPSENCOS_d_ff2_X[28]), .A1(n4314), .B0(
FPSENCOS_d_ff_Xn[28]), .B1(n2250), .Y(n1956) );
OA22X1TS U5463 ( .A0(FPSENCOS_d_ff_Xn[29]), .A1(n2250), .B0(
FPSENCOS_d_ff2_X[29]), .B1(n4314), .Y(n1955) );
NOR2X1TS U5464 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_490_n1), .Y(n4305) );
AOI21X1TS U5465 ( .A0(intadd_490_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4305),
.Y(n4304) );
OR3X1TS U5466 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_490_n1), .Y(n4308) );
NOR2X1TS U5467 ( .A(FPSENCOS_d_ff2_X[29]), .B(n4308), .Y(n4310) );
AOI21X1TS U5468 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n4308), .B0(n4310), .Y(
n4309) );
XOR2XLTS U5469 ( .A(FPSENCOS_d_ff2_X[30]), .B(n4310), .Y(n4311) );
AO22XLTS U5470 ( .A0(n4402), .A1(n2270), .B0(n4306), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1944) );
AOI22X1TS U5471 ( .A0(n4404), .A1(n4913), .B0(n5085), .B1(n4403), .Y(n1910)
);
AO22XLTS U5472 ( .A0(n4402), .A1(FPSENCOS_d_ff2_Y[0]), .B0(n4302), .B1(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1908) );
BUFX3TS U5473 ( .A(n2249), .Y(n4317) );
BUFX3TS U5474 ( .A(n4317), .Y(n4315) );
AO22XLTS U5475 ( .A0(n4402), .A1(FPSENCOS_d_ff2_Y[1]), .B0(n4302), .B1(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1906) );
AO22XLTS U5476 ( .A0(n4402), .A1(FPSENCOS_d_ff2_Y[2]), .B0(n2385), .B1(
FPSENCOS_d_ff3_sh_y_out[2]), .Y(n1904) );
AO22XLTS U5477 ( .A0(n4402), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n2243), .B1(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1902) );
AO22XLTS U5478 ( .A0(n4402), .A1(FPSENCOS_d_ff2_Y[4]), .B0(n2243), .B1(
FPSENCOS_d_ff3_sh_y_out[4]), .Y(n1900) );
AO22XLTS U5479 ( .A0(n4402), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n4401), .B1(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1898) );
AO22XLTS U5480 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n4401), .B1(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1896) );
AO22XLTS U5481 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n2385), .B1(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1894) );
AO22XLTS U5482 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[8]), .B0(n2243), .B1(
FPSENCOS_d_ff3_sh_y_out[8]), .Y(n1892) );
AO22XLTS U5483 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[9]), .B0(n4306), .B1(
FPSENCOS_d_ff3_sh_y_out[9]), .Y(n1890) );
AO22XLTS U5484 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[10]), .B0(n4332), .B1(
FPSENCOS_d_ff3_sh_y_out[10]), .Y(n1888) );
AO22XLTS U5485 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n4306), .B1(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1886) );
AO22XLTS U5486 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[12]), .B0(n4302), .B1(
FPSENCOS_d_ff3_sh_y_out[12]), .Y(n1884) );
AO22XLTS U5487 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n4332), .B1(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1882) );
AO22XLTS U5488 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n2243), .B1(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1880) );
AO22XLTS U5489 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n4332), .B1(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1878) );
AO22XLTS U5490 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n4401), .B1(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1876) );
AO22XLTS U5491 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n4306), .B1(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1874) );
AO22XLTS U5492 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n4306), .B1(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1872) );
AO22XLTS U5493 ( .A0(n4327), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n4306), .B1(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1870) );
AO22XLTS U5494 ( .A0(n4316), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n4401), .B1(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1866) );
AO22XLTS U5495 ( .A0(n4333), .A1(intadd_489_SUM_0_), .B0(n4332), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1854) );
AO22XLTS U5496 ( .A0(n4327), .A1(intadd_489_SUM_1_), .B0(n4302), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1853) );
AOI21X1TS U5497 ( .A0(intadd_489_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n4324),
.Y(n4321) );
NAND2X1TS U5498 ( .A(n4324), .B(n4323), .Y(n4326) );
AOI21X1TS U5499 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4326), .B0(n4329), .Y(
n4328) );
OAI22X1TS U5500 ( .A0(n4331), .A1(n2230), .B0(n5085), .B1(n2250), .Y(n1847)
);
AO22XLTS U5501 ( .A0(n4333), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n2243), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1846) );
AOI22X1TS U5502 ( .A0(Data_2[3]), .A1(n4361), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n4340), .Y(n4335) );
AOI22X1TS U5503 ( .A0(n4337), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n4336),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n4334) );
NAND2X1TS U5504 ( .A(n4374), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n4353) );
AOI22X1TS U5505 ( .A0(Data_2[5]), .A1(n4380), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n4340), .Y(n4339) );
BUFX3TS U5506 ( .A(n4336), .Y(n4373) );
AOI22X1TS U5507 ( .A0(n4337), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n4373),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n4338) );
NAND2X1TS U5508 ( .A(n4374), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n4348) );
AOI22X1TS U5509 ( .A0(Data_2[7]), .A1(n4380), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n4340), .Y(n4342) );
AOI22X1TS U5510 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n4373),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n4341) );
NAND2X1TS U5511 ( .A(n4374), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n4343) );
AOI22X1TS U5512 ( .A0(Data_2[11]), .A1(n4361), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n4365), .Y(n4345) );
AOI22X1TS U5513 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n4373),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n4344) );
AOI22X1TS U5514 ( .A0(Data_2[13]), .A1(n4380), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n4365), .Y(n4347) );
AOI22X1TS U5515 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n4373),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n4346) );
NAND2X1TS U5516 ( .A(n4374), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n4358) );
AOI22X1TS U5517 ( .A0(Data_2[14]), .A1(n4361), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n4365), .Y(n4350) );
AOI22X1TS U5518 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n4373),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n4349) );
AOI22X1TS U5519 ( .A0(Data_2[15]), .A1(n4361), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n4365), .Y(n4352) );
AOI22X1TS U5520 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n4373),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n4351) );
NAND2X1TS U5521 ( .A(n4374), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n4367) );
AOI22X1TS U5522 ( .A0(Data_2[16]), .A1(n4380), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n4365), .Y(n4355) );
AOI22X1TS U5523 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n4373),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n4354) );
AOI22X1TS U5524 ( .A0(Data_2[17]), .A1(n4380), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n4365), .Y(n4357) );
AOI22X1TS U5525 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n4373),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n4356) );
AOI22X1TS U5526 ( .A0(Data_2[18]), .A1(n4380), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n4365), .Y(n4360) );
AOI22X1TS U5527 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n4373),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n4359) );
AOI22X1TS U5528 ( .A0(Data_2[19]), .A1(n4361), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n4365), .Y(n4364) );
AOI22X1TS U5529 ( .A0(n4362), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n4373),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n4363) );
NAND2X1TS U5530 ( .A(n4374), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n4370) );
AOI22X1TS U5531 ( .A0(Data_2[20]), .A1(n4366), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n4365), .Y(n4369) );
AOI22X1TS U5532 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n4336),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n4368) );
AOI22X1TS U5533 ( .A0(Data_2[22]), .A1(n4377), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n4405), .Y(n4372) );
AOI22X1TS U5534 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n4336),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n4371) );
AOI22X1TS U5535 ( .A0(Data_2[27]), .A1(n4377), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n4405), .Y(n4376) );
AOI22X1TS U5536 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n4373),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n4375) );
NAND2X1TS U5537 ( .A(n4374), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n4381) );
AOI22X1TS U5538 ( .A0(Data_2[28]), .A1(n4377), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n4405), .Y(n4379) );
AOI22X1TS U5539 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n4336),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n4378) );
AOI22X1TS U5540 ( .A0(Data_2[29]), .A1(n4361), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n4405), .Y(n4383) );
AOI22X1TS U5541 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n4336),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n4382) );
AOI22X1TS U5542 ( .A0(FPSENCOS_d_ff3_sh_x_out[30]), .A1(n4336), .B0(
FPADDSUB_intDY_EWSW[30]), .B1(n4405), .Y(n4385) );
AOI22X1TS U5543 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[30]), .B0(n4377),
.B1(Data_2[30]), .Y(n4384) );
NAND2X1TS U5544 ( .A(n4385), .B(n4384), .Y(n1815) );
OAI22X1TS U5545 ( .A0(n4388), .A1(n4387), .B0(n4386), .B1(n4926), .Y(n1814)
);
AOI22X1TS U5546 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n4390), .B0(n4389),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n4393) );
AOI22X1TS U5547 ( .A0(n2257), .A1(n4391), .B0(n2255), .B1(n2220), .Y(n4392)
);
AO22XLTS U5548 ( .A0(n4398), .A1(result_add_subt[23]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[23]), .Y(n1787) );
AO22XLTS U5549 ( .A0(n4410), .A1(result_add_subt[23]), .B0(n4395), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(n1786) );
AO22XLTS U5550 ( .A0(n4398), .A1(result_add_subt[24]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[24]), .Y(n1784) );
AO22XLTS U5551 ( .A0(n4398), .A1(result_add_subt[25]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[25]), .Y(n1781) );
AO22XLTS U5552 ( .A0(n4398), .A1(result_add_subt[26]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[26]), .Y(n1778) );
AO22XLTS U5553 ( .A0(n4398), .A1(result_add_subt[27]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[27]), .Y(n1775) );
AO22XLTS U5554 ( .A0(n4398), .A1(result_add_subt[28]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[28]), .Y(n1772) );
AO22XLTS U5555 ( .A0(n4398), .A1(result_add_subt[29]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[29]), .Y(n1769) );
AO22XLTS U5556 ( .A0(n4410), .A1(result_add_subt[29]), .B0(n4396), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(n1768) );
AO22XLTS U5557 ( .A0(n4402), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4332), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1734) );
AO22XLTS U5558 ( .A0(n4398), .A1(result_add_subt[30]), .B0(n4403), .B1(
FPSENCOS_d_ff_Yn[30]), .Y(n1732) );
AO22XLTS U5559 ( .A0(n4410), .A1(result_add_subt[30]), .B0(n4396), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(n1731) );
AOI22X1TS U5560 ( .A0(FPSENCOS_d_ff3_sh_x_out[31]), .A1(n4336), .B0(
FPADDSUB_intDY_EWSW[31]), .B1(n4405), .Y(n4408) );
AOI22X1TS U5561 ( .A0(n2982), .A1(FPSENCOS_d_ff3_sh_y_out[31]), .B0(n4366),
.B1(Data_2[31]), .Y(n4407) );
NAND2X1TS U5562 ( .A(n4408), .B(n4407), .Y(n1730) );
AOI22X1TS U5563 ( .A0(n4300), .A1(n4913), .B0(n5097), .B1(n4409), .Y(n1729)
);
AO22XLTS U5564 ( .A0(n3674), .A1(Data_2[31]), .B0(n4411), .B1(
FPMULT_Op_MY[31]), .Y(n1696) );
AO22XLTS U5565 ( .A0(n3674), .A1(Data_1[31]), .B0(n4411), .B1(
FPMULT_Op_MX[31]), .Y(n1658) );
NOR4X1TS U5566 ( .A(FPMULT_Op_MY[27]), .B(FPMULT_Op_MY[26]), .C(
FPMULT_Op_MY[25]), .D(FPMULT_Op_MY[24]), .Y(n4415) );
NOR4X1TS U5567 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[30]), .C(
FPMULT_Op_MY[29]), .D(FPMULT_Op_MY[28]), .Y(n4412) );
NAND4XLTS U5568 ( .A(n4415), .B(n4414), .C(n4413), .D(n4412), .Y(n4431) );
NOR4X1TS U5569 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[12]), .C(n2241), .D(
FPMULT_Op_MY[6]), .Y(n4419) );
NAND4XLTS U5570 ( .A(n4419), .B(n4418), .C(n4417), .D(n4416), .Y(n4430) );
NOR4X1TS U5571 ( .A(FPMULT_Op_MX[27]), .B(n2259), .C(n2260), .D(
FPMULT_Op_MX[23]), .Y(n4422) );
NAND4XLTS U5572 ( .A(n4423), .B(n4422), .C(n4421), .D(n4420), .Y(n4429) );
NOR4X1TS U5573 ( .A(n2237), .B(n2293), .C(FPMULT_Op_MX[0]), .D(n2287), .Y(
n4424) );
NAND4XLTS U5574 ( .A(n4427), .B(n4426), .C(n4425), .D(n4424), .Y(n4428) );
OA22X1TS U5575 ( .A0(n4431), .A1(n4430), .B0(n4429), .B1(n4428), .Y(n4433)
);
AOI22X1TS U5576 ( .A0(n4434), .A1(n4433), .B0(n5132), .B1(n4432), .Y(n1626)
);
AOI32X1TS U5577 ( .A0(n4437), .A1(n2592), .A2(n4436), .B0(n5096), .B1(n4199),
.Y(n1625) );
AOI2BB2XLTS U5578 ( .B0(n4478), .B1(FPMULT_Sgf_normalized_result[0]), .A0N(
FPMULT_Add_result[0]), .A1N(n4478), .Y(n1624) );
NOR2XLTS U5579 ( .A(n2286), .B(FPMULT_Sgf_normalized_result[0]), .Y(n4438)
);
AOI21X1TS U5580 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n2286), .B0(
n4438), .Y(n4439) );
AOI2BB2XLTS U5581 ( .B0(n4488), .B1(n4439), .A0N(FPMULT_Add_result[1]),
.A1N(n4478), .Y(n1623) );
OR3X1TS U5582 ( .A(n2280), .B(n2286), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n4441) );
OAI21XLTS U5583 ( .A0(n2286), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
n2280), .Y(n4440) );
AOI32X1TS U5584 ( .A0(n4441), .A1(n4488), .A2(n4440), .B0(n5095), .B1(n4486),
.Y(n1622) );
OAI2BB1X1TS U5585 ( .A0N(FPMULT_Add_result[3]), .A1N(n4483), .B0(n4442), .Y(
n1621) );
OAI21XLTS U5586 ( .A0(n4443), .A1(n4956), .B0(n4445), .Y(n4444) );
OAI2BB1X1TS U5587 ( .A0N(FPMULT_Add_result[5]), .A1N(n4483), .B0(n4446), .Y(
n1619) );
NOR2X2TS U5588 ( .A(n4961), .B(n4447), .Y(n4449) );
AOI21X1TS U5589 ( .A0(n4961), .A1(n4447), .B0(n4449), .Y(n4448) );
OAI2BB1X1TS U5590 ( .A0N(FPMULT_Add_result[7]), .A1N(n4483), .B0(n4450), .Y(
n1617) );
NOR2X2TS U5591 ( .A(n4964), .B(n4451), .Y(n4453) );
AOI21X1TS U5592 ( .A0(n4964), .A1(n4451), .B0(n4453), .Y(n4452) );
OAI2BB1X1TS U5593 ( .A0N(FPMULT_Add_result[9]), .A1N(n4486), .B0(n4454), .Y(
n1615) );
NOR2X2TS U5594 ( .A(n4968), .B(n4455), .Y(n4457) );
AOI21X1TS U5595 ( .A0(n4968), .A1(n4455), .B0(n4457), .Y(n4456) );
OAI2BB1X1TS U5596 ( .A0N(FPMULT_Add_result[11]), .A1N(n4486), .B0(n4458),
.Y(n1613) );
NOR2X2TS U5597 ( .A(n4981), .B(n4459), .Y(n4461) );
AOI21X1TS U5598 ( .A0(n4981), .A1(n4459), .B0(n4461), .Y(n4460) );
OAI2BB1X1TS U5599 ( .A0N(FPMULT_Add_result[13]), .A1N(n4486), .B0(n4462),
.Y(n1611) );
NOR2X2TS U5600 ( .A(n4999), .B(n4463), .Y(n4465) );
AOI21X1TS U5601 ( .A0(n4999), .A1(n4463), .B0(n4465), .Y(n4464) );
OAI2BB1X1TS U5602 ( .A0N(FPMULT_Add_result[15]), .A1N(n4483), .B0(n4466),
.Y(n1609) );
NOR2X2TS U5603 ( .A(n5008), .B(n4467), .Y(n4469) );
AOI21X1TS U5604 ( .A0(n5008), .A1(n4467), .B0(n4469), .Y(n4468) );
OAI2BB1X1TS U5605 ( .A0N(FPMULT_Add_result[17]), .A1N(n4475), .B0(n4470),
.Y(n1607) );
NOR2X2TS U5606 ( .A(n5058), .B(n4471), .Y(n4473) );
AOI21X1TS U5607 ( .A0(n5058), .A1(n4471), .B0(n4473), .Y(n4472) );
OAI2BB1X1TS U5608 ( .A0N(FPMULT_Add_result[19]), .A1N(n4475), .B0(n4474),
.Y(n1605) );
NOR2X2TS U5609 ( .A(n5072), .B(n4476), .Y(n4479) );
AOI21X1TS U5610 ( .A0(n5072), .A1(n4476), .B0(n4479), .Y(n4477) );
OAI2BB1X1TS U5611 ( .A0N(FPMULT_Add_result[21]), .A1N(n4483), .B0(n4480),
.Y(n1603) );
NOR2X2TS U5612 ( .A(n5078), .B(n4481), .Y(n4484) );
AOI211X1TS U5613 ( .A0(n5078), .A1(n4481), .B0(n4484), .C0(n4486), .Y(n4482)
);
AOI21X1TS U5614 ( .A0(n4484), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
n4486), .Y(n4487) );
OAI2BB1X1TS U5615 ( .A0N(FPMULT_Add_result[23]), .A1N(n4486), .B0(n4485),
.Y(n1601) );
BUFX3TS U5616 ( .A(n4489), .Y(n4496) );
AO22XLTS U5617 ( .A0(n2286), .A1(n4490), .B0(mult_result[1]), .B1(n4496),
.Y(n1514) );
AO22XLTS U5618 ( .A0(n2280), .A1(n4490), .B0(mult_result[2]), .B1(n4496),
.Y(n1513) );
AO22XLTS U5619 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4490), .B0(
mult_result[3]), .B1(n4496), .Y(n1512) );
AO22XLTS U5620 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n4490), .B0(
mult_result[4]), .B1(n4496), .Y(n1511) );
AO22XLTS U5621 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4490), .B0(
mult_result[5]), .B1(n4496), .Y(n1510) );
AO22XLTS U5622 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n4490), .B0(
mult_result[6]), .B1(n4496), .Y(n1509) );
AO22XLTS U5623 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4490), .B0(
mult_result[7]), .B1(n4496), .Y(n1508) );
AO22XLTS U5624 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n4490), .B0(
mult_result[8]), .B1(n4496), .Y(n1507) );
AO22XLTS U5625 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4490), .B0(
mult_result[9]), .B1(n4496), .Y(n1506) );
AO22XLTS U5626 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n4490), .B0(
mult_result[10]), .B1(n4496), .Y(n1505) );
AO22XLTS U5627 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4490), .B0(
mult_result[11]), .B1(n4496), .Y(n1504) );
AO22XLTS U5628 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n4490), .B0(
mult_result[12]), .B1(n4489), .Y(n1503) );
INVX2TS U5629 ( .A(n2303), .Y(n4491) );
AO22XLTS U5630 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4491), .B0(
mult_result[13]), .B1(n4489), .Y(n1502) );
AO22XLTS U5631 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n4491), .B0(
mult_result[14]), .B1(n4489), .Y(n1501) );
AO22XLTS U5632 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4491), .B0(
mult_result[15]), .B1(n4489), .Y(n1500) );
AO22XLTS U5633 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n4491), .B0(
mult_result[16]), .B1(n4489), .Y(n1499) );
AO22XLTS U5634 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4491), .B0(
mult_result[17]), .B1(n4489), .Y(n1498) );
AO22XLTS U5635 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n4491), .B0(
mult_result[18]), .B1(n4489), .Y(n1497) );
AO22XLTS U5636 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4491), .B0(
mult_result[19]), .B1(n4489), .Y(n1496) );
AO22XLTS U5637 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n4491), .B0(
mult_result[20]), .B1(n4489), .Y(n1495) );
AO22XLTS U5638 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n4491), .B0(
mult_result[21]), .B1(n4489), .Y(n1494) );
AO22XLTS U5639 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n4491), .B0(
mult_result[22]), .B1(n4489), .Y(n1493) );
OA22X1TS U5640 ( .A0(FPMULT_exp_oper_result[0]), .A1(n2303), .B0(n4492),
.B1(mult_result[23]), .Y(n1492) );
OA22X1TS U5641 ( .A0(FPMULT_exp_oper_result[1]), .A1(n2303), .B0(n4492),
.B1(mult_result[24]), .Y(n1491) );
OA22X1TS U5642 ( .A0(FPMULT_exp_oper_result[2]), .A1(n2303), .B0(n4492),
.B1(mult_result[25]), .Y(n1490) );
OA22X1TS U5643 ( .A0(FPMULT_exp_oper_result[3]), .A1(n2303), .B0(n4492),
.B1(mult_result[26]), .Y(n1489) );
OA22X1TS U5644 ( .A0(FPMULT_exp_oper_result[4]), .A1(n2303), .B0(n4492),
.B1(mult_result[27]), .Y(n1488) );
OA22X1TS U5645 ( .A0(FPMULT_exp_oper_result[5]), .A1(n2303), .B0(n4492),
.B1(mult_result[28]), .Y(n1487) );
OA22X1TS U5646 ( .A0(FPMULT_exp_oper_result[6]), .A1(n2303), .B0(n4492),
.B1(mult_result[29]), .Y(n1486) );
OA22X1TS U5647 ( .A0(FPMULT_exp_oper_result[7]), .A1(n2303), .B0(n4492),
.B1(mult_result[30]), .Y(n1485) );
OAI2BB1X1TS U5648 ( .A0N(mult_result[31]), .A1N(n4496), .B0(n4495), .Y(n1483) );
NAND2X1TS U5649 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n4929), .Y(n4499) );
NAND2X1TS U5650 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n5073), .Y(n4507) );
INVX2TS U5651 ( .A(n4507), .Y(n4505) );
NOR2X1TS U5652 ( .A(n4879), .B(FPADDSUB_DMP_EXP_EWSW[24]), .Y(n4503) );
OAI22X1TS U5653 ( .A0(n4505), .A1(n4503), .B0(FPADDSUB_DmP_EXP_EWSW[24]),
.B1(n4880), .Y(n4501) );
AOI22X1TS U5654 ( .A0(FPADDSUB_DMP_EXP_EWSW[25]), .A1(n4937), .B0(n4499),
.B1(n4501), .Y(n4509) );
NOR2X1TS U5655 ( .A(n4934), .B(FPADDSUB_DMP_EXP_EWSW[26]), .Y(n4510) );
AOI21X1TS U5656 ( .A0(FPADDSUB_DMP_EXP_EWSW[26]), .A1(n4934), .B0(n4510),
.Y(n4497) );
XNOR2X1TS U5657 ( .A(n4509), .B(n4497), .Y(n4498) );
AO22XLTS U5658 ( .A0(n2229), .A1(n4498), .B0(n4634), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1480) );
OAI21XLTS U5659 ( .A0(FPADDSUB_DmP_EXP_EWSW[25]), .A1(n4929), .B0(n4499),
.Y(n4500) );
XNOR2X1TS U5660 ( .A(n4501), .B(n4500), .Y(n4502) );
AO22XLTS U5661 ( .A0(n2229), .A1(n4502), .B0(n4547), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1479) );
AOI21X1TS U5662 ( .A0(FPADDSUB_DMP_EXP_EWSW[24]), .A1(n4879), .B0(n4503),
.Y(n4504) );
XNOR2X1TS U5663 ( .A(n4505), .B(n4504), .Y(n4506) );
AO22XLTS U5664 ( .A0(n2229), .A1(n4506), .B0(n4547), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n1478) );
OAI21XLTS U5665 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n5073), .B0(n4507),
.Y(n4508) );
AO22XLTS U5666 ( .A0(n2229), .A1(n4508), .B0(n4547), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1477) );
OAI22X1TS U5667 ( .A0(n4510), .A1(n4509), .B0(FPADDSUB_DmP_EXP_EWSW[26]),
.B1(n4936), .Y(n4512) );
XNOR2X1TS U5668 ( .A(FPADDSUB_DmP_EXP_EWSW[27]), .B(
FPADDSUB_DMP_EXP_EWSW[27]), .Y(n4511) );
XOR2XLTS U5669 ( .A(n4512), .B(n4511), .Y(n4513) );
AO22XLTS U5670 ( .A0(n4798), .A1(n4513), .B0(n4547), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1476) );
OAI222X1TS U5671 ( .A0(n4514), .A1(n4935), .B0(n4880), .B1(n5156), .C0(n4867), .C1(n4515), .Y(n1466) );
OAI222X1TS U5672 ( .A0(n4514), .A1(n5080), .B0(n4929), .B1(n5156), .C0(n4877), .C1(n4515), .Y(n1465) );
OAI222X1TS U5673 ( .A0(n4514), .A1(n5079), .B0(n4936), .B1(n5156), .C0(n4876), .C1(n4515), .Y(n1464) );
AO22XLTS U5674 ( .A0(n4818), .A1(FPADDSUB_DMP_EXP_EWSW[23]), .B0(n5083),
.B1(FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1459) );
AO22XLTS U5675 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n2252),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1458) );
BUFX3TS U5676 ( .A(n4839), .Y(n4841) );
AO22XLTS U5677 ( .A0(n4820), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n4841),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1457) );
INVX2TS U5678 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n4713) );
AO22XLTS U5679 ( .A0(n4782), .A1(FPADDSUB_DMP_SFG[23]), .B0(n4790), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1456) );
AO22XLTS U5680 ( .A0(n4818), .A1(FPADDSUB_DMP_EXP_EWSW[24]), .B0(n5083),
.B1(FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1454) );
AO22XLTS U5681 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n2252),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1453) );
AO22XLTS U5682 ( .A0(n4820), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n4841),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1452) );
AO22XLTS U5683 ( .A0(n4782), .A1(FPADDSUB_DMP_SFG[24]), .B0(n4790), .B1(
FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1451) );
AO22XLTS U5684 ( .A0(n4569), .A1(FPADDSUB_DMP_EXP_EWSW[25]), .B0(n4547),
.B1(FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1449) );
AO22XLTS U5685 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n2252),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1448) );
AO22XLTS U5686 ( .A0(n4820), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n4841),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1447) );
AO22XLTS U5687 ( .A0(n4782), .A1(FPADDSUB_DMP_SFG[25]), .B0(n4790), .B1(
FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1446) );
AO22XLTS U5688 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[26]), .B0(n4547),
.B1(FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1444) );
AO22XLTS U5689 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n2252),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1443) );
AO22XLTS U5690 ( .A0(n4820), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n4841),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1442) );
AO22XLTS U5691 ( .A0(n4782), .A1(FPADDSUB_DMP_SFG[26]), .B0(n4790), .B1(
FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1441) );
AO22XLTS U5692 ( .A0(n4798), .A1(FPADDSUB_DMP_EXP_EWSW[27]), .B0(n4547),
.B1(FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1439) );
AO22XLTS U5693 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n2274),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1438) );
AO22XLTS U5694 ( .A0(n4820), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n4841),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1437) );
BUFX3TS U5695 ( .A(n4713), .Y(n4790) );
AO22XLTS U5696 ( .A0(n4782), .A1(FPADDSUB_DMP_SFG[27]), .B0(n4790), .B1(
FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1436) );
AO22XLTS U5697 ( .A0(n4569), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n4547),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1434) );
AO22XLTS U5698 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n2253),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1433) );
AO22XLTS U5699 ( .A0(n4820), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n4841),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1432) );
AO22XLTS U5700 ( .A0(n4782), .A1(FPADDSUB_DMP_SFG[28]), .B0(n4790), .B1(
FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1431) );
AO22XLTS U5701 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n4547),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1429) );
AO22XLTS U5702 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n2274),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1428) );
AO22XLTS U5703 ( .A0(n4820), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n4841),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1427) );
AO22XLTS U5704 ( .A0(n4782), .A1(FPADDSUB_DMP_SFG[29]), .B0(n4790), .B1(
FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1426) );
BUFX3TS U5705 ( .A(n4634), .Y(n4813) );
AO22XLTS U5706 ( .A0(n4569), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n4547),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1424) );
AO22XLTS U5707 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n2252),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1423) );
AO22XLTS U5708 ( .A0(n4820), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n4841),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1422) );
AO22XLTS U5709 ( .A0(n4782), .A1(FPADDSUB_DMP_SFG[30]), .B0(n4790), .B1(
FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1421) );
OAI222X1TS U5710 ( .A0(n4515), .A1(n4935), .B0(n4879), .B1(n5156), .C0(n4867), .C1(n4514), .Y(n1418) );
OAI222X1TS U5711 ( .A0(n4515), .A1(n5080), .B0(n4937), .B1(n5156), .C0(n4877), .C1(n4514), .Y(n1417) );
OAI222X1TS U5712 ( .A0(n4515), .A1(n5079), .B0(n4934), .B1(n5156), .C0(n4876), .C1(n4514), .Y(n1416) );
NOR2X1TS U5713 ( .A(FPADDSUB_DmP_mant_SFG_SWR[24]), .B(n5076), .Y(n4783) );
NAND2X1TS U5714 ( .A(FPADDSUB_DmP_mant_SFG_SWR[23]), .B(n5063), .Y(n4778) );
NOR2X1TS U5715 ( .A(FPADDSUB_DMP_SFG[20]), .B(n5062), .Y(n4768) );
NAND2X1TS U5716 ( .A(FPADDSUB_DmP_mant_SFG_SWR[21]), .B(n5056), .Y(n4764) );
NOR2X1TS U5717 ( .A(FPADDSUB_DMP_SFG[18]), .B(n5047), .Y(n4755) );
NAND2X1TS U5718 ( .A(FPADDSUB_DmP_mant_SFG_SWR[19]), .B(n5011), .Y(n4750) );
NOR2X1TS U5719 ( .A(FPADDSUB_DMP_SFG[16]), .B(n5010), .Y(n4739) );
NAND2X1TS U5720 ( .A(FPADDSUB_DmP_mant_SFG_SWR[17]), .B(n5004), .Y(n4735) );
NOR2X1TS U5721 ( .A(FPADDSUB_DMP_SFG[14]), .B(n5005), .Y(n4727) );
NAND2X1TS U5722 ( .A(FPADDSUB_DmP_mant_SFG_SWR[15]), .B(n4984), .Y(n4723) );
NOR2X1TS U5723 ( .A(FPADDSUB_DMP_SFG[12]), .B(n4985), .Y(n4715) );
NAND2X1TS U5724 ( .A(FPADDSUB_DmP_mant_SFG_SWR[13]), .B(n4975), .Y(n4710) );
NOR2X1TS U5725 ( .A(FPADDSUB_DMP_SFG[10]), .B(n4976), .Y(n4702) );
NAND2X1TS U5726 ( .A(FPADDSUB_DmP_mant_SFG_SWR[11]), .B(n4972), .Y(n4698) );
NOR2X1TS U5727 ( .A(FPADDSUB_DMP_SFG[8]), .B(n4967), .Y(n4689) );
NAND2X1TS U5728 ( .A(FPADDSUB_DmP_mant_SFG_SWR[9]), .B(n4893), .Y(n4685) );
NOR2X1TS U5729 ( .A(FPADDSUB_DMP_SFG[6]), .B(n4960), .Y(n4677) );
NAND2X1TS U5730 ( .A(FPADDSUB_DmP_mant_SFG_SWR[7]), .B(n4891), .Y(n4673) );
NOR2X1TS U5731 ( .A(FPADDSUB_DMP_SFG[4]), .B(n4954), .Y(n4665) );
NAND2X1TS U5732 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(n4883), .Y(n4661) );
NOR2X1TS U5733 ( .A(FPADDSUB_DMP_SFG[2]), .B(n4940), .Y(n4653) );
NAND2X1TS U5734 ( .A(FPADDSUB_DmP_mant_SFG_SWR[3]), .B(n2208), .Y(n4647) );
OAI2BB2X1TS U5735 ( .B0(n4653), .B1(n4655), .A0N(n4940), .A1N(
FPADDSUB_DMP_SFG[2]), .Y(n4660) );
OAI2BB2X1TS U5736 ( .B0(n4665), .B1(n4667), .A0N(n4954), .A1N(
FPADDSUB_DMP_SFG[4]), .Y(n4672) );
OAI2BB2X1TS U5737 ( .B0(n4677), .B1(n4679), .A0N(n4960), .A1N(
FPADDSUB_DMP_SFG[6]), .Y(n4684) );
OAI2BB2X1TS U5738 ( .B0(n4689), .B1(n4691), .A0N(n4967), .A1N(
FPADDSUB_DMP_SFG[8]), .Y(n4697) );
OAI2BB2X1TS U5739 ( .B0(n4702), .B1(n4704), .A0N(n4976), .A1N(
FPADDSUB_DMP_SFG[10]), .Y(n4709) );
OAI2BB2X1TS U5740 ( .B0(n4715), .B1(n4717), .A0N(n4985), .A1N(
FPADDSUB_DMP_SFG[12]), .Y(n4722) );
AOI22X1TS U5741 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n2217), .B0(n4723), .B1(
n4722), .Y(n4729) );
OAI2BB2X1TS U5742 ( .B0(n4727), .B1(n4729), .A0N(n5005), .A1N(
FPADDSUB_DMP_SFG[14]), .Y(n4734) );
OAI2BB2X1TS U5743 ( .B0(n4755), .B1(n4757), .A0N(n5047), .A1N(
FPADDSUB_DMP_SFG[18]), .Y(n4763) );
AOI21X1TS U5744 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n5076), .B0(n4786),
.Y(n4517) );
AOI222X4TS U5745 ( .A0(n4939), .A1(n2208), .B0(n4939), .B1(n4648), .C0(n2208), .C1(n4648), .Y(n4654) );
AOI222X4TS U5746 ( .A0(n4659), .A1(n4953), .B0(n4659), .B1(n4883), .C0(n4953), .C1(n4883), .Y(n4666) );
AOI222X4TS U5747 ( .A0(n4671), .A1(n4959), .B0(n4671), .B1(n4891), .C0(n4959), .C1(n4891), .Y(n4678) );
AOI222X4TS U5748 ( .A0(n4683), .A1(n4966), .B0(n4683), .B1(n4893), .C0(n4966), .C1(n4893), .Y(n4690) );
AOI222X4TS U5749 ( .A0(n4696), .A1(n4896), .B0(n4696), .B1(n4972), .C0(n4896), .C1(n4972), .Y(n4703) );
AOI222X4TS U5750 ( .A0(n4708), .A1(n4898), .B0(n4708), .B1(n4975), .C0(n4898), .C1(n4975), .Y(n4716) );
AOI222X4TS U5751 ( .A0(n4721), .A1(n2217), .B0(n4721), .B1(n4984), .C0(n2217), .C1(n4984), .Y(n4728) );
AOI222X4TS U5752 ( .A0(n4733), .A1(n4910), .B0(n4733), .B1(n5004), .C0(n4910), .C1(n5004), .Y(n4740) );
AOI222X4TS U5753 ( .A0(n4748), .A1(n4912), .B0(n4748), .B1(n5011), .C0(n4912), .C1(n5011), .Y(n4756) );
AOI222X4TS U5754 ( .A0(n4762), .A1(n4915), .B0(n4762), .B1(n5056), .C0(n4915), .C1(n5056), .Y(n4769) );
AOI222X4TS U5755 ( .A0(n4775), .A1(n4925), .B0(n4775), .B1(n5063), .C0(n4925), .C1(n5063), .Y(n4785) );
XOR2X1TS U5756 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .B(n4518), .Y(n4519) );
AOI22X1TS U5757 ( .A0(n4753), .A1(n4519), .B0(n2204), .B1(n4713), .Y(n1412)
);
NAND2BX2TS U5758 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n4580) );
NAND2X1TS U5759 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n5014), .Y(n4579)
);
OAI22X1TS U5760 ( .A0(n5070), .A1(n4580), .B0(n4926), .B1(n4579), .Y(n4521)
);
NAND3X1TS U5761 ( .A(n2196), .B(FPADDSUB_shift_value_SHT2_EWR[2]), .C(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4591) );
AOI22X1TS U5762 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n4522), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n2279), .Y(n4525) );
NOR2XLTS U5763 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n4579), .Y(n4523)
);
AOI22X1TS U5764 ( .A0(n2282), .A1(n4821), .B0(FPADDSUB_Data_array_SWR[1]),
.B1(n2236), .Y(n4524) );
OAI211X1TS U5765 ( .A0(n4560), .A1(n2196), .B0(n4525), .C0(n4524), .Y(n4828)
);
NAND2X1TS U5766 ( .A(n4829), .B(n4588), .Y(n4864) );
INVX2TS U5767 ( .A(n4864), .Y(n4585) );
NOR2X2TS U5768 ( .A(n4583), .B(n5012), .Y(n4576) );
AOI211X1TS U5769 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4828), .B0(n4585),
.C0(n4527), .Y(n4859) );
OAI22X1TS U5770 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5015), .B0(n4859),
.B1(n2290), .Y(n1410) );
AO22XLTS U5771 ( .A0(n4569), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n4547),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1408) );
INVX4TS U5772 ( .A(n5090), .Y(n4595) );
AOI22X1TS U5773 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n4522), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n2278), .Y(n4533) );
AOI22X1TS U5774 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n4821), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n2235), .Y(n4532) );
OAI211X1TS U5775 ( .A0(n4827), .A1(n2196), .B0(n4533), .C0(n4532), .Y(n4562)
);
AOI211X1TS U5776 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4562), .B0(n4585),
.C0(n4534), .Y(n4850) );
OAI22X1TS U5777 ( .A0(n4595), .A1(n5016), .B0(n4850), .B1(n4530), .Y(n1407)
);
AO22XLTS U5778 ( .A0(n4569), .A1(FPADDSUB_DmP_EXP_EWSW[15]), .B0(n4547),
.B1(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1405) );
OAI21X1TS U5779 ( .A0(n4926), .A1(n4580), .B0(n4548), .Y(n4535) );
AOI22X1TS U5780 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n4821), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n2235), .Y(n4537) );
AOI22X1TS U5781 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n4522), .B0(n2282),
.B1(n2278), .Y(n4536) );
OAI211X1TS U5782 ( .A0(n4793), .A1(n2196), .B0(n4537), .C0(n4536), .Y(n4747)
);
OAI21X1TS U5783 ( .A0(n4927), .A1(n4580), .B0(n4548), .Y(n4538) );
AOI211X1TS U5784 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4747), .B0(n4585),
.C0(n4539), .Y(n4854) );
OAI22X1TS U5785 ( .A0(n4595), .A1(n5017), .B0(n4854), .B1(n2290), .Y(n1404)
);
AO22XLTS U5786 ( .A0(n4569), .A1(FPADDSUB_DmP_EXP_EWSW[18]), .B0(n4547),
.B1(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1402) );
OAI21X1TS U5787 ( .A0(n5064), .A1(n4580), .B0(n4548), .Y(n4540) );
AOI22X1TS U5788 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n4821), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n2235), .Y(n4542) );
AOI22X1TS U5789 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n4522), .B0(
FPADDSUB_Data_array_SWR[6]), .B1(n2278), .Y(n4541) );
OAI211X1TS U5790 ( .A0(n4807), .A1(n2196), .B0(n4542), .C0(n4541), .Y(n4801)
);
AOI211X1TS U5791 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4801), .B0(n4585),
.C0(n4543), .Y(n4858) );
OAI22X1TS U5792 ( .A0(n4595), .A1(n5018), .B0(n4858), .B1(n2290), .Y(n1401)
);
AO22XLTS U5793 ( .A0(n4569), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n4547),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1399) );
AOI22X1TS U5794 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n4821), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n2235), .Y(n4545) );
AOI22X1TS U5795 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n4522), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n2278), .Y(n4544) );
OAI211X1TS U5796 ( .A0(n4745), .A1(n2196), .B0(n4545), .C0(n4544), .Y(n4795)
);
AOI211X1TS U5797 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4795), .B0(n4585),
.C0(n4546), .Y(n4855) );
OAI22X1TS U5798 ( .A0(n4595), .A1(n5019), .B0(n4855), .B1(n2290), .Y(n1398)
);
AO22XLTS U5799 ( .A0(n4569), .A1(FPADDSUB_DmP_EXP_EWSW[19]), .B0(n4547),
.B1(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1396) );
AOI22X1TS U5800 ( .A0(n2281), .A1(n4821), .B0(FPADDSUB_Data_array_SWR[3]),
.B1(n2236), .Y(n4551) );
AOI22X1TS U5801 ( .A0(n2285), .A1(n4522), .B0(FPADDSUB_Data_array_SWR[7]),
.B1(n2278), .Y(n4550) );
OAI211X1TS U5802 ( .A0(n4557), .A1(n2196), .B0(n4551), .C0(n4550), .Y(n4804)
);
AOI211X1TS U5803 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4804), .B0(n4585),
.C0(n4552), .Y(n4856) );
OAI22X1TS U5804 ( .A0(n4595), .A1(n5020), .B0(n4856), .B1(n2290), .Y(n1395)
);
AO22XLTS U5805 ( .A0(n4569), .A1(FPADDSUB_DmP_EXP_EWSW[20]), .B0(n4634),
.B1(FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1393) );
AOI22X1TS U5806 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n4522), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n2279), .Y(n4554) );
AOI22X1TS U5807 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n4821), .B0(
FPADDSUB_Data_array_SWR[6]), .B1(n2235), .Y(n4553) );
OAI211X1TS U5808 ( .A0(n4802), .A1(n2196), .B0(n4554), .C0(n4553), .Y(n4559)
);
AOI211X1TS U5809 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4559), .B0(n4585),
.C0(n4555), .Y(n4853) );
OAI22X1TS U5810 ( .A0(n4595), .A1(n5021), .B0(n4853), .B1(n2290), .Y(n1392)
);
AO22XLTS U5811 ( .A0(n4569), .A1(FPADDSUB_DmP_EXP_EWSW[17]), .B0(n4634),
.B1(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1390) );
NAND2X1TS U5812 ( .A(n2248), .B(n4588), .Y(n4830) );
INVX2TS U5813 ( .A(n4830), .Y(n4808) );
AOI211X1TS U5814 ( .A0(n4829), .A1(n4559), .B0(n4558), .C0(n4808), .Y(n4836)
);
OAI22X1TS U5815 ( .A0(n4595), .A1(n5022), .B0(n4836), .B1(n4530), .Y(n1389)
);
AO22XLTS U5816 ( .A0(n4569), .A1(FPADDSUB_DmP_EXP_EWSW[4]), .B0(n4634), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1387) );
AOI211X1TS U5817 ( .A0(n4829), .A1(n4562), .B0(n4561), .C0(n4808), .Y(n4838)
);
OAI22X1TS U5818 ( .A0(n4595), .A1(n5023), .B0(n4838), .B1(n4530), .Y(n1386)
);
AO22XLTS U5819 ( .A0(n4569), .A1(FPADDSUB_DmP_EXP_EWSW[6]), .B0(n4634), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1384) );
AOI21X1TS U5820 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2279), .B0(n4588),
.Y(n4564) );
AOI22X1TS U5821 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n4821), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n2236), .Y(n4563) );
OAI211X1TS U5822 ( .A0(n5064), .A1(n4591), .B0(n4564), .C0(n4563), .Y(n4570)
);
INVX2TS U5823 ( .A(n4821), .Y(n4594) );
NOR2X1TS U5824 ( .A(n4588), .B(n4582), .Y(n4593) );
AOI22X1TS U5825 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2279), .B0(n2285),
.B1(n2236), .Y(n4565) );
OAI211X1TS U5826 ( .A0(n5065), .A1(n4594), .B0(n4593), .C0(n4565), .Y(n4571)
);
AOI22X1TS U5827 ( .A0(n2248), .A1(n4570), .B0(n4571), .B1(n2247), .Y(n4848)
);
OAI22X1TS U5828 ( .A0(n4595), .A1(n5024), .B0(n4848), .B1(n2290), .Y(n1383)
);
AO22XLTS U5829 ( .A0(n4569), .A1(FPADDSUB_DmP_EXP_EWSW[13]), .B0(n4634),
.B1(FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1381) );
AOI22X1TS U5830 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n4522), .B0(n2281),
.B1(n2279), .Y(n4567) );
AOI22X1TS U5831 ( .A0(n2285), .A1(n4821), .B0(FPADDSUB_Data_array_SWR[7]),
.B1(n2235), .Y(n4566) );
OAI211X1TS U5832 ( .A0(n4799), .A1(n2196), .B0(n4567), .C0(n4566), .Y(n4810)
);
AOI211X1TS U5833 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4810), .B0(n4585),
.C0(n4568), .Y(n4852) );
OAI22X1TS U5834 ( .A0(n4595), .A1(n5025), .B0(n4852), .B1(n2290), .Y(n1380)
);
AO22XLTS U5835 ( .A0(n4569), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n4634),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1378) );
AOI22X1TS U5836 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4571), .B0(n4570),
.B1(n2247), .Y(n4842) );
OAI22X1TS U5837 ( .A0(n4595), .A1(n5026), .B0(n4842), .B1(n2290), .Y(n1377)
);
AO22XLTS U5838 ( .A0(n4798), .A1(FPADDSUB_DmP_EXP_EWSW[8]), .B0(n4634), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1375) );
AOI22X1TS U5839 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n4821), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n2235), .Y(n4573) );
AOI22X1TS U5840 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2278), .B0(
FPADDSUB_Data_array_SWR[21]), .B1(n4522), .Y(n4572) );
NAND2X1TS U5841 ( .A(n4573), .B(n4572), .Y(n4586) );
AOI22X1TS U5842 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n4821), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2236), .Y(n4575) );
AOI22X1TS U5843 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2278), .B0(
FPADDSUB_Data_array_SWR[22]), .B1(n4522), .Y(n4574) );
NAND2X1TS U5844 ( .A(n4575), .B(n4574), .Y(n4587) );
OAI22X1TS U5845 ( .A0(n4595), .A1(n5027), .B0(n4846), .B1(n4530), .Y(n1374)
);
AO22XLTS U5846 ( .A0(n4798), .A1(FPADDSUB_DmP_EXP_EWSW[11]), .B0(n4634),
.B1(FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1372) );
AOI22X1TS U5847 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n4522), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2278), .Y(n4578) );
AOI22X1TS U5848 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n4821), .B0(n2282),
.B1(n2235), .Y(n4577) );
OAI211X1TS U5849 ( .A0(n4860), .A1(n2196), .B0(n4578), .C0(n4577), .Y(n4797)
);
OAI22X1TS U5850 ( .A0(n5071), .A1(n4580), .B0(n4927), .B1(n4579), .Y(n4581)
);
AOI211X1TS U5851 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4797), .B0(n4585),
.C0(n4584), .Y(n4849) );
OAI22X1TS U5852 ( .A0(n4595), .A1(n5028), .B0(n4849), .B1(n2290), .Y(n1371)
);
AO22XLTS U5853 ( .A0(n4798), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n4634),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1369) );
AOI221X1TS U5854 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4587), .B0(n4829),
.B1(n4586), .C0(n4588), .Y(n4845) );
OAI22X1TS U5855 ( .A0(n4595), .A1(n5029), .B0(n4845), .B1(n4530), .Y(n1368)
);
AO22XLTS U5856 ( .A0(n4798), .A1(FPADDSUB_DmP_EXP_EWSW[10]), .B0(n4634),
.B1(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1366) );
AOI21X1TS U5857 ( .A0(n2285), .A1(n2279), .B0(n4588), .Y(n4590) );
AOI22X1TS U5858 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n4821), .B0(n2281),
.B1(n2236), .Y(n4589) );
OAI211X1TS U5859 ( .A0(n5065), .A1(n4591), .B0(n4590), .C0(n4589), .Y(n4805)
);
AOI22X1TS U5860 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n2279), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n2236), .Y(n4592) );
OAI211X1TS U5861 ( .A0(n5064), .A1(n4594), .B0(n4593), .C0(n4592), .Y(n4806)
);
AOI22X1TS U5862 ( .A0(n2248), .A1(n4805), .B0(n4806), .B1(n2247), .Y(n4847)
);
OAI22X1TS U5863 ( .A0(n4595), .A1(n5030), .B0(n4847), .B1(n2290), .Y(n1365)
);
AOI22X1TS U5864 ( .A0(n4922), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n5052), .B1(
FPADDSUB_intDY_EWSW[17]), .Y(n4596) );
AOI22X1TS U5865 ( .A0(n5046), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n5055), .B1(
FPADDSUB_intDY_EWSW[15]), .Y(n4597) );
AOI22X1TS U5866 ( .A0(n4921), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n5053), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n4598) );
OAI221XLTS U5867 ( .A0(n4921), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n5053),
.B1(FPADDSUB_intDY_EWSW[13]), .C0(n4598), .Y(n4601) );
AOI22X1TS U5868 ( .A0(n4920), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n5051), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n4599) );
OAI221XLTS U5869 ( .A0(n4920), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n5051),
.B1(FPADDSUB_intDY_EWSW[11]), .C0(n4599), .Y(n4600) );
NOR4X1TS U5870 ( .A(n4603), .B(n4601), .C(n4602), .D(n4600), .Y(n4630) );
AOI22X1TS U5871 ( .A0(n5045), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n5050), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n4604) );
AOI22X1TS U5872 ( .A0(n5066), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n4924), .B1(
FPADDSUB_intDY_EWSW[29]), .Y(n4605) );
OAI221XLTS U5873 ( .A0(n5066), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n4924),
.B1(FPADDSUB_intDY_EWSW[29]), .C0(n4605), .Y(n4610) );
AOI22X1TS U5874 ( .A0(n5067), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n5048), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n4606) );
AOI22X1TS U5875 ( .A0(n4877), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n5049), .B1(
FPADDSUB_intDY_EWSW[1]), .Y(n4607) );
OAI221XLTS U5876 ( .A0(n4877), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n5049),
.B1(FPADDSUB_intDY_EWSW[1]), .C0(n4607), .Y(n4608) );
NOR4X1TS U5877 ( .A(n4611), .B(n4610), .C(n4609), .D(n4608), .Y(n4629) );
AOI22X1TS U5878 ( .A0(n4867), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n5013), .B1(
FPADDSUB_intDY_EWSW[23]), .Y(n4612) );
AOI22X1TS U5879 ( .A0(n4923), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n5054), .B1(
FPADDSUB_intDY_EWSW[21]), .Y(n4613) );
OAI221XLTS U5880 ( .A0(n4923), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n5054),
.B1(FPADDSUB_intDY_EWSW[21]), .C0(n4613), .Y(n4626) );
OAI22X1TS U5881 ( .A0(n5044), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n4916), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n4614) );
AOI221X1TS U5882 ( .A0(n5044), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[20]), .B1(n4916), .C0(n4614), .Y(n4615) );
OAI221XLTS U5883 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n5057), .B0(n5069), .B1(
FPADDSUB_intDY_EWSW[7]), .C0(n4615), .Y(n4625) );
OAI22X1TS U5884 ( .A0(n5061), .A1(FPADDSUB_intDY_EWSW[0]), .B0(n4876), .B1(
FPADDSUB_intDY_EWSW[26]), .Y(n4616) );
AOI221X1TS U5885 ( .A0(n5061), .A1(FPADDSUB_intDY_EWSW[0]), .B0(
FPADDSUB_intDY_EWSW[26]), .B1(n4876), .C0(n4616), .Y(n4623) );
OAI22X1TS U5886 ( .A0(n5043), .A1(FPADDSUB_intDY_EWSW[2]), .B0(n4917), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n4617) );
AOI221X1TS U5887 ( .A0(n5043), .A1(FPADDSUB_intDY_EWSW[2]), .B0(
FPADDSUB_intDY_EWSW[3]), .B1(n4917), .C0(n4617), .Y(n4622) );
OAI22X1TS U5888 ( .A0(n4919), .A1(FPADDSUB_intDY_EWSW[4]), .B0(n5060), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n4618) );
OAI22X1TS U5889 ( .A0(n4918), .A1(FPADDSUB_intDY_EWSW[6]), .B0(n5042), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n4619) );
AOI221X1TS U5890 ( .A0(n4918), .A1(FPADDSUB_intDY_EWSW[6]), .B0(
FPADDSUB_intDY_EWSW[8]), .B1(n5042), .C0(n4619), .Y(n4620) );
NAND4XLTS U5891 ( .A(n4623), .B(n4622), .C(n4621), .D(n4620), .Y(n4624) );
NOR4X1TS U5892 ( .A(n4627), .B(n4626), .C(n4624), .D(n4625), .Y(n4628) );
CLKXOR2X2TS U5893 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(
n4636) );
OAI22X1TS U5894 ( .A0(FPADDSUB_intDX_EWSW[31]), .A1(n4632), .B0(n4631), .B1(
n4636), .Y(n4633) );
AO22XLTS U5895 ( .A0(n4798), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n4634), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1363) );
AO22XLTS U5896 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n2252), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1362) );
AO22XLTS U5897 ( .A0(n4820), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n4841), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1361) );
AO22XLTS U5898 ( .A0(n4782), .A1(FPADDSUB_SIGN_FLAG_SFG), .B0(n4790), .B1(
FPADDSUB_SIGN_FLAG_NRM), .Y(n1360) );
AO22XLTS U5899 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n2197), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n1359) );
AOI2BB2XLTS U5900 ( .B0(FPADDSUB_intDX_EWSW[31]), .B1(n4636), .A0N(n4636),
.A1N(FPADDSUB_intDX_EWSW[31]), .Y(n4638) );
AO22XLTS U5901 ( .A0(n5156), .A1(n4638), .B0(n4637), .B1(
FPADDSUB_OP_FLAG_EXP), .Y(n1357) );
AO22XLTS U5902 ( .A0(n4798), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n4817), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1356) );
INVX4TS U5903 ( .A(n2252), .Y(n4819) );
AO22XLTS U5904 ( .A0(n4819), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n2252), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1355) );
BUFX3TS U5905 ( .A(n4839), .Y(n4844) );
BUFX3TS U5906 ( .A(n4851), .Y(n4863) );
AO22XLTS U5907 ( .A0(n4844), .A1(n4787), .B0(n4865), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1354) );
AOI21X1TS U5908 ( .A0(n4639), .A1(n5086), .B0(n4787), .Y(n4640) );
AOI22X1TS U5909 ( .A0(n4792), .A1(n4868), .B0(n5068), .B1(n4790), .Y(n1351)
);
NOR2XLTS U5910 ( .A(n4774), .B(n4868), .Y(n4641) );
AOI22X1TS U5911 ( .A0(n4753), .A1(n4642), .B0(n4904), .B1(n4790), .Y(n1350)
);
NAND2X1TS U5912 ( .A(n4787), .B(n4643), .Y(n4645) );
OAI21XLTS U5913 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(FPADDSUB_DMP_SFG[0]), .B0(n4648), .Y(n4644) );
XNOR2X1TS U5914 ( .A(n4645), .B(n4644), .Y(n4646) );
AOI2BB2XLTS U5915 ( .B0(n4782), .B1(n4646), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[2]), .A1N(n4782), .Y(n1349) );
OAI21XLTS U5916 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n2208), .B0(n4647),
.Y(n4651) );
AOI22X1TS U5917 ( .A0(n4787), .A1(n4649), .B0(n4648), .B1(n4774), .Y(n4650)
);
XNOR2X1TS U5918 ( .A(n4651), .B(n4650), .Y(n4652) );
AOI22X1TS U5919 ( .A0(n4782), .A1(n4652), .B0(n4873), .B1(n4790), .Y(n1348)
);
AOI21X1TS U5920 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(n4940), .B0(n4653), .Y(n4657) );
AOI22X1TS U5921 ( .A0(n4787), .A1(n4655), .B0(n4654), .B1(n5084), .Y(n4656)
);
XNOR2X1TS U5922 ( .A(n4657), .B(n4656), .Y(n4658) );
AOI22X1TS U5923 ( .A0(n4782), .A1(n4658), .B0(n4875), .B1(n5098), .Y(n1347)
);
BUFX3TS U5924 ( .A(n4774), .Y(n4784) );
AOI22X1TS U5925 ( .A0(n4787), .A1(n4660), .B0(n4659), .B1(n4784), .Y(n4663)
);
OAI21XLTS U5926 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n4883), .B0(n4661),
.Y(n4662) );
XNOR2X1TS U5927 ( .A(n4663), .B(n4662), .Y(n4664) );
AOI22X1TS U5928 ( .A0(n4753), .A1(n4664), .B0(n4902), .B1(n5098), .Y(n1346)
);
AOI21X1TS U5929 ( .A0(FPADDSUB_DMP_SFG[4]), .A1(n4954), .B0(n4665), .Y(n4669) );
AOI22X1TS U5930 ( .A0(n4787), .A1(n4667), .B0(n4666), .B1(n4784), .Y(n4668)
);
XNOR2X1TS U5931 ( .A(n4669), .B(n4668), .Y(n4670) );
AOI22X1TS U5932 ( .A0(n4792), .A1(n4670), .B0(n4874), .B1(n4790), .Y(n1345)
);
AOI22X1TS U5933 ( .A0(n4787), .A1(n4672), .B0(n4671), .B1(n4784), .Y(n4675)
);
OAI21XLTS U5934 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n4891), .B0(n4673),
.Y(n4674) );
XNOR2X1TS U5935 ( .A(n4675), .B(n4674), .Y(n4676) );
AOI22X1TS U5936 ( .A0(n4753), .A1(n4676), .B0(n4911), .B1(n4713), .Y(n1344)
);
AOI21X1TS U5937 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(n4960), .B0(n4677), .Y(n4681) );
AOI22X1TS U5938 ( .A0(n4787), .A1(n4679), .B0(n4678), .B1(n4784), .Y(n4680)
);
XNOR2X1TS U5939 ( .A(n4681), .B(n4680), .Y(n4682) );
AOI22X1TS U5940 ( .A0(n4792), .A1(n4682), .B0(n4871), .B1(n4713), .Y(n1343)
);
AOI22X1TS U5941 ( .A0(n4787), .A1(n4684), .B0(n4683), .B1(n4784), .Y(n4687)
);
OAI21XLTS U5942 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n4893), .B0(n4685),
.Y(n4686) );
XNOR2X1TS U5943 ( .A(n4687), .B(n4686), .Y(n4688) );
AOI22X1TS U5944 ( .A0(n4753), .A1(n4688), .B0(n4895), .B1(n4713), .Y(n1342)
);
AOI21X1TS U5945 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(n4967), .B0(n4689), .Y(n4693) );
AOI22X1TS U5946 ( .A0(n4787), .A1(n4691), .B0(n4690), .B1(n4784), .Y(n4692)
);
XNOR2X1TS U5947 ( .A(n4693), .B(n4692), .Y(n4694) );
AOI22X1TS U5948 ( .A0(n4792), .A1(n4694), .B0(n4930), .B1(n4713), .Y(n1341)
);
AOI22X1TS U5949 ( .A0(n4777), .A1(n4697), .B0(n4696), .B1(n4784), .Y(n4700)
);
XNOR2X1TS U5950 ( .A(n4700), .B(n4699), .Y(n4701) );
AOI22X1TS U5951 ( .A0(n4753), .A1(n4701), .B0(n4878), .B1(n4713), .Y(n1340)
);
AOI21X1TS U5952 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(n4976), .B0(n4702), .Y(
n4706) );
AOI22X1TS U5953 ( .A0(n4777), .A1(n4704), .B0(n4703), .B1(n4784), .Y(n4705)
);
XNOR2X1TS U5954 ( .A(n4706), .B(n4705), .Y(n4707) );
AOI22X1TS U5955 ( .A0(n4792), .A1(n4707), .B0(n4908), .B1(n4713), .Y(n1339)
);
AOI22X1TS U5956 ( .A0(n4777), .A1(n4709), .B0(n4708), .B1(n4784), .Y(n4712)
);
OAI21XLTS U5957 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n4975), .B0(n4710),
.Y(n4711) );
XNOR2X1TS U5958 ( .A(n4712), .B(n4711), .Y(n4714) );
AOI22X1TS U5959 ( .A0(n4792), .A1(n4714), .B0(n4931), .B1(n4713), .Y(n1338)
);
AOI21X1TS U5960 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(n4985), .B0(n4715), .Y(
n4719) );
AOI22X1TS U5961 ( .A0(n4777), .A1(n4717), .B0(n4716), .B1(n4784), .Y(n4718)
);
XNOR2X1TS U5962 ( .A(n4719), .B(n4718), .Y(n4720) );
AOI22X1TS U5963 ( .A0(n4792), .A1(n4720), .B0(n5006), .B1(n4760), .Y(n1337)
);
AOI22X1TS U5964 ( .A0(n4777), .A1(n4722), .B0(n4721), .B1(n4774), .Y(n4725)
);
OAI21XLTS U5965 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(n4984), .B0(n4723),
.Y(n4724) );
XNOR2X1TS U5966 ( .A(n4725), .B(n4724), .Y(n4726) );
AOI22X1TS U5967 ( .A0(n4753), .A1(n4726), .B0(n4955), .B1(n4760), .Y(n1336)
);
AOI21X1TS U5968 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(n5005), .B0(n4727), .Y(
n4731) );
AOI22X1TS U5969 ( .A0(n4777), .A1(n4729), .B0(n4728), .B1(n4774), .Y(n4730)
);
XNOR2X1TS U5970 ( .A(n4731), .B(n4730), .Y(n4732) );
AOI22X1TS U5971 ( .A0(n4792), .A1(n4732), .B0(n4869), .B1(n5098), .Y(n1335)
);
AOI22X1TS U5972 ( .A0(n4777), .A1(n4734), .B0(n4733), .B1(n4774), .Y(n4737)
);
XNOR2X1TS U5973 ( .A(n4737), .B(n4736), .Y(n4738) );
AOI22X1TS U5974 ( .A0(n4792), .A1(n4738), .B0(n4890), .B1(n4760), .Y(n1334)
);
AOI21X1TS U5975 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(n5010), .B0(n4739), .Y(
n4743) );
AOI22X1TS U5976 ( .A0(n4777), .A1(n4741), .B0(n4740), .B1(n4774), .Y(n4742)
);
XNOR2X1TS U5977 ( .A(n4743), .B(n4742), .Y(n4744) );
AOI22X1TS U5978 ( .A0(n4753), .A1(n4744), .B0(n4995), .B1(n4760), .Y(n1333)
);
AOI211X1TS U5979 ( .A0(n4829), .A1(n4747), .B0(n4746), .C0(n4808), .Y(n4835)
);
OAI22X1TS U5980 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5031), .B0(n4835),
.B1(n4530), .Y(n1331) );
AO22XLTS U5981 ( .A0(n4798), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n4817), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1329) );
AO22XLTS U5982 ( .A0(n4798), .A1(FPADDSUB_DMP_EXP_EWSW[3]), .B0(n4817), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1327) );
AO22XLTS U5983 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(n2253),
.B1(FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1326) );
AO22XLTS U5984 ( .A0(n4841), .A1(FPADDSUB_DMP_SFG[3]), .B0(n4820), .B1(
FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1325) );
AOI22X1TS U5985 ( .A0(n4777), .A1(n4749), .B0(n4748), .B1(n4774), .Y(n4752)
);
XNOR2X1TS U5986 ( .A(n4752), .B(n4751), .Y(n4754) );
AOI21X1TS U5987 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(n5047), .B0(n4755), .Y(
n4759) );
AOI22X1TS U5988 ( .A0(n4777), .A1(n4757), .B0(n4756), .B1(n4774), .Y(n4758)
);
XNOR2X1TS U5989 ( .A(n4759), .B(n4758), .Y(n4761) );
AOI22X1TS U5990 ( .A0(n4753), .A1(n4761), .B0(n4996), .B1(n4760), .Y(n1322)
);
AOI22X1TS U5991 ( .A0(n4777), .A1(n4763), .B0(n4762), .B1(n4774), .Y(n4766)
);
XNOR2X1TS U5992 ( .A(n4766), .B(n4765), .Y(n4767) );
AOI22X1TS U5993 ( .A0(n4753), .A1(n4767), .B0(n4906), .B1(n4760), .Y(n1321)
);
AOI21X1TS U5994 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(n5062), .B0(n4768), .Y(
n4772) );
AOI22X1TS U5995 ( .A0(n4777), .A1(n4770), .B0(n4769), .B1(n4774), .Y(n4771)
);
XNOR2X1TS U5996 ( .A(n4772), .B(n4771), .Y(n4773) );
AOI22X1TS U5997 ( .A0(n4753), .A1(n4773), .B0(n2272), .B1(n4760), .Y(n1319)
);
AOI22X1TS U5998 ( .A0(n4777), .A1(n4776), .B0(n4775), .B1(n4774), .Y(n4780)
);
XNOR2X1TS U5999 ( .A(n4780), .B(n4779), .Y(n4781) );
AOI22X1TS U6000 ( .A0(n4792), .A1(n4781), .B0(n4882), .B1(n4760), .Y(n1318)
);
AOI21X1TS U6001 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n5076), .B0(n4783),
.Y(n4789) );
AOI22X1TS U6002 ( .A0(n4787), .A1(n4786), .B0(n4785), .B1(n4784), .Y(n4788)
);
XNOR2X1TS U6003 ( .A(n4789), .B(n4788), .Y(n4791) );
AOI22X1TS U6004 ( .A0(n4792), .A1(n4791), .B0(n4944), .B1(n5098), .Y(n1317)
);
AOI211X1TS U6005 ( .A0(n4829), .A1(n4795), .B0(n4794), .C0(n4808), .Y(n4834)
);
OAI22X1TS U6006 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5032), .B0(n4834),
.B1(n4530), .Y(n1315) );
AO22XLTS U6007 ( .A0(n4798), .A1(FPADDSUB_DmP_EXP_EWSW[2]), .B0(n4817), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1313) );
AO22XLTS U6008 ( .A0(n4798), .A1(FPADDSUB_DMP_EXP_EWSW[2]), .B0(n4817), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1311) );
AO22XLTS U6009 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(n2253),
.B1(FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1310) );
AO22XLTS U6010 ( .A0(n4839), .A1(FPADDSUB_DMP_SFG[2]), .B0(n4820), .B1(
FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1309) );
AOI211X1TS U6011 ( .A0(n2207), .A1(n4797), .B0(n4796), .C0(n4808), .Y(n4840)
);
OAI22X1TS U6012 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5033), .B0(n4840),
.B1(n4530), .Y(n1308) );
AO22XLTS U6013 ( .A0(n4798), .A1(FPADDSUB_DmP_EXP_EWSW[7]), .B0(n4817), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1306) );
AO22XLTS U6014 ( .A0(n4798), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n4817), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1304) );
AO22XLTS U6015 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(n5237), .B1(
FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1303) );
AO22XLTS U6016 ( .A0(n4839), .A1(FPADDSUB_DMP_SFG[7]), .B0(n4857), .B1(
FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1302) );
AOI211X1TS U6017 ( .A0(n4829), .A1(n4801), .B0(n4800), .C0(n4808), .Y(n4832)
);
OAI22X1TS U6018 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5034), .B0(n4832),
.B1(n4530), .Y(n1301) );
AO22XLTS U6019 ( .A0(n4818), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n4817), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1299) );
AO22XLTS U6020 ( .A0(n4818), .A1(FPADDSUB_DMP_EXP_EWSW[0]), .B0(n4817), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1297) );
AO22XLTS U6021 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(n2274), .B1(
FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1296) );
AO22XLTS U6022 ( .A0(n4839), .A1(FPADDSUB_DMP_SFG[0]), .B0(n4820), .B1(
FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1295) );
AOI211X1TS U6023 ( .A0(n4829), .A1(n4804), .B0(n4803), .C0(n4808), .Y(n4833)
);
OAI22X1TS U6024 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5035), .B0(n4833),
.B1(n4530), .Y(n1294) );
AO22XLTS U6025 ( .A0(n4818), .A1(FPADDSUB_DmP_EXP_EWSW[1]), .B0(n4817), .B1(
FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n1292) );
AO22XLTS U6026 ( .A0(n4818), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n4813), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1290) );
AO22XLTS U6027 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(n2253), .B1(
FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1289) );
AO22XLTS U6028 ( .A0(n4863), .A1(FPADDSUB_DMP_SFG[1]), .B0(n4857), .B1(
FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1288) );
AOI22X1TS U6029 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4806), .B0(n4805),
.B1(n2207), .Y(n4843) );
OAI22X1TS U6030 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5036), .B0(n4843),
.B1(n2290), .Y(n1287) );
AO22XLTS U6031 ( .A0(n4818), .A1(FPADDSUB_DmP_EXP_EWSW[9]), .B0(n4813), .B1(
FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n1285) );
AO22XLTS U6032 ( .A0(n4818), .A1(FPADDSUB_DMP_EXP_EWSW[9]), .B0(n4813), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1283) );
AO22XLTS U6033 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n2274), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1282) );
AO22XLTS U6034 ( .A0(n2244), .A1(FPADDSUB_DMP_SFG[9]), .B0(n4857), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1281) );
AOI211X1TS U6035 ( .A0(n2207), .A1(n4810), .B0(n4809), .C0(n4808), .Y(n4837)
);
OAI22X1TS U6036 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5037), .B0(n4837),
.B1(n4530), .Y(n1280) );
AO22XLTS U6037 ( .A0(n4818), .A1(FPADDSUB_DmP_EXP_EWSW[5]), .B0(n4813), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1278) );
AO22XLTS U6038 ( .A0(n4818), .A1(FPADDSUB_DMP_EXP_EWSW[5]), .B0(n4813), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1276) );
AO22XLTS U6039 ( .A0(n5245), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(n5237),
.B1(FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1275) );
AO22XLTS U6040 ( .A0(n4839), .A1(FPADDSUB_DMP_SFG[5]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1274) );
AO22XLTS U6041 ( .A0(n4818), .A1(FPADDSUB_DmP_EXP_EWSW[12]), .B0(n4813),
.B1(FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n1272) );
AO22XLTS U6042 ( .A0(n4818), .A1(FPADDSUB_DMP_EXP_EWSW[12]), .B0(n4813),
.B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1270) );
AO22XLTS U6043 ( .A0(n5245), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n5237),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1269) );
AO22XLTS U6044 ( .A0(n4839), .A1(FPADDSUB_DMP_SFG[12]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1268) );
AO22XLTS U6045 ( .A0(n4818), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n4813),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1266) );
AO22XLTS U6046 ( .A0(n5245), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n5237),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1265) );
AO22XLTS U6047 ( .A0(n4839), .A1(FPADDSUB_DMP_SFG[10]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1264) );
AO22XLTS U6048 ( .A0(n4818), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n4813),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1262) );
AO22XLTS U6049 ( .A0(n5245), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n5237),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1261) );
AO22XLTS U6050 ( .A0(n4839), .A1(FPADDSUB_DMP_SFG[14]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1260) );
AO22XLTS U6051 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[11]), .B0(n4813),
.B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1258) );
AO22XLTS U6052 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n5237),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1257) );
AO22XLTS U6053 ( .A0(n4839), .A1(FPADDSUB_DMP_SFG[11]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1256) );
AO22XLTS U6054 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n4813), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1254) );
AO22XLTS U6055 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n2274),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1253) );
AO22XLTS U6056 ( .A0(n4839), .A1(FPADDSUB_DMP_SFG[8]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1252) );
AO22XLTS U6057 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[16]), .B0(n4814),
.B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1250) );
AO22XLTS U6058 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n2253),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1249) );
AO22XLTS U6059 ( .A0(n4844), .A1(FPADDSUB_DMP_SFG[16]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1248) );
AO22XLTS U6060 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[13]), .B0(n4814),
.B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1246) );
AO22XLTS U6061 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n5237),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1245) );
AO22XLTS U6062 ( .A0(n4844), .A1(FPADDSUB_DMP_SFG[13]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1244) );
AO22XLTS U6063 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[6]), .B0(n4814), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1242) );
AO22XLTS U6064 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(n2253),
.B1(FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1241) );
AO22XLTS U6065 ( .A0(n4844), .A1(FPADDSUB_DMP_SFG[6]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1240) );
AO22XLTS U6066 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n4814), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1238) );
AO22XLTS U6067 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(n2274), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1237) );
AO22XLTS U6068 ( .A0(n4844), .A1(FPADDSUB_DMP_SFG[4]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1236) );
AO22XLTS U6069 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[17]), .B0(n4814),
.B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1234) );
AO22XLTS U6070 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n2253),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1233) );
AO22XLTS U6071 ( .A0(n4844), .A1(FPADDSUB_DMP_SFG[17]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1232) );
AO22XLTS U6072 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n4814),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1230) );
AO22XLTS U6073 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n5237),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1229) );
AO22XLTS U6074 ( .A0(n4844), .A1(FPADDSUB_DMP_SFG[20]), .B0(n4816), .B1(
FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1228) );
AO22XLTS U6075 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[19]), .B0(n4814),
.B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1226) );
AO22XLTS U6076 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n2253),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1225) );
AO22XLTS U6077 ( .A0(n4844), .A1(FPADDSUB_DMP_SFG[19]), .B0(n4820), .B1(
FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1224) );
AO22XLTS U6078 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[21]), .B0(n4814),
.B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1222) );
AO22XLTS U6079 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n2274),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1221) );
AO22XLTS U6080 ( .A0(n4844), .A1(FPADDSUB_DMP_SFG[21]), .B0(n2246), .B1(
FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1220) );
AO22XLTS U6081 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[18]), .B0(n4814),
.B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1218) );
AO22XLTS U6082 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n2253),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1217) );
AO22XLTS U6083 ( .A0(n4844), .A1(FPADDSUB_DMP_SFG[18]), .B0(n2246), .B1(
FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1216) );
AO22XLTS U6084 ( .A0(n4815), .A1(FPADDSUB_DMP_EXP_EWSW[15]), .B0(n4814),
.B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1214) );
AO22XLTS U6085 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n2274),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1213) );
AO22XLTS U6086 ( .A0(n4863), .A1(FPADDSUB_DMP_SFG[15]), .B0(n2246), .B1(
FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1212) );
AO22XLTS U6087 ( .A0(n4818), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n4817),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1210) );
AO22XLTS U6088 ( .A0(n4819), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n2274),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1209) );
AO22XLTS U6089 ( .A0(n4839), .A1(FPADDSUB_DMP_SFG[22]), .B0(n4820), .B1(
FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1208) );
AOI22X1TS U6090 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n4821), .B0(
FPADDSUB_Data_array_SWR[0]), .B1(n2236), .Y(n4823) );
AOI22X1TS U6091 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n4522), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n2279), .Y(n4822) );
OAI211X1TS U6092 ( .A0(n4825), .A1(n2196), .B0(n4823), .C0(n4822), .Y(n4861)
);
AOI2BB2XLTS U6093 ( .B0(n2207), .B1(n4861), .A0N(n4860), .A1N(n4556), .Y(
n4826) );
AOI32X1TS U6094 ( .A0(n4826), .A1(n2246), .A2(n4830), .B0(n4868), .B1(n4863),
.Y(n1207) );
AOI2BB2XLTS U6095 ( .B0(n2247), .B1(n4828), .A0N(n4827), .A1N(n4556), .Y(
n4831) );
AOI32X1TS U6096 ( .A0(n4831), .A1(n4865), .A2(n4830), .B0(n2200), .B1(n4863),
.Y(n1206) );
AOI22X1TS U6097 ( .A0(n4865), .A1(n4833), .B0(n4939), .B1(n4844), .Y(n1204)
);
AOI22X1TS U6098 ( .A0(n2245), .A1(n4834), .B0(n4940), .B1(n2244), .Y(n1203)
);
AOI22X1TS U6099 ( .A0(n2245), .A1(n4835), .B0(n4953), .B1(n2244), .Y(n1202)
);
AOI22X1TS U6100 ( .A0(n4865), .A1(n4836), .B0(n4954), .B1(n4839), .Y(n1201)
);
AOI22X1TS U6101 ( .A0(n2245), .A1(n4837), .B0(n4959), .B1(n4841), .Y(n1200)
);
AOI22X1TS U6102 ( .A0(n2245), .A1(n4838), .B0(n4960), .B1(n4839), .Y(n1199)
);
AOI22X1TS U6103 ( .A0(n4865), .A1(n4840), .B0(n4966), .B1(n4839), .Y(n1198)
);
AOI22X1TS U6104 ( .A0(n2245), .A1(n4842), .B0(n4967), .B1(n4841), .Y(n1197)
);
AOI22X1TS U6105 ( .A0(n2245), .A1(n4843), .B0(n4896), .B1(n4844), .Y(n1196)
);
AOI22X1TS U6106 ( .A0(n2245), .A1(n4845), .B0(n4976), .B1(n4844), .Y(n1195)
);
AOI22X1TS U6107 ( .A0(n4865), .A1(n4846), .B0(n4898), .B1(n2244), .Y(n1194)
);
AOI22X1TS U6108 ( .A0(n2245), .A1(n4847), .B0(n4985), .B1(n4851), .Y(n1193)
);
AOI22X1TS U6109 ( .A0(n2246), .A1(n4848), .B0(n2217), .B1(n4851), .Y(n1192)
);
AOI22X1TS U6110 ( .A0(n2245), .A1(n4849), .B0(n5005), .B1(n4851), .Y(n1191)
);
AOI22X1TS U6111 ( .A0(n4865), .A1(n4850), .B0(n4910), .B1(n4863), .Y(n1190)
);
AOI22X1TS U6112 ( .A0(n2246), .A1(n4852), .B0(n5010), .B1(n4851), .Y(n1189)
);
AOI22X1TS U6113 ( .A0(n2246), .A1(n4853), .B0(n4912), .B1(n4851), .Y(n1188)
);
AOI22X1TS U6114 ( .A0(n2246), .A1(n4854), .B0(n5047), .B1(n4863), .Y(n1187)
);
AOI22X1TS U6115 ( .A0(n4865), .A1(n4855), .B0(n4915), .B1(n4863), .Y(n1186)
);
AOI22X1TS U6116 ( .A0(n4865), .A1(n4856), .B0(n5062), .B1(n4851), .Y(n1185)
);
AOI22X1TS U6117 ( .A0(n2246), .A1(n4858), .B0(n4925), .B1(n4863), .Y(n1184)
);
AOI2BB2XLTS U6118 ( .B0(FPADDSUB_left_right_SHT2), .B1(n4861), .A0N(n4860),
.A1N(n4526), .Y(n4866) );
AOI32X1TS U6119 ( .A0(n4866), .A1(n2246), .A2(n4864), .B0(n5086), .B1(n4863),
.Y(n1182) );
CMPR42X1TS U6120 ( .A(mult_x_69_n1103), .B(mult_x_69_n1079), .C(
mult_x_69_n542), .D(mult_x_69_n534), .ICI(mult_x_69_n538), .S(
mult_x_69_n531), .ICO(mult_x_69_n529), .CO(mult_x_69_n530) );
CMPR42X1TS U6121 ( .A(mult_x_69_n698), .B(mult_x_69_n1214), .C(
mult_x_69_n699), .D(mult_x_69_n690), .ICI(mult_x_69_n695), .S(
mult_x_69_n687), .ICO(mult_x_69_n685), .CO(mult_x_69_n686) );
CMPR42X1TS U6122 ( .A(mult_x_69_n1054), .B(mult_x_69_n532), .C(
mult_x_69_n533), .D(mult_x_69_n526), .ICI(mult_x_69_n529), .S(
mult_x_69_n523), .ICO(mult_x_69_n521), .CO(mult_x_69_n522) );
CMPR42X1TS U6123 ( .A(mult_x_69_n528), .B(n4946), .C(mult_x_69_n535), .D(
mult_x_69_n1078), .ICI(mult_x_69_n1102), .S(mult_x_69_n526), .ICO(
mult_x_69_n524), .CO(mult_x_69_n525) );
CMPR42X1TS U6124 ( .A(mult_x_69_n1055), .B(n4947), .C(mult_x_69_n1127), .D(
mult_x_69_n536), .ICI(mult_x_69_n541), .S(mult_x_69_n534), .ICO(
mult_x_69_n532), .CO(mult_x_69_n533) );
CMPR42X1TS U6125 ( .A(mult_x_69_n712), .B(mult_x_69_n1144), .C(
mult_x_69_n1120), .D(mult_x_69_n1192), .ICI(mult_x_69_n716), .S(
mult_x_69_n710), .ICO(mult_x_69_n708), .CO(mult_x_69_n709) );
CMPR42X1TS U6126 ( .A(mult_x_69_n1208), .B(mult_x_69_n637), .C(
mult_x_69_n1160), .D(mult_x_69_n1184), .ICI(mult_x_69_n638), .S(
mult_x_69_n625), .ICO(mult_x_69_n623), .CO(mult_x_69_n624) );
CMPR42X1TS U6127 ( .A(mult_x_69_n1106), .B(mult_x_69_n569), .C(
mult_x_69_n570), .D(mult_x_69_n561), .ICI(mult_x_69_n566), .S(
mult_x_69_n558), .ICO(mult_x_69_n556), .CO(mult_x_69_n557) );
CMPR42X1TS U6128 ( .A(mult_x_69_n584), .B(mult_x_69_n594), .C(mult_x_69_n581), .D(mult_x_69_n591), .ICI(mult_x_69_n587), .S(mult_x_69_n578), .ICO(
mult_x_69_n576), .CO(mult_x_69_n577) );
CMPR42X1TS U6129 ( .A(mult_x_69_n1154), .B(mult_x_69_n1058), .C(
mult_x_69_n573), .D(mult_x_69_n1130), .ICI(mult_x_69_n564), .S(
mult_x_69_n561), .ICO(mult_x_69_n559), .CO(mult_x_69_n560) );
CMPR42X1TS U6130 ( .A(mult_x_69_n1076), .B(mult_x_69_n1052), .C(
mult_x_69_n518), .D(mult_x_69_n512), .ICI(mult_x_69_n514), .S(
mult_x_69_n509), .ICO(mult_x_69_n507), .CO(mult_x_69_n508) );
CMPR42X1TS U6131 ( .A(mult_x_69_n524), .B(mult_x_69_n1077), .C(
mult_x_69_n519), .D(mult_x_69_n525), .ICI(mult_x_69_n521), .S(
mult_x_69_n516), .ICO(mult_x_69_n514), .CO(mult_x_69_n515) );
CMPR42X1TS U6132 ( .A(mult_x_69_n1051), .B(mult_x_69_n1075), .C(
mult_x_69_n511), .D(mult_x_69_n506), .ICI(mult_x_69_n507), .S(
mult_x_69_n503), .ICO(mult_x_69_n501), .CO(mult_x_69_n502) );
CMPR42X1TS U6133 ( .A(mult_x_69_n498), .B(n4969), .C(mult_x_69_n493), .D(
mult_x_69_n1049), .ICI(mult_x_69_n495), .S(mult_x_69_n491), .ICO(
mult_x_69_n489), .CO(mult_x_69_n490) );
CMPR42X1TS U6134 ( .A(n5160), .B(n4892), .C(mult_x_69_n1046), .D(n4982),
.ICI(mult_x_69_n480), .S(mult_x_69_n478), .ICO(mult_x_69_n476), .CO(
mult_x_69_n477) );
CMPR42X1TS U6135 ( .A(n4892), .B(mult_x_69_n487), .C(mult_x_69_n1047), .D(
n4974), .ICI(mult_x_69_n484), .S(mult_x_69_n482), .ICO(mult_x_69_n480),
.CO(mult_x_69_n481) );
CMPR42X1TS U6136 ( .A(n4884), .B(n5161), .C(n2295), .D(n4983), .ICI(
mult_x_69_n476), .S(mult_x_69_n475), .ICO(mult_x_69_n473), .CO(
mult_x_69_n474) );
endmodule
|
/****************************************
Scheduler1 Unit (Out of Order Unit 1/2)
- Register Freelist & Comitbiffer
Make : 2010/11/05
Update :
****************************************/
`default_nettype none
module scheduler1(
//System
input wire iCLOCK,
input wire inRESET,
//Interrupt
input wire iIRQ_VALID,
//Free
input wire iEXCEPTION_EVENT,
input wire [5:0] iEXCEPTION_COMMIT_TAG,
input wire iEXCEPTION_RESTART,
output wire [31:0] oFREE_CURRENT_PC,
output wire [63:0] oFREE_REGISTER,
//Info
output wire [5:0] oINFO_COMMIT_COUNTER,
output wire oINFO_EXCEPTION_PROTECT,
//Register Rename Table - Rollback Info
output wire oRENAME_ROLLBACK_UPDATE_INFO0_VALID,
output wire [4:0] oRENAME_ROLLBACK_UPDATE_INFO0_LREGNAME,
output wire [5:0] oRENAME_ROLLBACK_UPDATE_INFO0_PREGNAME,
output wire oRENAME_ROLLBACK_UPDATE_INFO0_SYSREG,
output wire oRENAME_ROLLBACK_UPDATE_INFO1_VALID,
output wire [4:0] oRENAME_ROLLBACK_UPDATE_INFO1_LREGNAME,
output wire [5:0] oRENAME_ROLLBACK_UPDATE_INFO1_PREGNAME,
output wire oRENAME_ROLLBACK_UPDATE_INFO1_SYSREG,
output wire oRENAME_ROLLBACK_UPDATE_INFO2_VALID,
output wire [4:0] oRENAME_ROLLBACK_UPDATE_INFO2_LREGNAME,
output wire [5:0] oRENAME_ROLLBACK_UPDATE_INFO2_PREGNAME,
output wire oRENAME_ROLLBACK_UPDATE_INFO2_SYSREG,
output wire oRENAME_ROLLBACK_UPDATE_INFO3_VALID,
output wire [4:0] oRENAME_ROLLBACK_UPDATE_INFO3_LREGNAME,
output wire [5:0] oRENAME_ROLLBACK_UPDATE_INFO3_PREGNAME,
output wire oRENAME_ROLLBACK_UPDATE_INFO3_SYSREG,
output wire oFLAGR_RENAME_ROLLBACK_UPDATE_INFO0_VALID,
output wire [3:0] oFLAGR_RENAME_ROLLBACK_UPDATE_INFO0_PREGNAME,
output wire oFLAGR_RENAME_ROLLBACK_UPDATE_INFO1_VALID,
output wire [3:0] oFLAGR_RENAME_ROLLBACK_UPDATE_INFO1_PREGNAME,
output wire oFLAGR_RENAME_ROLLBACK_UPDATE_INFO2_VALID,
output wire [3:0] oFLAGR_RENAME_ROLLBACK_UPDATE_INFO2_PREGNAME,
output wire oFLAGR_RENAME_ROLLBACK_UPDATE_INFO3_VALID,
output wire [3:0] oFLAGR_RENAME_ROLLBACK_UPDATE_INFO3_PREGNAME,
//Commit Infomation
output wire [2:0] oCOMMIT_OFFSET,
//Re Order Buffer
output wire [63:0] oCOMMIT_ENTRY_COMMIT_VECTOR,
//EX_Output - Branch
input wire iSCHE1_EX_BRANCH_VALID,
input wire [5:0] iSCHE1_EX_BRANCH_COMMIT_TAG,
//EX_Output - ADDER
input wire iSCHE1_EX_ALU1_VALID,
input wire [5:0] iSCHE1_EX_ALU1_COMMIT_TAG,
//EX_Output - MULDIV
input wire iSCHE1_EX_ALU2_VALID,
input wire [5:0] iSCHE1_EX_ALU2_COMMIT_TAG,
//LDST_Output
input wire iSCHE1_EX_ALU3_VALID,
input wire [5:0] iSCHE1_EX_ALU3_COMMIT_TAG,
//StageInfo
output wire oSTAGE_INFO_0_VALID,
output wire oSTAGE_INFO_1_VALID,
output wire [5:0] oSTAGE_INFO_REGIST_POINTER,
output wire [5:0] oSTAGE_INFO_COMMIT_POINTER,
//Previous-0
input wire iPREVIOUS_0_VALID,
input wire iPREVIOUS_0_SOURCE0_ACTIVE,
input wire iPREVIOUS_0_SOURCE1_ACTIVE,
input wire iPREVIOUS_0_SOURCE0_SYSREG,
input wire iPREVIOUS_0_SOURCE1_SYSREG,
input wire iPREVIOUS_0_SOURCE0_SYSREG_RENAME,
input wire iPREVIOUS_0_SOURCE1_SYSREG_RENAME,
input wire iPREVIOUS_0_ADV_ACTIVE,
input wire iPREVIOUS_0_DESTINATION_SYSREG,
input wire iPREVIOUS_0_WRITEBACK,
input wire iPREVIOUS_0_FLAGS_WRITEBACK,
input wire [4:0] iPREVIOUS_0_CMD,
input wire [3:0] iPREVIOUS_0_CC_AFE,
input wire [3:0] iPREVIOUS_0_FLAGS_REGNAME,
input wire [5:0] iPREVIOUS_0_DESTINATION_REGNAME,
input wire [4:0] iPREVIOUS_0_LOGIC_DESTINATION,
input wire [5:0] iPREVIOUS_0_SOURCE0,
input wire [31:0] iPREVIOUS_0_SOURCE1,
input wire [5:0] iPREVIOUS_0_ADV_DATA,
input wire iPREVIOUS_0_SOURCE0_FLAGS,
input wire iPREVIOUS_0_SOURCE1_IMM,
input wire iPREVIOUS_0_EX_SYS_ADDER,
input wire iPREVIOUS_0_EX_SYS_LDST,
input wire iPREVIOUS_0_EX_LOGIC,
input wire iPREVIOUS_0_EX_SHIFT,
input wire iPREVIOUS_0_EX_ADDER,
input wire iPREVIOUS_0_EX_MUL,
input wire iPREVIOUS_0_EX_SDIV,
input wire iPREVIOUS_0_EX_UDIV,
input wire iPREVIOUS_0_EX_LDST,
input wire iPREVIOUS_0_EX_BRANCH,
//Previous-1
input wire iPREVIOUS_1_VALID,
input wire iPREVIOUS_1_SOURCE0_ACTIVE,
input wire iPREVIOUS_1_SOURCE1_ACTIVE,
input wire iPREVIOUS_1_SOURCE0_SYSREG,
input wire iPREVIOUS_1_SOURCE1_SYSREG,
input wire iPREVIOUS_1_SOURCE0_SYSREG_RENAME,
input wire iPREVIOUS_1_SOURCE1_SYSREG_RENAME,
input wire iPREVIOUS_1_ADV_ACTIVE,
input wire iPREVIOUS_1_DESTINATION_SYSREG,
input wire iPREVIOUS_1_WRITEBACK,
input wire iPREVIOUS_1_FLAGS_WRITEBACK,
input wire [4:0] iPREVIOUS_1_CMD,
input wire [3:0] iPREVIOUS_1_CC_AFE,
input wire [3:0] iPREVIOUS_1_FLAGS_REGNAME,
input wire [5:0] iPREVIOUS_1_DESTINATION_REGNAME,
input wire [4:0] iPREVIOUS_1_LOGIC_DESTINATION,
input wire [5:0] iPREVIOUS_1_SOURCE0,
input wire [31:0] iPREVIOUS_1_SOURCE1,
input wire [5:0] iPREVIOUS_1_ADV_DATA,
input wire iPREVIOUS_1_SOURCE0_FLAGS,
input wire iPREVIOUS_1_SOURCE1_IMM,
input wire iPREVIOUS_1_EX_SYS_ADDER,
input wire iPREVIOUS_1_EX_SYS_LDST,
input wire iPREVIOUS_1_EX_LOGIC,
input wire iPREVIOUS_1_EX_SHIFT,
input wire iPREVIOUS_1_EX_ADDER,
input wire iPREVIOUS_1_EX_MUL,
input wire iPREVIOUS_1_EX_SDIV,
input wire iPREVIOUS_1_EX_UDIV,
input wire iPREVIOUS_1_EX_LDST,
input wire iPREVIOUS_1_EX_BRANCH,
input wire [31:0] iPREVIOUS_PC,
output wire oPREVIOUS_LOCK,
//Previous-Register
input wire iFLAG_REGISTER_0_RD,
output wire [3:0] oFLAG_REGISTER_0_NUM,
output wire oFLAG_REGISTER_0_EMPTY,
input wire iFLAG_REGISTER_1_RD,
output wire [3:0] oFLAG_REGISTER_1_NUM,
output wire oFLAG_REGISTER_1_EMPTY,
input wire iOTHER_REGISTER_0_RD,
output wire [5:0] oOTHER_REGISTER_0_NUM,
output wire oOTHER_REGISTER_0_EMPTY,
input wire iOTHER_REGISTER_1_RD,
output wire [5:0] oOTHER_REGISTER_1_NUM,
output wire oOTHER_REGISTER_1_EMPTY,
//Next-Register
input wire iFLAG_REGISTER_0_WR,
input wire [3:0] iFLAG_REGISTER_0_NUM,
output wire oFLAG_REGISTER_0_FULL,
output wire [1:0] oFLAG_REGISTER_0_COUNT,
input wire iFLAG_REGISTER_1_WR,
input wire [3:0] iFLAG_REGISTER_1_NUM,
output wire oFLAG_REGISTER_1_FULL,
output wire [1:0] oFLAG_REGISTER_1_COUNT,
input wire iOTHER_REGISTER_0_WR,
input wire [5:0] iOTHER_REGISTER_0_NUM,
output wire oOTHER_REGISTER_0_FULL,
output wire [2:0] oOTHER_REGISTER_0_COUNT,
input wire iOTHER_REGISTER_1_WR,
input wire [5:0] iOTHER_REGISTER_1_NUM,
output wire oOTHER_REGISTER_1_FULL,
output wire [2:0] oOTHER_REGISTER_1_COUNT,
//Next-0
output wire oNEXT_0_VALID,
output wire oNEXT_0_SOURCE0_ACTIVE,
output wire oNEXT_0_SOURCE1_ACTIVE,
output wire oNEXT_0_SOURCE0_SYSREG,
output wire oNEXT_0_SOURCE1_SYSREG,
output wire oNEXT_0_SOURCE0_SYSREG_RENAME,
output wire oNEXT_0_SOURCE1_SYSREG_RENAME,
output wire oNEXT_0_ADV_ACTIVE,
output wire oNEXT_0_DESTINATION_SYSREG,
output wire oNEXT_0_WRITEBACK,
output wire oNEXT_0_FLAGS_WRITEBACK,
output wire [4:0] oNEXT_0_CMD,
output wire [5:0] oNEXT_0_COMMIT_TAG,
output wire [3:0] oNEXT_0_CC_AFE,
output wire [3:0] oNEXT_0_FLAGS_REGNAME,
output wire [5:0] oNEXT_0_DESTINATION_REGNAME,
output wire [4:0] oNEXT_0_LOGIC_DESTINATION,
output wire [5:0] oNEXT_0_SOURCE0,
output wire [31:0] oNEXT_0_SOURCE1,
output wire [5:0] oNEXT_0_ADV_DATA,
output wire oNEXT_0_SOURCE0_FLAGS,
output wire oNEXT_0_SOURCE1_IMM,
output wire oNEXT_0_EX_SYS_ADDER,
output wire oNEXT_0_EX_SYS_LDST,
output wire oNEXT_0_EX_LOGIC,
output wire oNEXT_0_EX_SHIFT,
output wire oNEXT_0_EX_ADDER,
output wire oNEXT_0_EX_MUL,
output wire oNEXT_0_EX_SDIV,
output wire oNEXT_0_EX_UDIV,
output wire oNEXT_0_EX_LDST,
output wire oNEXT_0_EX_BRANCH,
//Next-1
output wire oNEXT_1_VALID,
output wire oNEXT_1_SOURCE0_ACTIVE,
output wire oNEXT_1_SOURCE1_ACTIVE,
output wire oNEXT_1_SOURCE0_SYSREG,
output wire oNEXT_1_SOURCE1_SYSREG,
output wire oNEXT_1_SOURCE0_SYSREG_RENAME,
output wire oNEXT_1_SOURCE1_SYSREG_RENAME,
output wire oNEXT_1_ADV_ACTIVE,
output wire oNEXT_1_DESTINATION_SYSREG,
output wire oNEXT_1_WRITEBACK,
output wire oNEXT_1_FLAGS_WRITEBACK,
output wire [4:0] oNEXT_1_CMD,
output wire [5:0] oNEXT_1_COMMIT_TAG,
output wire [3:0] oNEXT_1_CC_AFE,
output wire [3:0] oNEXT_1_FLAGS_REGNAME,
output wire [5:0] oNEXT_1_DESTINATION_REGNAME,
output wire [4:0] oNEXT_1_LOGIC_DESTINATION,
output wire [5:0] oNEXT_1_SOURCE0,
output wire [31:0] oNEXT_1_SOURCE1,
output wire [5:0] oNEXT_1_ADV_DATA,
output wire oNEXT_1_SOURCE0_FLAGS,
output wire oNEXT_1_SOURCE1_IMM,
output wire oNEXT_1_EX_SYS_ADDER,
output wire oNEXT_1_EX_SYS_LDST,
output wire oNEXT_1_EX_LOGIC,
output wire oNEXT_1_EX_SHIFT,
output wire oNEXT_1_EX_ADDER,
output wire oNEXT_1_EX_MUL,
output wire oNEXT_1_EX_SDIV,
output wire oNEXT_1_EX_UDIV,
output wire oNEXT_1_EX_LDST,
output wire oNEXT_1_EX_BRANCH,
output wire [31:0] oNEXT_PC,
input wire iNEXT_LOCK
);
localparam PL_STT_NORMAL = 1'b0;
localparam PL_STT_EXCEPTION = 1'b1;
/***********************************************
Wire and Register
***********************************************/
//Generate
genvar i;
//Commit List
wire [63:0] entry_commit_valid;
wire entry_info_entry_valid[0:63];
wire entry_info_make_flags[0:63];
wire [31:0] entry_info_pc[0:63];
wire [3:0] entry_info_flags_regname[0:63];
wire entry_info_writeback[0:63];
wire [4:0] entry_info_logic_destination[0:63];
wire [5:0] entry_info_destination_regname[0:63];
wire entry_info_dest_sysreg[0:63];
wire entry_info_ex_branch[0:63];
wire [63:0] entry_info_ex_end;
//Commit Valid
wire entry_commit_0_valid;
wire entry_commit_1_valid;
wire entry_commit_2_valid;
wire entry_commit_3_valid;
wire [5:0] entry_commit_0_num;
wire [5:0] entry_commit_1_num;
wire [5:0] entry_commit_2_num;
wire [5:0] entry_commit_3_num;
//Exception Protect Check(Non Core Exceotion Block)
wire exception_protect;
//Commit Infomation
wire [6:0] w_commit_count;
wire [2:0] w_commit_offset;
wire [5:0] w_commit_pointer;
wire [5:0] w_register_pointer;
wire [5:0] ww_regist_pointer;
//Commit Count Register
reg [6:0] b_commit_pointer;
reg [6:0] b_regist_pointer;
reg [6:0] bb_regist_pointer;
//Commit Id Info
wire w_commit_id_n0_valid;
wire w_commit_id_n1_valid;
wire w_commit_id_n2_valid;
wire w_commit_id_n3_valid;
wire [5:0] w_commit_id_n0;
wire [5:0] w_commit_id_n1;
wire [5:0] w_commit_id_n2;
wire [5:0] w_commit_id_n3;
//RollBack Register
reg b_commit_id_n0_valid;
reg b_commit_id_n1_valid;
reg b_commit_id_n2_valid;
reg b_commit_id_n3_valid;
reg [5:0] b_commit_id_n0;
reg [5:0] b_commit_id_n1;
reg [5:0] b_commit_id_n2;
reg [5:0] b_commit_id_n3;
reg [4:0] b_commit_lregname_n0;
reg [4:0] b_commit_lregname_n1;
reg [4:0] b_commit_lregname_n2;
reg [4:0] b_commit_lregname_n3;
reg [5:0] b_commit_pregname_n0;
reg [5:0] b_commit_pregname_n1;
reg [5:0] b_commit_pregname_n2;
reg [5:0] b_commit_pregname_n3;
reg b_commit_writeback_n0;
reg b_commit_writeback_n1;
reg b_commit_writeback_n2;
reg b_commit_writeback_n3;
reg b_commit_dest_sysreg_n0;
reg b_commit_dest_sysreg_n1;
reg b_commit_dest_sysreg_n2;
reg b_commit_dest_sysreg_n3;
reg b_commit_flags_make_flags_n0;
reg b_commit_flags_make_flags_n1;
reg b_commit_flags_make_flags_n2;
reg b_commit_flags_make_flags_n3;
reg [3:0] b_commit_flags_p_regname_n0;
reg [3:0] b_commit_flags_p_regname_n1;
reg [3:0] b_commit_flags_p_regname_n2;
reg [3:0] b_commit_flags_p_regname_n3;
//Next Stage Buffer
//Instruction0
reg b0_valid;
reg b0_source0_active;
reg b0_source1_active;
reg b0_source0_sysreg;
reg b0_source1_sysreg;
reg b0_source0_sysreg_rename;
reg b0_source1_sysreg_rename;
reg b0_adv_active;
reg b0_destination_sysreg;
reg b0_data_writeback;
reg b0_flags_writeback;
reg [4:0] b0_cmd;
reg [5:0] b0_commit_tag;
reg [3:0] b0_cc_afe;
reg [3:0] b0_flags_regname;
reg [5:0] b0_destination_regname;
reg [4:0] b0_logic_destination;
reg [5:0] b0_source0;
reg [31:0] b0_source1;
reg [5:0] b0_adv_data;
reg b0_source0_flags;
reg b0_source1_imm;
reg b0_ex_sys_adder;
reg b0_ex_sys_ldst;
reg b0_ex_logic;
reg b0_ex_shift;
reg b0_ex_adder;
reg b0_ex_mul;
reg b0_ex_sdiv;
reg b0_ex_udiv;
reg b0_ex_ldst;
reg b0_ex_branch;
//Instruction1
reg b1_valid;
reg b1_source0_active;
reg b1_source1_active;
reg b1_source0_sysreg;
reg b1_source1_sysreg;
reg b1_source0_sysreg_rename;
reg b1_source1_sysreg_rename;
reg b1_adv_active;
reg b1_destination_sysreg;
reg b1_data_writeback;
reg b1_flags_writeback;
reg [4:0] b1_cmd;
reg [5:0] b1_commit_tag;
reg [3:0] b1_cc_afe;
reg [3:0] b1_flags_regname;
reg [5:0] b1_destination_regname;
reg [4:0] b1_logic_destination;
reg [5:0] b1_source0;
reg [31:0] b1_source1;
reg [5:0] b1_adv_data;
reg b1_source0_flags;
reg b1_source1_imm;
reg b1_ex_sys_adder;
reg b1_ex_sys_ldst;
reg b1_ex_logic;
reg b1_ex_shift;
reg b1_ex_adder;
reg b1_ex_mul;
reg b1_ex_sdiv;
reg b1_ex_udiv;
reg b1_ex_ldst;
reg b1_ex_branch;
reg [31:0] b_pc;
//Scheduler State
reg [1:0] b_scheduler_state;
//Lock
wire this_lock;
wire [6:0] check_counter;
/****************************************
LOCK
****************************************/
assign check_counter = w_commit_count[6:0] + 7'h02; //2011/12/18
assign this_lock = iNEXT_LOCK | check_counter[6] == 1'b1;//2011/12/18 iNEXT_LOCK | w_commit_count[6:5] == 2'b01;//2011/12/17 iNEXT_LOCK | w_commit_count[6] == 1'b1;
/****************************************
Next <-> Previous (Register Free List)
****************************************/
//parameter is N, DEPTH, DEPTH_N
mist1032sa_sync_fifo #(4, 4, 2) FRAG_REG_FREELIST0(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iREMOVE(iEXCEPTION_RESTART),
.oCOUNT(oFLAG_REGISTER_0_COUNT),
.iWR_EN(iFLAG_REGISTER_0_WR),
.iWR_DATA(iFLAG_REGISTER_0_NUM),
.oWR_FULL(oFLAG_REGISTER_0_FULL),
.iRD_EN(iFLAG_REGISTER_0_RD),
.oRD_DATA(oFLAG_REGISTER_0_NUM),
.oRD_EMPTY(oFLAG_REGISTER_0_EMPTY)
);
//parameter is N, DEPTH, DEPTH_N
mist1032sa_sync_fifo #(4, 4, 2) FRAG_REG_FREELIST1(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iREMOVE(iEXCEPTION_RESTART),
.oCOUNT(oFLAG_REGISTER_1_COUNT),
.iWR_EN(iFLAG_REGISTER_1_WR),
.iWR_DATA(iFLAG_REGISTER_1_NUM),
.oWR_FULL(oFLAG_REGISTER_1_FULL),
.iRD_EN(iFLAG_REGISTER_1_RD),
.oRD_DATA(oFLAG_REGISTER_1_NUM),
.oRD_EMPTY(oFLAG_REGISTER_1_EMPTY)
);
mist1032sa_sync_fifo #(6, 8, 3) GR_REG_FREELIST0(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iREMOVE(iEXCEPTION_RESTART/*restart*/),
.oCOUNT(oOTHER_REGISTER_0_COUNT),
.iWR_EN(iOTHER_REGISTER_0_WR),
.iWR_DATA(iOTHER_REGISTER_0_NUM),
.oWR_FULL(oOTHER_REGISTER_0_FULL),
.iRD_EN(iOTHER_REGISTER_0_RD),
.oRD_DATA(oOTHER_REGISTER_0_NUM),
.oRD_EMPTY(oOTHER_REGISTER_0_EMPTY)
);
mist1032sa_sync_fifo #(6, 8, 3) GR_REG_FREELIST1(
.iCLOCK(iCLOCK), .inRESET(inRESET),
.iREMOVE(iEXCEPTION_RESTART/*restart*/),
.oCOUNT(oOTHER_REGISTER_1_COUNT),
.iWR_EN(iOTHER_REGISTER_1_WR),
.iWR_DATA(iOTHER_REGISTER_1_NUM),
.oWR_FULL(oOTHER_REGISTER_1_FULL),
.iRD_EN(iOTHER_REGISTER_1_RD),
.oRD_DATA(oOTHER_REGISTER_1_NUM),
.oRD_EMPTY(oOTHER_REGISTER_1_EMPTY)
);
/****************************************
Commit Id Info
****************************************/
assign w_commit_id_n0_valid = (w_commit_offset == 3'h4 || w_commit_offset == 3'h3 || w_commit_offset == 3'h2 || w_commit_offset == 3'h1 || iEXCEPTION_RESTART/*iranai kamo sirenai*/)? 1'b1 : 1'b0;
assign w_commit_id_n1_valid = (w_commit_offset == 3'h4 || w_commit_offset == 3'h3 || w_commit_offset == 3'h2)? 1'b1 : 1'b0;
assign w_commit_id_n2_valid = (w_commit_offset == 3'h4 || w_commit_offset == 3'h3)? 1'b1 : 1'b0;
assign w_commit_id_n3_valid = (w_commit_offset == 3'h4)? 1'b1 : 1'b0;
assign w_commit_id_n0 = w_commit_pointer + 6'h00;
assign w_commit_id_n1 = w_commit_pointer + 6'h01;
assign w_commit_id_n2 = w_commit_pointer + 6'h02;
assign w_commit_id_n3 = w_commit_pointer + 6'h03;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_commit_id_n0_valid <= 1'b0;
b_commit_id_n1_valid <= 1'b0;
b_commit_id_n2_valid <= 1'b0;
b_commit_id_n3_valid <= 1'b0;
b_commit_id_n0 <= {6{1'b0}};
b_commit_id_n1 <= {6{1'b0}};
b_commit_id_n2 <= {6{1'b0}};
b_commit_id_n3 <= {6{1'b0}};
b_commit_lregname_n0 <= {5{1'b0}};
b_commit_lregname_n1 <= {5{1'b0}};
b_commit_lregname_n2 <= {5{1'b0}};
b_commit_lregname_n3 <= {5{1'b0}};
b_commit_pregname_n0 <= {6{1'b0}};
b_commit_pregname_n1 <= {6{1'b0}};
b_commit_pregname_n2 <= {6{1'b0}};
b_commit_pregname_n3 <= {6{1'b0}};
b_commit_writeback_n0 <= 1'b0;
b_commit_writeback_n1 <= 1'b0;
b_commit_writeback_n2 <= 1'b0;
b_commit_writeback_n3 <= 1'b0;
b_commit_dest_sysreg_n0 <= 1'b0;
b_commit_dest_sysreg_n1 <= 1'b0;
b_commit_dest_sysreg_n2 <= 1'b0;
b_commit_dest_sysreg_n3 <= 1'b0;
b_commit_flags_make_flags_n0 <= 1'b0;
b_commit_flags_make_flags_n1 <= 1'b0;
b_commit_flags_make_flags_n2 <= 1'b0;
b_commit_flags_make_flags_n3 <= 1'b0;
b_commit_flags_p_regname_n0 <= 4'h0;
b_commit_flags_p_regname_n1 <= 4'h0;
b_commit_flags_p_regname_n2 <= 4'h0;
b_commit_flags_p_regname_n3 <= 4'h0;
end
else begin
b_commit_id_n0_valid <= w_commit_id_n0_valid;
b_commit_id_n1_valid <= w_commit_id_n1_valid;
b_commit_id_n2_valid <= w_commit_id_n2_valid;
b_commit_id_n3_valid <= w_commit_id_n3_valid;
b_commit_id_n0 <= w_commit_id_n0;
b_commit_id_n1 <= w_commit_id_n1;
b_commit_id_n2 <= w_commit_id_n2;
b_commit_id_n3 <= w_commit_id_n3;
b_commit_lregname_n0 <= entry_info_logic_destination[w_commit_id_n0];
b_commit_lregname_n1 <= entry_info_logic_destination[w_commit_id_n1];
b_commit_lregname_n2 <= entry_info_logic_destination[w_commit_id_n2];
b_commit_lregname_n3 <= entry_info_logic_destination[w_commit_id_n3];
b_commit_pregname_n0 <= entry_info_destination_regname[w_commit_id_n0];
b_commit_pregname_n1 <= entry_info_destination_regname[w_commit_id_n1];
b_commit_pregname_n2 <= entry_info_destination_regname[w_commit_id_n2];
b_commit_pregname_n3 <= entry_info_destination_regname[w_commit_id_n3];
b_commit_writeback_n0 <= entry_info_writeback[w_commit_id_n0];
b_commit_writeback_n1 <= entry_info_writeback[w_commit_id_n1];
b_commit_writeback_n2 <= entry_info_writeback[w_commit_id_n2];
b_commit_writeback_n3 <= entry_info_writeback[w_commit_id_n3];
b_commit_dest_sysreg_n0 <= entry_info_dest_sysreg[w_commit_id_n0];
b_commit_dest_sysreg_n1 <= entry_info_dest_sysreg[w_commit_id_n1];
b_commit_dest_sysreg_n2 <= entry_info_dest_sysreg[w_commit_id_n2];
b_commit_dest_sysreg_n3 <= entry_info_dest_sysreg[w_commit_id_n3];
b_commit_flags_make_flags_n0 <= entry_info_make_flags[w_commit_id_n0];
b_commit_flags_make_flags_n1 <= entry_info_make_flags[w_commit_id_n1];
b_commit_flags_make_flags_n2 <= entry_info_make_flags[w_commit_id_n2];
b_commit_flags_make_flags_n3 <= entry_info_make_flags[w_commit_id_n3];
b_commit_flags_p_regname_n0 <= entry_info_flags_regname[w_commit_id_n0];
b_commit_flags_p_regname_n1 <= entry_info_flags_regname[w_commit_id_n1];
b_commit_flags_p_regname_n2 <= entry_info_flags_regname[w_commit_id_n2];
b_commit_flags_p_regname_n3 <= entry_info_flags_regname[w_commit_id_n3];
end
end //always
/****************************************
Next Stage Buffer
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
//Pipeline0
b0_valid <= 1'b0;
b0_source0_active <= 1'b0;
b0_source1_active <= 1'b0;
b0_source0_sysreg <= 1'b0;
b0_source1_sysreg <= 1'b0;
b0_source0_sysreg_rename <= 1'b0;
b0_source1_sysreg_rename <= 1'b0;
b0_adv_active <= 1'b0;
b0_destination_sysreg <= 1'b0;
b0_data_writeback <= 1'b0;
b0_flags_writeback <= 1'b0;
b0_cmd <= {5{1'b0}};
b0_commit_tag <= {6{1'b0}};
b0_cc_afe <= {4{1'b0}};
b0_flags_regname <= 4'h0;
b0_destination_regname <= {6{1'b0}};
b0_logic_destination <= {5{1'b0}};
b0_source0 <= {6{1'b0}};
b0_source1 <= {32{1'b0}};
b0_adv_data <= 6'h0;
b0_source0_flags <= 1'b0;
b0_source1_imm <= 1'b0;
b0_ex_sys_adder <= 1'b0;
b0_ex_sys_ldst <= 1'b0;
b0_ex_logic <= 1'b0;
b0_ex_shift <= 1'b0;
b0_ex_adder <= 1'b0;
b0_ex_mul <= 1'b0;
b0_ex_sdiv <= 1'b0;
b0_ex_udiv <= 1'b0;
b0_ex_ldst <= 1'b0;
b0_ex_branch <= 1'b0;
//Pipeline1
b1_valid <= 1'b0;
b1_source0_active <= 1'b0;
b1_source1_active <= 1'b0;
b1_source0_sysreg <= 1'b0;
b1_source1_sysreg <= 1'b0;
b1_source0_sysreg_rename <= 1'b0;
b1_source1_sysreg_rename <= 1'b0;
b1_adv_active <= 1'b0;
b1_destination_sysreg <= 1'b0;
b1_data_writeback <= 1'b0;
b1_flags_writeback <= 1'b0;
b1_cmd <= {5{1'b0}};
b1_commit_tag <= {6{1'b0}};
b1_cc_afe <= {4{1'b0}};
b1_flags_regname <= 4'h0;
b1_destination_regname <= {6{1'b0}};
b1_logic_destination <= {5{1'b0}};
b1_source0 <= {6{1'b0}};
b1_source1 <= {32{1'b0}};
b1_adv_data <= 6'h0;
b1_source0_flags <= 1'b0;
b1_source1_imm <= 1'b0;
b1_ex_sys_adder <= 1'b0;
b1_ex_sys_ldst <= 1'b0;
b1_ex_logic <= 1'b0;
b1_ex_shift <= 1'b0;
b1_ex_adder <= 1'b0;
b1_ex_mul <= 1'b0;
b1_ex_sdiv <= 1'b0;
b1_ex_udiv <= 1'b0;
b1_ex_ldst <= 1'b0;
b1_ex_branch <= 1'b0;
b_pc <= {32{1'b0}};
end
else if(iEXCEPTION_EVENT)begin
//Pipeline0
b0_valid <= 1'b0;
b0_source0_active <= 1'b0;
b0_source1_active <= 1'b0;
b0_source0_sysreg <= 1'b0;
b0_source1_sysreg <= 1'b0;
b0_source0_sysreg_rename <= 1'b0;
b0_source1_sysreg_rename <= 1'b0;
b0_adv_active <= 1'b0;
b0_destination_sysreg <= 1'b0;
b0_data_writeback <= 1'b0;
b0_flags_writeback <= 1'b0;
b0_cmd <= {5{1'b0}};
b0_commit_tag <= {6{1'b0}};
b0_cc_afe <= {4{1'b0}};
b0_flags_regname <= 4'h0;
b0_destination_regname <= {6{1'b0}};
b0_logic_destination <= {5{1'b0}};
b0_source0 <= {6{1'b0}};
b0_source1 <= {32{1'b0}};
b0_adv_data <= 6'h0;
b0_source0_flags <= 1'b0;
b0_source1_imm <= 1'b0;
b0_ex_sys_adder <= 1'b0;
b0_ex_sys_ldst <= 1'b0;
b0_ex_logic <= 1'b0;
b0_ex_shift <= 1'b0;
b0_ex_adder <= 1'b0;
b0_ex_mul <= 1'b0;
b0_ex_sdiv <= 1'b0;
b0_ex_udiv <= 1'b0;
b0_ex_ldst <= 1'b0;
b0_ex_branch <= 1'b0;
//Pipeline1
b1_valid <= 1'b0;
b1_source0_active <= 1'b0;
b1_source1_active <= 1'b0;
b1_source0_sysreg <= 1'b0;
b1_source1_sysreg <= 1'b0;
b1_source0_sysreg_rename <= 1'b0;
b1_source1_sysreg_rename <= 1'b0;
b1_adv_active <= 1'b0;
b1_destination_sysreg <= 1'b0;
b1_data_writeback <= 1'b0;
b1_flags_writeback <= 1'b0;
b1_cmd <= {5{1'b0}};
b1_commit_tag <= {6{1'b0}};
b1_cc_afe <= {4{1'b0}};
b1_flags_regname <= 4'h0;
b1_destination_regname <= {6{1'b0}};
b1_logic_destination <= {5{1'b0}};
b1_source0 <= {6{1'b0}};
b1_source1 <= {32{1'b0}};
b1_adv_data <= 6'h0;
b1_source0_flags <= 1'b0;
b1_source1_imm <= 1'b0;
b1_ex_sys_adder <= 1'b0;
b1_ex_sys_ldst <= 1'b0;
b1_ex_logic <= 1'b0;
b1_ex_shift <= 1'b0;
b1_ex_adder <= 1'b0;
b1_ex_mul <= 1'b0;
b1_ex_sdiv <= 1'b0;
b1_ex_udiv <= 1'b0;
b1_ex_ldst <= 1'b0;
b1_ex_branch <= 1'b0;
b_pc <= {32{1'b0}};
end
else begin
if(!/*iNEXT_LOCK*/this_lock)begin
//***Instruction0***//
b0_valid <= iPREVIOUS_0_VALID;
b0_source0_active <= iPREVIOUS_0_SOURCE0_ACTIVE;
b0_source1_active <= iPREVIOUS_0_SOURCE1_ACTIVE;
b0_source0_sysreg <= iPREVIOUS_0_SOURCE0_SYSREG;
b0_source1_sysreg <= iPREVIOUS_0_SOURCE1_SYSREG;
b0_source0_sysreg_rename <= iPREVIOUS_0_SOURCE0_SYSREG_RENAME;
b0_source1_sysreg_rename <= iPREVIOUS_0_SOURCE1_SYSREG_RENAME;
b0_adv_active <= iPREVIOUS_0_ADV_ACTIVE;
b0_destination_sysreg <= iPREVIOUS_0_DESTINATION_SYSREG;
b0_data_writeback <= iPREVIOUS_0_WRITEBACK;
b0_flags_writeback <= iPREVIOUS_0_FLAGS_WRITEBACK;
b0_cmd <= iPREVIOUS_0_CMD;
b0_commit_tag <= {6{1'b0}};
b0_cc_afe <= iPREVIOUS_0_CC_AFE;
b0_flags_regname <= iPREVIOUS_0_FLAGS_REGNAME;
b0_destination_regname <= iPREVIOUS_0_DESTINATION_REGNAME;
b0_logic_destination <= iPREVIOUS_0_LOGIC_DESTINATION;
b0_source0 <= iPREVIOUS_0_SOURCE0;
b0_source1 <= iPREVIOUS_0_SOURCE1;
b0_adv_data <= iPREVIOUS_0_ADV_DATA;
b0_source0_flags <= iPREVIOUS_0_SOURCE0_FLAGS;
b0_source1_imm <= iPREVIOUS_0_SOURCE1_IMM;
b0_ex_sys_adder <= iPREVIOUS_0_EX_SYS_ADDER;
b0_ex_sys_ldst <= iPREVIOUS_0_EX_SYS_LDST;
b0_ex_logic <= iPREVIOUS_0_EX_LOGIC;
b0_ex_shift <= iPREVIOUS_0_EX_SHIFT;
b0_ex_adder <= iPREVIOUS_0_EX_ADDER;
b0_ex_mul <= iPREVIOUS_0_EX_MUL;
b0_ex_sdiv <= iPREVIOUS_0_EX_SDIV;
b0_ex_udiv <= iPREVIOUS_0_EX_UDIV;
b0_ex_ldst <= iPREVIOUS_0_EX_LDST;
b0_ex_branch <= iPREVIOUS_0_EX_BRANCH;
//***Instruction1***//
b1_valid <= iPREVIOUS_1_VALID;
b1_source0_active <= iPREVIOUS_1_SOURCE0_ACTIVE;
b1_source1_active <= iPREVIOUS_1_SOURCE1_ACTIVE;
b1_source0_sysreg <= iPREVIOUS_1_SOURCE0_SYSREG;
b1_source1_sysreg <= iPREVIOUS_1_SOURCE1_SYSREG;
b1_source0_sysreg_rename <= iPREVIOUS_1_SOURCE0_SYSREG_RENAME;
b1_source1_sysreg_rename <= iPREVIOUS_1_SOURCE1_SYSREG_RENAME;
b1_adv_active <= iPREVIOUS_1_ADV_ACTIVE;
b1_destination_sysreg <= iPREVIOUS_1_DESTINATION_SYSREG;
b1_data_writeback <= iPREVIOUS_1_WRITEBACK;
b1_flags_writeback <= iPREVIOUS_1_FLAGS_WRITEBACK;
b1_cmd <= iPREVIOUS_1_CMD;
b1_commit_tag <= {6{1'b0}};
b1_cc_afe <= iPREVIOUS_1_CC_AFE;
b1_flags_regname <= iPREVIOUS_1_FLAGS_REGNAME;
b1_destination_regname <= iPREVIOUS_1_DESTINATION_REGNAME;
b1_logic_destination <= iPREVIOUS_1_LOGIC_DESTINATION;
b1_source0 <= iPREVIOUS_1_SOURCE0;
b1_source1 <= iPREVIOUS_1_SOURCE1;
b1_adv_data <= iPREVIOUS_1_ADV_DATA;
b1_source0_flags <= iPREVIOUS_1_SOURCE0_FLAGS;
b1_source1_imm <= iPREVIOUS_1_SOURCE1_IMM;
b1_ex_sys_adder <= iPREVIOUS_1_EX_SYS_ADDER;
b1_ex_sys_ldst <= iPREVIOUS_1_EX_SYS_LDST;
b1_ex_logic <= iPREVIOUS_1_EX_LOGIC;
b1_ex_shift <= iPREVIOUS_1_EX_SHIFT;
b1_ex_adder <= iPREVIOUS_1_EX_ADDER;
b1_ex_mul <= iPREVIOUS_1_EX_MUL;
b1_ex_sdiv <= iPREVIOUS_1_EX_SDIV;
b1_ex_udiv <= iPREVIOUS_1_EX_UDIV;
b1_ex_ldst <= iPREVIOUS_1_EX_LDST;
b1_ex_branch <= iPREVIOUS_1_EX_BRANCH;
b_pc <= iPREVIOUS_PC;
end
end
end //always
/****************************************
Scheduler State
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_scheduler_state <= PL_STT_NORMAL;
end
else begin
case(b_scheduler_state)
PL_STT_NORMAL:
begin
if(iEXCEPTION_EVENT)begin
b_scheduler_state <= PL_STT_EXCEPTION;
end
end
PL_STT_EXCEPTION:
begin
if(iEXCEPTION_RESTART)begin
b_scheduler_state <= PL_STT_NORMAL;
end
end
endcase
end
end
/****************************************
Commit List
****************************************/
generate
for(i = 0; i < 64; i = i + 1)begin : COMMIT_ENTRY
scheduler1_commit_entry #(i[5:0]) COMMIT_ENTRY (
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Regist
.iLOCK(this_lock),
.iRESTART_VALID(iEXCEPTION_RESTART),
.iREGIST_POINTER(w_register_pointer),
.iREGIST_0_VALID(iPREVIOUS_0_VALID & !this_lock),
.iREGIST_0_MAKE_FLAGS(iPREVIOUS_0_FLAGS_WRITEBACK),
.iREGIST_0_WRITEBACK(iPREVIOUS_0_WRITEBACK),
.iREGIST_0_FLAGS_PREG_POINTER(iPREVIOUS_0_FLAGS_REGNAME),
.iREGIST_0_DEST_PREG_POINTER(iPREVIOUS_0_DESTINATION_REGNAME),
.iREGIST_0_DEST_LREG_POINTER(iPREVIOUS_0_LOGIC_DESTINATION),
.iREGIST_0_DEST_SYSREG(iPREVIOUS_0_DESTINATION_SYSREG),
.iREGIST_0_EX_BRANCH(iPREVIOUS_0_EX_BRANCH),
.iREGIST_1_VALID(iPREVIOUS_0_VALID & iPREVIOUS_1_VALID & !this_lock),
.iREGIST_1_MAKE_FLAGS(iPREVIOUS_1_FLAGS_WRITEBACK),
.iREGIST_1_WRITEBACK(iPREVIOUS_1_WRITEBACK),
.iREGIST_1_FLAGS_PREG_POINTER(iPREVIOUS_1_FLAGS_REGNAME),
.iREGIST_1_DEST_PREG_POINTER(iPREVIOUS_1_DESTINATION_REGNAME),
.iREGIST_1_DEST_LREG_POINTER(iPREVIOUS_1_LOGIC_DESTINATION),
.iREGIST_1_DEST_SYSREG(iPREVIOUS_1_DESTINATION_SYSREG),
.iREGIST_1_EX_BRANCH(iPREVIOUS_1_EX_BRANCH),
.iREGIST_PC(iPREVIOUS_PC),
.iCOMMIT_VALID(entry_commit_valid[i[5:0]]),
.iEXEND_ALU0_VALID(iSCHE1_EX_BRANCH_VALID),
.iEXEND_ALU0_COMMIT_TAG(iSCHE1_EX_BRANCH_COMMIT_TAG),
.iEXEND_ALU1_VALID(iSCHE1_EX_ALU1_VALID),
.iEXEND_ALU1_COMMIT_TAG(iSCHE1_EX_ALU1_COMMIT_TAG),
.iEXEND_ALU2_VALID(iSCHE1_EX_ALU2_VALID),
.iEXEND_ALU2_COMMIT_TAG(iSCHE1_EX_ALU2_COMMIT_TAG),
.iEXEND_ALU3_VALID(iSCHE1_EX_ALU3_VALID),
.iEXEND_ALU3_COMMIT_TAG(iSCHE1_EX_ALU3_COMMIT_TAG),
//RollBack Info
.oINFO_VALID(entry_info_entry_valid[i[5:0]]),
.oINFO_MAKE_FLAGS_VALID(entry_info_make_flags[i[5:0]]),
.oINFO_WRITEBACK_VALID(entry_info_writeback[i[5:0]]),
.oINFO_PC(entry_info_pc[i[5:0]]),
.oINFO_FLAGS_PREG_POINTER(entry_info_flags_regname[i[5:0]]),
.oINFO_DEST_PREG_POINTER(entry_info_destination_regname[i[5:0]]),
.oINFO_DEST_LREG_POINTER(entry_info_logic_destination[i[5:0]]),
.oINFO_DEST_SYSREG(entry_info_dest_sysreg[i[5:0]]),
.oINFO_EX_BRANCH(entry_info_ex_branch[i[5:0]]),
.oINFO_EX_END(entry_info_ex_end[i[5:0]]),
.oINFO_FREE(oFREE_REGISTER[i[5:0]])
);
end
endgenerate
/***************************************************
Commit List
***************************************************/
assign {entry_commit_3_valid, entry_commit_3_num,
entry_commit_2_valid, entry_commit_2_num,
entry_commit_1_valid, entry_commit_1_num,
entry_commit_0_valid, entry_commit_0_num} = func_entry_commit_valid(w_commit_pointer, w_commit_offset);
function [27:0] func_entry_commit_valid;
/*
[27]
[26:21]
[20]
[19:14]
[13]
[12:7]
[6]
[5:0]
*/
input [5:0] func_entry_commit_valid_commit_pointer;
input [2:0] func_entry_commit_valid_commit_offset;
begin
func_entry_commit_valid [26:21] = func_entry_commit_valid_commit_pointer + {{3{1'b0}}, 3'h3};
func_entry_commit_valid [19:14] = func_entry_commit_valid_commit_pointer + {{3{1'b0}}, 3'h2};
func_entry_commit_valid [12:7] = func_entry_commit_valid_commit_pointer + {{3{1'b0}}, 3'h1};
func_entry_commit_valid [5:0] = func_entry_commit_valid_commit_pointer + {{3{1'b0}}, 3'h0};
if(func_entry_commit_valid_commit_offset == 3'h1)begin
func_entry_commit_valid [6] = 1'b1;
func_entry_commit_valid [13] = 1'b0;
func_entry_commit_valid [20] = 1'b0;
func_entry_commit_valid [27] = 1'b0;
end
else if(func_entry_commit_valid_commit_offset == 3'h2)begin
func_entry_commit_valid [6] = 1'b1;
func_entry_commit_valid [13] = 1'b1;
func_entry_commit_valid [20] = 1'b0;
func_entry_commit_valid [27] = 1'b0;
end
else if(func_entry_commit_valid_commit_offset == 3'h3)begin
func_entry_commit_valid [6] = 1'b1;
func_entry_commit_valid [13] = 1'b1;
func_entry_commit_valid [20] = 1'b1;
func_entry_commit_valid [27] = 1'b0;
end
else if(func_entry_commit_valid_commit_offset == 3'h4)begin
func_entry_commit_valid [6] = 1'b1;
func_entry_commit_valid [13] = 1'b1;
func_entry_commit_valid [20] = 1'b1;
func_entry_commit_valid [27] = 1'b1;
end
else begin
func_entry_commit_valid [6] = 1'b0;
func_entry_commit_valid [13] = 1'b0;
func_entry_commit_valid [20] = 1'b0;
func_entry_commit_valid [27] = 1'b0;
end
end
endfunction
generate
for(i = 0; i < 64; i = i + 1)begin : ENTRY_COMMIT_VALID
assign entry_commit_valid[i[5:0]] = ((entry_commit_0_valid & (entry_commit_0_num == i[5:0])) | (entry_commit_1_valid & (entry_commit_1_num == i[5:0])) |
(entry_commit_2_valid & (entry_commit_2_num == i[5:0])) | (entry_commit_3_valid & (entry_commit_3_num == i[5:0])))? 1'b1 : 1'b0;
end
endgenerate
//Exception Protect Check(Non Core Exceotion Block)
assign exception_protect = func_exception_protect_check(
w_register_pointer,
w_commit_pointer,
w_commit_offset,
entry_info_entry_valid[w_commit_pointer + 6'h1],
entry_info_entry_valid[w_commit_pointer + 6'h2],
entry_info_entry_valid[w_commit_pointer + 6'h3],
entry_info_entry_valid[w_commit_pointer + 6'h4],
entry_info_entry_valid[w_commit_pointer + 6'h5],
entry_info_ex_branch[w_commit_pointer + 6'h1],
entry_info_ex_branch[w_commit_pointer + 6'h2],
entry_info_ex_branch[w_commit_pointer + 6'h3],
entry_info_ex_branch[w_commit_pointer + 6'h4],
entry_info_ex_branch[w_commit_pointer + 6'h5]
);
function func_exception_protect_check;
input [5:0] func_regist_pointer;
input [5:0] func_commit_pointer;
input [2:0] func_cntry_commit_offset;
input func_commit_entry1_ex_branch_active;
input func_commit_entry2_ex_branch_active;
input func_commit_entry3_ex_branch_active;
input func_commit_entry4_ex_branch_active;
input func_commit_entry5_ex_branch_active;
input func_commit_entry1_ex_branch_flag;
input func_commit_entry2_ex_branch_flag;
input func_commit_entry3_ex_branch_flag;
input func_commit_entry4_ex_branch_flag;
input func_commit_entry5_ex_branch_flag;
reg [5:0] func_reg_regist_pointer_inc;
begin
//Initial
func_reg_regist_pointer_inc = func_commit_pointer + 6'h1;
if((func_regist_pointer == func_commit_pointer) || (func_regist_pointer == func_reg_regist_pointer_inc[5:0]))begin
func_exception_protect_check = 1'b1;
end
else begin
case(func_cntry_commit_offset)
3'h0:
begin
if(func_commit_entry1_ex_branch_flag || !func_commit_entry1_ex_branch_active)begin
func_exception_protect_check = 1'b1;
end
else begin
func_exception_protect_check = 1'b0;
end
end
3'h1:
begin
if((!func_commit_entry1_ex_branch_flag && func_commit_entry2_ex_branch_flag) || !func_commit_entry2_ex_branch_active)begin
func_exception_protect_check = 1'b1;
end
else begin
func_exception_protect_check = 1'b0;
end
end
3'h2:
begin
if((!func_commit_entry2_ex_branch_flag && func_commit_entry3_ex_branch_flag) || !func_commit_entry3_ex_branch_active)begin
func_exception_protect_check = 1'b1;
end
else begin
func_exception_protect_check = 1'b0;
end
end
3'h3:
begin
if((!func_commit_entry3_ex_branch_flag && func_commit_entry4_ex_branch_flag) || !func_commit_entry4_ex_branch_active)begin
func_exception_protect_check = 1'b1;
end
else begin
func_exception_protect_check = 1'b0;
end
end
3'h4:
begin
if((!func_commit_entry4_ex_branch_flag && func_commit_entry5_ex_branch_flag) || !func_commit_entry5_ex_branch_active)begin
func_exception_protect_check = 1'b1;
end
else begin
func_exception_protect_check = 1'b0;
end
end
endcase
end
end
endfunction
/*
assign exception_protect = func_exception_protect_check(
w_register_pointer,
w_commit_pointer,
w_commit_offset,
entry_info_ex_branch[w_commit_pointer],
entry_info_ex_branch[w_commit_pointer + 6'h1],
entry_info_ex_branch[w_commit_pointer + 6'h2],
entry_info_ex_branch[w_commit_pointer + 6'h3],
entry_info_ex_branch[w_commit_pointer + 6'h4]
);
function func_exception_protect_check;
input [5:0] func_regist_pointer;
input [5:0] func_commit_pointer;
input [1:0] func_cntry_commit_offset;
input func_commit_entry0_ex_branch_flag; //NOW
input func_commit_entry1_ex_branch_flag;
input func_commit_entry2_ex_branch_flag;
input func_commit_entry3_ex_branch_flag;
input func_commit_entry4_ex_branch_flag;
begin
if(func_regist_pointer == func_commit_pointer || func_regist_pointer == (func_commit_pointer + 6'h1))begin
func_exception_protect_check = 1'b1;
end
else begin
case(func_cntry_commit_offset)
2'h0:
begin
if(!func_commit_entry0_ex_branch_flag && func_commit_entry1_ex_branch_flag)begin
func_exception_protect_check = 1'b1;
end
else begin
func_exception_protect_check = 1'b0;
end
end
2'h1:
begin
if(!func_commit_entry1_ex_branch_flag && func_commit_entry2_ex_branch_flag)begin
func_exception_protect_check = 1'b1;
end
else begin
func_exception_protect_check = 1'b0;
end
end
2'h2:
begin
if(!func_commit_entry2_ex_branch_flag && func_commit_entry3_ex_branch_flag)begin
func_exception_protect_check = 1'b1;
end
else begin
func_exception_protect_check = 1'b0;
end
end
2'h3:
begin
if(!func_commit_entry3_ex_branch_flag && func_commit_entry4_ex_branch_flag)begin
func_exception_protect_check = 1'b1;
end
else begin
func_exception_protect_check = 1'b0;
end
end
endcase
end
end
endfunction
*/
//Commit Count
assign w_commit_offset = func_entry_commit_count
(
entry_info_ex_end[w_commit_pointer],
entry_info_ex_end[w_commit_pointer + 6'h1],
entry_info_ex_end[w_commit_pointer + 6'h2],
entry_info_ex_end[w_commit_pointer + 6'h3],
w_commit_pointer,
(iEXCEPTION_EVENT || (b_scheduler_state == PL_STT_EXCEPTION) || iEXCEPTION_RESTART),
iEXCEPTION_COMMIT_TAG
);
function [2:0] func_entry_commit_count;
//Execution End Infomation
input func_commit_entry_ex_end0;
input func_commit_entry_ex_end1;
input func_commit_entry_ex_end2;
input func_commit_entry_ex_end3;
//Now Commit Pointer
input [5:0] func_now_commit_pointer;
//Exception Request
input func_exception_request_valid;
input [5:0] func_exception_request_pointer;
//Internal(Private)
reg [2:0] pri_exend_count;
reg [2:0] pri_max_count;
begin
//Ex End Count
if(func_commit_entry_ex_end0)begin
if(func_commit_entry_ex_end1)begin
if(func_commit_entry_ex_end2)begin
if(func_commit_entry_ex_end3)begin
pri_exend_count = 3'h4;
end
else begin
pri_exend_count = 3'h3;
end
end
else begin
pri_exend_count = 3'h2;
end
end
else begin
pri_exend_count = 3'h1;
end
end
else begin
pri_exend_count = 3'h0;
end
//Max Count
if(func_now_commit_pointer != func_exception_request_pointer)begin
if(func_now_commit_pointer + 3'h1 != func_exception_request_pointer)begin
if(func_now_commit_pointer + 3'h2 != func_exception_request_pointer)begin
if(func_now_commit_pointer + 3'h3 != func_exception_request_pointer)begin
pri_max_count = 3'h4;
end
else begin
pri_max_count = 3'h3;
end
end
else begin
pri_max_count = 3'h2;
end
end
else begin
pri_max_count = 3'h1;
end
end
else begin
pri_max_count = 3'h0;
end
//Output Calc
if(!func_exception_request_valid)begin
func_entry_commit_count = pri_exend_count;
end
else begin
if(pri_exend_count <= pri_max_count)begin
func_entry_commit_count = pri_exend_count;
end
else begin
func_entry_commit_count = pri_max_count;
end
end
end
endfunction
assign w_commit_count = b_regist_pointer - b_commit_pointer;
//Commit & Regist Pointer
assign w_commit_pointer = b_commit_pointer[5:0];
assign w_register_pointer = b_regist_pointer[5:0];
assign ww_regist_pointer = bb_regist_pointer[5:0];
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_commit_pointer <= {7{1'b0}};
b_regist_pointer <= {7{1'b0}};
bb_regist_pointer <= {7{1'b0}};
end
else begin
if(iEXCEPTION_RESTART)begin
//Branch
b_regist_pointer <= ({1'b0, iEXCEPTION_COMMIT_TAG}) + 7'h01;
bb_regist_pointer <= b_regist_pointer;
b_commit_pointer <= ({1'b0, iEXCEPTION_COMMIT_TAG}) + 7'h01;
end
else begin
//Normal
b_commit_pointer <= b_commit_pointer + {3'h0, w_commit_offset};
if(!this_lock)begin
if(iPREVIOUS_0_VALID)begin
if(iPREVIOUS_1_VALID)begin
b_regist_pointer <= b_regist_pointer + 7'h02;
bb_regist_pointer <= b_regist_pointer;
end
else begin
b_regist_pointer <= b_regist_pointer + 7'h01;
bb_regist_pointer <= b_regist_pointer;
end
end
end
end
end
end //always
/**********************************************
Module Output
**********************************************/
//Module Info
assign oSTAGE_INFO_REGIST_POINTER = w_register_pointer;
assign oSTAGE_INFO_COMMIT_POINTER = w_commit_pointer;
//Commit Info
assign oINFO_COMMIT_COUNTER = w_commit_pointer;
assign oINFO_EXCEPTION_PROTECT = exception_protect; //1'b0 bug
wire [5:0] commit_pc_pointer = w_commit_pointer;
assign oFREE_CURRENT_PC = entry_info_pc[commit_pc_pointer];
assign oCOMMIT_OFFSET = w_commit_offset;
//Lock
assign oPREVIOUS_LOCK = this_lock;
//Stage Info
assign oSTAGE_INFO_0_VALID = b0_valid;
assign oSTAGE_INFO_1_VALID = b1_valid;
//RollBack Info
assign oRENAME_ROLLBACK_UPDATE_INFO0_VALID = b_commit_id_n0_valid && b_commit_writeback_n0;
assign oRENAME_ROLLBACK_UPDATE_INFO0_LREGNAME = b_commit_lregname_n0;
assign oRENAME_ROLLBACK_UPDATE_INFO0_PREGNAME = b_commit_pregname_n0;
assign oRENAME_ROLLBACK_UPDATE_INFO0_SYSREG = b_commit_dest_sysreg_n0;
assign oRENAME_ROLLBACK_UPDATE_INFO1_VALID = b_commit_id_n1_valid && b_commit_writeback_n1;
assign oRENAME_ROLLBACK_UPDATE_INFO1_LREGNAME = b_commit_lregname_n1;
assign oRENAME_ROLLBACK_UPDATE_INFO1_PREGNAME = b_commit_pregname_n1;
assign oRENAME_ROLLBACK_UPDATE_INFO1_SYSREG = b_commit_dest_sysreg_n1;
assign oRENAME_ROLLBACK_UPDATE_INFO2_VALID = b_commit_id_n2_valid && b_commit_writeback_n2;
assign oRENAME_ROLLBACK_UPDATE_INFO2_LREGNAME = b_commit_lregname_n2;
assign oRENAME_ROLLBACK_UPDATE_INFO2_PREGNAME = b_commit_pregname_n2;
assign oRENAME_ROLLBACK_UPDATE_INFO2_SYSREG = b_commit_dest_sysreg_n2;
assign oRENAME_ROLLBACK_UPDATE_INFO3_VALID = b_commit_id_n3_valid && b_commit_writeback_n3;
assign oRENAME_ROLLBACK_UPDATE_INFO3_LREGNAME = b_commit_lregname_n3;
assign oRENAME_ROLLBACK_UPDATE_INFO3_PREGNAME = b_commit_pregname_n3;
assign oRENAME_ROLLBACK_UPDATE_INFO3_SYSREG = b_commit_dest_sysreg_n3;
assign oFLAGR_RENAME_ROLLBACK_UPDATE_INFO0_VALID = b_commit_flags_make_flags_n0;
assign oFLAGR_RENAME_ROLLBACK_UPDATE_INFO0_PREGNAME = b_commit_flags_p_regname_n0;
assign oFLAGR_RENAME_ROLLBACK_UPDATE_INFO1_VALID = b_commit_flags_make_flags_n1;
assign oFLAGR_RENAME_ROLLBACK_UPDATE_INFO1_PREGNAME = b_commit_flags_p_regname_n1;
assign oFLAGR_RENAME_ROLLBACK_UPDATE_INFO2_VALID = b_commit_flags_make_flags_n2;
assign oFLAGR_RENAME_ROLLBACK_UPDATE_INFO2_PREGNAME = b_commit_flags_p_regname_n2;
assign oFLAGR_RENAME_ROLLBACK_UPDATE_INFO3_VALID = b_commit_flags_make_flags_n3;
assign oFLAGR_RENAME_ROLLBACK_UPDATE_INFO3_PREGNAME = b_commit_flags_p_regname_n3;
//Next-0
assign oNEXT_0_VALID = (!this_lock)? b0_valid && !iEXCEPTION_EVENT : 1'b0; //12/19 2:13 always@de this_lock or inext_loxk dotirawo tukauka mayota toki
assign oNEXT_0_SOURCE0_ACTIVE = b0_source0_active;
assign oNEXT_0_SOURCE1_ACTIVE = b0_source1_active;
assign oNEXT_0_SOURCE0_SYSREG = b0_source0_sysreg;
assign oNEXT_0_SOURCE1_SYSREG = b0_source1_sysreg;
assign oNEXT_0_SOURCE0_SYSREG_RENAME = b0_source0_sysreg_rename;
assign oNEXT_0_SOURCE1_SYSREG_RENAME = b0_source1_sysreg_rename;
assign oNEXT_0_ADV_ACTIVE = b0_adv_active;
assign oNEXT_0_DESTINATION_SYSREG = b0_destination_sysreg;
assign oNEXT_0_WRITEBACK = b0_data_writeback;
assign oNEXT_0_FLAGS_WRITEBACK = b0_flags_writeback;
assign oNEXT_0_CMD = b0_cmd;
assign oNEXT_0_COMMIT_TAG = ww_regist_pointer;
assign oNEXT_0_CC_AFE = b0_cc_afe;
assign oNEXT_0_FLAGS_REGNAME = b0_flags_regname;
assign oNEXT_0_DESTINATION_REGNAME = b0_destination_regname;
assign oNEXT_0_LOGIC_DESTINATION = b0_logic_destination;
assign oNEXT_0_SOURCE0 = b0_source0;
assign oNEXT_0_SOURCE1 = b0_source1;
assign oNEXT_0_ADV_DATA = b0_adv_data;
assign oNEXT_0_SOURCE0_FLAGS = b0_source0_flags;
assign oNEXT_0_SOURCE1_IMM = b0_source1_imm;
assign oNEXT_0_EX_SYS_ADDER = b0_ex_sys_adder;
assign oNEXT_0_EX_SYS_LDST = b0_ex_sys_ldst;
assign oNEXT_0_EX_LOGIC = b0_ex_logic;
assign oNEXT_0_EX_SHIFT = b0_ex_shift;
assign oNEXT_0_EX_ADDER = b0_ex_adder;
assign oNEXT_0_EX_MUL = b0_ex_mul;
assign oNEXT_0_EX_SDIV = b0_ex_sdiv;
assign oNEXT_0_EX_UDIV = b0_ex_udiv;
assign oNEXT_0_EX_LDST = b0_ex_ldst;
assign oNEXT_0_EX_BRANCH = b0_ex_branch;
//Next-1
assign oNEXT_1_VALID = (!this_lock)? b1_valid && !iEXCEPTION_EVENT : 1'b0; //12/19 2:13 always@de this_lock or inext_loxk dotirawo tukauka mayota toki
assign oNEXT_1_SOURCE0_ACTIVE = b1_source0_active;
assign oNEXT_1_SOURCE1_ACTIVE = b1_source1_active;
assign oNEXT_1_SOURCE0_SYSREG = b1_source0_sysreg;
assign oNEXT_1_SOURCE1_SYSREG = b1_source1_sysreg;
assign oNEXT_1_SOURCE0_SYSREG_RENAME = b1_source0_sysreg_rename;
assign oNEXT_1_SOURCE1_SYSREG_RENAME = b1_source1_sysreg_rename;
assign oNEXT_1_ADV_ACTIVE = b1_adv_active;
assign oNEXT_1_DESTINATION_SYSREG = b1_destination_sysreg;
assign oNEXT_1_WRITEBACK = b1_data_writeback;
assign oNEXT_1_FLAGS_WRITEBACK = b1_flags_writeback;
assign oNEXT_1_CMD = b1_cmd;
assign oNEXT_1_COMMIT_TAG = ww_regist_pointer + 6'h01;
assign oNEXT_1_CC_AFE = b1_cc_afe;
assign oNEXT_1_FLAGS_REGNAME = b1_flags_regname;
assign oNEXT_1_DESTINATION_REGNAME = b1_destination_regname;
assign oNEXT_1_LOGIC_DESTINATION = b1_logic_destination;
assign oNEXT_1_SOURCE0 = b1_source0;
assign oNEXT_1_SOURCE1 = b1_source1;
assign oNEXT_1_ADV_DATA = b1_adv_data;
assign oNEXT_1_SOURCE0_FLAGS = b1_source0_flags;
assign oNEXT_1_SOURCE1_IMM = b1_source1_imm;
assign oNEXT_1_EX_SYS_ADDER = b1_ex_sys_adder;
assign oNEXT_1_EX_SYS_LDST = b1_ex_sys_ldst;
assign oNEXT_1_EX_LOGIC = b1_ex_logic;
assign oNEXT_1_EX_SHIFT = b1_ex_shift;
assign oNEXT_1_EX_ADDER = b1_ex_adder;
assign oNEXT_1_EX_MUL = b1_ex_mul;
assign oNEXT_1_EX_SDIV = b1_ex_sdiv;
assign oNEXT_1_EX_UDIV = b1_ex_udiv;
assign oNEXT_1_EX_LDST = b1_ex_ldst;
assign oNEXT_1_EX_BRANCH = b1_ex_branch;
assign oNEXT_PC = b_pc;
//Commit Entry Vector
generate
for(i = 0; i < 64; i = i + 1)begin : COMMIT_VECTOR
assign oCOMMIT_ENTRY_COMMIT_VECTOR[i[5:0]] = (b_commit_id_n0_valid && i[5:0] == b_commit_id_n0) || (b_commit_id_n1_valid && i[5:0] == b_commit_id_n1) || (b_commit_id_n2_valid && i[5:0] == b_commit_id_n2) || (b_commit_id_n3_valid && i[5:0] == b_commit_id_n3)? 1'b1 : 1'b0;
end
endgenerate
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PS_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_PS_BLACKBOX_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$PS (
Q ,
D ,
CLK,
SET
);
output Q ;
input D ;
input CLK;
input SET;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PS_BLACKBOX_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module sends and receives data from the audio's and TV in's *
* control registers for the chips on Altera's DE2 board. Plus, it can *
* send and receive data from the TRDB_DC2 and TRDB_LCM add-on modules. *
* *
******************************************************************************/
`define USE_OB_MODE
//`define USE_OB_AUTO_INIT
//`define USE_OB_DE2_35_AUTO_INIT
//`define USE_AUTO_INIT
module nios_system_audio_config (
// Inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
// Bidirectionals
I2C_SDAT,
// Outputs
readdata,
waitrequest,
irq,
I2C_SCEN,
I2C_SCLK
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 1: 0] address;
input [ 3: 0] byteenable;
input read;
input write;
input [31: 0] writedata;
// Bidirectionals
inout I2C_SDAT;
// Outputs
output reg [31: 0] readdata;
output waitrequest;
output irq;
output I2C_SCEN;
output I2C_SCLK;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam DW = 26; // Serial protocol's datawidth
localparam CFG_TYPE = 8'h02;
localparam READ_MASK = {8'h00, 1'b1, 8'hFF, 1'b0, 8'h00, 1'b1};
localparam WRITE_MASK = {8'h00, 1'b1, 8'h00, 1'b1, 8'h00, 1'b1};
localparam RESTART_COUNTER = 'h9;
// Auto init parameters
localparam AIRS = 50; // Auto Init ROM's size
localparam AIAW = 5; // Auto Init ROM's address width
localparam AUD_LINE_IN_LC = 9'h01A;
localparam AUD_LINE_IN_RC = 9'h01A;
localparam AUD_LINE_OUT_LC = 9'h07B;
localparam AUD_LINE_OUT_RC = 9'h07B;
localparam AUD_ADC_PATH = 9'd149;
localparam AUD_DAC_PATH = 9'h006;
localparam AUD_POWER = 9'h000;
localparam AUD_DATA_FORMAT = 9'd65;
localparam AUD_SAMPLE_CTRL = 9'd24;
localparam AUD_SET_ACTIVE = 9'h001;
// Serial Bus Controller parameters
//parameter SBDW = 26; // Serial bus's datawidth
localparam SBCW = 4; // Serial bus counter's width
localparam SCCW = 11; // Slow clock's counter's width
// States for finite state machine
localparam STATE_0_IDLE = 3'h0,
STATE_1_PRE_WRITE = 3'h1,
STATE_2_WRITE_TRANSFER = 3'h2,
STATE_3_POST_WRITE = 3'h3,
STATE_4_PRE_READ = 3'h4,
STATE_5_READ_TRANSFER = 3'h5,
STATE_6_POST_READ = 3'h6;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire internal_reset;
// Auto init signals
wire [AIAW:0] rom_address;
wire [DW: 0] rom_data;
wire ack;
wire [DW: 0] auto_init_data;
wire auto_init_transfer_en;
wire auto_init_complete;
wire auto_init_error;
// Serial controller signals
wire [DW: 0] transfer_mask;
wire [DW: 0] data_to_controller;
wire [DW: 0] data_to_controller_on_restart;
wire [DW: 0] data_from_controller;
wire start_transfer;
wire transfer_complete;
// Internal Registers
reg [31: 0] control_reg;
reg [31: 0] address_reg;
reg [31: 0] data_reg;
reg start_external_transfer;
reg external_read_transfer;
reg [ 7: 0] address_for_transfer;
reg [ 1: 0] device_for_transfer;
// State Machine Registers
reg [ 2: 0] ns_serial_transfer;
reg [ 2: 0] s_serial_transfer;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (internal_reset)
s_serial_transfer <= STATE_0_IDLE;
else
s_serial_transfer <= ns_serial_transfer;
end
always @(*)
begin
// Defaults
ns_serial_transfer = STATE_0_IDLE;
case (s_serial_transfer)
STATE_0_IDLE:
begin
if (transfer_complete | ~auto_init_complete)
ns_serial_transfer = STATE_0_IDLE;
else if (write & (address == 2'h3))
ns_serial_transfer = STATE_1_PRE_WRITE;
else if (read & (address == 2'h3))
begin
if (control_reg[17:16] == 2'h0)
ns_serial_transfer = STATE_6_POST_READ;
else
ns_serial_transfer = STATE_4_PRE_READ;
end
else
ns_serial_transfer = STATE_0_IDLE;
end
STATE_1_PRE_WRITE:
begin
ns_serial_transfer = STATE_2_WRITE_TRANSFER;
end
STATE_2_WRITE_TRANSFER:
begin
if (transfer_complete)
ns_serial_transfer = STATE_3_POST_WRITE;
else
ns_serial_transfer = STATE_2_WRITE_TRANSFER;
end
STATE_3_POST_WRITE:
begin
ns_serial_transfer = STATE_0_IDLE;
end
STATE_4_PRE_READ:
begin
ns_serial_transfer = STATE_5_READ_TRANSFER;
end
STATE_5_READ_TRANSFER:
begin
if (transfer_complete)
ns_serial_transfer = STATE_6_POST_READ;
else
ns_serial_transfer = STATE_5_READ_TRANSFER;
end
STATE_6_POST_READ:
begin
ns_serial_transfer = STATE_0_IDLE;
end
default:
begin
ns_serial_transfer = STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output regsiters
always @(posedge clk)
begin
if (internal_reset)
readdata <= 32'h00000000;
else if (read)
begin
if (address == 2'h0)
readdata <= control_reg;
else if (address == 2'h1)
begin
readdata <= {8'h00, CFG_TYPE, 7'h00,
auto_init_complete & ~auto_init_error, 6'h00,
~start_external_transfer & auto_init_complete,
ack};
end
else if (address == 2'h2)
readdata <= address_reg;
else if (control_reg[17:16] == 2'h0)
readdata <= {23'h000000,
data_from_controller[10],
data_from_controller[ 8: 1]};
else
readdata <= {24'h000000, data_from_controller[ 8: 1]};
end
end
// Internal regsiters
always @(posedge clk)
begin
if (internal_reset)
begin
control_reg <= 32'h00000000;
address_reg <= 32'h00000000;
data_reg <= 32'h00000000;
end
else if (write & ~waitrequest)
begin
// Write to control register
if ((address == 2'h0) & byteenable[0])
control_reg[ 2: 1] <= writedata[ 2: 1];
if ((address == 2'h0) & byteenable[2])
control_reg[17:16] <= writedata[17:16];
// Write to address register
if ((address == 2'h2) & byteenable[0])
address_reg[ 7: 0] <= writedata[ 7: 0];
// Write to data register
if ((address == 2'h3) & byteenable[0])
data_reg[ 7: 0] <= writedata[ 7: 0];
if ((address == 2'h3) & byteenable[1])
data_reg[15: 8] <= writedata[15: 8];
if ((address == 2'h3) & byteenable[2])
data_reg[23:16] <= writedata[23:16];
if ((address == 2'h3) & byteenable[3])
data_reg[31:24] <= writedata[31:24];
end
end
always @(posedge clk)
begin
if (internal_reset)
begin
start_external_transfer <= 1'b0;
external_read_transfer <= 1'b0;
address_for_transfer <= 8'h00;
device_for_transfer <= 2'h0;
end
else if (transfer_complete)
begin
start_external_transfer <= 1'b0;
external_read_transfer <= 1'b0;
address_for_transfer <= 8'h00;
end
else if (s_serial_transfer == STATE_1_PRE_WRITE)
begin
start_external_transfer <= 1'b1;
external_read_transfer <= 1'b0;
address_for_transfer <= address_reg[7:0];
device_for_transfer <= control_reg[17:16];
end
else if (s_serial_transfer == STATE_4_PRE_READ)
begin
start_external_transfer <= 1'b1;
external_read_transfer <= 1'b1;
address_for_transfer <= address_reg[7:0];
device_for_transfer <= control_reg[17:16];
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign waitrequest =
((address == 2'h3) & write & (s_serial_transfer != STATE_1_PRE_WRITE)) |
((address == 2'h3) & read & (s_serial_transfer != STATE_6_POST_READ));
assign irq = control_reg[1] & ~start_external_transfer & auto_init_complete;
// Internal Assignments
assign internal_reset = reset |
((address == 2'h0) & write & byteenable[0] & writedata[0]);
// Signals to the serial controller
assign transfer_mask = WRITE_MASK;
assign data_to_controller =
(~auto_init_complete) ?
auto_init_data :
(device_for_transfer == 2'h0) ?
{8'h34, 1'b0,
address_for_transfer[6:0], data_reg[8], 1'b0,
data_reg[7:0], 1'b0} :
(device_for_transfer == 2'h1) ?
{8'h40, 1'b0,
address_for_transfer[7:0], external_read_transfer,
data_reg[7:0], 1'b0} :
{8'h42, 1'b0,
address_for_transfer[7:0], external_read_transfer,
data_reg[7:0], 1'b0};
assign data_to_controller_on_restart =
(device_for_transfer == 2'h1) ?
{8'h41, 1'b0, 8'h00, 1'b0, 8'h00, ack} :
{8'h43, 1'b0, 8'h00, 1'b0, 8'h00, ack};
// {8'h43, 1'b0, {2{8'h00, 1'b0}}};
assign start_transfer = (auto_init_complete) ?
start_external_transfer :
auto_init_transfer_en;
// Signals from the serial controller
assign ack = data_from_controller[18] |
data_from_controller[ 9] |
data_from_controller[ 0];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init AV_Config_Auto_Init (
// Inputs
.clk (clk),
.reset (internal_reset),
.clear_error (1'b0),
.ack (ack),
.transfer_complete (transfer_complete),
.rom_data (rom_data),
// Bidirectionals
// Outputs
.data_out (auto_init_data),
.transfer_data (auto_init_transfer_en),
.rom_address (rom_address),
.auto_init_complete (auto_init_complete),
.auto_init_error (auto_init_error)
);
defparam
AV_Config_Auto_Init.ROM_SIZE = AIRS,
AV_Config_Auto_Init.AW = AIAW,
AV_Config_Auto_Init.DW = DW;
altera_up_av_config_auto_init_ob_de2_35 Auto_Init_OB_Devices_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (rom_data)
);
defparam
Auto_Init_OB_Devices_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_OB_Devices_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_OB_Devices_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_OB_Devices_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_OB_Devices_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_OB_Devices_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_OB_Devices_ROM.AUD_POWER = AUD_POWER,
Auto_Init_OB_Devices_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_OB_Devices_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_OB_Devices_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
defparam
Auto_Init_OB_Devices_ROM.VID_INPUT_CONTROL = 16'h0040,
Auto_Init_OB_Devices_ROM.VID_CHROMA_GAIN_1 = 16'h2df4,
Auto_Init_OB_Devices_ROM.VID_CHROMA_GAIN_2 = 16'h2e00;
altera_up_av_config_serial_bus_controller Serial_Bus_Controller (
// Inputs
.clk (clk),
.reset (internal_reset),
.start_transfer (start_transfer),
.data_in (data_to_controller),
.transfer_mask (transfer_mask),
.restart_counter (RESTART_COUNTER),
.restart_data_in (data_to_controller_on_restart),
.restart_transfer_mask (READ_MASK),
// Bidirectionals
.serial_data (I2C_SDAT),
// Outputs
.serial_clk (I2C_SCLK),
.serial_en (I2C_SCEN),
.data_out (data_from_controller),
.transfer_complete (transfer_complete)
);
defparam
Serial_Bus_Controller.DW = DW,
Serial_Bus_Controller.CW = SBCW,
Serial_Bus_Controller.SCCW = SCCW;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Data Cache top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of all DC blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_top.v,v $
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.2 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.6 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.5 2002/08/18 19:54:47 lampret
// Added store buffer.
//
// Revision 1.4 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.4 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:53 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
//
// Data cache
//
module or1200_dc_top_wrapper(
// Rst, clk and clock control
clk, rst,
// External i/f
dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o,
dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
// Internal i/f
dc_en,
dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPRs
spr_cs, spr_write, spr_dat_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External I/F
//
output [dw-1:0] dcsb_dat_o;
output [31:0] dcsb_adr_o;
output dcsb_cyc_o;
output dcsb_stb_o;
output dcsb_we_o;
output [3:0] dcsb_sel_o;
output dcsb_cab_o;
input [dw-1:0] dcsb_dat_i;
input dcsb_ack_i;
input dcsb_err_i;
//
// Internal I/F
//
input dc_en;
input [31:0] dcqmem_adr_i;
input dcqmem_cycstb_i;
input dcqmem_ci_i;
input dcqmem_we_i;
input [3:0] dcqmem_sel_i;
input [3:0] dcqmem_tag_i;
input [dw-1:0] dcqmem_dat_i;
output [dw-1:0] dcqmem_dat_o;
output dcqmem_ack_o;
output dcqmem_rty_o;
output dcqmem_err_o;
output [3:0] dcqmem_tag_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_dat_i;
//
// Internal wires and regs
//
wire tag_v;
wire [`OR1200_DCTAG_W-2:0] tag;
wire [dw-1:0] to_dcram;
wire [dw-1:0] from_dcram;
wire [3:0] dcram_we;
wire dctag_we;
wire [31:0] dc_addr;
reg tagcomp_miss;
wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr;
wire dctag_en;
wire dctag_v;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_ram_so;
wire mbist_tag_so;
wire mbist_ram_si = mbist_si_i;
wire mbist_tag_si = mbist_ram_so;
assign mbist_so_o = mbist_tag_so;
`endif
//
// Instantiation of DC Top module
//
//
// Instantiation of Data Cache
//
or1200_dc_top or1200_dc_top(
.clk(clk),
.rst(rst),
// DC and QMEM
.dc_en(dc_en),
.dcqmem_adr_i(dcqmem_adr_i),
.dcqmem_cycstb_i(dcqmem_cycstb_i),
.dcqmem_ci_i(dcqmem_ci_i),
.dcqmem_we_i(dcqmem_we_i),
.dcqmem_sel_i(dcqmem_sel_i),
.dcqmem_tag_i(dcqmem_tag_i),
.dcqmem_dat_i(dcqmem_dat_i),
.dcqmem_dat_o(dcqmem_dat_o),
.dcqmem_ack_o(dcqmem_ack_o),
.dcqmem_rty_o(dcqmem_rty_o),
.dcqmem_err_o(dcqmem_err_o),
.dcqmem_tag_o(dcqmem_tag_o),
// SPR access
.spr_cs(spr_cs),
.spr_write(spr_write),
.spr_dat_i(spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS]),
// DC and BIU
.dcsb_dat_o(dcsb_dat_o),
.dcsb_adr_o(dcsb_adr_o),
.dcsb_cyc_o(dcsb_cyc_o),
.dcsb_stb_o(dcsb_stb_o),
.dcsb_we_o(dcsb_we_o),
.dcsb_sel_o(dcsb_sel_o),
.dcsb_cab_o(dcsb_cab_o),
.dcsb_dat_i(dcsb_dat_i),
.dcsb_ack_i(dcsb_ack_i),
.dcsb_err_i(dcsb_err_i),
.tag_v(tag_v),
.tag(tag),
.from_dcram(from_dcram),
.dc_addr(dc_addr),
.dcram_we(dcram_we),
.to_dcram(to_dcram),
.dctag_addr(dctag_addr),
.dctag_en(dctag_en),
.dctag_we(dctag_we),
.dctag_v(dctag_v)
);
//
// Instantiation of DC main memory
//
or1200_dc_ram or1200_dc_ram(
.clk(clk),
.rst(rst),
.addr(dc_addr[`OR1200_DCINDXH:2]),
.en(dc_en),
.we(dcram_we),
.datain(to_dcram),
.dataout(from_dcram)
);
//
// Instantiation of DC TAG memory
//
or1200_dc_tag or1200_dc_tag(
.clk(clk),
.rst(rst),
.addr(dctag_addr),
.en(dctag_en),
.we(dctag_we),
.datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}),
.tag_v(tag_v),
.tag(tag)
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 7
(* X_CORE_INFO = "axi_register_slice_v2_1_7_axi_register_slice,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_s01_regslice_0,axi_register_slice_v2_1_7_axi_register_slice,{}" *)
(* CORE_GENERATION_INFO = "zc702_s01_regslice_0,axi_register_slice_v2_1_7_axi_register_slice,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_s01_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_7_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(1),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/* ********************************************************************************************* */
/* * Activity Indicator LED Module * */
/* * Authors: * */
/* * André Bannwart Perina * */
/* ********************************************************************************************* */
/* * Copyright (c) 2016 André B. Perina * */
/* * * */
/* * Permission is hereby granted, free of charge, to any person obtaining a copy of this * */
/* * software and associated documentation files (the "Software"), to deal in the Software * */
/* * without restriction, including without limitation the rights to use, copy, modify, * */
/* * merge, publish, distribute, sublicense, and/or sell copies of the Software, and to * */
/* * permit persons to whom the Software is furnished to do so, subject to the following * */
/* * conditions: * */
/* * * */
/* * The above copyright notice and this permission notice shall be included in all copies * */
/* * or substantial portions of the Software. * */
/* * * */
/* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * */
/* * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR * */
/* * PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE * */
/* * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * */
/* * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * */
/* * DEALINGS IN THE SOFTWARE. * */
/* ********************************************************************************************* */
module ActivityLED(
clk,
rst_n,
sig_in,
led_out
);
/* Usual inputs */
input clk;
input rst_n;
/* Input signal and LED output */
input sig_in;
output led_out;
reg prevSigIn;
reg [23:0] ledCounter;
assign led_out = ledCounter[22];
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
prevSigIn <= 'b0;
ledCounter <= 'h0;
end
else begin
/* If changes are detected in sig_in, the LED will blink */
prevSigIn <= sig_in;
if(!ledCounter) begin
if(sig_in && !prevSigIn) begin
ledCounter <= 'h1;
end
end
else begin
ledCounter <= ledCounter + 'h1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTN_1_V
`define SKY130_FD_SC_LP__DLRTN_1_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTN_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXBP_2_V
`define SKY130_FD_SC_HDLL__SDFXBP_2_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxbp_2 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXBP_2_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller Definitions ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_defines.v,v 1.5 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_defines.v,v $
// Revision 1.5 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.4 2002/03/11 03:21:22 rudi
//
// - Added defines to select fifo depth between 4, 8 and 16 entries.
//
// Revision 1.3 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:14 rudi
// Initial Checkin
//
//
//
//
`timescale 1ns / 10ps
/////////////////////////////////////////////////////////////////////
// This AC97 Controller supports up to 6 Output and 3 Input Channels.
// Comment out the define statement for which channels you do not wish
// to support in your implementation. The main Left and Right channels
// are always supported.
// Surround Left + Right
`define AC97_SURROUND 1
// Center Channel
`define AC97_CENTER 1
// LFE Channel
`define AC97_LFE 1
// Stereo Input
`define AC97_SIN 1
// Mono Microphone Input
`define AC97_MICIN 1
/////////////////////////////////////////////////////////////////////
//
// This define selects how the WISHBONE interface determines if
// the internal register file is selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
`define AC97_REG_SEL (wb_addr_i[31:29] == 3'h0)
/////////////////////////////////////////////////////////////////////
//
// This is a prescaler that generates a pulse every 250 nS.
// The value here should one less than the actually calculated
// value.
// For a 200 MHz wishbone clock, this value is 49 (50-1).
`define AC97_250_PS 6'h31
/////////////////////////////////////////////////////////////////////
//
// AC97 Cold reset Must be asserted for at least 1uS. The AC97
// controller will stretch the reset pulse to at least 1uS.
// The reset timer is driven by the AC97_250_PS prescaler.
// This value should probably be never changed. Adjust the
// AC97_250_PS instead.
`define AC97_RST_DEL 3'h4
/////////////////////////////////////////////////////////////////////
//
// This value indicates for how long the resume signaling (asserting sync)
// should be done. This counter is driven by the AC97_250_PS prescaler.
// This value times 250nS is the duration of the resume signaling.
// The actual value must be incremented by one, as we do not know
// the current state of the prescaler, and must somehow insure we
// meet the minimum 1uS length. This value should probably be never
// changed. Modify the AC97_250_PS instead.
`define AC97_RES_SIG 3'h5
/////////////////////////////////////////////////////////////////////
//
// If the bit clock is absent for at least two "predicted" bit
// clock periods (163 nS) we should signal "suspended".
// This value defines how many WISHBONE cycles must pass without
// any change on the bit clock input before we signal "suspended".
// For a 200 MHz WISHBONE clock this would be about (163/5) 33 cycles.
`define AC97_SUSP_DET 6'h21
/////////////////////////////////////////////////////////////////////
//
// Select FIFO Depth. For most applications a FIFO depth of 4 should
// be sufficient. For systems with slow interrupt processing or slow
// DMA response or systems with low internal bus bandwidth you might
// want to increase the FIFO sizes to reduce the interrupt/DMA service
// request frequencies.
// Service request frequency can be calculated as follows:
// Channel bandwidth / FIFO size = Service Request Frequency
// For Example: 48KHz / 4 = 12 kHz
//
// Select Input FIFO depth by uncommenting ONE of the following define
// statements:
`define AC97_IN_FIFO_DEPTH_4
//`define AC97_IN_FIFO_DEPTH_8
//`define AC97_IN_FIFO_DEPTH_16
//
// Select Output FIFO depth by uncommenting ONE of the following define
// statements:
`define AC97_OUT_FIFO_DEPTH_4
//`define AC97_OUT_FIFO_DEPTH_8
//`define AC97_OUT_FIFO_DEPTH_16
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
// Date : Fri Nov 2 15:01:49 2018
// Host : graviton running 64-bit Debian GNU/Linux 7.11 (wheezy)
// Command : write_verilog -force -mode synth_stub
// /home/guest/cae/fpga/ntpserver/sv/ip/ocxo_clk_pll/ocxo_clk_pll_stub.v
// Design : ocxo_clk_pll
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module ocxo_clk_pll(clk_in1, clk_out1, resetn, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,resetn,locked" */;
input clk_in1;
output clk_out1;
input resetn;
output locked;
endmodule
|
/*
* tfr_mem.v - Memory transfer function
*
* Allows the support CPU to store stuff in the SDRAM memory
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2018 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
* Registers are:
* 0,1,2 Address of SDRAM memory (24 bits)
* 4 - WRITEONLY - Mark rom 1-31 as populated or un populated (Bit 7 = state, 4-0 = rom #)
* 4 - READONLY - Get ROM status flags ROMs 0-7
* 5 - READONLY - Get ROM status flags ROMs 8-15
* 6 - READONLY - Get ROM status flags ROMs 16-23
* 7 - READONLY - Get ROM status flags ROMs 24-31
* F - Write only - Data out
*/
`timescale 1ns/1ns
module tfr_mem (
// Signals
input wire memclk_i,
output reg [23:0] bus_A_o,
output reg [7:0] bus_D_o,
output reg [31:0] romflags_o,
// Bus signals
input busclk_i, // Clock for bus signals
input nreset_i,
input [3:0] A_i, // 10x8-bit registers, representing the 80 keys
input [7:0] D_i,
output reg [7:0] D_o,
input nWR_i,
input nRD_i
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
reg [23:0] addr_io;
// Assignments ================================================================================
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Other logic ================================================================================
function [7:0] lookup_register( input [3:0] a );
case( a )
4'h0: lookup_register = addr_io[7:0];
4'h1: lookup_register = addr_io[15:8];
4'h2: lookup_register = addr_io[23:16];
4'h4: lookup_register = romflags_o[7:0];
4'h5: lookup_register = romflags_o[15:8];
4'h6: lookup_register = romflags_o[23:16];
4'h7: lookup_register = romflags_o[31:24];
default: lookup_register = 8'hff;
endcase
endfunction
// Write a register by reference should match below for clarity, not function
task write_register(
input [3:0] a,
input [7:0] d
);
case( a )
4'h0: addr_io[7:0] <= d;
4'h1: addr_io[15:8] <= d;
4'h2: addr_io[23:16] <= d;
4'h4: romflags_o[d[4:0]] <= d[7];
4'hf: bus_D_o <= d;
default: ;
endcase
endtask
// IO Domain clock
always @(posedge busclk_i)
begin
if( !nreset_i ) begin
addr_io <= 24'd0;
bus_D_o <= 8'd0;
romflags_o <= 32'd0;
end
else begin
if( !nRD_i ) D_o <= lookup_register(A_i);
if( !nWR_i ) begin
write_register(A_i,D_i);
if( A_i == 4'hf ) addr_io <= addr_io + 1'b1;
end
end
end
// Memory Domain Clock
always @(posedge memclk_i)
begin
bus_A_o <= (addr_io -1'b1); // Correction for early increment
end
endmodule
|
//
// tmr.v -- programmable timer
//
module tmr(clk, reset,
en, wr, addr,
data_in, data_out,
wt, irq);
input clk;
input reset;
input en;
input wr;
input [3:2] addr;
input [31:0] data_in;
output reg [31:0] data_out;
output wt;
output irq;
reg [31:0] counter;
reg [31:0] divisor;
reg divisor_loaded;
reg expired;
reg alarm;
reg ien;
always @(posedge clk) begin
if (divisor_loaded == 1) begin
counter <= divisor;
expired <= 0;
end else begin
if (counter == 32'h00000001) begin
counter <= divisor;
expired <= 1;
end else begin
counter <= counter - 1;
expired <= 0;
end
end
end
always @(posedge clk) begin
if (reset == 1) begin
divisor <= 32'hFFFFFFFF;
divisor_loaded <= 1;
alarm <= 0;
ien <= 0;
end else begin
if (expired == 1) begin
alarm <= 1;
end else begin
if (en == 1 && wr == 1 && addr[3:2] == 2'b00) begin
alarm <= data_in[0];
ien <= data_in[1];
end
if (en == 1 && wr == 1 && addr[3:2] == 2'b01) begin
divisor <= data_in;
divisor_loaded <= 1;
end else begin
divisor_loaded <= 0;
end
end
end
end
always @(*) begin
case (addr[3:2])
2'b00:
// ctrl
data_out = { 28'h0000000, 2'b00, ien, alarm };
2'b01:
// divisor
data_out = divisor;
2'b10:
// counter
data_out = counter;
2'b11:
// not used
data_out = 32'hxxxxxxxx;
default:
data_out = 32'hxxxxxxxx;
endcase
end
assign wt = 0;
assign irq = ien & alarm;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/07 13:33:41
// Design Name:
// Module Name: down_counter_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module down_counter_tb(
);
parameter COUNT = 100;
parameter DELAY = 10;
parameter TIME = (COUNT * DELAY);
reg clk, start;
wire cnt_done;
integer i;
down_counter #(5) DUT (start, clk, cnt_done);
initial begin
#TIME $finish;
end
initial begin
clk = 0;
for (i = 0; i < COUNT; i = i + 1) begin
#DELAY clk = ~clk;
end
end
initial begin
start = 0;
#DELAY start = 1;
#DELAY start = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221O_2_V
`define SKY130_FD_SC_HD__A221O_2_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a221o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a221o_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221O_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Teske Virtual System
// Engineer: Lucas Teske
//
// Create Date: 19:14:43 07/04/2013
// Design Name: LVDS 7-to-1 Serializer
// Module Name: lvds_clockgen
// GitHub: https://github.com/racerxdl/LVDS-7-to-1-Serializer
//////////////////////////////////////////////////////////////////////////////////
module lvds_clockgen(
input clk,
output clk35,
output nclk35,
output rstclk,
output dataclock,
output lvdsclk
);
// Clock: 1100011
wire clk_lckd;
wire clkdcm;
wire clo;
DCM_SP #(.CLKIN_PERIOD ("15.625"),
.DESKEW_ADJUST ("0"),
.CLKFX_MULTIPLY (7),
.CLKFX_DIVIDE (2))
dcm_clk (
.CLKIN (clk),
.CLKFB (clo),
.RST (1'b0),
.CLK0 (clkdcm),
.CLKFX (clk35),
.CLKFX180 (nclk35),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLK90 (),
.CLKDV (),
.PSDONE (),
.STATUS (),
.DSSEN (1'b0),
.PSINCDEC (1'b0),
.PSEN (1'b0),
.PSCLK (1'b0),
.LOCKED (clk_lckd)) ;
BUFG clk_bufg (.I(clkdcm), .O(clo) ) ;
assign not_clk_lckd = ~clk_lckd ;
FDP fd_rst_clk (.D(not_clk_lckd), .C(clo), .Q(rst_clk)) ;
// The LVDS Clock is 4:3, if you need 3:4 you can use 7'b0011100
serializer lvdsclkman (
.clk(clo),
.clk35(clk35),
.notclk35(nclk35),
.data(7'b1100011),
.rst(rst_clk),
.out(lvdsclk)
);
assign rstclk = rst_clk;
assign dataclock = clo;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__TAPVGND2_BEHAVIORAL_PP_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_BEHAVIORAL_PP_V |
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