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`timescale 1ns/1ps
`define DEMO_FUNCTION_ADDR 1
module tb_cocotb (
//Virtual Host Interface Signals
input clk,
input sdio_clk,
input rst,
input request_read_wait,
input request_interrupt
);
//Parameters
//Registers/Wires
reg r_rst;
reg r_request_read_wait;
reg r_request_interrupt;
wire sdio_cmd;
wire [3:0] sdio_data;
// Function Interface From CIA
wire fbr1_csa_en;
wire [3:0] fbr1_pwr_mode;
wire [15:0] fbr1_block_size;
wire fbr2_csa_en;
wire [3:0] fbr2_pwr_mode;
wire [15:0] fbr2_block_size;
wire fbr3_csa_en;
wire [3:0] fbr3_pwr_mode;
wire [15:0] fbr3_block_size;
wire fbr4_csa_en;
wire [3:0] fbr4_pwr_mode;
wire [15:0] fbr4_block_size;
wire fbr5_csa_en;
wire [3:0] fbr5_pwr_mode;
wire [15:0] fbr5_block_size;
wire fbr6_csa_en;
wire [3:0] fbr6_pwr_mode;
wire [15:0] fbr6_block_size;
wire fbr7_csa_en;
wire [3:0] fbr7_pwr_mode;
wire [15:0] fbr7_block_size;
wire [7:0] function_enable;
reg [7:0] function_ready;
wire [2:0] function_abort;
wire [7:0] function_int_en;
reg [7:0] function_int_pend;
reg [7:0] function_exec_status;
wire function_activate;
wire function_inc_addr;
wire function_bock_mode;
wire function_finished;
reg [7:0] function_interrupt;
wire [3:0] func_num;
wire func_write_flag;
wire func_rd_after_wr;
wire [7:0] func_write_data;
wire [7:0] func_read_data;
wire func_data_rdy;
wire func_wr_data_stb;
wire func_host_rdy;
wire [17:0] func_addr;
wire [17:0] func_data_count;
wire func_rd_data_stb;
wire func_block_mode;
wire i_func_num;
wire o_read_wait;
wire o_interrupt;
wire demo_func_ready;
wire demo_func_enable;
wire demo_func_abort;
wire demo_func_int_en;
wire demo_func_int_pend;
wire demo_func_busy;
wire demo_func_activate;
wire demo_func_finished;
wire demo_func_inc_addr;
wire demo_func_block_mode;
/* COCOTB Synchronize */
always @ (*) r_rst = rst;
always @ (*) r_request_read_wait = request_read_wait;
always @ (*) r_request_interrupt = request_interrupt;
//Submodules
sdio_device_stack sdio_device (
.sdio_clk (sdio_clk ),
.rst (rst ),
// Function Interface From CIA
.o_fbr1_csa_en (fbr1_csa_en ),
.o_fbr1_pwr_mode (fbr1_pwr_mode ),
.o_fbr1_block_size (fbr1_block_size ),
.o_fbr2_csa_en (fbr2_csa_en ),
.o_fbr2_pwr_mode (fbr2_pwr_mode ),
.o_fbr2_block_size (fbr2_block_size ),
.o_fbr3_csa_en (fbr3_csa_en ),
.o_fbr3_pwr_mode (fbr3_pwr_mode ),
.o_fbr3_block_size (fbr3_block_size ),
.o_fbr4_csa_en (fbr4_csa_en ),
.o_fbr4_pwr_mode (fbr4_pwr_mode ),
.o_fbr4_block_size (fbr4_block_size ),
.o_fbr5_csa_en (fbr5_csa_en ),
.o_fbr5_pwr_mode (fbr5_pwr_mode ),
.o_fbr5_block_size (fbr5_block_size ),
.o_fbr6_csa_en (fbr6_csa_en ),
.o_fbr6_pwr_mode (fbr6_pwr_mode ),
.o_fbr6_block_size (fbr6_block_size ),
.o_fbr7_csa_en (fbr7_csa_en ),
.o_fbr7_pwr_mode (fbr7_pwr_mode ),
.o_fbr7_block_size (fbr7_block_size ),
.o_func_enable (function_enable ),
.i_func_ready (function_ready ),
.o_func_abort (function_abort ),
.o_func_int_en (function_int_en ),
.i_func_int_pending (function_int_pend ),
.i_func_exec_status (function_exec_status),
.o_func_activate (o_func_activate ),
.i_func_finished (i_func_finished ),
.o_func_inc_addr (o_func_inc_addr ),
.o_func_block_mode (o_func_block_mode ),
.o_func_num (func_num ),
.o_func_write_flag (func_write_flag ),
.o_func_rd_after_wr (func_rd_after_wr ),
.o_func_addr (func_addr ),
.o_func_write_data (func_write_data ),
.i_func_read_data (func_read_data ),
.o_func_data_rdy (func_data_rdy ),
.i_func_host_rdy (func_host_rdy ),
.o_func_data_count (func_data_count ),
.i_interrupt (function_interrupt),
.o_ddr_en (o_ddr_en ),
.i_sdio_cmd (sdio_cmd ),
.io_sdio_data (sdio_data )
);
demo_function demo (
.clk (clk ),
.sdio_clk (sdio_clk ),
.rst (r_rst ),
.i_csa_en (fbr1_csa_en ),
.i_block_size (fbr1_block_size ),
.i_enable (demo_func_enable ),
.o_ready (demo_func_ready ),
.i_abort (demo_func_abort ),
.i_interrupt_enable (demo_func_int_en ),
.o_interrupt_pending (demo_func_int_pend ),
.o_busy (demo_func_busy ),
.i_activate (demo_func_activate ),
.o_finished (demo_func_finished ),
.i_inc_addr (demo_func_inc_addr ),
.i_block_mode (demo_func_block_mode),
.i_write_flag (func_write_flag ),
.i_rd_after_wr (func_rd_after_wr ),
.i_addr (func_addr ),
.i_write_data (func_write_data ),
.o_read_data (func_read_data ),
.o_data_rdy (func_data_rdy ),
.i_data_stb (func_wr_data_stb ),
.i_host_rdy (func_host_rdy ),
.i_data_count (func_data_count ),
.o_data_stb (func_rd_data_stb ),
.o_read_wait (demo_func_read_wait ),
.o_interrupt (demo_func_interrupt ),
.i_request_read_wait (r_request_read_wait ),
.i_request_interrupt (r_request_interrupt )
);
//Asynchronous Logic
assign sdio_cmd = 0;
assign sdio_data = 0;
assign demo_func_enable = function_enable[`DEMO_FUNCTION_ADDR];
assign demo_func_abort = (function_abort == `DEMO_FUNCTION_ADDR);
assign demo_func_int_en = function_int_en[`DEMO_FUNCTION_ADDR];
assign demo_func_activate = (func_num == `DEMO_FUNCTION_ADDR) ? function_activate : 1'b0;
assign demo_func_inc_addr = (func_num == `DEMO_FUNCTION_ADDR) ? function_inc_addr : 18'h0;
assign demo_func_block_mode = (func_num == `DEMO_FUNCTION_ADDR) ? func_block_mode : 1'b0;
/* Make a multiplexer that will handle multiple function */
assign function_finished = (func_num == `DEMO_FUNCTION_ADDR) ? demo_func_finished : 1'b0;
assign function_read_wait = (func_num == `DEMO_FUNCTION_ADDR) ? demo_func_read_wait : 1'b0;
//Synchronous Logic
always @ (posedge sdio_clk) begin
if (r_rst) begin
function_ready <= 0;
function_int_pend <= 0;
function_exec_status <= 0;
function_interrupt <= 0;
end
else begin
function_ready[`DEMO_FUNCTION_ADDR] <= demo_func_ready;
function_int_pend[`DEMO_FUNCTION_ADDR] <= demo_func_int_pend;
function_exec_status[`DEMO_FUNCTION_ADDR] <= demo_func_busy;
function_interrupt[`DEMO_FUNCTION_ADDR] <= demo_func_interrupt;
end
end
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram30x4.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module ram30x4 (
address,
clock,
data,
wren,
q);
input [4:0] address;
input clock;
input [3:0] data;
input wren;
output [3:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "30"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: WidthData NUMERIC "4"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "30"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram30x4_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// -*- Mode: Verilog -*-
// Filename : simple_daq_master_00.v
// Description : Simple DAQ Master Test
// Author : Philip Tracton
// Created On : Wed Dec 16 21:44:30 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed Dec 16 21:44:30 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`include "wb_dsp_includes.vh"
module test_case (/*AUTOARG*/ ) ;
//
// Test Configuration
// These parameters need to be set for each test case
//
parameter simulation_name = "sum_00";
parameter ram_image = "sum_00.mem";
parameter channel0_adc_image = "sum_00_adc.mem";
parameter channel1_adc_image = "sum_00_adc.mem";
parameter channel2_adc_image = "sum_00_adc.mem";
parameter channel3_adc_image = "sum_00_adc.mem";
parameter number_of_tests = 80;
reg err;
reg [31:0] data_out;
integer i;
initial begin
$display("SUM 00 Test Case");
`TB.master_bfm.reset;
@(posedge `WB_RST);
@(negedge `WB_RST);
@(posedge `WB_CLK);
//
// Seq Address for equation 0
//
`TB.master_bfm.write(`WB_DSP_EQUATION0_ADDRESS_REG, `WB_DSP_RAM_BASE_ADDRESS+1024, 4'hF, err);
//
// Start running the equation
//
`TB.master_bfm.write(`WB_DSP_CONTROL_REG, 32'h0000_0021, 4'hF, err);
#500000;
`TEST_COMPLETE;
end
endmodule // test_case
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A222OI_PP_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_PP_BLACKBOX_V
|
`default_nettype none
`timescale 1ns / 1ps
module joypad_controller(
input wire clock,
input wire reset,
input wire int_ack,
output reg int_req,
input wire [15:0] A,
input wire [7:0] Di,
output wire [7:0] Do,
input wire rd_n,
input wire wr_n,
input wire cs,
output reg [1:0] button_sel,
input wire [3:0] button_data
);
////////////////////////////////////////////////
// Joypad Registers
//
// JOYP - Joypad (FF00)
// Bit 5: 0 <= select button keys (R/W)
// Bit 4: 0 <= select direction keys (R/W)
// Bit 3: 0 <= Down or Start
// Bit 2: 0 <= Up or Select
// Bit 1: 0 <= Left or B
// Bit 0: 0 <= Right or A
////////////////////////////////////////////////
always @(posedge clock) begin
if (reset)
int_req <= 0;
else begin
if (!wr_n) begin
if (A == 16'hFF00)
button_sel <= Di[5:4];
end
end
end
assign Do = (cs) ? { 2'b11, button_sel[1:0], button_data[3:0] } : 8'hFF;
endmodule
|
// ----------------------------------------------------------------------------
// Module: alu.v
// Project: MOS 6502 Processor
// Author: George Castillo
// Date: Sat Jul 8 15:31:17 2017
//
// Description: Arithmetic-logic unit for the MOS 6502 processor.
//
// Usage: The ALU is used by the processor to perform the majority of its
// arithmetic functions. Some details about the implementation follow.
//
// Control Signals:
// ADD = 3'b000
// SR = 3'b001
// AND = 3'b010
// OR = 3'b011
// XOR = 3'b100
//
// Logical and arithmetic operations do not distinguish between the A and B
// inputs. However, the right shift operation assumes exclusive use of the
// A input.
// ----------------------------------------------------------------------------
module alu
(
input [2:0] alu_control,
input [7:0] alu_AI,
input [7:0] alu_BI,
input alu_carry_in,
output reg [7:0] alu_Y,
output reg alu_carry_out,
output reg alu_overflow
);
`include "params.vh"
// --- Miscellaneous Signals
reg [8:0] add_result; // 9-bits to keep track of the carry
reg add_carry_out;
reg add_overflow;
reg sr_carry_out;
// Mux out the intended operation
always @(*) begin
case ( alu_control )
ADD: begin
add_result = {1'b0, alu_AI} + {1'b0, alu_BI} + {8'd0, alu_carry_in};
add_carry_out = add_result[8];
alu_Y = add_result[7:0];
alu_overflow = add_overflow;
end
SR: begin
alu_Y = {alu_carry_in, alu_AI[7:1]};
sr_carry_out = alu_AI[0];
alu_overflow = 1'b0;
end
AND: begin
alu_Y = alu_AI & alu_BI;
alu_overflow = 1'b0;
end
OR: begin
alu_Y = alu_AI | alu_BI;
alu_overflow = 1'b0;
end
XOR: begin
alu_Y = alu_AI ^ alu_BI;
alu_overflow = 1'b0;
end
default: begin end
endcase // case ( ctrl )
end
// Mux out the carry bit - note that only ADD and SR have any effect on this
// value
always @(*) begin
case ( alu_control )
ADD: begin
alu_carry_out = add_carry_out;
end
SR: begin
alu_carry_out = sr_carry_out;
end
default: begin
alu_carry_out = 1'b0;
end
endcase // case ( alu_control )
end
// Compute the overflow output
always @(*) begin
// The overflow condition is logically
//
// ((NOT A[7] AND NOT B[7]) AND ADD[7]) OR (A[7] AND B[7] AND NOT ADD[7])
//
// Which is equivalent to
//
// (A[7] XNOR B[7]) AND (A[7] XOR ADD[7])
add_overflow = (~(alu_AI[7] ^ alu_BI[7])) & (alu_AI[7] ^ alu_Y[7]);
end
endmodule // alu
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Basic register without reset.
module RegUN(CLK, EN, D_IN, Q_OUT);
parameter width = 1;
input CLK;
input EN;
input [width - 1 : 0] D_IN;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] Q_OUT;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
Q_OUT = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK)
begin
if (EN)
Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUF_8_V
`define SKY130_FD_SC_HS__BUF_8_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__buf_8 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__buf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUF_8_V
|
module TEST_TOP (
);
/*TEST AUTO_TEMPLATE
(
.abcd_efgh_ijklmno_f02_out_c(abcdefg_f02_clroilouull[5]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_be_2(abcdefg_f10_eg2_ab_cdefghijklm[49]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fh_2(abcdefg_f08_eg0_ab_a_fghi[6]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ch(abcdefg_f09_eg1_ab_cdefghijklm[36]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ej_1(abcdefg_f10_eg2_ab_cdefghijklm[14]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ga_1(abcdefg_f10_eg2_ab_cdefghijklm[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fe(abcdefg_f09_eg1_ab_cdefghijklm[9]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bi_2(abcdefg_f08_eg0_ab_cdefghijklm[45]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_24_1(abcdefg_f09_eg1_ab_fghijklm[24]),
.abcd_efgh_ijklmno_f01_oilouull_o_0_1(abcdefg_f01_oilouull[0]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cc_2(abcdefg_f10_eg2_ab_cdefghijklm[41]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_e_2(abcdefg_f11_eg3_ab_cdefghijklm[59]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_54_1(abcdefg_f11_eg3_ab_fghijklm[54]),
.abcd_efgh_ijklmno_f03_oilouull_o_3_1(abcdefg_f03_oilouull[3]),
.abcd_efgh_ijklmno_f02_out_h_2(abcdefg_f02_a_zxdf[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_g_1(abcdefg_f11_eg3_ab_a_fghi[57]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_b_2(abcdefg_f08_eg0_ab_cdefghijklm[62]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_9_1(abcdefg_f11_eg3_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_di_1(abcdefg_f09_eg1_ab_a_fghi[25]),
.abcd_efgh_ijklmno_f00_out_h_2(abcdefg_f00_a_zxdf[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_cg_2(abcdefg_f11_eg3_ab_cdefghijklm[37]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_eh_2(abcdefg_f10_eg2_ab_a_fghi[16]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_di_1(abcdefg_f08_eg0_ab_cdefghijklm[25]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ec_2(abcdefg_f11_eg3_ab_cdefghijklm[21]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_d_1(abcdefg_f11_eg3_ab_a_fghi[60]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bh_1(abcdefg_f11_eg3_ab_a_fghi[46]),
.abcd_efgh_ijklmno_f00_out_f(abcdefg_f00_clroilouull[2]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_52_1(abcdefg_f11_eg3_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f02_out_g(abcdefg_f02_clroilouull[1]),
.abcd_efgh_ijklmno_f07_out_e(abcdefg_f07_clroilouull[3]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ff_2(abcdefg_f10_eg2_ab_a_fghi[8]),
.abcd_efgh_ijklmno_f04_out_h(abcdefg_f04_clroilouull[0]),
.abcd_efgh_ijklmno_f04_out_g_2(abcdefg_f04_a_zxdf[1]),
.abcd_efgh_ijklmno_f02_out_c_2(abcdefg_f02_a_zxdf[5]),
.abcd_efgh_ijklmno_f04_out_a_3(abcdefg_f04_a_zxdf[7]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fa_1(abcdefg_f08_eg0_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ed_2(abcdefg_f08_eg0_ab_a_fghi[20]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ea_2(abcdefg_f10_eg2_ab_a_fghi[23]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_c_2(abcdefg_f10_eg2_ab_cdefghijklm[61]),
.abcd_efgh_ijklmno_f03_oilouull_o_0_1(abcdefg_f03_oilouull[0]),
.abcd_efgh_ijklmno_f00_out_e_2(abcdefg_f00_a_zxdf[3]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bg_3(abcdefg_f10_eg2_ab_a_fghi[47]),
.abcd_efgh_ijklmno_f05_oilouull_o_2_1(abcdefg_f05_oilouull[2]),
.abcd_efgh_ijklmno_f01_out_h_2(abcdefg_f01_a_zxdf[0]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_44_1(abcdefg_f10_eg2_ab_fghijklm[44]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_j_3(abcdefg_f08_eg0_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_39_1(abcdefg_f08_eg0_ab_fghijklm[39]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fj_2(abcdefg_f08_eg0_ab_a_fghi[4]),
.abcd_efgh_ijklmno_f05_out_h(abcdefg_f05_clroilouull[0]),
.abcd_efgh_ijklmno_f05_out_d_2(abcdefg_f05_a_zxdf[4]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_gb_2(abcdefg_f10_eg2_ab_a_fghi[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cb_3(abcdefg_f10_eg2_ab_a_fghi[42]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_52_1(abcdefg_f10_eg2_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_be_2(abcdefg_f11_eg3_ab_cdefghijklm[49]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_42_1(abcdefg_f11_eg3_ab_fghijklm[42]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ci_1(abcdefg_f11_eg3_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fh_1(abcdefg_f10_eg2_ab_cdefghijklm[6]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_24_1(abcdefg_f08_eg0_ab_fghijklm[24]),
.abcd_efgh_ijklmno_f02_out_g_2(abcdefg_f02_a_zxdf[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_d_2(abcdefg_f11_eg3_ab_cdefghijklm[60]),
.abcd_efgh_ijklmno_f06_out_d_2(abcdefg_f06_a_zxdf[4]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ea_1(abcdefg_f09_eg1_ab_a_fghi[23]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_dh_2(abcdefg_f11_eg3_ab_cdefghijklm[26]),
.abcd_efgh_ijklmno_f04_oilouull_o_7_2(abcdefg_f04_oilouull[7]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dh_1(abcdefg_f09_eg1_ab_a_fghi[26]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_18_1(abcdefg_f08_eg0_ab_fghijklm[18]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ba_2(abcdefg_f11_eg3_ab_cdefghijklm[53]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ce_1(abcdefg_f11_eg3_ab_a_fghi[39]),
.abcd_efgh_ijklmno_f03_oilouull_o_5_1(abcdefg_f03_oilouull[5]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ef_1(abcdefg_f09_eg1_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cj_2(abcdefg_f08_eg0_ab_cdefghijklm[34]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_j_2(abcdefg_f08_eg0_ab_cdefghijklm[54]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bh_3(abcdefg_f08_eg0_ab_a_fghi[46]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cb_1(abcdefg_f09_eg1_ab_a_fghi[42]),
.abcd_efgh_ijklmno_f01_oilouull_o_6_2(abcdefg_f01_oilouull[6]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ba_3(abcdefg_f10_eg2_ab_a_fghi[53]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_0_1(abcdefg_f11_eg3_ab_fghijklm[0]),
.abcd_efgh_ijklmno_f06_out_h_2(abcdefg_f06_a_zxdf[0]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_51_1(abcdefg_f08_eg0_ab_fghijklm[51]),
.abcd_efgh_ijklmno_f06_oilouull_o_4_1(abcdefg_f06_oilouull[4]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_10_1(abcdefg_f08_eg0_ab_fghijklm[10]),
.abcd_efgh_ijklmno_f01_oilouull_o_7_2(abcdefg_f01_oilouull[7]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_da_2(abcdefg_f11_eg3_ab_cdefghijklm[33]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_e_1(abcdefg_f09_eg1_ab_a_fghi[59]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_22_1(abcdefg_f08_eg0_ab_fghijklm[22]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_db_2(abcdefg_f11_eg3_ab_cdefghijklm[32]),
.abcd_efgh_ijklmno_f01_oilouull_o_2_1(abcdefg_f01_oilouull[2]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ci_3(abcdefg_f08_eg0_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f07_oilouull_o_6_2(abcdefg_f07_oilouull[6]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_62_1(abcdefg_f11_eg3_ab_fghijklm[62]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_34_1(abcdefg_f10_eg2_ab_fghijklm[34]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_9_1(abcdefg_f10_eg2_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_13_1(abcdefg_f10_eg2_ab_fghijklm[13]),
.abcd_efgh_ijklmno_f05_oilouull_o_7_2(abcdefg_f05_oilouull[7]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ch_1(abcdefg_f11_eg3_ab_a_fghi[36]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fd_1(abcdefg_f10_eg2_ab_cdefghijklm[10]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fc_2(abcdefg_f10_eg2_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ei_1(abcdefg_f09_eg1_ab_a_fghi[15]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_37_1(abcdefg_f08_eg0_ab_fghijklm[37]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_gb(abcdefg_f09_eg1_ab_cdefghijklm[2]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_7_1(abcdefg_f10_eg2_ab_fghijklm[7]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_dg_2(abcdefg_f11_eg3_ab_cdefghijklm[27]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ce(abcdefg_f09_eg1_ab_cdefghijklm[39]),
.abcd_efgh_ijklmno_f07_out_d_2(abcdefg_f07_a_zxdf[4]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cd_2(abcdefg_f08_eg0_ab_cdefghijklm[40]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_57_1(abcdefg_f10_eg2_ab_fghijklm[57]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_63_1(abcdefg_f10_eg2_ab_fghijklm[63]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_j_1(abcdefg_f09_eg1_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f00_out_a(abcdefg_f00_clroilouull[7]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_46_1(abcdefg_f09_eg1_ab_fghijklm[46]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_39_1(abcdefg_f10_eg2_ab_fghijklm[39]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_28_1(abcdefg_f08_eg0_ab_fghijklm[28]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_20_1(abcdefg_f08_eg0_ab_fghijklm[20]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_51_1(abcdefg_f11_eg3_ab_fghijklm[51]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ci_1(abcdefg_f09_eg1_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f04_out_h_2(abcdefg_f04_a_zxdf[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_bd(abcdefg_f09_eg1_ab_cdefghijklm[50]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dg_1(abcdefg_f10_eg2_ab_cdefghijklm[27]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_23_1(abcdefg_f09_eg1_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_1_2(abcdefg_f09_eg1_ab_fghijklm[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bc_2(abcdefg_f08_eg0_ab_cdefghijklm[51]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bc_3(abcdefg_f10_eg2_ab_a_fghi[51]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_62_1(abcdefg_f08_eg0_ab_fghijklm[62]),
.abcd_efgh_ijklmno_f01_out_g_2(abcdefg_f01_a_zxdf[1]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_23_1(abcdefg_f11_eg3_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f03_out_e_2(abcdefg_f03_a_zxdf[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_b_1(abcdefg_f09_eg1_ab_a_fghi[62]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eh(abcdefg_f09_eg1_ab_cdefghijklm[16]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dh_1(abcdefg_f10_eg2_ab_cdefghijklm[26]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_34_1(abcdefg_f09_eg1_ab_fghijklm[34]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_gc_1(abcdefg_f10_eg2_ab_cdefghijklm[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cg_2(abcdefg_f08_eg0_ab_cdefghijklm[37]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_13_1(abcdefg_f11_eg3_ab_fghijklm[13]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_2_1(abcdefg_f08_eg0_ab_fghijklm[2]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fb(abcdefg_f09_eg1_ab_cdefghijklm[12]),
.abcd_efgh_ijklmno_f00_oilouull_o_6_2(abcdefg_f00_oilouull[6]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_h_3(abcdefg_f08_eg0_ab_a_fghi[56]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_38_1(abcdefg_f09_eg1_ab_fghijklm[38]),
.abcd_efgh_ijklmno_f00_out_c(abcdefg_f00_clroilouull[5]),
.abcd_efgh_ijklmno_f06_out_a_3(abcdefg_f06_a_zxdf[7]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_60_1(abcdefg_f09_eg1_ab_fghijklm[60]),
.abcd_efgh_ijklmno_f06_oilouull_o_2_1(abcdefg_f06_oilouull[2]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_8_1(abcdefg_f09_eg1_ab_fghijklm[8]),
.abcd_efgh_ijklmno_f03_out_f(abcdefg_f03_clroilouull[2]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dj_1(abcdefg_f08_eg0_ab_cdefghijklm[24]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bg_2(abcdefg_f08_eg0_ab_cdefghijklm[47]),
.abcd_efgh_ijklmno_f01_oilouull_o_4_1(abcdefg_f01_oilouull[4]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ef_2(abcdefg_f10_eg2_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f01_out_a_3(abcdefg_f01_a_zxdf[7]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_12_1(abcdefg_f08_eg0_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f07_out_c_2(abcdefg_f07_a_zxdf[5]),
.abcd_efgh_ijklmno_f00_out_e(abcdefg_f00_clroilouull[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ca_1(abcdefg_f09_eg1_ab_a_fghi[43]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_eg_2(abcdefg_f08_eg0_ab_a_fghi[17]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_be_1(abcdefg_f11_eg3_ab_a_fghi[49]),
.abcd_efgh_ijklmno_f06_out_d(abcdefg_f06_clroilouull[4]),
.abcd_efgh_ijklmno_f00_out_g(abcdefg_f00_clroilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_b(abcdefg_f09_eg1_ab_cdefghijklm[62]),
.abcd_efgh_ijklmno_f00_out_f_2(abcdefg_f00_a_zxdf[2]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_gc_1(abcdefg_f09_eg1_ab_a_fghi[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ca_1(abcdefg_f11_eg3_ab_a_fghi[43]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ea(abcdefg_f09_eg1_ab_cdefghijklm[23]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_12_1(abcdefg_f10_eg2_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gd_2(abcdefg_f11_eg3_ab_cdefghijklm[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_i_1(abcdefg_f09_eg1_ab_a_fghi[55]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_e_2(abcdefg_f08_eg0_ab_cdefghijklm[59]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ff(abcdefg_f09_eg1_ab_cdefghijklm[8]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_17_1(abcdefg_f11_eg3_ab_fghijklm[17]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_be_3(abcdefg_f10_eg2_ab_a_fghi[49]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_20_1(abcdefg_f11_eg3_ab_fghijklm[20]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bc_1(abcdefg_f11_eg3_ab_a_fghi[51]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_43_1(abcdefg_f09_eg1_ab_fghijklm[43]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_54_1(abcdefg_f09_eg1_ab_fghijklm[54]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_be_2(abcdefg_f08_eg0_ab_cdefghijklm[49]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_36_1(abcdefg_f10_eg2_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f05_out_h_2(abcdefg_f05_a_zxdf[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cc(abcdefg_f09_eg1_ab_cdefghijklm[41]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_3_1(abcdefg_f11_eg3_ab_fghijklm[3]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ff_1(abcdefg_f11_eg3_ab_a_fghi[8]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_19_2(abcdefg_f11_eg3_ab_fghijklm[19]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bi_1(abcdefg_f11_eg3_ab_a_fghi[45]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_49_1(abcdefg_f08_eg0_ab_fghijklm[49]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ee_1(abcdefg_f10_eg2_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_29_1(abcdefg_f08_eg0_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_29_1(abcdefg_f09_eg1_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ed(abcdefg_f09_eg1_ab_cdefghijklm[20]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_de(abcdefg_f09_eg1_ab_cdefghijklm[29]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dg_2(abcdefg_f10_eg2_ab_a_fghi[27]),
.abcd_efgh_ijklmno_f04_oilouull_o_2_1(abcdefg_f04_oilouull[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_eb_2(abcdefg_f10_eg2_ab_a_fghi[22]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ea_2(abcdefg_f11_eg3_ab_cdefghijklm[23]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fc_1(abcdefg_f10_eg2_ab_cdefghijklm[11]),
.abcd_efgh_ijklmno_f06_out_g(abcdefg_f06_clroilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_61_1(abcdefg_f09_eg1_ab_fghijklm[61]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ee_2(abcdefg_f10_eg2_ab_a_fghi[19]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_47_1(abcdefg_f11_eg3_ab_fghijklm[47]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_36_1(abcdefg_f08_eg0_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f07_oilouull_o_0_1(abcdefg_f07_oilouull[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_j_1(abcdefg_f11_eg3_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_52_1(abcdefg_f08_eg0_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gd_1(abcdefg_f11_eg3_ab_a_fghi[0]),
.abcd_efgh_ijklmno_f07_out_h_2(abcdefg_f07_a_zxdf[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cg_1(abcdefg_f09_eg1_ab_a_fghi[37]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_8_1(abcdefg_f10_eg2_ab_fghijklm[8]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fh_1(abcdefg_f11_eg3_ab_a_fghi[6]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_52_1(abcdefg_f09_eg1_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ci_2(abcdefg_f11_eg3_ab_cdefghijklm[35]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_15_1(abcdefg_f10_eg2_ab_fghijklm[15]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_df(abcdefg_f09_eg1_ab_cdefghijklm[28]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ee(abcdefg_f09_eg1_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bd_1(abcdefg_f11_eg3_ab_a_fghi[50]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fe_1(abcdefg_f11_eg3_ab_a_fghi[9]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_di_2(abcdefg_f08_eg0_ab_a_fghi[25]),
.abcd_efgh_ijklmno_f00_out_d(abcdefg_f00_clroilouull[4]),
.abcd_efgh_ijklmno_f07_oilouull_o_5_1(abcdefg_f07_oilouull[5]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_41_1(abcdefg_f09_eg1_ab_fghijklm[41]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cf_2(abcdefg_f08_eg0_ab_cdefghijklm[38]),
.abcd_efgh_ijklmno_f05_out_b_3(abcdefg_f05_a_zxdf[6]),
.abcd_efgh_ijklmno_f03_oilouull_o_1_1(abcdefg_f03_oilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dg_1(abcdefg_f09_eg1_ab_a_fghi[27]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eg(abcdefg_f09_eg1_ab_cdefghijklm[17]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ce_1(abcdefg_f09_eg1_ab_a_fghi[39]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fi_2(abcdefg_f11_eg3_ab_cdefghijklm[5]),
.abcd_efgh_ijklmno_f05_out_g(abcdefg_f05_clroilouull[1]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bj_2(abcdefg_f10_eg2_ab_cdefghijklm[44]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_db(abcdefg_f09_eg1_ab_cdefghijklm[32]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_g_1(abcdefg_f09_eg1_ab_a_fghi[57]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bf_2(abcdefg_f08_eg0_ab_cdefghijklm[48]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bh_2(abcdefg_f08_eg0_ab_cdefghijklm[46]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_23_1(abcdefg_f10_eg2_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_61_1(abcdefg_f10_eg2_ab_fghijklm[61]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_db_1(abcdefg_f09_eg1_ab_a_fghi[32]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_f(abcdefg_f09_eg1_ab_cdefghijklm[58]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_57_1(abcdefg_f09_eg1_ab_fghijklm[57]),
.abcd_efgh_ijklmno_f01_oilouull_o_1_1(abcdefg_f01_oilouull[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_eh_2(abcdefg_f08_eg0_ab_a_fghi[16]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_41_1(abcdefg_f11_eg3_ab_fghijklm[41]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_c_2(abcdefg_f08_eg0_ab_cdefghijklm[61]),
.abcd_efgh_ijklmno_f06_out_e(abcdefg_f06_clroilouull[3]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ej_1(abcdefg_f11_eg3_ab_a_fghi[14]),
.abcd_efgh_ijklmno_f02_oilouull_o_1_1(abcdefg_f02_oilouull[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bd_2(abcdefg_f11_eg3_ab_cdefghijklm[50]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_6_1(abcdefg_f08_eg0_ab_fghijklm[6]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ee_1(abcdefg_f09_eg1_ab_a_fghi[19]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fc_2(abcdefg_f11_eg3_ab_cdefghijklm[11]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bd_3(abcdefg_f10_eg2_ab_a_fghi[50]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_df_1(abcdefg_f08_eg0_ab_cdefghijklm[28]),
.abcd_efgh_ijklmno_f03_out_a(abcdefg_f03_clroilouull[7]),
.abcd_efgh_ijklmno_f02_oilouull_o_0_1(abcdefg_f02_oilouull[0]),
.abcd_efgh_ijklmno_f00_out_g_2(abcdefg_f00_a_zxdf[1]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_43_1(abcdefg_f08_eg0_ab_fghijklm[43]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_59_1(abcdefg_f08_eg0_ab_fghijklm[59]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ff_1(abcdefg_f09_eg1_ab_a_fghi[8]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bh_2(abcdefg_f10_eg2_ab_cdefghijklm[46]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_0_1(abcdefg_f09_eg1_ab_fghijklm[0]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ec_2(abcdefg_f08_eg0_ab_a_fghi[21]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_33_1(abcdefg_f09_eg1_ab_fghijklm[33]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fh_1(abcdefg_f09_eg1_ab_a_fghi[6]),
.abcd_efgh_ijklmno_f02_oilouull_o_4_1(abcdefg_f02_oilouull[4]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_31_1(abcdefg_f10_eg2_ab_fghijklm[31]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fa_1(abcdefg_f10_eg2_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f05_out_f(abcdefg_f05_clroilouull[2]),
.abcd_efgh_ijklmno_f04_out_e_2(abcdefg_f04_a_zxdf[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dd_1(abcdefg_f09_eg1_ab_a_fghi[30]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_12_1(abcdefg_f11_eg3_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_bf_1(abcdefg_f09_eg1_ab_a_fghi[48]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_23_1(abcdefg_f08_eg0_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dj_2(abcdefg_f08_eg0_ab_a_fghi[24]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ci_3(abcdefg_f10_eg2_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_17_1(abcdefg_f08_eg0_ab_fghijklm[17]),
.abcd_efgh_ijklmno_f02_out_f_2(abcdefg_f02_a_zxdf[2]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bb_1(abcdefg_f11_eg3_ab_a_fghi[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_cc_1(abcdefg_f11_eg3_ab_a_fghi[41]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_f_1(abcdefg_f11_eg3_ab_a_fghi[58]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fi(abcdefg_f09_eg1_ab_cdefghijklm[5]),
.abcd_efgh_ijklmno_f03_out_h(abcdefg_f03_clroilouull[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_e_1(abcdefg_f11_eg3_ab_a_fghi[59]),
.abcd_efgh_ijklmno_f01_out_b_3(abcdefg_f01_a_zxdf[6]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_55_1(abcdefg_f08_eg0_ab_fghijklm[55]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bj_3(abcdefg_f10_eg2_ab_a_fghi[44]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_d_2(abcdefg_f08_eg0_ab_cdefghijklm[60]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bi_3(abcdefg_f08_eg0_ab_a_fghi[45]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fg_1(abcdefg_f09_eg1_ab_a_fghi[7]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ej_2(abcdefg_f10_eg2_ab_a_fghi[14]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cb_2(abcdefg_f08_eg0_ab_cdefghijklm[42]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fi_1(abcdefg_f10_eg2_ab_cdefghijklm[5]),
.abcd_efgh_ijklmno_f01_out_c(abcdefg_f01_clroilouull[5]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fa_2(abcdefg_f11_eg3_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f07_out_b_3(abcdefg_f07_a_zxdf[6]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_2_1(abcdefg_f09_eg1_ab_fghijklm[2]),
.abcd_efgh_ijklmno_f07_oilouull_o_2_1(abcdefg_f07_oilouull[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ed_2(abcdefg_f10_eg2_ab_a_fghi[20]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_32_1(abcdefg_f08_eg0_ab_fghijklm[32]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_29_1(abcdefg_f10_eg2_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ef_1(abcdefg_f11_eg3_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_15_1(abcdefg_f09_eg1_ab_fghijklm[15]),
.abcd_efgh_ijklmno_f04_out_c_2(abcdefg_f04_a_zxdf[5]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cd(abcdefg_f09_eg1_ab_cdefghijklm[40]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_57_1(abcdefg_f08_eg0_ab_fghijklm[57]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ee_2(abcdefg_f11_eg3_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_3_1(abcdefg_f09_eg1_ab_fghijklm[3]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_20_1(abcdefg_f10_eg2_ab_fghijklm[20]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_16_1(abcdefg_f08_eg0_ab_fghijklm[16]),
.abcd_efgh_ijklmno_f06_oilouull_o_1_1(abcdefg_f06_oilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cg(abcdefg_f09_eg1_ab_cdefghijklm[37]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cd_3(abcdefg_f10_eg2_ab_a_fghi[40]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_35_1(abcdefg_f10_eg2_ab_fghijklm[35]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_j_3(abcdefg_f10_eg2_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dc_2(abcdefg_f10_eg2_ab_a_fghi[31]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_34_1(abcdefg_f08_eg0_ab_fghijklm[34]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bi_2(abcdefg_f10_eg2_ab_cdefghijklm[45]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_48_1(abcdefg_f09_eg1_ab_fghijklm[48]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_1_2(abcdefg_f10_eg2_ab_fghijklm[1]),
.abcd_efgh_ijklmno_f07_out_g(abcdefg_f07_clroilouull[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_c_2(abcdefg_f11_eg3_ab_cdefghijklm[61]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_24_1(abcdefg_f10_eg2_ab_fghijklm[24]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fj_2(abcdefg_f10_eg2_ab_a_fghi[4]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_bi_1(abcdefg_f09_eg1_ab_a_fghi[45]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_eb_2(abcdefg_f11_eg3_ab_cdefghijklm[22]),
.abcd_efgh_ijklmno_f00_oilouull_o_5_1(abcdefg_f00_oilouull[5]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_30_1(abcdefg_f08_eg0_ab_fghijklm[30]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_11_1(abcdefg_f11_eg3_ab_fghijklm[11]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_26_1(abcdefg_f11_eg3_ab_fghijklm[26]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_45_1(abcdefg_f08_eg0_ab_fghijklm[45]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dj_1(abcdefg_f10_eg2_ab_cdefghijklm[24]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_gd_1(abcdefg_f10_eg2_ab_cdefghijklm[0]),
.abcd_efgh_ijklmno_f05_out_b(abcdefg_f05_clroilouull[6]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ef_2(abcdefg_f08_eg0_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dg(abcdefg_f09_eg1_ab_cdefghijklm[27]),
.abcd_efgh_ijklmno_f02_oilouull_o_6_2(abcdefg_f02_oilouull[6]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_39_1(abcdefg_f11_eg3_ab_fghijklm[39]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bh_3(abcdefg_f10_eg2_ab_a_fghi[46]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fc_1(abcdefg_f08_eg0_ab_cdefghijklm[11]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fa(abcdefg_f09_eg1_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f04_out_b_3(abcdefg_f04_a_zxdf[6]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_21_1(abcdefg_f08_eg0_ab_fghijklm[21]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bc_3(abcdefg_f08_eg0_ab_a_fghi[51]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dd_1(abcdefg_f08_eg0_ab_cdefghijklm[30]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fc_1(abcdefg_f09_eg1_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_22_1(abcdefg_f11_eg3_ab_fghijklm[22]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_14_1(abcdefg_f11_eg3_ab_fghijklm[14]),
.abcd_efgh_ijklmno_f02_out_d_2(abcdefg_f02_a_zxdf[4]),
.abcd_efgh_ijklmno_f06_out_h(abcdefg_f06_clroilouull[0]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_37_1(abcdefg_f09_eg1_ab_fghijklm[37]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eh_1(abcdefg_f09_eg1_ab_a_fghi[16]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_12_1(abcdefg_f09_eg1_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cd_1(abcdefg_f09_eg1_ab_a_fghi[40]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_60_1(abcdefg_f11_eg3_ab_fghijklm[60]),
.abcd_efgh_ijklmno_f03_out_f_2(abcdefg_f03_a_zxdf[2]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_43_1(abcdefg_f11_eg3_ab_fghijklm[43]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dc_2(abcdefg_f08_eg0_ab_a_fghi[31]),
.abcd_efgh_ijklmno_f07_out_b(abcdefg_f07_clroilouull[6]),
.abcd_efgh_ijklmno_f03_out_b_3(abcdefg_f03_a_zxdf[6]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ea_1(abcdefg_f10_eg2_ab_cdefghijklm[23]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_eg_1(abcdefg_f08_eg0_ab_cdefghijklm[17]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fc_2(abcdefg_f08_eg0_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_gc_1(abcdefg_f08_eg0_ab_cdefghijklm[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_da(abcdefg_f09_eg1_ab_cdefghijklm[33]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gb_2(abcdefg_f11_eg3_ab_cdefghijklm[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ba_2(abcdefg_f10_eg2_ab_cdefghijklm[53]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fb_2(abcdefg_f10_eg2_ab_a_fghi[12]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ee_1(abcdefg_f11_eg3_ab_a_fghi[19]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_32_1(abcdefg_f09_eg1_ab_fghijklm[32]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gc_2(abcdefg_f11_eg3_ab_cdefghijklm[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ee_1(abcdefg_f08_eg0_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_36_1(abcdefg_f09_eg1_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f02_out_a(abcdefg_f02_clroilouull[7]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_9_1(abcdefg_f08_eg0_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_5_1(abcdefg_f09_eg1_ab_fghijklm[5]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bh_2(abcdefg_f11_eg3_ab_cdefghijklm[46]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_35_1(abcdefg_f09_eg1_ab_fghijklm[35]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ca(abcdefg_f09_eg1_ab_cdefghijklm[43]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_47_1(abcdefg_f08_eg0_ab_fghijklm[47]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gc_1(abcdefg_f11_eg3_ab_a_fghi[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ba_2(abcdefg_f08_eg0_ab_cdefghijklm[53]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_44_1(abcdefg_f11_eg3_ab_fghijklm[44]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_9_1(abcdefg_f09_eg1_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f00_oilouull_o_3_1(abcdefg_f00_oilouull[3]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fe_2(abcdefg_f11_eg3_ab_cdefghijklm[9]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ec_1(abcdefg_f09_eg1_ab_a_fghi[21]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_de_2(abcdefg_f10_eg2_ab_a_fghi[29]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_29_1(abcdefg_f11_eg3_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_g_3(abcdefg_f08_eg0_ab_a_fghi[57]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fi_2(abcdefg_f10_eg2_ab_a_fghi[5]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_27_1(abcdefg_f08_eg0_ab_fghijklm[27]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fc_1(abcdefg_f11_eg3_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_42_1(abcdefg_f10_eg2_ab_fghijklm[42]),
.abcd_efgh_ijklmno_f04_oilouull_o_4_1(abcdefg_f04_oilouull[4]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_30_1(abcdefg_f09_eg1_ab_fghijklm[30]),
.abcd_efgh_ijklmno_f01_oilouull_o_3_1(abcdefg_f01_oilouull[3]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fj_1(abcdefg_f10_eg2_ab_cdefghijklm[4]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_55_1(abcdefg_f11_eg3_ab_fghijklm[55]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_42_1(abcdefg_f08_eg0_ab_fghijklm[42]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_gd(abcdefg_f09_eg1_ab_cdefghijklm[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eg_1(abcdefg_f09_eg1_ab_a_fghi[17]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_8_1(abcdefg_f08_eg0_ab_fghijklm[8]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_50_1(abcdefg_f11_eg3_ab_fghijklm[50]),
.abcd_efgh_ijklmno_f06_out_f_2(abcdefg_f06_a_zxdf[2]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_26_1(abcdefg_f09_eg1_ab_fghijklm[26]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_30_1(abcdefg_f11_eg3_ab_fghijklm[30]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_55_1(abcdefg_f10_eg2_ab_fghijklm[55]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_df_2(abcdefg_f08_eg0_ab_a_fghi[28]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_28_1(abcdefg_f09_eg1_ab_fghijklm[28]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_22_1(abcdefg_f09_eg1_ab_fghijklm[22]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_45_1(abcdefg_f09_eg1_ab_fghijklm[45]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_46_1(abcdefg_f08_eg0_ab_fghijklm[46]),
.abcd_efgh_ijklmno_f01_out_f(abcdefg_f01_clroilouull[2]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_36_1(abcdefg_f11_eg3_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f05_out_f_2(abcdefg_f05_a_zxdf[2]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ch_2(abcdefg_f08_eg0_ab_cdefghijklm[36]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cj_3(abcdefg_f10_eg2_ab_a_fghi[34]),
.abcd_efgh_ijklmno_f04_oilouull_o_3_1(abcdefg_f04_oilouull[3]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cd_3(abcdefg_f08_eg0_ab_a_fghi[40]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_56_1(abcdefg_f08_eg0_ab_fghijklm[56]),
);*/
TEST TEST (/*AUTOINST*/);
endmodule
module TEST (/*AUTOARG*/);
parameter NO = 6456;
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("select1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("select1_tb.vcd");
$dumpvars(0, cpu_tb);
#30
`assert(result, 1);
`assert(result_empty, 0);
$finish;
end
endmodule
|
//date:2016/3/16
//engineer: zhaishaomin
//module function :test whether mem_download will behave as what i want it to do ,such as handling coming flit correctly
/*
// test examples
//wbrep 11 flits long
flits_d_m_areg={flits_in[140:139],1'b1,local_id,1'b0,wbrep_cmd,5'b00000,seled_addr,data_read};
//ATflurep 11 flits long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,ATflurep_cmd,5'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],data_read};
//shrep 9 flits long
msg={temp_rep_head_flit,data_read,32'h00000000};
//SHexrep 9 flits long
msg={temp_rep_head_flit,data_read,32'h00000000};
//exrep 9 flits long
msg={temp_rep_head_flit,data_read,32'h00000000};
//wbreq 3 flits long
msg={temp_rep_head_flit,seled_addr,128'h0000};
//flushreq 3 flits long
msg={temp_req_head_flit,seled_addr,128'h0000};
//SCinvreq or invreq 3 flits long
msg={temp_req_head_flit,seled_addr,128'h0000};
//shreq 3 flits long
flits_d_m_areg={seled_addr[12:11],1'b0,local_id,1'b1,shreq_cmd,5'b00000,seled_addr,128'hzzzz};
//exreq 3 flits long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,exreq_cmd,5'b00000,seled_addr,128'hzzzz};
//C2Hinvrep 3 flits long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,C2Hinvrep_cmd,5'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],128'hzzzz};
//flushrep 3 flits long
flits_d_m_areg={flits_in[140:139],1'b1,local_id,1'b0,flushrep_cmd,5'b00000,seled_addr,128'h0000};
//flushfail_rep 3 flits long
flits_d_m_areg={flits_in[140:139],1'b1,flits_in[132:131],1'b0,flushfail_rep_cmd,5'b00000,seled_addr,128'h0000};
//wbfail_rep 3 flits long
flits_d_m_areg={flits_in[140:139],1'b1,flits_in[132:131],1'b0,wbfail_rep_cmd,5'b00000,seled_addr,128'h0000};
//nackrep 1 flit long
msg={temp_rep_head_flit,data_read,32'h00000000};
//C2Cinvrep 1 flit long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,C2Hinvrep_cmd,5'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],128'hzzzz};
//SCflushrep 1 flit long
msg={temp_rep_head_flit,data_read,32'h00000000};
*/
`timescale 1ns/1ps
module tb_m_download();
//input
reg clk;
reg rst;
reg [15:0] IN_flit_mem;
reg v_IN_flit_mem;
reg [1:0] In_flit_ctrl;
reg mem_done_access;
//output
wire v_m_download;
wire [175:0] m_donwload_flits;
wire [1:0] m_download_state;
//instantiate the uut
m_download(//input
.clk(clk),
.rst(rst),
.IN_flit_mem(IN_flit_mem),
.v_IN_flit_mem(v_IN_flit_mem),
.In_flit_ctrl(In_flit_ctrl),
.mem_done_access(mem_done_access),
//output
.v_m_download(v_m_download),
.m_donwload_flits(m_donwload_flits),
.m_download_state(m_download_state)
);
// store the simulation log into log_file
integer logfile;
// Initialize Inputs
initial begin
clk=1'b0;
rst=1'b1;
IN_flit_mem=16'h0000;
v_IN_flit_mem=1'b0;
In_flit_ctrl=2'b00;
mem_done_access=1'b0;
end
always #20 clk=~clk;
`define step #40;
initial begin
/////// mem_download test /////////
// First reset all //
$display("(%t) Initializing...", $time);
$fdisplay(log_file, "(%t) Initializing...", $time);
rst=1;
`step
rst=0;
`step
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////REP MSG FROM IN_REP_FIFO//////////////////////////////////////////////////////////////////////
//after a few cycles ,a rep msg from IN_local_rep fifo come and dc_download should be ready to receive the flits
// note :here are three kinds of reps and reqs totally,
// including :9 flits long msg : exrep , shrep, sh->exrep
// 3 flits long msg : invreq, wbreq, flushreq, scflushreq,
// 1 flit long msg : C2Cinvrep so far.
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 11 FLITS LONG MSG
//first flit
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b01;
`step
// second flit comes and is usefull for dc_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
`step
// 3rd flit comes and is usefull for dc_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
`step
// 4th flit comes and is usefull for dc_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
// 5th flit comes and is usefull for dc_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
`step
// 6th flit comes and is usefull for dc_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
//here assume IN_fifo not ready
`step
//7th invalid
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b0;
In_flit_ctrl=2'b10;
`step
// 7th flit comes and is usefull for dc_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
`step
// 8th flit comes and is usefull for dc_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
//here assume IN_fifo not ready
`step
//9th invalid
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b0;
In_flit_ctrl=2'b10;
`step
// 9th flit comes and is usefull for dc_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
`step
// 10th flit comes and is usefull for dc_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
`step
// 11th flit comes and is usefull for dc_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
mem_done_access=1'b1;
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 9 FLITS LONG MSG
//first flit
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b01;
//note :the 2nd to 9th are the flits which includes actual inst word betys
`step
// second flit comes and is usefull for ic_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
`step
// 3rd flit comes and is usefull for ic_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
`step
// 4th flit comes and is usefull for ic_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
// 5th flit comes and is usefull for ic_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
//here assume IN_fifo not ready
`step
//6th invalid
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b0;
In_flit_ctrl=2'b10;
`step
// 6th flit comes and is usefull for ic_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
// just test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
`step
// 7th flit comes and is usefull for ic_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
`step
// 8th flit comes and is usefull for ic_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
`step
// 9th flit comes and is usefull for ic_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
`step
`step
mem_done_access=1'b1;
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 3 FLITS LONG MSG
//first flit
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b01;
//here assume IN_fifo not ready
`step
//2th invalid
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b0;
In_flit_ctrl=2'b10;
`step
// second flit comes and is usefull for ic_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
// 3rd flit comes and is usefull for ic_download
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
mem_done_access=1'b1;
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 1 FLITS LONG MSG
//first flit
IN_flit_mem=16'h1234;
v_IN_flit_mem=1'b1;
In_flit_ctrl=2'b01;
`step
$display("(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
`step
`step
`step
`step
mem_done_access=1'b1;
`step
$display("(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$fdisplay(logfile,"(%t) msg to mem is :%h,and is vallid :%b ,and mem_download_state is:%b ",$time,m_donwload_flits,v_m_download,m_download_state);
$stop;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg_s/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg_s.v"
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X , not0_out, A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X, and0_out_X, VPWR, VGND, SLEEP);
buf buf0 (X , pwrgood0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V |
// soc_system_mm_interconnect_0_avalon_st_adapter_001.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0_avalon_st_adapter_001 #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__TAPMET1_PP_BLACKBOX_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapmet1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A22OI_BEHAVIORAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211AI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O211AI_FUNCTIONAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o211ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211AI_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_SYMBOL_V
`define SKY130_FD_SC_HVL__DLRTP_SYMBOL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_SYMBOL_V
|
//-----------------------------------------------------------------------------
// File : test_setup.v
// Creation date : 28.11.2017
// Creation time : 15:57:44
// Description : Test arrangement for verifying the SPI examples.
// Created by : TermosPullo
// Tool : Kactus2 3.4.1184 32-bit
// Plugin : Verilog generator 2.1
// This file was generated based on IP-XACT component tut.fi:communication.template.test:spi.setup:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/communication.template.test/spi.setup/1.0/spi.setup.1.0.xml
//-----------------------------------------------------------------------------
module test_setup();
// spi_slave_0_slave_if_to_spi_master_0_master_if wires:
wire spi_slave_0_slave_if_to_spi_master_0_master_ifMISO;
wire spi_slave_0_slave_if_to_spi_master_0_master_ifMOSI;
wire spi_slave_0_slave_if_to_spi_master_0_master_ifSCLK;
wire [2:0] spi_slave_0_slave_if_to_spi_master_0_master_ifSS;
// Ad-hoc wires:
wire spi_master_0_clk_in_to_clock_generator_0_clk_o;
wire clock_generator_0_rst_o_to_spi_slave_0_rst_in;
wire clock_generator_0_rst_o_to_spi_master_0_rst_in;
// clock_generator_0 port wires:
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
// spi_master_0 port wires:
wire spi_master_0_clk_in;
wire spi_master_0_clk_out;
wire spi_master_0_data_in;
wire spi_master_0_data_out;
wire spi_master_0_rst_in;
wire spi_master_0_slave_select1_out;
wire spi_master_0_slave_select2_out;
wire spi_master_0_slave_select3_out;
// spi_slave_0 port wires:
wire spi_slave_0_clk_in;
wire spi_slave_0_data_in;
wire spi_slave_0_data_out;
wire spi_slave_0_rst_in;
wire spi_slave_0_slave_select_in;
// clock_generator_0 assignments:
assign spi_master_0_clk_in_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_rst_o_to_spi_master_0_rst_in = clock_generator_0_rst_o;
assign clock_generator_0_rst_o_to_spi_slave_0_rst_in = clock_generator_0_rst_o;
// spi_master_0 assignments:
assign spi_master_0_clk_in = spi_master_0_clk_in_to_clock_generator_0_clk_o;
assign spi_slave_0_slave_if_to_spi_master_0_master_ifSCLK = spi_master_0_clk_out;
assign spi_master_0_data_in = spi_slave_0_slave_if_to_spi_master_0_master_ifMISO;
assign spi_slave_0_slave_if_to_spi_master_0_master_ifMOSI = spi_master_0_data_out;
assign spi_master_0_rst_in = clock_generator_0_rst_o_to_spi_master_0_rst_in;
assign spi_slave_0_slave_if_to_spi_master_0_master_ifSS[0] = spi_master_0_slave_select1_out;
assign spi_slave_0_slave_if_to_spi_master_0_master_ifSS[1] = spi_master_0_slave_select2_out;
assign spi_slave_0_slave_if_to_spi_master_0_master_ifSS[2] = spi_master_0_slave_select3_out;
// spi_slave_0 assignments:
assign spi_slave_0_clk_in = spi_slave_0_slave_if_to_spi_master_0_master_ifSCLK;
assign spi_slave_0_data_in = spi_slave_0_slave_if_to_spi_master_0_master_ifMOSI;
assign spi_slave_0_slave_if_to_spi_master_0_master_ifMISO = spi_slave_0_data_out;
assign spi_slave_0_rst_in = clock_generator_0_rst_o_to_spi_slave_0_rst_in;
assign spi_slave_0_slave_select_in = spi_slave_0_slave_if_to_spi_master_0_master_ifSS[0];
// IP-XACT VLNV: tut.fi:other.test:clock_generator:1.1
clock_generator clock_generator_0(
// Interface: wb_system
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
// IP-XACT VLNV: tut.fi:communication.template:spi_master:1.0
spi_master spi_master_0(
// Interface: master_if
.data_in (spi_master_0_data_in),
.clk_out (spi_master_0_clk_out),
.data_out (spi_master_0_data_out),
.slave_select1_out (spi_master_0_slave_select1_out),
.slave_select2_out (spi_master_0_slave_select2_out),
.slave_select3_out (spi_master_0_slave_select3_out),
// These ports are not in any interface
.clk_in (spi_master_0_clk_in),
.rst_in (spi_master_0_rst_in));
// IP-XACT VLNV: tut.fi:communication.template:spi_slave:1.0
spi_slave #(
.SLAVE_ID (0))
spi_slave_0(
// Interface: slave_if
.clk_in (spi_slave_0_clk_in),
.data_in (spi_slave_0_data_in),
.slave_select_in (spi_slave_0_slave_select_in),
.data_out (spi_slave_0_data_out),
// These ports are not in any interface
.rst_in (spi_slave_0_rst_in));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_TB_V
`define SKY130_FD_SC_MS__DFBBN_TB_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfbbn.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 RESET_B = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 RESET_B = 1'b0;
#340 SET_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SET_B = 1'b1;
#540 RESET_B = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SET_B = 1'bx;
#680 RESET_B = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ms__dfbbn dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_TB_V
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module counter_neg(
input negedge_clk,
input rx_resetn,
input rx_din,
output reg is_control,
output reg [5:0] counter_neg
);
reg control_bit_found;
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
is_control <= 1'b0;
control_bit_found <= 1'b0;
counter_neg <= 6'd1;
end
else
begin
control_bit_found <= rx_din;
case(counter_neg)
6'd1:
begin
counter_neg <= 6'd2;
end
6'd2:
begin
if(control_bit_found)
begin
is_control <= 1'b1;
end
else
begin
is_control <= 1'b0;
end
counter_neg <= 6'd4;
end
6'd4:
begin
is_control <= 1'b0;
if(is_control)
begin
counter_neg <= 6'd2;
end
else
begin
counter_neg <= 6'd8;
end
end
6'd8:
begin
is_control <= 1'b0;
counter_neg <= 6'd16;
end
6'd16:
begin
is_control <= 1'b0;
counter_neg <= 6'd32;
end
6'd32:
begin
is_control <= 1'b0;
counter_neg <= 6'd2;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_pg/sky130_fd_sc_hs__u_dfb_setdom_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hs__u_dfb_setdom_pg `UNIT_DELAY u_dfb_setdom_pg0 (buf_Q , SET, RESET, CLK, D, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module start_for_CvtColoudo_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module start_for_CvtColoudo (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_CvtColoudo_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_start_for_CvtColoudo_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
//
// N-dimensional wormhole dimension ordered decoder
//
// given input coordinates for the target of a message, and for the current node
// it will output a one hot vector which is which direction that header should be routed
//
//
`include "bsg_defines.v"
module bsg_wormhole_router_decoder_dor
#(parameter dims_p=2
// cord_dims_p is normally the same as dims_p. However, the override allows users to pass
// a larger cord array than necessary, useful for parameterizing between 1d/nd networks
,parameter cord_dims_p=dims_p
,parameter reverse_order_p=0 // e.g., 1->Y THEN X, 0->X THEN Y routing
// pass in the markers that delineates storage of dimension fields
// so for example {5, 4, 0} means dim0=[4-1:0], dim1=[5-1:4]
, parameter int cord_markers_pos_p[cord_dims_p:0] = '{ 5, 4, 0 }
, parameter output_dirs_lp=2*dims_p+1
)
(input [cord_markers_pos_p[dims_p]-1:0] target_cord_i
, input [cord_markers_pos_p[dims_p]-1:0] my_cord_i
, output [output_dirs_lp-1:0] req_o
);
genvar i;
logic [dims_p-1:0] eq, lt, gt;
for (i = 0; i < dims_p; i=i+1)
begin: rof
localparam upper_marker_lp = cord_markers_pos_p[i+1];
localparam lower_marker_lp = cord_markers_pos_p[i];
localparam local_cord_width_p = upper_marker_lp - lower_marker_lp;
wire [local_cord_width_p-1:0] targ_cord = target_cord_i[upper_marker_lp-1:lower_marker_lp];
wire [local_cord_width_p-1:0] my_cord = my_cord_i[upper_marker_lp-1:lower_marker_lp];
assign eq[i] = (targ_cord == my_cord);
assign lt[i] = (targ_cord < my_cord);
assign gt[i] = ~eq[i] & ~lt[i];
end // block: rof
// handle base case
assign req_o[0] = & eq; // processor is at 0 in enum
if (reverse_order_p)
begin: rev
assign req_o[(dims_p-1)*2+1] = lt[dims_p-1];
assign req_o[(dims_p-1)*2+1+1] = gt[dims_p-1];
if (dims_p > 1)
begin : fi1
for (i = (dims_p-1)-1; i >= 0; i--)
begin: rof3
assign req_o[i*2+1] = &eq[dims_p-1:i+1] & lt[i];
assign req_o[i*2+1+1] = &eq[dims_p-1:i+1] & gt[i];
end
end
end // if (reverse_order_p)
else
begin: fwd
assign req_o[1] = lt[0]; // down (W,N)
assign req_o[2] = gt[0]; // up (E,S)
for (i = 1; i < dims_p; i++)
begin: rof2
assign req_o[i*2+1] = (&eq[i-1:0]) & lt[i];
assign req_o[i*2+1+1] = (&eq[i-1:0]) & gt[i];
end
end // else: !if(reverse_order_p)
`ifndef SYNTHESIS
initial assert(bsg_noc_pkg::P == 0
&& bsg_noc_pkg::W == 1
&& bsg_noc_pkg::E == 2
&& bsg_noc_pkg::N == 3
&& bsg_noc_pkg::S == 4) else $error("%m: bsg_noc_pkg dirs are inconsistent with this module");
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_ls__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_ls__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_ls__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_V |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Advanced Mixed Mode Clock Manager (MMCM)
// /___/ /\ Filename : MMCME2_ADV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/07/08 - Initial version.
// 09/19/08 - Change CLKFBOUT_MULT to CLKFBOUT_MULT_F
// CLKOUT0_DIVIDE to CLKOUT0_DIVIDE_F
// 10/03/08 - Initial all signals.
// 10/30/08 - Clock source switching without reset (CR492263).
// 11/18/08 - Add timing check for DADDR[6:5].
// 12/02/08 - Fix bug of Duty cycle calculation (CR498696)
// 12/05/08 - change pll_res according to hardware spreadsheet (CR496137)
// 12/09/08 - Enable output at CLKFBOUT_MULT_F*8 for fraction mode (CR499322)
// 01/08/09 - Add phase and duty cycle checks for fraction divide (CR501181)
// 01/09/09 - make pll_res same for BANDWIDTH=HIGH and OPTIMIZED (CR496137)
// 01/14/09 - Fine phase shift wrap around to 0 after 56 times;
// - PSEN to PSDONE change to 12 PSCLK; RST minpusle to 5ns;
// - add pulldown to PWRDWN pin. (CR503425)
// 01/14/09 - increase clkout_en_time for fraction mode (CR499322)
// 01/21/09 - align CLKFBOUT to CLKIN for fraction mode (CR504602)
// 01/27/09 - update DRP register address (CR505271)
// 01/28/09 - assign clkout_en0 and clkout_en1 to 0 when RST=1 (CR505767)
// 02/03/09 - Fix bug in clkfb fine phase shift.
// - Add delay to clkout_en0_tmp (CR506530).
// 02/05/09 - Add ps_in_ps calculation to clkvco_delay when clkfb_fps_en=1.
// - round clk_ht clk_lt for duty_cycle (CR506531)
// 02/11/09 - Change VCO_FREQ_MAX and MIN to 1601 and 399 to cover the rounded
// error (CR507969)
// 02/25/09 - round clk_ht clk_lt for duty_cycle (509386)
// 02/26/09 - Fix for clkin and clkfbin stop case (CR503425)
// 03/04/09 - Fix for CLOCK_HOLD (CR510820).
// 03/27/09 - set default 1 to CLKINSEL pin (CR516951)
// 04/13/09 - Check vco range when CLKINSEL not connected (CR516951)
// 04/22/09 - Add reset to clkinstopped related signals (CR519102)
// 04/27/09 - Make duty cycle of fraction mode 50/50 (CR519505)
// 05/13/09 - Use period_avg for clkvco_delay calculation (CR521120)
// 07/23/09 - fix bug in clk0_dt (CR527643)
// 07/27/09 - Do divide when period_avg > 0 (CR528090)
// - Change DIVCLK_DIVIDE to 80 (CR525904)
// - Add initial lock setting (CR524523)
// - Update RES CP setting (CR524522)
// 07/31/09 - Add if else to handle the fracion and nonfraction for clkout_en.
// 08/10/09 - Calculate clkin_lost_val after lock_period=1 (CR528520).
// 08/15/09 - Update LFHF (CR524522)
// 08/19/09 - Set clkfb_lost_val initial value (CR531354)
// 08/28/09 - add clkin_period_tmp_t to handle period_avg calculation
// when clkin has jitter (CR528520)
// 09/11/09 - Change CLKIN_FREQ_MIN to 10 Mhz (CR532774)
// 10/01/09 - Change CLKIN_FREQ_MAX to 800Mhz (CR535076)
// Add reset check for clock switchover (CR534900)
// 10/08/09 - Change CLKIN_FREQ MAX & MIN, CLKPFD_FREQ
// MAX & MIN to parameter (CR535828)
// 10/14/09 - Add clkin_chk_t1 and clkin_chk_t2 to handle check (CR535662)
// 10/22/09 - Add period_vco_mf for clkvco_delay calculation (CR536951)
// Add cmpvco to compensate period_vco rounded error (CR537073)
// 12/02/09 - not stop clkvco_lk when jitter (CR538717)
// 01/08/10 - Change minimum RST pulse width from 5 ns to 1.5 ns
// Add 1 ns delay to locked_out_tmp when RST=1 (CR543857)
// 01/19/10 - make change to clkvoc_lk_tmp to handle M=1 case (CR544970)
// 02/09/10 - Add global PLL_LOCKG (CR547918)
// 02/23/10 - Not use edge for locked_out_tmp (CR549667)
// 03/04/10 - Change CLKFBOUT_MULT_F range to 5-64 (CR551618)
// 03/22/10 - Change CLKFBOUT_MULT_F default to 5 (554618)
// 03/24/10 - Add SIM_DEVICE attribute
// 04/07/10 - Generate clkvco_ps_tmp2_en correctly when ps_lock_dly rising
// and clkout_ps=1 case; increase lock_period time to 10 (CR556468)
// 05/07/10 - Use period_vco_half_rm1 to reduce jitter (CR558966)
// 07/28/10 - Update ref parameter values (CR569260)
// 08/17/10 - Add Decay output clocks when input clock stopped (CR555324)
// 09/03/10 - use %f for M_MIN and M_MAX (CR574247)
// 09/09/10 - Change to bus timing.
// 09/26/10 - Add RST to LOCKED timing path (CR567807)
// 02/22/11 - reduce clkin period check resolution to 0.001 (CR594003)
// 03/08/11 - Support fraction mode phase shifting with phase parameter
// setting (CR596402)
// 04/26/11 - Support fraction mode phase shifting with DRP(CR607989)
// 05/24/11 - Set frac_wf_f to 1 when divide=2.125 (CR611840)
// 06/06/11 - set period_vco_half_rm2 to 0 when period_vco=0 (CR613021)
// 06/08/11 - Disable clk0 fraction mode when CLKOUT0_DIVIDE_F in range
// greater than 1 and less than 2. Add DRC check for it (608893)
// 08/03/11 - use clk0_frac instead of clk0_sfrac (CR 618600)
// 10/26/11 - Add DRC check for samples CLKIN period with parameter setting (CR631150)
// Add spectrum attributes.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 02/22/12 - Modify DRC (638094).
// 03/01/12 - fraction enable for m/d (CR 648429)
// 03/07/12 - added vcoflag (CR 638088, CR 636493)
// 04/19/12 - 654951 - rounding issue with clk_out_para_cal
// 05/03/12 - ncsim issue with clkfb_frac_en (CR 655792)
// 05/03/12 - jittery clock (CR 652401)
// 05/03/12 - incorrect period (CR 654951)
// 05/10/12 - fractional divide calculation issue (CR 658151)
// 05/18/12 - fractional divide calculation issue (CR 660657)
// 06/11/12 - update cp and res settings (CR 664278)
// 06/20/12 - modify reset drc (CR 643540)
// 09/06/12 - 655711 - modify displayed MAX on CLK_DUTY_CYCLE
// 12/12/12 - fix clk_osc process for ncsim (CR 676829)
// 04/04/13 - fix clkvco_frac_en for DRP (CR 709093)
// 04/09/13 - Added DRP monitor (CR 695630).
// 05/03/13 - 670208 Fractional clock alignment issue
// 05/31/13 - 720783 - revert clock alignment fix
// 10/22/2014 808642 - Added #1 to $finish
// 11/26/2014 829050 - remove CLKIN -> CLKOUT* timing paths
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MMCME2_ADV #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter BANDWIDTH = "OPTIMIZED",
parameter real CLKFBOUT_MULT_F = 5.000,
parameter real CLKFBOUT_PHASE = 0.000,
parameter CLKFBOUT_USE_FINE_PS = "FALSE",
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKIN2_PERIOD = 0.000,
`ifdef XIL_TIMING
parameter real CLKIN_FREQ_MAX = 1066.000,
parameter real CLKIN_FREQ_MIN = 10.000,
`endif
parameter real CLKOUT0_DIVIDE_F = 1.000,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter CLKOUT0_USE_FINE_PS = "FALSE",
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter CLKOUT1_USE_FINE_PS = "FALSE",
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter CLKOUT2_USE_FINE_PS = "FALSE",
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter CLKOUT3_USE_FINE_PS = "FALSE",
parameter CLKOUT4_CASCADE = "FALSE",
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter CLKOUT4_USE_FINE_PS = "FALSE",
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter CLKOUT5_USE_FINE_PS = "FALSE",
parameter integer CLKOUT6_DIVIDE = 1,
parameter real CLKOUT6_DUTY_CYCLE = 0.500,
parameter real CLKOUT6_PHASE = 0.000,
parameter CLKOUT6_USE_FINE_PS = "FALSE",
`ifdef XIL_TIMING
parameter real CLKPFD_FREQ_MAX = 550.000,
parameter real CLKPFD_FREQ_MIN = 10.000,
`endif
parameter COMPENSATION = "ZHOLD",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
parameter [0:0] IS_PSEN_INVERTED = 1'b0,
parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter real REF_JITTER2 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter integer SS_MOD_PERIOD = 10000,
`ifdef XIL_TIMING
parameter STARTUP_WAIT = "FALSE",
parameter real VCOCLK_FREQ_MAX = 1600.000,
parameter real VCOCLK_FREQ_MIN = 600.000
`else
parameter STARTUP_WAIT = "FALSE"
`endif
)(
output CLKFBOUT,
output CLKFBOUTB,
output CLKFBSTOPPED,
output CLKINSTOPPED,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output [15:0] DO,
output DRDY,
output LOCKED,
output PSDONE,
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
input [6:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input PSCLK,
input PSEN,
input PSINCDEC,
input PWRDWN,
input RST
);
// define constants
localparam MODULE_NAME = "MMCME2_ADV";
// Parameter encodings and registers
localparam BANDWIDTH_HIGH = 1;
localparam BANDWIDTH_LOW = 2;
localparam BANDWIDTH_OPTIMIZED = 0;
localparam CLKFBOUT_USE_FINE_PS_FALSE = 0;
localparam CLKFBOUT_USE_FINE_PS_TRUE = 1;
localparam CLKOUT0_USE_FINE_PS_FALSE = 0;
localparam CLKOUT0_USE_FINE_PS_TRUE = 1;
localparam CLKOUT1_USE_FINE_PS_FALSE = 0;
localparam CLKOUT1_USE_FINE_PS_TRUE = 1;
localparam CLKOUT2_USE_FINE_PS_FALSE = 0;
localparam CLKOUT2_USE_FINE_PS_TRUE = 1;
localparam CLKOUT3_USE_FINE_PS_FALSE = 0;
localparam CLKOUT3_USE_FINE_PS_TRUE = 1;
localparam CLKOUT4_CASCADE_FALSE = 0;
localparam CLKOUT4_CASCADE_TRUE = 1;
localparam CLKOUT4_USE_FINE_PS_FALSE = 0;
localparam CLKOUT4_USE_FINE_PS_TRUE = 1;
localparam CLKOUT5_USE_FINE_PS_FALSE = 0;
localparam CLKOUT5_USE_FINE_PS_TRUE = 1;
localparam CLKOUT6_USE_FINE_PS_FALSE = 0;
localparam CLKOUT6_USE_FINE_PS_TRUE = 1;
localparam COMPENSATION_BUF_IN = 1;
localparam COMPENSATION_EXTERNAL = 2;
localparam COMPENSATION_INTERNAL = 3;
localparam COMPENSATION_ZHOLD = 4;
localparam SS_EN_FALSE = 0;
localparam SS_EN_TRUE = 1;
localparam SS_MODE_CENTER_HIGH = 0;
localparam SS_MODE_CENTER_LOW = 1;
localparam SS_MODE_DOWN_HIGH = 2;
localparam SS_MODE_DOWN_LOW = 3;
localparam STARTUP_WAIT_FALSE = 0;
localparam STARTUP_WAIT_TRUE = 1;
`ifndef XIL_TIMING
localparam real CLKIN_FREQ_MAX = 1066.0;
localparam real CLKIN_FREQ_MIN = 10.0;
localparam real CLKPFD_FREQ_MAX = 550.0;
localparam real CLKPFD_FREQ_MIN = 10.0;
localparam real VCOCLK_FREQ_MAX = 1600.0;
localparam real VCOCLK_FREQ_MIN = 600.0;
`endif
reg trig_attr = 1'b0;
localparam [72:1] BANDWIDTH_REG = BANDWIDTH;
localparam real CLKFBOUT_MULT_F_REG = CLKFBOUT_MULT_F;
localparam real CLKFBOUT_PHASE_REG = CLKFBOUT_PHASE;
localparam [40:1] CLKFBOUT_USE_FINE_PS_REG = CLKFBOUT_USE_FINE_PS;
localparam real CLKIN1_PERIOD_REG = CLKIN1_PERIOD;
localparam real CLKIN2_PERIOD_REG = CLKIN2_PERIOD;
localparam real CLKIN_FREQ_MAX_REG = CLKIN_FREQ_MAX;
localparam real CLKIN_FREQ_MIN_REG = CLKIN_FREQ_MIN;
localparam real CLKOUT0_DIVIDE_F_REG = CLKOUT0_DIVIDE_F;
localparam real CLKOUT0_DUTY_CYCLE_REG = CLKOUT0_DUTY_CYCLE;
localparam real CLKOUT0_PHASE_REG = CLKOUT0_PHASE;
localparam [40:1] CLKOUT0_USE_FINE_PS_REG = CLKOUT0_USE_FINE_PS;
localparam [7:0] CLKOUT1_DIVIDE_REG = CLKOUT1_DIVIDE;
localparam real CLKOUT1_DUTY_CYCLE_REG = CLKOUT1_DUTY_CYCLE;
localparam real CLKOUT1_PHASE_REG = CLKOUT1_PHASE;
localparam [40:1] CLKOUT1_USE_FINE_PS_REG = CLKOUT1_USE_FINE_PS;
localparam [7:0] CLKOUT2_DIVIDE_REG = CLKOUT2_DIVIDE;
localparam real CLKOUT2_DUTY_CYCLE_REG = CLKOUT2_DUTY_CYCLE;
localparam real CLKOUT2_PHASE_REG = CLKOUT2_PHASE;
localparam [40:1] CLKOUT2_USE_FINE_PS_REG = CLKOUT2_USE_FINE_PS;
localparam [7:0] CLKOUT3_DIVIDE_REG = CLKOUT3_DIVIDE;
localparam real CLKOUT3_DUTY_CYCLE_REG = CLKOUT3_DUTY_CYCLE;
localparam real CLKOUT3_PHASE_REG = CLKOUT3_PHASE;
localparam [40:1] CLKOUT3_USE_FINE_PS_REG = CLKOUT3_USE_FINE_PS;
localparam [40:1] CLKOUT4_CASCADE_REG = CLKOUT4_CASCADE;
localparam [7:0] CLKOUT4_DIVIDE_REG = CLKOUT4_DIVIDE;
localparam real CLKOUT4_DUTY_CYCLE_REG = CLKOUT4_DUTY_CYCLE;
localparam real CLKOUT4_PHASE_REG = CLKOUT4_PHASE;
localparam [40:1] CLKOUT4_USE_FINE_PS_REG = CLKOUT4_USE_FINE_PS;
localparam [7:0] CLKOUT5_DIVIDE_REG = CLKOUT5_DIVIDE;
localparam real CLKOUT5_DUTY_CYCLE_REG = CLKOUT5_DUTY_CYCLE;
localparam real CLKOUT5_PHASE_REG = CLKOUT5_PHASE;
localparam [40:1] CLKOUT5_USE_FINE_PS_REG = CLKOUT5_USE_FINE_PS;
localparam [7:0] CLKOUT6_DIVIDE_REG = CLKOUT6_DIVIDE;
localparam real CLKOUT6_DUTY_CYCLE_REG = CLKOUT6_DUTY_CYCLE;
localparam real CLKOUT6_PHASE_REG = CLKOUT6_PHASE;
localparam [40:1] CLKOUT6_USE_FINE_PS_REG = CLKOUT6_USE_FINE_PS;
localparam real CLKPFD_FREQ_MAX_REG = CLKPFD_FREQ_MAX;
localparam real CLKPFD_FREQ_MIN_REG = CLKPFD_FREQ_MIN;
localparam [64:1] COMPENSATION_REG = COMPENSATION;
localparam [6:0] DIVCLK_DIVIDE_REG = DIVCLK_DIVIDE;
localparam [0:0] IS_CLKINSEL_INVERTED_REG = IS_CLKINSEL_INVERTED;
localparam [0:0] IS_PSEN_INVERTED_REG = IS_PSEN_INVERTED;
localparam [0:0] IS_PSINCDEC_INVERTED_REG = IS_PSINCDEC_INVERTED;
localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam real REF_JITTER1_REG = REF_JITTER1;
localparam real REF_JITTER2_REG = REF_JITTER2;
localparam [40:1] SS_EN_REG = SS_EN;
localparam [88:1] SS_MODE_REG = SS_MODE;
localparam [15:0] SS_MOD_PERIOD_REG = SS_MOD_PERIOD;
localparam [40:1] STARTUP_WAIT_REG = STARTUP_WAIT;
localparam real VCOCLK_FREQ_MAX_REG = VCOCLK_FREQ_MAX;
localparam real VCOCLK_FREQ_MIN_REG = VCOCLK_FREQ_MIN;
wire [1:0] BANDWIDTH_BIN;
wire [63:0] CLKFBOUT_MULT_F_BIN;
wire [63:0] CLKFBOUT_PHASE_BIN;
wire CLKFBOUT_USE_FINE_PS_BIN;
wire [63:0] CLKIN1_PERIOD_BIN;
wire [63:0] CLKIN2_PERIOD_BIN;
wire [63:0] CLKIN_FREQ_MAX_BIN;
wire [63:0] CLKIN_FREQ_MIN_BIN;
wire [63:0] CLKOUT0_DIVIDE_F_BIN;
wire [63:0] CLKOUT0_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT0_PHASE_BIN;
wire CLKOUT0_USE_FINE_PS_BIN;
wire [7:0] CLKOUT1_DIVIDE_BIN;
wire [63:0] CLKOUT1_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT1_PHASE_BIN;
wire CLKOUT1_USE_FINE_PS_BIN;
wire [7:0] CLKOUT2_DIVIDE_BIN;
wire [63:0] CLKOUT2_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT2_PHASE_BIN;
wire CLKOUT2_USE_FINE_PS_BIN;
wire [7:0] CLKOUT3_DIVIDE_BIN;
wire [63:0] CLKOUT3_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT3_PHASE_BIN;
wire CLKOUT3_USE_FINE_PS_BIN;
wire CLKOUT4_CASCADE_BIN;
wire [7:0] CLKOUT4_DIVIDE_BIN;
wire [63:0] CLKOUT4_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT4_PHASE_BIN;
wire CLKOUT4_USE_FINE_PS_BIN;
wire [7:0] CLKOUT5_DIVIDE_BIN;
wire [63:0] CLKOUT5_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT5_PHASE_BIN;
wire CLKOUT5_USE_FINE_PS_BIN;
wire [7:0] CLKOUT6_DIVIDE_BIN;
wire [63:0] CLKOUT6_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT6_PHASE_BIN;
wire CLKOUT6_USE_FINE_PS_BIN;
wire [63:0] CLKPFD_FREQ_MAX_BIN;
wire [63:0] CLKPFD_FREQ_MIN_BIN;
wire [2:0] COMPENSATION_BIN;
wire [6:0] DIVCLK_DIVIDE_BIN;
wire IS_CLKINSEL_INVERTED_BIN;
wire IS_PSEN_INVERTED_BIN;
wire IS_PSINCDEC_INVERTED_BIN;
wire IS_PWRDWN_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
wire [63:0] REF_JITTER1_BIN;
wire [63:0] REF_JITTER2_BIN;
wire SS_EN_BIN;
wire [1:0] SS_MODE_BIN;
wire [15:0] SS_MOD_PERIOD_BIN;
wire STARTUP_WAIT_BIN;
wire [63:0] VCOCLK_FREQ_MAX_BIN;
wire [63:0] VCOCLK_FREQ_MIN_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire CLKFBOUTB_out;
reg CLKFBOUT_out;
reg CLKFBSTOPPED_out = 0;
reg CLKINSTOPPED_out = 0;
wire CLKOUT0B_out;
reg CLKOUT0_out;
wire CLKOUT1B_out;
reg CLKOUT1_out;
wire CLKOUT2B_out;
reg CLKOUT2_out;
wire CLKOUT3B_out;
reg CLKOUT3_out;
reg CLKOUT4_out;
reg CLKOUT5_out;
reg CLKOUT6_out;
reg DRDY_out;
reg LOCKED_out = 1'b0;
reg PSDONE_out;
reg [15:0] DO_out;
wire CLKFBIN_in;
wire CLKIN1_in;
wire CLKIN2_in;
wire CLKINSEL_in;
wire DCLK_in;
wire DEN_in;
wire DWE_in;
wire PSCLK_in;
wire PSEN_in;
wire PSINCDEC_in;
wire PWRDWN_in;
wire RST_in;
wire [15:0] DI_in;
wire [6:0] DADDR_in;
`ifdef XIL_TIMING
wire DCLK_delay;
wire DEN_delay;
wire DWE_delay;
wire PSCLK_delay;
wire PSEN_delay;
wire PSINCDEC_delay;
wire [15:0] DI_delay;
wire [6:0] DADDR_delay;
`endif
assign CLKFBOUT = CLKFBOUT_out;
assign CLKFBOUTB = ~CLKFBOUT_out;
assign CLKFBSTOPPED = CLKFBSTOPPED_out;
assign CLKINSTOPPED = CLKINSTOPPED_out;
assign CLKOUT0 = CLKOUT0_out;
assign CLKOUT0B = ~CLKOUT0_out;
assign CLKOUT1 = CLKOUT1_out;
assign CLKOUT1B = ~CLKOUT1_out;
assign CLKOUT2 = CLKOUT2_out;
assign CLKOUT2B = ~CLKOUT2_out;
assign CLKOUT3 = CLKOUT3_out;
assign CLKOUT3B = ~CLKOUT3_out;
assign CLKOUT4 = CLKOUT4_out;
assign CLKOUT5 = CLKOUT5_out;
assign CLKOUT6 = CLKOUT6_out;
assign DO = DO_out;
assign DRDY = DRDY_out;
assign LOCKED = LOCKED_out;
assign PSDONE = PSDONE_out;
//inputs with timing
`ifdef XIL_TIMING
assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR_delay[0]; // rv 0
assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR_delay[1]; // rv 0
assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR_delay[2]; // rv 0
assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR_delay[3]; // rv 0
assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR_delay[4]; // rv 0
assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR_delay[5]; // rv 0
assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR_delay[6]; // rv 0
assign DCLK_in = (DCLK !== 1'bz) && DCLK_delay; // rv 0
assign DEN_in = (DEN !== 1'bz) && DEN_delay; // rv 0
assign DI_in[0] = (DI[0] !== 1'bz) && DI_delay[0]; // rv 0
assign DI_in[10] = (DI[10] !== 1'bz) && DI_delay[10]; // rv 0
assign DI_in[11] = (DI[11] !== 1'bz) && DI_delay[11]; // rv 0
assign DI_in[12] = (DI[12] !== 1'bz) && DI_delay[12]; // rv 0
assign DI_in[13] = (DI[13] !== 1'bz) && DI_delay[13]; // rv 0
assign DI_in[14] = (DI[14] !== 1'bz) && DI_delay[14]; // rv 0
assign DI_in[15] = (DI[15] !== 1'bz) && DI_delay[15]; // rv 0
assign DI_in[1] = (DI[1] !== 1'bz) && DI_delay[1]; // rv 0
assign DI_in[2] = (DI[2] !== 1'bz) && DI_delay[2]; // rv 0
assign DI_in[3] = (DI[3] !== 1'bz) && DI_delay[3]; // rv 0
assign DI_in[4] = (DI[4] !== 1'bz) && DI_delay[4]; // rv 0
assign DI_in[5] = (DI[5] !== 1'bz) && DI_delay[5]; // rv 0
assign DI_in[6] = (DI[6] !== 1'bz) && DI_delay[6]; // rv 0
assign DI_in[7] = (DI[7] !== 1'bz) && DI_delay[7]; // rv 0
assign DI_in[8] = (DI[8] !== 1'bz) && DI_delay[8]; // rv 0
assign DI_in[9] = (DI[9] !== 1'bz) && DI_delay[9]; // rv 0
assign DWE_in = (DWE !== 1'bz) && DWE_delay; // rv 0
assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK_delay; // rv 0
assign PSEN_in = (PSEN !== 1'bz) && (PSEN_delay ^ IS_PSEN_INVERTED_BIN); // rv 0
assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC_delay ^ IS_PSINCDEC_INVERTED_BIN); // rv 0
`else
assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR[0]; // rv 0
assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR[1]; // rv 0
assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR[2]; // rv 0
assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR[3]; // rv 0
assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR[4]; // rv 0
assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR[5]; // rv 0
assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR[6]; // rv 0
assign DCLK_in = (DCLK !== 1'bz) && DCLK; // rv 0
assign DEN_in = (DEN !== 1'bz) && DEN; // rv 0
assign DI_in[0] = (DI[0] !== 1'bz) && DI[0]; // rv 0
assign DI_in[10] = (DI[10] !== 1'bz) && DI[10]; // rv 0
assign DI_in[11] = (DI[11] !== 1'bz) && DI[11]; // rv 0
assign DI_in[12] = (DI[12] !== 1'bz) && DI[12]; // rv 0
assign DI_in[13] = (DI[13] !== 1'bz) && DI[13]; // rv 0
assign DI_in[14] = (DI[14] !== 1'bz) && DI[14]; // rv 0
assign DI_in[15] = (DI[15] !== 1'bz) && DI[15]; // rv 0
assign DI_in[1] = (DI[1] !== 1'bz) && DI[1]; // rv 0
assign DI_in[2] = (DI[2] !== 1'bz) && DI[2]; // rv 0
assign DI_in[3] = (DI[3] !== 1'bz) && DI[3]; // rv 0
assign DI_in[4] = (DI[4] !== 1'bz) && DI[4]; // rv 0
assign DI_in[5] = (DI[5] !== 1'bz) && DI[5]; // rv 0
assign DI_in[6] = (DI[6] !== 1'bz) && DI[6]; // rv 0
assign DI_in[7] = (DI[7] !== 1'bz) && DI[7]; // rv 0
assign DI_in[8] = (DI[8] !== 1'bz) && DI[8]; // rv 0
assign DI_in[9] = (DI[9] !== 1'bz) && DI[9]; // rv 0
assign DWE_in = (DWE !== 1'bz) && DWE; // rv 0
assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK; // rv 0
assign PSEN_in = (PSEN !== 1'bz) && (PSEN ^ IS_PSEN_INVERTED_BIN); // rv 0
assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC ^ IS_PSINCDEC_INVERTED_BIN); // rv 0
`endif
assign CLKFBIN_in = (CLKFBIN !== 1'bz) && CLKFBIN; // rv 0
assign CLKIN1_in = (CLKIN1 !== 1'bz) && CLKIN1; // rv 0
assign CLKIN2_in = (CLKIN2 !== 1'bz) && CLKIN2; // rv 0
assign CLKINSEL_in = (CLKINSEL === 1'bz) || (CLKINSEL ^ IS_CLKINSEL_INVERTED_BIN); // rv 1
assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_BIN); // rv 0
assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_BIN); // rv 0
localparam VCOCLK_FREQ_TARGET = 1000;
localparam M_MIN = 2.000;
localparam M_MAX = 64.000;
localparam real VF_MIN = 600.000;
localparam D_MIN = 1;
localparam D_MAX = 106;
localparam O_MIN = 1;
localparam O_MAX = 128;
localparam O_MAX_HT_LT = 64;
localparam REF_CLK_JITTER_MAX = 1000;
localparam REF_CLK_JITTER_SCALE = 0.1;
localparam MAX_FEEDBACK_DELAY = 10.0;
localparam MAX_FEEDBACK_DELAY_SCALE = 1.0;
localparam ps_max = 55;
real CLKOUT0_DIVIDE_F_RND;
real CLKFBOUT_MULT_F_RND;
tri1 p_up;
wire glock;
integer pchk_tmp1, pchk_tmp2;
integer clkvco_div_fint;
real clkvco_div_frac;
reg clk0_out;
reg clkfbout_out;
integer clkvco_frac_en;
integer ps_in_init;
reg psdone_out1;
wire clk0_fps_en, clk1_fps_en, clk2_fps_en, clk3_fps_en, clk4_fps_en;
wire clk5_fps_en, clk6_fps_en, clkfbout_fps_en;
reg fps_en=1'b0, fps_clk_en=1'b0;
reg clkinstopped_out1;
reg clkin_hold_f = 0;
reg clkinstopped_out_dly2 = 0, clkin_stop_f = 0;
integer period_avg_stpi = 0, period_avg_stp = 0;
real tmp_stp1, tmp_stp2;
reg pd_stp_p = 0;
reg vco_stp_f = 0;
reg psen_w = 0;
reg clkinstopped_out_dly = 0;
reg clkfbin_stop_tmp, clkfbstopped_out1, clkin_stop_tmp;
reg rst_clkinstopped = 0, rst_clkfbstopped = 0, rst_clkinstopped_tm = 0;
reg rst_clkinstopped_rc = 0;
reg rst_clkinstopped_lk, rst_clkfbstopped_lk;
integer clkin_lost_cnt, clkfbin_lost_cnt;
reg clkinstopped_hold = 0;
integer ps_in_ps, ps_cnt;
integer ps_in_ps_neg, ps_cnt_neg;
wire clkout4_cascade_int;
reg [6:0] daddr_lat;
reg valid_daddr;
reg drdy_out1;
reg drp_lock;
integer drp_lock_lat = 4;
integer drp_lock_lat_cnt;
reg [15:0] dr_sram [127:0];
reg [160:0] tmp_string;
reg rst_int;
reg pwron_int;
wire rst_in_o;
wire locked_out1;
reg locked_out_tmp;
reg clk1_out, clk2_out, clk3_out, clk4_out, clk5_out, clk6_out;
reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp, clkout_en0_tmp1;
integer clkout_en_val, clkout_en_t;
integer clkin_lock_cnt;
integer clkout_en_time, locked_en_time, lock_cnt_max;
integer pll_lock_time, lock_period_time;
reg clkvco;
reg clkvco_lk_dly_tmp;
reg clkvco_lk_en;
reg clkvco_lk;
reg fbclk_tmp;
reg clkin_osc, clkin_p, clkfbin_osc, clkfbin_p;
reg clkinstopped_vco_f;
time rst_edge, rst_ht;
reg fb_delay_found=1'b0, fb_delay_found_tmp=1'b0;
reg clkfbout_tst=1'b0;
real fb_delay_max;
time fb_delay, clkvco_delay, val_tmp, dly_tmp, fb_comp_delay;
time dly_tmp1, tmp_ps_val2;
integer dly_tmp_int, tmp_ps_val1;
time clkin_edge, delay_edge;
real period_clkin, clkin_period_tmp;
integer clkin_period_tmp_t;
integer clkin_period [4:0];
integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm;
real period_vco_rl, period_vco_rl_half;
integer period_vco_half_rm1, period_vco_half_rm2;
real cmpvco = 0.0;
real clkvco_pdrm;
integer period_vco_mf;
integer period_vco_tmp;
integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt;
integer period_vco_cmp_flag;
integer period_vco_max, period_vco_min;
integer period_vco1, period_vco2, period_vco3, period_vco4;
integer period_vco5, period_vco6, period_vco7;
integer period_vco_target, period_vco_target_half;
integer period_fb=100000, period_avg=100000;
integer clk0_frac_lt, clk0_frac_ht;
integer clkfbout_frac_lt, clkfbout_frac_ht;
integer period_ps, period_ps_old;
reg ps_lock, ps_lock_dly;
real clkvco_freq_init_chk, clkfbout_pm_rl;
real tmp_real;
integer ik0, ik1, ik2, ik3, ik4, ib, i, j;
integer md_product, m_product, m_product2;
integer mf_product, clk0f_product;
// integer clkin_lost_val, clkfbin_lost_val, clkin_lost_val_lk;
integer clkin_lost_val, clkfbin_lost_val;
time pll_locked_delay, clkin_dly_t, clkfbin_dly_t;
wire pll_unlock, pll_unlock1;
reg pll_locked_tmp1, pll_locked_tmp2;
reg lock_period;
reg pll_locked_tm, unlock_recover;
reg clkpll_jitter_unlock;
integer clkin_jit, REF_CLK_JITTER_MAX_tmp;
wire init_trig, clkpll_r;
reg clk0in=1'b0,clk1in=1'b0,clk2in=1'b0,clk3in=1'b0,clk4in=1'b0,clk5in=1'b0,clk6in=1'b0;
reg clkpll_tmp1, clkpll;
reg clkfboutin=1'b0;
wire clkfbps_en;
reg chk_ok;
wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en, clk4ps_en, clk5ps_en, clk6ps_en;
reg [3:0] d_rsel, clkfbout_rsel, clk0_rsel;
reg [3:0] d_fsel, clkfbout_fsel, clk0_fsel;
reg [6:0] d_fht, clkfbout_fht, clk0_fht;
reg [6:0] d_flt, clkfbout_flt, clk0_flt;
reg [5:0] clk0_dly_cnt;
reg [5:0] clk1_dly_cnt;
reg [5:0] clk2_dly_cnt;
reg [5:0] clk3_dly_cnt;
reg [5:0] clk4_dly_cnt;
reg [5:0] clk5_dly_cnt;
reg [5:0] clk6_dly_cnt;
real clk0_phase, clk0_duty;
real clk1_phase, clk1_duty;
real clk2_phase, clk2_duty;
real clk3_phase, clk3_duty;
real clk4_phase, clk4_duty;
real clk5_phase, clk5_duty;
real clk6_phase, clk6_duty;
real divclk_phase=0.000, divclk_duty=0.500;
real clkfbout_phase, clkfbout_duty=0.500;
// mem cells
reg [2:0] d_frac, clkfbout_frac, clk0_frac;
reg d_frac_en, clkfbout_frac_en, clk0_frac_en;
reg d_wf_f, clkfbout_wf_f, clk0_wf_f;
reg d_wf_r, clkfbout_wf_r, clk0_wf_r;
reg [2:0] d_mx, clkfbout_mx, clk0_mx, clk1_mx, clk2_mx, clk3_mx, clk4_mx, clk5_mx, clk6_mx;
reg divclk_e, clkfbin_e;
reg clkfbout_e, clk0_e, clk1_e, clk2_e, clk3_e, clk4_e, clk5_e, clk6_e;
reg divclk_nc, clkfbin_nc;
reg clkfbout_nc, clk0_nc, clk1_nc, clk2_nc, clk3_nc, clk4_nc, clk5_nc, clk6_nc;
reg [5:0] d_dt, clkfbout_dt, clk0_dt, clk1_dt, clk2_dt, clk3_dt, clk4_dt, clk5_dt, clk6_dt;
reg [2:0] d_pm_f, clkfbout_pm_f, clk0_pm_f;
reg [2:0] clkfbout_pm_r, clk0_pm_r;
reg [2:0] d_pm, clk1_pm, clk2_pm, clk3_pm, clk4_pm, clk5_pm, clk6_pm;
reg divclk_en, clkfbout_en, clk0_en, clk1_en, clk2_en, clk3_en, clk4_en, clk5_en, clk6_en;
reg [5:0] clkfbin_ht;
reg [7:0] divclk_ht;
reg [5:0] clkfbout_ht, clk0_ht, clk1_ht, clk2_ht, clk3_ht, clk4_ht, clk5_ht, clk6_ht;
reg [5:0] clkfbin_lt;
reg [7:0] divclk_lt;
reg [6:0] clkfbout_lt, clk0_lt, clk1_lt, clk2_lt, clk3_lt, clk4_lt, clk5_lt, clk6_lt;
//
real clkfbout_f_div=1.0;
real clk0_f_div;
integer d_div, clkfbout_div, clk0_div;
reg [5:0] clkfbout_dly_cnt;
reg [7:0] clkfbout_cnt;
reg [7:0] clk0_cnt;
reg [7:0] clk1_cnt, clk1_div;
reg [7:0] clk2_cnt, clk2_div;
reg [7:0] clk3_cnt, clk3_div;
reg [7:0] clk4_cnt, clk4_div;
reg [7:0] clk5_cnt, clk5_div;
reg [7:0] clk6_cnt, clk6_div;
integer divclk_cnt_max, clkfbout_cnt_max, clk0_cnt_max;
integer clk1_cnt_max, clk2_cnt_max, clk3_cnt_max, clk4_cnt_max, clk5_cnt_max, clk6_cnt_max;
integer divclk_cnt_ht, clkfbout_cnt_ht, clk0_cnt_ht;
integer clk1_cnt_ht, clk2_cnt_ht, clk3_cnt_ht, clk4_cnt_ht, clk5_cnt_ht, clk6_cnt_ht;
reg [7:0] divclk_div=8'b1, divclk_cnt=8'b0;
reg divclk_out, divclk_out_tmp;
reg [3:0] pll_cp, pll_res;
reg [1:0] pll_lfhf;
reg [1:0] pll_cpres = 2'b01;
reg [4:0] drp_lock_ref_dly;
reg [4:0] drp_lock_fb_dly;
reg [9:0] drp_lock_cnt;
reg [9:0] drp_unlock_cnt;
reg [9:0] drp_lock_sat_high;
wire clkinsel_tmp;
real clkin_chk_t1, clkin_chk_t2;
real clkin_chk_t1_r, clkin_chk_t2_r;
integer clkin_chk_t1_i, clkin_chk_t2_i;
reg init_chk;
reg rst_clkinsel_flag = 0;
wire [15:0] do_out1;
wire pwrdwn_in1;
reg pwrdwn_in1_h = 0;
reg rst_input_r_h = 0;
reg pchk_clr = 0;
reg psincdec_chg = 0;
reg psincdec_chg_tmp = 0;
wire rst_input;
wire startup_wait_sig;
reg vcoflag = 0;
reg drp_updt = 1'b0;
real halfperiod_sum = 0.0;
integer halfperiod = 0;
reg clkvco_free = 1'b0;
integer ik10, ik11;
//drp monitor
reg den_r1 = 1'b0;
reg den_r2 = 1'b0;
reg dwe_r1 = 1'b0;
reg dwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge DCLK_in)
begin
// pipeline the DEN and DWE
den_r1 <= DEN_in;
dwe_r1 <= DWE_in;
den_r2 <= den_r1;
dwe_r2 <= dwe_r1;
// Check - if DEN or DWE is more than 1 DCLK
if ((den_r1 == 1'b1) && (den_r2 == 1'b1))
begin
$display("DRC Error : DEN is high for more than 1 DCLK. Instance %m");
$finish;
end
if ((dwe_r1 == 1'b1) && (dwe_r2 == 1'b1))
begin
$display("DRC Error : DWE is high for more than 1 DCLK. Instance %m");
$finish;
end
//After the 1st DEN pulse, check the DEN and DRDY.
case (sfsm)
FSM_IDLE:
begin
if(DEN_in == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DEN, 4 cases can happen
// DEN DRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DEN and DRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(DEN_in === 1'b1 && DRDY_out === 1'b0)
begin
$display("DRC Error : DEN is enabled before DRDY returns. Instance %m");
$finish;
end
//Add the check for another DWE pulse
if ((DWE_in === 1'b1) && (DEN_in === 1'b0))
begin
$display("DRC Error : DWE is enabled before DRDY returns. Instance %m");
$finish;
end
if ((DRDY_out === 1'b1) && (DEN_in === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((DRDY_out === 1'b1) && (DEN_in === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM. Instance %m");
$finish;
end
endcase
end // always @ (posedge DCLK)
//end drp monitor
always @(locked_out_tmp)
LOCKED_out = locked_out_tmp;
always @(drdy_out1)
DRDY_out = drdy_out1;
always @(do_out1)
DO_out = do_out1;
always @(psdone_out1)
PSDONE_out = psdone_out1;
assign clkfbout_fps_en =
(CLKFBOUT_USE_FINE_PS_REG == "FALSE") ? CLKFBOUT_USE_FINE_PS_FALSE :
(CLKFBOUT_USE_FINE_PS_REG == "TRUE") ? CLKFBOUT_USE_FINE_PS_TRUE :
CLKFBOUT_USE_FINE_PS_FALSE;
assign clk0_fps_en =
(CLKOUT0_USE_FINE_PS_REG == "FALSE") ? CLKOUT0_USE_FINE_PS_FALSE :
(CLKOUT0_USE_FINE_PS_REG == "TRUE") ? CLKOUT0_USE_FINE_PS_TRUE :
CLKOUT0_USE_FINE_PS_FALSE;
assign clk1_fps_en =
(CLKOUT1_USE_FINE_PS_REG == "FALSE") ? CLKOUT1_USE_FINE_PS_FALSE :
(CLKOUT1_USE_FINE_PS_REG == "TRUE") ? CLKOUT1_USE_FINE_PS_TRUE :
CLKOUT1_USE_FINE_PS_FALSE;
assign clk2_fps_en =
(CLKOUT2_USE_FINE_PS_REG == "FALSE") ? CLKOUT2_USE_FINE_PS_FALSE :
(CLKOUT2_USE_FINE_PS_REG == "TRUE") ? CLKOUT2_USE_FINE_PS_TRUE :
CLKOUT2_USE_FINE_PS_FALSE;
assign clk3_fps_en =
(CLKOUT3_USE_FINE_PS_REG == "FALSE") ? CLKOUT3_USE_FINE_PS_FALSE :
(CLKOUT3_USE_FINE_PS_REG == "TRUE") ? CLKOUT3_USE_FINE_PS_TRUE :
CLKOUT3_USE_FINE_PS_FALSE;
assign clkout4_cascade_int =
(CLKOUT4_CASCADE_REG == "FALSE") ? CLKOUT4_CASCADE_FALSE :
(CLKOUT4_CASCADE_REG == "TRUE") ? CLKOUT4_CASCADE_TRUE :
CLKOUT4_CASCADE_FALSE;
assign clk4_fps_en =
(CLKOUT4_USE_FINE_PS_REG == "FALSE") ? CLKOUT4_USE_FINE_PS_FALSE :
(CLKOUT4_USE_FINE_PS_REG == "TRUE") ? CLKOUT4_USE_FINE_PS_TRUE :
CLKOUT4_USE_FINE_PS_FALSE;
assign clk5_fps_en =
(CLKOUT5_USE_FINE_PS_REG == "FALSE") ? CLKOUT5_USE_FINE_PS_FALSE :
(CLKOUT5_USE_FINE_PS_REG == "TRUE") ? CLKOUT5_USE_FINE_PS_TRUE :
CLKOUT5_USE_FINE_PS_FALSE;
assign clk6_fps_en =
(CLKOUT6_USE_FINE_PS_REG == "FALSE") ? CLKOUT6_USE_FINE_PS_FALSE :
(CLKOUT6_USE_FINE_PS_REG == "TRUE") ? CLKOUT6_USE_FINE_PS_TRUE :
CLKOUT6_USE_FINE_PS_FALSE;
assign IS_CLKINSEL_INVERTED_BIN = IS_CLKINSEL_INVERTED_REG;
assign IS_PSEN_INVERTED_BIN = IS_PSEN_INVERTED_REG;
assign IS_PSINCDEC_INVERTED_BIN = IS_PSINCDEC_INVERTED_REG;
assign IS_PWRDWN_INVERTED_BIN = IS_PWRDWN_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
assign startup_wait_sig =
(STARTUP_WAIT_REG == "FALSE") ? STARTUP_WAIT_FALSE :
(STARTUP_WAIT_REG == "TRUE") ? STARTUP_WAIT_TRUE :
STARTUP_WAIT_FALSE;
initial begin
#1;
if ($realtime == 0) begin
$display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME);
$display ("The simulator resolution must be set to 1ps or smaller. Instance %m");
#1 $finish;
end
end
initial begin
#1;
if ((attr_test == 1'b1) ||
((BANDWIDTH_REG != "OPTIMIZED") &&
(BANDWIDTH_REG != "HIGH") &&
(BANDWIDTH_REG != "LOW"))) begin
$display("Error: [Unisim %s-101] BANDWIDTH attribute is set to %s. Legal values for this attribute are OPTIMIZED, HIGH or LOW. Instance: %m", MODULE_NAME, BANDWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKFBOUT_MULT_F_REG < 2.000 || CLKFBOUT_MULT_F_REG > M_MAX)) begin
$display("Error: [Unisim %s-102] CLKFBOUT_MULT_F attribute is set to %f. Legal values for this attribute are 2.000 to %3.3f. Instance: %m", MODULE_NAME, CLKFBOUT_MULT_F_REG, M_MAX);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKFBOUT_PHASE_REG < -360.000 || CLKFBOUT_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-103] CLKFBOUT_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKFBOUT_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKFBOUT_USE_FINE_PS_REG != "TRUE") &&
(CLKFBOUT_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-104] CLKFBOUT_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKFBOUT_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKIN1_PERIOD_REG < 0.000 || CLKIN1_PERIOD_REG > 100.000)) begin
$display("Error: [Unisim %s-105] CLKIN1_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN1_PERIOD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKIN2_PERIOD_REG < 0.000 || CLKIN2_PERIOD_REG > 100.000)) begin
$display("Error: [Unisim %s-106] CLKIN2_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN2_PERIOD_REG);
attr_err = 1'b1;
end
`ifdef XIL_TIMING
if ((attr_test == 1'b1) ||
(CLKIN_FREQ_MAX_REG < 800.000 || CLKIN_FREQ_MAX_REG > 1066.000)) begin
$display("Error: [Unisim %s-107] CLKIN_FREQ_MAX attribute is set to %f. Legal values for this attribute are 800.000 to 1066.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MAX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKIN_FREQ_MIN_REG < 10.000 || CLKIN_FREQ_MIN_REG > 10.000)) begin
$display("Error: [Unisim %s-108] CLKIN_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MIN_REG);
attr_err = 1'b1;
end
`endif
if ((attr_test == 1'b1) ||
(CLKOUT0_DIVIDE_F_REG < 1.000 || CLKOUT0_DIVIDE_F_REG > 128.000)) begin
$display("Error: [Unisim %s-109] CLKOUT0_DIVIDE_F attribute is set to %f. Legal values for this attribute are 1.000 to 128.000. Instance: %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT0_DUTY_CYCLE_REG < 0.001 || CLKOUT0_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-110] CLKOUT0_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT0_PHASE_REG < -360.000 || CLKOUT0_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-111] CLKOUT0_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT0_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT0_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT0_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-112] CLKOUT0_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT0_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT1_DIVIDE_REG < 1) || (CLKOUT1_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-113] CLKOUT1_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT1_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT1_DUTY_CYCLE_REG < 0.001 || CLKOUT1_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-114] CLKOUT1_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT1_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT1_PHASE_REG < -360.000 || CLKOUT1_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-115] CLKOUT1_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT1_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT1_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT1_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-116] CLKOUT1_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT1_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT2_DIVIDE_REG < 1) || (CLKOUT2_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-117] CLKOUT2_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT2_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT2_DUTY_CYCLE_REG < 0.001 || CLKOUT2_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-118] CLKOUT2_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT2_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT2_PHASE_REG < -360.000 || CLKOUT2_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-119] CLKOUT2_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT2_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT2_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT2_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-120] CLKOUT2_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT2_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT3_DIVIDE_REG < 1) || (CLKOUT3_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-121] CLKOUT3_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT3_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT3_DUTY_CYCLE_REG < 0.001 || CLKOUT3_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-122] CLKOUT3_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT3_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT3_PHASE_REG < -360.000 || CLKOUT3_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-123] CLKOUT3_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT3_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT3_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT3_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-124] CLKOUT3_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT3_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT4_CASCADE_REG != "FALSE") &&
(CLKOUT4_CASCADE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-125] CLKOUT4_CASCADE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT4_CASCADE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT4_DIVIDE_REG < 1) || (CLKOUT4_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-126] CLKOUT4_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT4_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT4_DUTY_CYCLE_REG < 0.001 || CLKOUT4_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-127] CLKOUT4_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT4_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT4_PHASE_REG < -360.000 || CLKOUT4_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-128] CLKOUT4_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT4_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT4_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT4_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-129] CLKOUT4_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT4_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT5_DIVIDE_REG < 1) || (CLKOUT5_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-130] CLKOUT5_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT5_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT5_DUTY_CYCLE_REG < 0.001 || CLKOUT5_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-131] CLKOUT5_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT5_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT5_PHASE_REG < -360.000 || CLKOUT5_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-132] CLKOUT5_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT5_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT5_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT5_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-133] CLKOUT5_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT5_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT6_DIVIDE_REG < 1) || (CLKOUT6_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-134] CLKOUT6_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT6_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT6_DUTY_CYCLE_REG < 0.001 || CLKOUT6_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-135] CLKOUT6_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT6_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT6_PHASE_REG < -360.000 || CLKOUT6_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-136] CLKOUT6_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT6_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT6_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT6_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-137] CLKOUT6_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT6_USE_FINE_PS_REG);
attr_err = 1'b1;
end
`ifdef XIL_TIMING
if ((attr_test == 1'b1) ||
(CLKPFD_FREQ_MAX_REG < 450.000 || CLKPFD_FREQ_MAX_REG > 550.000)) begin
$display("Error: [Unisim %s-138] CLKPFD_FREQ_MAX attribute is set to %f. Legal values for this attribute are 450.000 to 550.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MAX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKPFD_FREQ_MIN_REG < 10.000 || CLKPFD_FREQ_MIN_REG > 10.000)) begin
$display("Error: [Unisim %s-139] CLKPFD_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MIN_REG);
attr_err = 1'b1;
end
`endif
if ((attr_test == 1'b1) ||
((COMPENSATION_REG != "ZHOLD") &&
(COMPENSATION_REG != "BUF_IN") &&
(COMPENSATION_REG != "EXTERNAL") &&
(COMPENSATION_REG != "INTERNAL"))) begin
$display("Error: [Unisim %s-140] COMPENSATION attribute is set to %s. Legal values for this attribute are ZHOLD, BUF_IN, EXTERNAL or INTERNAL. Instance: %m", MODULE_NAME, COMPENSATION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DIVCLK_DIVIDE_REG < 1) || (DIVCLK_DIVIDE_REG > 106))) begin
$display("Error: [Unisim %s-141] DIVCLK_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 106. Instance: %m", MODULE_NAME, DIVCLK_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_CLKINSEL_INVERTED_REG !== 1'b0) && (IS_CLKINSEL_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-145] IS_CLKINSEL_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKINSEL_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_PSEN_INVERTED_REG !== 1'b0) && (IS_PSEN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-146] IS_PSEN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PSEN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_PSINCDEC_INVERTED_REG !== 1'b0) && (IS_PSINCDEC_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-147] IS_PSINCDEC_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PSINCDEC_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_PWRDWN_INVERTED_REG !== 1'b0) && (IS_PWRDWN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-148] IS_PWRDWN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PWRDWN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RST_INVERTED_REG !== 1'b0) && (IS_RST_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-149] IS_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(REF_JITTER1_REG < 0.000 || REF_JITTER1_REG > 0.999)) begin
$display("Error: [Unisim %s-150] REF_JITTER1 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(REF_JITTER2_REG < 0.000 || REF_JITTER2_REG > 0.999)) begin
$display("Error: [Unisim %s-151] REF_JITTER2 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SS_EN_REG != "FALSE") &&
(SS_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-152] SS_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SS_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SS_MODE_REG != "CENTER_HIGH") &&
(SS_MODE_REG != "CENTER_LOW") &&
(SS_MODE_REG != "DOWN_HIGH") &&
(SS_MODE_REG != "DOWN_LOW"))) begin
$display("Error: [Unisim %s-153] SS_MODE attribute is set to %s. Legal values for this attribute are CENTER_HIGH, CENTER_LOW, DOWN_HIGH or DOWN_LOW. Instance: %m", MODULE_NAME, SS_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SS_MOD_PERIOD_REG < 4000) || (SS_MOD_PERIOD_REG > 40000))) begin
$display("Error: [Unisim %s-154] SS_MOD_PERIOD attribute is set to %d. Legal values for this attribute are 4000 to 40000. Instance: %m", MODULE_NAME, SS_MOD_PERIOD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((STARTUP_WAIT_REG != "TRUE") &&
(STARTUP_WAIT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-155] STARTUP_WAIT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, STARTUP_WAIT_REG);
attr_err = 1'b1;
end
`ifdef XIL_TIMING
if ((attr_test == 1'b1) ||
(VCOCLK_FREQ_MAX_REG < 1200.000 || VCOCLK_FREQ_MAX_REG > 1600.000)) begin
$display("Error: [Unisim %s-156] VCOCLK_FREQ_MAX attribute is set to %f. Legal values for this attribute are 1200.000 to 1600.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MAX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(VCOCLK_FREQ_MIN_REG < VF_MIN || VCOCLK_FREQ_MIN_REG > VF_MIN)) begin
$display("Error: [Unisim %s-157] VCOCLK_FREQ_MIN attribute is set to %f. Legal values for this attribute is %3.3f. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MIN_REG, VF_MIN);
attr_err = 1'b1;
end
`endif
if (attr_err == 1'b1) #1 $finish;
if (CLKOUT0_DIVIDE_F_REG > 1.0000 && CLKOUT0_DIVIDE_F_REG < 2.0000) begin
$display("Error: [Unisim %s-2] The Attribute CLKOUT0_DIVIDE_F is set to %f. Values in range of greater than 1 and less than 2 are not allowed. Instance %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG);
#1 $finish;
end
CLKOUT0_DIVIDE_F_RND = $itor($rtoi((CLKOUT0_DIVIDE_F_REG + 0.0625) * 8.0)) / 8.0;
CLKFBOUT_MULT_F_RND = $itor($rtoi((CLKFBOUT_MULT_F_REG + 0.0625) * 8.0)) / 8.0;
if (CLKFBOUT_MULT_F_RND < CLKFBOUT_MULT_F_REG) begin
$display(" Warning [Unisim %s-35]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND);
end
else if (CLKFBOUT_MULT_F_RND > CLKFBOUT_MULT_F_REG) begin
$display(" Warning: [Unisim %s-36]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND);
end
if (CLKOUT0_DIVIDE_F_RND < CLKOUT0_DIVIDE_F_REG) begin
$display(" Warning: [Unisim %s-37]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND);
end
else if (CLKOUT0_DIVIDE_F_RND > CLKOUT0_DIVIDE_F_REG) begin
$display(" Warning: [Unisim %s-38]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND);
end
clkfbout_f_div = CLKFBOUT_MULT_F_RND;
attr_to_mc(clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, CLKFBOUT_MULT_F_REG, CLKFBOUT_PHASE_REG, clkfbout_duty);
ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div);
clk0_f_div = CLKOUT0_DIVIDE_F_RND;
attr_to_mc(clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, CLKOUT0_DIVIDE_F_REG, CLKOUT0_PHASE_REG, CLKOUT0_DUTY_CYCLE_REG);
ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div);
clk1_div = CLKOUT1_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, CLKOUT1_DIVIDE_REG, CLKOUT1_PHASE_REG, CLKOUT1_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div);
clk2_div = CLKOUT2_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, CLKOUT2_DIVIDE_REG, CLKOUT2_PHASE_REG, CLKOUT2_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div);
clk3_div = CLKOUT3_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, CLKOUT3_DIVIDE_REG, CLKOUT3_PHASE_REG, CLKOUT3_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div);
clk4_div = CLKOUT4_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, CLKOUT4_DIVIDE_REG, CLKOUT4_PHASE_REG, CLKOUT4_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div);
clk5_div = CLKOUT5_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, CLKOUT5_DIVIDE_REG, CLKOUT5_PHASE_REG, CLKOUT5_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div);
clk6_div = CLKOUT6_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, CLKOUT6_DIVIDE_REG, CLKOUT6_PHASE_REG, CLKOUT6_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div);
divclk_div = DIVCLK_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, d_mx, divclk_e, divclk_nc, d_dt, d_pm, divclk_en, divclk_ht, divclk_lt, DIVCLK_DIVIDE_REG, 0.000, 0.500);
ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div);
ps_in_init = 0;
ps_in_ps = ps_in_init;
ps_cnt = 0;
fps_en = clk0_fps_en || clk1_fps_en || clk2_fps_en || clk3_fps_en
|| clk4_fps_en || clk5_fps_en || clk6_fps_en || clkfbout_fps_en;
if (clk0_frac_en == 1'b1) begin
if (CLKOUT0_DUTY_CYCLE_REG != 0.5) begin
$display("Error: [Unisim %s-3] The Attribute CLKOUT0_DUTY_CYCLE is set to %f. This attribute should be set to 0.5 when CLKOUT0_DIVIDE_F has fraction part. Instance %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG);
#100
$finish;
end
end
pll_lfhf = 2'b00;
if (BANDWIDTH_REG === "LOW")
case (clkfbout_div)
1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
2 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end
3 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end
4 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end
5 : begin pll_cp = 4'b0010 ; pll_res = 4'b0111 ; end
6 : begin pll_cp = 4'b0010 ; pll_res = 4'b1011 ; end
7 : begin pll_cp = 4'b0010 ; pll_res = 4'b1101 ; end
8 : begin pll_cp = 4'b0010 ; pll_res = 4'b0011 ; end
9 : begin pll_cp = 4'b0010 ; pll_res = 4'b0101 ; end
10 : begin pll_cp = 4'b0010 ; pll_res = 4'b0101 ; end
11 : begin pll_cp = 4'b0010 ; pll_res = 4'b1001 ; end
12 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end
13 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end
14 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end
15 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end
16 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end
17 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end
18 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end
19 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
20 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
21 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
22 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
23 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
24 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
25 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
26 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end
27 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end
28 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end
29 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end
30 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end
31 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
32 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
33 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
34 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
35 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
36 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
37 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
38 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
39 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
40 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
41 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
47 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
48 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
49 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
50 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
51 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
52 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
53 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
54 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
55 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
56 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
57 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
62 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
63 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
64 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
endcase
else if (BANDWIDTH_REG === "HIGH")
case (clkfbout_div)
1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
2 : begin pll_cp = 4'b0100 ; pll_res = 4'b1111 ; end
3 : begin pll_cp = 4'b0101 ; pll_res = 4'b1011 ; end
4 : begin pll_cp = 4'b0111 ; pll_res = 4'b0111 ; end
5 : begin pll_cp = 4'b1101 ; pll_res = 4'b0111 ; end
6 : begin pll_cp = 4'b1110 ; pll_res = 4'b1011 ; end
7 : begin pll_cp = 4'b1110 ; pll_res = 4'b1101 ; end
8 : begin pll_cp = 4'b1111 ; pll_res = 4'b0011 ; end
9 : begin pll_cp = 4'b1110 ; pll_res = 4'b0101 ; end
10 : begin pll_cp = 4'b1111 ; pll_res = 4'b0101 ; end
11 : begin pll_cp = 4'b1111 ; pll_res = 4'b1001 ; end
12 : begin pll_cp = 4'b1101 ; pll_res = 4'b0001 ; end
13 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
14 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
15 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
16 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
19 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
20 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
21 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
22 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
26 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
27 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
28 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
29 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
30 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
31 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
32 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
33 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
34 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
35 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
36 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
37 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
38 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
39 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
40 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
41 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
47 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end
48 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end
49 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
50 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
51 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
52 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
53 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end
54 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end
55 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
56 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
57 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
62 : begin pll_cp = 4'b0100 ; pll_res = 4'b1010 ; end
63 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end
64 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end
endcase
else if (BANDWIDTH_REG === "OPTIMIZED")
case (clkfbout_div)
1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
2 : begin pll_cp = 4'b0100 ; pll_res = 4'b1111 ; end
3 : begin pll_cp = 4'b0101 ; pll_res = 4'b1011 ; end
4 : begin pll_cp = 4'b0111 ; pll_res = 4'b0111 ; end
5 : begin pll_cp = 4'b1101 ; pll_res = 4'b0111 ; end
6 : begin pll_cp = 4'b1110 ; pll_res = 4'b1011 ; end
7 : begin pll_cp = 4'b1110 ; pll_res = 4'b1101 ; end
8 : begin pll_cp = 4'b1111 ; pll_res = 4'b0011 ; end
9 : begin pll_cp = 4'b1110 ; pll_res = 4'b0101 ; end
10 : begin pll_cp = 4'b1111 ; pll_res = 4'b0101 ; end
11 : begin pll_cp = 4'b1111 ; pll_res = 4'b1001 ; end
12 : begin pll_cp = 4'b1101 ; pll_res = 4'b0001 ; end
13 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
14 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
15 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
16 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
19 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
20 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
21 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
22 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
26 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
27 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
28 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
29 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
30 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
31 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
32 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
33 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
34 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
35 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
36 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
37 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
38 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
39 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
40 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
41 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
47 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end
48 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end
49 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
50 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
51 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
52 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
53 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end
54 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end
55 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
56 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
57 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
62 : begin pll_cp = 4'b0100 ; pll_res = 4'b1010 ; end
63 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end
64 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end
endcase
case (clkfbout_div)
1 : begin drp_lock_ref_dly = 5'd6;
drp_lock_fb_dly = 5'd6;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
2 : begin drp_lock_ref_dly = 5'd6;
drp_lock_fb_dly = 5'd6;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
3 : begin drp_lock_ref_dly = 5'd8;
drp_lock_fb_dly = 5'd8;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
4 : begin drp_lock_ref_dly = 5'd11;
drp_lock_fb_dly = 5'd11;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
5 : begin drp_lock_ref_dly = 5'd14;
drp_lock_fb_dly = 5'd14;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
6 : begin drp_lock_ref_dly = 5'd17;
drp_lock_fb_dly = 5'd17;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
7 : begin drp_lock_ref_dly = 5'd19;
drp_lock_fb_dly = 5'd19;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
8 : begin drp_lock_ref_dly = 5'd22;
drp_lock_fb_dly = 5'd22;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
9 : begin drp_lock_ref_dly = 5'd25;
drp_lock_fb_dly = 5'd25;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
10 : begin drp_lock_ref_dly = 5'd28;
drp_lock_fb_dly = 5'd28;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
11 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd900;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
12 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd825;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
13 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd750;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
14 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd700;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
15 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd650;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
16 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd625;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
17 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd575;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
18 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd550;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
19 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd525;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
20 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd500;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
21 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd475;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
22 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd450;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
23 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd425;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
24 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd400;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
25 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd400;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
26 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd375;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
27 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd350;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
28 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd350;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
29 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd325;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
30 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd325;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
31 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd300;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
32 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd300;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
33 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd300;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
34 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd275;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
35 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd275;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
36 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd275;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
37 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
38 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
39 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
40 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
41 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
42 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
43 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
44 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
45 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
46 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
47 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
48 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
49 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
50 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
51 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
52 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
53 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
54 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
55 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
56 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
57 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
58 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
59 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
60 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
61 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
62 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
63 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
64 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
endcase
tmp_string = "DIVCLK_DIVIDE";
chk_ok = para_int_range_chk (DIVCLK_DIVIDE_REG, tmp_string, D_MIN, D_MAX);
tmp_string = "CLKFBOUT_MULT_F";
chk_ok = para_real_range_chk (CLKFBOUT_MULT_F_RND, tmp_string, M_MIN, M_MAX);
tmp_string = "CLKOUT6_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT6_DIVIDE_REG, CLKOUT6_DUTY_CYCLE_REG, tmp_string);
if(clk0_frac_en == 1'b0) begin
tmp_string = "CLKOUT0_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_F_RND, CLKOUT0_DUTY_CYCLE_REG, tmp_string);
end
tmp_string = "CLKOUT5_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE_REG, CLKOUT5_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT1_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT2_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE_REG, CLKOUT2_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT3_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE_REG, CLKOUT3_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT4_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE_REG, CLKOUT4_DUTY_CYCLE_REG, tmp_string);
period_vco_max = 1000000 / VCOCLK_FREQ_MIN_REG;
period_vco_min = 1000000 / VCOCLK_FREQ_MAX_REG;
period_vco_target = 1000000 / VCOCLK_FREQ_TARGET;
period_vco_target_half = period_vco_target / 2;
fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE;
clk0f_product = CLKOUT0_DIVIDE_F_RND * 8;
pll_lock_time = 12;
lock_period_time = 10;
if (clkfbout_frac_en == 1'b1) begin
md_product = clkfbout_div * DIVCLK_DIVIDE_REG;
m_product = clkfbout_div;
mf_product = CLKFBOUT_MULT_F_RND * 8;
clkout_en_val = mf_product - 1;
m_product2 = clkfbout_div / 2;
clkout_en_time = mf_product + 4 + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
else begin
md_product = clkfbout_div * DIVCLK_DIVIDE_REG;
m_product = clkfbout_div;
mf_product = CLKFBOUT_MULT_F_RND * 8;
m_product2 = clkfbout_div / 2;
clkout_en_val = m_product;
clkout_en_time = md_product + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX;
ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div);
ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div);
divclk_div = DIVCLK_DIVIDE_REG;
dr_sram[6] = {clk5_pm[2:0], clk5_en, clk5_ht[5:0], clk5_lt[5:0]};
dr_sram[7] = {2'bx, clk0_pm_f[2:0], clk0_wf_f,
2'b0, clk5_e, clk5_nc, clk5_dt[5:0]};
dr_sram[8] = {clk0_pm_r[2:0], clk0_en, clk0_ht[5:0], clk0_lt[5:0]};
dr_sram[9] = {1'bx, clk0_frac[2:0], clk0_frac_en, clk0_wf_r,
2'b0, clk0_e, clk0_nc, clk0_dt[5:0]};
dr_sram[10] = {clk1_pm[2:0], clk1_en, clk1_ht[5:0], clk1_lt[5:0]};
dr_sram[11] = {6'bx, 2'b0, clk1_e, clk1_nc, clk1_dt[5:0]};
dr_sram[12] = {clk2_pm[2:0], clk2_en, clk2_ht[5:0], clk2_lt[5:0]};
dr_sram[13] = {6'bx, 2'b0, clk2_e, clk2_nc, clk2_dt[5:0]};
dr_sram[14] = {clk3_pm[2:0], clk3_en, clk3_ht[5:0], clk3_lt[5:0]};
dr_sram[15] = {6'bx, 2'b0, clk3_e, clk3_nc, clk3_dt[5:0]};
dr_sram[16] = {clk4_pm[2:0], clk4_en, clk4_ht[5:0], clk4_lt[5:0]};
dr_sram[17] = {6'bx, 2'b0, clk4_e, clk4_nc, clk4_dt[5:0]};
dr_sram[18] = {clk6_pm[2:0], clk6_en, clk6_ht[5:0], clk6_lt[5:0]};
dr_sram[19] = {2'bx, clkfbout_pm_f[2:0], clkfbout_wf_f,
2'b0, clk6_e, clk6_nc, clk6_dt[5:0]};
dr_sram[20] = {clkfbout_pm_r[2:0], clkfbout_en, clkfbout_ht[5:0], clkfbout_lt[5:0]};
dr_sram[21] = {1'bx, clkfbout_frac[2:0], clkfbout_frac_en,
clkfbout_wf_r, 2'b0, clkfbout_e, clkfbout_nc, clkfbout_dt[5:0]};
dr_sram[22] = {2'bx, divclk_e, divclk_nc, divclk_ht[5:0], divclk_lt[5:0]};
dr_sram[23] = {2'bx, clkfbin_e, clkfbin_nc, clkfbin_ht[5:0], clkfbin_lt[5:0]};
dr_sram[24] = {6'bx, drp_lock_cnt};
dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt};
dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high};
dr_sram[40] = {1'b1, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 1'b1};
dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx};
dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx};
dr_sram[116] = {5'bx, 6'b0, 5'b00001};
end
initial begin
clkpll_jitter_unlock = 0;
clkinstopped_vco_f = 0;
rst_clkfbstopped = 0;
rst_clkinstopped = 0;
rst_clkfbstopped_lk = 0;
rst_clkinstopped_lk = 0;
clkfbin_stop_tmp = 0;
clkin_stop_tmp = 0;
clkvco_lk_en = 0;
clkvco_lk_dly_tmp = 0;
clkin_osc = 0;
clkfbin_osc = 0;
clkin_p = 0;
clkfbin_p = 0;
divclk_div = DIVCLK_DIVIDE_REG;
ps_lock = 0;
ps_lock_dly = 0;
PSDONE_out = 0;
psdone_out1 = 0;
rst_int = 0;
clkinstopped_out1 = 0;
clkfbstopped_out1 = 0;
clkin_period[0] = 0;
clkin_period[1] = 0;
clkin_period[2] = 0;
clkin_period[3] = 0;
clkin_period[4] = 0;
clkin_period_tmp_t = 0;
period_avg = 100000;
period_fb = 100000;
clkin_lost_val = 2;
clkfbin_lost_val = 2;
fb_delay = 0;
clkvco_delay = 0;
val_tmp = 0;
dly_tmp = 0;
fb_comp_delay = 0;
clkfbout_pm_rl = 0;
period_vco = 0;
period_vco1 = 0;
period_vco2 = 0;
period_vco3 = 0;
period_vco4 = 0;
period_vco5 = 0;
period_vco6 = 0;
period_vco7 = 0;
period_vco_half = 0;
period_vco_half1 = 0;
period_vco_half_rm = 0;
period_vco_half_rm1 = 0;
period_vco_half_rm2 = 0;
period_vco_rm = 0;
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
period_ps = 0;
period_ps_old = 0;
clkfbout_frac_ht = 0;
clkfbout_frac_lt = 0;
clk0_frac_ht = 0;
clk0_frac_lt = 0;
clkvco_rm_cnt = 0;
fb_delay_found = 1'b0;
fb_delay_found_tmp = 1'b0;
clkin_edge = 0;
delay_edge = 0;
fbclk_tmp = 0;
clkfbout_tst = 1'b0;
clkout_en = 0;
clkout_en0 = 0;
clkout_en_t = 0;
clkout_en0_tmp = 0;
clkout_en1 = 0;
pll_locked_tmp1 = 0;
pll_locked_tmp2 = 0;
pll_locked_tm = 0;
pll_locked_delay = 0;
unlock_recover = 0;
clkin_jit = 0;
clkin_lock_cnt = 0;
lock_period = 0;
rst_edge = 0;
rst_ht = 0;
DRDY_out = 0;
drdy_out1 = 0;
LOCKED_out = 0;
locked_out_tmp = 0;
DO_out = 16'b0;
drp_lock = 0;
drp_lock_lat_cnt = 0;
clk0_dly_cnt = 6'b0;
clk1_dly_cnt = 6'b0;
clk2_dly_cnt = 6'b0;
clk3_dly_cnt = 6'b0;
clk4_dly_cnt = 6'b0;
clk5_dly_cnt = 6'b0;
clk6_dly_cnt = 6'b0;
clkfbout_dly_cnt = 6'b0;
clk0_cnt = 8'b0;
clk1_cnt = 8'b0;
clk2_cnt = 8'b0;
clk3_cnt = 8'b0;
clk4_cnt = 8'b0;
clk5_cnt = 8'b0;
clk6_cnt = 8'b0;
clkfbout_cnt = 8'b0;
divclk_cnt = 8'b0;
CLKOUT0_out = 0;
CLKOUT1_out = 0;
CLKOUT2_out = 0;
CLKOUT3_out = 0;
CLKOUT4_out = 0;
CLKOUT5_out = 0;
CLKOUT6_out = 0;
clk1_out = 0;
clk2_out = 0;
clk3_out = 0;
clk4_out = 0;
clk5_out = 0;
clk6_out = 0;
CLKFBOUT_out = 0;
divclk_out = 0;
divclk_out_tmp = 0;
clkin_osc = 0;
clkfbin_osc = 0;
clkin_p = 0;
clkfbin_p = 0;
pwron_int = 1;
#100000 pwron_int = 0;
end
assign #2 clkinsel_tmp = CLKINSEL_in;
assign glock = (startup_wait_sig) ? locked_out_tmp : 1;
assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up;
initial begin
init_chk = 0;
#2;
init_chk = 1;
#1;
init_chk = 0;
end
always @(CLKINSEL_in or posedge init_chk ) begin
if (init_chk == 0 && $time > 2 && rst_int === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin
$display("Error: [Unisim %s-4] Input clock can only be switched when RST=1. CLKINSEL at time %t changed when RST=0. Instance %m", MODULE_NAME, $time);
$finish;
end
clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN_REG;
clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r);
clkin_chk_t1 = 0.001 * clkin_chk_t1_i;
clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX_REG;
clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r);
clkin_chk_t2 = 0.001 * clkin_chk_t2_i;
if (CLKINSEL_in === 1 && $time > 1 || CLKINSEL_in !== 0 && init_chk == 1) begin
if (CLKIN1_PERIOD_REG > clkin_chk_t1 || CLKIN1_PERIOD_REG < clkin_chk_t2) begin
$display ("Error: [Unisim %s-5] The attribute CLKIN1_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN1_PERIOD_REG, clkin_chk_t2, clkin_chk_t1);
$finish;
end
end
else if (CLKINSEL_in ===0 && $time > 1 || init_chk == 1 && clkinsel_tmp === 0 ) begin
if (CLKIN2_PERIOD_REG > clkin_chk_t1 || CLKIN2_PERIOD_REG < clkin_chk_t2) begin
$display ("Error: [Unisim %s-6] The attribute CLKIN2_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN2_PERIOD_REG, clkin_chk_t2, clkin_chk_t1);
$finish;
end
end
period_clkin = (CLKINSEL_in === 0) ? CLKIN2_PERIOD_REG : CLKIN1_PERIOD_REG;
if (period_clkin == 0) period_clkin = 10;
if (period_clkin < MAX_FEEDBACK_DELAY)
fb_delay_max = period_clkin * MAX_FEEDBACK_DELAY_SCALE;
else
fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE;
clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_F_RND) / (period_clkin * DIVCLK_DIVIDE_REG);
if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX_REG || clkvco_freq_init_chk < VCOCLK_FREQ_MIN_REG) begin
if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin
$display ("Error: [Unisim %s-7] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG);
$finish;
end
else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin
$display ("Error: [Unisim %s-8] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG);
$finish;
end
end
end
assign init_trig = 1;
assign clkpll_r = (CLKINSEL_in) ? CLKIN1_in : CLKIN2_in;
assign pwrdwn_in1 = (PWRDWN_in === 1) ? 1 : 0;
assign rst_input = (RST_in === 1 | pwrdwn_in1 === 1) ? 1 : 0;
always @(posedge clkpll_r or posedge rst_input)
if (rst_input)
rst_int <= 1;
else
rst_int <= rst_input ;
assign rst_in_o = (rst_int || rst_clkfbstopped || rst_clkinstopped);
//simprim_rst_h
always @(posedge pwrdwn_in1 or posedge pchk_clr)
if (pwrdwn_in1)
pwrdwn_in1_h <= 1;
else if (pchk_clr)
pwrdwn_in1_h <= 0;
always @(posedge RST_in or posedge pchk_clr)
if (RST_in)
rst_input_r_h <= 1;
else if (pchk_clr)
rst_input_r_h <= 0;
always @(rst_input )
if (rst_input==1) begin
rst_edge = $time;
pchk_clr = 0;
end
else if (rst_input==0 && rst_edge > 1) begin
rst_ht = $time - rst_edge;
if (rst_ht < 1500) begin
if (rst_input_r_h == 1 && pwrdwn_in1_h == 1)
$display("Warning: [Unisim %s-11] RST and PWRDWN at time %t must be asserted at least for 1.5 ns (actual %.3f ns) . Instance %m ", MODULE_NAME, $time, rst_ht/1000.0);
else if (rst_input_r_h == 1 && pwrdwn_in1_h == 0)
$display("Warning: [Unisim %s-12] RST at time %t must be asserted at least for 1.5 ns (actual %.3f ns). Instance %m", MODULE_NAME, $time, rst_ht/1000.0);
else if (rst_input_r_h == 0 && pwrdwn_in1_h == 1)
$display("Warning: [Unisim %s-13] PWRDWN at time %t must be asserted at least for 1.5 ns (actual %.3f ns). Instance %m", MODULE_NAME, $time, rst_ht/1000.0);
end
pchk_clr = 1;
end
//endsimprim_rst_h
//
// DRP port read and write
//
assign do_out1 = dr_sram[daddr_lat];
always @(posedge DCLK_in or posedge glblGSR)
if (glblGSR == 1) begin
drp_lock <= 0;
drp_lock_lat_cnt <= 0;
drp_updt <= 1'b0;
end
else begin
if (~RST_in && drp_updt) drp_updt <= 1'b0;
if (DEN_in == 1) begin
valid_daddr = addr_is_valid(DADDR_in);
if (drp_lock == 1) begin
$display("Error: [Unisim %s-14] DEN is high at time %t. Need wait for DRDY signal before next read/write operation through DRP. Instance %m ", MODULE_NAME, $time);
end
else begin
drp_lock <= 1;
drp_lock_lat_cnt <= drp_lock_lat_cnt + 1;
daddr_lat <= DADDR_in;
end
if (~valid_daddr) $display("Warning: [Unisim %s-15] Address DADDR=%b is unsupported at time %t. Instance %m ", MODULE_NAME, DADDR_in, $time);
if (DWE_in == 1) begin // write process
if (rst_input == 1) begin
if (valid_daddr) dr_sram[DADDR_in] <= DI_in;
if (valid_daddr || drp_updt) drp_updt <= 1'b1;
if (DADDR_in == 7'd6)
lower_drp(clk5_pm, clk5_en, clk5_ht, clk5_lt, DI_in);
else if (DADDR_in == 7'd7)
upper_mix_drp(clk0_pm_f, clk0_wf_f, clk5_mx, clk5_e, clk5_nc, clk5_dt, DI_in);
else if (DADDR_in == 7'd8)
lower_drp(clk0_pm_r, clk0_en, clk0_ht, clk0_lt, DI_in);
else if (DADDR_in == 7'd9)
upper_frac_drp(clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, DI_in);
else if (DADDR_in == 7'd10)
lower_drp(clk1_pm, clk1_en, clk1_ht, clk1_lt, DI_in);
else if (DADDR_in == 7'd11)
upper_drp(clk1_mx, clk1_e, clk1_nc, clk1_dt, DI_in);
else if (DADDR_in == 7'd12)
lower_drp(clk2_pm, clk2_en, clk2_ht, clk2_lt, DI_in);
else if (DADDR_in == 7'd13)
upper_drp(clk2_mx, clk2_e, clk2_nc, clk2_dt, DI_in);
else if (DADDR_in == 7'd14)
lower_drp(clk3_pm, clk3_en, clk3_ht, clk3_lt, DI_in);
else if (DADDR_in == 7'd15)
upper_drp(clk3_mx, clk3_e, clk3_nc, clk3_dt, DI_in);
else if (DADDR_in == 7'd16)
lower_drp(clk4_pm, clk4_en, clk4_ht, clk4_lt, DI_in);
else if (DADDR_in == 7'd17)
upper_drp(clk4_mx, clk4_e, clk4_nc, clk4_dt, DI_in);
else if (DADDR_in == 7'd18)
lower_drp(clk3_pm, clk6_en, clk6_ht, clk6_lt, DI_in);
else if (DADDR_in == 7'd19)
upper_mix_drp(clkfbout_pm_f, clkfbout_wf_f, clk6_mx, clk6_e, clk6_nc, clk6_dt, DI_in);
else if (DADDR_in == 7'd20)
lower_drp(clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, DI_in);
else if (DADDR_in == 7'd21)
upper_frac_drp(clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, DI_in);
else if (DADDR_in == 7'd22) begin
divclk_e = DI_in[13];
divclk_nc = DI_in[12];
divclk_ht = DI_in[11:6];
divclk_lt = DI_in[5:0];
end
end
else begin
$display("Error: [Unisim %s-18] RST is low at time %t. RST need to be high when changing paramters through DRP. Instance %m", MODULE_NAME, $time);
end
end //DWE
end //DEN
if ( drp_lock == 1) begin
if (drp_lock_lat_cnt < drp_lock_lat) begin
drp_lock_lat_cnt <= drp_lock_lat_cnt + 1;
end
else begin
drp_lock <= 0;
drdy_out1 <= 1;
drp_lock_lat_cnt <= 0;
end
end
if (drdy_out1 == 1) drdy_out1 <= 0;
end
function addr_is_valid;
input [6:0] daddr_in;
begin
addr_is_valid = 1'b1;
for (i=0; i<=6; i=i+1)
if (daddr_in[i] != 0 && daddr_in[i] != 1) addr_is_valid = 1'b0;
if ((addr_is_valid) &&
((daddr_in >= 7'd06 && daddr_in <= 7'd22) ||
(daddr_in >= 7'd24 && daddr_in <= 7'd26) ||
(daddr_in == 7'd40) ||
(daddr_in == 7'd78) ||
(daddr_in == 7'd79) ||
(daddr_in == 7'd116))) addr_is_valid = 1'b1;
else addr_is_valid = 1'b0;
end
endfunction
// end process drp;
//
// determine clock period
//
always @(posedge clkpll_r or posedge rst_int or posedge rst_clkinsel_flag)
if (rst_int || rst_clkinsel_flag)
begin
clkin_period[0] <= 1000 * period_clkin;
clkin_period[1] <= 1000 * period_clkin;
clkin_period[2] <= 1000 * period_clkin;
clkin_period[3] <= 1000 * period_clkin;
clkin_period[4] <= 1000 * period_clkin;
clkin_jit <= 0;
clkin_lock_cnt <= 0;
pll_locked_tm <= 0;
lock_period <= 0;
pll_locked_tmp1 <= 0;
clkout_en0_tmp <= 0;
unlock_recover <= 0;
clkin_edge <= 0;
end
else begin
clkin_edge <= $time;
if (clkin_edge != 0 && clkinstopped_out1 == 0 && rst_clkinsel_flag == 0) begin
clkin_period[4] <= clkin_period[3];
clkin_period[3] <= clkin_period[2];
clkin_period[2] <= clkin_period[1];
clkin_period[1] <= clkin_period[0];
clkin_period[0] <= $time - clkin_edge;
end
if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out1 == 0)
clkin_jit <= $time - clkin_edge - clkin_period[0];
else
clkin_jit <= 0;
if ( (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0)
clkin_lock_cnt <= clkin_lock_cnt + 1;
else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin
clkin_lock_cnt <= lock_cnt_max - 6;
unlock_recover <= 1;
end
if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0)
pll_locked_tm <= #1 1;
if ( clkin_lock_cnt == lock_period_time )
lock_period <= 1;
if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin
clkout_en0_tmp <= 1;
end
if (clkin_lock_cnt >= locked_en_time && clkout_en == 1)
pll_locked_tmp1 <= 1;
if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max)
unlock_recover <= 0;
end
always @(posedge pll_locked_tmp1)
if (CLKINSEL_in === 0) begin
pchk_tmp1 = CLKIN2_PERIOD_REG * 1100;
pchk_tmp2 = CLKIN2_PERIOD_REG * 900;
if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin
$display("Warning: [Unisim %s-19] Input CLKIN2 period and attribute CLKIN2_PERIOD are not same. Instance %m ", MODULE_NAME);
end
end
else begin
pchk_tmp1 = CLKIN1_PERIOD_REG * 1100;
pchk_tmp2 = CLKIN1_PERIOD_REG * 900;
if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin
$display("Warning: [Unisim %s-20] Input CLKIN1 period and attribute CLKIN1_PERIOD are not same. Instance %m ", MODULE_NAME);
end
end
always @(*)
if (rst_int == 0) begin
if (clkfbout_frac_en == 1'b0) begin
clkout_en_val = m_product;
clkout_en_time = md_product + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
else begin
clkout_en_val = mf_product - 1;
clkout_en_time = mf_product + 4 + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
end
always @(clkout_en0_tmp)
clkout_en0_tmp1 <= #1 clkout_en0_tmp;
always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp )
if (clkout_en0_tmp==0 )
clkout_en0 = 0;
else begin
if (clkfbout_frac_en == 1'b1) begin
if (clkout_en_t > clkout_en_val && clkout_en0_tmp1 == 1)
clkout_en0 <= #period_vco6 clkout_en0_tmp1;
end
else begin
if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1)
clkout_en0 <= #period_vco6 clkout_en0_tmp1;
end
end
always @(clkout_en0 )
clkout_en1 <= #(clkvco_delay) clkout_en0;
always @(clkout_en1 or rst_in_o )
if (rst_in_o)
clkout_en = 0;
else
clkout_en = clkout_en1;
always @(pll_locked_tmp1 )
if (pll_locked_tmp1==0)
pll_locked_tmp2 = pll_locked_tmp1;
else begin
pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1;
end
always @(rst_int)
if (rst_int) begin
assign pll_locked_tmp2 = 0;
assign clkout_en0 = 0;
assign clkout_en1 = 0;
end
else begin
deassign pll_locked_tmp2;
deassign clkout_en0;
deassign clkout_en1;
end
assign locked_out1 = (pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && !unlock_recover) ? 1 : 0;
always @(rst_int or locked_out1)
if (rst_int == 1)
locked_out_tmp <= #1000 0;
else
locked_out_tmp <= locked_out1;
always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or
clkin_period[3] or clkin_period[4]) begin
if (clkin_period[0] > clkin_period[1])
clkin_period_tmp_t = clkin_period[0] - clkin_period[1];
else
clkin_period_tmp_t = clkin_period[1] - clkin_period[0];
if ( ((clkin_period[0] > 0) && (clkin_period[0] != period_avg)) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp_t <= 300) )
period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2]
+ clkin_period[3] + clkin_period[4])/5;
end
always @(clkinstopped_out1 or clkin_hold_f or rst_int)
if (rst_int)
clkinstopped_hold = 0;
else begin
if (clkinstopped_out1)
clkinstopped_hold <= 1;
else begin
if (clkin_hold_f)
clkinstopped_hold = 0;
end
end
always @(posedge clkinstopped_out1) begin
period_avg_stpi <= period_avg;
pd_stp_p <= #1 1;
@(negedge clkvco)
pd_stp_p <= #1 0;
end
always @(negedge clkvco or posedge rst_int or posedge pd_stp_p)
if (rst_int) begin
period_avg_stp <= 1000;
vco_stp_f <= 0;
end
else if (pd_stp_p)
period_avg_stp <= period_avg_stpi;
else begin
if (clkinstopped_out_dly2 == 1 && clkin_hold_f == 0) begin
if (period_vco > 1739)
vco_stp_f <= 1;
else begin
period_avg_stp <= period_avg_stp + 1;
end
end
end
always @(period_avg or divclk_div or clkfbout_f_div or clkinstopped_hold
or period_avg_stp or posedge rst_clkinstopped_rc)
if (period_avg > 0 ) begin
md_product = divclk_div * clkfbout_f_div;
m_product = clkfbout_f_div;
m_product2 = clkfbout_f_div / 2;
clkvco_div_fint = $rtoi(clkfbout_f_div/divclk_div);
clkvco_div_frac = (clkfbout_f_div/divclk_div) - clkvco_div_fint;
if (clkvco_div_frac > 0.000)
clkvco_frac_en = 1;
else
clkvco_frac_en = 0;
period_fb = period_avg * divclk_div;
period_vco_tmp = period_fb / clkfbout_f_div;
period_vco_rl = 1.0 * period_fb / clkfbout_f_div;
period_vco_rl_half = period_vco_rl / 2.0;
clkvco_pdrm = (period_avg * divclk_div / clkfbout_f_div) - period_vco_tmp;
period_vco_mf = period_avg * 8;
if (clkinstopped_hold == 1) begin
if (clkin_hold_f) begin
period_vco = (20000 * period_vco_tmp) / (20000 - period_vco_tmp);
period_vco_rl = (20000 * period_vco_tmp) / (20000 - period_vco_tmp);
period_vco_rl_half = period_vco_rl / 2.0;
end
else begin
period_vco = period_avg_stp * divclk_div /clkfbout_f_div;
period_vco_rl = period_avg_stp * divclk_div /clkfbout_f_div;
period_vco_rl_half = period_vco_rl / 2.0;
end
end
else
period_vco = period_vco_tmp;
period_vco_rm = period_fb % clkfbout_div;
if (period_vco_rm > 1) begin
if (period_vco_rm > m_product2) begin
period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1;
period_vco_cmp_flag = 2;
end
else begin
period_vco_cmp_cnt = (m_product / period_vco_rm) - 1;
period_vco_cmp_flag = 1;
end
end
else begin
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
end
period_vco_half = period_vco /2;
period_vco_half_rm = period_vco - period_vco_half;
period_vco_half_rm1 = period_vco_half_rm + 1;
if (period_vco_half_rm < 1)
period_vco_half_rm2 = 0;
else
period_vco_half_rm2 = period_vco_half_rm - 1;
period_vco_half1 = period_vco - period_vco_half + 1;
pll_locked_delay = period_fb * clkfbout_f_div;
clkin_dly_t = period_avg * (divclk_div + 1.25);
clkfbin_dly_t = period_fb * 2.25 ;
period_vco1 = period_vco / 8;
period_vco2 = period_vco / 4;
period_vco3 = period_vco * 3/ 8;
period_vco4 = period_vco / 2;
period_vco5 = period_vco * 5 / 8;
period_vco6 = period_vco *3 / 4;
period_vco7 = period_vco * 7 / 8;
end
always @ (negedge RST_in) begin
if (drp_updt) begin
mc_to_attr(clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_phase, clkfbout_duty);
if (((clkfbout_f_div > M_MAX) || (clkfbout_f_div < M_MIN)) && ~clkfbout_nc)
$display(" Input Error : %s CLKFBOUT_MULT_F has been programmed through DRP to %f which is over the range of %f to %f. Instance %m at time %t.", MODULE_NAME, clkfbout_f_div, M_MIN, M_MAX, $time);
mc_to_attr(clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, clk0_f_div, clk0_phase, clk0_duty);
if (((clk0_f_div > O_MAX) || (clk0_f_div < O_MIN)) && ~clk0_nc)
$display(" Input Error : %s CLKOUT0_DIVIDE_F has been programmed through DRP to %f which is over the range of %d to %d. Instance %m at time %t.", MODULE_NAME, clk0_f_div, O_MIN, O_MAX, $time);
mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, clk1_div, clk1_phase, clk1_duty);
mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, clk2_div, clk2_phase, clk2_duty);
mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, clk3_div, clk3_phase, clk3_duty);
mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, clk4_div, clk4_phase, clk4_duty);
mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, clk5_div, clk5_phase, clk5_duty);
mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, clk6_div, clk6_phase, clk6_duty);
mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, 2'b0, divclk_e, divclk_nc, 6'b0, 3'b0, divclk_en, divclk_ht, divclk_lt, divclk_div, divclk_phase, divclk_duty);
if (((divclk_div > D_MAX) || (divclk_div < D_MIN)) && ~divclk_nc)
$display(" Error : [Unisim %s-34] DIVCLK_DIVIDE has been programmed through DRP to %f which is over the range of %d to %d at time %t. Instance %m", MODULE_NAME, divclk_div, D_MIN, D_MAX, $time);
ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div);
ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div);
ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div);
end
end
always @(clkfbout_f_div) begin
mf_product = clkfbout_f_div * 8;
end
always @(*) begin
if (clkfbout_frac_en) begin
clkfbout_frac_ht = period_vco_rl * clkfbout_fht + (period_vco_rl * clkfbout_rsel) / 8;
clkfbout_frac_lt = period_vco_rl * clkfbout_flt + (period_vco_rl * clkfbout_fsel) / 8;
end
end
always @(*) begin
if (clk0_frac_en) begin
clk0_frac_ht = period_vco_rl * clk0_fht + (period_vco_rl * clk0_rsel) / 8;
clk0_frac_lt = period_vco_rl * clk0_flt + (period_vco_rl * clk0_fsel) / 8;
end
end
reg ps_wr_to_max = 1'b0;
always @(period_vco or ps_in_ps)
if (fps_en == 1) begin
if (ps_in_ps < 0)
period_ps = period_vco + ps_in_ps * period_vco / 56.0;
else if ((ps_in_ps == 0) && PSINCDEC_in == 0)
period_ps = 0;
else
period_ps = ps_in_ps * period_vco / 56.0;
end
always @( clkpll_r )
clkpll_tmp1 <= #(period_avg) clkpll_r;
always @(clkpll_tmp1)
clkpll <= #(period_avg) clkpll_tmp1;
always @(posedge clkinstopped_out1 or posedge rst_int)
if ( rst_int)
clkinstopped_vco_f <= 0;
else begin
clkinstopped_vco_f <= 1;
@(negedge clkinstopped_out1 or posedge rst_int )
if (rst_int)
clkinstopped_vco_f <= 0;
else begin
@(posedge clkpll);
@(posedge clkpll)
clkinstopped_vco_f <= 0;
end
end
always @(posedge clkinstopped_out1 or posedge rst_int)
if (rst_int)
CLKINSTOPPED_out <= 0;
else begin
CLKINSTOPPED_out <= 1;
if (clkin_hold_f == 1) begin
@(posedge locked_out1 or posedge rst_int)
CLKINSTOPPED_out <= 0;
end
else begin
if (CLKINSEL_in == 1)
$display("Warning: [Unisim %s-21] Input CLKIN1 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time);
else
$display("Warning: [Unisim %s-22] Input CLKIN2 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time);
end
end
always @(posedge clkfbstopped_out1 or posedge rst_int)
if (rst_int)
CLKFBSTOPPED_out <= 0;
else begin
CLKFBSTOPPED_out <= 1;
@(posedge locked_out1)
CLKFBSTOPPED_out <= 0;
end
always @(clkout_en_t)
if (clkout_en_t >= clkout_en_val -3 && clkout_en_t < clkout_en_val)
rst_clkinstopped_tm = 1;
else
rst_clkinstopped_tm = 0;
always @(negedge clkinstopped_out1 or posedge rst_int)
if (rst_int)
rst_clkinstopped <= 0;
else
if (rst_clkinstopped_lk == 0 && clkin_hold_f == 1) begin
@(posedge rst_clkinstopped_tm)
rst_clkinstopped <= #period_vco4 1;
@(negedge rst_clkinstopped_tm ) begin
rst_clkinstopped <= #period_vco5 0;
rst_clkinstopped_rc <= #period_vco6 1;
rst_clkinstopped_rc <= #period_vco7 0;
end
end
always @(posedge clkinstopped_out1 or posedge rst_int)
if (rst_int)
clkinstopped_out_dly <= 0;
else begin
clkinstopped_out_dly <= 1;
if (clkin_hold_f == 1) begin
@(negedge rst_clkinstopped_rc or posedge rst_int)
clkinstopped_out_dly <= 0;
end
end
always @(clkinstopped_out1 or posedge rst_int)
if (rst_int)
clkinstopped_out_dly2 <= 0;
else
clkinstopped_out_dly2 <= clkinstopped_out1;
always @(negedge rst_clkinstopped or posedge rst_int)
if (rst_int)
rst_clkinstopped_lk <= 0;
else begin
rst_clkinstopped_lk <= 1;
@(posedge locked_out1)
rst_clkinstopped_lk <= 0;
end
always @(clkinstopped_vco_f or CLKINSTOPPED_out or clkvco_lk or clkvco_free or rst_int)
if (rst_int)
clkvco_lk = 0;
else begin
if (CLKINSTOPPED_out == 1 && clkin_stop_f == 0)
clkvco_lk <= #(period_vco_half) !clkvco_lk;
else if (clkinstopped_vco_f == 1 && period_vco_half > 0)
clkvco_lk <= #(period_vco_half) !clkvco_lk;
else
clkvco_lk = clkvco_free;
end
// free run vco comp
always @(posedge clkpll)
if (pll_locked_tm == 1 ) begin
clkvco_free = 1'b1;
halfperiod_sum = 0.0;
halfperiod = 0;
if (clkfbout_frac_en == 1'b1 || clkvco_frac_en == 1) begin
for (ik10=1; ik10 < mf_product; ik10=ik10+1) begin
clkout_en_t <= ik10;
halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod;
halfperiod = $rtoi(halfperiod_sum);
#halfperiod clkvco_free = 1'b0;
halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod;
halfperiod = $rtoi(halfperiod_sum);
#halfperiod clkvco_free = 1'b1;
end
clkout_en_t <= ik10;
end else begin
for (ik11=1; ik11 < m_product; ik11=ik11+1) begin
clkout_en_t <= ik11;
halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod;
halfperiod = $rtoi(halfperiod_sum);
#halfperiod clkvco_free = 1'b0;
halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod;
halfperiod = $rtoi(halfperiod_sum);
#halfperiod clkvco_free = 1'b1;
end
clkout_en_t <= ik11;
end
halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod;
halfperiod = $rtoi(halfperiod_sum);
#halfperiod clkvco_free = 1'b0;
end
always @(fb_delay or period_vco or period_vco_mf or clkfbout_dt or clkfbout_pm_rl
or lock_period or ps_in_ps )
if (lock_period == 1) begin
if (clkfbout_frac_en == 1'b1) begin
val_tmp = period_avg * DIVCLK_DIVIDE_REG;
fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl);
end
else begin
val_tmp = period_avg * DIVCLK_DIVIDE_REG;
fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl);
end
dly_tmp1 = fb_delay + fb_comp_delay;
dly_tmp_int = 1;
if (clkfbout_fps_en == 1) begin
if (ps_in_ps < 0) begin
tmp_ps_val1 = -1 * ps_in_ps;
tmp_ps_val2 = tmp_ps_val1 * period_vco / 56.0;
if (tmp_ps_val2 > dly_tmp1 ) begin
dly_tmp_int = -1;
dly_tmp = tmp_ps_val2 - dly_tmp1;
end
else if (tmp_ps_val2 == dly_tmp1 ) begin
dly_tmp_int = 0;
dly_tmp = 0;
end
else begin
dly_tmp_int = 1;
dly_tmp = dly_tmp1 - tmp_ps_val2;
end
end
else
dly_tmp = dly_tmp1 + ps_in_ps * period_vco / 56.0;
end
else
dly_tmp = dly_tmp1;
if (dly_tmp_int < 0)
clkvco_delay = dly_tmp;
else begin
if (clkfbout_frac_en == 1'b1 && dly_tmp == 0)
clkvco_delay = 0;
else if ( dly_tmp < val_tmp)
clkvco_delay = val_tmp - dly_tmp;
else
clkvco_delay = val_tmp - dly_tmp % val_tmp ;
end
end
always @(clkfbout_pm_r)
case (clkfbout_pm_r)
3'b000 : clkfbout_pm_rl = 0.0;
3'b001 : clkfbout_pm_rl = 0.125;
3'b010 : clkfbout_pm_rl = 0.25;
3'b011 : clkfbout_pm_rl = 0.375;
3'b100 : clkfbout_pm_rl = 0.50;
3'b101 : clkfbout_pm_rl = 0.625;
3'b110 : clkfbout_pm_rl = 0.75;
3'b111 : clkfbout_pm_rl = 0.875;
endcase
always @(clkvco_lk)
clkvco_lk_dly_tmp <= #clkvco_delay clkvco_lk;
always @(clkvco_lk_dly_tmp or clkvco_lk or pll_locked_tm)
if ( pll_locked_tm && vco_stp_f == 0) begin
if (dly_tmp == 0)
clkvco = clkvco_lk;
else
clkvco = clkvco_lk_dly_tmp;
end
else
clkvco = 0;
always @(posedge PSCLK_in or posedge rst_int)
if (rst_int) begin
ps_in_ps <= ps_in_init;
ps_cnt <= 0;
psen_w <= 0;
fps_clk_en <= 0;
ps_lock <= 0;
end
else if (fps_en == 1) begin
fps_clk_en <= 1;
if (PSEN_in) begin
if (psen_w == 1)
$display("Error: [Unisim %s-23] PSEN is active more than 1 PSCLK period at time %t. PSEN must be active for only one PSCLK period. Instance %m ", MODULE_NAME, $time);
psen_w <= 1;
if (ps_lock == 1)
$display("Warning: [Unisim %s-24] Please wait for PSDONE signal at time %t before adjusting the Phase Shift. Instance %m ", MODULE_NAME, $time);
else if (PSINCDEC_in == 1) begin
if (ps_cnt < ps_max)
ps_cnt <= ps_cnt + 1;
else
ps_cnt <= 0;
if (ps_in_ps < ps_max)
ps_in_ps <= ps_in_ps + 1;
else
ps_in_ps <= 0;
ps_lock <= 1;
end
else if (PSINCDEC_in == 0) begin
ps_cnt_neg = (-1) * ps_cnt;
ps_in_ps_neg = (-1) * ps_in_ps;
if (ps_cnt_neg < ps_max)
ps_cnt <= ps_cnt - 1;
else
ps_cnt <= 0;
if (ps_in_ps_neg < ps_max)
ps_in_ps <= ps_in_ps - 1;
else
ps_in_ps <= 0;
ps_lock <= 1;
end
end
else
psen_w <= 0;
if ( psdone_out1 == 1)
ps_lock <= 0;
end
always @(posedge ps_lock )
if (fps_en == 1) begin
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
begin
psdone_out1 = 1;
@(posedge PSCLK_in);
psdone_out1 = 0;
end
end
always @(rst_clkinstopped)
if (rst_clkinstopped) begin
assign clkfbout_frac_ht = 50;
assign clkfbout_frac_lt = 50;
end
else begin
deassign clkfbout_frac_ht;
deassign clkfbout_frac_lt;
end
integer clk0_delay=0, clk1_delay=0, clk2_delay=0, clk3_delay=0, clk4_delay=0, clk5_delay=0, clk6_delay=0, clkfbout_delay=0;
integer clk0_delay_next, clk1_delay_next, clk2_delay_next, clk3_delay_next, clk4_delay_next, clk5_delay_next, clk6_delay_next, clkfbout_delay_next;
always @(*) clk0_delay_next = clk0_pm_r*period_vco/8 + (clk0_fps_en*period_ps);
always @(*) clk1_delay_next = clk1_pm*period_vco/8 + (clk1_fps_en*period_ps);
always @(*) clk2_delay_next = clk2_pm*period_vco/8 + (clk2_fps_en*period_ps);
always @(*) clk3_delay_next = clk3_pm*period_vco/8 + (clk3_fps_en*period_ps);
always @(*) clk4_delay_next = clk4_pm*period_vco/8 + (clk4_fps_en*period_ps);
always @(*) clk5_delay_next = clk5_pm*period_vco/8 + (clk5_fps_en*period_ps);
always @(*) clk6_delay_next = clk6_pm*period_vco/8 + (clk6_fps_en*period_ps);
always @(*) clkfbout_delay_next = clkfbout_pm_r*period_vco/8 + (clkfbout_fps_en*period_ps);
always @ (posedge clkvco) begin
if (ps_lock) begin
if ((period_ps - period_ps_old) > period_vco/2)
ps_wr_to_max = 1'b1;
else
ps_wr_to_max <= 1'b0;
end
period_ps_old = period_ps;
clk0_delay <= clk0_delay_next;
clk1_delay <= clk1_delay_next;
clk2_delay <= clk2_delay_next;
clk3_delay <= clk3_delay_next;
clk4_delay <= clk4_delay_next;
clk5_delay <= clk5_delay_next;
clk6_delay <= clk6_delay_next;
clkfbout_delay <= clkfbout_delay_next;
end
always @ (clkvco) begin
if (clkout_en && clk0_en)
if (clk0_delay == 0) clk0in <= clkvco;
else if (clk0_fps_en && ps_wr_to_max && ~clkvco) begin
clk0in <= #(clk0_delay - period_ps) 1'b0;
clk0in <= #((2 * clk0_delay - period_ps)/2) 1'b1;
clk0in <= #(clk0_delay) 1'b0;
end else begin
clk0in <= #clk0_delay clkvco;
end
else clk0in <= 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk1_en)
if (clk1_delay == 0) clk1in <= clkvco;
else if (clk1_fps_en && ps_wr_to_max && ~clkvco) begin
clk1in <= #(clk1_delay - period_ps) 1'b0;
clk1in <= #((2 * clk1_delay - period_ps)/2) 1'b1;
clk1in <= #(clk1_delay) 1'b0;
end else begin
clk1in <= #clk1_delay clkvco;
end
else clk1in <= 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk2_en)
if (clk2_delay == 0) clk2in <= clkvco;
else if (clk2_fps_en && ps_wr_to_max && ~clkvco) begin
clk2in <= #(clk2_delay - period_ps) 1'b0;
clk2in <= #((2 * clk2_delay - period_ps)/2) 1'b1;
clk2in <= #(clk2_delay) 1'b0;
end else begin
clk2in <= #clk2_delay clkvco;
end
else clk2in <= 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk3_en)
if (clk3_delay == 0) clk3in <= clkvco;
else if (clk3_fps_en && ps_wr_to_max && ~clkvco) begin
clk3in <= #(clk3_delay - period_ps) 1'b0;
clk3in <= #((2 * clk3_delay - period_ps)/2) 1'b1;
clk3in <= #(clk3_delay) 1'b0;
end else begin
clk3in <= #clk3_delay clkvco;
end
else clk3in <= 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk4_en)
if (clkout4_cascade_int) clk4in <= clk6_out;
else if (clk4_delay == 0) clk4in <= clkvco;
else if (clk4_fps_en && ps_wr_to_max && ~clkvco) begin
clk4in <= #(clk4_delay - period_ps) 1'b0;
clk4in <= #((2 * clk4_delay - period_ps)/2) 1'b1;
clk4in <= #(clk4_delay) 1'b0;
end else begin
clk4in <= #clk4_delay clkvco;
end
else clk4in <= 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk5_en)
if (clk5_delay == 0) clk5in <= clkvco;
else if (clk5_fps_en && ps_wr_to_max && ~clkvco) begin
clk5in <= #(clk5_delay - period_ps) 1'b0;
clk5in <= #((2 * clk5_delay - period_ps)/2) 1'b1;
clk5in <= #(clk5_delay) 1'b0;
end else begin
clk5in <= #clk5_delay clkvco;
end
else clk5in <= 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk6_en)
if (clk6_delay == 0) clk6in <= clkvco;
else if (clk6_fps_en && ps_wr_to_max && ~clkvco) begin
clk6in <= #(clk6_delay - period_ps) 1'b0;
clk6in <= #((2 * clk6_delay - period_ps)/2) 1'b1;
clk6in <= #(clk6_delay) 1'b0;
end else begin
clk6in <= #clk6_delay clkvco;
end
else clk6in <= 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clkfbout_en)
if (clkfbout_delay == 0) clkfboutin <= clkvco;
else if (clkfbout_fps_en && ps_wr_to_max && ~clkvco) begin
clkfboutin <= #(clkfbout_delay - period_ps) 1'b0;
clkfboutin <= #((2 * clkfbout_delay - period_ps)/2) 1'b1;
clkfboutin <= #(clkfbout_delay) 1'b0;
end else begin
clkfboutin <= #clkfbout_delay clkvco;
end
else clkfboutin <= 1'b0;
end
assign clk0ps_en = (clk0_dly_cnt == clk0_dt) & clkout_en;
assign clk1ps_en = (clk1_dly_cnt == clk1_dt) & clkout_en;
assign clk2ps_en = (clk2_dly_cnt == clk2_dt) & clkout_en;
assign clk3ps_en = (clk3_dly_cnt == clk3_dt) & clkout_en;
assign clk4ps_en = (clk4_dly_cnt == clk4_dt) & clkout_en;
assign clk5ps_en = (clk5_dly_cnt == clk5_dt) & clkout_en;
assign clk6ps_en = (clk6_dly_cnt == clk6_dt) & clkout_en;
assign clkfbps_en = (clkfbout_dly_cnt == clkfbout_dt) & clkout_en;
always @(negedge clk0in or posedge rst_in_o)
if (rst_in_o)
clk0_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clk0_dly_cnt < clk0_dt)
clk0_dly_cnt <= clk0_dly_cnt + 1;
end
always @(negedge clk1in or posedge rst_in_o)
if (rst_in_o)
clk1_dly_cnt <= 6'b0;
else
if (clk1_dly_cnt < clk1_dt && clkout_en ==1)
clk1_dly_cnt <= clk1_dly_cnt + 1;
always @(negedge clk2in or posedge rst_in_o)
if (rst_in_o)
clk2_dly_cnt <= 6'b0;
else
if (clk2_dly_cnt < clk2_dt && clkout_en ==1)
clk2_dly_cnt <= clk2_dly_cnt + 1;
always @(negedge clk3in or posedge rst_in_o)
if (rst_in_o)
clk3_dly_cnt <= 6'b0;
else
if (clk3_dly_cnt < clk3_dt && clkout_en ==1)
clk3_dly_cnt <= clk3_dly_cnt + 1;
always @(negedge clk4in or posedge rst_in_o)
if (rst_in_o)
clk4_dly_cnt <= 6'b0;
else
if (clk4_dly_cnt < clk4_dt && clkout_en ==1)
clk4_dly_cnt <= clk4_dly_cnt + 1;
always @(negedge clk5in or posedge rst_in_o)
if (rst_in_o)
clk5_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clk5_dly_cnt < clk5_dt)
clk5_dly_cnt <= clk5_dly_cnt + 1;
end
always @(negedge clk6in or posedge rst_in_o)
if (rst_in_o)
clk6_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clk6_dly_cnt < clk6_dt)
clk6_dly_cnt <= clk6_dly_cnt + 1;
end
always @(negedge clkfboutin or posedge rst_in_o)
if (rst_in_o)
clkfbout_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clkfbout_dly_cnt < clkfbout_dt)
clkfbout_dly_cnt <= clkfbout_dly_cnt + 1;
end
always @(posedge clkfboutin or negedge clkfboutin or posedge rst_in_o)
if (rst_in_o || ~clkfbps_en) begin
clkfbout_cnt <= 8'b0;
clkfbout_out <= 0;
end
else if (clkfbout_nc) clkfbout_out <= ~clkfbout_out;
else if (~clkfbout_frac_en) begin
if (clkfbout_cnt < clkfbout_cnt_max)
clkfbout_cnt <= clkfbout_cnt + 1;
else
clkfbout_cnt <= 8'b0;
if (clkfbout_cnt < clkfbout_cnt_ht)
clkfbout_out <= 1;
else
clkfbout_out <= 0;
end
else if (clkfbout_frac_en && clkfboutin) begin
clkfbout_out <= 1;
for (ib=1; ib < 8; ib=ib+1) begin
#(clkfbout_frac_ht) clkfbout_out <= 0;
#(clkfbout_frac_lt) clkfbout_out <= 1;
end
#(clkfbout_frac_ht) clkfbout_out <= 0;
#(clkfbout_frac_lt - period_vco1);
end
always @(posedge clk0in or negedge clk0in or posedge rst_in_o)
if (rst_in_o || ~clk0ps_en) begin
clk0_cnt <= 8'b0;
clk0_out <= 0;
end
else if (clk0_nc) clk0_out <= ~clk0_out;
else if (~clk0_frac_en) begin
if (clk0_cnt < clk0_cnt_max)
clk0_cnt <= clk0_cnt + 1;
else
clk0_cnt <= 8'b0;
if (clk0_cnt < clk0_cnt_ht)
clk0_out <= 1;
else
clk0_out <= 0;
end
else if (clk0_frac_en && clk0in) begin
clk0_out <= 1;
for (ik0=1; ik0 < 8; ik0=ik0+1) begin
#(clk0_frac_ht) clk0_out <= 0;
#(clk0_frac_lt) clk0_out <= 1;
end
#(clk0_frac_ht) clk0_out <= 0;
#(clk0_frac_lt - period_vco1);
end
always @(posedge clk1in or negedge clk1in or posedge rst_in_o)
if (rst_in_o || ~clk1ps_en) begin
clk1_cnt <= 8'b0;
clk1_out <= 0;
end
else if (clk1_nc) clk1_out <= ~clk1_out;
else begin
if (clk1_cnt < clk1_cnt_max)
clk1_cnt <= clk1_cnt + 1;
else
clk1_cnt <= 8'b0;
if (clk1_cnt < clk1_cnt_ht)
clk1_out <= 1;
else
clk1_out <= 0;
end
always @(posedge clk2in or negedge clk2in or posedge rst_in_o)
if (rst_in_o || ~clk2ps_en) begin
clk2_cnt <= 8'b0;
clk2_out <= 0;
end
else if (clk2_nc) clk2_out <= ~clk2_out;
else begin
if (clk2_cnt < clk2_cnt_max)
clk2_cnt <= clk2_cnt + 1;
else
clk2_cnt <= 8'b0;
if (clk2_cnt < clk2_cnt_ht)
clk2_out <= 1;
else
clk2_out <= 0;
end
always @(posedge clk3in or negedge clk3in or posedge rst_in_o)
if (rst_in_o || ~clk3ps_en) begin
clk3_cnt <= 8'b0;
clk3_out <= 0;
end
else if (clk3_nc) clk3_out <= ~clk3_out;
else begin
if (clk3_cnt < clk3_cnt_max)
clk3_cnt <= clk3_cnt + 1;
else
clk3_cnt <= 8'b0;
if (clk3_cnt < clk3_cnt_ht)
clk3_out <= 1;
else
clk3_out <= 0;
end
always @(posedge clk4in or negedge clk4in or posedge rst_in_o)
if (rst_in_o || ~clk4ps_en) begin
clk4_cnt <= 8'b0;
clk4_out <= 0;
end
else if (clk4_nc) clk4_out <= ~clk4_out;
else begin
if (clk4_cnt < clk4_cnt_max)
clk4_cnt <= clk4_cnt + 1;
else
clk4_cnt <= 8'b0;
if (clk4_cnt < clk4_cnt_ht)
clk4_out <= 1;
else
clk4_out <= 0;
end
always @(posedge clk5in or negedge clk5in or posedge rst_in_o)
if (rst_in_o || ~clk5ps_en) begin
clk5_cnt <= 8'b0;
clk5_out <= 0;
end
else if (clk5_nc) clk5_out <= ~clk5_out;
else begin
if (clk5_cnt < clk5_cnt_max)
clk5_cnt <= clk5_cnt + 1;
else
clk5_cnt <= 8'b0;
if (clk5_cnt < clk5_cnt_ht)
clk5_out <= 1;
else
clk5_out <= 0;
end
always @(posedge clk6in or negedge clk6in or posedge rst_in_o)
if (rst_in_o || ~clk6ps_en) begin
clk6_cnt <= 8'b0;
clk6_out <= 0;
end
else if (clk6_nc) clk6_out <= ~clk6_out;
else begin
if (clk6_cnt < clk6_cnt_max)
clk6_cnt <= clk6_cnt + 1;
else
clk6_cnt <= 8'b0;
if (clk6_cnt < clk6_cnt_ht)
clk6_out <= 1;
else
clk6_out <= 0;
end
always @(clk0_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1)
CLKOUT0_out = clk0_out;
else
CLKOUT0_out = clkfbout_tst;
always @(clk1_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1)
CLKOUT1_out = clk1_out;
else
CLKOUT1_out = clkfbout_tst;
always @(clk2_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1)
CLKOUT2_out = clk2_out;
else
CLKOUT2_out = clkfbout_tst;
always @(clk3_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1)
CLKOUT3_out = clk3_out;
else
CLKOUT3_out = clkfbout_tst;
always @(clk4_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1)
CLKOUT4_out = clk4_out;
else
CLKOUT4_out = clkfbout_tst;
always @(clk5_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1)
CLKOUT5_out = clk5_out;
else
CLKOUT5_out = clkfbout_tst;
always @(clk6_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1)
CLKOUT6_out = clk6_out;
else
CLKOUT6_out = clkfbout_tst;
always @(clkfbout_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1)
CLKFBOUT_out = clkfbout_out;
else
CLKFBOUT_out = clkfbout_tst;
//
// determine feedback delay
//
always @(posedge clkpll_r )
if (fb_delay_found) clkfbout_tst <= 1'b0;
else clkfbout_tst <= ~clkfbout_tst;
always @( posedge clkfbout_tst )
delay_edge = $time;
always @( posedge rst_int )
begin
fb_delay <= 0;
fb_delay_found_tmp <= 0;
end
always @(posedge CLKFBIN_in )
if (fb_delay_found_tmp == 0 ) begin
if ( delay_edge != 0) begin
fb_delay <= ($time - delay_edge);
fb_delay_found_tmp <= 1;
end else begin
fb_delay <= 0;
fb_delay_found_tmp <= 0;
end
end
always @(negedge clkfbout_tst or negedge fb_delay_found_tmp)
fb_delay_found <= fb_delay_found_tmp;
always @(fb_delay or fb_delay_found)
if (rst_int==0 && fb_delay_found==1'b1 && (fb_delay/1000.0 > fb_delay_max)) begin
$display("Warning: [Unisim %s-25] The feedback delay at time %t is %f ns. It is over the maximum value %f ns. Instance %m ", MODULE_NAME, $time, fb_delay / 1000.0, fb_delay_max);
end
//
// generate unlock signal
//
always #(2*period_avg/3+250) clkin_osc = ~rst_int && ~clkin_osc;
always #(2*period_avg*divclk_div/3+250) clkfbin_osc = ~rst_int && ~clkfbin_osc;
always @(posedge clkpll_r or negedge clkpll_r) begin
clkin_p <= 1;
clkin_p <= #100 0;
end
always @(posedge CLKFBIN_in or negedge CLKFBIN_in) begin
clkfbin_p <= 1;
clkfbin_p <= #100 0;
end
always @(posedge clkin_osc or posedge rst_int or posedge clkin_p)
if (rst_int == 1) begin
clkinstopped_out1 <= 0;
clkin_lost_cnt <= 0;
end
else if (clkin_p == 1) begin
if (clkinstopped_out1 == 1) begin
@(posedge clkpll_r) begin
clkinstopped_out1 <= 0;
clkin_lost_cnt <= 0;
end
end
else begin
clkinstopped_out1 <= 0;
clkin_lost_cnt <= 0;
end
end
else if (lock_period) begin
if (clkin_lost_cnt < clkin_lost_val) begin
clkin_lost_cnt <= clkin_lost_cnt + 1;
clkinstopped_out1 <= 0;
end
else
clkinstopped_out1 <= 1;
end
always @(posedge clkfbin_osc or posedge rst_int or posedge clkfbin_p)
if (rst_int == 1 || clkfbin_p == 1) begin
clkfbstopped_out1 <= 0;
clkfbin_lost_cnt <= 0;
end
else if (clkout_en) begin
if (clkfbin_lost_cnt < clkfbin_lost_val) begin
clkfbin_lost_cnt <= clkfbin_lost_cnt + 1;
clkfbstopped_out1 <= 0;
end
else
clkfbstopped_out1 <= 1;
end
always @(clkin_jit or rst_int )
if (rst_int)
clkpll_jitter_unlock = 0;
else
if (pll_locked_tmp2 && clkfbstopped_out1 == 0 && clkinstopped_out1 == 0) begin
if ((clkin_jit > REF_CLK_JITTER_MAX_tmp && clkin_jit < period_avg) ||
(clkin_jit < -REF_CLK_JITTER_MAX_tmp && clkin_jit > -period_avg ))
clkpll_jitter_unlock = 1;
else
clkpll_jitter_unlock = 0;
end
else
clkpll_jitter_unlock = 0;
assign pll_unlock1 = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1) ? 1 : 0;
assign pll_unlock = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0;
// tasks
task mc_to_attr;
input [2:0] pm_f;
input wf_f;
input [2:0] frac;
input frac_en;
input wf_r;
input [1:0] mx;
input e;
input nc;
input [5:0] dt;
input [2:0] pm_r;
input en;
input [5:0] ht;
input [5:0] lt;
output real div;
output real phase;
output real duty;
integer odd_frac;
reg odd;
real frac_r;
integer div_2;
integer pm_f_c;
real duty_step;
real phase_step;
begin
if (nc == 1'b1) begin
div = 1.0;
phase = 0.0;
duty = 0.5;
end
else if (frac_en == 1'b1) begin
duty =0.50;
if (dt == 6'b0 && pm_r == 3'b0) pm_f_c = pm_f;
else if (pm_f >= pm_r) pm_f_c = pm_f - pm_r;
else pm_f_c = 8 + pm_f - pm_r;
if (pm_f_c < 4) begin
odd = 1'b0;
odd_frac = frac;
end
else begin
odd = 1'b1;
odd_frac = frac + 8;
end
frac_r = frac * 0.125;
if (odd_frac > 9) div_2 = lt;
else div_2 = lt + 1;
div = 2 * div_2 + odd + frac_r;
phase_step = 360.0 / (div * 8);
phase = phase_step * (dt*8.0 + pm_r);
end
else begin
if (ht == 6'b0 && lt == 6'b0) div = 128.0;
else if (ht == 6'b0) div = 64.0 + lt * 1.0;
else if (lt == 6'b0) div = ht * 1.0 + 64.0;
else div = ht * 1.0 + lt * 1.0;
duty_step = 0.5 / div;
duty = (2.0 * ht + e) * duty_step;
phase_step = 360.0 / div;
phase = dt * phase_step;
end
end
endtask
task upper_mix_drp;
output reg [2:0] pm_f;
output reg wf_f;
output reg [1:0] mx;
output reg e;
output reg nc;
output reg [5:0] dt;
input [15:0] DI;
begin
pm_f = DI[13:11];
wf_f = DI[10];
mx = DI[9:8];
e = DI[7];
nc = DI[6];
dt = DI[5:0];
end
endtask
task upper_frac_drp;
output reg [2:0] frac;
output reg frac_en;
output reg wf_r;
output reg [1:0] mx;
output reg e;
output reg nc;
output reg [5:0] dt;
input [15:0] DI;
begin
frac = DI[14:12];
frac_en = DI[11];
wf_r = DI[10];
mx = DI[9:8];
e = DI[7];
nc = DI[6];
dt = DI[5:0];
end
endtask
task upper_drp;
output reg [1:0] mx;
output reg e;
output reg nc;
output reg [5:0] dt;
input [15:0] DI;
begin
mx = DI[9:8];
e = DI[7];
nc = DI[6];
dt = DI[5:0];
end
endtask
task lower_drp;
output reg [2:0] pm_r;
output reg en;
output reg [5:0] ht;
output reg [5:0] lt;
input [15:0] DI;
begin
pm_r = DI[15:13];
en = DI[12];
ht = DI[11:6];
lt = DI[5:0];
end
endtask
//ht_calc( frac, frac_en, e, ht, lt, div_f, clk_rsel, clk_fsel, clk_fht, clk_flt, clk_cnt_max, clk_cnt_ht, clk_div)
task ht_calc;
input [2:0] frac;
input frac_en;
input e;
input [5:0] ht;
input [6:0] lt;
input real f_div;
output [3:0] clk_rsel;
output [3:0] clk_fsel;
output [6:0] clk_fht;
output [6:0] clk_flt;
output integer clk_cnt_max;
output integer clk_cnt_ht;
output integer clk_div_fint;
integer clk_div_fint_odd;
begin
clk_div_fint = $rtoi(f_div);
if (frac_en) begin
clk_fht = clk_div_fint / 2;
clk_flt = clk_div_fint / 2;
clk_div_fint_odd = clk_div_fint - clk_fht - clk_flt;
if (clk_div_fint_odd > 0) begin
clk_rsel = (8 + frac) / 2;
clk_fsel = 8 + frac - clk_rsel;
end
else begin
clk_rsel = frac / 2;
clk_fsel = frac - clk_rsel;
end
end
else begin
if (ht == 6'b0) clk_fht = 64; else clk_fht = ht;
if (lt == 7'b0) clk_flt = 64; else clk_flt = lt;
clk_cnt_max = 2 * (clk_fht + clk_flt) - 1;
clk_cnt_ht = 2 * clk_fht + e;
end
end
endtask
task attr_to_mc;
output reg [2:0] pm_f;
output reg wf_f;
output reg [2:0] frac;
output reg frac_en;
output reg wf_r;
output reg [1:0] mx;
output reg e;
output reg nc;
output reg [5:0] dt;
output reg [2:0] pm_r;
output reg en;
output reg [5:0] ht;
output reg [5:0] lt;
input real div;
input real phase;
input real duty;
integer div_int;
real div_frac;
real div_rnd;
reg [37:0] vector;
begin
// determine frac_en
div_int = $rtoi(div);
div_frac = div - $itor(div_int);
if (div_frac > 0.000) frac_en = 1'b1;
else frac_en = 1'b0;
// rnd frac to nearest 0.125 - may become .000
div_rnd = $itor($rtoi((div + 0.0625) * 8.0)) / 8.0;
// determine int and frac part
div_int = $rtoi(div_rnd);
div_frac = div_rnd - $itor(div_int);
if (div_int == 1) begin
// nc = 1, rest are dummy
pm_f = 3'b0;
wf_f = 1'b0;
frac = 3'b0;
frac_en = 1'b0;
wf_r = 1'b0;
mx = 2'b0;
e = 1'b0;
nc = 1'b1;
dt = 6'b0;
pm_r = 3'b0;
en = 1'b1;
ht = 6'b1;
lt = 6'b1; end
else begin
if (frac_en == 1'b1) vector = mmcm_frac_calc(div_int,phase*1000,duty*1000,div_frac*1000);
else vector = mmcm_calc(div_int,phase*1000,duty*100000);
if (frac_en == 1'b1) begin
pm_f = vector[35:33];
wf_f = vector[32];
frac = vector[30:28];
frac_en = vector[27];
wf_r = vector[26];
end
else begin
pm_f = 3'b0;
wf_f = 1'b0;
frac = 3'b0;
frac_en = 1'b0;
wf_r = 1'b0;
end
mx = vector[25:24];
e = vector[23];
nc = vector[22];
dt = vector[21:16];
pm_r = vector[15:13];
en = 1'b1;
ht = vector[11:6];
lt = vector[5:0];
end
end
endtask
`define MMCME2_ADV_FRAC_PRECISION 10
`define MMCME2_ADV_FIXED_WIDTH 32
// This function takes a fixed point number and rounds it to the nearest
// fractional precision bit.
function [`MMCME2_ADV_FIXED_WIDTH:1] round_frac
(
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
input [`MMCME2_ADV_FIXED_WIDTH:1] decimal,
// This describes the precision of the fraction, for example a value
// of 1 would modify the fractional so that instead of being a .16
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
input [`MMCME2_ADV_FIXED_WIDTH:1] precision
);
begin
// If the fractional precision bit is high then round up
if( decimal[(`MMCME2_ADV_FRAC_PRECISION-precision)] == 1'b1) begin
round_frac = decimal + (1'b1 << (`MMCME2_ADV_FRAC_PRECISION-precision));
end else begin
round_frac = decimal;
end
end
endfunction
// This function calculates high_time, low_time, w_edge, and no_count
// of a non-fractional counter based on the divide and duty cycle
//
// NOTE: high_time and low_time are returned as integers between 0 and 63
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
// ignore the overflow)
function [13:0] mmcm_divider
(
input [7:0] divide, // Max divide is 128
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
);
reg [`MMCME2_ADV_FIXED_WIDTH:1] duty_cycle_fix;
// High/Low time is initially calculated with a wider integer to prevent a
// calculation error when it overflows to 64.
reg [6:0] high_time;
reg [6:0] low_time;
reg w_edge;
reg no_count;
reg [`MMCME2_ADV_FIXED_WIDTH:1] temp;
begin
// Duty Cycle must be between 0 and 1,000
if(duty_cycle <=0 || duty_cycle >= 100000) begin
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
$finish;
end
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
duty_cycle_fix = (duty_cycle << `MMCME2_ADV_FRAC_PRECISION) / 100_000;
// If the divide is 1 nothing needs to be set except the no_count bit.
// Other values are dummies
if(divide == 7'h01) begin
high_time = 7'h01;
w_edge = 1'b0;
low_time = 7'h01;
no_count = 1'b1;
end else begin
temp = round_frac(duty_cycle_fix*divide, 1);
// comes from above round_frac
high_time = temp[`MMCME2_ADV_FRAC_PRECISION+7:`MMCME2_ADV_FRAC_PRECISION+1];
// If the duty cycle * divide rounded is .5 or greater then this bit
// is set.
w_edge = temp[`MMCME2_ADV_FRAC_PRECISION]; // comes from round_frac
// If the high time comes out to 0, it needs to be set to at least 1
// and w_edge set to 0
if(high_time == 7'h00) begin
high_time = 7'h01;
w_edge = 1'b0;
end
if(high_time == divide) begin
high_time = divide - 1;
w_edge = 1'b1;
end
// Calculate low_time based on the divide setting and set no_count to
// 0 as it is only used when divide is 1.
low_time = divide - high_time;
no_count = 1'b0;
end
// Set the return value.
mmcm_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
end
endfunction
// This function calculates mx, delay_time, and phase_mux
// of a non-fractional counter based on the divide and phase
//
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
// is used.
function [10:0] mmcm_phase
(
// divide must be an integer (use fractional if not)
// assumed that divide already checked to be valid
input [7:0] divide, // Max divide is 128
// Phase is given in degrees (-360,000 to 360,000)
input signed [31:0] phase
);
reg [`MMCME2_ADV_FIXED_WIDTH:1] phase_in_cycles;
reg [`MMCME2_ADV_FIXED_WIDTH:1] phase_fixed;
reg [1:0] mx;
reg [5:0] delay_time;
reg [2:0] phase_mux;
reg [`MMCME2_ADV_FIXED_WIDTH:1] temp;
begin
if ((phase < -360000) || (phase > 360000)) begin
$display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase);
$finish;
end
// If phase is less than 0, convert it to a positive phase shift
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
if(phase < 0) begin
phase_fixed = ( (phase + 360000) << `MMCME2_ADV_FRAC_PRECISION ) / 1000;
end else begin
phase_fixed = ( phase << `MMCME2_ADV_FRAC_PRECISION ) / 1000;
end
// Put phase in terms of decimal number of vco clock cycles
phase_in_cycles = ( phase_fixed * divide ) / 360;
temp = round_frac(phase_in_cycles, 3);
// set mx to 2'b00 that the phase mux from the VCO is enabled
mx = 2'b00;
phase_mux = temp[`MMCME2_ADV_FRAC_PRECISION:`MMCME2_ADV_FRAC_PRECISION-2];
delay_time = temp[`MMCME2_ADV_FRAC_PRECISION+6:`MMCME2_ADV_FRAC_PRECISION+1];
// Setup the return value
mmcm_phase={mx, phase_mux, delay_time};
end
endfunction
// This function takes in the divide, phase, and duty cycle
// setting to calculate the upper and lower counter registers.
function [37:0] mmcm_calc
(
input [7:0] divide, // Max divide is 128
input signed [31:0] phase,
input [31:0] duty_cycle // Multiplied by 100,000
);
reg [13:0] div_calc;
reg [16:0] phase_calc;
begin
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
div_calc = mmcm_divider(divide, duty_cycle);
// mx[10:9], pm[8:6], dt[5:0]
phase_calc = mmcm_phase(divide, phase);
// Return value is the upper and lower address of counter
// Upper address is:
// RESERVED [31:26]
// MX [25:24]
// EDGE [23]
// NOCOUNT [22]
// DELAY_TIME [21:16]
// Lower Address is:
// PHASE_MUX [15:13]
// RESERVED [12]
// HIGH_TIME [11:6]
// LOW_TIME [5:0]
mmcm_calc =
{
// Upper Address
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
// Lower Address
phase_calc[8:6], 1'b0, div_calc[11:0]
};
end
endfunction
// This function takes in the divide, phase, and duty cycle
// setting to calculate the upper and lower counter registers.
// for fractional multiply/divide functions.
//
//
function [37:0] mmcm_frac_calc
(
input [7:0] divide, // Max divide is 128
input signed [31:0] phase,
input [31:0] duty_cycle, // Multiplied by 1,000
input [9:0] frac // Multiplied by 1000
);
//Required for fractional divide calculations
reg [7:0] lt_frac;
reg [7:0] ht_frac;
reg /*[7:0]*/ wf_fall_frac;
reg /*[7:0]*/ wf_rise_frac;
reg [31:0] a;
reg [7:0] pm_rise_frac_filtered ;
reg [7:0] pm_fall_frac_filtered ;
reg [7:0] clkout0_divide_int;
reg [2:0] clkout0_divide_frac;
reg [7:0] even_part_high;
reg [7:0] even_part_low;
reg [7:0] odd;
reg [7:0] odd_and_frac;
reg [7:0] pm_fall;
reg [7:0] pm_rise;
reg [7:0] dt;
reg [7:0] dt_int;
reg [63:0] dt_calc;
reg [7:0] pm_rise_frac;
reg [7:0] pm_fall_frac;
reg [31:0] a_per_in_octets;
reg [31:0] a_phase_in_cycles;
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
reg [31: 0] phase_pos;
reg [31: 0] phase_vco;
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
reg [13:0] div_calc;
reg [16:0] phase_calc;
begin
//convert phase to fixed
if ((phase < -360000) || (phase > 360000)) begin
$display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase);
// $display("ERROR: phase of $phase is not between -360000 and 360000");
$finish;
end
// Return value is
// Transfer data
// RESERVED [37:36]
// FRAC_TIME [35:33]
// FRAC_WF_FALL [32]
// Upper address is:
// RESERVED [31:26]
// MX [25:24]
// EDGE [23]
// NOCOUNT [22]
// DELAY_TIME [21:16]
// Lower Address is:
// PHASE_MUX [15:13]
// RESERVED [12]
// HIGH_TIME [11:6]
// LOW_TIME [5:0]
clkout0_divide_frac = frac / 125;
clkout0_divide_int = divide;
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
even_part_low = even_part_high;
odd = clkout0_divide_int - even_part_high - even_part_low;
odd_and_frac = (8*odd) + clkout0_divide_frac;
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
pm_rise = 0; //0
wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
//Calculate phase in fractional cycles
a_per_in_octets = (8 * divide) + (frac / 125) ;
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
dt = dt_calc[7:0];
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
pm_fall_frac = pm_fall + pm_rise_frac;
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
div_calc = mmcm_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
phase_calc = mmcm_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
mmcm_frac_calc[37:0] =
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
} ;
end
endfunction
function clkout_duty_chk;
input CLKOUT_DIVIDE;
input CLKOUT_DUTY_CYCLE;
input reg [160:0] CLKOUT_DUTY_CYCLE_N;
integer CLKOUT_DIVIDE, step_tmp;
real CLKOUT_DUTY_CYCLE;
real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_CHK, CLK_DUTY_CYCLE_STEP;
real CLK_DUTY_CYCLE_MIN_rnd;
reg clk_duty_tmp_int;
begin
if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin
CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT )/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_CHK = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN;
end
else begin
if (CLKOUT_DIVIDE == 1) begin
CLK_DUTY_CYCLE_MIN = 0.0;
CLK_DUTY_CYCLE_MIN_rnd = 0.0;
end
else begin
step_tmp = 1000 / CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0;
CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE;
end
CLK_DUTY_CYCLE_CHK = 1.0;
CLK_DUTY_CYCLE_MAX = 1.0;
end
if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_CHK || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin
$display("Warning: [Unisim %s-30] %s is set to %f and is not in the allowed range %f to %f. Instance %m ", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX );
end
clk_duty_tmp_int = 0;
CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE;
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 &&
((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001)
clk_duty_tmp_int = 1;
if ( clk_duty_tmp_int != 1) begin
$display("Warning: [Unisim %s-31] %s is set to %f and is not an allowed value. Allowed values are:", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE);
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
$display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j);
$display(" Instance %m ");
end
clkout_duty_chk = 1'b1;
end
endfunction
function para_int_range_chk;
input para_in;
input reg [160:0] para_name;
input range_low;
input range_high;
integer para_in;
integer range_low;
integer range_high;
begin
if ( para_in < range_low || para_in > range_high) begin
$display("Error: [Unisim %s-32] The Attribute %s is set to %d. Legal values for this attribute are %d to %d. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high);
$finish;
end
para_int_range_chk = 1'b1;
end
endfunction
function para_real_range_chk;
input para_in;
input reg [160:0] para_name;
input range_low;
input range_high;
real para_in;
real range_low;
real range_high;
begin
if ( para_in < range_low || para_in > range_high) begin
$display("Error : [Unisim %s-33] The Attribute %s is set to %f. Legal values for this attribute are %f to %f. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high);
$finish;
end
para_real_range_chk = 1'b0;
end
endfunction
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(CLKIN1 => LOCKED) = (100:100:100, 100:100:100);
(CLKIN2 => LOCKED) = (100:100:100, 100:100:100);
(DCLK *> DO) = (100:100:100, 100:100:100);
(DCLK => DRDY) = (100:100:100, 100:100:100);
(PSCLK => PSDONE) = (100:100:100, 100:100:100);
(negedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100);
(negedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100);
(negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKFBOUTB, 0:0:0, notifier);
$period (negedge CLKIN1, 0:0:0, notifier);
$period (negedge CLKIN2, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUT2, 0:0:0, notifier);
$period (negedge CLKOUT2B, 0:0:0, notifier);
$period (negedge CLKOUT3, 0:0:0, notifier);
$period (negedge CLKOUT3B, 0:0:0, notifier);
$period (negedge CLKOUT4, 0:0:0, notifier);
$period (negedge CLKOUT5, 0:0:0, notifier);
$period (negedge CLKOUT6, 0:0:0, notifier);
$period (negedge DCLK, 0:0:0, notifier);
$period (negedge PSCLK, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKFBOUTB, 0:0:0, notifier);
$period (posedge CLKIN1, 0:0:0, notifier);
$period (posedge CLKIN2, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUT2, 0:0:0, notifier);
$period (posedge CLKOUT2B, 0:0:0, notifier);
$period (posedge CLKOUT3, 0:0:0, notifier);
$period (posedge CLKOUT3B, 0:0:0, notifier);
$period (posedge CLKOUT4, 0:0:0, notifier);
$period (posedge CLKOUT5, 0:0:0, notifier);
$period (posedge CLKOUT6, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$period (posedge PSCLK, 0:0:0, notifier);
$setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay);
$setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay);
$setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay);
$setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay);
$setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay);
$setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay);
$setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay);
$setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay);
$setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay);
$setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay);
$width (negedge CLKIN1, 0:0:0, 0, notifier);
$width (negedge CLKIN2, 0:0:0, 0, notifier);
$width (negedge DCLK, 0:0:0, 0, notifier);
$width (negedge PSCLK, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN1, 0:0:0, 0, notifier);
$width (posedge CLKIN2, 0:0:0, 0, notifier);
$width (posedge DCLK, 0:0:0, 0, notifier);
$width (posedge PSCLK, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//*****************************************************************************
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodrp_mcb_controller.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:25:50 $
// \ \ / \ Date Created: Mon Feb 9 2009
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: Xilinx reference design for IODRP controller for v0.9 device
//Reference:
//
// Revision: Date: Comment
// 1.0: 3/19/09: Initial version for IODRP_MCB read operations.
// 1.1: 4/03/09: SLH - Added left shift for certain IOI's
// End Revision
//**********************************************************************************
`timescale 1ps/1ps
`ifdef ALTERNATE_READ
`else
`define ALTERNATE_READ 1'b1
`endif
module iodrp_mcb_controller(
input wire [7:0] memcell_address,
input wire [7:0] write_data,
output reg [7:0] read_data = 0,
input wire rd_not_write,
input wire cmd_valid,
output wire rdy_busy_n,
input wire use_broadcast,
input wire [4:0] drp_ioi_addr,
input wire sync_rst,
input wire DRP_CLK,
output reg DRP_CS,
output wire DRP_SDI, //output to IODRP SDI pin
output reg DRP_ADD,
output reg DRP_BKST,
input wire DRP_SDO, //input from IODRP SDO pin
output reg MCB_UIREAD = 1'b0
);
reg [7:0] memcell_addr_reg; // Register where memcell_address is captured during the READY state
reg [7:0] data_reg; // Register which stores the write data until it is ready to be shifted out
reg [8:0] shift_through_reg; // The shift register which shifts out SDO and shifts in SDI.
// This register is loaded before the address or data phase, but continues to shift for a writeback of read data
reg load_shift_n; // The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
reg addr_data_sel_n; // The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
reg [2:0] bit_cnt= 3'b0; // The counter for which bit is being shifted during address or data phase
reg rd_not_write_reg;
reg AddressPhase; // This is set after the first address phase has executed
reg DRP_CS_pre;
reg extra_cs;
(* FSM_ENCODING="GRAY" *) reg [3:0] state, nextstate;
wire [8:0] data_out;
reg [8:0] data_out_mux; // The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
wire DRP_SDI_pre; //added so that DRP_SDI output is only active when DRP_CS is active
localparam READY = 4'h0;
localparam DECIDE = 4'h1;
localparam ADDR_PHASE = 4'h2;
localparam ADDR_TO_DATA_GAP = 4'h3;
localparam ADDR_TO_DATA_GAP2 = 4'h4;
localparam ADDR_TO_DATA_GAP3 = 4'h5;
localparam DATA_PHASE = 4'h6;
localparam ALMOST_READY = 4'h7;
localparam ALMOST_READY2 = 4'h8;
localparam ALMOST_READY3 = 4'h9;
localparam IOI_DQ0 = 5'h01;
localparam IOI_DQ1 = 5'h00;
localparam IOI_DQ2 = 5'h03;
localparam IOI_DQ3 = 5'h02;
localparam IOI_DQ4 = 5'h05;
localparam IOI_DQ5 = 5'h04;
localparam IOI_DQ6 = 5'h07;
localparam IOI_DQ7 = 5'h06;
localparam IOI_DQ8 = 5'h09;
localparam IOI_DQ9 = 5'h08;
localparam IOI_DQ10 = 5'h0B;
localparam IOI_DQ11 = 5'h0A;
localparam IOI_DQ12 = 5'h0D;
localparam IOI_DQ13 = 5'h0C;
localparam IOI_DQ14 = 5'h0F;
localparam IOI_DQ15 = 5'h0E;
localparam IOI_UDQS_CLK = 5'h1D;
localparam IOI_UDQS_PIN = 5'h1C;
localparam IOI_LDQS_CLK = 5'h1F;
localparam IOI_LDQS_PIN = 5'h1E;
//synthesis translate_off
reg [32*8-1:0] state_ascii;
always @ (state) begin
case (state)
READY :state_ascii<="READY";
DECIDE :state_ascii<="DECIDE";
ADDR_PHASE :state_ascii<="ADDR_PHASE";
ADDR_TO_DATA_GAP :state_ascii<="ADDR_TO_DATA_GAP";
ADDR_TO_DATA_GAP2 :state_ascii<="ADDR_TO_DATA_GAP2";
ADDR_TO_DATA_GAP3 :state_ascii<="ADDR_TO_DATA_GAP3";
DATA_PHASE :state_ascii<="DATA_PHASE";
ALMOST_READY :state_ascii<="ALMOST_READY";
ALMOST_READY2 :state_ascii<="ALMOST_READY2";
ALMOST_READY3 :state_ascii<="ALMOST_READY3";
endcase // case(state)
end
//synthesis translate_on
/*********************************************
* Input Registers
*********************************************/
always @ (posedge DRP_CLK) begin
if(state == READY) begin
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end
end
assign rdy_busy_n = (state == READY);
// The changes below are to compensate for an issue with 1.0 silicon.
// It may still be necessary to add a clock cycle to the ADD and CS signals
//`define DRP_v1_0_FIX // Uncomment out this line for synthesis
task shift_n_expand (
input [7:0] data_in,
output [8:0] data_out
);
begin
if (data_in[0])
data_out[1:0] = 2'b11;
else
data_out[1:0] = 2'b00;
if (data_in[1:0] == 2'b10)
data_out[2:1] = 2'b11;
else
data_out[2:1] = {data_in[1], data_out[1]};
if (data_in[2:1] == 2'b10)
data_out[3:2] = 2'b11;
else
data_out[3:2] = {data_in[2], data_out[2]};
if (data_in[3:2] == 2'b10)
data_out[4:3] = 2'b11;
else
data_out[4:3] = {data_in[3], data_out[3]};
if (data_in[4:3] == 2'b10)
data_out[5:4] = 2'b11;
else
data_out[5:4] = {data_in[4], data_out[4]};
if (data_in[5:4] == 2'b10)
data_out[6:5] = 2'b11;
else
data_out[6:5] = {data_in[5], data_out[5]};
if (data_in[6:5] == 2'b10)
data_out[7:6] = 2'b11;
else
data_out[7:6] = {data_in[6], data_out[6]};
if (data_in[7:6] == 2'b10)
data_out[8:7] = 2'b11;
else
data_out[8:7] = {data_in[7], data_out[7]};
end
endtask
always @(*) begin
case(drp_ioi_addr)
`ifdef DRP_v1_0_FIX
IOI_DQ0 : data_out_mux = data_out<<1;
IOI_DQ1 : data_out_mux = data_out;
IOI_DQ2 : data_out_mux = data_out<<1;
// IOI_DQ2 : data_out_mux = data_out;
IOI_DQ3 : data_out_mux = data_out;
IOI_DQ4 : data_out_mux = data_out;
IOI_DQ5 : data_out_mux = data_out;
IOI_DQ6 : shift_n_expand (data_out, data_out_mux);
// IOI_DQ6 : data_out_mux = data_out;
IOI_DQ7 : data_out_mux = data_out;
IOI_DQ8 : data_out_mux = data_out<<1;
IOI_DQ9 : data_out_mux = data_out;
IOI_DQ10 : data_out_mux = data_out<<1;
IOI_DQ11 : data_out_mux = data_out;
IOI_DQ12 : data_out_mux = data_out<<1;
IOI_DQ13 : data_out_mux = data_out;
IOI_DQ14 : data_out_mux = data_out<<1;
IOI_DQ15 : data_out_mux = data_out;
IOI_UDQS_CLK : data_out_mux = data_out<<1;
IOI_UDQS_PIN : data_out_mux = data_out<<1;
IOI_LDQS_CLK : data_out_mux = data_out;
IOI_LDQS_PIN : data_out_mux = data_out;
`else
`endif
IOI_DQ0 : data_out_mux = data_out;
IOI_DQ1 : data_out_mux = data_out;
IOI_DQ2 : data_out_mux = data_out;
IOI_DQ3 : data_out_mux = data_out;
IOI_DQ4 : data_out_mux = data_out;
IOI_DQ5 : data_out_mux = data_out;
IOI_DQ6 : data_out_mux = data_out;
IOI_DQ7 : data_out_mux = data_out;
IOI_DQ8 : data_out_mux = data_out;
IOI_DQ9 : data_out_mux = data_out;
IOI_DQ10 : data_out_mux = data_out;
IOI_DQ11 : data_out_mux = data_out;
IOI_DQ12 : data_out_mux = data_out;
IOI_DQ13 : data_out_mux = data_out;
IOI_DQ14 : data_out_mux = data_out;
IOI_DQ15 : data_out_mux = data_out;
IOI_UDQS_CLK : data_out_mux = data_out;
IOI_UDQS_PIN : data_out_mux = data_out;
IOI_LDQS_CLK : data_out_mux = data_out;
IOI_LDQS_PIN : data_out_mux = data_out;
default : data_out_mux = data_out;
endcase
end
/*********************************************
* Shift Registers / Bit Counter
*********************************************/
assign data_out = (addr_data_sel_n)? {1'b0, memcell_addr_reg} : {1'b0, data_reg};
always @ (posedge DRP_CLK) begin
if(sync_rst)
shift_through_reg <= 9'b0;
else begin
if (load_shift_n) //Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= {1'b0, DRP_SDO, shift_through_reg[7:1]};
end
end
always @ (posedge DRP_CLK) begin
if (((state == ADDR_PHASE) | (state == DATA_PHASE)) & !sync_rst)
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 3'b0;
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
read_data <= 8'h00;
end
else begin
if(state == ALMOST_READY3)
read_data <= shift_through_reg;
end
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
AddressPhase <= 1'b0;
end
else begin
if (AddressPhase) begin
// Keep it set until we finish the cycle
AddressPhase <= AddressPhase && ~(state == ALMOST_READY2);
end
else begin
// set the address phase when ever we finish the address phase
AddressPhase <= (state == ADDR_PHASE) && (bit_cnt == 3'b111);
end
end
end
/*********************************************
* DRP Signals
*********************************************/
always @ (posedge DRP_CLK) begin
DRP_ADD <= (nextstate == ADDR_PHASE);
DRP_CS <= (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
// DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
MCB_UIREAD <= (nextstate == DATA_PHASE) && rd_not_write_reg;
if (state == READY)
DRP_BKST <= use_broadcast;
end
assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
/*********************************************
* State Machine
*********************************************/
always @ (*) begin
addr_data_sel_n = 1'b0;
load_shift_n = 1'b0;
case (state)
READY: begin
load_shift_n = 0;
if(cmd_valid)
nextstate = DECIDE;
else
nextstate = READY;
end
DECIDE: begin
load_shift_n = 1;
addr_data_sel_n = 1;
nextstate = ADDR_PHASE;
end
ADDR_PHASE: begin
load_shift_n = 0;
if(&bit_cnt[2:0])
if (`ALTERNATE_READ && rd_not_write_reg)
if (AddressPhase)
// After the second pass go to end of statemachine
nextstate = ALMOST_READY;
else
// execute a second address phase for the alternative access method.
nextstate = DECIDE;
else
nextstate = ADDR_TO_DATA_GAP;
else
nextstate = ADDR_PHASE;
end
ADDR_TO_DATA_GAP: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP2;
end
ADDR_TO_DATA_GAP2: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP3;
end
ADDR_TO_DATA_GAP3: begin
load_shift_n = 1;
nextstate = DATA_PHASE;
end
DATA_PHASE: begin
load_shift_n = 0;
if(&bit_cnt)
nextstate = ALMOST_READY;
else
nextstate = DATA_PHASE;
end
ALMOST_READY: begin
load_shift_n = 0;
nextstate = ALMOST_READY2;
end
ALMOST_READY2: begin
load_shift_n = 0;
nextstate = ALMOST_READY3;
end
ALMOST_READY3: begin
load_shift_n = 0;
nextstate = READY;
end
default: begin
load_shift_n = 0;
nextstate = READY;
end
endcase
end
always @ (posedge DRP_CLK) begin
if(sync_rst)
state <= READY;
else
state <= nextstate;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_1clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Single clock, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module ram_1clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLK,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLK) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: output_block
-- Description: Bloque de salida de la interfaz de red. Se encarga de la
interaccion entre el elemento de procesamiento y el
router.
Este modulo toma el resultado del elemento de
procesamiento y lo empaquete en flits para su transporte
a travez de la red.
-- Dependencies: -- system.vh
-- output_control_unit.v
-- Parameters: -- CHANNEL_WIDTH: Numero de lineas de comunicacion
entre la interfaz de red y el
router.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 18 de Junio 2015: Creacion
*/
`include "system.vh"
module output_block
(
input wire clk,
input wire reset,
// -- inputs from pn ----------------------------------------- >>>>>
input wire done_strobe_din,
input wire [(2* `CHANNEL_WIDTH)-1:0] ciphertext_din,
input wire [`CHANNEL_WIDTH-1:0] shifted_header_din,
// -- to input block ----------------------------------------- >>>>>
output wire zero_credits_dout,
// -- output port -------------------------------------------- >>>>>
input wire credit_in_din,
output reg [`CHANNEL_WIDTH-1:0] output_channel_dout
);
/*
-- Instancia: output_control_unit
-- Descripcion: Unidad de control para el bloque de salida de la
interfaz de red. Este bloque se encarga de organizar la
salida de flits en direccion del router de la red.
El control de creditos se encuentra implementado dentro
de este modulo.
*/
wire [2:0] output_selector;
output_control_unit output_control_unit
(
.clk (clk),
.reset (reset),
// -- inputs --------------------------------------------- >>>>>
.credit_in_din (credit_in_din),
.done_strobe_din (done_strobe_din),
// -- outputs -------------------------------------------- >>>>>
.zero_credits_dout (zero_credits_dout),
.output_selector_dout (output_selector)
);
/*
-- Registro
-- Descripcion: Registro de captura del resultado del elemento de
procesamiento. Este registro proporciona el dato
procesado para ser liberado a la red.
Solo se captura el texto cifrado, la llave de encriptado
se desecha.
*/
reg [(2* `CHANNEL_WIDTH)-1:0] ciphertext_reg;
always @(posedge clk)
if (done_strobe_din)
ciphertext_reg <= ciphertext_din;
/*
-- Multiplexor
-- Descripcion: Multiplexor para la seleccion del flit que saldra
a la red durante el siguiente ciclo de reloj.
Los datos de entrada para el multiplexor son los
registros de resultado del PE y la flit de cabecera
modificado.
Los dos ultimos dos flits del paquete son cargados
con las constantes 'NUL1' y 'NUL2' por razones de
trazabilidad de errores.
Si no existe transito de flits el multiplexor mantiene
el canal en un valor de 0.
*/
always @(*)
begin
output_channel_dout = {`CHANNEL_WIDTH{1'b0}};
case (output_selector)
3'b101: output_channel_dout = shifted_header_din;
3'b100: output_channel_dout = ciphertext_reg[`CHANNEL_WIDTH-1:0];
3'b011: output_channel_dout = ciphertext_reg[(2 * `CHANNEL_WIDTH)-1:`CHANNEL_WIDTH];
3'b010: output_channel_dout = "NUL1";
3'b001: output_channel_dout = "NUL2";
3'b000: output_channel_dout = {`CHANNEL_WIDTH{1'b0}};
endcase
end
endmodule
/* -- Plantilla de instancia ------------------------------------- >>>>>
output_block bloque_de_salida
(
.clk (clk),
.reset (reset),
// -- inputs from PE ----------------------------------------- >>>>>
.done_strobe_din (done_strobe_din),
.ciphertext_din (ciphertext_din),
.shifted_header_din (shifted_header_din),
// -- to input block ----------------------------------------- >>>>>
.zero_credits_dout (zero_credits_dout),
// -- output port -------------------------------------------- >>>>>
.credit_in_din (credit_in_din),
.output_channel_dout (output_channel_dout)
);
*/ |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: audio_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 151 09/26/2007 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module audio_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [31:0] q = sub_wire2[31:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=7,",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=7,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFINV_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__BUFINV_PP_BLACKBOX_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__bufinv (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFINV_PP_BLACKBOX_V
|
/* HW4, Problem 16 */
module ct4(output reg [3:0] count, output reg carry_out, input enable_l, clk_l, reset, load, input [3:0] data);
always @(negedge clk_l)
if (reset) count <= 0;
else if (load) count <= data;
else if (!enable_l) count <= count + 1;
always @(count)
if (count == 'b1111) carry_out <= 1;
else carry_out <= 0;
endmodule
module ct8(output [7:0] count, output carry_out, input enable_l, clk_l, reset, load, input [7:0] data);
wire carry_out_inter;
ct4 dev1(count[3:0], carry_out_inter, enable_l, clk_l , reset, load, data[3:0]);
ct4 dev2(count[7:4], carry_out , enable_l, carry_out_inter, reset, load, data[7:4]);
endmodule
module tb_p16();
reg enable_l, clk_l, reset, load;
reg [7:0] data;
wire [7:0] count;
wire carry_out;
ct4 dev1(count[3:0], carry_out, enable_l, clk_l , reset, load, data[3:0]);
ct4 dev2(count[7:4], _ , enable_l, carry_out, reset, load, data[7:4]);
initial begin
clk_l = 0;
forever #5 clk_l = ~clk_l;
end
initial begin
enable_l = 1;
reset = 0;
load = 0;
data = 200;
reset = 1;
#5 reset = 0;
$dumpfile("p16.vcd");
$dumpvars(0, tb_p16);
fork
#100 enable_l = 1;
#120 load = 1;
#130 load = 0;
#150 enable_l = 0;
#200 load = 1;
#240 load = 0;
#300 reset = 1;
#320 reset = 0;
#500 $finish;
join
end
endmodule
|
module lru_stats
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(ways_p)
,localparam lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
)
(
input clk_i
,input reset_i
,input stat_mem_v_i
,input stat_mem_w_i
,input [lg_ways_lp-1:0] chosen_way_i
);
localparam ctr_width_lp = 17;
localparam max_ctr_lp = 2**ctr_width_lp; // Max amounts of traces used in python scripts
// Statistic of lru_way picked
integer hit_counter [ways_p-1:0];
logic [ways_p-1:0] counter_en_li;
bsg_decode_with_v
#(.num_out_p(ways_p))
bdwv
(.i(chosen_way_i)
,.v_i(stat_mem_v_i & stat_mem_w_i)
,.o(counter_en_li)
);
for (genvar i = 0; i < ways_p; i++)
begin
always_ff @(posedge clk_i)
begin
if (reset_i)
hit_counter[i] <= 0;
else
begin
if (counter_en_li[i])
hit_counter[i] <= hit_counter[i] + 1;
end
end
end
final
begin
// display statistic
$display("######## Hit Statistic: ########");
for (integer counter_index = 0; counter_index < ways_p; counter_index++)
begin
$display("Hit counter[%d]: %d ", counter_index, hit_counter[counter_index]);
end
end
endmodule
`BSG_ABSTRACT_MODULE(lru_stats)
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.07.2016 12:04:13
// Design Name:
// Module Name: axi4_reg_if
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//`define DEBUG_JJREG
module pc_ctrl_axi4_reg_if #(
parameter DATA_W_IN_BYTES = 4,
parameter ADDR_W_IN_BITS = 32,
parameter DCADDR_LOW_BIT_W = 8,
parameter DCADDR_STROBE_MEM_SEG = 2
) (
input wire [(ADDR_W_IN_BITS)-1 : 0] S_AXI_AWADDR, // Write channel Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT, // Write address valid. This signal indicates that the master signaling valid write address and control information.
input wire S_AXI_AWVALID, // Write address ready. This signal indicates that the slave is ready // to accept an address and associated control signals.
output reg S_AXI_AWREADY=0, // Write data (issued by master, acceped by Slave)
input wire [(DATA_W_IN_BYTES*8) - 1:0] S_AXI_WDATA, // Write strobes. This signal indicates which byte lanes hold // valid data. There is one write strobe bit for each eight // bits of the write data bus.
input wire [DATA_W_IN_BYTES-1 : 0] S_AXI_WSTRB, // Write valid. This signal indicates that valid write // data and strobes are available.
input wire S_AXI_WVALID, // Write ready. This signal indicates that the slave // can accept the write data.
output reg S_AXI_WREADY=0, // Write response. This signal indicates the status // of the write transaction.
output reg [1 : 0] S_AXI_BRESP=0, // Write response valid. This signal indicates that the channel // is signaling a valid write response.
output reg S_AXI_BVALID=0, // Response ready. This signal indicates that the master // can accept a write response.
input wire S_AXI_BREADY, // Read address (issued by master, acceped by Slave)
input wire [(ADDR_W_IN_BITS)-1 : 0] S_AXI_ARADDR, // Protection type. This signal indicates the privilege // and security level of the transaction, and whether the // transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT, // Read address valid. This signal indicates that the channel // is signaling valid read address and control information.
input wire S_AXI_ARVALID, // Read address ready. This signal indicates that the slave is // ready to accept an address and associated control signals.
output reg S_AXI_ARREADY=0, // Read data (issued by slave)
output reg [(DATA_W_IN_BYTES*8) - 1:0] S_AXI_RDATA=0, // Read response. This signal indicates the status of the // read transfer.
output wire [1 : 0] S_AXI_RRESP, // Read valid. This signal indicates that the channel is signaling the required read data.
output reg S_AXI_RVALID=0, // Read ready. This signal indicates that the master can accept the read data and response information.
input wire S_AXI_RREADY, //
output wire [DCADDR_STROBE_MEM_SEG - 1:0] reg_bank_rd_start, // read start strobe
input wire [DCADDR_STROBE_MEM_SEG - 1:0] reg_bank_rd_done, // read done strobe
output wire [DCADDR_LOW_BIT_W - 1:0] reg_bank_rd_addr, // read address bus
input wire [(DATA_W_IN_BYTES*8) - 1:0] reg_bank_rd_data, // read data bus
output wire [(ADDR_W_IN_BITS)-1:DCADDR_LOW_BIT_W] decode_rd_addr, // used external to the block to select the correct returning data
output wire [DCADDR_STROBE_MEM_SEG - 1:0] reg_bank_wr_start, // write start strobe
input wire [DCADDR_STROBE_MEM_SEG - 1:0] reg_bank_wr_done, // write done strobe
output wire [DCADDR_LOW_BIT_W - 1:0] reg_bank_wr_addr, // write address bus
output reg [(DATA_W_IN_BYTES*8) - 1:0] reg_bank_wr_data=0,// write data bus
input wire ACLK , // Clock source
input wire ARESETn // Reset source
);
//-----------------------------------------------------------------------------
// LocalParams
//-----------------------------------------------------------------------------
localparam access_state_idle = 0; // Idle
localparam access_state_rd_start = 1; // read started
localparam access_state_rd_wait_complete = 2; // Wait on internal bank completion
localparam access_state_rd_wait_ready = 3; // Wait on AXI interface completion
localparam access_state_wr_start = 4; // write started
localparam access_state_wr_wait_complete = 5; // Wait on internal bank completion
localparam access_state_wr_wait_ready = 6; // Wait on AXI interface completion
//-----------------------------------------------------------------------------
// Internal signals
//-----------------------------------------------------------------------------
reg [2:0] access_state=0; // State register for access sequencin
reg start_read =0; // Strobe indicating a read has started
reg start_write =0; // Strobe indicating a write has started
wire [DCADDR_STROBE_MEM_SEG - 1:0] read_decode; // Read strobe bus, one bit for each register bank
wire [DCADDR_STROBE_MEM_SEG - 1:0] write_decode; // Write strobe bus, one bit for each register bank
reg [(ADDR_W_IN_BITS)-1 : 0] rd_addr=0; // Keep a full copy of the address as we need the
reg [(ADDR_W_IN_BITS)-1 : 0] wr_addr=0; // to pass to the banks and decode the strobes
// wires to slice the top of the address used to decode the relevant bank
wire [(ADDR_W_IN_BITS)-1:DCADDR_LOW_BIT_W] decode_wr_addr;
//-----------------------------------------------------------------------------
// For simplicity everything is marked as OKAY.
//-----------------------------------------------------------------------------
assign S_AXI_RRESP = 'd0; // OKAY
//-----------------------------------------------------------------------------
// Address Decoding
// Wire bus registered in state process. One for each channel for debug ease
// Could optomise into one.
//-----------------------------------------------------------------------------
// Slice the address bus for the block outputs xx_addr are registers
assign reg_bank_rd_addr = rd_addr[DCADDR_LOW_BIT_W -1 : 0];
assign reg_bank_wr_addr = wr_addr[DCADDR_LOW_BIT_W -1 : 0];
assign decode_rd_addr = rd_addr[(ADDR_W_IN_BITS)-1:DCADDR_LOW_BIT_W];
assign decode_wr_addr = wr_addr[(ADDR_W_IN_BITS)-1:DCADDR_LOW_BIT_W];
// This generate loop allows us to generate a variable number of decode strobes
// for the attached banks.
genvar i;
generate
for (i = 0; i < DCADDR_STROBE_MEM_SEG ; i = i + 1) begin
// Read decoding logic
assign read_decode[i] = decode_rd_addr == i;
// write decoding logic
assign write_decode[i] = decode_wr_addr == i;
// Generate the strobes that leave this block to the blank. start_read is registered.
assign reg_bank_rd_start[i] = start_read & read_decode[i];
// Generate the strobes that leave this block to the blank. start_read is registered.
assign reg_bank_wr_start[i] = start_write & write_decode[i];
end
endgenerate
assign out_of_range_read = start_read & (reg_bank_rd_start=='d0);
assign out_of_range_write = start_write & (reg_bank_wr_start=='d0);
//-----------------------------------------------------------------------------
// Data muxing of the returned data must be done external to this block.
// Required signals are provided as outputs. The data from the external block
// must be valid when the corresponding ....xx_rd_done is set.
//-----------------------------------------------------------------------------
always @(posedge ACLK) begin
if (|reg_bank_rd_done) begin
S_AXI_RDATA <= reg_bank_rd_data;
end else begin
S_AXI_RDATA <= S_AXI_RDATA;
end
end
//-----------------------------------------------------------------------------
// SM that controls R/W access. We only allow one action at a time
//-----------------------------------------------------------------------------
always @(posedge ACLK) begin
if(!ARESETn)begin
access_state <= access_state_idle;
start_read <= 1'd0;
start_write <= 1'd0;
S_AXI_AWREADY <= 1'd0;
S_AXI_WREADY <= 1'd0;
S_AXI_BVALID <= 1'd0;
S_AXI_ARREADY <= 1'd0;
end else begin
access_state <= access_state;
// Write
S_AXI_AWREADY <= 1'd0; // Should only be high for a cycle
S_AXI_WREADY <= 1'd0; // Should only be high for a cycle
S_AXI_BVALID <= S_AXI_BVALID; // This signal may need to be held
start_write <= 1'd0; // Single pulse signal
// Read
S_AXI_ARREADY <= 1'd0; // Should only be high for a cycle
start_read <= 1'd0; // Signal pulse signal
case(access_state)
// In idle we can accept reads or writes, but not both at the same time
// for this controller. We will proritise reads over writes.
access_state_idle : begin
S_AXI_RVALID <= 1'd0; // Low until data is Valid
if(S_AXI_ARVALID) begin
S_AXI_ARREADY <= 1'd1; // Assert AXI strobe
access_state <= access_state_rd_start; // Read state sequence
rd_addr <= S_AXI_ARADDR; // Lock address for internal use
start_read <= 1'd1; // Atart the read internally
end else begin
if(S_AXI_AWVALID & S_AXI_WVALID) begin
// we can wait for both signals to be asserted before starting a write. Simplifies logic.
// the slave can wait for AWVALID or WVALID, or both before asserting AWREADY
// the slave can wait for AWVALID or WVALID, or both, before asserting WREADY
access_state <= access_state_wr_start; // Write state sequence
wr_addr <= S_AXI_AWADDR; // Lock the address & data for internal use
reg_bank_wr_data <= S_AXI_WDATA;
S_AXI_AWREADY <= 1'd1; // Assert ready strobes
S_AXI_WREADY <= 1'd1;
start_write <= 1'd1; // Start the write internally
end
end
end
// READ
access_state_rd_start : begin
S_AXI_ARREADY <= 1'd0; // was asserted on leaving idle, clear Address is locked
if (|reg_bank_rd_done | out_of_range_read) begin
// Internal bank access is complete
S_AXI_RVALID <= 1'd1;
access_state <= access_state_rd_wait_ready;
end else begin
access_state <= access_state_rd_wait_complete;
end
end
access_state_rd_wait_complete : begin
if (|reg_bank_rd_done | out_of_range_read) begin
S_AXI_RVALID <= 1'd1;
access_state <= access_state_rd_wait_ready;
end
end
access_state_rd_wait_ready : begin
if (S_AXI_RREADY) begin
S_AXI_RVALID <= 1'd0;
access_state <= access_state_idle;
end
end
// WRITE
access_state_wr_start : begin
S_AXI_AWREADY <= 1'd0;
S_AXI_WREADY <= 1'd0;
if (|reg_bank_wr_done | out_of_range_write) begin
S_AXI_BVALID <= 1'd1;
access_state <= access_state_wr_wait_ready;
end else begin
access_state <= access_state_wr_wait_complete;
end
end
access_state_wr_wait_complete : begin
if (|reg_bank_wr_done | out_of_range_write) begin
S_AXI_BVALID <= 1'd1;
access_state <= access_state_wr_wait_ready;
end else begin
access_state <= access_state_wr_wait_complete;
end
end
access_state_wr_wait_ready : begin
if (S_AXI_BREADY) begin
S_AXI_BVALID <= 1'd0;
access_state <= access_state_idle;
end
end
default : access_state <= access_state;
endcase
end
end
//-----------------------------------------------------------------------------
// Dependencies
// A3.3.1 AXI4_specification
// http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf
//-----------------------------------------------------------------------------
// Dependencies between channel handshake signals
// To prevent a deadlock situation, the dependency rules that exist between the handshake signals must be observed.
// As summarized in Channel signaling requirements on page A3-38, in any transaction:
// the VALID signal of the AXI interface sending information must not be dependent on the READY signal of the AXI interface receiving that information
// an AXI interface that is receiving information can wait until it detects a VALID signal before it asserts its corresponding READY signal.
// Note
// While it is acceptable to wait for VALID to be asserted before asserting READY, it is also acceptable to assert READY before detecting the corresponding VALID. This can result in a more efficient design.
// In addition, there are dependencies between the handshake signals on different channels, and AXI4 defines an additional write response dependency. The following subsections define these dependencies:
// Read transaction dependencies on page A3-41
// Write transaction dependencies on page A3-41
// AXI4 write response dependency on page A3-42. In the dependency diagrams:
//single-headed arrows point to signals that can be asserted before or after the signal at the start of the arrow
//double-headed arrows point to signals that must be asserted only after assertion of the signal at the start of the arrow.
//-----------------------------------------------------------------------------
// READ transaction
//-----------------------------------------------------------------------------
// ARVALID -------------->> RVALID
// \ >> \
// \ / \
// > ARREADY / > RREADY
//Figure A3-5 shows the read transaction handshake signal dependencies, and shows that, in a read transaction:
// the master must not wait for the slave to assert ARREADY before asserting ARVALID
// the slave can wait for ARVALID to be asserted before it asserts ARREADY
// the slave can assert ARREADY before ARVALID is asserted
// the slave must wait for both ARVALID and ARREADY to be asserted before it asserts RVALID to indicate that valid data is available
// the slave must not wait for the master to assert RREADY before asserting RVALID
// the master can wait for RVALID to be asserted before it asserts RREADY
// the master can assert RREADY before RVALID is asserted.
//-----------------------------------------------------------------------------
// WRITE transaction
//-----------------------------------------------------------------------------
// AWVALID --- WVALID ---------------->> BVALID \
// \ \__________ / \ />> \
// \ \/ \ / \
// \ /\ \_> / \
// > AWREADY </ \__________> WREADY / \__> BREADY
// Figure A3-6 shows the write transaction handshake signal dependencies, and shows that in a write transaction:
// the master must not wait for the slave to assert AWREADY or WREADY before asserting AWVALID or
// WVALID
// the slave can wait for AWVALID or WVALID, or both before asserting AWREADY
// the slave can assert AWREADY before AWVALID or WVALID, or both, are asserted
// the slave can wait for AWVALID or WVALID, or both, before asserting WREADY
// the slave can assert WREADY before AWVALID or WVALID, or both, are asserted
// the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID
// the slave must also wait for WLAST to be asserted before asserting BVALID, because the write response,
// BRESP, must be signaled only after the last data transfer of a write transaction
// the slave must not wait for the master to assert BREADY before asserting BVALID
// the master can wait for BVALID before asserting BREADY
// the master can assert BREADY before BVALID is asserted.
// ACLK Clock source ARESETn Reset source
// Description
// Global clock signal. See Clock on page A3-36.
// Global reset signal, active LOW. See Reset on page A3-36.
// Signal
// WID
// WDATA WSTRB
// WLAST WUSER
// WVALID WREADY
// Source Description
// Table A2-3 Write data channel signals
// Master Write ID tag. This signal is the ID tag of the write data transfer. Supported only in AXI3. See Transaction ID on page A5-77.
// Master Write data.
// Master Write strobes. This signal indicates which byte lanes hold valid data. There is one write
// strobe bit for each eight bits of the write data bus. See Write strobes on page A3-49. Master Write last. This signal indicates the last transfer in a write burst. See Write data channel
// on page A3-39.
// Master User signal. Optional User-defined signal in the write data channel.
// Supported only in AXI4. See User-defined signaling on page A8-100.
// Master Write valid. This signal indicates that valid write data and strobes are available. See
// Channel handshake signals on page A3-38.
// Slave Write ready. This signal indicates that the slave can accept the write data. See Channel
// handshake signals on page A3-38.
// Signal Source
// RID Slave RDATA Slave
// RRESP Slave RLAST Slave RUSER Slave
// RVALID Slave RREADY Master
// Description
// Table A2-6 Read data channel signals
// Read ID tag. This signal is the identification tag for the read data group of signals generated by the slave. See Transaction ID on page A5-77.
// Read data.
// Read response. This signal indicates the status of the read transfer. See Read and write
// response structure on page A3-54.
// Read last. This signal indicates the last transfer in a read burst. See Read data channel on
// page A3-39.
// User signal. Optional User-defined signal in the read data channel.
// Supported only in AXI4. See User-defined signaling on page A8-100.
// Read valid. This signal indicates that the channel is signaling the required read data. See
// Channel handshake signals on page A3-38.
// Read ready. This signal indicates that the master can accept the read data and response
// information. See Channel handshake signals on page A3-38.
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKMUX2_4_V
`define SKY130_FD_SC_HDLL__CLKMUX2_4_V
/**
* clkmux2: Clock mux.
*
* Verilog wrapper for clkmux2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkmux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkmux2_4 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkmux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkmux2_4 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkmux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKMUX2_4_V
|
//-----------------------------------------------------------------------------
// Title : Read-Only Memory (Instruction ROM)
// Project : ECE 313 - Computer Organization
//-----------------------------------------------------------------------------
// File : rom32.v
// Author : John Nestor <[email protected]>
// Organization : Lafayette College
//
// Created : October 2002
// Last modified : 7 January 2005
//-----------------------------------------------------------------------------
// Description :
// Behavioral model of a read-only memory used in the implementations of the MIPS
// processor subset described in Ch. 5-6 of "Computer Organization and Design, 3rd ed."
// by David Patterson & John Hennessey, Morgan Kaufmann, 2004 (COD3e).
//
// Note the use of the Verilog concatenation operator to specify different
// instruction fields in each memory element.
//
//-----------------------------------------------------------------------------
module rom32(address, data_out);
input [31:0] address;
output [31:0] data_out;
reg [31:0] data_out;
parameter BASE_ADDRESS = 25'd0; // address that applies to this memory
wire [4:0] mem_offset;
wire address_select;
assign mem_offset = address[6:2]; // drop 2 LSBs to get word offset
assign address_select = (address[31:7] == BASE_ADDRESS); // address decoding
always @(address_select or mem_offset)
begin
if ((address % 4) != 0) $display($time, " rom32 error: unaligned address %d", address);
if (address_select == 1)
begin
case (mem_offset)
/*
5'd0 : data_out = { 6'd35, 5'd0, 5'd2, 16'd4 }; // lw $2, 4($0) r2=0
5'd1 : data_out = { 6'd35, 5'd0, 5'd3, 16'd8 }; // lw $3, 8($0) r3=2
5'd2 : data_out = { 6'd35, 5'd0, 5'd4, 16'd20 }; // lw $4, 20($0) r4=5
5'd3 : data_out = { 6'd0, 5'd0, 5'd0, 5'd5, 5'd0, 6'd32 }; // add $5, $0, $0 r5=0
5'd4 : data_out = { 6'd0, 5'd5, 5'd2, 5'd5, 5'd0, 6'd32 }; // add $5, $5, $1 r5 = r5 + 1
5'd5 : data_out = { 6'd0, 5'd4, 5'd5, 5'd6, 5'd0, 6'd42 }; // slt $6, $4, $5 is $5 > $4?
5'd6 : data_out = { 6'd4, 5'd6, 5'd0, -16'd3 }; // beq $6, $zero, -3 if not, go back 2
5'd7 : data_out = { 6'd43, 5'd0, 5'd5, 16'd0 }; // MEM[0] = $5
5'd8 : data_out = { 6'd8, 5'd2, 5'd2, 16'd04 }; // addi $2 = $2 + 4 = 4
5'd9 : data_out = { 6'd5, 5'd2, 5'd3, -16'd3 }; // bne $2 != $3 goto -3
5'd10 : data_out = { 6'd2 , 26'd2 }; // j jump to location 2
*/
5'd0 : data_out = { 6'd35, 5'd0, 5'd4, 16'd20 }; //lw $4, 20($0) 4 = 5
5'd1 : data_out = { 6'd0, 5'd0, 5'd0, 5'd5, 5'd0, 6'd32 }; //add $5, $0, $0
5'd2 : data_out = { 6'd8, 5'd5, 5'd5, 16'd1 }; //addi $5, $5, 1
5'd3 : data_out = { 6'd5, 5'd5, 5'd4,-16'd2 }; //bne $5, $4, -2
5'd4 : data_out = { 6'd2 , 26'd1 }; //j 1
default data_out = 32'hxxxx;
endcase
$display($time, " reading data: rom32[%h] => %h", address, data_out);
end
end
endmodule
|
`timescale 1ns / 1ps
/*
Group Members: Thomas Hudson and Warren Seto
Lab Name: Combinational Logic
Project Name: eng312_proj2
Design Name: three_bit_comparator_test.v
Design Description: Verilog Test Module for Three Bit Comparator
*/
module three_bit_comparator_test;
// Inputs
reg [2:0] A;
reg [2:0] B;
// Outputs
wire GT;
wire LT;
wire EQ;
// Instantiate two counter variables for both loop
integer count;
// Instantiate the Unit Under Test (UUT)
three_bit_comparator uut
(
.A(A),
.B(B),
.GT(GT),
.LT(LT),
.EQ(EQ)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
// Initialize counter variables
count = 0;
end
// Whenever the value of either A or B changes, iterate the possible combinations
always @(A or B) begin
// Loops over the possible combinations for A and B
for (count = 0; count < 64; count = count + 1)
#1 {A, B} = count;
#5 $stop;
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:22 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/zynq_design_1_axi_gpio_0_0_stub.v
// Design : zynq_design_1_axi_gpio_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.2" *)
module zynq_design_1_axi_gpio_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output [7:0]gpio_io_o;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3_4_V
`define SKY130_FD_SC_LS__AND3_4_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3_4_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:49:55 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_axi_spi_master_0_0_stub.v
// Design : DemoInterconnect_axi_spi_master_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_spi_master_v1_0,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(m_spi_mosi, m_spi_miso, m_spi_ss, m_spi_sclk,
s00_axi_awaddr, s00_axi_awprot, s00_axi_awvalid, s00_axi_awready, s00_axi_wdata,
s00_axi_wstrb, s00_axi_wvalid, s00_axi_wready, s00_axi_bresp, s00_axi_bvalid,
s00_axi_bready, s00_axi_araddr, s00_axi_arprot, s00_axi_arvalid, s00_axi_arready,
s00_axi_rdata, s00_axi_rresp, s00_axi_rvalid, s00_axi_rready, s00_axi_aclk,
s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="m_spi_mosi,m_spi_miso,m_spi_ss,m_spi_sclk,s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output m_spi_mosi;
input m_spi_miso;
output m_spi_ss;
output m_spi_sclk;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_16 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_15 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_14 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_13 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_12 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_11 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_10 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_9 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_8 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_7 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_6 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_5 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_4 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_3 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_2 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_1 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module SNPS_CLOCK_GATE_HIGH_ff32_en_1 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3594, net3596, net3597, net3600;
assign net3594 = CLK;
assign ENCLK = net3596;
assign net3597 = EN;
DLL_X1 latch ( .D(net3597), .GN(net3594), .Q(net3600) );
AND2_X1 main_gate ( .A1(net3600), .A2(net3594), .ZN(net3596) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_33 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_32 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_31 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_30 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_29 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_28 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_27 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_26 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_25 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_24 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_23 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_22 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_21 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_20 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_19 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_18 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_17 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_16 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_15 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_14 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_13 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_12 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_11 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_10 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_9 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_8 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_7 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_6 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_5 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_4 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_3 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_2 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_1 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE5_3 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3349, net3351, net3352, net3355;
assign net3349 = CLK;
assign ENCLK = net3351;
assign net3352 = EN;
DLL_X1 latch ( .D(net3352), .GN(net3349), .Q(net3355) );
AND2_X1 main_gate ( .A1(net3355), .A2(net3349), .ZN(net3351) );
endmodule
module SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE5_2 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3349, net3351, net3352, net3355;
assign net3349 = CLK;
assign ENCLK = net3351;
assign net3352 = EN;
DLL_X1 latch ( .D(net3352), .GN(net3349), .Q(net3355) );
AND2_X1 main_gate ( .A1(net3355), .A2(net3349), .ZN(net3351) );
endmodule
module SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE32_5 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3334, net3336, net3337, net3340;
assign net3334 = CLK;
assign ENCLK = net3336;
assign net3337 = EN;
DLL_X1 latch ( .D(net3337), .GN(net3334), .Q(net3340) );
AND2_X1 main_gate ( .A1(net3340), .A2(net3334), .ZN(net3336) );
endmodule
module SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE32_4 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3334, net3336, net3337, net3340;
assign net3334 = CLK;
assign ENCLK = net3336;
assign net3337 = EN;
DLL_X1 latch ( .D(net3337), .GN(net3334), .Q(net3340) );
AND2_X1 main_gate ( .A1(net3340), .A2(net3334), .ZN(net3336) );
endmodule
module SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE32_1 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3334, net3336, net3337, net3340;
assign net3334 = CLK;
assign ENCLK = net3336;
assign net3337 = EN;
DLL_X1 latch ( .D(net3337), .GN(net3334), .Q(net3340) );
AND2_X1 main_gate ( .A1(net3340), .A2(net3334), .ZN(net3336) );
endmodule
module FA_127 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
endmodule
module FA_126 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_125 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_120 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XOR2_X1 U1 ( .A(B), .B(A), .Z(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module FA_119 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_118 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_117 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_116 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
OR2_X1 U1 ( .A1(A), .A2(B), .ZN(Co) );
XNOR2_X1 U2 ( .A(B), .B(A), .ZN(S) );
endmodule
module FA_115 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_114 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_113 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_112 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XOR2_X1 U1 ( .A(A), .B(B), .Z(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module FA_111 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_110 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_109 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_108 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
OR2_X1 U1 ( .A1(A), .A2(B), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(B), .ZN(S) );
endmodule
module FA_107 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_106 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_105 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_104 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XOR2_X1 U1 ( .A(A), .B(B), .Z(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module FA_103 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_102 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_101 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_100 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
OR2_X1 U1 ( .A1(A), .A2(B), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(B), .ZN(S) );
endmodule
module FA_99 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_98 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_97 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_96 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XOR2_X1 U1 ( .A(B), .B(A), .Z(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module FA_95 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_94 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_93 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n1;
XOR2_X1 U1 ( .A(B), .B(A), .Z(n1) );
XOR2_X1 U2 ( .A(Ci), .B(n1), .Z(S) );
endmodule
module FA_92 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
OR2_X1 U1 ( .A1(A), .A2(B), .ZN(Co) );
XNOR2_X1 U2 ( .A(B), .B(A), .ZN(S) );
endmodule
module FA_91 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_90 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U1 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U3 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_89 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n1;
XOR2_X1 U1 ( .A(B), .B(A), .Z(n1) );
XOR2_X1 U2 ( .A(Ci), .B(n1), .Z(S) );
endmodule
module FA_88 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XOR2_X1 U1 ( .A(B), .B(A), .Z(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module FA_87 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U1 ( .A1(B), .A2(Ci), .ZN(n5) );
OAI21_X1 U3 ( .B1(Ci), .B2(B), .A(A), .ZN(n4) );
NAND2_X1 U4 ( .A1(n4), .A2(n5), .ZN(Co) );
XNOR2_X1 U5 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_86 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U1 ( .A1(B), .A2(Ci), .ZN(n5) );
OAI21_X1 U2 ( .B1(Ci), .B2(B), .A(A), .ZN(n4) );
NAND2_X1 U3 ( .A1(n4), .A2(n5), .ZN(Co) );
XNOR2_X1 U4 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U5 ( .A(n6), .B(B), .ZN(S) );
endmodule
module FA_85 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U1 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U2 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_84 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
OR2_X1 U1 ( .A1(A), .A2(B), .ZN(Co) );
XNOR2_X1 U2 ( .A(B), .B(A), .ZN(S) );
endmodule
module FA_83 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U1 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U3 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_82 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U3 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U4 ( .A1(n5), .A2(n4), .ZN(Co) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_81 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
endmodule
module FA_80 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n3;
INV_X1 U1 ( .A(A), .ZN(n3) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
XNOR2_X1 U3 ( .A(n3), .B(B), .ZN(S) );
endmodule
module FA_79 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_78 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U3 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U4 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U5 ( .A1(n5), .A2(n4), .ZN(Co) );
endmodule
module FA_77 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
endmodule
module FA_76 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
OR2_X1 U1 ( .A1(A), .A2(B), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(B), .ZN(S) );
endmodule
module FA_75 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_74 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_73 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_72 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XOR2_X1 U1 ( .A(A), .B(B), .Z(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module FA_71 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_70 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2, n3, n4;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n4) );
OAI21_X1 U1 ( .B1(Ci), .B2(B), .A(A), .ZN(n2) );
NAND2_X1 U3 ( .A1(n2), .A2(n3), .ZN(Co) );
NAND2_X1 U4 ( .A1(Ci), .A2(B), .ZN(n3) );
XNOR2_X1 U5 ( .A(n4), .B(B), .ZN(S) );
endmodule
module FA_69 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
FA_X1 U1 ( .A(B), .B(A), .CI(Ci), .S(S) );
endmodule
module FA_68 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
OR2_X1 U1 ( .A1(A), .A2(B), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(B), .ZN(S) );
endmodule
module FA_67 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2, n3, n4;
OAI21_X1 U1 ( .B1(Ci), .B2(B), .A(A), .ZN(n2) );
NAND2_X1 U2 ( .A1(n2), .A2(n3), .ZN(Co) );
NAND2_X1 U3 ( .A1(Ci), .A2(B), .ZN(n3) );
XNOR2_X1 U4 ( .A(n4), .B(B), .ZN(S) );
XNOR2_X1 U5 ( .A(A), .B(Ci), .ZN(n4) );
endmodule
module FA_66 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2, n3, n4;
OAI21_X1 U1 ( .B1(Ci), .B2(B), .A(A), .ZN(n2) );
NAND2_X1 U2 ( .A1(n2), .A2(n3), .ZN(Co) );
NAND2_X1 U3 ( .A1(Ci), .A2(B), .ZN(n3) );
XNOR2_X1 U4 ( .A(n4), .B(B), .ZN(S) );
XNOR2_X1 U5 ( .A(Ci), .B(A), .ZN(n4) );
endmodule
module FA_65 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U1 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U2 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_64 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XOR2_X1 U1 ( .A(B), .B(A), .Z(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module FA_63 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_62 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_61 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_60 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
OR2_X1 U1 ( .A1(A), .A2(B), .ZN(Co) );
XNOR2_X1 U2 ( .A(B), .B(A), .ZN(S) );
endmodule
module FA_59 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_58 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_57 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_56 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XOR2_X1 U1 ( .A(B), .B(A), .Z(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module FA_55 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U1 ( .A1(B), .A2(Ci), .ZN(n4) );
XNOR2_X1 U4 ( .A(n6), .B(B), .ZN(S) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_54 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_53 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_52 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XNOR2_X1 U1 ( .A(B), .B(A), .ZN(S) );
OR2_X1 U2 ( .A1(A), .A2(B), .ZN(Co) );
endmodule
module FA_51 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U1 ( .A1(B), .A2(Ci), .ZN(n4) );
XNOR2_X1 U4 ( .A(n6), .B(B), .ZN(S) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_50 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_49 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_48 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XOR2_X1 U1 ( .A(B), .B(A), .Z(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module FA_47 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_46 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_45 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
FA_X1 U1 ( .A(B), .B(A), .CI(Ci), .S(S) );
endmodule
module FA_44 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XNOR2_X1 U1 ( .A(B), .B(A), .ZN(S) );
OR2_X1 U2 ( .A1(A), .A2(B), .ZN(Co) );
endmodule
module FA_43 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_42 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_41 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n1, n2;
INV_X1 U1 ( .A(A), .ZN(n2) );
XOR2_X1 U2 ( .A(B), .B(n2), .Z(n1) );
XNOR2_X1 U3 ( .A(Ci), .B(n1), .ZN(S) );
endmodule
module FA_40 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n3;
AND2_X1 U1 ( .A1(B), .A2(A), .ZN(Co) );
INV_X1 U2 ( .A(A), .ZN(n3) );
XNOR2_X1 U3 ( .A(n3), .B(B), .ZN(S) );
endmodule
module FA_39 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_38 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_37 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_36 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
OR2_X1 U1 ( .A1(A), .A2(B), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(B), .ZN(S) );
endmodule
module FA_35 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_34 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_33 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_32 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n3;
XNOR2_X1 U1 ( .A(n3), .B(B), .ZN(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
INV_X1 U3 ( .A(A), .ZN(n3) );
endmodule
module FA_31 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_30 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_29 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n1;
XNOR2_X1 U1 ( .A(A), .B(B), .ZN(n1) );
XNOR2_X1 U2 ( .A(Ci), .B(n1), .ZN(S) );
endmodule
module FA_28 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XNOR2_X1 U1 ( .A(A), .B(B), .ZN(S) );
OR2_X1 U2 ( .A1(A), .A2(B), .ZN(Co) );
endmodule
module FA_27 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_26 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_25 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n1;
XNOR2_X1 U1 ( .A(A), .B(B), .ZN(n1) );
XNOR2_X1 U2 ( .A(Ci), .B(n1), .ZN(S) );
endmodule
module FA_24 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n3;
INV_X1 U1 ( .A(A), .ZN(n3) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
XNOR2_X1 U3 ( .A(n3), .B(B), .ZN(S) );
endmodule
module FA_23 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_22 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_21 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_20 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
OR2_X1 U1 ( .A1(A), .A2(B), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(B), .ZN(S) );
endmodule
module FA_19 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_18 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_17 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_16 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XOR2_X1 U1 ( .A(A), .B(B), .Z(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module FA_15 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_14 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_13 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_12 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
OR2_X1 U1 ( .A1(A), .A2(B), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(B), .ZN(S) );
endmodule
module FA_11 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_10 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_9 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_8 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n3;
XNOR2_X1 U1 ( .A(n3), .B(B), .ZN(S) );
INV_X1 U2 ( .A(A), .ZN(n3) );
AND2_X1 U3 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module FA_7 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
OAI21_X1 U3 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
NAND2_X1 U5 ( .A1(n5), .A2(n4), .ZN(Co) );
endmodule
module FA_6 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
endmodule
module FA_5 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U1 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U2 ( .A(n2), .B(B), .ZN(S) );
endmodule
module FA_4 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XNOR2_X1 U1 ( .A(A), .B(B), .ZN(S) );
OR2_X1 U2 ( .A1(A), .A2(B), .ZN(Co) );
endmodule
module FA_3 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
endmodule
module FA_2 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n4, n5, n6;
OAI21_X1 U5 ( .B1(Ci), .B2(B), .A(A), .ZN(n5) );
NAND2_X1 U4 ( .A1(B), .A2(Ci), .ZN(n4) );
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n6) );
XNOR2_X1 U1 ( .A(n6), .B(B), .ZN(S) );
NAND2_X1 U3 ( .A1(n5), .A2(n4), .ZN(Co) );
endmodule
module FA_1 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
wire n2;
XNOR2_X1 U2 ( .A(A), .B(Ci), .ZN(n2) );
XNOR2_X1 U1 ( .A(n2), .B(B), .ZN(S) );
endmodule
module mux21_SIZE4_15 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U1 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U4 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
endmodule
module mux21_SIZE4_14 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U1 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U4 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
endmodule
module mux21_SIZE4_13 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U1 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U4 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
endmodule
module mux21_SIZE4_12 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U1 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U4 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
endmodule
module mux21_SIZE4_11 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U1 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
MUX2_X1 U4 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
endmodule
module mux21_SIZE4_10 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U4 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
MUX2_X1 U1 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
endmodule
module mux21_SIZE4_9 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U1 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U2 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
MUX2_X1 U4 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
endmodule
module mux21_SIZE4_8 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U1 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U4 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
endmodule
module mux21_SIZE4_7 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U1 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U2 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
MUX2_X1 U4 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
endmodule
module mux21_SIZE4_6 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U1 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
MUX2_X1 U4 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
endmodule
module mux21_SIZE4_5 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U1 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U4 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
endmodule
module mux21_SIZE4_4 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U4 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
MUX2_X1 U1 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
endmodule
module mux21_SIZE4_3 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U1 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
MUX2_X1 U2 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U4 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
endmodule
module mux21_SIZE4_2 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U1 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U3 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U4 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
endmodule
module mux21_SIZE4_1 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
MUX2_X1 U2 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U4 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
MUX2_X1 U1 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U3 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
endmodule
module RCA_N4_30 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_120 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_119 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_118 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_117 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_29 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_116 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_115 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_114 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_113 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_28 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_112 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_111 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_110 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_109 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_27 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_108 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_107 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_106 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_105 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_26 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_104 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_103 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_102 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_101 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_25 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_100 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_99 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_98 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_97 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_24 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_96 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_95 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_94 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_93 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_23 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_92 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_91 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_90 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_89 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_22 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_88 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_87 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_86 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_85 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_21 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_84 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_83 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_82 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_81 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_20 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_80 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_79 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_78 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_77 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_19 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_76 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_75 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_74 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_73 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_18 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_72 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_71 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_70 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_69 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_17 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_68 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_67 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_66 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_65 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_16 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_64 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_63 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_62 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_61 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_15 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_60 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_59 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_58 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_57 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_14 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_56 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_55 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_54 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_53 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_13 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_52 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_51 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_50 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_49 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_12 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_48 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_47 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_46 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_45 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_11 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_44 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_43 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_42 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_41 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_10 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_40 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_39 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_38 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_37 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_9 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_36 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_35 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_34 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_33 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_8 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_32 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_31 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_30 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_29 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_7 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_28 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_27 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_26 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_25 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_6 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_24 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_23 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_22 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_21 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_5 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_20 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_19 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_18 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_17 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_4 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_16 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_15 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_14 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_13 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_3 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_12 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_11 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_10 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_9 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_2 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_8 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_7 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_6 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_5 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module RCA_N4_1 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_4 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b1), .S(S[0]), .Co(CTMP[1]) );
FA_3 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_2 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_1 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module shift_N9_2 ( Clock, ALOAD, D, SO );
input [8:0] D;
input Clock, ALOAD;
output SO;
wire N11;
wire [8:1] tmp;
DFF_X1 \tmp_reg[8] ( .D(N11), .CK(Clock), .Q(tmp[8]) );
SDFF_X1 \tmp_reg[7] ( .D(tmp[8]), .SI(D[7]), .SE(ALOAD), .CK(Clock), .Q(
tmp[7]) );
SDFF_X1 \tmp_reg[6] ( .D(tmp[7]), .SI(D[6]), .SE(ALOAD), .CK(Clock), .Q(
tmp[6]) );
SDFF_X1 \tmp_reg[5] ( .D(tmp[6]), .SI(D[5]), .SE(ALOAD), .CK(Clock), .Q(
tmp[5]) );
SDFF_X1 \tmp_reg[4] ( .D(tmp[5]), .SI(D[4]), .SE(ALOAD), .CK(Clock), .Q(
tmp[4]) );
SDFF_X1 \tmp_reg[3] ( .D(tmp[4]), .SI(D[3]), .SE(ALOAD), .CK(Clock), .Q(
tmp[3]) );
SDFF_X1 \tmp_reg[2] ( .D(tmp[3]), .SI(D[2]), .SE(ALOAD), .CK(Clock), .Q(
tmp[2]) );
SDFF_X1 \tmp_reg[1] ( .D(tmp[2]), .SI(D[1]), .SE(ALOAD), .CK(Clock), .Q(
tmp[1]) );
SDFF_X1 \tmp_reg[0] ( .D(tmp[1]), .SI(D[0]), .SE(ALOAD), .CK(Clock), .Q(SO)
);
AND2_X1 U3 ( .A1(ALOAD), .A2(D[8]), .ZN(N11) );
endmodule
module shift_N9_1 ( Clock, ALOAD, D, SO );
input [8:0] D;
input Clock, ALOAD;
output SO;
wire N11;
wire [8:1] tmp;
DFF_X1 \tmp_reg[8] ( .D(N11), .CK(Clock), .Q(tmp[8]) );
SDFF_X1 \tmp_reg[7] ( .D(tmp[8]), .SI(D[7]), .SE(ALOAD), .CK(Clock), .Q(
tmp[7]) );
SDFF_X1 \tmp_reg[6] ( .D(tmp[7]), .SI(D[6]), .SE(ALOAD), .CK(Clock), .Q(
tmp[6]) );
SDFF_X1 \tmp_reg[5] ( .D(tmp[6]), .SI(D[5]), .SE(ALOAD), .CK(Clock), .Q(
tmp[5]) );
SDFF_X1 \tmp_reg[4] ( .D(tmp[5]), .SI(D[4]), .SE(ALOAD), .CK(Clock), .Q(
tmp[4]) );
SDFF_X1 \tmp_reg[3] ( .D(tmp[4]), .SI(D[3]), .SE(ALOAD), .CK(Clock), .Q(
tmp[3]) );
SDFF_X1 \tmp_reg[2] ( .D(tmp[3]), .SI(D[2]), .SE(ALOAD), .CK(Clock), .Q(
tmp[2]) );
SDFF_X1 \tmp_reg[1] ( .D(tmp[2]), .SI(D[1]), .SE(ALOAD), .CK(Clock), .Q(
tmp[1]) );
AND2_X1 U3 ( .A1(ALOAD), .A2(D[8]), .ZN(N11) );
SDFF_X2 \tmp_reg[0] ( .D(tmp[1]), .SI(D[0]), .SE(ALOAD), .CK(Clock), .Q(SO)
);
endmodule
module booth_encoder_8 ( B_in, A_out );
input [2:0] B_in;
output [2:0] A_out;
wire n6, n7, n8, n9;
OAI33_X1 U6 ( .A1(B_in[0]), .A2(B_in[1]), .A3(n6), .B1(n9), .B2(n8), .B3(
B_in[2]), .ZN(A_out[0]) );
NAND2_X1 U4 ( .A1(B_in[2]), .A2(n9), .ZN(n7) );
INV_X1 U9 ( .A(B_in[2]), .ZN(n6) );
INV_X1 U3 ( .A(B_in[1]), .ZN(n8) );
INV_X1 U5 ( .A(B_in[0]), .ZN(n9) );
OAI221_X1 U7 ( .B1(B_in[1]), .B2(n9), .C1(n8), .C2(B_in[2]), .A(n7), .ZN(
A_out[2]) );
AOI21_X1 U8 ( .B1(B_in[0]), .B2(B_in[1]), .A(n6), .ZN(A_out[1]) );
endmodule
module booth_encoder_7 ( B_in, A_out );
input [2:0] B_in;
output [2:0] A_out;
wire n6, n7, n8, n9;
OAI33_X1 U6 ( .A1(B_in[0]), .A2(B_in[1]), .A3(n6), .B1(n9), .B2(n8), .B3(
B_in[2]), .ZN(A_out[0]) );
AOI21_X1 U5 ( .B1(B_in[0]), .B2(B_in[1]), .A(n6), .ZN(A_out[1]) );
INV_X1 U8 ( .A(B_in[0]), .ZN(n9) );
INV_X1 U7 ( .A(B_in[1]), .ZN(n8) );
INV_X1 U3 ( .A(B_in[2]), .ZN(n6) );
OAI221_X1 U4 ( .B1(B_in[1]), .B2(n9), .C1(n8), .C2(B_in[2]), .A(n7), .ZN(
A_out[2]) );
NAND2_X1 U9 ( .A1(B_in[2]), .A2(n9), .ZN(n7) );
endmodule
module booth_encoder_6 ( B_in, A_out );
input [2:0] B_in;
output [2:0] A_out;
wire n1, n5, n6, n7;
OAI33_X1 U6 ( .A1(B_in[0]), .A2(B_in[1]), .A3(n1), .B1(n7), .B2(n6), .B3(
B_in[2]), .ZN(A_out[0]) );
INV_X1 U3 ( .A(B_in[2]), .ZN(n1) );
INV_X1 U4 ( .A(B_in[1]), .ZN(n6) );
INV_X1 U5 ( .A(B_in[0]), .ZN(n7) );
NAND2_X1 U7 ( .A1(B_in[2]), .A2(n7), .ZN(n5) );
OAI221_X1 U8 ( .B1(B_in[1]), .B2(n7), .C1(n6), .C2(B_in[2]), .A(n5), .ZN(
A_out[2]) );
AOI21_X1 U9 ( .B1(B_in[0]), .B2(B_in[1]), .A(n1), .ZN(A_out[1]) );
endmodule
module booth_encoder_5 ( B_in, A_out );
input [2:0] B_in;
output [2:0] A_out;
wire n1, n5, n6, n7;
OAI33_X1 U6 ( .A1(B_in[0]), .A2(B_in[1]), .A3(n1), .B1(n7), .B2(n6), .B3(
B_in[2]), .ZN(A_out[0]) );
INV_X1 U7 ( .A(B_in[1]), .ZN(n6) );
INV_X1 U3 ( .A(B_in[2]), .ZN(n1) );
INV_X1 U4 ( .A(B_in[0]), .ZN(n7) );
AOI21_X1 U5 ( .B1(B_in[0]), .B2(B_in[1]), .A(n1), .ZN(A_out[1]) );
OAI221_X1 U8 ( .B1(B_in[1]), .B2(n7), .C1(n6), .C2(B_in[2]), .A(n5), .ZN(
A_out[2]) );
NAND2_X1 U9 ( .A1(B_in[2]), .A2(n7), .ZN(n5) );
endmodule
module booth_encoder_4 ( B_in, A_out );
input [2:0] B_in;
output [2:0] A_out;
wire n1, n5, n6, n7;
OAI33_X1 U6 ( .A1(B_in[0]), .A2(B_in[1]), .A3(n1), .B1(n7), .B2(n6), .B3(
B_in[2]), .ZN(A_out[0]) );
INV_X1 U3 ( .A(B_in[2]), .ZN(n1) );
INV_X1 U4 ( .A(B_in[1]), .ZN(n6) );
INV_X1 U5 ( .A(B_in[0]), .ZN(n7) );
OAI221_X1 U7 ( .B1(B_in[1]), .B2(n7), .C1(n6), .C2(B_in[2]), .A(n5), .ZN(
A_out[2]) );
NAND2_X1 U8 ( .A1(B_in[2]), .A2(n7), .ZN(n5) );
AOI21_X1 U9 ( .B1(B_in[0]), .B2(B_in[1]), .A(n1), .ZN(A_out[1]) );
endmodule
module booth_encoder_3 ( B_in, A_out );
input [2:0] B_in;
output [2:0] A_out;
wire n1, n5, n6, n7;
OAI33_X1 U6 ( .A1(B_in[0]), .A2(B_in[1]), .A3(n1), .B1(n7), .B2(n6), .B3(
B_in[2]), .ZN(A_out[0]) );
INV_X1 U3 ( .A(B_in[2]), .ZN(n1) );
INV_X1 U4 ( .A(B_in[1]), .ZN(n6) );
INV_X1 U5 ( .A(B_in[0]), .ZN(n7) );
AOI21_X1 U7 ( .B1(B_in[0]), .B2(B_in[1]), .A(n1), .ZN(A_out[1]) );
OAI221_X1 U8 ( .B1(B_in[1]), .B2(n7), .C1(n6), .C2(B_in[2]), .A(n5), .ZN(
A_out[2]) );
NAND2_X1 U9 ( .A1(B_in[2]), .A2(n7), .ZN(n5) );
endmodule
module booth_encoder_2 ( B_in, A_out );
input [2:0] B_in;
output [2:0] A_out;
wire n1, n5, n6, n7;
OAI33_X1 U6 ( .A1(B_in[0]), .A2(B_in[1]), .A3(n1), .B1(n7), .B2(n6), .B3(
B_in[2]), .ZN(A_out[0]) );
INV_X1 U7 ( .A(B_in[1]), .ZN(n6) );
INV_X1 U3 ( .A(B_in[0]), .ZN(n7) );
INV_X1 U4 ( .A(B_in[2]), .ZN(n1) );
NAND2_X1 U5 ( .A1(B_in[2]), .A2(n7), .ZN(n5) );
OAI221_X1 U8 ( .B1(B_in[1]), .B2(n7), .C1(n6), .C2(B_in[2]), .A(n5), .ZN(
A_out[2]) );
AOI21_X1 U9 ( .B1(B_in[0]), .B2(B_in[1]), .A(n1), .ZN(A_out[1]) );
endmodule
module booth_encoder_1 ( B_in, A_out );
input [2:0] B_in;
output [2:0] A_out;
wire n1, n4, n5;
OAI33_X1 U6 ( .A1(B_in[0]), .A2(B_in[1]), .A3(n4), .B1(n5), .B2(n4), .B3(
B_in[2]), .ZN(A_out[0]) );
NAND2_X1 U4 ( .A1(B_in[2]), .A2(n5), .ZN(n1) );
OAI221_X1 U3 ( .B1(B_in[1]), .B2(n5), .C1(n4), .C2(B_in[2]), .A(n1), .ZN(
A_out[2]) );
INV_X1 U5 ( .A(B_in[0]), .ZN(n5) );
INV_X1 U7 ( .A(B_in[1]), .ZN(n4) );
AOI21_X1 U8 ( .B1(B_in[0]), .B2(B_in[1]), .A(n4), .ZN(A_out[1]) );
endmodule
module carry_sel_gen_N4_15 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_30 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_29 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_15 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_14 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_28 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_27 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_14 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_13 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_26 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_25 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_13 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_12 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_24 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_23 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_12 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_11 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_22 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_21 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_11 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_10 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_20 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_19 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_10 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_9 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_18 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_17 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_9 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_8 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_16 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_15 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_8 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_7 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_14 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_13 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_7 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_6 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_12 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_11 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_6 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_5 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_10 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_9 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_5 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_4 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_8 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_7 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_4 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_3 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_6 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_5 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_3 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_2 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_4 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_3 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_2 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module carry_sel_gen_N4_1 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
wire [3:0] carry_sum_to_mux;
RCA_N4_2 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
RCA_N4_1 rca_carry ( .A(A), .B(B), .Ci(1'b1), .S(carry_sum_to_mux) );
mux21_SIZE4_1 outmux ( .IN0(nocarry_sum_to_mux), .IN1(carry_sum_to_mux),
.CTRL(Ci), .OUT1(S) );
endmodule
module pg_53 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_52 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_51 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_50 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_49 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_48 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_47 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1, n2;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(g), .ZN(n2) );
NAND2_X1 U3 ( .A1(p), .A2(g_prec), .ZN(n1) );
NAND2_X1 U4 ( .A1(n1), .A2(n2), .ZN(g_out) );
endmodule
module pg_46 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1, n2;
INV_X1 U1 ( .A(g), .ZN(n2) );
AND2_X1 U2 ( .A1(p_prec), .A2(p), .ZN(p_out) );
NAND2_X1 U3 ( .A1(g_prec), .A2(p), .ZN(n1) );
NAND2_X1 U4 ( .A1(n1), .A2(n2), .ZN(g_out) );
endmodule
module pg_45 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1, n2;
INV_X1 U1 ( .A(g), .ZN(n2) );
AND2_X1 U2 ( .A1(p), .A2(p_prec), .ZN(p_out) );
NAND2_X1 U3 ( .A1(p), .A2(g_prec), .ZN(n1) );
NAND2_X1 U4 ( .A1(n1), .A2(n2), .ZN(g_out) );
endmodule
module pg_44 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U1 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AND2_X1 U3 ( .A1(p_prec), .A2(p), .ZN(p_out) );
endmodule
module pg_43 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
AOI21_X1 U2 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
INV_X1 U3 ( .A(n1), .ZN(g_out) );
endmodule
module pg_42 ( g, p, g_prec, p_prec, p_out, g_out_BAR );
input g, p, g_prec, p_prec;
output p_out, g_out_BAR;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
AOI21_X1 U2 ( .B1(p), .B2(g_prec), .A(g), .ZN(g_out_BAR) );
endmodule
module pg_39 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_38 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_37 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_36 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1, n2;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(g), .ZN(n2) );
NAND2_X1 U3 ( .A1(n1), .A2(n2), .ZN(g_out) );
NAND2_X1 U4 ( .A1(g_prec), .A2(p), .ZN(n1) );
endmodule
module pg_35 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1, n2;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(g), .ZN(n2) );
NAND2_X1 U3 ( .A1(n1), .A2(n2), .ZN(g_out) );
NAND2_X1 U4 ( .A1(g_prec), .A2(p), .ZN(n1) );
endmodule
module pg_34 ( p, g_prec, p_prec, g_out, p_out, g_BAR );
input p, g_prec, p_prec, g_BAR;
output g_out, p_out;
wire g, n1;
assign g = g_BAR;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
NAND2_X1 U2 ( .A1(g_prec), .A2(p), .ZN(n1) );
NAND2_X1 U3 ( .A1(n1), .A2(g), .ZN(g_out) );
endmodule
module pg_32 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_31 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module pg_29 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1, n2;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(g), .ZN(n2) );
NAND2_X1 U3 ( .A1(n1), .A2(n2), .ZN(g_out) );
NAND2_X1 U4 ( .A1(g_prec), .A2(p), .ZN(n1) );
endmodule
module pg_27 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1, n2;
INV_X1 U1 ( .A(g), .ZN(n2) );
AND2_X1 U2 ( .A1(p_prec), .A2(p), .ZN(p_out) );
NAND2_X1 U3 ( .A1(p), .A2(g_prec), .ZN(n1) );
NAND2_X1 U4 ( .A1(n1), .A2(n2), .ZN(g_out) );
endmodule
module pg_26 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U1 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AND2_X1 U3 ( .A1(p), .A2(p_prec), .ZN(p_out) );
endmodule
module pg_25 ( g, p, g_prec, p_prec, p_out, g_out_BAR );
input g, p, g_prec, p_prec;
output p_out, g_out_BAR;
AND2_X1 U1 ( .A1(p_prec), .A2(p), .ZN(p_out) );
AOI21_X1 U2 ( .B1(p), .B2(g_prec), .A(g), .ZN(g_out_BAR) );
endmodule
module pg_24 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U1 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AND2_X1 U3 ( .A1(p), .A2(p_prec), .ZN(p_out) );
endmodule
module pg_23 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1, n2;
INV_X1 U1 ( .A(g), .ZN(n2) );
AND2_X1 U2 ( .A1(p), .A2(p_prec), .ZN(p_out) );
NAND2_X1 U3 ( .A1(p), .A2(g_prec), .ZN(n1) );
NAND2_X1 U4 ( .A1(n1), .A2(n2), .ZN(g_out) );
endmodule
module pg_22 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AND2_X1 U2 ( .A1(p), .A2(p_prec), .ZN(p_out) );
AOI21_X1 U3 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
endmodule
module pg_21 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AND2_X1 U2 ( .A1(p), .A2(p_prec), .ZN(p_out) );
AOI21_X1 U3 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
endmodule
module pg_20 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module pg_19 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AND2_X1 U2 ( .A1(p_prec), .A2(p), .ZN(p_out) );
AOI21_X1 U3 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
endmodule
module pg_18 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n3;
INV_X1 U1 ( .A(n3), .ZN(g_out) );
AND2_X1 U2 ( .A1(p), .A2(p_prec), .ZN(p_out) );
AOI21_X1 U3 ( .B1(p), .B2(g_prec), .A(g), .ZN(n3) );
endmodule
module pg_17 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AND2_X1 U2 ( .A1(p), .A2(p_prec), .ZN(p_out) );
AOI21_X1 U3 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
endmodule
module pg_16 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module pg_15 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module pg_14 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_13 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_12 ( p, g_prec, p_prec, g_out, p_out, g_BAR );
input p, g_prec, p_prec, g_BAR;
output g_out, p_out;
wire g, n1;
assign g = g_BAR;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
NAND2_X1 U2 ( .A1(g_prec), .A2(p), .ZN(n1) );
NAND2_X1 U3 ( .A1(n1), .A2(g), .ZN(g_out) );
endmodule
module pg_11 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AND2_X1 U2 ( .A1(p), .A2(p_prec), .ZN(p_out) );
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module pg_10 ( g, p, g_prec, p_prec, p_out, g_out_BAR );
input g, p, g_prec, p_prec;
output p_out, g_out_BAR;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
AOI21_X1 U2 ( .B1(g_prec), .B2(p), .A(g), .ZN(g_out_BAR) );
endmodule
module pg_9 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AOI21_X1 U3 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
endmodule
module pg_8 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AND2_X1 U2 ( .A1(p), .A2(p_prec), .ZN(p_out) );
AOI21_X1 U3 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
endmodule
module pg_7 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_6 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module pg_5 ( p, g_prec, p_prec, g_out, p_out, g_BAR );
input p, g_prec, p_prec, g_BAR;
output g_out, p_out;
wire g, n1;
assign g = g_BAR;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
NAND2_X1 U2 ( .A1(g_prec), .A2(p), .ZN(n1) );
NAND2_X1 U3 ( .A1(n1), .A2(g), .ZN(g_out) );
endmodule
module pg_4 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module pg_3 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module pg_2 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module pg_1 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module g_19 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
AOI21_X1 U2 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
INV_X1 U1 ( .A(n1), .ZN(g_out) );
endmodule
module g_18 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
AOI21_X1 U2 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
INV_X1 U1 ( .A(n1), .ZN(g_out) );
endmodule
module g_17 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
AOI21_X1 U2 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
INV_X1 U1 ( .A(n1), .ZN(g_out) );
endmodule
module g_16 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
AOI21_X1 U2 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
INV_X1 U1 ( .A(n1), .ZN(g_out) );
endmodule
module g_15 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
AOI21_X1 U2 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
INV_X1 U1 ( .A(n1), .ZN(g_out) );
endmodule
module g_14 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AOI21_X1 U2 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
endmodule
module g_13 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AOI21_X1 U2 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
endmodule
module g_12 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
OR2_X2 U1 ( .A1(g), .A2(n1), .ZN(g_out) );
AND2_X1 U2 ( .A1(p), .A2(g_prec), .ZN(n1) );
endmodule
module g_10 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n2, n3;
INV_X1 U1 ( .A(g), .ZN(n3) );
NAND2_X1 U2 ( .A1(n2), .A2(n3), .ZN(g_out) );
NAND2_X1 U3 ( .A1(p), .A2(g_prec), .ZN(n2) );
endmodule
module g_9 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1, n2;
INV_X1 U1 ( .A(g), .ZN(n2) );
NAND2_X1 U2 ( .A1(n1), .A2(n2), .ZN(g_out) );
NAND2_X1 U3 ( .A1(g_prec), .A2(p), .ZN(n1) );
endmodule
module g_8 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AOI21_X1 U2 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module g_7 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1, n2;
NAND2_X1 U1 ( .A1(n2), .A2(n1), .ZN(g_out) );
INV_X1 U2 ( .A(g), .ZN(n1) );
NAND2_X1 U3 ( .A1(g_prec), .A2(p), .ZN(n2) );
endmodule
module g_6 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
AOI21_X1 U1 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
INV_X1 U2 ( .A(n1), .ZN(g_out) );
endmodule
module g_5 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AOI21_X1 U2 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module g_4 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1, n2;
NAND2_X1 U1 ( .A1(n1), .A2(n2), .ZN(g_out) );
INV_X1 U2 ( .A(g), .ZN(n2) );
NAND2_X1 U3 ( .A1(g_prec), .A2(p), .ZN(n1) );
endmodule
module g_3 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AOI21_X1 U2 ( .B1(p), .B2(g_prec), .A(g), .ZN(n1) );
endmodule
module g_2 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire n1;
INV_X1 U1 ( .A(n1), .ZN(g_out) );
AOI21_X1 U2 ( .B1(g_prec), .B2(p), .A(g), .ZN(n1) );
endmodule
module g_1 ( g, p, g_prec, g_out_BAR );
input g, p, g_prec;
output g_out_BAR;
AOI21_X1 U1 ( .B1(p), .B2(g_prec), .A(g), .ZN(g_out_BAR) );
endmodule
module pg_net_63 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_62 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_61 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_60 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_59 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_58 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_57 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_56 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_55 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_54 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_53 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_52 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_51 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_50 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_49 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_48 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
INV_X1 U2 ( .A(a), .ZN(n1) );
XNOR2_X1 U3 ( .A(b), .B(n1), .ZN(p_out) );
endmodule
module pg_net_47 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
INV_X1 U2 ( .A(a), .ZN(n1) );
XNOR2_X1 U3 ( .A(b), .B(n1), .ZN(p_out) );
endmodule
module pg_net_46 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_45 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_44 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U1 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U2 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_43 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
INV_X1 U2 ( .A(a), .ZN(n1) );
XNOR2_X1 U3 ( .A(b), .B(n1), .ZN(p_out) );
endmodule
module pg_net_42 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
INV_X1 U2 ( .A(a), .ZN(n1) );
XNOR2_X1 U3 ( .A(b), .B(n1), .ZN(p_out) );
endmodule
module pg_net_41 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(a), .A2(b), .ZN(g_out) );
endmodule
module pg_net_40 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_39 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_38 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_33 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_32 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
wire n2, n3, n4, n5;
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
INV_X1 U2 ( .A(b), .ZN(n2) );
INV_X1 U3 ( .A(a), .ZN(n3) );
NAND2_X1 U4 ( .A1(n2), .A2(a), .ZN(n5) );
NAND2_X1 U5 ( .A1(b), .A2(n3), .ZN(n4) );
NAND2_X1 U6 ( .A1(n4), .A2(n5), .ZN(p_out) );
endmodule
module pg_net_31 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_30 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_29 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_28 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
XOR2_X1 U2 ( .A(a), .B(b), .Z(p_out) );
endmodule
module pg_net_27 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
wire n1;
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
INV_X1 U2 ( .A(a), .ZN(n1) );
XNOR2_X1 U3 ( .A(b), .B(n1), .ZN(p_out) );
endmodule
module pg_net_26 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_25 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(a), .A2(b), .ZN(g_out) );
endmodule
module pg_net_24 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_23 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_22 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_21 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_20 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_19 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_18 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_17 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_16 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_15 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_14 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_13 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_12 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_11 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_10 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_9 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_8 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_7 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_6 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_5 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_4 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_3 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_2 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module pg_net_1 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
wire n1;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
CLKBUF_X1 U1 ( .A(b), .Z(n1) );
AND2_X1 U3 ( .A1(n1), .A2(a), .ZN(g_out) );
endmodule
module sum_gen_N32_1 ( A, B, Cin, S );
input [31:0] A;
input [31:0] B;
input [8:0] Cin;
output [31:0] S;
carry_sel_gen_N4_8 csel_N_0 ( .A(A[3:0]), .B(B[3:0]), .Ci(Cin[0]), .S(S[3:0]) );
carry_sel_gen_N4_7 csel_N_1 ( .A(A[7:4]), .B(B[7:4]), .Ci(Cin[1]), .S(S[7:4]) );
carry_sel_gen_N4_6 csel_N_2 ( .A(A[11:8]), .B(B[11:8]), .Ci(Cin[2]), .S(
S[11:8]) );
carry_sel_gen_N4_5 csel_N_3 ( .A(A[15:12]), .B(B[15:12]), .Ci(Cin[3]), .S(
S[15:12]) );
carry_sel_gen_N4_4 csel_N_4 ( .A(A[19:16]), .B(B[19:16]), .Ci(Cin[4]), .S(
S[19:16]) );
carry_sel_gen_N4_3 csel_N_5 ( .A(A[23:20]), .B(B[23:20]), .Ci(Cin[5]), .S(
S[23:20]) );
carry_sel_gen_N4_2 csel_N_6 ( .A(A[27:24]), .B(B[27:24]), .Ci(Cin[6]), .S(
S[27:24]) );
carry_sel_gen_N4_1 csel_N_7 ( .A(A[31:28]), .B(B[31:28]), .Ci(Cin[7]), .S(
S[31:28]) );
endmodule
module carry_tree_N32_logN5_1 ( A, B, Cin, \Cout[7]_BAR , \Cout[6] , \Cout[5] ,
\Cout[4] , \Cout[3] , \Cout[2] , \Cout[1] , \Cout[0] );
input [31:0] A;
input [31:0] B;
input Cin;
output \Cout[7]_BAR , \Cout[6] , \Cout[5] , \Cout[4] , \Cout[3] , \Cout[2] ,
\Cout[1] , \Cout[0] ;
wire n7, n8, \pg_1[15][1] , \pg_1[15][0] , \pg_1[14][1] , \pg_1[14][0] ,
\pg_1[13][1] , \pg_1[13][0] , \pg_1[12][1] , \pg_1[12][0] ,
\pg_1[11][1] , \pg_1[11][0] , \pg_1[10][1] , \pg_1[10][0] ,
\pg_1[9][1] , \pg_1[9][0] , \pg_1[8][1] , \pg_1[8][0] , \pg_1[7][1] ,
\pg_1[7][0] , \pg_1[6][1] , \pg_1[6][0] , \pg_1[5][1] , \pg_1[5][0] ,
\pg_1[4][1] , \pg_1[4][0] , \pg_1[3][1] , \pg_1[3][0] , \pg_1[2][1] ,
\pg_1[2][0] , \pg_1[1][1] , \pg_1[1][0] , \pg_1[0][0] ,
\pg_n[4][7][1] , \pg_n[4][7][0] , \pg_n[4][6][1] , \pg_n[4][6][0] ,
\pg_n[3][7][1] , \pg_n[3][7][0] , \pg_n[3][5][1] , \pg_n[3][5][0] ,
\pg_n[3][3][1] , \pg_n[3][3][0] , \pg_n[2][7][1] , \pg_n[2][7][0] ,
\pg_n[2][6][1] , \pg_n[2][6][0] , \pg_n[2][5][1] , \pg_n[2][5][0] ,
\pg_n[2][4][1] , \pg_n[2][4][0] , \pg_n[2][3][1] , \pg_n[2][3][0] ,
\pg_n[2][2][1] , \pg_n[2][2][0] , \pg_n[2][1][1] , \pg_n[2][1][0] ,
n1, n4;
wire [7:0] Cout;
wire [31:1] p_net;
wire [31:0] g_net;
wire [1:0] magic_pro;
assign \Cout[7]_BAR = Cout[7];
pg_net_32 pg_net_x_1 ( .a(A[1]), .b(B[1]), .g_out(g_net[1]), .p_out(p_net[1]) );
pg_net_31 pg_net_x_2 ( .a(A[2]), .b(B[2]), .g_out(g_net[2]), .p_out(p_net[2]) );
pg_net_30 pg_net_x_3 ( .a(A[3]), .b(B[3]), .g_out(g_net[3]), .p_out(p_net[3]) );
pg_net_29 pg_net_x_4 ( .a(A[4]), .b(B[4]), .g_out(g_net[4]), .p_out(p_net[4]) );
pg_net_28 pg_net_x_5 ( .a(A[5]), .b(B[5]), .g_out(g_net[5]), .p_out(p_net[5]) );
pg_net_27 pg_net_x_6 ( .a(A[6]), .b(B[6]), .g_out(g_net[6]), .p_out(p_net[6]) );
pg_net_26 pg_net_x_7 ( .a(A[7]), .b(B[7]), .g_out(g_net[7]), .p_out(p_net[7]) );
pg_net_25 pg_net_x_8 ( .a(A[8]), .b(B[8]), .g_out(g_net[8]), .p_out(p_net[8]) );
pg_net_24 pg_net_x_9 ( .a(A[9]), .b(B[9]), .g_out(g_net[9]), .p_out(p_net[9]) );
pg_net_23 pg_net_x_10 ( .a(A[10]), .b(B[10]), .g_out(g_net[10]), .p_out(
p_net[10]) );
pg_net_22 pg_net_x_11 ( .a(A[11]), .b(B[11]), .g_out(g_net[11]), .p_out(
p_net[11]) );
pg_net_21 pg_net_x_12 ( .a(A[12]), .b(B[12]), .g_out(g_net[12]), .p_out(
p_net[12]) );
pg_net_20 pg_net_x_13 ( .a(A[13]), .b(B[13]), .g_out(g_net[13]), .p_out(
p_net[13]) );
pg_net_19 pg_net_x_14 ( .a(A[14]), .b(B[14]), .g_out(g_net[14]), .p_out(
p_net[14]) );
pg_net_18 pg_net_x_15 ( .a(A[15]), .b(B[15]), .g_out(g_net[15]), .p_out(
p_net[15]) );
pg_net_17 pg_net_x_16 ( .a(A[16]), .b(B[16]), .g_out(g_net[16]), .p_out(
p_net[16]) );
pg_net_16 pg_net_x_17 ( .a(A[17]), .b(B[17]), .g_out(g_net[17]), .p_out(
p_net[17]) );
pg_net_15 pg_net_x_18 ( .a(A[18]), .b(B[18]), .g_out(g_net[18]), .p_out(
p_net[18]) );
pg_net_14 pg_net_x_19 ( .a(A[19]), .b(B[19]), .g_out(g_net[19]), .p_out(
p_net[19]) );
pg_net_13 pg_net_x_20 ( .a(A[20]), .b(B[20]), .g_out(g_net[20]), .p_out(
p_net[20]) );
pg_net_12 pg_net_x_21 ( .a(A[21]), .b(B[21]), .g_out(g_net[21]), .p_out(n1)
);
pg_net_11 pg_net_x_22 ( .a(A[22]), .b(B[22]), .g_out(g_net[22]), .p_out(
p_net[22]) );
pg_net_10 pg_net_x_23 ( .a(A[23]), .b(B[23]), .g_out(g_net[23]), .p_out(
p_net[23]) );
pg_net_9 pg_net_x_24 ( .a(A[24]), .b(B[24]), .g_out(g_net[24]), .p_out(
p_net[24]) );
pg_net_8 pg_net_x_25 ( .a(A[25]), .b(B[25]), .g_out(g_net[25]), .p_out(
p_net[25]) );
pg_net_7 pg_net_x_26 ( .a(A[26]), .b(B[26]), .g_out(g_net[26]), .p_out(
p_net[26]) );
pg_net_6 pg_net_x_27 ( .a(A[27]), .b(B[27]), .g_out(g_net[27]), .p_out(
p_net[27]) );
pg_net_5 pg_net_x_28 ( .a(A[28]), .b(B[28]), .g_out(g_net[28]), .p_out(
p_net[28]) );
pg_net_4 pg_net_x_29 ( .a(A[29]), .b(B[29]), .g_out(g_net[29]), .p_out(
p_net[29]) );
pg_net_3 pg_net_x_30 ( .a(A[30]), .b(B[30]), .g_out(g_net[30]), .p_out(
p_net[30]) );
pg_net_2 pg_net_x_31 ( .a(A[31]), .b(B[31]), .g_out(g_net[31]), .p_out(
p_net[31]) );
pg_net_1 pg_net_0_MAGIC ( .a(A[0]), .b(B[0]), .g_out(magic_pro[0]), .p_out(
magic_pro[1]) );
g_10 xG_0_0_MAGIC ( .g(magic_pro[0]), .p(magic_pro[1]), .g_prec(Cin),
.g_out(g_net[0]) );
g_9 xG_1_0 ( .g(g_net[1]), .p(p_net[1]), .g_prec(g_net[0]), .g_out(
\pg_1[0][0] ) );
pg_27 xPG_1_1 ( .g(g_net[3]), .p(p_net[3]), .g_prec(g_net[2]), .p_prec(
p_net[2]), .g_out(\pg_1[1][0] ), .p_out(\pg_1[1][1] ) );
pg_26 xPG_1_2 ( .g(g_net[5]), .p(p_net[5]), .g_prec(g_net[4]), .p_prec(
p_net[4]), .g_out(\pg_1[2][0] ), .p_out(\pg_1[2][1] ) );
pg_25 xPG_1_3 ( .g(g_net[7]), .p(p_net[7]), .g_prec(g_net[6]), .p_prec(
p_net[6]), .p_out(\pg_1[3][1] ), .g_out_BAR(\pg_1[3][0] ) );
pg_24 xPG_1_4 ( .g(g_net[9]), .p(p_net[9]), .g_prec(g_net[8]), .p_prec(
p_net[8]), .g_out(\pg_1[4][0] ), .p_out(\pg_1[4][1] ) );
pg_23 xPG_1_5 ( .g(g_net[11]), .p(p_net[11]), .g_prec(g_net[10]), .p_prec(
p_net[10]), .g_out(\pg_1[5][0] ), .p_out(\pg_1[5][1] ) );
pg_22 xPG_1_6 ( .g(g_net[13]), .p(p_net[13]), .g_prec(g_net[12]), .p_prec(
p_net[12]), .g_out(\pg_1[6][0] ), .p_out(\pg_1[6][1] ) );
pg_21 xPG_1_7 ( .g(g_net[15]), .p(p_net[15]), .g_prec(g_net[14]), .p_prec(
p_net[14]), .g_out(\pg_1[7][0] ), .p_out(\pg_1[7][1] ) );
pg_20 xPG_1_8 ( .g(g_net[17]), .p(p_net[17]), .g_prec(g_net[16]), .p_prec(
p_net[16]), .g_out(\pg_1[8][0] ), .p_out(\pg_1[8][1] ) );
pg_19 xPG_1_9 ( .g(g_net[19]), .p(p_net[19]), .g_prec(g_net[18]), .p_prec(
p_net[18]), .g_out(\pg_1[9][0] ), .p_out(\pg_1[9][1] ) );
pg_18 xPG_1_10 ( .g(g_net[21]), .p(n1), .g_prec(g_net[20]), .p_prec(
p_net[20]), .g_out(\pg_1[10][0] ), .p_out(\pg_1[10][1] ) );
pg_17 xPG_1_11 ( .g(g_net[23]), .p(p_net[23]), .g_prec(g_net[22]), .p_prec(
p_net[22]), .g_out(\pg_1[11][0] ), .p_out(\pg_1[11][1] ) );
pg_16 xPG_1_12 ( .g(g_net[25]), .p(p_net[25]), .g_prec(g_net[24]), .p_prec(
p_net[24]), .g_out(\pg_1[12][0] ), .p_out(\pg_1[12][1] ) );
pg_15 xPG_1_13 ( .g(g_net[27]), .p(p_net[27]), .g_prec(g_net[26]), .p_prec(
p_net[26]), .g_out(\pg_1[13][0] ), .p_out(\pg_1[13][1] ) );
pg_14 xPG_1_14 ( .g(g_net[29]), .p(p_net[29]), .g_prec(g_net[28]), .p_prec(
p_net[28]), .g_out(\pg_1[14][0] ), .p_out(\pg_1[14][1] ) );
pg_13 xPG_1_15 ( .g(g_net[31]), .p(p_net[31]), .g_prec(g_net[30]), .p_prec(
p_net[30]), .g_out(\pg_1[15][0] ), .p_out(\pg_1[15][1] ) );
g_8 xG_2_0 ( .g(\pg_1[1][0] ), .p(\pg_1[1][1] ), .g_prec(\pg_1[0][0] ),
.g_out(\Cout[0] [0]) );
pg_12 xPG_2_1 ( .p(\pg_1[3][1] ), .g_prec(\pg_1[2][0] ), .p_prec(
\pg_1[2][1] ), .g_out(\pg_n[2][1][0] ), .p_out(\pg_n[2][1][1] ),
.g_BAR(\pg_1[3][0] ) );
pg_11 xPG_2_2 ( .g(\pg_1[5][0] ), .p(\pg_1[5][1] ), .g_prec(\pg_1[4][0] ),
.p_prec(\pg_1[4][1] ), .g_out(\pg_n[2][2][0] ), .p_out(\pg_n[2][2][1] ) );
pg_10 xPG_2_3 ( .g(\pg_1[7][0] ), .p(\pg_1[7][1] ), .g_prec(\pg_1[6][0] ),
.p_prec(\pg_1[6][1] ), .p_out(\pg_n[2][3][1] ), .g_out_BAR(
\pg_n[2][3][0] ) );
pg_9 xPG_2_4 ( .g(\pg_1[9][0] ), .p(\pg_1[9][1] ), .g_prec(\pg_1[8][0] ),
.p_prec(\pg_1[8][1] ), .g_out(\pg_n[2][4][0] ), .p_out(\pg_n[2][4][1] ) );
pg_8 xPG_2_5 ( .g(\pg_1[11][0] ), .p(\pg_1[11][1] ), .g_prec(\pg_1[10][0] ),
.p_prec(\pg_1[10][1] ), .g_out(\pg_n[2][5][0] ), .p_out(
\pg_n[2][5][1] ) );
pg_7 xPG_2_6 ( .g(\pg_1[13][0] ), .p(\pg_1[13][1] ), .g_prec(\pg_1[12][0] ),
.p_prec(\pg_1[12][1] ), .g_out(\pg_n[2][6][0] ), .p_out(
\pg_n[2][6][1] ) );
pg_6 xPG_2_7 ( .g(\pg_1[15][0] ), .p(\pg_1[15][1] ), .g_prec(\pg_1[14][0] ),
.p_prec(\pg_1[14][1] ), .g_out(\pg_n[2][7][0] ), .p_out(
\pg_n[2][7][1] ) );
g_7 xG_3_1 ( .g(\pg_n[2][1][0] ), .p(\pg_n[2][1][1] ), .g_prec(\Cout[0] [0]),
.g_out(n8) );
g_6 xG_4_2 ( .g(\pg_n[2][2][0] ), .p(\pg_n[2][2][1] ), .g_prec(\Cout[1] [1]),
.g_out(\Cout[2] [2]) );
g_5 xG_4_3 ( .g(\pg_n[3][3][0] ), .p(\pg_n[3][3][1] ), .g_prec(n8), .g_out(
n7) );
g_4 xG_5_4 ( .g(\pg_n[2][4][0] ), .p(\pg_n[2][4][1] ), .g_prec(n7), .g_out(
\Cout[4] [4]) );
g_3 xG_5_5 ( .g(n4), .p(\pg_n[3][5][1] ), .g_prec(n7), .g_out(\Cout[5] [5])
);
g_2 xG_5_6 ( .g(\pg_n[4][6][0] ), .p(\pg_n[4][6][1] ), .g_prec(n7), .g_out(
\Cout[6] [6]) );
g_1 xG_5_7 ( .g(\pg_n[4][7][0] ), .p(\pg_n[4][7][1] ), .g_prec(\Cout[3] [3]),
.g_out_BAR(Cout[7]) );
pg_5 xPG_3_3 ( .p(\pg_n[2][3][1] ), .g_prec(\pg_n[2][2][0] ), .p_prec(
\pg_n[2][2][1] ), .g_out(\pg_n[3][3][0] ), .p_out(\pg_n[3][3][1] ),
.g_BAR(\pg_n[2][3][0] ) );
pg_4 xPG_3_5 ( .g(\pg_n[2][5][0] ), .p(\pg_n[2][5][1] ), .g_prec(
\pg_n[2][4][0] ), .p_prec(\pg_n[2][4][1] ), .g_out(\pg_n[3][5][0] ),
.p_out(\pg_n[3][5][1] ) );
pg_3 xPG_3_7 ( .g(\pg_n[2][7][0] ), .p(\pg_n[2][7][1] ), .g_prec(
\pg_n[2][6][0] ), .p_prec(\pg_n[2][6][1] ), .g_out(\pg_n[3][7][0] ),
.p_out(\pg_n[3][7][1] ) );
pg_2 xPG_4_6 ( .g(\pg_n[2][6][0] ), .p(\pg_n[2][6][1] ), .g_prec(
\pg_n[3][5][0] ), .p_prec(\pg_n[3][5][1] ), .g_out(\pg_n[4][6][0] ),
.p_out(\pg_n[4][6][1] ) );
pg_1 xPG_4_7 ( .g(\pg_n[3][7][0] ), .p(\pg_n[3][7][1] ), .g_prec(n4),
.p_prec(\pg_n[3][5][1] ), .g_out(\pg_n[4][7][0] ), .p_out(
\pg_n[4][7][1] ) );
CLKBUF_X2 U1 ( .A(n8), .Z(\Cout[1] [1]) );
BUF_X1 U2 ( .A(n7), .Z(\Cout[3] [3]) );
CLKBUF_X1 U3 ( .A(\pg_n[3][5][0] ), .Z(n4) );
endmodule
module xor_gen_N32_1 ( A, B, S );
input [31:0] A;
output [31:0] S;
input B;
wire n2, n3, n4, n5;
XOR2_X1 U8 ( .A(B), .B(A[31]), .Z(S[31]) );
XOR2_X1 U9 ( .A(B), .B(A[30]), .Z(S[30]) );
XOR2_X1 U11 ( .A(B), .B(A[29]), .Z(S[29]) );
XOR2_X1 U13 ( .A(B), .B(A[27]), .Z(S[27]) );
XOR2_X1 U14 ( .A(B), .B(A[26]), .Z(S[26]) );
XOR2_X1 U16 ( .A(B), .B(A[24]), .Z(S[24]) );
XOR2_X1 U20 ( .A(B), .B(A[20]), .Z(S[20]) );
XOR2_X1 U22 ( .A(B), .B(A[19]), .Z(S[19]) );
XOR2_X1 U25 ( .A(B), .B(A[16]), .Z(S[16]) );
XOR2_X1 U26 ( .A(B), .B(A[15]), .Z(S[15]) );
XOR2_X1 U30 ( .A(B), .B(A[11]), .Z(S[11]) );
XOR2_X1 U32 ( .A(B), .B(A[0]), .Z(S[0]) );
MUX2_X1 U1 ( .A(B), .B(n2), .S(A[23]), .Z(S[23]) );
XOR2_X1 U2 ( .A(B), .B(A[5]), .Z(S[5]) );
MUX2_X1 U3 ( .A(B), .B(n2), .S(A[10]), .Z(S[10]) );
MUX2_X1 U4 ( .A(B), .B(n2), .S(A[6]), .Z(S[6]) );
XNOR2_X1 U5 ( .A(A[3]), .B(n2), .ZN(S[3]) );
XOR2_X1 U6 ( .A(B), .B(A[13]), .Z(S[13]) );
MUX2_X1 U7 ( .A(B), .B(n2), .S(A[7]), .Z(S[7]) );
XOR2_X2 U10 ( .A(A[2]), .B(B), .Z(S[2]) );
XOR2_X2 U12 ( .A(A[1]), .B(B), .Z(S[1]) );
NAND2_X1 U15 ( .A1(n4), .A2(n5), .ZN(S[21]) );
INV_X1 U17 ( .A(A[21]), .ZN(n3) );
XOR2_X1 U18 ( .A(A[8]), .B(B), .Z(S[8]) );
XOR2_X1 U19 ( .A(B), .B(A[4]), .Z(S[4]) );
INV_X1 U21 ( .A(B), .ZN(n2) );
XOR2_X1 U23 ( .A(B), .B(A[12]), .Z(S[12]) );
XOR2_X1 U24 ( .A(B), .B(A[18]), .Z(S[18]) );
XOR2_X1 U27 ( .A(B), .B(A[25]), .Z(S[25]) );
XOR2_X1 U28 ( .A(B), .B(A[28]), .Z(S[28]) );
XOR2_X1 U29 ( .A(B), .B(A[22]), .Z(S[22]) );
XOR2_X1 U31 ( .A(B), .B(A[17]), .Z(S[17]) );
XOR2_X1 U33 ( .A(B), .B(A[14]), .Z(S[14]) );
XOR2_X1 U34 ( .A(B), .B(A[9]), .Z(S[9]) );
NAND2_X1 U35 ( .A1(B), .A2(n3), .ZN(n4) );
NAND2_X1 U36 ( .A1(n2), .A2(A[21]), .ZN(n5) );
endmodule
module ff32_en_SIZE5_3 ( D, en, clk, rst, Q );
input [4:0] D;
output [4:0] Q;
input en, clk, rst;
wire net3361, n5;
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(net3361), .RN(n5), .Q(Q[4]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(net3361), .RN(n5), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(net3361), .RN(n5), .Q(Q[1]) );
SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE5_3 clk_gate_Q_reg ( .CLK(clk), .EN(en),
.ENCLK(net3361) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(net3361), .RN(n5), .Q(Q[3]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(net3361), .RN(n5), .Q(Q[0]) );
INV_X1 U2 ( .A(rst), .ZN(n5) );
endmodule
module ff32_en_SIZE5_2 ( D, en, clk, rst, Q );
input [4:0] D;
output [4:0] Q;
input en, clk, rst;
wire net3361, n5;
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(net3361), .RN(n5), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(net3361), .RN(n5), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(net3361), .RN(n5), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(net3361), .RN(n5), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(net3361), .RN(n5), .Q(Q[0]) );
SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE5_2 clk_gate_Q_reg ( .CLK(clk), .EN(en),
.ENCLK(net3361) );
INV_X1 U2 ( .A(rst), .ZN(n5) );
endmodule
module ff32_en_SIZE5_1 ( D, en, clk, rst, Q );
input [4:0] D;
output [4:0] Q;
input en, clk, rst;
wire n6;
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(clk), .RN(n6), .Q(Q[3]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(clk), .RN(n6), .Q(Q[1]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(clk), .RN(n6), .Q(Q[2]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(clk), .RN(n6), .Q(Q[0]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(clk), .RN(n6), .Q(Q[4]) );
INV_X1 U2 ( .A(rst), .ZN(n6) );
endmodule
module ff32_en_SIZE32_5 ( D, en, clk, rst, Q );
input [31:0] D;
output [31:0] Q;
input en, clk, rst;
wire net3346, n32;
DFFR_X1 \Q_reg[31] ( .D(D[31]), .CK(net3346), .RN(n32), .Q(Q[31]) );
DFFR_X1 \Q_reg[30] ( .D(D[30]), .CK(net3346), .RN(n32), .Q(Q[30]) );
DFFR_X1 \Q_reg[29] ( .D(D[29]), .CK(net3346), .RN(n32), .Q(Q[29]) );
DFFR_X1 \Q_reg[28] ( .D(D[28]), .CK(net3346), .RN(n32), .Q(Q[28]) );
DFFR_X1 \Q_reg[27] ( .D(D[27]), .CK(net3346), .RN(n32), .Q(Q[27]) );
DFFR_X1 \Q_reg[26] ( .D(D[26]), .CK(net3346), .RN(n32), .Q(Q[26]) );
DFFR_X1 \Q_reg[25] ( .D(D[25]), .CK(net3346), .RN(n32), .Q(Q[25]) );
DFFR_X1 \Q_reg[24] ( .D(D[24]), .CK(net3346), .RN(n32), .Q(Q[24]) );
DFFR_X1 \Q_reg[23] ( .D(D[23]), .CK(net3346), .RN(n32), .Q(Q[23]) );
DFFR_X1 \Q_reg[22] ( .D(D[22]), .CK(net3346), .RN(n32), .Q(Q[22]) );
DFFR_X1 \Q_reg[21] ( .D(D[21]), .CK(net3346), .RN(n32), .Q(Q[21]) );
DFFR_X1 \Q_reg[20] ( .D(D[20]), .CK(net3346), .RN(n32), .Q(Q[20]) );
DFFR_X1 \Q_reg[19] ( .D(D[19]), .CK(net3346), .RN(n32), .Q(Q[19]) );
DFFR_X1 \Q_reg[18] ( .D(D[18]), .CK(net3346), .RN(n32), .Q(Q[18]) );
DFFR_X1 \Q_reg[17] ( .D(D[17]), .CK(net3346), .RN(n32), .Q(Q[17]) );
DFFR_X1 \Q_reg[16] ( .D(D[16]), .CK(net3346), .RN(n32), .Q(Q[16]) );
DFFR_X1 \Q_reg[15] ( .D(D[15]), .CK(net3346), .RN(n32), .Q(Q[15]) );
DFFR_X1 \Q_reg[14] ( .D(D[14]), .CK(net3346), .RN(n32), .Q(Q[14]) );
DFFR_X1 \Q_reg[13] ( .D(D[13]), .CK(net3346), .RN(n32), .Q(Q[13]) );
DFFR_X1 \Q_reg[12] ( .D(D[12]), .CK(net3346), .RN(n32), .Q(Q[12]) );
DFFR_X1 \Q_reg[11] ( .D(D[11]), .CK(net3346), .RN(n32), .Q(Q[11]) );
DFFR_X1 \Q_reg[10] ( .D(D[10]), .CK(net3346), .RN(n32), .Q(Q[10]) );
DFFR_X1 \Q_reg[9] ( .D(D[9]), .CK(net3346), .RN(n32), .Q(Q[9]) );
DFFR_X1 \Q_reg[8] ( .D(D[8]), .CK(net3346), .RN(n32), .Q(Q[8]) );
DFFR_X1 \Q_reg[7] ( .D(D[7]), .CK(net3346), .RN(n32), .Q(Q[7]) );
DFFR_X1 \Q_reg[6] ( .D(D[6]), .CK(net3346), .RN(n32), .Q(Q[6]) );
DFFR_X1 \Q_reg[5] ( .D(D[5]), .CK(net3346), .RN(n32), .Q(Q[5]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(net3346), .RN(n32), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(net3346), .RN(n32), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(net3346), .RN(n32), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(net3346), .RN(n32), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(net3346), .RN(n32), .Q(Q[0]) );
SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE32_5 clk_gate_Q_reg ( .CLK(clk), .EN(en),
.ENCLK(net3346) );
INV_X2 U2 ( .A(rst), .ZN(n32) );
endmodule
module ff32_en_SIZE32_4 ( D, en, clk, rst, Q );
input [31:0] D;
output [31:0] Q;
input en, clk, rst;
wire net3346, n32;
DFFR_X1 \Q_reg[31] ( .D(D[31]), .CK(net3346), .RN(n32), .Q(Q[31]) );
DFFR_X1 \Q_reg[30] ( .D(D[30]), .CK(net3346), .RN(n32), .Q(Q[30]) );
DFFR_X1 \Q_reg[29] ( .D(D[29]), .CK(net3346), .RN(n32), .Q(Q[29]) );
DFFR_X1 \Q_reg[28] ( .D(D[28]), .CK(net3346), .RN(n32), .Q(Q[28]) );
DFFR_X1 \Q_reg[27] ( .D(D[27]), .CK(net3346), .RN(n32), .Q(Q[27]) );
DFFR_X1 \Q_reg[26] ( .D(D[26]), .CK(net3346), .RN(n32), .Q(Q[26]) );
DFFR_X1 \Q_reg[25] ( .D(D[25]), .CK(net3346), .RN(n32), .Q(Q[25]) );
DFFR_X1 \Q_reg[24] ( .D(D[24]), .CK(net3346), .RN(n32), .Q(Q[24]) );
DFFR_X1 \Q_reg[23] ( .D(D[23]), .CK(net3346), .RN(n32), .Q(Q[23]) );
DFFR_X1 \Q_reg[22] ( .D(D[22]), .CK(net3346), .RN(n32), .Q(Q[22]) );
DFFR_X1 \Q_reg[21] ( .D(D[21]), .CK(net3346), .RN(n32), .Q(Q[21]) );
DFFR_X1 \Q_reg[20] ( .D(D[20]), .CK(net3346), .RN(n32), .Q(Q[20]) );
DFFR_X1 \Q_reg[19] ( .D(D[19]), .CK(net3346), .RN(n32), .Q(Q[19]) );
DFFR_X1 \Q_reg[18] ( .D(D[18]), .CK(net3346), .RN(n32), .Q(Q[18]) );
DFFR_X1 \Q_reg[17] ( .D(D[17]), .CK(net3346), .RN(n32), .Q(Q[17]) );
DFFR_X1 \Q_reg[16] ( .D(D[16]), .CK(net3346), .RN(n32), .Q(Q[16]) );
DFFR_X1 \Q_reg[15] ( .D(D[15]), .CK(net3346), .RN(n32), .Q(Q[15]) );
DFFR_X1 \Q_reg[14] ( .D(D[14]), .CK(net3346), .RN(n32), .Q(Q[14]) );
DFFR_X1 \Q_reg[13] ( .D(D[13]), .CK(net3346), .RN(n32), .Q(Q[13]) );
DFFR_X1 \Q_reg[12] ( .D(D[12]), .CK(net3346), .RN(n32), .Q(Q[12]) );
DFFR_X1 \Q_reg[11] ( .D(D[11]), .CK(net3346), .RN(n32), .Q(Q[11]) );
DFFR_X1 \Q_reg[10] ( .D(D[10]), .CK(net3346), .RN(n32), .Q(Q[10]) );
DFFR_X1 \Q_reg[9] ( .D(D[9]), .CK(net3346), .RN(n32), .Q(Q[9]) );
DFFR_X1 \Q_reg[8] ( .D(D[8]), .CK(net3346), .RN(n32), .Q(Q[8]) );
DFFR_X1 \Q_reg[7] ( .D(D[7]), .CK(net3346), .RN(n32), .Q(Q[7]) );
DFFR_X1 \Q_reg[6] ( .D(D[6]), .CK(net3346), .RN(n32), .Q(Q[6]) );
DFFR_X1 \Q_reg[5] ( .D(D[5]), .CK(net3346), .RN(n32), .Q(Q[5]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(net3346), .RN(n32), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(net3346), .RN(n32), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(net3346), .RN(n32), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(net3346), .RN(n32), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(net3346), .RN(n32), .Q(Q[0]) );
SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE32_4 clk_gate_Q_reg ( .CLK(clk), .EN(en),
.ENCLK(net3346) );
INV_X2 U2 ( .A(rst), .ZN(n32) );
endmodule
module ff32_en_SIZE32_3 ( D, en, clk, rst, Q );
input [31:0] D;
output [31:0] Q;
input en, clk, rst;
wire n32;
DFFR_X1 \Q_reg[31] ( .D(D[31]), .CK(clk), .RN(n32), .Q(Q[31]) );
DFFR_X1 \Q_reg[30] ( .D(D[30]), .CK(clk), .RN(n32), .Q(Q[30]) );
DFFR_X1 \Q_reg[29] ( .D(D[29]), .CK(clk), .RN(n32), .Q(Q[29]) );
DFFR_X1 \Q_reg[28] ( .D(D[28]), .CK(clk), .RN(n32), .Q(Q[28]) );
DFFR_X1 \Q_reg[27] ( .D(D[27]), .CK(clk), .RN(n32), .Q(Q[27]) );
DFFR_X1 \Q_reg[26] ( .D(D[26]), .CK(clk), .RN(n32), .Q(Q[26]) );
DFFR_X1 \Q_reg[25] ( .D(D[25]), .CK(clk), .RN(n32), .Q(Q[25]) );
DFFR_X1 \Q_reg[24] ( .D(D[24]), .CK(clk), .RN(n32), .Q(Q[24]) );
DFFR_X1 \Q_reg[23] ( .D(D[23]), .CK(clk), .RN(n32), .Q(Q[23]) );
DFFR_X1 \Q_reg[22] ( .D(D[22]), .CK(clk), .RN(n32), .Q(Q[22]) );
DFFR_X1 \Q_reg[21] ( .D(D[21]), .CK(clk), .RN(n32), .Q(Q[21]) );
DFFR_X1 \Q_reg[20] ( .D(D[20]), .CK(clk), .RN(n32), .Q(Q[20]) );
DFFR_X1 \Q_reg[19] ( .D(D[19]), .CK(clk), .RN(n32), .Q(Q[19]) );
DFFR_X1 \Q_reg[18] ( .D(D[18]), .CK(clk), .RN(n32), .Q(Q[18]) );
DFFR_X1 \Q_reg[17] ( .D(D[17]), .CK(clk), .RN(n32), .Q(Q[17]) );
DFFR_X1 \Q_reg[16] ( .D(D[16]), .CK(clk), .RN(n32), .Q(Q[16]) );
DFFR_X1 \Q_reg[15] ( .D(D[15]), .CK(clk), .RN(n32), .Q(Q[15]) );
DFFR_X1 \Q_reg[14] ( .D(D[14]), .CK(clk), .RN(n32), .Q(Q[14]) );
DFFR_X1 \Q_reg[13] ( .D(D[13]), .CK(clk), .RN(n32), .Q(Q[13]) );
DFFR_X1 \Q_reg[12] ( .D(D[12]), .CK(clk), .RN(n32), .Q(Q[12]) );
DFFR_X1 \Q_reg[11] ( .D(D[11]), .CK(clk), .RN(n32), .Q(Q[11]) );
DFFR_X1 \Q_reg[10] ( .D(D[10]), .CK(clk), .RN(n32), .Q(Q[10]) );
DFFR_X1 \Q_reg[9] ( .D(D[9]), .CK(clk), .RN(n32), .Q(Q[9]) );
DFFR_X1 \Q_reg[8] ( .D(D[8]), .CK(clk), .RN(n32), .Q(Q[8]) );
DFFR_X1 \Q_reg[7] ( .D(D[7]), .CK(clk), .RN(n32), .Q(Q[7]) );
DFFR_X1 \Q_reg[6] ( .D(D[6]), .CK(clk), .RN(n32), .Q(Q[6]) );
DFFR_X1 \Q_reg[5] ( .D(D[5]), .CK(clk), .RN(n32), .Q(Q[5]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(clk), .RN(n32), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(clk), .RN(n32), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(clk), .RN(n32), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(clk), .RN(n32), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(clk), .RN(n32), .Q(Q[0]) );
INV_X2 U2 ( .A(rst), .ZN(n32) );
endmodule
module ff32_en_SIZE32_2 ( D, en, clk, rst, Q );
input [31:0] D;
output [31:0] Q;
input en, clk, rst;
wire n34;
DFFR_X1 \Q_reg[31] ( .D(D[31]), .CK(clk), .RN(n34), .Q(Q[31]) );
DFFR_X1 \Q_reg[30] ( .D(D[30]), .CK(clk), .RN(n34), .Q(Q[30]) );
DFFR_X1 \Q_reg[29] ( .D(D[29]), .CK(clk), .RN(n34), .Q(Q[29]) );
DFFR_X1 \Q_reg[28] ( .D(D[28]), .CK(clk), .RN(n34), .Q(Q[28]) );
DFFR_X1 \Q_reg[27] ( .D(D[27]), .CK(clk), .RN(n34), .Q(Q[27]) );
DFFR_X1 \Q_reg[26] ( .D(D[26]), .CK(clk), .RN(n34), .Q(Q[26]) );
DFFR_X1 \Q_reg[25] ( .D(D[25]), .CK(clk), .RN(n34), .Q(Q[25]) );
DFFR_X1 \Q_reg[24] ( .D(D[24]), .CK(clk), .RN(n34), .Q(Q[24]) );
DFFR_X1 \Q_reg[23] ( .D(D[23]), .CK(clk), .RN(n34), .Q(Q[23]) );
DFFR_X1 \Q_reg[22] ( .D(D[22]), .CK(clk), .RN(n34), .Q(Q[22]) );
DFFR_X1 \Q_reg[21] ( .D(D[21]), .CK(clk), .RN(n34), .Q(Q[21]) );
DFFR_X1 \Q_reg[20] ( .D(D[20]), .CK(clk), .RN(n34), .Q(Q[20]) );
DFFR_X1 \Q_reg[19] ( .D(D[19]), .CK(clk), .RN(n34), .Q(Q[19]) );
DFFR_X1 \Q_reg[18] ( .D(D[18]), .CK(clk), .RN(n34), .Q(Q[18]) );
DFFR_X1 \Q_reg[17] ( .D(D[17]), .CK(clk), .RN(n34), .Q(Q[17]) );
DFFR_X1 \Q_reg[16] ( .D(D[16]), .CK(clk), .RN(n34), .Q(Q[16]) );
DFFR_X1 \Q_reg[15] ( .D(D[15]), .CK(clk), .RN(n34), .Q(Q[15]) );
DFFR_X1 \Q_reg[14] ( .D(D[14]), .CK(clk), .RN(n34), .Q(Q[14]) );
DFFR_X1 \Q_reg[13] ( .D(D[13]), .CK(clk), .RN(n34), .Q(Q[13]) );
DFFR_X1 \Q_reg[12] ( .D(D[12]), .CK(clk), .RN(n34), .Q(Q[12]) );
DFFR_X1 \Q_reg[11] ( .D(D[11]), .CK(clk), .RN(n34), .Q(Q[11]) );
DFFR_X1 \Q_reg[10] ( .D(D[10]), .CK(clk), .RN(n34), .Q(Q[10]) );
DFFR_X1 \Q_reg[9] ( .D(D[9]), .CK(clk), .RN(n34), .Q(Q[9]) );
DFFR_X1 \Q_reg[8] ( .D(D[8]), .CK(clk), .RN(n34), .Q(Q[8]) );
DFFR_X1 \Q_reg[7] ( .D(D[7]), .CK(clk), .RN(n34), .Q(Q[7]) );
DFFR_X1 \Q_reg[6] ( .D(D[6]), .CK(clk), .RN(n34), .Q(Q[6]) );
DFFR_X1 \Q_reg[5] ( .D(D[5]), .CK(clk), .RN(n34), .Q(Q[5]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(clk), .RN(n34), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(clk), .RN(n34), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(clk), .RN(n34), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(clk), .RN(n34), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(clk), .RN(n34), .Q(Q[0]) );
INV_X2 U2 ( .A(rst), .ZN(n34) );
endmodule
module ff32_en_SIZE32_1 ( D, en, clk, rst, Q );
input [31:0] D;
output [31:0] Q;
input en, clk, rst;
wire net3346, n32;
DFFR_X1 \Q_reg[31] ( .D(D[31]), .CK(net3346), .RN(n32), .Q(Q[31]) );
DFFR_X1 \Q_reg[30] ( .D(D[30]), .CK(net3346), .RN(n32), .Q(Q[30]) );
DFFR_X1 \Q_reg[29] ( .D(D[29]), .CK(net3346), .RN(n32), .Q(Q[29]) );
DFFR_X1 \Q_reg[28] ( .D(D[28]), .CK(net3346), .RN(n32), .Q(Q[28]) );
DFFR_X1 \Q_reg[27] ( .D(D[27]), .CK(net3346), .RN(n32), .Q(Q[27]) );
DFFR_X1 \Q_reg[26] ( .D(D[26]), .CK(net3346), .RN(n32), .Q(Q[26]) );
DFFR_X1 \Q_reg[25] ( .D(D[25]), .CK(net3346), .RN(n32), .Q(Q[25]) );
DFFR_X1 \Q_reg[24] ( .D(D[24]), .CK(net3346), .RN(n32), .Q(Q[24]) );
DFFR_X1 \Q_reg[23] ( .D(D[23]), .CK(net3346), .RN(n32), .Q(Q[23]) );
DFFR_X1 \Q_reg[22] ( .D(D[22]), .CK(net3346), .RN(n32), .Q(Q[22]) );
DFFR_X1 \Q_reg[21] ( .D(D[21]), .CK(net3346), .RN(n32), .Q(Q[21]) );
DFFR_X1 \Q_reg[20] ( .D(D[20]), .CK(net3346), .RN(n32), .Q(Q[20]) );
DFFR_X1 \Q_reg[19] ( .D(D[19]), .CK(net3346), .RN(n32), .Q(Q[19]) );
DFFR_X1 \Q_reg[18] ( .D(D[18]), .CK(net3346), .RN(n32), .Q(Q[18]) );
DFFR_X1 \Q_reg[17] ( .D(D[17]), .CK(net3346), .RN(n32), .Q(Q[17]) );
DFFR_X1 \Q_reg[16] ( .D(D[16]), .CK(net3346), .RN(n32), .Q(Q[16]) );
DFFR_X1 \Q_reg[15] ( .D(D[15]), .CK(net3346), .RN(n32), .Q(Q[15]) );
DFFR_X1 \Q_reg[14] ( .D(D[14]), .CK(net3346), .RN(n32), .Q(Q[14]) );
DFFR_X1 \Q_reg[13] ( .D(D[13]), .CK(net3346), .RN(n32), .Q(Q[13]) );
DFFR_X1 \Q_reg[12] ( .D(D[12]), .CK(net3346), .RN(n32), .Q(Q[12]) );
DFFR_X1 \Q_reg[11] ( .D(D[11]), .CK(net3346), .RN(n32), .Q(Q[11]) );
DFFR_X1 \Q_reg[10] ( .D(D[10]), .CK(net3346), .RN(n32), .Q(Q[10]) );
DFFR_X1 \Q_reg[9] ( .D(D[9]), .CK(net3346), .RN(n32), .Q(Q[9]) );
DFFR_X1 \Q_reg[8] ( .D(D[8]), .CK(net3346), .RN(n32), .Q(Q[8]) );
DFFR_X1 \Q_reg[7] ( .D(D[7]), .CK(net3346), .RN(n32), .Q(Q[7]) );
DFFR_X1 \Q_reg[6] ( .D(D[6]), .CK(net3346), .RN(n32), .Q(Q[6]) );
DFFR_X1 \Q_reg[5] ( .D(D[5]), .CK(net3346), .RN(n32), .Q(Q[5]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(net3346), .RN(n32), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(net3346), .RN(n32), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(net3346), .RN(n32), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(net3346), .RN(n32), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(net3346), .RN(n32), .Q(Q[0]) );
SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE32_1 clk_gate_Q_reg ( .CLK(clk), .EN(en),
.ENCLK(net3346) );
INV_X2 U2 ( .A(rst), .ZN(n32) );
endmodule
module mux41_MUX_SIZE32_2 ( IN0, IN1, IN2, IN3, CTRL, OUT1 );
input [31:0] IN0;
input [31:0] IN1;
input [31:0] IN2;
input [31:0] IN3;
input [1:0] CTRL;
output [31:0] OUT1;
wire n1, n2, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83,
n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109,
n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120,
n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131,
n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142,
n143, n144, n145, n146;
AOI22_X1 U87 ( .A1(n142), .A2(IN1[12]), .B1(n73), .B2(IN0[12]), .ZN(n86) );
AOI22_X1 U63 ( .A1(n142), .A2(IN1[1]), .B1(n73), .B2(IN0[1]), .ZN(n102) );
AOI22_X1 U98 ( .A1(n142), .A2(IN1[0]), .B1(n73), .B2(IN0[0]), .ZN(n80) );
AOI22_X1 U21 ( .A1(n75), .A2(IN1[3]), .B1(n72), .B2(IN0[3]), .ZN(n130) );
AOI22_X1 U30 ( .A1(n74), .A2(IN1[2]), .B1(n72), .B2(IN0[2]), .ZN(n124) );
AOI22_X1 U12 ( .A1(n75), .A2(IN1[6]), .B1(n72), .B2(IN0[6]), .ZN(n136) );
AOI22_X1 U11 ( .A1(n2), .A2(IN3[6]), .B1(n1), .B2(IN2[6]), .ZN(n135) );
AOI22_X1 U9 ( .A1(n75), .A2(IN1[7]), .B1(n72), .B2(IN0[7]), .ZN(n138) );
AOI22_X1 U8 ( .A1(n2), .A2(IN3[7]), .B1(n1), .B2(IN2[7]), .ZN(n137) );
AOI22_X1 U15 ( .A1(n75), .A2(IN1[5]), .B1(n72), .B2(IN0[5]), .ZN(n134) );
AOI22_X1 U14 ( .A1(n2), .A2(IN3[5]), .B1(n1), .B2(IN2[5]), .ZN(n133) );
AOI22_X1 U18 ( .A1(n75), .A2(IN1[4]), .B1(n72), .B2(IN0[4]), .ZN(n132) );
AOI22_X1 U17 ( .A1(n2), .A2(IN3[4]), .B1(n1), .B2(IN2[4]), .ZN(n131) );
AOI22_X1 U90 ( .A1(n75), .A2(IN1[11]), .B1(n73), .B2(IN0[11]), .ZN(n84) );
AOI22_X1 U93 ( .A1(n142), .A2(IN1[10]), .B1(n73), .B2(IN0[10]), .ZN(n82) );
AOI22_X1 U3 ( .A1(n75), .A2(IN1[9]), .B1(n72), .B2(IN0[9]), .ZN(n146) );
AOI22_X1 U2 ( .A1(n2), .A2(IN3[9]), .B1(n1), .B2(IN2[9]), .ZN(n145) );
AOI22_X1 U6 ( .A1(n75), .A2(IN1[8]), .B1(n72), .B2(IN0[8]), .ZN(n140) );
AOI22_X1 U5 ( .A1(n2), .A2(IN3[8]), .B1(n1), .B2(IN2[8]), .ZN(n139) );
AOI22_X1 U81 ( .A1(n142), .A2(IN1[14]), .B1(n73), .B2(IN0[14]), .ZN(n90) );
AOI22_X1 U84 ( .A1(n142), .A2(IN1[13]), .B1(n73), .B2(IN0[13]), .ZN(n88) );
AOI22_X1 U78 ( .A1(n75), .A2(IN1[15]), .B1(n73), .B2(IN0[15]), .ZN(n92) );
AOI22_X1 U75 ( .A1(n142), .A2(IN1[16]), .B1(n73), .B2(IN0[16]), .ZN(n94) );
NAND2_X1 U73 ( .A1(n94), .A2(n93), .ZN(OUT1[16]) );
AOI22_X1 U51 ( .A1(n74), .A2(IN1[23]), .B1(n72), .B2(IN0[23]), .ZN(n110) );
NAND2_X1 U49 ( .A1(n110), .A2(n109), .ZN(OUT1[23]) );
AOI22_X1 U60 ( .A1(n74), .A2(IN1[20]), .B1(n72), .B2(IN0[20]), .ZN(n104) );
AOI22_X1 U59 ( .A1(n2), .A2(IN3[20]), .B1(n1), .B2(IN2[20]), .ZN(n103) );
NAND2_X1 U58 ( .A1(n104), .A2(n103), .ZN(OUT1[20]) );
AOI22_X1 U57 ( .A1(n74), .A2(IN1[21]), .B1(n72), .B2(IN0[21]), .ZN(n106) );
NAND2_X1 U55 ( .A1(n106), .A2(n105), .ZN(OUT1[21]) );
AOI22_X1 U54 ( .A1(n74), .A2(IN1[22]), .B1(n72), .B2(IN0[22]), .ZN(n108) );
NAND2_X1 U52 ( .A1(n108), .A2(n107), .ZN(OUT1[22]) );
AOI22_X1 U69 ( .A1(n142), .A2(IN1[18]), .B1(n73), .B2(IN0[18]), .ZN(n98) );
NAND2_X1 U67 ( .A1(n98), .A2(n97), .ZN(OUT1[18]) );
AOI22_X1 U66 ( .A1(n142), .A2(IN1[19]), .B1(n73), .B2(IN0[19]), .ZN(n100) );
NAND2_X1 U64 ( .A1(n100), .A2(n99), .ZN(OUT1[19]) );
AOI22_X1 U72 ( .A1(n75), .A2(IN1[17]), .B1(n73), .B2(IN0[17]), .ZN(n96) );
NAND2_X1 U70 ( .A1(n96), .A2(n95), .ZN(OUT1[17]) );
AOI22_X1 U24 ( .A1(n75), .A2(IN1[31]), .B1(n72), .B2(IN0[31]), .ZN(n128) );
AOI22_X1 U23 ( .A1(n2), .A2(IN3[31]), .B1(n1), .B2(IN2[31]), .ZN(n127) );
NAND2_X1 U22 ( .A1(n128), .A2(n127), .ZN(OUT1[31]) );
AOI22_X1 U36 ( .A1(n74), .A2(IN1[28]), .B1(n72), .B2(IN0[28]), .ZN(n120) );
AOI22_X1 U35 ( .A1(n2), .A2(IN3[28]), .B1(n1), .B2(IN2[28]), .ZN(n119) );
NAND2_X1 U34 ( .A1(n120), .A2(n119), .ZN(OUT1[28]) );
AOI22_X1 U33 ( .A1(n74), .A2(IN1[29]), .B1(n72), .B2(IN0[29]), .ZN(n122) );
AOI22_X1 U32 ( .A1(n2), .A2(IN3[29]), .B1(n1), .B2(IN2[29]), .ZN(n121) );
NAND2_X1 U31 ( .A1(n122), .A2(n121), .ZN(OUT1[29]) );
AOI22_X1 U27 ( .A1(n74), .A2(IN1[30]), .B1(n72), .B2(IN0[30]), .ZN(n126) );
AOI22_X1 U26 ( .A1(n2), .A2(IN3[30]), .B1(n1), .B2(IN2[30]), .ZN(n125) );
NAND2_X1 U25 ( .A1(n126), .A2(n125), .ZN(OUT1[30]) );
AOI22_X1 U39 ( .A1(n74), .A2(IN1[27]), .B1(n72), .B2(IN0[27]), .ZN(n118) );
NAND2_X1 U37 ( .A1(n118), .A2(n117), .ZN(OUT1[27]) );
AOI22_X1 U42 ( .A1(n74), .A2(IN1[26]), .B1(n72), .B2(IN0[26]), .ZN(n116) );
AOI22_X1 U41 ( .A1(n2), .A2(IN3[26]), .B1(n1), .B2(IN2[26]), .ZN(n115) );
NAND2_X1 U40 ( .A1(n116), .A2(n115), .ZN(OUT1[26]) );
AOI22_X1 U45 ( .A1(n74), .A2(IN1[25]), .B1(n72), .B2(IN0[25]), .ZN(n114) );
NAND2_X1 U43 ( .A1(n114), .A2(n113), .ZN(OUT1[25]) );
AOI22_X1 U48 ( .A1(n74), .A2(IN1[24]), .B1(n72), .B2(IN0[24]), .ZN(n112) );
AOI22_X1 U47 ( .A1(n2), .A2(IN3[24]), .B1(n1), .B2(IN2[24]), .ZN(n111) );
NAND2_X1 U46 ( .A1(n112), .A2(n111), .ZN(OUT1[24]) );
NAND2_X1 U28 ( .A1(n124), .A2(n123), .ZN(OUT1[2]) );
NAND2_X1 U10 ( .A1(n136), .A2(n135), .ZN(OUT1[6]) );
NAND2_X1 U13 ( .A1(n134), .A2(n133), .ZN(OUT1[5]) );
NAND2_X1 U16 ( .A1(n132), .A2(n131), .ZN(OUT1[4]) );
NAND2_X1 U88 ( .A1(n84), .A2(n83), .ZN(OUT1[11]) );
NAND2_X1 U91 ( .A1(n82), .A2(n81), .ZN(OUT1[10]) );
NAND2_X1 U1 ( .A1(n146), .A2(n145), .ZN(OUT1[9]) );
NAND2_X1 U79 ( .A1(n90), .A2(n89), .ZN(OUT1[14]) );
NAND2_X1 U82 ( .A1(n88), .A2(n87), .ZN(OUT1[13]) );
NAND2_X1 U85 ( .A1(n86), .A2(n85), .ZN(OUT1[12]) );
NAND2_X1 U61 ( .A1(n102), .A2(n101), .ZN(OUT1[1]) );
NAND2_X1 U19 ( .A1(n130), .A2(n129), .ZN(OUT1[3]) );
NAND2_X1 U7 ( .A1(n138), .A2(n137), .ZN(OUT1[7]) );
NAND2_X1 U4 ( .A1(n140), .A2(n139), .ZN(OUT1[8]) );
NAND2_X1 U76 ( .A1(n92), .A2(n91), .ZN(OUT1[15]) );
BUF_X4 U20 ( .A(n143), .Z(n1) );
AND2_X2 U29 ( .A1(n78), .A2(CTRL[0]), .ZN(n142) );
BUF_X2 U38 ( .A(n142), .Z(n75) );
BUF_X1 U44 ( .A(n142), .Z(n74) );
BUF_X2 U50 ( .A(n144), .Z(n2) );
BUF_X1 U53 ( .A(n144), .Z(n77) );
BUF_X1 U56 ( .A(n141), .Z(n73) );
BUF_X2 U62 ( .A(n141), .Z(n72) );
BUF_X2 U65 ( .A(n143), .Z(n76) );
INV_X1 U68 ( .A(CTRL[1]), .ZN(n78) );
AND2_X1 U71 ( .A1(CTRL[0]), .A2(CTRL[1]), .ZN(n144) );
AOI22_X1 U74 ( .A1(n2), .A2(IN3[23]), .B1(n1), .B2(IN2[23]), .ZN(n109) );
AOI22_X1 U77 ( .A1(n2), .A2(IN3[21]), .B1(n1), .B2(IN2[21]), .ZN(n105) );
AOI22_X1 U80 ( .A1(n2), .A2(IN3[22]), .B1(n1), .B2(IN2[22]), .ZN(n107) );
AOI22_X1 U83 ( .A1(n2), .A2(IN3[2]), .B1(n1), .B2(IN2[2]), .ZN(n123) );
AOI22_X1 U86 ( .A1(n2), .A2(IN3[27]), .B1(n1), .B2(IN2[27]), .ZN(n117) );
AOI22_X1 U89 ( .A1(n2), .A2(IN3[25]), .B1(n1), .B2(IN2[25]), .ZN(n113) );
AOI22_X1 U92 ( .A1(n2), .A2(IN3[3]), .B1(n1), .B2(IN2[3]), .ZN(n129) );
NAND2_X1 U94 ( .A1(n80), .A2(n79), .ZN(OUT1[0]) );
AOI22_X1 U95 ( .A1(n77), .A2(IN3[16]), .B1(n76), .B2(IN2[16]), .ZN(n93) );
AOI22_X1 U96 ( .A1(n77), .A2(IN3[12]), .B1(n76), .B2(IN2[12]), .ZN(n85) );
AOI22_X1 U97 ( .A1(n77), .A2(IN3[18]), .B1(n76), .B2(IN2[18]), .ZN(n97) );
AOI22_X1 U99 ( .A1(n77), .A2(IN3[10]), .B1(n76), .B2(IN2[10]), .ZN(n81) );
AOI22_X1 U100 ( .A1(n77), .A2(IN3[14]), .B1(n76), .B2(IN2[14]), .ZN(n89) );
AOI22_X1 U101 ( .A1(n77), .A2(IN3[13]), .B1(n76), .B2(IN2[13]), .ZN(n87) );
AOI22_X1 U102 ( .A1(n77), .A2(IN3[19]), .B1(n76), .B2(IN2[19]), .ZN(n99) );
AOI22_X1 U103 ( .A1(n77), .A2(IN3[17]), .B1(n76), .B2(IN2[17]), .ZN(n95) );
AOI22_X1 U104 ( .A1(n77), .A2(IN3[1]), .B1(n76), .B2(IN2[1]), .ZN(n101) );
AOI22_X1 U105 ( .A1(n77), .A2(IN3[15]), .B1(n76), .B2(IN2[15]), .ZN(n91) );
AOI22_X1 U106 ( .A1(n77), .A2(IN3[11]), .B1(n76), .B2(IN2[11]), .ZN(n83) );
AOI22_X1 U107 ( .A1(n77), .A2(IN3[0]), .B1(n76), .B2(IN2[0]), .ZN(n79) );
NOR2_X1 U108 ( .A1(CTRL[1]), .A2(CTRL[0]), .ZN(n141) );
NOR2_X1 U109 ( .A1(CTRL[0]), .A2(n78), .ZN(n143) );
endmodule
module mux41_MUX_SIZE32_1 ( IN0, IN1, IN2, IN3, CTRL, OUT1 );
input [31:0] IN0;
input [31:0] IN1;
input [31:0] IN2;
input [31:0] IN3;
input [1:0] CTRL;
output [31:0] OUT1;
wire n1, n2, n47, n48, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127,
n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n146, n147;
NAND2_X1 U25 ( .A1(n128), .A2(n127), .ZN(OUT1[30]) );
NAND2_X1 U22 ( .A1(n130), .A2(n129), .ZN(OUT1[31]) );
NAND2_X1 U46 ( .A1(n114), .A2(n113), .ZN(OUT1[24]) );
BUF_X1 U1 ( .A(n69), .Z(n2) );
CLKBUF_X3 U2 ( .A(n69), .Z(n1) );
BUF_X1 U3 ( .A(n69), .Z(n47) );
NOR2_X1 U4 ( .A1(n48), .A2(CTRL[0]), .ZN(n69) );
BUF_X2 U5 ( .A(n144), .Z(n79) );
AND2_X2 U6 ( .A1(n48), .A2(CTRL[0]), .ZN(n144) );
BUF_X1 U7 ( .A(n144), .Z(n74) );
BUF_X1 U8 ( .A(n145), .Z(n82) );
BUF_X1 U9 ( .A(n145), .Z(n84) );
BUF_X2 U10 ( .A(n144), .Z(n80) );
BUF_X2 U11 ( .A(n144), .Z(n81) );
BUF_X2 U12 ( .A(n144), .Z(n75) );
BUF_X2 U13 ( .A(n143), .Z(n78) );
BUF_X2 U14 ( .A(n143), .Z(n77) );
BUF_X2 U15 ( .A(n143), .Z(n76) );
BUF_X2 U16 ( .A(n145), .Z(n83) );
AND2_X1 U17 ( .A1(CTRL[1]), .A2(CTRL[0]), .ZN(n145) );
INV_X1 U18 ( .A(CTRL[1]), .ZN(n48) );
NAND2_X1 U19 ( .A1(n1), .A2(IN2[1]), .ZN(n70) );
NAND2_X1 U20 ( .A1(n1), .A2(IN2[0]), .ZN(n72) );
AOI22_X1 U21 ( .A1(n84), .A2(IN3[6]), .B1(n47), .B2(IN2[6]), .ZN(n137) );
AOI22_X1 U23 ( .A1(n82), .A2(IN3[18]), .B1(n1), .B2(IN2[18]), .ZN(n101) );
AOI22_X1 U24 ( .A1(n82), .A2(IN3[13]), .B1(n2), .B2(IN2[13]), .ZN(n91) );
AOI22_X1 U26 ( .A1(n82), .A2(IN3[15]), .B1(n1), .B2(IN2[15]), .ZN(n95) );
AOI22_X1 U27 ( .A1(n83), .A2(IN3[23]), .B1(n2), .B2(IN2[23]), .ZN(n111) );
NAND2_X1 U28 ( .A1(n72), .A2(n73), .ZN(OUT1[0]) );
NOR2_X1 U29 ( .A1(CTRL[0]), .A2(CTRL[1]), .ZN(n143) );
AOI22_X1 U30 ( .A1(n79), .A2(IN1[1]), .B1(n78), .B2(IN0[1]), .ZN(n71) );
NAND2_X1 U31 ( .A1(n71), .A2(n70), .ZN(OUT1[1]) );
AOI22_X1 U32 ( .A1(n79), .A2(IN1[0]), .B1(n78), .B2(IN0[0]), .ZN(n73) );
NAND2_X1 U33 ( .A1(n2), .A2(IN2[19]), .ZN(n103) );
NAND2_X1 U34 ( .A1(n131), .A2(n132), .ZN(OUT1[3]) );
NAND2_X1 U35 ( .A1(n106), .A2(n105), .ZN(OUT1[20]) );
NAND2_X1 U36 ( .A1(n124), .A2(n123), .ZN(OUT1[29]) );
NAND2_X1 U37 ( .A1(n120), .A2(n119), .ZN(OUT1[27]) );
NAND2_X1 U38 ( .A1(n90), .A2(n89), .ZN(OUT1[12]) );
NAND2_X1 U39 ( .A1(n98), .A2(n97), .ZN(OUT1[16]) );
NAND2_X1 U40 ( .A1(n118), .A2(n117), .ZN(OUT1[26]) );
NAND2_X1 U41 ( .A1(n142), .A2(n141), .ZN(OUT1[8]) );
NAND2_X1 U42 ( .A1(n138), .A2(n137), .ZN(OUT1[6]) );
NAND2_X1 U43 ( .A1(n134), .A2(n133), .ZN(OUT1[4]) );
NAND2_X1 U44 ( .A1(n122), .A2(n121), .ZN(OUT1[28]) );
NAND2_X1 U45 ( .A1(n86), .A2(n85), .ZN(OUT1[10]) );
NAND2_X1 U47 ( .A1(n109), .A2(n110), .ZN(OUT1[22]) );
NAND2_X1 U48 ( .A1(n104), .A2(n103), .ZN(OUT1[19]) );
NAND2_X1 U49 ( .A1(n107), .A2(n108), .ZN(OUT1[21]) );
NAND2_X1 U50 ( .A1(n96), .A2(n95), .ZN(OUT1[15]) );
NAND2_X1 U51 ( .A1(n147), .A2(n146), .ZN(OUT1[9]) );
NAND2_X1 U52 ( .A1(n100), .A2(n99), .ZN(OUT1[17]) );
NAND2_X1 U53 ( .A1(n102), .A2(n101), .ZN(OUT1[18]) );
AOI22_X1 U54 ( .A1(n74), .A2(IN1[30]), .B1(n77), .B2(IN0[30]), .ZN(n128) );
AOI22_X1 U55 ( .A1(n75), .A2(IN1[29]), .B1(n77), .B2(IN0[29]), .ZN(n124) );
AOI22_X1 U56 ( .A1(n75), .A2(IN1[25]), .B1(n77), .B2(IN0[25]), .ZN(n116) );
AOI22_X1 U57 ( .A1(n81), .A2(IN1[24]), .B1(n76), .B2(IN0[24]), .ZN(n114) );
AOI22_X1 U58 ( .A1(n74), .A2(IN1[27]), .B1(n76), .B2(IN0[27]), .ZN(n120) );
AOI22_X1 U59 ( .A1(n80), .A2(IN1[26]), .B1(n77), .B2(IN0[26]), .ZN(n118) );
AOI22_X1 U60 ( .A1(n81), .A2(IN1[20]), .B1(n76), .B2(IN0[20]), .ZN(n106) );
AOI22_X1 U61 ( .A1(n81), .A2(IN1[2]), .B1(n76), .B2(IN0[2]), .ZN(n126) );
AOI22_X1 U62 ( .A1(n75), .A2(IN1[22]), .B1(n76), .B2(IN0[22]), .ZN(n110) );
AOI22_X1 U63 ( .A1(n74), .A2(IN1[23]), .B1(n76), .B2(IN0[23]), .ZN(n112) );
AOI22_X1 U64 ( .A1(n74), .A2(IN1[28]), .B1(n77), .B2(IN0[28]), .ZN(n122) );
AOI22_X1 U65 ( .A1(n74), .A2(IN1[21]), .B1(n77), .B2(IN0[21]), .ZN(n108) );
NAND2_X1 U66 ( .A1(n112), .A2(n111), .ZN(OUT1[23]) );
AOI22_X1 U67 ( .A1(n80), .A2(IN1[31]), .B1(n76), .B2(IN0[31]), .ZN(n130) );
AOI22_X1 U68 ( .A1(n79), .A2(IN1[3]), .B1(n78), .B2(IN0[3]), .ZN(n132) );
AOI22_X1 U69 ( .A1(n75), .A2(IN1[6]), .B1(n77), .B2(IN0[6]), .ZN(n138) );
AOI22_X1 U70 ( .A1(n81), .A2(IN1[8]), .B1(n77), .B2(IN0[8]), .ZN(n142) );
AOI22_X1 U71 ( .A1(n80), .A2(IN1[4]), .B1(n77), .B2(IN0[4]), .ZN(n134) );
AOI22_X1 U72 ( .A1(n79), .A2(IN1[7]), .B1(n76), .B2(IN0[7]), .ZN(n140) );
AOI22_X1 U73 ( .A1(n81), .A2(IN1[5]), .B1(n76), .B2(IN0[5]), .ZN(n136) );
AOI22_X1 U74 ( .A1(n74), .A2(IN1[9]), .B1(n76), .B2(IN0[9]), .ZN(n147) );
NAND2_X1 U75 ( .A1(n92), .A2(n91), .ZN(OUT1[13]) );
AOI22_X1 U76 ( .A1(n84), .A2(IN3[31]), .B1(n47), .B2(IN2[31]), .ZN(n129) );
AOI22_X1 U77 ( .A1(n84), .A2(IN3[3]), .B1(n2), .B2(IN2[3]), .ZN(n131) );
AOI22_X1 U78 ( .A1(n84), .A2(IN3[4]), .B1(n47), .B2(IN2[4]), .ZN(n133) );
AOI22_X1 U79 ( .A1(n84), .A2(IN3[7]), .B1(n2), .B2(IN2[7]), .ZN(n139) );
AOI22_X1 U80 ( .A1(n84), .A2(IN3[5]), .B1(n47), .B2(IN2[5]), .ZN(n135) );
AOI22_X1 U81 ( .A1(n84), .A2(IN3[8]), .B1(n47), .B2(IN2[8]), .ZN(n141) );
AOI22_X1 U82 ( .A1(n84), .A2(IN3[9]), .B1(n47), .B2(IN2[9]), .ZN(n146) );
NAND2_X1 U83 ( .A1(n125), .A2(n126), .ZN(OUT1[2]) );
NAND2_X1 U84 ( .A1(n116), .A2(n115), .ZN(OUT1[25]) );
NAND2_X1 U85 ( .A1(n88), .A2(n87), .ZN(OUT1[11]) );
NAND2_X1 U86 ( .A1(n94), .A2(n93), .ZN(OUT1[14]) );
NAND2_X1 U87 ( .A1(n140), .A2(n139), .ZN(OUT1[7]) );
AOI22_X1 U88 ( .A1(n83), .A2(IN3[30]), .B1(n2), .B2(IN2[30]), .ZN(n127) );
AOI22_X1 U89 ( .A1(n83), .A2(IN3[29]), .B1(n47), .B2(IN2[29]), .ZN(n123) );
AOI22_X1 U90 ( .A1(n83), .A2(IN3[24]), .B1(n2), .B2(IN2[24]), .ZN(n113) );
AOI22_X1 U91 ( .A1(n83), .A2(IN3[27]), .B1(n1), .B2(IN2[27]), .ZN(n119) );
AOI22_X1 U92 ( .A1(n83), .A2(IN3[26]), .B1(n2), .B2(IN2[26]), .ZN(n117) );
AOI22_X1 U93 ( .A1(n83), .A2(IN3[28]), .B1(n1), .B2(IN2[28]), .ZN(n121) );
AOI22_X1 U94 ( .A1(n83), .A2(IN3[20]), .B1(n2), .B2(IN2[20]), .ZN(n105) );
AOI22_X1 U95 ( .A1(n83), .A2(IN3[25]), .B1(n47), .B2(IN2[25]), .ZN(n115) );
AOI22_X1 U96 ( .A1(n83), .A2(IN3[22]), .B1(n1), .B2(IN2[22]), .ZN(n109) );
AOI22_X1 U97 ( .A1(n83), .A2(IN3[2]), .B1(IN2[2]), .B2(n2), .ZN(n125) );
AOI22_X1 U98 ( .A1(n83), .A2(IN3[21]), .B1(n1), .B2(IN2[21]), .ZN(n107) );
AOI22_X1 U99 ( .A1(n81), .A2(IN1[16]), .B1(n76), .B2(IN0[16]), .ZN(n98) );
AOI22_X1 U100 ( .A1(n81), .A2(IN1[19]), .B1(n78), .B2(IN0[19]), .ZN(n104) );
AOI22_X1 U101 ( .A1(n75), .A2(IN1[12]), .B1(n77), .B2(IN0[12]), .ZN(n90) );
AOI22_X1 U102 ( .A1(n80), .A2(IN1[18]), .B1(n78), .B2(IN0[18]), .ZN(n102) );
AOI22_X1 U103 ( .A1(n80), .A2(IN1[11]), .B1(n76), .B2(IN0[11]), .ZN(n88) );
AOI22_X1 U104 ( .A1(n79), .A2(IN1[10]), .B1(n77), .B2(IN0[10]), .ZN(n86) );
AOI22_X1 U105 ( .A1(n80), .A2(IN1[14]), .B1(n77), .B2(IN0[14]), .ZN(n94) );
AOI22_X1 U106 ( .A1(n74), .A2(IN1[15]), .B1(n77), .B2(IN0[15]), .ZN(n96) );
AOI22_X1 U107 ( .A1(n75), .A2(IN1[17]), .B1(n78), .B2(IN0[17]), .ZN(n100) );
AOI22_X1 U108 ( .A1(n75), .A2(IN1[13]), .B1(n76), .B2(IN0[13]), .ZN(n92) );
NAND2_X1 U109 ( .A1(n136), .A2(n135), .ZN(OUT1[5]) );
AOI22_X1 U110 ( .A1(n82), .A2(IN3[16]), .B1(n2), .B2(IN2[16]), .ZN(n97) );
AOI22_X1 U111 ( .A1(n82), .A2(IN3[12]), .B1(n1), .B2(IN2[12]), .ZN(n89) );
AOI22_X1 U112 ( .A1(n82), .A2(IN3[11]), .B1(n47), .B2(IN2[11]), .ZN(n87) );
AOI22_X1 U113 ( .A1(n82), .A2(IN3[10]), .B1(n1), .B2(IN2[10]), .ZN(n85) );
AOI22_X1 U114 ( .A1(n82), .A2(IN3[17]), .B1(n1), .B2(IN2[17]), .ZN(n99) );
AOI22_X1 U115 ( .A1(n82), .A2(IN3[14]), .B1(n47), .B2(IN2[14]), .ZN(n93) );
endmodule
module mux21_4 ( IN0, IN1, CTRL, OUT1 );
input [31:0] IN0;
input [31:0] IN1;
output [31:0] OUT1;
input CTRL;
MUX2_X1 U1 ( .A(IN0[9]), .B(IN1[9]), .S(CTRL), .Z(OUT1[9]) );
MUX2_X1 U2 ( .A(IN0[8]), .B(IN1[8]), .S(CTRL), .Z(OUT1[8]) );
MUX2_X1 U3 ( .A(IN0[7]), .B(IN1[7]), .S(CTRL), .Z(OUT1[7]) );
MUX2_X1 U4 ( .A(IN0[6]), .B(IN1[6]), .S(CTRL), .Z(OUT1[6]) );
MUX2_X1 U5 ( .A(IN0[5]), .B(IN1[5]), .S(CTRL), .Z(OUT1[5]) );
MUX2_X1 U6 ( .A(IN0[4]), .B(IN1[4]), .S(CTRL), .Z(OUT1[4]) );
MUX2_X1 U7 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U8 ( .A(IN0[31]), .B(IN1[31]), .S(CTRL), .Z(OUT1[31]) );
MUX2_X1 U9 ( .A(IN0[30]), .B(IN1[30]), .S(CTRL), .Z(OUT1[30]) );
MUX2_X1 U10 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U11 ( .A(IN0[29]), .B(IN1[29]), .S(CTRL), .Z(OUT1[29]) );
MUX2_X1 U12 ( .A(IN0[28]), .B(IN1[28]), .S(CTRL), .Z(OUT1[28]) );
MUX2_X1 U16 ( .A(IN0[24]), .B(IN1[24]), .S(CTRL), .Z(OUT1[24]) );
MUX2_X1 U17 ( .A(IN0[23]), .B(IN1[23]), .S(CTRL), .Z(OUT1[23]) );
MUX2_X1 U18 ( .A(IN0[22]), .B(IN1[22]), .S(CTRL), .Z(OUT1[22]) );
MUX2_X1 U19 ( .A(IN0[21]), .B(IN1[21]), .S(CTRL), .Z(OUT1[21]) );
MUX2_X1 U20 ( .A(IN0[20]), .B(IN1[20]), .S(CTRL), .Z(OUT1[20]) );
MUX2_X1 U21 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U22 ( .A(IN0[19]), .B(IN1[19]), .S(CTRL), .Z(OUT1[19]) );
MUX2_X1 U23 ( .A(IN0[18]), .B(IN1[18]), .S(CTRL), .Z(OUT1[18]) );
MUX2_X1 U24 ( .A(IN0[17]), .B(IN1[17]), .S(CTRL), .Z(OUT1[17]) );
MUX2_X1 U25 ( .A(IN0[16]), .B(IN1[16]), .S(CTRL), .Z(OUT1[16]) );
MUX2_X1 U26 ( .A(IN0[15]), .B(IN1[15]), .S(CTRL), .Z(OUT1[15]) );
MUX2_X1 U27 ( .A(IN0[14]), .B(IN1[14]), .S(CTRL), .Z(OUT1[14]) );
MUX2_X1 U28 ( .A(IN0[13]), .B(IN1[13]), .S(CTRL), .Z(OUT1[13]) );
MUX2_X1 U29 ( .A(IN0[12]), .B(IN1[12]), .S(CTRL), .Z(OUT1[12]) );
MUX2_X1 U30 ( .A(IN0[11]), .B(IN1[11]), .S(CTRL), .Z(OUT1[11]) );
MUX2_X1 U31 ( .A(IN0[10]), .B(IN1[10]), .S(CTRL), .Z(OUT1[10]) );
MUX2_X1 U32 ( .A(IN0[0]), .B(IN1[0]), .S(CTRL), .Z(OUT1[0]) );
MUX2_X1 U13 ( .A(IN0[27]), .B(IN1[27]), .S(CTRL), .Z(OUT1[27]) );
MUX2_X1 U14 ( .A(IN0[26]), .B(IN1[26]), .S(CTRL), .Z(OUT1[26]) );
MUX2_X1 U15 ( .A(IN0[25]), .B(IN1[25]), .S(CTRL), .Z(OUT1[25]) );
endmodule
module mux21_3 ( IN0, IN1, CTRL, OUT1 );
input [31:0] IN0;
input [31:0] IN1;
output [31:0] OUT1;
input CTRL;
wire n1, n3, n4, n5, n6, n7;
MUX2_X1 U2 ( .A(IN0[8]), .B(IN1[8]), .S(CTRL), .Z(OUT1[8]) );
MUX2_X1 U8 ( .A(IN0[31]), .B(IN1[31]), .S(CTRL), .Z(OUT1[31]) );
MUX2_X1 U9 ( .A(IN0[30]), .B(IN1[30]), .S(CTRL), .Z(OUT1[30]) );
MUX2_X1 U11 ( .A(IN0[29]), .B(IN1[29]), .S(CTRL), .Z(OUT1[29]) );
MUX2_X1 U13 ( .A(IN0[27]), .B(IN1[27]), .S(CTRL), .Z(OUT1[27]) );
MUX2_X1 U14 ( .A(IN0[26]), .B(IN1[26]), .S(CTRL), .Z(OUT1[26]) );
MUX2_X1 U16 ( .A(IN0[24]), .B(IN1[24]), .S(CTRL), .Z(OUT1[24]) );
MUX2_X1 U20 ( .A(IN0[20]), .B(IN1[20]), .S(CTRL), .Z(OUT1[20]) );
MUX2_X1 U1 ( .A(IN0[18]), .B(IN1[18]), .S(CTRL), .Z(OUT1[18]) );
AOI22_X1 U3 ( .A1(CTRL), .A2(IN1[6]), .B1(n3), .B2(IN0[6]), .ZN(n1) );
INV_X1 U4 ( .A(n1), .ZN(OUT1[6]) );
MUX2_X1 U5 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X2 U6 ( .A(IN0[4]), .B(IN1[4]), .S(CTRL), .Z(OUT1[4]) );
NAND2_X1 U7 ( .A1(IN0[13]), .A2(n3), .ZN(n4) );
NAND2_X1 U10 ( .A1(IN1[13]), .A2(CTRL), .ZN(n5) );
NAND2_X2 U12 ( .A1(n4), .A2(n5), .ZN(OUT1[13]) );
INV_X1 U15 ( .A(CTRL), .ZN(n3) );
MUX2_X1 U17 ( .A(IN0[25]), .B(IN1[25]), .S(CTRL), .Z(OUT1[25]) );
MUX2_X1 U18 ( .A(IN0[28]), .B(IN1[28]), .S(CTRL), .Z(OUT1[28]) );
MUX2_X1 U19 ( .A(IN0[23]), .B(IN1[23]), .S(CTRL), .Z(OUT1[23]) );
MUX2_X1 U21 ( .A(IN0[22]), .B(IN1[22]), .S(CTRL), .Z(OUT1[22]) );
MUX2_X1 U22 ( .A(IN0[16]), .B(IN1[16]), .S(CTRL), .Z(OUT1[16]) );
MUX2_X1 U23 ( .A(IN0[9]), .B(IN1[9]), .S(CTRL), .Z(OUT1[9]) );
MUX2_X1 U24 ( .A(IN0[10]), .B(IN1[10]), .S(CTRL), .Z(OUT1[10]) );
MUX2_X1 U25 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U26 ( .A(IN0[12]), .B(IN1[12]), .S(CTRL), .Z(OUT1[12]) );
NAND2_X1 U27 ( .A1(n6), .A2(n7), .ZN(OUT1[0]) );
MUX2_X1 U28 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
NAND2_X1 U29 ( .A1(IN1[0]), .A2(CTRL), .ZN(n7) );
NAND2_X1 U30 ( .A1(IN0[0]), .A2(n3), .ZN(n6) );
MUX2_X1 U31 ( .A(IN0[19]), .B(IN1[19]), .S(CTRL), .Z(OUT1[19]) );
MUX2_X1 U32 ( .A(IN0[7]), .B(IN1[7]), .S(CTRL), .Z(OUT1[7]) );
MUX2_X1 U33 ( .A(IN0[17]), .B(IN1[17]), .S(CTRL), .Z(OUT1[17]) );
MUX2_X1 U34 ( .A(IN0[21]), .B(IN1[21]), .S(CTRL), .Z(OUT1[21]) );
MUX2_X1 U35 ( .A(IN0[14]), .B(IN1[14]), .S(CTRL), .Z(OUT1[14]) );
MUX2_X1 U36 ( .A(IN0[11]), .B(IN1[11]), .S(CTRL), .Z(OUT1[11]) );
MUX2_X1 U37 ( .A(IN0[15]), .B(IN1[15]), .S(CTRL), .Z(OUT1[15]) );
MUX2_X1 U38 ( .A(IN0[5]), .B(IN1[5]), .S(CTRL), .Z(OUT1[5]) );
endmodule
module mux21_2 ( IN0, IN1, OUT1, CTRL_BAR );
input [31:0] IN0;
input [31:0] IN1;
output [31:0] OUT1;
input CTRL_BAR;
wire CTRL, n1, n2, n3;
assign CTRL = CTRL_BAR;
MUX2_X1 U1 ( .A(IN0[9]), .B(IN1[9]), .S(n3), .Z(OUT1[9]) );
MUX2_X1 U2 ( .A(IN0[8]), .B(IN1[8]), .S(n3), .Z(OUT1[8]) );
MUX2_X1 U3 ( .A(IN0[7]), .B(IN1[7]), .S(n3), .Z(OUT1[7]) );
MUX2_X1 U4 ( .A(IN0[6]), .B(IN1[6]), .S(n3), .Z(OUT1[6]) );
MUX2_X1 U5 ( .A(IN0[5]), .B(IN1[5]), .S(n3), .Z(OUT1[5]) );
MUX2_X1 U6 ( .A(IN0[4]), .B(IN1[4]), .S(n3), .Z(OUT1[4]) );
MUX2_X1 U7 ( .A(IN0[3]), .B(IN1[3]), .S(n3), .Z(OUT1[3]) );
MUX2_X1 U8 ( .A(IN0[31]), .B(IN1[31]), .S(n3), .Z(OUT1[31]) );
MUX2_X1 U9 ( .A(IN0[30]), .B(IN1[30]), .S(n3), .Z(OUT1[30]) );
MUX2_X1 U10 ( .A(IN0[2]), .B(IN1[2]), .S(n3), .Z(OUT1[2]) );
MUX2_X1 U11 ( .A(IN0[29]), .B(IN1[29]), .S(n3), .Z(OUT1[29]) );
MUX2_X1 U12 ( .A(IN0[28]), .B(IN1[28]), .S(n3), .Z(OUT1[28]) );
MUX2_X1 U13 ( .A(IN0[27]), .B(IN1[27]), .S(n2), .Z(OUT1[27]) );
MUX2_X1 U14 ( .A(IN0[26]), .B(IN1[26]), .S(n2), .Z(OUT1[26]) );
MUX2_X1 U15 ( .A(IN0[25]), .B(IN1[25]), .S(n2), .Z(OUT1[25]) );
MUX2_X1 U16 ( .A(IN0[24]), .B(IN1[24]), .S(n2), .Z(OUT1[24]) );
MUX2_X1 U17 ( .A(IN0[23]), .B(IN1[23]), .S(n2), .Z(OUT1[23]) );
MUX2_X1 U18 ( .A(IN0[22]), .B(IN1[22]), .S(n2), .Z(OUT1[22]) );
MUX2_X1 U19 ( .A(IN0[21]), .B(IN1[21]), .S(n2), .Z(OUT1[21]) );
MUX2_X1 U20 ( .A(IN0[20]), .B(IN1[20]), .S(n2), .Z(OUT1[20]) );
MUX2_X1 U21 ( .A(IN0[1]), .B(IN1[1]), .S(n2), .Z(OUT1[1]) );
MUX2_X1 U22 ( .A(IN0[19]), .B(IN1[19]), .S(n2), .Z(OUT1[19]) );
MUX2_X1 U23 ( .A(IN0[18]), .B(IN1[18]), .S(n2), .Z(OUT1[18]) );
MUX2_X1 U24 ( .A(IN0[17]), .B(IN1[17]), .S(n2), .Z(OUT1[17]) );
MUX2_X1 U25 ( .A(IN0[16]), .B(IN1[16]), .S(n1), .Z(OUT1[16]) );
MUX2_X1 U26 ( .A(IN0[15]), .B(IN1[15]), .S(n1), .Z(OUT1[15]) );
MUX2_X1 U27 ( .A(IN0[14]), .B(IN1[14]), .S(n1), .Z(OUT1[14]) );
MUX2_X1 U28 ( .A(IN0[13]), .B(IN1[13]), .S(n1), .Z(OUT1[13]) );
MUX2_X1 U29 ( .A(IN0[12]), .B(IN1[12]), .S(n1), .Z(OUT1[12]) );
MUX2_X1 U30 ( .A(IN0[11]), .B(IN1[11]), .S(n1), .Z(OUT1[11]) );
MUX2_X1 U31 ( .A(IN0[10]), .B(IN1[10]), .S(n1), .Z(OUT1[10]) );
MUX2_X1 U32 ( .A(IN0[0]), .B(IN1[0]), .S(n1), .Z(OUT1[0]) );
INV_X1 U33 ( .A(CTRL), .ZN(n1) );
INV_X1 U34 ( .A(CTRL), .ZN(n2) );
INV_X1 U35 ( .A(CTRL), .ZN(n3) );
endmodule
module mux21_1 ( IN0, IN1, CTRL, OUT1 );
input [31:0] IN0;
input [31:0] IN1;
output [31:0] OUT1;
input CTRL;
wire n1;
MUX2_X1 U1 ( .A(IN0[9]), .B(IN1[9]), .S(CTRL), .Z(OUT1[9]) );
MUX2_X1 U2 ( .A(IN0[8]), .B(IN1[8]), .S(CTRL), .Z(OUT1[8]) );
MUX2_X1 U3 ( .A(IN0[7]), .B(IN1[7]), .S(CTRL), .Z(OUT1[7]) );
MUX2_X1 U4 ( .A(IN0[6]), .B(IN1[6]), .S(CTRL), .Z(OUT1[6]) );
MUX2_X1 U6 ( .A(IN0[4]), .B(IN1[4]), .S(CTRL), .Z(OUT1[4]) );
MUX2_X1 U7 ( .A(IN0[3]), .B(IN1[3]), .S(CTRL), .Z(OUT1[3]) );
MUX2_X1 U8 ( .A(IN0[31]), .B(IN1[31]), .S(CTRL), .Z(OUT1[31]) );
MUX2_X1 U9 ( .A(IN0[30]), .B(IN1[30]), .S(CTRL), .Z(OUT1[30]) );
MUX2_X1 U10 ( .A(IN0[2]), .B(IN1[2]), .S(CTRL), .Z(OUT1[2]) );
MUX2_X1 U11 ( .A(IN0[29]), .B(IN1[29]), .S(CTRL), .Z(OUT1[29]) );
MUX2_X1 U12 ( .A(IN0[28]), .B(IN1[28]), .S(CTRL), .Z(OUT1[28]) );
MUX2_X1 U13 ( .A(IN0[27]), .B(IN1[27]), .S(CTRL), .Z(OUT1[27]) );
MUX2_X1 U14 ( .A(IN0[26]), .B(IN1[26]), .S(CTRL), .Z(OUT1[26]) );
MUX2_X1 U15 ( .A(IN0[25]), .B(IN1[25]), .S(CTRL), .Z(OUT1[25]) );
MUX2_X1 U16 ( .A(IN0[24]), .B(IN1[24]), .S(CTRL), .Z(OUT1[24]) );
MUX2_X1 U17 ( .A(IN0[23]), .B(IN1[23]), .S(CTRL), .Z(OUT1[23]) );
MUX2_X1 U18 ( .A(IN0[22]), .B(IN1[22]), .S(CTRL), .Z(OUT1[22]) );
MUX2_X1 U19 ( .A(IN0[21]), .B(IN1[21]), .S(CTRL), .Z(OUT1[21]) );
MUX2_X1 U20 ( .A(IN0[20]), .B(IN1[20]), .S(CTRL), .Z(OUT1[20]) );
MUX2_X1 U21 ( .A(IN0[1]), .B(IN1[1]), .S(CTRL), .Z(OUT1[1]) );
MUX2_X1 U22 ( .A(IN0[19]), .B(IN1[19]), .S(CTRL), .Z(OUT1[19]) );
MUX2_X1 U23 ( .A(IN0[18]), .B(IN1[18]), .S(CTRL), .Z(OUT1[18]) );
MUX2_X1 U24 ( .A(IN0[17]), .B(IN1[17]), .S(CTRL), .Z(OUT1[17]) );
MUX2_X1 U25 ( .A(IN0[16]), .B(IN1[16]), .S(CTRL), .Z(OUT1[16]) );
MUX2_X1 U26 ( .A(IN0[15]), .B(IN1[15]), .S(CTRL), .Z(OUT1[15]) );
MUX2_X1 U27 ( .A(IN0[14]), .B(IN1[14]), .S(CTRL), .Z(OUT1[14]) );
MUX2_X1 U28 ( .A(IN0[13]), .B(IN1[13]), .S(CTRL), .Z(OUT1[13]) );
MUX2_X1 U29 ( .A(IN0[12]), .B(IN1[12]), .S(CTRL), .Z(OUT1[12]) );
MUX2_X1 U30 ( .A(IN0[11]), .B(IN1[11]), .S(CTRL), .Z(OUT1[11]) );
MUX2_X1 U31 ( .A(IN0[10]), .B(IN1[10]), .S(CTRL), .Z(OUT1[10]) );
MUX2_X1 U5 ( .A(IN0[5]), .B(IN1[5]), .S(CTRL), .Z(OUT1[5]) );
INV_X1 U32 ( .A(IN0[0]), .ZN(n1) );
NOR2_X1 U33 ( .A1(CTRL), .A2(n1), .ZN(OUT1[0]) );
endmodule
module p4add_N32_logN5_1 ( A, B, Cin, sign, S, Cout_BAR );
input [31:0] A;
input [31:0] B;
output [31:0] S;
input Cin, sign;
output Cout_BAR;
wire Cout, n1, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13;
wire [31:0] new_B;
wire [7:0] carry_pro;
assign Cout_BAR = Cout;
xor_gen_N32_1 xor32 ( .A(B), .B(sign), .S({new_B[31:2], n1, new_B[0]}) );
carry_tree_N32_logN5_1 ct ( .A(A), .B({new_B[31:2], n1, new_B[0]}), .Cin(
sign), .\Cout[7]_BAR (Cout), .\Cout[6] (carry_pro[7]), .\Cout[5] (
carry_pro[6]), .\Cout[4] (carry_pro[5]), .\Cout[3] (carry_pro[4]),
.\Cout[2] (carry_pro[3]), .\Cout[1] (carry_pro[2]), .\Cout[0] (
carry_pro[1]) );
sum_gen_N32_1 add ( .A(A), .B({new_B[31:24], n6, new_B[22], n3, new_B[20:18],
n9, new_B[16], n5, new_B[14], n13, n7, new_B[11], n8, n11, new_B[8:7],
n4, n12, new_B[4:2], n1, n10}), .Cin({1'b0, carry_pro[7:1], sign}),
.S(S) );
BUF_X1 U1 ( .A(new_B[12]), .Z(n7) );
BUF_X1 U2 ( .A(new_B[9]), .Z(n11) );
BUF_X1 U3 ( .A(new_B[17]), .Z(n9) );
BUF_X1 U4 ( .A(new_B[15]), .Z(n5) );
BUF_X1 U5 ( .A(new_B[5]), .Z(n12) );
BUF_X1 U6 ( .A(new_B[21]), .Z(n3) );
BUF_X1 U7 ( .A(new_B[6]), .Z(n4) );
CLKBUF_X1 U8 ( .A(new_B[23]), .Z(n6) );
CLKBUF_X1 U9 ( .A(new_B[13]), .Z(n13) );
CLKBUF_X1 U10 ( .A(new_B[0]), .Z(n10) );
CLKBUF_X1 U11 ( .A(new_B[10]), .Z(n8) );
endmodule
module predictor_2_15 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_14 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_13 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_12 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_11 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_10 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_9 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_8 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_7 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_6 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_5 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_4 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_3 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_2 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module predictor_2_1 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n1, n2, n5, n7, n8, n9, n10;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n7), .CK(clock), .RN(n2), .Q(n1), .QN(n5) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n8), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n8) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n7) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n10) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n9) );
OAI21_X1 U6 ( .B1(n10), .B2(n1), .A(n9), .ZN(N11) );
OAI21_X1 U5 ( .B1(n5), .B2(n10), .A(n9), .ZN(N12) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module mux41_1 ( IN0, IN1, IN2, IN3, CTRL, OUT1 );
input [31:0] IN0;
input [31:0] IN1;
input [31:0] IN2;
input [31:0] IN3;
input [1:0] CTRL;
output [31:0] OUT1;
wire n1, n6, n7, n8, n21, n22, n23, n24, n27, n28, n29, n30, n39, n40, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132,
n133, n134, n135, n136, n137, n138;
AOI22_X1 U1 ( .A1(IN1[28]), .A2(n71), .B1(IN0[28]), .B2(n73), .ZN(n1) );
NAND2_X1 U2 ( .A1(n8), .A2(n1), .ZN(OUT1[28]) );
BUF_X2 U3 ( .A(n83), .Z(n73) );
BUF_X2 U4 ( .A(n83), .Z(n74) );
BUF_X2 U5 ( .A(n82), .Z(n71) );
CLKBUF_X3 U6 ( .A(n83), .Z(n75) );
CLKBUF_X3 U7 ( .A(n82), .Z(n72) );
BUF_X2 U8 ( .A(n82), .Z(n40) );
BUF_X2 U9 ( .A(n84), .Z(n78) );
BUF_X2 U10 ( .A(n6), .Z(n79) );
BUF_X2 U11 ( .A(n6), .Z(n80) );
BUF_X2 U12 ( .A(n6), .Z(n7) );
BUF_X2 U13 ( .A(n84), .Z(n76) );
BUF_X2 U14 ( .A(n84), .Z(n77) );
AND2_X1 U15 ( .A1(CTRL[1]), .A2(n81), .ZN(n6) );
AND2_X1 U16 ( .A1(CTRL[1]), .A2(CTRL[0]), .ZN(n84) );
INV_X1 U17 ( .A(CTRL[0]), .ZN(n81) );
AOI22_X1 U18 ( .A1(n77), .A2(IN3[23]), .B1(n79), .B2(IN2[23]), .ZN(n23) );
AOI22_X1 U19 ( .A1(n80), .A2(IN2[30]), .B1(n78), .B2(IN3[30]), .ZN(n28) );
AOI22_X1 U20 ( .A1(n76), .A2(IN3[10]), .B1(n80), .B2(IN2[10]), .ZN(n87) );
AOI22_X1 U21 ( .A1(n76), .A2(IN3[17]), .B1(n79), .B2(IN2[17]), .ZN(n101) );
AOI22_X1 U22 ( .A1(n77), .A2(IN3[4]), .B1(n7), .B2(IN2[4]), .ZN(n127) );
AOI22_X1 U23 ( .A1(n77), .A2(IN3[24]), .B1(n80), .B2(IN2[24]), .ZN(n115) );
AOI22_X1 U24 ( .A1(n77), .A2(IN3[21]), .B1(n79), .B2(IN2[21]), .ZN(n111) );
AOI22_X1 U25 ( .A1(n77), .A2(IN3[3]), .B1(n79), .B2(IN2[3]), .ZN(n125) );
AOI22_X1 U26 ( .A1(n78), .A2(IN3[9]), .B1(n79), .B2(IN2[9]), .ZN(n137) );
AOI22_X1 U27 ( .A1(n76), .A2(IN3[13]), .B1(n80), .B2(IN2[13]), .ZN(n93) );
AOI22_X1 U28 ( .A1(n76), .A2(IN3[14]), .B1(n7), .B2(IN2[14]), .ZN(n95) );
NAND3_X1 U29 ( .A1(n23), .A2(n22), .A3(n21), .ZN(OUT1[23]) );
AOI22_X1 U30 ( .A1(n80), .A2(IN2[28]), .B1(n78), .B2(IN3[28]), .ZN(n8) );
NAND2_X1 U31 ( .A1(n74), .A2(IN0[23]), .ZN(n22) );
NAND2_X1 U32 ( .A1(n40), .A2(IN1[23]), .ZN(n21) );
NAND2_X1 U33 ( .A1(n27), .A2(n24), .ZN(OUT1[29]) );
NAND2_X1 U34 ( .A1(n29), .A2(n28), .ZN(OUT1[30]) );
NAND2_X1 U35 ( .A1(n39), .A2(n30), .ZN(OUT1[31]) );
NOR2_X1 U36 ( .A1(CTRL[1]), .A2(CTRL[0]), .ZN(n83) );
AOI22_X1 U37 ( .A1(n72), .A2(IN1[29]), .B1(n73), .B2(IN0[29]), .ZN(n27) );
AOI22_X1 U38 ( .A1(n7), .A2(IN2[29]), .B1(n78), .B2(IN3[29]), .ZN(n24) );
AOI22_X1 U39 ( .A1(n72), .A2(IN1[30]), .B1(n74), .B2(IN0[30]), .ZN(n29) );
AOI22_X1 U40 ( .A1(n71), .A2(IN1[31]), .B1(n75), .B2(IN0[31]), .ZN(n39) );
AOI22_X1 U41 ( .A1(n7), .A2(IN2[31]), .B1(n78), .B2(IN3[31]), .ZN(n30) );
NAND2_X1 U42 ( .A1(n93), .A2(n94), .ZN(OUT1[13]) );
NAND2_X1 U43 ( .A1(n96), .A2(n95), .ZN(OUT1[14]) );
NAND2_X1 U44 ( .A1(n98), .A2(n97), .ZN(OUT1[15]) );
NAND2_X1 U45 ( .A1(n86), .A2(n85), .ZN(OUT1[0]) );
NAND2_X1 U46 ( .A1(n100), .A2(n99), .ZN(OUT1[16]) );
NAND2_X1 U47 ( .A1(n122), .A2(n121), .ZN(OUT1[27]) );
NAND2_X1 U48 ( .A1(n92), .A2(n91), .ZN(OUT1[12]) );
NAND2_X1 U49 ( .A1(n90), .A2(n89), .ZN(OUT1[11]) );
NAND2_X1 U50 ( .A1(n87), .A2(n88), .ZN(OUT1[10]) );
NAND2_X1 U51 ( .A1(n118), .A2(n117), .ZN(OUT1[25]) );
NAND2_X1 U52 ( .A1(n112), .A2(n111), .ZN(OUT1[21]) );
NAND2_X1 U53 ( .A1(n108), .A2(n107), .ZN(OUT1[1]) );
NAND2_X1 U54 ( .A1(n120), .A2(n119), .ZN(OUT1[26]) );
NAND2_X1 U55 ( .A1(n116), .A2(n115), .ZN(OUT1[24]) );
NAND2_X1 U56 ( .A1(n114), .A2(n113), .ZN(OUT1[22]) );
NAND2_X1 U57 ( .A1(n110), .A2(n109), .ZN(OUT1[20]) );
NAND2_X1 U58 ( .A1(n102), .A2(n101), .ZN(OUT1[17]) );
NAND2_X1 U59 ( .A1(n106), .A2(n105), .ZN(OUT1[19]) );
NAND2_X1 U60 ( .A1(n138), .A2(n137), .ZN(OUT1[9]) );
NAND2_X1 U61 ( .A1(n134), .A2(n133), .ZN(OUT1[7]) );
NAND2_X1 U62 ( .A1(n130), .A2(n129), .ZN(OUT1[5]) );
NAND2_X1 U63 ( .A1(n126), .A2(n125), .ZN(OUT1[3]) );
NAND2_X1 U64 ( .A1(n136), .A2(n135), .ZN(OUT1[8]) );
NAND2_X1 U65 ( .A1(n132), .A2(n131), .ZN(OUT1[6]) );
NAND2_X1 U66 ( .A1(n128), .A2(n127), .ZN(OUT1[4]) );
AOI22_X1 U67 ( .A1(n71), .A2(IN1[11]), .B1(n73), .B2(IN0[11]), .ZN(n90) );
AOI22_X1 U68 ( .A1(n40), .A2(IN1[10]), .B1(n74), .B2(IN0[10]), .ZN(n88) );
AOI22_X1 U69 ( .A1(n71), .A2(IN1[15]), .B1(n75), .B2(IN0[15]), .ZN(n98) );
AOI22_X1 U70 ( .A1(n40), .A2(IN1[13]), .B1(n73), .B2(IN0[13]), .ZN(n94) );
AOI22_X1 U71 ( .A1(n71), .A2(IN1[0]), .B1(n74), .B2(IN0[0]), .ZN(n86) );
AOI22_X1 U72 ( .A1(n40), .A2(IN1[12]), .B1(n73), .B2(IN0[12]), .ZN(n92) );
AOI22_X1 U73 ( .A1(n71), .A2(IN1[14]), .B1(n74), .B2(IN0[14]), .ZN(n96) );
AOI22_X1 U74 ( .A1(n40), .A2(IN1[16]), .B1(n73), .B2(IN0[16]), .ZN(n100) );
AOI22_X1 U75 ( .A1(n76), .A2(IN3[0]), .B1(n80), .B2(IN2[0]), .ZN(n85) );
AOI22_X1 U76 ( .A1(n76), .A2(IN3[12]), .B1(n79), .B2(IN2[12]), .ZN(n91) );
AOI22_X1 U77 ( .A1(n76), .A2(IN3[15]), .B1(n80), .B2(IN2[15]), .ZN(n97) );
AOI22_X1 U78 ( .A1(n76), .A2(IN3[11]), .B1(n79), .B2(IN2[11]), .ZN(n89) );
AOI22_X1 U79 ( .A1(n76), .A2(IN3[16]), .B1(n7), .B2(IN2[16]), .ZN(n99) );
AOI22_X1 U80 ( .A1(n40), .A2(IN1[2]), .B1(n75), .B2(IN0[2]), .ZN(n124) );
AOI22_X1 U81 ( .A1(n72), .A2(IN1[9]), .B1(n75), .B2(IN0[9]), .ZN(n138) );
AOI22_X1 U82 ( .A1(n40), .A2(IN1[6]), .B1(n75), .B2(IN0[6]), .ZN(n132) );
AOI22_X1 U83 ( .A1(n72), .A2(IN1[7]), .B1(n73), .B2(IN0[7]), .ZN(n134) );
AOI22_X1 U84 ( .A1(n71), .A2(IN1[8]), .B1(n75), .B2(IN0[8]), .ZN(n136) );
AOI22_X1 U85 ( .A1(n71), .A2(IN1[5]), .B1(n75), .B2(IN0[5]), .ZN(n130) );
AOI22_X1 U86 ( .A1(n72), .A2(IN1[3]), .B1(n74), .B2(IN0[3]), .ZN(n126) );
AOI22_X1 U87 ( .A1(n71), .A2(IN1[4]), .B1(n73), .B2(IN0[4]), .ZN(n128) );
AOI22_X1 U88 ( .A1(n40), .A2(IN1[18]), .B1(n75), .B2(IN0[18]), .ZN(n104) );
AOI22_X1 U89 ( .A1(n71), .A2(IN1[1]), .B1(n73), .B2(IN0[1]), .ZN(n108) );
AOI22_X1 U90 ( .A1(n40), .A2(IN1[27]), .B1(n75), .B2(IN0[27]), .ZN(n122) );
AOI22_X1 U91 ( .A1(n72), .A2(IN1[25]), .B1(n73), .B2(IN0[25]), .ZN(n118) );
AOI22_X1 U92 ( .A1(n72), .A2(IN1[17]), .B1(n74), .B2(IN0[17]), .ZN(n102) );
AOI22_X1 U93 ( .A1(n40), .A2(IN1[21]), .B1(n74), .B2(IN0[21]), .ZN(n112) );
AOI22_X1 U94 ( .A1(n72), .A2(IN1[19]), .B1(n75), .B2(IN0[19]), .ZN(n106) );
AOI22_X1 U95 ( .A1(n72), .A2(IN1[24]), .B1(n75), .B2(IN0[24]), .ZN(n116) );
AOI22_X1 U96 ( .A1(n72), .A2(IN1[26]), .B1(n73), .B2(IN0[26]), .ZN(n120) );
AOI22_X1 U97 ( .A1(n72), .A2(IN1[20]), .B1(n74), .B2(IN0[20]), .ZN(n110) );
AOI22_X1 U98 ( .A1(n40), .A2(IN1[22]), .B1(n74), .B2(IN0[22]), .ZN(n114) );
NOR2_X1 U99 ( .A1(n81), .A2(CTRL[1]), .ZN(n82) );
NAND2_X1 U100 ( .A1(n104), .A2(n103), .ZN(OUT1[18]) );
NAND2_X1 U101 ( .A1(n124), .A2(n123), .ZN(OUT1[2]) );
AOI22_X1 U102 ( .A1(n76), .A2(IN3[1]), .B1(n80), .B2(IN2[1]), .ZN(n107) );
AOI22_X1 U103 ( .A1(n76), .A2(IN3[19]), .B1(n7), .B2(IN2[19]), .ZN(n105) );
AOI22_X1 U104 ( .A1(n77), .A2(IN3[27]), .B1(n80), .B2(IN2[27]), .ZN(n121) );
AOI22_X1 U105 ( .A1(n77), .A2(IN3[25]), .B1(n80), .B2(IN2[25]), .ZN(n117) );
AOI22_X1 U106 ( .A1(n76), .A2(IN3[18]), .B1(n7), .B2(IN2[18]), .ZN(n103) );
AOI22_X1 U107 ( .A1(n77), .A2(IN3[20]), .B1(n7), .B2(IN2[20]), .ZN(n109) );
AOI22_X1 U108 ( .A1(n77), .A2(IN3[22]), .B1(n79), .B2(IN2[22]), .ZN(n113) );
AOI22_X1 U109 ( .A1(n77), .A2(IN3[26]), .B1(n7), .B2(IN2[26]), .ZN(n119) );
AOI22_X1 U110 ( .A1(n78), .A2(IN3[7]), .B1(n80), .B2(IN2[7]), .ZN(n133) );
AOI22_X1 U111 ( .A1(n77), .A2(IN3[5]), .B1(n7), .B2(IN2[5]), .ZN(n129) );
AOI22_X1 U112 ( .A1(n77), .A2(IN3[2]), .B1(n7), .B2(IN2[2]), .ZN(n123) );
AOI22_X1 U113 ( .A1(n78), .A2(IN3[8]), .B1(n80), .B2(IN2[8]), .ZN(n135) );
AOI22_X1 U114 ( .A1(n78), .A2(IN3[6]), .B1(n7), .B2(IN2[6]), .ZN(n131) );
endmodule
module ff32_en_1 ( D, en, clk, rst, Q );
input [31:0] D;
output [31:0] Q;
input en, clk, rst;
wire net3606, n32;
DFFR_X1 \Q_reg[31] ( .D(D[31]), .CK(net3606), .RN(n32), .Q(Q[31]) );
DFFR_X1 \Q_reg[30] ( .D(D[30]), .CK(net3606), .RN(n32), .Q(Q[30]) );
DFFR_X1 \Q_reg[29] ( .D(D[29]), .CK(net3606), .RN(n32), .Q(Q[29]) );
DFFR_X1 \Q_reg[28] ( .D(D[28]), .CK(net3606), .RN(n32), .Q(Q[28]) );
DFFR_X1 \Q_reg[27] ( .D(D[27]), .CK(net3606), .RN(n32), .Q(Q[27]) );
DFFR_X1 \Q_reg[26] ( .D(D[26]), .CK(net3606), .RN(n32), .Q(Q[26]) );
DFFR_X1 \Q_reg[25] ( .D(D[25]), .CK(net3606), .RN(n32), .Q(Q[25]) );
DFFR_X1 \Q_reg[24] ( .D(D[24]), .CK(net3606), .RN(n32), .Q(Q[24]) );
DFFR_X1 \Q_reg[23] ( .D(D[23]), .CK(net3606), .RN(n32), .Q(Q[23]) );
DFFR_X1 \Q_reg[22] ( .D(D[22]), .CK(net3606), .RN(n32), .Q(Q[22]) );
DFFR_X1 \Q_reg[21] ( .D(D[21]), .CK(net3606), .RN(n32), .Q(Q[21]) );
DFFR_X1 \Q_reg[20] ( .D(D[20]), .CK(net3606), .RN(n32), .Q(Q[20]) );
DFFR_X1 \Q_reg[19] ( .D(D[19]), .CK(net3606), .RN(n32), .Q(Q[19]) );
DFFR_X1 \Q_reg[18] ( .D(D[18]), .CK(net3606), .RN(n32), .Q(Q[18]) );
DFFR_X1 \Q_reg[17] ( .D(D[17]), .CK(net3606), .RN(n32), .Q(Q[17]) );
DFFR_X1 \Q_reg[16] ( .D(D[16]), .CK(net3606), .RN(n32), .Q(Q[16]) );
DFFR_X1 \Q_reg[15] ( .D(D[15]), .CK(net3606), .RN(n32), .Q(Q[15]) );
DFFR_X1 \Q_reg[14] ( .D(D[14]), .CK(net3606), .RN(n32), .Q(Q[14]) );
DFFR_X1 \Q_reg[13] ( .D(D[13]), .CK(net3606), .RN(n32), .Q(Q[13]) );
DFFR_X1 \Q_reg[12] ( .D(D[12]), .CK(net3606), .RN(n32), .Q(Q[12]) );
DFFR_X1 \Q_reg[11] ( .D(D[11]), .CK(net3606), .RN(n32), .Q(Q[11]) );
DFFR_X1 \Q_reg[10] ( .D(D[10]), .CK(net3606), .RN(n32), .Q(Q[10]) );
DFFR_X1 \Q_reg[9] ( .D(D[9]), .CK(net3606), .RN(n32), .Q(Q[9]) );
DFFR_X1 \Q_reg[8] ( .D(D[8]), .CK(net3606), .RN(n32), .Q(Q[8]) );
DFFR_X1 \Q_reg[7] ( .D(D[7]), .CK(net3606), .RN(n32), .Q(Q[7]) );
DFFR_X1 \Q_reg[6] ( .D(D[6]), .CK(net3606), .RN(n32), .Q(Q[6]) );
DFFR_X1 \Q_reg[5] ( .D(D[5]), .CK(net3606), .RN(n32), .Q(Q[5]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(net3606), .RN(n32), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(net3606), .RN(n32), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(net3606), .RN(n32), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(net3606), .RN(n32), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(net3606), .RN(n32), .Q(Q[0]) );
SNPS_CLOCK_GATE_HIGH_ff32_en_1 clk_gate_Q_reg ( .CLK(clk), .EN(en), .ENCLK(
net3606) );
INV_X2 U2 ( .A(rst), .ZN(n32) );
endmodule
module FA_0 ( A, B, Ci, S, Co );
input A, B, Ci;
output S, Co;
XOR2_X1 U1 ( .A(B), .B(A), .Z(S) );
AND2_X1 U2 ( .A1(B), .A2(A), .ZN(Co) );
endmodule
module mux21_SIZE4_0 ( IN0, IN1, CTRL, OUT1 );
input [3:0] IN0;
input [3:0] IN1;
output [3:0] OUT1;
input CTRL;
assign OUT1[3] = IN0[3];
assign OUT1[2] = IN0[2];
assign OUT1[1] = IN0[1];
assign OUT1[0] = IN0[0];
endmodule
module RCA_N4_0 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:1] CTMP;
FA_0 FAI_1 ( .A(A[0]), .B(B[0]), .Ci(1'b0), .S(S[0]), .Co(CTMP[1]) );
FA_127 FAI_2 ( .A(A[1]), .B(B[1]), .Ci(CTMP[1]), .S(S[1]), .Co(CTMP[2]) );
FA_126 FAI_3 ( .A(A[2]), .B(B[2]), .Ci(CTMP[2]), .S(S[2]), .Co(CTMP[3]) );
FA_125 FAI_4 ( .A(A[3]), .B(B[3]), .Ci(CTMP[3]), .S(S[3]) );
endmodule
module shift_thirdLevel ( sel, A, Y );
input [2:0] sel;
input [38:0] A;
output [31:0] Y;
wire n2, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n1, n3, n71,
n72, n73, n74, n75, n76;
MUX2_X1 U7 ( .A(n7), .B(n6), .S(n71), .Z(Y[30]) );
MUX2_X1 U10 ( .A(n6), .B(n9), .S(n71), .Z(Y[29]) );
MUX2_X1 U13 ( .A(n9), .B(n11), .S(sel[0]), .Z(Y[28]) );
MUX2_X1 U16 ( .A(n11), .B(n13), .S(n71), .Z(Y[27]) );
MUX2_X1 U19 ( .A(n13), .B(n15), .S(n71), .Z(Y[26]) );
MUX2_X1 U22 ( .A(n15), .B(n17), .S(n3), .Z(Y[25]) );
MUX2_X1 U25 ( .A(n17), .B(n19), .S(n3), .Z(Y[24]) );
MUX2_X1 U28 ( .A(n19), .B(n21), .S(n3), .Z(Y[23]) );
MUX2_X1 U31 ( .A(n21), .B(n23), .S(sel[0]), .Z(Y[22]) );
MUX2_X1 U34 ( .A(n23), .B(n25), .S(sel[0]), .Z(Y[21]) );
MUX2_X1 U37 ( .A(n25), .B(n27), .S(sel[0]), .Z(Y[20]) );
MUX2_X1 U40 ( .A(n27), .B(n29), .S(n71), .Z(Y[19]) );
MUX2_X1 U43 ( .A(n29), .B(n31), .S(n3), .Z(Y[18]) );
MUX2_X1 U46 ( .A(n31), .B(n33), .S(n3), .Z(Y[17]) );
MUX2_X1 U49 ( .A(n33), .B(n35), .S(n3), .Z(Y[16]) );
MUX2_X1 U52 ( .A(n35), .B(n37), .S(n3), .Z(Y[15]) );
MUX2_X1 U55 ( .A(n37), .B(n39), .S(n3), .Z(Y[14]) );
MUX2_X1 U58 ( .A(n39), .B(n41), .S(n3), .Z(Y[13]) );
MUX2_X1 U61 ( .A(n41), .B(n43), .S(n3), .Z(Y[12]) );
MUX2_X1 U64 ( .A(n43), .B(n45), .S(n3), .Z(Y[11]) );
MUX2_X1 U67 ( .A(n45), .B(n47), .S(n3), .Z(Y[10]) );
MUX2_X1 U70 ( .A(n47), .B(n49), .S(n3), .Z(Y[9]) );
MUX2_X1 U73 ( .A(n49), .B(n51), .S(n3), .Z(Y[8]) );
MUX2_X1 U76 ( .A(n51), .B(n53), .S(n3), .Z(Y[7]) );
MUX2_X1 U79 ( .A(n53), .B(n55), .S(n71), .Z(Y[6]) );
MUX2_X1 U82 ( .A(n55), .B(n57), .S(n71), .Z(Y[5]) );
MUX2_X1 U85 ( .A(n57), .B(n59), .S(n71), .Z(Y[4]) );
MUX2_X1 U88 ( .A(n59), .B(n61), .S(n71), .Z(Y[3]) );
MUX2_X1 U92 ( .A(n63), .B(n64), .S(n71), .Z(Y[1]) );
MUX2_X1 U97 ( .A(n64), .B(n67), .S(n71), .Z(Y[0]) );
MUX2_X1 U102 ( .A(n70), .B(n7), .S(n71), .Z(Y[31]) );
AOI22_X1 U93 ( .A1(n75), .A2(A[1]), .B1(A[5]), .B2(n74), .ZN(n65) );
AOI22_X1 U86 ( .A1(n75), .A2(A[3]), .B1(A[7]), .B2(n74), .ZN(n60) );
AOI22_X1 U94 ( .A1(n73), .A2(n65), .B1(n60), .B2(n1), .ZN(n64) );
AOI22_X1 U95 ( .A1(n75), .A2(A[0]), .B1(A[4]), .B2(n74), .ZN(n66) );
AOI22_X1 U89 ( .A1(n75), .A2(A[2]), .B1(A[6]), .B2(n74), .ZN(n62) );
AOI22_X1 U96 ( .A1(n73), .A2(n66), .B1(n62), .B2(n1), .ZN(n67) );
AOI22_X1 U71 ( .A1(n75), .A2(A[8]), .B1(A[12]), .B2(n74), .ZN(n50) );
AOI22_X1 U65 ( .A1(n75), .A2(A[10]), .B1(A[14]), .B2(n74), .ZN(n46) );
AOI22_X1 U72 ( .A1(n73), .A2(n50), .B1(n46), .B2(n1), .ZN(n51) );
AOI22_X1 U74 ( .A1(n76), .A2(A[7]), .B1(A[11]), .B2(n74), .ZN(n52) );
AOI22_X1 U68 ( .A1(n75), .A2(A[9]), .B1(A[13]), .B2(n74), .ZN(n48) );
AOI22_X1 U75 ( .A1(n73), .A2(n52), .B1(n48), .B2(n1), .ZN(n53) );
AOI22_X1 U5 ( .A1(n75), .A2(A[30]), .B1(A[34]), .B2(n74), .ZN(n5) );
AOI22_X1 U2 ( .A1(sel[2]), .A2(A[32]), .B1(A[36]), .B2(n74), .ZN(n2) );
AOI22_X1 U6 ( .A1(n73), .A2(n5), .B1(n2), .B2(n72), .ZN(n6) );
AOI22_X1 U8 ( .A1(sel[2]), .A2(A[29]), .B1(A[33]), .B2(n74), .ZN(n8) );
AOI22_X1 U4 ( .A1(sel[2]), .A2(A[31]), .B1(A[35]), .B2(n74), .ZN(n4) );
AOI22_X1 U9 ( .A1(n73), .A2(n8), .B1(n4), .B2(n72), .ZN(n9) );
AOI22_X1 U23 ( .A1(n76), .A2(A[24]), .B1(A[28]), .B2(n74), .ZN(n18) );
AOI22_X1 U17 ( .A1(n76), .A2(A[26]), .B1(A[30]), .B2(n74), .ZN(n14) );
AOI22_X1 U24 ( .A1(n73), .A2(n18), .B1(n14), .B2(n72), .ZN(n19) );
AOI22_X1 U26 ( .A1(n75), .A2(A[23]), .B1(A[27]), .B2(n74), .ZN(n20) );
AOI22_X1 U20 ( .A1(n76), .A2(A[25]), .B1(A[29]), .B2(n74), .ZN(n16) );
AOI22_X1 U27 ( .A1(n73), .A2(n20), .B1(n16), .B2(n72), .ZN(n21) );
AOI22_X1 U47 ( .A1(n76), .A2(A[16]), .B1(A[20]), .B2(n74), .ZN(n34) );
AOI22_X1 U41 ( .A1(n76), .A2(A[18]), .B1(A[22]), .B2(n74), .ZN(n30) );
AOI22_X1 U48 ( .A1(n73), .A2(n34), .B1(n30), .B2(n1), .ZN(n35) );
AOI22_X1 U50 ( .A1(n76), .A2(A[15]), .B1(A[19]), .B2(n74), .ZN(n36) );
AOI22_X1 U44 ( .A1(n76), .A2(A[17]), .B1(A[21]), .B2(n74), .ZN(n32) );
AOI22_X1 U51 ( .A1(n73), .A2(n36), .B1(n32), .B2(n1), .ZN(n37) );
AOI22_X1 U35 ( .A1(n76), .A2(A[20]), .B1(A[24]), .B2(n74), .ZN(n26) );
AOI22_X1 U29 ( .A1(n76), .A2(A[22]), .B1(A[26]), .B2(n74), .ZN(n22) );
AOI22_X1 U36 ( .A1(n73), .A2(n26), .B1(n22), .B2(n72), .ZN(n27) );
AOI22_X1 U38 ( .A1(n76), .A2(A[19]), .B1(A[23]), .B2(n74), .ZN(n28) );
AOI22_X1 U32 ( .A1(n76), .A2(A[21]), .B1(A[25]), .B2(n74), .ZN(n24) );
AOI22_X1 U39 ( .A1(n73), .A2(n28), .B1(n24), .B2(n72), .ZN(n29) );
AOI22_X1 U42 ( .A1(n73), .A2(n30), .B1(n26), .B2(n1), .ZN(n31) );
AOI22_X1 U45 ( .A1(n73), .A2(n32), .B1(n28), .B2(n1), .ZN(n33) );
AOI22_X1 U11 ( .A1(sel[2]), .A2(A[28]), .B1(A[32]), .B2(n74), .ZN(n10) );
AOI22_X1 U18 ( .A1(n73), .A2(n14), .B1(n10), .B2(n72), .ZN(n15) );
AOI22_X1 U14 ( .A1(n76), .A2(A[27]), .B1(A[31]), .B2(n74), .ZN(n12) );
AOI22_X1 U21 ( .A1(n73), .A2(n16), .B1(n12), .B2(n72), .ZN(n17) );
AOI22_X1 U12 ( .A1(n73), .A2(n10), .B1(n5), .B2(n72), .ZN(n11) );
AOI22_X1 U15 ( .A1(n73), .A2(n12), .B1(n8), .B2(n72), .ZN(n13) );
AOI22_X1 U98 ( .A1(n75), .A2(A[33]), .B1(A[37]), .B2(n74), .ZN(n68) );
AOI22_X1 U99 ( .A1(n73), .A2(n4), .B1(n68), .B2(n1), .ZN(n7) );
AOI22_X1 U30 ( .A1(n73), .A2(n22), .B1(n18), .B2(n72), .ZN(n23) );
AOI22_X1 U33 ( .A1(n73), .A2(n24), .B1(n20), .B2(n72), .ZN(n25) );
AOI22_X1 U100 ( .A1(n75), .A2(A[34]), .B1(A[38]), .B2(n74), .ZN(n69) );
AOI22_X1 U101 ( .A1(sel[1]), .A2(n2), .B1(n69), .B2(n1), .ZN(n70) );
AOI22_X1 U53 ( .A1(n76), .A2(A[14]), .B1(A[18]), .B2(n74), .ZN(n38) );
AOI22_X1 U54 ( .A1(n73), .A2(n38), .B1(n34), .B2(n1), .ZN(n39) );
AOI22_X1 U83 ( .A1(n76), .A2(A[4]), .B1(A[8]), .B2(n74), .ZN(n58) );
AOI22_X1 U77 ( .A1(n76), .A2(A[6]), .B1(A[10]), .B2(n74), .ZN(n54) );
AOI22_X1 U84 ( .A1(n73), .A2(n58), .B1(n54), .B2(n1), .ZN(n59) );
AOI22_X1 U80 ( .A1(n75), .A2(A[5]), .B1(A[9]), .B2(n74), .ZN(n56) );
AOI22_X1 U87 ( .A1(n73), .A2(n60), .B1(n56), .B2(n1), .ZN(n61) );
AOI22_X1 U56 ( .A1(n76), .A2(A[13]), .B1(A[17]), .B2(n74), .ZN(n40) );
AOI22_X1 U57 ( .A1(n73), .A2(n40), .B1(n36), .B2(n1), .ZN(n41) );
AOI22_X1 U59 ( .A1(n75), .A2(A[12]), .B1(A[16]), .B2(n74), .ZN(n42) );
AOI22_X1 U60 ( .A1(sel[1]), .A2(n42), .B1(n38), .B2(n1), .ZN(n43) );
AOI22_X1 U62 ( .A1(n75), .A2(A[11]), .B1(A[15]), .B2(n74), .ZN(n44) );
AOI22_X1 U63 ( .A1(sel[1]), .A2(n44), .B1(n40), .B2(n1), .ZN(n45) );
AOI22_X1 U66 ( .A1(sel[1]), .A2(n46), .B1(n42), .B2(n1), .ZN(n47) );
AOI22_X1 U69 ( .A1(n73), .A2(n48), .B1(n44), .B2(n1), .ZN(n49) );
AOI22_X1 U90 ( .A1(n73), .A2(n62), .B1(n58), .B2(n1), .ZN(n63) );
AOI22_X1 U78 ( .A1(sel[1]), .A2(n54), .B1(n50), .B2(n1), .ZN(n55) );
AOI22_X1 U81 ( .A1(sel[1]), .A2(n56), .B1(n52), .B2(n1), .ZN(n57) );
MUX2_X1 U1 ( .A(n61), .B(n63), .S(n71), .Z(Y[2]) );
INV_X2 U3 ( .A(sel[2]), .ZN(n74) );
INV_X2 U91 ( .A(n73), .ZN(n1) );
BUF_X1 U103 ( .A(sel[0]), .Z(n71) );
BUF_X1 U104 ( .A(sel[0]), .Z(n3) );
BUF_X1 U105 ( .A(sel[2]), .Z(n75) );
BUF_X1 U106 ( .A(sel[2]), .Z(n76) );
BUF_X2 U107 ( .A(sel[1]), .Z(n73) );
INV_X1 U108 ( .A(n73), .ZN(n72) );
endmodule
module shift_secondLevel ( sel, mask00, mask08, mask16, Y );
input [1:0] sel;
input [38:0] mask00;
input [38:0] mask08;
input [38:0] mask16;
output [38:0] Y;
wire n42, n43, n44, n45, n46, n48, n49, n50, n51, n52, n53, n54, n55, n56,
n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70,
n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84,
n1, n3, n4, n12;
AOI222_X1 U57 ( .A1(n4), .A2(mask00[1]), .B1(n44), .B2(mask16[1]), .C1(n3),
.C2(mask08[1]), .ZN(n72) );
AOI222_X1 U11 ( .A1(n4), .A2(mask00[5]), .B1(n44), .B2(mask16[5]), .C1(n3),
.C2(mask08[5]), .ZN(n49) );
AOI222_X1 U15 ( .A1(n4), .A2(mask00[3]), .B1(n44), .B2(mask16[3]), .C1(n3),
.C2(mask08[3]), .ZN(n51) );
AOI222_X1 U79 ( .A1(n4), .A2(mask00[0]), .B1(n44), .B2(mask16[0]), .C1(n3),
.C2(mask08[0]), .ZN(n83) );
AOI222_X1 U13 ( .A1(n4), .A2(mask00[4]), .B1(n44), .B2(mask16[4]), .C1(n3),
.C2(mask08[4]), .ZN(n50) );
AOI222_X1 U35 ( .A1(n12), .A2(mask00[2]), .B1(n44), .B2(mask16[2]), .C1(n45),
.C2(mask08[2]), .ZN(n61) );
AOI222_X1 U9 ( .A1(n4), .A2(mask00[6]), .B1(n44), .B2(mask16[6]), .C1(n3),
.C2(mask08[6]), .ZN(n48) );
AOI222_X1 U5 ( .A1(n4), .A2(mask00[8]), .B1(n44), .B2(mask16[8]), .C1(n3),
.C2(mask08[8]), .ZN(n46) );
AOI222_X1 U73 ( .A1(n4), .A2(mask00[12]), .B1(n44), .B2(mask16[12]), .C1(n3),
.C2(mask08[12]), .ZN(n80) );
AOI222_X1 U77 ( .A1(n4), .A2(mask00[10]), .B1(n44), .B2(mask16[10]), .C1(n3),
.C2(mask08[10]), .ZN(n82) );
AOI222_X1 U69 ( .A1(n4), .A2(mask00[14]), .B1(n44), .B2(mask16[14]), .C1(n3),
.C2(mask08[14]), .ZN(n78) );
AOI222_X1 U75 ( .A1(n4), .A2(mask00[11]), .B1(n44), .B2(mask16[11]), .C1(n3),
.C2(mask08[11]), .ZN(n81) );
AOI222_X1 U3 ( .A1(n12), .A2(mask00[9]), .B1(n44), .B2(mask16[9]), .C1(n45),
.C2(mask08[9]), .ZN(n42) );
AOI222_X1 U71 ( .A1(n4), .A2(mask00[13]), .B1(n44), .B2(mask16[13]), .C1(n3),
.C2(mask08[13]), .ZN(n79) );
AOI222_X1 U33 ( .A1(n12), .A2(mask00[30]), .B1(n44), .B2(mask16[30]), .C1(
n45), .C2(mask08[30]), .ZN(n60) );
AOI222_X1 U25 ( .A1(n4), .A2(mask00[34]), .B1(n44), .B2(mask16[34]), .C1(n3),
.C2(mask08[34]), .ZN(n56) );
AOI222_X1 U29 ( .A1(n4), .A2(mask00[32]), .B1(n44), .B2(mask16[32]), .C1(n3),
.C2(mask08[32]), .ZN(n58) );
AOI222_X1 U21 ( .A1(n4), .A2(mask00[36]), .B1(n44), .B2(mask16[36]), .C1(n3),
.C2(mask08[36]), .ZN(n54) );
AOI222_X1 U37 ( .A1(n12), .A2(mask00[29]), .B1(n44), .B2(mask16[29]), .C1(
n45), .C2(mask08[29]), .ZN(n62) );
AOI222_X1 U27 ( .A1(n4), .A2(mask00[33]), .B1(n44), .B2(mask16[33]), .C1(n3),
.C2(mask08[33]), .ZN(n57) );
AOI222_X1 U31 ( .A1(n4), .A2(mask00[31]), .B1(n44), .B2(mask16[31]), .C1(n3),
.C2(mask08[31]), .ZN(n59) );
AOI222_X1 U23 ( .A1(n4), .A2(mask00[35]), .B1(n44), .B2(mask16[35]), .C1(n3),
.C2(mask08[35]), .ZN(n55) );
AOI222_X1 U47 ( .A1(n12), .A2(mask00[24]), .B1(n44), .B2(mask16[24]), .C1(
n45), .C2(mask08[24]), .ZN(n67) );
AOI222_X1 U39 ( .A1(n12), .A2(mask00[28]), .B1(n44), .B2(mask16[28]), .C1(
n45), .C2(mask08[28]), .ZN(n63) );
AOI222_X1 U43 ( .A1(n12), .A2(mask00[26]), .B1(n44), .B2(mask16[26]), .C1(
n45), .C2(mask08[26]), .ZN(n65) );
AOI222_X1 U49 ( .A1(n12), .A2(mask00[23]), .B1(n44), .B2(mask16[23]), .C1(
n45), .C2(mask08[23]), .ZN(n68) );
AOI222_X1 U41 ( .A1(n12), .A2(mask00[27]), .B1(n44), .B2(mask16[27]), .C1(
n45), .C2(mask08[27]), .ZN(n64) );
AOI222_X1 U45 ( .A1(n12), .A2(mask00[25]), .B1(n44), .B2(mask16[25]), .C1(
n45), .C2(mask08[25]), .ZN(n66) );
AOI222_X1 U65 ( .A1(n4), .A2(mask00[16]), .B1(n44), .B2(mask16[16]), .C1(n3),
.C2(mask08[16]), .ZN(n76) );
AOI222_X1 U55 ( .A1(n12), .A2(mask00[20]), .B1(n44), .B2(mask16[20]), .C1(
n45), .C2(mask08[20]), .ZN(n71) );
AOI222_X1 U61 ( .A1(n4), .A2(mask00[18]), .B1(n44), .B2(mask16[18]), .C1(n3),
.C2(mask08[18]), .ZN(n74) );
AOI222_X1 U51 ( .A1(n12), .A2(mask00[22]), .B1(n44), .B2(mask16[22]), .C1(
n45), .C2(mask08[22]), .ZN(n69) );
AOI222_X1 U67 ( .A1(n4), .A2(mask00[15]), .B1(n44), .B2(mask16[15]), .C1(n3),
.C2(mask08[15]), .ZN(n77) );
AOI222_X1 U59 ( .A1(n4), .A2(mask00[19]), .B1(n44), .B2(mask16[19]), .C1(n3),
.C2(mask08[19]), .ZN(n73) );
AOI222_X1 U63 ( .A1(n4), .A2(mask00[17]), .B1(n44), .B2(mask16[17]), .C1(n3),
.C2(mask08[17]), .ZN(n75) );
AOI222_X1 U53 ( .A1(n12), .A2(mask00[21]), .B1(n44), .B2(mask16[21]), .C1(
n45), .C2(mask08[21]), .ZN(n70) );
AOI222_X1 U19 ( .A1(n4), .A2(mask00[37]), .B1(n44), .B2(mask16[37]), .C1(n3),
.C2(mask08[37]), .ZN(n53) );
AOI222_X1 U17 ( .A1(n4), .A2(mask00[38]), .B1(n44), .B2(mask16[38]), .C1(n3),
.C2(mask08[38]), .ZN(n52) );
INV_X1 U82 ( .A(sel[0]), .ZN(n84) );
INV_X1 U56 ( .A(n72), .ZN(Y[1]) );
INV_X1 U10 ( .A(n49), .ZN(Y[5]) );
INV_X1 U14 ( .A(n51), .ZN(Y[3]) );
INV_X1 U78 ( .A(n83), .ZN(Y[0]) );
INV_X1 U12 ( .A(n50), .ZN(Y[4]) );
INV_X1 U34 ( .A(n61), .ZN(Y[2]) );
INV_X1 U8 ( .A(n48), .ZN(Y[6]) );
INV_X1 U4 ( .A(n46), .ZN(Y[8]) );
INV_X1 U72 ( .A(n80), .ZN(Y[12]) );
INV_X1 U76 ( .A(n82), .ZN(Y[10]) );
INV_X1 U68 ( .A(n78), .ZN(Y[14]) );
INV_X1 U74 ( .A(n81), .ZN(Y[11]) );
INV_X1 U2 ( .A(n42), .ZN(Y[9]) );
INV_X1 U70 ( .A(n79), .ZN(Y[13]) );
INV_X1 U32 ( .A(n60), .ZN(Y[30]) );
INV_X1 U24 ( .A(n56), .ZN(Y[34]) );
INV_X1 U28 ( .A(n58), .ZN(Y[32]) );
INV_X1 U20 ( .A(n54), .ZN(Y[36]) );
INV_X1 U36 ( .A(n62), .ZN(Y[29]) );
INV_X1 U26 ( .A(n57), .ZN(Y[33]) );
INV_X1 U30 ( .A(n59), .ZN(Y[31]) );
INV_X1 U22 ( .A(n55), .ZN(Y[35]) );
INV_X1 U46 ( .A(n67), .ZN(Y[24]) );
INV_X1 U38 ( .A(n63), .ZN(Y[28]) );
INV_X1 U42 ( .A(n65), .ZN(Y[26]) );
INV_X1 U48 ( .A(n68), .ZN(Y[23]) );
INV_X1 U40 ( .A(n64), .ZN(Y[27]) );
INV_X1 U44 ( .A(n66), .ZN(Y[25]) );
INV_X1 U64 ( .A(n76), .ZN(Y[16]) );
INV_X1 U54 ( .A(n71), .ZN(Y[20]) );
INV_X1 U60 ( .A(n74), .ZN(Y[18]) );
INV_X1 U50 ( .A(n69), .ZN(Y[22]) );
INV_X1 U66 ( .A(n77), .ZN(Y[15]) );
INV_X1 U58 ( .A(n73), .ZN(Y[19]) );
INV_X1 U62 ( .A(n75), .ZN(Y[17]) );
INV_X1 U52 ( .A(n70), .ZN(Y[21]) );
INV_X1 U18 ( .A(n53), .ZN(Y[37]) );
INV_X1 U16 ( .A(n52), .ZN(Y[38]) );
AOI222_X1 U6 ( .A1(mask00[7]), .A2(n4), .B1(mask08[7]), .B2(n3), .C1(
mask16[7]), .C2(n44), .ZN(n1) );
INV_X1 U7 ( .A(n1), .ZN(Y[7]) );
NOR2_X2 U80 ( .A1(sel[1]), .A2(n84), .ZN(n45) );
AND2_X4 U81 ( .A1(n84), .A2(sel[1]), .ZN(n44) );
BUF_X1 U83 ( .A(n45), .Z(n3) );
BUF_X1 U84 ( .A(n43), .Z(n12) );
BUF_X2 U85 ( .A(n43), .Z(n4) );
NOR2_X1 U86 ( .A1(sel[1]), .A2(sel[0]), .ZN(n43) );
endmodule
module shift_firstLevel ( A, sel, mask00, mask08, mask16 );
input [31:0] A;
input [1:0] sel;
output [38:0] mask00;
output [38:0] mask08;
output [38:0] mask16;
wire n37, n38, n39, n40, \mask16[17] , n42, n43, n44, n45, n46, n47, n48,
n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62,
n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76,
n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n89, n90, n91, n92,
n93, n94, n95, n96, n1, n2, n3;
assign mask08[30] = mask16[38];
assign mask08[29] = mask16[37];
assign mask08[28] = mask16[36];
assign mask08[27] = mask16[35];
assign mask08[26] = mask16[34];
assign mask08[25] = mask16[33];
assign mask08[24] = mask16[32];
assign mask08[14] = mask16[6];
assign mask08[13] = mask16[5];
assign mask08[12] = mask16[4];
assign mask08[11] = mask16[3];
assign mask08[10] = mask16[2];
assign mask08[9] = mask16[1];
assign mask08[8] = mask16[0];
assign mask16[16] = \mask16[17] ;
assign mask16[21] = \mask16[17] ;
assign mask16[22] = \mask16[17] ;
assign mask16[20] = \mask16[17] ;
assign mask16[19] = \mask16[17] ;
assign mask16[18] = \mask16[17] ;
assign mask16[17] = \mask16[17] ;
NAND2_X1 U134 ( .A1(sel[0]), .A2(A[17]), .ZN(n55) );
NAND2_X1 U59 ( .A1(sel[0]), .A2(A[9]), .ZN(n79) );
NAND2_X1 U122 ( .A1(sel[0]), .A2(A[21]), .ZN(n81) );
NAND2_X1 U146 ( .A1(sel[0]), .A2(A[13]), .ZN(n59) );
NAND2_X1 U129 ( .A1(sel[0]), .A2(A[19]), .ZN(n83) );
NAND2_X1 U152 ( .A1(sel[0]), .A2(A[11]), .ZN(n61) );
NOR2_X1 U157 ( .A1(sel[0]), .A2(sel[1]), .ZN(n86) );
NAND2_X1 U116 ( .A1(sel[0]), .A2(A[23]), .ZN(n39) );
NAND2_X1 U140 ( .A1(sel[0]), .A2(A[15]), .ZN(n57) );
NAND2_X1 U137 ( .A1(sel[0]), .A2(A[16]), .ZN(n56) );
NAND2_X1 U62 ( .A1(sel[0]), .A2(A[8]), .ZN(n85) );
NAND2_X1 U125 ( .A1(sel[0]), .A2(A[20]), .ZN(n82) );
NAND2_X1 U149 ( .A1(sel[0]), .A2(A[12]), .ZN(n60) );
NAND2_X1 U131 ( .A1(sel[0]), .A2(A[18]), .ZN(n84) );
NAND2_X1 U155 ( .A1(sel[0]), .A2(A[10]), .ZN(n71) );
NAND2_X1 U119 ( .A1(sel[0]), .A2(A[22]), .ZN(n80) );
NAND2_X1 U143 ( .A1(sel[0]), .A2(A[14]), .ZN(n58) );
NAND2_X1 U63 ( .A1(n2), .A2(A[1]), .ZN(n48) );
NAND2_X1 U61 ( .A1(n48), .A2(n85), .ZN(mask00[8]) );
NAND2_X1 U113 ( .A1(sel[0]), .A2(A[24]), .ZN(n38) );
NAND2_X1 U150 ( .A1(n2), .A2(A[5]), .ZN(n44) );
NAND2_X1 U148 ( .A1(n44), .A2(n60), .ZN(mask00[12]) );
NAND2_X1 U101 ( .A1(sel[0]), .A2(A[28]), .ZN(n52) );
NAND2_X1 U156 ( .A1(n86), .A2(A[3]), .ZN(n46) );
NAND2_X1 U154 ( .A1(n46), .A2(n71), .ZN(mask00[10]) );
NAND2_X1 U107 ( .A1(sel[0]), .A2(A[26]), .ZN(n54) );
NAND2_X1 U144 ( .A1(n2), .A2(A[7]), .ZN(n42) );
NAND2_X1 U142 ( .A1(n42), .A2(n58), .ZN(mask00[14]) );
NAND2_X1 U94 ( .A1(sel[0]), .A2(A[30]), .ZN(n50) );
NAND2_X1 U153 ( .A1(n2), .A2(A[4]), .ZN(n45) );
NAND2_X1 U151 ( .A1(n45), .A2(n61), .ZN(mask00[11]) );
NAND2_X1 U104 ( .A1(sel[0]), .A2(A[27]), .ZN(n53) );
NAND2_X1 U60 ( .A1(n2), .A2(A[2]), .ZN(n47) );
NAND2_X1 U58 ( .A1(n47), .A2(n79), .ZN(mask00[9]) );
NAND2_X1 U110 ( .A1(sel[0]), .A2(A[25]), .ZN(n37) );
NAND2_X1 U147 ( .A1(n2), .A2(A[6]), .ZN(n43) );
NAND2_X1 U145 ( .A1(n43), .A2(n59), .ZN(mask00[13]) );
NAND2_X1 U98 ( .A1(sel[0]), .A2(A[29]), .ZN(n51) );
NAND2_X1 U93 ( .A1(n2), .A2(A[23]), .ZN(n62) );
NAND2_X1 U92 ( .A1(n50), .A2(n62), .ZN(mask00[30]) );
NAND2_X1 U91 ( .A1(sel[0]), .A2(A[31]), .ZN(n78) );
NAND2_X1 U6 ( .A1(n42), .A2(n3), .ZN(mask16[30]) );
NAND2_X1 U118 ( .A1(n86), .A2(A[15]), .ZN(n70) );
NAND2_X1 U34 ( .A1(n70), .A2(n3), .ZN(mask16[38]) );
AOI21_X1 U81 ( .B1(A[27]), .B2(n2), .A(\mask16[17] ), .ZN(n93) );
NAND2_X1 U132 ( .A1(n86), .A2(A[11]), .ZN(n75) );
NAND2_X1 U39 ( .A1(n75), .A2(n3), .ZN(mask16[34]) );
NAND2_X1 U106 ( .A1(n2), .A2(A[19]), .ZN(n66) );
NAND2_X1 U30 ( .A1(n66), .A2(n3), .ZN(mask08[34]) );
AOI21_X1 U85 ( .B1(A[25]), .B2(n2), .A(\mask16[17] ), .ZN(n95) );
NAND2_X1 U138 ( .A1(n2), .A2(A[9]), .ZN(n77) );
NAND2_X1 U41 ( .A1(n77), .A2(n3), .ZN(mask16[32]) );
NAND2_X1 U112 ( .A1(n2), .A2(A[17]), .ZN(n68) );
NAND2_X1 U32 ( .A1(n68), .A2(n3), .ZN(mask08[32]) );
AOI21_X1 U77 ( .B1(A[29]), .B2(n2), .A(\mask16[17] ), .ZN(n91) );
NAND2_X1 U124 ( .A1(n86), .A2(A[13]), .ZN(n73) );
NAND2_X1 U37 ( .A1(n73), .A2(n3), .ZN(mask16[36]) );
NAND2_X1 U100 ( .A1(n2), .A2(A[21]), .ZN(n64) );
NAND2_X1 U28 ( .A1(n64), .A2(n3), .ZN(mask08[36]) );
NAND2_X1 U97 ( .A1(n2), .A2(A[22]), .ZN(n63) );
NAND2_X1 U96 ( .A1(n51), .A2(n63), .ZN(mask00[29]) );
NAND2_X1 U7 ( .A1(n43), .A2(n3), .ZN(mask16[29]) );
NAND2_X1 U121 ( .A1(n86), .A2(A[14]), .ZN(n72) );
NAND2_X1 U36 ( .A1(n72), .A2(n3), .ZN(mask16[37]) );
AOI21_X1 U83 ( .B1(A[26]), .B2(n2), .A(\mask16[17] ), .ZN(n94) );
NAND2_X1 U135 ( .A1(n2), .A2(A[10]), .ZN(n76) );
NAND2_X1 U40 ( .A1(n76), .A2(n3), .ZN(mask16[33]) );
NAND2_X1 U109 ( .A1(n2), .A2(A[18]), .ZN(n67) );
NAND2_X1 U31 ( .A1(n67), .A2(n3), .ZN(mask08[33]) );
AOI21_X1 U89 ( .B1(A[24]), .B2(n2), .A(mask16[15]), .ZN(n96) );
NAND2_X1 U141 ( .A1(n2), .A2(A[8]), .ZN(n40) );
NAND2_X1 U5 ( .A1(n40), .A2(n3), .ZN(mask16[31]) );
NAND2_X1 U115 ( .A1(n2), .A2(A[16]), .ZN(n69) );
NAND2_X1 U33 ( .A1(n69), .A2(n3), .ZN(mask08[31]) );
AOI21_X1 U79 ( .B1(A[28]), .B2(n2), .A(\mask16[17] ), .ZN(n92) );
NAND2_X1 U128 ( .A1(n86), .A2(A[12]), .ZN(n74) );
NAND2_X1 U38 ( .A1(n74), .A2(n3), .ZN(mask16[35]) );
NAND2_X1 U103 ( .A1(n2), .A2(A[20]), .ZN(n65) );
NAND2_X1 U29 ( .A1(n65), .A2(n3), .ZN(mask08[35]) );
NAND2_X1 U111 ( .A1(n38), .A2(n68), .ZN(mask00[24]) );
NAND2_X1 U12 ( .A1(n3), .A2(n48), .ZN(mask16[24]) );
NAND2_X1 U99 ( .A1(n52), .A2(n64), .ZN(mask00[28]) );
NAND2_X1 U8 ( .A1(n44), .A2(n3), .ZN(mask16[28]) );
NAND2_X1 U105 ( .A1(n54), .A2(n66), .ZN(mask00[26]) );
NAND2_X1 U10 ( .A1(n46), .A2(n3), .ZN(mask16[26]) );
NAND2_X1 U114 ( .A1(n39), .A2(n69), .ZN(mask00[23]) );
NAND2_X1 U13 ( .A1(n3), .A2(n49), .ZN(mask16[23]) );
NAND2_X1 U42 ( .A1(n40), .A2(n78), .ZN(mask08[23]) );
NAND2_X1 U102 ( .A1(n53), .A2(n65), .ZN(mask00[27]) );
NAND2_X1 U9 ( .A1(n45), .A2(n3), .ZN(mask16[27]) );
NAND2_X1 U108 ( .A1(n37), .A2(n67), .ZN(mask00[25]) );
NAND2_X1 U11 ( .A1(n3), .A2(n47), .ZN(mask16[25]) );
NAND2_X1 U136 ( .A1(n77), .A2(n56), .ZN(mask00[16]) );
NAND2_X1 U50 ( .A1(n38), .A2(n48), .ZN(mask08[16]) );
NAND2_X1 U123 ( .A1(n82), .A2(n73), .ZN(mask00[20]) );
NAND2_X1 U45 ( .A1(n44), .A2(n52), .ZN(mask08[20]) );
NAND2_X1 U130 ( .A1(n75), .A2(n84), .ZN(mask00[18]) );
NAND2_X1 U48 ( .A1(n46), .A2(n54), .ZN(mask08[18]) );
NAND2_X1 U117 ( .A1(n80), .A2(n70), .ZN(mask00[22]) );
NAND2_X1 U43 ( .A1(n42), .A2(n50), .ZN(mask08[22]) );
NAND2_X1 U139 ( .A1(n40), .A2(n57), .ZN(mask00[15]) );
NAND2_X1 U51 ( .A1(n39), .A2(n49), .ZN(mask08[15]) );
NAND2_X1 U127 ( .A1(n83), .A2(n74), .ZN(mask00[19]) );
NAND2_X1 U47 ( .A1(n45), .A2(n53), .ZN(mask08[19]) );
NAND2_X1 U133 ( .A1(n76), .A2(n55), .ZN(mask00[17]) );
NAND2_X1 U49 ( .A1(n37), .A2(n47), .ZN(mask08[17]) );
NAND2_X1 U120 ( .A1(n81), .A2(n72), .ZN(mask00[21]) );
NAND2_X1 U44 ( .A1(n43), .A2(n51), .ZN(mask08[21]) );
AOI21_X1 U75 ( .B1(A[30]), .B2(n2), .A(\mask16[17] ), .ZN(n90) );
NAND2_X1 U27 ( .A1(n63), .A2(n3), .ZN(mask08[37]) );
AOI21_X1 U73 ( .B1(A[31]), .B2(n2), .A(\mask16[17] ), .ZN(n89) );
NAND2_X1 U26 ( .A1(n62), .A2(n3), .ZN(mask08[38]) );
AND2_X1 U126 ( .A1(sel[0]), .A2(A[1]), .ZN(mask00[1]) );
INV_X1 U19 ( .A(n55), .ZN(mask16[1]) );
INV_X1 U46 ( .A(n79), .ZN(mask08[1]) );
AND2_X1 U69 ( .A1(sel[0]), .A2(A[5]), .ZN(mask00[5]) );
INV_X1 U53 ( .A(n81), .ZN(mask16[5]) );
INV_X1 U23 ( .A(n59), .ZN(mask08[5]) );
AND2_X1 U71 ( .A1(sel[0]), .A2(A[3]), .ZN(mask00[3]) );
INV_X1 U55 ( .A(n83), .ZN(mask16[3]) );
INV_X1 U25 ( .A(n61), .ZN(mask08[3]) );
INV_X1 U20 ( .A(n56), .ZN(mask16[0]) );
INV_X1 U57 ( .A(n85), .ZN(mask08[0]) );
AND2_X1 U70 ( .A1(sel[0]), .A2(A[4]), .ZN(mask00[4]) );
INV_X1 U54 ( .A(n82), .ZN(mask16[4]) );
INV_X1 U24 ( .A(n60), .ZN(mask08[4]) );
AND2_X1 U95 ( .A1(sel[0]), .A2(A[2]), .ZN(mask00[2]) );
INV_X1 U56 ( .A(n84), .ZN(mask16[2]) );
INV_X1 U35 ( .A(n71), .ZN(mask08[2]) );
AND2_X1 U68 ( .A1(sel[0]), .A2(A[6]), .ZN(mask00[6]) );
INV_X1 U52 ( .A(n80), .ZN(mask16[6]) );
INV_X1 U22 ( .A(n58), .ZN(mask08[6]) );
INV_X1 U3 ( .A(n38), .ZN(mask16[8]) );
INV_X1 U16 ( .A(n52), .ZN(mask16[12]) );
INV_X1 U18 ( .A(n54), .ZN(mask16[10]) );
INV_X1 U14 ( .A(n50), .ZN(mask16[14]) );
INV_X1 U17 ( .A(n53), .ZN(mask16[11]) );
INV_X1 U2 ( .A(n37), .ZN(mask16[9]) );
INV_X1 U15 ( .A(n51), .ZN(mask16[13]) );
INV_X1 U90 ( .A(n78), .ZN(mask16[15]) );
INV_X1 U80 ( .A(n93), .ZN(mask00[34]) );
INV_X1 U84 ( .A(n95), .ZN(mask00[32]) );
INV_X1 U76 ( .A(n91), .ZN(mask00[36]) );
INV_X1 U82 ( .A(n94), .ZN(mask00[33]) );
INV_X1 U88 ( .A(n96), .ZN(mask00[31]) );
INV_X1 U78 ( .A(n92), .ZN(mask00[35]) );
INV_X1 U74 ( .A(n90), .ZN(mask00[37]) );
INV_X1 U72 ( .A(n89), .ZN(mask00[38]) );
INV_X1 U4 ( .A(n57), .ZN(mask08[7]) );
INV_X1 U21 ( .A(n39), .ZN(mask16[7]) );
NAND2_X1 U64 ( .A1(sel[0]), .A2(A[7]), .ZN(n1) );
NAND2_X1 U65 ( .A1(n49), .A2(n1), .ZN(mask00[7]) );
AND2_X2 U66 ( .A1(sel[1]), .A2(mask16[15]), .ZN(\mask16[17] ) );
INV_X2 U67 ( .A(\mask16[17] ), .ZN(n3) );
BUF_X1 U86 ( .A(n86), .Z(n2) );
AND2_X1 U87 ( .A1(sel[0]), .A2(A[0]), .ZN(mask00[0]) );
NAND2_X1 U158 ( .A1(n2), .A2(A[0]), .ZN(n49) );
endmodule
module SNPS_CLOCK_GATE_HIGH_simple_booth_add_ext_N16 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3319, net3321, net3322, net3325;
assign net3319 = CLK;
assign ENCLK = net3321;
assign net3322 = EN;
DLL_X1 latch ( .D(net3322), .GN(net3319), .Q(net3325) );
AND2_X1 main_gate ( .A1(net3325), .A2(net3319), .ZN(net3321) );
endmodule
module piso_r_2_N32 ( Clock, ALOAD, D, SO );
input [31:0] D;
output [31:0] SO;
input Clock, ALOAD;
wire N3, N4;
DFF_X1 \tmp_reg[1] ( .D(N4), .CK(Clock), .Q(SO[1]) );
SDFF_X1 \tmp_reg[3] ( .D(SO[1]), .SI(D[3]), .SE(ALOAD), .CK(Clock), .Q(
SO[3]) );
SDFF_X1 \tmp_reg[5] ( .D(SO[3]), .SI(D[5]), .SE(ALOAD), .CK(Clock), .Q(
SO[5]) );
SDFF_X1 \tmp_reg[7] ( .D(SO[5]), .SI(D[7]), .SE(ALOAD), .CK(Clock), .Q(
SO[7]) );
SDFF_X1 \tmp_reg[9] ( .D(SO[7]), .SI(D[9]), .SE(ALOAD), .CK(Clock), .Q(
SO[9]) );
SDFF_X1 \tmp_reg[11] ( .D(SO[9]), .SI(D[11]), .SE(ALOAD), .CK(Clock), .Q(
SO[11]) );
SDFF_X1 \tmp_reg[13] ( .D(SO[11]), .SI(D[13]), .SE(ALOAD), .CK(Clock), .Q(
SO[13]) );
SDFF_X1 \tmp_reg[15] ( .D(SO[13]), .SI(D[15]), .SE(ALOAD), .CK(Clock), .Q(
SO[15]) );
SDFF_X1 \tmp_reg[17] ( .D(SO[15]), .SI(D[17]), .SE(ALOAD), .CK(Clock), .Q(
SO[17]) );
SDFF_X1 \tmp_reg[19] ( .D(SO[17]), .SI(D[19]), .SE(ALOAD), .CK(Clock), .Q(
SO[19]) );
SDFF_X1 \tmp_reg[21] ( .D(SO[19]), .SI(D[21]), .SE(ALOAD), .CK(Clock), .Q(
SO[21]) );
SDFF_X1 \tmp_reg[23] ( .D(SO[21]), .SI(D[23]), .SE(ALOAD), .CK(Clock), .Q(
SO[23]) );
SDFF_X1 \tmp_reg[25] ( .D(SO[23]), .SI(D[25]), .SE(ALOAD), .CK(Clock), .Q(
SO[25]) );
SDFF_X1 \tmp_reg[27] ( .D(SO[25]), .SI(D[27]), .SE(ALOAD), .CK(Clock), .Q(
SO[27]) );
SDFF_X1 \tmp_reg[29] ( .D(SO[27]), .SI(D[29]), .SE(ALOAD), .CK(Clock), .Q(
SO[29]) );
SDFF_X1 \tmp_reg[31] ( .D(SO[29]), .SI(D[31]), .SE(ALOAD), .CK(Clock), .Q(
SO[31]) );
DFF_X1 \tmp_reg[0] ( .D(N3), .CK(Clock), .Q(SO[0]) );
SDFF_X1 \tmp_reg[2] ( .D(SO[0]), .SI(D[2]), .SE(ALOAD), .CK(Clock), .Q(
SO[2]) );
SDFF_X1 \tmp_reg[4] ( .D(SO[2]), .SI(D[4]), .SE(ALOAD), .CK(Clock), .Q(
SO[4]) );
SDFF_X1 \tmp_reg[6] ( .D(SO[4]), .SI(D[6]), .SE(ALOAD), .CK(Clock), .Q(
SO[6]) );
SDFF_X1 \tmp_reg[8] ( .D(SO[6]), .SI(D[8]), .SE(ALOAD), .CK(Clock), .Q(
SO[8]) );
SDFF_X1 \tmp_reg[10] ( .D(SO[8]), .SI(D[10]), .SE(ALOAD), .CK(Clock), .Q(
SO[10]) );
SDFF_X1 \tmp_reg[12] ( .D(SO[10]), .SI(D[12]), .SE(ALOAD), .CK(Clock), .Q(
SO[12]) );
SDFF_X1 \tmp_reg[14] ( .D(SO[12]), .SI(D[14]), .SE(ALOAD), .CK(Clock), .Q(
SO[14]) );
SDFF_X1 \tmp_reg[16] ( .D(SO[14]), .SI(D[16]), .SE(ALOAD), .CK(Clock), .Q(
SO[16]) );
SDFF_X1 \tmp_reg[18] ( .D(SO[16]), .SI(D[18]), .SE(ALOAD), .CK(Clock), .Q(
SO[18]) );
SDFF_X1 \tmp_reg[20] ( .D(SO[18]), .SI(D[20]), .SE(ALOAD), .CK(Clock), .Q(
SO[20]) );
SDFF_X1 \tmp_reg[22] ( .D(SO[20]), .SI(D[22]), .SE(ALOAD), .CK(Clock), .Q(
SO[22]) );
SDFF_X1 \tmp_reg[24] ( .D(SO[22]), .SI(D[24]), .SE(ALOAD), .CK(Clock), .Q(
SO[24]) );
SDFF_X1 \tmp_reg[26] ( .D(SO[24]), .SI(D[26]), .SE(ALOAD), .CK(Clock), .Q(
SO[26]) );
SDFF_X1 \tmp_reg[28] ( .D(SO[26]), .SI(D[28]), .SE(ALOAD), .CK(Clock), .Q(
SO[28]) );
SDFF_X1 \tmp_reg[30] ( .D(SO[28]), .SI(D[30]), .SE(ALOAD), .CK(Clock), .Q(
SO[30]) );
AND2_X1 U3 ( .A1(ALOAD), .A2(D[1]), .ZN(N4) );
AND2_X1 U4 ( .A1(ALOAD), .A2(D[0]), .ZN(N3) );
endmodule
module shift_N9_0 ( Clock, ALOAD, D, SO );
input [8:0] D;
input Clock, ALOAD;
output SO;
wire N11;
wire [8:1] tmp;
DFF_X1 \tmp_reg[8] ( .D(N11), .CK(Clock), .Q(tmp[8]) );
SDFF_X1 \tmp_reg[7] ( .D(tmp[8]), .SI(D[7]), .SE(ALOAD), .CK(Clock), .Q(
tmp[7]) );
SDFF_X1 \tmp_reg[6] ( .D(tmp[7]), .SI(D[6]), .SE(ALOAD), .CK(Clock), .Q(
tmp[6]) );
SDFF_X1 \tmp_reg[5] ( .D(tmp[6]), .SI(D[5]), .SE(ALOAD), .CK(Clock), .Q(
tmp[5]) );
SDFF_X1 \tmp_reg[4] ( .D(tmp[5]), .SI(D[4]), .SE(ALOAD), .CK(Clock), .Q(
tmp[4]) );
SDFF_X1 \tmp_reg[3] ( .D(tmp[4]), .SI(D[3]), .SE(ALOAD), .CK(Clock), .Q(
tmp[3]) );
SDFF_X1 \tmp_reg[2] ( .D(tmp[3]), .SI(D[2]), .SE(ALOAD), .CK(Clock), .Q(
tmp[2]) );
SDFF_X1 \tmp_reg[1] ( .D(tmp[2]), .SI(D[1]), .SE(ALOAD), .CK(Clock), .Q(
tmp[1]) );
AND2_X1 U3 ( .A1(ALOAD), .A2(D[8]), .ZN(N11) );
SDFF_X2 \tmp_reg[0] ( .D(tmp[1]), .SI(D[0]), .SE(ALOAD), .CK(Clock), .Q(SO)
);
endmodule
module booth_encoder_0 ( B_in, A_out );
input [2:0] B_in;
output [2:0] A_out;
wire n3, n4;
assign A_out[1] = B_in[2];
INV_X1 U3 ( .A(B_in[1]), .ZN(n3) );
INV_X1 U4 ( .A(B_in[2]), .ZN(n4) );
NAND2_X1 U5 ( .A1(n4), .A2(n3), .ZN(A_out[2]) );
NOR2_X1 U6 ( .A1(B_in[1]), .A2(n4), .ZN(A_out[0]) );
endmodule
module carry_sel_gen_N4_0 ( A, B, Ci, S, Co );
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire [3:0] nocarry_sum_to_mux;
RCA_N4_0 rca_nocarry ( .A(A), .B(B), .Ci(1'b0), .S(nocarry_sum_to_mux) );
mux21_SIZE4_0 outmux ( .IN0(nocarry_sum_to_mux), .IN1({1'b0, 1'b0, 1'b0,
1'b0}), .CTRL(1'b0), .OUT1(S) );
endmodule
module pg_0 ( g, p, g_prec, p_prec, g_out, p_out );
input g, p, g_prec, p_prec;
output g_out, p_out;
wire n2;
AOI21_X1 U3 ( .B1(g_prec), .B2(p), .A(g), .ZN(n2) );
AND2_X1 U1 ( .A1(p), .A2(p_prec), .ZN(p_out) );
INV_X1 U2 ( .A(n2), .ZN(g_out) );
endmodule
module g_0 ( g, p, g_prec, g_out );
input g, p, g_prec;
output g_out;
wire g;
assign g_out = g;
endmodule
module pg_net_0 ( a, b, g_out, p_out );
input a, b;
output g_out, p_out;
XOR2_X1 U2 ( .A(b), .B(a), .Z(p_out) );
AND2_X1 U1 ( .A1(b), .A2(a), .ZN(g_out) );
endmodule
module logic_unit_SIZE32 ( IN1, IN2, CTRL, OUT1 );
input [31:0] IN1;
input [31:0] IN2;
input [1:0] CTRL;
output [31:0] OUT1;
wire n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61,
n62, n63, n64, n65, n1, n2, n22, n23;
AOI21_X1 U8 ( .B1(n3), .B2(n8), .A(n9), .ZN(OUT1[7]) );
AOI21_X1 U32 ( .B1(n3), .B2(n24), .A(n25), .ZN(OUT1[29]) );
AOI21_X1 U50 ( .B1(n3), .B2(n36), .A(n37), .ZN(OUT1[23]) );
AOI21_X1 U77 ( .B1(n3), .B2(n54), .A(n55), .ZN(OUT1[15]) );
AOI21_X1 U67 ( .B1(IN2[19]), .B2(IN1[19]), .A(CTRL[0]), .ZN(n46) );
OAI22_X1 U66 ( .A1(IN1[19]), .A2(IN2[19]), .B1(n3), .B2(n46), .ZN(n47) );
AOI21_X1 U65 ( .B1(n3), .B2(n46), .A(n47), .ZN(OUT1[19]) );
AOI21_X1 U70 ( .B1(IN2[18]), .B2(IN1[18]), .A(CTRL[0]), .ZN(n48) );
OAI22_X1 U69 ( .A1(IN1[18]), .A2(IN2[18]), .B1(n3), .B2(n48), .ZN(n49) );
AOI21_X1 U68 ( .B1(n3), .B2(n48), .A(n49), .ZN(OUT1[18]) );
AOI21_X1 U73 ( .B1(IN2[17]), .B2(IN1[17]), .A(CTRL[0]), .ZN(n50) );
OAI22_X1 U72 ( .A1(IN1[17]), .A2(IN2[17]), .B1(n3), .B2(n50), .ZN(n51) );
AOI21_X1 U71 ( .B1(n3), .B2(n50), .A(n51), .ZN(OUT1[17]) );
AOI21_X1 U46 ( .B1(IN2[25]), .B2(IN1[25]), .A(CTRL[0]), .ZN(n32) );
OAI22_X1 U45 ( .A1(IN1[25]), .A2(IN2[25]), .B1(n3), .B2(n32), .ZN(n33) );
AOI21_X1 U44 ( .B1(n3), .B2(n32), .A(n33), .ZN(OUT1[25]) );
AOI21_X1 U40 ( .B1(IN2[27]), .B2(IN1[27]), .A(CTRL[0]), .ZN(n28) );
OAI22_X1 U39 ( .A1(IN1[27]), .A2(IN2[27]), .B1(n3), .B2(n28), .ZN(n29) );
AOI21_X1 U38 ( .B1(n3), .B2(n28), .A(n29), .ZN(OUT1[27]) );
AOI21_X1 U43 ( .B1(IN2[26]), .B2(IN1[26]), .A(CTRL[0]), .ZN(n30) );
OAI22_X1 U42 ( .A1(IN1[26]), .A2(IN2[26]), .B1(n3), .B2(n30), .ZN(n31) );
AOI21_X1 U41 ( .B1(n3), .B2(n30), .A(n31), .ZN(OUT1[26]) );
AOI21_X1 U28 ( .B1(IN2[30]), .B2(IN1[30]), .A(CTRL[0]), .ZN(n20) );
OAI22_X1 U27 ( .A1(IN1[30]), .A2(IN2[30]), .B1(n3), .B2(n20), .ZN(n21) );
AOI21_X1 U26 ( .B1(n3), .B2(n20), .A(n21), .ZN(OUT1[30]) );
AOI21_X1 U49 ( .B1(IN2[24]), .B2(IN1[24]), .A(CTRL[0]), .ZN(n34) );
OAI22_X1 U48 ( .A1(IN1[24]), .A2(IN2[24]), .B1(n3), .B2(n34), .ZN(n35) );
AOI21_X1 U47 ( .B1(n3), .B2(n34), .A(n35), .ZN(OUT1[24]) );
AOI21_X1 U55 ( .B1(IN2[22]), .B2(IN1[22]), .A(CTRL[0]), .ZN(n38) );
OAI22_X1 U54 ( .A1(IN1[22]), .A2(IN2[22]), .B1(n3), .B2(n38), .ZN(n39) );
AOI21_X1 U53 ( .B1(n3), .B2(n38), .A(n39), .ZN(OUT1[22]) );
AOI21_X1 U58 ( .B1(IN2[21]), .B2(IN1[21]), .A(CTRL[0]), .ZN(n40) );
OAI22_X1 U57 ( .A1(IN1[21]), .A2(IN2[21]), .B1(n3), .B2(n40), .ZN(n41) );
AOI21_X1 U56 ( .B1(n3), .B2(n40), .A(n41), .ZN(OUT1[21]) );
AOI21_X1 U25 ( .B1(IN2[31]), .B2(IN1[31]), .A(CTRL[0]), .ZN(n18) );
OAI22_X1 U24 ( .A1(IN1[31]), .A2(IN2[31]), .B1(n3), .B2(n18), .ZN(n19) );
AOI21_X1 U23 ( .B1(n3), .B2(n18), .A(n19), .ZN(OUT1[31]) );
AOI21_X1 U61 ( .B1(IN2[20]), .B2(IN1[20]), .A(CTRL[0]), .ZN(n42) );
OAI22_X1 U60 ( .A1(IN1[20]), .A2(IN2[20]), .B1(n3), .B2(n42), .ZN(n43) );
AOI21_X1 U59 ( .B1(n3), .B2(n42), .A(n43), .ZN(OUT1[20]) );
AOI21_X1 U37 ( .B1(IN2[28]), .B2(IN1[28]), .A(CTRL[0]), .ZN(n26) );
OAI22_X1 U36 ( .A1(IN1[28]), .A2(IN2[28]), .B1(n3), .B2(n26), .ZN(n27) );
AOI21_X1 U35 ( .B1(n3), .B2(n26), .A(n27), .ZN(OUT1[28]) );
AOI21_X1 U82 ( .B1(IN2[14]), .B2(IN1[14]), .A(CTRL[0]), .ZN(n56) );
OAI22_X1 U81 ( .A1(IN1[14]), .A2(IN2[14]), .B1(n3), .B2(n56), .ZN(n57) );
AOI21_X1 U80 ( .B1(n3), .B2(n56), .A(n57), .ZN(OUT1[14]) );
AOI21_X1 U22 ( .B1(IN2[3]), .B2(IN1[3]), .A(CTRL[0]), .ZN(n16) );
OAI22_X1 U21 ( .A1(IN1[3]), .A2(IN2[3]), .B1(n3), .B2(n16), .ZN(n17) );
AOI21_X1 U20 ( .B1(n3), .B2(n16), .A(n17), .ZN(OUT1[3]) );
AOI21_X1 U86 ( .B1(n3), .B2(n60), .A(n61), .ZN(OUT1[12]) );
AOI21_X1 U89 ( .B1(n3), .B2(n62), .A(n63), .ZN(OUT1[11]) );
AOI21_X1 U76 ( .B1(IN2[16]), .B2(IN1[16]), .A(CTRL[0]), .ZN(n52) );
OAI22_X1 U75 ( .A1(IN1[16]), .A2(IN2[16]), .B1(n3), .B2(n52), .ZN(n53) );
AOI21_X1 U74 ( .B1(n3), .B2(n52), .A(n53), .ZN(OUT1[16]) );
AOI21_X1 U83 ( .B1(n3), .B2(n58), .A(n59), .ZN(OUT1[13]) );
AOI21_X1 U2 ( .B1(n3), .B2(n4), .A(n5), .ZN(OUT1[9]) );
AOI21_X1 U11 ( .B1(n3), .B2(n10), .A(n11), .ZN(OUT1[6]) );
AOI21_X1 U7 ( .B1(IN2[8]), .B2(IN1[8]), .A(CTRL[0]), .ZN(n6) );
OAI22_X1 U6 ( .A1(IN1[8]), .A2(IN2[8]), .B1(n3), .B2(n6), .ZN(n7) );
AOI21_X1 U5 ( .B1(n3), .B2(n6), .A(n7), .ZN(OUT1[8]) );
AOI21_X1 U92 ( .B1(n3), .B2(n64), .A(n65), .ZN(OUT1[10]) );
AOI21_X1 U14 ( .B1(n3), .B2(n12), .A(n13), .ZN(OUT1[5]) );
AOI21_X1 U19 ( .B1(IN2[4]), .B2(IN1[4]), .A(CTRL[0]), .ZN(n14) );
OAI22_X1 U18 ( .A1(IN1[4]), .A2(IN2[4]), .B1(n3), .B2(n14), .ZN(n15) );
AOI21_X1 U17 ( .B1(n3), .B2(n14), .A(n15), .ZN(OUT1[4]) );
AOI21_X1 U62 ( .B1(n3), .B2(n44), .A(n45), .ZN(OUT1[1]) );
AOI21_X1 U3 ( .B1(IN1[0]), .B2(IN2[0]), .A(CTRL[0]), .ZN(n1) );
OAI22_X1 U4 ( .A1(IN2[0]), .A2(IN1[0]), .B1(n3), .B2(n1), .ZN(n2) );
AOI21_X1 U9 ( .B1(n3), .B2(n1), .A(n2), .ZN(OUT1[0]) );
AOI21_X1 U10 ( .B1(IN1[2]), .B2(IN2[2]), .A(CTRL[0]), .ZN(n22) );
OAI22_X1 U12 ( .A1(IN2[2]), .A2(IN1[2]), .B1(n3), .B2(n22), .ZN(n23) );
AOI21_X1 U13 ( .B1(n3), .B2(n22), .A(n23), .ZN(OUT1[2]) );
INV_X4 U15 ( .A(CTRL[1]), .ZN(n3) );
OAI22_X1 U16 ( .A1(IN1[10]), .A2(IN2[10]), .B1(n3), .B2(n64), .ZN(n65) );
AOI21_X1 U29 ( .B1(IN2[10]), .B2(IN1[10]), .A(CTRL[0]), .ZN(n64) );
OAI22_X1 U30 ( .A1(IN1[29]), .A2(IN2[29]), .B1(n3), .B2(n24), .ZN(n25) );
AOI21_X1 U31 ( .B1(IN2[29]), .B2(IN1[29]), .A(CTRL[0]), .ZN(n24) );
OAI22_X1 U33 ( .A1(IN1[12]), .A2(IN2[12]), .B1(n3), .B2(n60), .ZN(n61) );
AOI21_X1 U34 ( .B1(IN2[12]), .B2(IN1[12]), .A(CTRL[0]), .ZN(n60) );
OAI22_X1 U51 ( .A1(IN1[23]), .A2(IN2[23]), .B1(n3), .B2(n36), .ZN(n37) );
AOI21_X1 U52 ( .B1(IN2[23]), .B2(IN1[23]), .A(CTRL[0]), .ZN(n36) );
OAI22_X1 U63 ( .A1(IN1[11]), .A2(IN2[11]), .B1(n3), .B2(n62), .ZN(n63) );
AOI21_X1 U64 ( .B1(IN2[11]), .B2(IN1[11]), .A(CTRL[0]), .ZN(n62) );
OAI22_X1 U78 ( .A1(IN1[15]), .A2(IN2[15]), .B1(n3), .B2(n54), .ZN(n55) );
AOI21_X1 U79 ( .B1(IN2[15]), .B2(IN1[15]), .A(CTRL[0]), .ZN(n54) );
OAI22_X1 U84 ( .A1(IN1[7]), .A2(IN2[7]), .B1(n3), .B2(n8), .ZN(n9) );
AOI21_X1 U85 ( .B1(IN2[7]), .B2(IN1[7]), .A(CTRL[0]), .ZN(n8) );
OAI22_X1 U87 ( .A1(IN1[6]), .A2(IN2[6]), .B1(n3), .B2(n10), .ZN(n11) );
AOI21_X1 U88 ( .B1(IN2[6]), .B2(IN1[6]), .A(CTRL[0]), .ZN(n10) );
OAI22_X1 U90 ( .A1(IN1[9]), .A2(IN2[9]), .B1(n3), .B2(n4), .ZN(n5) );
AOI21_X1 U91 ( .B1(IN2[9]), .B2(IN1[9]), .A(CTRL[0]), .ZN(n4) );
OAI22_X1 U93 ( .A1(IN1[13]), .A2(IN2[13]), .B1(n3), .B2(n58), .ZN(n59) );
AOI21_X1 U94 ( .B1(IN2[13]), .B2(IN1[13]), .A(CTRL[0]), .ZN(n58) );
OAI22_X1 U95 ( .A1(IN1[5]), .A2(IN2[5]), .B1(n3), .B2(n12), .ZN(n13) );
AOI21_X1 U96 ( .B1(IN2[5]), .B2(IN1[5]), .A(CTRL[0]), .ZN(n12) );
OAI22_X1 U97 ( .A1(IN1[1]), .A2(IN2[1]), .B1(n3), .B2(n44), .ZN(n45) );
AOI21_X1 U98 ( .B1(IN2[1]), .B2(IN1[1]), .A(CTRL[0]), .ZN(n44) );
endmodule
module shifter ( A, B, LOGIC_ARITH, LEFT_RIGHT, OUTPUT );
input [31:0] A;
input [4:0] B;
output [31:0] OUTPUT;
input LOGIC_ARITH, LEFT_RIGHT;
wire n6, n8, n9, n10, n2, n3, n4, n5, n7, n11, n12, n13;
wire [2:0] s3;
wire [38:0] m0;
wire [38:0] m8;
wire [38:0] m16;
wire [38:0] y;
shift_firstLevel IL ( .A(A), .sel({LOGIC_ARITH, LEFT_RIGHT}), .mask00(m0),
.mask08(m8), .mask16({m16[38:23], n4, n3, n5, n7, n11, n12, n2,
m16[15:0]}) );
shift_secondLevel IIL ( .sel(B[4:3]), .mask00(m0), .mask08(m8), .mask16({
m16[38:23], n4, n3, n5, n7, n11, n12, n2, m16[15:0]}), .Y(y) );
shift_thirdLevel IIIL ( .sel(s3), .A(y), .Y(OUTPUT) );
OR2_X1 U8 ( .A1(LOGIC_ARITH), .A2(LEFT_RIGHT), .ZN(n6) );
INV_X1 U1 ( .A(B[0]), .ZN(n10) );
INV_X1 U2 ( .A(B[2]), .ZN(n8) );
INV_X1 U3 ( .A(B[1]), .ZN(n9) );
INV_X1 U4 ( .A(LEFT_RIGHT), .ZN(n13) );
AOI22_X1 U5 ( .A1(B[1]), .A2(n6), .B1(n13), .B2(n9), .ZN(s3[1]) );
AOI22_X1 U6 ( .A1(B[2]), .A2(n6), .B1(n13), .B2(n8), .ZN(s3[2]) );
AOI22_X1 U7 ( .A1(B[0]), .A2(n6), .B1(n13), .B2(n10), .ZN(s3[0]) );
endmodule
module comparator_M32 ( V, SUM, sel, sign, S, C_BAR );
input [31:0] SUM;
input [2:0] sel;
input V, sign, C_BAR;
output S;
wire C, n8, n6, n1, n2, n3, n4, n5, n7, n9, n10, n11, n12, n13, n14, n15,
n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29,
n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40;
assign C = C_BAR;
NOR4_X1 U1 ( .A1(SUM[6]), .A2(SUM[5]), .A3(SUM[3]), .A4(SUM[4]), .ZN(n25) );
AND2_X1 U2 ( .A1(n16), .A2(n17), .ZN(n1) );
CLKBUF_X1 U3 ( .A(SUM[31]), .Z(n2) );
INV_X1 U4 ( .A(n40), .ZN(n14) );
INV_X1 U5 ( .A(sel[2]), .ZN(n13) );
INV_X1 U6 ( .A(n12), .ZN(n11) );
INV_X1 U7 ( .A(sign), .ZN(n18) );
OR2_X1 U8 ( .A1(n6), .A2(sel[0]), .ZN(n15) );
AND4_X1 U9 ( .A1(n23), .A2(n25), .A3(n24), .A4(n26), .ZN(n39) );
INV_X1 U10 ( .A(SUM[9]), .ZN(n26) );
INV_X1 U11 ( .A(SUM[31]), .ZN(n23) );
INV_X1 U12 ( .A(SUM[0]), .ZN(n38) );
INV_X1 U13 ( .A(SUM[10]), .ZN(n37) );
NOR2_X1 U14 ( .A1(n40), .A2(n10), .ZN(n9) );
NOR2_X1 U15 ( .A1(sel[0]), .A2(sel[2]), .ZN(n10) );
OAI21_X1 U16 ( .B1(sel[1]), .B2(sel[0]), .A(sel[2]), .ZN(n12) );
NAND2_X1 U17 ( .A1(C), .A2(n18), .ZN(n17) );
NOR2_X1 U18 ( .A1(sel[1]), .A2(sel[2]), .ZN(n40) );
NOR4_X1 U19 ( .A1(SUM[25]), .A2(SUM[24]), .A3(SUM[26]), .A4(SUM[27]), .ZN(
n22) );
NOR4_X1 U20 ( .A1(SUM[29]), .A2(SUM[30]), .A3(SUM[28]), .A4(SUM[2]), .ZN(n21) );
NAND4_X1 U21 ( .A1(n20), .A2(n39), .A3(n21), .A4(n22), .ZN(n6) );
XNOR2_X1 U22 ( .A(n6), .B(n11), .ZN(n7) );
NAND3_X1 U23 ( .A1(n8), .A2(n13), .A3(n14), .ZN(n4) );
NAND2_X1 U24 ( .A1(n7), .A2(n9), .ZN(n5) );
NAND3_X1 U25 ( .A1(n15), .A2(n40), .A3(n1), .ZN(n3) );
NAND3_X1 U26 ( .A1(n5), .A2(n3), .A3(n4), .ZN(S) );
NAND2_X1 U27 ( .A1(V), .A2(n2), .ZN(n19) );
OAI211_X1 U28 ( .C1(V), .C2(n2), .A(n19), .B(sign), .ZN(n16) );
NAND2_X1 U29 ( .A1(n16), .A2(n17), .ZN(n8) );
NAND3_X1 U30 ( .A1(n33), .A2(n34), .A3(n35), .ZN(n27) );
NAND2_X1 U31 ( .A1(n37), .A2(n38), .ZN(n36) );
NOR2_X1 U32 ( .A1(SUM[22]), .A2(SUM[23]), .ZN(n29) );
NAND4_X1 U33 ( .A1(n30), .A2(n29), .A3(n31), .A4(n32), .ZN(n28) );
NOR3_X1 U34 ( .A1(SUM[12]), .A2(SUM[11]), .A3(n36), .ZN(n33) );
NOR2_X1 U35 ( .A1(SUM[21]), .A2(SUM[20]), .ZN(n30) );
NOR2_X1 U36 ( .A1(SUM[18]), .A2(SUM[17]), .ZN(n31) );
NOR2_X1 U37 ( .A1(SUM[19]), .A2(SUM[1]), .ZN(n32) );
NOR2_X1 U38 ( .A1(SUM[14]), .A2(SUM[13]), .ZN(n34) );
NOR2_X1 U39 ( .A1(SUM[15]), .A2(SUM[16]), .ZN(n35) );
NOR2_X1 U40 ( .A1(n28), .A2(n27), .ZN(n20) );
NOR2_X1 U41 ( .A1(SUM[7]), .A2(SUM[8]), .ZN(n24) );
endmodule
module simple_booth_add_ext_N16 ( Clock, Reset, sign, enable, valid, A, B,
A_to_add, B_to_add, sign_to_add, final_out, ACC_from_add );
input [15:0] A;
input [15:0] B;
output [31:0] A_to_add;
output [31:0] B_to_add;
output [31:0] final_out;
input [31:0] ACC_from_add;
input Clock, Reset, sign, enable;
output valid, sign_to_add;
wire \enc_N2_in[2] , \extend_vector[15] , \input_mux_sel[2] ,
input_mux_sel_0, reg_enable, N23, N37, N39, N41, N43, N44, N45,
net3331, n8, n9, n10, n11, n1, n4, n6, n7, n12, n13, n14, n16, n17,
n18, n19;
wire [8:0] piso_0_in;
wire [8:0] piso_1_in;
wire [8:0] piso_2_in;
wire [31:0] A_to_mux;
wire [31:0] next_accumulate;
wire [4:0] count;
DFFS_X1 \count_reg[0] ( .D(N37), .CK(net3331), .SN(n19), .Q(count[0]), .QN(
n13) );
DFFR_X1 \count_reg[1] ( .D(N39), .CK(net3331), .RN(n19), .Q(count[1]) );
DFFR_X1 \count_reg[2] ( .D(N41), .CK(net3331), .RN(n19), .Q(count[2]), .QN(
n14) );
DFFS_X1 \count_reg[3] ( .D(N43), .CK(net3331), .SN(n19), .Q(count[3]) );
DFFR_X1 \count_reg[4] ( .D(N45), .CK(net3331), .RN(n19), .Q(count[4]) );
MUX2_X1 U51 ( .A(A_to_add[9]), .B(ACC_from_add[9]), .S(\input_mux_sel[2] ),
.Z(final_out[9]) );
MUX2_X1 U52 ( .A(A_to_add[8]), .B(ACC_from_add[8]), .S(\input_mux_sel[2] ),
.Z(final_out[8]) );
MUX2_X1 U53 ( .A(A_to_add[7]), .B(ACC_from_add[7]), .S(\input_mux_sel[2] ),
.Z(final_out[7]) );
MUX2_X1 U54 ( .A(A_to_add[6]), .B(ACC_from_add[6]), .S(\input_mux_sel[2] ),
.Z(final_out[6]) );
MUX2_X1 U55 ( .A(A_to_add[5]), .B(ACC_from_add[5]), .S(\input_mux_sel[2] ),
.Z(final_out[5]) );
MUX2_X1 U56 ( .A(A_to_add[4]), .B(ACC_from_add[4]), .S(\input_mux_sel[2] ),
.Z(final_out[4]) );
MUX2_X1 U57 ( .A(A_to_add[3]), .B(ACC_from_add[3]), .S(\input_mux_sel[2] ),
.Z(final_out[3]) );
MUX2_X1 U58 ( .A(A_to_add[31]), .B(ACC_from_add[31]), .S(\input_mux_sel[2] ),
.Z(final_out[31]) );
MUX2_X1 U59 ( .A(A_to_add[30]), .B(ACC_from_add[30]), .S(\input_mux_sel[2] ),
.Z(final_out[30]) );
MUX2_X1 U61 ( .A(A_to_add[29]), .B(ACC_from_add[29]), .S(\input_mux_sel[2] ),
.Z(final_out[29]) );
MUX2_X1 U62 ( .A(A_to_add[28]), .B(ACC_from_add[28]), .S(\input_mux_sel[2] ),
.Z(final_out[28]) );
MUX2_X1 U63 ( .A(A_to_add[27]), .B(ACC_from_add[27]), .S(\input_mux_sel[2] ),
.Z(final_out[27]) );
MUX2_X1 U64 ( .A(A_to_add[26]), .B(ACC_from_add[26]), .S(\input_mux_sel[2] ),
.Z(final_out[26]) );
MUX2_X1 U65 ( .A(A_to_add[25]), .B(ACC_from_add[25]), .S(\input_mux_sel[2] ),
.Z(final_out[25]) );
MUX2_X1 U66 ( .A(A_to_add[24]), .B(ACC_from_add[24]), .S(\input_mux_sel[2] ),
.Z(final_out[24]) );
MUX2_X1 U67 ( .A(A_to_add[23]), .B(ACC_from_add[23]), .S(\input_mux_sel[2] ),
.Z(final_out[23]) );
MUX2_X1 U68 ( .A(A_to_add[22]), .B(ACC_from_add[22]), .S(\input_mux_sel[2] ),
.Z(final_out[22]) );
MUX2_X1 U69 ( .A(A_to_add[21]), .B(ACC_from_add[21]), .S(\input_mux_sel[2] ),
.Z(final_out[21]) );
MUX2_X1 U70 ( .A(A_to_add[20]), .B(ACC_from_add[20]), .S(\input_mux_sel[2] ),
.Z(final_out[20]) );
MUX2_X1 U71 ( .A(A_to_add[1]), .B(ACC_from_add[1]), .S(\input_mux_sel[2] ),
.Z(final_out[1]) );
MUX2_X1 U72 ( .A(A_to_add[19]), .B(ACC_from_add[19]), .S(\input_mux_sel[2] ),
.Z(final_out[19]) );
MUX2_X1 U73 ( .A(A_to_add[18]), .B(ACC_from_add[18]), .S(\input_mux_sel[2] ),
.Z(final_out[18]) );
MUX2_X1 U74 ( .A(A_to_add[17]), .B(ACC_from_add[17]), .S(\input_mux_sel[2] ),
.Z(final_out[17]) );
MUX2_X1 U75 ( .A(A_to_add[16]), .B(ACC_from_add[16]), .S(\input_mux_sel[2] ),
.Z(final_out[16]) );
MUX2_X1 U76 ( .A(A_to_add[15]), .B(ACC_from_add[15]), .S(\input_mux_sel[2] ),
.Z(final_out[15]) );
MUX2_X1 U77 ( .A(A_to_add[14]), .B(ACC_from_add[14]), .S(\input_mux_sel[2] ),
.Z(final_out[14]) );
MUX2_X1 U78 ( .A(A_to_add[13]), .B(ACC_from_add[13]), .S(\input_mux_sel[2] ),
.Z(final_out[13]) );
MUX2_X1 U79 ( .A(A_to_add[12]), .B(ACC_from_add[12]), .S(\input_mux_sel[2] ),
.Z(final_out[12]) );
MUX2_X1 U80 ( .A(A_to_add[11]), .B(ACC_from_add[11]), .S(\input_mux_sel[2] ),
.Z(final_out[11]) );
MUX2_X1 U81 ( .A(A_to_add[10]), .B(ACC_from_add[10]), .S(\input_mux_sel[2] ),
.Z(final_out[10]) );
booth_encoder_0 encod_0_0 ( .B_in({B[1:0], 1'b0}), .A_out({piso_2_in[0],
piso_1_in[0], piso_0_in[0]}) );
booth_encoder_8 encod_i_1 ( .B_in(B[3:1]), .A_out({piso_2_in[1],
piso_1_in[1], piso_0_in[1]}) );
booth_encoder_7 encod_i_2 ( .B_in(B[5:3]), .A_out({piso_2_in[2],
piso_1_in[2], piso_0_in[2]}) );
booth_encoder_6 encod_i_3 ( .B_in(B[7:5]), .A_out({piso_2_in[3],
piso_1_in[3], piso_0_in[3]}) );
booth_encoder_5 encod_i_4 ( .B_in(B[9:7]), .A_out({piso_2_in[4],
piso_1_in[4], piso_0_in[4]}) );
booth_encoder_4 encod_i_5 ( .B_in(B[11:9]), .A_out({piso_2_in[5],
piso_1_in[5], piso_0_in[5]}) );
booth_encoder_3 encod_i_6 ( .B_in(B[13:11]), .A_out({piso_2_in[6],
piso_1_in[6], piso_0_in[6]}) );
booth_encoder_2 encod_i_7 ( .B_in(B[15:13]), .A_out({piso_2_in[7],
piso_1_in[7], piso_0_in[7]}) );
booth_encoder_1 encod_i_8 ( .B_in({\enc_N2_in[2] , \enc_N2_in[2] , B[15]}),
.A_out({piso_2_in[8], piso_1_in[8], piso_0_in[8]}) );
shift_N9_0 piso_0 ( .Clock(Clock), .ALOAD(n18), .D(piso_0_in), .SO(
input_mux_sel_0) );
shift_N9_2 piso_1 ( .Clock(Clock), .ALOAD(n18), .D(piso_1_in), .SO(
sign_to_add) );
shift_N9_1 piso_2 ( .Clock(Clock), .ALOAD(n18), .D(piso_2_in), .SO(
\input_mux_sel[2] ) );
piso_r_2_N32 A_reg ( .Clock(Clock), .ALOAD(n18), .D({\extend_vector[15] ,
\extend_vector[15] , \extend_vector[15] , \extend_vector[15] ,
\extend_vector[15] , \extend_vector[15] , \extend_vector[15] ,
\extend_vector[15] , \extend_vector[15] , \extend_vector[15] ,
\extend_vector[15] , \extend_vector[15] , \extend_vector[15] ,
\extend_vector[15] , \extend_vector[15] , \extend_vector[15] , A}),
.SO(A_to_mux) );
mux21_1 INPUTMUX ( .IN0(A_to_mux), .IN1({A_to_mux[30:0], 1'b0}), .CTRL(
input_mux_sel_0), .OUT1(B_to_add) );
ff32_en_SIZE32_1 ACCUMULATOR ( .D(next_accumulate), .en(reg_enable), .clk(
Clock), .rst(Reset), .Q(A_to_add) );
SNPS_CLOCK_GATE_HIGH_simple_booth_add_ext_N16 clk_gate_count_reg ( .CLK(
Clock), .EN(N44), .ENCLK(net3331) );
OR2_X1 U41 ( .A1(valid), .A2(enable), .ZN(N44) );
INV_X1 U48 ( .A(n9), .ZN(n11) );
OR2_X1 U4 ( .A1(n18), .A2(\input_mux_sel[2] ), .ZN(reg_enable) );
AND2_X1 U17 ( .A1(n8), .A2(ACC_from_add[27]), .ZN(next_accumulate[27]) );
AND2_X1 U7 ( .A1(n8), .A2(ACC_from_add[7]), .ZN(next_accumulate[7]) );
AND2_X1 U13 ( .A1(n8), .A2(ACC_from_add[30]), .ZN(next_accumulate[30]) );
AND2_X1 U15 ( .A1(n8), .A2(ACC_from_add[29]), .ZN(next_accumulate[29]) );
AND2_X1 U18 ( .A1(n8), .A2(ACC_from_add[26]), .ZN(next_accumulate[26]) );
AND2_X1 U19 ( .A1(n8), .A2(ACC_from_add[25]), .ZN(next_accumulate[25]) );
AND2_X1 U30 ( .A1(n8), .A2(ACC_from_add[15]), .ZN(next_accumulate[15]) );
AND2_X1 U31 ( .A1(n8), .A2(ACC_from_add[14]), .ZN(next_accumulate[14]) );
AND2_X1 U11 ( .A1(n8), .A2(ACC_from_add[3]), .ZN(next_accumulate[3]) );
AND2_X1 U21 ( .A1(n8), .A2(ACC_from_add[23]), .ZN(next_accumulate[23]) );
AND2_X1 U33 ( .A1(n8), .A2(ACC_from_add[12]), .ZN(next_accumulate[12]) );
AND2_X1 U26 ( .A1(n8), .A2(ACC_from_add[19]), .ZN(next_accumulate[19]) );
AND2_X1 U27 ( .A1(n8), .A2(ACC_from_add[18]), .ZN(next_accumulate[18]) );
AND2_X1 U28 ( .A1(n8), .A2(ACC_from_add[17]), .ZN(next_accumulate[17]) );
AND2_X1 U29 ( .A1(n8), .A2(ACC_from_add[16]), .ZN(next_accumulate[16]) );
AND2_X1 U34 ( .A1(n8), .A2(ACC_from_add[11]), .ZN(next_accumulate[11]) );
AND2_X1 U8 ( .A1(n8), .A2(ACC_from_add[6]), .ZN(next_accumulate[6]) );
AND2_X1 U5 ( .A1(n8), .A2(ACC_from_add[9]), .ZN(next_accumulate[9]) );
AND2_X1 U6 ( .A1(n8), .A2(ACC_from_add[8]), .ZN(next_accumulate[8]) );
AND2_X1 U35 ( .A1(n8), .A2(ACC_from_add[10]), .ZN(next_accumulate[10]) );
AND2_X1 U14 ( .A1(n8), .A2(ACC_from_add[2]), .ZN(next_accumulate[2]) );
AND2_X1 U9 ( .A1(n8), .A2(ACC_from_add[5]), .ZN(next_accumulate[5]) );
AND2_X1 U25 ( .A1(n8), .A2(ACC_from_add[1]), .ZN(next_accumulate[1]) );
AND2_X1 U10 ( .A1(n8), .A2(ACC_from_add[4]), .ZN(next_accumulate[4]) );
AND2_X1 U36 ( .A1(n8), .A2(ACC_from_add[0]), .ZN(next_accumulate[0]) );
AND2_X1 U38 ( .A1(sign), .A2(A[15]), .ZN(\extend_vector[15] ) );
INV_X1 U45 ( .A(valid), .ZN(n10) );
AND2_X1 U43 ( .A1(N23), .A2(n10), .ZN(N41) );
OR2_X1 U46 ( .A1(valid), .A2(n13), .ZN(N37) );
NOR3_X1 U49 ( .A1(count[1]), .A2(count[4]), .A3(count[2]), .ZN(n9) );
NOR3_X1 U47 ( .A1(count[3]), .A2(count[0]), .A3(n11), .ZN(valid) );
NOR2_X1 U3 ( .A1(count[3]), .A2(n17), .ZN(n1) );
OAI21_X1 U12 ( .B1(count[4]), .B2(n1), .A(n10), .ZN(n4) );
AOI21_X1 U16 ( .B1(count[4]), .B2(n1), .A(n4), .ZN(N45) );
MUX2_X1 U20 ( .A(A_to_add[0]), .B(ACC_from_add[0]), .S(\input_mux_sel[2] ),
.Z(final_out[0]) );
AOI21_X1 U22 ( .B1(n17), .B2(count[3]), .A(valid), .ZN(n6) );
OAI21_X1 U23 ( .B1(n17), .B2(count[3]), .A(n6), .ZN(N43) );
MUX2_X1 U24 ( .A(A_to_add[2]), .B(ACC_from_add[2]), .S(\input_mux_sel[2] ),
.Z(final_out[2]) );
INV_X1 U32 ( .A(n10), .ZN(n7) );
AOI21_X1 U37 ( .B1(count[1]), .B2(count[0]), .A(n16), .ZN(n12) );
NOR2_X1 U39 ( .A1(n12), .A2(n7), .ZN(N39) );
INV_X4 U40 ( .A(n8), .ZN(n18) );
NOR2_X1 U42 ( .A1(count[0]), .A2(count[1]), .ZN(n16) );
OR3_X1 U44 ( .A1(count[2]), .A2(count[0]), .A3(count[1]), .ZN(n17) );
OAI21_X1 U50 ( .B1(n16), .B2(n14), .A(n17), .ZN(N23) );
INV_X1 U60 ( .A(Reset), .ZN(n19) );
AND2_X1 U82 ( .A1(sign), .A2(B[15]), .ZN(\enc_N2_in[2] ) );
AND2_X1 U83 ( .A1(n8), .A2(ACC_from_add[13]), .ZN(next_accumulate[13]) );
AND2_X1 U84 ( .A1(n8), .A2(ACC_from_add[21]), .ZN(next_accumulate[21]) );
AND2_X1 U85 ( .A1(n8), .A2(ACC_from_add[20]), .ZN(next_accumulate[20]) );
AND2_X1 U86 ( .A1(n8), .A2(ACC_from_add[22]), .ZN(next_accumulate[22]) );
AND2_X1 U87 ( .A1(n8), .A2(ACC_from_add[24]), .ZN(next_accumulate[24]) );
AND2_X1 U88 ( .A1(n8), .A2(ACC_from_add[28]), .ZN(next_accumulate[28]) );
AND2_X1 U89 ( .A1(n8), .A2(ACC_from_add[31]), .ZN(next_accumulate[31]) );
NAND3_X2 U90 ( .A1(n9), .A2(count[3]), .A3(count[0]), .ZN(n8) );
endmodule
module SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE13 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3364, net3366, net3367, net3370;
assign net3364 = CLK;
assign ENCLK = net3366;
assign net3367 = EN;
DLL_X1 latch ( .D(net3367), .GN(net3364), .Q(net3370) );
AND2_X1 main_gate ( .A1(net3370), .A2(net3364), .ZN(net3366) );
endmodule
module SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE5_0 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3349, net3351, net3352, net3355;
assign net3349 = CLK;
assign ENCLK = net3351;
assign net3352 = EN;
DLL_X1 latch ( .D(net3352), .GN(net3349), .Q(net3355) );
AND2_X1 main_gate ( .A1(net3355), .A2(net3349), .ZN(net3351) );
endmodule
module SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE32_0 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3334, net3336, net3337, net3340;
assign net3334 = CLK;
assign ENCLK = net3336;
assign net3337 = EN;
DLL_X1 latch ( .D(net3337), .GN(net3334), .Q(net3340) );
AND2_X1 main_gate ( .A1(net3340), .A2(net3334), .ZN(net3336) );
endmodule
module sum_gen_N32_0 ( A, B, Cin, S );
input [31:0] A;
input [31:0] B;
input [8:0] Cin;
output [31:0] S;
carry_sel_gen_N4_0 csel_N_0 ( .A(A[3:0]), .B(B[3:0]), .Ci(1'b0), .S(S[3:0])
);
carry_sel_gen_N4_15 csel_N_1 ( .A(A[7:4]), .B(B[7:4]), .Ci(Cin[1]), .S(
S[7:4]) );
carry_sel_gen_N4_14 csel_N_2 ( .A(A[11:8]), .B(B[11:8]), .Ci(Cin[2]), .S(
S[11:8]) );
carry_sel_gen_N4_13 csel_N_3 ( .A(A[15:12]), .B(B[15:12]), .Ci(Cin[3]), .S(
S[15:12]) );
carry_sel_gen_N4_12 csel_N_4 ( .A(A[19:16]), .B(B[19:16]), .Ci(Cin[4]), .S(
S[19:16]) );
carry_sel_gen_N4_11 csel_N_5 ( .A(A[23:20]), .B(B[23:20]), .Ci(Cin[5]), .S(
S[23:20]) );
carry_sel_gen_N4_10 csel_N_6 ( .A(A[27:24]), .B(B[27:24]), .Ci(Cin[6]), .S(
S[27:24]) );
carry_sel_gen_N4_9 csel_N_7 ( .A(A[31:28]), .B(B[31:28]), .Ci(Cin[7]), .S(
S[31:28]) );
endmodule
module carry_tree_N32_logN5_0 ( A, B, Cin, Cout );
input [31:0] A;
input [31:0] B;
output [7:0] Cout;
input Cin;
wire \magic_pro[0] , \pg_1[13][1] , \pg_1[13][0] , \pg_1[12][1] ,
\pg_1[12][0] , \pg_1[11][1] , \pg_1[11][0] , \pg_1[10][1] ,
\pg_1[10][0] , \pg_1[9][1] , \pg_1[9][0] , \pg_1[8][1] , \pg_1[8][0] ,
\pg_1[7][1] , \pg_1[7][0] , \pg_1[6][1] , \pg_1[6][0] , \pg_1[5][1] ,
\pg_1[5][0] , \pg_1[4][1] , \pg_1[4][0] , \pg_1[3][1] , \pg_1[3][0] ,
\pg_1[2][1] , \pg_1[2][0] , \pg_1[1][1] , \pg_1[1][0] , \pg_1[0][0] ,
\pg_n[4][6][1] , \pg_n[4][6][0] , \pg_n[3][5][1] , \pg_n[3][5][0] ,
\pg_n[3][3][1] , \pg_n[3][3][0] , \pg_n[2][6][1] , \pg_n[2][6][0] ,
\pg_n[2][5][1] , \pg_n[2][5][0] , \pg_n[2][4][1] , \pg_n[2][4][0] ,
\pg_n[2][3][1] , \pg_n[2][3][0] , \pg_n[2][2][1] , \pg_n[2][2][0] ,
\pg_n[2][1][1] , \pg_n[2][1][0] ;
wire [31:1] p_net;
wire [31:0] g_net;
pg_net_0 pg_net_x_1 ( .a(A[1]), .b(B[1]), .g_out(g_net[1]), .p_out(p_net[1])
);
pg_net_63 pg_net_x_2 ( .a(A[2]), .b(B[2]), .g_out(g_net[2]), .p_out(p_net[2]) );
pg_net_62 pg_net_x_3 ( .a(A[3]), .b(B[3]), .g_out(g_net[3]), .p_out(p_net[3]) );
pg_net_61 pg_net_x_4 ( .a(A[4]), .b(B[4]), .g_out(g_net[4]), .p_out(p_net[4]) );
pg_net_60 pg_net_x_5 ( .a(A[5]), .b(B[5]), .g_out(g_net[5]), .p_out(p_net[5]) );
pg_net_59 pg_net_x_6 ( .a(A[6]), .b(B[6]), .g_out(g_net[6]), .p_out(p_net[6]) );
pg_net_58 pg_net_x_7 ( .a(A[7]), .b(B[7]), .g_out(g_net[7]), .p_out(p_net[7]) );
pg_net_57 pg_net_x_8 ( .a(A[8]), .b(B[8]), .g_out(g_net[8]), .p_out(p_net[8]) );
pg_net_56 pg_net_x_9 ( .a(A[9]), .b(B[9]), .g_out(g_net[9]), .p_out(p_net[9]) );
pg_net_55 pg_net_x_10 ( .a(A[10]), .b(B[10]), .g_out(g_net[10]), .p_out(
p_net[10]) );
pg_net_54 pg_net_x_11 ( .a(A[11]), .b(B[11]), .g_out(g_net[11]), .p_out(
p_net[11]) );
pg_net_53 pg_net_x_12 ( .a(A[12]), .b(B[12]), .g_out(g_net[12]), .p_out(
p_net[12]) );
pg_net_52 pg_net_x_13 ( .a(A[13]), .b(B[13]), .g_out(g_net[13]), .p_out(
p_net[13]) );
pg_net_51 pg_net_x_14 ( .a(A[14]), .b(B[14]), .g_out(g_net[14]), .p_out(
p_net[14]) );
pg_net_50 pg_net_x_15 ( .a(A[15]), .b(B[15]), .g_out(g_net[15]), .p_out(
p_net[15]) );
pg_net_49 pg_net_x_16 ( .a(A[16]), .b(B[16]), .g_out(g_net[16]), .p_out(
p_net[16]) );
pg_net_48 pg_net_x_17 ( .a(A[17]), .b(B[17]), .g_out(g_net[17]), .p_out(
p_net[17]) );
pg_net_47 pg_net_x_18 ( .a(A[18]), .b(B[18]), .g_out(g_net[18]), .p_out(
p_net[18]) );
pg_net_46 pg_net_x_19 ( .a(A[19]), .b(B[19]), .g_out(g_net[19]), .p_out(
p_net[19]) );
pg_net_45 pg_net_x_20 ( .a(A[20]), .b(B[20]), .g_out(g_net[20]), .p_out(
p_net[20]) );
pg_net_44 pg_net_x_21 ( .a(A[21]), .b(B[21]), .g_out(g_net[21]), .p_out(
p_net[21]) );
pg_net_43 pg_net_x_22 ( .a(A[22]), .b(B[22]), .g_out(g_net[22]), .p_out(
p_net[22]) );
pg_net_42 pg_net_x_23 ( .a(A[23]), .b(B[23]), .g_out(g_net[23]), .p_out(
p_net[23]) );
pg_net_41 pg_net_x_24 ( .a(A[24]), .b(B[24]), .g_out(g_net[24]), .p_out(
p_net[24]) );
pg_net_40 pg_net_x_25 ( .a(A[25]), .b(B[25]), .g_out(g_net[25]), .p_out(
p_net[25]) );
pg_net_39 pg_net_x_26 ( .a(A[26]), .b(B[26]), .g_out(g_net[26]), .p_out(
p_net[26]) );
pg_net_38 pg_net_x_27 ( .a(A[27]), .b(B[27]), .g_out(g_net[27]), .p_out(
p_net[27]) );
pg_net_33 pg_net_0_MAGIC ( .a(A[0]), .b(B[0]), .g_out(\magic_pro[0] ) );
g_0 xG_0_0_MAGIC ( .g(\magic_pro[0] ), .p(1'b0), .g_prec(1'b0), .g_out(
g_net[0]) );
g_19 xG_1_0 ( .g(g_net[1]), .p(p_net[1]), .g_prec(g_net[0]), .g_out(
\pg_1[0][0] ) );
pg_0 xPG_1_1 ( .g(g_net[3]), .p(p_net[3]), .g_prec(g_net[2]), .p_prec(
p_net[2]), .g_out(\pg_1[1][0] ), .p_out(\pg_1[1][1] ) );
pg_53 xPG_1_2 ( .g(g_net[5]), .p(p_net[5]), .g_prec(g_net[4]), .p_prec(
p_net[4]), .g_out(\pg_1[2][0] ), .p_out(\pg_1[2][1] ) );
pg_52 xPG_1_3 ( .g(g_net[7]), .p(p_net[7]), .g_prec(g_net[6]), .p_prec(
p_net[6]), .g_out(\pg_1[3][0] ), .p_out(\pg_1[3][1] ) );
pg_51 xPG_1_4 ( .g(g_net[9]), .p(p_net[9]), .g_prec(g_net[8]), .p_prec(
p_net[8]), .g_out(\pg_1[4][0] ), .p_out(\pg_1[4][1] ) );
pg_50 xPG_1_5 ( .g(g_net[11]), .p(p_net[11]), .g_prec(g_net[10]), .p_prec(
p_net[10]), .g_out(\pg_1[5][0] ), .p_out(\pg_1[5][1] ) );
pg_49 xPG_1_6 ( .g(g_net[13]), .p(p_net[13]), .g_prec(g_net[12]), .p_prec(
p_net[12]), .g_out(\pg_1[6][0] ), .p_out(\pg_1[6][1] ) );
pg_48 xPG_1_7 ( .g(g_net[15]), .p(p_net[15]), .g_prec(g_net[14]), .p_prec(
p_net[14]), .g_out(\pg_1[7][0] ), .p_out(\pg_1[7][1] ) );
pg_47 xPG_1_8 ( .g(g_net[17]), .p(p_net[17]), .g_prec(g_net[16]), .p_prec(
p_net[16]), .g_out(\pg_1[8][0] ), .p_out(\pg_1[8][1] ) );
pg_46 xPG_1_9 ( .g(g_net[19]), .p(p_net[19]), .g_prec(g_net[18]), .p_prec(
p_net[18]), .g_out(\pg_1[9][0] ), .p_out(\pg_1[9][1] ) );
pg_45 xPG_1_10 ( .g(g_net[21]), .p(p_net[21]), .g_prec(g_net[20]), .p_prec(
p_net[20]), .g_out(\pg_1[10][0] ), .p_out(\pg_1[10][1] ) );
pg_44 xPG_1_11 ( .g(g_net[23]), .p(p_net[23]), .g_prec(g_net[22]), .p_prec(
p_net[22]), .g_out(\pg_1[11][0] ), .p_out(\pg_1[11][1] ) );
pg_43 xPG_1_12 ( .g(g_net[25]), .p(p_net[25]), .g_prec(g_net[24]), .p_prec(
p_net[24]), .g_out(\pg_1[12][0] ), .p_out(\pg_1[12][1] ) );
pg_42 xPG_1_13 ( .g(g_net[27]), .p(p_net[27]), .g_prec(g_net[26]), .p_prec(
p_net[26]), .p_out(\pg_1[13][1] ), .g_out_BAR(\pg_1[13][0] ) );
g_18 xG_2_0 ( .g(\pg_1[1][0] ), .p(\pg_1[1][1] ), .g_prec(\pg_1[0][0] ),
.g_out(Cout[0]) );
pg_39 xPG_2_1 ( .g(\pg_1[3][0] ), .p(\pg_1[3][1] ), .g_prec(\pg_1[2][0] ),
.p_prec(\pg_1[2][1] ), .g_out(\pg_n[2][1][0] ), .p_out(\pg_n[2][1][1] ) );
pg_38 xPG_2_2 ( .g(\pg_1[5][0] ), .p(\pg_1[5][1] ), .g_prec(\pg_1[4][0] ),
.p_prec(\pg_1[4][1] ), .g_out(\pg_n[2][2][0] ), .p_out(\pg_n[2][2][1] ) );
pg_37 xPG_2_3 ( .g(\pg_1[7][0] ), .p(\pg_1[7][1] ), .g_prec(\pg_1[6][0] ),
.p_prec(\pg_1[6][1] ), .g_out(\pg_n[2][3][0] ), .p_out(\pg_n[2][3][1] ) );
pg_36 xPG_2_4 ( .g(\pg_1[9][0] ), .p(\pg_1[9][1] ), .g_prec(\pg_1[8][0] ),
.p_prec(\pg_1[8][1] ), .g_out(\pg_n[2][4][0] ), .p_out(\pg_n[2][4][1] ) );
pg_35 xPG_2_5 ( .g(\pg_1[11][0] ), .p(\pg_1[11][1] ), .g_prec(\pg_1[10][0] ),
.p_prec(\pg_1[10][1] ), .g_out(\pg_n[2][5][0] ), .p_out(
\pg_n[2][5][1] ) );
pg_34 xPG_2_6 ( .p(\pg_1[13][1] ), .g_prec(\pg_1[12][0] ), .p_prec(
\pg_1[12][1] ), .g_out(\pg_n[2][6][0] ), .p_out(\pg_n[2][6][1] ),
.g_BAR(\pg_1[13][0] ) );
g_17 xG_3_1 ( .g(\pg_n[2][1][0] ), .p(\pg_n[2][1][1] ), .g_prec(Cout[0]),
.g_out(Cout[1]) );
g_16 xG_4_2 ( .g(\pg_n[2][2][0] ), .p(\pg_n[2][2][1] ), .g_prec(Cout[1]),
.g_out(Cout[2]) );
g_15 xG_4_3 ( .g(\pg_n[3][3][0] ), .p(\pg_n[3][3][1] ), .g_prec(Cout[1]),
.g_out(Cout[3]) );
g_14 xG_5_4 ( .g(\pg_n[2][4][0] ), .p(\pg_n[2][4][1] ), .g_prec(Cout[3]),
.g_out(Cout[4]) );
g_13 xG_5_5 ( .g(\pg_n[3][5][0] ), .p(\pg_n[3][5][1] ), .g_prec(Cout[3]),
.g_out(Cout[5]) );
g_12 xG_5_6 ( .g(\pg_n[4][6][0] ), .p(\pg_n[4][6][1] ), .g_prec(Cout[3]),
.g_out(Cout[6]) );
pg_32 xPG_3_3 ( .g(\pg_n[2][3][0] ), .p(\pg_n[2][3][1] ), .g_prec(
\pg_n[2][2][0] ), .p_prec(\pg_n[2][2][1] ), .g_out(\pg_n[3][3][0] ),
.p_out(\pg_n[3][3][1] ) );
pg_31 xPG_3_5 ( .g(\pg_n[2][5][0] ), .p(\pg_n[2][5][1] ), .g_prec(
\pg_n[2][4][0] ), .p_prec(\pg_n[2][4][1] ), .g_out(\pg_n[3][5][0] ),
.p_out(\pg_n[3][5][1] ) );
pg_29 xPG_4_6 ( .g(\pg_n[2][6][0] ), .p(\pg_n[2][6][1] ), .g_prec(
\pg_n[3][5][0] ), .p_prec(\pg_n[3][5][1] ), .g_out(\pg_n[4][6][0] ),
.p_out(\pg_n[4][6][1] ) );
endmodule
module xor_gen_N32_0 ( A, B, S );
input [31:0] A;
output [31:0] S;
input B;
assign S[31] = A[31];
assign S[30] = A[30];
assign S[29] = A[29];
assign S[28] = A[28];
assign S[27] = A[27];
assign S[26] = A[26];
assign S[25] = A[25];
assign S[24] = A[24];
assign S[23] = A[23];
assign S[22] = A[22];
assign S[21] = A[21];
assign S[20] = A[20];
assign S[19] = A[19];
assign S[18] = A[18];
assign S[17] = A[17];
assign S[16] = A[16];
assign S[15] = A[15];
assign S[14] = A[14];
assign S[13] = A[13];
assign S[12] = A[12];
assign S[11] = A[11];
assign S[10] = A[10];
assign S[9] = A[9];
assign S[8] = A[8];
assign S[7] = A[7];
assign S[6] = A[6];
assign S[5] = A[5];
assign S[4] = A[4];
assign S[3] = A[3];
assign S[2] = A[2];
assign S[1] = A[1];
assign S[0] = A[0];
endmodule
module SNPS_CLOCK_GATE_HIGH_ff32_en_IR ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3579, net3581, net3582, net3585;
assign net3579 = CLK;
assign ENCLK = net3581;
assign net3582 = EN;
DLL_X1 latch ( .D(net3582), .GN(net3579), .Q(net3585) );
AND2_X1 main_gate ( .A1(net3585), .A2(net3579), .ZN(net3581) );
endmodule
module SNPS_CLOCK_GATE_HIGH_ff32_en_0 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3594, net3596, net3597, net3600;
assign net3594 = CLK;
assign ENCLK = net3596;
assign net3597 = EN;
DLL_X1 latch ( .D(net3597), .GN(net3594), .Q(net3600) );
AND2_X1 main_gate ( .A1(net3600), .A2(net3594), .ZN(net3596) );
endmodule
module ff32_SIZE5 ( D, clk, rst, Q );
input [4:0] D;
output [4:0] Q;
input clk, rst;
wire n9;
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(clk), .RN(n9), .Q(Q[4]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(clk), .RN(n9), .Q(Q[0]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(clk), .RN(n9), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(clk), .RN(n9), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(clk), .RN(n9), .Q(Q[1]) );
INV_X1 U3 ( .A(rst), .ZN(n9) );
endmodule
module ff32_SIZE32 ( D, clk, rst, Q );
input [31:0] D;
output [31:0] Q;
input clk, rst;
wire n32;
DFFR_X1 \Q_reg[31] ( .D(D[31]), .CK(clk), .RN(n32), .Q(Q[31]) );
DFFR_X1 \Q_reg[30] ( .D(D[30]), .CK(clk), .RN(n32), .Q(Q[30]) );
DFFR_X1 \Q_reg[29] ( .D(D[29]), .CK(clk), .RN(n32), .Q(Q[29]) );
DFFR_X1 \Q_reg[28] ( .D(D[28]), .CK(clk), .RN(n32), .Q(Q[28]) );
DFFR_X1 \Q_reg[27] ( .D(D[27]), .CK(clk), .RN(n32), .Q(Q[27]) );
DFFR_X1 \Q_reg[26] ( .D(D[26]), .CK(clk), .RN(n32), .Q(Q[26]) );
DFFR_X1 \Q_reg[25] ( .D(D[25]), .CK(clk), .RN(n32), .Q(Q[25]) );
DFFR_X1 \Q_reg[24] ( .D(D[24]), .CK(clk), .RN(n32), .Q(Q[24]) );
DFFR_X1 \Q_reg[23] ( .D(D[23]), .CK(clk), .RN(n32), .Q(Q[23]) );
DFFR_X1 \Q_reg[22] ( .D(D[22]), .CK(clk), .RN(n32), .Q(Q[22]) );
DFFR_X1 \Q_reg[21] ( .D(D[21]), .CK(clk), .RN(n32), .Q(Q[21]) );
DFFR_X1 \Q_reg[20] ( .D(D[20]), .CK(clk), .RN(n32), .Q(Q[20]) );
DFFR_X1 \Q_reg[19] ( .D(D[19]), .CK(clk), .RN(n32), .Q(Q[19]) );
DFFR_X1 \Q_reg[18] ( .D(D[18]), .CK(clk), .RN(n32), .Q(Q[18]) );
DFFR_X1 \Q_reg[17] ( .D(D[17]), .CK(clk), .RN(n32), .Q(Q[17]) );
DFFR_X1 \Q_reg[16] ( .D(D[16]), .CK(clk), .RN(n32), .Q(Q[16]) );
DFFR_X1 \Q_reg[15] ( .D(D[15]), .CK(clk), .RN(n32), .Q(Q[15]) );
DFFR_X1 \Q_reg[14] ( .D(D[14]), .CK(clk), .RN(n32), .Q(Q[14]) );
DFFR_X1 \Q_reg[13] ( .D(D[13]), .CK(clk), .RN(n32), .Q(Q[13]) );
DFFR_X1 \Q_reg[12] ( .D(D[12]), .CK(clk), .RN(n32), .Q(Q[12]) );
DFFR_X1 \Q_reg[11] ( .D(D[11]), .CK(clk), .RN(n32), .Q(Q[11]) );
DFFR_X1 \Q_reg[10] ( .D(D[10]), .CK(clk), .RN(n32), .Q(Q[10]) );
DFFR_X1 \Q_reg[9] ( .D(D[9]), .CK(clk), .RN(n32), .Q(Q[9]) );
DFFR_X1 \Q_reg[8] ( .D(D[8]), .CK(clk), .RN(n32), .Q(Q[8]) );
DFFR_X1 \Q_reg[7] ( .D(D[7]), .CK(clk), .RN(n32), .Q(Q[7]) );
DFFR_X1 \Q_reg[6] ( .D(D[6]), .CK(clk), .RN(n32), .Q(Q[6]) );
DFFR_X1 \Q_reg[5] ( .D(D[5]), .CK(clk), .RN(n32), .Q(Q[5]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(clk), .RN(n32), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(clk), .RN(n32), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(clk), .RN(n32), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(clk), .RN(n32), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(clk), .RN(n32), .Q(Q[0]) );
INV_X2 U3 ( .A(rst), .ZN(n32) );
endmodule
module mux41_MUX_SIZE5 ( IN0, IN1, IN2, IN3, CTRL, OUT1 );
input [4:0] IN0;
input [4:0] IN1;
input [4:0] IN2;
input [4:0] IN3;
input [1:0] CTRL;
output [4:0] OUT1;
wire n3, n4, n5, n6, n7, n9, n10, n11, n12, n13, n14, n15, n16, n17;
NAND2_X1 U7 ( .A1(n11), .A2(n12), .ZN(OUT1[2]) );
AOI22_X1 U17 ( .A1(n6), .A2(IN2[0]), .B1(n7), .B2(IN1[0]), .ZN(n15) );
NAND2_X1 U4 ( .A1(n9), .A2(n10), .ZN(OUT1[3]) );
NAND2_X1 U10 ( .A1(n13), .A2(n14), .ZN(OUT1[1]) );
INV_X1 U20 ( .A(CTRL[1]), .ZN(n17) );
AND2_X1 U18 ( .A1(n17), .A2(CTRL[0]), .ZN(n7) );
NOR2_X1 U19 ( .A1(CTRL[0]), .A2(n17), .ZN(n6) );
AND2_X1 U16 ( .A1(CTRL[0]), .A2(CTRL[1]), .ZN(n5) );
NAND2_X1 U13 ( .A1(n15), .A2(n16), .ZN(OUT1[0]) );
INV_X1 U1 ( .A(n5), .ZN(n16) );
AOI21_X1 U2 ( .B1(n6), .B2(IN2[1]), .A(n5), .ZN(n14) );
NAND2_X1 U3 ( .A1(n7), .A2(IN1[1]), .ZN(n13) );
AOI21_X1 U5 ( .B1(n6), .B2(IN2[2]), .A(n5), .ZN(n12) );
NAND2_X1 U6 ( .A1(n7), .A2(IN1[2]), .ZN(n11) );
AOI21_X1 U8 ( .B1(n6), .B2(IN2[3]), .A(n5), .ZN(n10) );
NAND2_X1 U9 ( .A1(n7), .A2(IN1[3]), .ZN(n9) );
AOI21_X1 U11 ( .B1(n6), .B2(IN2[4]), .A(n5), .ZN(n4) );
NAND2_X1 U12 ( .A1(n7), .A2(IN1[4]), .ZN(n3) );
NAND2_X1 U14 ( .A1(n3), .A2(n4), .ZN(OUT1[4]) );
endmodule
module real_alu_DATA_SIZE32 ( IN1, IN2, ALUW_i, DOUT, stall_o, Clock, Reset );
input [31:0] IN1;
input [31:0] IN2;
input [12:0] ALUW_i;
output [31:0] DOUT;
input Clock, Reset;
output stall_o;
wire mux_sign, sign_booth_to_add, valid_from_booth, carry_from_adder,
overflow, comp_out, n9, n11, n13, n14, n15, n16, n17, n18, n19, n20,
n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34,
n35, n36, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50,
n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64,
n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n84, n85, n1, n2, n3, n4, n5, n6, n7, n8, n10, n12, n37,
n38, n81, n83, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96,
n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119;
wire [31:0] mux_A;
wire [31:0] A_booth_to_add;
wire [31:0] mux_B;
wire [31:0] B_booth_to_add;
wire [31:0] mult_out;
wire [31:0] sum_out;
wire [31:0] shift_out;
wire [31:0] lu_out;
MUX2_X1 U120 ( .A(B_booth_to_add[31]), .B(IN2[31]), .S(n9), .Z(mux_B[31]) );
MUX2_X1 U121 ( .A(B_booth_to_add[30]), .B(IN2[30]), .S(n9), .Z(mux_B[30]) );
MUX2_X1 U123 ( .A(B_booth_to_add[29]), .B(IN2[29]), .S(n9), .Z(mux_B[29]) );
MUX2_X1 U124 ( .A(B_booth_to_add[28]), .B(IN2[28]), .S(n9), .Z(mux_B[28]) );
MUX2_X1 U125 ( .A(B_booth_to_add[27]), .B(IN2[27]), .S(n9), .Z(mux_B[27]) );
MUX2_X1 U126 ( .A(B_booth_to_add[26]), .B(IN2[26]), .S(n9), .Z(mux_B[26]) );
MUX2_X1 U128 ( .A(B_booth_to_add[24]), .B(IN2[24]), .S(n9), .Z(mux_B[24]) );
MUX2_X1 U132 ( .A(B_booth_to_add[20]), .B(IN2[20]), .S(n9), .Z(mux_B[20]) );
MUX2_X1 U134 ( .A(B_booth_to_add[19]), .B(IN2[19]), .S(n9), .Z(mux_B[19]) );
MUX2_X1 U138 ( .A(B_booth_to_add[15]), .B(IN2[15]), .S(n9), .Z(mux_B[15]) );
MUX2_X1 U139 ( .A(B_booth_to_add[14]), .B(IN2[14]), .S(n9), .Z(mux_B[14]) );
MUX2_X1 U141 ( .A(B_booth_to_add[12]), .B(IN2[12]), .S(n9), .Z(mux_B[12]) );
MUX2_X1 U143 ( .A(B_booth_to_add[10]), .B(IN2[10]), .S(n9), .Z(mux_B[10]) );
MUX2_X1 U145 ( .A(A_booth_to_add[9]), .B(IN1[9]), .S(n9), .Z(mux_A[9]) );
MUX2_X1 U146 ( .A(A_booth_to_add[8]), .B(IN1[8]), .S(n9), .Z(mux_A[8]) );
MUX2_X1 U147 ( .A(A_booth_to_add[7]), .B(IN1[7]), .S(n9), .Z(mux_A[7]) );
MUX2_X1 U148 ( .A(A_booth_to_add[6]), .B(IN1[6]), .S(n9), .Z(mux_A[6]) );
MUX2_X1 U150 ( .A(A_booth_to_add[4]), .B(IN1[4]), .S(n9), .Z(mux_A[4]) );
MUX2_X1 U152 ( .A(A_booth_to_add[31]), .B(IN1[31]), .S(n9), .Z(mux_A[31]) );
MUX2_X1 U153 ( .A(A_booth_to_add[30]), .B(IN1[30]), .S(n9), .Z(mux_A[30]) );
MUX2_X1 U154 ( .A(A_booth_to_add[2]), .B(IN1[2]), .S(n9), .Z(mux_A[2]) );
MUX2_X1 U155 ( .A(A_booth_to_add[29]), .B(IN1[29]), .S(n9), .Z(mux_A[29]) );
MUX2_X1 U156 ( .A(A_booth_to_add[28]), .B(IN1[28]), .S(n9), .Z(mux_A[28]) );
MUX2_X1 U157 ( .A(A_booth_to_add[27]), .B(IN1[27]), .S(n9), .Z(mux_A[27]) );
MUX2_X1 U158 ( .A(A_booth_to_add[26]), .B(IN1[26]), .S(n9), .Z(mux_A[26]) );
MUX2_X1 U159 ( .A(A_booth_to_add[25]), .B(IN1[25]), .S(n9), .Z(mux_A[25]) );
MUX2_X1 U160 ( .A(A_booth_to_add[24]), .B(IN1[24]), .S(n9), .Z(mux_A[24]) );
MUX2_X1 U161 ( .A(A_booth_to_add[23]), .B(IN1[23]), .S(n9), .Z(mux_A[23]) );
MUX2_X1 U162 ( .A(A_booth_to_add[22]), .B(IN1[22]), .S(n9), .Z(mux_A[22]) );
MUX2_X1 U163 ( .A(A_booth_to_add[21]), .B(IN1[21]), .S(n9), .Z(mux_A[21]) );
MUX2_X1 U164 ( .A(A_booth_to_add[20]), .B(IN1[20]), .S(n9), .Z(mux_A[20]) );
MUX2_X1 U166 ( .A(A_booth_to_add[19]), .B(IN1[19]), .S(n9), .Z(mux_A[19]) );
MUX2_X1 U167 ( .A(A_booth_to_add[18]), .B(IN1[18]), .S(n9), .Z(mux_A[18]) );
MUX2_X1 U168 ( .A(A_booth_to_add[17]), .B(IN1[17]), .S(n9), .Z(mux_A[17]) );
MUX2_X1 U169 ( .A(A_booth_to_add[16]), .B(IN1[16]), .S(n9), .Z(mux_A[16]) );
MUX2_X1 U170 ( .A(A_booth_to_add[15]), .B(IN1[15]), .S(n9), .Z(mux_A[15]) );
MUX2_X1 U171 ( .A(A_booth_to_add[14]), .B(IN1[14]), .S(n9), .Z(mux_A[14]) );
MUX2_X1 U172 ( .A(A_booth_to_add[13]), .B(IN1[13]), .S(n9), .Z(mux_A[13]) );
MUX2_X1 U173 ( .A(A_booth_to_add[12]), .B(IN1[12]), .S(n9), .Z(mux_A[12]) );
MUX2_X1 U174 ( .A(A_booth_to_add[11]), .B(IN1[11]), .S(n9), .Z(mux_A[11]) );
MUX2_X1 U175 ( .A(A_booth_to_add[10]), .B(IN1[10]), .S(n9), .Z(mux_A[10]) );
NAND3_X1 U178 ( .A1(n84), .A2(n85), .A3(ALUW_i[12]), .ZN(n32) );
simple_booth_add_ext_N16 MULT ( .Clock(Clock), .Reset(Reset), .sign(
ALUW_i[0]), .enable(ALUW_i[1]), .valid(valid_from_booth), .A({
IN1[15:1], n108}), .B({n112, n110, IN2[13:12], n111, IN2[10], n113,
IN2[8], n107, IN2[6], n114, IN2[4], n117, n81, n115, n116}),
.A_to_add(A_booth_to_add), .B_to_add(B_booth_to_add), .sign_to_add(
sign_booth_to_add), .final_out(mult_out), .ACC_from_add({
sum_out[31:24], n87, n86, n38, n88, sum_out[19:0]}) );
p4add_N32_logN5_1 ADDER ( .A(mux_A), .B(mux_B), .Cin(1'b0), .sign(mux_sign),
.S(sum_out), .Cout_BAR(carry_from_adder) );
comparator_M32 COMP ( .V(overflow), .SUM(sum_out), .sel(ALUW_i[4:2]), .sign(
ALUW_i[0]), .S(comp_out), .C_BAR(carry_from_adder) );
shifter SHIFT ( .A({IN1[31:1], n108}), .B({IN2[4], n117, n81, n115, n116}),
.LOGIC_ARITH(ALUW_i[8]), .LEFT_RIGHT(ALUW_i[9]), .OUTPUT(shift_out) );
logic_unit_SIZE32 LU ( .IN1({IN1[31:1], n108}), .IN2({IN2[31:24], n12, n109,
IN2[21:20], n106, IN2[18:16], n112, n110, IN2[13:12], n111, IN2[10],
n113, IN2[8], n107, IN2[6], n114, IN2[4], n117, n81, n115, n116}),
.CTRL(ALUW_i[6:5]), .OUT1(lu_out) );
MUX2_X1 U114 ( .A(B_booth_to_add[8]), .B(IN2[8]), .S(n9), .Z(mux_B[8]) );
MUX2_X1 U137 ( .A(B_booth_to_add[16]), .B(IN2[16]), .S(n9), .Z(mux_B[16]) );
AOI22_X1 U13 ( .A1(n15), .A2(shift_out[7]), .B1(n119), .B2(sum_out[7]), .ZN(
n23) );
NAND2_X1 U12 ( .A1(n22), .A2(n23), .ZN(DOUT[7]) );
AOI22_X1 U38 ( .A1(n83), .A2(shift_out[29]), .B1(n119), .B2(sum_out[29]),
.ZN(n40) );
NAND2_X1 U37 ( .A1(n39), .A2(n40), .ZN(DOUT[29]) );
AOI22_X1 U56 ( .A1(n83), .A2(shift_out[23]), .B1(n119), .B2(n87), .ZN(n52)
);
NAND2_X1 U55 ( .A1(n51), .A2(n52), .ZN(DOUT[23]) );
AOI22_X1 U83 ( .A1(n83), .A2(shift_out[15]), .B1(n119), .B2(sum_out[15]),
.ZN(n70) );
NAND2_X1 U82 ( .A1(n69), .A2(n70), .ZN(DOUT[15]) );
AOI222_X1 U72 ( .A1(n106), .A2(n17), .B1(n118), .B2(lu_out[19]), .C1(n19),
.C2(mult_out[19]), .ZN(n61) );
AOI22_X1 U71 ( .A1(n83), .A2(shift_out[19]), .B1(n119), .B2(sum_out[19]),
.ZN(n62) );
NAND2_X1 U70 ( .A1(n61), .A2(n62), .ZN(DOUT[19]) );
AOI222_X1 U75 ( .A1(IN2[18]), .A2(n17), .B1(n18), .B2(lu_out[18]), .C1(n19),
.C2(mult_out[18]), .ZN(n63) );
AOI22_X1 U74 ( .A1(n83), .A2(shift_out[18]), .B1(n119), .B2(sum_out[18]),
.ZN(n64) );
NAND2_X1 U73 ( .A1(n63), .A2(n64), .ZN(DOUT[18]) );
AOI222_X1 U78 ( .A1(IN2[17]), .A2(n17), .B1(n118), .B2(lu_out[17]), .C1(n19),
.C2(mult_out[17]), .ZN(n65) );
AOI22_X1 U77 ( .A1(n83), .A2(shift_out[17]), .B1(n119), .B2(sum_out[17]),
.ZN(n66) );
NAND2_X1 U76 ( .A1(n65), .A2(n66), .ZN(DOUT[17]) );
AOI222_X1 U51 ( .A1(IN2[25]), .A2(n17), .B1(n118), .B2(lu_out[25]), .C1(n19),
.C2(mult_out[25]), .ZN(n47) );
AOI22_X1 U50 ( .A1(n83), .A2(shift_out[25]), .B1(n119), .B2(sum_out[25]),
.ZN(n48) );
NAND2_X1 U49 ( .A1(n47), .A2(n48), .ZN(DOUT[25]) );
AOI222_X1 U45 ( .A1(IN2[27]), .A2(n17), .B1(n118), .B2(lu_out[27]), .C1(n19),
.C2(mult_out[27]), .ZN(n43) );
AOI22_X1 U44 ( .A1(n83), .A2(shift_out[27]), .B1(n119), .B2(sum_out[27]),
.ZN(n44) );
NAND2_X1 U43 ( .A1(n43), .A2(n44), .ZN(DOUT[27]) );
AOI222_X1 U48 ( .A1(IN2[26]), .A2(n17), .B1(n118), .B2(lu_out[26]), .C1(n19),
.C2(mult_out[26]), .ZN(n45) );
AOI22_X1 U47 ( .A1(n83), .A2(shift_out[26]), .B1(n119), .B2(sum_out[26]),
.ZN(n46) );
NAND2_X1 U46 ( .A1(n45), .A2(n46), .ZN(DOUT[26]) );
AOI222_X1 U33 ( .A1(IN2[30]), .A2(n17), .B1(n118), .B2(lu_out[30]), .C1(n19),
.C2(mult_out[30]), .ZN(n35) );
AOI22_X1 U32 ( .A1(n83), .A2(shift_out[30]), .B1(n119), .B2(sum_out[30]),
.ZN(n36) );
NAND2_X1 U31 ( .A1(n35), .A2(n36), .ZN(DOUT[30]) );
AOI222_X1 U54 ( .A1(IN2[24]), .A2(n17), .B1(n118), .B2(lu_out[24]), .C1(n19),
.C2(mult_out[24]), .ZN(n49) );
NAND2_X1 U52 ( .A1(n49), .A2(n50), .ZN(DOUT[24]) );
AOI222_X1 U60 ( .A1(n109), .A2(n17), .B1(n118), .B2(lu_out[22]), .C1(n19),
.C2(mult_out[22]), .ZN(n53) );
NAND2_X1 U58 ( .A1(n53), .A2(n54), .ZN(DOUT[22]) );
AOI222_X1 U63 ( .A1(IN2[21]), .A2(n17), .B1(n118), .B2(lu_out[21]), .C1(n19),
.C2(mult_out[21]), .ZN(n55) );
NAND2_X1 U61 ( .A1(n55), .A2(n56), .ZN(DOUT[21]) );
AOI22_X1 U28 ( .A1(n118), .A2(lu_out[31]), .B1(n19), .B2(mult_out[31]), .ZN(
n34) );
OAI211_X1 U27 ( .C1(n32), .C2(n11), .A(n33), .B(n34), .ZN(DOUT[31]) );
AOI222_X1 U66 ( .A1(IN2[20]), .A2(n17), .B1(n118), .B2(lu_out[20]), .C1(n19),
.C2(mult_out[20]), .ZN(n57) );
NAND2_X1 U64 ( .A1(n57), .A2(n58), .ZN(DOUT[20]) );
AOI222_X1 U42 ( .A1(IN2[28]), .A2(n17), .B1(n118), .B2(lu_out[28]), .C1(n19),
.C2(mult_out[28]), .ZN(n41) );
NAND2_X1 U40 ( .A1(n41), .A2(n42), .ZN(DOUT[28]) );
AOI222_X1 U87 ( .A1(n110), .A2(n17), .B1(n118), .B2(lu_out[14]), .C1(n19),
.C2(mult_out[14]), .ZN(n71) );
AOI22_X1 U86 ( .A1(n83), .A2(shift_out[14]), .B1(n119), .B2(sum_out[14]),
.ZN(n72) );
NAND2_X1 U85 ( .A1(n71), .A2(n72), .ZN(DOUT[14]) );
AOI222_X1 U26 ( .A1(n117), .A2(n17), .B1(n118), .B2(lu_out[3]), .C1(n19),
.C2(mult_out[3]), .ZN(n30) );
AOI22_X1 U25 ( .A1(n83), .A2(shift_out[3]), .B1(n119), .B2(sum_out[3]), .ZN(
n31) );
NAND2_X1 U24 ( .A1(n30), .A2(n31), .ZN(DOUT[3]) );
AOI22_X1 U92 ( .A1(n83), .A2(shift_out[12]), .B1(n119), .B2(sum_out[12]),
.ZN(n76) );
NAND2_X1 U91 ( .A1(n75), .A2(n76), .ZN(DOUT[12]) );
AOI22_X1 U95 ( .A1(n83), .A2(shift_out[11]), .B1(n119), .B2(sum_out[11]),
.ZN(n78) );
NAND2_X1 U94 ( .A1(n77), .A2(n78), .ZN(DOUT[11]) );
AOI222_X1 U81 ( .A1(IN2[16]), .A2(n17), .B1(n118), .B2(lu_out[16]), .C1(n19),
.C2(mult_out[16]), .ZN(n67) );
AOI22_X1 U80 ( .A1(n83), .A2(shift_out[16]), .B1(n119), .B2(sum_out[16]),
.ZN(n68) );
NAND2_X1 U79 ( .A1(n67), .A2(n68), .ZN(DOUT[16]) );
NAND2_X1 U88 ( .A1(n73), .A2(n74), .ZN(DOUT[13]) );
AOI22_X1 U7 ( .A1(n15), .A2(shift_out[9]), .B1(n119), .B2(sum_out[9]), .ZN(
n14) );
NAND2_X1 U6 ( .A1(n13), .A2(n14), .ZN(DOUT[9]) );
AOI22_X1 U16 ( .A1(n83), .A2(shift_out[6]), .B1(n16), .B2(sum_out[6]), .ZN(
n25) );
NAND2_X1 U15 ( .A1(n24), .A2(n25), .ZN(DOUT[6]) );
AOI222_X1 U11 ( .A1(IN2[8]), .A2(n17), .B1(n118), .B2(lu_out[8]), .C1(n19),
.C2(mult_out[8]), .ZN(n20) );
AOI22_X1 U10 ( .A1(n83), .A2(shift_out[8]), .B1(n119), .B2(sum_out[8]), .ZN(
n21) );
NAND2_X1 U9 ( .A1(n20), .A2(n21), .ZN(DOUT[8]) );
AOI22_X1 U98 ( .A1(n83), .A2(shift_out[10]), .B1(n119), .B2(sum_out[10]),
.ZN(n80) );
NAND2_X1 U97 ( .A1(n79), .A2(n80), .ZN(DOUT[10]) );
AOI22_X1 U19 ( .A1(n83), .A2(shift_out[5]), .B1(n119), .B2(sum_out[5]), .ZN(
n27) );
NAND2_X1 U18 ( .A1(n26), .A2(n27), .ZN(DOUT[5]) );
AOI222_X1 U23 ( .A1(IN2[4]), .A2(n17), .B1(n118), .B2(lu_out[4]), .C1(n19),
.C2(mult_out[4]), .ZN(n28) );
AOI22_X1 U22 ( .A1(n83), .A2(shift_out[4]), .B1(n119), .B2(sum_out[4]), .ZN(
n29) );
NAND2_X1 U21 ( .A1(n28), .A2(n29), .ZN(DOUT[4]) );
AOI22_X1 U68 ( .A1(n83), .A2(shift_out[1]), .B1(n119), .B2(sum_out[1]), .ZN(
n60) );
NAND2_X1 U67 ( .A1(n59), .A2(n60), .ZN(DOUT[1]) );
INV_X1 U108 ( .A(ALUW_i[11]), .ZN(n84) );
MUX2_X2 U112 ( .A(sign_booth_to_add), .B(ALUW_i[7]), .S(n9), .Z(mux_sign) );
NOR2_X1 U2 ( .A1(valid_from_booth), .A2(n9), .ZN(stall_o) );
MUX2_X1 U3 ( .A(B_booth_to_add[23]), .B(IN2[23]), .S(n9), .Z(mux_B[23]) );
AOI22_X1 U4 ( .A1(ALUW_i[1]), .A2(B_booth_to_add[5]), .B1(n9), .B2(IN2[5]),
.ZN(n1) );
INV_X1 U5 ( .A(n1), .ZN(mux_B[5]) );
MUX2_X1 U8 ( .A(B_booth_to_add[6]), .B(IN2[6]), .S(n9), .Z(mux_B[6]) );
MUX2_X1 U14 ( .A(B_booth_to_add[3]), .B(IN2[3]), .S(n9), .Z(mux_B[3]) );
AOI222_X1 U17 ( .A1(sum_out[0]), .A2(n119), .B1(n118), .B2(lu_out[0]), .C1(
n116), .C2(n17), .ZN(n2) );
INV_X1 U20 ( .A(n2), .ZN(n3) );
AOI21_X1 U29 ( .B1(n19), .B2(mult_out[0]), .A(n3), .ZN(n104) );
AOI22_X1 U30 ( .A1(ALUW_i[1]), .A2(B_booth_to_add[13]), .B1(n9), .B2(IN2[13]), .ZN(n4) );
INV_X1 U34 ( .A(n4), .ZN(mux_B[13]) );
MUX2_X1 U35 ( .A(A_booth_to_add[5]), .B(IN1[5]), .S(n9), .Z(mux_A[5]) );
MUX2_X1 U36 ( .A(B_booth_to_add[7]), .B(IN2[7]), .S(n9), .Z(mux_B[7]) );
INV_X1 U39 ( .A(ALUW_i[10]), .ZN(n5) );
NOR3_X1 U41 ( .A1(ALUW_i[12]), .A2(n84), .A3(n5), .ZN(n90) );
INV_X1 U53 ( .A(n17), .ZN(n6) );
INV_X1 U57 ( .A(n81), .ZN(n7) );
AOI22_X1 U59 ( .A1(mult_out[2]), .A2(n19), .B1(lu_out[2]), .B2(n118), .ZN(n8) );
AOI22_X1 U62 ( .A1(sum_out[2]), .A2(n119), .B1(shift_out[2]), .B2(n83), .ZN(
n10) );
OAI211_X1 U65 ( .C1(n6), .C2(n7), .A(n8), .B(n10), .ZN(DOUT[2]) );
CLKBUF_X1 U69 ( .A(IN2[23]), .Z(n12) );
CLKBUF_X1 U84 ( .A(sum_out[31]), .Z(n37) );
CLKBUF_X1 U89 ( .A(sum_out[21]), .Z(n38) );
CLKBUF_X1 U90 ( .A(IN2[2]), .Z(n81) );
BUF_X1 U93 ( .A(IN2[3]), .Z(n117) );
BUF_X1 U96 ( .A(IN2[15]), .Z(n112) );
BUF_X1 U99 ( .A(IN1[0]), .Z(n108) );
AND2_X1 U100 ( .A1(n105), .A2(n104), .ZN(n89) );
BUF_X1 U101 ( .A(IN2[5]), .Z(n114) );
BUF_X1 U102 ( .A(IN2[14]), .Z(n110) );
BUF_X1 U103 ( .A(IN2[1]), .Z(n115) );
BUF_X1 U104 ( .A(IN2[9]), .Z(n113) );
BUF_X1 U105 ( .A(n18), .Z(n118) );
AND2_X2 U106 ( .A1(n32), .A2(ALUW_i[12]), .ZN(n19) );
BUF_X1 U107 ( .A(n16), .Z(n119) );
BUF_X2 U109 ( .A(n15), .Z(n83) );
INV_X2 U110 ( .A(n32), .ZN(n17) );
CLKBUF_X1 U111 ( .A(sum_out[22]), .Z(n86) );
CLKBUF_X1 U113 ( .A(sum_out[23]), .Z(n87) );
CLKBUF_X1 U115 ( .A(sum_out[20]), .Z(n88) );
NAND2_X1 U116 ( .A1(n103), .A2(n89), .ZN(DOUT[0]) );
AOI222_X1 U117 ( .A1(IN2[13]), .A2(n17), .B1(n18), .B2(lu_out[13]), .C1(n19),
.C2(mult_out[13]), .ZN(n73) );
NAND2_X1 U118 ( .A1(comp_out), .A2(n90), .ZN(n103) );
CLKBUF_X1 U119 ( .A(IN2[11]), .Z(n111) );
CLKBUF_X1 U122 ( .A(IN2[22]), .Z(n109) );
CLKBUF_X1 U127 ( .A(IN2[19]), .Z(n106) );
CLKBUF_X1 U129 ( .A(IN2[7]), .Z(n107) );
CLKBUF_X1 U130 ( .A(IN2[0]), .Z(n116) );
INV_X1 U131 ( .A(ALUW_i[10]), .ZN(n85) );
INV_X1 U133 ( .A(IN2[31]), .ZN(n11) );
OR2_X1 U135 ( .A1(n9), .A2(n97), .ZN(n92) );
INV_X1 U136 ( .A(B_booth_to_add[11]), .ZN(n97) );
OR2_X1 U140 ( .A1(n9), .A2(n99), .ZN(n93) );
INV_X1 U142 ( .A(B_booth_to_add[0]), .ZN(n99) );
OR2_X1 U144 ( .A1(n9), .A2(n95), .ZN(n91) );
INV_X1 U149 ( .A(B_booth_to_add[1]), .ZN(n95) );
INV_X4 U151 ( .A(ALUW_i[1]), .ZN(n9) );
NOR3_X1 U165 ( .A1(ALUW_i[12]), .A2(ALUW_i[10]), .A3(n84), .ZN(n15) );
NOR3_X1 U176 ( .A1(ALUW_i[11]), .A2(ALUW_i[12]), .A3(n85), .ZN(n18) );
NOR3_X1 U177 ( .A1(ALUW_i[11]), .A2(ALUW_i[12]), .A3(ALUW_i[10]), .ZN(n16)
);
AOI222_X1 U179 ( .A1(n115), .A2(n17), .B1(n118), .B2(lu_out[1]), .C1(n19),
.C2(mult_out[1]), .ZN(n59) );
AOI222_X1 U180 ( .A1(n113), .A2(n17), .B1(n18), .B2(lu_out[9]), .C1(n19),
.C2(mult_out[9]), .ZN(n13) );
AOI222_X1 U181 ( .A1(n111), .A2(n17), .B1(n18), .B2(lu_out[11]), .C1(n19),
.C2(mult_out[11]), .ZN(n77) );
AOI222_X1 U182 ( .A1(n112), .A2(n17), .B1(n118), .B2(lu_out[15]), .C1(n19),
.C2(mult_out[15]), .ZN(n69) );
AOI222_X1 U183 ( .A1(n12), .A2(n17), .B1(n18), .B2(lu_out[23]), .C1(n19),
.C2(mult_out[23]), .ZN(n51) );
AOI222_X1 U184 ( .A1(IN2[29]), .A2(n17), .B1(n118), .B2(lu_out[29]), .C1(n19), .C2(mult_out[29]), .ZN(n39) );
AOI222_X1 U185 ( .A1(n107), .A2(n17), .B1(n118), .B2(lu_out[7]), .C1(n19),
.C2(mult_out[7]), .ZN(n22) );
NAND2_X1 U186 ( .A1(shift_out[0]), .A2(n83), .ZN(n105) );
NOR2_X1 U187 ( .A1(n11), .A2(IN1[31]), .ZN(n102) );
NAND2_X1 U188 ( .A1(IN1[31]), .A2(n11), .ZN(n100) );
MUX2_X1 U189 ( .A(B_booth_to_add[25]), .B(IN2[25]), .S(n9), .Z(mux_B[25]) );
MUX2_X1 U190 ( .A(B_booth_to_add[17]), .B(IN2[17]), .S(n9), .Z(mux_B[17]) );
MUX2_X1 U191 ( .A(B_booth_to_add[18]), .B(IN2[18]), .S(n9), .Z(mux_B[18]) );
MUX2_X1 U192 ( .A(B_booth_to_add[22]), .B(IN2[22]), .S(n9), .Z(mux_B[22]) );
MUX2_X1 U193 ( .A(B_booth_to_add[21]), .B(IN2[21]), .S(n9), .Z(mux_B[21]) );
MUX2_X1 U194 ( .A(B_booth_to_add[9]), .B(IN2[9]), .S(n9), .Z(mux_B[9]) );
MUX2_X1 U195 ( .A(B_booth_to_add[4]), .B(IN2[4]), .S(n9), .Z(mux_B[4]) );
MUX2_X1 U196 ( .A(B_booth_to_add[2]), .B(IN2[2]), .S(n9), .Z(mux_B[2]) );
MUX2_X1 U197 ( .A(A_booth_to_add[3]), .B(IN1[3]), .S(n9), .Z(mux_A[3]) );
MUX2_X1 U198 ( .A(A_booth_to_add[0]), .B(IN1[0]), .S(n9), .Z(mux_A[0]) );
MUX2_X1 U199 ( .A(A_booth_to_add[1]), .B(IN1[1]), .S(n9), .Z(mux_A[1]) );
NAND2_X1 U200 ( .A1(n98), .A2(n93), .ZN(mux_B[0]) );
NAND2_X1 U201 ( .A1(IN2[1]), .A2(n9), .ZN(n94) );
NAND2_X1 U202 ( .A1(n94), .A2(n91), .ZN(mux_B[1]) );
NAND2_X1 U203 ( .A1(IN2[11]), .A2(n9), .ZN(n96) );
NAND2_X1 U204 ( .A1(n96), .A2(n92), .ZN(mux_B[11]) );
NAND2_X1 U205 ( .A1(IN2[0]), .A2(n9), .ZN(n98) );
NAND2_X1 U206 ( .A1(sum_out[31]), .A2(n102), .ZN(n101) );
OAI21_X1 U207 ( .B1(sum_out[31]), .B2(n100), .A(n101), .ZN(overflow) );
AOI222_X1 U208 ( .A1(IN2[6]), .A2(n17), .B1(n118), .B2(lu_out[6]), .C1(n19),
.C2(mult_out[6]), .ZN(n24) );
AOI222_X1 U209 ( .A1(IN2[10]), .A2(n17), .B1(n118), .B2(lu_out[10]), .C1(n19), .C2(mult_out[10]), .ZN(n79) );
AOI222_X1 U210 ( .A1(IN2[12]), .A2(n17), .B1(n18), .B2(lu_out[12]), .C1(n19),
.C2(mult_out[12]), .ZN(n75) );
AOI22_X1 U211 ( .A1(n83), .A2(shift_out[13]), .B1(n119), .B2(sum_out[13]),
.ZN(n74) );
AOI222_X1 U212 ( .A1(n114), .A2(n17), .B1(n118), .B2(lu_out[5]), .C1(n19),
.C2(mult_out[5]), .ZN(n26) );
AOI22_X1 U213 ( .A1(n83), .A2(shift_out[22]), .B1(n16), .B2(n86), .ZN(n54)
);
AOI22_X1 U214 ( .A1(n83), .A2(shift_out[21]), .B1(n16), .B2(n38), .ZN(n56)
);
AOI22_X1 U215 ( .A1(n83), .A2(shift_out[28]), .B1(n16), .B2(sum_out[28]),
.ZN(n42) );
AOI22_X1 U216 ( .A1(n83), .A2(shift_out[20]), .B1(n88), .B2(n16), .ZN(n58)
);
AOI22_X1 U217 ( .A1(n83), .A2(shift_out[24]), .B1(n16), .B2(sum_out[24]),
.ZN(n50) );
AOI22_X1 U218 ( .A1(n83), .A2(shift_out[31]), .B1(n119), .B2(n37), .ZN(n33)
);
endmodule
module ff32_en_SIZE13 ( D, en, clk, rst, Q );
input [12:0] D;
output [12:0] Q;
input en, clk, rst;
wire net3376, n13;
DFFR_X1 \Q_reg[12] ( .D(D[12]), .CK(net3376), .RN(n13), .Q(Q[12]) );
DFFR_X1 \Q_reg[11] ( .D(D[11]), .CK(net3376), .RN(n13), .Q(Q[11]) );
DFFR_X1 \Q_reg[10] ( .D(D[10]), .CK(net3376), .RN(n13), .Q(Q[10]) );
DFFR_X1 \Q_reg[8] ( .D(D[8]), .CK(net3376), .RN(n13), .Q(Q[8]) );
DFFR_X1 \Q_reg[7] ( .D(D[7]), .CK(net3376), .RN(n13), .Q(Q[7]) );
DFFR_X1 \Q_reg[6] ( .D(D[6]), .CK(net3376), .RN(n13), .Q(Q[6]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(net3376), .RN(n13), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(net3376), .RN(n13), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(net3376), .RN(n13), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(net3376), .RN(n13), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(net3376), .RN(n13), .Q(Q[0]) );
SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE13 clk_gate_Q_reg ( .CLK(clk), .EN(en),
.ENCLK(net3376) );
DFFR_X2 \Q_reg[9] ( .D(D[9]), .CK(net3376), .RN(n13), .Q(Q[9]) );
DFFR_X2 \Q_reg[5] ( .D(D[5]), .CK(net3376), .RN(n13), .Q(Q[5]) );
INV_X1 U2 ( .A(rst), .ZN(n13) );
endmodule
module ff32_en_SIZE5_0 ( D, en, clk, rst, Q );
input [4:0] D;
output [4:0] Q;
input en, clk, rst;
wire net3361, n5;
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(net3361), .RN(n5), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(net3361), .RN(n5), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(net3361), .RN(n5), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(net3361), .RN(n5), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(net3361), .RN(n5), .Q(Q[0]) );
SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE5_0 clk_gate_Q_reg ( .CLK(clk), .EN(en),
.ENCLK(net3361) );
INV_X1 U2 ( .A(rst), .ZN(n5) );
endmodule
module ff32_en_SIZE32_0 ( D, en, clk, rst, Q );
input [31:0] D;
output [31:0] Q;
input en, clk, rst;
wire net3346, n32;
DFFR_X1 \Q_reg[31] ( .D(D[31]), .CK(net3346), .RN(n32), .Q(Q[31]) );
DFFR_X1 \Q_reg[30] ( .D(D[30]), .CK(net3346), .RN(n32), .Q(Q[30]) );
DFFR_X1 \Q_reg[29] ( .D(D[29]), .CK(net3346), .RN(n32), .Q(Q[29]) );
DFFR_X1 \Q_reg[28] ( .D(D[28]), .CK(net3346), .RN(n32), .Q(Q[28]) );
DFFR_X1 \Q_reg[27] ( .D(D[27]), .CK(net3346), .RN(n32), .Q(Q[27]) );
DFFR_X1 \Q_reg[26] ( .D(D[26]), .CK(net3346), .RN(n32), .Q(Q[26]) );
DFFR_X1 \Q_reg[25] ( .D(D[25]), .CK(net3346), .RN(n32), .Q(Q[25]) );
DFFR_X1 \Q_reg[24] ( .D(D[24]), .CK(net3346), .RN(n32), .Q(Q[24]) );
DFFR_X1 \Q_reg[23] ( .D(D[23]), .CK(net3346), .RN(n32), .Q(Q[23]) );
DFFR_X1 \Q_reg[22] ( .D(D[22]), .CK(net3346), .RN(n32), .Q(Q[22]) );
DFFR_X1 \Q_reg[21] ( .D(D[21]), .CK(net3346), .RN(n32), .Q(Q[21]) );
DFFR_X1 \Q_reg[20] ( .D(D[20]), .CK(net3346), .RN(n32), .Q(Q[20]) );
DFFR_X1 \Q_reg[19] ( .D(D[19]), .CK(net3346), .RN(n32), .Q(Q[19]) );
DFFR_X1 \Q_reg[18] ( .D(D[18]), .CK(net3346), .RN(n32), .Q(Q[18]) );
DFFR_X1 \Q_reg[17] ( .D(D[17]), .CK(net3346), .RN(n32), .Q(Q[17]) );
DFFR_X1 \Q_reg[16] ( .D(D[16]), .CK(net3346), .RN(n32), .Q(Q[16]) );
DFFR_X1 \Q_reg[15] ( .D(D[15]), .CK(net3346), .RN(n32), .Q(Q[15]) );
DFFR_X1 \Q_reg[14] ( .D(D[14]), .CK(net3346), .RN(n32), .Q(Q[14]) );
DFFR_X1 \Q_reg[13] ( .D(D[13]), .CK(net3346), .RN(n32), .Q(Q[13]) );
DFFR_X1 \Q_reg[12] ( .D(D[12]), .CK(net3346), .RN(n32), .Q(Q[12]) );
DFFR_X1 \Q_reg[11] ( .D(D[11]), .CK(net3346), .RN(n32), .Q(Q[11]) );
DFFR_X1 \Q_reg[10] ( .D(D[10]), .CK(net3346), .RN(n32), .Q(Q[10]) );
DFFR_X1 \Q_reg[9] ( .D(D[9]), .CK(net3346), .RN(n32), .Q(Q[9]) );
DFFR_X1 \Q_reg[8] ( .D(D[8]), .CK(net3346), .RN(n32), .Q(Q[8]) );
DFFR_X1 \Q_reg[7] ( .D(D[7]), .CK(net3346), .RN(n32), .Q(Q[7]) );
DFFR_X1 \Q_reg[6] ( .D(D[6]), .CK(net3346), .RN(n32), .Q(Q[6]) );
DFFR_X1 \Q_reg[5] ( .D(D[5]), .CK(net3346), .RN(n32), .Q(Q[5]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(net3346), .RN(n32), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(net3346), .RN(n32), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(net3346), .RN(n32), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(net3346), .RN(n32), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(net3346), .RN(n32), .Q(Q[0]) );
SNPS_CLOCK_GATE_HIGH_ff32_en_SIZE32_0 clk_gate_Q_reg ( .CLK(clk), .EN(en),
.ENCLK(net3346) );
INV_X2 U2 ( .A(rst), .ZN(n32) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_regfile_0 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3379, net3381, net3382, net3385;
assign net3379 = CLK;
assign ENCLK = net3381;
assign net3382 = EN;
DLL_X1 latch ( .D(net3382), .GN(net3379), .Q(net3385) );
AND2_X1 main_gate ( .A1(net3385), .A2(net3379), .ZN(net3381) );
endmodule
module SNPS_CLOCK_GATE_HIGH_dlx_cu_MICROCODE_MEM_SIZE64_FUNC_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE13_0 (
CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3559, net3561, net3562, net3565;
assign net3559 = CLK;
assign ENCLK = net3561;
assign net3562 = EN;
DLL_X1 latch ( .D(net3562), .GN(net3559), .Q(net3565) );
AND2_X1 main_gate ( .A1(net3565), .A2(net3559), .ZN(net3561) );
endmodule
module alu_ctrl ( .OP({\OP[4] , \OP[3] , \OP[2] , \OP[1] , \OP[0] }), ALU_WORD
);
output [12:0] ALU_WORD;
input \OP[4] , \OP[3] , \OP[2] , \OP[1] , \OP[0] ;
wire N20, N21, N22, N23, N24, N25, N26, N27, N28, N29, N30, N31, N32, N33,
n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35;
DLH_X1 \comp_sel_reg[2] ( .G(N32), .D(N33), .Q(ALU_WORD[4]) );
DLH_X1 \comp_sel_reg[1] ( .G(N32), .D(N31), .Q(ALU_WORD[3]) );
DLH_X1 \comp_sel_reg[0] ( .G(N32), .D(N30), .Q(ALU_WORD[2]) );
DLH_X1 sign_to_booth_reg ( .G(N20), .D(N21), .Q(ALU_WORD[0]) );
DLH_X1 left_right_reg ( .G(N23), .D(N22), .Q(ALU_WORD[9]) );
DLH_X1 logic_arith_reg ( .G(N23), .D(N24), .Q(ALU_WORD[8]) );
DLH_X1 sign_to_adder_reg ( .G(N25), .D(N26), .Q(ALU_WORD[7]) );
DLH_X1 \lu_ctrl_reg[1] ( .G(N28), .D(N29), .Q(ALU_WORD[6]) );
DLH_X1 \lu_ctrl_reg[0] ( .G(N28), .D(N27), .Q(ALU_WORD[5]) );
NAND3_X1 U53 ( .A1(n9), .A2(OP[1]), .A3(n28), .ZN(n30) );
NAND3_X1 U54 ( .A1(n15), .A2(n35), .A3(n22), .ZN(n19) );
NOR3_X1 U48 ( .A1(OP[2]), .A2(OP[0]), .A3(n22), .ZN(n10) );
NAND2_X1 U47 ( .A1(OP[3]), .A2(n23), .ZN(n3) );
NOR3_X1 U45 ( .A1(OP[2]), .A2(n35), .A3(n22), .ZN(n33) );
NOR2_X1 U43 ( .A1(n3), .A2(n2), .ZN(n32) );
NOR2_X1 U41 ( .A1(OP[0]), .A2(n15), .ZN(n28) );
NAND2_X1 U40 ( .A1(n28), .A2(n22), .ZN(n1) );
NOR2_X1 U39 ( .A1(n19), .A2(OP[3]), .ZN(n34) );
NOR4_X1 U38 ( .A1(n15), .A2(n3), .A3(n35), .A4(n22), .ZN(n8) );
AOI21_X1 U37 ( .B1(n34), .B2(OP[4]), .A(n8), .ZN(n18) );
NAND2_X1 U36 ( .A1(n33), .A2(n26), .ZN(n6) );
OAI211_X1 U35 ( .C1(n1), .C2(n16), .A(n18), .B(n6), .ZN(N30) );
AOI211_X1 U34 ( .C1(n26), .C2(n10), .A(n32), .B(N30), .ZN(n29) );
NAND2_X1 U33 ( .A1(OP[0]), .A2(n22), .ZN(n27) );
NOR2_X1 U32 ( .A1(n3), .A2(n27), .ZN(n31) );
NAND2_X1 U31 ( .A1(OP[2]), .A2(n31), .ZN(n4) );
NOR2_X1 U29 ( .A1(OP[2]), .A2(n27), .ZN(n24) );
NAND2_X1 U28 ( .A1(n26), .A2(n24), .ZN(n7) );
NAND4_X1 U27 ( .A1(n29), .A2(n4), .A3(n30), .A4(n7), .ZN(N32) );
AOI211_X1 U26 ( .C1(OP[0]), .C2(OP[1]), .A(OP[2]), .B(n3), .ZN(N28) );
NAND2_X1 U25 ( .A1(OP[1]), .A2(n28), .ZN(n17) );
OAI21_X1 U24 ( .B1(n27), .B2(n15), .A(n17), .ZN(n25) );
NAND2_X1 U23 ( .A1(n25), .A2(n26), .ZN(n20) );
NOR3_X1 U18 ( .A1(OP[2]), .A2(n22), .A3(n13), .ZN(N22) );
OAI21_X1 U16 ( .B1(n11), .B2(n13), .A(n21), .ZN(N23) );
OAI21_X1 U14 ( .B1(n19), .B2(n13), .A(n20), .ZN(ALU_WORD[12]) );
NOR2_X1 U6 ( .A1(n3), .A2(n11), .ZN(N27) );
NAND2_X1 U8 ( .A1(OP[2]), .A2(OP[1]), .ZN(n12) );
OAI21_X1 U7 ( .B1(n12), .B2(n13), .A(n14), .ZN(N26) );
NOR2_X1 U11 ( .A1(n2), .A2(n13), .ZN(N24) );
OAI211_X1 U12 ( .C1(n16), .C2(n17), .A(n18), .B(n4), .ZN(N21) );
NAND4_X1 U3 ( .A1(n4), .A2(n5), .A3(n6), .A4(n7), .ZN(N31) );
AOI21_X1 U2 ( .B1(n1), .B2(n2), .A(n3), .ZN(N33) );
OAI21_X1 U9 ( .B1(n15), .B2(n13), .A(n14), .ZN(N25) );
NAND2_X1 U19 ( .A1(n23), .A2(n16), .ZN(n13) );
NOR2_X1 U50 ( .A1(n23), .A2(n16), .ZN(n26) );
INV_X1 U52 ( .A(OP[4]), .ZN(n23) );
INV_X1 U51 ( .A(OP[3]), .ZN(n16) );
INV_X1 U49 ( .A(OP[1]), .ZN(n22) );
INV_X1 U46 ( .A(OP[0]), .ZN(n35) );
INV_X1 U44 ( .A(n33), .ZN(n2) );
INV_X1 U42 ( .A(OP[2]), .ZN(n15) );
INV_X1 U30 ( .A(n3), .ZN(n9) );
INV_X1 U22 ( .A(n20), .ZN(ALU_WORD[1]) );
OR3_X1 U21 ( .A1(N32), .A2(N28), .A3(ALU_WORD[1]), .ZN(ALU_WORD[10]) );
INV_X1 U20 ( .A(n24), .ZN(n11) );
INV_X1 U17 ( .A(N22), .ZN(n21) );
OR2_X1 U15 ( .A1(N32), .A2(N23), .ZN(ALU_WORD[11]) );
AND2_X1 U5 ( .A1(n9), .A2(n10), .ZN(N29) );
INV_X1 U10 ( .A(N32), .ZN(n14) );
INV_X1 U4 ( .A(n8), .ZN(n5) );
OR2_X1 U13 ( .A1(N32), .A2(ALU_WORD[12]), .ZN(N20) );
endmodule
module cw_mem_MICROCODE_MEM_SIZE64_OP_CODE_SIZE6_CW_SIZE13 ( OPCODE_IN, CW_OUT
);
input [5:0] OPCODE_IN;
output [12:0] CW_OUT;
wire \CW_OUT[5] , CW_OUT_4, CW_OUT_3, CW_OUT_2, CW_OUT_1, CW_OUT_0, n7, n8,
n9, n10, n11, n12, n13, n14, n17, n18, n19, n20, n21, n22, n23, n24,
n25, n26, n27, n28, n29, n16, n15, n1, n2, n3, n4, n5, n6;
assign CW_OUT[6] = \CW_OUT[5] ;
assign CW_OUT[5] = \CW_OUT[5] ;
assign CW_OUT[4] = CW_OUT_4;
assign CW_OUT[3] = CW_OUT_3;
assign CW_OUT[2] = CW_OUT_2;
assign CW_OUT[1] = CW_OUT_1;
assign CW_OUT[0] = CW_OUT_0;
NAND3_X1 U35 ( .A1(OPCODE_IN[3]), .A2(n23), .A3(n24), .ZN(n22) );
NAND3_X1 U36 ( .A1(OPCODE_IN[4]), .A2(n14), .A3(n25), .ZN(n29) );
NAND3_X1 U34 ( .A1(OPCODE_IN[3]), .A2(n13), .A3(n14), .ZN(n15) );
NOR2_X1 U8 ( .A1(n10), .A2(n17), .ZN(CW_OUT[8]) );
OAI21_X1 U23 ( .B1(OPCODE_IN[3]), .B2(n17), .A(n29), .ZN(CW_OUT[11]) );
OAI22_X1 U4 ( .A1(OPCODE_IN[3]), .A2(n11), .B1(n12), .B2(n10), .ZN(CW_OUT_4)
);
NOR2_X1 U19 ( .A1(n7), .A2(n8), .ZN(CW_OUT_3) );
NAND2_X1 U16 ( .A1(OPCODE_IN[3]), .A2(OPCODE_IN[4]), .ZN(n20) );
NAND2_X1 U15 ( .A1(n23), .A2(n7), .ZN(n27) );
NOR3_X1 U1 ( .A1(n2), .A2(n7), .A3(n8), .ZN(CW_OUT_2) );
NOR2_X1 U3 ( .A1(n8), .A2(n10), .ZN(CW_OUT_1) );
INV_X1 U21 ( .A(OPCODE_IN[0]), .ZN(n7) );
NAND2_X1 U18 ( .A1(OPCODE_IN[0]), .A2(n2), .ZN(n10) );
INV_X1 U30 ( .A(OPCODE_IN[5]), .ZN(n23) );
OR2_X1 U10 ( .A1(CW_OUT[7]), .A2(n18), .ZN(n9) );
OR2_X1 U9 ( .A1(CW_OUT_3), .A2(n9), .ZN(\CW_OUT[5] ) );
OR3_X1 U2 ( .A1(n9), .A2(CW_OUT_4), .A3(CW_OUT_1), .ZN(CW_OUT_0) );
NOR3_X1 U5 ( .A1(OPCODE_IN[5]), .A2(n19), .A3(n10), .ZN(CW_OUT[7]) );
INV_X1 U6 ( .A(OPCODE_IN[3]), .ZN(n2) );
INV_X1 U7 ( .A(OPCODE_IN[2]), .ZN(n14) );
CLKBUF_X1 U11 ( .A(n28), .Z(n5) );
INV_X1 U12 ( .A(n16), .ZN(CW_OUT[12]) );
AND3_X1 U13 ( .A1(n23), .A2(n2), .A3(n6), .ZN(n25) );
CLKBUF_X1 U14 ( .A(OPCODE_IN[1]), .Z(n6) );
OR2_X1 U17 ( .A1(OPCODE_IN[0]), .A2(n15), .ZN(n4) );
NAND2_X1 U20 ( .A1(n28), .A2(n23), .ZN(n12) );
NOR2_X1 U22 ( .A1(n19), .A2(OPCODE_IN[4]), .ZN(n28) );
NAND2_X1 U24 ( .A1(n14), .A2(OPCODE_IN[1]), .ZN(n19) );
OR2_X1 U25 ( .A1(OPCODE_IN[0]), .A2(n12), .ZN(n3) );
NOR3_X1 U26 ( .A1(OPCODE_IN[5]), .A2(OPCODE_IN[1]), .A3(OPCODE_IN[4]), .ZN(
n13) );
NAND2_X1 U27 ( .A1(n12), .A2(n17), .ZN(n1) );
NAND2_X1 U28 ( .A1(n1), .A2(n2), .ZN(n16) );
NAND3_X1 U29 ( .A1(n16), .A2(n3), .A3(n4), .ZN(CW_OUT[9]) );
NOR2_X1 U31 ( .A1(n12), .A2(OPCODE_IN[3]), .ZN(CW_OUT[10]) );
NAND2_X1 U32 ( .A1(n13), .A2(n14), .ZN(n11) );
OAI211_X1 U33 ( .C1(n25), .C2(n26), .A(OPCODE_IN[2]), .B(OPCODE_IN[4]), .ZN(
n21) );
NAND2_X1 U37 ( .A1(OPCODE_IN[2]), .A2(n13), .ZN(n17) );
NAND2_X1 U38 ( .A1(OPCODE_IN[5]), .A2(n5), .ZN(n8) );
OAI211_X1 U39 ( .C1(n19), .C2(n20), .A(n21), .B(n22), .ZN(n18) );
AOI21_X1 U40 ( .B1(n2), .B2(n27), .A(n6), .ZN(n26) );
OAI211_X1 U41 ( .C1(OPCODE_IN[4]), .C2(OPCODE_IN[0]), .A(n6), .B(
OPCODE_IN[2]), .ZN(n24) );
endmodule
module stall_logic_FUNC_SIZE11_OP_CODE_SIZE6 ( OPCODE_i, FUNC_i, rA_i, rB_i,
D1_i, D2_i, S_mem_LOAD_i, S_exe_LOAD_i, S_exe_WRITE_i, S_MUX_PC_BUS_i,
mispredict_i, bubble_dec_o, bubble_exe_o, stall_exe_o, stall_dec_o,
stall_btb_o, stall_fetch_o );
input [5:0] OPCODE_i;
input [10:0] FUNC_i;
input [4:0] rA_i;
input [4:0] rB_i;
input [4:0] D1_i;
input [4:0] D2_i;
input [1:0] S_MUX_PC_BUS_i;
input S_mem_LOAD_i, S_exe_LOAD_i, S_exe_WRITE_i, mispredict_i;
output bubble_dec_o, bubble_exe_o, stall_exe_o, stall_dec_o, stall_btb_o,
stall_fetch_o;
wire stall_fetch_o, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26,
n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40,
n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54,
n55, n56, n57, n58;
assign stall_dec_o = stall_fetch_o;
assign stall_btb_o = stall_fetch_o;
OAI33_X1 U46 ( .A1(OPCODE_i[2]), .A2(n52), .A3(n53), .B1(n50), .B2(
OPCODE_i[4]), .B3(OPCODE_i[1]), .ZN(n51) );
NAND4_X1 U36 ( .A1(S_mem_LOAD_i), .A2(n54), .A3(n55), .A4(n56), .ZN(n17) );
NOR2_X1 U35 ( .A1(OPCODE_i[5]), .A2(OPCODE_i[3]), .ZN(n27) );
NAND2_X1 U31 ( .A1(n27), .A2(n51), .ZN(n18) );
OAI21_X1 U30 ( .B1(OPCODE_i[0]), .B2(n50), .A(OPCODE_i[4]), .ZN(n48) );
AOI21_X1 U26 ( .B1(n27), .B2(n46), .A(n47), .ZN(n34) );
XNOR2_X1 U23 ( .A(n31), .B(rA_i[4]), .ZN(n37) );
AOI22_X1 U22 ( .A1(n43), .A2(D1_i[3]), .B1(D1_i[2]), .B2(n44), .ZN(n45) );
OAI221_X1 U21 ( .B1(n43), .B2(D1_i[3]), .C1(n44), .C2(D1_i[2]), .A(n45),
.ZN(n38) );
AOI22_X1 U20 ( .A1(n40), .A2(D1_i[1]), .B1(D1_i[0]), .B2(n41), .ZN(n42) );
OAI221_X1 U19 ( .B1(n40), .B2(D1_i[1]), .C1(n41), .C2(D1_i[0]), .A(n42),
.ZN(n39) );
NOR3_X1 U18 ( .A1(n37), .A2(n38), .A3(n39), .ZN(n36) );
OAI221_X1 U17 ( .B1(n34), .B2(n35), .C1(n34), .C2(S_exe_WRITE_i), .A(n36),
.ZN(n19) );
OAI22_X1 U15 ( .A1(n31), .A2(rB_i[4]), .B1(n32), .B2(rB_i[2]), .ZN(n33) );
AOI221_X1 U14 ( .B1(n31), .B2(rB_i[4]), .C1(rB_i[2]), .C2(n32), .A(n33),
.ZN(n21) );
OAI22_X1 U11 ( .A1(n28), .A2(rB_i[0]), .B1(n29), .B2(rB_i[3]), .ZN(n30) );
AOI221_X1 U10 ( .B1(n28), .B2(rB_i[0]), .C1(rB_i[3]), .C2(n29), .A(n30),
.ZN(n22) );
OAI211_X1 U7 ( .C1(n25), .C2(rB_i[1]), .A(S_exe_LOAD_i), .B(n27), .ZN(n26)
);
AOI21_X1 U6 ( .B1(n25), .B2(rB_i[1]), .A(n26), .ZN(n24) );
NAND4_X1 U5 ( .A1(n21), .A2(n22), .A3(n23), .A4(n24), .ZN(n20) );
NOR2_X1 U2 ( .A1(stall_fetch_o), .A2(n16), .ZN(bubble_dec_o) );
INV_X1 U45 ( .A(rA_i[3]), .ZN(n43) );
INV_X1 U44 ( .A(rA_i[1]), .ZN(n40) );
INV_X1 U41 ( .A(rA_i[0]), .ZN(n41) );
INV_X1 U40 ( .A(rA_i[2]), .ZN(n44) );
INV_X1 U34 ( .A(OPCODE_i[4]), .ZN(n52) );
INV_X1 U27 ( .A(S_exe_LOAD_i), .ZN(n47) );
INV_X1 U25 ( .A(n18), .ZN(n35) );
INV_X1 U24 ( .A(D1_i[4]), .ZN(n31) );
INV_X1 U16 ( .A(D1_i[2]), .ZN(n32) );
INV_X1 U13 ( .A(D1_i[0]), .ZN(n28) );
INV_X1 U12 ( .A(D1_i[3]), .ZN(n29) );
INV_X1 U8 ( .A(D1_i[1]), .ZN(n25) );
OAI211_X1 U4 ( .C1(n17), .C2(n18), .A(n19), .B(n20), .ZN(stall_fetch_o) );
AOI221_X1 U3 ( .B1(n41), .B2(D2_i[0]), .C1(D2_i[2]), .C2(n44), .A(n57), .ZN(
n55) );
INV_X1 U9 ( .A(mispredict_i), .ZN(n16) );
INV_X1 U28 ( .A(OPCODE_i[2]), .ZN(n50) );
AOI221_X1 U29 ( .B1(n43), .B2(D2_i[3]), .C1(D2_i[1]), .C2(n40), .A(n58),
.ZN(n54) );
XNOR2_X1 U32 ( .A(rA_i[4]), .B(D2_i[4]), .ZN(n56) );
OAI22_X1 U33 ( .A1(n41), .A2(D2_i[0]), .B1(n44), .B2(D2_i[2]), .ZN(n57) );
OAI22_X1 U37 ( .A1(n43), .A2(D2_i[3]), .B1(n40), .B2(D2_i[1]), .ZN(n58) );
NOR4_X1 U38 ( .A1(OPCODE_i[2]), .A2(OPCODE_i[4]), .A3(OPCODE_i[1]), .A4(
OPCODE_i[0]), .ZN(n23) );
OAI22_X1 U39 ( .A1(OPCODE_i[1]), .A2(n48), .B1(OPCODE_i[4]), .B2(n49), .ZN(
n46) );
NAND2_X1 U42 ( .A1(OPCODE_i[1]), .A2(n50), .ZN(n49) );
INV_X1 U43 ( .A(OPCODE_i[1]), .ZN(n53) );
endmodule
module mux41_MUX_SIZE32_0 ( IN0, IN1, IN2, IN3, CTRL, OUT1 );
input [31:0] IN0;
input [31:0] IN1;
input [31:0] IN2;
input [31:0] IN3;
input [1:0] CTRL;
output [31:0] OUT1;
wire n3, n4, n6, n7, n8, n15, n16, n23, n24, n31, n32, n33, n34, n39, n40,
n41, n42, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n63, n64, n65, n66, n67, n68, n71, n1, n2, n5, n9, n10, n11, n12, n13,
n14, n17, n18, n19, n20, n21, n22, n25, n26, n27, n28, n29, n30, n35,
n36, n37, n38, n43, n44, n45, n46, n59, n60, n61, n62, n69, n70, n72,
n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86,
n87, n88, n89, n90, n91, n92, n93, n94;
NAND2_X1 U61 ( .A1(n47), .A2(n48), .ZN(OUT1[1]) );
NAND2_X1 U64 ( .A1(n49), .A2(n50), .ZN(OUT1[19]) );
AOI22_X1 U51 ( .A1(n89), .A2(IN1[23]), .B1(n88), .B2(IN0[23]), .ZN(n39) );
NAND2_X1 U49 ( .A1(n39), .A2(n40), .ZN(OUT1[23]) );
AOI22_X1 U54 ( .A1(n91), .A2(IN1[22]), .B1(n86), .B2(IN0[22]), .ZN(n41) );
NAND2_X1 U85 ( .A1(n63), .A2(n64), .ZN(OUT1[12]) );
NAND2_X1 U88 ( .A1(n65), .A2(n66), .ZN(OUT1[11]) );
NAND2_X1 U73 ( .A1(n55), .A2(n56), .ZN(OUT1[16]) );
NAND2_X1 U76 ( .A1(n57), .A2(n58), .ZN(OUT1[15]) );
AOI22_X1 U39 ( .A1(n91), .A2(IN1[27]), .B1(n88), .B2(IN0[27]), .ZN(n31) );
AOI22_X1 U42 ( .A1(n91), .A2(IN1[26]), .B1(n86), .B2(IN0[26]), .ZN(n33) );
AOI22_X1 U3 ( .A1(n89), .A2(IN1[9]), .B1(n87), .B2(IN0[9]), .ZN(n3) );
NAND2_X1 U1 ( .A1(n3), .A2(n4), .ZN(OUT1[9]) );
AOI22_X1 U15 ( .A1(n90), .A2(IN1[5]), .B1(n88), .B2(IN0[5]), .ZN(n15) );
NAND2_X1 U13 ( .A1(n15), .A2(n16), .ZN(OUT1[5]) );
AOI22_X1 U27 ( .A1(n91), .A2(IN1[30]), .B1(n87), .B2(IN0[30]), .ZN(n23) );
BUF_X2 U2 ( .A(n8), .Z(n87) );
BUF_X1 U4 ( .A(n6), .Z(n94) );
AND2_X1 U5 ( .A1(n71), .A2(CTRL[0]), .ZN(n7) );
BUF_X1 U6 ( .A(CTRL[1]), .Z(n85) );
BUF_X2 U7 ( .A(n7), .Z(n91) );
BUF_X2 U8 ( .A(n6), .Z(n92) );
BUF_X2 U9 ( .A(n6), .Z(n93) );
BUF_X2 U10 ( .A(n7), .Z(n90) );
BUF_X2 U11 ( .A(n7), .Z(n89) );
BUF_X2 U12 ( .A(n8), .Z(n86) );
BUF_X2 U14 ( .A(n8), .Z(n88) );
NOR2_X1 U16 ( .A1(n71), .A2(CTRL[0]), .ZN(n6) );
NOR2_X1 U17 ( .A1(CTRL[0]), .A2(n85), .ZN(n8) );
INV_X1 U18 ( .A(CTRL[1]), .ZN(n71) );
NAND2_X1 U19 ( .A1(n94), .A2(IN2[30]), .ZN(n24) );
NAND2_X1 U20 ( .A1(n93), .A2(IN2[5]), .ZN(n16) );
NAND2_X1 U21 ( .A1(n93), .A2(IN2[9]), .ZN(n4) );
NAND2_X1 U22 ( .A1(n94), .A2(IN2[26]), .ZN(n34) );
NAND2_X1 U23 ( .A1(n94), .A2(IN2[27]), .ZN(n32) );
NAND2_X1 U24 ( .A1(n93), .A2(IN2[15]), .ZN(n58) );
NAND2_X1 U25 ( .A1(n93), .A2(IN2[16]), .ZN(n56) );
NAND2_X1 U26 ( .A1(n92), .A2(IN2[11]), .ZN(n66) );
NAND2_X1 U28 ( .A1(n92), .A2(IN2[12]), .ZN(n64) );
NAND2_X1 U29 ( .A1(n92), .A2(IN2[22]), .ZN(n42) );
NAND2_X1 U30 ( .A1(n92), .A2(IN2[23]), .ZN(n40) );
NAND2_X1 U31 ( .A1(n92), .A2(IN2[19]), .ZN(n50) );
NAND2_X1 U32 ( .A1(n92), .A2(IN2[1]), .ZN(n48) );
NAND3_X1 U33 ( .A1(n2), .A2(n1), .A3(n5), .ZN(OUT1[0]) );
NAND2_X1 U34 ( .A1(n90), .A2(IN1[0]), .ZN(n2) );
NAND2_X1 U35 ( .A1(n88), .A2(IN0[0]), .ZN(n5) );
NAND2_X1 U36 ( .A1(n93), .A2(IN2[0]), .ZN(n1) );
NAND3_X1 U37 ( .A1(n11), .A2(n9), .A3(n10), .ZN(OUT1[2]) );
NAND2_X1 U38 ( .A1(n88), .A2(IN0[2]), .ZN(n9) );
NAND2_X1 U40 ( .A1(n91), .A2(IN1[2]), .ZN(n11) );
NAND2_X1 U41 ( .A1(n94), .A2(IN2[2]), .ZN(n10) );
NAND3_X1 U43 ( .A1(n13), .A2(n12), .A3(n14), .ZN(OUT1[8]) );
NAND2_X1 U44 ( .A1(n90), .A2(IN1[8]), .ZN(n13) );
NAND2_X1 U45 ( .A1(n88), .A2(IN0[8]), .ZN(n14) );
NAND2_X1 U46 ( .A1(n93), .A2(IN2[8]), .ZN(n12) );
NAND3_X1 U47 ( .A1(n18), .A2(n17), .A3(n19), .ZN(OUT1[14]) );
NAND2_X1 U48 ( .A1(n91), .A2(IN1[14]), .ZN(n18) );
NAND2_X1 U50 ( .A1(n88), .A2(IN0[14]), .ZN(n19) );
NAND2_X1 U52 ( .A1(n93), .A2(IN2[14]), .ZN(n17) );
NAND3_X1 U53 ( .A1(n21), .A2(n20), .A3(n22), .ZN(OUT1[13]) );
NAND2_X1 U55 ( .A1(n89), .A2(IN1[13]), .ZN(n21) );
NAND2_X1 U56 ( .A1(n87), .A2(IN0[13]), .ZN(n22) );
NAND2_X1 U57 ( .A1(n93), .A2(IN2[13]), .ZN(n20) );
NAND3_X1 U58 ( .A1(n26), .A2(n25), .A3(n27), .ZN(OUT1[25]) );
NAND2_X1 U59 ( .A1(n94), .A2(IN2[25]), .ZN(n26) );
NAND2_X1 U60 ( .A1(n87), .A2(IN0[25]), .ZN(n25) );
NAND2_X1 U62 ( .A1(n90), .A2(IN1[25]), .ZN(n27) );
NAND3_X1 U63 ( .A1(n29), .A2(n28), .A3(n30), .ZN(OUT1[4]) );
NAND2_X1 U65 ( .A1(n93), .A2(IN2[4]), .ZN(n29) );
NAND2_X1 U66 ( .A1(n89), .A2(IN1[4]), .ZN(n30) );
NAND2_X1 U67 ( .A1(n87), .A2(IN0[4]), .ZN(n28) );
NAND3_X1 U68 ( .A1(n36), .A2(n35), .A3(n37), .ZN(OUT1[29]) );
NAND2_X1 U69 ( .A1(n94), .A2(IN2[29]), .ZN(n36) );
NAND2_X1 U70 ( .A1(n87), .A2(IN0[29]), .ZN(n35) );
NAND2_X1 U71 ( .A1(n90), .A2(IN1[29]), .ZN(n37) );
NAND3_X1 U72 ( .A1(n43), .A2(n38), .A3(n44), .ZN(OUT1[24]) );
NAND2_X1 U74 ( .A1(n94), .A2(IN2[24]), .ZN(n43) );
NAND2_X1 U75 ( .A1(n87), .A2(IN0[24]), .ZN(n38) );
NAND2_X1 U77 ( .A1(n89), .A2(IN1[24]), .ZN(n44) );
NAND3_X1 U78 ( .A1(n46), .A2(n45), .A3(n59), .ZN(OUT1[3]) );
NAND2_X1 U79 ( .A1(n93), .A2(IN2[3]), .ZN(n46) );
NAND2_X1 U80 ( .A1(n90), .A2(IN1[3]), .ZN(n59) );
NAND2_X1 U81 ( .A1(n88), .A2(IN0[3]), .ZN(n45) );
NAND3_X1 U82 ( .A1(n61), .A2(n60), .A3(n62), .ZN(OUT1[20]) );
NAND2_X1 U83 ( .A1(n92), .A2(IN2[20]), .ZN(n61) );
NAND2_X1 U84 ( .A1(n87), .A2(IN0[20]), .ZN(n60) );
NAND2_X1 U86 ( .A1(n89), .A2(IN1[20]), .ZN(n62) );
NAND3_X1 U87 ( .A1(n70), .A2(n69), .A3(n72), .ZN(OUT1[28]) );
NAND2_X1 U89 ( .A1(n94), .A2(IN2[28]), .ZN(n70) );
NAND2_X1 U90 ( .A1(n88), .A2(IN0[28]), .ZN(n69) );
NAND2_X1 U91 ( .A1(n90), .A2(IN1[28]), .ZN(n72) );
NAND3_X1 U92 ( .A1(n74), .A2(n73), .A3(n75), .ZN(OUT1[6]) );
NAND2_X1 U93 ( .A1(n93), .A2(IN2[6]), .ZN(n74) );
NAND2_X1 U94 ( .A1(n91), .A2(IN1[6]), .ZN(n75) );
NAND2_X1 U95 ( .A1(n88), .A2(IN0[6]), .ZN(n73) );
NAND3_X1 U96 ( .A1(n77), .A2(n76), .A3(n78), .ZN(OUT1[21]) );
NAND2_X1 U97 ( .A1(n92), .A2(IN2[21]), .ZN(n77) );
NAND2_X1 U98 ( .A1(n88), .A2(IN0[21]), .ZN(n76) );
NAND2_X1 U99 ( .A1(n89), .A2(IN1[21]), .ZN(n78) );
NAND3_X1 U100 ( .A1(n80), .A2(n79), .A3(n81), .ZN(OUT1[31]) );
NAND2_X1 U101 ( .A1(n92), .A2(IN2[31]), .ZN(n80) );
NAND2_X1 U102 ( .A1(n89), .A2(IN1[31]), .ZN(n81) );
NAND2_X1 U103 ( .A1(n88), .A2(IN0[31]), .ZN(n79) );
NAND3_X1 U104 ( .A1(n83), .A2(n82), .A3(n84), .ZN(OUT1[7]) );
NAND2_X1 U105 ( .A1(n93), .A2(IN2[7]), .ZN(n83) );
NAND2_X1 U106 ( .A1(n91), .A2(IN1[7]), .ZN(n84) );
NAND2_X1 U107 ( .A1(n87), .A2(IN0[7]), .ZN(n82) );
AOI22_X1 U108 ( .A1(n90), .A2(IN1[1]), .B1(n87), .B2(IN0[1]), .ZN(n47) );
AOI22_X1 U109 ( .A1(n89), .A2(IN1[16]), .B1(n87), .B2(IN0[16]), .ZN(n55) );
AOI22_X1 U110 ( .A1(n90), .A2(IN1[12]), .B1(n87), .B2(IN0[12]), .ZN(n63) );
AOI22_X1 U111 ( .A1(n90), .A2(IN1[19]), .B1(n86), .B2(IN0[19]), .ZN(n49) );
AOI22_X1 U112 ( .A1(n91), .A2(IN1[15]), .B1(n86), .B2(IN0[15]), .ZN(n57) );
AOI22_X1 U113 ( .A1(n91), .A2(IN1[18]), .B1(n86), .B2(IN0[18]), .ZN(n51) );
AOI22_X1 U114 ( .A1(n89), .A2(IN1[11]), .B1(n86), .B2(IN0[11]), .ZN(n65) );
AOI22_X1 U115 ( .A1(n90), .A2(IN1[17]), .B1(n86), .B2(IN0[17]), .ZN(n53) );
AOI22_X1 U116 ( .A1(n89), .A2(IN1[10]), .B1(n86), .B2(IN0[10]), .ZN(n67) );
NAND2_X1 U117 ( .A1(n53), .A2(n54), .ZN(OUT1[17]) );
NAND2_X1 U118 ( .A1(n51), .A2(n52), .ZN(OUT1[18]) );
NAND2_X1 U119 ( .A1(n23), .A2(n24), .ZN(OUT1[30]) );
NAND2_X1 U120 ( .A1(n31), .A2(n32), .ZN(OUT1[27]) );
NAND2_X1 U121 ( .A1(n67), .A2(n68), .ZN(OUT1[10]) );
NAND2_X1 U122 ( .A1(n33), .A2(n34), .ZN(OUT1[26]) );
NAND2_X1 U123 ( .A1(n92), .A2(IN2[17]), .ZN(n54) );
NAND2_X1 U124 ( .A1(n92), .A2(IN2[10]), .ZN(n68) );
NAND2_X1 U125 ( .A1(n92), .A2(IN2[18]), .ZN(n52) );
NAND2_X1 U126 ( .A1(n41), .A2(n42), .ZN(OUT1[22]) );
endmodule
module zerocheck ( IN0, CTRL, OUT1 );
input [31:0] IN0;
input CTRL;
output OUT1;
wire n9, n8, n7, n6, n5, n4, n3, n2, n12, n11, n10;
XNOR2_X1 U1 ( .A(n2), .B(CTRL), .ZN(OUT1) );
NOR2_X1 U2 ( .A1(n3), .A2(n4), .ZN(n2) );
NOR4_X1 U3 ( .A1(IN0[30]), .A2(IN0[2]), .A3(IN0[29]), .A4(IN0[28]), .ZN(n8)
);
NOR4_X1 U4 ( .A1(IN0[5]), .A2(IN0[4]), .A3(IN0[3]), .A4(IN0[31]), .ZN(n5) );
NOR4_X1 U5 ( .A1(IN0[9]), .A2(IN0[8]), .A3(IN0[7]), .A4(IN0[6]), .ZN(n6) );
NOR4_X1 U6 ( .A1(IN0[27]), .A2(IN0[26]), .A3(IN0[25]), .A4(IN0[24]), .ZN(n7)
);
NOR4_X1 U7 ( .A1(IN0[16]), .A2(IN0[15]), .A3(IN0[14]), .A4(IN0[13]), .ZN(n12) );
NOR4_X1 U8 ( .A1(IN0[12]), .A2(IN0[11]), .A3(IN0[10]), .A4(IN0[0]), .ZN(n11)
);
NOR4_X1 U9 ( .A1(IN0[23]), .A2(IN0[22]), .A3(IN0[21]), .A4(IN0[20]), .ZN(n10) );
NOR4_X1 U10 ( .A1(IN0[1]), .A2(IN0[19]), .A3(IN0[18]), .A4(IN0[17]), .ZN(n9)
);
NAND4_X1 U11 ( .A1(n7), .A2(n6), .A3(n5), .A4(n8), .ZN(n4) );
NAND4_X1 U12 ( .A1(n9), .A2(n10), .A3(n11), .A4(n12), .ZN(n3) );
endmodule
module mux21_0 ( IN0, IN1, CTRL, OUT1 );
input [31:0] IN0;
input [31:0] IN1;
output [31:0] OUT1;
input CTRL;
wire n1, n2, n3;
MUX2_X1 U1 ( .A(IN0[9]), .B(IN1[9]), .S(n3), .Z(OUT1[9]) );
MUX2_X1 U2 ( .A(IN0[8]), .B(IN1[8]), .S(n3), .Z(OUT1[8]) );
MUX2_X1 U3 ( .A(IN0[7]), .B(IN1[7]), .S(n2), .Z(OUT1[7]) );
MUX2_X1 U4 ( .A(IN0[6]), .B(IN1[6]), .S(n1), .Z(OUT1[6]) );
MUX2_X1 U7 ( .A(IN0[3]), .B(IN1[3]), .S(n1), .Z(OUT1[3]) );
MUX2_X1 U18 ( .A(IN0[22]), .B(IN1[22]), .S(n2), .Z(OUT1[22]) );
MUX2_X1 U19 ( .A(IN0[21]), .B(IN1[21]), .S(n3), .Z(OUT1[21]) );
MUX2_X1 U20 ( .A(IN0[20]), .B(IN1[20]), .S(n1), .Z(OUT1[20]) );
MUX2_X1 U23 ( .A(IN0[18]), .B(IN1[18]), .S(n2), .Z(OUT1[18]) );
MUX2_X1 U24 ( .A(IN0[17]), .B(IN1[17]), .S(n2), .Z(OUT1[17]) );
MUX2_X1 U25 ( .A(IN0[16]), .B(IN1[16]), .S(n2), .Z(OUT1[16]) );
MUX2_X1 U26 ( .A(IN0[15]), .B(IN1[15]), .S(n1), .Z(OUT1[15]) );
MUX2_X1 U29 ( .A(IN0[12]), .B(IN1[12]), .S(n1), .Z(OUT1[12]) );
MUX2_X1 U32 ( .A(IN0[0]), .B(IN1[0]), .S(n1), .Z(OUT1[0]) );
MUX2_X1 U22 ( .A(IN0[19]), .B(IN1[19]), .S(n3), .Z(OUT1[19]) );
MUX2_X1 U6 ( .A(IN0[4]), .B(IN1[4]), .S(n1), .Z(OUT1[4]) );
MUX2_X1 U27 ( .A(IN0[14]), .B(IN1[14]), .S(n1), .Z(OUT1[14]) );
MUX2_X1 U31 ( .A(IN0[10]), .B(IN1[10]), .S(n3), .Z(OUT1[10]) );
MUX2_X1 U30 ( .A(IN0[11]), .B(IN1[11]), .S(n2), .Z(OUT1[11]) );
MUX2_X1 U13 ( .A(IN0[27]), .B(IN1[27]), .S(n2), .Z(OUT1[27]) );
MUX2_X1 U28 ( .A(IN0[13]), .B(IN1[13]), .S(n1), .Z(OUT1[13]) );
MUX2_X1 U21 ( .A(IN0[1]), .B(IN1[1]), .S(n3), .Z(OUT1[1]) );
MUX2_X1 U10 ( .A(IN0[2]), .B(IN1[2]), .S(n1), .Z(OUT1[2]) );
MUX2_X1 U5 ( .A(IN0[5]), .B(IN1[5]), .S(n2), .Z(OUT1[5]) );
MUX2_X1 U11 ( .A(IN0[29]), .B(IN1[29]), .S(n2), .Z(OUT1[29]) );
MUX2_X1 U17 ( .A(IN0[23]), .B(IN1[23]), .S(n2), .Z(OUT1[23]) );
MUX2_X1 U8 ( .A(IN0[31]), .B(IN1[31]), .S(n3), .Z(OUT1[31]) );
BUF_X2 U9 ( .A(CTRL), .Z(n2) );
MUX2_X1 U12 ( .A(IN0[25]), .B(IN1[25]), .S(n3), .Z(OUT1[25]) );
MUX2_X1 U14 ( .A(IN0[24]), .B(IN1[24]), .S(n3), .Z(OUT1[24]) );
MUX2_X1 U15 ( .A(IN0[26]), .B(IN1[26]), .S(n2), .Z(OUT1[26]) );
CLKBUF_X2 U16 ( .A(CTRL), .Z(n3) );
BUF_X2 U33 ( .A(CTRL), .Z(n1) );
MUX2_X1 U34 ( .A(IN0[28]), .B(IN1[28]), .S(n3), .Z(OUT1[28]) );
MUX2_X1 U35 ( .A(IN0[30]), .B(IN1[30]), .S(n3), .Z(OUT1[30]) );
endmodule
module p4add_N32_logN5_0 ( A, B, Cin, sign, S, Cout );
input [31:0] A;
input [31:0] B;
output [31:0] S;
input Cin, sign;
output Cout;
wire [31:0] new_B;
wire [7:0] carry_pro;
wire SYNOPSYS_UNCONNECTED__0;
xor_gen_N32_0 xor32 ( .A(B), .B(1'b0), .S(new_B) );
carry_tree_N32_logN5_0 ct ( .A({1'b0, 1'b0, 1'b0, 1'b0, A[27:0]}), .B({1'b0,
1'b0, 1'b0, 1'b0, new_B[27:0]}), .Cin(1'b0), .Cout({
SYNOPSYS_UNCONNECTED__0, carry_pro[7:1]}) );
sum_gen_N32_0 add ( .A(A), .B({new_B[31:28], new_B[31], new_B[26:0]}), .Cin(
{1'b0, carry_pro[7:1], 1'b0}), .S(S) );
endmodule
module extender_32 ( IN1, CTRL, SIGN, OUT1 );
input [31:0] IN1;
output [31:0] OUT1;
input CTRL, SIGN;
wire OUT1_31, n4, n5, n6, n8, n9, n10, n13, n11, n7, n12, n1, n2, n3, n14,
n15, n16, n17, n18, \OUT1[25] , \OUT1[28] ;
assign OUT1[15] = IN1[15];
assign OUT1[14] = IN1[14];
assign OUT1[13] = IN1[13];
assign OUT1[12] = IN1[12];
assign OUT1[11] = IN1[11];
assign OUT1[10] = IN1[10];
assign OUT1[9] = IN1[9];
assign OUT1[8] = IN1[8];
assign OUT1[7] = IN1[7];
assign OUT1[6] = IN1[6];
assign OUT1[5] = IN1[5];
assign OUT1[4] = IN1[4];
assign OUT1[3] = IN1[3];
assign OUT1[2] = IN1[2];
assign OUT1[1] = IN1[1];
assign OUT1[0] = IN1[0];
assign OUT1[29] = \OUT1[25] ;
assign OUT1[30] = \OUT1[25] ;
assign OUT1[25] = \OUT1[25] ;
assign OUT1[26] = \OUT1[28] ;
assign OUT1[27] = \OUT1[28] ;
assign OUT1[31] = \OUT1[28] ;
assign OUT1[28] = \OUT1[28] ;
CLKBUF_X1 U2 ( .A(CTRL), .Z(n15) );
NAND2_X2 U3 ( .A1(n14), .A2(n8), .ZN(OUT1[21]) );
NAND2_X2 U4 ( .A1(n18), .A2(n12), .ZN(OUT1[17]) );
BUF_X4 U5 ( .A(OUT1_31), .Z(\OUT1[28] ) );
BUF_X4 U6 ( .A(n16), .Z(\OUT1[25] ) );
NAND2_X1 U7 ( .A1(n18), .A2(n5), .ZN(OUT1[24]) );
NAND2_X1 U8 ( .A1(n17), .A2(n9), .ZN(OUT1[20]) );
NAND2_X1 U9 ( .A1(n7), .A2(n14), .ZN(OUT1[22]) );
NAND2_X1 U10 ( .A1(n10), .A2(n14), .ZN(OUT1[19]) );
NAND2_X1 U11 ( .A1(SIGN), .A2(n1), .ZN(n14) );
NAND2_X1 U12 ( .A1(n17), .A2(n11), .ZN(OUT1[18]) );
NAND2_X1 U13 ( .A1(n17), .A2(n13), .ZN(OUT1[16]) );
NAND2_X1 U14 ( .A1(n3), .A2(SIGN), .ZN(n17) );
NAND2_X1 U15 ( .A1(n3), .A2(SIGN), .ZN(n18) );
NOR2_X1 U16 ( .A1(CTRL), .A2(n2), .ZN(n3) );
INV_X1 U17 ( .A(IN1[15]), .ZN(n2) );
NAND2_X1 U18 ( .A1(CTRL), .A2(IN1[17]), .ZN(n12) );
NOR2_X1 U19 ( .A1(CTRL), .A2(n2), .ZN(n1) );
NAND2_X1 U20 ( .A1(CTRL), .A2(IN1[22]), .ZN(n7) );
NAND2_X1 U21 ( .A1(CTRL), .A2(IN1[18]), .ZN(n11) );
NAND2_X1 U22 ( .A1(n18), .A2(n4), .ZN(n16) );
NAND2_X1 U23 ( .A1(n15), .A2(IN1[24]), .ZN(n5) );
NAND2_X1 U24 ( .A1(n15), .A2(IN1[16]), .ZN(n13) );
NAND2_X1 U25 ( .A1(CTRL), .A2(IN1[20]), .ZN(n9) );
NAND2_X1 U26 ( .A1(CTRL), .A2(IN1[19]), .ZN(n10) );
NAND2_X1 U27 ( .A1(CTRL), .A2(IN1[23]), .ZN(n6) );
NAND2_X1 U28 ( .A1(CTRL), .A2(IN1[25]), .ZN(n4) );
NAND2_X1 U29 ( .A1(CTRL), .A2(IN1[21]), .ZN(n8) );
NAND2_X1 U30 ( .A1(n17), .A2(n6), .ZN(OUT1[23]) );
NAND2_X1 U31 ( .A1(n18), .A2(n4), .ZN(OUT1_31) );
endmodule
module ff32_en_IR ( D, en, clk, rst, Q );
input [31:0] D;
output [31:0] Q;
input en, clk, rst;
wire net3591, n32;
DFFR_X1 \Q_reg[31] ( .D(D[31]), .CK(net3591), .RN(n32), .Q(Q[31]) );
DFFS_X1 \Q_reg[26] ( .D(D[26]), .CK(net3591), .SN(n32), .Q(Q[26]) );
DFFR_X1 \Q_reg[25] ( .D(D[25]), .CK(net3591), .RN(n32), .Q(Q[25]) );
DFFR_X1 \Q_reg[24] ( .D(D[24]), .CK(net3591), .RN(n32), .Q(Q[24]) );
DFFR_X1 \Q_reg[23] ( .D(D[23]), .CK(net3591), .RN(n32), .Q(Q[23]) );
DFFR_X1 \Q_reg[22] ( .D(D[22]), .CK(net3591), .RN(n32), .Q(Q[22]) );
DFFR_X1 \Q_reg[21] ( .D(D[21]), .CK(net3591), .RN(n32), .Q(Q[21]) );
DFFR_X1 \Q_reg[20] ( .D(D[20]), .CK(net3591), .RN(n32), .Q(Q[20]) );
DFFR_X1 \Q_reg[19] ( .D(D[19]), .CK(net3591), .RN(n32), .Q(Q[19]) );
DFFR_X1 \Q_reg[18] ( .D(D[18]), .CK(net3591), .RN(n32), .Q(Q[18]) );
DFFR_X1 \Q_reg[17] ( .D(D[17]), .CK(net3591), .RN(n32), .Q(Q[17]) );
DFFR_X1 \Q_reg[16] ( .D(D[16]), .CK(net3591), .RN(n32), .Q(Q[16]) );
DFFR_X1 \Q_reg[15] ( .D(D[15]), .CK(net3591), .RN(n32), .Q(Q[15]) );
DFFR_X1 \Q_reg[14] ( .D(D[14]), .CK(net3591), .RN(n32), .Q(Q[14]) );
DFFR_X1 \Q_reg[13] ( .D(D[13]), .CK(net3591), .RN(n32), .Q(Q[13]) );
DFFR_X1 \Q_reg[12] ( .D(D[12]), .CK(net3591), .RN(n32), .Q(Q[12]) );
DFFR_X1 \Q_reg[11] ( .D(D[11]), .CK(net3591), .RN(n32), .Q(Q[11]) );
DFFR_X1 \Q_reg[10] ( .D(D[10]), .CK(net3591), .RN(n32), .Q(Q[10]) );
DFFR_X1 \Q_reg[9] ( .D(D[9]), .CK(net3591), .RN(n32), .Q(Q[9]) );
DFFR_X1 \Q_reg[8] ( .D(D[8]), .CK(net3591), .RN(n32), .Q(Q[8]) );
DFFR_X1 \Q_reg[7] ( .D(D[7]), .CK(net3591), .RN(n32), .Q(Q[7]) );
DFFR_X1 \Q_reg[6] ( .D(D[6]), .CK(net3591), .RN(n32), .Q(Q[6]) );
DFFR_X1 \Q_reg[5] ( .D(D[5]), .CK(net3591), .RN(n32), .Q(Q[5]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(net3591), .RN(n32), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(net3591), .RN(n32), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(net3591), .RN(n32), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(net3591), .RN(n32), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(net3591), .RN(n32), .Q(Q[0]) );
SNPS_CLOCK_GATE_HIGH_ff32_en_IR clk_gate_Q_reg ( .CLK(clk), .EN(en), .ENCLK(
net3591) );
DFFS_X2 \Q_reg[28] ( .D(D[28]), .CK(net3591), .SN(n32), .Q(Q[28]) );
DFFS_X2 \Q_reg[30] ( .D(D[30]), .CK(net3591), .SN(n32), .Q(Q[30]) );
DFFR_X1 \Q_reg[29] ( .D(D[29]), .CK(net3591), .RN(n32), .Q(Q[29]) );
DFFR_X2 \Q_reg[27] ( .D(D[27]), .CK(net3591), .RN(n32), .Q(Q[27]) );
INV_X2 U2 ( .A(rst), .ZN(n32) );
endmodule
module SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_0 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net3609, net3611, net3612, net3615;
assign net3609 = CLK;
assign ENCLK = net3611;
assign net3612 = EN;
DLL_X1 latch ( .D(net3612), .GN(net3609), .Q(net3615) );
AND2_X1 main_gate ( .A1(net3615), .A2(net3609), .ZN(net3611) );
endmodule
module predictor_2_0 ( clock, reset, enable, taken_i, prediction_o );
input clock, reset, enable, taken_i;
output prediction_o;
wire N11, N12, n3, n4, n6, n8, n9, n1, n2;
wire [1:0] next_STATE;
DLH_X1 \next_STATE_reg[0] ( .G(enable), .D(N11), .Q(next_STATE[0]) );
DFFR_X1 \STATE_reg[0] ( .D(n8), .CK(clock), .RN(n2), .Q(n1), .QN(n9) );
DLH_X1 \next_STATE_reg[1] ( .G(enable), .D(N12), .Q(next_STATE[1]) );
DFFR_X1 \STATE_reg[1] ( .D(n6), .CK(clock), .RN(n2), .Q(prediction_o) );
MUX2_X1 U2 ( .A(prediction_o), .B(next_STATE[1]), .S(enable), .Z(n6) );
MUX2_X1 U4 ( .A(n1), .B(next_STATE[0]), .S(enable), .Z(n8) );
NOR2_X1 U9 ( .A1(prediction_o), .A2(taken_i), .ZN(n3) );
NAND2_X1 U7 ( .A1(prediction_o), .A2(taken_i), .ZN(n4) );
OAI21_X1 U5 ( .B1(n9), .B2(n3), .A(n4), .ZN(N12) );
OAI21_X1 U6 ( .B1(n3), .B2(n1), .A(n4), .ZN(N11) );
INV_X1 U3 ( .A(reset), .ZN(n2) );
endmodule
module mux41_0 ( IN0, IN1, IN2, IN3, CTRL, OUT1 );
input [31:0] IN0;
input [31:0] IN1;
input [31:0] IN2;
input [31:0] IN3;
input [1:0] CTRL;
output [31:0] OUT1;
wire n5, n6, n7, n8, n45, n46, n51, n52, n71, n1, n2, n3, n4, n9, n10, n11,
n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25,
n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39,
n40, n41, n42, n43, n44, n47, n48, n49, n50, n53, n54, n55, n56, n57,
n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n72,
n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86,
n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121;
AOI22_X1 U69 ( .A1(n7), .A2(IN1[18]), .B1(n16), .B2(IN0[18]), .ZN(n51) );
AOI22_X1 U68 ( .A1(n5), .A2(IN3[18]), .B1(n121), .B2(IN2[18]), .ZN(n52) );
AOI22_X1 U60 ( .A1(n7), .A2(IN1[20]), .B1(n16), .B2(IN0[20]), .ZN(n45) );
INV_X1 U101 ( .A(CTRL[1]), .ZN(n71) );
NOR2_X1 U99 ( .A1(CTRL[0]), .A2(CTRL[1]), .ZN(n8) );
NAND2_X1 U1 ( .A1(n86), .A2(n87), .ZN(OUT1[30]) );
NAND3_X2 U2 ( .A1(n43), .A2(n44), .A3(n47), .ZN(OUT1[2]) );
NAND3_X2 U3 ( .A1(n30), .A2(n31), .A3(n32), .ZN(OUT1[4]) );
NAND3_X2 U4 ( .A1(n35), .A2(n36), .A3(n37), .ZN(OUT1[6]) );
AOI222_X1 U5 ( .A1(n121), .A2(IN2[25]), .B1(IN0[25]), .B2(n16), .C1(n7),
.C2(IN1[25]), .ZN(n1) );
NAND2_X1 U6 ( .A1(n5), .A2(IN3[25]), .ZN(n2) );
NAND2_X1 U7 ( .A1(n1), .A2(n2), .ZN(OUT1[25]) );
AOI22_X1 U8 ( .A1(IN1[24]), .A2(n7), .B1(IN3[24]), .B2(n5), .ZN(n3) );
NAND2_X1 U9 ( .A1(n121), .A2(IN2[24]), .ZN(n4) );
NAND3_X1 U10 ( .A1(n4), .A2(n54), .A3(n3), .ZN(OUT1[24]) );
AOI22_X1 U11 ( .A1(IN0[31]), .A2(n8), .B1(n7), .B2(IN1[31]), .ZN(n9) );
INV_X1 U12 ( .A(n9), .ZN(n24) );
AOI22_X1 U13 ( .A1(IN0[15]), .A2(n16), .B1(n7), .B2(IN1[15]), .ZN(n10) );
INV_X1 U14 ( .A(n10), .ZN(n95) );
AOI22_X1 U15 ( .A1(IN0[23]), .A2(n16), .B1(n7), .B2(IN1[23]), .ZN(n11) );
INV_X1 U16 ( .A(n11), .ZN(n50) );
AOI22_X1 U17 ( .A1(IN3[28]), .A2(n5), .B1(IN2[28]), .B2(n121), .ZN(n12) );
NAND3_X1 U18 ( .A1(n116), .A2(n117), .A3(n12), .ZN(OUT1[28]) );
AOI22_X1 U19 ( .A1(IN1[26]), .A2(n7), .B1(IN3[26]), .B2(n5), .ZN(n13) );
NAND2_X1 U20 ( .A1(n121), .A2(IN2[26]), .ZN(n14) );
NAND3_X1 U21 ( .A1(n14), .A2(n53), .A3(n13), .ZN(OUT1[26]) );
AOI22_X1 U22 ( .A1(IN0[13]), .A2(n16), .B1(n7), .B2(IN1[13]), .ZN(n15) );
INV_X1 U23 ( .A(n15), .ZN(n120) );
NAND2_X2 U24 ( .A1(n74), .A2(n75), .ZN(OUT1[10]) );
NAND3_X2 U25 ( .A1(n58), .A2(n59), .A3(n60), .ZN(OUT1[0]) );
AND2_X2 U26 ( .A1(CTRL[0]), .A2(CTRL[1]), .ZN(n5) );
BUF_X1 U27 ( .A(n6), .Z(n121) );
AND2_X2 U28 ( .A1(n71), .A2(CTRL[0]), .ZN(n7) );
BUF_X2 U29 ( .A(n8), .Z(n16) );
NAND2_X2 U30 ( .A1(n63), .A2(n64), .ZN(OUT1[17]) );
NAND2_X2 U31 ( .A1(n81), .A2(n82), .ZN(OUT1[19]) );
NAND2_X2 U32 ( .A1(n101), .A2(n102), .ZN(OUT1[14]) );
NAND2_X2 U33 ( .A1(n91), .A2(n92), .ZN(OUT1[9]) );
NAND2_X2 U34 ( .A1(n106), .A2(n107), .ZN(OUT1[12]) );
NAND2_X2 U35 ( .A1(n76), .A2(n77), .ZN(OUT1[16]) );
NAND2_X2 U36 ( .A1(n72), .A2(n73), .ZN(OUT1[7]) );
NAND2_X2 U37 ( .A1(n33), .A2(n34), .ZN(OUT1[8]) );
NAND2_X2 U38 ( .A1(n38), .A2(n39), .ZN(OUT1[21]) );
NAND2_X2 U39 ( .A1(n111), .A2(n112), .ZN(OUT1[3]) );
NAND2_X2 U40 ( .A1(n25), .A2(n26), .ZN(OUT1[22]) );
NAND2_X2 U41 ( .A1(n48), .A2(n49), .ZN(OUT1[23]) );
NAND2_X2 U42 ( .A1(n51), .A2(n52), .ZN(OUT1[18]) );
NAND2_X2 U43 ( .A1(n45), .A2(n46), .ZN(OUT1[20]) );
NAND3_X2 U44 ( .A1(n68), .A2(n69), .A3(n70), .ZN(OUT1[5]) );
NAND3_X2 U45 ( .A1(n55), .A2(n56), .A3(n57), .ZN(OUT1[1]) );
NAND2_X1 U46 ( .A1(n118), .A2(n119), .ZN(OUT1[13]) );
NAND2_X1 U47 ( .A1(n93), .A2(n94), .ZN(OUT1[15]) );
NAND2_X1 U48 ( .A1(n17), .A2(n18), .ZN(OUT1[27]) );
NAND2_X1 U49 ( .A1(n61), .A2(n62), .ZN(OUT1[11]) );
NOR2_X1 U50 ( .A1(CTRL[0]), .A2(n71), .ZN(n6) );
NAND2_X1 U51 ( .A1(IN1[2]), .A2(n7), .ZN(n47) );
AOI22_X1 U52 ( .A1(n16), .A2(IN0[2]), .B1(n121), .B2(IN2[2]), .ZN(n44) );
AOI21_X1 U53 ( .B1(IN1[3]), .B2(n7), .A(n113), .ZN(n112) );
NAND2_X1 U54 ( .A1(n114), .A2(n115), .ZN(n113) );
NAND2_X1 U55 ( .A1(n16), .A2(IN0[3]), .ZN(n115) );
NAND2_X1 U56 ( .A1(IN2[3]), .A2(n6), .ZN(n114) );
AOI21_X1 U57 ( .B1(IN2[12]), .B2(n121), .A(n108), .ZN(n107) );
NAND2_X1 U58 ( .A1(n109), .A2(n110), .ZN(n108) );
NAND2_X1 U59 ( .A1(n16), .A2(IN0[12]), .ZN(n110) );
NAND2_X1 U61 ( .A1(IN1[12]), .A2(n7), .ZN(n109) );
AOI21_X1 U62 ( .B1(IN2[13]), .B2(n121), .A(n120), .ZN(n119) );
AOI21_X1 U63 ( .B1(IN2[14]), .B2(n121), .A(n103), .ZN(n102) );
NAND2_X1 U64 ( .A1(n104), .A2(n105), .ZN(n103) );
NAND2_X1 U65 ( .A1(n16), .A2(IN0[14]), .ZN(n105) );
NAND2_X1 U66 ( .A1(IN1[14]), .A2(n7), .ZN(n104) );
AOI21_X1 U67 ( .B1(IN2[15]), .B2(n121), .A(n95), .ZN(n94) );
AOI222_X1 U70 ( .A1(IN1[8]), .A2(n7), .B1(IN2[8]), .B2(n6), .C1(n16), .C2(
IN0[8]), .ZN(n34) );
AOI222_X1 U71 ( .A1(n7), .A2(IN1[9]), .B1(IN2[9]), .B2(n6), .C1(n16), .C2(
IN0[9]), .ZN(n92) );
AOI21_X1 U72 ( .B1(IN2[22]), .B2(n121), .A(n27), .ZN(n26) );
NAND2_X1 U73 ( .A1(n28), .A2(n29), .ZN(n27) );
NAND2_X1 U74 ( .A1(n16), .A2(IN0[22]), .ZN(n29) );
NAND2_X1 U75 ( .A1(IN1[22]), .A2(n7), .ZN(n28) );
NAND2_X1 U76 ( .A1(IN1[4]), .A2(n7), .ZN(n32) );
AOI22_X1 U77 ( .A1(n6), .A2(IN2[4]), .B1(n8), .B2(IN0[4]), .ZN(n31) );
NAND2_X1 U78 ( .A1(IN1[5]), .A2(n7), .ZN(n70) );
AOI22_X1 U79 ( .A1(n6), .A2(IN2[5]), .B1(n8), .B2(IN0[5]), .ZN(n69) );
NAND2_X1 U80 ( .A1(IN1[6]), .A2(n7), .ZN(n37) );
AOI22_X1 U81 ( .A1(IN2[6]), .A2(n6), .B1(n8), .B2(IN0[6]), .ZN(n36) );
AOI222_X1 U82 ( .A1(IN2[7]), .A2(n6), .B1(n7), .B2(IN1[7]), .C1(n16), .C2(
IN0[7]), .ZN(n73) );
NAND2_X1 U83 ( .A1(IN1[0]), .A2(n7), .ZN(n60) );
AOI22_X1 U84 ( .A1(n121), .A2(IN2[0]), .B1(n16), .B2(IN0[0]), .ZN(n59) );
NAND2_X1 U85 ( .A1(IN1[1]), .A2(n7), .ZN(n57) );
AOI22_X1 U86 ( .A1(n121), .A2(IN2[1]), .B1(n16), .B2(IN0[1]), .ZN(n56) );
AOI21_X1 U87 ( .B1(IN2[21]), .B2(n121), .A(n40), .ZN(n39) );
NAND2_X1 U88 ( .A1(n41), .A2(n42), .ZN(n40) );
NAND2_X1 U89 ( .A1(n16), .A2(IN0[21]), .ZN(n42) );
NAND2_X1 U90 ( .A1(IN1[21]), .A2(n7), .ZN(n41) );
NAND2_X1 U91 ( .A1(n16), .A2(IN0[24]), .ZN(n54) );
NAND2_X1 U92 ( .A1(n16), .A2(IN0[26]), .ZN(n53) );
AOI21_X1 U93 ( .B1(IN2[27]), .B2(n121), .A(n19), .ZN(n18) );
NAND2_X1 U94 ( .A1(n20), .A2(n21), .ZN(n19) );
NAND2_X1 U95 ( .A1(n16), .A2(IN0[27]), .ZN(n21) );
NAND2_X1 U96 ( .A1(IN1[27]), .A2(n7), .ZN(n20) );
AOI21_X1 U97 ( .B1(IN2[30]), .B2(n121), .A(n88), .ZN(n87) );
NAND2_X1 U98 ( .A1(n89), .A2(n90), .ZN(n88) );
NAND2_X1 U100 ( .A1(n16), .A2(IN0[30]), .ZN(n90) );
NAND2_X1 U102 ( .A1(IN1[30]), .A2(n7), .ZN(n89) );
AOI21_X1 U103 ( .B1(IN2[31]), .B2(n6), .A(n24), .ZN(n23) );
AOI222_X1 U104 ( .A1(IN2[10]), .A2(n121), .B1(IN1[10]), .B2(n7), .C1(n16),
.C2(IN0[10]), .ZN(n75) );
AOI222_X1 U105 ( .A1(IN2[11]), .A2(n121), .B1(IN1[11]), .B2(n7), .C1(n16),
.C2(IN0[11]), .ZN(n62) );
AOI21_X1 U106 ( .B1(IN2[16]), .B2(n121), .A(n78), .ZN(n77) );
NAND2_X1 U107 ( .A1(n79), .A2(n80), .ZN(n78) );
NAND2_X1 U108 ( .A1(n16), .A2(IN0[16]), .ZN(n80) );
NAND2_X1 U109 ( .A1(IN1[16]), .A2(n7), .ZN(n79) );
AOI21_X1 U110 ( .B1(IN2[17]), .B2(n121), .A(n65), .ZN(n64) );
NAND2_X1 U111 ( .A1(n66), .A2(n67), .ZN(n65) );
NAND2_X1 U112 ( .A1(n16), .A2(IN0[17]), .ZN(n67) );
NAND2_X1 U113 ( .A1(IN1[17]), .A2(n7), .ZN(n66) );
AOI21_X1 U114 ( .B1(IN2[19]), .B2(n121), .A(n83), .ZN(n82) );
NAND2_X1 U115 ( .A1(n84), .A2(n85), .ZN(n83) );
NAND2_X1 U116 ( .A1(n16), .A2(IN0[19]), .ZN(n85) );
NAND2_X1 U117 ( .A1(IN1[19]), .A2(n7), .ZN(n84) );
NAND2_X1 U118 ( .A1(n16), .A2(IN0[28]), .ZN(n117) );
NAND2_X1 U119 ( .A1(IN1[28]), .A2(n7), .ZN(n116) );
AOI21_X1 U120 ( .B1(IN2[29]), .B2(n121), .A(n98), .ZN(n97) );
NAND2_X1 U121 ( .A1(n99), .A2(n100), .ZN(n98) );
NAND2_X1 U122 ( .A1(n16), .A2(IN0[29]), .ZN(n100) );
NAND2_X1 U123 ( .A1(IN1[29]), .A2(n7), .ZN(n99) );
NAND2_X1 U124 ( .A1(n96), .A2(n97), .ZN(OUT1[29]) );
NAND2_X1 U125 ( .A1(IN3[27]), .A2(n5), .ZN(n17) );
NAND2_X1 U126 ( .A1(IN3[31]), .A2(n5), .ZN(n22) );
NAND2_X1 U127 ( .A1(n22), .A2(n23), .ZN(OUT1[31]) );
NAND2_X1 U128 ( .A1(IN3[22]), .A2(n5), .ZN(n25) );
NAND2_X1 U129 ( .A1(IN3[4]), .A2(n5), .ZN(n30) );
NAND2_X1 U130 ( .A1(IN3[8]), .A2(n5), .ZN(n33) );
NAND2_X1 U131 ( .A1(IN3[6]), .A2(n5), .ZN(n35) );
NAND2_X1 U132 ( .A1(IN3[21]), .A2(n5), .ZN(n38) );
NAND2_X1 U133 ( .A1(IN3[2]), .A2(n5), .ZN(n43) );
NAND2_X1 U134 ( .A1(IN3[23]), .A2(n5), .ZN(n48) );
AOI21_X1 U135 ( .B1(IN2[23]), .B2(n121), .A(n50), .ZN(n49) );
NAND2_X1 U136 ( .A1(IN3[1]), .A2(n5), .ZN(n55) );
NAND2_X1 U137 ( .A1(IN3[0]), .A2(n5), .ZN(n58) );
NAND2_X1 U138 ( .A1(IN3[11]), .A2(n5), .ZN(n61) );
NAND2_X1 U139 ( .A1(IN3[17]), .A2(n5), .ZN(n63) );
NAND2_X1 U140 ( .A1(IN3[5]), .A2(n5), .ZN(n68) );
NAND2_X1 U141 ( .A1(IN3[7]), .A2(n5), .ZN(n72) );
NAND2_X1 U142 ( .A1(IN3[10]), .A2(n5), .ZN(n74) );
NAND2_X1 U143 ( .A1(IN3[16]), .A2(n5), .ZN(n76) );
NAND2_X1 U144 ( .A1(IN3[19]), .A2(n5), .ZN(n81) );
NAND2_X1 U145 ( .A1(IN3[30]), .A2(n5), .ZN(n86) );
NAND2_X1 U146 ( .A1(IN3[9]), .A2(n5), .ZN(n91) );
NAND2_X1 U147 ( .A1(IN3[15]), .A2(n5), .ZN(n93) );
NAND2_X1 U148 ( .A1(IN3[29]), .A2(n5), .ZN(n96) );
NAND2_X1 U149 ( .A1(IN3[14]), .A2(n5), .ZN(n101) );
NAND2_X1 U150 ( .A1(IN3[12]), .A2(n5), .ZN(n106) );
NAND2_X1 U151 ( .A1(IN3[3]), .A2(n5), .ZN(n111) );
NAND2_X1 U152 ( .A1(IN3[13]), .A2(n5), .ZN(n118) );
AOI22_X1 U153 ( .A1(n5), .A2(IN3[20]), .B1(n121), .B2(IN2[20]), .ZN(n46) );
endmodule
module add4 ( IN1, OUT1 );
input [31:0] IN1;
output [31:0] OUT1;
wire \IN1[1] , \IN1[0] , n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26,
n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40,
n41, n42, n43, n44, n45, n46, n47;
assign OUT1[1] = \IN1[1] ;
assign \IN1[1] = IN1[1];
assign OUT1[0] = \IN1[0] ;
assign \IN1[0] = IN1[0];
NAND2_X1 U3 ( .A1(IN1[15]), .A2(n15), .ZN(n1) );
NOR4_X1 U4 ( .A1(n17), .A2(n16), .A3(n18), .A4(n1), .ZN(n2) );
NAND3_X1 U5 ( .A1(n14), .A2(IN1[13]), .A3(n2), .ZN(n20) );
XOR2_X1 U6 ( .A(n39), .B(IN1[29]), .Z(OUT1[29]) );
NAND2_X1 U7 ( .A1(n44), .A2(IN1[6]), .ZN(n3) );
XNOR2_X1 U8 ( .A(n3), .B(IN1[7]), .ZN(OUT1[7]) );
NOR2_X1 U9 ( .A1(n8), .A2(n9), .ZN(n4) );
XOR2_X1 U10 ( .A(IN1[11]), .B(n4), .Z(OUT1[11]) );
NOR2_X1 U11 ( .A1(n18), .A2(n13), .ZN(n5) );
XOR2_X1 U12 ( .A(IN1[15]), .B(n5), .Z(OUT1[15]) );
XOR2_X1 U13 ( .A(n21), .B(IN1[17]), .Z(OUT1[17]) );
XOR2_X1 U14 ( .A(n24), .B(IN1[19]), .Z(OUT1[19]) );
XOR2_X1 U15 ( .A(n27), .B(IN1[21]), .Z(OUT1[21]) );
XOR2_X1 U16 ( .A(n30), .B(IN1[23]), .Z(OUT1[23]) );
XOR2_X1 U17 ( .A(n33), .B(IN1[25]), .Z(OUT1[25]) );
XOR2_X1 U18 ( .A(n36), .B(IN1[27]), .Z(OUT1[27]) );
INV_X1 U19 ( .A(n40), .ZN(n6) );
NAND2_X1 U20 ( .A1(IN1[30]), .A2(n6), .ZN(n7) );
XNOR2_X1 U21 ( .A(IN1[31]), .B(n7), .ZN(OUT1[31]) );
NOR2_X1 U22 ( .A1(n45), .A2(n16), .ZN(n10) );
XOR2_X1 U23 ( .A(n8), .B(n9), .Z(OUT1[10]) );
NAND4_X1 U24 ( .A1(IN1[8]), .A2(IN1[9]), .A3(IN1[10]), .A4(IN1[11]), .ZN(n16) );
XNOR2_X1 U25 ( .A(n10), .B(n17), .ZN(OUT1[12]) );
XOR2_X1 U26 ( .A(IN1[13]), .B(n12), .Z(OUT1[13]) );
XNOR2_X1 U27 ( .A(n13), .B(IN1[14]), .ZN(OUT1[14]) );
XNOR2_X1 U28 ( .A(n20), .B(IN1[16]), .ZN(OUT1[16]) );
XNOR2_X1 U29 ( .A(n23), .B(IN1[18]), .ZN(OUT1[18]) );
XNOR2_X1 U30 ( .A(n26), .B(IN1[20]), .ZN(OUT1[20]) );
XNOR2_X1 U31 ( .A(n29), .B(IN1[22]), .ZN(OUT1[22]) );
XNOR2_X1 U32 ( .A(n32), .B(IN1[24]), .ZN(OUT1[24]) );
XNOR2_X1 U33 ( .A(n35), .B(IN1[26]), .ZN(OUT1[26]) );
XNOR2_X1 U34 ( .A(n38), .B(IN1[28]), .ZN(OUT1[28]) );
XNOR2_X1 U35 ( .A(n40), .B(IN1[30]), .ZN(OUT1[30]) );
XNOR2_X1 U36 ( .A(IN1[2]), .B(n41), .ZN(OUT1[3]) );
XOR2_X1 U37 ( .A(IN1[4]), .B(n14), .Z(OUT1[4]) );
XOR2_X1 U38 ( .A(n42), .B(n43), .Z(OUT1[5]) );
XOR2_X1 U39 ( .A(IN1[6]), .B(n44), .Z(OUT1[6]) );
XOR2_X1 U40 ( .A(n46), .B(n45), .Z(OUT1[8]) );
XOR2_X1 U41 ( .A(IN1[9]), .B(n47), .Z(OUT1[9]) );
NAND2_X1 U42 ( .A1(n14), .A2(n15), .ZN(n45) );
NAND2_X1 U43 ( .A1(n12), .A2(IN1[13]), .ZN(n13) );
NOR2_X1 U44 ( .A1(n45), .A2(n46), .ZN(n47) );
NAND2_X1 U45 ( .A1(n47), .A2(IN1[9]), .ZN(n9) );
NAND2_X1 U46 ( .A1(n14), .A2(IN1[4]), .ZN(n43) );
NOR2_X1 U47 ( .A1(n43), .A2(n42), .ZN(n44) );
NAND2_X1 U48 ( .A1(n39), .A2(IN1[29]), .ZN(n40) );
NAND2_X1 U49 ( .A1(n36), .A2(IN1[27]), .ZN(n38) );
INV_X1 U50 ( .A(IN1[5]), .ZN(n42) );
AND4_X1 U51 ( .A1(IN1[5]), .A2(IN1[4]), .A3(IN1[6]), .A4(IN1[7]), .ZN(n15)
);
INV_X1 U52 ( .A(IN1[3]), .ZN(n41) );
INV_X1 U53 ( .A(IN1[2]), .ZN(OUT1[2]) );
NAND2_X1 U54 ( .A1(n21), .A2(IN1[17]), .ZN(n23) );
NAND2_X1 U55 ( .A1(n24), .A2(IN1[19]), .ZN(n26) );
NAND2_X1 U56 ( .A1(n27), .A2(IN1[21]), .ZN(n29) );
NAND2_X1 U57 ( .A1(n30), .A2(IN1[23]), .ZN(n32) );
NAND2_X1 U58 ( .A1(n33), .A2(IN1[25]), .ZN(n35) );
NOR2_X1 U59 ( .A1(n11), .A2(n17), .ZN(n12) );
NOR2_X1 U60 ( .A1(n38), .A2(n37), .ZN(n39) );
NOR2_X1 U61 ( .A1(n41), .A2(OUT1[2]), .ZN(n14) );
NOR2_X1 U62 ( .A1(n20), .A2(n19), .ZN(n21) );
NOR2_X1 U63 ( .A1(n23), .A2(n22), .ZN(n24) );
NOR2_X1 U64 ( .A1(n26), .A2(n25), .ZN(n27) );
NOR2_X1 U65 ( .A1(n29), .A2(n28), .ZN(n30) );
NOR2_X1 U66 ( .A1(n32), .A2(n31), .ZN(n33) );
NOR2_X1 U67 ( .A1(n35), .A2(n34), .ZN(n36) );
INV_X1 U68 ( .A(IN1[14]), .ZN(n18) );
INV_X1 U69 ( .A(IN1[12]), .ZN(n17) );
INV_X1 U70 ( .A(IN1[16]), .ZN(n19) );
INV_X1 U71 ( .A(IN1[18]), .ZN(n22) );
INV_X1 U72 ( .A(IN1[20]), .ZN(n25) );
INV_X1 U73 ( .A(IN1[22]), .ZN(n28) );
INV_X1 U74 ( .A(IN1[24]), .ZN(n31) );
INV_X1 U75 ( .A(IN1[26]), .ZN(n34) );
INV_X1 U76 ( .A(IN1[8]), .ZN(n46) );
INV_X1 U77 ( .A(IN1[28]), .ZN(n37) );
INV_X1 U78 ( .A(IN1[10]), .ZN(n8) );
INV_X1 U79 ( .A(n10), .ZN(n11) );
endmodule
module ff32_en_0 ( D, en, clk, rst, Q );
input [31:0] D;
output [31:0] Q;
input en, clk, rst;
wire net3606, n32;
DFFR_X1 \Q_reg[31] ( .D(D[31]), .CK(net3606), .RN(n32), .Q(Q[31]) );
DFFR_X1 \Q_reg[30] ( .D(D[30]), .CK(net3606), .RN(n32), .Q(Q[30]) );
DFFR_X1 \Q_reg[29] ( .D(D[29]), .CK(net3606), .RN(n32), .Q(Q[29]) );
DFFR_X1 \Q_reg[28] ( .D(D[28]), .CK(net3606), .RN(n32), .Q(Q[28]) );
DFFR_X1 \Q_reg[27] ( .D(D[27]), .CK(net3606), .RN(n32), .Q(Q[27]) );
DFFR_X1 \Q_reg[26] ( .D(D[26]), .CK(net3606), .RN(n32), .Q(Q[26]) );
DFFR_X1 \Q_reg[25] ( .D(D[25]), .CK(net3606), .RN(n32), .Q(Q[25]) );
DFFR_X1 \Q_reg[24] ( .D(D[24]), .CK(net3606), .RN(n32), .Q(Q[24]) );
DFFR_X1 \Q_reg[23] ( .D(D[23]), .CK(net3606), .RN(n32), .Q(Q[23]) );
DFFR_X1 \Q_reg[22] ( .D(D[22]), .CK(net3606), .RN(n32), .Q(Q[22]) );
DFFR_X1 \Q_reg[21] ( .D(D[21]), .CK(net3606), .RN(n32), .Q(Q[21]) );
DFFR_X1 \Q_reg[20] ( .D(D[20]), .CK(net3606), .RN(n32), .Q(Q[20]) );
DFFR_X1 \Q_reg[19] ( .D(D[19]), .CK(net3606), .RN(n32), .Q(Q[19]) );
DFFR_X1 \Q_reg[18] ( .D(D[18]), .CK(net3606), .RN(n32), .Q(Q[18]) );
DFFR_X1 \Q_reg[17] ( .D(D[17]), .CK(net3606), .RN(n32), .Q(Q[17]) );
DFFR_X1 \Q_reg[16] ( .D(D[16]), .CK(net3606), .RN(n32), .Q(Q[16]) );
DFFR_X1 \Q_reg[15] ( .D(D[15]), .CK(net3606), .RN(n32), .Q(Q[15]) );
DFFR_X1 \Q_reg[14] ( .D(D[14]), .CK(net3606), .RN(n32), .Q(Q[14]) );
DFFR_X1 \Q_reg[13] ( .D(D[13]), .CK(net3606), .RN(n32), .Q(Q[13]) );
DFFR_X1 \Q_reg[12] ( .D(D[12]), .CK(net3606), .RN(n32), .Q(Q[12]) );
DFFR_X1 \Q_reg[11] ( .D(D[11]), .CK(net3606), .RN(n32), .Q(Q[11]) );
DFFR_X1 \Q_reg[10] ( .D(D[10]), .CK(net3606), .RN(n32), .Q(Q[10]) );
DFFR_X1 \Q_reg[9] ( .D(D[9]), .CK(net3606), .RN(n32), .Q(Q[9]) );
DFFR_X1 \Q_reg[8] ( .D(D[8]), .CK(net3606), .RN(n32), .Q(Q[8]) );
DFFR_X1 \Q_reg[7] ( .D(D[7]), .CK(net3606), .RN(n32), .Q(Q[7]) );
DFFR_X1 \Q_reg[6] ( .D(D[6]), .CK(net3606), .RN(n32), .Q(Q[6]) );
DFFR_X1 \Q_reg[5] ( .D(D[5]), .CK(net3606), .RN(n32), .Q(Q[5]) );
DFFR_X1 \Q_reg[4] ( .D(D[4]), .CK(net3606), .RN(n32), .Q(Q[4]) );
DFFR_X1 \Q_reg[3] ( .D(D[3]), .CK(net3606), .RN(n32), .Q(Q[3]) );
DFFR_X1 \Q_reg[2] ( .D(D[2]), .CK(net3606), .RN(n32), .Q(Q[2]) );
DFFR_X1 \Q_reg[1] ( .D(D[1]), .CK(net3606), .RN(n32), .Q(Q[1]) );
DFFR_X1 \Q_reg[0] ( .D(D[0]), .CK(net3606), .RN(n32), .Q(Q[0]) );
SNPS_CLOCK_GATE_HIGH_ff32_en_0 clk_gate_Q_reg ( .CLK(clk), .EN(en), .ENCLK(
net3606) );
INV_X2 U2 ( .A(rst), .ZN(n32) );
endmodule
module fw_logic ( D1_i, rAdec_i, D2_i, D3_i, rA_i, rB_i, S_mem_W, S_wb_W,
S_exe_W, S_FWAdec, S_FWA, S_FWB, S_mem_LOAD_BAR );
input [4:0] D1_i;
input [4:0] rAdec_i;
input [4:0] D2_i;
input [4:0] D3_i;
input [4:0] rA_i;
input [4:0] rB_i;
output [1:0] S_FWAdec;
output [1:0] S_FWA;
output [1:0] S_FWB;
input S_mem_W, S_wb_W, S_exe_W, S_mem_LOAD_BAR;
wire S_mem_LOAD, n22, n23, n29, n30, n31, n32, n33, n34, n35, n36, n37,
n38, n39, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62,
n63, n64, n65, n45, n44, n43, n42, n41, n40, n1, n2, n3, n5, n6, n7,
n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
n24, n25, n26, n27, n28, n46, n47, n48, n49, n50, n66, n67, n68, n69,
n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83,
n84, n85, n86;
assign S_mem_LOAD = S_mem_LOAD_BAR;
XOR2_X1 U53 ( .A(D2_i[4]), .B(rB_i[4]), .Z(n30) );
XOR2_X1 U55 ( .A(D2_i[4]), .B(rA_i[4]), .Z(n61) );
INV_X1 U34 ( .A(rA_i[0]), .ZN(n54) );
INV_X1 U33 ( .A(rA_i[2]), .ZN(n55) );
INV_X1 U38 ( .A(rA_i[3]), .ZN(n57) );
INV_X1 U37 ( .A(rA_i[1]), .ZN(n58) );
INV_X1 U41 ( .A(D3_i[4]), .ZN(n29) );
INV_X1 U40 ( .A(rA_i[4]), .ZN(n60) );
INV_X1 U24 ( .A(rAdec_i[4]), .ZN(n45) );
BUF_X1 U2 ( .A(n9), .Z(S_FWB[0]) );
OR3_X1 U3 ( .A1(n42), .A2(n41), .A3(n40), .ZN(n75) );
NOR3_X2 U4 ( .A1(n62), .A2(n63), .A3(n8), .ZN(S_FWA[0]) );
INV_X1 U5 ( .A(D2_i[2]), .ZN(n1) );
OR2_X1 U6 ( .A1(n25), .A2(D3_i[1]), .ZN(n2) );
NAND2_X1 U7 ( .A1(n2), .A2(n26), .ZN(n24) );
OR2_X1 U8 ( .A1(n18), .A2(D3_i[2]), .ZN(n3) );
NAND2_X1 U9 ( .A1(n3), .A2(n19), .ZN(n17) );
OR3_X1 U10 ( .A1(n53), .A2(n52), .A3(n51), .ZN(n84) );
NOR2_X1 U11 ( .A1(n48), .A2(n49), .ZN(S_FWAdec[0]) );
INV_X1 U12 ( .A(n29), .ZN(n5) );
INV_X1 U13 ( .A(D2_i[1]), .ZN(n6) );
INV_X1 U14 ( .A(n79), .ZN(n7) );
NOR2_X1 U15 ( .A1(S_FWAdec[0]), .A2(n75), .ZN(S_FWAdec[1]) );
INV_X1 U16 ( .A(n31), .ZN(n50) );
AOI21_X1 U17 ( .B1(n10), .B2(n11), .A(n12), .ZN(S_FWB[1]) );
INV_X1 U18 ( .A(D3_i[0]), .ZN(n20) );
INV_X1 U19 ( .A(rB_i[2]), .ZN(n18) );
INV_X1 U20 ( .A(D3_i[0]), .ZN(n22) );
INV_X1 U21 ( .A(D3_i[3]), .ZN(n27) );
INV_X1 U22 ( .A(rB_i[1]), .ZN(n25) );
INV_X1 U23 ( .A(D3_i[3]), .ZN(n79) );
INV_X1 U25 ( .A(n28), .ZN(n13) );
INV_X1 U26 ( .A(D3_i[4]), .ZN(n47) );
INV_X1 U27 ( .A(n78), .ZN(n11) );
OR2_X1 U28 ( .A1(n30), .A2(n31), .ZN(n78) );
OR2_X1 U29 ( .A1(n38), .A2(rB_i[1]), .ZN(n86) );
OR2_X1 U30 ( .A1(n37), .A2(rB_i[3]), .ZN(n85) );
OR2_X1 U31 ( .A1(n34), .A2(rB_i[0]), .ZN(n82) );
OR2_X1 U32 ( .A1(n35), .A2(rB_i[2]), .ZN(n83) );
INV_X1 U35 ( .A(D2_i[2]), .ZN(n35) );
NOR2_X1 U36 ( .A1(S_FWA[0]), .A2(n84), .ZN(S_FWA[1]) );
INV_X1 U39 ( .A(n81), .ZN(n80) );
INV_X1 U42 ( .A(D3_i[1]), .ZN(n81) );
INV_X1 U43 ( .A(n23), .ZN(n76) );
INV_X1 U44 ( .A(D3_i[2]), .ZN(n23) );
CLKBUF_X1 U45 ( .A(D3_i[0]), .Z(n77) );
OR2_X1 U46 ( .A1(n61), .A2(n31), .ZN(n8) );
INV_X1 U47 ( .A(D2_i[0]), .ZN(n34) );
INV_X1 U48 ( .A(D2_i[1]), .ZN(n38) );
INV_X1 U49 ( .A(D2_i[3]), .ZN(n37) );
NAND2_X1 U50 ( .A1(S_mem_W), .A2(S_mem_LOAD), .ZN(n31) );
INV_X1 U51 ( .A(n74), .ZN(n67) );
OAI22_X1 U52 ( .A1(n22), .A2(rB_i[0]), .B1(n23), .B2(rB_i[2]), .ZN(n16) );
NOR3_X1 U54 ( .A1(n33), .A2(n78), .A3(n32), .ZN(n9) );
NAND3_X1 U56 ( .A1(n15), .A2(n14), .A3(n13), .ZN(n12) );
NAND2_X1 U57 ( .A1(n47), .A2(rB_i[4]), .ZN(n46) );
NAND2_X1 U58 ( .A1(n20), .A2(rB_i[0]), .ZN(n19) );
NAND2_X1 U59 ( .A1(n27), .A2(rB_i[3]), .ZN(n26) );
OAI211_X1 U60 ( .C1(n29), .C2(rB_i[4]), .A(n46), .B(S_wb_W), .ZN(n28) );
NOR2_X1 U61 ( .A1(n17), .A2(n16), .ZN(n15) );
NOR2_X1 U62 ( .A1(n33), .A2(n32), .ZN(n10) );
OAI22_X1 U63 ( .A1(rB_i[1]), .A2(n81), .B1(n79), .B2(rB_i[3]), .ZN(n21) );
NOR2_X1 U64 ( .A1(n24), .A2(n21), .ZN(n14) );
NAND3_X1 U65 ( .A1(n69), .A2(n67), .A3(n68), .ZN(n48) );
NAND2_X1 U66 ( .A1(n37), .A2(rAdec_i[3]), .ZN(n72) );
NAND2_X1 U67 ( .A1(n72), .A2(n73), .ZN(n70) );
OAI22_X1 U68 ( .A1(n1), .A2(rAdec_i[2]), .B1(rAdec_i[0]), .B2(n34), .ZN(n74)
);
NAND2_X1 U69 ( .A1(n38), .A2(rAdec_i[1]), .ZN(n73) );
OAI22_X1 U70 ( .A1(n37), .A2(rAdec_i[3]), .B1(n6), .B2(rAdec_i[1]), .ZN(n71)
);
NOR2_X1 U71 ( .A1(n70), .A2(n71), .ZN(n69) );
NAND2_X1 U72 ( .A1(n50), .A2(n66), .ZN(n49) );
XNOR2_X1 U73 ( .A(rAdec_i[4]), .B(D2_i[4]), .ZN(n66) );
AOI22_X1 U74 ( .A1(n1), .A2(rAdec_i[2]), .B1(rAdec_i[0]), .B2(n34), .ZN(n68)
);
AOI22_X1 U75 ( .A1(n79), .A2(rAdec_i[3]), .B1(rAdec_i[1]), .B2(n81), .ZN(n44) );
AOI22_X1 U76 ( .A1(n22), .A2(rAdec_i[0]), .B1(rAdec_i[2]), .B2(n23), .ZN(n43) );
OAI221_X1 U77 ( .B1(n5), .B2(n45), .C1(n29), .C2(rAdec_i[4]), .A(S_wb_W),
.ZN(n40) );
OAI221_X1 U78 ( .B1(n79), .B2(rAdec_i[3]), .C1(n81), .C2(rAdec_i[1]), .A(n44), .ZN(n41) );
OAI221_X1 U79 ( .B1(n22), .B2(rAdec_i[0]), .C1(n23), .C2(rAdec_i[2]), .A(n43), .ZN(n42) );
OAI221_X1 U80 ( .B1(n37), .B2(rA_i[3]), .C1(n6), .C2(rA_i[1]), .A(n65), .ZN(
n62) );
AOI22_X1 U81 ( .A1(n54), .A2(n77), .B1(n76), .B2(n55), .ZN(n56) );
OAI221_X1 U82 ( .B1(n34), .B2(rA_i[0]), .C1(n1), .C2(rA_i[2]), .A(n64), .ZN(
n63) );
AOI22_X1 U83 ( .A1(n57), .A2(n7), .B1(n80), .B2(n58), .ZN(n59) );
AOI22_X1 U84 ( .A1(n37), .A2(rA_i[3]), .B1(rA_i[1]), .B2(n6), .ZN(n65) );
NAND3_X1 U85 ( .A1(n36), .A2(n83), .A3(n82), .ZN(n33) );
OAI221_X1 U86 ( .B1(rA_i[4]), .B2(n29), .C1(n60), .C2(n5), .A(S_wb_W), .ZN(
n51) );
OAI221_X1 U87 ( .B1(n57), .B2(n7), .C1(n58), .C2(n80), .A(n59), .ZN(n52) );
OAI221_X1 U88 ( .B1(n54), .B2(n77), .C1(n55), .C2(n76), .A(n56), .ZN(n53) );
AOI22_X1 U89 ( .A1(n34), .A2(rA_i[0]), .B1(rA_i[2]), .B2(n35), .ZN(n64) );
NAND3_X1 U90 ( .A1(n85), .A2(n86), .A3(n39), .ZN(n32) );
AOI22_X1 U91 ( .A1(n34), .A2(rB_i[0]), .B1(rB_i[2]), .B2(n35), .ZN(n36) );
AOI22_X1 U92 ( .A1(n37), .A2(rB_i[3]), .B1(n38), .B2(rB_i[1]), .ZN(n39) );
endmodule
module mem_block ( X_i, LOAD_i, W_o, S_MUX_MEM_i_BAR );
input [31:0] X_i;
input [31:0] LOAD_i;
output [31:0] W_o;
input S_MUX_MEM_i_BAR;
wire S_MUX_MEM_i;
assign S_MUX_MEM_i = S_MUX_MEM_i_BAR;
mux21_2 MUXMEM ( .IN0(X_i), .IN1(LOAD_i), .OUT1(W_o), .CTRL_BAR(S_MUX_MEM_i)
);
endmodule
module mem_regs ( W_i, D3_i, W_o, D3_o, clk, rst );
input [31:0] W_i;
input [4:0] D3_i;
output [31:0] W_o;
output [4:0] D3_o;
input clk, rst;
ff32_SIZE32 W ( .D(W_i), .clk(clk), .rst(rst), .Q(W_o) );
ff32_SIZE5 D3 ( .D(D3_i), .clk(clk), .rst(rst), .Q(D3_o) );
endmodule
module execute_block ( IMM_i, A_i, rB_i, rC_i, MUXED_B_i, S_MUX_ALUIN_i,
FW_X_i, FW_W_i, S_FW_A_i, S_FW_B_i, muxed_dest, muxed_B, S_MUX_DEST_i,
.OP({\OP[4] , \OP[3] , \OP[2] , \OP[1] , \OP[0] }), ALUW_i, DOUT, stall_o,
Clock, Reset );
input [31:0] IMM_i;
input [31:0] A_i;
input [4:0] rB_i;
input [4:0] rC_i;
input [31:0] MUXED_B_i;
input [31:0] FW_X_i;
input [31:0] FW_W_i;
input [1:0] S_FW_A_i;
input [1:0] S_FW_B_i;
output [4:0] muxed_dest;
output [31:0] muxed_B;
input [1:0] S_MUX_DEST_i;
input [12:0] ALUW_i;
output [31:0] DOUT;
input S_MUX_ALUIN_i, \OP[4] , \OP[3] , \OP[2] , \OP[1] , \OP[0] , Clock,
Reset;
output stall_o;
wire n5, n3;
wire [31:0] FWB2alu;
wire [31:0] FWA2alu;
mux21_3 ALUIN_MUX ( .IN0({muxed_B[31:1], n5}), .IN1(IMM_i), .CTRL(
S_MUX_ALUIN_i), .OUT1({FWB2alu[31:22], n3, FWB2alu[20:0]}) );
real_alu_DATA_SIZE32 ALU ( .IN1(FWA2alu), .IN2({FWB2alu[31:22], n3,
FWB2alu[20:0]}), .ALUW_i(ALUW_i), .DOUT(DOUT), .stall_o(stall_o),
.Clock(Clock), .Reset(Reset) );
mux41_MUX_SIZE5 MUXDEST ( .IN0({1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), .IN1(rC_i),
.IN2(rB_i), .IN3({1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), .CTRL(S_MUX_DEST_i),
.OUT1(muxed_dest) );
mux41_MUX_SIZE32_2 MUX_FWA ( .IN0(A_i), .IN1(FW_X_i), .IN2(FW_W_i), .IN3({
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), .CTRL(S_FW_A_i),
.OUT1(FWA2alu) );
mux41_MUX_SIZE32_1 MUX_FWB ( .IN0(MUXED_B_i), .IN1(FW_X_i), .IN2(FW_W_i),
.IN3({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), .CTRL(S_FW_B_i), .OUT1({muxed_B[31:1], n5}) );
CLKBUF_X1 U5 ( .A(n5), .Z(muxed_B[0]) );
endmodule
module execute_regs ( X_i, S_i, D2_i, X_o, S_o, D2_o, stall_i, clk, rst );
input [31:0] X_i;
input [31:0] S_i;
input [4:0] D2_i;
output [31:0] X_o;
output [31:0] S_o;
output [4:0] D2_o;
input stall_i, clk, rst;
ff32_en_SIZE32_3 X ( .D(X_i), .en(1'b1), .clk(clk), .rst(rst), .Q(X_o) );
ff32_en_SIZE32_2 S ( .D(S_i), .en(1'b1), .clk(clk), .rst(rst), .Q(S_o) );
ff32_en_SIZE5_1 D2 ( .D(D2_i), .en(1'b1), .clk(clk), .rst(rst), .Q(D2_o) );
endmodule
module decode_regs ( A_i, B_i, rA_i, rB_i, rC_i, IMM_i, ALUW_i, A_o, B_o, rA_o,
rB_o, rC_o, IMM_o, ALUW_o, stall_i, clk, rst );
input [31:0] A_i;
input [31:0] B_i;
input [4:0] rA_i;
input [4:0] rB_i;
input [4:0] rC_i;
input [31:0] IMM_i;
input [12:0] ALUW_i;
output [31:0] A_o;
output [31:0] B_o;
output [4:0] rA_o;
output [4:0] rB_o;
output [4:0] rC_o;
output [31:0] IMM_o;
output [12:0] ALUW_o;
input stall_i, clk, rst;
wire enable;
ff32_en_SIZE32_0 A ( .D(A_i), .en(enable), .clk(clk), .rst(rst), .Q(A_o) );
ff32_en_SIZE32_5 B ( .D(B_i), .en(enable), .clk(clk), .rst(rst), .Q(B_o) );
ff32_en_SIZE5_0 rA ( .D(rA_i), .en(enable), .clk(clk), .rst(rst), .Q(rA_o)
);
ff32_en_SIZE5_3 rB ( .D(rB_i), .en(enable), .clk(clk), .rst(rst), .Q(rB_o)
);
ff32_en_SIZE5_2 rC ( .D(rC_i), .en(enable), .clk(clk), .rst(rst), .Q(rC_o)
);
ff32_en_SIZE32_4 IMM ( .D(IMM_i), .en(enable), .clk(clk), .rst(rst), .Q(
IMM_o) );
ff32_en_SIZE13 ALUW ( .D(ALUW_i), .en(enable), .clk(clk), .rst(rst), .Q(
ALUW_o) );
INV_X1 U1 ( .A(stall_i), .ZN(enable) );
endmodule
module dlx_regfile ( Clk, Rst, ENABLE, RD1, RD2, WR, ADD_WR, ADD_RD1, ADD_RD2,
DATAIN, OUT1, OUT2 );
input [4:0] ADD_WR;
input [4:0] ADD_RD1;
input [4:0] ADD_RD2;
input [31:0] DATAIN;
output [31:0] OUT1;
output [31:0] OUT2;
input Clk, Rst, ENABLE, RD1, RD2, WR;
wire N2503, N2567, N2631, N2695, N2759, N2823, N2887, N2951, N3015, N3079,
N3143, N3207, N3271, N3335, N3399, N3463, N3527, N3591, N3655, N3719,
N3783, N3847, N3911, N3975, N4039, N4103, N4167, N4231, N4295, N4359,
N4423, N4487, N4490, N4492, N4494, N4496, N4498, N4500, N4502, N4504,
N4506, N4508, N4510, N4512, N4514, N4516, N4518, N4520, N4522, N4524,
N4526, N4528, N4530, N4532, N4534, N4536, N4538, N4540, N4542, N4544,
N4546, N4548, N4550, N4552, N4554, N4556, N4558, N4560, N4562, N4564,
N4566, N4568, N4570, N4572, N4574, N4576, N4578, N4580, N4582, N4584,
N4586, N4588, N4590, N4592, N4594, N4596, N4598, N4600, N4602, N4604,
N4606, N4608, N4610, N4612, N4614, N4615, N4616, net3391, net3396,
net3401, net3406, net3411, net3416, net3421, net3426, net3431,
net3436, net3441, net3446, net3451, net3456, net3461, net3466,
net3471, net3476, net3481, net3486, net3491, net3496, net3501,
net3506, net3511, net3516, net3521, net3526, net3531, net3536,
net3541, net3546, net3551, net3556, n1094, n1150, n1172, n1194, n1216,
n1238, n1260, n1282, n1304, n1326, n1348, n1370, n1392, n1414, n1436,
n1458, n1480, n1502, n1524, n1546, n1568, n1590, n1612, n1634, n1656,
n1678, n1700, n1722, n1744, n1766, n1788, n1810, n1, n2, n3, n37, n39,
n41, n43, n45, n47, n49, n51, n53, n55, n57, n59, n61, n63, n65, n67,
n69, n71, n73, n75, n77, n79, n81, n83, n85, n87, n89, n91, n93, n95,
n97, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109,
n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120,
n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131,
n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142,
n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164,
n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175,
n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186,
n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197,
n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208,
n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230,
n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241,
n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252,
n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263,
n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274,
n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, n285,
n286, n287, n288, n289, n290, n291, n292, n293, n294, n295, n296,
n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307,
n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, n318,
n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, n329,
n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340,
n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351,
n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362,
n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373,
n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384,
n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395,
n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406,
n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417,
n418, n419, n420, n421, n422, n423, n424, n425, n426, n427, n428,
n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, n439,
n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, n450,
n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, n461,
n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472,
n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483,
n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494,
n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, n505,
n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516,
n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527,
n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, n538,
n539, n540, n541, n542, n543, n544, n545, n546, n547, n548, n549,
n550, n551, n552, n553, n554, n555, n556, n557, n558, n559, n560,
n561, n562, n563, n564, n565, n566, n567, n568, n569, n570, n571,
n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, n582,
n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593,
n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604,
n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626,
n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648,
n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659,
n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670,
n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681,
n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692,
n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714,
n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736,
n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780,
n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791,
n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802,
n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813,
n814, n815, n816, n817, n818, n819, n820, n821, n822, n823, n824,
n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846,
n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857,
n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868,
n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879,
n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890,
n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901,
n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912,
n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923,
n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945,
n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956,
n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967,
n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978,
n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989,
n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000,
n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010,
n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020,
n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030,
n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1151, n1152,
n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162,
n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1173,
n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183,
n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1324, n1325, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1393,
n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403,
n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466,
n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476,
n1477, n1478, n1479, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1520, n1521, n1522, n1523, n1525, n1526, n1527, n1528, n1529,
n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1542, n1543, n1544, n1545, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1591, n1592,
n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1613,
n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623,
n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633,
n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644,
n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654,
n1655, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1719, n1720, n1721, n1723, n1724, n1725, n1726, n1727, n1728,
n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738,
n1739, n1740, n1741, n1742, n1743, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1789, n1790, n1791,
n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801,
n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962,
n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152,
n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162,
n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172,
n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182,
n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192,
n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202,
n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482,
n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492,
n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542,
n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552,
n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562,
n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572,
n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582,
n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592,
n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602,
n2603, n2604, n2605, n2606, n2607, n2608, n2609;
assign N4487 = Rst;
DFF_X1 \REGISTERS_reg[0][31] ( .D(n1094), .CK(net3396), .Q(n177) );
DFF_X1 \REGISTERS_reg[0][30] ( .D(n1150), .CK(net3396), .Q(n176) );
DFF_X1 \REGISTERS_reg[0][29] ( .D(n1172), .CK(net3396), .Q(n174) );
DFF_X1 \REGISTERS_reg[0][28] ( .D(n1194), .CK(net3396), .Q(n173) );
DFF_X1 \REGISTERS_reg[0][27] ( .D(n1216), .CK(net3396), .Q(n172) );
DFF_X1 \REGISTERS_reg[0][26] ( .D(n1238), .CK(net3396), .Q(n171) );
DFF_X1 \REGISTERS_reg[0][25] ( .D(n1260), .CK(net3396), .Q(n170) );
DFF_X1 \REGISTERS_reg[0][24] ( .D(n1282), .CK(net3396), .Q(n169) );
DFF_X1 \REGISTERS_reg[0][23] ( .D(n1304), .CK(net3396), .Q(n168) );
DFF_X1 \REGISTERS_reg[0][22] ( .D(n1326), .CK(net3396), .Q(n167) );
DFF_X1 \REGISTERS_reg[0][21] ( .D(n1348), .CK(net3396), .Q(n166) );
DFF_X1 \REGISTERS_reg[0][20] ( .D(n1370), .CK(net3396), .Q(n165) );
DFF_X1 \REGISTERS_reg[0][19] ( .D(n1392), .CK(net3396), .Q(n163) );
DFF_X1 \REGISTERS_reg[0][18] ( .D(n1414), .CK(net3396), .Q(n162) );
DFF_X1 \REGISTERS_reg[0][17] ( .D(n1436), .CK(net3396), .Q(n161) );
DFF_X1 \REGISTERS_reg[0][16] ( .D(n1458), .CK(net3396), .Q(n160) );
DFF_X1 \REGISTERS_reg[0][15] ( .D(n1480), .CK(net3396), .Q(n159) );
DFF_X1 \REGISTERS_reg[0][14] ( .D(n1502), .CK(net3396), .Q(n158) );
DFF_X1 \REGISTERS_reg[0][13] ( .D(n1524), .CK(net3396), .Q(n157) );
DFF_X1 \REGISTERS_reg[0][12] ( .D(n1546), .CK(net3396), .Q(n156) );
DFF_X1 \REGISTERS_reg[0][11] ( .D(n1568), .CK(net3396), .Q(n155) );
DFF_X1 \REGISTERS_reg[0][10] ( .D(n1590), .CK(net3396), .Q(n154) );
DFF_X1 \REGISTERS_reg[0][9] ( .D(n1612), .CK(net3396), .Q(n152) );
DFF_X1 \REGISTERS_reg[0][8] ( .D(n1634), .CK(net3396), .Q(n151) );
DFF_X1 \REGISTERS_reg[0][7] ( .D(n1656), .CK(net3396), .Q(n150) );
DFF_X1 \REGISTERS_reg[0][6] ( .D(n1678), .CK(net3396), .Q(n149) );
DFF_X1 \REGISTERS_reg[0][5] ( .D(n1700), .CK(net3396), .Q(n148) );
DFF_X1 \REGISTERS_reg[0][4] ( .D(n1722), .CK(net3396), .Q(n147) );
DFF_X1 \REGISTERS_reg[0][3] ( .D(n1744), .CK(net3396), .Q(n146) );
DFF_X1 \REGISTERS_reg[0][2] ( .D(n1766), .CK(net3396), .Q(n145) );
DFF_X1 \REGISTERS_reg[0][1] ( .D(n1788), .CK(net3396), .Q(n144) );
DFF_X1 \REGISTERS_reg[0][0] ( .D(n1810), .CK(net3396), .Q(n143) );
DFF_X1 \REGISTERS_reg[1][31] ( .D(n1094), .CK(net3401), .Q(n141) );
DFF_X1 \REGISTERS_reg[1][30] ( .D(n1150), .CK(net3401), .Q(n140) );
DFF_X1 \REGISTERS_reg[1][29] ( .D(n1172), .CK(net3401), .Q(n139) );
DFF_X1 \REGISTERS_reg[1][28] ( .D(n1194), .CK(net3401), .Q(n138) );
DFF_X1 \REGISTERS_reg[1][27] ( .D(n1216), .CK(net3401), .Q(n137) );
DFF_X1 \REGISTERS_reg[1][26] ( .D(n1238), .CK(net3401), .Q(n136) );
DFF_X1 \REGISTERS_reg[1][25] ( .D(n1260), .CK(net3401), .Q(n135) );
DFF_X1 \REGISTERS_reg[1][24] ( .D(n1282), .CK(net3401), .Q(n134) );
DFF_X1 \REGISTERS_reg[1][23] ( .D(n1304), .CK(net3401), .Q(n133) );
DFF_X1 \REGISTERS_reg[1][22] ( .D(n1326), .CK(net3401), .Q(n132) );
DFF_X1 \REGISTERS_reg[1][21] ( .D(n1348), .CK(net3401), .Q(n130) );
DFF_X1 \REGISTERS_reg[1][20] ( .D(n1370), .CK(net3401), .Q(n129) );
DFF_X1 \REGISTERS_reg[1][19] ( .D(n1392), .CK(net3401), .Q(n128) );
DFF_X1 \REGISTERS_reg[1][18] ( .D(n1414), .CK(net3401), .Q(n127) );
DFF_X1 \REGISTERS_reg[1][17] ( .D(n1436), .CK(net3401), .Q(n126) );
DFF_X1 \REGISTERS_reg[1][16] ( .D(n1458), .CK(net3401), .Q(n125) );
DFF_X1 \REGISTERS_reg[1][15] ( .D(n1480), .CK(net3401), .Q(n124) );
DFF_X1 \REGISTERS_reg[1][14] ( .D(n1502), .CK(net3401), .Q(n123) );
DFF_X1 \REGISTERS_reg[1][13] ( .D(n1524), .CK(net3401), .Q(n122) );
DFF_X1 \REGISTERS_reg[1][12] ( .D(n1546), .CK(net3401), .Q(n121) );
DFF_X1 \REGISTERS_reg[1][11] ( .D(n1568), .CK(net3401), .Q(n119) );
DFF_X1 \REGISTERS_reg[1][10] ( .D(n1590), .CK(net3401), .Q(n118) );
DFF_X1 \REGISTERS_reg[1][9] ( .D(n1612), .CK(net3401), .Q(n117) );
DFF_X1 \REGISTERS_reg[1][8] ( .D(n1634), .CK(net3401), .Q(n116) );
DFF_X1 \REGISTERS_reg[1][7] ( .D(n1656), .CK(net3401), .Q(n115) );
DFF_X1 \REGISTERS_reg[1][6] ( .D(n1678), .CK(net3401), .Q(n114) );
DFF_X1 \REGISTERS_reg[1][5] ( .D(n1700), .CK(net3401), .Q(n113) );
DFF_X1 \REGISTERS_reg[1][4] ( .D(n1722), .CK(net3401), .Q(n112) );
DFF_X1 \REGISTERS_reg[1][3] ( .D(n1744), .CK(net3401), .Q(n111) );
DFF_X1 \REGISTERS_reg[1][2] ( .D(n1766), .CK(net3401), .Q(n110) );
DFF_X1 \REGISTERS_reg[1][1] ( .D(n1788), .CK(net3401), .Q(n108) );
DFF_X1 \REGISTERS_reg[1][0] ( .D(n1810), .CK(net3401), .Q(n107) );
DFF_X1 \REGISTERS_reg[2][31] ( .D(n1094), .CK(net3406), .Q(n106) );
DFF_X1 \REGISTERS_reg[2][30] ( .D(n1150), .CK(net3406), .Q(n105) );
DFF_X1 \REGISTERS_reg[2][29] ( .D(n1172), .CK(net3406), .Q(n104) );
DFF_X1 \REGISTERS_reg[2][28] ( .D(n1194), .CK(net3406), .Q(n103) );
DFF_X1 \REGISTERS_reg[2][27] ( .D(n1216), .CK(net3406), .Q(n102) );
DFF_X1 \REGISTERS_reg[2][26] ( .D(n1238), .CK(net3406), .Q(n101) );
DFF_X1 \REGISTERS_reg[2][25] ( .D(n1260), .CK(net3406), .Q(n100) );
DFF_X1 \REGISTERS_reg[2][24] ( .D(n1282), .CK(net3406), .Q(n99) );
DFF_X1 \REGISTERS_reg[2][23] ( .D(n1304), .CK(net3406), .Q(n95) );
DFF_X1 \REGISTERS_reg[2][22] ( .D(n1326), .CK(net3406), .Q(n93) );
DFF_X1 \REGISTERS_reg[2][21] ( .D(n1348), .CK(net3406), .Q(n91) );
DFF_X1 \REGISTERS_reg[2][20] ( .D(n1370), .CK(net3406), .Q(n89) );
DFF_X1 \REGISTERS_reg[2][19] ( .D(n1392), .CK(net3406), .Q(n87) );
DFF_X1 \REGISTERS_reg[2][18] ( .D(n1414), .CK(net3406), .Q(n85) );
DFF_X1 \REGISTERS_reg[2][17] ( .D(n1436), .CK(net3406), .Q(n83) );
DFF_X1 \REGISTERS_reg[2][16] ( .D(n1458), .CK(net3406), .Q(n81) );
DFF_X1 \REGISTERS_reg[2][15] ( .D(n1480), .CK(net3406), .Q(n79) );
DFF_X1 \REGISTERS_reg[2][14] ( .D(n1502), .CK(net3406), .Q(n77) );
DFF_X1 \REGISTERS_reg[2][13] ( .D(n1524), .CK(net3406), .Q(n73) );
DFF_X1 \REGISTERS_reg[2][12] ( .D(n1546), .CK(net3406), .Q(n71) );
DFF_X1 \REGISTERS_reg[2][11] ( .D(n1568), .CK(net3406), .Q(n69) );
DFF_X1 \REGISTERS_reg[2][10] ( .D(n1590), .CK(net3406), .Q(n67) );
DFF_X1 \REGISTERS_reg[2][9] ( .D(n1612), .CK(net3406), .Q(n65) );
DFF_X1 \REGISTERS_reg[2][8] ( .D(n1634), .CK(net3406), .Q(n63) );
DFF_X1 \REGISTERS_reg[2][7] ( .D(n1656), .CK(net3406), .Q(n61) );
DFF_X1 \REGISTERS_reg[2][6] ( .D(n1678), .CK(net3406), .Q(n59) );
DFF_X1 \REGISTERS_reg[2][5] ( .D(n1700), .CK(net3406), .Q(n57) );
DFF_X1 \REGISTERS_reg[2][4] ( .D(n1722), .CK(net3406), .Q(n55) );
DFF_X1 \REGISTERS_reg[2][3] ( .D(n1744), .CK(net3406), .Q(n1100) );
DFF_X1 \REGISTERS_reg[2][2] ( .D(n1766), .CK(net3406), .Q(n1099) );
DFF_X1 \REGISTERS_reg[2][1] ( .D(n1788), .CK(net3406), .Q(n1098) );
DFF_X1 \REGISTERS_reg[2][0] ( .D(n1810), .CK(net3406), .Q(n1097) );
DFF_X1 \REGISTERS_reg[3][31] ( .D(n1094), .CK(net3411), .Q(n1096) );
DFF_X1 \REGISTERS_reg[3][30] ( .D(n1150), .CK(net3411), .Q(n1095) );
DFF_X1 \REGISTERS_reg[3][29] ( .D(n1172), .CK(net3411), .Q(n1093) );
DFF_X1 \REGISTERS_reg[3][28] ( .D(n1194), .CK(net3411), .Q(n1092) );
DFF_X1 \REGISTERS_reg[3][27] ( .D(n1216), .CK(net3411), .Q(n1091) );
DFF_X1 \REGISTERS_reg[3][26] ( .D(n1238), .CK(net3411), .Q(n1090) );
DFF_X1 \REGISTERS_reg[3][25] ( .D(n1260), .CK(net3411), .Q(n1088) );
DFF_X1 \REGISTERS_reg[3][24] ( .D(n1282), .CK(net3411), .Q(n1087) );
DFF_X1 \REGISTERS_reg[3][23] ( .D(n1304), .CK(net3411), .Q(n1086) );
DFF_X1 \REGISTERS_reg[3][22] ( .D(n1326), .CK(net3411), .Q(n1085) );
DFF_X1 \REGISTERS_reg[3][21] ( .D(n1348), .CK(net3411), .Q(n1084) );
DFF_X1 \REGISTERS_reg[3][20] ( .D(n1370), .CK(net3411), .Q(n1083) );
DFF_X1 \REGISTERS_reg[3][19] ( .D(n1392), .CK(net3411), .Q(n1082) );
DFF_X1 \REGISTERS_reg[3][18] ( .D(n1414), .CK(net3411), .Q(n1081) );
DFF_X1 \REGISTERS_reg[3][17] ( .D(n1436), .CK(net3411), .Q(n1080) );
DFF_X1 \REGISTERS_reg[3][16] ( .D(n1458), .CK(net3411), .Q(n1079) );
DFF_X1 \REGISTERS_reg[3][15] ( .D(n1480), .CK(net3411), .Q(n1078) );
DFF_X1 \REGISTERS_reg[3][14] ( .D(n1502), .CK(net3411), .Q(n1077) );
DFF_X1 \REGISTERS_reg[3][13] ( .D(n1524), .CK(net3411), .Q(n1076) );
DFF_X1 \REGISTERS_reg[3][12] ( .D(n1546), .CK(net3411), .Q(n1075) );
DFF_X1 \REGISTERS_reg[3][11] ( .D(n1568), .CK(net3411), .Q(n1074) );
DFF_X1 \REGISTERS_reg[3][10] ( .D(n1590), .CK(net3411), .Q(n1073) );
DFF_X1 \REGISTERS_reg[3][9] ( .D(n1612), .CK(net3411), .Q(n1072) );
DFF_X1 \REGISTERS_reg[3][8] ( .D(n1634), .CK(net3411), .Q(n1071) );
DFF_X1 \REGISTERS_reg[3][7] ( .D(n1656), .CK(net3411), .Q(n1070) );
DFF_X1 \REGISTERS_reg[3][6] ( .D(n1678), .CK(net3411), .Q(n1069) );
DFF_X1 \REGISTERS_reg[3][5] ( .D(n1700), .CK(net3411), .Q(n1067) );
DFF_X1 \REGISTERS_reg[3][4] ( .D(n1722), .CK(net3411), .Q(n1066) );
DFF_X1 \REGISTERS_reg[3][3] ( .D(n1744), .CK(net3411), .Q(n1065) );
DFF_X1 \REGISTERS_reg[3][2] ( .D(n1766), .CK(net3411), .Q(n1064) );
DFF_X1 \REGISTERS_reg[3][1] ( .D(n1788), .CK(net3411), .Q(n1063) );
DFF_X1 \REGISTERS_reg[3][0] ( .D(n1810), .CK(net3411), .Q(n1062) );
DFF_X1 \REGISTERS_reg[4][31] ( .D(n1094), .CK(net3416), .Q(n1061) );
DFF_X1 \REGISTERS_reg[4][30] ( .D(n1150), .CK(net3416), .Q(n1060) );
DFF_X1 \REGISTERS_reg[4][29] ( .D(n1172), .CK(net3416), .Q(n1059) );
DFF_X1 \REGISTERS_reg[4][28] ( .D(n1194), .CK(net3416), .Q(n1058) );
DFF_X1 \REGISTERS_reg[4][27] ( .D(n1216), .CK(net3416), .Q(n1057) );
DFF_X1 \REGISTERS_reg[4][26] ( .D(n1238), .CK(net3416), .Q(n1056) );
DFF_X1 \REGISTERS_reg[4][25] ( .D(n1260), .CK(net3416), .Q(n1055) );
DFF_X1 \REGISTERS_reg[4][24] ( .D(n1282), .CK(net3416), .Q(n1054) );
DFF_X1 \REGISTERS_reg[4][23] ( .D(n1304), .CK(net3416), .Q(n1053) );
DFF_X1 \REGISTERS_reg[4][22] ( .D(n1326), .CK(net3416), .Q(n1052) );
DFF_X1 \REGISTERS_reg[4][21] ( .D(n1348), .CK(net3416), .Q(n1051) );
DFF_X1 \REGISTERS_reg[4][20] ( .D(n1370), .CK(net3416), .Q(n1050) );
DFF_X1 \REGISTERS_reg[4][19] ( .D(n1392), .CK(net3416), .Q(n1049) );
DFF_X1 \REGISTERS_reg[4][18] ( .D(n1414), .CK(net3416), .Q(n1048) );
DFF_X1 \REGISTERS_reg[4][17] ( .D(n1436), .CK(net3416), .Q(n1046) );
DFF_X1 \REGISTERS_reg[4][16] ( .D(n1458), .CK(net3416), .Q(n1045) );
DFF_X1 \REGISTERS_reg[4][15] ( .D(n1480), .CK(net3416), .Q(n1044) );
DFF_X1 \REGISTERS_reg[4][14] ( .D(n1502), .CK(net3416), .Q(n1043) );
DFF_X1 \REGISTERS_reg[4][13] ( .D(n1524), .CK(net3416), .Q(n1042) );
DFF_X1 \REGISTERS_reg[4][12] ( .D(n1546), .CK(net3416), .Q(n1041) );
DFF_X1 \REGISTERS_reg[4][11] ( .D(n1568), .CK(net3416), .Q(n1040) );
DFF_X1 \REGISTERS_reg[4][10] ( .D(n1590), .CK(net3416), .Q(n1039) );
DFF_X1 \REGISTERS_reg[4][9] ( .D(n1612), .CK(net3416), .Q(n1038) );
DFF_X1 \REGISTERS_reg[4][8] ( .D(n1634), .CK(net3416), .Q(n1037) );
DFF_X1 \REGISTERS_reg[4][7] ( .D(n1656), .CK(net3416), .Q(n1036) );
DFF_X1 \REGISTERS_reg[4][6] ( .D(n1678), .CK(net3416), .Q(n1035) );
DFF_X1 \REGISTERS_reg[4][5] ( .D(n1700), .CK(net3416), .Q(n1034) );
DFF_X1 \REGISTERS_reg[4][4] ( .D(n1722), .CK(net3416), .Q(n1033) );
DFF_X1 \REGISTERS_reg[4][3] ( .D(n1744), .CK(net3416), .Q(n1032) );
DFF_X1 \REGISTERS_reg[4][2] ( .D(n1766), .CK(net3416), .Q(n1031) );
DFF_X1 \REGISTERS_reg[4][1] ( .D(n1788), .CK(net3416), .Q(n1030) );
DFF_X1 \REGISTERS_reg[4][0] ( .D(n1810), .CK(net3416), .Q(n1029) );
DFF_X1 \REGISTERS_reg[5][31] ( .D(n1094), .CK(net3421), .Q(n1028) );
DFF_X1 \REGISTERS_reg[5][30] ( .D(n1150), .CK(net3421), .Q(n1027) );
DFF_X1 \REGISTERS_reg[5][29] ( .D(n1172), .CK(net3421), .Q(n1025) );
DFF_X1 \REGISTERS_reg[5][28] ( .D(n1194), .CK(net3421), .Q(n1024) );
DFF_X1 \REGISTERS_reg[5][27] ( .D(n1216), .CK(net3421), .Q(n1023) );
DFF_X1 \REGISTERS_reg[5][26] ( .D(n1238), .CK(net3421), .Q(n1022) );
DFF_X1 \REGISTERS_reg[5][25] ( .D(n1260), .CK(net3421), .Q(n1021) );
DFF_X1 \REGISTERS_reg[5][24] ( .D(n1282), .CK(net3421), .Q(n1020) );
DFF_X1 \REGISTERS_reg[5][23] ( .D(n1304), .CK(net3421), .Q(n1019) );
DFF_X1 \REGISTERS_reg[5][22] ( .D(n1326), .CK(net3421), .Q(n1018) );
DFF_X1 \REGISTERS_reg[5][21] ( .D(n1348), .CK(net3421), .Q(n1017) );
DFF_X1 \REGISTERS_reg[5][20] ( .D(n1370), .CK(net3421), .Q(n1016) );
DFF_X1 \REGISTERS_reg[5][19] ( .D(n1392), .CK(net3421), .Q(n1015) );
DFF_X1 \REGISTERS_reg[5][18] ( .D(n1414), .CK(net3421), .Q(n1014) );
DFF_X1 \REGISTERS_reg[5][17] ( .D(n1436), .CK(net3421), .Q(n1013) );
DFF_X1 \REGISTERS_reg[5][16] ( .D(n1458), .CK(net3421), .Q(n1012) );
DFF_X1 \REGISTERS_reg[5][15] ( .D(n1480), .CK(net3421), .Q(n1011) );
DFF_X1 \REGISTERS_reg[5][14] ( .D(n1502), .CK(net3421), .Q(n1010) );
DFF_X1 \REGISTERS_reg[5][13] ( .D(n1524), .CK(net3421), .Q(n1009) );
DFF_X1 \REGISTERS_reg[5][12] ( .D(n1546), .CK(net3421), .Q(n1008) );
DFF_X1 \REGISTERS_reg[5][11] ( .D(n1568), .CK(net3421), .Q(n1007) );
DFF_X1 \REGISTERS_reg[5][10] ( .D(n1590), .CK(net3421), .Q(n1006) );
DFF_X1 \REGISTERS_reg[5][9] ( .D(n1612), .CK(net3421), .Q(n1004) );
DFF_X1 \REGISTERS_reg[5][8] ( .D(n1634), .CK(net3421), .Q(n1003) );
DFF_X1 \REGISTERS_reg[5][7] ( .D(n1656), .CK(net3421), .Q(n1002) );
DFF_X1 \REGISTERS_reg[5][6] ( .D(n1678), .CK(net3421), .Q(n1001) );
DFF_X1 \REGISTERS_reg[5][5] ( .D(n1700), .CK(net3421), .Q(n1000) );
DFF_X1 \REGISTERS_reg[5][4] ( .D(n1722), .CK(net3421), .Q(n999) );
DFF_X1 \REGISTERS_reg[5][3] ( .D(n1744), .CK(net3421), .Q(n998) );
DFF_X1 \REGISTERS_reg[5][2] ( .D(n1766), .CK(net3421), .Q(n997) );
DFF_X1 \REGISTERS_reg[5][1] ( .D(n1788), .CK(net3421), .Q(n996) );
DFF_X1 \REGISTERS_reg[5][0] ( .D(n1810), .CK(net3421), .Q(n995) );
DFF_X1 \REGISTERS_reg[6][31] ( .D(n1094), .CK(net3426), .Q(n994) );
DFF_X1 \REGISTERS_reg[6][30] ( .D(n1150), .CK(net3426), .Q(n993) );
DFF_X1 \REGISTERS_reg[6][29] ( .D(n1172), .CK(net3426), .Q(n992) );
DFF_X1 \REGISTERS_reg[6][28] ( .D(n1194), .CK(net3426), .Q(n991) );
DFF_X1 \REGISTERS_reg[6][27] ( .D(n1216), .CK(net3426), .Q(n990) );
DFF_X1 \REGISTERS_reg[6][26] ( .D(n1238), .CK(net3426), .Q(n989) );
DFF_X1 \REGISTERS_reg[6][25] ( .D(n1260), .CK(net3426), .Q(n988) );
DFF_X1 \REGISTERS_reg[6][24] ( .D(n1282), .CK(net3426), .Q(n987) );
DFF_X1 \REGISTERS_reg[6][23] ( .D(n1304), .CK(net3426), .Q(n986) );
DFF_X1 \REGISTERS_reg[6][22] ( .D(n1326), .CK(net3426), .Q(n985) );
DFF_X1 \REGISTERS_reg[6][21] ( .D(n1348), .CK(net3426), .Q(n983) );
DFF_X1 \REGISTERS_reg[6][20] ( .D(n1370), .CK(net3426), .Q(n982) );
DFF_X1 \REGISTERS_reg[6][19] ( .D(n1392), .CK(net3426), .Q(n981) );
DFF_X1 \REGISTERS_reg[6][18] ( .D(n1414), .CK(net3426), .Q(n980) );
DFF_X1 \REGISTERS_reg[6][17] ( .D(n1436), .CK(net3426), .Q(n979) );
DFF_X1 \REGISTERS_reg[6][16] ( .D(n1458), .CK(net3426), .Q(n978) );
DFF_X1 \REGISTERS_reg[6][15] ( .D(n1480), .CK(net3426), .Q(n977) );
DFF_X1 \REGISTERS_reg[6][14] ( .D(n1502), .CK(net3426), .Q(n976) );
DFF_X1 \REGISTERS_reg[6][13] ( .D(n1524), .CK(net3426), .Q(n975) );
DFF_X1 \REGISTERS_reg[6][12] ( .D(n1546), .CK(net3426), .Q(n974) );
DFF_X1 \REGISTERS_reg[6][11] ( .D(n1568), .CK(net3426), .Q(n973) );
DFF_X1 \REGISTERS_reg[6][10] ( .D(n1590), .CK(net3426), .Q(n972) );
DFF_X1 \REGISTERS_reg[6][9] ( .D(n1612), .CK(net3426), .Q(n971) );
DFF_X1 \REGISTERS_reg[6][8] ( .D(n1634), .CK(net3426), .Q(n970) );
DFF_X1 \REGISTERS_reg[6][7] ( .D(n1656), .CK(net3426), .Q(n969) );
DFF_X1 \REGISTERS_reg[6][6] ( .D(n1678), .CK(net3426), .Q(n968) );
DFF_X1 \REGISTERS_reg[6][5] ( .D(n1700), .CK(net3426), .Q(n967) );
DFF_X1 \REGISTERS_reg[6][4] ( .D(n1722), .CK(net3426), .Q(n966) );
DFF_X1 \REGISTERS_reg[6][3] ( .D(n1744), .CK(net3426), .Q(n965) );
DFF_X1 \REGISTERS_reg[6][2] ( .D(n1766), .CK(net3426), .Q(n964) );
DFF_X1 \REGISTERS_reg[6][1] ( .D(n1788), .CK(net3426), .Q(n962) );
DFF_X1 \REGISTERS_reg[6][0] ( .D(n1810), .CK(net3426), .Q(n961) );
DFF_X1 \REGISTERS_reg[7][31] ( .D(n1094), .CK(net3431), .Q(n960) );
DFF_X1 \REGISTERS_reg[7][30] ( .D(n1150), .CK(net3431), .Q(n959) );
DFF_X1 \REGISTERS_reg[7][29] ( .D(n1172), .CK(net3431), .Q(n958) );
DFF_X1 \REGISTERS_reg[7][28] ( .D(n1194), .CK(net3431), .Q(n957) );
DFF_X1 \REGISTERS_reg[7][27] ( .D(n1216), .CK(net3431), .Q(n956) );
DFF_X1 \REGISTERS_reg[7][26] ( .D(n1238), .CK(net3431), .Q(n955) );
DFF_X1 \REGISTERS_reg[7][25] ( .D(n1260), .CK(net3431), .Q(n954) );
DFF_X1 \REGISTERS_reg[7][24] ( .D(n1282), .CK(net3431), .Q(n953) );
DFF_X1 \REGISTERS_reg[7][23] ( .D(n1304), .CK(net3431), .Q(n952) );
DFF_X1 \REGISTERS_reg[7][22] ( .D(n1326), .CK(net3431), .Q(n951) );
DFF_X1 \REGISTERS_reg[7][21] ( .D(n1348), .CK(net3431), .Q(n950) );
DFF_X1 \REGISTERS_reg[7][20] ( .D(n1370), .CK(net3431), .Q(n949) );
DFF_X1 \REGISTERS_reg[7][19] ( .D(n1392), .CK(net3431), .Q(n948) );
DFF_X1 \REGISTERS_reg[7][18] ( .D(n1414), .CK(net3431), .Q(n947) );
DFF_X1 \REGISTERS_reg[7][17] ( .D(n1436), .CK(net3431), .Q(n946) );
DFF_X1 \REGISTERS_reg[7][16] ( .D(n1458), .CK(net3431), .Q(n945) );
DFF_X1 \REGISTERS_reg[7][15] ( .D(n1480), .CK(net3431), .Q(n944) );
DFF_X1 \REGISTERS_reg[7][14] ( .D(n1502), .CK(net3431), .Q(n943) );
DFF_X1 \REGISTERS_reg[7][13] ( .D(n1524), .CK(net3431), .Q(n941) );
DFF_X1 \REGISTERS_reg[7][12] ( .D(n1546), .CK(net3431), .Q(n940) );
DFF_X1 \REGISTERS_reg[7][11] ( .D(n1568), .CK(net3431), .Q(n939) );
DFF_X1 \REGISTERS_reg[7][10] ( .D(n1590), .CK(net3431), .Q(n938) );
DFF_X1 \REGISTERS_reg[7][9] ( .D(n1612), .CK(net3431), .Q(n937) );
DFF_X1 \REGISTERS_reg[7][8] ( .D(n1634), .CK(net3431), .Q(n936) );
DFF_X1 \REGISTERS_reg[7][7] ( .D(n1656), .CK(net3431), .Q(n935) );
DFF_X1 \REGISTERS_reg[7][6] ( .D(n1678), .CK(net3431), .Q(n934) );
DFF_X1 \REGISTERS_reg[7][5] ( .D(n1700), .CK(net3431), .Q(n933) );
DFF_X1 \REGISTERS_reg[7][4] ( .D(n1722), .CK(net3431), .Q(n932) );
DFF_X1 \REGISTERS_reg[7][3] ( .D(n1744), .CK(net3431), .Q(n931) );
DFF_X1 \REGISTERS_reg[7][2] ( .D(n1766), .CK(net3431), .Q(n930) );
DFF_X1 \REGISTERS_reg[7][1] ( .D(n1788), .CK(net3431), .Q(n929) );
DFF_X1 \REGISTERS_reg[7][0] ( .D(n1810), .CK(net3431), .Q(n928) );
DFF_X1 \REGISTERS_reg[8][31] ( .D(n1094), .CK(net3436), .Q(n927) );
DFF_X1 \REGISTERS_reg[8][30] ( .D(n1150), .CK(net3436), .Q(n926) );
DFF_X1 \REGISTERS_reg[8][29] ( .D(n1172), .CK(net3436), .Q(n925) );
DFF_X1 \REGISTERS_reg[8][28] ( .D(n1194), .CK(net3436), .Q(n924) );
DFF_X1 \REGISTERS_reg[8][27] ( .D(n1216), .CK(net3436), .Q(n923) );
DFF_X1 \REGISTERS_reg[8][26] ( .D(n1238), .CK(net3436), .Q(n922) );
DFF_X1 \REGISTERS_reg[8][25] ( .D(n1260), .CK(net3436), .Q(n920) );
DFF_X1 \REGISTERS_reg[8][24] ( .D(n1282), .CK(net3436), .Q(n919) );
DFF_X1 \REGISTERS_reg[8][23] ( .D(n1304), .CK(net3436), .Q(n918) );
DFF_X1 \REGISTERS_reg[8][22] ( .D(n1326), .CK(net3436), .Q(n917) );
DFF_X1 \REGISTERS_reg[8][21] ( .D(n1348), .CK(net3436), .Q(n916) );
DFF_X1 \REGISTERS_reg[8][20] ( .D(n1370), .CK(net3436), .Q(n915) );
DFF_X1 \REGISTERS_reg[8][19] ( .D(n1392), .CK(net3436), .Q(n914) );
DFF_X1 \REGISTERS_reg[8][18] ( .D(n1414), .CK(net3436), .Q(n913) );
DFF_X1 \REGISTERS_reg[8][17] ( .D(n1436), .CK(net3436), .Q(n912) );
DFF_X1 \REGISTERS_reg[8][16] ( .D(n1458), .CK(net3436), .Q(n911) );
DFF_X1 \REGISTERS_reg[8][15] ( .D(n1480), .CK(net3436), .Q(n910) );
DFF_X1 \REGISTERS_reg[8][14] ( .D(n1502), .CK(net3436), .Q(n909) );
DFF_X1 \REGISTERS_reg[8][13] ( .D(n1524), .CK(net3436), .Q(n908) );
DFF_X1 \REGISTERS_reg[8][12] ( .D(n1546), .CK(net3436), .Q(n907) );
DFF_X1 \REGISTERS_reg[8][11] ( .D(n1568), .CK(net3436), .Q(n906) );
DFF_X1 \REGISTERS_reg[8][10] ( .D(n1590), .CK(net3436), .Q(n905) );
DFF_X1 \REGISTERS_reg[8][9] ( .D(n1612), .CK(net3436), .Q(n904) );
DFF_X1 \REGISTERS_reg[8][8] ( .D(n1634), .CK(net3436), .Q(n903) );
DFF_X1 \REGISTERS_reg[8][7] ( .D(n1656), .CK(net3436), .Q(n902) );
DFF_X1 \REGISTERS_reg[8][6] ( .D(n1678), .CK(net3436), .Q(n901) );
DFF_X1 \REGISTERS_reg[8][5] ( .D(n1700), .CK(net3436), .Q(n899) );
DFF_X1 \REGISTERS_reg[8][4] ( .D(n1722), .CK(net3436), .Q(n898) );
DFF_X1 \REGISTERS_reg[8][3] ( .D(n1744), .CK(net3436), .Q(n897) );
DFF_X1 \REGISTERS_reg[8][2] ( .D(n1766), .CK(net3436), .Q(n896) );
DFF_X1 \REGISTERS_reg[8][1] ( .D(n1788), .CK(net3436), .Q(n895) );
DFF_X1 \REGISTERS_reg[8][0] ( .D(n1810), .CK(net3436), .Q(n894) );
DFF_X1 \REGISTERS_reg[9][31] ( .D(n1094), .CK(net3441), .Q(n893) );
DFF_X1 \REGISTERS_reg[9][30] ( .D(n1150), .CK(net3441), .Q(n892) );
DFF_X1 \REGISTERS_reg[9][29] ( .D(n1172), .CK(net3441), .Q(n891) );
DFF_X1 \REGISTERS_reg[9][28] ( .D(n1194), .CK(net3441), .Q(n890) );
DFF_X1 \REGISTERS_reg[9][27] ( .D(n1216), .CK(net3441), .Q(n889) );
DFF_X1 \REGISTERS_reg[9][26] ( .D(n1238), .CK(net3441), .Q(n888) );
DFF_X1 \REGISTERS_reg[9][25] ( .D(n1260), .CK(net3441), .Q(n887) );
DFF_X1 \REGISTERS_reg[9][24] ( .D(n1282), .CK(net3441), .Q(n886) );
DFF_X1 \REGISTERS_reg[9][23] ( .D(n1304), .CK(net3441), .Q(n885) );
DFF_X1 \REGISTERS_reg[9][22] ( .D(n1326), .CK(net3441), .Q(n884) );
DFF_X1 \REGISTERS_reg[9][21] ( .D(n1348), .CK(net3441), .Q(n883) );
DFF_X1 \REGISTERS_reg[9][20] ( .D(n1370), .CK(net3441), .Q(n882) );
DFF_X1 \REGISTERS_reg[9][19] ( .D(n1392), .CK(net3441), .Q(n881) );
DFF_X1 \REGISTERS_reg[9][18] ( .D(n1414), .CK(net3441), .Q(n880) );
DFF_X1 \REGISTERS_reg[9][17] ( .D(n1436), .CK(net3441), .Q(n878) );
DFF_X1 \REGISTERS_reg[9][16] ( .D(n1458), .CK(net3441), .Q(n877) );
DFF_X1 \REGISTERS_reg[9][15] ( .D(n1480), .CK(net3441), .Q(n876) );
DFF_X1 \REGISTERS_reg[9][14] ( .D(n1502), .CK(net3441), .Q(n875) );
DFF_X1 \REGISTERS_reg[9][13] ( .D(n1524), .CK(net3441), .Q(n874) );
DFF_X1 \REGISTERS_reg[9][12] ( .D(n1546), .CK(net3441), .Q(n873) );
DFF_X1 \REGISTERS_reg[9][11] ( .D(n1568), .CK(net3441), .Q(n872) );
DFF_X1 \REGISTERS_reg[9][10] ( .D(n1590), .CK(net3441), .Q(n871) );
DFF_X1 \REGISTERS_reg[9][9] ( .D(n1612), .CK(net3441), .Q(n870) );
DFF_X1 \REGISTERS_reg[9][8] ( .D(n1634), .CK(net3441), .Q(n869) );
DFF_X1 \REGISTERS_reg[9][7] ( .D(n1656), .CK(net3441), .Q(n868) );
DFF_X1 \REGISTERS_reg[9][6] ( .D(n1678), .CK(net3441), .Q(n867) );
DFF_X1 \REGISTERS_reg[9][5] ( .D(n1700), .CK(net3441), .Q(n866) );
DFF_X1 \REGISTERS_reg[9][4] ( .D(n1722), .CK(net3441), .Q(n865) );
DFF_X1 \REGISTERS_reg[9][3] ( .D(n1744), .CK(net3441), .Q(n864) );
DFF_X1 \REGISTERS_reg[9][2] ( .D(n1766), .CK(net3441), .Q(n863) );
DFF_X1 \REGISTERS_reg[9][1] ( .D(n1788), .CK(net3441), .Q(n862) );
DFF_X1 \REGISTERS_reg[9][0] ( .D(n1810), .CK(net3441), .Q(n861) );
DFF_X1 \REGISTERS_reg[10][31] ( .D(n1094), .CK(net3446), .Q(n860) );
DFF_X1 \REGISTERS_reg[10][30] ( .D(n1150), .CK(net3446), .Q(n859) );
DFF_X1 \REGISTERS_reg[10][29] ( .D(n1172), .CK(net3446), .Q(n857) );
DFF_X1 \REGISTERS_reg[10][28] ( .D(n1194), .CK(net3446), .Q(n856) );
DFF_X1 \REGISTERS_reg[10][27] ( .D(n1216), .CK(net3446), .Q(n855) );
DFF_X1 \REGISTERS_reg[10][26] ( .D(n1238), .CK(net3446), .Q(n854) );
DFF_X1 \REGISTERS_reg[10][25] ( .D(n1260), .CK(net3446), .Q(n853) );
DFF_X1 \REGISTERS_reg[10][24] ( .D(n1282), .CK(net3446), .Q(n852) );
DFF_X1 \REGISTERS_reg[10][23] ( .D(n1304), .CK(net3446), .Q(n851) );
DFF_X1 \REGISTERS_reg[10][22] ( .D(n1326), .CK(net3446), .Q(n850) );
DFF_X1 \REGISTERS_reg[10][21] ( .D(n1348), .CK(net3446), .Q(n849) );
DFF_X1 \REGISTERS_reg[10][20] ( .D(n1370), .CK(net3446), .Q(n848) );
DFF_X1 \REGISTERS_reg[10][19] ( .D(n1392), .CK(net3446), .Q(n847) );
DFF_X1 \REGISTERS_reg[10][18] ( .D(n1414), .CK(net3446), .Q(n846) );
DFF_X1 \REGISTERS_reg[10][17] ( .D(n1436), .CK(net3446), .Q(n845) );
DFF_X1 \REGISTERS_reg[10][16] ( .D(n1458), .CK(net3446), .Q(n844) );
DFF_X1 \REGISTERS_reg[10][15] ( .D(n1480), .CK(net3446), .Q(n843) );
DFF_X1 \REGISTERS_reg[10][14] ( .D(n1502), .CK(net3446), .Q(n842) );
DFF_X1 \REGISTERS_reg[10][13] ( .D(n1524), .CK(net3446), .Q(n841) );
DFF_X1 \REGISTERS_reg[10][12] ( .D(n1546), .CK(net3446), .Q(n840) );
DFF_X1 \REGISTERS_reg[10][11] ( .D(n1568), .CK(net3446), .Q(n839) );
DFF_X1 \REGISTERS_reg[10][10] ( .D(n1590), .CK(net3446), .Q(n838) );
DFF_X1 \REGISTERS_reg[10][9] ( .D(n1612), .CK(net3446), .Q(n836) );
DFF_X1 \REGISTERS_reg[10][8] ( .D(n1634), .CK(net3446), .Q(n835) );
DFF_X1 \REGISTERS_reg[10][7] ( .D(n1656), .CK(net3446), .Q(n834) );
DFF_X1 \REGISTERS_reg[10][6] ( .D(n1678), .CK(net3446), .Q(n833) );
DFF_X1 \REGISTERS_reg[10][5] ( .D(n1700), .CK(net3446), .Q(n832) );
DFF_X1 \REGISTERS_reg[10][4] ( .D(n1722), .CK(net3446), .Q(n831) );
DFF_X1 \REGISTERS_reg[10][3] ( .D(n1744), .CK(net3446), .Q(n830) );
DFF_X1 \REGISTERS_reg[10][2] ( .D(n1766), .CK(net3446), .Q(n829) );
DFF_X1 \REGISTERS_reg[10][1] ( .D(n1788), .CK(net3446), .Q(n828) );
DFF_X1 \REGISTERS_reg[10][0] ( .D(n1810), .CK(net3446), .Q(n827) );
DFF_X1 \REGISTERS_reg[11][31] ( .D(n1094), .CK(net3451), .Q(n826) );
DFF_X1 \REGISTERS_reg[11][30] ( .D(n1150), .CK(net3451), .Q(n825) );
DFF_X1 \REGISTERS_reg[11][29] ( .D(n1172), .CK(net3451), .Q(n824) );
DFF_X1 \REGISTERS_reg[11][28] ( .D(n1194), .CK(net3451), .Q(n823) );
DFF_X1 \REGISTERS_reg[11][27] ( .D(n1216), .CK(net3451), .Q(n822) );
DFF_X1 \REGISTERS_reg[11][26] ( .D(n1238), .CK(net3451), .Q(n821) );
DFF_X1 \REGISTERS_reg[11][25] ( .D(n1260), .CK(net3451), .Q(n820) );
DFF_X1 \REGISTERS_reg[11][24] ( .D(n1282), .CK(net3451), .Q(n819) );
DFF_X1 \REGISTERS_reg[11][23] ( .D(n1304), .CK(net3451), .Q(n818) );
DFF_X1 \REGISTERS_reg[11][22] ( .D(n1326), .CK(net3451), .Q(n817) );
DFF_X1 \REGISTERS_reg[11][21] ( .D(n1348), .CK(net3451), .Q(n815) );
DFF_X1 \REGISTERS_reg[11][20] ( .D(n1370), .CK(net3451), .Q(n814) );
DFF_X1 \REGISTERS_reg[11][19] ( .D(n1392), .CK(net3451), .Q(n813) );
DFF_X1 \REGISTERS_reg[11][18] ( .D(n1414), .CK(net3451), .Q(n812) );
DFF_X1 \REGISTERS_reg[11][17] ( .D(n1436), .CK(net3451), .Q(n811) );
DFF_X1 \REGISTERS_reg[11][16] ( .D(n1458), .CK(net3451), .Q(n810) );
DFF_X1 \REGISTERS_reg[11][15] ( .D(n1480), .CK(net3451), .Q(n809) );
DFF_X1 \REGISTERS_reg[11][14] ( .D(n1502), .CK(net3451), .Q(n808) );
DFF_X1 \REGISTERS_reg[11][13] ( .D(n1524), .CK(net3451), .Q(n807) );
DFF_X1 \REGISTERS_reg[11][12] ( .D(n1546), .CK(net3451), .Q(n806) );
DFF_X1 \REGISTERS_reg[11][11] ( .D(n1568), .CK(net3451), .Q(n805) );
DFF_X1 \REGISTERS_reg[11][10] ( .D(n1590), .CK(net3451), .Q(n804) );
DFF_X1 \REGISTERS_reg[11][9] ( .D(n1612), .CK(net3451), .Q(n803) );
DFF_X1 \REGISTERS_reg[11][8] ( .D(n1634), .CK(net3451), .Q(n802) );
DFF_X1 \REGISTERS_reg[11][7] ( .D(n1656), .CK(net3451), .Q(n801) );
DFF_X1 \REGISTERS_reg[11][6] ( .D(n1678), .CK(net3451), .Q(n800) );
DFF_X1 \REGISTERS_reg[11][5] ( .D(n1700), .CK(net3451), .Q(n799) );
DFF_X1 \REGISTERS_reg[11][4] ( .D(n1722), .CK(net3451), .Q(n798) );
DFF_X1 \REGISTERS_reg[11][3] ( .D(n1744), .CK(net3451), .Q(n797) );
DFF_X1 \REGISTERS_reg[11][2] ( .D(n1766), .CK(net3451), .Q(n796) );
DFF_X1 \REGISTERS_reg[11][1] ( .D(n1788), .CK(net3451), .Q(n794) );
DFF_X1 \REGISTERS_reg[11][0] ( .D(n1810), .CK(net3451), .Q(n793) );
DFF_X1 \REGISTERS_reg[12][31] ( .D(n1094), .CK(net3456), .Q(n792) );
DFF_X1 \REGISTERS_reg[12][30] ( .D(n1150), .CK(net3456), .Q(n791) );
DFF_X1 \REGISTERS_reg[12][29] ( .D(n1172), .CK(net3456), .Q(n790) );
DFF_X1 \REGISTERS_reg[12][28] ( .D(n1194), .CK(net3456), .Q(n789) );
DFF_X1 \REGISTERS_reg[12][27] ( .D(n1216), .CK(net3456), .Q(n788) );
DFF_X1 \REGISTERS_reg[12][26] ( .D(n1238), .CK(net3456), .Q(n787) );
DFF_X1 \REGISTERS_reg[12][25] ( .D(n1260), .CK(net3456), .Q(n786) );
DFF_X1 \REGISTERS_reg[12][24] ( .D(n1282), .CK(net3456), .Q(n785) );
DFF_X1 \REGISTERS_reg[12][23] ( .D(n1304), .CK(net3456), .Q(n784) );
DFF_X1 \REGISTERS_reg[12][22] ( .D(n1326), .CK(net3456), .Q(n783) );
DFF_X1 \REGISTERS_reg[12][21] ( .D(n1348), .CK(net3456), .Q(n782) );
DFF_X1 \REGISTERS_reg[12][20] ( .D(n1370), .CK(net3456), .Q(n781) );
DFF_X1 \REGISTERS_reg[12][19] ( .D(n1392), .CK(net3456), .Q(n780) );
DFF_X1 \REGISTERS_reg[12][18] ( .D(n1414), .CK(net3456), .Q(n779) );
DFF_X1 \REGISTERS_reg[12][17] ( .D(n1436), .CK(net3456), .Q(n778) );
DFF_X1 \REGISTERS_reg[12][16] ( .D(n1458), .CK(net3456), .Q(n777) );
DFF_X1 \REGISTERS_reg[12][15] ( .D(n1480), .CK(net3456), .Q(n776) );
DFF_X1 \REGISTERS_reg[12][14] ( .D(n1502), .CK(net3456), .Q(n775) );
DFF_X1 \REGISTERS_reg[12][13] ( .D(n1524), .CK(net3456), .Q(n773) );
DFF_X1 \REGISTERS_reg[12][12] ( .D(n1546), .CK(net3456), .Q(n772) );
DFF_X1 \REGISTERS_reg[12][11] ( .D(n1568), .CK(net3456), .Q(n771) );
DFF_X1 \REGISTERS_reg[12][10] ( .D(n1590), .CK(net3456), .Q(n770) );
DFF_X1 \REGISTERS_reg[12][9] ( .D(n1612), .CK(net3456), .Q(n769) );
DFF_X1 \REGISTERS_reg[12][8] ( .D(n1634), .CK(net3456), .Q(n768) );
DFF_X1 \REGISTERS_reg[12][7] ( .D(n1656), .CK(net3456), .Q(n767) );
DFF_X1 \REGISTERS_reg[12][6] ( .D(n1678), .CK(net3456), .Q(n766) );
DFF_X1 \REGISTERS_reg[12][5] ( .D(n1700), .CK(net3456), .Q(n765) );
DFF_X1 \REGISTERS_reg[12][4] ( .D(n1722), .CK(net3456), .Q(n764) );
DFF_X1 \REGISTERS_reg[12][3] ( .D(n1744), .CK(net3456), .Q(n763) );
DFF_X1 \REGISTERS_reg[12][2] ( .D(n1766), .CK(net3456), .Q(n762) );
DFF_X1 \REGISTERS_reg[12][1] ( .D(n1788), .CK(net3456), .Q(n761) );
DFF_X1 \REGISTERS_reg[12][0] ( .D(n1810), .CK(net3456), .Q(n760) );
DFF_X1 \REGISTERS_reg[13][31] ( .D(n1094), .CK(net3461), .Q(n759) );
DFF_X1 \REGISTERS_reg[13][30] ( .D(n1150), .CK(net3461), .Q(n758) );
DFF_X1 \REGISTERS_reg[13][29] ( .D(n1172), .CK(net3461), .Q(n757) );
DFF_X1 \REGISTERS_reg[13][28] ( .D(n1194), .CK(net3461), .Q(n756) );
DFF_X1 \REGISTERS_reg[13][27] ( .D(n1216), .CK(net3461), .Q(n755) );
DFF_X1 \REGISTERS_reg[13][26] ( .D(n1238), .CK(net3461), .Q(n754) );
DFF_X1 \REGISTERS_reg[13][25] ( .D(n1260), .CK(net3461), .Q(n752) );
DFF_X1 \REGISTERS_reg[13][24] ( .D(n1282), .CK(net3461), .Q(n751) );
DFF_X1 \REGISTERS_reg[13][23] ( .D(n1304), .CK(net3461), .Q(n750) );
DFF_X1 \REGISTERS_reg[13][22] ( .D(n1326), .CK(net3461), .Q(n749) );
DFF_X1 \REGISTERS_reg[13][21] ( .D(n1348), .CK(net3461), .Q(n748) );
DFF_X1 \REGISTERS_reg[13][20] ( .D(n1370), .CK(net3461), .Q(n747) );
DFF_X1 \REGISTERS_reg[13][19] ( .D(n1392), .CK(net3461), .Q(n746) );
DFF_X1 \REGISTERS_reg[13][18] ( .D(n1414), .CK(net3461), .Q(n745) );
DFF_X1 \REGISTERS_reg[13][17] ( .D(n1436), .CK(net3461), .Q(n744) );
DFF_X1 \REGISTERS_reg[13][16] ( .D(n1458), .CK(net3461), .Q(n743) );
DFF_X1 \REGISTERS_reg[13][15] ( .D(n1480), .CK(net3461), .Q(n742) );
DFF_X1 \REGISTERS_reg[13][14] ( .D(n1502), .CK(net3461), .Q(n741) );
DFF_X1 \REGISTERS_reg[13][13] ( .D(n1524), .CK(net3461), .Q(n740) );
DFF_X1 \REGISTERS_reg[13][12] ( .D(n1546), .CK(net3461), .Q(n739) );
DFF_X1 \REGISTERS_reg[13][11] ( .D(n1568), .CK(net3461), .Q(n738) );
DFF_X1 \REGISTERS_reg[13][10] ( .D(n1590), .CK(net3461), .Q(n737) );
DFF_X1 \REGISTERS_reg[13][9] ( .D(n1612), .CK(net3461), .Q(n736) );
DFF_X1 \REGISTERS_reg[13][8] ( .D(n1634), .CK(net3461), .Q(n735) );
DFF_X1 \REGISTERS_reg[13][7] ( .D(n1656), .CK(net3461), .Q(n734) );
DFF_X1 \REGISTERS_reg[13][6] ( .D(n1678), .CK(net3461), .Q(n733) );
DFF_X1 \REGISTERS_reg[13][5] ( .D(n1700), .CK(net3461), .Q(n731) );
DFF_X1 \REGISTERS_reg[13][4] ( .D(n1722), .CK(net3461), .Q(n730) );
DFF_X1 \REGISTERS_reg[13][3] ( .D(n1744), .CK(net3461), .Q(n729) );
DFF_X1 \REGISTERS_reg[13][2] ( .D(n1766), .CK(net3461), .Q(n728) );
DFF_X1 \REGISTERS_reg[13][1] ( .D(n1788), .CK(net3461), .Q(n727) );
DFF_X1 \REGISTERS_reg[13][0] ( .D(n1810), .CK(net3461), .Q(n726) );
DFF_X1 \REGISTERS_reg[14][31] ( .D(n1094), .CK(net3466), .Q(n725) );
DFF_X1 \REGISTERS_reg[14][30] ( .D(n1150), .CK(net3466), .Q(n724) );
DFF_X1 \REGISTERS_reg[14][29] ( .D(n1172), .CK(net3466), .Q(n723) );
DFF_X1 \REGISTERS_reg[14][28] ( .D(n1194), .CK(net3466), .Q(n722) );
DFF_X1 \REGISTERS_reg[14][27] ( .D(n1216), .CK(net3466), .Q(n721) );
DFF_X1 \REGISTERS_reg[14][26] ( .D(n1238), .CK(net3466), .Q(n720) );
DFF_X1 \REGISTERS_reg[14][25] ( .D(n1260), .CK(net3466), .Q(n719) );
DFF_X1 \REGISTERS_reg[14][24] ( .D(n1282), .CK(net3466), .Q(n718) );
DFF_X1 \REGISTERS_reg[14][23] ( .D(n1304), .CK(net3466), .Q(n717) );
DFF_X1 \REGISTERS_reg[14][22] ( .D(n1326), .CK(net3466), .Q(n716) );
DFF_X1 \REGISTERS_reg[14][21] ( .D(n1348), .CK(net3466), .Q(n715) );
DFF_X1 \REGISTERS_reg[14][20] ( .D(n1370), .CK(net3466), .Q(n714) );
DFF_X1 \REGISTERS_reg[14][19] ( .D(n1392), .CK(net3466), .Q(n713) );
DFF_X1 \REGISTERS_reg[14][18] ( .D(n1414), .CK(net3466), .Q(n712) );
DFF_X1 \REGISTERS_reg[14][17] ( .D(n1436), .CK(net3466), .Q(n710) );
DFF_X1 \REGISTERS_reg[14][16] ( .D(n1458), .CK(net3466), .Q(n709) );
DFF_X1 \REGISTERS_reg[14][15] ( .D(n1480), .CK(net3466), .Q(n708) );
DFF_X1 \REGISTERS_reg[14][14] ( .D(n1502), .CK(net3466), .Q(n707) );
DFF_X1 \REGISTERS_reg[14][13] ( .D(n1524), .CK(net3466), .Q(n706) );
DFF_X1 \REGISTERS_reg[14][12] ( .D(n1546), .CK(net3466), .Q(n705) );
DFF_X1 \REGISTERS_reg[14][11] ( .D(n1568), .CK(net3466), .Q(n704) );
DFF_X1 \REGISTERS_reg[14][10] ( .D(n1590), .CK(net3466), .Q(n703) );
DFF_X1 \REGISTERS_reg[14][9] ( .D(n1612), .CK(net3466), .Q(n702) );
DFF_X1 \REGISTERS_reg[14][8] ( .D(n1634), .CK(net3466), .Q(n701) );
DFF_X1 \REGISTERS_reg[14][7] ( .D(n1656), .CK(net3466), .Q(n700) );
DFF_X1 \REGISTERS_reg[14][6] ( .D(n1678), .CK(net3466), .Q(n699) );
DFF_X1 \REGISTERS_reg[14][5] ( .D(n1700), .CK(net3466), .Q(n698) );
DFF_X1 \REGISTERS_reg[14][4] ( .D(n1722), .CK(net3466), .Q(n697) );
DFF_X1 \REGISTERS_reg[14][3] ( .D(n1744), .CK(net3466), .Q(n696) );
DFF_X1 \REGISTERS_reg[14][2] ( .D(n1766), .CK(net3466), .Q(n695) );
DFF_X1 \REGISTERS_reg[14][1] ( .D(n1788), .CK(net3466), .Q(n694) );
DFF_X1 \REGISTERS_reg[14][0] ( .D(n1810), .CK(net3466), .Q(n693) );
DFF_X1 \REGISTERS_reg[15][31] ( .D(n1094), .CK(net3471), .Q(n692) );
DFF_X1 \REGISTERS_reg[15][30] ( .D(n1150), .CK(net3471), .Q(n691) );
DFF_X1 \REGISTERS_reg[15][29] ( .D(n1172), .CK(net3471), .Q(n689) );
DFF_X1 \REGISTERS_reg[15][28] ( .D(n1194), .CK(net3471), .Q(n688) );
DFF_X1 \REGISTERS_reg[15][27] ( .D(n1216), .CK(net3471), .Q(n687) );
DFF_X1 \REGISTERS_reg[15][26] ( .D(n1238), .CK(net3471), .Q(n686) );
DFF_X1 \REGISTERS_reg[15][25] ( .D(n1260), .CK(net3471), .Q(n685) );
DFF_X1 \REGISTERS_reg[15][24] ( .D(n1282), .CK(net3471), .Q(n684) );
DFF_X1 \REGISTERS_reg[15][23] ( .D(n1304), .CK(net3471), .Q(n683) );
DFF_X1 \REGISTERS_reg[15][22] ( .D(n1326), .CK(net3471), .Q(n682) );
DFF_X1 \REGISTERS_reg[15][21] ( .D(n1348), .CK(net3471), .Q(n681) );
DFF_X1 \REGISTERS_reg[15][20] ( .D(n1370), .CK(net3471), .Q(n680) );
DFF_X1 \REGISTERS_reg[15][19] ( .D(n1392), .CK(net3471), .Q(n679) );
DFF_X1 \REGISTERS_reg[15][18] ( .D(n1414), .CK(net3471), .Q(n678) );
DFF_X1 \REGISTERS_reg[15][17] ( .D(n1436), .CK(net3471), .Q(n677) );
DFF_X1 \REGISTERS_reg[15][16] ( .D(n1458), .CK(net3471), .Q(n676) );
DFF_X1 \REGISTERS_reg[15][15] ( .D(n1480), .CK(net3471), .Q(n675) );
DFF_X1 \REGISTERS_reg[15][14] ( .D(n1502), .CK(net3471), .Q(n674) );
DFF_X1 \REGISTERS_reg[15][13] ( .D(n1524), .CK(net3471), .Q(n673) );
DFF_X1 \REGISTERS_reg[15][12] ( .D(n1546), .CK(net3471), .Q(n672) );
DFF_X1 \REGISTERS_reg[15][11] ( .D(n1568), .CK(net3471), .Q(n671) );
DFF_X1 \REGISTERS_reg[15][10] ( .D(n1590), .CK(net3471), .Q(n670) );
DFF_X1 \REGISTERS_reg[15][9] ( .D(n1612), .CK(net3471), .Q(n668) );
DFF_X1 \REGISTERS_reg[15][8] ( .D(n1634), .CK(net3471), .Q(n667) );
DFF_X1 \REGISTERS_reg[15][7] ( .D(n1656), .CK(net3471), .Q(n666) );
DFF_X1 \REGISTERS_reg[15][6] ( .D(n1678), .CK(net3471), .Q(n665) );
DFF_X1 \REGISTERS_reg[15][5] ( .D(n1700), .CK(net3471), .Q(n664) );
DFF_X1 \REGISTERS_reg[15][4] ( .D(n1722), .CK(net3471), .Q(n663) );
DFF_X1 \REGISTERS_reg[15][3] ( .D(n1744), .CK(net3471), .Q(n662) );
DFF_X1 \REGISTERS_reg[15][2] ( .D(n1766), .CK(net3471), .Q(n661) );
DFF_X1 \REGISTERS_reg[15][1] ( .D(n1788), .CK(net3471), .Q(n660) );
DFF_X1 \REGISTERS_reg[15][0] ( .D(n1810), .CK(net3471), .Q(n659) );
DFF_X1 \REGISTERS_reg[16][31] ( .D(n1094), .CK(net3476), .Q(n658) );
DFF_X1 \REGISTERS_reg[16][30] ( .D(n1150), .CK(net3476), .Q(n657) );
DFF_X1 \REGISTERS_reg[16][29] ( .D(n1172), .CK(net3476), .Q(n656) );
DFF_X1 \REGISTERS_reg[16][28] ( .D(n1194), .CK(net3476), .Q(n655) );
DFF_X1 \REGISTERS_reg[16][27] ( .D(n1216), .CK(net3476), .Q(n654) );
DFF_X1 \REGISTERS_reg[16][26] ( .D(n1238), .CK(net3476), .Q(n653) );
DFF_X1 \REGISTERS_reg[16][25] ( .D(n1260), .CK(net3476), .Q(n652) );
DFF_X1 \REGISTERS_reg[16][24] ( .D(n1282), .CK(net3476), .Q(n651) );
DFF_X1 \REGISTERS_reg[16][23] ( .D(n1304), .CK(net3476), .Q(n650) );
DFF_X1 \REGISTERS_reg[16][22] ( .D(n1326), .CK(net3476), .Q(n649) );
DFF_X1 \REGISTERS_reg[16][21] ( .D(n1348), .CK(net3476), .Q(n647) );
DFF_X1 \REGISTERS_reg[16][20] ( .D(n1370), .CK(net3476), .Q(n646) );
DFF_X1 \REGISTERS_reg[16][19] ( .D(n1392), .CK(net3476), .Q(n645) );
DFF_X1 \REGISTERS_reg[16][18] ( .D(n1414), .CK(net3476), .Q(n644) );
DFF_X1 \REGISTERS_reg[16][17] ( .D(n1436), .CK(net3476), .Q(n643) );
DFF_X1 \REGISTERS_reg[16][16] ( .D(n1458), .CK(net3476), .Q(n642) );
DFF_X1 \REGISTERS_reg[16][15] ( .D(n1480), .CK(net3476), .Q(n641) );
DFF_X1 \REGISTERS_reg[16][14] ( .D(n1502), .CK(net3476), .Q(n640) );
DFF_X1 \REGISTERS_reg[16][13] ( .D(n1524), .CK(net3476), .Q(n639) );
DFF_X1 \REGISTERS_reg[16][12] ( .D(n1546), .CK(net3476), .Q(n638) );
DFF_X1 \REGISTERS_reg[16][11] ( .D(n1568), .CK(net3476), .Q(n637) );
DFF_X1 \REGISTERS_reg[16][10] ( .D(n1590), .CK(net3476), .Q(n636) );
DFF_X1 \REGISTERS_reg[16][9] ( .D(n1612), .CK(net3476), .Q(n635) );
DFF_X1 \REGISTERS_reg[16][8] ( .D(n1634), .CK(net3476), .Q(n634) );
DFF_X1 \REGISTERS_reg[16][7] ( .D(n1656), .CK(net3476), .Q(n633) );
DFF_X1 \REGISTERS_reg[16][6] ( .D(n1678), .CK(net3476), .Q(n632) );
DFF_X1 \REGISTERS_reg[16][5] ( .D(n1700), .CK(net3476), .Q(n631) );
DFF_X1 \REGISTERS_reg[16][4] ( .D(n1722), .CK(net3476), .Q(n630) );
DFF_X1 \REGISTERS_reg[16][3] ( .D(n1744), .CK(net3476), .Q(n629) );
DFF_X1 \REGISTERS_reg[16][2] ( .D(n1766), .CK(net3476), .Q(n628) );
DFF_X1 \REGISTERS_reg[16][1] ( .D(n1788), .CK(net3476), .Q(n626) );
DFF_X1 \REGISTERS_reg[16][0] ( .D(n1810), .CK(net3476), .Q(n625) );
DFF_X1 \REGISTERS_reg[17][31] ( .D(n1094), .CK(net3481), .Q(n624) );
DFF_X1 \REGISTERS_reg[17][30] ( .D(n1150), .CK(net3481), .Q(n623) );
DFF_X1 \REGISTERS_reg[17][29] ( .D(n1172), .CK(net3481), .Q(n622) );
DFF_X1 \REGISTERS_reg[17][28] ( .D(n1194), .CK(net3481), .Q(n621) );
DFF_X1 \REGISTERS_reg[17][27] ( .D(n1216), .CK(net3481), .Q(n620) );
DFF_X1 \REGISTERS_reg[17][26] ( .D(n1238), .CK(net3481), .Q(n619) );
DFF_X1 \REGISTERS_reg[17][25] ( .D(n1260), .CK(net3481), .Q(n618) );
DFF_X1 \REGISTERS_reg[17][24] ( .D(n1282), .CK(net3481), .Q(n617) );
DFF_X1 \REGISTERS_reg[17][23] ( .D(n1304), .CK(net3481), .Q(n616) );
DFF_X1 \REGISTERS_reg[17][22] ( .D(n1326), .CK(net3481), .Q(n615) );
DFF_X1 \REGISTERS_reg[17][21] ( .D(n1348), .CK(net3481), .Q(n614) );
DFF_X1 \REGISTERS_reg[17][20] ( .D(n1370), .CK(net3481), .Q(n613) );
DFF_X1 \REGISTERS_reg[17][19] ( .D(n1392), .CK(net3481), .Q(n612) );
DFF_X1 \REGISTERS_reg[17][18] ( .D(n1414), .CK(net3481), .Q(n611) );
DFF_X1 \REGISTERS_reg[17][17] ( .D(n1436), .CK(net3481), .Q(n610) );
DFF_X1 \REGISTERS_reg[17][16] ( .D(n1458), .CK(net3481), .Q(n609) );
DFF_X1 \REGISTERS_reg[17][15] ( .D(n1480), .CK(net3481), .Q(n608) );
DFF_X1 \REGISTERS_reg[17][14] ( .D(n1502), .CK(net3481), .Q(n607) );
DFF_X1 \REGISTERS_reg[17][13] ( .D(n1524), .CK(net3481), .Q(n605) );
DFF_X1 \REGISTERS_reg[17][12] ( .D(n1546), .CK(net3481), .Q(n604) );
DFF_X1 \REGISTERS_reg[17][11] ( .D(n1568), .CK(net3481), .Q(n603) );
DFF_X1 \REGISTERS_reg[17][10] ( .D(n1590), .CK(net3481), .Q(n602) );
DFF_X1 \REGISTERS_reg[17][9] ( .D(n1612), .CK(net3481), .Q(n601) );
DFF_X1 \REGISTERS_reg[17][8] ( .D(n1634), .CK(net3481), .Q(n600) );
DFF_X1 \REGISTERS_reg[17][7] ( .D(n1656), .CK(net3481), .Q(n599) );
DFF_X1 \REGISTERS_reg[17][6] ( .D(n1678), .CK(net3481), .Q(n598) );
DFF_X1 \REGISTERS_reg[17][5] ( .D(n1700), .CK(net3481), .Q(n597) );
DFF_X1 \REGISTERS_reg[17][4] ( .D(n1722), .CK(net3481), .Q(n596) );
DFF_X1 \REGISTERS_reg[17][3] ( .D(n1744), .CK(net3481), .Q(n595) );
DFF_X1 \REGISTERS_reg[17][2] ( .D(n1766), .CK(net3481), .Q(n594) );
DFF_X1 \REGISTERS_reg[17][1] ( .D(n1788), .CK(net3481), .Q(n593) );
DFF_X1 \REGISTERS_reg[17][0] ( .D(n1810), .CK(net3481), .Q(n592) );
DFF_X1 \REGISTERS_reg[18][31] ( .D(n1094), .CK(net3486), .Q(n591) );
DFF_X1 \REGISTERS_reg[18][30] ( .D(n1150), .CK(net3486), .Q(n590) );
DFF_X1 \REGISTERS_reg[18][29] ( .D(n1172), .CK(net3486), .Q(n589) );
DFF_X1 \REGISTERS_reg[18][28] ( .D(n1194), .CK(net3486), .Q(n588) );
DFF_X1 \REGISTERS_reg[18][27] ( .D(n1216), .CK(net3486), .Q(n587) );
DFF_X1 \REGISTERS_reg[18][26] ( .D(n1238), .CK(net3486), .Q(n586) );
DFF_X1 \REGISTERS_reg[18][25] ( .D(n1260), .CK(net3486), .Q(n584) );
DFF_X1 \REGISTERS_reg[18][24] ( .D(n1282), .CK(net3486), .Q(n583) );
DFF_X1 \REGISTERS_reg[18][23] ( .D(n1304), .CK(net3486), .Q(n582) );
DFF_X1 \REGISTERS_reg[18][22] ( .D(n1326), .CK(net3486), .Q(n581) );
DFF_X1 \REGISTERS_reg[18][21] ( .D(n1348), .CK(net3486), .Q(n580) );
DFF_X1 \REGISTERS_reg[18][20] ( .D(n1370), .CK(net3486), .Q(n579) );
DFF_X1 \REGISTERS_reg[18][19] ( .D(n1392), .CK(net3486), .Q(n578) );
DFF_X1 \REGISTERS_reg[18][18] ( .D(n1414), .CK(net3486), .Q(n577) );
DFF_X1 \REGISTERS_reg[18][17] ( .D(n1436), .CK(net3486), .Q(n576) );
DFF_X1 \REGISTERS_reg[18][16] ( .D(n1458), .CK(net3486), .Q(n575) );
DFF_X1 \REGISTERS_reg[18][15] ( .D(n1480), .CK(net3486), .Q(n574) );
DFF_X1 \REGISTERS_reg[18][14] ( .D(n1502), .CK(net3486), .Q(n573) );
DFF_X1 \REGISTERS_reg[18][13] ( .D(n1524), .CK(net3486), .Q(n572) );
DFF_X1 \REGISTERS_reg[18][12] ( .D(n1546), .CK(net3486), .Q(n571) );
DFF_X1 \REGISTERS_reg[18][11] ( .D(n1568), .CK(net3486), .Q(n570) );
DFF_X1 \REGISTERS_reg[18][10] ( .D(n1590), .CK(net3486), .Q(n569) );
DFF_X1 \REGISTERS_reg[18][9] ( .D(n1612), .CK(net3486), .Q(n568) );
DFF_X1 \REGISTERS_reg[18][8] ( .D(n1634), .CK(net3486), .Q(n567) );
DFF_X1 \REGISTERS_reg[18][7] ( .D(n1656), .CK(net3486), .Q(n566) );
DFF_X1 \REGISTERS_reg[18][6] ( .D(n1678), .CK(net3486), .Q(n565) );
DFF_X1 \REGISTERS_reg[18][5] ( .D(n1700), .CK(net3486), .Q(n563) );
DFF_X1 \REGISTERS_reg[18][4] ( .D(n1722), .CK(net3486), .Q(n562) );
DFF_X1 \REGISTERS_reg[18][3] ( .D(n1744), .CK(net3486), .Q(n561) );
DFF_X1 \REGISTERS_reg[18][2] ( .D(n1766), .CK(net3486), .Q(n560) );
DFF_X1 \REGISTERS_reg[18][1] ( .D(n1788), .CK(net3486), .Q(n559) );
DFF_X1 \REGISTERS_reg[18][0] ( .D(n1810), .CK(net3486), .Q(n558) );
DFF_X1 \REGISTERS_reg[19][31] ( .D(n1094), .CK(net3491), .Q(n557) );
DFF_X1 \REGISTERS_reg[19][30] ( .D(n1150), .CK(net3491), .Q(n556) );
DFF_X1 \REGISTERS_reg[19][29] ( .D(n1172), .CK(net3491), .Q(n555) );
DFF_X1 \REGISTERS_reg[19][28] ( .D(n1194), .CK(net3491), .Q(n554) );
DFF_X1 \REGISTERS_reg[19][27] ( .D(n1216), .CK(net3491), .Q(n553) );
DFF_X1 \REGISTERS_reg[19][26] ( .D(n1238), .CK(net3491), .Q(n552) );
DFF_X1 \REGISTERS_reg[19][25] ( .D(n1260), .CK(net3491), .Q(n551) );
DFF_X1 \REGISTERS_reg[19][24] ( .D(n1282), .CK(net3491), .Q(n550) );
DFF_X1 \REGISTERS_reg[19][23] ( .D(n1304), .CK(net3491), .Q(n549) );
DFF_X1 \REGISTERS_reg[19][22] ( .D(n1326), .CK(net3491), .Q(n548) );
DFF_X1 \REGISTERS_reg[19][21] ( .D(n1348), .CK(net3491), .Q(n547) );
DFF_X1 \REGISTERS_reg[19][20] ( .D(n1370), .CK(net3491), .Q(n546) );
DFF_X1 \REGISTERS_reg[19][19] ( .D(n1392), .CK(net3491), .Q(n545) );
DFF_X1 \REGISTERS_reg[19][18] ( .D(n1414), .CK(net3491), .Q(n544) );
DFF_X1 \REGISTERS_reg[19][17] ( .D(n1436), .CK(net3491), .Q(n542) );
DFF_X1 \REGISTERS_reg[19][16] ( .D(n1458), .CK(net3491), .Q(n541) );
DFF_X1 \REGISTERS_reg[19][15] ( .D(n1480), .CK(net3491), .Q(n540) );
DFF_X1 \REGISTERS_reg[19][14] ( .D(n1502), .CK(net3491), .Q(n539) );
DFF_X1 \REGISTERS_reg[19][13] ( .D(n1524), .CK(net3491), .Q(n538) );
DFF_X1 \REGISTERS_reg[19][12] ( .D(n1546), .CK(net3491), .Q(n537) );
DFF_X1 \REGISTERS_reg[19][11] ( .D(n1568), .CK(net3491), .Q(n536) );
DFF_X1 \REGISTERS_reg[19][10] ( .D(n1590), .CK(net3491), .Q(n535) );
DFF_X1 \REGISTERS_reg[19][9] ( .D(n1612), .CK(net3491), .Q(n534) );
DFF_X1 \REGISTERS_reg[19][8] ( .D(n1634), .CK(net3491), .Q(n533) );
DFF_X1 \REGISTERS_reg[19][7] ( .D(n1656), .CK(net3491), .Q(n532) );
DFF_X1 \REGISTERS_reg[19][6] ( .D(n1678), .CK(net3491), .Q(n531) );
DFF_X1 \REGISTERS_reg[19][5] ( .D(n1700), .CK(net3491), .Q(n530) );
DFF_X1 \REGISTERS_reg[19][4] ( .D(n1722), .CK(net3491), .Q(n529) );
DFF_X1 \REGISTERS_reg[19][3] ( .D(n1744), .CK(net3491), .Q(n528) );
DFF_X1 \REGISTERS_reg[19][2] ( .D(n1766), .CK(net3491), .Q(n527) );
DFF_X1 \REGISTERS_reg[19][1] ( .D(n1788), .CK(net3491), .Q(n526) );
DFF_X1 \REGISTERS_reg[19][0] ( .D(n1810), .CK(net3491), .Q(n525) );
DFF_X1 \REGISTERS_reg[20][31] ( .D(n1094), .CK(net3496), .Q(n524) );
DFF_X1 \REGISTERS_reg[20][30] ( .D(n1150), .CK(net3496), .Q(n523) );
DFF_X1 \REGISTERS_reg[20][29] ( .D(n1172), .CK(net3496), .Q(n521) );
DFF_X1 \REGISTERS_reg[20][28] ( .D(n1194), .CK(net3496), .Q(n520) );
DFF_X1 \REGISTERS_reg[20][27] ( .D(n1216), .CK(net3496), .Q(n519) );
DFF_X1 \REGISTERS_reg[20][26] ( .D(n1238), .CK(net3496), .Q(n518) );
DFF_X1 \REGISTERS_reg[20][25] ( .D(n1260), .CK(net3496), .Q(n517) );
DFF_X1 \REGISTERS_reg[20][24] ( .D(n1282), .CK(net3496), .Q(n516) );
DFF_X1 \REGISTERS_reg[20][23] ( .D(n1304), .CK(net3496), .Q(n515) );
DFF_X1 \REGISTERS_reg[20][22] ( .D(n1326), .CK(net3496), .Q(n514) );
DFF_X1 \REGISTERS_reg[20][21] ( .D(n1348), .CK(net3496), .Q(n513) );
DFF_X1 \REGISTERS_reg[20][20] ( .D(n1370), .CK(net3496), .Q(n512) );
DFF_X1 \REGISTERS_reg[20][19] ( .D(n1392), .CK(net3496), .Q(n511) );
DFF_X1 \REGISTERS_reg[20][18] ( .D(n1414), .CK(net3496), .Q(n510) );
DFF_X1 \REGISTERS_reg[20][17] ( .D(n1436), .CK(net3496), .Q(n509) );
DFF_X1 \REGISTERS_reg[20][16] ( .D(n1458), .CK(net3496), .Q(n508) );
DFF_X1 \REGISTERS_reg[20][15] ( .D(n1480), .CK(net3496), .Q(n507) );
DFF_X1 \REGISTERS_reg[20][14] ( .D(n1502), .CK(net3496), .Q(n506) );
DFF_X1 \REGISTERS_reg[20][13] ( .D(n1524), .CK(net3496), .Q(n505) );
DFF_X1 \REGISTERS_reg[20][12] ( .D(n1546), .CK(net3496), .Q(n504) );
DFF_X1 \REGISTERS_reg[20][11] ( .D(n1568), .CK(net3496), .Q(n503) );
DFF_X1 \REGISTERS_reg[20][10] ( .D(n1590), .CK(net3496), .Q(n502) );
DFF_X1 \REGISTERS_reg[20][9] ( .D(n1612), .CK(net3496), .Q(n500) );
DFF_X1 \REGISTERS_reg[20][8] ( .D(n1634), .CK(net3496), .Q(n499) );
DFF_X1 \REGISTERS_reg[20][7] ( .D(n1656), .CK(net3496), .Q(n498) );
DFF_X1 \REGISTERS_reg[20][6] ( .D(n1678), .CK(net3496), .Q(n497) );
DFF_X1 \REGISTERS_reg[20][5] ( .D(n1700), .CK(net3496), .Q(n496) );
DFF_X1 \REGISTERS_reg[20][4] ( .D(n1722), .CK(net3496), .Q(n495) );
DFF_X1 \REGISTERS_reg[20][3] ( .D(n1744), .CK(net3496), .Q(n494) );
DFF_X1 \REGISTERS_reg[20][2] ( .D(n1766), .CK(net3496), .Q(n493) );
DFF_X1 \REGISTERS_reg[20][1] ( .D(n1788), .CK(net3496), .Q(n492) );
DFF_X1 \REGISTERS_reg[20][0] ( .D(n1810), .CK(net3496), .Q(n491) );
DFF_X1 \REGISTERS_reg[21][31] ( .D(n1094), .CK(net3501), .Q(n490) );
DFF_X1 \REGISTERS_reg[21][30] ( .D(n1150), .CK(net3501), .Q(n489) );
DFF_X1 \REGISTERS_reg[21][29] ( .D(n1172), .CK(net3501), .Q(n488) );
DFF_X1 \REGISTERS_reg[21][28] ( .D(n1194), .CK(net3501), .Q(n487) );
DFF_X1 \REGISTERS_reg[21][27] ( .D(n1216), .CK(net3501), .Q(n486) );
DFF_X1 \REGISTERS_reg[21][26] ( .D(n1238), .CK(net3501), .Q(n485) );
DFF_X1 \REGISTERS_reg[21][25] ( .D(n1260), .CK(net3501), .Q(n484) );
DFF_X1 \REGISTERS_reg[21][24] ( .D(n1282), .CK(net3501), .Q(n483) );
DFF_X1 \REGISTERS_reg[21][23] ( .D(n1304), .CK(net3501), .Q(n482) );
DFF_X1 \REGISTERS_reg[21][22] ( .D(n1326), .CK(net3501), .Q(n481) );
DFF_X1 \REGISTERS_reg[21][21] ( .D(n1348), .CK(net3501), .Q(n479) );
DFF_X1 \REGISTERS_reg[21][20] ( .D(n1370), .CK(net3501), .Q(n478) );
DFF_X1 \REGISTERS_reg[21][19] ( .D(n1392), .CK(net3501), .Q(n477) );
DFF_X1 \REGISTERS_reg[21][18] ( .D(n1414), .CK(net3501), .Q(n476) );
DFF_X1 \REGISTERS_reg[21][17] ( .D(n1436), .CK(net3501), .Q(n475) );
DFF_X1 \REGISTERS_reg[21][16] ( .D(n1458), .CK(net3501), .Q(n474) );
DFF_X1 \REGISTERS_reg[21][15] ( .D(n1480), .CK(net3501), .Q(n473) );
DFF_X1 \REGISTERS_reg[21][14] ( .D(n1502), .CK(net3501), .Q(n472) );
DFF_X1 \REGISTERS_reg[21][13] ( .D(n1524), .CK(net3501), .Q(n471) );
DFF_X1 \REGISTERS_reg[21][12] ( .D(n1546), .CK(net3501), .Q(n470) );
DFF_X1 \REGISTERS_reg[21][11] ( .D(n1568), .CK(net3501), .Q(n469) );
DFF_X1 \REGISTERS_reg[21][10] ( .D(n1590), .CK(net3501), .Q(n468) );
DFF_X1 \REGISTERS_reg[21][9] ( .D(n1612), .CK(net3501), .Q(n467) );
DFF_X1 \REGISTERS_reg[21][8] ( .D(n1634), .CK(net3501), .Q(n466) );
DFF_X1 \REGISTERS_reg[21][7] ( .D(n1656), .CK(net3501), .Q(n465) );
DFF_X1 \REGISTERS_reg[21][6] ( .D(n1678), .CK(net3501), .Q(n464) );
DFF_X1 \REGISTERS_reg[21][5] ( .D(n1700), .CK(net3501), .Q(n463) );
DFF_X1 \REGISTERS_reg[21][4] ( .D(n1722), .CK(net3501), .Q(n462) );
DFF_X1 \REGISTERS_reg[21][3] ( .D(n1744), .CK(net3501), .Q(n461) );
DFF_X1 \REGISTERS_reg[21][2] ( .D(n1766), .CK(net3501), .Q(n460) );
DFF_X1 \REGISTERS_reg[21][1] ( .D(n1788), .CK(net3501), .Q(n458) );
DFF_X1 \REGISTERS_reg[21][0] ( .D(n1810), .CK(net3501), .Q(n457) );
DFF_X1 \REGISTERS_reg[22][31] ( .D(n1094), .CK(net3506), .Q(n456) );
DFF_X1 \REGISTERS_reg[22][30] ( .D(n1150), .CK(net3506), .Q(n455) );
DFF_X1 \REGISTERS_reg[22][29] ( .D(n1172), .CK(net3506), .Q(n454) );
DFF_X1 \REGISTERS_reg[22][28] ( .D(n1194), .CK(net3506), .Q(n453) );
DFF_X1 \REGISTERS_reg[22][27] ( .D(n1216), .CK(net3506), .Q(n452) );
DFF_X1 \REGISTERS_reg[22][26] ( .D(n1238), .CK(net3506), .Q(n451) );
DFF_X1 \REGISTERS_reg[22][25] ( .D(n1260), .CK(net3506), .Q(n450) );
DFF_X1 \REGISTERS_reg[22][24] ( .D(n1282), .CK(net3506), .Q(n449) );
DFF_X1 \REGISTERS_reg[22][23] ( .D(n1304), .CK(net3506), .Q(n448) );
DFF_X1 \REGISTERS_reg[22][22] ( .D(n1326), .CK(net3506), .Q(n447) );
DFF_X1 \REGISTERS_reg[22][21] ( .D(n1348), .CK(net3506), .Q(n446) );
DFF_X1 \REGISTERS_reg[22][20] ( .D(n1370), .CK(net3506), .Q(n445) );
DFF_X1 \REGISTERS_reg[22][19] ( .D(n1392), .CK(net3506), .Q(n444) );
DFF_X1 \REGISTERS_reg[22][18] ( .D(n1414), .CK(net3506), .Q(n443) );
DFF_X1 \REGISTERS_reg[22][17] ( .D(n1436), .CK(net3506), .Q(n442) );
DFF_X1 \REGISTERS_reg[22][16] ( .D(n1458), .CK(net3506), .Q(n441) );
DFF_X1 \REGISTERS_reg[22][15] ( .D(n1480), .CK(net3506), .Q(n440) );
DFF_X1 \REGISTERS_reg[22][14] ( .D(n1502), .CK(net3506), .Q(n439) );
DFF_X1 \REGISTERS_reg[22][13] ( .D(n1524), .CK(net3506), .Q(n437) );
DFF_X1 \REGISTERS_reg[22][12] ( .D(n1546), .CK(net3506), .Q(n436) );
DFF_X1 \REGISTERS_reg[22][11] ( .D(n1568), .CK(net3506), .Q(n435) );
DFF_X1 \REGISTERS_reg[22][10] ( .D(n1590), .CK(net3506), .Q(n434) );
DFF_X1 \REGISTERS_reg[22][9] ( .D(n1612), .CK(net3506), .Q(n433) );
DFF_X1 \REGISTERS_reg[22][8] ( .D(n1634), .CK(net3506), .Q(n432) );
DFF_X1 \REGISTERS_reg[22][7] ( .D(n1656), .CK(net3506), .Q(n431) );
DFF_X1 \REGISTERS_reg[22][6] ( .D(n1678), .CK(net3506), .Q(n430) );
DFF_X1 \REGISTERS_reg[22][5] ( .D(n1700), .CK(net3506), .Q(n429) );
DFF_X1 \REGISTERS_reg[22][4] ( .D(n1722), .CK(net3506), .Q(n428) );
DFF_X1 \REGISTERS_reg[22][3] ( .D(n1744), .CK(net3506), .Q(n427) );
DFF_X1 \REGISTERS_reg[22][2] ( .D(n1766), .CK(net3506), .Q(n426) );
DFF_X1 \REGISTERS_reg[22][1] ( .D(n1788), .CK(net3506), .Q(n425) );
DFF_X1 \REGISTERS_reg[22][0] ( .D(n1810), .CK(net3506), .Q(n424) );
DFF_X1 \REGISTERS_reg[23][31] ( .D(n1094), .CK(net3511), .Q(n423) );
DFF_X1 \REGISTERS_reg[23][30] ( .D(n1150), .CK(net3511), .Q(n422) );
DFF_X1 \REGISTERS_reg[23][29] ( .D(n1172), .CK(net3511), .Q(n421) );
DFF_X1 \REGISTERS_reg[23][28] ( .D(n1194), .CK(net3511), .Q(n420) );
DFF_X1 \REGISTERS_reg[23][27] ( .D(n1216), .CK(net3511), .Q(n419) );
DFF_X1 \REGISTERS_reg[23][26] ( .D(n1238), .CK(net3511), .Q(n418) );
DFF_X1 \REGISTERS_reg[23][25] ( .D(n1260), .CK(net3511), .Q(n417) );
DFF_X1 \REGISTERS_reg[23][24] ( .D(n1282), .CK(net3511), .Q(n416) );
DFF_X1 \REGISTERS_reg[23][23] ( .D(n1304), .CK(net3511), .Q(n415) );
DFF_X1 \REGISTERS_reg[23][22] ( .D(n1326), .CK(net3511), .Q(n414) );
DFF_X1 \REGISTERS_reg[23][21] ( .D(n1348), .CK(net3511), .Q(n413) );
DFF_X1 \REGISTERS_reg[23][20] ( .D(n1370), .CK(net3511), .Q(n412) );
DFF_X1 \REGISTERS_reg[23][19] ( .D(n1392), .CK(net3511), .Q(n411) );
DFF_X1 \REGISTERS_reg[23][18] ( .D(n1414), .CK(net3511), .Q(n410) );
DFF_X1 \REGISTERS_reg[23][17] ( .D(n1436), .CK(net3511), .Q(n409) );
DFF_X1 \REGISTERS_reg[23][16] ( .D(n1458), .CK(net3511), .Q(n408) );
DFF_X1 \REGISTERS_reg[23][15] ( .D(n1480), .CK(net3511), .Q(n407) );
DFF_X1 \REGISTERS_reg[23][14] ( .D(n1502), .CK(net3511), .Q(n406) );
DFF_X1 \REGISTERS_reg[23][13] ( .D(n1524), .CK(net3511), .Q(n405) );
DFF_X1 \REGISTERS_reg[23][12] ( .D(n1546), .CK(net3511), .Q(n404) );
DFF_X1 \REGISTERS_reg[23][11] ( .D(n1568), .CK(net3511), .Q(n403) );
DFF_X1 \REGISTERS_reg[23][10] ( .D(n1590), .CK(net3511), .Q(n402) );
DFF_X1 \REGISTERS_reg[23][9] ( .D(n1612), .CK(net3511), .Q(n401) );
DFF_X1 \REGISTERS_reg[23][8] ( .D(n1634), .CK(net3511), .Q(n400) );
DFF_X1 \REGISTERS_reg[23][7] ( .D(n1656), .CK(net3511), .Q(n399) );
DFF_X1 \REGISTERS_reg[23][6] ( .D(n1678), .CK(net3511), .Q(n398) );
DFF_X1 \REGISTERS_reg[23][5] ( .D(n1700), .CK(net3511), .Q(n397) );
DFF_X1 \REGISTERS_reg[23][4] ( .D(n1722), .CK(net3511), .Q(n396) );
DFF_X1 \REGISTERS_reg[23][3] ( .D(n1744), .CK(net3511), .Q(n395) );
DFF_X1 \REGISTERS_reg[23][2] ( .D(n1766), .CK(net3511), .Q(n394) );
DFF_X1 \REGISTERS_reg[23][1] ( .D(n1788), .CK(net3511), .Q(n393) );
DFF_X1 \REGISTERS_reg[23][0] ( .D(n1810), .CK(net3511), .Q(n392) );
DFF_X1 \REGISTERS_reg[24][31] ( .D(n1094), .CK(net3516), .Q(n391) );
DFF_X1 \REGISTERS_reg[24][30] ( .D(n1150), .CK(net3516), .Q(n390) );
DFF_X1 \REGISTERS_reg[24][29] ( .D(n1172), .CK(net3516), .Q(n389) );
DFF_X1 \REGISTERS_reg[24][28] ( .D(n1194), .CK(net3516), .Q(n388) );
DFF_X1 \REGISTERS_reg[24][27] ( .D(n1216), .CK(net3516), .Q(n387) );
DFF_X1 \REGISTERS_reg[24][26] ( .D(n1238), .CK(net3516), .Q(n386) );
DFF_X1 \REGISTERS_reg[24][25] ( .D(n1260), .CK(net3516), .Q(n385) );
DFF_X1 \REGISTERS_reg[24][24] ( .D(n1282), .CK(net3516), .Q(n384) );
DFF_X1 \REGISTERS_reg[24][23] ( .D(n1304), .CK(net3516), .Q(n383) );
DFF_X1 \REGISTERS_reg[24][22] ( .D(n1326), .CK(net3516), .Q(n382) );
DFF_X1 \REGISTERS_reg[24][21] ( .D(n1348), .CK(net3516), .Q(n381) );
DFF_X1 \REGISTERS_reg[24][20] ( .D(n1370), .CK(net3516), .Q(n380) );
DFF_X1 \REGISTERS_reg[24][19] ( .D(n1392), .CK(net3516), .Q(n379) );
DFF_X1 \REGISTERS_reg[24][18] ( .D(n1414), .CK(net3516), .Q(n378) );
DFF_X1 \REGISTERS_reg[24][17] ( .D(n1436), .CK(net3516), .Q(n377) );
DFF_X1 \REGISTERS_reg[24][16] ( .D(n1458), .CK(net3516), .Q(n376) );
DFF_X1 \REGISTERS_reg[24][15] ( .D(n1480), .CK(net3516), .Q(n375) );
DFF_X1 \REGISTERS_reg[24][14] ( .D(n1502), .CK(net3516), .Q(n374) );
DFF_X1 \REGISTERS_reg[24][13] ( .D(n1524), .CK(net3516), .Q(n373) );
DFF_X1 \REGISTERS_reg[24][12] ( .D(n1546), .CK(net3516), .Q(n372) );
DFF_X1 \REGISTERS_reg[24][11] ( .D(n1568), .CK(net3516), .Q(n371) );
DFF_X1 \REGISTERS_reg[24][10] ( .D(n1590), .CK(net3516), .Q(n370) );
DFF_X1 \REGISTERS_reg[24][9] ( .D(n1612), .CK(net3516), .Q(n369) );
DFF_X1 \REGISTERS_reg[24][8] ( .D(n1634), .CK(net3516), .Q(n368) );
DFF_X1 \REGISTERS_reg[24][7] ( .D(n1656), .CK(net3516), .Q(n367) );
DFF_X1 \REGISTERS_reg[24][6] ( .D(n1678), .CK(net3516), .Q(n366) );
DFF_X1 \REGISTERS_reg[24][5] ( .D(n1700), .CK(net3516), .Q(n365) );
DFF_X1 \REGISTERS_reg[24][4] ( .D(n1722), .CK(net3516), .Q(n364) );
DFF_X1 \REGISTERS_reg[24][3] ( .D(n1744), .CK(net3516), .Q(n363) );
DFF_X1 \REGISTERS_reg[24][2] ( .D(n1766), .CK(net3516), .Q(n362) );
DFF_X1 \REGISTERS_reg[24][1] ( .D(n1788), .CK(net3516), .Q(n361) );
DFF_X1 \REGISTERS_reg[24][0] ( .D(n1810), .CK(net3516), .Q(n360) );
DFF_X1 \REGISTERS_reg[25][31] ( .D(n1094), .CK(net3521), .Q(n359) );
DFF_X1 \REGISTERS_reg[25][30] ( .D(n1150), .CK(net3521), .Q(n358) );
DFF_X1 \REGISTERS_reg[25][29] ( .D(n1172), .CK(net3521), .Q(n357) );
DFF_X1 \REGISTERS_reg[25][28] ( .D(n1194), .CK(net3521), .Q(n356) );
DFF_X1 \REGISTERS_reg[25][27] ( .D(n1216), .CK(net3521), .Q(n355) );
DFF_X1 \REGISTERS_reg[25][26] ( .D(n1238), .CK(net3521), .Q(n354) );
DFF_X1 \REGISTERS_reg[25][25] ( .D(n1260), .CK(net3521), .Q(n353) );
DFF_X1 \REGISTERS_reg[25][24] ( .D(n1282), .CK(net3521), .Q(n352) );
DFF_X1 \REGISTERS_reg[25][23] ( .D(n1304), .CK(net3521), .Q(n351) );
DFF_X1 \REGISTERS_reg[25][22] ( .D(n1326), .CK(net3521), .Q(n350) );
DFF_X1 \REGISTERS_reg[25][21] ( .D(n1348), .CK(net3521), .Q(n349) );
DFF_X1 \REGISTERS_reg[25][20] ( .D(n1370), .CK(net3521), .Q(n348) );
DFF_X1 \REGISTERS_reg[25][19] ( .D(n1392), .CK(net3521), .Q(n347) );
DFF_X1 \REGISTERS_reg[25][18] ( .D(n1414), .CK(net3521), .Q(n346) );
DFF_X1 \REGISTERS_reg[25][17] ( .D(n1436), .CK(net3521), .Q(n345) );
DFF_X1 \REGISTERS_reg[25][16] ( .D(n1458), .CK(net3521), .Q(n344) );
DFF_X1 \REGISTERS_reg[25][15] ( .D(n1480), .CK(net3521), .Q(n343) );
DFF_X1 \REGISTERS_reg[25][14] ( .D(n1502), .CK(net3521), .Q(n342) );
DFF_X1 \REGISTERS_reg[25][13] ( .D(n1524), .CK(net3521), .Q(n341) );
DFF_X1 \REGISTERS_reg[25][12] ( .D(n1546), .CK(net3521), .Q(n340) );
DFF_X1 \REGISTERS_reg[25][11] ( .D(n1568), .CK(net3521), .Q(n339) );
DFF_X1 \REGISTERS_reg[25][10] ( .D(n1590), .CK(net3521), .Q(n338) );
DFF_X1 \REGISTERS_reg[25][9] ( .D(n1612), .CK(net3521), .Q(n337) );
DFF_X1 \REGISTERS_reg[25][8] ( .D(n1634), .CK(net3521), .Q(n336) );
DFF_X1 \REGISTERS_reg[25][7] ( .D(n1656), .CK(net3521), .Q(n335) );
DFF_X1 \REGISTERS_reg[25][6] ( .D(n1678), .CK(net3521), .Q(n334) );
DFF_X1 \REGISTERS_reg[25][5] ( .D(n1700), .CK(net3521), .Q(n333) );
DFF_X1 \REGISTERS_reg[25][4] ( .D(n1722), .CK(net3521), .Q(n332) );
DFF_X1 \REGISTERS_reg[25][3] ( .D(n1744), .CK(net3521), .Q(n331) );
DFF_X1 \REGISTERS_reg[25][2] ( .D(n1766), .CK(net3521), .Q(n330) );
DFF_X1 \REGISTERS_reg[25][1] ( .D(n1788), .CK(net3521), .Q(n329) );
DFF_X1 \REGISTERS_reg[25][0] ( .D(n1810), .CK(net3521), .Q(n328) );
DFF_X1 \REGISTERS_reg[26][31] ( .D(n1094), .CK(net3526), .Q(n327) );
DFF_X1 \REGISTERS_reg[26][30] ( .D(n1150), .CK(net3526), .Q(n326) );
DFF_X1 \REGISTERS_reg[26][29] ( .D(n1172), .CK(net3526), .Q(n325) );
DFF_X1 \REGISTERS_reg[26][28] ( .D(n1194), .CK(net3526), .Q(n324) );
DFF_X1 \REGISTERS_reg[26][27] ( .D(n1216), .CK(net3526), .Q(n323) );
DFF_X1 \REGISTERS_reg[26][26] ( .D(n1238), .CK(net3526), .Q(n322) );
DFF_X1 \REGISTERS_reg[26][25] ( .D(n1260), .CK(net3526), .Q(n321) );
DFF_X1 \REGISTERS_reg[26][24] ( .D(n1282), .CK(net3526), .Q(n320) );
DFF_X1 \REGISTERS_reg[26][23] ( .D(n1304), .CK(net3526), .Q(n319) );
DFF_X1 \REGISTERS_reg[26][22] ( .D(n1326), .CK(net3526), .Q(n318) );
DFF_X1 \REGISTERS_reg[26][21] ( .D(n1348), .CK(net3526), .Q(n317) );
DFF_X1 \REGISTERS_reg[26][20] ( .D(n1370), .CK(net3526), .Q(n316) );
DFF_X1 \REGISTERS_reg[26][19] ( .D(n1392), .CK(net3526), .Q(n315) );
DFF_X1 \REGISTERS_reg[26][18] ( .D(n1414), .CK(net3526), .Q(n314) );
DFF_X1 \REGISTERS_reg[26][17] ( .D(n1436), .CK(net3526), .Q(n313) );
DFF_X1 \REGISTERS_reg[26][16] ( .D(n1458), .CK(net3526), .Q(n312) );
DFF_X1 \REGISTERS_reg[26][15] ( .D(n1480), .CK(net3526), .Q(n311) );
DFF_X1 \REGISTERS_reg[26][14] ( .D(n1502), .CK(net3526), .Q(n310) );
DFF_X1 \REGISTERS_reg[26][13] ( .D(n1524), .CK(net3526), .Q(n309) );
DFF_X1 \REGISTERS_reg[26][12] ( .D(n1546), .CK(net3526), .Q(n308) );
DFF_X1 \REGISTERS_reg[26][11] ( .D(n1568), .CK(net3526), .Q(n307) );
DFF_X1 \REGISTERS_reg[26][10] ( .D(n1590), .CK(net3526), .Q(n306) );
DFF_X1 \REGISTERS_reg[26][9] ( .D(n1612), .CK(net3526), .Q(n305) );
DFF_X1 \REGISTERS_reg[26][8] ( .D(n1634), .CK(net3526), .Q(n304) );
DFF_X1 \REGISTERS_reg[26][7] ( .D(n1656), .CK(net3526), .Q(n303) );
DFF_X1 \REGISTERS_reg[26][6] ( .D(n1678), .CK(net3526), .Q(n302) );
DFF_X1 \REGISTERS_reg[26][5] ( .D(n1700), .CK(net3526), .Q(n301) );
DFF_X1 \REGISTERS_reg[26][4] ( .D(n1722), .CK(net3526), .Q(n300) );
DFF_X1 \REGISTERS_reg[26][3] ( .D(n1744), .CK(net3526), .Q(n299) );
DFF_X1 \REGISTERS_reg[26][2] ( .D(n1766), .CK(net3526), .Q(n298) );
DFF_X1 \REGISTERS_reg[26][1] ( .D(n1788), .CK(net3526), .Q(n297) );
DFF_X1 \REGISTERS_reg[26][0] ( .D(n1810), .CK(net3526), .Q(n296) );
DFF_X1 \REGISTERS_reg[27][31] ( .D(n1094), .CK(net3531), .Q(n295) );
DFF_X1 \REGISTERS_reg[27][30] ( .D(n1150), .CK(net3531), .Q(n294) );
DFF_X1 \REGISTERS_reg[27][29] ( .D(n1172), .CK(net3531), .Q(n293) );
DFF_X1 \REGISTERS_reg[27][28] ( .D(n1194), .CK(net3531), .Q(n292) );
DFF_X1 \REGISTERS_reg[27][27] ( .D(n1216), .CK(net3531), .Q(n291) );
DFF_X1 \REGISTERS_reg[27][26] ( .D(n1238), .CK(net3531), .Q(n290) );
DFF_X1 \REGISTERS_reg[27][25] ( .D(n1260), .CK(net3531), .Q(n289) );
DFF_X1 \REGISTERS_reg[27][24] ( .D(n1282), .CK(net3531), .Q(n288) );
DFF_X1 \REGISTERS_reg[27][23] ( .D(n1304), .CK(net3531), .Q(n287) );
DFF_X1 \REGISTERS_reg[27][22] ( .D(n1326), .CK(net3531), .Q(n286) );
DFF_X1 \REGISTERS_reg[27][21] ( .D(n1348), .CK(net3531), .Q(n285) );
DFF_X1 \REGISTERS_reg[27][20] ( .D(n1370), .CK(net3531), .Q(n284) );
DFF_X1 \REGISTERS_reg[27][19] ( .D(n1392), .CK(net3531), .Q(n283) );
DFF_X1 \REGISTERS_reg[27][18] ( .D(n1414), .CK(net3531), .Q(n282) );
DFF_X1 \REGISTERS_reg[27][17] ( .D(n1436), .CK(net3531), .Q(n281) );
DFF_X1 \REGISTERS_reg[27][16] ( .D(n1458), .CK(net3531), .Q(n280) );
DFF_X1 \REGISTERS_reg[27][15] ( .D(n1480), .CK(net3531), .Q(n279) );
DFF_X1 \REGISTERS_reg[27][14] ( .D(n1502), .CK(net3531), .Q(n278) );
DFF_X1 \REGISTERS_reg[27][13] ( .D(n1524), .CK(net3531), .Q(n277) );
DFF_X1 \REGISTERS_reg[27][12] ( .D(n1546), .CK(net3531), .Q(n276) );
DFF_X1 \REGISTERS_reg[27][11] ( .D(n1568), .CK(net3531), .Q(n275) );
DFF_X1 \REGISTERS_reg[27][10] ( .D(n1590), .CK(net3531), .Q(n274) );
DFF_X1 \REGISTERS_reg[27][9] ( .D(n1612), .CK(net3531), .Q(n273) );
DFF_X1 \REGISTERS_reg[27][8] ( .D(n1634), .CK(net3531), .Q(n272) );
DFF_X1 \REGISTERS_reg[27][7] ( .D(n1656), .CK(net3531), .Q(n271) );
DFF_X1 \REGISTERS_reg[27][6] ( .D(n1678), .CK(net3531), .Q(n270) );
DFF_X1 \REGISTERS_reg[27][5] ( .D(n1700), .CK(net3531), .Q(n269) );
DFF_X1 \REGISTERS_reg[27][4] ( .D(n1722), .CK(net3531), .Q(n268) );
DFF_X1 \REGISTERS_reg[27][3] ( .D(n1744), .CK(net3531), .Q(n267) );
DFF_X1 \REGISTERS_reg[27][2] ( .D(n1766), .CK(net3531), .Q(n266) );
DFF_X1 \REGISTERS_reg[27][1] ( .D(n1788), .CK(net3531), .Q(n265) );
DFF_X1 \REGISTERS_reg[27][0] ( .D(n1810), .CK(net3531), .Q(n264) );
DFF_X1 \REGISTERS_reg[28][31] ( .D(n1094), .CK(net3536), .Q(n263) );
DFF_X1 \REGISTERS_reg[28][30] ( .D(n1150), .CK(net3536), .Q(n262) );
DFF_X1 \REGISTERS_reg[28][29] ( .D(n1172), .CK(net3536), .Q(n261) );
DFF_X1 \REGISTERS_reg[28][28] ( .D(n1194), .CK(net3536), .Q(n260) );
DFF_X1 \REGISTERS_reg[28][27] ( .D(n1216), .CK(net3536), .Q(n259) );
DFF_X1 \REGISTERS_reg[28][26] ( .D(n1238), .CK(net3536), .Q(n258) );
DFF_X1 \REGISTERS_reg[28][25] ( .D(n1260), .CK(net3536), .Q(n257) );
DFF_X1 \REGISTERS_reg[28][24] ( .D(n1282), .CK(net3536), .Q(n256) );
DFF_X1 \REGISTERS_reg[28][23] ( .D(n1304), .CK(net3536), .Q(n255) );
DFF_X1 \REGISTERS_reg[28][22] ( .D(n1326), .CK(net3536), .Q(n254) );
DFF_X1 \REGISTERS_reg[28][21] ( .D(n1348), .CK(net3536), .Q(n253) );
DFF_X1 \REGISTERS_reg[28][20] ( .D(n1370), .CK(net3536), .Q(n252) );
DFF_X1 \REGISTERS_reg[28][19] ( .D(n1392), .CK(net3536), .Q(n251) );
DFF_X1 \REGISTERS_reg[28][18] ( .D(n1414), .CK(net3536), .Q(n250) );
DFF_X1 \REGISTERS_reg[28][17] ( .D(n1436), .CK(net3536), .Q(n249) );
DFF_X1 \REGISTERS_reg[28][16] ( .D(n1458), .CK(net3536), .Q(n248) );
DFF_X1 \REGISTERS_reg[28][15] ( .D(n1480), .CK(net3536), .Q(n247) );
DFF_X1 \REGISTERS_reg[28][14] ( .D(n1502), .CK(net3536), .Q(n246) );
DFF_X1 \REGISTERS_reg[28][13] ( .D(n1524), .CK(net3536), .Q(n245) );
DFF_X1 \REGISTERS_reg[28][12] ( .D(n1546), .CK(net3536), .Q(n244) );
DFF_X1 \REGISTERS_reg[28][11] ( .D(n1568), .CK(net3536), .Q(n243) );
DFF_X1 \REGISTERS_reg[28][10] ( .D(n1590), .CK(net3536), .Q(n242) );
DFF_X1 \REGISTERS_reg[28][9] ( .D(n1612), .CK(net3536), .Q(n241) );
DFF_X1 \REGISTERS_reg[28][8] ( .D(n1634), .CK(net3536), .Q(n240) );
DFF_X1 \REGISTERS_reg[28][7] ( .D(n1656), .CK(net3536), .Q(n239) );
DFF_X1 \REGISTERS_reg[28][6] ( .D(n1678), .CK(net3536), .Q(n238) );
DFF_X1 \REGISTERS_reg[28][5] ( .D(n1700), .CK(net3536), .Q(n237) );
DFF_X1 \REGISTERS_reg[28][4] ( .D(n1722), .CK(net3536), .Q(n236) );
DFF_X1 \REGISTERS_reg[28][3] ( .D(n1744), .CK(net3536), .Q(n235) );
DFF_X1 \REGISTERS_reg[28][2] ( .D(n1766), .CK(net3536), .Q(n234) );
DFF_X1 \REGISTERS_reg[28][1] ( .D(n1788), .CK(net3536), .Q(n233) );
DFF_X1 \REGISTERS_reg[28][0] ( .D(n1810), .CK(net3536), .Q(n232) );
DFF_X1 \REGISTERS_reg[29][31] ( .D(n1094), .CK(net3541), .Q(n231) );
DFF_X1 \REGISTERS_reg[29][30] ( .D(n1150), .CK(net3541), .Q(n230) );
DFF_X1 \REGISTERS_reg[29][29] ( .D(n1172), .CK(net3541), .Q(n229) );
DFF_X1 \REGISTERS_reg[29][28] ( .D(n1194), .CK(net3541), .Q(n228) );
DFF_X1 \REGISTERS_reg[29][27] ( .D(n1216), .CK(net3541), .Q(n227) );
DFF_X1 \REGISTERS_reg[29][26] ( .D(n1238), .CK(net3541), .Q(n226) );
DFF_X1 \REGISTERS_reg[29][25] ( .D(n1260), .CK(net3541), .Q(n225) );
DFF_X1 \REGISTERS_reg[29][24] ( .D(n1282), .CK(net3541), .Q(n224) );
DFF_X1 \REGISTERS_reg[29][23] ( .D(n1304), .CK(net3541), .Q(n223) );
DFF_X1 \REGISTERS_reg[29][22] ( .D(n1326), .CK(net3541), .Q(n222) );
DFF_X1 \REGISTERS_reg[29][21] ( .D(n1348), .CK(net3541), .Q(n221) );
DFF_X1 \REGISTERS_reg[29][20] ( .D(n1370), .CK(net3541), .Q(n220) );
DFF_X1 \REGISTERS_reg[29][19] ( .D(n1392), .CK(net3541), .Q(n219) );
DFF_X1 \REGISTERS_reg[29][18] ( .D(n1414), .CK(net3541), .Q(n218) );
DFF_X1 \REGISTERS_reg[29][17] ( .D(n1436), .CK(net3541), .Q(n217) );
DFF_X1 \REGISTERS_reg[29][16] ( .D(n1458), .CK(net3541), .Q(n216) );
DFF_X1 \REGISTERS_reg[29][15] ( .D(n1480), .CK(net3541), .Q(n215) );
DFF_X1 \REGISTERS_reg[29][14] ( .D(n1502), .CK(net3541), .Q(n214) );
DFF_X1 \REGISTERS_reg[29][13] ( .D(n1524), .CK(net3541), .Q(n213) );
DFF_X1 \REGISTERS_reg[29][12] ( .D(n1546), .CK(net3541), .Q(n212) );
DFF_X1 \REGISTERS_reg[29][11] ( .D(n1568), .CK(net3541), .Q(n211) );
DFF_X1 \REGISTERS_reg[29][10] ( .D(n1590), .CK(net3541), .Q(n210) );
DFF_X1 \REGISTERS_reg[29][9] ( .D(n1612), .CK(net3541), .Q(n209) );
DFF_X1 \REGISTERS_reg[29][8] ( .D(n1634), .CK(net3541), .Q(n208) );
DFF_X1 \REGISTERS_reg[29][7] ( .D(n1656), .CK(net3541), .Q(n207) );
DFF_X1 \REGISTERS_reg[29][6] ( .D(n1678), .CK(net3541), .Q(n206) );
DFF_X1 \REGISTERS_reg[29][5] ( .D(n1700), .CK(net3541), .Q(n205) );
DFF_X1 \REGISTERS_reg[29][4] ( .D(n1722), .CK(net3541), .Q(n204) );
DFF_X1 \REGISTERS_reg[29][3] ( .D(n1744), .CK(net3541), .Q(n203) );
DFF_X1 \REGISTERS_reg[29][2] ( .D(n1766), .CK(net3541), .Q(n202) );
DFF_X1 \REGISTERS_reg[29][1] ( .D(n1788), .CK(net3541), .Q(n201) );
DFF_X1 \REGISTERS_reg[29][0] ( .D(n1810), .CK(net3541), .Q(n200) );
DFF_X1 \REGISTERS_reg[30][31] ( .D(n1094), .CK(net3546), .Q(n199) );
DFF_X1 \REGISTERS_reg[30][30] ( .D(n1150), .CK(net3546), .Q(n198) );
DFF_X1 \REGISTERS_reg[30][29] ( .D(n1172), .CK(net3546), .Q(n197) );
DFF_X1 \REGISTERS_reg[30][28] ( .D(n1194), .CK(net3546), .Q(n196) );
DFF_X1 \REGISTERS_reg[30][27] ( .D(n1216), .CK(net3546), .Q(n195) );
DFF_X1 \REGISTERS_reg[30][26] ( .D(n1238), .CK(net3546), .Q(n194) );
DFF_X1 \REGISTERS_reg[30][25] ( .D(n1260), .CK(net3546), .Q(n193) );
DFF_X1 \REGISTERS_reg[30][24] ( .D(n1282), .CK(net3546), .Q(n192) );
DFF_X1 \REGISTERS_reg[30][23] ( .D(n1304), .CK(net3546), .Q(n191) );
DFF_X1 \REGISTERS_reg[30][22] ( .D(n1326), .CK(net3546), .Q(n190) );
DFF_X1 \REGISTERS_reg[30][21] ( .D(n1348), .CK(net3546), .Q(n189) );
DFF_X1 \REGISTERS_reg[30][20] ( .D(n1370), .CK(net3546), .Q(n188) );
DFF_X1 \REGISTERS_reg[30][19] ( .D(n1392), .CK(net3546), .Q(n187) );
DFF_X1 \REGISTERS_reg[30][18] ( .D(n1414), .CK(net3546), .Q(n186) );
DFF_X1 \REGISTERS_reg[30][17] ( .D(n1436), .CK(net3546), .Q(n185) );
DFF_X1 \REGISTERS_reg[30][16] ( .D(n1458), .CK(net3546), .Q(n184) );
DFF_X1 \REGISTERS_reg[30][15] ( .D(n1480), .CK(net3546), .Q(n183) );
DFF_X1 \REGISTERS_reg[30][14] ( .D(n1502), .CK(net3546), .Q(n182) );
DFF_X1 \REGISTERS_reg[30][13] ( .D(n1524), .CK(net3546), .Q(n181) );
DFF_X1 \REGISTERS_reg[30][12] ( .D(n1546), .CK(net3546), .Q(n180) );
DFF_X1 \REGISTERS_reg[30][11] ( .D(n1568), .CK(net3546), .Q(n179) );
DFF_X1 \REGISTERS_reg[30][10] ( .D(n1590), .CK(net3546), .Q(n178) );
DFF_X1 \REGISTERS_reg[30][9] ( .D(n1612), .CK(net3546), .Q(n175) );
DFF_X1 \REGISTERS_reg[30][8] ( .D(n1634), .CK(net3546), .Q(n164) );
DFF_X1 \REGISTERS_reg[30][7] ( .D(n1656), .CK(net3546), .Q(n153) );
DFF_X1 \REGISTERS_reg[30][6] ( .D(n1678), .CK(net3546), .Q(n142) );
DFF_X1 \REGISTERS_reg[30][5] ( .D(n1700), .CK(net3546), .Q(n131) );
DFF_X1 \REGISTERS_reg[30][4] ( .D(n1722), .CK(net3546), .Q(n120) );
DFF_X1 \REGISTERS_reg[30][3] ( .D(n1744), .CK(net3546), .Q(n109) );
DFF_X1 \REGISTERS_reg[30][2] ( .D(n1766), .CK(net3546), .Q(n97) );
DFF_X1 \REGISTERS_reg[30][1] ( .D(n1788), .CK(net3546), .Q(n75) );
DFF_X1 \REGISTERS_reg[30][0] ( .D(n1810), .CK(net3546), .Q(n53) );
DFF_X1 \REGISTERS_reg[31][31] ( .D(n1094), .CK(net3551), .Q(n1089) );
DFF_X1 \OUT2_reg[31] ( .D(N4616), .CK(net3391), .Q(OUT2[31]) );
DFF_X1 \REGISTERS_reg[31][30] ( .D(n1150), .CK(net3551), .Q(n1068) );
DFF_X1 \OUT2_reg[30] ( .D(N4614), .CK(net3391), .Q(OUT2[30]) );
DFF_X1 \REGISTERS_reg[31][29] ( .D(n1172), .CK(net3551), .Q(n1047) );
DFF_X1 \OUT2_reg[29] ( .D(N4612), .CK(net3391), .Q(OUT2[29]) );
DFF_X1 \REGISTERS_reg[31][28] ( .D(n1194), .CK(net3551), .Q(n1026) );
DFF_X1 \OUT2_reg[28] ( .D(N4610), .CK(net3391), .Q(OUT2[28]) );
DFF_X1 \REGISTERS_reg[31][27] ( .D(n1216), .CK(net3551), .Q(n1005) );
DFF_X1 \OUT2_reg[27] ( .D(N4608), .CK(net3391), .Q(OUT2[27]) );
DFF_X1 \REGISTERS_reg[31][26] ( .D(n1238), .CK(net3551), .Q(n984) );
DFF_X1 \OUT2_reg[26] ( .D(N4606), .CK(net3391), .Q(OUT2[26]) );
DFF_X1 \REGISTERS_reg[31][25] ( .D(n1260), .CK(net3551), .Q(n963) );
DFF_X1 \OUT2_reg[25] ( .D(N4604), .CK(net3391), .Q(OUT2[25]) );
DFF_X1 \REGISTERS_reg[31][24] ( .D(n1282), .CK(net3551), .Q(n942) );
DFF_X1 \OUT2_reg[24] ( .D(N4602), .CK(net3391), .Q(OUT2[24]) );
DFF_X1 \REGISTERS_reg[31][23] ( .D(n1304), .CK(net3551), .Q(n921) );
DFF_X1 \OUT2_reg[23] ( .D(N4600), .CK(net3391), .Q(OUT2[23]) );
DFF_X1 \REGISTERS_reg[31][22] ( .D(n1326), .CK(net3551), .Q(n900) );
DFF_X1 \OUT2_reg[22] ( .D(N4598), .CK(net3391), .Q(OUT2[22]) );
DFF_X1 \REGISTERS_reg[31][21] ( .D(n1348), .CK(net3551), .Q(n879) );
DFF_X1 \OUT2_reg[21] ( .D(N4596), .CK(net3391), .Q(OUT2[21]) );
DFF_X1 \REGISTERS_reg[31][20] ( .D(n1370), .CK(net3551), .Q(n858) );
DFF_X1 \OUT2_reg[20] ( .D(N4594), .CK(net3391), .Q(OUT2[20]) );
DFF_X1 \REGISTERS_reg[31][19] ( .D(n1392), .CK(net3551), .Q(n837) );
DFF_X1 \OUT2_reg[19] ( .D(N4592), .CK(net3391), .Q(OUT2[19]) );
DFF_X1 \REGISTERS_reg[31][18] ( .D(n1414), .CK(net3551), .Q(n816) );
DFF_X1 \OUT2_reg[18] ( .D(N4590), .CK(net3391), .Q(OUT2[18]) );
DFF_X1 \REGISTERS_reg[31][17] ( .D(n1436), .CK(net3551), .Q(n795) );
DFF_X1 \OUT2_reg[17] ( .D(N4588), .CK(net3391), .Q(OUT2[17]) );
DFF_X1 \REGISTERS_reg[31][16] ( .D(n1458), .CK(net3551), .Q(n774) );
DFF_X1 \OUT2_reg[16] ( .D(N4586), .CK(net3391), .Q(OUT2[16]) );
DFF_X1 \REGISTERS_reg[31][15] ( .D(n1480), .CK(net3551), .Q(n753) );
DFF_X1 \OUT2_reg[15] ( .D(N4584), .CK(net3391), .Q(OUT2[15]) );
DFF_X1 \REGISTERS_reg[31][14] ( .D(n1502), .CK(net3551), .Q(n732) );
DFF_X1 \OUT2_reg[14] ( .D(N4582), .CK(net3391), .Q(OUT2[14]) );
DFF_X1 \REGISTERS_reg[31][13] ( .D(n1524), .CK(net3551), .Q(n711) );
DFF_X1 \OUT2_reg[13] ( .D(N4580), .CK(net3391), .Q(OUT2[13]) );
DFF_X1 \REGISTERS_reg[31][12] ( .D(n1546), .CK(net3551), .Q(n690) );
DFF_X1 \OUT2_reg[12] ( .D(N4578), .CK(net3391), .Q(OUT2[12]) );
DFF_X1 \REGISTERS_reg[31][11] ( .D(n1568), .CK(net3551), .Q(n669) );
DFF_X1 \OUT2_reg[11] ( .D(N4576), .CK(net3391), .Q(OUT2[11]) );
DFF_X1 \REGISTERS_reg[31][10] ( .D(n1590), .CK(net3551), .Q(n648) );
DFF_X1 \OUT2_reg[10] ( .D(N4574), .CK(net3391), .Q(OUT2[10]) );
DFF_X1 \REGISTERS_reg[31][9] ( .D(n1612), .CK(net3551), .Q(n627) );
DFF_X1 \OUT2_reg[9] ( .D(N4572), .CK(net3391), .Q(OUT2[9]) );
DFF_X1 \REGISTERS_reg[31][8] ( .D(n1634), .CK(net3551), .Q(n606) );
DFF_X1 \OUT2_reg[8] ( .D(N4570), .CK(net3391), .Q(OUT2[8]) );
DFF_X1 \REGISTERS_reg[31][7] ( .D(n1656), .CK(net3551), .Q(n585) );
DFF_X1 \OUT2_reg[7] ( .D(N4568), .CK(net3391), .Q(OUT2[7]) );
DFF_X1 \REGISTERS_reg[31][6] ( .D(n1678), .CK(net3551), .Q(n564) );
DFF_X1 \OUT2_reg[6] ( .D(N4566), .CK(net3391), .Q(OUT2[6]) );
DFF_X1 \REGISTERS_reg[31][5] ( .D(n1700), .CK(net3551), .Q(n543) );
DFF_X1 \OUT2_reg[5] ( .D(N4564), .CK(net3391), .Q(OUT2[5]) );
DFF_X1 \REGISTERS_reg[31][4] ( .D(n1722), .CK(net3551), .Q(n522) );
DFF_X1 \OUT2_reg[4] ( .D(N4562), .CK(net3391), .Q(OUT2[4]) );
DFF_X1 \REGISTERS_reg[31][3] ( .D(n1744), .CK(net3551), .Q(n501) );
DFF_X1 \OUT2_reg[3] ( .D(N4560), .CK(net3391), .Q(OUT2[3]) );
DFF_X1 \REGISTERS_reg[31][2] ( .D(n1766), .CK(net3551), .Q(n480) );
DFF_X1 \OUT2_reg[2] ( .D(N4558), .CK(net3391), .Q(OUT2[2]) );
DFF_X1 \REGISTERS_reg[31][1] ( .D(n1788), .CK(net3551), .Q(n459) );
DFF_X1 \OUT2_reg[1] ( .D(N4556), .CK(net3391), .Q(OUT2[1]) );
DFF_X1 \REGISTERS_reg[31][0] ( .D(n1810), .CK(net3551), .Q(n438) );
DFF_X1 \OUT2_reg[0] ( .D(N4554), .CK(net3391), .Q(OUT2[0]) );
DFF_X1 \OUT1_reg[31] ( .D(N4552), .CK(net3556), .Q(OUT1[31]) );
DFF_X1 \OUT1_reg[30] ( .D(N4550), .CK(net3556), .Q(OUT1[30]) );
DFF_X1 \OUT1_reg[29] ( .D(N4548), .CK(net3556), .Q(OUT1[29]) );
DFF_X1 \OUT1_reg[28] ( .D(N4546), .CK(net3556), .Q(OUT1[28]) );
DFF_X1 \OUT1_reg[27] ( .D(N4544), .CK(net3556), .Q(OUT1[27]) );
DFF_X1 \OUT1_reg[26] ( .D(N4542), .CK(net3556), .Q(OUT1[26]) );
DFF_X1 \OUT1_reg[25] ( .D(N4540), .CK(net3556), .Q(OUT1[25]) );
DFF_X1 \OUT1_reg[24] ( .D(N4538), .CK(net3556), .Q(OUT1[24]) );
DFF_X1 \OUT1_reg[23] ( .D(N4536), .CK(net3556), .Q(OUT1[23]) );
DFF_X1 \OUT1_reg[22] ( .D(N4534), .CK(net3556), .Q(OUT1[22]) );
DFF_X1 \OUT1_reg[21] ( .D(N4532), .CK(net3556), .Q(OUT1[21]) );
DFF_X1 \OUT1_reg[20] ( .D(N4530), .CK(net3556), .Q(OUT1[20]) );
DFF_X1 \OUT1_reg[19] ( .D(N4528), .CK(net3556), .Q(OUT1[19]) );
DFF_X1 \OUT1_reg[18] ( .D(N4526), .CK(net3556), .Q(OUT1[18]) );
DFF_X1 \OUT1_reg[17] ( .D(N4524), .CK(net3556), .Q(OUT1[17]) );
DFF_X1 \OUT1_reg[16] ( .D(N4522), .CK(net3556), .Q(OUT1[16]) );
DFF_X1 \OUT1_reg[15] ( .D(N4520), .CK(net3556), .Q(OUT1[15]) );
DFF_X1 \OUT1_reg[14] ( .D(N4518), .CK(net3556), .Q(OUT1[14]) );
DFF_X1 \OUT1_reg[13] ( .D(N4516), .CK(net3556), .Q(OUT1[13]) );
DFF_X1 \OUT1_reg[12] ( .D(N4514), .CK(net3556), .Q(OUT1[12]) );
DFF_X1 \OUT1_reg[11] ( .D(N4512), .CK(net3556), .Q(OUT1[11]) );
DFF_X1 \OUT1_reg[10] ( .D(N4510), .CK(net3556), .Q(OUT1[10]) );
DFF_X1 \OUT1_reg[9] ( .D(N4508), .CK(net3556), .Q(OUT1[9]) );
DFF_X1 \OUT1_reg[8] ( .D(N4506), .CK(net3556), .Q(OUT1[8]) );
DFF_X1 \OUT1_reg[7] ( .D(N4504), .CK(net3556), .Q(OUT1[7]) );
DFF_X1 \OUT1_reg[6] ( .D(N4502), .CK(net3556), .Q(OUT1[6]) );
DFF_X1 \OUT1_reg[5] ( .D(N4500), .CK(net3556), .Q(OUT1[5]) );
DFF_X1 \OUT1_reg[4] ( .D(N4498), .CK(net3556), .Q(OUT1[4]) );
DFF_X1 \OUT1_reg[3] ( .D(N4496), .CK(net3556), .Q(OUT1[3]) );
DFF_X1 \OUT1_reg[2] ( .D(N4494), .CK(net3556), .Q(OUT1[2]) );
DFF_X1 \OUT1_reg[1] ( .D(N4492), .CK(net3556), .Q(OUT1[1]) );
DFF_X1 \OUT1_reg[0] ( .D(N4490), .CK(net3556), .Q(OUT1[0]) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_0 clk_gate_OUT2_reg ( .CLK(Clk), .EN(N4615),
.ENCLK(net3391) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_33 \clk_gate_REGISTERS_reg[0] ( .CLK(Clk),
.EN(N4487), .ENCLK(net3396) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_32 \clk_gate_REGISTERS_reg[1] ( .CLK(Clk),
.EN(N4423), .ENCLK(net3401) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_31 \clk_gate_REGISTERS_reg[2] ( .CLK(Clk),
.EN(N4359), .ENCLK(net3406) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_30 \clk_gate_REGISTERS_reg[3] ( .CLK(Clk),
.EN(N4295), .ENCLK(net3411) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_29 \clk_gate_REGISTERS_reg[4] ( .CLK(Clk),
.EN(N4231), .ENCLK(net3416) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_28 \clk_gate_REGISTERS_reg[5] ( .CLK(Clk),
.EN(N4167), .ENCLK(net3421) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_27 \clk_gate_REGISTERS_reg[6] ( .CLK(Clk),
.EN(N4103), .ENCLK(net3426) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_26 \clk_gate_REGISTERS_reg[7] ( .CLK(Clk),
.EN(N4039), .ENCLK(net3431) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_25 \clk_gate_REGISTERS_reg[8] ( .CLK(Clk),
.EN(N3975), .ENCLK(net3436) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_24 \clk_gate_REGISTERS_reg[9] ( .CLK(Clk),
.EN(N3911), .ENCLK(net3441) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_23 \clk_gate_REGISTERS_reg[10] ( .CLK(Clk),
.EN(N3847), .ENCLK(net3446) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_22 \clk_gate_REGISTERS_reg[11] ( .CLK(Clk),
.EN(N3783), .ENCLK(net3451) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_21 \clk_gate_REGISTERS_reg[12] ( .CLK(Clk),
.EN(N3719), .ENCLK(net3456) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_20 \clk_gate_REGISTERS_reg[13] ( .CLK(Clk),
.EN(N3655), .ENCLK(net3461) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_19 \clk_gate_REGISTERS_reg[14] ( .CLK(Clk),
.EN(N3591), .ENCLK(net3466) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_18 \clk_gate_REGISTERS_reg[15] ( .CLK(Clk),
.EN(N3527), .ENCLK(net3471) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_17 \clk_gate_REGISTERS_reg[16] ( .CLK(Clk),
.EN(N3463), .ENCLK(net3476) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_16 \clk_gate_REGISTERS_reg[17] ( .CLK(Clk),
.EN(N3399), .ENCLK(net3481) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_15 \clk_gate_REGISTERS_reg[18] ( .CLK(Clk),
.EN(N3335), .ENCLK(net3486) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_14 \clk_gate_REGISTERS_reg[19] ( .CLK(Clk),
.EN(N3271), .ENCLK(net3491) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_13 \clk_gate_REGISTERS_reg[20] ( .CLK(Clk),
.EN(N3207), .ENCLK(net3496) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_12 \clk_gate_REGISTERS_reg[21] ( .CLK(Clk),
.EN(N3143), .ENCLK(net3501) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_11 \clk_gate_REGISTERS_reg[22] ( .CLK(Clk),
.EN(N3079), .ENCLK(net3506) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_10 \clk_gate_REGISTERS_reg[23] ( .CLK(Clk),
.EN(N3015), .ENCLK(net3511) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_9 \clk_gate_REGISTERS_reg[24] ( .CLK(Clk),
.EN(N2951), .ENCLK(net3516) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_8 \clk_gate_REGISTERS_reg[25] ( .CLK(Clk),
.EN(N2887), .ENCLK(net3521) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_7 \clk_gate_REGISTERS_reg[26] ( .CLK(Clk),
.EN(N2823), .ENCLK(net3526) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_6 \clk_gate_REGISTERS_reg[27] ( .CLK(Clk),
.EN(N2759), .ENCLK(net3531) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_5 \clk_gate_REGISTERS_reg[28] ( .CLK(Clk),
.EN(N2695), .ENCLK(net3536) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_4 \clk_gate_REGISTERS_reg[29] ( .CLK(Clk),
.EN(N2631), .ENCLK(net3541) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_3 \clk_gate_REGISTERS_reg[30] ( .CLK(Clk),
.EN(N2567), .ENCLK(net3546) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_2 \clk_gate_REGISTERS_reg[31] ( .CLK(Clk),
.EN(N2503), .ENCLK(net3551) );
SNPS_CLOCK_GATE_HIGH_dlx_regfile_1 clk_gate_OUT1_reg ( .CLK(Clk), .EN(N4615),
.ENCLK(net3556) );
INV_X1 U3 ( .A(N4487), .ZN(n51) );
INV_X1 U4 ( .A(N4487), .ZN(n47) );
INV_X2 U5 ( .A(N4487), .ZN(n49) );
NAND2_X2 U6 ( .A1(n49), .A2(n1868), .ZN(n1867) );
NAND2_X2 U7 ( .A1(n47), .A2(n1103), .ZN(n1102) );
NAND3_X2 U8 ( .A1(n1819), .A2(n1820), .A3(n1821), .ZN(n1103) );
NAND3_X2 U9 ( .A1(n1819), .A2(n2553), .A3(n2554), .ZN(n1868) );
NAND2_X2 U10 ( .A1(DATAIN[1]), .A2(n49), .ZN(n1788) );
NAND2_X2 U11 ( .A1(DATAIN[31]), .A2(n47), .ZN(n1094) );
NAND2_X2 U12 ( .A1(DATAIN[2]), .A2(n49), .ZN(n1766) );
NAND2_X2 U13 ( .A1(DATAIN[3]), .A2(n51), .ZN(n1744) );
NAND2_X2 U14 ( .A1(DATAIN[30]), .A2(n47), .ZN(n1150) );
NAND2_X2 U15 ( .A1(DATAIN[4]), .A2(n51), .ZN(n1722) );
NAND2_X2 U16 ( .A1(DATAIN[5]), .A2(n51), .ZN(n1700) );
NAND2_X2 U17 ( .A1(DATAIN[29]), .A2(n47), .ZN(n1172) );
NAND2_X2 U18 ( .A1(DATAIN[6]), .A2(n51), .ZN(n1678) );
NAND2_X2 U19 ( .A1(DATAIN[7]), .A2(n51), .ZN(n1656) );
NAND2_X2 U20 ( .A1(DATAIN[28]), .A2(n47), .ZN(n1194) );
NAND2_X2 U21 ( .A1(DATAIN[8]), .A2(n51), .ZN(n1634) );
NAND2_X2 U22 ( .A1(DATAIN[0]), .A2(n47), .ZN(n1810) );
NAND2_X2 U23 ( .A1(DATAIN[16]), .A2(n49), .ZN(n1458) );
NAND2_X2 U24 ( .A1(DATAIN[17]), .A2(n49), .ZN(n1436) );
NAND2_X2 U25 ( .A1(DATAIN[23]), .A2(n49), .ZN(n1304) );
NAND2_X2 U26 ( .A1(DATAIN[18]), .A2(n49), .ZN(n1414) );
NAND2_X2 U27 ( .A1(DATAIN[19]), .A2(n49), .ZN(n1392) );
NAND2_X2 U28 ( .A1(DATAIN[22]), .A2(n49), .ZN(n1326) );
NAND2_X2 U29 ( .A1(DATAIN[20]), .A2(n49), .ZN(n1370) );
NAND2_X2 U30 ( .A1(DATAIN[21]), .A2(n49), .ZN(n1348) );
NAND2_X2 U31 ( .A1(DATAIN[9]), .A2(n51), .ZN(n1612) );
NAND2_X2 U32 ( .A1(DATAIN[27]), .A2(n47), .ZN(n1216) );
NAND2_X2 U33 ( .A1(DATAIN[10]), .A2(n51), .ZN(n1590) );
NAND2_X2 U34 ( .A1(DATAIN[11]), .A2(n51), .ZN(n1568) );
NAND2_X2 U35 ( .A1(DATAIN[26]), .A2(n49), .ZN(n1238) );
NAND2_X2 U36 ( .A1(DATAIN[12]), .A2(n51), .ZN(n1546) );
NAND2_X2 U37 ( .A1(DATAIN[13]), .A2(n51), .ZN(n1524) );
NAND2_X2 U38 ( .A1(DATAIN[25]), .A2(n49), .ZN(n1260) );
NAND2_X2 U39 ( .A1(DATAIN[14]), .A2(n51), .ZN(n1502) );
NAND2_X2 U40 ( .A1(DATAIN[15]), .A2(n49), .ZN(n1480) );
NAND2_X2 U41 ( .A1(DATAIN[24]), .A2(n49), .ZN(n1282) );
BUF_X1 U42 ( .A(n1154), .Z(n3) );
BUF_X1 U43 ( .A(n1153), .Z(n2) );
BUF_X1 U44 ( .A(n1142), .Z(n1) );
BUF_X1 U45 ( .A(n1156), .Z(n37) );
BUF_X1 U46 ( .A(n1918), .Z(n43) );
BUF_X1 U47 ( .A(n1907), .Z(n39) );
BUF_X1 U48 ( .A(n1917), .Z(n41) );
BUF_X1 U49 ( .A(n1920), .Z(n45) );
NAND2_X2 U50 ( .A1(n2572), .A2(n2597), .ZN(n1914) );
NAND2_X2 U51 ( .A1(n2575), .A2(n2597), .ZN(n1916) );
NAND2_X2 U52 ( .A1(n2598), .A2(n2575), .ZN(n1915) );
NAND2_X2 U53 ( .A1(n2591), .A2(n2577), .ZN(n1908) );
NAND2_X2 U54 ( .A1(n2572), .A2(n2573), .ZN(n1878) );
NAND2_X2 U55 ( .A1(n2572), .A2(n2574), .ZN(n1877) );
NAND2_X2 U56 ( .A1(n2575), .A2(n2573), .ZN(n1880) );
NAND2_X2 U57 ( .A1(n2575), .A2(n2574), .ZN(n1879) );
NAND2_X2 U58 ( .A1(n2576), .A2(n2573), .ZN(n1882) );
NAND2_X2 U59 ( .A1(n2576), .A2(n2574), .ZN(n1881) );
NAND2_X2 U60 ( .A1(n2577), .A2(n2573), .ZN(n1884) );
NAND2_X2 U61 ( .A1(n2577), .A2(n2574), .ZN(n1883) );
NAND2_X2 U62 ( .A1(n2572), .A2(n2585), .ZN(n1890) );
NAND2_X2 U63 ( .A1(n2572), .A2(n2586), .ZN(n1889) );
NAND2_X2 U64 ( .A1(n2585), .A2(n2575), .ZN(n1892) );
NAND2_X2 U65 ( .A1(n2586), .A2(n2575), .ZN(n1891) );
NAND2_X2 U66 ( .A1(n2576), .A2(n2585), .ZN(n1894) );
NAND2_X2 U67 ( .A1(n2576), .A2(n2586), .ZN(n1893) );
NAND2_X2 U68 ( .A1(n2577), .A2(n2585), .ZN(n1896) );
NAND2_X2 U69 ( .A1(n2577), .A2(n2586), .ZN(n1895) );
NAND2_X2 U70 ( .A1(n2572), .A2(n2591), .ZN(n1902) );
NAND2_X2 U71 ( .A1(n2572), .A2(n2592), .ZN(n1901) );
NAND2_X2 U72 ( .A1(n2591), .A2(n2575), .ZN(n1904) );
NAND2_X2 U73 ( .A1(n2575), .A2(n2592), .ZN(n1903) );
NAND2_X2 U74 ( .A1(n2576), .A2(n2591), .ZN(n1906) );
NAND2_X2 U75 ( .A1(n2576), .A2(n2592), .ZN(n1905) );
NAND2_X2 U76 ( .A1(n1865), .A2(n1842), .ZN(n1151) );
NAND2_X2 U77 ( .A1(n1842), .A2(n1864), .ZN(n1152) );
NAND2_X2 U78 ( .A1(n1839), .A2(n1864), .ZN(n1149) );
NAND2_X2 U79 ( .A1(n1858), .A2(n1844), .ZN(n1143) );
NAND2_X2 U80 ( .A1(n1843), .A2(n1859), .ZN(n1140) );
NAND2_X2 U81 ( .A1(n1843), .A2(n1858), .ZN(n1141) );
NAND2_X2 U82 ( .A1(n1842), .A2(n1859), .ZN(n1138) );
NAND2_X2 U83 ( .A1(n1858), .A2(n1842), .ZN(n1139) );
NAND2_X2 U84 ( .A1(n1839), .A2(n1859), .ZN(n1136) );
NAND2_X2 U85 ( .A1(n1839), .A2(n1858), .ZN(n1137) );
NAND2_X2 U86 ( .A1(n1844), .A2(n1853), .ZN(n1130) );
NAND2_X2 U87 ( .A1(n1844), .A2(n1852), .ZN(n1131) );
NAND2_X2 U88 ( .A1(n1843), .A2(n1853), .ZN(n1128) );
NAND2_X2 U89 ( .A1(n1843), .A2(n1852), .ZN(n1129) );
NAND2_X2 U90 ( .A1(n1853), .A2(n1842), .ZN(n1126) );
NAND2_X2 U91 ( .A1(n1852), .A2(n1842), .ZN(n1127) );
NAND2_X2 U92 ( .A1(n1839), .A2(n1853), .ZN(n1124) );
NAND2_X2 U93 ( .A1(n1839), .A2(n1852), .ZN(n1125) );
NAND2_X2 U94 ( .A1(n1844), .A2(n1841), .ZN(n1118) );
NAND2_X2 U95 ( .A1(n1844), .A2(n1840), .ZN(n1119) );
NAND2_X2 U96 ( .A1(n1843), .A2(n1841), .ZN(n1116) );
NAND2_X2 U97 ( .A1(n1843), .A2(n1840), .ZN(n1117) );
NAND2_X2 U98 ( .A1(n1842), .A2(n1841), .ZN(n1114) );
NAND2_X2 U99 ( .A1(n1842), .A2(n1840), .ZN(n1115) );
NAND2_X2 U100 ( .A1(n1839), .A2(n1841), .ZN(n1112) );
NAND2_X2 U101 ( .A1(n1839), .A2(n1840), .ZN(n1113) );
NAND2_X2 U102 ( .A1(n1865), .A2(n1844), .ZN(n1155) );
NAND2_X2 U103 ( .A1(n1865), .A2(n1839), .ZN(n1148) );
NAND2_X2 U104 ( .A1(n2598), .A2(n2577), .ZN(n1919) );
NAND2_X2 U105 ( .A1(n2598), .A2(n2572), .ZN(n1913) );
AND4_X1 U106 ( .A1(n1334), .A2(n1335), .A3(n1336), .A4(n1337), .ZN(n1333) );
AND4_X1 U107 ( .A1(n1202), .A2(n1203), .A3(n1204), .A4(n1205), .ZN(n1201) );
AND4_X1 U108 ( .A1(n1268), .A2(n1269), .A3(n1270), .A4(n1271), .ZN(n1267) );
AND4_X1 U109 ( .A1(n1554), .A2(n1555), .A3(n1556), .A4(n1557), .ZN(n1553) );
AND4_X1 U110 ( .A1(n1180), .A2(n1181), .A3(n1182), .A4(n1183), .ZN(n1179) );
AND4_X1 U111 ( .A1(n1356), .A2(n1357), .A3(n1358), .A4(n1359), .ZN(n1355) );
AND4_X1 U112 ( .A1(n1224), .A2(n1225), .A3(n1226), .A4(n1227), .ZN(n1223) );
AND4_X1 U113 ( .A1(n1532), .A2(n1533), .A3(n1534), .A4(n1535), .ZN(n1531) );
AND4_X1 U114 ( .A1(n1312), .A2(n1313), .A3(n1314), .A4(n1315), .ZN(n1311) );
AND4_X1 U115 ( .A1(n1422), .A2(n1423), .A3(n1424), .A4(n1425), .ZN(n1421) );
AND4_X1 U116 ( .A1(n1444), .A2(n1445), .A3(n1446), .A4(n1447), .ZN(n1443) );
AND4_X1 U117 ( .A1(n1510), .A2(n1511), .A3(n1512), .A4(n1513), .ZN(n1509) );
AND4_X1 U118 ( .A1(n1158), .A2(n1159), .A3(n1160), .A4(n1161), .ZN(n1157) );
AND4_X1 U119 ( .A1(n1400), .A2(n1401), .A3(n1402), .A4(n1403), .ZN(n1399) );
AND4_X1 U120 ( .A1(n1378), .A2(n1379), .A3(n1380), .A4(n1381), .ZN(n1377) );
AND4_X1 U121 ( .A1(n1488), .A2(n1489), .A3(n1490), .A4(n1491), .ZN(n1487) );
AND4_X1 U122 ( .A1(n1104), .A2(n1105), .A3(n1106), .A4(n1107), .ZN(n1101) );
AND4_X1 U123 ( .A1(n1466), .A2(n1467), .A3(n1468), .A4(n1469), .ZN(n1465) );
AND4_X1 U124 ( .A1(n1290), .A2(n1291), .A3(n1292), .A4(n1293), .ZN(n1289) );
AND4_X1 U125 ( .A1(n2279), .A2(n2280), .A3(n2281), .A4(n2282), .ZN(n2278) );
AND4_X1 U126 ( .A1(n2300), .A2(n2301), .A3(n2302), .A4(n2303), .ZN(n2299) );
AND4_X1 U127 ( .A1(n2174), .A2(n2175), .A3(n2176), .A4(n2177), .ZN(n2173) );
AND4_X1 U128 ( .A1(n2258), .A2(n2259), .A3(n2260), .A4(n2261), .ZN(n2257) );
AND4_X1 U129 ( .A1(n2027), .A2(n2028), .A3(n2029), .A4(n2030), .ZN(n2026) );
AND4_X1 U130 ( .A1(n1964), .A2(n1965), .A3(n1966), .A4(n1967), .ZN(n1963) );
AND4_X1 U131 ( .A1(n1985), .A2(n1986), .A3(n1987), .A4(n1988), .ZN(n1984) );
AND4_X1 U132 ( .A1(n2237), .A2(n2238), .A3(n2239), .A4(n2240), .ZN(n2236) );
AND4_X1 U133 ( .A1(n1943), .A2(n1944), .A3(n1945), .A4(n1946), .ZN(n1942) );
AND4_X1 U134 ( .A1(n2216), .A2(n2217), .A3(n2218), .A4(n2219), .ZN(n2215) );
AND4_X1 U135 ( .A1(n2153), .A2(n2154), .A3(n2155), .A4(n2156), .ZN(n2152) );
AND4_X1 U136 ( .A1(n2195), .A2(n2196), .A3(n2197), .A4(n2198), .ZN(n2194) );
AND4_X1 U137 ( .A1(n2090), .A2(n2091), .A3(n2092), .A4(n2093), .ZN(n2089) );
AND4_X1 U138 ( .A1(n1922), .A2(n1923), .A3(n1924), .A4(n1925), .ZN(n1921) );
AND4_X1 U139 ( .A1(n2069), .A2(n2070), .A3(n2071), .A4(n2072), .ZN(n2068) );
AND4_X1 U140 ( .A1(n1869), .A2(n1870), .A3(n1871), .A4(n1872), .ZN(n1866) );
AND4_X1 U141 ( .A1(n2048), .A2(n2049), .A3(n2050), .A4(n2051), .ZN(n2047) );
AND4_X1 U142 ( .A1(n2132), .A2(n2133), .A3(n2134), .A4(n2135), .ZN(n2131) );
AND4_X1 U143 ( .A1(n2111), .A2(n2112), .A3(n2113), .A4(n2114), .ZN(n2110) );
INV_X1 U144 ( .A(n1773), .ZN(n1767) );
AND4_X1 U145 ( .A1(n1730), .A2(n1731), .A3(n1732), .A4(n1733), .ZN(n1729) );
AND4_X1 U146 ( .A1(n1664), .A2(n1665), .A3(n1666), .A4(n1667), .ZN(n1663) );
AND4_X1 U147 ( .A1(n1686), .A2(n1687), .A3(n1688), .A4(n1689), .ZN(n1685) );
AND4_X1 U148 ( .A1(n1775), .A2(n1776), .A3(n1777), .A4(n1778), .ZN(n1774) );
AND4_X1 U149 ( .A1(n1831), .A2(n1832), .A3(n1833), .A4(n1834), .ZN(n1818) );
AND4_X1 U150 ( .A1(n1797), .A2(n1798), .A3(n1799), .A4(n1800), .ZN(n1796) );
AND4_X1 U151 ( .A1(n1708), .A2(n1709), .A3(n1710), .A4(n1711), .ZN(n1707) );
AND4_X1 U152 ( .A1(n2447), .A2(n2448), .A3(n2449), .A4(n2450), .ZN(n2446) );
AND4_X1 U153 ( .A1(n2532), .A2(n2533), .A3(n2534), .A4(n2535), .ZN(n2531) );
AND4_X1 U154 ( .A1(n2511), .A2(n2512), .A3(n2513), .A4(n2514), .ZN(n2510) );
AND4_X1 U155 ( .A1(n2564), .A2(n2565), .A3(n2566), .A4(n2567), .ZN(n2552) );
AND4_X1 U156 ( .A1(n2405), .A2(n2406), .A3(n2407), .A4(n2408), .ZN(n2404) );
AND4_X1 U157 ( .A1(n2468), .A2(n2469), .A3(n2470), .A4(n2471), .ZN(n2467) );
INV_X1 U158 ( .A(n2509), .ZN(n2503) );
AND4_X1 U159 ( .A1(n2426), .A2(n2427), .A3(n2428), .A4(n2429), .ZN(n2425) );
AND4_X1 U160 ( .A1(n1598), .A2(n1599), .A3(n1600), .A4(n1601), .ZN(n1597) );
AND4_X1 U161 ( .A1(n1642), .A2(n1643), .A3(n1644), .A4(n1645), .ZN(n1641) );
AND4_X1 U162 ( .A1(n1576), .A2(n1577), .A3(n1578), .A4(n1579), .ZN(n1575) );
AND4_X1 U163 ( .A1(n1620), .A2(n1621), .A3(n1622), .A4(n1623), .ZN(n1619) );
AND4_X1 U164 ( .A1(n1246), .A2(n1247), .A3(n1248), .A4(n1249), .ZN(n1245) );
INV_X1 U165 ( .A(ADD_RD2[4]), .ZN(n1828) );
INV_X1 U166 ( .A(ADD_RD2[3]), .ZN(n1845) );
AND2_X1 U167 ( .A1(ADD_RD2[1]), .A2(ADD_RD2[2]), .ZN(n1839) );
AND2_X1 U168 ( .A1(n1822), .A2(ADD_RD2[2]), .ZN(n1842) );
INV_X1 U169 ( .A(ADD_RD2[1]), .ZN(n1822) );
INV_X1 U170 ( .A(ADD_RD2[0]), .ZN(n1846) );
AND4_X1 U171 ( .A1(n2384), .A2(n2385), .A3(n2386), .A4(n2387), .ZN(n2383) );
AND4_X1 U172 ( .A1(n2363), .A2(n2364), .A3(n2365), .A4(n2366), .ZN(n2362) );
AND4_X1 U173 ( .A1(n2321), .A2(n2322), .A3(n2323), .A4(n2324), .ZN(n2320) );
AND4_X1 U174 ( .A1(n2006), .A2(n2007), .A3(n2008), .A4(n2009), .ZN(n2005) );
INV_X1 U175 ( .A(n2563), .ZN(n2560) );
AND4_X1 U176 ( .A1(n2342), .A2(n2343), .A3(n2344), .A4(n2345), .ZN(n2341) );
INV_X1 U177 ( .A(ADD_RD1[4]), .ZN(n2558) );
INV_X1 U178 ( .A(ADD_RD1[3]), .ZN(n2578) );
AND2_X1 U179 ( .A1(ADD_RD1[1]), .A2(ADD_RD1[2]), .ZN(n2572) );
AND2_X1 U180 ( .A1(n2555), .A2(ADD_RD1[2]), .ZN(n2575) );
INV_X1 U181 ( .A(ADD_RD1[1]), .ZN(n2555) );
INV_X1 U182 ( .A(ADD_RD1[0]), .ZN(n2579) );
INV_X1 U183 ( .A(ADD_WR[0]), .ZN(n1826) );
OR3_X1 U184 ( .A1(n1829), .A2(n2562), .A3(ADD_WR[4]), .ZN(n2607) );
INV_X1 U185 ( .A(ADD_WR[3]), .ZN(n1829) );
INV_X1 U186 ( .A(ADD_WR[1]), .ZN(n1823) );
OR2_X1 U187 ( .A1(N4487), .A2(ENABLE), .ZN(N4615) );
INV_X1 U188 ( .A(ADD_WR[2]), .ZN(n1825) );
NOR2_X1 U189 ( .A1(ADD_RD2[2]), .A2(n1822), .ZN(n1843) );
AOI21_X1 U190 ( .B1(n2560), .B2(n2561), .A(n2562), .ZN(n1819) );
NOR2_X1 U191 ( .A1(ADD_RD1[2]), .A2(n2555), .ZN(n2576) );
NOR2_X1 U192 ( .A1(ADD_RD2[1]), .A2(ADD_RD2[2]), .ZN(n1844) );
NOR2_X1 U193 ( .A1(ADD_RD1[1]), .A2(ADD_RD1[2]), .ZN(n2577) );
NOR2_X1 U194 ( .A1(ADD_WR[4]), .A2(ADD_WR[3]), .ZN(n2561) );
AOI221_X1 U195 ( .B1(ADD_WR[1]), .B2(n1822), .C1(n1823), .C2(ADD_RD2[1]),
.A(n1824), .ZN(n1821) );
NOR2_X1 U196 ( .A1(ADD_RD2[0]), .A2(n1847), .ZN(n1841) );
AOI221_X1 U197 ( .B1(ADD_WR[1]), .B2(n2555), .C1(n1823), .C2(ADD_RD1[1]),
.A(n2556), .ZN(n2554) );
NOR2_X1 U198 ( .A1(ADD_RD1[0]), .A2(n2580), .ZN(n2574) );
NAND3_X1 U199 ( .A1(n1826), .A2(n1825), .A3(n1823), .ZN(n2563) );
OAI22_X1 U200 ( .A1(n1101), .A2(n1102), .B1(n1103), .B2(n1094), .ZN(N4616)
);
NOR4_X1 U201 ( .A1(n1108), .A2(n1109), .A3(n1110), .A4(n1111), .ZN(n1107) );
OAI22_X1 U202 ( .A1(n199), .A2(n1112), .B1(n1089), .B2(n1113), .ZN(n1111) );
OAI22_X1 U203 ( .A1(n263), .A2(n1114), .B1(n231), .B2(n1115), .ZN(n1110) );
OAI22_X1 U204 ( .A1(n327), .A2(n1116), .B1(n295), .B2(n1117), .ZN(n1109) );
OAI22_X1 U205 ( .A1(n391), .A2(n1118), .B1(n359), .B2(n1119), .ZN(n1108) );
NOR4_X1 U206 ( .A1(n1120), .A2(n1121), .A3(n1122), .A4(n1123), .ZN(n1106) );
OAI22_X1 U207 ( .A1(n456), .A2(n1124), .B1(n423), .B2(n1125), .ZN(n1123) );
OAI22_X1 U208 ( .A1(n524), .A2(n1126), .B1(n490), .B2(n1127), .ZN(n1122) );
OAI22_X1 U209 ( .A1(n591), .A2(n1128), .B1(n557), .B2(n1129), .ZN(n1121) );
OAI22_X1 U210 ( .A1(n658), .A2(n1130), .B1(n624), .B2(n1131), .ZN(n1120) );
NOR4_X1 U211 ( .A1(n1132), .A2(n1133), .A3(n1134), .A4(n1135), .ZN(n1105) );
OAI22_X1 U212 ( .A1(n725), .A2(n1136), .B1(n692), .B2(n1137), .ZN(n1135) );
OAI22_X1 U213 ( .A1(n792), .A2(n1138), .B1(n759), .B2(n1139), .ZN(n1134) );
OAI22_X1 U214 ( .A1(n860), .A2(n1140), .B1(n826), .B2(n1141), .ZN(n1133) );
OAI22_X1 U215 ( .A1(n927), .A2(n1142), .B1(n893), .B2(n1143), .ZN(n1132) );
NOR4_X1 U216 ( .A1(n1144), .A2(n1145), .A3(n1146), .A4(n1147), .ZN(n1104) );
OAI22_X1 U217 ( .A1(n994), .A2(n1148), .B1(n960), .B2(n1149), .ZN(n1147) );
OAI22_X1 U218 ( .A1(n1061), .A2(n1151), .B1(n1028), .B2(n1152), .ZN(n1146)
);
OAI22_X1 U219 ( .A1(n106), .A2(n2), .B1(n1096), .B2(n1154), .ZN(n1145) );
OAI22_X1 U220 ( .A1(n177), .A2(n1155), .B1(n141), .B2(n1156), .ZN(n1144) );
OAI22_X1 U221 ( .A1(n1157), .A2(n1102), .B1(n1103), .B2(n1150), .ZN(N4614)
);
NOR4_X1 U222 ( .A1(n1162), .A2(n1163), .A3(n1164), .A4(n1165), .ZN(n1161) );
OAI22_X1 U223 ( .A1(n198), .A2(n1112), .B1(n1068), .B2(n1113), .ZN(n1165) );
OAI22_X1 U224 ( .A1(n262), .A2(n1114), .B1(n230), .B2(n1115), .ZN(n1164) );
OAI22_X1 U225 ( .A1(n326), .A2(n1116), .B1(n294), .B2(n1117), .ZN(n1163) );
OAI22_X1 U226 ( .A1(n390), .A2(n1118), .B1(n358), .B2(n1119), .ZN(n1162) );
NOR4_X1 U227 ( .A1(n1166), .A2(n1167), .A3(n1168), .A4(n1169), .ZN(n1160) );
OAI22_X1 U228 ( .A1(n455), .A2(n1124), .B1(n422), .B2(n1125), .ZN(n1169) );
OAI22_X1 U229 ( .A1(n523), .A2(n1126), .B1(n489), .B2(n1127), .ZN(n1168) );
OAI22_X1 U230 ( .A1(n590), .A2(n1128), .B1(n556), .B2(n1129), .ZN(n1167) );
OAI22_X1 U231 ( .A1(n657), .A2(n1130), .B1(n623), .B2(n1131), .ZN(n1166) );
NOR4_X1 U232 ( .A1(n1170), .A2(n1171), .A3(n1173), .A4(n1174), .ZN(n1159) );
OAI22_X1 U233 ( .A1(n724), .A2(n1136), .B1(n691), .B2(n1137), .ZN(n1174) );
OAI22_X1 U234 ( .A1(n791), .A2(n1138), .B1(n758), .B2(n1139), .ZN(n1173) );
OAI22_X1 U235 ( .A1(n859), .A2(n1140), .B1(n825), .B2(n1141), .ZN(n1171) );
OAI22_X1 U236 ( .A1(n926), .A2(n1), .B1(n892), .B2(n1143), .ZN(n1170) );
NOR4_X1 U237 ( .A1(n1175), .A2(n1176), .A3(n1177), .A4(n1178), .ZN(n1158) );
OAI22_X1 U238 ( .A1(n993), .A2(n1148), .B1(n959), .B2(n1149), .ZN(n1178) );
OAI22_X1 U239 ( .A1(n1060), .A2(n1151), .B1(n1027), .B2(n1152), .ZN(n1177)
);
OAI22_X1 U240 ( .A1(n105), .A2(n1153), .B1(n1095), .B2(n1154), .ZN(n1176) );
OAI22_X1 U241 ( .A1(n176), .A2(n1155), .B1(n140), .B2(n37), .ZN(n1175) );
OAI22_X1 U242 ( .A1(n1179), .A2(n1102), .B1(n1103), .B2(n1172), .ZN(N4612)
);
NOR4_X1 U243 ( .A1(n1184), .A2(n1185), .A3(n1186), .A4(n1187), .ZN(n1183) );
OAI22_X1 U244 ( .A1(n197), .A2(n1112), .B1(n1047), .B2(n1113), .ZN(n1187) );
OAI22_X1 U245 ( .A1(n261), .A2(n1114), .B1(n229), .B2(n1115), .ZN(n1186) );
OAI22_X1 U246 ( .A1(n325), .A2(n1116), .B1(n293), .B2(n1117), .ZN(n1185) );
OAI22_X1 U247 ( .A1(n389), .A2(n1118), .B1(n357), .B2(n1119), .ZN(n1184) );
NOR4_X1 U248 ( .A1(n1188), .A2(n1189), .A3(n1190), .A4(n1191), .ZN(n1182) );
OAI22_X1 U249 ( .A1(n454), .A2(n1124), .B1(n421), .B2(n1125), .ZN(n1191) );
OAI22_X1 U250 ( .A1(n521), .A2(n1126), .B1(n488), .B2(n1127), .ZN(n1190) );
OAI22_X1 U251 ( .A1(n589), .A2(n1128), .B1(n555), .B2(n1129), .ZN(n1189) );
OAI22_X1 U252 ( .A1(n656), .A2(n1130), .B1(n622), .B2(n1131), .ZN(n1188) );
NOR4_X1 U253 ( .A1(n1192), .A2(n1193), .A3(n1195), .A4(n1196), .ZN(n1181) );
OAI22_X1 U254 ( .A1(n723), .A2(n1136), .B1(n689), .B2(n1137), .ZN(n1196) );
OAI22_X1 U255 ( .A1(n790), .A2(n1138), .B1(n757), .B2(n1139), .ZN(n1195) );
OAI22_X1 U256 ( .A1(n857), .A2(n1140), .B1(n824), .B2(n1141), .ZN(n1193) );
OAI22_X1 U257 ( .A1(n925), .A2(n1142), .B1(n891), .B2(n1143), .ZN(n1192) );
NOR4_X1 U258 ( .A1(n1197), .A2(n1198), .A3(n1199), .A4(n1200), .ZN(n1180) );
OAI22_X1 U259 ( .A1(n992), .A2(n1148), .B1(n958), .B2(n1149), .ZN(n1200) );
OAI22_X1 U260 ( .A1(n1059), .A2(n1151), .B1(n1025), .B2(n1152), .ZN(n1199)
);
OAI22_X1 U261 ( .A1(n104), .A2(n1153), .B1(n1093), .B2(n1154), .ZN(n1198) );
OAI22_X1 U262 ( .A1(n174), .A2(n1155), .B1(n139), .B2(n37), .ZN(n1197) );
OAI22_X1 U263 ( .A1(n1201), .A2(n1102), .B1(n1103), .B2(n1194), .ZN(N4610)
);
NOR4_X1 U264 ( .A1(n1206), .A2(n1207), .A3(n1208), .A4(n1209), .ZN(n1205) );
OAI22_X1 U265 ( .A1(n196), .A2(n1112), .B1(n1026), .B2(n1113), .ZN(n1209) );
OAI22_X1 U266 ( .A1(n260), .A2(n1114), .B1(n228), .B2(n1115), .ZN(n1208) );
OAI22_X1 U267 ( .A1(n324), .A2(n1116), .B1(n292), .B2(n1117), .ZN(n1207) );
OAI22_X1 U268 ( .A1(n388), .A2(n1118), .B1(n356), .B2(n1119), .ZN(n1206) );
NOR4_X1 U269 ( .A1(n1210), .A2(n1211), .A3(n1212), .A4(n1213), .ZN(n1204) );
OAI22_X1 U270 ( .A1(n453), .A2(n1124), .B1(n420), .B2(n1125), .ZN(n1213) );
OAI22_X1 U271 ( .A1(n520), .A2(n1126), .B1(n487), .B2(n1127), .ZN(n1212) );
OAI22_X1 U272 ( .A1(n588), .A2(n1128), .B1(n554), .B2(n1129), .ZN(n1211) );
OAI22_X1 U273 ( .A1(n655), .A2(n1130), .B1(n621), .B2(n1131), .ZN(n1210) );
NOR4_X1 U274 ( .A1(n1214), .A2(n1215), .A3(n1217), .A4(n1218), .ZN(n1203) );
OAI22_X1 U275 ( .A1(n722), .A2(n1136), .B1(n688), .B2(n1137), .ZN(n1218) );
OAI22_X1 U276 ( .A1(n789), .A2(n1138), .B1(n756), .B2(n1139), .ZN(n1217) );
OAI22_X1 U277 ( .A1(n856), .A2(n1140), .B1(n823), .B2(n1141), .ZN(n1215) );
OAI22_X1 U278 ( .A1(n924), .A2(n1142), .B1(n890), .B2(n1143), .ZN(n1214) );
NOR4_X1 U279 ( .A1(n1219), .A2(n1220), .A3(n1221), .A4(n1222), .ZN(n1202) );
OAI22_X1 U280 ( .A1(n991), .A2(n1148), .B1(n957), .B2(n1149), .ZN(n1222) );
OAI22_X1 U281 ( .A1(n1058), .A2(n1151), .B1(n1024), .B2(n1152), .ZN(n1221)
);
OAI22_X1 U282 ( .A1(n103), .A2(n1153), .B1(n1092), .B2(n3), .ZN(n1220) );
OAI22_X1 U283 ( .A1(n173), .A2(n1155), .B1(n138), .B2(n37), .ZN(n1219) );
OAI22_X1 U284 ( .A1(n1223), .A2(n1102), .B1(n1103), .B2(n1216), .ZN(N4608)
);
NOR4_X1 U285 ( .A1(n1228), .A2(n1229), .A3(n1230), .A4(n1231), .ZN(n1227) );
OAI22_X1 U286 ( .A1(n195), .A2(n1112), .B1(n1005), .B2(n1113), .ZN(n1231) );
OAI22_X1 U287 ( .A1(n259), .A2(n1114), .B1(n227), .B2(n1115), .ZN(n1230) );
OAI22_X1 U288 ( .A1(n323), .A2(n1116), .B1(n291), .B2(n1117), .ZN(n1229) );
OAI22_X1 U289 ( .A1(n387), .A2(n1118), .B1(n355), .B2(n1119), .ZN(n1228) );
NOR4_X1 U290 ( .A1(n1232), .A2(n1233), .A3(n1234), .A4(n1235), .ZN(n1226) );
OAI22_X1 U291 ( .A1(n452), .A2(n1124), .B1(n419), .B2(n1125), .ZN(n1235) );
OAI22_X1 U292 ( .A1(n519), .A2(n1126), .B1(n486), .B2(n1127), .ZN(n1234) );
OAI22_X1 U293 ( .A1(n587), .A2(n1128), .B1(n553), .B2(n1129), .ZN(n1233) );
OAI22_X1 U294 ( .A1(n654), .A2(n1130), .B1(n620), .B2(n1131), .ZN(n1232) );
NOR4_X1 U295 ( .A1(n1236), .A2(n1237), .A3(n1239), .A4(n1240), .ZN(n1225) );
OAI22_X1 U296 ( .A1(n721), .A2(n1136), .B1(n687), .B2(n1137), .ZN(n1240) );
OAI22_X1 U297 ( .A1(n788), .A2(n1138), .B1(n755), .B2(n1139), .ZN(n1239) );
OAI22_X1 U298 ( .A1(n855), .A2(n1140), .B1(n822), .B2(n1141), .ZN(n1237) );
OAI22_X1 U299 ( .A1(n923), .A2(n1142), .B1(n889), .B2(n1143), .ZN(n1236) );
NOR4_X1 U300 ( .A1(n1241), .A2(n1242), .A3(n1243), .A4(n1244), .ZN(n1224) );
OAI22_X1 U301 ( .A1(n990), .A2(n1148), .B1(n956), .B2(n1149), .ZN(n1244) );
OAI22_X1 U302 ( .A1(n1057), .A2(n1151), .B1(n1023), .B2(n1152), .ZN(n1243)
);
OAI22_X1 U303 ( .A1(n102), .A2(n1153), .B1(n1091), .B2(n3), .ZN(n1242) );
OAI22_X1 U304 ( .A1(n172), .A2(n1155), .B1(n137), .B2(n37), .ZN(n1241) );
OAI22_X1 U305 ( .A1(n1245), .A2(n1102), .B1(n1103), .B2(n1238), .ZN(N4606)
);
NOR4_X1 U306 ( .A1(n1250), .A2(n1251), .A3(n1252), .A4(n1253), .ZN(n1249) );
OAI22_X1 U307 ( .A1(n194), .A2(n1112), .B1(n984), .B2(n1113), .ZN(n1253) );
OAI22_X1 U308 ( .A1(n258), .A2(n1114), .B1(n226), .B2(n1115), .ZN(n1252) );
OAI22_X1 U309 ( .A1(n322), .A2(n1116), .B1(n290), .B2(n1117), .ZN(n1251) );
OAI22_X1 U310 ( .A1(n386), .A2(n1118), .B1(n354), .B2(n1119), .ZN(n1250) );
NOR4_X1 U311 ( .A1(n1254), .A2(n1255), .A3(n1256), .A4(n1257), .ZN(n1248) );
OAI22_X1 U312 ( .A1(n451), .A2(n1124), .B1(n418), .B2(n1125), .ZN(n1257) );
OAI22_X1 U313 ( .A1(n518), .A2(n1126), .B1(n485), .B2(n1127), .ZN(n1256) );
OAI22_X1 U314 ( .A1(n586), .A2(n1128), .B1(n552), .B2(n1129), .ZN(n1255) );
OAI22_X1 U315 ( .A1(n653), .A2(n1130), .B1(n619), .B2(n1131), .ZN(n1254) );
NOR4_X1 U316 ( .A1(n1258), .A2(n1259), .A3(n1261), .A4(n1262), .ZN(n1247) );
OAI22_X1 U317 ( .A1(n720), .A2(n1136), .B1(n686), .B2(n1137), .ZN(n1262) );
OAI22_X1 U318 ( .A1(n787), .A2(n1138), .B1(n754), .B2(n1139), .ZN(n1261) );
OAI22_X1 U319 ( .A1(n854), .A2(n1140), .B1(n821), .B2(n1141), .ZN(n1259) );
OAI22_X1 U320 ( .A1(n922), .A2(n1142), .B1(n888), .B2(n1143), .ZN(n1258) );
NOR4_X1 U321 ( .A1(n1263), .A2(n1264), .A3(n1265), .A4(n1266), .ZN(n1246) );
OAI22_X1 U322 ( .A1(n989), .A2(n1148), .B1(n955), .B2(n1149), .ZN(n1266) );
OAI22_X1 U323 ( .A1(n1056), .A2(n1151), .B1(n1022), .B2(n1152), .ZN(n1265)
);
OAI22_X1 U324 ( .A1(n101), .A2(n1153), .B1(n1090), .B2(n1154), .ZN(n1264) );
OAI22_X1 U325 ( .A1(n171), .A2(n1155), .B1(n136), .B2(n37), .ZN(n1263) );
OAI22_X1 U326 ( .A1(n1267), .A2(n1102), .B1(n1103), .B2(n1260), .ZN(N4604)
);
NOR4_X1 U327 ( .A1(n1272), .A2(n1273), .A3(n1274), .A4(n1275), .ZN(n1271) );
OAI22_X1 U328 ( .A1(n193), .A2(n1112), .B1(n963), .B2(n1113), .ZN(n1275) );
OAI22_X1 U329 ( .A1(n257), .A2(n1114), .B1(n225), .B2(n1115), .ZN(n1274) );
OAI22_X1 U330 ( .A1(n321), .A2(n1116), .B1(n289), .B2(n1117), .ZN(n1273) );
OAI22_X1 U331 ( .A1(n385), .A2(n1118), .B1(n353), .B2(n1119), .ZN(n1272) );
NOR4_X1 U332 ( .A1(n1276), .A2(n1277), .A3(n1278), .A4(n1279), .ZN(n1270) );
OAI22_X1 U333 ( .A1(n450), .A2(n1124), .B1(n417), .B2(n1125), .ZN(n1279) );
OAI22_X1 U334 ( .A1(n517), .A2(n1126), .B1(n484), .B2(n1127), .ZN(n1278) );
OAI22_X1 U335 ( .A1(n584), .A2(n1128), .B1(n551), .B2(n1129), .ZN(n1277) );
OAI22_X1 U336 ( .A1(n652), .A2(n1130), .B1(n618), .B2(n1131), .ZN(n1276) );
NOR4_X1 U337 ( .A1(n1280), .A2(n1281), .A3(n1283), .A4(n1284), .ZN(n1269) );
OAI22_X1 U338 ( .A1(n719), .A2(n1136), .B1(n685), .B2(n1137), .ZN(n1284) );
OAI22_X1 U339 ( .A1(n786), .A2(n1138), .B1(n752), .B2(n1139), .ZN(n1283) );
OAI22_X1 U340 ( .A1(n853), .A2(n1140), .B1(n820), .B2(n1141), .ZN(n1281) );
OAI22_X1 U341 ( .A1(n920), .A2(n1142), .B1(n887), .B2(n1143), .ZN(n1280) );
NOR4_X1 U342 ( .A1(n1285), .A2(n1286), .A3(n1287), .A4(n1288), .ZN(n1268) );
OAI22_X1 U343 ( .A1(n988), .A2(n1148), .B1(n954), .B2(n1149), .ZN(n1288) );
OAI22_X1 U344 ( .A1(n1055), .A2(n1151), .B1(n1021), .B2(n1152), .ZN(n1287)
);
OAI22_X1 U345 ( .A1(n100), .A2(n1153), .B1(n1088), .B2(n3), .ZN(n1286) );
OAI22_X1 U346 ( .A1(n170), .A2(n1155), .B1(n135), .B2(n37), .ZN(n1285) );
OAI22_X1 U347 ( .A1(n1289), .A2(n1102), .B1(n1103), .B2(n1282), .ZN(N4602)
);
NOR4_X1 U348 ( .A1(n1294), .A2(n1295), .A3(n1296), .A4(n1297), .ZN(n1293) );
OAI22_X1 U349 ( .A1(n192), .A2(n1112), .B1(n942), .B2(n1113), .ZN(n1297) );
OAI22_X1 U350 ( .A1(n256), .A2(n1114), .B1(n224), .B2(n1115), .ZN(n1296) );
OAI22_X1 U351 ( .A1(n320), .A2(n1116), .B1(n288), .B2(n1117), .ZN(n1295) );
OAI22_X1 U352 ( .A1(n384), .A2(n1118), .B1(n352), .B2(n1119), .ZN(n1294) );
NOR4_X1 U353 ( .A1(n1298), .A2(n1299), .A3(n1300), .A4(n1301), .ZN(n1292) );
OAI22_X1 U354 ( .A1(n449), .A2(n1124), .B1(n416), .B2(n1125), .ZN(n1301) );
OAI22_X1 U355 ( .A1(n516), .A2(n1126), .B1(n483), .B2(n1127), .ZN(n1300) );
OAI22_X1 U356 ( .A1(n583), .A2(n1128), .B1(n550), .B2(n1129), .ZN(n1299) );
OAI22_X1 U357 ( .A1(n651), .A2(n1130), .B1(n617), .B2(n1131), .ZN(n1298) );
NOR4_X1 U358 ( .A1(n1302), .A2(n1303), .A3(n1305), .A4(n1306), .ZN(n1291) );
OAI22_X1 U359 ( .A1(n718), .A2(n1136), .B1(n684), .B2(n1137), .ZN(n1306) );
OAI22_X1 U360 ( .A1(n785), .A2(n1138), .B1(n751), .B2(n1139), .ZN(n1305) );
OAI22_X1 U361 ( .A1(n852), .A2(n1140), .B1(n819), .B2(n1141), .ZN(n1303) );
OAI22_X1 U362 ( .A1(n919), .A2(n1142), .B1(n886), .B2(n1143), .ZN(n1302) );
NOR4_X1 U363 ( .A1(n1307), .A2(n1308), .A3(n1309), .A4(n1310), .ZN(n1290) );
OAI22_X1 U364 ( .A1(n987), .A2(n1148), .B1(n953), .B2(n1149), .ZN(n1310) );
OAI22_X1 U365 ( .A1(n1054), .A2(n1151), .B1(n1020), .B2(n1152), .ZN(n1309)
);
OAI22_X1 U366 ( .A1(n99), .A2(n1153), .B1(n1087), .B2(n1154), .ZN(n1308) );
OAI22_X1 U367 ( .A1(n169), .A2(n1155), .B1(n134), .B2(n37), .ZN(n1307) );
OAI22_X1 U368 ( .A1(n1311), .A2(n1102), .B1(n1103), .B2(n1304), .ZN(N4600)
);
NOR4_X1 U369 ( .A1(n1316), .A2(n1317), .A3(n1318), .A4(n1319), .ZN(n1315) );
OAI22_X1 U370 ( .A1(n191), .A2(n1112), .B1(n921), .B2(n1113), .ZN(n1319) );
OAI22_X1 U371 ( .A1(n255), .A2(n1114), .B1(n223), .B2(n1115), .ZN(n1318) );
OAI22_X1 U372 ( .A1(n319), .A2(n1116), .B1(n287), .B2(n1117), .ZN(n1317) );
OAI22_X1 U373 ( .A1(n383), .A2(n1118), .B1(n351), .B2(n1119), .ZN(n1316) );
NOR4_X1 U374 ( .A1(n1320), .A2(n1321), .A3(n1322), .A4(n1323), .ZN(n1314) );
OAI22_X1 U375 ( .A1(n448), .A2(n1124), .B1(n415), .B2(n1125), .ZN(n1323) );
OAI22_X1 U376 ( .A1(n515), .A2(n1126), .B1(n482), .B2(n1127), .ZN(n1322) );
OAI22_X1 U377 ( .A1(n582), .A2(n1128), .B1(n549), .B2(n1129), .ZN(n1321) );
OAI22_X1 U378 ( .A1(n650), .A2(n1130), .B1(n616), .B2(n1131), .ZN(n1320) );
NOR4_X1 U379 ( .A1(n1324), .A2(n1325), .A3(n1327), .A4(n1328), .ZN(n1313) );
OAI22_X1 U380 ( .A1(n717), .A2(n1136), .B1(n683), .B2(n1137), .ZN(n1328) );
OAI22_X1 U381 ( .A1(n784), .A2(n1138), .B1(n750), .B2(n1139), .ZN(n1327) );
OAI22_X1 U382 ( .A1(n851), .A2(n1140), .B1(n818), .B2(n1141), .ZN(n1325) );
OAI22_X1 U383 ( .A1(n918), .A2(n1142), .B1(n885), .B2(n1143), .ZN(n1324) );
NOR4_X1 U384 ( .A1(n1329), .A2(n1330), .A3(n1331), .A4(n1332), .ZN(n1312) );
OAI22_X1 U385 ( .A1(n986), .A2(n1148), .B1(n952), .B2(n1149), .ZN(n1332) );
OAI22_X1 U386 ( .A1(n1053), .A2(n1151), .B1(n1019), .B2(n1152), .ZN(n1331)
);
OAI22_X1 U387 ( .A1(n95), .A2(n1153), .B1(n1086), .B2(n3), .ZN(n1330) );
OAI22_X1 U388 ( .A1(n168), .A2(n1155), .B1(n133), .B2(n37), .ZN(n1329) );
OAI22_X1 U389 ( .A1(n1333), .A2(n1102), .B1(n1103), .B2(n1326), .ZN(N4598)
);
NOR4_X1 U390 ( .A1(n1338), .A2(n1339), .A3(n1340), .A4(n1341), .ZN(n1337) );
OAI22_X1 U391 ( .A1(n190), .A2(n1112), .B1(n900), .B2(n1113), .ZN(n1341) );
OAI22_X1 U392 ( .A1(n254), .A2(n1114), .B1(n222), .B2(n1115), .ZN(n1340) );
OAI22_X1 U393 ( .A1(n318), .A2(n1116), .B1(n286), .B2(n1117), .ZN(n1339) );
OAI22_X1 U394 ( .A1(n382), .A2(n1118), .B1(n350), .B2(n1119), .ZN(n1338) );
NOR4_X1 U395 ( .A1(n1342), .A2(n1343), .A3(n1344), .A4(n1345), .ZN(n1336) );
OAI22_X1 U396 ( .A1(n447), .A2(n1124), .B1(n414), .B2(n1125), .ZN(n1345) );
OAI22_X1 U397 ( .A1(n514), .A2(n1126), .B1(n481), .B2(n1127), .ZN(n1344) );
OAI22_X1 U398 ( .A1(n581), .A2(n1128), .B1(n548), .B2(n1129), .ZN(n1343) );
OAI22_X1 U399 ( .A1(n649), .A2(n1130), .B1(n615), .B2(n1131), .ZN(n1342) );
NOR4_X1 U400 ( .A1(n1346), .A2(n1347), .A3(n1349), .A4(n1350), .ZN(n1335) );
OAI22_X1 U401 ( .A1(n716), .A2(n1136), .B1(n682), .B2(n1137), .ZN(n1350) );
OAI22_X1 U402 ( .A1(n783), .A2(n1138), .B1(n749), .B2(n1139), .ZN(n1349) );
OAI22_X1 U403 ( .A1(n850), .A2(n1140), .B1(n817), .B2(n1141), .ZN(n1347) );
OAI22_X1 U404 ( .A1(n917), .A2(n1142), .B1(n884), .B2(n1143), .ZN(n1346) );
NOR4_X1 U405 ( .A1(n1351), .A2(n1352), .A3(n1353), .A4(n1354), .ZN(n1334) );
OAI22_X1 U406 ( .A1(n985), .A2(n1148), .B1(n951), .B2(n1149), .ZN(n1354) );
OAI22_X1 U407 ( .A1(n1052), .A2(n1151), .B1(n1018), .B2(n1152), .ZN(n1353)
);
OAI22_X1 U408 ( .A1(n93), .A2(n1153), .B1(n1085), .B2(n3), .ZN(n1352) );
OAI22_X1 U409 ( .A1(n167), .A2(n1155), .B1(n132), .B2(n37), .ZN(n1351) );
OAI22_X1 U410 ( .A1(n1355), .A2(n1102), .B1(n1103), .B2(n1348), .ZN(N4596)
);
NOR4_X1 U411 ( .A1(n1360), .A2(n1361), .A3(n1362), .A4(n1363), .ZN(n1359) );
OAI22_X1 U412 ( .A1(n189), .A2(n1112), .B1(n879), .B2(n1113), .ZN(n1363) );
OAI22_X1 U413 ( .A1(n253), .A2(n1114), .B1(n221), .B2(n1115), .ZN(n1362) );
OAI22_X1 U414 ( .A1(n317), .A2(n1116), .B1(n285), .B2(n1117), .ZN(n1361) );
OAI22_X1 U415 ( .A1(n381), .A2(n1118), .B1(n349), .B2(n1119), .ZN(n1360) );
NOR4_X1 U416 ( .A1(n1364), .A2(n1365), .A3(n1366), .A4(n1367), .ZN(n1358) );
OAI22_X1 U417 ( .A1(n446), .A2(n1124), .B1(n413), .B2(n1125), .ZN(n1367) );
OAI22_X1 U418 ( .A1(n513), .A2(n1126), .B1(n479), .B2(n1127), .ZN(n1366) );
OAI22_X1 U419 ( .A1(n580), .A2(n1128), .B1(n547), .B2(n1129), .ZN(n1365) );
OAI22_X1 U420 ( .A1(n647), .A2(n1130), .B1(n614), .B2(n1131), .ZN(n1364) );
NOR4_X1 U421 ( .A1(n1368), .A2(n1369), .A3(n1371), .A4(n1372), .ZN(n1357) );
OAI22_X1 U422 ( .A1(n715), .A2(n1136), .B1(n681), .B2(n1137), .ZN(n1372) );
OAI22_X1 U423 ( .A1(n782), .A2(n1138), .B1(n748), .B2(n1139), .ZN(n1371) );
OAI22_X1 U424 ( .A1(n849), .A2(n1140), .B1(n815), .B2(n1141), .ZN(n1369) );
OAI22_X1 U425 ( .A1(n916), .A2(n1142), .B1(n883), .B2(n1143), .ZN(n1368) );
NOR4_X1 U426 ( .A1(n1373), .A2(n1374), .A3(n1375), .A4(n1376), .ZN(n1356) );
OAI22_X1 U427 ( .A1(n983), .A2(n1148), .B1(n950), .B2(n1149), .ZN(n1376) );
OAI22_X1 U428 ( .A1(n1051), .A2(n1151), .B1(n1017), .B2(n1152), .ZN(n1375)
);
OAI22_X1 U429 ( .A1(n91), .A2(n1153), .B1(n1084), .B2(n3), .ZN(n1374) );
OAI22_X1 U430 ( .A1(n166), .A2(n1155), .B1(n130), .B2(n37), .ZN(n1373) );
OAI22_X1 U431 ( .A1(n1377), .A2(n1102), .B1(n1103), .B2(n1370), .ZN(N4594)
);
NOR4_X1 U432 ( .A1(n1382), .A2(n1383), .A3(n1384), .A4(n1385), .ZN(n1381) );
OAI22_X1 U433 ( .A1(n188), .A2(n1112), .B1(n858), .B2(n1113), .ZN(n1385) );
OAI22_X1 U434 ( .A1(n252), .A2(n1114), .B1(n220), .B2(n1115), .ZN(n1384) );
OAI22_X1 U435 ( .A1(n316), .A2(n1116), .B1(n284), .B2(n1117), .ZN(n1383) );
OAI22_X1 U436 ( .A1(n380), .A2(n1118), .B1(n348), .B2(n1119), .ZN(n1382) );
NOR4_X1 U437 ( .A1(n1386), .A2(n1387), .A3(n1388), .A4(n1389), .ZN(n1380) );
OAI22_X1 U438 ( .A1(n445), .A2(n1124), .B1(n412), .B2(n1125), .ZN(n1389) );
OAI22_X1 U439 ( .A1(n512), .A2(n1126), .B1(n478), .B2(n1127), .ZN(n1388) );
OAI22_X1 U440 ( .A1(n579), .A2(n1128), .B1(n546), .B2(n1129), .ZN(n1387) );
OAI22_X1 U441 ( .A1(n646), .A2(n1130), .B1(n613), .B2(n1131), .ZN(n1386) );
NOR4_X1 U442 ( .A1(n1390), .A2(n1391), .A3(n1393), .A4(n1394), .ZN(n1379) );
OAI22_X1 U443 ( .A1(n714), .A2(n1136), .B1(n680), .B2(n1137), .ZN(n1394) );
OAI22_X1 U444 ( .A1(n781), .A2(n1138), .B1(n747), .B2(n1139), .ZN(n1393) );
OAI22_X1 U445 ( .A1(n848), .A2(n1140), .B1(n814), .B2(n1141), .ZN(n1391) );
OAI22_X1 U446 ( .A1(n915), .A2(n1142), .B1(n882), .B2(n1143), .ZN(n1390) );
NOR4_X1 U447 ( .A1(n1395), .A2(n1396), .A3(n1397), .A4(n1398), .ZN(n1378) );
OAI22_X1 U448 ( .A1(n982), .A2(n1148), .B1(n949), .B2(n1149), .ZN(n1398) );
OAI22_X1 U449 ( .A1(n1050), .A2(n1151), .B1(n1016), .B2(n1152), .ZN(n1397)
);
OAI22_X1 U450 ( .A1(n89), .A2(n1153), .B1(n1083), .B2(n3), .ZN(n1396) );
OAI22_X1 U451 ( .A1(n165), .A2(n1155), .B1(n129), .B2(n1156), .ZN(n1395) );
OAI22_X1 U452 ( .A1(n1399), .A2(n1102), .B1(n1103), .B2(n1392), .ZN(N4592)
);
NOR4_X1 U453 ( .A1(n1404), .A2(n1405), .A3(n1406), .A4(n1407), .ZN(n1403) );
OAI22_X1 U454 ( .A1(n187), .A2(n1112), .B1(n837), .B2(n1113), .ZN(n1407) );
OAI22_X1 U455 ( .A1(n251), .A2(n1114), .B1(n219), .B2(n1115), .ZN(n1406) );
OAI22_X1 U456 ( .A1(n315), .A2(n1116), .B1(n283), .B2(n1117), .ZN(n1405) );
OAI22_X1 U457 ( .A1(n379), .A2(n1118), .B1(n347), .B2(n1119), .ZN(n1404) );
NOR4_X1 U458 ( .A1(n1408), .A2(n1409), .A3(n1410), .A4(n1411), .ZN(n1402) );
OAI22_X1 U459 ( .A1(n444), .A2(n1124), .B1(n411), .B2(n1125), .ZN(n1411) );
OAI22_X1 U460 ( .A1(n511), .A2(n1126), .B1(n477), .B2(n1127), .ZN(n1410) );
OAI22_X1 U461 ( .A1(n578), .A2(n1128), .B1(n545), .B2(n1129), .ZN(n1409) );
OAI22_X1 U462 ( .A1(n645), .A2(n1130), .B1(n612), .B2(n1131), .ZN(n1408) );
NOR4_X1 U463 ( .A1(n1412), .A2(n1413), .A3(n1415), .A4(n1416), .ZN(n1401) );
OAI22_X1 U464 ( .A1(n713), .A2(n1136), .B1(n679), .B2(n1137), .ZN(n1416) );
OAI22_X1 U465 ( .A1(n780), .A2(n1138), .B1(n746), .B2(n1139), .ZN(n1415) );
OAI22_X1 U466 ( .A1(n847), .A2(n1140), .B1(n813), .B2(n1141), .ZN(n1413) );
OAI22_X1 U467 ( .A1(n914), .A2(n1142), .B1(n881), .B2(n1143), .ZN(n1412) );
NOR4_X1 U468 ( .A1(n1417), .A2(n1418), .A3(n1419), .A4(n1420), .ZN(n1400) );
OAI22_X1 U469 ( .A1(n981), .A2(n1148), .B1(n948), .B2(n1149), .ZN(n1420) );
OAI22_X1 U470 ( .A1(n1049), .A2(n1151), .B1(n1015), .B2(n1152), .ZN(n1419)
);
OAI22_X1 U471 ( .A1(n87), .A2(n2), .B1(n1082), .B2(n3), .ZN(n1418) );
OAI22_X1 U472 ( .A1(n163), .A2(n1155), .B1(n128), .B2(n1156), .ZN(n1417) );
OAI22_X1 U473 ( .A1(n1421), .A2(n1102), .B1(n1103), .B2(n1414), .ZN(N4590)
);
NOR4_X1 U474 ( .A1(n1426), .A2(n1427), .A3(n1428), .A4(n1429), .ZN(n1425) );
OAI22_X1 U475 ( .A1(n186), .A2(n1112), .B1(n816), .B2(n1113), .ZN(n1429) );
OAI22_X1 U476 ( .A1(n250), .A2(n1114), .B1(n218), .B2(n1115), .ZN(n1428) );
OAI22_X1 U477 ( .A1(n314), .A2(n1116), .B1(n282), .B2(n1117), .ZN(n1427) );
OAI22_X1 U478 ( .A1(n378), .A2(n1118), .B1(n346), .B2(n1119), .ZN(n1426) );
NOR4_X1 U479 ( .A1(n1430), .A2(n1431), .A3(n1432), .A4(n1433), .ZN(n1424) );
OAI22_X1 U480 ( .A1(n443), .A2(n1124), .B1(n410), .B2(n1125), .ZN(n1433) );
OAI22_X1 U481 ( .A1(n510), .A2(n1126), .B1(n476), .B2(n1127), .ZN(n1432) );
OAI22_X1 U482 ( .A1(n577), .A2(n1128), .B1(n544), .B2(n1129), .ZN(n1431) );
OAI22_X1 U483 ( .A1(n644), .A2(n1130), .B1(n611), .B2(n1131), .ZN(n1430) );
NOR4_X1 U484 ( .A1(n1434), .A2(n1435), .A3(n1437), .A4(n1438), .ZN(n1423) );
OAI22_X1 U485 ( .A1(n712), .A2(n1136), .B1(n678), .B2(n1137), .ZN(n1438) );
OAI22_X1 U486 ( .A1(n779), .A2(n1138), .B1(n745), .B2(n1139), .ZN(n1437) );
OAI22_X1 U487 ( .A1(n846), .A2(n1140), .B1(n812), .B2(n1141), .ZN(n1435) );
OAI22_X1 U488 ( .A1(n913), .A2(n1142), .B1(n880), .B2(n1143), .ZN(n1434) );
NOR4_X1 U489 ( .A1(n1439), .A2(n1440), .A3(n1441), .A4(n1442), .ZN(n1422) );
OAI22_X1 U490 ( .A1(n980), .A2(n1148), .B1(n947), .B2(n1149), .ZN(n1442) );
OAI22_X1 U491 ( .A1(n1048), .A2(n1151), .B1(n1014), .B2(n1152), .ZN(n1441)
);
OAI22_X1 U492 ( .A1(n85), .A2(n2), .B1(n1081), .B2(n3), .ZN(n1440) );
OAI22_X1 U493 ( .A1(n162), .A2(n1155), .B1(n127), .B2(n1156), .ZN(n1439) );
OAI22_X1 U494 ( .A1(n1443), .A2(n1102), .B1(n1103), .B2(n1436), .ZN(N4588)
);
NOR4_X1 U495 ( .A1(n1448), .A2(n1449), .A3(n1450), .A4(n1451), .ZN(n1447) );
OAI22_X1 U496 ( .A1(n185), .A2(n1112), .B1(n795), .B2(n1113), .ZN(n1451) );
OAI22_X1 U497 ( .A1(n249), .A2(n1114), .B1(n217), .B2(n1115), .ZN(n1450) );
OAI22_X1 U498 ( .A1(n313), .A2(n1116), .B1(n281), .B2(n1117), .ZN(n1449) );
OAI22_X1 U499 ( .A1(n377), .A2(n1118), .B1(n345), .B2(n1119), .ZN(n1448) );
NOR4_X1 U500 ( .A1(n1452), .A2(n1453), .A3(n1454), .A4(n1455), .ZN(n1446) );
OAI22_X1 U501 ( .A1(n442), .A2(n1124), .B1(n409), .B2(n1125), .ZN(n1455) );
OAI22_X1 U502 ( .A1(n509), .A2(n1126), .B1(n475), .B2(n1127), .ZN(n1454) );
OAI22_X1 U503 ( .A1(n576), .A2(n1128), .B1(n542), .B2(n1129), .ZN(n1453) );
OAI22_X1 U504 ( .A1(n643), .A2(n1130), .B1(n610), .B2(n1131), .ZN(n1452) );
NOR4_X1 U505 ( .A1(n1456), .A2(n1457), .A3(n1459), .A4(n1460), .ZN(n1445) );
OAI22_X1 U506 ( .A1(n710), .A2(n1136), .B1(n677), .B2(n1137), .ZN(n1460) );
OAI22_X1 U507 ( .A1(n778), .A2(n1138), .B1(n744), .B2(n1139), .ZN(n1459) );
OAI22_X1 U508 ( .A1(n845), .A2(n1140), .B1(n811), .B2(n1141), .ZN(n1457) );
OAI22_X1 U509 ( .A1(n912), .A2(n1142), .B1(n878), .B2(n1143), .ZN(n1456) );
NOR4_X1 U510 ( .A1(n1461), .A2(n1462), .A3(n1463), .A4(n1464), .ZN(n1444) );
OAI22_X1 U511 ( .A1(n979), .A2(n1148), .B1(n946), .B2(n1149), .ZN(n1464) );
OAI22_X1 U512 ( .A1(n1046), .A2(n1151), .B1(n1013), .B2(n1152), .ZN(n1463)
);
OAI22_X1 U513 ( .A1(n83), .A2(n2), .B1(n1080), .B2(n3), .ZN(n1462) );
OAI22_X1 U514 ( .A1(n161), .A2(n1155), .B1(n126), .B2(n1156), .ZN(n1461) );
OAI22_X1 U515 ( .A1(n1465), .A2(n1102), .B1(n1103), .B2(n1458), .ZN(N4586)
);
NOR4_X1 U516 ( .A1(n1470), .A2(n1471), .A3(n1472), .A4(n1473), .ZN(n1469) );
OAI22_X1 U517 ( .A1(n184), .A2(n1112), .B1(n774), .B2(n1113), .ZN(n1473) );
OAI22_X1 U518 ( .A1(n248), .A2(n1114), .B1(n216), .B2(n1115), .ZN(n1472) );
OAI22_X1 U519 ( .A1(n312), .A2(n1116), .B1(n280), .B2(n1117), .ZN(n1471) );
OAI22_X1 U520 ( .A1(n376), .A2(n1118), .B1(n344), .B2(n1119), .ZN(n1470) );
NOR4_X1 U521 ( .A1(n1474), .A2(n1475), .A3(n1476), .A4(n1477), .ZN(n1468) );
OAI22_X1 U522 ( .A1(n441), .A2(n1124), .B1(n408), .B2(n1125), .ZN(n1477) );
OAI22_X1 U523 ( .A1(n508), .A2(n1126), .B1(n474), .B2(n1127), .ZN(n1476) );
OAI22_X1 U524 ( .A1(n575), .A2(n1128), .B1(n541), .B2(n1129), .ZN(n1475) );
OAI22_X1 U525 ( .A1(n642), .A2(n1130), .B1(n609), .B2(n1131), .ZN(n1474) );
NOR4_X1 U526 ( .A1(n1478), .A2(n1479), .A3(n1481), .A4(n1482), .ZN(n1467) );
OAI22_X1 U527 ( .A1(n709), .A2(n1136), .B1(n676), .B2(n1137), .ZN(n1482) );
OAI22_X1 U528 ( .A1(n777), .A2(n1138), .B1(n743), .B2(n1139), .ZN(n1481) );
OAI22_X1 U529 ( .A1(n844), .A2(n1140), .B1(n810), .B2(n1141), .ZN(n1479) );
OAI22_X1 U530 ( .A1(n911), .A2(n1142), .B1(n877), .B2(n1143), .ZN(n1478) );
NOR4_X1 U531 ( .A1(n1483), .A2(n1484), .A3(n1485), .A4(n1486), .ZN(n1466) );
OAI22_X1 U532 ( .A1(n978), .A2(n1148), .B1(n945), .B2(n1149), .ZN(n1486) );
OAI22_X1 U533 ( .A1(n1045), .A2(n1151), .B1(n1012), .B2(n1152), .ZN(n1485)
);
OAI22_X1 U534 ( .A1(n81), .A2(n2), .B1(n1079), .B2(n3), .ZN(n1484) );
OAI22_X1 U535 ( .A1(n160), .A2(n1155), .B1(n125), .B2(n1156), .ZN(n1483) );
OAI22_X1 U536 ( .A1(n1487), .A2(n1102), .B1(n1103), .B2(n1480), .ZN(N4584)
);
NOR4_X1 U537 ( .A1(n1492), .A2(n1493), .A3(n1494), .A4(n1495), .ZN(n1491) );
OAI22_X1 U538 ( .A1(n183), .A2(n1112), .B1(n753), .B2(n1113), .ZN(n1495) );
OAI22_X1 U539 ( .A1(n247), .A2(n1114), .B1(n215), .B2(n1115), .ZN(n1494) );
OAI22_X1 U540 ( .A1(n311), .A2(n1116), .B1(n279), .B2(n1117), .ZN(n1493) );
OAI22_X1 U541 ( .A1(n375), .A2(n1118), .B1(n343), .B2(n1119), .ZN(n1492) );
NOR4_X1 U542 ( .A1(n1496), .A2(n1497), .A3(n1498), .A4(n1499), .ZN(n1490) );
OAI22_X1 U543 ( .A1(n440), .A2(n1124), .B1(n407), .B2(n1125), .ZN(n1499) );
OAI22_X1 U544 ( .A1(n507), .A2(n1126), .B1(n473), .B2(n1127), .ZN(n1498) );
OAI22_X1 U545 ( .A1(n574), .A2(n1128), .B1(n540), .B2(n1129), .ZN(n1497) );
OAI22_X1 U546 ( .A1(n641), .A2(n1130), .B1(n608), .B2(n1131), .ZN(n1496) );
NOR4_X1 U547 ( .A1(n1500), .A2(n1501), .A3(n1503), .A4(n1504), .ZN(n1489) );
OAI22_X1 U548 ( .A1(n708), .A2(n1136), .B1(n675), .B2(n1137), .ZN(n1504) );
OAI22_X1 U549 ( .A1(n776), .A2(n1138), .B1(n742), .B2(n1139), .ZN(n1503) );
OAI22_X1 U550 ( .A1(n843), .A2(n1140), .B1(n809), .B2(n1141), .ZN(n1501) );
OAI22_X1 U551 ( .A1(n910), .A2(n1142), .B1(n876), .B2(n1143), .ZN(n1500) );
NOR4_X1 U552 ( .A1(n1505), .A2(n1506), .A3(n1507), .A4(n1508), .ZN(n1488) );
OAI22_X1 U553 ( .A1(n977), .A2(n1148), .B1(n944), .B2(n1149), .ZN(n1508) );
OAI22_X1 U554 ( .A1(n1044), .A2(n1151), .B1(n1011), .B2(n1152), .ZN(n1507)
);
OAI22_X1 U555 ( .A1(n79), .A2(n2), .B1(n1078), .B2(n3), .ZN(n1506) );
OAI22_X1 U556 ( .A1(n159), .A2(n1155), .B1(n124), .B2(n1156), .ZN(n1505) );
OAI22_X1 U557 ( .A1(n1509), .A2(n1102), .B1(n1103), .B2(n1502), .ZN(N4582)
);
NOR4_X1 U558 ( .A1(n1514), .A2(n1515), .A3(n1516), .A4(n1517), .ZN(n1513) );
OAI22_X1 U559 ( .A1(n182), .A2(n1112), .B1(n732), .B2(n1113), .ZN(n1517) );
OAI22_X1 U560 ( .A1(n246), .A2(n1114), .B1(n214), .B2(n1115), .ZN(n1516) );
OAI22_X1 U561 ( .A1(n310), .A2(n1116), .B1(n278), .B2(n1117), .ZN(n1515) );
OAI22_X1 U562 ( .A1(n374), .A2(n1118), .B1(n342), .B2(n1119), .ZN(n1514) );
NOR4_X1 U563 ( .A1(n1518), .A2(n1519), .A3(n1520), .A4(n1521), .ZN(n1512) );
OAI22_X1 U564 ( .A1(n439), .A2(n1124), .B1(n406), .B2(n1125), .ZN(n1521) );
OAI22_X1 U565 ( .A1(n506), .A2(n1126), .B1(n472), .B2(n1127), .ZN(n1520) );
OAI22_X1 U566 ( .A1(n573), .A2(n1128), .B1(n539), .B2(n1129), .ZN(n1519) );
OAI22_X1 U567 ( .A1(n640), .A2(n1130), .B1(n607), .B2(n1131), .ZN(n1518) );
NOR4_X1 U568 ( .A1(n1522), .A2(n1523), .A3(n1525), .A4(n1526), .ZN(n1511) );
OAI22_X1 U569 ( .A1(n707), .A2(n1136), .B1(n674), .B2(n1137), .ZN(n1526) );
OAI22_X1 U570 ( .A1(n775), .A2(n1138), .B1(n741), .B2(n1139), .ZN(n1525) );
OAI22_X1 U571 ( .A1(n842), .A2(n1140), .B1(n808), .B2(n1141), .ZN(n1523) );
OAI22_X1 U572 ( .A1(n909), .A2(n1142), .B1(n875), .B2(n1143), .ZN(n1522) );
NOR4_X1 U573 ( .A1(n1527), .A2(n1528), .A3(n1529), .A4(n1530), .ZN(n1510) );
OAI22_X1 U574 ( .A1(n976), .A2(n1148), .B1(n943), .B2(n1149), .ZN(n1530) );
OAI22_X1 U575 ( .A1(n1043), .A2(n1151), .B1(n1010), .B2(n1152), .ZN(n1529)
);
OAI22_X1 U576 ( .A1(n77), .A2(n2), .B1(n1077), .B2(n3), .ZN(n1528) );
OAI22_X1 U577 ( .A1(n158), .A2(n1155), .B1(n123), .B2(n1156), .ZN(n1527) );
OAI22_X1 U578 ( .A1(n1531), .A2(n1102), .B1(n1103), .B2(n1524), .ZN(N4580)
);
NOR4_X1 U579 ( .A1(n1536), .A2(n1537), .A3(n1538), .A4(n1539), .ZN(n1535) );
OAI22_X1 U580 ( .A1(n181), .A2(n1112), .B1(n711), .B2(n1113), .ZN(n1539) );
OAI22_X1 U581 ( .A1(n245), .A2(n1114), .B1(n213), .B2(n1115), .ZN(n1538) );
OAI22_X1 U582 ( .A1(n309), .A2(n1116), .B1(n277), .B2(n1117), .ZN(n1537) );
OAI22_X1 U583 ( .A1(n373), .A2(n1118), .B1(n341), .B2(n1119), .ZN(n1536) );
NOR4_X1 U584 ( .A1(n1540), .A2(n1541), .A3(n1542), .A4(n1543), .ZN(n1534) );
OAI22_X1 U585 ( .A1(n437), .A2(n1124), .B1(n405), .B2(n1125), .ZN(n1543) );
OAI22_X1 U586 ( .A1(n505), .A2(n1126), .B1(n471), .B2(n1127), .ZN(n1542) );
OAI22_X1 U587 ( .A1(n572), .A2(n1128), .B1(n538), .B2(n1129), .ZN(n1541) );
OAI22_X1 U588 ( .A1(n639), .A2(n1130), .B1(n605), .B2(n1131), .ZN(n1540) );
NOR4_X1 U589 ( .A1(n1544), .A2(n1545), .A3(n1547), .A4(n1548), .ZN(n1533) );
OAI22_X1 U590 ( .A1(n706), .A2(n1136), .B1(n673), .B2(n1137), .ZN(n1548) );
OAI22_X1 U591 ( .A1(n773), .A2(n1138), .B1(n740), .B2(n1139), .ZN(n1547) );
OAI22_X1 U592 ( .A1(n841), .A2(n1140), .B1(n807), .B2(n1141), .ZN(n1545) );
OAI22_X1 U593 ( .A1(n908), .A2(n1142), .B1(n874), .B2(n1143), .ZN(n1544) );
NOR4_X1 U594 ( .A1(n1549), .A2(n1550), .A3(n1551), .A4(n1552), .ZN(n1532) );
OAI22_X1 U595 ( .A1(n975), .A2(n1148), .B1(n941), .B2(n1149), .ZN(n1552) );
OAI22_X1 U596 ( .A1(n1042), .A2(n1151), .B1(n1009), .B2(n1152), .ZN(n1551)
);
OAI22_X1 U597 ( .A1(n73), .A2(n2), .B1(n1076), .B2(n3), .ZN(n1550) );
OAI22_X1 U598 ( .A1(n157), .A2(n1155), .B1(n122), .B2(n1156), .ZN(n1549) );
OAI22_X1 U599 ( .A1(n1553), .A2(n1102), .B1(n1103), .B2(n1546), .ZN(N4578)
);
NOR4_X1 U600 ( .A1(n1558), .A2(n1559), .A3(n1560), .A4(n1561), .ZN(n1557) );
OAI22_X1 U601 ( .A1(n180), .A2(n1112), .B1(n690), .B2(n1113), .ZN(n1561) );
OAI22_X1 U602 ( .A1(n244), .A2(n1114), .B1(n212), .B2(n1115), .ZN(n1560) );
OAI22_X1 U603 ( .A1(n308), .A2(n1116), .B1(n276), .B2(n1117), .ZN(n1559) );
OAI22_X1 U604 ( .A1(n372), .A2(n1118), .B1(n340), .B2(n1119), .ZN(n1558) );
NOR4_X1 U605 ( .A1(n1562), .A2(n1563), .A3(n1564), .A4(n1565), .ZN(n1556) );
OAI22_X1 U606 ( .A1(n436), .A2(n1124), .B1(n404), .B2(n1125), .ZN(n1565) );
OAI22_X1 U607 ( .A1(n504), .A2(n1126), .B1(n470), .B2(n1127), .ZN(n1564) );
OAI22_X1 U608 ( .A1(n571), .A2(n1128), .B1(n537), .B2(n1129), .ZN(n1563) );
OAI22_X1 U609 ( .A1(n638), .A2(n1130), .B1(n604), .B2(n1131), .ZN(n1562) );
NOR4_X1 U610 ( .A1(n1566), .A2(n1567), .A3(n1569), .A4(n1570), .ZN(n1555) );
OAI22_X1 U611 ( .A1(n705), .A2(n1136), .B1(n672), .B2(n1137), .ZN(n1570) );
OAI22_X1 U612 ( .A1(n772), .A2(n1138), .B1(n739), .B2(n1139), .ZN(n1569) );
OAI22_X1 U613 ( .A1(n840), .A2(n1140), .B1(n806), .B2(n1141), .ZN(n1567) );
OAI22_X1 U614 ( .A1(n907), .A2(n1142), .B1(n873), .B2(n1143), .ZN(n1566) );
NOR4_X1 U615 ( .A1(n1571), .A2(n1572), .A3(n1573), .A4(n1574), .ZN(n1554) );
OAI22_X1 U616 ( .A1(n974), .A2(n1148), .B1(n940), .B2(n1149), .ZN(n1574) );
OAI22_X1 U617 ( .A1(n1041), .A2(n1151), .B1(n1008), .B2(n1152), .ZN(n1573)
);
OAI22_X1 U618 ( .A1(n71), .A2(n2), .B1(n1075), .B2(n3), .ZN(n1572) );
OAI22_X1 U619 ( .A1(n156), .A2(n1155), .B1(n121), .B2(n1156), .ZN(n1571) );
OAI22_X1 U620 ( .A1(n1575), .A2(n1102), .B1(n1103), .B2(n1568), .ZN(N4576)
);
NOR4_X1 U621 ( .A1(n1580), .A2(n1581), .A3(n1582), .A4(n1583), .ZN(n1579) );
OAI22_X1 U622 ( .A1(n179), .A2(n1112), .B1(n669), .B2(n1113), .ZN(n1583) );
OAI22_X1 U623 ( .A1(n243), .A2(n1114), .B1(n211), .B2(n1115), .ZN(n1582) );
OAI22_X1 U624 ( .A1(n307), .A2(n1116), .B1(n275), .B2(n1117), .ZN(n1581) );
OAI22_X1 U625 ( .A1(n371), .A2(n1118), .B1(n339), .B2(n1119), .ZN(n1580) );
NOR4_X1 U626 ( .A1(n1584), .A2(n1585), .A3(n1586), .A4(n1587), .ZN(n1578) );
OAI22_X1 U627 ( .A1(n435), .A2(n1124), .B1(n403), .B2(n1125), .ZN(n1587) );
OAI22_X1 U628 ( .A1(n503), .A2(n1126), .B1(n469), .B2(n1127), .ZN(n1586) );
OAI22_X1 U629 ( .A1(n570), .A2(n1128), .B1(n536), .B2(n1129), .ZN(n1585) );
OAI22_X1 U630 ( .A1(n637), .A2(n1130), .B1(n603), .B2(n1131), .ZN(n1584) );
NOR4_X1 U631 ( .A1(n1588), .A2(n1589), .A3(n1591), .A4(n1592), .ZN(n1577) );
OAI22_X1 U632 ( .A1(n704), .A2(n1136), .B1(n671), .B2(n1137), .ZN(n1592) );
OAI22_X1 U633 ( .A1(n771), .A2(n1138), .B1(n738), .B2(n1139), .ZN(n1591) );
OAI22_X1 U634 ( .A1(n839), .A2(n1140), .B1(n805), .B2(n1141), .ZN(n1589) );
OAI22_X1 U635 ( .A1(n906), .A2(n1), .B1(n872), .B2(n1143), .ZN(n1588) );
NOR4_X1 U636 ( .A1(n1593), .A2(n1594), .A3(n1595), .A4(n1596), .ZN(n1576) );
OAI22_X1 U637 ( .A1(n973), .A2(n1148), .B1(n939), .B2(n1149), .ZN(n1596) );
OAI22_X1 U638 ( .A1(n1040), .A2(n1151), .B1(n1007), .B2(n1152), .ZN(n1595)
);
OAI22_X1 U639 ( .A1(n69), .A2(n2), .B1(n1074), .B2(n1154), .ZN(n1594) );
OAI22_X1 U640 ( .A1(n155), .A2(n1155), .B1(n119), .B2(n1156), .ZN(n1593) );
OAI22_X1 U641 ( .A1(n1597), .A2(n1102), .B1(n1103), .B2(n1590), .ZN(N4574)
);
NOR4_X1 U642 ( .A1(n1602), .A2(n1603), .A3(n1604), .A4(n1605), .ZN(n1601) );
OAI22_X1 U643 ( .A1(n178), .A2(n1112), .B1(n648), .B2(n1113), .ZN(n1605) );
OAI22_X1 U644 ( .A1(n242), .A2(n1114), .B1(n210), .B2(n1115), .ZN(n1604) );
OAI22_X1 U645 ( .A1(n306), .A2(n1116), .B1(n274), .B2(n1117), .ZN(n1603) );
OAI22_X1 U646 ( .A1(n370), .A2(n1118), .B1(n338), .B2(n1119), .ZN(n1602) );
NOR4_X1 U647 ( .A1(n1606), .A2(n1607), .A3(n1608), .A4(n1609), .ZN(n1600) );
OAI22_X1 U648 ( .A1(n434), .A2(n1124), .B1(n402), .B2(n1125), .ZN(n1609) );
OAI22_X1 U649 ( .A1(n502), .A2(n1126), .B1(n468), .B2(n1127), .ZN(n1608) );
OAI22_X1 U650 ( .A1(n569), .A2(n1128), .B1(n535), .B2(n1129), .ZN(n1607) );
OAI22_X1 U651 ( .A1(n636), .A2(n1130), .B1(n602), .B2(n1131), .ZN(n1606) );
NOR4_X1 U652 ( .A1(n1610), .A2(n1611), .A3(n1613), .A4(n1614), .ZN(n1599) );
OAI22_X1 U653 ( .A1(n703), .A2(n1136), .B1(n670), .B2(n1137), .ZN(n1614) );
OAI22_X1 U654 ( .A1(n770), .A2(n1138), .B1(n737), .B2(n1139), .ZN(n1613) );
OAI22_X1 U655 ( .A1(n838), .A2(n1140), .B1(n804), .B2(n1141), .ZN(n1611) );
OAI22_X1 U656 ( .A1(n905), .A2(n1), .B1(n871), .B2(n1143), .ZN(n1610) );
NOR4_X1 U657 ( .A1(n1615), .A2(n1616), .A3(n1617), .A4(n1618), .ZN(n1598) );
OAI22_X1 U658 ( .A1(n972), .A2(n1148), .B1(n938), .B2(n1149), .ZN(n1618) );
OAI22_X1 U659 ( .A1(n1039), .A2(n1151), .B1(n1006), .B2(n1152), .ZN(n1617)
);
OAI22_X1 U660 ( .A1(n67), .A2(n2), .B1(n1073), .B2(n1154), .ZN(n1616) );
OAI22_X1 U661 ( .A1(n154), .A2(n1155), .B1(n118), .B2(n1156), .ZN(n1615) );
OAI22_X1 U662 ( .A1(n1619), .A2(n1102), .B1(n1103), .B2(n1612), .ZN(N4572)
);
NOR4_X1 U663 ( .A1(n1624), .A2(n1625), .A3(n1626), .A4(n1627), .ZN(n1623) );
OAI22_X1 U664 ( .A1(n175), .A2(n1112), .B1(n627), .B2(n1113), .ZN(n1627) );
OAI22_X1 U665 ( .A1(n241), .A2(n1114), .B1(n209), .B2(n1115), .ZN(n1626) );
OAI22_X1 U666 ( .A1(n305), .A2(n1116), .B1(n273), .B2(n1117), .ZN(n1625) );
OAI22_X1 U667 ( .A1(n369), .A2(n1118), .B1(n337), .B2(n1119), .ZN(n1624) );
NOR4_X1 U668 ( .A1(n1628), .A2(n1629), .A3(n1630), .A4(n1631), .ZN(n1622) );
OAI22_X1 U669 ( .A1(n433), .A2(n1124), .B1(n401), .B2(n1125), .ZN(n1631) );
OAI22_X1 U670 ( .A1(n500), .A2(n1126), .B1(n467), .B2(n1127), .ZN(n1630) );
OAI22_X1 U671 ( .A1(n568), .A2(n1128), .B1(n534), .B2(n1129), .ZN(n1629) );
OAI22_X1 U672 ( .A1(n635), .A2(n1130), .B1(n601), .B2(n1131), .ZN(n1628) );
NOR4_X1 U673 ( .A1(n1632), .A2(n1633), .A3(n1635), .A4(n1636), .ZN(n1621) );
OAI22_X1 U674 ( .A1(n702), .A2(n1136), .B1(n668), .B2(n1137), .ZN(n1636) );
OAI22_X1 U675 ( .A1(n769), .A2(n1138), .B1(n736), .B2(n1139), .ZN(n1635) );
OAI22_X1 U676 ( .A1(n836), .A2(n1140), .B1(n803), .B2(n1141), .ZN(n1633) );
OAI22_X1 U677 ( .A1(n904), .A2(n1), .B1(n870), .B2(n1143), .ZN(n1632) );
NOR4_X1 U678 ( .A1(n1637), .A2(n1638), .A3(n1639), .A4(n1640), .ZN(n1620) );
OAI22_X1 U679 ( .A1(n971), .A2(n1148), .B1(n937), .B2(n1149), .ZN(n1640) );
OAI22_X1 U680 ( .A1(n1038), .A2(n1151), .B1(n1004), .B2(n1152), .ZN(n1639)
);
OAI22_X1 U681 ( .A1(n65), .A2(n2), .B1(n1072), .B2(n1154), .ZN(n1638) );
OAI22_X1 U682 ( .A1(n152), .A2(n1155), .B1(n117), .B2(n1156), .ZN(n1637) );
OAI22_X1 U683 ( .A1(n1641), .A2(n1102), .B1(n1103), .B2(n1634), .ZN(N4570)
);
NOR4_X1 U684 ( .A1(n1646), .A2(n1647), .A3(n1648), .A4(n1649), .ZN(n1645) );
OAI22_X1 U685 ( .A1(n164), .A2(n1112), .B1(n606), .B2(n1113), .ZN(n1649) );
OAI22_X1 U686 ( .A1(n240), .A2(n1114), .B1(n208), .B2(n1115), .ZN(n1648) );
OAI22_X1 U687 ( .A1(n304), .A2(n1116), .B1(n272), .B2(n1117), .ZN(n1647) );
OAI22_X1 U688 ( .A1(n368), .A2(n1118), .B1(n336), .B2(n1119), .ZN(n1646) );
NOR4_X1 U689 ( .A1(n1650), .A2(n1651), .A3(n1652), .A4(n1653), .ZN(n1644) );
OAI22_X1 U690 ( .A1(n432), .A2(n1124), .B1(n400), .B2(n1125), .ZN(n1653) );
OAI22_X1 U691 ( .A1(n499), .A2(n1126), .B1(n466), .B2(n1127), .ZN(n1652) );
OAI22_X1 U692 ( .A1(n567), .A2(n1128), .B1(n533), .B2(n1129), .ZN(n1651) );
OAI22_X1 U693 ( .A1(n634), .A2(n1130), .B1(n600), .B2(n1131), .ZN(n1650) );
NOR4_X1 U694 ( .A1(n1654), .A2(n1655), .A3(n1657), .A4(n1658), .ZN(n1643) );
OAI22_X1 U695 ( .A1(n701), .A2(n1136), .B1(n667), .B2(n1137), .ZN(n1658) );
OAI22_X1 U696 ( .A1(n768), .A2(n1138), .B1(n735), .B2(n1139), .ZN(n1657) );
OAI22_X1 U697 ( .A1(n835), .A2(n1140), .B1(n802), .B2(n1141), .ZN(n1655) );
OAI22_X1 U698 ( .A1(n903), .A2(n1), .B1(n869), .B2(n1143), .ZN(n1654) );
NOR4_X1 U699 ( .A1(n1659), .A2(n1660), .A3(n1661), .A4(n1662), .ZN(n1642) );
OAI22_X1 U700 ( .A1(n970), .A2(n1148), .B1(n936), .B2(n1149), .ZN(n1662) );
OAI22_X1 U701 ( .A1(n1037), .A2(n1151), .B1(n1003), .B2(n1152), .ZN(n1661)
);
OAI22_X1 U702 ( .A1(n63), .A2(n2), .B1(n1071), .B2(n1154), .ZN(n1660) );
OAI22_X1 U703 ( .A1(n151), .A2(n1155), .B1(n116), .B2(n37), .ZN(n1659) );
OAI22_X1 U704 ( .A1(n1663), .A2(n1102), .B1(n1103), .B2(n1656), .ZN(N4568)
);
NOR4_X1 U705 ( .A1(n1668), .A2(n1669), .A3(n1670), .A4(n1671), .ZN(n1667) );
OAI22_X1 U706 ( .A1(n153), .A2(n1112), .B1(n585), .B2(n1113), .ZN(n1671) );
OAI22_X1 U707 ( .A1(n239), .A2(n1114), .B1(n207), .B2(n1115), .ZN(n1670) );
OAI22_X1 U708 ( .A1(n303), .A2(n1116), .B1(n271), .B2(n1117), .ZN(n1669) );
OAI22_X1 U709 ( .A1(n367), .A2(n1118), .B1(n335), .B2(n1119), .ZN(n1668) );
NOR4_X1 U710 ( .A1(n1672), .A2(n1673), .A3(n1674), .A4(n1675), .ZN(n1666) );
OAI22_X1 U711 ( .A1(n431), .A2(n1124), .B1(n399), .B2(n1125), .ZN(n1675) );
OAI22_X1 U712 ( .A1(n498), .A2(n1126), .B1(n465), .B2(n1127), .ZN(n1674) );
OAI22_X1 U713 ( .A1(n566), .A2(n1128), .B1(n532), .B2(n1129), .ZN(n1673) );
OAI22_X1 U714 ( .A1(n633), .A2(n1130), .B1(n599), .B2(n1131), .ZN(n1672) );
NOR4_X1 U715 ( .A1(n1676), .A2(n1677), .A3(n1679), .A4(n1680), .ZN(n1665) );
OAI22_X1 U716 ( .A1(n700), .A2(n1136), .B1(n666), .B2(n1137), .ZN(n1680) );
OAI22_X1 U717 ( .A1(n767), .A2(n1138), .B1(n734), .B2(n1139), .ZN(n1679) );
OAI22_X1 U718 ( .A1(n834), .A2(n1140), .B1(n801), .B2(n1141), .ZN(n1677) );
OAI22_X1 U719 ( .A1(n902), .A2(n1), .B1(n868), .B2(n1143), .ZN(n1676) );
NOR4_X1 U720 ( .A1(n1681), .A2(n1682), .A3(n1683), .A4(n1684), .ZN(n1664) );
OAI22_X1 U721 ( .A1(n969), .A2(n1148), .B1(n935), .B2(n1149), .ZN(n1684) );
OAI22_X1 U722 ( .A1(n1036), .A2(n1151), .B1(n1002), .B2(n1152), .ZN(n1683)
);
OAI22_X1 U723 ( .A1(n61), .A2(n2), .B1(n1070), .B2(n1154), .ZN(n1682) );
OAI22_X1 U724 ( .A1(n150), .A2(n1155), .B1(n115), .B2(n1156), .ZN(n1681) );
OAI22_X1 U725 ( .A1(n1685), .A2(n1102), .B1(n1103), .B2(n1678), .ZN(N4566)
);
NOR4_X1 U726 ( .A1(n1690), .A2(n1691), .A3(n1692), .A4(n1693), .ZN(n1689) );
OAI22_X1 U727 ( .A1(n142), .A2(n1112), .B1(n564), .B2(n1113), .ZN(n1693) );
OAI22_X1 U728 ( .A1(n238), .A2(n1114), .B1(n206), .B2(n1115), .ZN(n1692) );
OAI22_X1 U729 ( .A1(n302), .A2(n1116), .B1(n270), .B2(n1117), .ZN(n1691) );
OAI22_X1 U730 ( .A1(n366), .A2(n1118), .B1(n334), .B2(n1119), .ZN(n1690) );
NOR4_X1 U731 ( .A1(n1694), .A2(n1695), .A3(n1696), .A4(n1697), .ZN(n1688) );
OAI22_X1 U732 ( .A1(n430), .A2(n1124), .B1(n398), .B2(n1125), .ZN(n1697) );
OAI22_X1 U733 ( .A1(n497), .A2(n1126), .B1(n464), .B2(n1127), .ZN(n1696) );
OAI22_X1 U734 ( .A1(n565), .A2(n1128), .B1(n531), .B2(n1129), .ZN(n1695) );
OAI22_X1 U735 ( .A1(n632), .A2(n1130), .B1(n598), .B2(n1131), .ZN(n1694) );
NOR4_X1 U736 ( .A1(n1698), .A2(n1699), .A3(n1701), .A4(n1702), .ZN(n1687) );
OAI22_X1 U737 ( .A1(n699), .A2(n1136), .B1(n665), .B2(n1137), .ZN(n1702) );
OAI22_X1 U738 ( .A1(n766), .A2(n1138), .B1(n733), .B2(n1139), .ZN(n1701) );
OAI22_X1 U739 ( .A1(n833), .A2(n1140), .B1(n800), .B2(n1141), .ZN(n1699) );
OAI22_X1 U740 ( .A1(n901), .A2(n1), .B1(n867), .B2(n1143), .ZN(n1698) );
NOR4_X1 U741 ( .A1(n1703), .A2(n1704), .A3(n1705), .A4(n1706), .ZN(n1686) );
OAI22_X1 U742 ( .A1(n968), .A2(n1148), .B1(n934), .B2(n1149), .ZN(n1706) );
OAI22_X1 U743 ( .A1(n1035), .A2(n1151), .B1(n1001), .B2(n1152), .ZN(n1705)
);
OAI22_X1 U744 ( .A1(n59), .A2(n1153), .B1(n1069), .B2(n1154), .ZN(n1704) );
OAI22_X1 U745 ( .A1(n149), .A2(n1155), .B1(n114), .B2(n37), .ZN(n1703) );
OAI22_X1 U746 ( .A1(n1707), .A2(n1102), .B1(n1103), .B2(n1700), .ZN(N4564)
);
NOR4_X1 U747 ( .A1(n1712), .A2(n1713), .A3(n1714), .A4(n1715), .ZN(n1711) );
OAI22_X1 U748 ( .A1(n131), .A2(n1112), .B1(n543), .B2(n1113), .ZN(n1715) );
OAI22_X1 U749 ( .A1(n237), .A2(n1114), .B1(n205), .B2(n1115), .ZN(n1714) );
OAI22_X1 U750 ( .A1(n301), .A2(n1116), .B1(n269), .B2(n1117), .ZN(n1713) );
OAI22_X1 U751 ( .A1(n365), .A2(n1118), .B1(n333), .B2(n1119), .ZN(n1712) );
NOR4_X1 U752 ( .A1(n1716), .A2(n1717), .A3(n1718), .A4(n1719), .ZN(n1710) );
OAI22_X1 U753 ( .A1(n429), .A2(n1124), .B1(n397), .B2(n1125), .ZN(n1719) );
OAI22_X1 U754 ( .A1(n496), .A2(n1126), .B1(n463), .B2(n1127), .ZN(n1718) );
OAI22_X1 U755 ( .A1(n563), .A2(n1128), .B1(n530), .B2(n1129), .ZN(n1717) );
OAI22_X1 U756 ( .A1(n631), .A2(n1130), .B1(n597), .B2(n1131), .ZN(n1716) );
NOR4_X1 U757 ( .A1(n1720), .A2(n1721), .A3(n1723), .A4(n1724), .ZN(n1709) );
OAI22_X1 U758 ( .A1(n698), .A2(n1136), .B1(n664), .B2(n1137), .ZN(n1724) );
OAI22_X1 U759 ( .A1(n765), .A2(n1138), .B1(n731), .B2(n1139), .ZN(n1723) );
OAI22_X1 U760 ( .A1(n832), .A2(n1140), .B1(n799), .B2(n1141), .ZN(n1721) );
OAI22_X1 U761 ( .A1(n899), .A2(n1), .B1(n866), .B2(n1143), .ZN(n1720) );
NOR4_X1 U762 ( .A1(n1725), .A2(n1726), .A3(n1727), .A4(n1728), .ZN(n1708) );
OAI22_X1 U763 ( .A1(n967), .A2(n1148), .B1(n933), .B2(n1149), .ZN(n1728) );
OAI22_X1 U764 ( .A1(n1034), .A2(n1151), .B1(n1000), .B2(n1152), .ZN(n1727)
);
OAI22_X1 U765 ( .A1(n57), .A2(n1153), .B1(n1067), .B2(n1154), .ZN(n1726) );
OAI22_X1 U766 ( .A1(n148), .A2(n1155), .B1(n113), .B2(n1156), .ZN(n1725) );
OAI22_X1 U767 ( .A1(n1729), .A2(n1102), .B1(n1103), .B2(n1722), .ZN(N4562)
);
NOR4_X1 U768 ( .A1(n1734), .A2(n1735), .A3(n1736), .A4(n1737), .ZN(n1733) );
OAI22_X1 U769 ( .A1(n120), .A2(n1112), .B1(n522), .B2(n1113), .ZN(n1737) );
OAI22_X1 U770 ( .A1(n236), .A2(n1114), .B1(n204), .B2(n1115), .ZN(n1736) );
OAI22_X1 U771 ( .A1(n300), .A2(n1116), .B1(n268), .B2(n1117), .ZN(n1735) );
OAI22_X1 U772 ( .A1(n364), .A2(n1118), .B1(n332), .B2(n1119), .ZN(n1734) );
NOR4_X1 U773 ( .A1(n1738), .A2(n1739), .A3(n1740), .A4(n1741), .ZN(n1732) );
OAI22_X1 U774 ( .A1(n428), .A2(n1124), .B1(n396), .B2(n1125), .ZN(n1741) );
OAI22_X1 U775 ( .A1(n495), .A2(n1126), .B1(n462), .B2(n1127), .ZN(n1740) );
OAI22_X1 U776 ( .A1(n562), .A2(n1128), .B1(n529), .B2(n1129), .ZN(n1739) );
OAI22_X1 U777 ( .A1(n630), .A2(n1130), .B1(n596), .B2(n1131), .ZN(n1738) );
NOR4_X1 U778 ( .A1(n1742), .A2(n1743), .A3(n1745), .A4(n1746), .ZN(n1731) );
OAI22_X1 U779 ( .A1(n697), .A2(n1136), .B1(n663), .B2(n1137), .ZN(n1746) );
OAI22_X1 U780 ( .A1(n764), .A2(n1138), .B1(n730), .B2(n1139), .ZN(n1745) );
OAI22_X1 U781 ( .A1(n831), .A2(n1140), .B1(n798), .B2(n1141), .ZN(n1743) );
OAI22_X1 U782 ( .A1(n898), .A2(n1), .B1(n865), .B2(n1143), .ZN(n1742) );
NOR4_X1 U783 ( .A1(n1747), .A2(n1748), .A3(n1749), .A4(n1750), .ZN(n1730) );
OAI22_X1 U784 ( .A1(n966), .A2(n1148), .B1(n932), .B2(n1149), .ZN(n1750) );
OAI22_X1 U785 ( .A1(n1033), .A2(n1151), .B1(n999), .B2(n1152), .ZN(n1749) );
OAI22_X1 U786 ( .A1(n55), .A2(n1153), .B1(n1066), .B2(n1154), .ZN(n1748) );
OAI22_X1 U787 ( .A1(n147), .A2(n1155), .B1(n112), .B2(n1156), .ZN(n1747) );
OAI22_X1 U788 ( .A1(n1751), .A2(n1102), .B1(n1744), .B2(n1103), .ZN(N4560)
);
NOR4_X1 U789 ( .A1(n1752), .A2(n1753), .A3(n1754), .A4(n1755), .ZN(n1751) );
OAI211_X1 U790 ( .C1(n1100), .C2(n1153), .A(n1756), .B(n1757), .ZN(n1755) );
NOR4_X1 U791 ( .A1(n1758), .A2(n1759), .A3(n1760), .A4(n1761), .ZN(n1757) );
OAI22_X1 U792 ( .A1(n109), .A2(n1112), .B1(n203), .B2(n1115), .ZN(n1761) );
OAI22_X1 U793 ( .A1(n235), .A2(n1114), .B1(n267), .B2(n1117), .ZN(n1760) );
OAI22_X1 U794 ( .A1(n299), .A2(n1116), .B1(n331), .B2(n1119), .ZN(n1759) );
OAI22_X1 U795 ( .A1(n363), .A2(n1118), .B1(n395), .B2(n1125), .ZN(n1758) );
NOR4_X1 U796 ( .A1(n1762), .A2(n1763), .A3(n1764), .A4(n1765), .ZN(n1756) );
OAI22_X1 U797 ( .A1(n427), .A2(n1124), .B1(n461), .B2(n1127), .ZN(n1765) );
OAI22_X1 U798 ( .A1(n494), .A2(n1126), .B1(n528), .B2(n1129), .ZN(n1764) );
OAI22_X1 U799 ( .A1(n561), .A2(n1128), .B1(n595), .B2(n1131), .ZN(n1763) );
OAI22_X1 U800 ( .A1(n629), .A2(n1130), .B1(n662), .B2(n1137), .ZN(n1762) );
OAI211_X1 U801 ( .C1(n146), .C2(n1155), .A(n1767), .B(n1768), .ZN(n1754) );
NOR4_X1 U802 ( .A1(n1769), .A2(n1770), .A3(n1771), .A4(n1772), .ZN(n1768) );
OAI22_X1 U803 ( .A1(n763), .A2(n1138), .B1(n797), .B2(n1141), .ZN(n1772) );
OAI22_X1 U804 ( .A1(n696), .A2(n1136), .B1(n729), .B2(n1139), .ZN(n1771) );
OAI22_X1 U805 ( .A1(n897), .A2(n1), .B1(n931), .B2(n1149), .ZN(n1770) );
OAI22_X1 U806 ( .A1(n830), .A2(n1140), .B1(n864), .B2(n1143), .ZN(n1769) );
OAI22_X1 U807 ( .A1(n1113), .A2(n501), .B1(n37), .B2(n111), .ZN(n1773) );
OAI22_X1 U808 ( .A1(n1032), .A2(n1151), .B1(n1065), .B2(n1154), .ZN(n1753)
);
OAI22_X1 U809 ( .A1(n965), .A2(n1148), .B1(n998), .B2(n1152), .ZN(n1752) );
OAI22_X1 U810 ( .A1(n1774), .A2(n1102), .B1(n1103), .B2(n1766), .ZN(N4558)
);
NOR4_X1 U811 ( .A1(n1779), .A2(n1780), .A3(n1781), .A4(n1782), .ZN(n1778) );
OAI22_X1 U812 ( .A1(n97), .A2(n1112), .B1(n480), .B2(n1113), .ZN(n1782) );
OAI22_X1 U813 ( .A1(n234), .A2(n1114), .B1(n202), .B2(n1115), .ZN(n1781) );
OAI22_X1 U814 ( .A1(n298), .A2(n1116), .B1(n266), .B2(n1117), .ZN(n1780) );
OAI22_X1 U815 ( .A1(n362), .A2(n1118), .B1(n330), .B2(n1119), .ZN(n1779) );
NOR4_X1 U816 ( .A1(n1783), .A2(n1784), .A3(n1785), .A4(n1786), .ZN(n1777) );
OAI22_X1 U817 ( .A1(n426), .A2(n1124), .B1(n394), .B2(n1125), .ZN(n1786) );
OAI22_X1 U818 ( .A1(n493), .A2(n1126), .B1(n460), .B2(n1127), .ZN(n1785) );
OAI22_X1 U819 ( .A1(n560), .A2(n1128), .B1(n527), .B2(n1129), .ZN(n1784) );
OAI22_X1 U820 ( .A1(n628), .A2(n1130), .B1(n594), .B2(n1131), .ZN(n1783) );
NOR4_X1 U821 ( .A1(n1787), .A2(n1789), .A3(n1790), .A4(n1791), .ZN(n1776) );
OAI22_X1 U822 ( .A1(n695), .A2(n1136), .B1(n661), .B2(n1137), .ZN(n1791) );
OAI22_X1 U823 ( .A1(n762), .A2(n1138), .B1(n728), .B2(n1139), .ZN(n1790) );
OAI22_X1 U824 ( .A1(n829), .A2(n1140), .B1(n796), .B2(n1141), .ZN(n1789) );
OAI22_X1 U825 ( .A1(n896), .A2(n1), .B1(n863), .B2(n1143), .ZN(n1787) );
NOR4_X1 U826 ( .A1(n1792), .A2(n1793), .A3(n1794), .A4(n1795), .ZN(n1775) );
OAI22_X1 U827 ( .A1(n964), .A2(n1148), .B1(n930), .B2(n1149), .ZN(n1795) );
OAI22_X1 U828 ( .A1(n1031), .A2(n1151), .B1(n997), .B2(n1152), .ZN(n1794) );
OAI22_X1 U829 ( .A1(n1099), .A2(n1153), .B1(n1064), .B2(n1154), .ZN(n1793)
);
OAI22_X1 U830 ( .A1(n145), .A2(n1155), .B1(n110), .B2(n1156), .ZN(n1792) );
OAI22_X1 U831 ( .A1(n1796), .A2(n1102), .B1(n1103), .B2(n1788), .ZN(N4556)
);
NOR4_X1 U832 ( .A1(n1801), .A2(n1802), .A3(n1803), .A4(n1804), .ZN(n1800) );
OAI22_X1 U833 ( .A1(n75), .A2(n1112), .B1(n459), .B2(n1113), .ZN(n1804) );
OAI22_X1 U834 ( .A1(n233), .A2(n1114), .B1(n201), .B2(n1115), .ZN(n1803) );
OAI22_X1 U835 ( .A1(n297), .A2(n1116), .B1(n265), .B2(n1117), .ZN(n1802) );
OAI22_X1 U836 ( .A1(n361), .A2(n1118), .B1(n329), .B2(n1119), .ZN(n1801) );
NOR4_X1 U837 ( .A1(n1805), .A2(n1806), .A3(n1807), .A4(n1808), .ZN(n1799) );
OAI22_X1 U838 ( .A1(n425), .A2(n1124), .B1(n393), .B2(n1125), .ZN(n1808) );
OAI22_X1 U839 ( .A1(n492), .A2(n1126), .B1(n458), .B2(n1127), .ZN(n1807) );
OAI22_X1 U840 ( .A1(n559), .A2(n1128), .B1(n526), .B2(n1129), .ZN(n1806) );
OAI22_X1 U841 ( .A1(n626), .A2(n1130), .B1(n593), .B2(n1131), .ZN(n1805) );
NOR4_X1 U842 ( .A1(n1809), .A2(n1811), .A3(n1812), .A4(n1813), .ZN(n1798) );
OAI22_X1 U843 ( .A1(n694), .A2(n1136), .B1(n660), .B2(n1137), .ZN(n1813) );
OAI22_X1 U844 ( .A1(n761), .A2(n1138), .B1(n727), .B2(n1139), .ZN(n1812) );
OAI22_X1 U845 ( .A1(n828), .A2(n1140), .B1(n794), .B2(n1141), .ZN(n1811) );
OAI22_X1 U846 ( .A1(n895), .A2(n1), .B1(n862), .B2(n1143), .ZN(n1809) );
NOR4_X1 U847 ( .A1(n1814), .A2(n1815), .A3(n1816), .A4(n1817), .ZN(n1797) );
OAI22_X1 U848 ( .A1(n962), .A2(n1148), .B1(n929), .B2(n1149), .ZN(n1817) );
OAI22_X1 U849 ( .A1(n1030), .A2(n1151), .B1(n996), .B2(n1152), .ZN(n1816) );
OAI22_X1 U850 ( .A1(n1098), .A2(n1153), .B1(n1063), .B2(n1154), .ZN(n1815)
);
OAI22_X1 U851 ( .A1(n144), .A2(n1155), .B1(n108), .B2(n1156), .ZN(n1814) );
OAI22_X1 U852 ( .A1(n1818), .A2(n1102), .B1(n1103), .B2(n1810), .ZN(N4554)
);
OAI221_X1 U853 ( .B1(n1825), .B2(ADD_RD2[2]), .C1(n1826), .C2(ADD_RD2[0]),
.A(n1827), .ZN(n1824) );
AOI22_X1 U854 ( .A1(n1825), .A2(ADD_RD2[2]), .B1(n1826), .B2(ADD_RD2[0]),
.ZN(n1827) );
AOI221_X1 U855 ( .B1(n1828), .B2(ADD_WR[4]), .C1(n1829), .C2(ADD_RD2[3]),
.A(n1830), .ZN(n1820) );
OAI22_X1 U856 ( .A1(ADD_WR[4]), .A2(n1828), .B1(n1829), .B2(ADD_RD2[3]),
.ZN(n1830) );
NOR4_X1 U857 ( .A1(n1835), .A2(n1836), .A3(n1837), .A4(n1838), .ZN(n1834) );
OAI22_X1 U858 ( .A1(n53), .A2(n1112), .B1(n438), .B2(n1113), .ZN(n1838) );
OAI22_X1 U859 ( .A1(n232), .A2(n1114), .B1(n200), .B2(n1115), .ZN(n1837) );
OAI22_X1 U860 ( .A1(n296), .A2(n1116), .B1(n264), .B2(n1117), .ZN(n1836) );
OAI22_X1 U861 ( .A1(n360), .A2(n1118), .B1(n328), .B2(n1119), .ZN(n1835) );
NOR3_X1 U862 ( .A1(n1828), .A2(n1845), .A3(n1846), .ZN(n1840) );
NAND2_X1 U863 ( .A1(ADD_RD2[4]), .A2(ADD_RD2[3]), .ZN(n1847) );
NOR4_X1 U864 ( .A1(n1848), .A2(n1849), .A3(n1850), .A4(n1851), .ZN(n1833) );
OAI22_X1 U865 ( .A1(n424), .A2(n1124), .B1(n392), .B2(n1125), .ZN(n1851) );
OAI22_X1 U866 ( .A1(n491), .A2(n1126), .B1(n457), .B2(n1127), .ZN(n1850) );
OAI22_X1 U867 ( .A1(n558), .A2(n1128), .B1(n525), .B2(n1129), .ZN(n1849) );
OAI22_X1 U868 ( .A1(n625), .A2(n1130), .B1(n592), .B2(n1131), .ZN(n1848) );
NOR3_X1 U869 ( .A1(ADD_RD2[3]), .A2(n1828), .A3(n1846), .ZN(n1852) );
NOR3_X1 U870 ( .A1(ADD_RD2[3]), .A2(ADD_RD2[0]), .A3(n1828), .ZN(n1853) );
NOR4_X1 U871 ( .A1(n1854), .A2(n1855), .A3(n1856), .A4(n1857), .ZN(n1832) );
OAI22_X1 U872 ( .A1(n693), .A2(n1136), .B1(n659), .B2(n1137), .ZN(n1857) );
OAI22_X1 U873 ( .A1(n760), .A2(n1138), .B1(n726), .B2(n1139), .ZN(n1856) );
OAI22_X1 U874 ( .A1(n827), .A2(n1140), .B1(n793), .B2(n1141), .ZN(n1855) );
OAI22_X1 U875 ( .A1(n894), .A2(n1), .B1(n861), .B2(n1143), .ZN(n1854) );
NOR3_X1 U876 ( .A1(ADD_RD2[4]), .A2(n1845), .A3(n1846), .ZN(n1858) );
NAND2_X1 U877 ( .A1(n1844), .A2(n1859), .ZN(n1142) );
NOR3_X1 U878 ( .A1(ADD_RD2[4]), .A2(ADD_RD2[0]), .A3(n1845), .ZN(n1859) );
NOR4_X1 U879 ( .A1(n1860), .A2(n1861), .A3(n1862), .A4(n1863), .ZN(n1831) );
OAI22_X1 U880 ( .A1(n961), .A2(n1148), .B1(n928), .B2(n1149), .ZN(n1863) );
OAI22_X1 U881 ( .A1(n1029), .A2(n1151), .B1(n995), .B2(n1152), .ZN(n1862) );
OAI22_X1 U882 ( .A1(n1097), .A2(n1153), .B1(n1062), .B2(n1154), .ZN(n1861)
);
NAND2_X1 U883 ( .A1(n1843), .A2(n1864), .ZN(n1154) );
NAND2_X1 U884 ( .A1(n1865), .A2(n1843), .ZN(n1153) );
OAI22_X1 U885 ( .A1(n143), .A2(n1155), .B1(n107), .B2(n37), .ZN(n1860) );
NAND2_X1 U886 ( .A1(n1844), .A2(n1864), .ZN(n1156) );
NOR3_X1 U887 ( .A1(ADD_RD2[4]), .A2(ADD_RD2[3]), .A3(n1846), .ZN(n1864) );
NOR3_X1 U888 ( .A1(ADD_RD2[4]), .A2(ADD_RD2[3]), .A3(ADD_RD2[0]), .ZN(n1865)
);
OAI22_X1 U889 ( .A1(n1866), .A2(n1867), .B1(n1868), .B2(n1094), .ZN(N4552)
);
NOR4_X1 U890 ( .A1(n1873), .A2(n1874), .A3(n1875), .A4(n1876), .ZN(n1872) );
OAI22_X1 U891 ( .A1(n199), .A2(n1877), .B1(n1089), .B2(n1878), .ZN(n1876) );
OAI22_X1 U892 ( .A1(n263), .A2(n1879), .B1(n231), .B2(n1880), .ZN(n1875) );
OAI22_X1 U893 ( .A1(n327), .A2(n1881), .B1(n295), .B2(n1882), .ZN(n1874) );
OAI22_X1 U894 ( .A1(n391), .A2(n1883), .B1(n359), .B2(n1884), .ZN(n1873) );
NOR4_X1 U895 ( .A1(n1885), .A2(n1886), .A3(n1887), .A4(n1888), .ZN(n1871) );
OAI22_X1 U896 ( .A1(n456), .A2(n1889), .B1(n423), .B2(n1890), .ZN(n1888) );
OAI22_X1 U897 ( .A1(n524), .A2(n1891), .B1(n490), .B2(n1892), .ZN(n1887) );
OAI22_X1 U898 ( .A1(n591), .A2(n1893), .B1(n557), .B2(n1894), .ZN(n1886) );
OAI22_X1 U899 ( .A1(n658), .A2(n1895), .B1(n624), .B2(n1896), .ZN(n1885) );
NOR4_X1 U900 ( .A1(n1897), .A2(n1898), .A3(n1899), .A4(n1900), .ZN(n1870) );
OAI22_X1 U901 ( .A1(n725), .A2(n1901), .B1(n692), .B2(n1902), .ZN(n1900) );
OAI22_X1 U902 ( .A1(n792), .A2(n1903), .B1(n759), .B2(n1904), .ZN(n1899) );
OAI22_X1 U903 ( .A1(n860), .A2(n1905), .B1(n826), .B2(n1906), .ZN(n1898) );
OAI22_X1 U904 ( .A1(n927), .A2(n1907), .B1(n893), .B2(n1908), .ZN(n1897) );
NOR4_X1 U905 ( .A1(n1909), .A2(n1910), .A3(n1911), .A4(n1912), .ZN(n1869) );
OAI22_X1 U906 ( .A1(n994), .A2(n1913), .B1(n960), .B2(n1914), .ZN(n1912) );
OAI22_X1 U907 ( .A1(n1061), .A2(n1915), .B1(n1028), .B2(n1916), .ZN(n1911)
);
OAI22_X1 U908 ( .A1(n106), .A2(n41), .B1(n1096), .B2(n1918), .ZN(n1910) );
OAI22_X1 U909 ( .A1(n177), .A2(n1919), .B1(n141), .B2(n1920), .ZN(n1909) );
OAI22_X1 U910 ( .A1(n1921), .A2(n1867), .B1(n1868), .B2(n1150), .ZN(N4550)
);
NOR4_X1 U911 ( .A1(n1926), .A2(n1927), .A3(n1928), .A4(n1929), .ZN(n1925) );
OAI22_X1 U912 ( .A1(n198), .A2(n1877), .B1(n1068), .B2(n1878), .ZN(n1929) );
OAI22_X1 U913 ( .A1(n262), .A2(n1879), .B1(n230), .B2(n1880), .ZN(n1928) );
OAI22_X1 U914 ( .A1(n326), .A2(n1881), .B1(n294), .B2(n1882), .ZN(n1927) );
OAI22_X1 U915 ( .A1(n390), .A2(n1883), .B1(n358), .B2(n1884), .ZN(n1926) );
NOR4_X1 U916 ( .A1(n1930), .A2(n1931), .A3(n1932), .A4(n1933), .ZN(n1924) );
OAI22_X1 U917 ( .A1(n455), .A2(n1889), .B1(n422), .B2(n1890), .ZN(n1933) );
OAI22_X1 U918 ( .A1(n523), .A2(n1891), .B1(n489), .B2(n1892), .ZN(n1932) );
OAI22_X1 U919 ( .A1(n590), .A2(n1893), .B1(n556), .B2(n1894), .ZN(n1931) );
OAI22_X1 U920 ( .A1(n657), .A2(n1895), .B1(n623), .B2(n1896), .ZN(n1930) );
NOR4_X1 U921 ( .A1(n1934), .A2(n1935), .A3(n1936), .A4(n1937), .ZN(n1923) );
OAI22_X1 U922 ( .A1(n724), .A2(n1901), .B1(n691), .B2(n1902), .ZN(n1937) );
OAI22_X1 U923 ( .A1(n791), .A2(n1903), .B1(n758), .B2(n1904), .ZN(n1936) );
OAI22_X1 U924 ( .A1(n859), .A2(n1905), .B1(n825), .B2(n1906), .ZN(n1935) );
OAI22_X1 U925 ( .A1(n926), .A2(n39), .B1(n892), .B2(n1908), .ZN(n1934) );
NOR4_X1 U926 ( .A1(n1938), .A2(n1939), .A3(n1940), .A4(n1941), .ZN(n1922) );
OAI22_X1 U927 ( .A1(n993), .A2(n1913), .B1(n959), .B2(n1914), .ZN(n1941) );
OAI22_X1 U928 ( .A1(n1060), .A2(n1915), .B1(n1027), .B2(n1916), .ZN(n1940)
);
OAI22_X1 U929 ( .A1(n105), .A2(n1917), .B1(n1095), .B2(n1918), .ZN(n1939) );
OAI22_X1 U930 ( .A1(n176), .A2(n1919), .B1(n140), .B2(n45), .ZN(n1938) );
OAI22_X1 U931 ( .A1(n1942), .A2(n1867), .B1(n1868), .B2(n1172), .ZN(N4548)
);
NOR4_X1 U932 ( .A1(n1947), .A2(n1948), .A3(n1949), .A4(n1950), .ZN(n1946) );
OAI22_X1 U933 ( .A1(n197), .A2(n1877), .B1(n1047), .B2(n1878), .ZN(n1950) );
OAI22_X1 U934 ( .A1(n261), .A2(n1879), .B1(n229), .B2(n1880), .ZN(n1949) );
OAI22_X1 U935 ( .A1(n325), .A2(n1881), .B1(n293), .B2(n1882), .ZN(n1948) );
OAI22_X1 U936 ( .A1(n389), .A2(n1883), .B1(n357), .B2(n1884), .ZN(n1947) );
NOR4_X1 U937 ( .A1(n1951), .A2(n1952), .A3(n1953), .A4(n1954), .ZN(n1945) );
OAI22_X1 U938 ( .A1(n454), .A2(n1889), .B1(n421), .B2(n1890), .ZN(n1954) );
OAI22_X1 U939 ( .A1(n521), .A2(n1891), .B1(n488), .B2(n1892), .ZN(n1953) );
OAI22_X1 U940 ( .A1(n589), .A2(n1893), .B1(n555), .B2(n1894), .ZN(n1952) );
OAI22_X1 U941 ( .A1(n656), .A2(n1895), .B1(n622), .B2(n1896), .ZN(n1951) );
NOR4_X1 U942 ( .A1(n1955), .A2(n1956), .A3(n1957), .A4(n1958), .ZN(n1944) );
OAI22_X1 U943 ( .A1(n723), .A2(n1901), .B1(n689), .B2(n1902), .ZN(n1958) );
OAI22_X1 U944 ( .A1(n790), .A2(n1903), .B1(n757), .B2(n1904), .ZN(n1957) );
OAI22_X1 U945 ( .A1(n857), .A2(n1905), .B1(n824), .B2(n1906), .ZN(n1956) );
OAI22_X1 U946 ( .A1(n925), .A2(n1907), .B1(n891), .B2(n1908), .ZN(n1955) );
NOR4_X1 U947 ( .A1(n1959), .A2(n1960), .A3(n1961), .A4(n1962), .ZN(n1943) );
OAI22_X1 U948 ( .A1(n992), .A2(n1913), .B1(n958), .B2(n1914), .ZN(n1962) );
OAI22_X1 U949 ( .A1(n1059), .A2(n1915), .B1(n1025), .B2(n1916), .ZN(n1961)
);
OAI22_X1 U950 ( .A1(n104), .A2(n1917), .B1(n1093), .B2(n1918), .ZN(n1960) );
OAI22_X1 U951 ( .A1(n174), .A2(n1919), .B1(n139), .B2(n45), .ZN(n1959) );
OAI22_X1 U952 ( .A1(n1963), .A2(n1867), .B1(n1868), .B2(n1194), .ZN(N4546)
);
NOR4_X1 U953 ( .A1(n1968), .A2(n1969), .A3(n1970), .A4(n1971), .ZN(n1967) );
OAI22_X1 U954 ( .A1(n196), .A2(n1877), .B1(n1026), .B2(n1878), .ZN(n1971) );
OAI22_X1 U955 ( .A1(n260), .A2(n1879), .B1(n228), .B2(n1880), .ZN(n1970) );
OAI22_X1 U956 ( .A1(n324), .A2(n1881), .B1(n292), .B2(n1882), .ZN(n1969) );
OAI22_X1 U957 ( .A1(n388), .A2(n1883), .B1(n356), .B2(n1884), .ZN(n1968) );
NOR4_X1 U958 ( .A1(n1972), .A2(n1973), .A3(n1974), .A4(n1975), .ZN(n1966) );
OAI22_X1 U959 ( .A1(n453), .A2(n1889), .B1(n420), .B2(n1890), .ZN(n1975) );
OAI22_X1 U960 ( .A1(n520), .A2(n1891), .B1(n487), .B2(n1892), .ZN(n1974) );
OAI22_X1 U961 ( .A1(n588), .A2(n1893), .B1(n554), .B2(n1894), .ZN(n1973) );
OAI22_X1 U962 ( .A1(n655), .A2(n1895), .B1(n621), .B2(n1896), .ZN(n1972) );
NOR4_X1 U963 ( .A1(n1976), .A2(n1977), .A3(n1978), .A4(n1979), .ZN(n1965) );
OAI22_X1 U964 ( .A1(n722), .A2(n1901), .B1(n688), .B2(n1902), .ZN(n1979) );
OAI22_X1 U965 ( .A1(n789), .A2(n1903), .B1(n756), .B2(n1904), .ZN(n1978) );
OAI22_X1 U966 ( .A1(n856), .A2(n1905), .B1(n823), .B2(n1906), .ZN(n1977) );
OAI22_X1 U967 ( .A1(n924), .A2(n1907), .B1(n890), .B2(n1908), .ZN(n1976) );
NOR4_X1 U968 ( .A1(n1980), .A2(n1981), .A3(n1982), .A4(n1983), .ZN(n1964) );
OAI22_X1 U969 ( .A1(n991), .A2(n1913), .B1(n957), .B2(n1914), .ZN(n1983) );
OAI22_X1 U970 ( .A1(n1058), .A2(n1915), .B1(n1024), .B2(n1916), .ZN(n1982)
);
OAI22_X1 U971 ( .A1(n103), .A2(n1917), .B1(n1092), .B2(n43), .ZN(n1981) );
OAI22_X1 U972 ( .A1(n173), .A2(n1919), .B1(n138), .B2(n45), .ZN(n1980) );
OAI22_X1 U973 ( .A1(n1984), .A2(n1867), .B1(n1868), .B2(n1216), .ZN(N4544)
);
NOR4_X1 U974 ( .A1(n1989), .A2(n1990), .A3(n1991), .A4(n1992), .ZN(n1988) );
OAI22_X1 U975 ( .A1(n195), .A2(n1877), .B1(n1005), .B2(n1878), .ZN(n1992) );
OAI22_X1 U976 ( .A1(n259), .A2(n1879), .B1(n227), .B2(n1880), .ZN(n1991) );
OAI22_X1 U977 ( .A1(n323), .A2(n1881), .B1(n291), .B2(n1882), .ZN(n1990) );
OAI22_X1 U978 ( .A1(n387), .A2(n1883), .B1(n355), .B2(n1884), .ZN(n1989) );
NOR4_X1 U979 ( .A1(n1993), .A2(n1994), .A3(n1995), .A4(n1996), .ZN(n1987) );
OAI22_X1 U980 ( .A1(n452), .A2(n1889), .B1(n419), .B2(n1890), .ZN(n1996) );
OAI22_X1 U981 ( .A1(n519), .A2(n1891), .B1(n486), .B2(n1892), .ZN(n1995) );
OAI22_X1 U982 ( .A1(n587), .A2(n1893), .B1(n553), .B2(n1894), .ZN(n1994) );
OAI22_X1 U983 ( .A1(n654), .A2(n1895), .B1(n620), .B2(n1896), .ZN(n1993) );
NOR4_X1 U984 ( .A1(n1997), .A2(n1998), .A3(n1999), .A4(n2000), .ZN(n1986) );
OAI22_X1 U985 ( .A1(n721), .A2(n1901), .B1(n687), .B2(n1902), .ZN(n2000) );
OAI22_X1 U986 ( .A1(n788), .A2(n1903), .B1(n755), .B2(n1904), .ZN(n1999) );
OAI22_X1 U987 ( .A1(n855), .A2(n1905), .B1(n822), .B2(n1906), .ZN(n1998) );
OAI22_X1 U988 ( .A1(n923), .A2(n1907), .B1(n889), .B2(n1908), .ZN(n1997) );
NOR4_X1 U989 ( .A1(n2001), .A2(n2002), .A3(n2003), .A4(n2004), .ZN(n1985) );
OAI22_X1 U990 ( .A1(n990), .A2(n1913), .B1(n956), .B2(n1914), .ZN(n2004) );
OAI22_X1 U991 ( .A1(n1057), .A2(n1915), .B1(n1023), .B2(n1916), .ZN(n2003)
);
OAI22_X1 U992 ( .A1(n102), .A2(n1917), .B1(n1091), .B2(n43), .ZN(n2002) );
OAI22_X1 U993 ( .A1(n172), .A2(n1919), .B1(n137), .B2(n45), .ZN(n2001) );
OAI22_X1 U994 ( .A1(n2005), .A2(n1867), .B1(n1868), .B2(n1238), .ZN(N4542)
);
NOR4_X1 U995 ( .A1(n2010), .A2(n2011), .A3(n2012), .A4(n2013), .ZN(n2009) );
OAI22_X1 U996 ( .A1(n194), .A2(n1877), .B1(n984), .B2(n1878), .ZN(n2013) );
OAI22_X1 U997 ( .A1(n258), .A2(n1879), .B1(n226), .B2(n1880), .ZN(n2012) );
OAI22_X1 U998 ( .A1(n322), .A2(n1881), .B1(n290), .B2(n1882), .ZN(n2011) );
OAI22_X1 U999 ( .A1(n386), .A2(n1883), .B1(n354), .B2(n1884), .ZN(n2010) );
NOR4_X1 U1000 ( .A1(n2014), .A2(n2015), .A3(n2016), .A4(n2017), .ZN(n2008)
);
OAI22_X1 U1001 ( .A1(n451), .A2(n1889), .B1(n418), .B2(n1890), .ZN(n2017) );
OAI22_X1 U1002 ( .A1(n518), .A2(n1891), .B1(n485), .B2(n1892), .ZN(n2016) );
OAI22_X1 U1003 ( .A1(n586), .A2(n1893), .B1(n552), .B2(n1894), .ZN(n2015) );
OAI22_X1 U1004 ( .A1(n653), .A2(n1895), .B1(n619), .B2(n1896), .ZN(n2014) );
NOR4_X1 U1005 ( .A1(n2018), .A2(n2019), .A3(n2020), .A4(n2021), .ZN(n2007)
);
OAI22_X1 U1006 ( .A1(n720), .A2(n1901), .B1(n686), .B2(n1902), .ZN(n2021) );
OAI22_X1 U1007 ( .A1(n787), .A2(n1903), .B1(n754), .B2(n1904), .ZN(n2020) );
OAI22_X1 U1008 ( .A1(n854), .A2(n1905), .B1(n821), .B2(n1906), .ZN(n2019) );
OAI22_X1 U1009 ( .A1(n922), .A2(n1907), .B1(n888), .B2(n1908), .ZN(n2018) );
NOR4_X1 U1010 ( .A1(n2022), .A2(n2023), .A3(n2024), .A4(n2025), .ZN(n2006)
);
OAI22_X1 U1011 ( .A1(n989), .A2(n1913), .B1(n955), .B2(n1914), .ZN(n2025) );
OAI22_X1 U1012 ( .A1(n1056), .A2(n1915), .B1(n1022), .B2(n1916), .ZN(n2024)
);
OAI22_X1 U1013 ( .A1(n101), .A2(n1917), .B1(n1090), .B2(n1918), .ZN(n2023)
);
OAI22_X1 U1014 ( .A1(n171), .A2(n1919), .B1(n136), .B2(n45), .ZN(n2022) );
OAI22_X1 U1015 ( .A1(n2026), .A2(n1867), .B1(n1868), .B2(n1260), .ZN(N4540)
);
NOR4_X1 U1016 ( .A1(n2031), .A2(n2032), .A3(n2033), .A4(n2034), .ZN(n2030)
);
OAI22_X1 U1017 ( .A1(n193), .A2(n1877), .B1(n963), .B2(n1878), .ZN(n2034) );
OAI22_X1 U1018 ( .A1(n257), .A2(n1879), .B1(n225), .B2(n1880), .ZN(n2033) );
OAI22_X1 U1019 ( .A1(n321), .A2(n1881), .B1(n289), .B2(n1882), .ZN(n2032) );
OAI22_X1 U1020 ( .A1(n385), .A2(n1883), .B1(n353), .B2(n1884), .ZN(n2031) );
NOR4_X1 U1021 ( .A1(n2035), .A2(n2036), .A3(n2037), .A4(n2038), .ZN(n2029)
);
OAI22_X1 U1022 ( .A1(n450), .A2(n1889), .B1(n417), .B2(n1890), .ZN(n2038) );
OAI22_X1 U1023 ( .A1(n517), .A2(n1891), .B1(n484), .B2(n1892), .ZN(n2037) );
OAI22_X1 U1024 ( .A1(n584), .A2(n1893), .B1(n551), .B2(n1894), .ZN(n2036) );
OAI22_X1 U1025 ( .A1(n652), .A2(n1895), .B1(n618), .B2(n1896), .ZN(n2035) );
NOR4_X1 U1026 ( .A1(n2039), .A2(n2040), .A3(n2041), .A4(n2042), .ZN(n2028)
);
OAI22_X1 U1027 ( .A1(n719), .A2(n1901), .B1(n685), .B2(n1902), .ZN(n2042) );
OAI22_X1 U1028 ( .A1(n786), .A2(n1903), .B1(n752), .B2(n1904), .ZN(n2041) );
OAI22_X1 U1029 ( .A1(n853), .A2(n1905), .B1(n820), .B2(n1906), .ZN(n2040) );
OAI22_X1 U1030 ( .A1(n920), .A2(n1907), .B1(n887), .B2(n1908), .ZN(n2039) );
NOR4_X1 U1031 ( .A1(n2043), .A2(n2044), .A3(n2045), .A4(n2046), .ZN(n2027)
);
OAI22_X1 U1032 ( .A1(n988), .A2(n1913), .B1(n954), .B2(n1914), .ZN(n2046) );
OAI22_X1 U1033 ( .A1(n1055), .A2(n1915), .B1(n1021), .B2(n1916), .ZN(n2045)
);
OAI22_X1 U1034 ( .A1(n100), .A2(n1917), .B1(n1088), .B2(n43), .ZN(n2044) );
OAI22_X1 U1035 ( .A1(n170), .A2(n1919), .B1(n135), .B2(n45), .ZN(n2043) );
OAI22_X1 U1036 ( .A1(n2047), .A2(n1867), .B1(n1868), .B2(n1282), .ZN(N4538)
);
NOR4_X1 U1037 ( .A1(n2052), .A2(n2053), .A3(n2054), .A4(n2055), .ZN(n2051)
);
OAI22_X1 U1038 ( .A1(n192), .A2(n1877), .B1(n942), .B2(n1878), .ZN(n2055) );
OAI22_X1 U1039 ( .A1(n256), .A2(n1879), .B1(n224), .B2(n1880), .ZN(n2054) );
OAI22_X1 U1040 ( .A1(n320), .A2(n1881), .B1(n288), .B2(n1882), .ZN(n2053) );
OAI22_X1 U1041 ( .A1(n384), .A2(n1883), .B1(n352), .B2(n1884), .ZN(n2052) );
NOR4_X1 U1042 ( .A1(n2056), .A2(n2057), .A3(n2058), .A4(n2059), .ZN(n2050)
);
OAI22_X1 U1043 ( .A1(n449), .A2(n1889), .B1(n416), .B2(n1890), .ZN(n2059) );
OAI22_X1 U1044 ( .A1(n516), .A2(n1891), .B1(n483), .B2(n1892), .ZN(n2058) );
OAI22_X1 U1045 ( .A1(n583), .A2(n1893), .B1(n550), .B2(n1894), .ZN(n2057) );
OAI22_X1 U1046 ( .A1(n651), .A2(n1895), .B1(n617), .B2(n1896), .ZN(n2056) );
NOR4_X1 U1047 ( .A1(n2060), .A2(n2061), .A3(n2062), .A4(n2063), .ZN(n2049)
);
OAI22_X1 U1048 ( .A1(n718), .A2(n1901), .B1(n684), .B2(n1902), .ZN(n2063) );
OAI22_X1 U1049 ( .A1(n785), .A2(n1903), .B1(n751), .B2(n1904), .ZN(n2062) );
OAI22_X1 U1050 ( .A1(n852), .A2(n1905), .B1(n819), .B2(n1906), .ZN(n2061) );
OAI22_X1 U1051 ( .A1(n919), .A2(n1907), .B1(n886), .B2(n1908), .ZN(n2060) );
NOR4_X1 U1052 ( .A1(n2064), .A2(n2065), .A3(n2066), .A4(n2067), .ZN(n2048)
);
OAI22_X1 U1053 ( .A1(n987), .A2(n1913), .B1(n953), .B2(n1914), .ZN(n2067) );
OAI22_X1 U1054 ( .A1(n1054), .A2(n1915), .B1(n1020), .B2(n1916), .ZN(n2066)
);
OAI22_X1 U1055 ( .A1(n99), .A2(n1917), .B1(n1087), .B2(n1918), .ZN(n2065) );
OAI22_X1 U1056 ( .A1(n169), .A2(n1919), .B1(n134), .B2(n45), .ZN(n2064) );
OAI22_X1 U1057 ( .A1(n2068), .A2(n1867), .B1(n1868), .B2(n1304), .ZN(N4536)
);
NOR4_X1 U1058 ( .A1(n2073), .A2(n2074), .A3(n2075), .A4(n2076), .ZN(n2072)
);
OAI22_X1 U1059 ( .A1(n191), .A2(n1877), .B1(n921), .B2(n1878), .ZN(n2076) );
OAI22_X1 U1060 ( .A1(n255), .A2(n1879), .B1(n223), .B2(n1880), .ZN(n2075) );
OAI22_X1 U1061 ( .A1(n319), .A2(n1881), .B1(n287), .B2(n1882), .ZN(n2074) );
OAI22_X1 U1062 ( .A1(n383), .A2(n1883), .B1(n351), .B2(n1884), .ZN(n2073) );
NOR4_X1 U1063 ( .A1(n2077), .A2(n2078), .A3(n2079), .A4(n2080), .ZN(n2071)
);
OAI22_X1 U1064 ( .A1(n448), .A2(n1889), .B1(n415), .B2(n1890), .ZN(n2080) );
OAI22_X1 U1065 ( .A1(n515), .A2(n1891), .B1(n482), .B2(n1892), .ZN(n2079) );
OAI22_X1 U1066 ( .A1(n582), .A2(n1893), .B1(n549), .B2(n1894), .ZN(n2078) );
OAI22_X1 U1067 ( .A1(n650), .A2(n1895), .B1(n616), .B2(n1896), .ZN(n2077) );
NOR4_X1 U1068 ( .A1(n2081), .A2(n2082), .A3(n2083), .A4(n2084), .ZN(n2070)
);
OAI22_X1 U1069 ( .A1(n717), .A2(n1901), .B1(n683), .B2(n1902), .ZN(n2084) );
OAI22_X1 U1070 ( .A1(n784), .A2(n1903), .B1(n750), .B2(n1904), .ZN(n2083) );
OAI22_X1 U1071 ( .A1(n851), .A2(n1905), .B1(n818), .B2(n1906), .ZN(n2082) );
OAI22_X1 U1072 ( .A1(n918), .A2(n1907), .B1(n885), .B2(n1908), .ZN(n2081) );
NOR4_X1 U1073 ( .A1(n2085), .A2(n2086), .A3(n2087), .A4(n2088), .ZN(n2069)
);
OAI22_X1 U1074 ( .A1(n986), .A2(n1913), .B1(n952), .B2(n1914), .ZN(n2088) );
OAI22_X1 U1075 ( .A1(n1053), .A2(n1915), .B1(n1019), .B2(n1916), .ZN(n2087)
);
OAI22_X1 U1076 ( .A1(n95), .A2(n1917), .B1(n1086), .B2(n43), .ZN(n2086) );
OAI22_X1 U1077 ( .A1(n168), .A2(n1919), .B1(n133), .B2(n45), .ZN(n2085) );
OAI22_X1 U1078 ( .A1(n2089), .A2(n1867), .B1(n1868), .B2(n1326), .ZN(N4534)
);
NOR4_X1 U1079 ( .A1(n2094), .A2(n2095), .A3(n2096), .A4(n2097), .ZN(n2093)
);
OAI22_X1 U1080 ( .A1(n190), .A2(n1877), .B1(n900), .B2(n1878), .ZN(n2097) );
OAI22_X1 U1081 ( .A1(n254), .A2(n1879), .B1(n222), .B2(n1880), .ZN(n2096) );
OAI22_X1 U1082 ( .A1(n318), .A2(n1881), .B1(n286), .B2(n1882), .ZN(n2095) );
OAI22_X1 U1083 ( .A1(n382), .A2(n1883), .B1(n350), .B2(n1884), .ZN(n2094) );
NOR4_X1 U1084 ( .A1(n2098), .A2(n2099), .A3(n2100), .A4(n2101), .ZN(n2092)
);
OAI22_X1 U1085 ( .A1(n447), .A2(n1889), .B1(n414), .B2(n1890), .ZN(n2101) );
OAI22_X1 U1086 ( .A1(n514), .A2(n1891), .B1(n481), .B2(n1892), .ZN(n2100) );
OAI22_X1 U1087 ( .A1(n581), .A2(n1893), .B1(n548), .B2(n1894), .ZN(n2099) );
OAI22_X1 U1088 ( .A1(n649), .A2(n1895), .B1(n615), .B2(n1896), .ZN(n2098) );
NOR4_X1 U1089 ( .A1(n2102), .A2(n2103), .A3(n2104), .A4(n2105), .ZN(n2091)
);
OAI22_X1 U1090 ( .A1(n716), .A2(n1901), .B1(n682), .B2(n1902), .ZN(n2105) );
OAI22_X1 U1091 ( .A1(n783), .A2(n1903), .B1(n749), .B2(n1904), .ZN(n2104) );
OAI22_X1 U1092 ( .A1(n850), .A2(n1905), .B1(n817), .B2(n1906), .ZN(n2103) );
OAI22_X1 U1093 ( .A1(n917), .A2(n1907), .B1(n884), .B2(n1908), .ZN(n2102) );
NOR4_X1 U1094 ( .A1(n2106), .A2(n2107), .A3(n2108), .A4(n2109), .ZN(n2090)
);
OAI22_X1 U1095 ( .A1(n985), .A2(n1913), .B1(n951), .B2(n1914), .ZN(n2109) );
OAI22_X1 U1096 ( .A1(n1052), .A2(n1915), .B1(n1018), .B2(n1916), .ZN(n2108)
);
OAI22_X1 U1097 ( .A1(n93), .A2(n1917), .B1(n1085), .B2(n43), .ZN(n2107) );
OAI22_X1 U1098 ( .A1(n167), .A2(n1919), .B1(n132), .B2(n45), .ZN(n2106) );
OAI22_X1 U1099 ( .A1(n2110), .A2(n1867), .B1(n1868), .B2(n1348), .ZN(N4532)
);
NOR4_X1 U1100 ( .A1(n2115), .A2(n2116), .A3(n2117), .A4(n2118), .ZN(n2114)
);
OAI22_X1 U1101 ( .A1(n189), .A2(n1877), .B1(n879), .B2(n1878), .ZN(n2118) );
OAI22_X1 U1102 ( .A1(n253), .A2(n1879), .B1(n221), .B2(n1880), .ZN(n2117) );
OAI22_X1 U1103 ( .A1(n317), .A2(n1881), .B1(n285), .B2(n1882), .ZN(n2116) );
OAI22_X1 U1104 ( .A1(n381), .A2(n1883), .B1(n349), .B2(n1884), .ZN(n2115) );
NOR4_X1 U1105 ( .A1(n2119), .A2(n2120), .A3(n2121), .A4(n2122), .ZN(n2113)
);
OAI22_X1 U1106 ( .A1(n446), .A2(n1889), .B1(n413), .B2(n1890), .ZN(n2122) );
OAI22_X1 U1107 ( .A1(n513), .A2(n1891), .B1(n479), .B2(n1892), .ZN(n2121) );
OAI22_X1 U1108 ( .A1(n580), .A2(n1893), .B1(n547), .B2(n1894), .ZN(n2120) );
OAI22_X1 U1109 ( .A1(n647), .A2(n1895), .B1(n614), .B2(n1896), .ZN(n2119) );
NOR4_X1 U1110 ( .A1(n2123), .A2(n2124), .A3(n2125), .A4(n2126), .ZN(n2112)
);
OAI22_X1 U1111 ( .A1(n715), .A2(n1901), .B1(n681), .B2(n1902), .ZN(n2126) );
OAI22_X1 U1112 ( .A1(n782), .A2(n1903), .B1(n748), .B2(n1904), .ZN(n2125) );
OAI22_X1 U1113 ( .A1(n849), .A2(n1905), .B1(n815), .B2(n1906), .ZN(n2124) );
OAI22_X1 U1114 ( .A1(n916), .A2(n1907), .B1(n883), .B2(n1908), .ZN(n2123) );
NOR4_X1 U1115 ( .A1(n2127), .A2(n2128), .A3(n2129), .A4(n2130), .ZN(n2111)
);
OAI22_X1 U1116 ( .A1(n983), .A2(n1913), .B1(n950), .B2(n1914), .ZN(n2130) );
OAI22_X1 U1117 ( .A1(n1051), .A2(n1915), .B1(n1017), .B2(n1916), .ZN(n2129)
);
OAI22_X1 U1118 ( .A1(n91), .A2(n1917), .B1(n1084), .B2(n43), .ZN(n2128) );
OAI22_X1 U1119 ( .A1(n166), .A2(n1919), .B1(n130), .B2(n45), .ZN(n2127) );
OAI22_X1 U1120 ( .A1(n2131), .A2(n1867), .B1(n1868), .B2(n1370), .ZN(N4530)
);
NOR4_X1 U1121 ( .A1(n2136), .A2(n2137), .A3(n2138), .A4(n2139), .ZN(n2135)
);
OAI22_X1 U1122 ( .A1(n188), .A2(n1877), .B1(n858), .B2(n1878), .ZN(n2139) );
OAI22_X1 U1123 ( .A1(n252), .A2(n1879), .B1(n220), .B2(n1880), .ZN(n2138) );
OAI22_X1 U1124 ( .A1(n316), .A2(n1881), .B1(n284), .B2(n1882), .ZN(n2137) );
OAI22_X1 U1125 ( .A1(n380), .A2(n1883), .B1(n348), .B2(n1884), .ZN(n2136) );
NOR4_X1 U1126 ( .A1(n2140), .A2(n2141), .A3(n2142), .A4(n2143), .ZN(n2134)
);
OAI22_X1 U1127 ( .A1(n445), .A2(n1889), .B1(n412), .B2(n1890), .ZN(n2143) );
OAI22_X1 U1128 ( .A1(n512), .A2(n1891), .B1(n478), .B2(n1892), .ZN(n2142) );
OAI22_X1 U1129 ( .A1(n579), .A2(n1893), .B1(n546), .B2(n1894), .ZN(n2141) );
OAI22_X1 U1130 ( .A1(n646), .A2(n1895), .B1(n613), .B2(n1896), .ZN(n2140) );
NOR4_X1 U1131 ( .A1(n2144), .A2(n2145), .A3(n2146), .A4(n2147), .ZN(n2133)
);
OAI22_X1 U1132 ( .A1(n714), .A2(n1901), .B1(n680), .B2(n1902), .ZN(n2147) );
OAI22_X1 U1133 ( .A1(n781), .A2(n1903), .B1(n747), .B2(n1904), .ZN(n2146) );
OAI22_X1 U1134 ( .A1(n848), .A2(n1905), .B1(n814), .B2(n1906), .ZN(n2145) );
OAI22_X1 U1135 ( .A1(n915), .A2(n1907), .B1(n882), .B2(n1908), .ZN(n2144) );
NOR4_X1 U1136 ( .A1(n2148), .A2(n2149), .A3(n2150), .A4(n2151), .ZN(n2132)
);
OAI22_X1 U1137 ( .A1(n982), .A2(n1913), .B1(n949), .B2(n1914), .ZN(n2151) );
OAI22_X1 U1138 ( .A1(n1050), .A2(n1915), .B1(n1016), .B2(n1916), .ZN(n2150)
);
OAI22_X1 U1139 ( .A1(n89), .A2(n1917), .B1(n1083), .B2(n43), .ZN(n2149) );
OAI22_X1 U1140 ( .A1(n165), .A2(n1919), .B1(n129), .B2(n1920), .ZN(n2148) );
OAI22_X1 U1141 ( .A1(n2152), .A2(n1867), .B1(n1868), .B2(n1392), .ZN(N4528)
);
NOR4_X1 U1142 ( .A1(n2157), .A2(n2158), .A3(n2159), .A4(n2160), .ZN(n2156)
);
OAI22_X1 U1143 ( .A1(n187), .A2(n1877), .B1(n837), .B2(n1878), .ZN(n2160) );
OAI22_X1 U1144 ( .A1(n251), .A2(n1879), .B1(n219), .B2(n1880), .ZN(n2159) );
OAI22_X1 U1145 ( .A1(n315), .A2(n1881), .B1(n283), .B2(n1882), .ZN(n2158) );
OAI22_X1 U1146 ( .A1(n379), .A2(n1883), .B1(n347), .B2(n1884), .ZN(n2157) );
NOR4_X1 U1147 ( .A1(n2161), .A2(n2162), .A3(n2163), .A4(n2164), .ZN(n2155)
);
OAI22_X1 U1148 ( .A1(n444), .A2(n1889), .B1(n411), .B2(n1890), .ZN(n2164) );
OAI22_X1 U1149 ( .A1(n511), .A2(n1891), .B1(n477), .B2(n1892), .ZN(n2163) );
OAI22_X1 U1150 ( .A1(n578), .A2(n1893), .B1(n545), .B2(n1894), .ZN(n2162) );
OAI22_X1 U1151 ( .A1(n645), .A2(n1895), .B1(n612), .B2(n1896), .ZN(n2161) );
NOR4_X1 U1152 ( .A1(n2165), .A2(n2166), .A3(n2167), .A4(n2168), .ZN(n2154)
);
OAI22_X1 U1153 ( .A1(n713), .A2(n1901), .B1(n679), .B2(n1902), .ZN(n2168) );
OAI22_X1 U1154 ( .A1(n780), .A2(n1903), .B1(n746), .B2(n1904), .ZN(n2167) );
OAI22_X1 U1155 ( .A1(n847), .A2(n1905), .B1(n813), .B2(n1906), .ZN(n2166) );
OAI22_X1 U1156 ( .A1(n914), .A2(n1907), .B1(n881), .B2(n1908), .ZN(n2165) );
NOR4_X1 U1157 ( .A1(n2169), .A2(n2170), .A3(n2171), .A4(n2172), .ZN(n2153)
);
OAI22_X1 U1158 ( .A1(n981), .A2(n1913), .B1(n948), .B2(n1914), .ZN(n2172) );
OAI22_X1 U1159 ( .A1(n1049), .A2(n1915), .B1(n1015), .B2(n1916), .ZN(n2171)
);
OAI22_X1 U1160 ( .A1(n87), .A2(n41), .B1(n1082), .B2(n43), .ZN(n2170) );
OAI22_X1 U1161 ( .A1(n163), .A2(n1919), .B1(n128), .B2(n1920), .ZN(n2169) );
OAI22_X1 U1162 ( .A1(n2173), .A2(n1867), .B1(n1868), .B2(n1414), .ZN(N4526)
);
NOR4_X1 U1163 ( .A1(n2178), .A2(n2179), .A3(n2180), .A4(n2181), .ZN(n2177)
);
OAI22_X1 U1164 ( .A1(n186), .A2(n1877), .B1(n816), .B2(n1878), .ZN(n2181) );
OAI22_X1 U1165 ( .A1(n250), .A2(n1879), .B1(n218), .B2(n1880), .ZN(n2180) );
OAI22_X1 U1166 ( .A1(n314), .A2(n1881), .B1(n282), .B2(n1882), .ZN(n2179) );
OAI22_X1 U1167 ( .A1(n378), .A2(n1883), .B1(n346), .B2(n1884), .ZN(n2178) );
NOR4_X1 U1168 ( .A1(n2182), .A2(n2183), .A3(n2184), .A4(n2185), .ZN(n2176)
);
OAI22_X1 U1169 ( .A1(n443), .A2(n1889), .B1(n410), .B2(n1890), .ZN(n2185) );
OAI22_X1 U1170 ( .A1(n510), .A2(n1891), .B1(n476), .B2(n1892), .ZN(n2184) );
OAI22_X1 U1171 ( .A1(n577), .A2(n1893), .B1(n544), .B2(n1894), .ZN(n2183) );
OAI22_X1 U1172 ( .A1(n644), .A2(n1895), .B1(n611), .B2(n1896), .ZN(n2182) );
NOR4_X1 U1173 ( .A1(n2186), .A2(n2187), .A3(n2188), .A4(n2189), .ZN(n2175)
);
OAI22_X1 U1174 ( .A1(n712), .A2(n1901), .B1(n678), .B2(n1902), .ZN(n2189) );
OAI22_X1 U1175 ( .A1(n779), .A2(n1903), .B1(n745), .B2(n1904), .ZN(n2188) );
OAI22_X1 U1176 ( .A1(n846), .A2(n1905), .B1(n812), .B2(n1906), .ZN(n2187) );
OAI22_X1 U1177 ( .A1(n913), .A2(n1907), .B1(n880), .B2(n1908), .ZN(n2186) );
NOR4_X1 U1178 ( .A1(n2190), .A2(n2191), .A3(n2192), .A4(n2193), .ZN(n2174)
);
OAI22_X1 U1179 ( .A1(n980), .A2(n1913), .B1(n947), .B2(n1914), .ZN(n2193) );
OAI22_X1 U1180 ( .A1(n1048), .A2(n1915), .B1(n1014), .B2(n1916), .ZN(n2192)
);
OAI22_X1 U1181 ( .A1(n85), .A2(n41), .B1(n1081), .B2(n43), .ZN(n2191) );
OAI22_X1 U1182 ( .A1(n162), .A2(n1919), .B1(n127), .B2(n1920), .ZN(n2190) );
OAI22_X1 U1183 ( .A1(n2194), .A2(n1867), .B1(n1868), .B2(n1436), .ZN(N4524)
);
NOR4_X1 U1184 ( .A1(n2199), .A2(n2200), .A3(n2201), .A4(n2202), .ZN(n2198)
);
OAI22_X1 U1185 ( .A1(n185), .A2(n1877), .B1(n795), .B2(n1878), .ZN(n2202) );
OAI22_X1 U1186 ( .A1(n249), .A2(n1879), .B1(n217), .B2(n1880), .ZN(n2201) );
OAI22_X1 U1187 ( .A1(n313), .A2(n1881), .B1(n281), .B2(n1882), .ZN(n2200) );
OAI22_X1 U1188 ( .A1(n377), .A2(n1883), .B1(n345), .B2(n1884), .ZN(n2199) );
NOR4_X1 U1189 ( .A1(n2203), .A2(n2204), .A3(n2205), .A4(n2206), .ZN(n2197)
);
OAI22_X1 U1190 ( .A1(n442), .A2(n1889), .B1(n409), .B2(n1890), .ZN(n2206) );
OAI22_X1 U1191 ( .A1(n509), .A2(n1891), .B1(n475), .B2(n1892), .ZN(n2205) );
OAI22_X1 U1192 ( .A1(n576), .A2(n1893), .B1(n542), .B2(n1894), .ZN(n2204) );
OAI22_X1 U1193 ( .A1(n643), .A2(n1895), .B1(n610), .B2(n1896), .ZN(n2203) );
NOR4_X1 U1194 ( .A1(n2207), .A2(n2208), .A3(n2209), .A4(n2210), .ZN(n2196)
);
OAI22_X1 U1195 ( .A1(n710), .A2(n1901), .B1(n677), .B2(n1902), .ZN(n2210) );
OAI22_X1 U1196 ( .A1(n778), .A2(n1903), .B1(n744), .B2(n1904), .ZN(n2209) );
OAI22_X1 U1197 ( .A1(n845), .A2(n1905), .B1(n811), .B2(n1906), .ZN(n2208) );
OAI22_X1 U1198 ( .A1(n912), .A2(n1907), .B1(n878), .B2(n1908), .ZN(n2207) );
NOR4_X1 U1199 ( .A1(n2211), .A2(n2212), .A3(n2213), .A4(n2214), .ZN(n2195)
);
OAI22_X1 U1200 ( .A1(n979), .A2(n1913), .B1(n946), .B2(n1914), .ZN(n2214) );
OAI22_X1 U1201 ( .A1(n1046), .A2(n1915), .B1(n1013), .B2(n1916), .ZN(n2213)
);
OAI22_X1 U1202 ( .A1(n83), .A2(n41), .B1(n1080), .B2(n43), .ZN(n2212) );
OAI22_X1 U1203 ( .A1(n161), .A2(n1919), .B1(n126), .B2(n1920), .ZN(n2211) );
OAI22_X1 U1204 ( .A1(n2215), .A2(n1867), .B1(n1868), .B2(n1458), .ZN(N4522)
);
NOR4_X1 U1205 ( .A1(n2220), .A2(n2221), .A3(n2222), .A4(n2223), .ZN(n2219)
);
OAI22_X1 U1206 ( .A1(n184), .A2(n1877), .B1(n774), .B2(n1878), .ZN(n2223) );
OAI22_X1 U1207 ( .A1(n248), .A2(n1879), .B1(n216), .B2(n1880), .ZN(n2222) );
OAI22_X1 U1208 ( .A1(n312), .A2(n1881), .B1(n280), .B2(n1882), .ZN(n2221) );
OAI22_X1 U1209 ( .A1(n376), .A2(n1883), .B1(n344), .B2(n1884), .ZN(n2220) );
NOR4_X1 U1210 ( .A1(n2224), .A2(n2225), .A3(n2226), .A4(n2227), .ZN(n2218)
);
OAI22_X1 U1211 ( .A1(n441), .A2(n1889), .B1(n408), .B2(n1890), .ZN(n2227) );
OAI22_X1 U1212 ( .A1(n508), .A2(n1891), .B1(n474), .B2(n1892), .ZN(n2226) );
OAI22_X1 U1213 ( .A1(n575), .A2(n1893), .B1(n541), .B2(n1894), .ZN(n2225) );
OAI22_X1 U1214 ( .A1(n642), .A2(n1895), .B1(n609), .B2(n1896), .ZN(n2224) );
NOR4_X1 U1215 ( .A1(n2228), .A2(n2229), .A3(n2230), .A4(n2231), .ZN(n2217)
);
OAI22_X1 U1216 ( .A1(n709), .A2(n1901), .B1(n676), .B2(n1902), .ZN(n2231) );
OAI22_X1 U1217 ( .A1(n777), .A2(n1903), .B1(n743), .B2(n1904), .ZN(n2230) );
OAI22_X1 U1218 ( .A1(n844), .A2(n1905), .B1(n810), .B2(n1906), .ZN(n2229) );
OAI22_X1 U1219 ( .A1(n911), .A2(n1907), .B1(n877), .B2(n1908), .ZN(n2228) );
NOR4_X1 U1220 ( .A1(n2232), .A2(n2233), .A3(n2234), .A4(n2235), .ZN(n2216)
);
OAI22_X1 U1221 ( .A1(n978), .A2(n1913), .B1(n945), .B2(n1914), .ZN(n2235) );
OAI22_X1 U1222 ( .A1(n1045), .A2(n1915), .B1(n1012), .B2(n1916), .ZN(n2234)
);
OAI22_X1 U1223 ( .A1(n81), .A2(n41), .B1(n1079), .B2(n43), .ZN(n2233) );
OAI22_X1 U1224 ( .A1(n160), .A2(n1919), .B1(n125), .B2(n1920), .ZN(n2232) );
OAI22_X1 U1225 ( .A1(n2236), .A2(n1867), .B1(n1868), .B2(n1480), .ZN(N4520)
);
NOR4_X1 U1226 ( .A1(n2241), .A2(n2242), .A3(n2243), .A4(n2244), .ZN(n2240)
);
OAI22_X1 U1227 ( .A1(n183), .A2(n1877), .B1(n753), .B2(n1878), .ZN(n2244) );
OAI22_X1 U1228 ( .A1(n247), .A2(n1879), .B1(n215), .B2(n1880), .ZN(n2243) );
OAI22_X1 U1229 ( .A1(n311), .A2(n1881), .B1(n279), .B2(n1882), .ZN(n2242) );
OAI22_X1 U1230 ( .A1(n375), .A2(n1883), .B1(n343), .B2(n1884), .ZN(n2241) );
NOR4_X1 U1231 ( .A1(n2245), .A2(n2246), .A3(n2247), .A4(n2248), .ZN(n2239)
);
OAI22_X1 U1232 ( .A1(n440), .A2(n1889), .B1(n407), .B2(n1890), .ZN(n2248) );
OAI22_X1 U1233 ( .A1(n507), .A2(n1891), .B1(n473), .B2(n1892), .ZN(n2247) );
OAI22_X1 U1234 ( .A1(n574), .A2(n1893), .B1(n540), .B2(n1894), .ZN(n2246) );
OAI22_X1 U1235 ( .A1(n641), .A2(n1895), .B1(n608), .B2(n1896), .ZN(n2245) );
NOR4_X1 U1236 ( .A1(n2249), .A2(n2250), .A3(n2251), .A4(n2252), .ZN(n2238)
);
OAI22_X1 U1237 ( .A1(n708), .A2(n1901), .B1(n675), .B2(n1902), .ZN(n2252) );
OAI22_X1 U1238 ( .A1(n776), .A2(n1903), .B1(n742), .B2(n1904), .ZN(n2251) );
OAI22_X1 U1239 ( .A1(n843), .A2(n1905), .B1(n809), .B2(n1906), .ZN(n2250) );
OAI22_X1 U1240 ( .A1(n910), .A2(n1907), .B1(n876), .B2(n1908), .ZN(n2249) );
NOR4_X1 U1241 ( .A1(n2253), .A2(n2254), .A3(n2255), .A4(n2256), .ZN(n2237)
);
OAI22_X1 U1242 ( .A1(n977), .A2(n1913), .B1(n944), .B2(n1914), .ZN(n2256) );
OAI22_X1 U1243 ( .A1(n1044), .A2(n1915), .B1(n1011), .B2(n1916), .ZN(n2255)
);
OAI22_X1 U1244 ( .A1(n79), .A2(n41), .B1(n1078), .B2(n43), .ZN(n2254) );
OAI22_X1 U1245 ( .A1(n159), .A2(n1919), .B1(n124), .B2(n1920), .ZN(n2253) );
OAI22_X1 U1246 ( .A1(n2257), .A2(n1867), .B1(n1868), .B2(n1502), .ZN(N4518)
);
NOR4_X1 U1247 ( .A1(n2262), .A2(n2263), .A3(n2264), .A4(n2265), .ZN(n2261)
);
OAI22_X1 U1248 ( .A1(n182), .A2(n1877), .B1(n732), .B2(n1878), .ZN(n2265) );
OAI22_X1 U1249 ( .A1(n246), .A2(n1879), .B1(n214), .B2(n1880), .ZN(n2264) );
OAI22_X1 U1250 ( .A1(n310), .A2(n1881), .B1(n278), .B2(n1882), .ZN(n2263) );
OAI22_X1 U1251 ( .A1(n374), .A2(n1883), .B1(n342), .B2(n1884), .ZN(n2262) );
NOR4_X1 U1252 ( .A1(n2266), .A2(n2267), .A3(n2268), .A4(n2269), .ZN(n2260)
);
OAI22_X1 U1253 ( .A1(n439), .A2(n1889), .B1(n406), .B2(n1890), .ZN(n2269) );
OAI22_X1 U1254 ( .A1(n506), .A2(n1891), .B1(n472), .B2(n1892), .ZN(n2268) );
OAI22_X1 U1255 ( .A1(n573), .A2(n1893), .B1(n539), .B2(n1894), .ZN(n2267) );
OAI22_X1 U1256 ( .A1(n640), .A2(n1895), .B1(n607), .B2(n1896), .ZN(n2266) );
NOR4_X1 U1257 ( .A1(n2270), .A2(n2271), .A3(n2272), .A4(n2273), .ZN(n2259)
);
OAI22_X1 U1258 ( .A1(n707), .A2(n1901), .B1(n674), .B2(n1902), .ZN(n2273) );
OAI22_X1 U1259 ( .A1(n775), .A2(n1903), .B1(n741), .B2(n1904), .ZN(n2272) );
OAI22_X1 U1260 ( .A1(n842), .A2(n1905), .B1(n808), .B2(n1906), .ZN(n2271) );
OAI22_X1 U1261 ( .A1(n909), .A2(n1907), .B1(n875), .B2(n1908), .ZN(n2270) );
NOR4_X1 U1262 ( .A1(n2274), .A2(n2275), .A3(n2276), .A4(n2277), .ZN(n2258)
);
OAI22_X1 U1263 ( .A1(n976), .A2(n1913), .B1(n943), .B2(n1914), .ZN(n2277) );
OAI22_X1 U1264 ( .A1(n1043), .A2(n1915), .B1(n1010), .B2(n1916), .ZN(n2276)
);
OAI22_X1 U1265 ( .A1(n77), .A2(n41), .B1(n1077), .B2(n43), .ZN(n2275) );
OAI22_X1 U1266 ( .A1(n158), .A2(n1919), .B1(n123), .B2(n1920), .ZN(n2274) );
OAI22_X1 U1267 ( .A1(n2278), .A2(n1867), .B1(n1868), .B2(n1524), .ZN(N4516)
);
NOR4_X1 U1268 ( .A1(n2283), .A2(n2284), .A3(n2285), .A4(n2286), .ZN(n2282)
);
OAI22_X1 U1269 ( .A1(n181), .A2(n1877), .B1(n711), .B2(n1878), .ZN(n2286) );
OAI22_X1 U1270 ( .A1(n245), .A2(n1879), .B1(n213), .B2(n1880), .ZN(n2285) );
OAI22_X1 U1271 ( .A1(n309), .A2(n1881), .B1(n277), .B2(n1882), .ZN(n2284) );
OAI22_X1 U1272 ( .A1(n373), .A2(n1883), .B1(n341), .B2(n1884), .ZN(n2283) );
NOR4_X1 U1273 ( .A1(n2287), .A2(n2288), .A3(n2289), .A4(n2290), .ZN(n2281)
);
OAI22_X1 U1274 ( .A1(n437), .A2(n1889), .B1(n405), .B2(n1890), .ZN(n2290) );
OAI22_X1 U1275 ( .A1(n505), .A2(n1891), .B1(n471), .B2(n1892), .ZN(n2289) );
OAI22_X1 U1276 ( .A1(n572), .A2(n1893), .B1(n538), .B2(n1894), .ZN(n2288) );
OAI22_X1 U1277 ( .A1(n639), .A2(n1895), .B1(n605), .B2(n1896), .ZN(n2287) );
NOR4_X1 U1278 ( .A1(n2291), .A2(n2292), .A3(n2293), .A4(n2294), .ZN(n2280)
);
OAI22_X1 U1279 ( .A1(n706), .A2(n1901), .B1(n673), .B2(n1902), .ZN(n2294) );
OAI22_X1 U1280 ( .A1(n773), .A2(n1903), .B1(n740), .B2(n1904), .ZN(n2293) );
OAI22_X1 U1281 ( .A1(n841), .A2(n1905), .B1(n807), .B2(n1906), .ZN(n2292) );
OAI22_X1 U1282 ( .A1(n908), .A2(n1907), .B1(n874), .B2(n1908), .ZN(n2291) );
NOR4_X1 U1283 ( .A1(n2295), .A2(n2296), .A3(n2297), .A4(n2298), .ZN(n2279)
);
OAI22_X1 U1284 ( .A1(n975), .A2(n1913), .B1(n941), .B2(n1914), .ZN(n2298) );
OAI22_X1 U1285 ( .A1(n1042), .A2(n1915), .B1(n1009), .B2(n1916), .ZN(n2297)
);
OAI22_X1 U1286 ( .A1(n73), .A2(n41), .B1(n1076), .B2(n43), .ZN(n2296) );
OAI22_X1 U1287 ( .A1(n157), .A2(n1919), .B1(n122), .B2(n1920), .ZN(n2295) );
OAI22_X1 U1288 ( .A1(n2299), .A2(n1867), .B1(n1868), .B2(n1546), .ZN(N4514)
);
NOR4_X1 U1289 ( .A1(n2304), .A2(n2305), .A3(n2306), .A4(n2307), .ZN(n2303)
);
OAI22_X1 U1290 ( .A1(n180), .A2(n1877), .B1(n690), .B2(n1878), .ZN(n2307) );
OAI22_X1 U1291 ( .A1(n244), .A2(n1879), .B1(n212), .B2(n1880), .ZN(n2306) );
OAI22_X1 U1292 ( .A1(n308), .A2(n1881), .B1(n276), .B2(n1882), .ZN(n2305) );
OAI22_X1 U1293 ( .A1(n372), .A2(n1883), .B1(n340), .B2(n1884), .ZN(n2304) );
NOR4_X1 U1294 ( .A1(n2308), .A2(n2309), .A3(n2310), .A4(n2311), .ZN(n2302)
);
OAI22_X1 U1295 ( .A1(n436), .A2(n1889), .B1(n404), .B2(n1890), .ZN(n2311) );
OAI22_X1 U1296 ( .A1(n504), .A2(n1891), .B1(n470), .B2(n1892), .ZN(n2310) );
OAI22_X1 U1297 ( .A1(n571), .A2(n1893), .B1(n537), .B2(n1894), .ZN(n2309) );
OAI22_X1 U1298 ( .A1(n638), .A2(n1895), .B1(n604), .B2(n1896), .ZN(n2308) );
NOR4_X1 U1299 ( .A1(n2312), .A2(n2313), .A3(n2314), .A4(n2315), .ZN(n2301)
);
OAI22_X1 U1300 ( .A1(n705), .A2(n1901), .B1(n672), .B2(n1902), .ZN(n2315) );
OAI22_X1 U1301 ( .A1(n772), .A2(n1903), .B1(n739), .B2(n1904), .ZN(n2314) );
OAI22_X1 U1302 ( .A1(n840), .A2(n1905), .B1(n806), .B2(n1906), .ZN(n2313) );
OAI22_X1 U1303 ( .A1(n907), .A2(n1907), .B1(n873), .B2(n1908), .ZN(n2312) );
NOR4_X1 U1304 ( .A1(n2316), .A2(n2317), .A3(n2318), .A4(n2319), .ZN(n2300)
);
OAI22_X1 U1305 ( .A1(n974), .A2(n1913), .B1(n940), .B2(n1914), .ZN(n2319) );
OAI22_X1 U1306 ( .A1(n1041), .A2(n1915), .B1(n1008), .B2(n1916), .ZN(n2318)
);
OAI22_X1 U1307 ( .A1(n71), .A2(n41), .B1(n1075), .B2(n43), .ZN(n2317) );
OAI22_X1 U1308 ( .A1(n156), .A2(n1919), .B1(n121), .B2(n1920), .ZN(n2316) );
OAI22_X1 U1309 ( .A1(n2320), .A2(n1867), .B1(n1868), .B2(n1568), .ZN(N4512)
);
NOR4_X1 U1310 ( .A1(n2325), .A2(n2326), .A3(n2327), .A4(n2328), .ZN(n2324)
);
OAI22_X1 U1311 ( .A1(n179), .A2(n1877), .B1(n669), .B2(n1878), .ZN(n2328) );
OAI22_X1 U1312 ( .A1(n243), .A2(n1879), .B1(n211), .B2(n1880), .ZN(n2327) );
OAI22_X1 U1313 ( .A1(n307), .A2(n1881), .B1(n275), .B2(n1882), .ZN(n2326) );
OAI22_X1 U1314 ( .A1(n371), .A2(n1883), .B1(n339), .B2(n1884), .ZN(n2325) );
NOR4_X1 U1315 ( .A1(n2329), .A2(n2330), .A3(n2331), .A4(n2332), .ZN(n2323)
);
OAI22_X1 U1316 ( .A1(n435), .A2(n1889), .B1(n403), .B2(n1890), .ZN(n2332) );
OAI22_X1 U1317 ( .A1(n503), .A2(n1891), .B1(n469), .B2(n1892), .ZN(n2331) );
OAI22_X1 U1318 ( .A1(n570), .A2(n1893), .B1(n536), .B2(n1894), .ZN(n2330) );
OAI22_X1 U1319 ( .A1(n637), .A2(n1895), .B1(n603), .B2(n1896), .ZN(n2329) );
NOR4_X1 U1320 ( .A1(n2333), .A2(n2334), .A3(n2335), .A4(n2336), .ZN(n2322)
);
OAI22_X1 U1321 ( .A1(n704), .A2(n1901), .B1(n671), .B2(n1902), .ZN(n2336) );
OAI22_X1 U1322 ( .A1(n771), .A2(n1903), .B1(n738), .B2(n1904), .ZN(n2335) );
OAI22_X1 U1323 ( .A1(n839), .A2(n1905), .B1(n805), .B2(n1906), .ZN(n2334) );
OAI22_X1 U1324 ( .A1(n906), .A2(n39), .B1(n872), .B2(n1908), .ZN(n2333) );
NOR4_X1 U1325 ( .A1(n2337), .A2(n2338), .A3(n2339), .A4(n2340), .ZN(n2321)
);
OAI22_X1 U1326 ( .A1(n973), .A2(n1913), .B1(n939), .B2(n1914), .ZN(n2340) );
OAI22_X1 U1327 ( .A1(n1040), .A2(n1915), .B1(n1007), .B2(n1916), .ZN(n2339)
);
OAI22_X1 U1328 ( .A1(n69), .A2(n41), .B1(n1074), .B2(n1918), .ZN(n2338) );
OAI22_X1 U1329 ( .A1(n155), .A2(n1919), .B1(n119), .B2(n1920), .ZN(n2337) );
OAI22_X1 U1330 ( .A1(n2341), .A2(n1867), .B1(n1868), .B2(n1590), .ZN(N4510)
);
NOR4_X1 U1331 ( .A1(n2346), .A2(n2347), .A3(n2348), .A4(n2349), .ZN(n2345)
);
OAI22_X1 U1332 ( .A1(n178), .A2(n1877), .B1(n648), .B2(n1878), .ZN(n2349) );
OAI22_X1 U1333 ( .A1(n242), .A2(n1879), .B1(n210), .B2(n1880), .ZN(n2348) );
OAI22_X1 U1334 ( .A1(n306), .A2(n1881), .B1(n274), .B2(n1882), .ZN(n2347) );
OAI22_X1 U1335 ( .A1(n370), .A2(n1883), .B1(n338), .B2(n1884), .ZN(n2346) );
NOR4_X1 U1336 ( .A1(n2350), .A2(n2351), .A3(n2352), .A4(n2353), .ZN(n2344)
);
OAI22_X1 U1337 ( .A1(n434), .A2(n1889), .B1(n402), .B2(n1890), .ZN(n2353) );
OAI22_X1 U1338 ( .A1(n502), .A2(n1891), .B1(n468), .B2(n1892), .ZN(n2352) );
OAI22_X1 U1339 ( .A1(n569), .A2(n1893), .B1(n535), .B2(n1894), .ZN(n2351) );
OAI22_X1 U1340 ( .A1(n636), .A2(n1895), .B1(n602), .B2(n1896), .ZN(n2350) );
NOR4_X1 U1341 ( .A1(n2354), .A2(n2355), .A3(n2356), .A4(n2357), .ZN(n2343)
);
OAI22_X1 U1342 ( .A1(n703), .A2(n1901), .B1(n670), .B2(n1902), .ZN(n2357) );
OAI22_X1 U1343 ( .A1(n770), .A2(n1903), .B1(n737), .B2(n1904), .ZN(n2356) );
OAI22_X1 U1344 ( .A1(n838), .A2(n1905), .B1(n804), .B2(n1906), .ZN(n2355) );
OAI22_X1 U1345 ( .A1(n905), .A2(n39), .B1(n871), .B2(n1908), .ZN(n2354) );
NOR4_X1 U1346 ( .A1(n2358), .A2(n2359), .A3(n2360), .A4(n2361), .ZN(n2342)
);
OAI22_X1 U1347 ( .A1(n972), .A2(n1913), .B1(n938), .B2(n1914), .ZN(n2361) );
OAI22_X1 U1348 ( .A1(n1039), .A2(n1915), .B1(n1006), .B2(n1916), .ZN(n2360)
);
OAI22_X1 U1349 ( .A1(n67), .A2(n41), .B1(n1073), .B2(n1918), .ZN(n2359) );
OAI22_X1 U1350 ( .A1(n154), .A2(n1919), .B1(n118), .B2(n1920), .ZN(n2358) );
OAI22_X1 U1351 ( .A1(n2362), .A2(n1867), .B1(n1868), .B2(n1612), .ZN(N4508)
);
NOR4_X1 U1352 ( .A1(n2367), .A2(n2368), .A3(n2369), .A4(n2370), .ZN(n2366)
);
OAI22_X1 U1353 ( .A1(n175), .A2(n1877), .B1(n627), .B2(n1878), .ZN(n2370) );
OAI22_X1 U1354 ( .A1(n241), .A2(n1879), .B1(n209), .B2(n1880), .ZN(n2369) );
OAI22_X1 U1355 ( .A1(n305), .A2(n1881), .B1(n273), .B2(n1882), .ZN(n2368) );
OAI22_X1 U1356 ( .A1(n369), .A2(n1883), .B1(n337), .B2(n1884), .ZN(n2367) );
NOR4_X1 U1357 ( .A1(n2371), .A2(n2372), .A3(n2373), .A4(n2374), .ZN(n2365)
);
OAI22_X1 U1358 ( .A1(n433), .A2(n1889), .B1(n401), .B2(n1890), .ZN(n2374) );
OAI22_X1 U1359 ( .A1(n500), .A2(n1891), .B1(n467), .B2(n1892), .ZN(n2373) );
OAI22_X1 U1360 ( .A1(n568), .A2(n1893), .B1(n534), .B2(n1894), .ZN(n2372) );
OAI22_X1 U1361 ( .A1(n635), .A2(n1895), .B1(n601), .B2(n1896), .ZN(n2371) );
NOR4_X1 U1362 ( .A1(n2375), .A2(n2376), .A3(n2377), .A4(n2378), .ZN(n2364)
);
OAI22_X1 U1363 ( .A1(n702), .A2(n1901), .B1(n668), .B2(n1902), .ZN(n2378) );
OAI22_X1 U1364 ( .A1(n769), .A2(n1903), .B1(n736), .B2(n1904), .ZN(n2377) );
OAI22_X1 U1365 ( .A1(n836), .A2(n1905), .B1(n803), .B2(n1906), .ZN(n2376) );
OAI22_X1 U1366 ( .A1(n904), .A2(n39), .B1(n870), .B2(n1908), .ZN(n2375) );
NOR4_X1 U1367 ( .A1(n2379), .A2(n2380), .A3(n2381), .A4(n2382), .ZN(n2363)
);
OAI22_X1 U1368 ( .A1(n971), .A2(n1913), .B1(n937), .B2(n1914), .ZN(n2382) );
OAI22_X1 U1369 ( .A1(n1038), .A2(n1915), .B1(n1004), .B2(n1916), .ZN(n2381)
);
OAI22_X1 U1370 ( .A1(n65), .A2(n41), .B1(n1072), .B2(n1918), .ZN(n2380) );
OAI22_X1 U1371 ( .A1(n152), .A2(n1919), .B1(n117), .B2(n1920), .ZN(n2379) );
OAI22_X1 U1372 ( .A1(n2383), .A2(n1867), .B1(n1868), .B2(n1634), .ZN(N4506)
);
NOR4_X1 U1373 ( .A1(n2388), .A2(n2389), .A3(n2390), .A4(n2391), .ZN(n2387)
);
OAI22_X1 U1374 ( .A1(n164), .A2(n1877), .B1(n606), .B2(n1878), .ZN(n2391) );
OAI22_X1 U1375 ( .A1(n240), .A2(n1879), .B1(n208), .B2(n1880), .ZN(n2390) );
OAI22_X1 U1376 ( .A1(n304), .A2(n1881), .B1(n272), .B2(n1882), .ZN(n2389) );
OAI22_X1 U1377 ( .A1(n368), .A2(n1883), .B1(n336), .B2(n1884), .ZN(n2388) );
NOR4_X1 U1378 ( .A1(n2392), .A2(n2393), .A3(n2394), .A4(n2395), .ZN(n2386)
);
OAI22_X1 U1379 ( .A1(n432), .A2(n1889), .B1(n400), .B2(n1890), .ZN(n2395) );
OAI22_X1 U1380 ( .A1(n499), .A2(n1891), .B1(n466), .B2(n1892), .ZN(n2394) );
OAI22_X1 U1381 ( .A1(n567), .A2(n1893), .B1(n533), .B2(n1894), .ZN(n2393) );
OAI22_X1 U1382 ( .A1(n634), .A2(n1895), .B1(n600), .B2(n1896), .ZN(n2392) );
NOR4_X1 U1383 ( .A1(n2396), .A2(n2397), .A3(n2398), .A4(n2399), .ZN(n2385)
);
OAI22_X1 U1384 ( .A1(n701), .A2(n1901), .B1(n667), .B2(n1902), .ZN(n2399) );
OAI22_X1 U1385 ( .A1(n768), .A2(n1903), .B1(n735), .B2(n1904), .ZN(n2398) );
OAI22_X1 U1386 ( .A1(n835), .A2(n1905), .B1(n802), .B2(n1906), .ZN(n2397) );
OAI22_X1 U1387 ( .A1(n903), .A2(n39), .B1(n869), .B2(n1908), .ZN(n2396) );
NOR4_X1 U1388 ( .A1(n2400), .A2(n2401), .A3(n2402), .A4(n2403), .ZN(n2384)
);
OAI22_X1 U1389 ( .A1(n970), .A2(n1913), .B1(n936), .B2(n1914), .ZN(n2403) );
OAI22_X1 U1390 ( .A1(n1037), .A2(n1915), .B1(n1003), .B2(n1916), .ZN(n2402)
);
OAI22_X1 U1391 ( .A1(n63), .A2(n41), .B1(n1071), .B2(n1918), .ZN(n2401) );
OAI22_X1 U1392 ( .A1(n151), .A2(n1919), .B1(n116), .B2(n45), .ZN(n2400) );
OAI22_X1 U1393 ( .A1(n2404), .A2(n1867), .B1(n1868), .B2(n1656), .ZN(N4504)
);
NOR4_X1 U1394 ( .A1(n2409), .A2(n2410), .A3(n2411), .A4(n2412), .ZN(n2408)
);
OAI22_X1 U1395 ( .A1(n153), .A2(n1877), .B1(n585), .B2(n1878), .ZN(n2412) );
OAI22_X1 U1396 ( .A1(n239), .A2(n1879), .B1(n207), .B2(n1880), .ZN(n2411) );
OAI22_X1 U1397 ( .A1(n303), .A2(n1881), .B1(n271), .B2(n1882), .ZN(n2410) );
OAI22_X1 U1398 ( .A1(n367), .A2(n1883), .B1(n335), .B2(n1884), .ZN(n2409) );
NOR4_X1 U1399 ( .A1(n2413), .A2(n2414), .A3(n2415), .A4(n2416), .ZN(n2407)
);
OAI22_X1 U1400 ( .A1(n431), .A2(n1889), .B1(n399), .B2(n1890), .ZN(n2416) );
OAI22_X1 U1401 ( .A1(n498), .A2(n1891), .B1(n465), .B2(n1892), .ZN(n2415) );
OAI22_X1 U1402 ( .A1(n566), .A2(n1893), .B1(n532), .B2(n1894), .ZN(n2414) );
OAI22_X1 U1403 ( .A1(n633), .A2(n1895), .B1(n599), .B2(n1896), .ZN(n2413) );
NOR4_X1 U1404 ( .A1(n2417), .A2(n2418), .A3(n2419), .A4(n2420), .ZN(n2406)
);
OAI22_X1 U1405 ( .A1(n700), .A2(n1901), .B1(n666), .B2(n1902), .ZN(n2420) );
OAI22_X1 U1406 ( .A1(n767), .A2(n1903), .B1(n734), .B2(n1904), .ZN(n2419) );
OAI22_X1 U1407 ( .A1(n834), .A2(n1905), .B1(n801), .B2(n1906), .ZN(n2418) );
OAI22_X1 U1408 ( .A1(n902), .A2(n39), .B1(n868), .B2(n1908), .ZN(n2417) );
NOR4_X1 U1409 ( .A1(n2421), .A2(n2422), .A3(n2423), .A4(n2424), .ZN(n2405)
);
OAI22_X1 U1410 ( .A1(n969), .A2(n1913), .B1(n935), .B2(n1914), .ZN(n2424) );
OAI22_X1 U1411 ( .A1(n1036), .A2(n1915), .B1(n1002), .B2(n1916), .ZN(n2423)
);
OAI22_X1 U1412 ( .A1(n61), .A2(n41), .B1(n1070), .B2(n1918), .ZN(n2422) );
OAI22_X1 U1413 ( .A1(n150), .A2(n1919), .B1(n115), .B2(n1920), .ZN(n2421) );
OAI22_X1 U1414 ( .A1(n2425), .A2(n1867), .B1(n1868), .B2(n1678), .ZN(N4502)
);
NOR4_X1 U1415 ( .A1(n2430), .A2(n2431), .A3(n2432), .A4(n2433), .ZN(n2429)
);
OAI22_X1 U1416 ( .A1(n142), .A2(n1877), .B1(n564), .B2(n1878), .ZN(n2433) );
OAI22_X1 U1417 ( .A1(n238), .A2(n1879), .B1(n206), .B2(n1880), .ZN(n2432) );
OAI22_X1 U1418 ( .A1(n302), .A2(n1881), .B1(n270), .B2(n1882), .ZN(n2431) );
OAI22_X1 U1419 ( .A1(n366), .A2(n1883), .B1(n334), .B2(n1884), .ZN(n2430) );
NOR4_X1 U1420 ( .A1(n2434), .A2(n2435), .A3(n2436), .A4(n2437), .ZN(n2428)
);
OAI22_X1 U1421 ( .A1(n430), .A2(n1889), .B1(n398), .B2(n1890), .ZN(n2437) );
OAI22_X1 U1422 ( .A1(n497), .A2(n1891), .B1(n464), .B2(n1892), .ZN(n2436) );
OAI22_X1 U1423 ( .A1(n565), .A2(n1893), .B1(n531), .B2(n1894), .ZN(n2435) );
OAI22_X1 U1424 ( .A1(n632), .A2(n1895), .B1(n598), .B2(n1896), .ZN(n2434) );
NOR4_X1 U1425 ( .A1(n2438), .A2(n2439), .A3(n2440), .A4(n2441), .ZN(n2427)
);
OAI22_X1 U1426 ( .A1(n699), .A2(n1901), .B1(n665), .B2(n1902), .ZN(n2441) );
OAI22_X1 U1427 ( .A1(n766), .A2(n1903), .B1(n733), .B2(n1904), .ZN(n2440) );
OAI22_X1 U1428 ( .A1(n833), .A2(n1905), .B1(n800), .B2(n1906), .ZN(n2439) );
OAI22_X1 U1429 ( .A1(n901), .A2(n39), .B1(n867), .B2(n1908), .ZN(n2438) );
NOR4_X1 U1430 ( .A1(n2442), .A2(n2443), .A3(n2444), .A4(n2445), .ZN(n2426)
);
OAI22_X1 U1431 ( .A1(n968), .A2(n1913), .B1(n934), .B2(n1914), .ZN(n2445) );
OAI22_X1 U1432 ( .A1(n1035), .A2(n1915), .B1(n1001), .B2(n1916), .ZN(n2444)
);
OAI22_X1 U1433 ( .A1(n59), .A2(n1917), .B1(n1069), .B2(n1918), .ZN(n2443) );
OAI22_X1 U1434 ( .A1(n149), .A2(n1919), .B1(n114), .B2(n45), .ZN(n2442) );
OAI22_X1 U1435 ( .A1(n2446), .A2(n1867), .B1(n1868), .B2(n1700), .ZN(N4500)
);
NOR4_X1 U1436 ( .A1(n2451), .A2(n2452), .A3(n2453), .A4(n2454), .ZN(n2450)
);
OAI22_X1 U1437 ( .A1(n131), .A2(n1877), .B1(n543), .B2(n1878), .ZN(n2454) );
OAI22_X1 U1438 ( .A1(n237), .A2(n1879), .B1(n205), .B2(n1880), .ZN(n2453) );
OAI22_X1 U1439 ( .A1(n301), .A2(n1881), .B1(n269), .B2(n1882), .ZN(n2452) );
OAI22_X1 U1440 ( .A1(n365), .A2(n1883), .B1(n333), .B2(n1884), .ZN(n2451) );
NOR4_X1 U1441 ( .A1(n2455), .A2(n2456), .A3(n2457), .A4(n2458), .ZN(n2449)
);
OAI22_X1 U1442 ( .A1(n429), .A2(n1889), .B1(n397), .B2(n1890), .ZN(n2458) );
OAI22_X1 U1443 ( .A1(n496), .A2(n1891), .B1(n463), .B2(n1892), .ZN(n2457) );
OAI22_X1 U1444 ( .A1(n563), .A2(n1893), .B1(n530), .B2(n1894), .ZN(n2456) );
OAI22_X1 U1445 ( .A1(n631), .A2(n1895), .B1(n597), .B2(n1896), .ZN(n2455) );
NOR4_X1 U1446 ( .A1(n2459), .A2(n2460), .A3(n2461), .A4(n2462), .ZN(n2448)
);
OAI22_X1 U1447 ( .A1(n698), .A2(n1901), .B1(n664), .B2(n1902), .ZN(n2462) );
OAI22_X1 U1448 ( .A1(n765), .A2(n1903), .B1(n731), .B2(n1904), .ZN(n2461) );
OAI22_X1 U1449 ( .A1(n832), .A2(n1905), .B1(n799), .B2(n1906), .ZN(n2460) );
OAI22_X1 U1450 ( .A1(n899), .A2(n39), .B1(n866), .B2(n1908), .ZN(n2459) );
NOR4_X1 U1451 ( .A1(n2463), .A2(n2464), .A3(n2465), .A4(n2466), .ZN(n2447)
);
OAI22_X1 U1452 ( .A1(n967), .A2(n1913), .B1(n933), .B2(n1914), .ZN(n2466) );
OAI22_X1 U1453 ( .A1(n1034), .A2(n1915), .B1(n1000), .B2(n1916), .ZN(n2465)
);
OAI22_X1 U1454 ( .A1(n57), .A2(n1917), .B1(n1067), .B2(n1918), .ZN(n2464) );
OAI22_X1 U1455 ( .A1(n148), .A2(n1919), .B1(n113), .B2(n1920), .ZN(n2463) );
OAI22_X1 U1456 ( .A1(n2467), .A2(n1867), .B1(n1868), .B2(n1722), .ZN(N4498)
);
NOR4_X1 U1457 ( .A1(n2472), .A2(n2473), .A3(n2474), .A4(n2475), .ZN(n2471)
);
OAI22_X1 U1458 ( .A1(n120), .A2(n1877), .B1(n522), .B2(n1878), .ZN(n2475) );
OAI22_X1 U1459 ( .A1(n236), .A2(n1879), .B1(n204), .B2(n1880), .ZN(n2474) );
OAI22_X1 U1460 ( .A1(n300), .A2(n1881), .B1(n268), .B2(n1882), .ZN(n2473) );
OAI22_X1 U1461 ( .A1(n364), .A2(n1883), .B1(n332), .B2(n1884), .ZN(n2472) );
NOR4_X1 U1462 ( .A1(n2476), .A2(n2477), .A3(n2478), .A4(n2479), .ZN(n2470)
);
OAI22_X1 U1463 ( .A1(n428), .A2(n1889), .B1(n396), .B2(n1890), .ZN(n2479) );
OAI22_X1 U1464 ( .A1(n495), .A2(n1891), .B1(n462), .B2(n1892), .ZN(n2478) );
OAI22_X1 U1465 ( .A1(n562), .A2(n1893), .B1(n529), .B2(n1894), .ZN(n2477) );
OAI22_X1 U1466 ( .A1(n630), .A2(n1895), .B1(n596), .B2(n1896), .ZN(n2476) );
NOR4_X1 U1467 ( .A1(n2480), .A2(n2481), .A3(n2482), .A4(n2483), .ZN(n2469)
);
OAI22_X1 U1468 ( .A1(n697), .A2(n1901), .B1(n663), .B2(n1902), .ZN(n2483) );
OAI22_X1 U1469 ( .A1(n764), .A2(n1903), .B1(n730), .B2(n1904), .ZN(n2482) );
OAI22_X1 U1470 ( .A1(n831), .A2(n1905), .B1(n798), .B2(n1906), .ZN(n2481) );
OAI22_X1 U1471 ( .A1(n898), .A2(n39), .B1(n865), .B2(n1908), .ZN(n2480) );
NOR4_X1 U1472 ( .A1(n2484), .A2(n2485), .A3(n2486), .A4(n2487), .ZN(n2468)
);
OAI22_X1 U1473 ( .A1(n966), .A2(n1913), .B1(n932), .B2(n1914), .ZN(n2487) );
OAI22_X1 U1474 ( .A1(n1033), .A2(n1915), .B1(n999), .B2(n1916), .ZN(n2486)
);
OAI22_X1 U1475 ( .A1(n55), .A2(n1917), .B1(n1066), .B2(n1918), .ZN(n2485) );
OAI22_X1 U1476 ( .A1(n147), .A2(n1919), .B1(n112), .B2(n1920), .ZN(n2484) );
OAI22_X1 U1477 ( .A1(n2488), .A2(n1867), .B1(n1868), .B2(n1744), .ZN(N4496)
);
NOR4_X1 U1478 ( .A1(n2489), .A2(n2490), .A3(n2491), .A4(n2492), .ZN(n2488)
);
OAI211_X1 U1479 ( .C1(n1100), .C2(n1917), .A(n2493), .B(n2494), .ZN(n2492)
);
NOR4_X1 U1480 ( .A1(n2495), .A2(n2496), .A3(n2497), .A4(n2498), .ZN(n2494)
);
OAI22_X1 U1481 ( .A1(n109), .A2(n1877), .B1(n203), .B2(n1880), .ZN(n2498) );
OAI22_X1 U1482 ( .A1(n235), .A2(n1879), .B1(n267), .B2(n1882), .ZN(n2497) );
OAI22_X1 U1483 ( .A1(n299), .A2(n1881), .B1(n331), .B2(n1884), .ZN(n2496) );
OAI22_X1 U1484 ( .A1(n363), .A2(n1883), .B1(n395), .B2(n1890), .ZN(n2495) );
NOR4_X1 U1485 ( .A1(n2499), .A2(n2500), .A3(n2501), .A4(n2502), .ZN(n2493)
);
OAI22_X1 U1486 ( .A1(n427), .A2(n1889), .B1(n461), .B2(n1892), .ZN(n2502) );
OAI22_X1 U1487 ( .A1(n494), .A2(n1891), .B1(n528), .B2(n1894), .ZN(n2501) );
OAI22_X1 U1488 ( .A1(n561), .A2(n1893), .B1(n595), .B2(n1896), .ZN(n2500) );
OAI22_X1 U1489 ( .A1(n629), .A2(n1895), .B1(n662), .B2(n1902), .ZN(n2499) );
OAI211_X1 U1490 ( .C1(n146), .C2(n1919), .A(n2503), .B(n2504), .ZN(n2491) );
NOR4_X1 U1491 ( .A1(n2505), .A2(n2506), .A3(n2507), .A4(n2508), .ZN(n2504)
);
OAI22_X1 U1492 ( .A1(n763), .A2(n1903), .B1(n797), .B2(n1906), .ZN(n2508) );
OAI22_X1 U1493 ( .A1(n696), .A2(n1901), .B1(n729), .B2(n1904), .ZN(n2507) );
OAI22_X1 U1494 ( .A1(n897), .A2(n39), .B1(n931), .B2(n1914), .ZN(n2506) );
OAI22_X1 U1495 ( .A1(n830), .A2(n1905), .B1(n864), .B2(n1908), .ZN(n2505) );
OAI22_X1 U1496 ( .A1(n1878), .A2(n501), .B1(n45), .B2(n111), .ZN(n2509) );
OAI22_X1 U1497 ( .A1(n1032), .A2(n1915), .B1(n1065), .B2(n1918), .ZN(n2490)
);
OAI22_X1 U1498 ( .A1(n965), .A2(n1913), .B1(n998), .B2(n1916), .ZN(n2489) );
OAI22_X1 U1499 ( .A1(n2510), .A2(n1867), .B1(n1868), .B2(n1766), .ZN(N4494)
);
NOR4_X1 U1500 ( .A1(n2515), .A2(n2516), .A3(n2517), .A4(n2518), .ZN(n2514)
);
OAI22_X1 U1501 ( .A1(n97), .A2(n1877), .B1(n480), .B2(n1878), .ZN(n2518) );
OAI22_X1 U1502 ( .A1(n234), .A2(n1879), .B1(n202), .B2(n1880), .ZN(n2517) );
OAI22_X1 U1503 ( .A1(n298), .A2(n1881), .B1(n266), .B2(n1882), .ZN(n2516) );
OAI22_X1 U1504 ( .A1(n362), .A2(n1883), .B1(n330), .B2(n1884), .ZN(n2515) );
NOR4_X1 U1505 ( .A1(n2519), .A2(n2520), .A3(n2521), .A4(n2522), .ZN(n2513)
);
OAI22_X1 U1506 ( .A1(n426), .A2(n1889), .B1(n394), .B2(n1890), .ZN(n2522) );
OAI22_X1 U1507 ( .A1(n493), .A2(n1891), .B1(n460), .B2(n1892), .ZN(n2521) );
OAI22_X1 U1508 ( .A1(n560), .A2(n1893), .B1(n527), .B2(n1894), .ZN(n2520) );
OAI22_X1 U1509 ( .A1(n628), .A2(n1895), .B1(n594), .B2(n1896), .ZN(n2519) );
NOR4_X1 U1510 ( .A1(n2523), .A2(n2524), .A3(n2525), .A4(n2526), .ZN(n2512)
);
OAI22_X1 U1511 ( .A1(n695), .A2(n1901), .B1(n661), .B2(n1902), .ZN(n2526) );
OAI22_X1 U1512 ( .A1(n762), .A2(n1903), .B1(n728), .B2(n1904), .ZN(n2525) );
OAI22_X1 U1513 ( .A1(n829), .A2(n1905), .B1(n796), .B2(n1906), .ZN(n2524) );
OAI22_X1 U1514 ( .A1(n896), .A2(n39), .B1(n863), .B2(n1908), .ZN(n2523) );
NOR4_X1 U1515 ( .A1(n2527), .A2(n2528), .A3(n2529), .A4(n2530), .ZN(n2511)
);
OAI22_X1 U1516 ( .A1(n964), .A2(n1913), .B1(n930), .B2(n1914), .ZN(n2530) );
OAI22_X1 U1517 ( .A1(n1031), .A2(n1915), .B1(n997), .B2(n1916), .ZN(n2529)
);
OAI22_X1 U1518 ( .A1(n1099), .A2(n1917), .B1(n1064), .B2(n1918), .ZN(n2528)
);
OAI22_X1 U1519 ( .A1(n145), .A2(n1919), .B1(n110), .B2(n1920), .ZN(n2527) );
OAI22_X1 U1520 ( .A1(n2531), .A2(n1867), .B1(n1868), .B2(n1788), .ZN(N4492)
);
NOR4_X1 U1521 ( .A1(n2536), .A2(n2537), .A3(n2538), .A4(n2539), .ZN(n2535)
);
OAI22_X1 U1522 ( .A1(n75), .A2(n1877), .B1(n459), .B2(n1878), .ZN(n2539) );
OAI22_X1 U1523 ( .A1(n233), .A2(n1879), .B1(n201), .B2(n1880), .ZN(n2538) );
OAI22_X1 U1524 ( .A1(n297), .A2(n1881), .B1(n265), .B2(n1882), .ZN(n2537) );
OAI22_X1 U1525 ( .A1(n361), .A2(n1883), .B1(n329), .B2(n1884), .ZN(n2536) );
NOR4_X1 U1526 ( .A1(n2540), .A2(n2541), .A3(n2542), .A4(n2543), .ZN(n2534)
);
OAI22_X1 U1527 ( .A1(n425), .A2(n1889), .B1(n393), .B2(n1890), .ZN(n2543) );
OAI22_X1 U1528 ( .A1(n492), .A2(n1891), .B1(n458), .B2(n1892), .ZN(n2542) );
OAI22_X1 U1529 ( .A1(n559), .A2(n1893), .B1(n526), .B2(n1894), .ZN(n2541) );
OAI22_X1 U1530 ( .A1(n626), .A2(n1895), .B1(n593), .B2(n1896), .ZN(n2540) );
NOR4_X1 U1531 ( .A1(n2544), .A2(n2545), .A3(n2546), .A4(n2547), .ZN(n2533)
);
OAI22_X1 U1532 ( .A1(n694), .A2(n1901), .B1(n660), .B2(n1902), .ZN(n2547) );
OAI22_X1 U1533 ( .A1(n761), .A2(n1903), .B1(n727), .B2(n1904), .ZN(n2546) );
OAI22_X1 U1534 ( .A1(n828), .A2(n1905), .B1(n794), .B2(n1906), .ZN(n2545) );
OAI22_X1 U1535 ( .A1(n895), .A2(n39), .B1(n862), .B2(n1908), .ZN(n2544) );
NOR4_X1 U1536 ( .A1(n2548), .A2(n2549), .A3(n2550), .A4(n2551), .ZN(n2532)
);
OAI22_X1 U1537 ( .A1(n962), .A2(n1913), .B1(n929), .B2(n1914), .ZN(n2551) );
OAI22_X1 U1538 ( .A1(n1030), .A2(n1915), .B1(n996), .B2(n1916), .ZN(n2550)
);
OAI22_X1 U1539 ( .A1(n1098), .A2(n1917), .B1(n1063), .B2(n1918), .ZN(n2549)
);
OAI22_X1 U1540 ( .A1(n144), .A2(n1919), .B1(n108), .B2(n1920), .ZN(n2548) );
OAI22_X1 U1541 ( .A1(n2552), .A2(n1867), .B1(n1868), .B2(n1810), .ZN(N4490)
);
OAI221_X1 U1542 ( .B1(n1825), .B2(ADD_RD1[2]), .C1(n1826), .C2(ADD_RD1[0]),
.A(n2557), .ZN(n2556) );
AOI22_X1 U1543 ( .A1(n1825), .A2(ADD_RD1[2]), .B1(n1826), .B2(ADD_RD1[0]),
.ZN(n2557) );
AOI221_X1 U1544 ( .B1(n2558), .B2(ADD_WR[4]), .C1(n1829), .C2(ADD_RD1[3]),
.A(n2559), .ZN(n2553) );
OAI22_X1 U1545 ( .A1(ADD_WR[4]), .A2(n2558), .B1(n1829), .B2(ADD_RD1[3]),
.ZN(n2559) );
NOR4_X1 U1546 ( .A1(n2568), .A2(n2569), .A3(n2570), .A4(n2571), .ZN(n2567)
);
OAI22_X1 U1547 ( .A1(n53), .A2(n1877), .B1(n438), .B2(n1878), .ZN(n2571) );
OAI22_X1 U1548 ( .A1(n232), .A2(n1879), .B1(n200), .B2(n1880), .ZN(n2570) );
OAI22_X1 U1549 ( .A1(n296), .A2(n1881), .B1(n264), .B2(n1882), .ZN(n2569) );
OAI22_X1 U1550 ( .A1(n360), .A2(n1883), .B1(n328), .B2(n1884), .ZN(n2568) );
NOR3_X1 U1551 ( .A1(n2558), .A2(n2578), .A3(n2579), .ZN(n2573) );
NAND2_X1 U1552 ( .A1(ADD_RD1[4]), .A2(ADD_RD1[3]), .ZN(n2580) );
NOR4_X1 U1553 ( .A1(n2581), .A2(n2582), .A3(n2583), .A4(n2584), .ZN(n2566)
);
OAI22_X1 U1554 ( .A1(n424), .A2(n1889), .B1(n392), .B2(n1890), .ZN(n2584) );
OAI22_X1 U1555 ( .A1(n491), .A2(n1891), .B1(n457), .B2(n1892), .ZN(n2583) );
OAI22_X1 U1556 ( .A1(n558), .A2(n1893), .B1(n525), .B2(n1894), .ZN(n2582) );
OAI22_X1 U1557 ( .A1(n625), .A2(n1895), .B1(n592), .B2(n1896), .ZN(n2581) );
NOR3_X1 U1558 ( .A1(ADD_RD1[3]), .A2(n2558), .A3(n2579), .ZN(n2585) );
NOR3_X1 U1559 ( .A1(ADD_RD1[3]), .A2(ADD_RD1[0]), .A3(n2558), .ZN(n2586) );
NOR4_X1 U1560 ( .A1(n2587), .A2(n2588), .A3(n2589), .A4(n2590), .ZN(n2565)
);
OAI22_X1 U1561 ( .A1(n693), .A2(n1901), .B1(n659), .B2(n1902), .ZN(n2590) );
OAI22_X1 U1562 ( .A1(n760), .A2(n1903), .B1(n726), .B2(n1904), .ZN(n2589) );
OAI22_X1 U1563 ( .A1(n827), .A2(n1905), .B1(n793), .B2(n1906), .ZN(n2588) );
OAI22_X1 U1564 ( .A1(n894), .A2(n39), .B1(n861), .B2(n1908), .ZN(n2587) );
NOR3_X1 U1565 ( .A1(ADD_RD1[4]), .A2(n2578), .A3(n2579), .ZN(n2591) );
NAND2_X1 U1566 ( .A1(n2577), .A2(n2592), .ZN(n1907) );
NOR3_X1 U1567 ( .A1(ADD_RD1[4]), .A2(ADD_RD1[0]), .A3(n2578), .ZN(n2592) );
NOR4_X1 U1568 ( .A1(n2593), .A2(n2594), .A3(n2595), .A4(n2596), .ZN(n2564)
);
OAI22_X1 U1569 ( .A1(n961), .A2(n1913), .B1(n928), .B2(n1914), .ZN(n2596) );
OAI22_X1 U1570 ( .A1(n1029), .A2(n1915), .B1(n995), .B2(n1916), .ZN(n2595)
);
OAI22_X1 U1571 ( .A1(n1097), .A2(n1917), .B1(n1062), .B2(n1918), .ZN(n2594)
);
NAND2_X1 U1572 ( .A1(n2576), .A2(n2597), .ZN(n1918) );
NAND2_X1 U1573 ( .A1(n2598), .A2(n2576), .ZN(n1917) );
OAI22_X1 U1574 ( .A1(n143), .A2(n1919), .B1(n107), .B2(n45), .ZN(n2593) );
NAND2_X1 U1575 ( .A1(n2577), .A2(n2597), .ZN(n1920) );
NOR3_X1 U1576 ( .A1(ADD_RD1[4]), .A2(ADD_RD1[3]), .A3(n2579), .ZN(n2597) );
NOR3_X1 U1577 ( .A1(ADD_RD1[4]), .A2(ADD_RD1[3]), .A3(ADD_RD1[0]), .ZN(n2598) );
OAI21_X1 U1578 ( .B1(n2599), .B2(n2600), .A(n47), .ZN(N4423) );
OAI21_X1 U1579 ( .B1(n2600), .B2(n2601), .A(n47), .ZN(N4359) );
OAI21_X1 U1580 ( .B1(n2600), .B2(n2602), .A(n47), .ZN(N4295) );
OAI21_X1 U1581 ( .B1(n2600), .B2(n2603), .A(n47), .ZN(N4231) );
OAI21_X1 U1582 ( .B1(n2600), .B2(n2604), .A(n47), .ZN(N4167) );
OAI21_X1 U1583 ( .B1(n2600), .B2(n2605), .A(n47), .ZN(N4103) );
OAI21_X1 U1584 ( .B1(n2600), .B2(n2606), .A(n47), .ZN(N4039) );
NAND2_X1 U1585 ( .A1(n2561), .A2(WR), .ZN(n2600) );
OAI21_X1 U1586 ( .B1(n2563), .B2(n2607), .A(n49), .ZN(N3975) );
OAI21_X1 U1587 ( .B1(n2599), .B2(n2607), .A(n51), .ZN(N3911) );
OAI21_X1 U1588 ( .B1(n2607), .B2(n2601), .A(n49), .ZN(N3847) );
OAI21_X1 U1589 ( .B1(n2607), .B2(n2602), .A(n49), .ZN(N3783) );
OAI21_X1 U1590 ( .B1(n2607), .B2(n2603), .A(n49), .ZN(N3719) );
OAI21_X1 U1591 ( .B1(n2607), .B2(n2604), .A(n49), .ZN(N3655) );
OAI21_X1 U1592 ( .B1(n2607), .B2(n2605), .A(n49), .ZN(N3591) );
OAI21_X1 U1593 ( .B1(n2607), .B2(n2606), .A(n49), .ZN(N3527) );
INV_X1 U1594 ( .A(WR), .ZN(n2562) );
OAI21_X1 U1595 ( .B1(n2563), .B2(n2608), .A(n49), .ZN(N3463) );
OAI21_X1 U1596 ( .B1(n2599), .B2(n2608), .A(n47), .ZN(N3399) );
OAI21_X1 U1597 ( .B1(n2608), .B2(n2601), .A(n49), .ZN(N3335) );
OAI21_X1 U1598 ( .B1(n2608), .B2(n2602), .A(n49), .ZN(N3271) );
OAI21_X1 U1599 ( .B1(n2608), .B2(n2603), .A(n47), .ZN(N3207) );
OAI21_X1 U1600 ( .B1(n2608), .B2(n2604), .A(n47), .ZN(N3143) );
OAI21_X1 U1601 ( .B1(n2608), .B2(n2605), .A(n51), .ZN(N3079) );
OAI21_X1 U1602 ( .B1(n2608), .B2(n2606), .A(n49), .ZN(N3015) );
NAND3_X1 U1603 ( .A1(ADD_WR[4]), .A2(WR), .A3(n1829), .ZN(n2608) );
OAI21_X1 U1604 ( .B1(n2563), .B2(n2609), .A(n51), .ZN(N2951) );
OAI21_X1 U1605 ( .B1(n2599), .B2(n2609), .A(n49), .ZN(N2887) );
NAND3_X1 U1606 ( .A1(ADD_WR[0]), .A2(n1825), .A3(n1823), .ZN(n2599) );
OAI21_X1 U1607 ( .B1(n2609), .B2(n2601), .A(n47), .ZN(N2823) );
NAND3_X1 U1608 ( .A1(ADD_WR[1]), .A2(n1826), .A3(n1825), .ZN(n2601) );
OAI21_X1 U1609 ( .B1(n2609), .B2(n2602), .A(n47), .ZN(N2759) );
NAND3_X1 U1610 ( .A1(ADD_WR[0]), .A2(ADD_WR[1]), .A3(n1825), .ZN(n2602) );
OAI21_X1 U1611 ( .B1(n2609), .B2(n2603), .A(n51), .ZN(N2695) );
NAND3_X1 U1612 ( .A1(ADD_WR[2]), .A2(n1826), .A3(n1823), .ZN(n2603) );
OAI21_X1 U1613 ( .B1(n2609), .B2(n2604), .A(n49), .ZN(N2631) );
NAND3_X1 U1614 ( .A1(ADD_WR[2]), .A2(ADD_WR[0]), .A3(n1823), .ZN(n2604) );
OAI21_X1 U1615 ( .B1(n2609), .B2(n2605), .A(n49), .ZN(N2567) );
NAND3_X1 U1616 ( .A1(ADD_WR[2]), .A2(ADD_WR[1]), .A3(n1826), .ZN(n2605) );
OAI21_X1 U1617 ( .B1(n2609), .B2(n2606), .A(n51), .ZN(N2503) );
NAND3_X1 U1618 ( .A1(ADD_WR[0]), .A2(ADD_WR[2]), .A3(ADD_WR[1]), .ZN(n2606)
);
NAND3_X1 U1619 ( .A1(ADD_WR[4]), .A2(ADD_WR[3]), .A3(WR), .ZN(n2609) );
endmodule
module dlx_cu_MICROCODE_MEM_SIZE64_FUNC_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE13 (
Clk, Rst, IR_IN, stall_exe_i, mispredict_i, D1_i, D2_i, S1_LATCH_EN,
S2_LATCH_EN, S3_LATCH_EN, S_MUX_PC_BUS, S_EXT, S_EXT_SIGN, S_EQ_NEQ,
S_MUX_DEST, S_MUX_LINK, S_MEM_W_R, S_MEM_EN, S_RF_W_wb, S_RF_W_mem,
S_RF_W_exe, S_MUX_ALUIN, stall_exe_o, stall_dec_o, stall_fetch_o,
stall_btb_o, was_branch_o, was_jmp_o, ALU_WORD_o, .ALU_OPCODE({
\ALU_OPCODE[4] , \ALU_OPCODE[3] , \ALU_OPCODE[2] , \ALU_OPCODE[1] ,
\ALU_OPCODE[0] }), S_MUX_MEM_BAR );
input [31:0] IR_IN;
input [4:0] D1_i;
input [4:0] D2_i;
output [1:0] S_MUX_PC_BUS;
output [1:0] S_MUX_DEST;
output [12:0] ALU_WORD_o;
input Clk, Rst, stall_exe_i, mispredict_i;
output S1_LATCH_EN, S2_LATCH_EN, S3_LATCH_EN, S_EXT, S_EXT_SIGN, S_EQ_NEQ,
S_MUX_LINK, S_MEM_W_R, S_MEM_EN, S_RF_W_wb, S_RF_W_mem, S_RF_W_exe,
S_MUX_ALUIN, stall_exe_o, stall_dec_o, stall_fetch_o, stall_btb_o,
was_branch_o, was_jmp_o, \ALU_OPCODE[4] , \ALU_OPCODE[3] ,
\ALU_OPCODE[2] , \ALU_OPCODE[1] , \ALU_OPCODE[0] , S_MUX_MEM_BAR;
wire IR_IN_10, IR_IN_9, IR_IN_8, IR_IN_7, IR_IN_6, IR_IN_5, IR_IN_4,
IR_IN_3, IR_IN_2, IR_IN_1, IR_IN_0, stall_exe_i, n130, S_MEM_LOAD,
S_EXE_LOAD, next_bubble_dec, stall_dec_o_TEMP, stall_btb_o_TEMP,
stall_fetch_o_TEMP, N20, N21, N22, N23, N24, N25, N26, N27, N29, N30,
N31, N32, net3570, n2, n3, n4, n5, n15, n16, n17, n18, n19, n20, n21,
n22, n23, n24, n25, n26, n27, n28, n31, n33, n34, n37, n38, n39, n40,
n41, n43, n44, n45, n46, n47, n48, n50, n51, n52, n53, n54, n55, n56,
n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70,
n71, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n111, n114, n115, n116, n118,
n123, n124, n125, n1, n6, n7, n8, n9, n10, n11, n12, n13, n14, n29,
n36, n42, n49;
wire [12:0] cw_from_mem;
wire [4:0] aluOpcode_d;
assign IR_IN_10 = IR_IN[10];
assign IR_IN_9 = IR_IN[9];
assign IR_IN_8 = IR_IN[8];
assign IR_IN_7 = IR_IN[7];
assign IR_IN_6 = IR_IN[6];
assign IR_IN_5 = IR_IN[5];
assign IR_IN_4 = IR_IN[4];
assign IR_IN_3 = IR_IN[3];
assign IR_IN_2 = IR_IN[2];
assign IR_IN_1 = IR_IN[1];
assign IR_IN_0 = IR_IN[0];
assign stall_exe_o = stall_exe_i;
DFF_X1 bubble_dec_reg ( .D(n123), .CK(Clk), .Q(n36), .QN(n124) );
DFFR_X1 \cw_e_reg[0] ( .D(N21), .CK(net3570), .RN(n49), .Q(n130), .QN(n2)
);
DFFR_X1 \cw_e_reg[5] ( .D(N26), .CK(net3570), .RN(n49), .Q(S_MUX_DEST[1])
);
DFFR_X1 \cw_e_reg[4] ( .D(N25), .CK(net3570), .RN(n49), .Q(S_MUX_DEST[0])
);
DFFR_X1 \cw_e_reg[3] ( .D(N24), .CK(net3570), .RN(n49), .Q(n3) );
DFFR_X1 \cw_m_reg[3] ( .D(N32), .CK(Clk), .RN(n49), .Q(S_MEM_EN), .QN(n125)
);
DFFR_X1 \cw_m_reg[2] ( .D(N31), .CK(Clk), .RN(n49), .Q(S_MEM_W_R) );
DFFR_X1 \cw_m_reg[1] ( .D(N30), .CK(Clk), .RN(n49), .QN(S_MUX_MEM_BAR) );
DFFR_X1 \cw_m_reg[0] ( .D(N29), .CK(Clk), .RN(n49), .Q(S_RF_W_mem), .QN(
n118) );
DFFS_X1 \cw_w_reg[0] ( .D(n118), .CK(Clk), .SN(n49), .QN(S_RF_W_wb) );
XOR2_X1 U3 ( .A(S_MUX_PC_BUS[1]), .B(S_MUX_PC_BUS[0]), .Z(was_jmp_o) );
MUX2_X1 U8 ( .A(next_bubble_dec), .B(n36), .S(Rst), .Z(n123) );
NAND3_X1 U59 ( .A1(IR_IN_3), .A2(n77), .A3(n78), .ZN(n70) );
NAND3_X1 U67 ( .A1(IR_IN_4), .A2(IR_IN_5), .A3(IR_IN_0), .ZN(n64) );
NAND3_X1 U71 ( .A1(IR_IN_4), .A2(n77), .A3(n91), .ZN(n71) );
NAND3_X1 U82 ( .A1(n48), .A2(n101), .A3(n46), .ZN(n76) );
NAND3_X1 U122 ( .A1(IR_IN_2), .A2(IR_IN_3), .A3(n63), .ZN(n27) );
NAND3_X1 U128 ( .A1(n43), .A2(n114), .A3(n115), .ZN(n93) );
stall_logic_FUNC_SIZE11_OP_CODE_SIZE6 STALL_L ( .OPCODE_i(IR_IN[31:26]),
.FUNC_i({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0}), .rA_i(IR_IN[25:21]), .rB_i(IR_IN[20:16]), .D1_i(D1_i), .D2_i(
D2_i), .S_mem_LOAD_i(S_MEM_LOAD), .S_exe_LOAD_i(S_EXE_LOAD),
.S_exe_WRITE_i(n130), .S_MUX_PC_BUS_i({1'b0, 1'b0}), .mispredict_i(
mispredict_i), .bubble_dec_o(next_bubble_dec), .stall_dec_o(
stall_dec_o_TEMP), .stall_btb_o(stall_btb_o_TEMP), .stall_fetch_o(
stall_fetch_o_TEMP) );
cw_mem_MICROCODE_MEM_SIZE64_OP_CODE_SIZE6_CW_SIZE13 CWM ( .OPCODE_IN(
IR_IN[31:26]), .CW_OUT(cw_from_mem) );
alu_ctrl ALU_C ( .OP(aluOpcode_d), .ALU_WORD(ALU_WORD_o) );
SNPS_CLOCK_GATE_HIGH_dlx_cu_MICROCODE_MEM_SIZE64_FUNC_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE13_0 clk_gate_cw_e_reg (
.CLK(Clk), .EN(N20), .ENCLK(net3570) );
AND2_X1 U17 ( .A1(n124), .A2(cw_from_mem[8]), .ZN(S_EQ_NEQ) );
NOR2_X1 U12 ( .A1(n125), .A2(S_MEM_W_R), .ZN(S_MEM_LOAD) );
NOR4_X1 U130 ( .A1(IR_IN_9), .A2(IR_IN_8), .A3(IR_IN_7), .A4(IR_IN_6), .ZN(
n114) );
NOR2_X1 U129 ( .A1(IR_IN[31]), .A2(IR_IN_10), .ZN(n115) );
NAND2_X1 U91 ( .A1(n46), .A2(n91), .ZN(n15) );
NAND2_X1 U126 ( .A1(IR_IN_4), .A2(IR_IN_5), .ZN(n16) );
NAND2_X1 U105 ( .A1(IR_IN[30]), .A2(IR_IN[29]), .ZN(n111) );
NAND2_X1 U103 ( .A1(IR_IN[31]), .A2(n19), .ZN(n24) );
NAND2_X1 U89 ( .A1(n105), .A2(IR_IN_2), .ZN(n94) );
NOR3_X1 U72 ( .A1(IR_IN[29]), .A2(IR_IN_0), .A3(n92), .ZN(n77) );
OAI211_X1 U52 ( .C1(n24), .C2(n69), .A(n70), .B(n71), .ZN(n20) );
INV_X1 U109 ( .A(IR_IN[31]), .ZN(n22) );
NAND2_X1 U115 ( .A1(IR_IN_0), .A2(n48), .ZN(n28) );
OAI211_X1 U23 ( .C1(n22), .C2(n23), .A(n24), .B(n25), .ZN(n21) );
AOI211_X1 U22 ( .C1(IR_IN[26]), .C2(n19), .A(n20), .B(n21), .ZN(n17) );
NOR2_X1 U85 ( .A1(n91), .A2(IR_IN_2), .ZN(n47) );
NAND2_X1 U84 ( .A1(IR_IN_1), .A2(n47), .ZN(n38) );
AOI211_X1 U32 ( .C1(n27), .C2(n38), .A(n26), .B(n16), .ZN(n37) );
OAI211_X1 U21 ( .C1(n15), .C2(n16), .A(n17), .B(n18), .ZN(aluOpcode_d[4]) );
NOR2_X1 U48 ( .A1(n60), .A2(n15), .ZN(n45) );
NAND2_X1 U118 ( .A1(n48), .A2(n104), .ZN(n62) );
NOR2_X1 U53 ( .A1(n27), .A2(n62), .ZN(n67) );
AOI211_X1 U51 ( .C1(n46), .C2(n67), .A(n68), .B(n20), .ZN(n31) );
AOI221_X1 U46 ( .B1(n62), .B2(n63), .C1(n62), .C2(n64), .A(IR_IN_3), .ZN(n61) );
OAI21_X1 U41 ( .B1(IR_IN[26]), .B2(n56), .A(n23), .ZN(n34) );
NAND2_X1 U108 ( .A1(IR_IN[29]), .A2(n22), .ZN(n44) );
AOI221_X1 U49 ( .B1(IR_IN_2), .B2(n64), .C1(n60), .C2(n28), .A(IR_IN_1),
.ZN(n65) );
NOR2_X1 U125 ( .A1(IR_IN_0), .A2(n16), .ZN(n66) );
AOI22_X1 U47 ( .A1(n46), .A2(n65), .B1(n66), .B2(n45), .ZN(n50) );
NOR2_X1 U114 ( .A1(IR_IN_2), .A2(n28), .ZN(n58) );
AOI22_X1 U44 ( .A1(n58), .A2(n59), .B1(n33), .B2(n60), .ZN(n51) );
NOR2_X1 U43 ( .A1(n57), .A2(n41), .ZN(n53) );
AOI221_X1 U39 ( .B1(n53), .B2(IR_IN[31]), .C1(n34), .C2(n22), .A(n54), .ZN(
n52) );
NOR2_X1 U95 ( .A1(IR_IN[30]), .A2(n44), .ZN(n84) );
NOR4_X1 U93 ( .A1(IR_IN[31]), .A2(IR_IN[29]), .A3(n39), .A4(n40), .ZN(n99)
);
AOI22_X1 U92 ( .A1(n95), .A2(n84), .B1(n106), .B2(n99), .ZN(n89) );
NOR2_X1 U88 ( .A1(IR_IN_4), .A2(n94), .ZN(n87) );
OAI221_X1 U87 ( .B1(IR_IN_0), .B2(n63), .C1(n104), .C2(IR_IN_1), .A(n87),
.ZN(n102) );
OAI211_X1 U86 ( .C1(IR_IN_1), .C2(n28), .A(n102), .B(n103), .ZN(n96) );
NAND2_X1 U81 ( .A1(n101), .A2(n66), .ZN(n100) );
OAI22_X1 U79 ( .A1(IR_IN_0), .A2(n76), .B1(n100), .B2(n26), .ZN(n97) );
AOI22_X1 U76 ( .A1(IR_IN[26]), .A2(n83), .B1(n23), .B2(n69), .ZN(n98) );
AOI211_X1 U75 ( .C1(n59), .C2(n96), .A(n97), .B(n98), .ZN(n90) );
NAND4_X1 U70 ( .A1(n73), .A2(n89), .A3(n90), .A4(n71), .ZN(aluOpcode_d[0])
);
NOR2_X1 U66 ( .A1(n38), .A2(n64), .ZN(n79) );
NOR2_X1 U65 ( .A1(n86), .A2(n87), .ZN(n85) );
AOI221_X1 U64 ( .B1(IR_IN_1), .B2(n85), .C1(n63), .C2(n64), .A(n15), .ZN(n80) );
OAI221_X1 U62 ( .B1(IR_IN[26]), .B2(n82), .C1(n69), .C2(n23), .A(n83), .ZN(
n81) );
AOI211_X1 U61 ( .C1(n46), .C2(n79), .A(n80), .B(n81), .ZN(n74) );
NAND2_X1 U57 ( .A1(IR_IN_0), .A2(n68), .ZN(n75) );
NAND4_X1 U56 ( .A1(n73), .A2(n74), .A3(n70), .A4(n75), .ZN(aluOpcode_d[1])
);
OR2_X1 U5 ( .A1(stall_exe_i), .A2(stall_fetch_o_TEMP), .ZN(stall_fetch_o) );
NOR2_X1 U133 ( .A1(n4), .A2(stall_exe_i), .ZN(N31) );
NOR2_X1 U134 ( .A1(n5), .A2(stall_exe_i), .ZN(N30) );
NOR2_X1 U135 ( .A1(n2), .A2(stall_exe_i), .ZN(N29) );
INV_X1 U97 ( .A(IR_IN[26]), .ZN(n69) );
NOR2_X1 U120 ( .A1(IR_IN_4), .A2(n105), .ZN(n48) );
NAND4_X1 U38 ( .A1(n31), .A2(n50), .A3(n51), .A4(n52), .ZN(aluOpcode_d[2])
);
NOR2_X1 U144 ( .A1(stall_dec_o_TEMP), .A2(n36), .ZN(n116) );
AND2_X1 U4 ( .A1(S_MUX_PC_BUS[1]), .A2(S_MUX_PC_BUS[0]), .ZN(was_branch_o)
);
AND2_X1 U16 ( .A1(n4), .A2(n3), .ZN(S_EXE_LOAD) );
OR2_X1 U6 ( .A1(stall_exe_i), .A2(stall_dec_o_TEMP), .ZN(stall_dec_o) );
INV_X1 U113 ( .A(IR_IN_3), .ZN(n91) );
INV_X1 U121 ( .A(IR_IN_5), .ZN(n105) );
INV_X1 U123 ( .A(IR_IN_1), .ZN(n63) );
INV_X1 U74 ( .A(n95), .ZN(n55) );
OR4_X1 U73 ( .A1(n93), .A2(n94), .A3(n63), .A4(n55), .ZN(n92) );
INV_X1 U60 ( .A(IR_IN_4), .ZN(n78) );
INV_X1 U80 ( .A(n46), .ZN(n26) );
OR3_X1 U24 ( .A1(n26), .A2(n27), .A3(n28), .ZN(n25) );
INV_X1 U31 ( .A(n37), .ZN(n18) );
INV_X1 U50 ( .A(IR_IN_2), .ZN(n60) );
INV_X1 U119 ( .A(IR_IN_0), .ZN(n104) );
INV_X1 U83 ( .A(n38), .ZN(n101) );
INV_X1 U58 ( .A(n76), .ZN(n68) );
AND2_X1 U45 ( .A1(n61), .A2(n46), .ZN(n33) );
INV_X1 U42 ( .A(n19), .ZN(n56) );
INV_X1 U110 ( .A(IR_IN[30]), .ZN(n40) );
INV_X1 U90 ( .A(n15), .ZN(n59) );
INV_X1 U102 ( .A(n43), .ZN(n57) );
INV_X1 U124 ( .A(n66), .ZN(n103) );
INV_X1 U117 ( .A(n62), .ZN(n86) );
AND2_X1 U139 ( .A1(n116), .A2(cw_from_mem[4]), .ZN(N25) );
AND2_X1 U138 ( .A1(n116), .A2(cw_from_mem[5]), .ZN(N26) );
AND2_X1 U141 ( .A1(n116), .A2(cw_from_mem[2]), .ZN(N23) );
AND2_X1 U142 ( .A1(n116), .A2(cw_from_mem[1]), .ZN(N22) );
AND2_X1 U143 ( .A1(n116), .A2(cw_from_mem[0]), .ZN(N21) );
AND2_X1 U137 ( .A1(n116), .A2(cw_from_mem[6]), .ZN(N27) );
AND2_X1 U140 ( .A1(n116), .A2(cw_from_mem[3]), .ZN(N24) );
AND2_X1 U132 ( .A1(N20), .A2(n3), .ZN(N32) );
DFFR_X2 \cw_e_reg[6] ( .D(N27), .CK(net3570), .RN(n49), .Q(S_MUX_ALUIN) );
AND2_X1 U10 ( .A1(n124), .A2(cw_from_mem[11]), .ZN(S_MUX_PC_BUS[0]) );
OR2_X1 U7 ( .A1(stall_exe_i), .A2(stall_btb_o_TEMP), .ZN(stall_btb_o) );
DFFR_X1 \cw_e_reg[2] ( .D(N23), .CK(net3570), .RN(n49), .QN(n4) );
DFFR_X1 \cw_e_reg[1] ( .D(N22), .CK(net3570), .RN(n49), .QN(n5) );
OAI21_X1 U9 ( .B1(n44), .B2(n1), .A(n18), .ZN(n8) );
OR2_X1 U11 ( .A1(n43), .A2(n7), .ZN(n1) );
OAI221_X1 U13 ( .B1(n45), .B2(n46), .C1(n45), .C2(n47), .A(n48), .ZN(n6) );
AOI21_X1 U14 ( .B1(n41), .B2(n40), .A(n39), .ZN(n7) );
AOI211_X1 U15 ( .C1(IR_IN_2), .C2(n33), .A(n34), .B(n8), .ZN(n9) );
OAI211_X1 U18 ( .C1(IR_IN_1), .C2(n6), .A(n31), .B(n9), .ZN(aluOpcode_d[3])
);
NAND3_X1 U19 ( .A1(IR_IN_3), .A2(n63), .A3(n86), .ZN(n10) );
OAI211_X1 U20 ( .C1(n66), .C2(n58), .A(IR_IN_1), .B(n91), .ZN(n11) );
OAI211_X1 U25 ( .C1(n103), .C2(n27), .A(n10), .B(n11), .ZN(n12) );
NOR3_X1 U26 ( .A1(n44), .A2(n57), .A3(n41), .ZN(n13) );
OR3_X1 U27 ( .A1(n42), .A2(n44), .A3(n40), .ZN(n14) );
AOI21_X1 U28 ( .B1(n24), .B2(n14), .A(IR_IN[26]), .ZN(n29) );
AOI211_X1 U29 ( .C1(n46), .C2(n12), .A(n13), .B(n29), .ZN(n73) );
AND2_X1 U30 ( .A1(cw_from_mem[12]), .A2(n124), .ZN(S_MUX_PC_BUS[1]) );
AND2_X2 U33 ( .A1(n124), .A2(cw_from_mem[7]), .ZN(S_MUX_LINK) );
AND2_X2 U34 ( .A1(cw_from_mem[10]), .A2(n124), .ZN(S_EXT) );
INV_X1 U35 ( .A(Rst), .ZN(n49) );
INV_X1 U36 ( .A(stall_exe_i), .ZN(N20) );
INV_X1 U37 ( .A(IR_IN[28]), .ZN(n39) );
CLKBUF_X1 U40 ( .A(IR_IN[27]), .Z(n42) );
AND2_X1 U54 ( .A1(cw_from_mem[9]), .A2(n124), .ZN(S_EXT_SIGN) );
NOR4_X2 U55 ( .A1(IR_IN[26]), .A2(IR_IN[29]), .A3(IR_IN[27]), .A4(n93), .ZN(
n46) );
AOI211_X1 U63 ( .C1(IR_IN[30]), .C2(n55), .A(IR_IN[28]), .B(n44), .ZN(n54)
);
NOR2_X1 U68 ( .A1(IR_IN[30]), .A2(IR_IN[28]), .ZN(n43) );
NOR2_X1 U69 ( .A1(IR_IN[26]), .A2(n42), .ZN(n106) );
NAND2_X1 U77 ( .A1(n42), .A2(n84), .ZN(n82) );
NAND2_X1 U78 ( .A1(n42), .A2(n99), .ZN(n83) );
NAND2_X1 U94 ( .A1(IR_IN[26]), .A2(n42), .ZN(n41) );
NAND4_X1 U96 ( .A1(IR_IN[30]), .A2(IR_IN[29]), .A3(n42), .A4(n39), .ZN(n23)
);
NOR3_X1 U98 ( .A1(n42), .A2(n39), .A3(n111), .ZN(n19) );
NOR2_X1 U99 ( .A1(IR_IN[27]), .A2(n69), .ZN(n95) );
endmodule
module jump_logic ( NPCF_i, IR_i, A_i, A_o, rA_o, rB_o, rC_o, branch_target_o,
sum_addr_o, extended_imm, taken_o, FW_X_i, FW_W_i, S_FW_Adec_i,
S_EXT_i, S_EXT_SIGN_i, S_MUX_LINK_i, S_EQ_NEQ_i );
input [31:0] NPCF_i;
input [31:0] IR_i;
input [31:0] A_i;
output [31:0] A_o;
output [4:0] rA_o;
output [4:0] rB_o;
output [4:0] rC_o;
output [31:0] branch_target_o;
output [31:0] sum_addr_o;
output [31:0] extended_imm;
input [31:0] FW_X_i;
input [31:0] FW_W_i;
input [1:0] S_FW_Adec_i;
input S_EXT_i, S_EXT_SIGN_i, S_MUX_LINK_i, S_EQ_NEQ_i;
output taken_o;
wire \IR_i[25] , \IR_i[24] , \IR_i[23] , \IR_i[22] , \IR_i[21] ,
\IR_i[20] , \IR_i[19] , \IR_i[18] , \IR_i[17] , \IR_i[16] ,
\IR_i[15] , \IR_i[14] , \IR_i[13] , \IR_i[12] , \IR_i[11] ,
branch_sel, n1;
wire [31:0] ext_imm;
assign rA_o[4] = \IR_i[25] ;
assign \IR_i[25] = IR_i[25];
assign rA_o[3] = \IR_i[24] ;
assign \IR_i[24] = IR_i[24];
assign rA_o[2] = \IR_i[23] ;
assign \IR_i[23] = IR_i[23];
assign rA_o[1] = \IR_i[22] ;
assign \IR_i[22] = IR_i[22];
assign rA_o[0] = \IR_i[21] ;
assign \IR_i[21] = IR_i[21];
assign rB_o[4] = \IR_i[20] ;
assign \IR_i[20] = IR_i[20];
assign rB_o[3] = \IR_i[19] ;
assign \IR_i[19] = IR_i[19];
assign rB_o[2] = \IR_i[18] ;
assign \IR_i[18] = IR_i[18];
assign rB_o[1] = \IR_i[17] ;
assign \IR_i[17] = IR_i[17];
assign rB_o[0] = \IR_i[16] ;
assign \IR_i[16] = IR_i[16];
assign rC_o[4] = \IR_i[15] ;
assign \IR_i[15] = IR_i[15];
assign rC_o[3] = \IR_i[14] ;
assign \IR_i[14] = IR_i[14];
assign rC_o[2] = \IR_i[13] ;
assign \IR_i[13] = IR_i[13];
assign rC_o[1] = \IR_i[12] ;
assign \IR_i[12] = IR_i[12];
assign rC_o[0] = \IR_i[11] ;
assign \IR_i[11] = IR_i[11];
extender_32 EXTENDER ( .IN1({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, \IR_i[25] ,
\IR_i[24] , \IR_i[23] , \IR_i[22] , \IR_i[21] , \IR_i[20] , \IR_i[19] ,
\IR_i[18] , \IR_i[17] , \IR_i[16] , \IR_i[15] , \IR_i[14] , \IR_i[13] ,
\IR_i[12] , \IR_i[11] , IR_i[10:0]}), .CTRL(S_EXT_i), .SIGN(
S_EXT_SIGN_i), .OUT1(ext_imm) );
p4add_N32_logN5_0 JUMPADDER ( .A(NPCF_i), .B(ext_imm), .Cin(1'b0), .sign(
1'b0), .S(sum_addr_o) );
mux21_0 BRANCHMUX ( .IN0(sum_addr_o), .IN1(NPCF_i), .CTRL(branch_sel),
.OUT1(branch_target_o) );
zerocheck ZC ( .IN0(A_o), .CTRL(S_EQ_NEQ_i), .OUT1(branch_sel) );
mux21_4 MUXLINK ( .IN0(ext_imm), .IN1(NPCF_i), .CTRL(S_MUX_LINK_i), .OUT1(
extended_imm) );
mux41_MUX_SIZE32_0 MUX_FWA ( .IN0(A_i), .IN1(FW_X_i), .IN2(FW_W_i), .IN3({
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), .CTRL(S_FW_Adec_i),
.OUT1(A_o) );
CLKBUF_X1 U2 ( .A(branch_sel), .Z(n1) );
INV_X1 U3 ( .A(n1), .ZN(taken_o) );
endmodule
module fetch_regs ( NPCF_i, IR_i, NPCF_o, IR_o, stall_i, clk, rst );
input [31:0] NPCF_i;
input [31:0] IR_i;
output [31:0] NPCF_o;
output [31:0] IR_o;
input stall_i, clk, rst;
wire enable;
ff32_en_1 NPCF ( .D(NPCF_i), .en(enable), .clk(clk), .rst(rst), .Q(NPCF_o)
);
ff32_en_IR IR ( .D(IR_i), .en(enable), .clk(clk), .rst(rst), .Q(IR_o) );
INV_X1 U1 ( .A(stall_i), .ZN(enable) );
endmodule
module btb_N_LINES4_SIZE32 ( clock, reset, stall_i, TAG_i, target_PC_i,
was_taken_i, predicted_next_PC_o, taken_o, mispredict_o );
input [3:0] TAG_i;
input [31:0] target_PC_i;
output [31:0] predicted_next_PC_o;
input clock, reset, stall_i, was_taken_i;
output taken_o, mispredict_o;
wire \predict_PC[0][31] , \predict_PC[0][30] , \predict_PC[0][29] ,
\predict_PC[0][28] , \predict_PC[0][27] , \predict_PC[0][26] ,
\predict_PC[0][25] , \predict_PC[0][24] , \predict_PC[0][23] ,
\predict_PC[0][22] , \predict_PC[0][21] , \predict_PC[0][20] ,
\predict_PC[0][19] , \predict_PC[0][18] , \predict_PC[0][17] ,
\predict_PC[0][16] , \predict_PC[0][15] , \predict_PC[0][14] ,
\predict_PC[0][13] , \predict_PC[0][12] , \predict_PC[0][11] ,
\predict_PC[0][10] , \predict_PC[0][9] , \predict_PC[0][8] ,
\predict_PC[0][7] , \predict_PC[0][6] , \predict_PC[0][5] ,
\predict_PC[0][4] , \predict_PC[0][3] , \predict_PC[0][2] ,
\predict_PC[0][1] , \predict_PC[0][0] , \predict_PC[1][31] ,
\predict_PC[1][30] , \predict_PC[1][29] , \predict_PC[1][28] ,
\predict_PC[1][27] , \predict_PC[1][26] , \predict_PC[1][25] ,
\predict_PC[1][24] , \predict_PC[1][23] , \predict_PC[1][22] ,
\predict_PC[1][21] , \predict_PC[1][20] , \predict_PC[1][19] ,
\predict_PC[1][18] , \predict_PC[1][17] , \predict_PC[1][16] ,
\predict_PC[1][15] , \predict_PC[1][14] , \predict_PC[1][13] ,
\predict_PC[1][12] , \predict_PC[1][11] , \predict_PC[1][10] ,
\predict_PC[1][9] , \predict_PC[1][8] , \predict_PC[1][7] ,
\predict_PC[1][6] , \predict_PC[1][5] , \predict_PC[1][4] ,
\predict_PC[1][3] , \predict_PC[1][2] , \predict_PC[1][1] ,
\predict_PC[1][0] , \predict_PC[2][31] , \predict_PC[2][30] ,
\predict_PC[2][29] , \predict_PC[2][28] , \predict_PC[2][27] ,
\predict_PC[2][26] , \predict_PC[2][25] , \predict_PC[2][24] ,
\predict_PC[2][23] , \predict_PC[2][22] , \predict_PC[2][21] ,
\predict_PC[2][20] , \predict_PC[2][19] , \predict_PC[2][18] ,
\predict_PC[2][17] , \predict_PC[2][16] , \predict_PC[2][15] ,
\predict_PC[2][14] , \predict_PC[2][13] , \predict_PC[2][12] ,
\predict_PC[2][11] , \predict_PC[2][10] , \predict_PC[2][9] ,
\predict_PC[2][8] , \predict_PC[2][7] , \predict_PC[2][6] ,
\predict_PC[2][5] , \predict_PC[2][4] , \predict_PC[2][3] ,
\predict_PC[2][2] , \predict_PC[2][1] , \predict_PC[2][0] ,
\predict_PC[3][31] , \predict_PC[3][30] , \predict_PC[3][29] ,
\predict_PC[3][28] , \predict_PC[3][27] , \predict_PC[3][26] ,
\predict_PC[3][25] , \predict_PC[3][24] , \predict_PC[3][23] ,
\predict_PC[3][22] , \predict_PC[3][21] , \predict_PC[3][20] ,
\predict_PC[3][19] , \predict_PC[3][18] , \predict_PC[3][17] ,
\predict_PC[3][16] , \predict_PC[3][15] , \predict_PC[3][14] ,
\predict_PC[3][13] , \predict_PC[3][12] , \predict_PC[3][11] ,
\predict_PC[3][10] , \predict_PC[3][9] , \predict_PC[3][8] ,
\predict_PC[3][7] , \predict_PC[3][6] , \predict_PC[3][5] ,
\predict_PC[3][4] , \predict_PC[3][3] , \predict_PC[3][2] ,
\predict_PC[3][1] , \predict_PC[3][0] , \predict_PC[4][31] ,
\predict_PC[4][30] , \predict_PC[4][29] , \predict_PC[4][28] ,
\predict_PC[4][27] , \predict_PC[4][26] , \predict_PC[4][25] ,
\predict_PC[4][24] , \predict_PC[4][23] , \predict_PC[4][22] ,
\predict_PC[4][21] , \predict_PC[4][20] , \predict_PC[4][19] ,
\predict_PC[4][18] , \predict_PC[4][17] , \predict_PC[4][16] ,
\predict_PC[4][15] , \predict_PC[4][14] , \predict_PC[4][13] ,
\predict_PC[4][12] , \predict_PC[4][11] , \predict_PC[4][10] ,
\predict_PC[4][9] , \predict_PC[4][8] , \predict_PC[4][7] ,
\predict_PC[4][6] , \predict_PC[4][5] , \predict_PC[4][4] ,
\predict_PC[4][3] , \predict_PC[4][2] , \predict_PC[4][1] ,
\predict_PC[4][0] , \predict_PC[5][31] , \predict_PC[5][30] ,
\predict_PC[5][29] , \predict_PC[5][28] , \predict_PC[5][27] ,
\predict_PC[5][26] , \predict_PC[5][25] , \predict_PC[5][24] ,
\predict_PC[5][23] , \predict_PC[5][22] , \predict_PC[5][21] ,
\predict_PC[5][20] , \predict_PC[5][19] , \predict_PC[5][18] ,
\predict_PC[5][17] , \predict_PC[5][16] , \predict_PC[5][15] ,
\predict_PC[5][14] , \predict_PC[5][13] , \predict_PC[5][12] ,
\predict_PC[5][11] , \predict_PC[5][10] , \predict_PC[5][9] ,
\predict_PC[5][8] , \predict_PC[5][7] , \predict_PC[5][6] ,
\predict_PC[5][5] , \predict_PC[5][4] , \predict_PC[5][3] ,
\predict_PC[5][2] , \predict_PC[5][1] , \predict_PC[5][0] ,
\predict_PC[6][31] , \predict_PC[6][30] , \predict_PC[6][29] ,
\predict_PC[6][28] , \predict_PC[6][27] , \predict_PC[6][26] ,
\predict_PC[6][25] , \predict_PC[6][24] , \predict_PC[6][23] ,
\predict_PC[6][22] , \predict_PC[6][21] , \predict_PC[6][20] ,
\predict_PC[6][19] , \predict_PC[6][18] , \predict_PC[6][17] ,
\predict_PC[6][16] , \predict_PC[6][15] , \predict_PC[6][14] ,
\predict_PC[6][13] , \predict_PC[6][12] , \predict_PC[6][11] ,
\predict_PC[6][10] , \predict_PC[6][9] , \predict_PC[6][8] ,
\predict_PC[6][7] , \predict_PC[6][6] , \predict_PC[6][5] ,
\predict_PC[6][4] , \predict_PC[6][3] , \predict_PC[6][2] ,
\predict_PC[6][1] , \predict_PC[6][0] , \predict_PC[7][31] ,
\predict_PC[7][30] , \predict_PC[7][29] , \predict_PC[7][28] ,
\predict_PC[7][27] , \predict_PC[7][26] , \predict_PC[7][25] ,
\predict_PC[7][24] , \predict_PC[7][23] , \predict_PC[7][22] ,
\predict_PC[7][21] , \predict_PC[7][20] , \predict_PC[7][19] ,
\predict_PC[7][18] , \predict_PC[7][17] , \predict_PC[7][16] ,
\predict_PC[7][15] , \predict_PC[7][14] , \predict_PC[7][13] ,
\predict_PC[7][12] , \predict_PC[7][11] , \predict_PC[7][10] ,
\predict_PC[7][9] , \predict_PC[7][8] , \predict_PC[7][7] ,
\predict_PC[7][6] , \predict_PC[7][5] , \predict_PC[7][4] ,
\predict_PC[7][3] , \predict_PC[7][2] , \predict_PC[7][1] ,
\predict_PC[7][0] , \predict_PC[8][31] , \predict_PC[8][30] ,
\predict_PC[8][29] , \predict_PC[8][28] , \predict_PC[8][27] ,
\predict_PC[8][26] , \predict_PC[8][25] , \predict_PC[8][24] ,
\predict_PC[8][23] , \predict_PC[8][22] , \predict_PC[8][21] ,
\predict_PC[8][20] , \predict_PC[8][19] , \predict_PC[8][18] ,
\predict_PC[8][17] , \predict_PC[8][16] , \predict_PC[8][15] ,
\predict_PC[8][14] , \predict_PC[8][13] , \predict_PC[8][12] ,
\predict_PC[8][11] , \predict_PC[8][10] , \predict_PC[8][9] ,
\predict_PC[8][8] , \predict_PC[8][7] , \predict_PC[8][6] ,
\predict_PC[8][5] , \predict_PC[8][4] , \predict_PC[8][3] ,
\predict_PC[8][2] , \predict_PC[8][1] , \predict_PC[8][0] ,
\predict_PC[9][31] , \predict_PC[9][30] , \predict_PC[9][29] ,
\predict_PC[9][28] , \predict_PC[9][27] , \predict_PC[9][26] ,
\predict_PC[9][25] , \predict_PC[9][24] , \predict_PC[9][23] ,
\predict_PC[9][22] , \predict_PC[9][21] , \predict_PC[9][20] ,
\predict_PC[9][19] , \predict_PC[9][18] , \predict_PC[9][17] ,
\predict_PC[9][16] , \predict_PC[9][15] , \predict_PC[9][14] ,
\predict_PC[9][13] , \predict_PC[9][12] , \predict_PC[9][11] ,
\predict_PC[9][10] , \predict_PC[9][9] , \predict_PC[9][8] ,
\predict_PC[9][7] , \predict_PC[9][6] , \predict_PC[9][5] ,
\predict_PC[9][4] , \predict_PC[9][3] , \predict_PC[9][2] ,
\predict_PC[9][1] , \predict_PC[9][0] , \predict_PC[10][31] ,
\predict_PC[10][30] , \predict_PC[10][29] , \predict_PC[10][28] ,
\predict_PC[10][27] , \predict_PC[10][26] , \predict_PC[10][25] ,
\predict_PC[10][24] , \predict_PC[10][23] , \predict_PC[10][22] ,
\predict_PC[10][21] , \predict_PC[10][20] , \predict_PC[10][19] ,
\predict_PC[10][18] , \predict_PC[10][17] , \predict_PC[10][16] ,
\predict_PC[10][15] , \predict_PC[10][14] , \predict_PC[10][13] ,
\predict_PC[10][12] , \predict_PC[10][11] , \predict_PC[10][10] ,
\predict_PC[10][9] , \predict_PC[10][8] , \predict_PC[10][7] ,
\predict_PC[10][6] , \predict_PC[10][5] , \predict_PC[10][4] ,
\predict_PC[10][3] , \predict_PC[10][2] , \predict_PC[10][1] ,
\predict_PC[10][0] , \predict_PC[11][31] , \predict_PC[11][30] ,
\predict_PC[11][29] , \predict_PC[11][28] , \predict_PC[11][27] ,
\predict_PC[11][26] , \predict_PC[11][25] , \predict_PC[11][24] ,
\predict_PC[11][23] , \predict_PC[11][22] , \predict_PC[11][21] ,
\predict_PC[11][20] , \predict_PC[11][19] , \predict_PC[11][18] ,
\predict_PC[11][17] , \predict_PC[11][16] , \predict_PC[11][15] ,
\predict_PC[11][14] , \predict_PC[11][13] , \predict_PC[11][12] ,
\predict_PC[11][11] , \predict_PC[11][10] , \predict_PC[11][9] ,
\predict_PC[11][8] , \predict_PC[11][7] , \predict_PC[11][6] ,
\predict_PC[11][5] , \predict_PC[11][4] , \predict_PC[11][3] ,
\predict_PC[11][2] , \predict_PC[11][1] , \predict_PC[11][0] ,
\predict_PC[12][31] , \predict_PC[12][30] , \predict_PC[12][29] ,
\predict_PC[12][28] , \predict_PC[12][27] , \predict_PC[12][26] ,
\predict_PC[12][25] , \predict_PC[12][24] , \predict_PC[12][23] ,
\predict_PC[12][22] , \predict_PC[12][21] , \predict_PC[12][20] ,
\predict_PC[12][19] , \predict_PC[12][18] , \predict_PC[12][17] ,
\predict_PC[12][16] , \predict_PC[12][15] , \predict_PC[12][14] ,
\predict_PC[12][13] , \predict_PC[12][12] , \predict_PC[12][11] ,
\predict_PC[12][10] , \predict_PC[12][9] , \predict_PC[12][8] ,
\predict_PC[12][7] , \predict_PC[12][6] , \predict_PC[12][5] ,
\predict_PC[12][4] , \predict_PC[12][3] , \predict_PC[12][2] ,
\predict_PC[12][1] , \predict_PC[12][0] , \predict_PC[13][31] ,
\predict_PC[13][30] , \predict_PC[13][29] , \predict_PC[13][28] ,
\predict_PC[13][27] , \predict_PC[13][26] , \predict_PC[13][25] ,
\predict_PC[13][24] , \predict_PC[13][23] , \predict_PC[13][22] ,
\predict_PC[13][21] , \predict_PC[13][20] , \predict_PC[13][19] ,
\predict_PC[13][18] , \predict_PC[13][17] , \predict_PC[13][16] ,
\predict_PC[13][15] , \predict_PC[13][14] , \predict_PC[13][13] ,
\predict_PC[13][12] , \predict_PC[13][11] , \predict_PC[13][10] ,
\predict_PC[13][9] , \predict_PC[13][8] , \predict_PC[13][7] ,
\predict_PC[13][6] , \predict_PC[13][5] , \predict_PC[13][4] ,
\predict_PC[13][3] , \predict_PC[13][2] , \predict_PC[13][1] ,
\predict_PC[13][0] , \predict_PC[14][31] , \predict_PC[14][30] ,
\predict_PC[14][29] , \predict_PC[14][28] , \predict_PC[14][27] ,
\predict_PC[14][26] , \predict_PC[14][25] , \predict_PC[14][24] ,
\predict_PC[14][23] , \predict_PC[14][22] , \predict_PC[14][21] ,
\predict_PC[14][20] , \predict_PC[14][19] , \predict_PC[14][18] ,
\predict_PC[14][17] , \predict_PC[14][16] , \predict_PC[14][15] ,
\predict_PC[14][14] , \predict_PC[14][13] , \predict_PC[14][12] ,
\predict_PC[14][11] , \predict_PC[14][10] , \predict_PC[14][9] ,
\predict_PC[14][8] , \predict_PC[14][7] , \predict_PC[14][6] ,
\predict_PC[14][5] , \predict_PC[14][4] , \predict_PC[14][3] ,
\predict_PC[14][2] , \predict_PC[14][1] , \predict_PC[14][0] ,
\predict_PC[15][31] , \predict_PC[15][30] , \predict_PC[15][29] ,
\predict_PC[15][28] , \predict_PC[15][27] , \predict_PC[15][26] ,
\predict_PC[15][25] , \predict_PC[15][24] , \predict_PC[15][23] ,
\predict_PC[15][22] , \predict_PC[15][21] , \predict_PC[15][20] ,
\predict_PC[15][19] , \predict_PC[15][18] , \predict_PC[15][17] ,
\predict_PC[15][16] , \predict_PC[15][15] , \predict_PC[15][14] ,
\predict_PC[15][13] , \predict_PC[15][12] , \predict_PC[15][11] ,
\predict_PC[15][10] , \predict_PC[15][9] , \predict_PC[15][8] ,
\predict_PC[15][7] , \predict_PC[15][6] , \predict_PC[15][5] ,
\predict_PC[15][4] , \predict_PC[15][3] , \predict_PC[15][2] ,
\predict_PC[15][1] , \predict_PC[15][0] , N38, N39, N40, N41, N42,
N43, N44, N45, N46, N47, N48, N49, N50, N51, N52, N53, N86, N118,
N150, N182, N214, N246, N278, N310, N342, N374, N406, N438, N470,
N502, N534, N566, N567, net3621, net3626, net3631, net3636, net3641,
net3646, net3651, net3656, net3661, net3666, net3671, net3676,
net3681, net3686, net3691, net3696, net3701, n483, n485, n487, n489,
n491, n493, n495, n497, n499, n501, n503, n505, n507, n509, n511,
n513, n515, n517, n519, n521, n523, n525, n527, n529, n531, n533,
n535, n537, n539, n541, n543, n545, n546, n547, n548, n549, n550,
n551, n552, n553, n554, n555, n556, n557, n558, n559, n560, n561,
n562, n563, n564, n565, n566, n567, n568, n569, n570, n571, n572,
n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583,
n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594,
n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605,
n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616,
n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638,
n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649,
n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660,
n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671,
n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682,
n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693,
n694, n695, n696, n697, n698, n699, n700, n701, n702, n703, n704,
n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715,
n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726,
n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737,
n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748,
n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759,
n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770,
n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792,
n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803,
n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814,
n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, n825,
n826, n827, n828, n829, n830, n831, n832, n833, n834, n835, n836,
n837, n838, n839, n840, n841, n842, n843, n844, n845, n846, n847,
n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858,
n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869,
n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880,
n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891,
n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902,
n903, n943, n944, n945, n946, n947, n948, n949, n951, n955, n972,
n973, n974, n975, n976, n977, n978, n979, n942, n941, n940, n939,
n938, n937, n936, n935, n934, n933, n932, n931, n930, n929, n928,
n927, n926, n925, n924, n923, n922, n921, n920, n919, n918, n917,
n916, n915, n914, n913, n912, n911, n906, n905, n35, n36, n37, n38,
n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52,
n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66,
n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80,
n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94,
n95, n96, n97, n98, n99, n100;
wire [15:0] taken;
wire [15:0] write_enable;
DFFS_X1 \last_TAG_reg[3] ( .D(n972), .CK(net3621), .SN(n86), .Q(n977), .QN(
n53) );
DFFS_X1 \last_TAG_reg[2] ( .D(n973), .CK(net3621), .SN(n77), .Q(n976), .QN(
n51) );
DFFS_X1 \last_TAG_reg[1] ( .D(n974), .CK(net3621), .SN(n79), .Q(n979), .QN(
n52) );
DFFR_X1 \last_TAG_reg[0] ( .D(TAG_i[0]), .CK(net3621), .RN(n87), .Q(n50),
.QN(n978) );
DFFR_X1 \write_enable_reg[15] ( .D(N53), .CK(net3621), .RN(n81), .Q(
write_enable[15]) );
DFFR_X1 \write_enable_reg[14] ( .D(N52), .CK(net3621), .RN(n79), .Q(
write_enable[14]) );
DFFR_X1 \write_enable_reg[13] ( .D(N51), .CK(net3621), .RN(n82), .Q(
write_enable[13]) );
DFFR_X1 \write_enable_reg[12] ( .D(N50), .CK(net3621), .RN(n83), .Q(
write_enable[12]) );
DFFR_X1 \write_enable_reg[11] ( .D(N49), .CK(net3621), .RN(n85), .Q(
write_enable[11]) );
DFFR_X1 \write_enable_reg[10] ( .D(N48), .CK(net3621), .RN(n86), .Q(
write_enable[10]) );
DFFR_X1 \write_enable_reg[9] ( .D(N47), .CK(net3621), .RN(n85), .Q(
write_enable[9]) );
DFFR_X1 \write_enable_reg[8] ( .D(N46), .CK(net3621), .RN(n84), .Q(
write_enable[8]) );
DFFR_X1 \write_enable_reg[7] ( .D(N45), .CK(net3621), .RN(n87), .Q(
write_enable[7]) );
DFFR_X1 \write_enable_reg[6] ( .D(N44), .CK(net3621), .RN(n84), .Q(
write_enable[6]) );
DFFR_X1 \write_enable_reg[5] ( .D(N43), .CK(net3621), .RN(n86), .Q(
write_enable[5]) );
DFFR_X1 \write_enable_reg[4] ( .D(N42), .CK(net3621), .RN(n85), .Q(
write_enable[4]) );
DFFR_X1 \write_enable_reg[3] ( .D(N41), .CK(net3621), .RN(n84), .Q(
write_enable[3]) );
DFFR_X1 \write_enable_reg[2] ( .D(N40), .CK(net3621), .RN(n87), .Q(
write_enable[2]) );
DFFR_X1 \write_enable_reg[1] ( .D(N39), .CK(net3621), .RN(n87), .Q(
write_enable[1]) );
DFFR_X1 \write_enable_reg[0] ( .D(N38), .CK(net3621), .RN(n86), .Q(
write_enable[0]) );
DFF_X1 last_taken_reg ( .D(n955), .CK(clock), .Q(n54), .QN(n975) );
DFFR_X1 \predict_PC_reg[0][31] ( .D(n59), .CK(net3626), .RN(n87), .Q(
\predict_PC[0][31] ) );
DFFR_X1 \predict_PC_reg[0][30] ( .D(n38), .CK(net3626), .RN(n84), .Q(
\predict_PC[0][30] ) );
DFFR_X1 \predict_PC_reg[0][29] ( .D(n58), .CK(net3626), .RN(n85), .Q(
\predict_PC[0][29] ) );
DFFR_X1 \predict_PC_reg[0][28] ( .D(n39), .CK(net3626), .RN(n86), .Q(
\predict_PC[0][28] ) );
DFFR_X1 \predict_PC_reg[0][27] ( .D(n60), .CK(net3626), .RN(n87), .Q(
\predict_PC[0][27] ) );
DFFR_X1 \predict_PC_reg[0][26] ( .D(n37), .CK(net3626), .RN(n84), .Q(
\predict_PC[0][26] ) );
DFFR_X1 \predict_PC_reg[0][25] ( .D(n35), .CK(net3626), .RN(n85), .Q(
\predict_PC[0][25] ) );
DFFR_X1 \predict_PC_reg[0][24] ( .D(n36), .CK(net3626), .RN(n86), .Q(
\predict_PC[0][24] ) );
DFFR_X1 \predict_PC_reg[0][23] ( .D(target_PC_i[23]), .CK(net3626), .RN(n87), .Q(\predict_PC[0][23] ) );
DFFR_X1 \predict_PC_reg[0][22] ( .D(target_PC_i[22]), .CK(net3626), .RN(n84), .Q(\predict_PC[0][22] ) );
DFFR_X1 \predict_PC_reg[0][21] ( .D(target_PC_i[21]), .CK(net3626), .RN(n85), .Q(\predict_PC[0][21] ) );
DFFR_X1 \predict_PC_reg[0][20] ( .D(target_PC_i[20]), .CK(net3626), .RN(n86), .Q(\predict_PC[0][20] ) );
DFFR_X1 \predict_PC_reg[0][19] ( .D(target_PC_i[19]), .CK(net3626), .RN(n84), .Q(\predict_PC[0][19] ) );
DFFR_X1 \predict_PC_reg[0][18] ( .D(target_PC_i[18]), .CK(net3626), .RN(n84), .Q(\predict_PC[0][18] ) );
DFFR_X1 \predict_PC_reg[0][17] ( .D(target_PC_i[17]), .CK(net3626), .RN(n84), .Q(\predict_PC[0][17] ) );
DFFR_X1 \predict_PC_reg[0][16] ( .D(target_PC_i[16]), .CK(net3626), .RN(n84), .Q(\predict_PC[0][16] ) );
DFFR_X1 \predict_PC_reg[0][15] ( .D(target_PC_i[15]), .CK(net3626), .RN(n84), .Q(\predict_PC[0][15] ) );
DFFR_X1 \predict_PC_reg[0][14] ( .D(target_PC_i[14]), .CK(net3626), .RN(n84), .Q(\predict_PC[0][14] ) );
DFFR_X1 \predict_PC_reg[0][13] ( .D(target_PC_i[13]), .CK(net3626), .RN(n84), .Q(\predict_PC[0][13] ) );
DFFR_X1 \predict_PC_reg[0][12] ( .D(target_PC_i[12]), .CK(net3626), .RN(n84), .Q(\predict_PC[0][12] ) );
DFFR_X1 \predict_PC_reg[0][11] ( .D(target_PC_i[11]), .CK(net3626), .RN(n84), .Q(\predict_PC[0][11] ) );
DFFR_X1 \predict_PC_reg[0][10] ( .D(target_PC_i[10]), .CK(net3626), .RN(n84), .Q(\predict_PC[0][10] ) );
DFFR_X1 \predict_PC_reg[0][9] ( .D(target_PC_i[9]), .CK(net3626), .RN(n84),
.Q(\predict_PC[0][9] ) );
DFFR_X1 \predict_PC_reg[0][8] ( .D(target_PC_i[8]), .CK(net3626), .RN(n84),
.Q(\predict_PC[0][8] ) );
DFFR_X1 \predict_PC_reg[0][7] ( .D(target_PC_i[7]), .CK(net3626), .RN(n85),
.Q(\predict_PC[0][7] ) );
DFFR_X1 \predict_PC_reg[0][6] ( .D(target_PC_i[6]), .CK(net3626), .RN(n85),
.Q(\predict_PC[0][6] ) );
DFFR_X1 \predict_PC_reg[0][5] ( .D(target_PC_i[5]), .CK(net3626), .RN(n85),
.Q(\predict_PC[0][5] ) );
DFFR_X1 \predict_PC_reg[0][4] ( .D(target_PC_i[4]), .CK(net3626), .RN(n85),
.Q(\predict_PC[0][4] ) );
DFFR_X1 \predict_PC_reg[0][3] ( .D(target_PC_i[3]), .CK(net3626), .RN(n85),
.Q(\predict_PC[0][3] ) );
DFFR_X1 \predict_PC_reg[0][2] ( .D(target_PC_i[2]), .CK(net3626), .RN(n85),
.Q(\predict_PC[0][2] ) );
DFFR_X1 \predict_PC_reg[0][1] ( .D(target_PC_i[1]), .CK(net3626), .RN(n85),
.Q(\predict_PC[0][1] ) );
DFFR_X1 \predict_PC_reg[0][0] ( .D(target_PC_i[0]), .CK(net3626), .RN(n85),
.Q(\predict_PC[0][0] ) );
DFFR_X1 \predict_PC_reg[1][31] ( .D(n59), .CK(net3631), .RN(n85), .Q(
\predict_PC[1][31] ) );
DFFR_X1 \predict_PC_reg[1][30] ( .D(n38), .CK(net3631), .RN(n85), .Q(
\predict_PC[1][30] ) );
DFFR_X1 \predict_PC_reg[1][29] ( .D(n58), .CK(net3631), .RN(n85), .Q(
\predict_PC[1][29] ) );
DFFR_X1 \predict_PC_reg[1][28] ( .D(n39), .CK(net3631), .RN(n85), .Q(
\predict_PC[1][28] ) );
DFFR_X1 \predict_PC_reg[1][27] ( .D(n60), .CK(net3631), .RN(n86), .Q(
\predict_PC[1][27] ) );
DFFR_X1 \predict_PC_reg[1][26] ( .D(n37), .CK(net3631), .RN(n86), .Q(
\predict_PC[1][26] ) );
DFFR_X1 \predict_PC_reg[1][25] ( .D(n35), .CK(net3631), .RN(n86), .Q(
\predict_PC[1][25] ) );
DFFR_X1 \predict_PC_reg[1][24] ( .D(n36), .CK(net3631), .RN(n86), .Q(
\predict_PC[1][24] ) );
DFFR_X1 \predict_PC_reg[1][23] ( .D(target_PC_i[23]), .CK(net3631), .RN(n86), .Q(\predict_PC[1][23] ) );
DFFR_X1 \predict_PC_reg[1][22] ( .D(target_PC_i[22]), .CK(net3631), .RN(n86), .Q(\predict_PC[1][22] ) );
DFFR_X1 \predict_PC_reg[1][21] ( .D(target_PC_i[21]), .CK(net3631), .RN(n86), .Q(\predict_PC[1][21] ) );
DFFR_X1 \predict_PC_reg[1][20] ( .D(target_PC_i[20]), .CK(net3631), .RN(n86), .Q(\predict_PC[1][20] ) );
DFFR_X1 \predict_PC_reg[1][19] ( .D(target_PC_i[19]), .CK(net3631), .RN(n86), .Q(\predict_PC[1][19] ) );
DFFR_X1 \predict_PC_reg[1][18] ( .D(target_PC_i[18]), .CK(net3631), .RN(n86), .Q(\predict_PC[1][18] ) );
DFFR_X1 \predict_PC_reg[1][17] ( .D(target_PC_i[17]), .CK(net3631), .RN(n86), .Q(\predict_PC[1][17] ) );
DFFR_X1 \predict_PC_reg[1][16] ( .D(target_PC_i[16]), .CK(net3631), .RN(n86), .Q(\predict_PC[1][16] ) );
DFFR_X1 \predict_PC_reg[1][15] ( .D(target_PC_i[15]), .CK(net3631), .RN(n87), .Q(\predict_PC[1][15] ) );
DFFR_X1 \predict_PC_reg[1][14] ( .D(target_PC_i[14]), .CK(net3631), .RN(n87), .Q(\predict_PC[1][14] ) );
DFFR_X1 \predict_PC_reg[1][13] ( .D(target_PC_i[13]), .CK(net3631), .RN(n87), .Q(\predict_PC[1][13] ) );
DFFR_X1 \predict_PC_reg[1][12] ( .D(target_PC_i[12]), .CK(net3631), .RN(n87), .Q(\predict_PC[1][12] ) );
DFFR_X1 \predict_PC_reg[1][11] ( .D(target_PC_i[11]), .CK(net3631), .RN(n87), .Q(\predict_PC[1][11] ) );
DFFR_X1 \predict_PC_reg[1][10] ( .D(target_PC_i[10]), .CK(net3631), .RN(n87), .Q(\predict_PC[1][10] ) );
DFFR_X1 \predict_PC_reg[1][9] ( .D(target_PC_i[9]), .CK(net3631), .RN(n87),
.Q(\predict_PC[1][9] ) );
DFFR_X1 \predict_PC_reg[1][8] ( .D(target_PC_i[8]), .CK(net3631), .RN(n87),
.Q(\predict_PC[1][8] ) );
DFFR_X1 \predict_PC_reg[1][7] ( .D(target_PC_i[7]), .CK(net3631), .RN(n87),
.Q(\predict_PC[1][7] ) );
DFFR_X1 \predict_PC_reg[1][6] ( .D(target_PC_i[6]), .CK(net3631), .RN(n87),
.Q(\predict_PC[1][6] ) );
DFFR_X1 \predict_PC_reg[1][5] ( .D(target_PC_i[5]), .CK(net3631), .RN(n87),
.Q(\predict_PC[1][5] ) );
DFFR_X1 \predict_PC_reg[1][4] ( .D(target_PC_i[4]), .CK(net3631), .RN(n88),
.Q(\predict_PC[1][4] ) );
DFFR_X1 \predict_PC_reg[1][3] ( .D(target_PC_i[3]), .CK(net3631), .RN(n88),
.Q(\predict_PC[1][3] ) );
DFFR_X1 \predict_PC_reg[1][2] ( .D(target_PC_i[2]), .CK(net3631), .RN(n88),
.Q(\predict_PC[1][2] ) );
DFFR_X1 \predict_PC_reg[1][1] ( .D(target_PC_i[1]), .CK(net3631), .RN(n88),
.Q(\predict_PC[1][1] ) );
DFFR_X1 \predict_PC_reg[1][0] ( .D(target_PC_i[0]), .CK(net3631), .RN(n88),
.Q(\predict_PC[1][0] ) );
DFFR_X1 \predict_PC_reg[2][31] ( .D(n59), .CK(net3636), .RN(n88), .Q(
\predict_PC[2][31] ) );
DFFR_X1 \predict_PC_reg[2][30] ( .D(n38), .CK(net3636), .RN(n88), .Q(
\predict_PC[2][30] ) );
DFFR_X1 \predict_PC_reg[2][29] ( .D(n58), .CK(net3636), .RN(n88), .Q(
\predict_PC[2][29] ) );
DFFR_X1 \predict_PC_reg[2][28] ( .D(n39), .CK(net3636), .RN(n88), .Q(
\predict_PC[2][28] ) );
DFFR_X1 \predict_PC_reg[2][27] ( .D(n60), .CK(net3636), .RN(n88), .Q(
\predict_PC[2][27] ) );
DFFR_X1 \predict_PC_reg[2][26] ( .D(n37), .CK(net3636), .RN(n88), .Q(
\predict_PC[2][26] ) );
DFFR_X1 \predict_PC_reg[2][25] ( .D(n35), .CK(net3636), .RN(n88), .Q(
\predict_PC[2][25] ) );
DFFR_X1 \predict_PC_reg[2][24] ( .D(n36), .CK(net3636), .RN(n89), .Q(
\predict_PC[2][24] ) );
DFFR_X1 \predict_PC_reg[2][23] ( .D(target_PC_i[23]), .CK(net3636), .RN(n89), .Q(\predict_PC[2][23] ) );
DFFR_X1 \predict_PC_reg[2][22] ( .D(target_PC_i[22]), .CK(net3636), .RN(n89), .Q(\predict_PC[2][22] ) );
DFFR_X1 \predict_PC_reg[2][21] ( .D(target_PC_i[21]), .CK(net3636), .RN(n89), .Q(\predict_PC[2][21] ) );
DFFR_X1 \predict_PC_reg[2][20] ( .D(target_PC_i[20]), .CK(net3636), .RN(n89), .Q(\predict_PC[2][20] ) );
DFFR_X1 \predict_PC_reg[2][19] ( .D(target_PC_i[19]), .CK(net3636), .RN(n89), .Q(\predict_PC[2][19] ) );
DFFR_X1 \predict_PC_reg[2][18] ( .D(target_PC_i[18]), .CK(net3636), .RN(n89), .Q(\predict_PC[2][18] ) );
DFFR_X1 \predict_PC_reg[2][17] ( .D(target_PC_i[17]), .CK(net3636), .RN(n89), .Q(\predict_PC[2][17] ) );
DFFR_X1 \predict_PC_reg[2][16] ( .D(target_PC_i[16]), .CK(net3636), .RN(n89), .Q(\predict_PC[2][16] ) );
DFFR_X1 \predict_PC_reg[2][15] ( .D(target_PC_i[15]), .CK(net3636), .RN(n89), .Q(\predict_PC[2][15] ) );
DFFR_X1 \predict_PC_reg[2][14] ( .D(target_PC_i[14]), .CK(net3636), .RN(n89), .Q(\predict_PC[2][14] ) );
DFFR_X1 \predict_PC_reg[2][13] ( .D(target_PC_i[13]), .CK(net3636), .RN(n89), .Q(\predict_PC[2][13] ) );
DFFR_X1 \predict_PC_reg[2][12] ( .D(target_PC_i[12]), .CK(net3636), .RN(n90), .Q(\predict_PC[2][12] ) );
DFFR_X1 \predict_PC_reg[2][11] ( .D(target_PC_i[11]), .CK(net3636), .RN(n90), .Q(\predict_PC[2][11] ) );
DFFR_X1 \predict_PC_reg[2][10] ( .D(target_PC_i[10]), .CK(net3636), .RN(n90), .Q(\predict_PC[2][10] ) );
DFFR_X1 \predict_PC_reg[2][9] ( .D(target_PC_i[9]), .CK(net3636), .RN(n90),
.Q(\predict_PC[2][9] ) );
DFFR_X1 \predict_PC_reg[2][8] ( .D(target_PC_i[8]), .CK(net3636), .RN(n90),
.Q(\predict_PC[2][8] ) );
DFFR_X1 \predict_PC_reg[2][7] ( .D(target_PC_i[7]), .CK(net3636), .RN(n90),
.Q(\predict_PC[2][7] ) );
DFFR_X1 \predict_PC_reg[2][6] ( .D(target_PC_i[6]), .CK(net3636), .RN(n90),
.Q(\predict_PC[2][6] ) );
DFFR_X1 \predict_PC_reg[2][5] ( .D(target_PC_i[5]), .CK(net3636), .RN(n90),
.Q(\predict_PC[2][5] ) );
DFFR_X1 \predict_PC_reg[2][4] ( .D(target_PC_i[4]), .CK(net3636), .RN(n90),
.Q(\predict_PC[2][4] ) );
DFFR_X1 \predict_PC_reg[2][3] ( .D(target_PC_i[3]), .CK(net3636), .RN(n90),
.Q(\predict_PC[2][3] ) );
DFFR_X1 \predict_PC_reg[2][2] ( .D(target_PC_i[2]), .CK(net3636), .RN(n90),
.Q(\predict_PC[2][2] ) );
DFFR_X1 \predict_PC_reg[2][1] ( .D(target_PC_i[1]), .CK(net3636), .RN(n90),
.Q(\predict_PC[2][1] ) );
DFFR_X1 \predict_PC_reg[2][0] ( .D(target_PC_i[0]), .CK(net3636), .RN(n91),
.Q(\predict_PC[2][0] ) );
DFFR_X1 \predict_PC_reg[3][31] ( .D(n59), .CK(net3641), .RN(n91), .Q(
\predict_PC[3][31] ) );
DFFR_X1 \predict_PC_reg[3][30] ( .D(target_PC_i[30]), .CK(net3641), .RN(n91), .Q(\predict_PC[3][30] ) );
DFFR_X1 \predict_PC_reg[3][29] ( .D(n58), .CK(net3641), .RN(n91), .Q(
\predict_PC[3][29] ) );
DFFR_X1 \predict_PC_reg[3][28] ( .D(n39), .CK(net3641), .RN(n91), .Q(
\predict_PC[3][28] ) );
DFFR_X1 \predict_PC_reg[3][27] ( .D(target_PC_i[27]), .CK(net3641), .RN(n91), .Q(\predict_PC[3][27] ) );
DFFR_X1 \predict_PC_reg[3][26] ( .D(n37), .CK(net3641), .RN(n91), .Q(
\predict_PC[3][26] ) );
DFFR_X1 \predict_PC_reg[3][25] ( .D(n35), .CK(net3641), .RN(n91), .Q(
\predict_PC[3][25] ) );
DFFR_X1 \predict_PC_reg[3][24] ( .D(n36), .CK(net3641), .RN(n91), .Q(
\predict_PC[3][24] ) );
DFFR_X1 \predict_PC_reg[3][23] ( .D(target_PC_i[23]), .CK(net3641), .RN(n91), .Q(\predict_PC[3][23] ) );
DFFR_X1 \predict_PC_reg[3][22] ( .D(target_PC_i[22]), .CK(net3641), .RN(n91), .Q(\predict_PC[3][22] ) );
DFFR_X1 \predict_PC_reg[3][21] ( .D(target_PC_i[21]), .CK(net3641), .RN(n91), .Q(\predict_PC[3][21] ) );
DFFR_X1 \predict_PC_reg[3][20] ( .D(target_PC_i[20]), .CK(net3641), .RN(n92), .Q(\predict_PC[3][20] ) );
DFFR_X1 \predict_PC_reg[3][19] ( .D(target_PC_i[19]), .CK(net3641), .RN(n92), .Q(\predict_PC[3][19] ) );
DFFR_X1 \predict_PC_reg[3][18] ( .D(target_PC_i[18]), .CK(net3641), .RN(n92), .Q(\predict_PC[3][18] ) );
DFFR_X1 \predict_PC_reg[3][17] ( .D(target_PC_i[17]), .CK(net3641), .RN(n92), .Q(\predict_PC[3][17] ) );
DFFR_X1 \predict_PC_reg[3][16] ( .D(target_PC_i[16]), .CK(net3641), .RN(n92), .Q(\predict_PC[3][16] ) );
DFFR_X1 \predict_PC_reg[3][15] ( .D(target_PC_i[15]), .CK(net3641), .RN(n92), .Q(\predict_PC[3][15] ) );
DFFR_X1 \predict_PC_reg[3][14] ( .D(target_PC_i[14]), .CK(net3641), .RN(n92), .Q(\predict_PC[3][14] ) );
DFFR_X1 \predict_PC_reg[3][13] ( .D(target_PC_i[13]), .CK(net3641), .RN(n92), .Q(\predict_PC[3][13] ) );
DFFR_X1 \predict_PC_reg[3][12] ( .D(target_PC_i[12]), .CK(net3641), .RN(n92), .Q(\predict_PC[3][12] ) );
DFFR_X1 \predict_PC_reg[3][11] ( .D(target_PC_i[11]), .CK(net3641), .RN(n92), .Q(\predict_PC[3][11] ) );
DFFR_X1 \predict_PC_reg[3][10] ( .D(target_PC_i[10]), .CK(net3641), .RN(n92), .Q(\predict_PC[3][10] ) );
DFFR_X1 \predict_PC_reg[3][9] ( .D(target_PC_i[9]), .CK(net3641), .RN(n92),
.Q(\predict_PC[3][9] ) );
DFFR_X1 \predict_PC_reg[3][8] ( .D(target_PC_i[8]), .CK(net3641), .RN(n93),
.Q(\predict_PC[3][8] ) );
DFFR_X1 \predict_PC_reg[3][7] ( .D(target_PC_i[7]), .CK(net3641), .RN(n93),
.Q(\predict_PC[3][7] ) );
DFFR_X1 \predict_PC_reg[3][6] ( .D(target_PC_i[6]), .CK(net3641), .RN(n93),
.Q(\predict_PC[3][6] ) );
DFFR_X1 \predict_PC_reg[3][5] ( .D(target_PC_i[5]), .CK(net3641), .RN(n93),
.Q(\predict_PC[3][5] ) );
DFFR_X1 \predict_PC_reg[3][4] ( .D(target_PC_i[4]), .CK(net3641), .RN(n93),
.Q(\predict_PC[3][4] ) );
DFFR_X1 \predict_PC_reg[3][3] ( .D(target_PC_i[3]), .CK(net3641), .RN(n93),
.Q(\predict_PC[3][3] ) );
DFFR_X1 \predict_PC_reg[3][2] ( .D(target_PC_i[2]), .CK(net3641), .RN(n80),
.Q(\predict_PC[3][2] ) );
DFFR_X1 \predict_PC_reg[3][1] ( .D(target_PC_i[1]), .CK(net3641), .RN(n77),
.Q(\predict_PC[3][1] ) );
DFFR_X1 \predict_PC_reg[3][0] ( .D(target_PC_i[0]), .CK(net3641), .RN(n78),
.Q(\predict_PC[3][0] ) );
DFFR_X1 \predict_PC_reg[4][31] ( .D(n59), .CK(net3646), .RN(n78), .Q(
\predict_PC[4][31] ) );
DFFR_X1 \predict_PC_reg[4][30] ( .D(n38), .CK(net3646), .RN(n79), .Q(
\predict_PC[4][30] ) );
DFFR_X1 \predict_PC_reg[4][29] ( .D(n58), .CK(net3646), .RN(n77), .Q(
\predict_PC[4][29] ) );
DFFR_X1 \predict_PC_reg[4][28] ( .D(n39), .CK(net3646), .RN(n79), .Q(
\predict_PC[4][28] ) );
DFFR_X1 \predict_PC_reg[4][27] ( .D(n60), .CK(net3646), .RN(n78), .Q(
\predict_PC[4][27] ) );
DFFR_X1 \predict_PC_reg[4][26] ( .D(target_PC_i[26]), .CK(net3646), .RN(n79), .Q(\predict_PC[4][26] ) );
DFFR_X1 \predict_PC_reg[4][25] ( .D(n35), .CK(net3646), .RN(n77), .Q(
\predict_PC[4][25] ) );
DFFR_X1 \predict_PC_reg[4][24] ( .D(target_PC_i[24]), .CK(net3646), .RN(n77), .Q(\predict_PC[4][24] ) );
DFFR_X1 \predict_PC_reg[4][23] ( .D(target_PC_i[23]), .CK(net3646), .RN(n78), .Q(\predict_PC[4][23] ) );
DFFR_X1 \predict_PC_reg[4][22] ( .D(target_PC_i[22]), .CK(net3646), .RN(n78), .Q(\predict_PC[4][22] ) );
DFFR_X1 \predict_PC_reg[4][21] ( .D(target_PC_i[21]), .CK(net3646), .RN(n77), .Q(\predict_PC[4][21] ) );
DFFR_X1 \predict_PC_reg[4][20] ( .D(target_PC_i[20]), .CK(net3646), .RN(n78), .Q(\predict_PC[4][20] ) );
DFFR_X1 \predict_PC_reg[4][19] ( .D(target_PC_i[19]), .CK(net3646), .RN(n79), .Q(\predict_PC[4][19] ) );
DFFR_X1 \predict_PC_reg[4][18] ( .D(target_PC_i[18]), .CK(net3646), .RN(n77), .Q(\predict_PC[4][18] ) );
DFFR_X1 \predict_PC_reg[4][17] ( .D(target_PC_i[17]), .CK(net3646), .RN(n78), .Q(\predict_PC[4][17] ) );
DFFR_X1 \predict_PC_reg[4][16] ( .D(target_PC_i[16]), .CK(net3646), .RN(n79), .Q(\predict_PC[4][16] ) );
DFFR_X1 \predict_PC_reg[4][15] ( .D(target_PC_i[15]), .CK(net3646), .RN(n77), .Q(\predict_PC[4][15] ) );
DFFR_X1 \predict_PC_reg[4][14] ( .D(target_PC_i[14]), .CK(net3646), .RN(n78), .Q(\predict_PC[4][14] ) );
DFFR_X1 \predict_PC_reg[4][13] ( .D(target_PC_i[13]), .CK(net3646), .RN(n79), .Q(\predict_PC[4][13] ) );
DFFR_X1 \predict_PC_reg[4][12] ( .D(target_PC_i[12]), .CK(net3646), .RN(n77), .Q(\predict_PC[4][12] ) );
DFFR_X1 \predict_PC_reg[4][11] ( .D(target_PC_i[11]), .CK(net3646), .RN(n78), .Q(\predict_PC[4][11] ) );
DFFR_X1 \predict_PC_reg[4][10] ( .D(target_PC_i[10]), .CK(net3646), .RN(n77), .Q(\predict_PC[4][10] ) );
DFFR_X1 \predict_PC_reg[4][9] ( .D(target_PC_i[9]), .CK(net3646), .RN(n77),
.Q(\predict_PC[4][9] ) );
DFFR_X1 \predict_PC_reg[4][8] ( .D(target_PC_i[8]), .CK(net3646), .RN(n77),
.Q(\predict_PC[4][8] ) );
DFFR_X1 \predict_PC_reg[4][7] ( .D(target_PC_i[7]), .CK(net3646), .RN(n77),
.Q(\predict_PC[4][7] ) );
DFFR_X1 \predict_PC_reg[4][6] ( .D(target_PC_i[6]), .CK(net3646), .RN(n77),
.Q(\predict_PC[4][6] ) );
DFFR_X1 \predict_PC_reg[4][5] ( .D(target_PC_i[5]), .CK(net3646), .RN(n77),
.Q(\predict_PC[4][5] ) );
DFFR_X1 \predict_PC_reg[4][4] ( .D(target_PC_i[4]), .CK(net3646), .RN(n77),
.Q(\predict_PC[4][4] ) );
DFFR_X1 \predict_PC_reg[4][3] ( .D(target_PC_i[3]), .CK(net3646), .RN(n77),
.Q(\predict_PC[4][3] ) );
DFFR_X1 \predict_PC_reg[4][2] ( .D(target_PC_i[2]), .CK(net3646), .RN(n77),
.Q(\predict_PC[4][2] ) );
DFFR_X1 \predict_PC_reg[4][1] ( .D(target_PC_i[1]), .CK(net3646), .RN(n77),
.Q(\predict_PC[4][1] ) );
DFFR_X1 \predict_PC_reg[4][0] ( .D(target_PC_i[0]), .CK(net3646), .RN(n77),
.Q(\predict_PC[4][0] ) );
DFFR_X1 \predict_PC_reg[5][31] ( .D(n59), .CK(net3651), .RN(n77), .Q(
\predict_PC[5][31] ) );
DFFR_X1 \predict_PC_reg[5][30] ( .D(n38), .CK(net3651), .RN(n78), .Q(
\predict_PC[5][30] ) );
DFFR_X1 \predict_PC_reg[5][29] ( .D(n58), .CK(net3651), .RN(n78), .Q(
\predict_PC[5][29] ) );
DFFR_X1 \predict_PC_reg[5][28] ( .D(n39), .CK(net3651), .RN(n78), .Q(
\predict_PC[5][28] ) );
DFFR_X1 \predict_PC_reg[5][27] ( .D(n60), .CK(net3651), .RN(n78), .Q(
\predict_PC[5][27] ) );
DFFR_X1 \predict_PC_reg[5][26] ( .D(n37), .CK(net3651), .RN(n78), .Q(
\predict_PC[5][26] ) );
DFFR_X1 \predict_PC_reg[5][25] ( .D(n35), .CK(net3651), .RN(n78), .Q(
\predict_PC[5][25] ) );
DFFR_X1 \predict_PC_reg[5][24] ( .D(n36), .CK(net3651), .RN(n78), .Q(
\predict_PC[5][24] ) );
DFFR_X1 \predict_PC_reg[5][23] ( .D(target_PC_i[23]), .CK(net3651), .RN(n78), .Q(\predict_PC[5][23] ) );
DFFR_X1 \predict_PC_reg[5][22] ( .D(target_PC_i[22]), .CK(net3651), .RN(n78), .Q(\predict_PC[5][22] ) );
DFFR_X1 \predict_PC_reg[5][21] ( .D(target_PC_i[21]), .CK(net3651), .RN(n78), .Q(\predict_PC[5][21] ) );
DFFR_X1 \predict_PC_reg[5][20] ( .D(target_PC_i[20]), .CK(net3651), .RN(n78), .Q(\predict_PC[5][20] ) );
DFFR_X1 \predict_PC_reg[5][19] ( .D(target_PC_i[19]), .CK(net3651), .RN(n78), .Q(\predict_PC[5][19] ) );
DFFR_X1 \predict_PC_reg[5][18] ( .D(target_PC_i[18]), .CK(net3651), .RN(n79), .Q(\predict_PC[5][18] ) );
DFFR_X1 \predict_PC_reg[5][17] ( .D(target_PC_i[17]), .CK(net3651), .RN(n79), .Q(\predict_PC[5][17] ) );
DFFR_X1 \predict_PC_reg[5][16] ( .D(target_PC_i[16]), .CK(net3651), .RN(n79), .Q(\predict_PC[5][16] ) );
DFFR_X1 \predict_PC_reg[5][15] ( .D(target_PC_i[15]), .CK(net3651), .RN(n79), .Q(\predict_PC[5][15] ) );
DFFR_X1 \predict_PC_reg[5][14] ( .D(target_PC_i[14]), .CK(net3651), .RN(n79), .Q(\predict_PC[5][14] ) );
DFFR_X1 \predict_PC_reg[5][13] ( .D(target_PC_i[13]), .CK(net3651), .RN(n79), .Q(\predict_PC[5][13] ) );
DFFR_X1 \predict_PC_reg[5][12] ( .D(target_PC_i[12]), .CK(net3651), .RN(n79), .Q(\predict_PC[5][12] ) );
DFFR_X1 \predict_PC_reg[5][11] ( .D(target_PC_i[11]), .CK(net3651), .RN(n79), .Q(\predict_PC[5][11] ) );
DFFR_X1 \predict_PC_reg[5][10] ( .D(target_PC_i[10]), .CK(net3651), .RN(n79), .Q(\predict_PC[5][10] ) );
DFFR_X1 \predict_PC_reg[5][9] ( .D(target_PC_i[9]), .CK(net3651), .RN(n79),
.Q(\predict_PC[5][9] ) );
DFFR_X1 \predict_PC_reg[5][8] ( .D(target_PC_i[8]), .CK(net3651), .RN(n79),
.Q(\predict_PC[5][8] ) );
DFFR_X1 \predict_PC_reg[5][7] ( .D(target_PC_i[7]), .CK(net3651), .RN(n79),
.Q(\predict_PC[5][7] ) );
DFFR_X1 \predict_PC_reg[5][6] ( .D(target_PC_i[6]), .CK(net3651), .RN(n80),
.Q(\predict_PC[5][6] ) );
DFFR_X1 \predict_PC_reg[5][5] ( .D(target_PC_i[5]), .CK(net3651), .RN(n81),
.Q(\predict_PC[5][5] ) );
DFFR_X1 \predict_PC_reg[5][4] ( .D(target_PC_i[4]), .CK(net3651), .RN(n82),
.Q(\predict_PC[5][4] ) );
DFFR_X1 \predict_PC_reg[5][3] ( .D(target_PC_i[3]), .CK(net3651), .RN(n83),
.Q(\predict_PC[5][3] ) );
DFFR_X1 \predict_PC_reg[5][2] ( .D(target_PC_i[2]), .CK(net3651), .RN(n83),
.Q(\predict_PC[5][2] ) );
DFFR_X1 \predict_PC_reg[5][1] ( .D(target_PC_i[1]), .CK(net3651), .RN(n80),
.Q(\predict_PC[5][1] ) );
DFFR_X1 \predict_PC_reg[5][0] ( .D(target_PC_i[0]), .CK(net3651), .RN(n81),
.Q(\predict_PC[5][0] ) );
DFFR_X1 \predict_PC_reg[6][31] ( .D(n59), .CK(net3656), .RN(n82), .Q(
\predict_PC[6][31] ) );
DFFR_X1 \predict_PC_reg[6][30] ( .D(n38), .CK(net3656), .RN(n83), .Q(
\predict_PC[6][30] ) );
DFFR_X1 \predict_PC_reg[6][29] ( .D(n58), .CK(net3656), .RN(n83), .Q(
\predict_PC[6][29] ) );
DFFR_X1 \predict_PC_reg[6][28] ( .D(n39), .CK(net3656), .RN(n81), .Q(
\predict_PC[6][28] ) );
DFFR_X1 \predict_PC_reg[6][27] ( .D(n60), .CK(net3656), .RN(n81), .Q(
\predict_PC[6][27] ) );
DFFR_X1 \predict_PC_reg[6][26] ( .D(n37), .CK(net3656), .RN(n82), .Q(
\predict_PC[6][26] ) );
DFFR_X1 \predict_PC_reg[6][25] ( .D(n35), .CK(net3656), .RN(n83), .Q(
\predict_PC[6][25] ) );
DFFR_X1 \predict_PC_reg[6][24] ( .D(n36), .CK(net3656), .RN(n80), .Q(
\predict_PC[6][24] ) );
DFFR_X1 \predict_PC_reg[6][23] ( .D(target_PC_i[23]), .CK(net3656), .RN(n81), .Q(\predict_PC[6][23] ) );
DFFR_X1 \predict_PC_reg[6][22] ( .D(target_PC_i[22]), .CK(net3656), .RN(n82), .Q(\predict_PC[6][22] ) );
DFFR_X1 \predict_PC_reg[6][21] ( .D(target_PC_i[21]), .CK(net3656), .RN(n83), .Q(\predict_PC[6][21] ) );
DFFR_X1 \predict_PC_reg[6][20] ( .D(target_PC_i[20]), .CK(net3656), .RN(n80), .Q(\predict_PC[6][20] ) );
DFFR_X1 \predict_PC_reg[6][19] ( .D(target_PC_i[19]), .CK(net3656), .RN(n81), .Q(\predict_PC[6][19] ) );
DFFR_X1 \predict_PC_reg[6][18] ( .D(target_PC_i[18]), .CK(net3656), .RN(n82), .Q(\predict_PC[6][18] ) );
DFFR_X1 \predict_PC_reg[6][17] ( .D(target_PC_i[17]), .CK(net3656), .RN(n83), .Q(\predict_PC[6][17] ) );
DFFR_X1 \predict_PC_reg[6][16] ( .D(target_PC_i[16]), .CK(net3656), .RN(n80), .Q(\predict_PC[6][16] ) );
DFFR_X1 \predict_PC_reg[6][15] ( .D(target_PC_i[15]), .CK(net3656), .RN(n80), .Q(\predict_PC[6][15] ) );
DFFR_X1 \predict_PC_reg[6][14] ( .D(target_PC_i[14]), .CK(net3656), .RN(n80), .Q(\predict_PC[6][14] ) );
DFFR_X1 \predict_PC_reg[6][13] ( .D(target_PC_i[13]), .CK(net3656), .RN(n80), .Q(\predict_PC[6][13] ) );
DFFR_X1 \predict_PC_reg[6][12] ( .D(target_PC_i[12]), .CK(net3656), .RN(n80), .Q(\predict_PC[6][12] ) );
DFFR_X1 \predict_PC_reg[6][11] ( .D(target_PC_i[11]), .CK(net3656), .RN(n80), .Q(\predict_PC[6][11] ) );
DFFR_X1 \predict_PC_reg[6][10] ( .D(target_PC_i[10]), .CK(net3656), .RN(n80), .Q(\predict_PC[6][10] ) );
DFFR_X1 \predict_PC_reg[6][9] ( .D(target_PC_i[9]), .CK(net3656), .RN(n80),
.Q(\predict_PC[6][9] ) );
DFFR_X1 \predict_PC_reg[6][8] ( .D(target_PC_i[8]), .CK(net3656), .RN(n80),
.Q(\predict_PC[6][8] ) );
DFFR_X1 \predict_PC_reg[6][7] ( .D(target_PC_i[7]), .CK(net3656), .RN(n80),
.Q(\predict_PC[6][7] ) );
DFFR_X1 \predict_PC_reg[6][6] ( .D(target_PC_i[6]), .CK(net3656), .RN(n80),
.Q(\predict_PC[6][6] ) );
DFFR_X1 \predict_PC_reg[6][5] ( .D(target_PC_i[5]), .CK(net3656), .RN(n80),
.Q(\predict_PC[6][5] ) );
DFFR_X1 \predict_PC_reg[6][4] ( .D(target_PC_i[4]), .CK(net3656), .RN(n80),
.Q(\predict_PC[6][4] ) );
DFFR_X1 \predict_PC_reg[6][3] ( .D(target_PC_i[3]), .CK(net3656), .RN(n81),
.Q(\predict_PC[6][3] ) );
DFFR_X1 \predict_PC_reg[6][2] ( .D(target_PC_i[2]), .CK(net3656), .RN(n81),
.Q(\predict_PC[6][2] ) );
DFFR_X1 \predict_PC_reg[6][1] ( .D(target_PC_i[1]), .CK(net3656), .RN(n81),
.Q(\predict_PC[6][1] ) );
DFFR_X1 \predict_PC_reg[6][0] ( .D(target_PC_i[0]), .CK(net3656), .RN(n81),
.Q(\predict_PC[6][0] ) );
DFFR_X1 \predict_PC_reg[7][31] ( .D(n59), .CK(net3661), .RN(n81), .Q(
\predict_PC[7][31] ) );
DFFR_X1 \predict_PC_reg[7][30] ( .D(n38), .CK(net3661), .RN(n81), .Q(
\predict_PC[7][30] ) );
DFFR_X1 \predict_PC_reg[7][29] ( .D(n58), .CK(net3661), .RN(n81), .Q(
\predict_PC[7][29] ) );
DFFR_X1 \predict_PC_reg[7][28] ( .D(n39), .CK(net3661), .RN(n81), .Q(
\predict_PC[7][28] ) );
DFFR_X1 \predict_PC_reg[7][27] ( .D(n60), .CK(net3661), .RN(n81), .Q(
\predict_PC[7][27] ) );
DFFR_X1 \predict_PC_reg[7][26] ( .D(n37), .CK(net3661), .RN(n81), .Q(
\predict_PC[7][26] ) );
DFFR_X1 \predict_PC_reg[7][25] ( .D(n35), .CK(net3661), .RN(n81), .Q(
\predict_PC[7][25] ) );
DFFR_X1 \predict_PC_reg[7][24] ( .D(n36), .CK(net3661), .RN(n81), .Q(
\predict_PC[7][24] ) );
DFFR_X1 \predict_PC_reg[7][23] ( .D(target_PC_i[23]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][23] ) );
DFFR_X1 \predict_PC_reg[7][22] ( .D(target_PC_i[22]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][22] ) );
DFFR_X1 \predict_PC_reg[7][21] ( .D(target_PC_i[21]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][21] ) );
DFFR_X1 \predict_PC_reg[7][20] ( .D(target_PC_i[20]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][20] ) );
DFFR_X1 \predict_PC_reg[7][19] ( .D(target_PC_i[19]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][19] ) );
DFFR_X1 \predict_PC_reg[7][18] ( .D(target_PC_i[18]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][18] ) );
DFFR_X1 \predict_PC_reg[7][17] ( .D(target_PC_i[17]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][17] ) );
DFFR_X1 \predict_PC_reg[7][16] ( .D(target_PC_i[16]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][16] ) );
DFFR_X1 \predict_PC_reg[7][15] ( .D(target_PC_i[15]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][15] ) );
DFFR_X1 \predict_PC_reg[7][14] ( .D(target_PC_i[14]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][14] ) );
DFFR_X1 \predict_PC_reg[7][13] ( .D(target_PC_i[13]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][13] ) );
DFFR_X1 \predict_PC_reg[7][12] ( .D(target_PC_i[12]), .CK(net3661), .RN(n82), .Q(\predict_PC[7][12] ) );
DFFR_X1 \predict_PC_reg[7][11] ( .D(target_PC_i[11]), .CK(net3661), .RN(n83), .Q(\predict_PC[7][11] ) );
DFFR_X1 \predict_PC_reg[7][10] ( .D(target_PC_i[10]), .CK(net3661), .RN(n83), .Q(\predict_PC[7][10] ) );
DFFR_X1 \predict_PC_reg[7][9] ( .D(target_PC_i[9]), .CK(net3661), .RN(n83),
.Q(\predict_PC[7][9] ) );
DFFR_X1 \predict_PC_reg[7][8] ( .D(target_PC_i[8]), .CK(net3661), .RN(n83),
.Q(\predict_PC[7][8] ) );
DFFR_X1 \predict_PC_reg[7][7] ( .D(target_PC_i[7]), .CK(net3661), .RN(n83),
.Q(\predict_PC[7][7] ) );
DFFR_X1 \predict_PC_reg[7][6] ( .D(target_PC_i[6]), .CK(net3661), .RN(n83),
.Q(\predict_PC[7][6] ) );
DFFR_X1 \predict_PC_reg[7][5] ( .D(target_PC_i[5]), .CK(net3661), .RN(n83),
.Q(\predict_PC[7][5] ) );
DFFR_X1 \predict_PC_reg[7][4] ( .D(target_PC_i[4]), .CK(net3661), .RN(n83),
.Q(\predict_PC[7][4] ) );
DFFR_X1 \predict_PC_reg[7][3] ( .D(target_PC_i[3]), .CK(net3661), .RN(n83),
.Q(\predict_PC[7][3] ) );
DFFR_X1 \predict_PC_reg[7][2] ( .D(target_PC_i[2]), .CK(net3661), .RN(n83),
.Q(\predict_PC[7][2] ) );
DFFR_X1 \predict_PC_reg[7][1] ( .D(target_PC_i[1]), .CK(net3661), .RN(n83),
.Q(\predict_PC[7][1] ) );
DFFR_X1 \predict_PC_reg[7][0] ( .D(target_PC_i[0]), .CK(net3661), .RN(n83),
.Q(\predict_PC[7][0] ) );
DFFR_X1 \predict_PC_reg[8][31] ( .D(n59), .CK(net3666), .RN(n82), .Q(
\predict_PC[8][31] ) );
DFFR_X1 \predict_PC_reg[8][30] ( .D(target_PC_i[30]), .CK(net3666), .RN(n81), .Q(\predict_PC[8][30] ) );
DFFR_X1 \predict_PC_reg[8][29] ( .D(n58), .CK(net3666), .RN(n80), .Q(
\predict_PC[8][29] ) );
DFFR_X1 \predict_PC_reg[8][28] ( .D(n39), .CK(net3666), .RN(n81), .Q(
\predict_PC[8][28] ) );
DFFR_X1 \predict_PC_reg[8][27] ( .D(target_PC_i[27]), .CK(net3666), .RN(n82), .Q(\predict_PC[8][27] ) );
DFFR_X1 \predict_PC_reg[8][26] ( .D(n37), .CK(net3666), .RN(n83), .Q(
\predict_PC[8][26] ) );
DFFR_X1 \predict_PC_reg[8][25] ( .D(n35), .CK(net3666), .RN(n80), .Q(
\predict_PC[8][25] ) );
DFFR_X1 \predict_PC_reg[8][24] ( .D(n36), .CK(net3666), .RN(n82), .Q(
\predict_PC[8][24] ) );
DFFR_X1 \predict_PC_reg[8][23] ( .D(target_PC_i[23]), .CK(net3666), .RN(n80), .Q(\predict_PC[8][23] ) );
DFFR_X1 \predict_PC_reg[8][22] ( .D(target_PC_i[22]), .CK(net3666), .RN(n97), .Q(\predict_PC[8][22] ) );
DFFR_X1 \predict_PC_reg[8][21] ( .D(target_PC_i[21]), .CK(net3666), .RN(n97), .Q(\predict_PC[8][21] ) );
DFFR_X1 \predict_PC_reg[8][20] ( .D(target_PC_i[20]), .CK(net3666), .RN(n85), .Q(\predict_PC[8][20] ) );
DFFR_X1 \predict_PC_reg[8][19] ( .D(target_PC_i[19]), .CK(net3666), .RN(n91), .Q(\predict_PC[8][19] ) );
DFFR_X1 \predict_PC_reg[8][18] ( .D(target_PC_i[18]), .CK(net3666), .RN(n90), .Q(\predict_PC[8][18] ) );
DFFR_X1 \predict_PC_reg[8][17] ( .D(target_PC_i[17]), .CK(net3666), .RN(n89), .Q(\predict_PC[8][17] ) );
DFFR_X1 \predict_PC_reg[8][16] ( .D(target_PC_i[16]), .CK(net3666), .RN(n88), .Q(\predict_PC[8][16] ) );
DFFR_X1 \predict_PC_reg[8][15] ( .D(target_PC_i[15]), .CK(net3666), .RN(n93), .Q(\predict_PC[8][15] ) );
DFFR_X1 \predict_PC_reg[8][14] ( .D(target_PC_i[14]), .CK(net3666), .RN(n92), .Q(\predict_PC[8][14] ) );
DFFR_X1 \predict_PC_reg[8][13] ( .D(target_PC_i[13]), .CK(net3666), .RN(n94), .Q(\predict_PC[8][13] ) );
DFFR_X1 \predict_PC_reg[8][12] ( .D(target_PC_i[12]), .CK(net3666), .RN(n87), .Q(\predict_PC[8][12] ) );
DFFR_X1 \predict_PC_reg[8][11] ( .D(target_PC_i[11]), .CK(net3666), .RN(n99), .Q(\predict_PC[8][11] ) );
DFFR_X1 \predict_PC_reg[8][10] ( .D(target_PC_i[10]), .CK(net3666), .RN(n91), .Q(\predict_PC[8][10] ) );
DFFR_X1 \predict_PC_reg[8][9] ( .D(target_PC_i[9]), .CK(net3666), .RN(n92),
.Q(\predict_PC[8][9] ) );
DFFR_X1 \predict_PC_reg[8][8] ( .D(target_PC_i[8]), .CK(net3666), .RN(n92),
.Q(\predict_PC[8][8] ) );
DFFR_X1 \predict_PC_reg[8][7] ( .D(target_PC_i[7]), .CK(net3666), .RN(n82),
.Q(\predict_PC[8][7] ) );
DFFR_X1 \predict_PC_reg[8][6] ( .D(target_PC_i[6]), .CK(net3666), .RN(n90),
.Q(\predict_PC[8][6] ) );
DFFR_X1 \predict_PC_reg[8][5] ( .D(target_PC_i[5]), .CK(net3666), .RN(n98),
.Q(\predict_PC[8][5] ) );
DFFR_X1 \predict_PC_reg[8][4] ( .D(target_PC_i[4]), .CK(net3666), .RN(n96),
.Q(\predict_PC[8][4] ) );
DFFR_X1 \predict_PC_reg[8][3] ( .D(target_PC_i[3]), .CK(net3666), .RN(n92),
.Q(\predict_PC[8][3] ) );
DFFR_X1 \predict_PC_reg[8][2] ( .D(target_PC_i[2]), .CK(net3666), .RN(n84),
.Q(\predict_PC[8][2] ) );
DFFR_X1 \predict_PC_reg[8][1] ( .D(target_PC_i[1]), .CK(net3666), .RN(n93),
.Q(\predict_PC[8][1] ) );
DFFR_X1 \predict_PC_reg[8][0] ( .D(target_PC_i[0]), .CK(net3666), .RN(n83),
.Q(\predict_PC[8][0] ) );
DFFR_X1 \predict_PC_reg[9][31] ( .D(n59), .CK(net3671), .RN(n97), .Q(
\predict_PC[9][31] ) );
DFFR_X1 \predict_PC_reg[9][30] ( .D(n38), .CK(net3671), .RN(n97), .Q(
\predict_PC[9][30] ) );
DFFR_X1 \predict_PC_reg[9][29] ( .D(n58), .CK(net3671), .RN(n97), .Q(
\predict_PC[9][29] ) );
DFFR_X1 \predict_PC_reg[9][28] ( .D(n39), .CK(net3671), .RN(n97), .Q(
\predict_PC[9][28] ) );
DFFR_X1 \predict_PC_reg[9][27] ( .D(n60), .CK(net3671), .RN(n97), .Q(
\predict_PC[9][27] ) );
DFFR_X1 \predict_PC_reg[9][26] ( .D(n37), .CK(net3671), .RN(n97), .Q(
\predict_PC[9][26] ) );
DFFR_X1 \predict_PC_reg[9][25] ( .D(n35), .CK(net3671), .RN(n97), .Q(
\predict_PC[9][25] ) );
DFFR_X1 \predict_PC_reg[9][24] ( .D(n36), .CK(net3671), .RN(n97), .Q(
\predict_PC[9][24] ) );
DFFR_X1 \predict_PC_reg[9][23] ( .D(target_PC_i[23]), .CK(net3671), .RN(n97), .Q(\predict_PC[9][23] ) );
DFFR_X1 \predict_PC_reg[9][22] ( .D(target_PC_i[22]), .CK(net3671), .RN(n97), .Q(\predict_PC[9][22] ) );
DFFR_X1 \predict_PC_reg[9][21] ( .D(target_PC_i[21]), .CK(net3671), .RN(n97), .Q(\predict_PC[9][21] ) );
DFFR_X1 \predict_PC_reg[9][20] ( .D(target_PC_i[20]), .CK(net3671), .RN(n97), .Q(\predict_PC[9][20] ) );
DFFR_X1 \predict_PC_reg[9][19] ( .D(target_PC_i[19]), .CK(net3671), .RN(n98), .Q(\predict_PC[9][19] ) );
DFFR_X1 \predict_PC_reg[9][18] ( .D(target_PC_i[18]), .CK(net3671), .RN(n98), .Q(\predict_PC[9][18] ) );
DFFR_X1 \predict_PC_reg[9][17] ( .D(target_PC_i[17]), .CK(net3671), .RN(n98), .Q(\predict_PC[9][17] ) );
DFFR_X1 \predict_PC_reg[9][16] ( .D(target_PC_i[16]), .CK(net3671), .RN(n98), .Q(\predict_PC[9][16] ) );
DFFR_X1 \predict_PC_reg[9][15] ( .D(target_PC_i[15]), .CK(net3671), .RN(n98), .Q(\predict_PC[9][15] ) );
DFFR_X1 \predict_PC_reg[9][14] ( .D(target_PC_i[14]), .CK(net3671), .RN(n98), .Q(\predict_PC[9][14] ) );
DFFR_X1 \predict_PC_reg[9][13] ( .D(target_PC_i[13]), .CK(net3671), .RN(n98), .Q(\predict_PC[9][13] ) );
DFFR_X1 \predict_PC_reg[9][12] ( .D(target_PC_i[12]), .CK(net3671), .RN(n98), .Q(\predict_PC[9][12] ) );
DFFR_X1 \predict_PC_reg[9][11] ( .D(target_PC_i[11]), .CK(net3671), .RN(n98), .Q(\predict_PC[9][11] ) );
DFFR_X1 \predict_PC_reg[9][10] ( .D(target_PC_i[10]), .CK(net3671), .RN(n98), .Q(\predict_PC[9][10] ) );
DFFR_X1 \predict_PC_reg[9][9] ( .D(target_PC_i[9]), .CK(net3671), .RN(n98),
.Q(\predict_PC[9][9] ) );
DFFR_X1 \predict_PC_reg[9][8] ( .D(target_PC_i[8]), .CK(net3671), .RN(n98),
.Q(\predict_PC[9][8] ) );
DFFR_X1 \predict_PC_reg[9][7] ( .D(target_PC_i[7]), .CK(net3671), .RN(n83),
.Q(\predict_PC[9][7] ) );
DFFR_X1 \predict_PC_reg[9][6] ( .D(target_PC_i[6]), .CK(net3671), .RN(n91),
.Q(\predict_PC[9][6] ) );
DFFR_X1 \predict_PC_reg[9][5] ( .D(target_PC_i[5]), .CK(net3671), .RN(n90),
.Q(\predict_PC[9][5] ) );
DFFR_X1 \predict_PC_reg[9][4] ( .D(target_PC_i[4]), .CK(net3671), .RN(n89),
.Q(\predict_PC[9][4] ) );
DFFR_X1 \predict_PC_reg[9][3] ( .D(target_PC_i[3]), .CK(net3671), .RN(n88),
.Q(\predict_PC[9][3] ) );
DFFR_X1 \predict_PC_reg[9][2] ( .D(target_PC_i[2]), .CK(net3671), .RN(n93),
.Q(\predict_PC[9][2] ) );
DFFR_X1 \predict_PC_reg[9][1] ( .D(target_PC_i[1]), .CK(net3671), .RN(n92),
.Q(\predict_PC[9][1] ) );
DFFR_X1 \predict_PC_reg[9][0] ( .D(target_PC_i[0]), .CK(net3671), .RN(n94),
.Q(\predict_PC[9][0] ) );
DFFR_X1 \predict_PC_reg[10][31] ( .D(n59), .CK(net3676), .RN(n88), .Q(
\predict_PC[10][31] ) );
DFFR_X1 \predict_PC_reg[10][30] ( .D(n38), .CK(net3676), .RN(n90), .Q(
\predict_PC[10][30] ) );
DFFR_X1 \predict_PC_reg[10][29] ( .D(n58), .CK(net3676), .RN(n100), .Q(
\predict_PC[10][29] ) );
DFFR_X1 \predict_PC_reg[10][28] ( .D(n39), .CK(net3676), .RN(n99), .Q(
\predict_PC[10][28] ) );
DFFR_X1 \predict_PC_reg[10][27] ( .D(target_PC_i[27]), .CK(net3676), .RN(
n96), .Q(\predict_PC[10][27] ) );
DFFR_X1 \predict_PC_reg[10][26] ( .D(n37), .CK(net3676), .RN(n95), .Q(
\predict_PC[10][26] ) );
DFFR_X1 \predict_PC_reg[10][25] ( .D(n35), .CK(net3676), .RN(n81), .Q(
\predict_PC[10][25] ) );
DFFR_X1 \predict_PC_reg[10][24] ( .D(n36), .CK(net3676), .RN(n98), .Q(
\predict_PC[10][24] ) );
DFFR_X1 \predict_PC_reg[10][23] ( .D(target_PC_i[23]), .CK(net3676), .RN(
n97), .Q(\predict_PC[10][23] ) );
DFFR_X1 \predict_PC_reg[10][22] ( .D(target_PC_i[22]), .CK(net3676), .RN(
n91), .Q(\predict_PC[10][22] ) );
DFFR_X1 \predict_PC_reg[10][21] ( .D(target_PC_i[21]), .CK(net3676), .RN(
n90), .Q(\predict_PC[10][21] ) );
DFFR_X1 \predict_PC_reg[10][20] ( .D(target_PC_i[20]), .CK(net3676), .RN(
n89), .Q(\predict_PC[10][20] ) );
DFFR_X1 \predict_PC_reg[10][19] ( .D(target_PC_i[19]), .CK(net3676), .RN(
n88), .Q(\predict_PC[10][19] ) );
DFFR_X1 \predict_PC_reg[10][18] ( .D(target_PC_i[18]), .CK(net3676), .RN(
n93), .Q(\predict_PC[10][18] ) );
DFFR_X1 \predict_PC_reg[10][17] ( .D(target_PC_i[17]), .CK(net3676), .RN(
n92), .Q(\predict_PC[10][17] ) );
DFFR_X1 \predict_PC_reg[10][16] ( .D(target_PC_i[16]), .CK(net3676), .RN(
n94), .Q(\predict_PC[10][16] ) );
DFFR_X1 \predict_PC_reg[10][15] ( .D(target_PC_i[15]), .CK(net3676), .RN(
n85), .Q(\predict_PC[10][15] ) );
DFFR_X1 \predict_PC_reg[10][14] ( .D(target_PC_i[14]), .CK(net3676), .RN(
n89), .Q(\predict_PC[10][14] ) );
DFFR_X1 \predict_PC_reg[10][13] ( .D(target_PC_i[13]), .CK(net3676), .RN(
n89), .Q(\predict_PC[10][13] ) );
DFFR_X1 \predict_PC_reg[10][12] ( .D(target_PC_i[12]), .CK(net3676), .RN(
n94), .Q(\predict_PC[10][12] ) );
DFFR_X1 \predict_PC_reg[10][11] ( .D(target_PC_i[11]), .CK(net3676), .RN(
n99), .Q(\predict_PC[10][11] ) );
DFFR_X1 \predict_PC_reg[10][10] ( .D(target_PC_i[10]), .CK(net3676), .RN(
n96), .Q(\predict_PC[10][10] ) );
DFFR_X1 \predict_PC_reg[10][9] ( .D(target_PC_i[9]), .CK(net3676), .RN(n88),
.Q(\predict_PC[10][9] ) );
DFFR_X1 \predict_PC_reg[10][8] ( .D(target_PC_i[8]), .CK(net3676), .RN(n93),
.Q(\predict_PC[10][8] ) );
DFFR_X1 \predict_PC_reg[10][7] ( .D(target_PC_i[7]), .CK(net3676), .RN(n98),
.Q(\predict_PC[10][7] ) );
DFFR_X1 \predict_PC_reg[10][6] ( .D(target_PC_i[6]), .CK(net3676), .RN(n95),
.Q(\predict_PC[10][6] ) );
DFFR_X1 \predict_PC_reg[10][5] ( .D(target_PC_i[5]), .CK(net3676), .RN(n100), .Q(\predict_PC[10][5] ) );
DFFR_X1 \predict_PC_reg[10][4] ( .D(target_PC_i[4]), .CK(net3676), .RN(n82),
.Q(\predict_PC[10][4] ) );
DFFR_X1 \predict_PC_reg[10][3] ( .D(target_PC_i[3]), .CK(net3676), .RN(n82),
.Q(\predict_PC[10][3] ) );
DFFR_X1 \predict_PC_reg[10][2] ( .D(target_PC_i[2]), .CK(net3676), .RN(n95),
.Q(\predict_PC[10][2] ) );
DFFR_X1 \predict_PC_reg[10][1] ( .D(target_PC_i[1]), .CK(net3676), .RN(n84),
.Q(\predict_PC[10][1] ) );
DFFR_X1 \predict_PC_reg[10][0] ( .D(target_PC_i[0]), .CK(net3676), .RN(n98),
.Q(\predict_PC[10][0] ) );
DFFR_X1 \predict_PC_reg[11][31] ( .D(n59), .CK(net3681), .RN(n97), .Q(
\predict_PC[11][31] ) );
DFFR_X1 \predict_PC_reg[11][30] ( .D(n38), .CK(net3681), .RN(n85), .Q(
\predict_PC[11][30] ) );
DFFR_X1 \predict_PC_reg[11][29] ( .D(n58), .CK(net3681), .RN(n87), .Q(
\predict_PC[11][29] ) );
DFFR_X1 \predict_PC_reg[11][28] ( .D(target_PC_i[28]), .CK(net3681), .RN(
n84), .Q(\predict_PC[11][28] ) );
DFFR_X1 \predict_PC_reg[11][27] ( .D(target_PC_i[27]), .CK(net3681), .RN(
n91), .Q(\predict_PC[11][27] ) );
DFFR_X1 \predict_PC_reg[11][26] ( .D(n37), .CK(net3681), .RN(n90), .Q(
\predict_PC[11][26] ) );
DFFR_X1 \predict_PC_reg[11][25] ( .D(target_PC_i[25]), .CK(net3681), .RN(
n92), .Q(\predict_PC[11][25] ) );
DFFR_X1 \predict_PC_reg[11][24] ( .D(n36), .CK(net3681), .RN(n99), .Q(
\predict_PC[11][24] ) );
DFFR_X1 \predict_PC_reg[11][23] ( .D(target_PC_i[23]), .CK(net3681), .RN(
n96), .Q(\predict_PC[11][23] ) );
DFFR_X1 \predict_PC_reg[11][22] ( .D(target_PC_i[22]), .CK(net3681), .RN(
n81), .Q(\predict_PC[11][22] ) );
DFFR_X1 \predict_PC_reg[11][21] ( .D(target_PC_i[21]), .CK(net3681), .RN(
n81), .Q(\predict_PC[11][21] ) );
DFFR_X1 \predict_PC_reg[11][20] ( .D(target_PC_i[20]), .CK(net3681), .RN(
n95), .Q(\predict_PC[11][20] ) );
DFFR_X1 \predict_PC_reg[11][19] ( .D(target_PC_i[19]), .CK(net3681), .RN(
n80), .Q(\predict_PC[11][19] ) );
DFFR_X1 \predict_PC_reg[11][18] ( .D(target_PC_i[18]), .CK(net3681), .RN(
n98), .Q(\predict_PC[11][18] ) );
DFFR_X1 \predict_PC_reg[11][17] ( .D(target_PC_i[17]), .CK(net3681), .RN(
n97), .Q(\predict_PC[11][17] ) );
DFFR_X1 \predict_PC_reg[11][16] ( .D(target_PC_i[16]), .CK(net3681), .RN(
n86), .Q(\predict_PC[11][16] ) );
DFFR_X1 \predict_PC_reg[11][15] ( .D(target_PC_i[15]), .CK(net3681), .RN(
n85), .Q(\predict_PC[11][15] ) );
DFFR_X1 \predict_PC_reg[11][14] ( .D(target_PC_i[14]), .CK(net3681), .RN(
n87), .Q(\predict_PC[11][14] ) );
DFFR_X1 \predict_PC_reg[11][13] ( .D(target_PC_i[13]), .CK(net3681), .RN(
n99), .Q(\predict_PC[11][13] ) );
DFFR_X1 \predict_PC_reg[11][12] ( .D(target_PC_i[12]), .CK(net3681), .RN(
n99), .Q(\predict_PC[11][12] ) );
DFFR_X1 \predict_PC_reg[11][11] ( .D(target_PC_i[11]), .CK(net3681), .RN(
n99), .Q(\predict_PC[11][11] ) );
DFFR_X1 \predict_PC_reg[11][10] ( .D(target_PC_i[10]), .CK(net3681), .RN(
n99), .Q(\predict_PC[11][10] ) );
DFFR_X1 \predict_PC_reg[11][9] ( .D(target_PC_i[9]), .CK(net3681), .RN(n99),
.Q(\predict_PC[11][9] ) );
DFFR_X1 \predict_PC_reg[11][8] ( .D(target_PC_i[8]), .CK(net3681), .RN(n99),
.Q(\predict_PC[11][8] ) );
DFFR_X1 \predict_PC_reg[11][7] ( .D(target_PC_i[7]), .CK(net3681), .RN(n99),
.Q(\predict_PC[11][7] ) );
DFFR_X1 \predict_PC_reg[11][6] ( .D(target_PC_i[6]), .CK(net3681), .RN(n99),
.Q(\predict_PC[11][6] ) );
DFFR_X1 \predict_PC_reg[11][5] ( .D(target_PC_i[5]), .CK(net3681), .RN(n84),
.Q(\predict_PC[11][5] ) );
DFFR_X1 \predict_PC_reg[11][4] ( .D(target_PC_i[4]), .CK(net3681), .RN(n99),
.Q(\predict_PC[11][4] ) );
DFFR_X1 \predict_PC_reg[11][3] ( .D(target_PC_i[3]), .CK(net3681), .RN(n99),
.Q(\predict_PC[11][3] ) );
DFFR_X1 \predict_PC_reg[11][2] ( .D(target_PC_i[2]), .CK(net3681), .RN(n99),
.Q(\predict_PC[11][2] ) );
DFFR_X1 \predict_PC_reg[11][1] ( .D(target_PC_i[1]), .CK(net3681), .RN(n100), .Q(\predict_PC[11][1] ) );
DFFR_X1 \predict_PC_reg[11][0] ( .D(target_PC_i[0]), .CK(net3681), .RN(n100), .Q(\predict_PC[11][0] ) );
DFFR_X1 \predict_PC_reg[12][31] ( .D(n59), .CK(net3686), .RN(n100), .Q(
\predict_PC[12][31] ) );
DFFR_X1 \predict_PC_reg[12][30] ( .D(n38), .CK(net3686), .RN(n100), .Q(
\predict_PC[12][30] ) );
DFFR_X1 \predict_PC_reg[12][29] ( .D(n58), .CK(net3686), .RN(n100), .Q(
\predict_PC[12][29] ) );
DFFR_X1 \predict_PC_reg[12][28] ( .D(n39), .CK(net3686), .RN(n100), .Q(
\predict_PC[12][28] ) );
DFFR_X1 \predict_PC_reg[12][27] ( .D(target_PC_i[27]), .CK(net3686), .RN(
n100), .Q(\predict_PC[12][27] ) );
DFFR_X1 \predict_PC_reg[12][26] ( .D(n37), .CK(net3686), .RN(n100), .Q(
\predict_PC[12][26] ) );
DFFR_X1 \predict_PC_reg[12][25] ( .D(n35), .CK(net3686), .RN(n100), .Q(
\predict_PC[12][25] ) );
DFFR_X1 \predict_PC_reg[12][24] ( .D(n36), .CK(net3686), .RN(n100), .Q(
\predict_PC[12][24] ) );
DFFR_X1 \predict_PC_reg[12][23] ( .D(target_PC_i[23]), .CK(net3686), .RN(
n99), .Q(\predict_PC[12][23] ) );
DFFR_X1 \predict_PC_reg[12][22] ( .D(target_PC_i[22]), .CK(net3686), .RN(
n100), .Q(\predict_PC[12][22] ) );
DFFR_X1 \predict_PC_reg[12][21] ( .D(target_PC_i[21]), .CK(net3686), .RN(
n79), .Q(\predict_PC[12][21] ) );
DFFR_X1 \predict_PC_reg[12][20] ( .D(target_PC_i[20]), .CK(net3686), .RN(
n79), .Q(\predict_PC[12][20] ) );
DFFR_X1 \predict_PC_reg[12][19] ( .D(target_PC_i[19]), .CK(net3686), .RN(
n78), .Q(\predict_PC[12][19] ) );
DFFR_X1 \predict_PC_reg[12][18] ( .D(target_PC_i[18]), .CK(net3686), .RN(
n78), .Q(\predict_PC[12][18] ) );
DFFR_X1 \predict_PC_reg[12][17] ( .D(target_PC_i[17]), .CK(net3686), .RN(
n79), .Q(\predict_PC[12][17] ) );
DFFR_X1 \predict_PC_reg[12][16] ( .D(target_PC_i[16]), .CK(net3686), .RN(
n77), .Q(\predict_PC[12][16] ) );
DFFR_X1 \predict_PC_reg[12][15] ( .D(target_PC_i[15]), .CK(net3686), .RN(
n77), .Q(\predict_PC[12][15] ) );
DFFR_X1 \predict_PC_reg[12][14] ( .D(target_PC_i[14]), .CK(net3686), .RN(
n77), .Q(\predict_PC[12][14] ) );
DFFR_X1 \predict_PC_reg[12][13] ( .D(target_PC_i[13]), .CK(net3686), .RN(
n78), .Q(\predict_PC[12][13] ) );
DFFR_X1 \predict_PC_reg[12][12] ( .D(target_PC_i[12]), .CK(net3686), .RN(
n79), .Q(\predict_PC[12][12] ) );
DFFR_X1 \predict_PC_reg[12][11] ( .D(target_PC_i[11]), .CK(net3686), .RN(
n100), .Q(\predict_PC[12][11] ) );
DFFR_X1 \predict_PC_reg[12][10] ( .D(target_PC_i[10]), .CK(net3686), .RN(
n99), .Q(\predict_PC[12][10] ) );
DFFR_X1 \predict_PC_reg[12][9] ( .D(target_PC_i[9]), .CK(net3686), .RN(n93),
.Q(\predict_PC[12][9] ) );
DFFR_X1 \predict_PC_reg[12][8] ( .D(target_PC_i[8]), .CK(net3686), .RN(n93),
.Q(\predict_PC[12][8] ) );
DFFR_X1 \predict_PC_reg[12][7] ( .D(target_PC_i[7]), .CK(net3686), .RN(n93),
.Q(\predict_PC[12][7] ) );
DFFR_X1 \predict_PC_reg[12][6] ( .D(target_PC_i[6]), .CK(net3686), .RN(n93),
.Q(\predict_PC[12][6] ) );
DFFR_X1 \predict_PC_reg[12][5] ( .D(target_PC_i[5]), .CK(net3686), .RN(n93),
.Q(\predict_PC[12][5] ) );
DFFR_X1 \predict_PC_reg[12][4] ( .D(target_PC_i[4]), .CK(net3686), .RN(n93),
.Q(\predict_PC[12][4] ) );
DFFR_X1 \predict_PC_reg[12][3] ( .D(target_PC_i[3]), .CK(net3686), .RN(n94),
.Q(\predict_PC[12][3] ) );
DFFR_X1 \predict_PC_reg[12][2] ( .D(target_PC_i[2]), .CK(net3686), .RN(n94),
.Q(\predict_PC[12][2] ) );
DFFR_X1 \predict_PC_reg[12][1] ( .D(target_PC_i[1]), .CK(net3686), .RN(n94),
.Q(\predict_PC[12][1] ) );
DFFR_X1 \predict_PC_reg[12][0] ( .D(target_PC_i[0]), .CK(net3686), .RN(n94),
.Q(\predict_PC[12][0] ) );
DFFR_X1 \predict_PC_reg[13][31] ( .D(n59), .CK(net3691), .RN(n94), .Q(
\predict_PC[13][31] ) );
DFFR_X1 \predict_PC_reg[13][30] ( .D(n38), .CK(net3691), .RN(n94), .Q(
\predict_PC[13][30] ) );
DFFR_X1 \predict_PC_reg[13][29] ( .D(n58), .CK(net3691), .RN(n94), .Q(
\predict_PC[13][29] ) );
DFFR_X1 \predict_PC_reg[13][28] ( .D(n39), .CK(net3691), .RN(n94), .Q(
\predict_PC[13][28] ) );
DFFR_X1 \predict_PC_reg[13][27] ( .D(n60), .CK(net3691), .RN(n94), .Q(
\predict_PC[13][27] ) );
DFFR_X1 \predict_PC_reg[13][26] ( .D(n37), .CK(net3691), .RN(n94), .Q(
\predict_PC[13][26] ) );
DFFR_X1 \predict_PC_reg[13][25] ( .D(n35), .CK(net3691), .RN(n94), .Q(
\predict_PC[13][25] ) );
DFFR_X1 \predict_PC_reg[13][24] ( .D(n36), .CK(net3691), .RN(n94), .Q(
\predict_PC[13][24] ) );
DFFR_X1 \predict_PC_reg[13][23] ( .D(target_PC_i[23]), .CK(net3691), .RN(
n90), .Q(\predict_PC[13][23] ) );
DFFR_X1 \predict_PC_reg[13][22] ( .D(target_PC_i[22]), .CK(net3691), .RN(
n92), .Q(\predict_PC[13][22] ) );
DFFR_X1 \predict_PC_reg[13][21] ( .D(target_PC_i[21]), .CK(net3691), .RN(
n94), .Q(\predict_PC[13][21] ) );
DFFR_X1 \predict_PC_reg[13][20] ( .D(target_PC_i[20]), .CK(net3691), .RN(
n100), .Q(\predict_PC[13][20] ) );
DFFR_X1 \predict_PC_reg[13][19] ( .D(target_PC_i[19]), .CK(net3691), .RN(
n99), .Q(\predict_PC[13][19] ) );
DFFR_X1 \predict_PC_reg[13][18] ( .D(target_PC_i[18]), .CK(net3691), .RN(
n96), .Q(\predict_PC[13][18] ) );
DFFR_X1 \predict_PC_reg[13][17] ( .D(target_PC_i[17]), .CK(net3691), .RN(
n84), .Q(\predict_PC[13][17] ) );
DFFR_X1 \predict_PC_reg[13][16] ( .D(target_PC_i[16]), .CK(net3691), .RN(
n84), .Q(\predict_PC[13][16] ) );
DFFR_X1 \predict_PC_reg[13][15] ( .D(target_PC_i[15]), .CK(net3691), .RN(
n95), .Q(\predict_PC[13][15] ) );
DFFR_X1 \predict_PC_reg[13][14] ( .D(target_PC_i[14]), .CK(net3691), .RN(
n98), .Q(\predict_PC[13][14] ) );
DFFR_X1 \predict_PC_reg[13][13] ( .D(target_PC_i[13]), .CK(net3691), .RN(
n97), .Q(\predict_PC[13][13] ) );
DFFR_X1 \predict_PC_reg[13][12] ( .D(target_PC_i[12]), .CK(net3691), .RN(
n86), .Q(\predict_PC[13][12] ) );
DFFR_X1 \predict_PC_reg[13][11] ( .D(target_PC_i[11]), .CK(net3691), .RN(
n95), .Q(\predict_PC[13][11] ) );
DFFR_X1 \predict_PC_reg[13][10] ( .D(target_PC_i[10]), .CK(net3691), .RN(
n95), .Q(\predict_PC[13][10] ) );
DFFR_X1 \predict_PC_reg[13][9] ( .D(target_PC_i[9]), .CK(net3691), .RN(n95),
.Q(\predict_PC[13][9] ) );
DFFR_X1 \predict_PC_reg[13][8] ( .D(target_PC_i[8]), .CK(net3691), .RN(n95),
.Q(\predict_PC[13][8] ) );
DFFR_X1 \predict_PC_reg[13][7] ( .D(target_PC_i[7]), .CK(net3691), .RN(n95),
.Q(\predict_PC[13][7] ) );
DFFR_X1 \predict_PC_reg[13][6] ( .D(target_PC_i[6]), .CK(net3691), .RN(n95),
.Q(\predict_PC[13][6] ) );
DFFR_X1 \predict_PC_reg[13][5] ( .D(target_PC_i[5]), .CK(net3691), .RN(n95),
.Q(\predict_PC[13][5] ) );
DFFR_X1 \predict_PC_reg[13][4] ( .D(target_PC_i[4]), .CK(net3691), .RN(n95),
.Q(\predict_PC[13][4] ) );
DFFR_X1 \predict_PC_reg[13][3] ( .D(target_PC_i[3]), .CK(net3691), .RN(n95),
.Q(\predict_PC[13][3] ) );
DFFR_X1 \predict_PC_reg[13][2] ( .D(target_PC_i[2]), .CK(net3691), .RN(n95),
.Q(\predict_PC[13][2] ) );
DFFR_X1 \predict_PC_reg[13][1] ( .D(target_PC_i[1]), .CK(net3691), .RN(n95),
.Q(\predict_PC[13][1] ) );
DFFR_X1 \predict_PC_reg[13][0] ( .D(target_PC_i[0]), .CK(net3691), .RN(n95),
.Q(\predict_PC[13][0] ) );
DFFR_X1 \predict_PC_reg[14][31] ( .D(n59), .CK(net3696), .RN(n95), .Q(
\predict_PC[14][31] ) );
DFFR_X1 \predict_PC_reg[14][30] ( .D(n38), .CK(net3696), .RN(n98), .Q(
\predict_PC[14][30] ) );
DFFR_X1 \predict_PC_reg[14][29] ( .D(n58), .CK(net3696), .RN(n91), .Q(
\predict_PC[14][29] ) );
DFFR_X1 \predict_PC_reg[14][28] ( .D(n39), .CK(net3696), .RN(n89), .Q(
\predict_PC[14][28] ) );
DFFR_X1 \predict_PC_reg[14][27] ( .D(n60), .CK(net3696), .RN(n88), .Q(
\predict_PC[14][27] ) );
DFFR_X1 \predict_PC_reg[14][26] ( .D(n37), .CK(net3696), .RN(n93), .Q(
\predict_PC[14][26] ) );
DFFR_X1 \predict_PC_reg[14][25] ( .D(n35), .CK(net3696), .RN(n92), .Q(
\predict_PC[14][25] ) );
DFFR_X1 \predict_PC_reg[14][24] ( .D(n36), .CK(net3696), .RN(n94), .Q(
\predict_PC[14][24] ) );
DFFR_X1 \predict_PC_reg[14][23] ( .D(target_PC_i[23]), .CK(net3696), .RN(
n100), .Q(\predict_PC[14][23] ) );
DFFR_X1 \predict_PC_reg[14][22] ( .D(target_PC_i[22]), .CK(net3696), .RN(
n99), .Q(\predict_PC[14][22] ) );
DFFR_X1 \predict_PC_reg[14][21] ( .D(target_PC_i[21]), .CK(net3696), .RN(
n96), .Q(\predict_PC[14][21] ) );
DFFR_X1 \predict_PC_reg[14][20] ( .D(target_PC_i[20]), .CK(net3696), .RN(
n91), .Q(\predict_PC[14][20] ) );
DFFR_X1 \predict_PC_reg[14][19] ( .D(target_PC_i[19]), .CK(net3696), .RN(
n90), .Q(\predict_PC[14][19] ) );
DFFR_X1 \predict_PC_reg[14][18] ( .D(target_PC_i[18]), .CK(net3696), .RN(
n90), .Q(\predict_PC[14][18] ) );
DFFR_X1 \predict_PC_reg[14][17] ( .D(target_PC_i[17]), .CK(net3696), .RN(
n89), .Q(\predict_PC[14][17] ) );
DFFR_X1 \predict_PC_reg[14][16] ( .D(target_PC_i[16]), .CK(net3696), .RN(
n88), .Q(\predict_PC[14][16] ) );
DFFR_X1 \predict_PC_reg[14][15] ( .D(target_PC_i[15]), .CK(net3696), .RN(
n93), .Q(\predict_PC[14][15] ) );
DFFR_X1 \predict_PC_reg[14][14] ( .D(target_PC_i[14]), .CK(net3696), .RN(
n92), .Q(\predict_PC[14][14] ) );
DFFR_X1 \predict_PC_reg[14][13] ( .D(target_PC_i[13]), .CK(net3696), .RN(
n94), .Q(\predict_PC[14][13] ) );
DFFR_X1 \predict_PC_reg[14][12] ( .D(target_PC_i[12]), .CK(net3696), .RN(
n100), .Q(\predict_PC[14][12] ) );
DFFR_X1 \predict_PC_reg[14][11] ( .D(target_PC_i[11]), .CK(net3696), .RN(
n99), .Q(\predict_PC[14][11] ) );
DFFR_X1 \predict_PC_reg[14][10] ( .D(target_PC_i[10]), .CK(net3696), .RN(
n96), .Q(\predict_PC[14][10] ) );
DFFR_X1 \predict_PC_reg[14][9] ( .D(target_PC_i[9]), .CK(net3696), .RN(n95),
.Q(\predict_PC[14][9] ) );
DFFR_X1 \predict_PC_reg[14][8] ( .D(target_PC_i[8]), .CK(net3696), .RN(n98),
.Q(\predict_PC[14][8] ) );
DFFR_X1 \predict_PC_reg[14][7] ( .D(target_PC_i[7]), .CK(net3696), .RN(n93),
.Q(\predict_PC[14][7] ) );
DFFR_X1 \predict_PC_reg[14][6] ( .D(target_PC_i[6]), .CK(net3696), .RN(n94),
.Q(\predict_PC[14][6] ) );
DFFR_X1 \predict_PC_reg[14][5] ( .D(target_PC_i[5]), .CK(net3696), .RN(n100), .Q(\predict_PC[14][5] ) );
DFFR_X1 \predict_PC_reg[14][4] ( .D(target_PC_i[4]), .CK(net3696), .RN(n96),
.Q(\predict_PC[14][4] ) );
DFFR_X1 \predict_PC_reg[14][3] ( .D(target_PC_i[3]), .CK(net3696), .RN(n91),
.Q(\predict_PC[14][3] ) );
DFFR_X1 \predict_PC_reg[14][2] ( .D(target_PC_i[2]), .CK(net3696), .RN(n80),
.Q(\predict_PC[14][2] ) );
DFFR_X1 \predict_PC_reg[14][1] ( .D(target_PC_i[1]), .CK(net3696), .RN(n80),
.Q(\predict_PC[14][1] ) );
DFFR_X1 \predict_PC_reg[14][0] ( .D(target_PC_i[0]), .CK(net3696), .RN(n95),
.Q(\predict_PC[14][0] ) );
DFFR_X1 \predict_PC_reg[15][31] ( .D(n59), .CK(net3701), .RN(n91), .Q(
\predict_PC[15][31] ) );
DFFR_X1 \predict_PC_reg[15][30] ( .D(n38), .CK(net3701), .RN(n98), .Q(
\predict_PC[15][30] ) );
DFFR_X1 \predict_PC_reg[15][29] ( .D(n58), .CK(net3701), .RN(n97), .Q(
\predict_PC[15][29] ) );
DFFR_X1 \predict_PC_reg[15][28] ( .D(n39), .CK(net3701), .RN(n94), .Q(
\predict_PC[15][28] ) );
DFFR_X1 \predict_PC_reg[15][27] ( .D(n60), .CK(net3701), .RN(n91), .Q(
\predict_PC[15][27] ) );
DFFR_X1 \predict_PC_reg[15][26] ( .D(n37), .CK(net3701), .RN(n100), .Q(
\predict_PC[15][26] ) );
DFFR_X1 \predict_PC_reg[15][25] ( .D(n35), .CK(net3701), .RN(n99), .Q(
\predict_PC[15][25] ) );
DFFR_X1 \predict_PC_reg[15][24] ( .D(n36), .CK(net3701), .RN(n89), .Q(
\predict_PC[15][24] ) );
DFFR_X1 \predict_PC_reg[15][23] ( .D(target_PC_i[23]), .CK(net3701), .RN(
n97), .Q(\predict_PC[15][23] ) );
DFFR_X1 \predict_PC_reg[15][22] ( .D(target_PC_i[22]), .CK(net3701), .RN(
n88), .Q(\predict_PC[15][22] ) );
DFFR_X1 \predict_PC_reg[15][21] ( .D(target_PC_i[21]), .CK(net3701), .RN(
n100), .Q(\predict_PC[15][21] ) );
DFFR_X1 \predict_PC_reg[15][20] ( .D(target_PC_i[20]), .CK(net3701), .RN(
n88), .Q(\predict_PC[15][20] ) );
DFFR_X1 \predict_PC_reg[15][19] ( .D(target_PC_i[19]), .CK(net3701), .RN(
n96), .Q(\predict_PC[15][19] ) );
DFFR_X1 \predict_PC_reg[15][18] ( .D(target_PC_i[18]), .CK(net3701), .RN(
n93), .Q(\predict_PC[15][18] ) );
DFFR_X1 \predict_PC_reg[15][17] ( .D(target_PC_i[17]), .CK(net3701), .RN(
n96), .Q(\predict_PC[15][17] ) );
DFFR_X1 \predict_PC_reg[15][16] ( .D(target_PC_i[16]), .CK(net3701), .RN(
n91), .Q(\predict_PC[15][16] ) );
DFFR_X1 \predict_PC_reg[15][15] ( .D(target_PC_i[15]), .CK(net3701), .RN(
n90), .Q(\predict_PC[15][15] ) );
DFFR_X1 \predict_PC_reg[15][14] ( .D(target_PC_i[14]), .CK(net3701), .RN(
n89), .Q(\predict_PC[15][14] ) );
DFFR_X1 \predict_PC_reg[15][13] ( .D(target_PC_i[13]), .CK(net3701), .RN(
n88), .Q(\predict_PC[15][13] ) );
DFFR_X1 \predict_PC_reg[15][12] ( .D(target_PC_i[12]), .CK(net3701), .RN(
n93), .Q(\predict_PC[15][12] ) );
DFFR_X1 \predict_PC_reg[15][11] ( .D(target_PC_i[11]), .CK(net3701), .RN(
n92), .Q(\predict_PC[15][11] ) );
DFFR_X1 \predict_PC_reg[15][10] ( .D(target_PC_i[10]), .CK(net3701), .RN(
n96), .Q(\predict_PC[15][10] ) );
DFFR_X1 \predict_PC_reg[15][9] ( .D(target_PC_i[9]), .CK(net3701), .RN(n98),
.Q(\predict_PC[15][9] ) );
DFFR_X1 \predict_PC_reg[15][8] ( .D(target_PC_i[8]), .CK(net3701), .RN(n85),
.Q(\predict_PC[15][8] ) );
DFFR_X1 \predict_PC_reg[15][7] ( .D(target_PC_i[7]), .CK(net3701), .RN(n85),
.Q(\predict_PC[15][7] ) );
DFFR_X1 \predict_PC_reg[15][6] ( .D(target_PC_i[6]), .CK(net3701), .RN(n95),
.Q(\predict_PC[15][6] ) );
DFFR_X1 \predict_PC_reg[15][5] ( .D(target_PC_i[5]), .CK(net3701), .RN(n96),
.Q(\predict_PC[15][5] ) );
DFFR_X1 \predict_PC_reg[15][4] ( .D(target_PC_i[4]), .CK(net3701), .RN(n96),
.Q(\predict_PC[15][4] ) );
DFFR_X1 \predict_PC_reg[15][3] ( .D(target_PC_i[3]), .CK(net3701), .RN(n96),
.Q(\predict_PC[15][3] ) );
DFFR_X1 \predict_PC_reg[15][2] ( .D(target_PC_i[2]), .CK(net3701), .RN(n96),
.Q(\predict_PC[15][2] ) );
DFFR_X1 \predict_PC_reg[15][1] ( .D(target_PC_i[1]), .CK(net3701), .RN(n96),
.Q(\predict_PC[15][1] ) );
DFFR_X1 \predict_PC_reg[15][0] ( .D(target_PC_i[0]), .CK(net3701), .RN(n96),
.Q(\predict_PC[15][0] ) );
predictor_2_0 pred_x_0 ( .clock(clock), .reset(reset), .enable(
write_enable[0]), .taken_i(was_taken_i), .prediction_o(taken[0]) );
predictor_2_15 pred_x_1 ( .clock(clock), .reset(reset), .enable(
write_enable[1]), .taken_i(was_taken_i), .prediction_o(taken[1]) );
predictor_2_14 pred_x_2 ( .clock(clock), .reset(reset), .enable(
write_enable[2]), .taken_i(was_taken_i), .prediction_o(taken[2]) );
predictor_2_13 pred_x_3 ( .clock(clock), .reset(reset), .enable(
write_enable[3]), .taken_i(was_taken_i), .prediction_o(taken[3]) );
predictor_2_12 pred_x_4 ( .clock(clock), .reset(reset), .enable(
write_enable[4]), .taken_i(was_taken_i), .prediction_o(taken[4]) );
predictor_2_11 pred_x_5 ( .clock(clock), .reset(reset), .enable(
write_enable[5]), .taken_i(was_taken_i), .prediction_o(taken[5]) );
predictor_2_10 pred_x_6 ( .clock(clock), .reset(reset), .enable(
write_enable[6]), .taken_i(was_taken_i), .prediction_o(taken[6]) );
predictor_2_9 pred_x_7 ( .clock(clock), .reset(reset), .enable(
write_enable[7]), .taken_i(was_taken_i), .prediction_o(taken[7]) );
predictor_2_8 pred_x_8 ( .clock(clock), .reset(reset), .enable(
write_enable[8]), .taken_i(was_taken_i), .prediction_o(taken[8]) );
predictor_2_7 pred_x_9 ( .clock(clock), .reset(reset), .enable(
write_enable[9]), .taken_i(was_taken_i), .prediction_o(taken[9]) );
predictor_2_6 pred_x_10 ( .clock(clock), .reset(reset), .enable(
write_enable[10]), .taken_i(was_taken_i), .prediction_o(taken[10]) );
predictor_2_5 pred_x_11 ( .clock(clock), .reset(reset), .enable(
write_enable[11]), .taken_i(was_taken_i), .prediction_o(taken[11]) );
predictor_2_4 pred_x_12 ( .clock(clock), .reset(reset), .enable(
write_enable[12]), .taken_i(was_taken_i), .prediction_o(taken[12]) );
predictor_2_3 pred_x_13 ( .clock(clock), .reset(reset), .enable(
write_enable[13]), .taken_i(was_taken_i), .prediction_o(taken[13]) );
predictor_2_2 pred_x_14 ( .clock(clock), .reset(reset), .enable(
write_enable[14]), .taken_i(was_taken_i), .prediction_o(taken[14]) );
predictor_2_1 pred_x_15 ( .clock(clock), .reset(reset), .enable(
write_enable[15]), .taken_i(was_taken_i), .prediction_o(taken[15]) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_0 clk_gate_last_TAG_reg ( .CLK(
clock), .EN(N567), .ENCLK(net3621) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_16 \clk_gate_predict_PC_reg[0] (
.CLK(clock), .EN(N566), .ENCLK(net3626) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_15 \clk_gate_predict_PC_reg[1] (
.CLK(clock), .EN(N534), .ENCLK(net3631) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_14 \clk_gate_predict_PC_reg[2] (
.CLK(clock), .EN(N502), .ENCLK(net3636) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_13 \clk_gate_predict_PC_reg[3] (
.CLK(clock), .EN(N470), .ENCLK(net3641) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_12 \clk_gate_predict_PC_reg[4] (
.CLK(clock), .EN(N438), .ENCLK(net3646) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_11 \clk_gate_predict_PC_reg[5] (
.CLK(clock), .EN(N406), .ENCLK(net3651) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_10 \clk_gate_predict_PC_reg[6] (
.CLK(clock), .EN(N374), .ENCLK(net3656) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_9 \clk_gate_predict_PC_reg[7] (
.CLK(clock), .EN(N342), .ENCLK(net3661) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_8 \clk_gate_predict_PC_reg[8] (
.CLK(clock), .EN(N310), .ENCLK(net3666) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_7 \clk_gate_predict_PC_reg[9] (
.CLK(clock), .EN(N278), .ENCLK(net3671) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_6 \clk_gate_predict_PC_reg[10] (
.CLK(clock), .EN(N246), .ENCLK(net3676) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_5 \clk_gate_predict_PC_reg[11] (
.CLK(clock), .EN(N214), .ENCLK(net3681) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_4 \clk_gate_predict_PC_reg[12] (
.CLK(clock), .EN(N182), .ENCLK(net3686) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_3 \clk_gate_predict_PC_reg[13] (
.CLK(clock), .EN(N150), .ENCLK(net3691) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_2 \clk_gate_predict_PC_reg[14] (
.CLK(clock), .EN(N118), .ENCLK(net3696) );
SNPS_CLOCK_GATE_HIGH_btb_N_LINES4_SIZE32_1 \clk_gate_predict_PC_reg[15] (
.CLK(clock), .EN(N86), .ENCLK(net3701) );
NAND2_X1 U391 ( .A1(TAG_i[1]), .A2(n903), .ZN(n895) );
NAND2_X1 U390 ( .A1(TAG_i[3]), .A2(n973), .ZN(n902) );
AOI22_X1 U386 ( .A1(n557), .A2(taken[10]), .B1(n558), .B2(taken[11]), .ZN(
n897) );
AOI22_X1 U381 ( .A1(n559), .A2(taken[8]), .B1(n69), .B2(taken[9]), .ZN(n898)
);
NAND2_X1 U380 ( .A1(TAG_i[2]), .A2(TAG_i[3]), .ZN(n901) );
AOI22_X1 U377 ( .A1(n553), .A2(taken[14]), .B1(n554), .B2(taken[15]), .ZN(
n899) );
AOI22_X1 U374 ( .A1(n555), .A2(taken[12]), .B1(n556), .B2(taken[13]), .ZN(
n900) );
AOI22_X1 U369 ( .A1(n64), .A2(taken[2]), .B1(n63), .B2(taken[3]), .ZN(n887)
);
AOI22_X1 U366 ( .A1(n62), .A2(taken[0]), .B1(n61), .B2(taken[1]), .ZN(n888)
);
NAND2_X1 U365 ( .A1(TAG_i[2]), .A2(n972), .ZN(n892) );
AOI22_X1 U362 ( .A1(n68), .A2(taken[6]), .B1(n67), .B2(taken[7]), .ZN(n889)
);
AOI22_X1 U359 ( .A1(n66), .A2(taken[4]), .B1(n65), .B2(taken[5]), .ZN(n890)
);
OAI22_X1 U430 ( .A1(target_PC_i[17]), .A2(n511), .B1(target_PC_i[16]), .B2(
n513), .ZN(n940) );
AOI221_X1 U429 ( .B1(target_PC_i[17]), .B2(n511), .C1(n513), .C2(
target_PC_i[16]), .A(n940), .ZN(n937) );
OAI22_X1 U428 ( .A1(target_PC_i[11]), .A2(n523), .B1(target_PC_i[10]), .B2(
n525), .ZN(n939) );
AOI22_X1 U188 ( .A1(n62), .A2(\predict_PC[0][23] ), .B1(n61), .B2(
\predict_PC[1][23] ), .ZN(n729) );
AOI22_X1 U187 ( .A1(n64), .A2(\predict_PC[2][23] ), .B1(n63), .B2(
\predict_PC[3][23] ), .ZN(n730) );
AOI22_X1 U186 ( .A1(n66), .A2(\predict_PC[4][23] ), .B1(n65), .B2(
\predict_PC[5][23] ), .ZN(n731) );
AOI22_X1 U185 ( .A1(n68), .A2(\predict_PC[6][23] ), .B1(n67), .B2(
\predict_PC[7][23] ), .ZN(n732) );
NAND4_X1 U184 ( .A1(n729), .A2(n730), .A3(n731), .A4(n732), .ZN(n723) );
AOI22_X1 U183 ( .A1(n70), .A2(\predict_PC[8][23] ), .B1(n69), .B2(
\predict_PC[9][23] ), .ZN(n725) );
AOI22_X1 U182 ( .A1(n72), .A2(\predict_PC[10][23] ), .B1(n71), .B2(
\predict_PC[11][23] ), .ZN(n726) );
AOI22_X1 U181 ( .A1(n74), .A2(\predict_PC[12][23] ), .B1(n73), .B2(
\predict_PC[13][23] ), .ZN(n727) );
AOI22_X1 U180 ( .A1(n76), .A2(\predict_PC[14][23] ), .B1(n75), .B2(
\predict_PC[15][23] ), .ZN(n728) );
NAND4_X1 U179 ( .A1(n725), .A2(n726), .A3(n727), .A4(n728), .ZN(n724) );
AOI22_X1 U133 ( .A1(n62), .A2(\predict_PC[0][28] ), .B1(n61), .B2(
\predict_PC[1][28] ), .ZN(n679) );
AOI22_X1 U132 ( .A1(n64), .A2(\predict_PC[2][28] ), .B1(n63), .B2(
\predict_PC[3][28] ), .ZN(n680) );
AOI22_X1 U131 ( .A1(n66), .A2(\predict_PC[4][28] ), .B1(n65), .B2(
\predict_PC[5][28] ), .ZN(n681) );
AOI22_X1 U130 ( .A1(n68), .A2(\predict_PC[6][28] ), .B1(n67), .B2(
\predict_PC[7][28] ), .ZN(n682) );
NAND4_X1 U129 ( .A1(n679), .A2(n680), .A3(n681), .A4(n682), .ZN(n673) );
AOI22_X1 U128 ( .A1(n70), .A2(\predict_PC[8][28] ), .B1(n69), .B2(
\predict_PC[9][28] ), .ZN(n675) );
AOI22_X1 U127 ( .A1(n72), .A2(\predict_PC[10][28] ), .B1(n71), .B2(
\predict_PC[11][28] ), .ZN(n676) );
AOI22_X1 U126 ( .A1(n74), .A2(\predict_PC[12][28] ), .B1(n73), .B2(
\predict_PC[13][28] ), .ZN(n677) );
AOI22_X1 U125 ( .A1(n76), .A2(\predict_PC[14][28] ), .B1(n75), .B2(
\predict_PC[15][28] ), .ZN(n678) );
NAND4_X1 U124 ( .A1(n675), .A2(n676), .A3(n677), .A4(n678), .ZN(n674) );
AOI22_X1 U111 ( .A1(n62), .A2(\predict_PC[0][2] ), .B1(n61), .B2(
\predict_PC[1][2] ), .ZN(n659) );
AOI22_X1 U110 ( .A1(n64), .A2(\predict_PC[2][2] ), .B1(n63), .B2(
\predict_PC[3][2] ), .ZN(n660) );
AOI22_X1 U109 ( .A1(n66), .A2(\predict_PC[4][2] ), .B1(n65), .B2(
\predict_PC[5][2] ), .ZN(n661) );
AOI22_X1 U108 ( .A1(n68), .A2(\predict_PC[6][2] ), .B1(n67), .B2(
\predict_PC[7][2] ), .ZN(n662) );
NAND4_X1 U107 ( .A1(n659), .A2(n660), .A3(n661), .A4(n662), .ZN(n653) );
AOI22_X1 U106 ( .A1(n70), .A2(\predict_PC[8][2] ), .B1(n69), .B2(
\predict_PC[9][2] ), .ZN(n655) );
AOI22_X1 U105 ( .A1(n72), .A2(\predict_PC[10][2] ), .B1(n71), .B2(
\predict_PC[11][2] ), .ZN(n656) );
AOI22_X1 U104 ( .A1(n74), .A2(\predict_PC[12][2] ), .B1(n73), .B2(
\predict_PC[13][2] ), .ZN(n657) );
AOI22_X1 U103 ( .A1(n76), .A2(\predict_PC[14][2] ), .B1(n75), .B2(
\predict_PC[15][2] ), .ZN(n658) );
NAND4_X1 U102 ( .A1(n655), .A2(n656), .A3(n657), .A4(n658), .ZN(n654) );
AOI22_X1 U45 ( .A1(n62), .A2(\predict_PC[0][6] ), .B1(n61), .B2(
\predict_PC[1][6] ), .ZN(n599) );
AOI22_X1 U44 ( .A1(n64), .A2(\predict_PC[2][6] ), .B1(n63), .B2(
\predict_PC[3][6] ), .ZN(n600) );
AOI22_X1 U43 ( .A1(n66), .A2(\predict_PC[4][6] ), .B1(n65), .B2(
\predict_PC[5][6] ), .ZN(n601) );
AOI22_X1 U42 ( .A1(n68), .A2(\predict_PC[6][6] ), .B1(n67), .B2(
\predict_PC[7][6] ), .ZN(n602) );
NAND4_X1 U41 ( .A1(n599), .A2(n600), .A3(n601), .A4(n602), .ZN(n593) );
AOI22_X1 U40 ( .A1(n70), .A2(\predict_PC[8][6] ), .B1(n69), .B2(
\predict_PC[9][6] ), .ZN(n595) );
AOI22_X1 U39 ( .A1(n72), .A2(\predict_PC[10][6] ), .B1(n71), .B2(
\predict_PC[11][6] ), .ZN(n596) );
AOI22_X1 U38 ( .A1(n74), .A2(\predict_PC[12][6] ), .B1(n73), .B2(
\predict_PC[13][6] ), .ZN(n597) );
AOI22_X1 U37 ( .A1(n76), .A2(\predict_PC[14][6] ), .B1(n75), .B2(
\predict_PC[15][6] ), .ZN(n598) );
NAND4_X1 U36 ( .A1(n595), .A2(n596), .A3(n597), .A4(n598), .ZN(n594) );
AOI22_X1 U67 ( .A1(n62), .A2(\predict_PC[0][4] ), .B1(n61), .B2(
\predict_PC[1][4] ), .ZN(n619) );
AOI22_X1 U66 ( .A1(n64), .A2(\predict_PC[2][4] ), .B1(n63), .B2(
\predict_PC[3][4] ), .ZN(n620) );
AOI22_X1 U65 ( .A1(n66), .A2(\predict_PC[4][4] ), .B1(n65), .B2(
\predict_PC[5][4] ), .ZN(n621) );
AOI22_X1 U64 ( .A1(n68), .A2(\predict_PC[6][4] ), .B1(n67), .B2(
\predict_PC[7][4] ), .ZN(n622) );
NAND4_X1 U63 ( .A1(n619), .A2(n620), .A3(n621), .A4(n622), .ZN(n613) );
AOI22_X1 U62 ( .A1(n70), .A2(\predict_PC[8][4] ), .B1(n69), .B2(
\predict_PC[9][4] ), .ZN(n615) );
AOI22_X1 U61 ( .A1(n72), .A2(\predict_PC[10][4] ), .B1(n71), .B2(
\predict_PC[11][4] ), .ZN(n616) );
AOI22_X1 U60 ( .A1(n74), .A2(\predict_PC[12][4] ), .B1(n73), .B2(
\predict_PC[13][4] ), .ZN(n617) );
AOI22_X1 U59 ( .A1(n76), .A2(\predict_PC[14][4] ), .B1(n75), .B2(
\predict_PC[15][4] ), .ZN(n618) );
NAND4_X1 U58 ( .A1(n615), .A2(n616), .A3(n617), .A4(n618), .ZN(n614) );
AOI22_X1 U56 ( .A1(n62), .A2(\predict_PC[0][5] ), .B1(n61), .B2(
\predict_PC[1][5] ), .ZN(n609) );
AOI22_X1 U55 ( .A1(n64), .A2(\predict_PC[2][5] ), .B1(n63), .B2(
\predict_PC[3][5] ), .ZN(n610) );
AOI22_X1 U54 ( .A1(n66), .A2(\predict_PC[4][5] ), .B1(n65), .B2(
\predict_PC[5][5] ), .ZN(n611) );
AOI22_X1 U53 ( .A1(n68), .A2(\predict_PC[6][5] ), .B1(n67), .B2(
\predict_PC[7][5] ), .ZN(n612) );
NAND4_X1 U52 ( .A1(n609), .A2(n610), .A3(n611), .A4(n612), .ZN(n603) );
AOI22_X1 U51 ( .A1(n70), .A2(\predict_PC[8][5] ), .B1(n69), .B2(
\predict_PC[9][5] ), .ZN(n605) );
AOI22_X1 U50 ( .A1(n72), .A2(\predict_PC[10][5] ), .B1(n71), .B2(
\predict_PC[11][5] ), .ZN(n606) );
AOI22_X1 U49 ( .A1(n74), .A2(\predict_PC[12][5] ), .B1(n73), .B2(
\predict_PC[13][5] ), .ZN(n607) );
AOI22_X1 U48 ( .A1(n76), .A2(\predict_PC[14][5] ), .B1(n75), .B2(
\predict_PC[15][5] ), .ZN(n608) );
NAND4_X1 U47 ( .A1(n605), .A2(n606), .A3(n607), .A4(n608), .ZN(n604) );
AOI22_X1 U12 ( .A1(n62), .A2(\predict_PC[0][9] ), .B1(n572), .B2(
\predict_PC[1][9] ), .ZN(n561) );
AOI22_X1 U11 ( .A1(n64), .A2(\predict_PC[2][9] ), .B1(n570), .B2(
\predict_PC[3][9] ), .ZN(n562) );
AOI22_X1 U10 ( .A1(n66), .A2(\predict_PC[4][9] ), .B1(n568), .B2(
\predict_PC[5][9] ), .ZN(n563) );
AOI22_X1 U9 ( .A1(n68), .A2(\predict_PC[6][9] ), .B1(n566), .B2(
\predict_PC[7][9] ), .ZN(n564) );
NAND4_X1 U8 ( .A1(n561), .A2(n562), .A3(n563), .A4(n564), .ZN(n547) );
AOI22_X1 U7 ( .A1(n70), .A2(\predict_PC[8][9] ), .B1(n560), .B2(
\predict_PC[9][9] ), .ZN(n549) );
AOI22_X1 U6 ( .A1(n72), .A2(\predict_PC[10][9] ), .B1(n71), .B2(
\predict_PC[11][9] ), .ZN(n550) );
AOI22_X1 U5 ( .A1(n74), .A2(\predict_PC[12][9] ), .B1(n73), .B2(
\predict_PC[13][9] ), .ZN(n551) );
AOI22_X1 U4 ( .A1(n76), .A2(\predict_PC[14][9] ), .B1(n75), .B2(
\predict_PC[15][9] ), .ZN(n552) );
NAND4_X1 U3 ( .A1(n549), .A2(n550), .A3(n551), .A4(n552), .ZN(n548) );
AOI22_X1 U34 ( .A1(n62), .A2(\predict_PC[0][7] ), .B1(n61), .B2(
\predict_PC[1][7] ), .ZN(n589) );
AOI22_X1 U33 ( .A1(n64), .A2(\predict_PC[2][7] ), .B1(n63), .B2(
\predict_PC[3][7] ), .ZN(n590) );
AOI22_X1 U32 ( .A1(n66), .A2(\predict_PC[4][7] ), .B1(n65), .B2(
\predict_PC[5][7] ), .ZN(n591) );
AOI22_X1 U31 ( .A1(n68), .A2(\predict_PC[6][7] ), .B1(n67), .B2(
\predict_PC[7][7] ), .ZN(n592) );
NAND4_X1 U30 ( .A1(n589), .A2(n590), .A3(n591), .A4(n592), .ZN(n583) );
AOI22_X1 U29 ( .A1(n70), .A2(\predict_PC[8][7] ), .B1(n69), .B2(
\predict_PC[9][7] ), .ZN(n585) );
AOI22_X1 U28 ( .A1(n72), .A2(\predict_PC[10][7] ), .B1(n71), .B2(
\predict_PC[11][7] ), .ZN(n586) );
AOI22_X1 U27 ( .A1(n74), .A2(\predict_PC[12][7] ), .B1(n73), .B2(
\predict_PC[13][7] ), .ZN(n587) );
AOI22_X1 U26 ( .A1(n76), .A2(\predict_PC[14][7] ), .B1(n75), .B2(
\predict_PC[15][7] ), .ZN(n588) );
NAND4_X1 U25 ( .A1(n585), .A2(n586), .A3(n587), .A4(n588), .ZN(n584) );
AOI22_X1 U23 ( .A1(n62), .A2(\predict_PC[0][8] ), .B1(n61), .B2(
\predict_PC[1][8] ), .ZN(n579) );
AOI22_X1 U22 ( .A1(n64), .A2(\predict_PC[2][8] ), .B1(n63), .B2(
\predict_PC[3][8] ), .ZN(n580) );
AOI22_X1 U21 ( .A1(n66), .A2(\predict_PC[4][8] ), .B1(n65), .B2(
\predict_PC[5][8] ), .ZN(n581) );
AOI22_X1 U20 ( .A1(n68), .A2(\predict_PC[6][8] ), .B1(n67), .B2(
\predict_PC[7][8] ), .ZN(n582) );
NAND4_X1 U19 ( .A1(n579), .A2(n580), .A3(n581), .A4(n582), .ZN(n573) );
AOI22_X1 U18 ( .A1(n70), .A2(\predict_PC[8][8] ), .B1(n69), .B2(
\predict_PC[9][8] ), .ZN(n575) );
AOI22_X1 U17 ( .A1(n72), .A2(\predict_PC[10][8] ), .B1(n71), .B2(
\predict_PC[11][8] ), .ZN(n576) );
AOI22_X1 U16 ( .A1(n74), .A2(\predict_PC[12][8] ), .B1(n73), .B2(
\predict_PC[13][8] ), .ZN(n577) );
AOI22_X1 U15 ( .A1(n76), .A2(\predict_PC[14][8] ), .B1(n75), .B2(
\predict_PC[15][8] ), .ZN(n578) );
NAND4_X1 U14 ( .A1(n575), .A2(n576), .A3(n577), .A4(n578), .ZN(n574) );
AOI22_X1 U78 ( .A1(n62), .A2(\predict_PC[0][3] ), .B1(n61), .B2(
\predict_PC[1][3] ), .ZN(n629) );
AOI22_X1 U77 ( .A1(n64), .A2(\predict_PC[2][3] ), .B1(n63), .B2(
\predict_PC[3][3] ), .ZN(n630) );
AOI22_X1 U76 ( .A1(n66), .A2(\predict_PC[4][3] ), .B1(n65), .B2(
\predict_PC[5][3] ), .ZN(n631) );
AOI22_X1 U75 ( .A1(n68), .A2(\predict_PC[6][3] ), .B1(n67), .B2(
\predict_PC[7][3] ), .ZN(n632) );
NAND4_X1 U74 ( .A1(n629), .A2(n630), .A3(n631), .A4(n632), .ZN(n623) );
AOI22_X1 U73 ( .A1(n70), .A2(\predict_PC[8][3] ), .B1(n69), .B2(
\predict_PC[9][3] ), .ZN(n625) );
AOI22_X1 U72 ( .A1(n72), .A2(\predict_PC[10][3] ), .B1(n71), .B2(
\predict_PC[11][3] ), .ZN(n626) );
AOI22_X1 U71 ( .A1(n74), .A2(\predict_PC[12][3] ), .B1(n73), .B2(
\predict_PC[13][3] ), .ZN(n627) );
AOI22_X1 U70 ( .A1(n76), .A2(\predict_PC[14][3] ), .B1(n75), .B2(
\predict_PC[15][3] ), .ZN(n628) );
NAND4_X1 U69 ( .A1(n625), .A2(n626), .A3(n627), .A4(n628), .ZN(n624) );
AOI22_X1 U122 ( .A1(n62), .A2(\predict_PC[0][29] ), .B1(n61), .B2(
\predict_PC[1][29] ), .ZN(n669) );
AOI22_X1 U121 ( .A1(n64), .A2(\predict_PC[2][29] ), .B1(n63), .B2(
\predict_PC[3][29] ), .ZN(n670) );
AOI22_X1 U120 ( .A1(n66), .A2(\predict_PC[4][29] ), .B1(n65), .B2(
\predict_PC[5][29] ), .ZN(n671) );
AOI22_X1 U119 ( .A1(n68), .A2(\predict_PC[6][29] ), .B1(n67), .B2(
\predict_PC[7][29] ), .ZN(n672) );
NAND4_X1 U118 ( .A1(n669), .A2(n670), .A3(n671), .A4(n672), .ZN(n663) );
AOI22_X1 U117 ( .A1(n70), .A2(\predict_PC[8][29] ), .B1(n69), .B2(
\predict_PC[9][29] ), .ZN(n665) );
AOI22_X1 U116 ( .A1(n72), .A2(\predict_PC[10][29] ), .B1(n71), .B2(
\predict_PC[11][29] ), .ZN(n666) );
AOI22_X1 U115 ( .A1(n74), .A2(\predict_PC[12][29] ), .B1(n73), .B2(
\predict_PC[13][29] ), .ZN(n667) );
AOI22_X1 U114 ( .A1(n76), .A2(\predict_PC[14][29] ), .B1(n75), .B2(
\predict_PC[15][29] ), .ZN(n668) );
NAND4_X1 U113 ( .A1(n665), .A2(n666), .A3(n667), .A4(n668), .ZN(n664) );
AOI22_X1 U100 ( .A1(n62), .A2(\predict_PC[0][30] ), .B1(n61), .B2(
\predict_PC[1][30] ), .ZN(n649) );
AOI22_X1 U99 ( .A1(n64), .A2(\predict_PC[2][30] ), .B1(n63), .B2(
\predict_PC[3][30] ), .ZN(n650) );
AOI22_X1 U98 ( .A1(n66), .A2(\predict_PC[4][30] ), .B1(n65), .B2(
\predict_PC[5][30] ), .ZN(n651) );
AOI22_X1 U97 ( .A1(n68), .A2(\predict_PC[6][30] ), .B1(n67), .B2(
\predict_PC[7][30] ), .ZN(n652) );
NAND4_X1 U96 ( .A1(n649), .A2(n650), .A3(n651), .A4(n652), .ZN(n643) );
AOI22_X1 U95 ( .A1(n70), .A2(\predict_PC[8][30] ), .B1(n69), .B2(
\predict_PC[9][30] ), .ZN(n645) );
AOI22_X1 U94 ( .A1(n72), .A2(\predict_PC[10][30] ), .B1(n71), .B2(
\predict_PC[11][30] ), .ZN(n646) );
AOI22_X1 U93 ( .A1(n74), .A2(\predict_PC[12][30] ), .B1(n73), .B2(
\predict_PC[13][30] ), .ZN(n647) );
AOI22_X1 U92 ( .A1(n76), .A2(\predict_PC[14][30] ), .B1(n75), .B2(
\predict_PC[15][30] ), .ZN(n648) );
NAND4_X1 U91 ( .A1(n645), .A2(n646), .A3(n647), .A4(n648), .ZN(n644) );
AOI22_X1 U89 ( .A1(n62), .A2(\predict_PC[0][31] ), .B1(n61), .B2(
\predict_PC[1][31] ), .ZN(n639) );
AOI22_X1 U88 ( .A1(n64), .A2(\predict_PC[2][31] ), .B1(n63), .B2(
\predict_PC[3][31] ), .ZN(n640) );
AOI22_X1 U87 ( .A1(n66), .A2(\predict_PC[4][31] ), .B1(n65), .B2(
\predict_PC[5][31] ), .ZN(n641) );
AOI22_X1 U86 ( .A1(n68), .A2(\predict_PC[6][31] ), .B1(n67), .B2(
\predict_PC[7][31] ), .ZN(n642) );
NAND4_X1 U85 ( .A1(n639), .A2(n640), .A3(n641), .A4(n642), .ZN(n633) );
AOI22_X1 U84 ( .A1(n70), .A2(\predict_PC[8][31] ), .B1(n69), .B2(
\predict_PC[9][31] ), .ZN(n635) );
AOI22_X1 U83 ( .A1(n72), .A2(\predict_PC[10][31] ), .B1(n71), .B2(
\predict_PC[11][31] ), .ZN(n636) );
AOI22_X1 U82 ( .A1(n74), .A2(\predict_PC[12][31] ), .B1(n73), .B2(
\predict_PC[13][31] ), .ZN(n637) );
AOI22_X1 U81 ( .A1(n76), .A2(\predict_PC[14][31] ), .B1(n75), .B2(
\predict_PC[15][31] ), .ZN(n638) );
NAND4_X1 U80 ( .A1(n635), .A2(n636), .A3(n637), .A4(n638), .ZN(n634) );
AOI22_X1 U265 ( .A1(n62), .A2(\predict_PC[0][17] ), .B1(n61), .B2(
\predict_PC[1][17] ), .ZN(n799) );
AOI22_X1 U264 ( .A1(n64), .A2(\predict_PC[2][17] ), .B1(n63), .B2(
\predict_PC[3][17] ), .ZN(n800) );
AOI22_X1 U263 ( .A1(n66), .A2(\predict_PC[4][17] ), .B1(n65), .B2(
\predict_PC[5][17] ), .ZN(n801) );
AOI22_X1 U262 ( .A1(n68), .A2(\predict_PC[6][17] ), .B1(n67), .B2(
\predict_PC[7][17] ), .ZN(n802) );
NAND4_X1 U261 ( .A1(n799), .A2(n800), .A3(n801), .A4(n802), .ZN(n793) );
AOI22_X1 U260 ( .A1(n70), .A2(\predict_PC[8][17] ), .B1(n69), .B2(
\predict_PC[9][17] ), .ZN(n795) );
AOI22_X1 U259 ( .A1(n72), .A2(\predict_PC[10][17] ), .B1(n71), .B2(
\predict_PC[11][17] ), .ZN(n796) );
AOI22_X1 U258 ( .A1(n74), .A2(\predict_PC[12][17] ), .B1(n73), .B2(
\predict_PC[13][17] ), .ZN(n797) );
AOI22_X1 U257 ( .A1(n76), .A2(\predict_PC[14][17] ), .B1(n75), .B2(
\predict_PC[15][17] ), .ZN(n798) );
NAND4_X1 U256 ( .A1(n795), .A2(n796), .A3(n797), .A4(n798), .ZN(n794) );
AOI22_X1 U232 ( .A1(n571), .A2(\predict_PC[0][1] ), .B1(n572), .B2(
\predict_PC[1][1] ), .ZN(n769) );
AOI22_X1 U231 ( .A1(n569), .A2(\predict_PC[2][1] ), .B1(n570), .B2(
\predict_PC[3][1] ), .ZN(n770) );
AOI22_X1 U230 ( .A1(n567), .A2(\predict_PC[4][1] ), .B1(n568), .B2(
\predict_PC[5][1] ), .ZN(n771) );
AOI22_X1 U229 ( .A1(n565), .A2(\predict_PC[6][1] ), .B1(n566), .B2(
\predict_PC[7][1] ), .ZN(n772) );
NAND4_X1 U228 ( .A1(n769), .A2(n770), .A3(n771), .A4(n772), .ZN(n763) );
AOI22_X1 U227 ( .A1(n70), .A2(\predict_PC[8][1] ), .B1(n560), .B2(
\predict_PC[9][1] ), .ZN(n765) );
AOI22_X1 U226 ( .A1(n72), .A2(\predict_PC[10][1] ), .B1(n71), .B2(
\predict_PC[11][1] ), .ZN(n766) );
AOI22_X1 U225 ( .A1(n74), .A2(\predict_PC[12][1] ), .B1(n73), .B2(
\predict_PC[13][1] ), .ZN(n767) );
AOI22_X1 U224 ( .A1(n76), .A2(\predict_PC[14][1] ), .B1(n75), .B2(
\predict_PC[15][1] ), .ZN(n768) );
NAND4_X1 U223 ( .A1(n765), .A2(n766), .A3(n767), .A4(n768), .ZN(n764) );
AOI22_X1 U177 ( .A1(n571), .A2(\predict_PC[0][24] ), .B1(n572), .B2(
\predict_PC[1][24] ), .ZN(n719) );
AOI22_X1 U176 ( .A1(n569), .A2(\predict_PC[2][24] ), .B1(n570), .B2(
\predict_PC[3][24] ), .ZN(n720) );
AOI22_X1 U175 ( .A1(n567), .A2(\predict_PC[4][24] ), .B1(n568), .B2(
\predict_PC[5][24] ), .ZN(n721) );
AOI22_X1 U174 ( .A1(n565), .A2(\predict_PC[6][24] ), .B1(n566), .B2(
\predict_PC[7][24] ), .ZN(n722) );
NAND4_X1 U173 ( .A1(n719), .A2(n720), .A3(n721), .A4(n722), .ZN(n713) );
AOI22_X1 U172 ( .A1(n70), .A2(\predict_PC[8][24] ), .B1(n560), .B2(
\predict_PC[9][24] ), .ZN(n715) );
AOI22_X1 U171 ( .A1(n72), .A2(\predict_PC[10][24] ), .B1(n71), .B2(
\predict_PC[11][24] ), .ZN(n716) );
AOI22_X1 U170 ( .A1(n74), .A2(\predict_PC[12][24] ), .B1(n73), .B2(
\predict_PC[13][24] ), .ZN(n717) );
AOI22_X1 U169 ( .A1(n76), .A2(\predict_PC[14][24] ), .B1(n75), .B2(
\predict_PC[15][24] ), .ZN(n718) );
NAND4_X1 U168 ( .A1(n715), .A2(n716), .A3(n717), .A4(n718), .ZN(n714) );
AOI22_X1 U221 ( .A1(n62), .A2(\predict_PC[0][20] ), .B1(n61), .B2(
\predict_PC[1][20] ), .ZN(n759) );
AOI22_X1 U220 ( .A1(n64), .A2(\predict_PC[2][20] ), .B1(n63), .B2(
\predict_PC[3][20] ), .ZN(n760) );
AOI22_X1 U219 ( .A1(n66), .A2(\predict_PC[4][20] ), .B1(n65), .B2(
\predict_PC[5][20] ), .ZN(n761) );
AOI22_X1 U218 ( .A1(n68), .A2(\predict_PC[6][20] ), .B1(n67), .B2(
\predict_PC[7][20] ), .ZN(n762) );
NAND4_X1 U217 ( .A1(n759), .A2(n760), .A3(n761), .A4(n762), .ZN(n753) );
AOI22_X1 U216 ( .A1(n70), .A2(\predict_PC[8][20] ), .B1(n69), .B2(
\predict_PC[9][20] ), .ZN(n755) );
AOI22_X1 U215 ( .A1(n72), .A2(\predict_PC[10][20] ), .B1(n71), .B2(
\predict_PC[11][20] ), .ZN(n756) );
AOI22_X1 U214 ( .A1(n74), .A2(\predict_PC[12][20] ), .B1(n73), .B2(
\predict_PC[13][20] ), .ZN(n757) );
AOI22_X1 U213 ( .A1(n76), .A2(\predict_PC[14][20] ), .B1(n75), .B2(
\predict_PC[15][20] ), .ZN(n758) );
NAND4_X1 U212 ( .A1(n755), .A2(n756), .A3(n757), .A4(n758), .ZN(n754) );
AOI22_X1 U155 ( .A1(n571), .A2(\predict_PC[0][26] ), .B1(n572), .B2(
\predict_PC[1][26] ), .ZN(n699) );
AOI22_X1 U154 ( .A1(n569), .A2(\predict_PC[2][26] ), .B1(n570), .B2(
\predict_PC[3][26] ), .ZN(n700) );
AOI22_X1 U153 ( .A1(n567), .A2(\predict_PC[4][26] ), .B1(n568), .B2(
\predict_PC[5][26] ), .ZN(n701) );
AOI22_X1 U152 ( .A1(n565), .A2(\predict_PC[6][26] ), .B1(n566), .B2(
\predict_PC[7][26] ), .ZN(n702) );
NAND4_X1 U151 ( .A1(n699), .A2(n700), .A3(n701), .A4(n702), .ZN(n693) );
AOI22_X1 U150 ( .A1(n70), .A2(\predict_PC[8][26] ), .B1(n560), .B2(
\predict_PC[9][26] ), .ZN(n695) );
AOI22_X1 U149 ( .A1(n72), .A2(\predict_PC[10][26] ), .B1(n71), .B2(
\predict_PC[11][26] ), .ZN(n696) );
AOI22_X1 U148 ( .A1(n74), .A2(\predict_PC[12][26] ), .B1(n73), .B2(
\predict_PC[13][26] ), .ZN(n697) );
AOI22_X1 U147 ( .A1(n76), .A2(\predict_PC[14][26] ), .B1(n75), .B2(
\predict_PC[15][26] ), .ZN(n698) );
NAND4_X1 U146 ( .A1(n695), .A2(n696), .A3(n697), .A4(n698), .ZN(n694) );
AOI22_X1 U254 ( .A1(n571), .A2(\predict_PC[0][18] ), .B1(n572), .B2(
\predict_PC[1][18] ), .ZN(n789) );
AOI22_X1 U253 ( .A1(n569), .A2(\predict_PC[2][18] ), .B1(n570), .B2(
\predict_PC[3][18] ), .ZN(n790) );
AOI22_X1 U252 ( .A1(n567), .A2(\predict_PC[4][18] ), .B1(n568), .B2(
\predict_PC[5][18] ), .ZN(n791) );
AOI22_X1 U251 ( .A1(n565), .A2(\predict_PC[6][18] ), .B1(n566), .B2(
\predict_PC[7][18] ), .ZN(n792) );
NAND4_X1 U250 ( .A1(n789), .A2(n790), .A3(n791), .A4(n792), .ZN(n783) );
AOI22_X1 U249 ( .A1(n70), .A2(\predict_PC[8][18] ), .B1(n69), .B2(
\predict_PC[9][18] ), .ZN(n785) );
AOI22_X1 U248 ( .A1(n72), .A2(\predict_PC[10][18] ), .B1(n71), .B2(
\predict_PC[11][18] ), .ZN(n786) );
AOI22_X1 U247 ( .A1(n74), .A2(\predict_PC[12][18] ), .B1(n73), .B2(
\predict_PC[13][18] ), .ZN(n787) );
AOI22_X1 U246 ( .A1(n76), .A2(\predict_PC[14][18] ), .B1(n75), .B2(
\predict_PC[15][18] ), .ZN(n788) );
NAND4_X1 U245 ( .A1(n785), .A2(n786), .A3(n787), .A4(n788), .ZN(n784) );
AOI22_X1 U199 ( .A1(n571), .A2(\predict_PC[0][22] ), .B1(n61), .B2(
\predict_PC[1][22] ), .ZN(n739) );
AOI22_X1 U198 ( .A1(n569), .A2(\predict_PC[2][22] ), .B1(n63), .B2(
\predict_PC[3][22] ), .ZN(n740) );
AOI22_X1 U197 ( .A1(n567), .A2(\predict_PC[4][22] ), .B1(n65), .B2(
\predict_PC[5][22] ), .ZN(n741) );
AOI22_X1 U196 ( .A1(n565), .A2(\predict_PC[6][22] ), .B1(n67), .B2(
\predict_PC[7][22] ), .ZN(n742) );
NAND4_X1 U195 ( .A1(n739), .A2(n740), .A3(n741), .A4(n742), .ZN(n733) );
AOI22_X1 U194 ( .A1(n70), .A2(\predict_PC[8][22] ), .B1(n69), .B2(
\predict_PC[9][22] ), .ZN(n735) );
AOI22_X1 U193 ( .A1(n72), .A2(\predict_PC[10][22] ), .B1(n71), .B2(
\predict_PC[11][22] ), .ZN(n736) );
AOI22_X1 U192 ( .A1(n74), .A2(\predict_PC[12][22] ), .B1(n73), .B2(
\predict_PC[13][22] ), .ZN(n737) );
AOI22_X1 U191 ( .A1(n76), .A2(\predict_PC[14][22] ), .B1(n75), .B2(
\predict_PC[15][22] ), .ZN(n738) );
NAND4_X1 U190 ( .A1(n735), .A2(n736), .A3(n737), .A4(n738), .ZN(n734) );
AOI22_X1 U210 ( .A1(n571), .A2(\predict_PC[0][21] ), .B1(n572), .B2(
\predict_PC[1][21] ), .ZN(n749) );
AOI22_X1 U209 ( .A1(n569), .A2(\predict_PC[2][21] ), .B1(n570), .B2(
\predict_PC[3][21] ), .ZN(n750) );
AOI22_X1 U208 ( .A1(n567), .A2(\predict_PC[4][21] ), .B1(n568), .B2(
\predict_PC[5][21] ), .ZN(n751) );
AOI22_X1 U207 ( .A1(n565), .A2(\predict_PC[6][21] ), .B1(n566), .B2(
\predict_PC[7][21] ), .ZN(n752) );
NAND4_X1 U206 ( .A1(n749), .A2(n750), .A3(n751), .A4(n752), .ZN(n743) );
AOI22_X1 U205 ( .A1(n70), .A2(\predict_PC[8][21] ), .B1(n560), .B2(
\predict_PC[9][21] ), .ZN(n745) );
AOI22_X1 U204 ( .A1(n72), .A2(\predict_PC[10][21] ), .B1(n71), .B2(
\predict_PC[11][21] ), .ZN(n746) );
AOI22_X1 U203 ( .A1(n74), .A2(\predict_PC[12][21] ), .B1(n73), .B2(
\predict_PC[13][21] ), .ZN(n747) );
AOI22_X1 U202 ( .A1(n76), .A2(\predict_PC[14][21] ), .B1(n75), .B2(
\predict_PC[15][21] ), .ZN(n748) );
NAND4_X1 U201 ( .A1(n745), .A2(n746), .A3(n747), .A4(n748), .ZN(n744) );
AOI22_X1 U243 ( .A1(n62), .A2(\predict_PC[0][19] ), .B1(n61), .B2(
\predict_PC[1][19] ), .ZN(n779) );
AOI22_X1 U242 ( .A1(n64), .A2(\predict_PC[2][19] ), .B1(n63), .B2(
\predict_PC[3][19] ), .ZN(n780) );
AOI22_X1 U241 ( .A1(n66), .A2(\predict_PC[4][19] ), .B1(n65), .B2(
\predict_PC[5][19] ), .ZN(n781) );
AOI22_X1 U240 ( .A1(n68), .A2(\predict_PC[6][19] ), .B1(n67), .B2(
\predict_PC[7][19] ), .ZN(n782) );
NAND4_X1 U239 ( .A1(n779), .A2(n780), .A3(n781), .A4(n782), .ZN(n773) );
AOI22_X1 U238 ( .A1(n70), .A2(\predict_PC[8][19] ), .B1(n69), .B2(
\predict_PC[9][19] ), .ZN(n775) );
AOI22_X1 U237 ( .A1(n72), .A2(\predict_PC[10][19] ), .B1(n71), .B2(
\predict_PC[11][19] ), .ZN(n776) );
AOI22_X1 U236 ( .A1(n74), .A2(\predict_PC[12][19] ), .B1(n73), .B2(
\predict_PC[13][19] ), .ZN(n777) );
AOI22_X1 U235 ( .A1(n76), .A2(\predict_PC[14][19] ), .B1(n75), .B2(
\predict_PC[15][19] ), .ZN(n778) );
NAND4_X1 U234 ( .A1(n775), .A2(n776), .A3(n777), .A4(n778), .ZN(n774) );
AOI22_X1 U166 ( .A1(n62), .A2(\predict_PC[0][25] ), .B1(n572), .B2(
\predict_PC[1][25] ), .ZN(n709) );
AOI22_X1 U165 ( .A1(n64), .A2(\predict_PC[2][25] ), .B1(n570), .B2(
\predict_PC[3][25] ), .ZN(n710) );
AOI22_X1 U164 ( .A1(n66), .A2(\predict_PC[4][25] ), .B1(n568), .B2(
\predict_PC[5][25] ), .ZN(n711) );
AOI22_X1 U163 ( .A1(n68), .A2(\predict_PC[6][25] ), .B1(n566), .B2(
\predict_PC[7][25] ), .ZN(n712) );
NAND4_X1 U162 ( .A1(n709), .A2(n710), .A3(n711), .A4(n712), .ZN(n703) );
AOI22_X1 U161 ( .A1(n70), .A2(\predict_PC[8][25] ), .B1(n560), .B2(
\predict_PC[9][25] ), .ZN(n705) );
AOI22_X1 U160 ( .A1(n72), .A2(\predict_PC[10][25] ), .B1(n71), .B2(
\predict_PC[11][25] ), .ZN(n706) );
AOI22_X1 U159 ( .A1(n74), .A2(\predict_PC[12][25] ), .B1(n73), .B2(
\predict_PC[13][25] ), .ZN(n707) );
AOI22_X1 U158 ( .A1(n76), .A2(\predict_PC[14][25] ), .B1(n75), .B2(
\predict_PC[15][25] ), .ZN(n708) );
NAND4_X1 U157 ( .A1(n705), .A2(n706), .A3(n707), .A4(n708), .ZN(n704) );
AOI22_X1 U144 ( .A1(n62), .A2(\predict_PC[0][27] ), .B1(n61), .B2(
\predict_PC[1][27] ), .ZN(n689) );
AOI22_X1 U143 ( .A1(n64), .A2(\predict_PC[2][27] ), .B1(n63), .B2(
\predict_PC[3][27] ), .ZN(n690) );
AOI22_X1 U142 ( .A1(n66), .A2(\predict_PC[4][27] ), .B1(n65), .B2(
\predict_PC[5][27] ), .ZN(n691) );
AOI22_X1 U141 ( .A1(n68), .A2(\predict_PC[6][27] ), .B1(n67), .B2(
\predict_PC[7][27] ), .ZN(n692) );
NAND4_X1 U140 ( .A1(n689), .A2(n690), .A3(n691), .A4(n692), .ZN(n683) );
AOI22_X1 U139 ( .A1(n70), .A2(\predict_PC[8][27] ), .B1(n560), .B2(
\predict_PC[9][27] ), .ZN(n685) );
AOI22_X1 U138 ( .A1(n72), .A2(\predict_PC[10][27] ), .B1(n71), .B2(
\predict_PC[11][27] ), .ZN(n686) );
AOI22_X1 U137 ( .A1(n74), .A2(\predict_PC[12][27] ), .B1(n73), .B2(
\predict_PC[13][27] ), .ZN(n687) );
AOI22_X1 U136 ( .A1(n76), .A2(\predict_PC[14][27] ), .B1(n75), .B2(
\predict_PC[15][27] ), .ZN(n688) );
NAND4_X1 U135 ( .A1(n685), .A2(n686), .A3(n687), .A4(n688), .ZN(n684) );
AOI22_X1 U353 ( .A1(n62), .A2(\predict_PC[0][0] ), .B1(n61), .B2(
\predict_PC[1][0] ), .ZN(n879) );
AOI22_X1 U352 ( .A1(n64), .A2(\predict_PC[2][0] ), .B1(n63), .B2(
\predict_PC[3][0] ), .ZN(n880) );
AOI22_X1 U351 ( .A1(n66), .A2(\predict_PC[4][0] ), .B1(n65), .B2(
\predict_PC[5][0] ), .ZN(n881) );
AOI22_X1 U350 ( .A1(n68), .A2(\predict_PC[6][0] ), .B1(n67), .B2(
\predict_PC[7][0] ), .ZN(n882) );
NAND4_X1 U349 ( .A1(n879), .A2(n880), .A3(n881), .A4(n882), .ZN(n873) );
AOI22_X1 U348 ( .A1(n70), .A2(\predict_PC[8][0] ), .B1(n69), .B2(
\predict_PC[9][0] ), .ZN(n875) );
AOI22_X1 U347 ( .A1(n557), .A2(\predict_PC[10][0] ), .B1(n558), .B2(
\predict_PC[11][0] ), .ZN(n876) );
AOI22_X1 U346 ( .A1(n74), .A2(\predict_PC[12][0] ), .B1(n73), .B2(
\predict_PC[13][0] ), .ZN(n877) );
AOI22_X1 U345 ( .A1(n553), .A2(\predict_PC[14][0] ), .B1(n554), .B2(
\predict_PC[15][0] ), .ZN(n878) );
NAND4_X1 U344 ( .A1(n875), .A2(n876), .A3(n877), .A4(n878), .ZN(n874) );
AOI22_X1 U331 ( .A1(n62), .A2(\predict_PC[0][11] ), .B1(n61), .B2(
\predict_PC[1][11] ), .ZN(n859) );
AOI22_X1 U330 ( .A1(n64), .A2(\predict_PC[2][11] ), .B1(n63), .B2(
\predict_PC[3][11] ), .ZN(n860) );
AOI22_X1 U329 ( .A1(n66), .A2(\predict_PC[4][11] ), .B1(n65), .B2(
\predict_PC[5][11] ), .ZN(n861) );
AOI22_X1 U328 ( .A1(n68), .A2(\predict_PC[6][11] ), .B1(n67), .B2(
\predict_PC[7][11] ), .ZN(n862) );
NAND4_X1 U327 ( .A1(n859), .A2(n860), .A3(n861), .A4(n862), .ZN(n853) );
AOI22_X1 U326 ( .A1(n70), .A2(\predict_PC[8][11] ), .B1(n69), .B2(
\predict_PC[9][11] ), .ZN(n855) );
AOI22_X1 U325 ( .A1(n557), .A2(\predict_PC[10][11] ), .B1(n558), .B2(
\predict_PC[11][11] ), .ZN(n856) );
AOI22_X1 U324 ( .A1(n74), .A2(\predict_PC[12][11] ), .B1(n73), .B2(
\predict_PC[13][11] ), .ZN(n857) );
AOI22_X1 U323 ( .A1(n553), .A2(\predict_PC[14][11] ), .B1(n554), .B2(
\predict_PC[15][11] ), .ZN(n858) );
NAND4_X1 U322 ( .A1(n855), .A2(n856), .A3(n857), .A4(n858), .ZN(n854) );
AOI22_X1 U320 ( .A1(n62), .A2(\predict_PC[0][12] ), .B1(n61), .B2(
\predict_PC[1][12] ), .ZN(n849) );
AOI22_X1 U319 ( .A1(n64), .A2(\predict_PC[2][12] ), .B1(n63), .B2(
\predict_PC[3][12] ), .ZN(n850) );
AOI22_X1 U318 ( .A1(n66), .A2(\predict_PC[4][12] ), .B1(n65), .B2(
\predict_PC[5][12] ), .ZN(n851) );
AOI22_X1 U317 ( .A1(n68), .A2(\predict_PC[6][12] ), .B1(n67), .B2(
\predict_PC[7][12] ), .ZN(n852) );
NAND4_X1 U316 ( .A1(n849), .A2(n850), .A3(n851), .A4(n852), .ZN(n843) );
AOI22_X1 U315 ( .A1(n70), .A2(\predict_PC[8][12] ), .B1(n69), .B2(
\predict_PC[9][12] ), .ZN(n845) );
AOI22_X1 U314 ( .A1(n557), .A2(\predict_PC[10][12] ), .B1(n558), .B2(
\predict_PC[11][12] ), .ZN(n846) );
AOI22_X1 U313 ( .A1(n74), .A2(\predict_PC[12][12] ), .B1(n73), .B2(
\predict_PC[13][12] ), .ZN(n847) );
AOI22_X1 U312 ( .A1(n553), .A2(\predict_PC[14][12] ), .B1(n554), .B2(
\predict_PC[15][12] ), .ZN(n848) );
NAND4_X1 U311 ( .A1(n845), .A2(n846), .A3(n847), .A4(n848), .ZN(n844) );
AOI22_X1 U342 ( .A1(n62), .A2(\predict_PC[0][10] ), .B1(n61), .B2(
\predict_PC[1][10] ), .ZN(n869) );
AOI22_X1 U341 ( .A1(n64), .A2(\predict_PC[2][10] ), .B1(n63), .B2(
\predict_PC[3][10] ), .ZN(n870) );
AOI22_X1 U340 ( .A1(n66), .A2(\predict_PC[4][10] ), .B1(n65), .B2(
\predict_PC[5][10] ), .ZN(n871) );
AOI22_X1 U339 ( .A1(n68), .A2(\predict_PC[6][10] ), .B1(n67), .B2(
\predict_PC[7][10] ), .ZN(n872) );
NAND4_X1 U338 ( .A1(n869), .A2(n870), .A3(n871), .A4(n872), .ZN(n863) );
AOI22_X1 U337 ( .A1(n70), .A2(\predict_PC[8][10] ), .B1(n69), .B2(
\predict_PC[9][10] ), .ZN(n865) );
AOI22_X1 U336 ( .A1(n557), .A2(\predict_PC[10][10] ), .B1(n558), .B2(
\predict_PC[11][10] ), .ZN(n866) );
AOI22_X1 U335 ( .A1(n74), .A2(\predict_PC[12][10] ), .B1(n73), .B2(
\predict_PC[13][10] ), .ZN(n867) );
AOI22_X1 U334 ( .A1(n553), .A2(\predict_PC[14][10] ), .B1(n554), .B2(
\predict_PC[15][10] ), .ZN(n868) );
NAND4_X1 U333 ( .A1(n865), .A2(n866), .A3(n867), .A4(n868), .ZN(n864) );
AOI22_X1 U276 ( .A1(n62), .A2(\predict_PC[0][16] ), .B1(n61), .B2(
\predict_PC[1][16] ), .ZN(n809) );
AOI22_X1 U275 ( .A1(n64), .A2(\predict_PC[2][16] ), .B1(n63), .B2(
\predict_PC[3][16] ), .ZN(n810) );
AOI22_X1 U274 ( .A1(n66), .A2(\predict_PC[4][16] ), .B1(n65), .B2(
\predict_PC[5][16] ), .ZN(n811) );
AOI22_X1 U273 ( .A1(n68), .A2(\predict_PC[6][16] ), .B1(n67), .B2(
\predict_PC[7][16] ), .ZN(n812) );
NAND4_X1 U272 ( .A1(n809), .A2(n810), .A3(n811), .A4(n812), .ZN(n803) );
AOI22_X1 U271 ( .A1(n70), .A2(\predict_PC[8][16] ), .B1(n69), .B2(
\predict_PC[9][16] ), .ZN(n805) );
AOI22_X1 U270 ( .A1(n557), .A2(\predict_PC[10][16] ), .B1(n558), .B2(
\predict_PC[11][16] ), .ZN(n806) );
AOI22_X1 U269 ( .A1(n74), .A2(\predict_PC[12][16] ), .B1(n73), .B2(
\predict_PC[13][16] ), .ZN(n807) );
AOI22_X1 U268 ( .A1(n553), .A2(\predict_PC[14][16] ), .B1(n554), .B2(
\predict_PC[15][16] ), .ZN(n808) );
NAND4_X1 U267 ( .A1(n805), .A2(n806), .A3(n807), .A4(n808), .ZN(n804) );
AOI22_X1 U287 ( .A1(n62), .A2(\predict_PC[0][15] ), .B1(n61), .B2(
\predict_PC[1][15] ), .ZN(n819) );
AOI22_X1 U286 ( .A1(n64), .A2(\predict_PC[2][15] ), .B1(n63), .B2(
\predict_PC[3][15] ), .ZN(n820) );
AOI22_X1 U285 ( .A1(n66), .A2(\predict_PC[4][15] ), .B1(n65), .B2(
\predict_PC[5][15] ), .ZN(n821) );
AOI22_X1 U284 ( .A1(n68), .A2(\predict_PC[6][15] ), .B1(n67), .B2(
\predict_PC[7][15] ), .ZN(n822) );
NAND4_X1 U283 ( .A1(n819), .A2(n820), .A3(n821), .A4(n822), .ZN(n813) );
AOI22_X1 U282 ( .A1(n70), .A2(\predict_PC[8][15] ), .B1(n69), .B2(
\predict_PC[9][15] ), .ZN(n815) );
AOI22_X1 U281 ( .A1(n557), .A2(\predict_PC[10][15] ), .B1(n558), .B2(
\predict_PC[11][15] ), .ZN(n816) );
AOI22_X1 U280 ( .A1(n74), .A2(\predict_PC[12][15] ), .B1(n73), .B2(
\predict_PC[13][15] ), .ZN(n817) );
AOI22_X1 U279 ( .A1(n553), .A2(\predict_PC[14][15] ), .B1(n554), .B2(
\predict_PC[15][15] ), .ZN(n818) );
NAND4_X1 U278 ( .A1(n815), .A2(n816), .A3(n817), .A4(n818), .ZN(n814) );
AOI22_X1 U298 ( .A1(n62), .A2(\predict_PC[0][14] ), .B1(n61), .B2(
\predict_PC[1][14] ), .ZN(n829) );
AOI22_X1 U297 ( .A1(n64), .A2(\predict_PC[2][14] ), .B1(n63), .B2(
\predict_PC[3][14] ), .ZN(n830) );
AOI22_X1 U296 ( .A1(n66), .A2(\predict_PC[4][14] ), .B1(n65), .B2(
\predict_PC[5][14] ), .ZN(n831) );
AOI22_X1 U295 ( .A1(n68), .A2(\predict_PC[6][14] ), .B1(n67), .B2(
\predict_PC[7][14] ), .ZN(n832) );
NAND4_X1 U294 ( .A1(n829), .A2(n830), .A3(n831), .A4(n832), .ZN(n823) );
AOI22_X1 U293 ( .A1(n70), .A2(\predict_PC[8][14] ), .B1(n69), .B2(
\predict_PC[9][14] ), .ZN(n825) );
AOI22_X1 U292 ( .A1(n557), .A2(\predict_PC[10][14] ), .B1(n558), .B2(
\predict_PC[11][14] ), .ZN(n826) );
AOI22_X1 U291 ( .A1(n74), .A2(\predict_PC[12][14] ), .B1(n73), .B2(
\predict_PC[13][14] ), .ZN(n827) );
AOI22_X1 U290 ( .A1(n553), .A2(\predict_PC[14][14] ), .B1(n554), .B2(
\predict_PC[15][14] ), .ZN(n828) );
NAND4_X1 U289 ( .A1(n825), .A2(n826), .A3(n827), .A4(n828), .ZN(n824) );
AOI22_X1 U309 ( .A1(n62), .A2(\predict_PC[0][13] ), .B1(n61), .B2(
\predict_PC[1][13] ), .ZN(n839) );
AOI22_X1 U308 ( .A1(n64), .A2(\predict_PC[2][13] ), .B1(n63), .B2(
\predict_PC[3][13] ), .ZN(n840) );
AOI22_X1 U307 ( .A1(n66), .A2(\predict_PC[4][13] ), .B1(n65), .B2(
\predict_PC[5][13] ), .ZN(n841) );
AOI22_X1 U306 ( .A1(n68), .A2(\predict_PC[6][13] ), .B1(n67), .B2(
\predict_PC[7][13] ), .ZN(n842) );
NAND4_X1 U305 ( .A1(n839), .A2(n840), .A3(n841), .A4(n842), .ZN(n833) );
AOI22_X1 U304 ( .A1(n70), .A2(\predict_PC[8][13] ), .B1(n69), .B2(
\predict_PC[9][13] ), .ZN(n835) );
AOI22_X1 U303 ( .A1(n557), .A2(\predict_PC[10][13] ), .B1(n558), .B2(
\predict_PC[11][13] ), .ZN(n836) );
AOI22_X1 U302 ( .A1(n74), .A2(\predict_PC[12][13] ), .B1(n73), .B2(
\predict_PC[13][13] ), .ZN(n837) );
AOI22_X1 U301 ( .A1(n553), .A2(\predict_PC[14][13] ), .B1(n554), .B2(
\predict_PC[15][13] ), .ZN(n838) );
NAND4_X1 U300 ( .A1(n835), .A2(n836), .A3(n837), .A4(n838), .ZN(n834) );
NAND2_X1 U477 ( .A1(n978), .A2(n52), .ZN(n949) );
NAND2_X1 U465 ( .A1(n976), .A2(n53), .ZN(n951) );
NOR2_X1 U462 ( .A1(n949), .A2(n951), .ZN(N48) );
NAND2_X1 U469 ( .A1(n979), .A2(n978), .ZN(n945) );
NOR2_X1 U458 ( .A1(n945), .A2(n951), .ZN(N46) );
NAND2_X1 U479 ( .A1(n53), .A2(n51), .ZN(n943) );
NOR2_X1 U476 ( .A1(n943), .A2(n949), .ZN(N52) );
NAND2_X1 U456 ( .A1(n977), .A2(n51), .ZN(n946) );
NOR2_X1 U444 ( .A1(n945), .A2(n946), .ZN(N42) );
NOR2_X1 U448 ( .A1(n949), .A2(n947), .ZN(N40) );
NAND2_X1 U466 ( .A1(n52), .A2(n50), .ZN(n944) );
NOR2_X1 U455 ( .A1(n944), .A2(n946), .ZN(N45) );
NOR2_X1 U453 ( .A1(n949), .A2(n946), .ZN(N44) );
NOR2_X1 U464 ( .A1(n944), .A2(n951), .ZN(N49) );
NOR2_X1 U449 ( .A1(n948), .A2(n947), .ZN(N39) );
NOR2_X1 U460 ( .A1(n948), .A2(n951), .ZN(N47) );
NOR2_X1 U447 ( .A1(n948), .A2(n946), .ZN(N43) );
NOR2_X1 U471 ( .A1(n943), .A2(n948), .ZN(N51) );
NOR2_X1 U440 ( .A1(n943), .A2(n944), .ZN(N53) );
NOR2_X1 U450 ( .A1(n945), .A2(n947), .ZN(N38) );
NOR2_X1 U468 ( .A1(n943), .A2(n945), .ZN(N50) );
NOR2_X1 U445 ( .A1(n944), .A2(n947), .ZN(N41) );
NOR2_X1 U355 ( .A1(stall_i), .A2(reset), .ZN(n884) );
OAI22_X1 U354 ( .A1(stall_i), .A2(n883), .B1(n884), .B2(n975), .ZN(n955) );
NAND2_X1 U451 ( .A1(n977), .A2(n976), .ZN(n947) );
NAND2_X1 U472 ( .A1(n979), .A2(n50), .ZN(n948) );
INV_X1 U393 ( .A(TAG_i[1]), .ZN(n974) );
INV_X1 U394 ( .A(TAG_i[2]), .ZN(n973) );
NAND2_X1 U385 ( .A1(n903), .A2(n974), .ZN(n893) );
INV_X1 U395 ( .A(TAG_i[3]), .ZN(n972) );
NAND2_X1 U372 ( .A1(n973), .A2(n972), .ZN(n896) );
NOR2_X1 U371 ( .A1(n895), .A2(n896), .ZN(n569) );
NOR2_X1 U370 ( .A1(n894), .A2(n896), .ZN(n570) );
NOR2_X1 U368 ( .A1(n893), .A2(n896), .ZN(n571) );
NOR2_X1 U367 ( .A1(n891), .A2(n896), .ZN(n572) );
NOR2_X1 U364 ( .A1(n895), .A2(n892), .ZN(n565) );
NOR2_X1 U363 ( .A1(n894), .A2(n892), .ZN(n566) );
NOR2_X1 U361 ( .A1(n893), .A2(n892), .ZN(n567) );
NOR2_X1 U360 ( .A1(n891), .A2(n892), .ZN(n568) );
NOR2_X1 U382 ( .A1(n902), .A2(n891), .ZN(n560) );
OAI21_X1 U397 ( .B1(was_taken_i), .B2(n54), .A(n546), .ZN(n906) );
AND4_X1 U373 ( .A1(n897), .A2(n898), .A3(n899), .A4(n900), .ZN(n885) );
AND4_X1 U358 ( .A1(n887), .A2(n888), .A3(n889), .A4(n890), .ZN(n886) );
OR2_X1 U178 ( .A1(n723), .A2(n724), .ZN(predicted_next_PC_o[23]) );
OR2_X1 U123 ( .A1(n673), .A2(n674), .ZN(predicted_next_PC_o[28]) );
OR2_X1 U101 ( .A1(n653), .A2(n654), .ZN(predicted_next_PC_o[2]) );
OR2_X1 U35 ( .A1(n593), .A2(n594), .ZN(predicted_next_PC_o[6]) );
OR2_X1 U57 ( .A1(n613), .A2(n614), .ZN(predicted_next_PC_o[4]) );
OR2_X1 U46 ( .A1(n603), .A2(n604), .ZN(predicted_next_PC_o[5]) );
OR2_X1 U2 ( .A1(n547), .A2(n548), .ZN(predicted_next_PC_o[9]) );
OR2_X1 U24 ( .A1(n583), .A2(n584), .ZN(predicted_next_PC_o[7]) );
OR2_X1 U13 ( .A1(n573), .A2(n574), .ZN(predicted_next_PC_o[8]) );
OR2_X1 U68 ( .A1(n623), .A2(n624), .ZN(predicted_next_PC_o[3]) );
OR2_X1 U112 ( .A1(n663), .A2(n664), .ZN(predicted_next_PC_o[29]) );
OR2_X1 U90 ( .A1(n643), .A2(n644), .ZN(predicted_next_PC_o[30]) );
OR2_X1 U79 ( .A1(n633), .A2(n634), .ZN(predicted_next_PC_o[31]) );
OR2_X1 U255 ( .A1(n793), .A2(n794), .ZN(predicted_next_PC_o[17]) );
OR2_X1 U222 ( .A1(n763), .A2(n764), .ZN(predicted_next_PC_o[1]) );
OR2_X1 U167 ( .A1(n713), .A2(n714), .ZN(predicted_next_PC_o[24]) );
OR2_X1 U211 ( .A1(n753), .A2(n754), .ZN(predicted_next_PC_o[20]) );
OR2_X1 U145 ( .A1(n693), .A2(n694), .ZN(predicted_next_PC_o[26]) );
OR2_X1 U244 ( .A1(n783), .A2(n784), .ZN(predicted_next_PC_o[18]) );
OR2_X1 U189 ( .A1(n733), .A2(n734), .ZN(predicted_next_PC_o[22]) );
OR2_X1 U200 ( .A1(n743), .A2(n744), .ZN(predicted_next_PC_o[21]) );
OR2_X1 U233 ( .A1(n773), .A2(n774), .ZN(predicted_next_PC_o[19]) );
OR2_X1 U156 ( .A1(n703), .A2(n704), .ZN(predicted_next_PC_o[25]) );
OR2_X1 U134 ( .A1(n683), .A2(n684), .ZN(predicted_next_PC_o[27]) );
OR2_X1 U343 ( .A1(n873), .A2(n874), .ZN(predicted_next_PC_o[0]) );
OR2_X1 U321 ( .A1(n853), .A2(n854), .ZN(predicted_next_PC_o[11]) );
OR2_X1 U310 ( .A1(n843), .A2(n844), .ZN(predicted_next_PC_o[12]) );
OR2_X1 U332 ( .A1(n863), .A2(n864), .ZN(predicted_next_PC_o[10]) );
OR2_X1 U266 ( .A1(n803), .A2(n804), .ZN(predicted_next_PC_o[16]) );
OR2_X1 U277 ( .A1(n813), .A2(n814), .ZN(predicted_next_PC_o[15]) );
OR2_X1 U288 ( .A1(n823), .A2(n824), .ZN(predicted_next_PC_o[14]) );
OR2_X1 U299 ( .A1(n833), .A2(n834), .ZN(predicted_next_PC_o[13]) );
INV_X1 U475 ( .A(stall_i), .ZN(N567) );
AND2_X1 U461 ( .A1(N48), .A2(N567), .ZN(N246) );
AND2_X1 U457 ( .A1(N46), .A2(N567), .ZN(N310) );
AND2_X1 U474 ( .A1(N52), .A2(N567), .ZN(N118) );
AND2_X1 U443 ( .A1(N42), .A2(N567), .ZN(N438) );
AND2_X1 U441 ( .A1(N40), .A2(N567), .ZN(N502) );
AND2_X1 U454 ( .A1(N45), .A2(N567), .ZN(N342) );
AND2_X1 U452 ( .A1(N44), .A2(N567), .ZN(N374) );
AND2_X1 U463 ( .A1(N49), .A2(N567), .ZN(N214) );
AND2_X1 U439 ( .A1(N39), .A2(N567), .ZN(N534) );
AND2_X1 U459 ( .A1(N47), .A2(N567), .ZN(N278) );
AND2_X1 U446 ( .A1(N43), .A2(N567), .ZN(N406) );
AND2_X1 U470 ( .A1(N51), .A2(N567), .ZN(N150) );
AND2_X1 U436 ( .A1(N53), .A2(N567), .ZN(N86) );
AND2_X1 U438 ( .A1(N38), .A2(N567), .ZN(N566) );
AND2_X1 U467 ( .A1(N50), .A2(N567), .ZN(N182) );
AND2_X1 U442 ( .A1(N41), .A2(N567), .ZN(N470) );
INV_X1 U356 ( .A(taken_o), .ZN(n883) );
DFFR_X1 \last_PC_reg[16] ( .D(predicted_next_PC_o[16]), .CK(net3621), .RN(
n99), .QN(n513) );
DFFR_X1 \last_PC_reg[15] ( .D(predicted_next_PC_o[15]), .CK(net3621), .RN(
n94), .QN(n515) );
DFFR_X1 \last_PC_reg[14] ( .D(predicted_next_PC_o[14]), .CK(net3621), .RN(
n96), .QN(n517) );
DFFR_X1 \last_PC_reg[13] ( .D(predicted_next_PC_o[13]), .CK(net3621), .RN(
n99), .QN(n519) );
DFFR_X1 \last_PC_reg[12] ( .D(predicted_next_PC_o[12]), .CK(net3621), .RN(
n96), .QN(n521) );
DFFR_X1 \last_PC_reg[11] ( .D(predicted_next_PC_o[11]), .CK(net3621), .RN(
n96), .QN(n523) );
DFFR_X1 \last_PC_reg[10] ( .D(predicted_next_PC_o[10]), .CK(net3621), .RN(
n86), .QN(n525) );
DFFR_X1 \last_PC_reg[0] ( .D(predicted_next_PC_o[0]), .CK(net3621), .RN(n97), .QN(n545) );
DFFR_X1 \last_PC_reg[28] ( .D(predicted_next_PC_o[28]), .CK(net3621), .RN(
n90), .QN(n489) );
DFFR_X1 \last_PC_reg[23] ( .D(predicted_next_PC_o[23]), .CK(net3621), .RN(
n86), .QN(n499) );
DFFR_X1 \last_PC_reg[31] ( .D(predicted_next_PC_o[31]), .CK(net3621), .RN(
n83), .QN(n483) );
DFFR_X1 \last_PC_reg[30] ( .D(predicted_next_PC_o[30]), .CK(net3621), .RN(
n96), .QN(n485) );
DFFR_X1 \last_PC_reg[29] ( .D(predicted_next_PC_o[29]), .CK(net3621), .RN(
n91), .QN(n487) );
DFFR_X1 \last_PC_reg[27] ( .D(predicted_next_PC_o[27]), .CK(net3621), .RN(
n100), .QN(n491) );
DFFR_X1 \last_PC_reg[26] ( .D(predicted_next_PC_o[26]), .CK(net3621), .RN(
n86), .QN(n493) );
DFFR_X1 \last_PC_reg[25] ( .D(predicted_next_PC_o[25]), .CK(net3621), .RN(
n100), .QN(n495) );
DFFR_X1 \last_PC_reg[24] ( .D(predicted_next_PC_o[24]), .CK(net3621), .RN(
n97), .QN(n497) );
DFFR_X1 \last_PC_reg[22] ( .D(predicted_next_PC_o[22]), .CK(net3621), .RN(
n96), .QN(n501) );
DFFR_X1 \last_PC_reg[21] ( .D(predicted_next_PC_o[21]), .CK(net3621), .RN(
n90), .QN(n503) );
DFFR_X1 \last_PC_reg[20] ( .D(predicted_next_PC_o[20]), .CK(net3621), .RN(
n93), .QN(n505) );
DFFR_X1 \last_PC_reg[19] ( .D(predicted_next_PC_o[19]), .CK(net3621), .RN(
n95), .QN(n507) );
DFFR_X1 \last_PC_reg[18] ( .D(predicted_next_PC_o[18]), .CK(net3621), .RN(
n87), .QN(n509) );
DFFR_X1 \last_PC_reg[17] ( .D(predicted_next_PC_o[17]), .CK(net3621), .RN(
n89), .QN(n511) );
DFFR_X1 \last_PC_reg[9] ( .D(predicted_next_PC_o[9]), .CK(net3621), .RN(
n100), .QN(n527) );
DFFR_X1 \last_PC_reg[8] ( .D(predicted_next_PC_o[8]), .CK(net3621), .RN(n96), .QN(n529) );
DFFR_X1 \last_PC_reg[7] ( .D(predicted_next_PC_o[7]), .CK(net3621), .RN(n89), .QN(n531) );
DFFR_X1 \last_PC_reg[6] ( .D(predicted_next_PC_o[6]), .CK(net3621), .RN(n94), .QN(n533) );
DFFR_X1 \last_PC_reg[5] ( .D(predicted_next_PC_o[5]), .CK(net3621), .RN(n87), .QN(n535) );
DFFR_X1 \last_PC_reg[4] ( .D(predicted_next_PC_o[4]), .CK(net3621), .RN(n88), .QN(n537) );
DFFR_X1 \last_PC_reg[3] ( .D(predicted_next_PC_o[3]), .CK(net3621), .RN(n87), .QN(n539) );
DFFR_X1 \last_PC_reg[2] ( .D(predicted_next_PC_o[2]), .CK(net3621), .RN(n97), .QN(n541) );
DFFR_X1 \last_PC_reg[1] ( .D(predicted_next_PC_o[1]), .CK(net3621), .RN(n98), .QN(n543) );
DFFR_X1 last_mispredict_reg ( .D(mispredict_o), .CK(net3621), .RN(n95), .QN(
n546) );
AOI21_X2 U357 ( .B1(n905), .B2(n54), .A(n906), .ZN(mispredict_o) );
AND4_X2 U375 ( .A1(n46), .A2(n47), .A3(n48), .A4(n49), .ZN(n905) );
NOR2_X1 U376 ( .A1(n895), .A2(n901), .ZN(n553) );
BUF_X1 U378 ( .A(target_PC_i[29]), .Z(n58) );
BUF_X1 U379 ( .A(target_PC_i[28]), .Z(n39) );
BUF_X1 U383 ( .A(target_PC_i[27]), .Z(n60) );
BUF_X1 U384 ( .A(n560), .Z(n69) );
BUF_X2 U387 ( .A(n569), .Z(n64) );
BUF_X2 U388 ( .A(n559), .Z(n70) );
BUF_X1 U389 ( .A(n557), .Z(n72) );
BUF_X1 U392 ( .A(n558), .Z(n71) );
BUF_X2 U396 ( .A(n555), .Z(n74) );
BUF_X2 U398 ( .A(n556), .Z(n73) );
BUF_X1 U399 ( .A(n553), .Z(n76) );
BUF_X1 U400 ( .A(n568), .Z(n65) );
BUF_X2 U401 ( .A(n567), .Z(n66) );
BUF_X1 U402 ( .A(n566), .Z(n67) );
BUF_X2 U403 ( .A(n565), .Z(n68) );
BUF_X1 U404 ( .A(n572), .Z(n61) );
BUF_X2 U405 ( .A(n571), .Z(n62) );
BUF_X1 U406 ( .A(n570), .Z(n63) );
BUF_X1 U407 ( .A(n554), .Z(n75) );
BUF_X1 U408 ( .A(target_PC_i[25]), .Z(n35) );
BUF_X1 U409 ( .A(target_PC_i[24]), .Z(n36) );
BUF_X1 U410 ( .A(target_PC_i[26]), .Z(n37) );
CLKBUF_X1 U411 ( .A(target_PC_i[30]), .Z(n38) );
AND2_X1 U412 ( .A1(target_PC_i[15]), .A2(n515), .ZN(n40) );
AND2_X1 U413 ( .A1(n517), .A2(target_PC_i[14]), .ZN(n41) );
NOR3_X1 U414 ( .A1(n40), .A2(n41), .A3(n933), .ZN(n928) );
AND2_X1 U415 ( .A1(target_PC_i[13]), .A2(n519), .ZN(n42) );
AND2_X1 U416 ( .A1(n521), .A2(target_PC_i[12]), .ZN(n43) );
NOR3_X1 U417 ( .A1(n42), .A2(n43), .A3(n932), .ZN(n929) );
AND2_X1 U418 ( .A1(target_PC_i[11]), .A2(n523), .ZN(n44) );
AND2_X1 U419 ( .A1(target_PC_i[10]), .A2(n525), .ZN(n45) );
NOR3_X1 U420 ( .A1(n44), .A2(n45), .A3(n939), .ZN(n938) );
AND4_X1 U421 ( .A1(n935), .A2(n936), .A3(n937), .A4(n938), .ZN(n46) );
AND4_X1 U422 ( .A1(n913), .A2(n912), .A3(n914), .A4(n911), .ZN(n47) );
AND4_X1 U423 ( .A1(n919), .A2(n922), .A3(n921), .A4(n920), .ZN(n48) );
AND4_X1 U424 ( .A1(n927), .A2(n928), .A3(n929), .A4(n930), .ZN(n49) );
INV_X1 U425 ( .A(reset), .ZN(n97) );
INV_X1 U426 ( .A(reset), .ZN(n98) );
INV_X1 U427 ( .A(reset), .ZN(n95) );
INV_X1 U431 ( .A(reset), .ZN(n96) );
INV_X1 U432 ( .A(reset), .ZN(n99) );
INV_X1 U433 ( .A(reset), .ZN(n100) );
INV_X1 U434 ( .A(reset), .ZN(n94) );
INV_X1 U435 ( .A(reset), .ZN(n92) );
INV_X1 U437 ( .A(reset), .ZN(n93) );
INV_X1 U473 ( .A(reset), .ZN(n88) );
INV_X1 U478 ( .A(reset), .ZN(n89) );
INV_X1 U480 ( .A(reset), .ZN(n90) );
INV_X1 U481 ( .A(reset), .ZN(n91) );
INV_X1 U482 ( .A(reset), .ZN(n84) );
INV_X1 U483 ( .A(reset), .ZN(n80) );
INV_X1 U484 ( .A(reset), .ZN(n81) );
INV_X1 U485 ( .A(reset), .ZN(n82) );
INV_X1 U486 ( .A(reset), .ZN(n83) );
INV_X1 U487 ( .A(reset), .ZN(n77) );
INV_X1 U488 ( .A(reset), .ZN(n78) );
INV_X1 U489 ( .A(reset), .ZN(n79) );
INV_X1 U490 ( .A(reset), .ZN(n87) );
INV_X1 U491 ( .A(reset), .ZN(n85) );
INV_X1 U492 ( .A(reset), .ZN(n86) );
CLKBUF_X1 U493 ( .A(target_PC_i[31]), .Z(n59) );
AND3_X1 U494 ( .A1(n55), .A2(n56), .A3(n57), .ZN(n911) );
INV_X1 U495 ( .A(n918), .ZN(n57) );
AOI21_X1 U496 ( .B1(n885), .B2(n886), .A(reset), .ZN(taken_o) );
INV_X1 U497 ( .A(TAG_i[0]), .ZN(n903) );
NOR2_X1 U498 ( .A1(n902), .A2(n893), .ZN(n559) );
NOR2_X1 U499 ( .A1(n895), .A2(n902), .ZN(n557) );
NOR2_X1 U500 ( .A1(n893), .A2(n901), .ZN(n555) );
NOR2_X1 U501 ( .A1(n902), .A2(n894), .ZN(n558) );
NOR2_X1 U502 ( .A1(n894), .A2(n901), .ZN(n554) );
NOR2_X1 U503 ( .A1(n891), .A2(n901), .ZN(n556) );
OAI22_X1 U504 ( .A1(target_PC_i[29]), .A2(n487), .B1(target_PC_i[28]), .B2(
n489), .ZN(n942) );
OAI22_X1 U505 ( .A1(target_PC_i[31]), .A2(n483), .B1(target_PC_i[30]), .B2(
n485), .ZN(n918) );
OAI22_X1 U506 ( .A1(target_PC_i[3]), .A2(n539), .B1(target_PC_i[2]), .B2(
n541), .ZN(n931) );
OAI22_X1 U507 ( .A1(target_PC_i[13]), .A2(n519), .B1(target_PC_i[12]), .B2(
n521), .ZN(n932) );
OAI22_X1 U508 ( .A1(target_PC_i[15]), .A2(n515), .B1(target_PC_i[14]), .B2(
n517), .ZN(n933) );
OAI22_X1 U509 ( .A1(target_PC_i[9]), .A2(n527), .B1(target_PC_i[8]), .B2(
n529), .ZN(n934) );
OAI22_X1 U510 ( .A1(target_PC_i[23]), .A2(n499), .B1(target_PC_i[22]), .B2(
n501), .ZN(n923) );
OAI22_X1 U511 ( .A1(target_PC_i[5]), .A2(n535), .B1(target_PC_i[4]), .B2(
n537), .ZN(n924) );
OAI22_X1 U512 ( .A1(target_PC_i[7]), .A2(n531), .B1(target_PC_i[6]), .B2(
n533), .ZN(n925) );
OAI22_X1 U513 ( .A1(target_PC_i[1]), .A2(n543), .B1(target_PC_i[0]), .B2(
n545), .ZN(n926) );
OAI22_X1 U514 ( .A1(target_PC_i[21]), .A2(n503), .B1(target_PC_i[20]), .B2(
n505), .ZN(n915) );
OAI22_X1 U515 ( .A1(target_PC_i[25]), .A2(n495), .B1(target_PC_i[24]), .B2(
n497), .ZN(n916) );
OAI22_X1 U516 ( .A1(target_PC_i[27]), .A2(n491), .B1(target_PC_i[26]), .B2(
n493), .ZN(n917) );
NAND2_X1 U517 ( .A1(n485), .A2(target_PC_i[30]), .ZN(n56) );
NAND2_X1 U518 ( .A1(target_PC_i[31]), .A2(n483), .ZN(n55) );
OAI22_X1 U519 ( .A1(target_PC_i[19]), .A2(n507), .B1(target_PC_i[18]), .B2(
n509), .ZN(n941) );
AOI221_X1 U520 ( .B1(target_PC_i[3]), .B2(n539), .C1(n541), .C2(
target_PC_i[2]), .A(n931), .ZN(n930) );
AOI221_X1 U521 ( .B1(target_PC_i[9]), .B2(n527), .C1(target_PC_i[8]), .C2(
n529), .A(n934), .ZN(n927) );
AOI221_X1 U522 ( .B1(target_PC_i[23]), .B2(n499), .C1(n501), .C2(
target_PC_i[22]), .A(n923), .ZN(n922) );
AOI221_X1 U523 ( .B1(target_PC_i[5]), .B2(n535), .C1(n537), .C2(
target_PC_i[4]), .A(n924), .ZN(n921) );
AOI221_X1 U524 ( .B1(target_PC_i[7]), .B2(n531), .C1(n533), .C2(
target_PC_i[6]), .A(n925), .ZN(n920) );
AOI221_X1 U525 ( .B1(target_PC_i[1]), .B2(n543), .C1(n545), .C2(
target_PC_i[0]), .A(n926), .ZN(n919) );
AOI221_X1 U526 ( .B1(target_PC_i[21]), .B2(n503), .C1(n505), .C2(
target_PC_i[20]), .A(n915), .ZN(n914) );
AOI221_X1 U527 ( .B1(target_PC_i[25]), .B2(n495), .C1(n497), .C2(
target_PC_i[24]), .A(n916), .ZN(n913) );
AOI221_X1 U528 ( .B1(target_PC_i[27]), .B2(n491), .C1(n493), .C2(
target_PC_i[26]), .A(n917), .ZN(n912) );
AOI221_X1 U529 ( .B1(target_PC_i[19]), .B2(n507), .C1(n509), .C2(
target_PC_i[18]), .A(n941), .ZN(n936) );
AOI221_X1 U530 ( .B1(target_PC_i[29]), .B2(n487), .C1(n489), .C2(
target_PC_i[28]), .A(n942), .ZN(n935) );
NAND2_X1 U531 ( .A1(TAG_i[0]), .A2(TAG_i[1]), .ZN(n894) );
NAND2_X1 U532 ( .A1(TAG_i[0]), .A2(n974), .ZN(n891) );
endmodule
module fetch_block ( branch_target_i, sum_addr_i, A_i, NPC4_i, S_MUX_PC_BUS_i,
PC_o, PC4_o, PC_BUS_pre_BTB, stall_i, take_prediction_i, mispredict_i,
predicted_PC, clk, rst );
input [31:0] branch_target_i;
input [31:0] sum_addr_i;
input [31:0] A_i;
input [31:0] NPC4_i;
input [1:0] S_MUX_PC_BUS_i;
output [31:0] PC_o;
output [31:0] PC4_o;
output [31:0] PC_BUS_pre_BTB;
input [31:0] predicted_PC;
input stall_i, take_prediction_i, mispredict_i, clk, rst;
wire en_IR, n1;
wire [31:0] PC_BUS;
ff32_en_0 PC ( .D(PC_BUS), .en(en_IR), .clk(clk), .rst(rst), .Q(PC_o) );
add4 PCADD ( .IN1(PC_o), .OUT1(PC4_o) );
mux41_0 MUXTARGET ( .IN0(NPC4_i), .IN1(A_i), .IN2(sum_addr_i), .IN3(
branch_target_i), .CTRL(S_MUX_PC_BUS_i), .OUT1(PC_BUS_pre_BTB) );
mux41_1 MUXPREDICTION ( .IN0(PC4_o), .IN1(predicted_PC), .IN2({
PC_BUS_pre_BTB[31:21], n1, PC_BUS_pre_BTB[19:0]}), .IN3({
PC_BUS_pre_BTB[31:21], n1, PC_BUS_pre_BTB[19:0]}), .CTRL({mispredict_i,
take_prediction_i}), .OUT1(PC_BUS) );
INV_X1 U1 ( .A(stall_i), .ZN(en_IR) );
CLKBUF_X1 U2 ( .A(PC_BUS_pre_BTB[20]), .Z(n1) );
endmodule
module top_level ( clock, rst, IRAM_Addr_o, IRAM_Dout_i, DRAM_Enable_o,
DRAM_WR_o, DRAM_Din_o, DRAM_Addr_o, DRAM_Dout_i );
output [31:0] IRAM_Addr_o;
input [31:0] IRAM_Dout_i;
output [31:0] DRAM_Din_o;
output [31:0] DRAM_Addr_o;
input [31:0] DRAM_Dout_i;
input clock, rst;
output DRAM_Enable_o, DRAM_WR_o;
wire was_taken_from_jl, was_branch, was_jmp, was_taken, stall_fetch,
mispredict, take_prediction, stall_btb, stall_decode, dummy_S_EXT,
dummy_S_EXT_SIGN, dummy_S_EQ_NEQ, exe_stall_cu, dummy_S_MUX_MEM,
dummy_S_RF_W_wb, dummy_S_RF_W_mem, dummy_S_MUX_ALUIN, stall_exe,
enable_regfile, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13;
wire [31:0] dummy_branch_target;
wire [31:0] dummy_sum_addr;
wire [31:0] dummy_A;
wire [31:0] NPCF;
wire [1:0] dummy_S_MUX_PC_BUS;
wire [31:0] PC4;
wire [31:0] TARGET_PC;
wire [31:0] predicted_PC;
wire [31:0] IR;
wire [31:0] AtoComp;
wire [4:0] rA2reg;
wire [4:0] rB2reg;
wire [4:0] rC2reg;
wire [31:0] help_IMM;
wire [31:0] wb2reg;
wire [1:0] dummy_S_FWAdec;
wire [4:0] muxed_dest2exe;
wire [4:0] D22D3;
wire [1:0] dummy_S_MUX_DEST;
wire [12:0] ALUW_dec;
wire [31:0] W2wb;
wire [31:0] dummy_B;
wire [31:0] A2exe;
wire [31:0] B2exe;
wire [4:0] rA2fw;
wire [4:0] rB2mux;
wire [4:0] rC2mux;
wire [31:0] IMM2exe;
wire [12:0] ALUW;
wire [31:0] X2mem;
wire [31:0] S2mem;
wire [1:0] dummy_S_FWA2exe;
wire [1:0] dummy_S_FWB2exe;
wire [4:0] D32reg;
fetch_block UFETCH_BLOCK ( .branch_target_i(dummy_branch_target),
.sum_addr_i(dummy_sum_addr), .A_i(dummy_A), .NPC4_i(NPCF),
.S_MUX_PC_BUS_i(dummy_S_MUX_PC_BUS), .PC_o(IRAM_Addr_o), .PC4_o(PC4),
.PC_BUS_pre_BTB({TARGET_PC[31:30], n5, TARGET_PC[28:0]}), .stall_i(
stall_fetch), .take_prediction_i(take_prediction), .mispredict_i(
mispredict), .predicted_PC(predicted_PC), .clk(clock), .rst(rst) );
btb_N_LINES4_SIZE32 UBTB ( .clock(clock), .reset(rst), .stall_i(stall_btb),
.TAG_i(IRAM_Addr_o[5:2]), .target_PC_i({TARGET_PC[31:30], n5,
TARGET_PC[28:0]}), .was_taken_i(was_taken), .predicted_next_PC_o(
predicted_PC), .taken_o(take_prediction), .mispredict_o(mispredict) );
fetch_regs UFEETCH_REGS ( .NPCF_i(PC4), .IR_i(IRAM_Dout_i), .NPCF_o(NPCF),
.IR_o(IR), .stall_i(stall_decode), .clk(clock), .rst(rst) );
jump_logic UJUMP_LOGIC ( .NPCF_i(NPCF), .IR_i({1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, IR[25:0]}), .A_i(AtoComp), .A_o(dummy_A), .rA_o(rA2reg), .rB_o(
rB2reg), .rC_o(rC2reg), .branch_target_o(dummy_branch_target),
.sum_addr_o(dummy_sum_addr), .extended_imm(help_IMM), .taken_o(
was_taken_from_jl), .FW_X_i(DRAM_Addr_o), .FW_W_i(wb2reg),
.S_FW_Adec_i(dummy_S_FWAdec), .S_EXT_i(dummy_S_EXT), .S_EXT_SIGN_i(
dummy_S_EXT_SIGN), .S_MUX_LINK_i(n6), .S_EQ_NEQ_i(dummy_S_EQ_NEQ) );
dlx_cu_MICROCODE_MEM_SIZE64_FUNC_SIZE11_OP_CODE_SIZE6_IR_SIZE32_CW_SIZE13 UCU (
.Clk(clock), .Rst(rst), .IR_IN({IR[31:16], 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, IR[10:0]}), .stall_exe_i(exe_stall_cu), .mispredict_i(n4),
.D1_i(muxed_dest2exe), .D2_i({n10, n12, n9, n13, n11}), .S_MUX_PC_BUS(
dummy_S_MUX_PC_BUS), .S_EXT(dummy_S_EXT), .S_EXT_SIGN(dummy_S_EXT_SIGN), .S_EQ_NEQ(dummy_S_EQ_NEQ), .S_MUX_DEST(dummy_S_MUX_DEST), .S_MUX_LINK(n6),
.S_MEM_W_R(DRAM_WR_o), .S_MEM_EN(DRAM_Enable_o), .S_RF_W_wb(
dummy_S_RF_W_wb), .S_RF_W_mem(dummy_S_RF_W_mem), .S_MUX_ALUIN(
dummy_S_MUX_ALUIN), .stall_exe_o(stall_exe), .stall_dec_o(stall_decode), .stall_fetch_o(stall_fetch), .stall_btb_o(stall_btb), .was_branch_o(
was_branch), .was_jmp_o(was_jmp), .ALU_WORD_o(ALUW_dec),
.S_MUX_MEM_BAR(dummy_S_MUX_MEM) );
dlx_regfile RF ( .Clk(clock), .Rst(rst), .ENABLE(enable_regfile), .RD1(1'b1),
.RD2(1'b1), .WR(dummy_S_RF_W_mem), .ADD_WR({n10, n12, n9, n13, n11}),
.ADD_RD1(IRAM_Dout_i[25:21]), .ADD_RD2(IRAM_Dout_i[20:16]), .DATAIN(
W2wb), .OUT1(AtoComp), .OUT2(dummy_B) );
decode_regs UDECODE_REGS ( .A_i(AtoComp), .B_i(dummy_B), .rA_i(rA2reg),
.rB_i(rB2reg), .rC_i(rC2reg), .IMM_i(help_IMM), .ALUW_i(ALUW_dec),
.A_o(A2exe), .B_o(B2exe), .rA_o(rA2fw), .rB_o(rB2mux), .rC_o(rC2mux),
.IMM_o(IMM2exe), .ALUW_o(ALUW), .stall_i(stall_exe), .clk(clock),
.rst(rst) );
execute_regs UEXECUTE_REGS ( .X_i(X2mem), .S_i({S2mem[31:2], n7, S2mem[0]}),
.D2_i(muxed_dest2exe), .X_o(DRAM_Addr_o), .S_o(DRAM_Din_o), .D2_o({
D22D3[4:3], n8, D22D3[1:0]}), .stall_i(1'b0), .clk(clock), .rst(rst)
);
execute_block UEXECUTE_BLOCK ( .IMM_i(IMM2exe), .A_i(A2exe), .rB_i(rB2mux),
.rC_i(rC2mux), .MUXED_B_i(B2exe), .S_MUX_ALUIN_i(dummy_S_MUX_ALUIN),
.FW_X_i(DRAM_Addr_o), .FW_W_i(wb2reg), .S_FW_A_i(dummy_S_FWA2exe),
.S_FW_B_i(dummy_S_FWB2exe), .muxed_dest(muxed_dest2exe), .muxed_B({
S2mem[31:2], n7, S2mem[0]}), .S_MUX_DEST_i(dummy_S_MUX_DEST), .OP({
1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), .ALUW_i(ALUW), .DOUT(X2mem), .stall_o(
exe_stall_cu), .Clock(clock), .Reset(rst) );
mem_regs UMEM_REGS ( .W_i(W2wb), .D3_i({n10, n12, n9, n13, n11}), .W_o(
wb2reg), .D3_o(D32reg), .clk(clock), .rst(rst) );
mem_block UMEM_BLOCK ( .X_i(DRAM_Addr_o), .LOAD_i(DRAM_Dout_i), .W_o(W2wb),
.S_MUX_MEM_i_BAR(dummy_S_MUX_MEM) );
fw_logic UFW_LOGIC ( .D1_i({1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), .rAdec_i(
IR[25:21]), .D2_i({D22D3[4:3], n8, D22D3[1:0]}), .D3_i(D32reg), .rA_i(
rA2fw), .rB_i(rB2mux), .S_mem_W(dummy_S_RF_W_mem), .S_wb_W(
dummy_S_RF_W_wb), .S_exe_W(1'b0), .S_FWAdec(dummy_S_FWAdec), .S_FWA(
dummy_S_FWA2exe), .S_FWB(dummy_S_FWB2exe), .S_mem_LOAD_BAR(
dummy_S_MUX_MEM) );
INV_X1 U5 ( .A(stall_decode), .ZN(enable_regfile) );
CLKBUF_X1 U6 ( .A(mispredict), .Z(n4) );
CLKBUF_X1 U7 ( .A(D22D3[1]), .Z(n13) );
BUF_X1 U8 ( .A(D22D3[4]), .Z(n10) );
BUF_X1 U9 ( .A(n8), .Z(n9) );
BUF_X1 U10 ( .A(D22D3[0]), .Z(n11) );
BUF_X1 U11 ( .A(D22D3[3]), .Z(n12) );
INV_X2 U12 ( .A(n3), .ZN(was_taken) );
AOI21_X1 U13 ( .B1(was_taken_from_jl), .B2(was_branch), .A(was_jmp), .ZN(n3)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_4_V
`define SKY130_FD_SC_MS__NOR3B_4_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor3b_4 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor3b_4 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_4_V
|
module sin_lut (input [5:0] lookup, output [7:0] value);
assign value = (lookup == 6'd0) ? 128 :
(lookup == 6'd1) ? 140 :
(lookup == 6'd2) ? 152 :
(lookup == 6'd3) ? 165 :
(lookup == 6'd4) ? 176 :
(lookup == 6'd5) ? 188 :
(lookup == 6'd6) ? 198 :
(lookup == 6'd7) ? 208 :
(lookup == 6'd8) ? 218 :
(lookup == 6'd9) ? 226 :
(lookup == 6'd10) ? 234 :
(lookup == 6'd11) ? 240 :
(lookup == 6'd12) ? 245 :
(lookup == 6'd13) ? 250 :
(lookup == 6'd14) ? 253 :
(lookup == 6'd15) ? 254 :
(lookup == 6'd16) ? 255 :
(lookup == 6'd17) ? 254 :
(lookup == 6'd18) ? 253 :
(lookup == 6'd19) ? 250 :
(lookup == 6'd20) ? 245 :
(lookup == 6'd21) ? 240 :
(lookup == 6'd22) ? 234 :
(lookup == 6'd23) ? 226 :
(lookup == 6'd24) ? 218 :
(lookup == 6'd25) ? 208 :
(lookup == 6'd26) ? 198 :
(lookup == 6'd27) ? 188 :
(lookup == 6'd28) ? 176 :
(lookup == 6'd29) ? 165 :
(lookup == 6'd30) ? 152 :
(lookup == 6'd31) ? 140 :
(lookup == 6'd32) ? 128 :
(lookup == 6'd33) ? 115 :
(lookup == 6'd34) ? 103 :
(lookup == 6'd35) ? 90 :
(lookup == 6'd36) ? 79 :
(lookup == 6'd37) ? 67 :
(lookup == 6'd38) ? 57 :
(lookup == 6'd39) ? 47 :
(lookup == 6'd40) ? 37 :
(lookup == 6'd41) ? 29 :
(lookup == 6'd42) ? 21 :
(lookup == 6'd43) ? 15 :
(lookup == 6'd44) ? 10 :
(lookup == 6'd45) ? 5 :
(lookup == 6'd46) ? 2 :
(lookup == 6'd47) ? 1 :
(lookup == 6'd48) ? 0 :
(lookup == 6'd49) ? 1 :
(lookup == 6'd50) ? 2 :
(lookup == 6'd51) ? 5 :
(lookup == 6'd52) ? 10 :
(lookup == 6'd53) ? 15 :
(lookup == 6'd54) ? 21 :
(lookup == 6'd55) ? 29 :
(lookup == 6'd56) ? 37 :
(lookup == 6'd57) ? 47 :
(lookup == 6'd58) ? 57 :
(lookup == 6'd59) ? 67 :
(lookup == 6'd60) ? 79 :
(lookup == 6'd61) ? 90 :
(lookup == 6'd62) ? 103 :
(lookup == 6'd63) ? 115 :
/*lookup undefined*/ 0 ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDFRBP_PP_BLACKBOX_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfrbp (
RESET_B,
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRBP_PP_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dbginit_mon.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////;
// dbginit_mon.v
//
// Description: dbginit_mon Monitor
////////////////////////////////////////////////////////
module dbginit_mon (
);
// from rtl get the wire and declare here
//wire
wire cmp_clk = cmp_top.iop.cmp_gclk;
wire dram_clk = cmp_top.iop.dram_gclk;
wire jbus_clk = cmp_top.iop.jbus_gclk;
wire cmp_rst = cmp_top.iop.cmp_grst_out_l;
wire dram_rst = cmp_top.iop.dram_grst_l;
wire jbus_rst = cmp_top.iop.jbus_grst_l;
wire cmp_dbginit = cmp_top.iop.ccx.ccx_gdbginit_l;
wire dram_dbginit = cmp_top.iop.dram02.dbginit_l;
wire jbus_dbginit = cmp_top.iop.iobdg.jbus_gdbginit_l;
wire pcx_arb0_dir = cmp_top.iop.ccx.pcx.arb0.direction;
wire pcx_arb1_dir = cmp_top.iop.ccx.pcx.arb1.direction;
wire pcx_arb2_dir = cmp_top.iop.ccx.pcx.arb2.direction;
wire pcx_arb3_dir = cmp_top.iop.ccx.pcx.arb3.direction;
wire pcx_arb4_dir = cmp_top.iop.ccx.pcx.arb4.direction;
wire ccx_arb0_dir = cmp_top.iop.ccx.cpx.arb0.ccx_arb.arbctl.direction;
wire ccx_arb1_dir = cmp_top.iop.ccx.cpx.arb1.ccx_arb.arbctl.direction;
wire ccx_arb2_dir = cmp_top.iop.ccx.cpx.arb2.ccx_arb.arbctl.direction;
wire ccx_arb3_dir = cmp_top.iop.ccx.cpx.arb3.ccx_arb.arbctl.direction;
wire ccx_arb4_dir = cmp_top.iop.ccx.cpx.arb4.ccx_arb.direction;
wire ccx_arb5_dir = cmp_top.iop.ccx.cpx.arb5.ccx_arb.arbctl.direction;
wire ccx_arb6_dir = cmp_top.iop.ccx.cpx.arb6.ccx_arb.arbctl.direction;
wire ccx_arb7_dir = cmp_top.iop.ccx.cpx.arb7.ccx_arb.arbctl.direction;
wire [3:0] sc0_dircnt = cmp_top.iop.sctag0.arbctl.dir_addr_cnt_c3[3:0];
wire [3:0] sc1_dircnt = cmp_top.iop.sctag1.arbctl.dir_addr_cnt_c3[3:0];
wire [3:0] sc2_dircnt = cmp_top.iop.sctag2.arbctl.dir_addr_cnt_c3[3:0];
wire [3:0] sc3_dircnt = cmp_top.iop.sctag3.arbctl.dir_addr_cnt_c3[3:0];
wire [6:0] sc3_tcnt = cmp_top.iop.sctag3.arbctl.tecc_st_cnt[6:0] ;
wire [6:0] sc2_tcnt = cmp_top.iop.sctag2.arbctl.tecc_st_cnt[6:0];
wire [6:0] sc1_tcnt = cmp_top.iop.sctag1.arbctl.tecc_st_cnt[6:0];
wire [6:0] sc0_tcnt = cmp_top.iop.sctag0.arbctl.tecc_st_cnt[6:0];
wire [9:0] sc0_didx = cmp_top.iop.sctag0.arbaddrdp.data_ecc_idx[9:0];
wire [9:0] sc1_didx = cmp_top.iop.sctag1.arbaddrdp.data_ecc_idx[9:0];
wire [9:0] sc2_didx = cmp_top.iop.sctag2.arbaddrdp.data_ecc_idx[9:0];
wire [9:0] sc3_didx = cmp_top.iop.sctag3.arbaddrdp.data_ecc_idx[9:0];
wire [31:0] sc3_scrbcntr = cmp_top.iop.sctag3.csr.scrub_counter[31:0];
wire [31:0] sc2_scrbcntr = cmp_top.iop.sctag2.csr.scrub_counter[31:0];
wire [31:0] sc1_scrbcntr = cmp_top.iop.sctag1.csr.scrub_counter[31:0];
wire [31:0] sc0_scrbcntr = cmp_top.iop.sctag0.csr.scrub_counter[31:0];
wire [3:0] sc0_pickst = cmp_top.iop.sctag0.mbctl.dram_pick_state[3:0];
wire [3:0] sc1_pickst = cmp_top.iop.sctag1.mbctl.dram_pick_state[3:0];
wire [3:0] sc2_pickst = cmp_top.iop.sctag2.mbctl.dram_pick_state[3:0];
wire [3:0] sc3_pickst = cmp_top.iop.sctag3.mbctl.dram_pick_state[3:0];
wire [3:0] sc3_l2rdst = cmp_top.iop.sctag3.fbctl.l2_rd_state[3:0];
wire [3:0] sc2_l2rdst = cmp_top.iop.sctag2.fbctl.l2_rd_state[3:0];
wire [3:0] sc1_l2rdst = cmp_top.iop.sctag1.fbctl.l2_rd_state[3:0];
wire [3:0] sc0_l2rdst = cmp_top.iop.sctag0.fbctl.l2_rd_state[3:0];
wire [6:0] sc0_scbacnt = cmp_top.iop.sctag0.tagctl.scrub_addr_cnt[6:0];
wire [3:0] sc0_scbfcnt = cmp_top.iop.sctag0.tagctl.scrub_fsm_cnt[3:0];
wire [6:0] sc1_scbacnt = cmp_top.iop.sctag1.tagctl.scrub_addr_cnt[6:0];
wire [3:0] sc1_scbfcnt = cmp_top.iop.sctag1.tagctl.scrub_fsm_cnt[3:0];
wire [6:0] sc2_scbacnt = cmp_top.iop.sctag2.tagctl.scrub_addr_cnt[6:0];
wire [3:0] sc2_scbfcnt = cmp_top.iop.sctag2.tagctl.scrub_fsm_cnt[3:0] ;
wire [6:0] sc3_scbacnt = cmp_top.iop.sctag3.tagctl.scrub_addr_cnt[6:0];
wire [3:0] sc3_scbfcnt = cmp_top.iop.sctag3.tagctl.scrub_fsm_cnt[3:0] ;
wire [3:0] sc3_lrust = cmp_top.iop.sctag3.tagdp_ctl.lru_state[3:0];
wire [2:0] sc3_tad0 = cmp_top.iop.sctag3.tagdp_ctl.lru_state_triad0[2:0];
wire [2:0] sc3_tad1 = cmp_top.iop.sctag3.tagdp_ctl.lru_state_triad1[2:0];
wire [2:0] sc3_tad2 = cmp_top.iop.sctag3.tagdp_ctl.lru_state_triad2[2:0];
wire [2:0] sc3_tad3 = cmp_top.iop.sctag3.tagdp_ctl.lru_state_triad3[2:0];
wire [3:0] sc2_lrust = cmp_top.iop.sctag2.tagdp_ctl.lru_state[3:0];
wire [2:0] sc2_tad0 = cmp_top.iop.sctag2.tagdp_ctl.lru_state_triad0[2:0];
wire [2:0] sc2_tad1 = cmp_top.iop.sctag2.tagdp_ctl.lru_state_triad1[2:0];
wire [2:0] sc2_tad2 = cmp_top.iop.sctag2.tagdp_ctl.lru_state_triad2[2:0];
wire [2:0] sc2_tad3 = cmp_top.iop.sctag2.tagdp_ctl.lru_state_triad3[2:0];
wire [3:0] sc1_lrust = cmp_top.iop.sctag1.tagdp_ctl.lru_state[3:0];
wire [2:0] sc1_tad0 = cmp_top.iop.sctag1.tagdp_ctl.lru_state_triad0[2:0];
wire [2:0] sc1_tad1 = cmp_top.iop.sctag1.tagdp_ctl.lru_state_triad1[2:0];
wire [2:0] sc1_tad2 = cmp_top.iop.sctag1.tagdp_ctl.lru_state_triad2[2:0];
wire [2:0] sc1_tad3 = cmp_top.iop.sctag1.tagdp_ctl.lru_state_triad3[2:0];
wire [3:0] sc0_lrust = cmp_top.iop.sctag0.tagdp_ctl.lru_state[3:0];
wire [2:0] sc0_tad0 = cmp_top.iop.sctag0.tagdp_ctl.lru_state_triad0[2:0];
wire [2:0] sc0_tad1 = cmp_top.iop.sctag0.tagdp_ctl.lru_state_triad1[2:0];
wire [2:0] sc0_tad2 = cmp_top.iop.sctag0.tagdp_ctl.lru_state_triad2[2:0];
wire [2:0] sc0_tad3 = cmp_top.iop.sctag0.tagdp_ctl.lru_state_triad3[2:0];
wire [3:0] sc0_qd0st = cmp_top.iop.sctag0.wbctl.quad0_state[3:0];
wire [3:0] sc0_qd1st = cmp_top.iop.sctag0.wbctl.quad1_state[3:0];
wire [3:0] sc0_qd2st = cmp_top.iop.sctag0.wbctl.quad2_state[3:0];
wire [2:0] sc0_qdst = cmp_top.iop.sctag0.wbctl.quad_state[2:0];
wire [3:0] sc1_qd0st = cmp_top.iop.sctag1.wbctl.quad0_state[3:0];
wire [3:0] sc1_qd1st = cmp_top.iop.sctag1.wbctl.quad1_state[3:0];
wire [3:0] sc1_qd2st = cmp_top.iop.sctag1.wbctl.quad2_state[3:0];
wire [2:0] sc1_qdst = cmp_top.iop.sctag1.wbctl.quad_state[2:0];
wire [3:0] sc2_qd0st = cmp_top.iop.sctag2.wbctl.quad0_state[3:0];
wire [3:0] sc2_qd1st = cmp_top.iop.sctag2.wbctl.quad1_state[3:0];
wire [3:0] sc2_qd2st = cmp_top.iop.sctag2.wbctl.quad2_state[3:0];
wire [2:0] sc2_qdst = cmp_top.iop.sctag2.wbctl.quad_state[2:0];
wire [3:0] sc3_qd0st = cmp_top.iop.sctag3.wbctl.quad0_state[3:0];
wire [3:0] sc3_qd1st = cmp_top.iop.sctag3.wbctl.quad1_state[3:0];
wire [3:0] sc3_qd2st = cmp_top.iop.sctag3.wbctl.quad2_state[3:0];
wire [2:0] sc3_qdst = cmp_top.iop.sctag3.wbctl.quad_state[2:0];
`ifdef RTL_SPARC0
wire [3:0] sp0_usd0 = cmp_top.iop.sparc0.ifu.swl.thr_sched.used0[3:0];
wire [3:0] sp0_usd1 = cmp_top.iop.sparc0.ifu.swl.thr_sched.used1[3:0];
wire [3:0] sp0_usd2 = cmp_top.iop.sparc0.ifu.swl.thr_sched.used2[3:0];
wire [3:0] sp0_usd3 = cmp_top.iop.sparc0.ifu.swl.thr_sched.used3[3:0];
wire [4:0] sp0_q = cmp_top.iop.sparc0.ifu.ifqctl.lfsr.q[4:0];
wire [3:0] sp0_pv = cmp_top.iop.sparc0.ifu.ifqctl.pcxrndrob.pv[3:0];
`endif
`ifdef RTL_SPARC1
wire [3:0] sp1_usd0 = cmp_top.iop.sparc1.ifu.swl.thr_sched.used0[3:0];
wire [3:0] sp1_usd1 = cmp_top.iop.sparc1.ifu.swl.thr_sched.used1[3:0];
wire [3:0] sp1_usd2 = cmp_top.iop.sparc1.ifu.swl.thr_sched.used2[3:0];
wire [3:0] sp1_usd3 = cmp_top.iop.sparc1.ifu.swl.thr_sched.used3[3:0];
wire [4:0] sp1_q = cmp_top.iop.sparc1.ifu.ifqctl.lfsr.q[4:0];
wire [3:0] sp1_pv = cmp_top.iop.sparc1.ifu.ifqctl.pcxrndrob.pv[3:0];
`endif
`ifdef RTL_SPARC2
wire [3:0] sp2_pv = cmp_top.iop.sparc2.ifu.ifqctl.pcxrndrob.pv[3:0];
wire [4:0] sp2_q = cmp_top.iop.sparc2.ifu.ifqctl.lfsr.q[4:0];
wire [3:0] sp2_usd0 = cmp_top.iop.sparc2.ifu.swl.thr_sched.used0[3:0];
wire [3:0] sp2_usd1 = cmp_top.iop.sparc2.ifu.swl.thr_sched.used1[3:0];
wire [3:0] sp2_usd2 = cmp_top.iop.sparc2.ifu.swl.thr_sched.used2[3:0];
wire [3:0] sp2_usd3 = cmp_top.iop.sparc2.ifu.swl.thr_sched.used3[3:0];
`endif
`ifdef RTL_SPARC3
wire [4:0] sp3_q = cmp_top.iop.sparc3.ifu.ifqctl.lfsr.q[4:0];
wire [3:0] sp3_pv = cmp_top.iop.sparc3.ifu.ifqctl.pcxrndrob.pv[3:0];
wire [3:0] sp3_usd0 = cmp_top.iop.sparc3.ifu.swl.thr_sched.used0[3:0];
wire [3:0] sp3_usd1 = cmp_top.iop.sparc3.ifu.swl.thr_sched.used1[3:0];
wire [3:0] sp3_usd2 = cmp_top.iop.sparc3.ifu.swl.thr_sched.used2[3:0];
wire [3:0] sp3_usd3 = cmp_top.iop.sparc3.ifu.swl.thr_sched.used3[3:0];
`endif
`ifdef RTL_SPARC4
wire [3:0] sp4_pv = cmp_top.iop.sparc4.ifu.ifqctl.pcxrndrob.pv[3:0];
wire [4:0] sp4_q = cmp_top.iop.sparc4.ifu.ifqctl.lfsr.q[4:0];
wire [3:0] sp4_usd0 = cmp_top.iop.sparc4.ifu.swl.thr_sched.used0[3:0];
wire [3:0] sp4_usd1 = cmp_top.iop.sparc4.ifu.swl.thr_sched.used1[3:0];
wire [3:0] sp4_usd2 = cmp_top.iop.sparc4.ifu.swl.thr_sched.used2[3:0];
wire [3:0] sp4_usd3 = cmp_top.iop.sparc4.ifu.swl.thr_sched.used3[3:0];
`endif
`ifdef RTL_SPARC5
wire [3:0] sp5_pv = cmp_top.iop.sparc5.ifu.ifqctl.pcxrndrob.pv[3:0];
wire [4:0] sp5_q = cmp_top.iop.sparc5.ifu.ifqctl.lfsr.q[4:0];
wire [3:0] sp5_usd0 = cmp_top.iop.sparc5.ifu.swl.thr_sched.used0[3:0];
wire [3:0] sp5_usd1 = cmp_top.iop.sparc5.ifu.swl.thr_sched.used1[3:0];
wire [3:0] sp5_usd2 = cmp_top.iop.sparc5.ifu.swl.thr_sched.used2[3:0];
wire [3:0] sp5_usd3 = cmp_top.iop.sparc5.ifu.swl.thr_sched.used3[3:0];
`endif
`ifdef RTL_SPARC6
wire [4:0] sp6_q = cmp_top.iop.sparc6.ifu.ifqctl.lfsr.q[4:0];
wire [3:0] sp6_pv = cmp_top.iop.sparc6.ifu.ifqctl.pcxrndrob.pv[3:0];
wire [3:0] sp6_usd0 = cmp_top.iop.sparc6.ifu.swl.thr_sched.used0[3:0];
wire [3:0] sp6_usd1 = cmp_top.iop.sparc6.ifu.swl.thr_sched.used1[3:0];
wire [3:0] sp6_usd2 = cmp_top.iop.sparc6.ifu.swl.thr_sched.used2[3:0];
wire [3:0] sp6_usd3 = cmp_top.iop.sparc6.ifu.swl.thr_sched.used3[3:0];
`endif
`ifdef RTL_SPARC7
wire [3:0] sp7_pv = cmp_top.iop.sparc7.ifu.ifqctl.pcxrndrob.pv[3:0];
wire [4:0] sp7_q = cmp_top.iop.sparc7.ifu.ifqctl.lfsr.q[4:0];
wire [3:0] sp7_usd0 = cmp_top.iop.sparc7.ifu.swl.thr_sched.used0[3:0];
wire [3:0] sp7_usd1 = cmp_top.iop.sparc7.ifu.swl.thr_sched.used1[3:0];
wire [3:0] sp7_usd2 = cmp_top.iop.sparc7.ifu.swl.thr_sched.used2[3:0];
wire [3:0] sp7_usd3 = cmp_top.iop.sparc7.ifu.swl.thr_sched.used3[3:0];
`endif
wire [32:0] dr02_q0scbad = cmp_top.iop.dram02.dramctl0.dram_dctl.dram_que.que_scrb_addr_p1[32:0];
wire [8:0] dr02_q0scbca = cmp_top.iop.dram02.dramctl0.dram_dctl.dram_que.que_scrb_cas_addr[8:0];
wire dr02_q0scbrk = cmp_top.iop.dram02.dramctl0.dram_dctl.dram_que.que_scrb_rank_addr;
wire [14:0] dr02_q0scbrs = cmp_top.iop.dram02.dramctl0.dram_dctl.dram_que.que_scrb_ras_addr[14:0];
wire dr02_q0scbsk = cmp_top.iop.dram02.dramctl0.dram_dctl.dram_que.que_scrb_stack_addr;
wire [2:0] dr02_q0scbbk = cmp_top.iop.dram02.dramctl0.dram_dctl.dram_que.que_scrb_bank[2:0];
wire [2:0] dr02_q1scbbk = cmp_top.iop.dram02.dramctl1.dram_dctl.dram_que.que_scrb_bank[2:0];
wire [8:0] dr02_q1scbca = cmp_top.iop.dram02.dramctl1.dram_dctl.dram_que.que_scrb_cas_addr[8:0];
wire dr02_q1scbrk = cmp_top.iop.dram02.dramctl1.dram_dctl.dram_que.que_scrb_rank_addr;
wire [14:0] dr02_q1scbrs = cmp_top.iop.dram02.dramctl1.dram_dctl.dram_que.que_scrb_ras_addr[14:0];
wire dr02_q1scbsk = cmp_top.iop.dram02.dramctl1.dram_dctl.dram_que.que_scrb_stack_addr;
wire [32:0] dr02_q1scbad = cmp_top.iop.dram02.dramctl1.dram_dctl.dram_que.que_scrb_addr_p1[32:0];
wire [32:0] dr13_q0scbad = cmp_top.iop.dram13.dramctl0.dram_dctl.dram_que.que_scrb_addr_p1[32:0];
wire [8:0] dr13_q0scbca = cmp_top.iop.dram13.dramctl0.dram_dctl.dram_que.que_scrb_cas_addr[8:0];
wire dr13_q0scbrk = cmp_top.iop.dram13.dramctl0.dram_dctl.dram_que.que_scrb_rank_addr;
wire [14:0] dr13_q0scbrs = cmp_top.iop.dram13.dramctl0.dram_dctl.dram_que.que_scrb_ras_addr[14:0];
wire dr13_q0scbsk = cmp_top.iop.dram13.dramctl0.dram_dctl.dram_que.que_scrb_stack_addr;
wire [2:0] dr13_q0scbbk = cmp_top.iop.dram13.dramctl0.dram_dctl.dram_que.que_scrb_bank[2:0];
wire [2:0] dr13_q1scbbk = cmp_top.iop.dram13.dramctl1.dram_dctl.dram_que.que_scrb_bank[2:0];
wire [32:0] dr13_q1scbad = cmp_top.iop.dram13.dramctl1.dram_dctl.dram_que.que_scrb_addr_p1[32:0];
wire [8:0] dr13_q1scbca = cmp_top.iop.dram13.dramctl1.dram_dctl.dram_que.que_scrb_cas_addr[8:0];
wire dr13_q1scbrk = cmp_top.iop.dram13.dramctl1.dram_dctl.dram_que.que_scrb_rank_addr;
wire [14:0] dr13_q1scbrs = cmp_top.iop.dram13.dramctl1.dram_dctl.dram_que.que_scrb_ras_addr[14:0];
wire dr13_q1scbsk = cmp_top.iop.dram13.dramctl1.dram_dctl.dram_que.que_scrb_stack_addr;
wire[10:0] cmp_cnt = 11'hc;
wire[10:0] dram_cnt = 11'hc;
wire[10:0] jbus_cnt = 11'hc;
// module instantiations
// dbginit_inst
// cmp_clk
dbginit_inst #(1) cmp_dbginit1 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (pcx_arb0_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(1) );
dbginit_inst #(1) cmp_dbginit2 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (pcx_arb1_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(2) );
dbginit_inst #(1) cmp_dbginit3 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (pcx_arb2_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(3) );
dbginit_inst #(1) cmp_dbginit4 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (pcx_arb3_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(4) );
dbginit_inst #(1) cmp_dbginit5 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (pcx_arb4_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(5) );
dbginit_inst #(1) cmp_dbginit6 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (ccx_arb0_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(6) );
dbginit_inst #(1) cmp_dbginit7 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (ccx_arb1_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(7) );
dbginit_inst #(1) cmp_dbginit8 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (ccx_arb2_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(8) );
dbginit_inst #(1) cmp_dbginit9 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (ccx_arb3_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(9) );
dbginit_inst #(1) cmp_dbginit10 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (ccx_arb4_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(10) );
dbginit_inst #(1) cmp_dbginit11 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (ccx_arb5_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(11) );
dbginit_inst #(1) cmp_dbginit12 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (ccx_arb6_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(12) );
dbginit_inst #(1) cmp_dbginit13 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (ccx_arb7_dir), .expected (1'b1),.cnt_val(cmp_cnt), .mon_num(13) );
dbginit_inst #(4) cmp_dbginit14 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_dircnt), .expected (4'b0),.cnt_val(cmp_cnt), .mon_num(14) );
dbginit_inst #(4) cmp_dbginit15 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_dircnt), .expected (4'b0),.cnt_val(cmp_cnt), .mon_num(15) );
dbginit_inst #(4) cmp_dbginit16 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_dircnt), .expected (4'b0),.cnt_val(cmp_cnt), .mon_num(16) );
dbginit_inst #(4) cmp_dbginit17 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_dircnt), .expected (4'b0),.cnt_val(cmp_cnt), .mon_num(17) );
dbginit_inst #(7) cmp_dbginit18 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_tcnt), .expected (7'b0),.cnt_val(cmp_cnt), .mon_num(18) );
dbginit_inst #(7) cmp_dbginit19 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_tcnt), .expected (7'b0),.cnt_val(cmp_cnt), .mon_num(19) );
dbginit_inst #(7) cmp_dbginit20( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_tcnt), .expected (7'b0),.cnt_val(cmp_cnt), .mon_num(20) );
dbginit_inst #(7) cmp_dbginit21 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_tcnt), .expected (7'b0),.cnt_val(cmp_cnt), .mon_num(21) );
dbginit_inst #(10) cmp_dbginit22 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_didx), .expected (10'b0),.cnt_val(cmp_cnt), .mon_num(22) );
dbginit_inst #(10) cmp_dbginit23 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_didx), .expected (10'b0),.cnt_val(cmp_cnt), .mon_num(23) );
dbginit_inst #(10) cmp_dbginit24 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_didx), .expected (10'b0),.cnt_val(cmp_cnt), .mon_num(24) );
dbginit_inst #(10) cmp_dbginit25 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_didx), .expected (10'b0),.cnt_val(cmp_cnt), .mon_num(25) );
dbginit_inst #(32) cmp_dbginit26 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_scrbcntr), .expected (32'b0),.cnt_val(cmp_cnt), .mon_num(26) );
dbginit_inst #(32) cmp_dbginit27 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_scrbcntr), .expected (32'b0),.cnt_val(cmp_cnt), .mon_num(27) );
dbginit_inst #(32) cmp_dbginit28 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_scrbcntr), .expected (32'b0),.cnt_val(cmp_cnt), .mon_num(28) );
dbginit_inst #(32) cmp_dbginit29 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_scrbcntr), .expected (32'b0),.cnt_val(cmp_cnt), .mon_num(29) );
dbginit_inst #(4) cmp_dbginit30 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_pickst), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(30) );
dbginit_inst #(4) cmp_dbginit31 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_pickst), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(31) );
dbginit_inst #(4) cmp_dbginit32 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_pickst), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(32) );
dbginit_inst #(4) cmp_dbginit33 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_pickst), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(33) );
dbginit_inst #(4) cmp_dbginit34 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_l2rdst), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(34) );
dbginit_inst #(4) cmp_dbginit35 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_l2rdst), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(35) );
dbginit_inst #(4) cmp_dbginit36 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_l2rdst), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(36) );
dbginit_inst #(4) cmp_dbginit37 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_l2rdst), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(37) );
dbginit_inst #(7) cmp_dbginit38 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_scbacnt), .expected (7'b0),.cnt_val(cmp_cnt), .mon_num(38) );
dbginit_inst #(7) cmp_dbginit39 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_scbacnt), .expected (7'b0),.cnt_val(cmp_cnt), .mon_num(39) );
dbginit_inst #(7) cmp_dbginit40 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_scbacnt), .expected (7'b0),.cnt_val(cmp_cnt), .mon_num(40) );
dbginit_inst #(7) cmp_dbginit41 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_scbacnt), .expected (7'b0),.cnt_val(cmp_cnt), .mon_num(41) );
dbginit_inst #(4) cmp_dbginit42 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_scbfcnt), .expected (4'b0),.cnt_val(cmp_cnt), .mon_num(42) );
dbginit_inst #(4) cmp_dbginit43 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_scbfcnt), .expected (4'b0),.cnt_val(cmp_cnt), .mon_num(43) );
dbginit_inst #(4) cmp_dbginit44 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_scbfcnt), .expected (4'b0),.cnt_val(cmp_cnt), .mon_num(44) );
dbginit_inst #(4) cmp_dbginit45 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_scbfcnt), .expected (4'b0),.cnt_val(cmp_cnt), .mon_num(45) );
dbginit_inst #(4) cmp_dbginit46 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_lrust), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(46) );
dbginit_inst #(4) cmp_dbginit47 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_lrust), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(47) );
dbginit_inst #(4) cmp_dbginit48 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_lrust), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(48) );
dbginit_inst #(4) cmp_dbginit49 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_lrust), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(49) );
dbginit_inst #(3) cmp_dbginit50 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_tad0), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(50) );
dbginit_inst #(3) cmp_dbginit51 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_tad1), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(51) );
dbginit_inst #(3) cmp_dbginit52 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_tad2), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(52) );
dbginit_inst #(3) cmp_dbginit53 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_tad3), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(53) );
dbginit_inst #(3) cmp_dbginit54 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_tad0), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(54) );
dbginit_inst #(3) cmp_dbginit55 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_tad1), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(55) );
dbginit_inst #(3) cmp_dbginit56 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_tad2), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(56) );
dbginit_inst #(3) cmp_dbginit57 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_tad3), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(57) );
dbginit_inst #(3) cmp_dbginit58 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_tad0), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(58) );
dbginit_inst #(3) cmp_dbginit59 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_tad1), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(59) );
dbginit_inst #(3) cmp_dbginit60 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_tad2), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(60) );
dbginit_inst #(3) cmp_dbginit61 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_tad3), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(61) );
dbginit_inst #(3) cmp_dbginit62 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_tad0), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(62) );
dbginit_inst #(3) cmp_dbginit63 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_tad1), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(63) );
dbginit_inst #(3) cmp_dbginit64 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_tad2), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(64) );
dbginit_inst #(3) cmp_dbginit65 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_tad3), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(65) );
dbginit_inst #(4) cmp_dbginit66 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_qd0st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(66) );
dbginit_inst #(4) cmp_dbginit67 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_qd1st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(67) );
dbginit_inst #(4) cmp_dbginit68 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_qd2st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(68) );
dbginit_inst #(3) cmp_dbginit69 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc0_qdst), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(69) );
dbginit_inst #(4) cmp_dbginit70 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_qd0st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(70) );
dbginit_inst #(4) cmp_dbginit71 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_qd1st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(71) );
dbginit_inst #(4) cmp_dbginit72 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_qd2st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(72) );
dbginit_inst #(3) cmp_dbginit73 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc1_qdst), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(73) );
dbginit_inst #(4) cmp_dbginit74 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_qd0st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(74) );
dbginit_inst #(4) cmp_dbginit75 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_qd1st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(75) );
dbginit_inst #(4) cmp_dbginit76 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_qd2st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(76) );
dbginit_inst #(3) cmp_dbginit77 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc2_qdst), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(77) );
dbginit_inst #(4) cmp_dbginit78 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_qd0st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(78) );
dbginit_inst #(4) cmp_dbginit79 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_qd1st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(79) );
dbginit_inst #(4) cmp_dbginit80 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_qd2st), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(80) );
dbginit_inst #(3) cmp_dbginit81 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sc3_qdst), .expected (3'b1),.cnt_val(cmp_cnt), .mon_num(81) );
`ifdef RTL_SPARC0
dbginit_inst #(4) cmp_dbginit82 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp0_usd0), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(82) );
dbginit_inst #(4) cmp_dbginit83 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp0_usd1), .expected (4'h2),.cnt_val(cmp_cnt), .mon_num(83) );
dbginit_inst #(4) cmp_dbginit84 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp0_usd2), .expected (4'h4),.cnt_val(cmp_cnt), .mon_num(84) );
dbginit_inst #(4) cmp_dbginit85 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp0_usd3), .expected (4'h8),.cnt_val(cmp_cnt), .mon_num(85) );
dbginit_inst #(5) cmp_dbginit86 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp0_q), .expected (5'h1f),.cnt_val(cmp_cnt), .mon_num(86) );
dbginit_inst #(4) cmp_dbginit87 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp0_pv), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(87) );
`endif
`ifdef RTL_SPARC1
dbginit_inst #(4) cmp_dbginit88 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp1_usd0), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(88) );
dbginit_inst #(4) cmp_dbginit89 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp1_usd1), .expected (4'h2),.cnt_val(cmp_cnt), .mon_num(89) );
dbginit_inst #(4) cmp_dbginit90 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp1_usd2), .expected (4'h4),.cnt_val(cmp_cnt), .mon_num(90) );
dbginit_inst #(4) cmp_dbginit91 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp1_usd3), .expected (4'h8),.cnt_val(cmp_cnt), .mon_num(91) );
dbginit_inst #(5) cmp_dbginit92 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp1_q), .expected (5'h1f),.cnt_val(cmp_cnt), .mon_num(92) );
dbginit_inst #(4) cmp_dbginit93 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp1_pv), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(93) );
`endif
`ifdef RTL_SPARC2
dbginit_inst #(4) cmp_dbginit94 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp2_usd0), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(94) );
dbginit_inst #(4) cmp_dbginit95 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp2_usd1), .expected (4'h2),.cnt_val(cmp_cnt), .mon_num(95) );
dbginit_inst #(4) cmp_dbginit96 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp2_usd2), .expected (4'h4),.cnt_val(cmp_cnt), .mon_num(96) );
dbginit_inst #(4) cmp_dbginit97 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp2_usd3), .expected (4'h8),.cnt_val(cmp_cnt), .mon_num(97) );
dbginit_inst #(5) cmp_dbginit98 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp2_q), .expected (5'h1f),.cnt_val(cmp_cnt), .mon_num(98) );
dbginit_inst #(4) cmp_dbginit99 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp2_pv), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(99) );
`endif
`ifdef RTL_SPARC3
dbginit_inst #(4) cmp_dbginit100 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp3_usd0), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(100) );
dbginit_inst #(4) cmp_dbginit101 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp3_usd1), .expected (4'h2),.cnt_val(cmp_cnt), .mon_num(101) );
dbginit_inst #(4) cmp_dbginit102 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp3_usd2), .expected (4'h4),.cnt_val(cmp_cnt), .mon_num(102) );
dbginit_inst #(4) cmp_dbginit103 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp3_usd3), .expected (4'h8),.cnt_val(cmp_cnt), .mon_num(103) );
dbginit_inst #(5) cmp_dbginit104 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp3_q), .expected (5'h1f),.cnt_val(cmp_cnt), .mon_num(104) );
dbginit_inst #(4) cmp_dbginit105 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp3_pv), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(105) );
`endif
`ifdef RTL_SPARC4
dbginit_inst #(4) cmp_dbginit106 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp4_usd0), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(106) );
dbginit_inst #(4) cmp_dbginit107 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp4_usd1), .expected (4'h2),.cnt_val(cmp_cnt), .mon_num(107) );
dbginit_inst #(4) cmp_dbginit108 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp4_usd2), .expected (4'h4),.cnt_val(cmp_cnt), .mon_num(108) );
dbginit_inst #(4) cmp_dbginit109 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp4_usd3), .expected (4'h8),.cnt_val(cmp_cnt), .mon_num(109) );
dbginit_inst #(5) cmp_dbginit110 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp4_q), .expected (5'h1f),.cnt_val(cmp_cnt), .mon_num(110) );
dbginit_inst #(4) cmp_dbginit111 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp4_pv), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(111) );
`endif
`ifdef RTL_SPARC5
dbginit_inst #(4) cmp_dbginit112 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp5_usd0), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(112) );
dbginit_inst #(4) cmp_dbginit113 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp5_usd1), .expected (4'h2),.cnt_val(cmp_cnt), .mon_num(113) );
dbginit_inst #(4) cmp_dbginit114 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp5_usd2), .expected (4'h4),.cnt_val(cmp_cnt), .mon_num(114) );
dbginit_inst #(4) cmp_dbginit115 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp5_usd3), .expected (4'h8),.cnt_val(cmp_cnt), .mon_num(115) );
dbginit_inst #(5) cmp_dbginit116 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp5_q), .expected (5'h1f),.cnt_val(cmp_cnt), .mon_num(116) );
dbginit_inst #(4) cmp_dbginit117 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp5_pv), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(117) );
`endif
`ifdef RTL_SPARC6
dbginit_inst #(4) cmp_dbginit118 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp6_usd0), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(118) );
dbginit_inst #(4) cmp_dbginit119 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp6_usd1), .expected (4'h2),.cnt_val(cmp_cnt), .mon_num(119) );
dbginit_inst #(4) cmp_dbginit120 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp6_usd2), .expected (4'h4),.cnt_val(cmp_cnt), .mon_num(120) );
dbginit_inst #(4) cmp_dbginit121 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp6_usd3), .expected (4'h8),.cnt_val(cmp_cnt), .mon_num(121) );
dbginit_inst #(5) cmp_dbginit122 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp6_q), .expected (5'h1f),.cnt_val(cmp_cnt), .mon_num(122) );
dbginit_inst #(4) cmp_dbginit123 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp6_pv), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(123) );
`endif
`ifdef RTL_SPARC7
dbginit_inst #(4) cmp_dbginit124 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp7_usd0), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(124) );
dbginit_inst #(4) cmp_dbginit125 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp7_usd1), .expected (4'h2),.cnt_val(cmp_cnt), .mon_num(125) );
dbginit_inst #(4) cmp_dbginit126 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp7_usd2), .expected (4'h4),.cnt_val(cmp_cnt), .mon_num(126) );
dbginit_inst #(4) cmp_dbginit127 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp7_usd3), .expected (4'h8),.cnt_val(cmp_cnt), .mon_num(127) );
dbginit_inst #(5) cmp_dbginit128 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp7_q), .expected (5'h1f),.cnt_val(cmp_cnt), .mon_num(128) );
dbginit_inst #(4) cmp_dbginit129 ( .rst (cmp_rst), .clk (cmp_clk), .dbginit (cmp_dbginit), .actual (sp7_pv), .expected (4'b1),.cnt_val(cmp_cnt), .mon_num(129) );
`endif
// dram clk
dbginit_inst #(33) dram_dbginit1 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q0scbad), .expected (33'b0),.cnt_val(dram_cnt), .mon_num(130) );
dbginit_inst #(9) dram_dbginit2 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q0scbca), .expected ( 9'b0),.cnt_val(dram_cnt), .mon_num(131) );
dbginit_inst #(1) dram_dbginit3 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q0scbrk), .expected ( 1'b0),.cnt_val(dram_cnt), .mon_num(132) );
dbginit_inst #(15) dram_dbginit4 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q0scbrs), .expected (15'b0),.cnt_val(dram_cnt), .mon_num(133) );
dbginit_inst #(1) dram_dbginit5 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q0scbsk), .expected ( 1'b0),.cnt_val(dram_cnt), .mon_num(134) );
dbginit_inst #(3) dram_dbginit6 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q0scbbk), .expected ( 3'b0),.cnt_val(dram_cnt), .mon_num(135) );
dbginit_inst #(33) dram_dbginit7 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q1scbad), .expected (33'b0),.cnt_val(dram_cnt), .mon_num(136) );
dbginit_inst #(9) dram_dbginit8 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q1scbca), .expected ( 9'b0),.cnt_val(dram_cnt), .mon_num(137) );
dbginit_inst #(1) dram_dbginit9 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q1scbrk), .expected ( 1'b0),.cnt_val(dram_cnt), .mon_num(138) );
dbginit_inst #(15) dram_dbginit10 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q1scbrs), .expected (15'b0),.cnt_val(dram_cnt), .mon_num(139) );
dbginit_inst #(1) dram_dbginit11 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q1scbsk), .expected ( 1'b0),.cnt_val(dram_cnt), .mon_num(140) );
dbginit_inst #(3) dram_dbginit12 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr02_q1scbbk), .expected ( 3'b0),.cnt_val(dram_cnt), .mon_num(141) );
dbginit_inst #(33) dram_dbginit13 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q0scbad), .expected (33'b0),.cnt_val(dram_cnt), .mon_num(142) );
dbginit_inst #(9) dram_dbginit14 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q0scbca), .expected ( 9'b0),.cnt_val(dram_cnt), .mon_num(143) );
dbginit_inst #(1) dram_dbginit15 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q0scbrk), .expected ( 1'b0),.cnt_val(dram_cnt), .mon_num(144) );
dbginit_inst #(15) dram_dbginit16 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q0scbrs), .expected (15'b0),.cnt_val(dram_cnt), .mon_num(145) );
dbginit_inst #(1) dram_dbginit17 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q0scbsk), .expected ( 1'b0),.cnt_val(dram_cnt), .mon_num(146) );
dbginit_inst #(3) dram_dbginit18 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q0scbbk), .expected ( 3'b0),.cnt_val(dram_cnt), .mon_num(147) );
dbginit_inst #(33) dram_dbginit19 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q1scbad), .expected (33'b0),.cnt_val(dram_cnt), .mon_num(148) );
dbginit_inst #(9) dram_dbginit20 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q1scbca), .expected ( 9'b0),.cnt_val(dram_cnt), .mon_num(149) );
dbginit_inst #(1) dram_dbginit21 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q1scbrk), .expected ( 1'b0),.cnt_val(dram_cnt), .mon_num(150) );
dbginit_inst #(15) dram_dbginit22 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q1scbrs), .expected (15'b0),.cnt_val(dram_cnt), .mon_num(151) );
dbginit_inst #(1) dram_dbginit23 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q1scbsk), .expected ( 1'b0),.cnt_val(dram_cnt), .mon_num(152) );
dbginit_inst #(3) dram_dbginit24 ( .rst(dram_rst), .clk (dram_clk), .dbginit (dram_dbginit), .actual (dr13_q1scbbk), .expected ( 3'b0),.cnt_val(dram_cnt), .mon_num(153) );
// jbus clock
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
assign valid_test_expr = ~((^test_expr) ^ (^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if ((^(test_expr)) == 1'b1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression does not exhibit even parity");
end
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @(posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
reg [width-1:0] prev_test_expr;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_SANITY_ON) begin //sanity coverage
if (test_expr != prev_test_expr) begin
ovl_cover_t("test_expr_change covered");
end
prev_test_expr <= test_expr;
end //sanity coverage
end // OVL_COVER_NONE
end
else begin
`ifdef OVL_INIT_REG
prev_test_expr <= {width{1'b0}};
`endif
end
end //always
`endif // OVL_COVER_ON
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sat May 27 21:25:06 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_rgb888_to_g8_0_0 -prefix
// system_rgb888_to_g8_0_0_ system_rgb888_to_g8_0_0_stub.v
// Design : system_rgb888_to_g8_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb888_to_g8,Vivado 2016.4" *)
module system_rgb888_to_g8_0_0(clk, rgb888, g8)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb888[23:0],g8[7:0]" */;
input clk;
input [23:0]rgb888;
output [7:0]g8;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBN_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFBBN_BLACKBOX_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBN_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DECAP_FUNCTIONAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFRTP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_BLACKBOX_V
|
module ibex_load_store_unit (
clk_i,
rst_ni,
data_req_o,
data_gnt_i,
data_rvalid_i,
data_err_i,
data_pmp_err_i,
data_addr_o,
data_we_o,
data_be_o,
data_wdata_o,
data_rdata_i,
data_we_ex_i,
data_type_ex_i,
data_wdata_ex_i,
data_sign_ext_ex_i,
data_rdata_ex_o,
data_req_ex_i,
adder_result_ex_i,
addr_incr_req_o,
addr_last_o,
data_valid_o,
load_err_o,
store_err_o,
busy_o,
illegal_insn_id_i,
instr_valid_id_i
);
localparam [2:0] IDLE = 0;
localparam [2:0] WAIT_GNT_MIS = 1;
localparam [2:0] WAIT_RVALID_MIS = 2;
localparam [2:0] WAIT_GNT = 3;
localparam [2:0] WAIT_RVALID = 4;
localparam [2:0] WAIT_RVALID_DONE = 5;
input wire clk_i;
input wire rst_ni;
output reg data_req_o;
input wire data_gnt_i;
input wire data_rvalid_i;
input wire data_err_i;
input wire data_pmp_err_i;
output wire [31:0] data_addr_o;
output wire data_we_o;
output wire [3:0] data_be_o;
output wire [31:0] data_wdata_o;
input wire [31:0] data_rdata_i;
input wire data_we_ex_i;
input wire [1:0] data_type_ex_i;
input wire [31:0] data_wdata_ex_i;
input wire data_sign_ext_ex_i;
output wire [31:0] data_rdata_ex_o;
input wire data_req_ex_i;
input wire [31:0] adder_result_ex_i;
output reg addr_incr_req_o;
output wire [31:0] addr_last_o;
output reg data_valid_o;
output wire load_err_o;
output wire store_err_o;
output wire busy_o;
input wire illegal_insn_id_i;
input wire instr_valid_id_i;
wire [31:0] data_addr;
wire [31:0] data_addr_w_aligned;
reg [31:0] addr_last_q;
reg addr_update;
reg ctrl_update;
reg rdata_update;
reg [31:8] rdata_q;
reg [1:0] rdata_offset_q;
reg [1:0] data_type_q;
reg data_sign_ext_q;
reg data_we_q;
wire [1:0] data_offset;
reg [3:0] data_be;
reg [31:0] data_wdata;
reg [31:0] data_rdata_ext;
reg [31:0] rdata_w_ext;
reg [31:0] rdata_h_ext;
reg [31:0] rdata_b_ext;
wire split_misaligned_access;
reg handle_misaligned_q;
reg handle_misaligned_d;
reg pmp_err_q;
reg pmp_err_d;
reg lsu_err_q;
reg lsu_err_d;
reg data_or_pmp_err;
reg [2:0] ls_fsm_cs;
reg [2:0] ls_fsm_ns;
assign data_addr = adder_result_ex_i;
assign data_offset = data_addr[1:0];
always @(*)
case (data_type_ex_i)
2'b00:
if (!handle_misaligned_q)
case (data_offset)
2'b00: data_be = 4'b1111;
2'b01: data_be = 4'b1110;
2'b10: data_be = 4'b1100;
2'b11: data_be = 4'b1000;
default: data_be = 4'b1111;
endcase
else
case (data_offset)
2'b00: data_be = 4'b0000;
2'b01: data_be = 4'b0001;
2'b10: data_be = 4'b0011;
2'b11: data_be = 4'b0111;
default: data_be = 4'b1111;
endcase
2'b01:
if (!handle_misaligned_q)
case (data_offset)
2'b00: data_be = 4'b0011;
2'b01: data_be = 4'b0110;
2'b10: data_be = 4'b1100;
2'b11: data_be = 4'b1000;
default: data_be = 4'b1111;
endcase
else
data_be = 4'b0001;
2'b10, 2'b11:
case (data_offset)
2'b00: data_be = 4'b0001;
2'b01: data_be = 4'b0010;
2'b10: data_be = 4'b0100;
2'b11: data_be = 4'b1000;
default: data_be = 4'b1111;
endcase
default: data_be = 4'b1111;
endcase
always @(*)
case (data_offset)
2'b00: data_wdata = data_wdata_ex_i[31:0];
2'b01: data_wdata = {data_wdata_ex_i[23:0], data_wdata_ex_i[31:24]};
2'b10: data_wdata = {data_wdata_ex_i[15:0], data_wdata_ex_i[31:16]};
2'b11: data_wdata = {data_wdata_ex_i[7:0], data_wdata_ex_i[31:8]};
default: data_wdata = data_wdata_ex_i[31:0];
endcase
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
rdata_q <= 1'sb0;
else if (rdata_update)
rdata_q <= data_rdata_i[31:8];
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
rdata_offset_q <= 2'h0;
data_type_q <= 2'h0;
data_sign_ext_q <= 1'b0;
data_we_q <= 1'b0;
end
else if (ctrl_update) begin
rdata_offset_q <= data_offset;
data_type_q <= data_type_ex_i;
data_sign_ext_q <= data_sign_ext_ex_i;
data_we_q <= data_we_ex_i;
end
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
addr_last_q <= 1'sb0;
else if (addr_update)
addr_last_q <= data_addr;
always @(*)
case (rdata_offset_q)
2'b00: rdata_w_ext = data_rdata_i[31:0];
2'b01: rdata_w_ext = {data_rdata_i[7:0], rdata_q[31:8]};
2'b10: rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]};
2'b11: rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]};
default: rdata_w_ext = data_rdata_i[31:0];
endcase
always @(*)
case (rdata_offset_q)
2'b00:
if (!data_sign_ext_q)
rdata_h_ext = {16'h0000, data_rdata_i[15:0]};
else
rdata_h_ext = {{16 {data_rdata_i[15]}}, data_rdata_i[15:0]};
2'b01:
if (!data_sign_ext_q)
rdata_h_ext = {16'h0000, data_rdata_i[23:8]};
else
rdata_h_ext = {{16 {data_rdata_i[23]}}, data_rdata_i[23:8]};
2'b10:
if (!data_sign_ext_q)
rdata_h_ext = {16'h0000, data_rdata_i[31:16]};
else
rdata_h_ext = {{16 {data_rdata_i[31]}}, data_rdata_i[31:16]};
2'b11:
if (!data_sign_ext_q)
rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]};
else
rdata_h_ext = {{16 {data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]};
default: rdata_h_ext = {16'h0000, data_rdata_i[15:0]};
endcase
always @(*)
case (rdata_offset_q)
2'b00:
if (!data_sign_ext_q)
rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]};
else
rdata_b_ext = {{24 {data_rdata_i[7]}}, data_rdata_i[7:0]};
2'b01:
if (!data_sign_ext_q)
rdata_b_ext = {24'h00_0000, data_rdata_i[15:8]};
else
rdata_b_ext = {{24 {data_rdata_i[15]}}, data_rdata_i[15:8]};
2'b10:
if (!data_sign_ext_q)
rdata_b_ext = {24'h00_0000, data_rdata_i[23:16]};
else
rdata_b_ext = {{24 {data_rdata_i[23]}}, data_rdata_i[23:16]};
2'b11:
if (!data_sign_ext_q)
rdata_b_ext = {24'h00_0000, data_rdata_i[31:24]};
else
rdata_b_ext = {{24 {data_rdata_i[31]}}, data_rdata_i[31:24]};
default: rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]};
endcase
always @(*)
case (data_type_q)
2'b00: data_rdata_ext = rdata_w_ext;
2'b01: data_rdata_ext = rdata_h_ext;
2'b10, 2'b11: data_rdata_ext = rdata_b_ext;
default: data_rdata_ext = rdata_w_ext;
endcase
assign split_misaligned_access = (((data_type_ex_i == 2'b00) && (data_offset != 2'b00)) || ((data_type_ex_i == 2'b01) && (data_offset == 2'b11)));
always @(*) begin
ls_fsm_ns = ls_fsm_cs;
data_req_o = 1'b0;
data_valid_o = 1'b0;
addr_incr_req_o = 1'b0;
handle_misaligned_d = handle_misaligned_q;
data_or_pmp_err = 1'b0;
pmp_err_d = pmp_err_q;
lsu_err_d = lsu_err_q;
addr_update = 1'b0;
ctrl_update = 1'b0;
rdata_update = 1'b0;
case (ls_fsm_cs)
IDLE:
if (data_req_ex_i) begin
data_req_o = 1'b1;
pmp_err_d = data_pmp_err_i;
lsu_err_d = 1'b0;
if (data_gnt_i) begin
ctrl_update = 1'b1;
addr_update = 1'b1;
handle_misaligned_d = split_misaligned_access;
ls_fsm_ns = (split_misaligned_access ? WAIT_RVALID_MIS : WAIT_RVALID);
end
else
ls_fsm_ns = (split_misaligned_access ? WAIT_GNT_MIS : WAIT_GNT);
end
WAIT_GNT_MIS: begin
data_req_o = 1'b1;
if ((data_gnt_i || pmp_err_q)) begin
addr_update = 1'b1;
ctrl_update = 1'b1;
handle_misaligned_d = 1'b1;
ls_fsm_ns = WAIT_RVALID_MIS;
end
end
WAIT_RVALID_MIS: begin
data_req_o = 1'b1;
addr_incr_req_o = 1'b1;
if ((data_rvalid_i || pmp_err_q)) begin
pmp_err_d = data_pmp_err_i;
lsu_err_d = (data_err_i | pmp_err_q);
rdata_update = ~data_we_q;
ls_fsm_ns = (data_gnt_i ? WAIT_RVALID : WAIT_GNT);
addr_update = (data_gnt_i & ~(data_err_i | pmp_err_q));
end
else if (data_gnt_i)
ls_fsm_ns = WAIT_RVALID_DONE;
end
WAIT_GNT: begin
addr_incr_req_o = handle_misaligned_q;
data_req_o = 1'b1;
if ((data_gnt_i || pmp_err_q)) begin
ctrl_update = 1'b1;
addr_update = ~lsu_err_q;
ls_fsm_ns = WAIT_RVALID;
end
end
WAIT_RVALID:
if ((data_rvalid_i || pmp_err_q)) begin
data_valid_o = 1'b1;
data_or_pmp_err = ((lsu_err_q | data_err_i) | pmp_err_q);
handle_misaligned_d = 1'b0;
ls_fsm_ns = IDLE;
end
else
ls_fsm_ns = WAIT_RVALID;
WAIT_RVALID_DONE: begin
addr_incr_req_o = 1'b1;
if (data_rvalid_i) begin
pmp_err_d = data_pmp_err_i;
lsu_err_d = data_err_i;
addr_update = ~data_err_i;
rdata_update = ~data_we_q;
ls_fsm_ns = WAIT_RVALID;
end
end
default: ls_fsm_ns = IDLE;
endcase
end
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
ls_fsm_cs <= IDLE;
handle_misaligned_q <= 1'sb0;
pmp_err_q <= 1'sb0;
lsu_err_q <= 1'sb0;
end
else begin
ls_fsm_cs <= ls_fsm_ns;
handle_misaligned_q <= handle_misaligned_d;
pmp_err_q <= pmp_err_d;
lsu_err_q <= lsu_err_d;
end
assign data_rdata_ex_o = data_rdata_ext;
assign data_addr_w_aligned = {data_addr[31:2], 2'b00};
assign data_addr_o = data_addr_w_aligned;
assign data_wdata_o = data_wdata;
assign data_we_o = data_we_ex_i;
assign data_be_o = data_be;
assign addr_last_o = addr_last_q;
assign load_err_o = (data_or_pmp_err & ~data_we_q);
assign store_err_o = (data_or_pmp_err & data_we_q);
assign busy_o = (ls_fsm_cs != IDLE);
wire unused_instr_valid_id;
wire unused_illegal_insn_id;
assign unused_instr_valid_id = instr_valid_id_i;
assign unused_illegal_insn_id = illegal_insn_id_i;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211O_1_V
`define SKY130_FD_SC_MS__A211O_1_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211o_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211O_1_V
|
//-----------------------------------------------------------------------------
// system_processing_system7_0_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "processing_system7_v4_03_a" *)
(* CORE_GENERATION_INFO = "processing_system7_0,processing_system7,{C_UART1_PERIPHERAL_ENABLE = 1,C_UART1_UART1_IO = MIO 48 .. 49,C_UART1_GRP_FULL_ENABLE = 0,C_SD0_GRP_WP_ENABLE = 1,C_SD0_PERIPHERAL_ENABLE = 1,C_SD0_GRP_CD_IO = MIO 47,C_SD0_GRP_POW_ENABLE = 0,C_SD0_GRP_WP_IO = MIO 46,C_SD0_GRP_CD_ENABLE = 1,C_TTC0_TTC0_IO = EMIO,C_TTC0_PERIPHERAL_ENABLE = 1,C_ENET0_GRP_MDIO_IO = MIO 52 .. 53,C_ENET0_ENET0_IO = MIO 16 .. 27,C_ENET0_PERIPHERAL_ENABLE = 1,C_ENET0_GRP_MDIO_ENABLE = 1,C_PJTAG_PERIPHERAL_ENABLE = 0,C_MIO_MIO[2]_PULLUP = disabled,C_MIO_MIO[2]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[2]_SLEW = fast,C_MIO_MIO[1]_SLEW = fast,C_MIO_MIO[0]_PULLUP = disabled,C_MIO_MIO[0]_SLEW = slow,C_MIO_MIO[1]_PULLUP = disabled,C_MIO_MIO[1]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[0]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[13]_PULLUP = disabled,C_MIO_MIO[13]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[13]_SLEW = slow,C_MIO_MIO[12]_PULLUP = disabled,C_MIO_MIO[12]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[12]_SLEW = slow,C_MIO_MIO[11]_PULLUP = disabled,C_MIO_MIO[11]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[11]_SLEW = slow,C_MIO_MIO[10]_SLEW = slow,C_MIO_MIO[10]_PULLUP = disabled,C_MIO_MIO[10]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[15]_PULLUP = disabled,C_MIO_MIO[15]_SLEW = slow,C_MIO_MIO[14]_PULLUP = disabled,C_MIO_MIO[14]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[15]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[14]_SLEW = slow,C_MIO_MIO[22]_PULLUP = disabled,C_MIO_MIO[22]_SLEW = fast,C_MIO_MIO[21]_PULLUP = disabled,C_MIO_MIO[21]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[20]_SLEW = fast,C_MIO_MIO[19]_PULLUP = disabled,C_MIO_MIO[19]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[18]_SLEW = fast,C_MIO_MIO[17]_PULLUP = disabled,C_MIO_MIO[17]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[16]_SLEW = fast,C_MIO_MIO[22]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[21]_SLEW = fast,C_MIO_MIO[20]_PULLUP = disabled,C_MIO_MIO[20]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[19]_SLEW = fast,C_MIO_MIO[18]_PULLUP = disabled,C_MIO_MIO[18]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[17]_SLEW = fast,C_MIO_MIO[16]_PULLUP = disabled,C_MIO_MIO[16]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[23]_PULLUP = disabled,C_MIO_MIO[23]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[25]_PULLUP = disabled,C_MIO_MIO[25]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[25]_SLEW = fast,C_MIO_MIO[24]_PULLUP = disabled,C_MIO_MIO[24]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[24]_SLEW = fast,C_MIO_MIO[23]_SLEW = fast,C_MIO_MIO[30]_PULLUP = disabled,C_MIO_MIO[30]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[30]_SLEW = fast,C_MIO_MIO[29]_PULLUP = disabled,C_MIO_MIO[29]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[28]_SLEW = fast,C_MIO_MIO[27]_PULLUP = disabled,C_MIO_MIO[27]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[26]_SLEW = fast,C_MIO_MIO[29]_SLEW = fast,C_MIO_MIO[28]_PULLUP = disabled,C_MIO_MIO[28]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[27]_SLEW = fast,C_MIO_MIO[26]_PULLUP = disabled,C_MIO_MIO[26]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[36]_SLEW = fast,C_MIO_MIO[35]_PULLUP = disabled,C_MIO_MIO[35]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[34]_SLEW = fast,C_MIO_MIO[33]_PULLUP = disabled,C_MIO_MIO[33]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[32]_SLEW = fast,C_MIO_MIO[31]_PULLUP = disabled,C_MIO_MIO[31]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[37]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[37]_SLEW = fast,C_MIO_MIO[36]_PULLUP = disabled,C_MIO_MIO[36]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[35]_SLEW = fast,C_MIO_MIO[34]_PULLUP = disabled,C_MIO_MIO[34]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[33]_SLEW = fast,C_MIO_MIO[32]_PULLUP = disabled,C_MIO_MIO[32]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[31]_SLEW = fast,C_MIO_MIO[37]_PULLUP = disabled,C_MIO_MIO[39]_PULLUP = disabled,C_MIO_MIO[39]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[39]_SLEW = fast,C_MIO_MIO[38]_PULLUP = disabled,C_MIO_MIO[38]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[38]_SLEW = fast,C_MIO_MIO[43]_PULLUP = disabled,C_MIO_MIO[43]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[42]_SLEW = fast,C_MIO_MIO[41]_PULLUP = disabled,C_MIO_MIO[41]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[45]_PULLUP = disabled,C_MIO_MIO[45]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[45]_SLEW = fast,C_MIO_MIO[44]_PULLUP = disabled,C_MIO_MIO[44]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[44]_SLEW = fast,C_MIO_MIO[43]_SLEW = fast,C_MIO_MIO[42]_PULLUP = disabled,C_MIO_MIO[42]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[41]_SLEW = fast,C_MIO_MIO[40]_PULLUP = disabled,C_MIO_MIO[40]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[40]_SLEW = fast,C_MIO_MIO[52]_PULLUP = disabled,C_MIO_MIO[52]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[51]_DIRECTION = in,C_MIO_MIO[50]_PULLUP = disabled,C_MIO_MIO[50]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[48]_PULLUP = disabled,C_MIO_MIO[48]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[46]_PULLUP = disabled,C_MIO_MIO[46]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[51]_PULLUP = disabled,C_MIO_MIO[51]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[50]_DIRECTION = in,C_MIO_MIO[49]_PULLUP = disabled,C_MIO_MIO[49]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[47]_PULLUP = disabled,C_MIO_MIO[47]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[53]_PULLUP = disabled,C_MIO_MIO[53]_IOTYPE = LVCMOS 1.8V,C_UIPARAM_DDR_BOARD_DELAY2 = 0.341,C_UIPARAM_DDR_BOARD_DELAY0 = 0.41,C_UIPARAM_DDR_USE_INTERNAL_VREF = 1,C_UIPARAM_DDR_TRAIN_READ_GATE = 1,C_UIPARAM_DDR_BOARD_DELAY3 = 0.358,C_UIPARAM_DDR_BOARD_DELAY1 = 0.411,C_UIPARAM_DDR_TRAIN_DATA_EYE = 1,C_UIPARAM_DDR_TRAIN_WRITE_LEVEL = 1,C_DDR_V4.00.A_C_S_AXI_HP3_HIGHADDR = 0x1FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP2_HIGHADDR = 0x1FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP1_HIGHADDR = 0x1FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP0_HIGHADDR = 0x1FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP3_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP2_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP1_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP0_BASEADDR = 0x00000000,C_GPIO_GPIO_IO = MIO,C_GPIO_PERIPHERAL_ENABLE = 1,C:GPIO_EMIO_GPIO_WIDTH = 64,C_CAN_PERIPHERAL_FREQMHZ = 100,C_UART_PERIPHERAL_FREQMHZ = 50,C_ENET0_PERIPHERAL_FREQMHZ = 1000 Mbps,C_QSPI_PERIPHERAL_FREQMHZ = 200.000000,C_FPGA3_PERIPHERAL_FREQMHZ = 50.000000,C_FPGA1_PERIPHERAL_FREQMHZ = 150.000000,C_APU_PERIPHERAL_FREQMHZ = 666.666667,C_PRESET_GLOBAL_DEFAULT = powerup,C_SDIO_PERIPHERAL_FREQMHZ = 50,C_FPGA2_PERIPHERAL_FREQMHZ = 50.000000,C_FPGA0_PERIPHERAL_FREQMHZ = 100.000000,C_PRESET_GLOBAL_CONFIG = Default,C_PRESET_BANK0_VOLTAGE = LVCMOS 3.3V,C_PRESET_FPGA_SPEED = -1,C_PRESET_BANK1_VOLTAGE = LVCMOS 1.8V,C_PRESET_FPGA_PARTNUMBER = xc7z020clg484-1,C_USB0_USB0_IO = MIO 28 .. 39,C_USB0_PERIPHERAL_ENABLE = 1,C_QSPI_PERIPHERAL_ENABLE = 1,C_QSPI_QSPI_IO = MIO 1 .. 6,C_MIO_MIO[3]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[3]_SLEW = fast,C_MIO_MIO[3]_PULLUP = disabled,C_MIO_MIO[6]_PULLUP = disabled,C_MIO_MIO[6]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[6]_SLEW = fast,C_MIO_MIO[5]_PULLUP = disabled,C_MIO_MIO[5]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[5]_SLEW = fast,C_MIO_MIO[4]_PULLUP = disabled,C_MIO_MIO[4]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[4]_SLEW = fast,C_MIO_MIO[9]_PULLUP = disabled,C_MIO_MIO[9]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[9]_SLEW = slow,C_MIO_MIO[8]_PULLUP = disabled,C_MIO_MIO[8]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[8]_SLEW = fast,C_MIO_MIO[7]_PULLUP = disabled,C_MIO_MIO[7]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[7]_SLEW = slow,C_I2C0_PERIPHERAL_ENABLE = 0,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 = -0.061,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 = 0.028,C_UIPARAM_DDR_T_RAS_MIN = 36.0,C_UIPARAM_DDR_T_RP = 7,C_UIPARAM_DDR_CWL = 6,C_UIPARAM_DDR_FREQ_MHZ = 533.333313,C_UIPARAM_DDR_SPEED_BIN = DDR3_1066F,C_UIPARAM_DDR_DEVICE_CAPACITY = 2048 MBits,C_UIPARAM_DDR_BL = 8,C_UIPARAM_DDR_MEMORY_TYPE = DDR 3,C_UIPARAM_DDR_DRAM_WIDTH = 16 Bits,C_UIPARAM_DDR_PARTNO = MT41J128M16 HA-15E,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 = -0.009,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 = 0.025,C_UIPARAM_DDR_T_FAW = 45.0,C_UIPARAM_DDR_T_RC = 49.5,C_UIPARAM_DDR_T_RCD = 7,C_UIPARAM_DDR_CL = 7,C_UIPARAM_DDR_ROW_ADDR_COUNT = 14}" *)
module system_processing_system7_0_wrapper
(
CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_EXT_INTIN,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_EXT_INTIN,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TD_I,
PJTAG_TD_T,
PJTAG_TD_O,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
USB0_PORT_INDCTL,
USB1_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB1_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_AWREADY,
S_AXI_ACP_ARREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA0_DRTYPE,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA1_DRTYPE,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_DRVALID,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA2_DRTYPE,
DMA3_DRTYPE,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG,
FTMT_F2P_TRIGACK,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK,
FTMT_P2F_TRIG,
FTMT_P2F_DEBUG,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FPGA_IDLE_N,
DDR_ARB,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
MIO,
DDR_Clk,
DDR_Clk_n,
DDR_CKE,
DDR_CS_n,
DDR_RAS_n,
DDR_CAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_ODT,
DDR_DRSTB,
DDR_DQ,
DDR_DM,
DDR_DQS,
DDR_DQS_n,
DDR_VRN,
DDR_VRP,
PS_SRSTB,
PS_CLK,
PS_PORB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1
);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0] ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_EXT_INTIN;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input [7:0] ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0] ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_EXT_INTIN;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input [7:0] ENET1_GMII_RXD;
input [63:0] GPIO_I;
output [63:0] GPIO_O;
output [63:0] GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TD_I;
output PJTAG_TD_T;
output PJTAG_TD_O;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0] SDIO0_DATA_I;
output [3:0] SDIO0_DATA_O;
output [3:0] SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0] SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0] SDIO1_DATA_I;
output [3:0] SDIO1_DATA_O;
output [3:0] SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0] SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [31:0] TRACE_DATA;
output [1:0] USB0_PORT_INDCTL;
output [1:0] USB1_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
output USB1_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0] M_AXI_GP0_ARID;
output [11:0] M_AXI_GP0_AWID;
output [11:0] M_AXI_GP0_WID;
output [1:0] M_AXI_GP0_ARBURST;
output [1:0] M_AXI_GP0_ARLOCK;
output [2:0] M_AXI_GP0_ARSIZE;
output [1:0] M_AXI_GP0_AWBURST;
output [1:0] M_AXI_GP0_AWLOCK;
output [2:0] M_AXI_GP0_AWSIZE;
output [2:0] M_AXI_GP0_ARPROT;
output [2:0] M_AXI_GP0_AWPROT;
output [31:0] M_AXI_GP0_ARADDR;
output [31:0] M_AXI_GP0_AWADDR;
output [31:0] M_AXI_GP0_WDATA;
output [3:0] M_AXI_GP0_ARCACHE;
output [3:0] M_AXI_GP0_ARLEN;
output [3:0] M_AXI_GP0_ARQOS;
output [3:0] M_AXI_GP0_AWCACHE;
output [3:0] M_AXI_GP0_AWLEN;
output [3:0] M_AXI_GP0_AWQOS;
output [3:0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0] M_AXI_GP0_BID;
input [11:0] M_AXI_GP0_RID;
input [1:0] M_AXI_GP0_BRESP;
input [1:0] M_AXI_GP0_RRESP;
input [31:0] M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0] M_AXI_GP1_ARID;
output [11:0] M_AXI_GP1_AWID;
output [11:0] M_AXI_GP1_WID;
output [1:0] M_AXI_GP1_ARBURST;
output [1:0] M_AXI_GP1_ARLOCK;
output [2:0] M_AXI_GP1_ARSIZE;
output [1:0] M_AXI_GP1_AWBURST;
output [1:0] M_AXI_GP1_AWLOCK;
output [2:0] M_AXI_GP1_AWSIZE;
output [2:0] M_AXI_GP1_ARPROT;
output [2:0] M_AXI_GP1_AWPROT;
output [31:0] M_AXI_GP1_ARADDR;
output [31:0] M_AXI_GP1_AWADDR;
output [31:0] M_AXI_GP1_WDATA;
output [3:0] M_AXI_GP1_ARCACHE;
output [3:0] M_AXI_GP1_ARLEN;
output [3:0] M_AXI_GP1_ARQOS;
output [3:0] M_AXI_GP1_AWCACHE;
output [3:0] M_AXI_GP1_AWLEN;
output [3:0] M_AXI_GP1_AWQOS;
output [3:0] M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0] M_AXI_GP1_BID;
input [11:0] M_AXI_GP1_RID;
input [1:0] M_AXI_GP1_BRESP;
input [1:0] M_AXI_GP1_RRESP;
input [31:0] M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0] S_AXI_GP0_BRESP;
output [1:0] S_AXI_GP0_RRESP;
output [31:0] S_AXI_GP0_RDATA;
output [5:0] S_AXI_GP0_BID;
output [5:0] S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0] S_AXI_GP0_ARBURST;
input [1:0] S_AXI_GP0_ARLOCK;
input [2:0] S_AXI_GP0_ARSIZE;
input [1:0] S_AXI_GP0_AWBURST;
input [1:0] S_AXI_GP0_AWLOCK;
input [2:0] S_AXI_GP0_AWSIZE;
input [2:0] S_AXI_GP0_ARPROT;
input [2:0] S_AXI_GP0_AWPROT;
input [31:0] S_AXI_GP0_ARADDR;
input [31:0] S_AXI_GP0_AWADDR;
input [31:0] S_AXI_GP0_WDATA;
input [3:0] S_AXI_GP0_ARCACHE;
input [3:0] S_AXI_GP0_ARLEN;
input [3:0] S_AXI_GP0_ARQOS;
input [3:0] S_AXI_GP0_AWCACHE;
input [3:0] S_AXI_GP0_AWLEN;
input [3:0] S_AXI_GP0_AWQOS;
input [3:0] S_AXI_GP0_WSTRB;
input [5:0] S_AXI_GP0_ARID;
input [5:0] S_AXI_GP0_AWID;
input [5:0] S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0] S_AXI_GP1_BRESP;
output [1:0] S_AXI_GP1_RRESP;
output [31:0] S_AXI_GP1_RDATA;
output [5:0] S_AXI_GP1_BID;
output [5:0] S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0] S_AXI_GP1_ARBURST;
input [1:0] S_AXI_GP1_ARLOCK;
input [2:0] S_AXI_GP1_ARSIZE;
input [1:0] S_AXI_GP1_AWBURST;
input [1:0] S_AXI_GP1_AWLOCK;
input [2:0] S_AXI_GP1_AWSIZE;
input [2:0] S_AXI_GP1_ARPROT;
input [2:0] S_AXI_GP1_AWPROT;
input [31:0] S_AXI_GP1_ARADDR;
input [31:0] S_AXI_GP1_AWADDR;
input [31:0] S_AXI_GP1_WDATA;
input [3:0] S_AXI_GP1_ARCACHE;
input [3:0] S_AXI_GP1_ARLEN;
input [3:0] S_AXI_GP1_ARQOS;
input [3:0] S_AXI_GP1_AWCACHE;
input [3:0] S_AXI_GP1_AWLEN;
input [3:0] S_AXI_GP1_AWQOS;
input [3:0] S_AXI_GP1_WSTRB;
input [5:0] S_AXI_GP1_ARID;
input [5:0] S_AXI_GP1_AWID;
input [5:0] S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0] S_AXI_ACP_BRESP;
output [1:0] S_AXI_ACP_RRESP;
output [2:0] S_AXI_ACP_BID;
output [2:0] S_AXI_ACP_RID;
output [63:0] S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0] S_AXI_ACP_ARID;
input [2:0] S_AXI_ACP_ARPROT;
input [2:0] S_AXI_ACP_AWID;
input [2:0] S_AXI_ACP_AWPROT;
input [2:0] S_AXI_ACP_WID;
input [31:0] S_AXI_ACP_ARADDR;
input [31:0] S_AXI_ACP_AWADDR;
input [3:0] S_AXI_ACP_ARCACHE;
input [3:0] S_AXI_ACP_ARLEN;
input [3:0] S_AXI_ACP_ARQOS;
input [3:0] S_AXI_ACP_AWCACHE;
input [3:0] S_AXI_ACP_AWLEN;
input [3:0] S_AXI_ACP_AWQOS;
input [1:0] S_AXI_ACP_ARBURST;
input [1:0] S_AXI_ACP_ARLOCK;
input [2:0] S_AXI_ACP_ARSIZE;
input [1:0] S_AXI_ACP_AWBURST;
input [1:0] S_AXI_ACP_AWLOCK;
input [2:0] S_AXI_ACP_AWSIZE;
input [4:0] S_AXI_ACP_ARUSER;
input [4:0] S_AXI_ACP_AWUSER;
input [63:0] S_AXI_ACP_WDATA;
input [7:0] S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0] S_AXI_HP0_BRESP;
output [1:0] S_AXI_HP0_RRESP;
output [1:0] S_AXI_HP0_BID;
output [1:0] S_AXI_HP0_RID;
output [63:0] S_AXI_HP0_RDATA;
output [7:0] S_AXI_HP0_RCOUNT;
output [7:0] S_AXI_HP0_WCOUNT;
output [2:0] S_AXI_HP0_RACOUNT;
output [5:0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0] S_AXI_HP0_ARBURST;
input [1:0] S_AXI_HP0_ARLOCK;
input [2:0] S_AXI_HP0_ARSIZE;
input [1:0] S_AXI_HP0_AWBURST;
input [1:0] S_AXI_HP0_AWLOCK;
input [2:0] S_AXI_HP0_AWSIZE;
input [2:0] S_AXI_HP0_ARPROT;
input [2:0] S_AXI_HP0_AWPROT;
input [31:0] S_AXI_HP0_ARADDR;
input [31:0] S_AXI_HP0_AWADDR;
input [3:0] S_AXI_HP0_ARCACHE;
input [3:0] S_AXI_HP0_ARLEN;
input [3:0] S_AXI_HP0_ARQOS;
input [3:0] S_AXI_HP0_AWCACHE;
input [3:0] S_AXI_HP0_AWLEN;
input [3:0] S_AXI_HP0_AWQOS;
input [1:0] S_AXI_HP0_ARID;
input [1:0] S_AXI_HP0_AWID;
input [1:0] S_AXI_HP0_WID;
input [63:0] S_AXI_HP0_WDATA;
input [7:0] S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0] S_AXI_HP1_BRESP;
output [1:0] S_AXI_HP1_RRESP;
output [5:0] S_AXI_HP1_BID;
output [5:0] S_AXI_HP1_RID;
output [63:0] S_AXI_HP1_RDATA;
output [7:0] S_AXI_HP1_RCOUNT;
output [7:0] S_AXI_HP1_WCOUNT;
output [2:0] S_AXI_HP1_RACOUNT;
output [5:0] S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0] S_AXI_HP1_ARBURST;
input [1:0] S_AXI_HP1_ARLOCK;
input [2:0] S_AXI_HP1_ARSIZE;
input [1:0] S_AXI_HP1_AWBURST;
input [1:0] S_AXI_HP1_AWLOCK;
input [2:0] S_AXI_HP1_AWSIZE;
input [2:0] S_AXI_HP1_ARPROT;
input [2:0] S_AXI_HP1_AWPROT;
input [31:0] S_AXI_HP1_ARADDR;
input [31:0] S_AXI_HP1_AWADDR;
input [3:0] S_AXI_HP1_ARCACHE;
input [3:0] S_AXI_HP1_ARLEN;
input [3:0] S_AXI_HP1_ARQOS;
input [3:0] S_AXI_HP1_AWCACHE;
input [3:0] S_AXI_HP1_AWLEN;
input [3:0] S_AXI_HP1_AWQOS;
input [5:0] S_AXI_HP1_ARID;
input [5:0] S_AXI_HP1_AWID;
input [5:0] S_AXI_HP1_WID;
input [63:0] S_AXI_HP1_WDATA;
input [7:0] S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0] S_AXI_HP2_BRESP;
output [1:0] S_AXI_HP2_RRESP;
output [5:0] S_AXI_HP2_BID;
output [5:0] S_AXI_HP2_RID;
output [63:0] S_AXI_HP2_RDATA;
output [7:0] S_AXI_HP2_RCOUNT;
output [7:0] S_AXI_HP2_WCOUNT;
output [2:0] S_AXI_HP2_RACOUNT;
output [5:0] S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0] S_AXI_HP2_ARBURST;
input [1:0] S_AXI_HP2_ARLOCK;
input [2:0] S_AXI_HP2_ARSIZE;
input [1:0] S_AXI_HP2_AWBURST;
input [1:0] S_AXI_HP2_AWLOCK;
input [2:0] S_AXI_HP2_AWSIZE;
input [2:0] S_AXI_HP2_ARPROT;
input [2:0] S_AXI_HP2_AWPROT;
input [31:0] S_AXI_HP2_ARADDR;
input [31:0] S_AXI_HP2_AWADDR;
input [3:0] S_AXI_HP2_ARCACHE;
input [3:0] S_AXI_HP2_ARLEN;
input [3:0] S_AXI_HP2_ARQOS;
input [3:0] S_AXI_HP2_AWCACHE;
input [3:0] S_AXI_HP2_AWLEN;
input [3:0] S_AXI_HP2_AWQOS;
input [5:0] S_AXI_HP2_ARID;
input [5:0] S_AXI_HP2_AWID;
input [5:0] S_AXI_HP2_WID;
input [63:0] S_AXI_HP2_WDATA;
input [7:0] S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0] S_AXI_HP3_BRESP;
output [1:0] S_AXI_HP3_RRESP;
output [5:0] S_AXI_HP3_BID;
output [5:0] S_AXI_HP3_RID;
output [63:0] S_AXI_HP3_RDATA;
output [7:0] S_AXI_HP3_RCOUNT;
output [7:0] S_AXI_HP3_WCOUNT;
output [2:0] S_AXI_HP3_RACOUNT;
output [5:0] S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0] S_AXI_HP3_ARBURST;
input [1:0] S_AXI_HP3_ARLOCK;
input [2:0] S_AXI_HP3_ARSIZE;
input [1:0] S_AXI_HP3_AWBURST;
input [1:0] S_AXI_HP3_AWLOCK;
input [2:0] S_AXI_HP3_AWSIZE;
input [2:0] S_AXI_HP3_ARPROT;
input [2:0] S_AXI_HP3_AWPROT;
input [31:0] S_AXI_HP3_ARADDR;
input [31:0] S_AXI_HP3_AWADDR;
input [3:0] S_AXI_HP3_ARCACHE;
input [3:0] S_AXI_HP3_ARLEN;
input [3:0] S_AXI_HP3_ARQOS;
input [3:0] S_AXI_HP3_AWCACHE;
input [3:0] S_AXI_HP3_AWLEN;
input [3:0] S_AXI_HP3_AWQOS;
input [5:0] S_AXI_HP3_ARID;
input [5:0] S_AXI_HP3_AWID;
input [5:0] S_AXI_HP3_WID;
input [63:0] S_AXI_HP3_WDATA;
input [7:0] S_AXI_HP3_WSTRB;
output [1:0] DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input [1:0] DMA0_DRTYPE;
output [1:0] DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input [1:0] DMA1_DRTYPE;
output [1:0] DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_DRVALID;
output [1:0] DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input [1:0] DMA2_DRTYPE;
input [1:0] DMA3_DRTYPE;
input [31:0] FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0] FTMD_TRACEIN_ATID;
input [3:0] FTMT_F2P_TRIG;
output [3:0] FTMT_F2P_TRIGACK;
input [31:0] FTMT_F2P_DEBUG;
input [3:0] FTMT_P2F_TRIGACK;
output [3:0] FTMT_P2F_TRIG;
output [31:0] FTMT_P2F_DEBUG;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input FPGA_IDLE_N;
input [3:0] DDR_ARB;
input [1:0] IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output EVENT_EVENTO;
output [1:0] EVENT_STANDBYWFE;
output [1:0] EVENT_STANDBYWFI;
input EVENT_EVENTI;
inout [53:0] MIO;
inout DDR_Clk;
inout DDR_Clk_n;
inout DDR_CKE;
inout DDR_CS_n;
inout DDR_RAS_n;
inout DDR_CAS_n;
output DDR_WEB;
inout [2:0] DDR_BankAddr;
inout [14:0] DDR_Addr;
inout DDR_ODT;
inout DDR_DRSTB;
inout [31:0] DDR_DQ;
inout [3:0] DDR_DM;
inout [3:0] DDR_DQS;
inout [3:0] DDR_DQS_n;
inout DDR_VRN;
inout DDR_VRP;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
(* CORE_GENERATION_INFO = "processing_system7_0,processing_system7,{C_UART1_PERIPHERAL_ENABLE = 1,C_UART1_UART1_IO = MIO 48 .. 49,C_UART1_GRP_FULL_ENABLE = 0,C_SD0_GRP_WP_ENABLE = 1,C_SD0_PERIPHERAL_ENABLE = 1,C_SD0_GRP_CD_IO = MIO 47,C_SD0_GRP_POW_ENABLE = 0,C_SD0_GRP_WP_IO = MIO 46,C_SD0_GRP_CD_ENABLE = 1,C_TTC0_TTC0_IO = EMIO,C_TTC0_PERIPHERAL_ENABLE = 1,C_ENET0_GRP_MDIO_IO = MIO 52 .. 53,C_ENET0_ENET0_IO = MIO 16 .. 27,C_ENET0_PERIPHERAL_ENABLE = 1,C_ENET0_GRP_MDIO_ENABLE = 1,C_PJTAG_PERIPHERAL_ENABLE = 0,C_MIO_MIO[2]_PULLUP = disabled,C_MIO_MIO[2]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[2]_SLEW = fast,C_MIO_MIO[1]_SLEW = fast,C_MIO_MIO[0]_PULLUP = disabled,C_MIO_MIO[0]_SLEW = slow,C_MIO_MIO[1]_PULLUP = disabled,C_MIO_MIO[1]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[0]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[13]_PULLUP = disabled,C_MIO_MIO[13]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[13]_SLEW = slow,C_MIO_MIO[12]_PULLUP = disabled,C_MIO_MIO[12]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[12]_SLEW = slow,C_MIO_MIO[11]_PULLUP = disabled,C_MIO_MIO[11]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[11]_SLEW = slow,C_MIO_MIO[10]_SLEW = slow,C_MIO_MIO[10]_PULLUP = disabled,C_MIO_MIO[10]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[15]_PULLUP = disabled,C_MIO_MIO[15]_SLEW = slow,C_MIO_MIO[14]_PULLUP = disabled,C_MIO_MIO[14]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[15]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[14]_SLEW = slow,C_MIO_MIO[22]_PULLUP = disabled,C_MIO_MIO[22]_SLEW = fast,C_MIO_MIO[21]_PULLUP = disabled,C_MIO_MIO[21]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[20]_SLEW = fast,C_MIO_MIO[19]_PULLUP = disabled,C_MIO_MIO[19]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[18]_SLEW = fast,C_MIO_MIO[17]_PULLUP = disabled,C_MIO_MIO[17]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[16]_SLEW = fast,C_MIO_MIO[22]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[21]_SLEW = fast,C_MIO_MIO[20]_PULLUP = disabled,C_MIO_MIO[20]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[19]_SLEW = fast,C_MIO_MIO[18]_PULLUP = disabled,C_MIO_MIO[18]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[17]_SLEW = fast,C_MIO_MIO[16]_PULLUP = disabled,C_MIO_MIO[16]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[23]_PULLUP = disabled,C_MIO_MIO[23]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[25]_PULLUP = disabled,C_MIO_MIO[25]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[25]_SLEW = fast,C_MIO_MIO[24]_PULLUP = disabled,C_MIO_MIO[24]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[24]_SLEW = fast,C_MIO_MIO[23]_SLEW = fast,C_MIO_MIO[30]_PULLUP = disabled,C_MIO_MIO[30]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[30]_SLEW = fast,C_MIO_MIO[29]_PULLUP = disabled,C_MIO_MIO[29]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[28]_SLEW = fast,C_MIO_MIO[27]_PULLUP = disabled,C_MIO_MIO[27]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[26]_SLEW = fast,C_MIO_MIO[29]_SLEW = fast,C_MIO_MIO[28]_PULLUP = disabled,C_MIO_MIO[28]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[27]_SLEW = fast,C_MIO_MIO[26]_PULLUP = disabled,C_MIO_MIO[26]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[36]_SLEW = fast,C_MIO_MIO[35]_PULLUP = disabled,C_MIO_MIO[35]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[34]_SLEW = fast,C_MIO_MIO[33]_PULLUP = disabled,C_MIO_MIO[33]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[32]_SLEW = fast,C_MIO_MIO[31]_PULLUP = disabled,C_MIO_MIO[31]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[37]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[37]_SLEW = fast,C_MIO_MIO[36]_PULLUP = disabled,C_MIO_MIO[36]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[35]_SLEW = fast,C_MIO_MIO[34]_PULLUP = disabled,C_MIO_MIO[34]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[33]_SLEW = fast,C_MIO_MIO[32]_PULLUP = disabled,C_MIO_MIO[32]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[31]_SLEW = fast,C_MIO_MIO[37]_PULLUP = disabled,C_MIO_MIO[39]_PULLUP = disabled,C_MIO_MIO[39]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[39]_SLEW = fast,C_MIO_MIO[38]_PULLUP = disabled,C_MIO_MIO[38]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[38]_SLEW = fast,C_MIO_MIO[43]_PULLUP = disabled,C_MIO_MIO[43]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[42]_SLEW = fast,C_MIO_MIO[41]_PULLUP = disabled,C_MIO_MIO[41]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[45]_PULLUP = disabled,C_MIO_MIO[45]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[45]_SLEW = fast,C_MIO_MIO[44]_PULLUP = disabled,C_MIO_MIO[44]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[44]_SLEW = fast,C_MIO_MIO[43]_SLEW = fast,C_MIO_MIO[42]_PULLUP = disabled,C_MIO_MIO[42]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[41]_SLEW = fast,C_MIO_MIO[40]_PULLUP = disabled,C_MIO_MIO[40]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[40]_SLEW = fast,C_MIO_MIO[52]_PULLUP = disabled,C_MIO_MIO[52]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[51]_DIRECTION = in,C_MIO_MIO[50]_PULLUP = disabled,C_MIO_MIO[50]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[48]_PULLUP = disabled,C_MIO_MIO[48]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[46]_PULLUP = disabled,C_MIO_MIO[46]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[51]_PULLUP = disabled,C_MIO_MIO[51]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[50]_DIRECTION = in,C_MIO_MIO[49]_PULLUP = disabled,C_MIO_MIO[49]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[47]_PULLUP = disabled,C_MIO_MIO[47]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[53]_PULLUP = disabled,C_MIO_MIO[53]_IOTYPE = LVCMOS 1.8V,C_UIPARAM_DDR_BOARD_DELAY2 = 0.341,C_UIPARAM_DDR_BOARD_DELAY0 = 0.41,C_UIPARAM_DDR_USE_INTERNAL_VREF = 1,C_UIPARAM_DDR_TRAIN_READ_GATE = 1,C_UIPARAM_DDR_BOARD_DELAY3 = 0.358,C_UIPARAM_DDR_BOARD_DELAY1 = 0.411,C_UIPARAM_DDR_TRAIN_DATA_EYE = 1,C_UIPARAM_DDR_TRAIN_WRITE_LEVEL = 1,C_DDR_V4.00.A_C_S_AXI_HP3_HIGHADDR = 0x1FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP2_HIGHADDR = 0x1FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP1_HIGHADDR = 0x1FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP0_HIGHADDR = 0x1FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP3_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP2_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP1_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP0_BASEADDR = 0x00000000,C_GPIO_GPIO_IO = MIO,C_GPIO_PERIPHERAL_ENABLE = 1,C:GPIO_EMIO_GPIO_WIDTH = 64,C_CAN_PERIPHERAL_FREQMHZ = 100,C_UART_PERIPHERAL_FREQMHZ = 50,C_ENET0_PERIPHERAL_FREQMHZ = 1000 Mbps,C_QSPI_PERIPHERAL_FREQMHZ = 200.000000,C_FPGA3_PERIPHERAL_FREQMHZ = 50.000000,C_FPGA1_PERIPHERAL_FREQMHZ = 150.000000,C_APU_PERIPHERAL_FREQMHZ = 666.666667,C_PRESET_GLOBAL_DEFAULT = powerup,C_SDIO_PERIPHERAL_FREQMHZ = 50,C_FPGA2_PERIPHERAL_FREQMHZ = 50.000000,C_FPGA0_PERIPHERAL_FREQMHZ = 100.000000,C_PRESET_GLOBAL_CONFIG = Default,C_PRESET_BANK0_VOLTAGE = LVCMOS 3.3V,C_PRESET_FPGA_SPEED = -1,C_PRESET_BANK1_VOLTAGE = LVCMOS 1.8V,C_PRESET_FPGA_PARTNUMBER = xc7z020clg484-1,C_USB0_USB0_IO = MIO 28 .. 39,C_USB0_PERIPHERAL_ENABLE = 1,C_QSPI_PERIPHERAL_ENABLE = 1,C_QSPI_QSPI_IO = MIO 1 .. 6,C_MIO_MIO[3]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[3]_SLEW = fast,C_MIO_MIO[3]_PULLUP = disabled,C_MIO_MIO[6]_PULLUP = disabled,C_MIO_MIO[6]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[6]_SLEW = fast,C_MIO_MIO[5]_PULLUP = disabled,C_MIO_MIO[5]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[5]_SLEW = fast,C_MIO_MIO[4]_PULLUP = disabled,C_MIO_MIO[4]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[4]_SLEW = fast,C_MIO_MIO[9]_PULLUP = disabled,C_MIO_MIO[9]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[9]_SLEW = slow,C_MIO_MIO[8]_PULLUP = disabled,C_MIO_MIO[8]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[8]_SLEW = fast,C_MIO_MIO[7]_PULLUP = disabled,C_MIO_MIO[7]_IOTYPE = LVCMOS 3.3V,C_MIO_MIO[7]_SLEW = slow,C_I2C0_PERIPHERAL_ENABLE = 0,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 = -0.061,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 = 0.028,C_UIPARAM_DDR_T_RAS_MIN = 36.0,C_UIPARAM_DDR_T_RP = 7,C_UIPARAM_DDR_CWL = 6,C_UIPARAM_DDR_FREQ_MHZ = 533.333313,C_UIPARAM_DDR_SPEED_BIN = DDR3_1066F,C_UIPARAM_DDR_DEVICE_CAPACITY = 2048 MBits,C_UIPARAM_DDR_BL = 8,C_UIPARAM_DDR_MEMORY_TYPE = DDR 3,C_UIPARAM_DDR_DRAM_WIDTH = 16 Bits,C_UIPARAM_DDR_PARTNO = MT41J128M16 HA-15E,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 = -0.009,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 = 0.025,C_UIPARAM_DDR_T_FAW = 45.0,C_UIPARAM_DDR_T_RC = 49.5,C_UIPARAM_DDR_T_RCD = 7,C_UIPARAM_DDR_CL = 7,C_UIPARAM_DDR_ROW_ADDR_COUNT = 14}" *)
processing_system7
#(
.C_EN_EMIO_ENET0 ( 0 ),
.C_EN_EMIO_ENET1 ( 0 ),
.C_EN_EMIO_TRACE ( 0 ),
.C_INCLUDE_TRACE_BUFFER ( 0 ),
.C_TRACE_BUFFER_FIFO_SIZE ( 128 ),
.USE_TRACE_DATA_EDGE_DETECTOR ( 0 ),
.C_TRACE_BUFFER_CLOCK_DELAY ( 12 ),
.C_EMIO_GPIO_WIDTH ( 64 ),
.C_INCLUDE_ACP_TRANS_CHECK ( 0 ),
.C_USE_DEFAULT_ACP_USER_VAL ( 0 ),
.C_S_AXI_ACP_ARUSER_VAL ( 31 ),
.C_S_AXI_ACP_AWUSER_VAL ( 31 ),
.C_DQ_WIDTH ( 32 ),
.C_DQS_WIDTH ( 4 ),
.C_DM_WIDTH ( 4 ),
.C_MIO_PRIMITIVE ( 54 ),
.C_PACKAGE_NAME ( "clg484" ),
.C_PS7_SI_REV ( "PRODUCTION" ),
.C_M_AXI_GP0_ID_WIDTH ( 12 ),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP ( 0 ),
.C_M_AXI_GP1_ID_WIDTH ( 12 ),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP ( 0 ),
.C_S_AXI_GP0_ID_WIDTH ( 6 ),
.C_S_AXI_GP1_ID_WIDTH ( 6 ),
.C_S_AXI_ACP_ID_WIDTH ( 3 ),
.C_S_AXI_HP0_ID_WIDTH ( 2 ),
.C_S_AXI_HP0_DATA_WIDTH ( 64 ),
.C_S_AXI_HP1_ID_WIDTH ( 6 ),
.C_S_AXI_HP1_DATA_WIDTH ( 64 ),
.C_S_AXI_HP2_ID_WIDTH ( 6 ),
.C_S_AXI_HP2_DATA_WIDTH ( 64 ),
.C_S_AXI_HP3_ID_WIDTH ( 6 ),
.C_S_AXI_HP3_DATA_WIDTH ( 64 ),
.C_M_AXI_GP0_THREAD_ID_WIDTH ( 12 ),
.C_M_AXI_GP1_THREAD_ID_WIDTH ( 12 ),
.C_NUM_F2P_INTR_INPUTS ( 2 ),
.C_FCLK_CLK0_BUF ( "TRUE" ),
.C_FCLK_CLK1_BUF ( "FALSE" ),
.C_FCLK_CLK2_BUF ( "FALSE" ),
.C_FCLK_CLK3_BUF ( "FALSE" )
)
processing_system7_0 (
.CAN0_PHY_TX ( CAN0_PHY_TX ),
.CAN0_PHY_RX ( CAN0_PHY_RX ),
.CAN1_PHY_TX ( CAN1_PHY_TX ),
.CAN1_PHY_RX ( CAN1_PHY_RX ),
.ENET0_GMII_TX_EN ( ENET0_GMII_TX_EN ),
.ENET0_GMII_TX_ER ( ENET0_GMII_TX_ER ),
.ENET0_MDIO_MDC ( ENET0_MDIO_MDC ),
.ENET0_MDIO_O ( ENET0_MDIO_O ),
.ENET0_MDIO_T ( ENET0_MDIO_T ),
.ENET0_PTP_DELAY_REQ_RX ( ENET0_PTP_DELAY_REQ_RX ),
.ENET0_PTP_DELAY_REQ_TX ( ENET0_PTP_DELAY_REQ_TX ),
.ENET0_PTP_PDELAY_REQ_RX ( ENET0_PTP_PDELAY_REQ_RX ),
.ENET0_PTP_PDELAY_REQ_TX ( ENET0_PTP_PDELAY_REQ_TX ),
.ENET0_PTP_PDELAY_RESP_RX ( ENET0_PTP_PDELAY_RESP_RX ),
.ENET0_PTP_PDELAY_RESP_TX ( ENET0_PTP_PDELAY_RESP_TX ),
.ENET0_PTP_SYNC_FRAME_RX ( ENET0_PTP_SYNC_FRAME_RX ),
.ENET0_PTP_SYNC_FRAME_TX ( ENET0_PTP_SYNC_FRAME_TX ),
.ENET0_SOF_RX ( ENET0_SOF_RX ),
.ENET0_SOF_TX ( ENET0_SOF_TX ),
.ENET0_GMII_TXD ( ENET0_GMII_TXD ),
.ENET0_GMII_COL ( ENET0_GMII_COL ),
.ENET0_GMII_CRS ( ENET0_GMII_CRS ),
.ENET0_EXT_INTIN ( ENET0_EXT_INTIN ),
.ENET0_GMII_RX_CLK ( ENET0_GMII_RX_CLK ),
.ENET0_GMII_RX_DV ( ENET0_GMII_RX_DV ),
.ENET0_GMII_RX_ER ( ENET0_GMII_RX_ER ),
.ENET0_GMII_TX_CLK ( ENET0_GMII_TX_CLK ),
.ENET0_MDIO_I ( ENET0_MDIO_I ),
.ENET0_GMII_RXD ( ENET0_GMII_RXD ),
.ENET1_GMII_TX_EN ( ENET1_GMII_TX_EN ),
.ENET1_GMII_TX_ER ( ENET1_GMII_TX_ER ),
.ENET1_MDIO_MDC ( ENET1_MDIO_MDC ),
.ENET1_MDIO_O ( ENET1_MDIO_O ),
.ENET1_MDIO_T ( ENET1_MDIO_T ),
.ENET1_PTP_DELAY_REQ_RX ( ENET1_PTP_DELAY_REQ_RX ),
.ENET1_PTP_DELAY_REQ_TX ( ENET1_PTP_DELAY_REQ_TX ),
.ENET1_PTP_PDELAY_REQ_RX ( ENET1_PTP_PDELAY_REQ_RX ),
.ENET1_PTP_PDELAY_REQ_TX ( ENET1_PTP_PDELAY_REQ_TX ),
.ENET1_PTP_PDELAY_RESP_RX ( ENET1_PTP_PDELAY_RESP_RX ),
.ENET1_PTP_PDELAY_RESP_TX ( ENET1_PTP_PDELAY_RESP_TX ),
.ENET1_PTP_SYNC_FRAME_RX ( ENET1_PTP_SYNC_FRAME_RX ),
.ENET1_PTP_SYNC_FRAME_TX ( ENET1_PTP_SYNC_FRAME_TX ),
.ENET1_SOF_RX ( ENET1_SOF_RX ),
.ENET1_SOF_TX ( ENET1_SOF_TX ),
.ENET1_GMII_TXD ( ENET1_GMII_TXD ),
.ENET1_GMII_COL ( ENET1_GMII_COL ),
.ENET1_GMII_CRS ( ENET1_GMII_CRS ),
.ENET1_EXT_INTIN ( ENET1_EXT_INTIN ),
.ENET1_GMII_RX_CLK ( ENET1_GMII_RX_CLK ),
.ENET1_GMII_RX_DV ( ENET1_GMII_RX_DV ),
.ENET1_GMII_RX_ER ( ENET1_GMII_RX_ER ),
.ENET1_GMII_TX_CLK ( ENET1_GMII_TX_CLK ),
.ENET1_MDIO_I ( ENET1_MDIO_I ),
.ENET1_GMII_RXD ( ENET1_GMII_RXD ),
.GPIO_I ( GPIO_I ),
.GPIO_O ( GPIO_O ),
.GPIO_T ( GPIO_T ),
.I2C0_SDA_I ( I2C0_SDA_I ),
.I2C0_SDA_O ( I2C0_SDA_O ),
.I2C0_SDA_T ( I2C0_SDA_T ),
.I2C0_SCL_I ( I2C0_SCL_I ),
.I2C0_SCL_O ( I2C0_SCL_O ),
.I2C0_SCL_T ( I2C0_SCL_T ),
.I2C1_SDA_I ( I2C1_SDA_I ),
.I2C1_SDA_O ( I2C1_SDA_O ),
.I2C1_SDA_T ( I2C1_SDA_T ),
.I2C1_SCL_I ( I2C1_SCL_I ),
.I2C1_SCL_O ( I2C1_SCL_O ),
.I2C1_SCL_T ( I2C1_SCL_T ),
.PJTAG_TCK ( PJTAG_TCK ),
.PJTAG_TMS ( PJTAG_TMS ),
.PJTAG_TD_I ( PJTAG_TD_I ),
.PJTAG_TD_T ( PJTAG_TD_T ),
.PJTAG_TD_O ( PJTAG_TD_O ),
.SDIO0_CLK ( SDIO0_CLK ),
.SDIO0_CLK_FB ( SDIO0_CLK_FB ),
.SDIO0_CMD_O ( SDIO0_CMD_O ),
.SDIO0_CMD_I ( SDIO0_CMD_I ),
.SDIO0_CMD_T ( SDIO0_CMD_T ),
.SDIO0_DATA_I ( SDIO0_DATA_I ),
.SDIO0_DATA_O ( SDIO0_DATA_O ),
.SDIO0_DATA_T ( SDIO0_DATA_T ),
.SDIO0_LED ( SDIO0_LED ),
.SDIO0_CDN ( SDIO0_CDN ),
.SDIO0_WP ( SDIO0_WP ),
.SDIO0_BUSPOW ( SDIO0_BUSPOW ),
.SDIO0_BUSVOLT ( SDIO0_BUSVOLT ),
.SDIO1_CLK ( SDIO1_CLK ),
.SDIO1_CLK_FB ( SDIO1_CLK_FB ),
.SDIO1_CMD_O ( SDIO1_CMD_O ),
.SDIO1_CMD_I ( SDIO1_CMD_I ),
.SDIO1_CMD_T ( SDIO1_CMD_T ),
.SDIO1_DATA_I ( SDIO1_DATA_I ),
.SDIO1_DATA_O ( SDIO1_DATA_O ),
.SDIO1_DATA_T ( SDIO1_DATA_T ),
.SDIO1_LED ( SDIO1_LED ),
.SDIO1_CDN ( SDIO1_CDN ),
.SDIO1_WP ( SDIO1_WP ),
.SDIO1_BUSPOW ( SDIO1_BUSPOW ),
.SDIO1_BUSVOLT ( SDIO1_BUSVOLT ),
.SPI0_SCLK_I ( SPI0_SCLK_I ),
.SPI0_SCLK_O ( SPI0_SCLK_O ),
.SPI0_SCLK_T ( SPI0_SCLK_T ),
.SPI0_MOSI_I ( SPI0_MOSI_I ),
.SPI0_MOSI_O ( SPI0_MOSI_O ),
.SPI0_MOSI_T ( SPI0_MOSI_T ),
.SPI0_MISO_I ( SPI0_MISO_I ),
.SPI0_MISO_O ( SPI0_MISO_O ),
.SPI0_MISO_T ( SPI0_MISO_T ),
.SPI0_SS_I ( SPI0_SS_I ),
.SPI0_SS_O ( SPI0_SS_O ),
.SPI0_SS1_O ( SPI0_SS1_O ),
.SPI0_SS2_O ( SPI0_SS2_O ),
.SPI0_SS_T ( SPI0_SS_T ),
.SPI1_SCLK_I ( SPI1_SCLK_I ),
.SPI1_SCLK_O ( SPI1_SCLK_O ),
.SPI1_SCLK_T ( SPI1_SCLK_T ),
.SPI1_MOSI_I ( SPI1_MOSI_I ),
.SPI1_MOSI_O ( SPI1_MOSI_O ),
.SPI1_MOSI_T ( SPI1_MOSI_T ),
.SPI1_MISO_I ( SPI1_MISO_I ),
.SPI1_MISO_O ( SPI1_MISO_O ),
.SPI1_MISO_T ( SPI1_MISO_T ),
.SPI1_SS_I ( SPI1_SS_I ),
.SPI1_SS_O ( SPI1_SS_O ),
.SPI1_SS1_O ( SPI1_SS1_O ),
.SPI1_SS2_O ( SPI1_SS2_O ),
.SPI1_SS_T ( SPI1_SS_T ),
.UART0_DTRN ( UART0_DTRN ),
.UART0_RTSN ( UART0_RTSN ),
.UART0_TX ( UART0_TX ),
.UART0_CTSN ( UART0_CTSN ),
.UART0_DCDN ( UART0_DCDN ),
.UART0_DSRN ( UART0_DSRN ),
.UART0_RIN ( UART0_RIN ),
.UART0_RX ( UART0_RX ),
.UART1_DTRN ( UART1_DTRN ),
.UART1_RTSN ( UART1_RTSN ),
.UART1_TX ( UART1_TX ),
.UART1_CTSN ( UART1_CTSN ),
.UART1_DCDN ( UART1_DCDN ),
.UART1_DSRN ( UART1_DSRN ),
.UART1_RIN ( UART1_RIN ),
.UART1_RX ( UART1_RX ),
.TTC0_WAVE0_OUT ( TTC0_WAVE0_OUT ),
.TTC0_WAVE1_OUT ( TTC0_WAVE1_OUT ),
.TTC0_WAVE2_OUT ( TTC0_WAVE2_OUT ),
.TTC0_CLK0_IN ( TTC0_CLK0_IN ),
.TTC0_CLK1_IN ( TTC0_CLK1_IN ),
.TTC0_CLK2_IN ( TTC0_CLK2_IN ),
.TTC1_WAVE0_OUT ( TTC1_WAVE0_OUT ),
.TTC1_WAVE1_OUT ( TTC1_WAVE1_OUT ),
.TTC1_WAVE2_OUT ( TTC1_WAVE2_OUT ),
.TTC1_CLK0_IN ( TTC1_CLK0_IN ),
.TTC1_CLK1_IN ( TTC1_CLK1_IN ),
.TTC1_CLK2_IN ( TTC1_CLK2_IN ),
.WDT_CLK_IN ( WDT_CLK_IN ),
.WDT_RST_OUT ( WDT_RST_OUT ),
.TRACE_CLK ( TRACE_CLK ),
.TRACE_CTL ( TRACE_CTL ),
.TRACE_DATA ( TRACE_DATA ),
.USB0_PORT_INDCTL ( USB0_PORT_INDCTL ),
.USB1_PORT_INDCTL ( USB1_PORT_INDCTL ),
.USB0_VBUS_PWRSELECT ( USB0_VBUS_PWRSELECT ),
.USB1_VBUS_PWRSELECT ( USB1_VBUS_PWRSELECT ),
.USB0_VBUS_PWRFAULT ( USB0_VBUS_PWRFAULT ),
.USB1_VBUS_PWRFAULT ( USB1_VBUS_PWRFAULT ),
.SRAM_INTIN ( SRAM_INTIN ),
.M_AXI_GP0_ARESETN ( M_AXI_GP0_ARESETN ),
.M_AXI_GP0_ARVALID ( M_AXI_GP0_ARVALID ),
.M_AXI_GP0_AWVALID ( M_AXI_GP0_AWVALID ),
.M_AXI_GP0_BREADY ( M_AXI_GP0_BREADY ),
.M_AXI_GP0_RREADY ( M_AXI_GP0_RREADY ),
.M_AXI_GP0_WLAST ( M_AXI_GP0_WLAST ),
.M_AXI_GP0_WVALID ( M_AXI_GP0_WVALID ),
.M_AXI_GP0_ARID ( M_AXI_GP0_ARID ),
.M_AXI_GP0_AWID ( M_AXI_GP0_AWID ),
.M_AXI_GP0_WID ( M_AXI_GP0_WID ),
.M_AXI_GP0_ARBURST ( M_AXI_GP0_ARBURST ),
.M_AXI_GP0_ARLOCK ( M_AXI_GP0_ARLOCK ),
.M_AXI_GP0_ARSIZE ( M_AXI_GP0_ARSIZE ),
.M_AXI_GP0_AWBURST ( M_AXI_GP0_AWBURST ),
.M_AXI_GP0_AWLOCK ( M_AXI_GP0_AWLOCK ),
.M_AXI_GP0_AWSIZE ( M_AXI_GP0_AWSIZE ),
.M_AXI_GP0_ARPROT ( M_AXI_GP0_ARPROT ),
.M_AXI_GP0_AWPROT ( M_AXI_GP0_AWPROT ),
.M_AXI_GP0_ARADDR ( M_AXI_GP0_ARADDR ),
.M_AXI_GP0_AWADDR ( M_AXI_GP0_AWADDR ),
.M_AXI_GP0_WDATA ( M_AXI_GP0_WDATA ),
.M_AXI_GP0_ARCACHE ( M_AXI_GP0_ARCACHE ),
.M_AXI_GP0_ARLEN ( M_AXI_GP0_ARLEN ),
.M_AXI_GP0_ARQOS ( M_AXI_GP0_ARQOS ),
.M_AXI_GP0_AWCACHE ( M_AXI_GP0_AWCACHE ),
.M_AXI_GP0_AWLEN ( M_AXI_GP0_AWLEN ),
.M_AXI_GP0_AWQOS ( M_AXI_GP0_AWQOS ),
.M_AXI_GP0_WSTRB ( M_AXI_GP0_WSTRB ),
.M_AXI_GP0_ACLK ( M_AXI_GP0_ACLK ),
.M_AXI_GP0_ARREADY ( M_AXI_GP0_ARREADY ),
.M_AXI_GP0_AWREADY ( M_AXI_GP0_AWREADY ),
.M_AXI_GP0_BVALID ( M_AXI_GP0_BVALID ),
.M_AXI_GP0_RLAST ( M_AXI_GP0_RLAST ),
.M_AXI_GP0_RVALID ( M_AXI_GP0_RVALID ),
.M_AXI_GP0_WREADY ( M_AXI_GP0_WREADY ),
.M_AXI_GP0_BID ( M_AXI_GP0_BID ),
.M_AXI_GP0_RID ( M_AXI_GP0_RID ),
.M_AXI_GP0_BRESP ( M_AXI_GP0_BRESP ),
.M_AXI_GP0_RRESP ( M_AXI_GP0_RRESP ),
.M_AXI_GP0_RDATA ( M_AXI_GP0_RDATA ),
.M_AXI_GP1_ARESETN ( M_AXI_GP1_ARESETN ),
.M_AXI_GP1_ARVALID ( M_AXI_GP1_ARVALID ),
.M_AXI_GP1_AWVALID ( M_AXI_GP1_AWVALID ),
.M_AXI_GP1_BREADY ( M_AXI_GP1_BREADY ),
.M_AXI_GP1_RREADY ( M_AXI_GP1_RREADY ),
.M_AXI_GP1_WLAST ( M_AXI_GP1_WLAST ),
.M_AXI_GP1_WVALID ( M_AXI_GP1_WVALID ),
.M_AXI_GP1_ARID ( M_AXI_GP1_ARID ),
.M_AXI_GP1_AWID ( M_AXI_GP1_AWID ),
.M_AXI_GP1_WID ( M_AXI_GP1_WID ),
.M_AXI_GP1_ARBURST ( M_AXI_GP1_ARBURST ),
.M_AXI_GP1_ARLOCK ( M_AXI_GP1_ARLOCK ),
.M_AXI_GP1_ARSIZE ( M_AXI_GP1_ARSIZE ),
.M_AXI_GP1_AWBURST ( M_AXI_GP1_AWBURST ),
.M_AXI_GP1_AWLOCK ( M_AXI_GP1_AWLOCK ),
.M_AXI_GP1_AWSIZE ( M_AXI_GP1_AWSIZE ),
.M_AXI_GP1_ARPROT ( M_AXI_GP1_ARPROT ),
.M_AXI_GP1_AWPROT ( M_AXI_GP1_AWPROT ),
.M_AXI_GP1_ARADDR ( M_AXI_GP1_ARADDR ),
.M_AXI_GP1_AWADDR ( M_AXI_GP1_AWADDR ),
.M_AXI_GP1_WDATA ( M_AXI_GP1_WDATA ),
.M_AXI_GP1_ARCACHE ( M_AXI_GP1_ARCACHE ),
.M_AXI_GP1_ARLEN ( M_AXI_GP1_ARLEN ),
.M_AXI_GP1_ARQOS ( M_AXI_GP1_ARQOS ),
.M_AXI_GP1_AWCACHE ( M_AXI_GP1_AWCACHE ),
.M_AXI_GP1_AWLEN ( M_AXI_GP1_AWLEN ),
.M_AXI_GP1_AWQOS ( M_AXI_GP1_AWQOS ),
.M_AXI_GP1_WSTRB ( M_AXI_GP1_WSTRB ),
.M_AXI_GP1_ACLK ( M_AXI_GP1_ACLK ),
.M_AXI_GP1_ARREADY ( M_AXI_GP1_ARREADY ),
.M_AXI_GP1_AWREADY ( M_AXI_GP1_AWREADY ),
.M_AXI_GP1_BVALID ( M_AXI_GP1_BVALID ),
.M_AXI_GP1_RLAST ( M_AXI_GP1_RLAST ),
.M_AXI_GP1_RVALID ( M_AXI_GP1_RVALID ),
.M_AXI_GP1_WREADY ( M_AXI_GP1_WREADY ),
.M_AXI_GP1_BID ( M_AXI_GP1_BID ),
.M_AXI_GP1_RID ( M_AXI_GP1_RID ),
.M_AXI_GP1_BRESP ( M_AXI_GP1_BRESP ),
.M_AXI_GP1_RRESP ( M_AXI_GP1_RRESP ),
.M_AXI_GP1_RDATA ( M_AXI_GP1_RDATA ),
.S_AXI_GP0_ARESETN ( S_AXI_GP0_ARESETN ),
.S_AXI_GP0_ARREADY ( S_AXI_GP0_ARREADY ),
.S_AXI_GP0_AWREADY ( S_AXI_GP0_AWREADY ),
.S_AXI_GP0_BVALID ( S_AXI_GP0_BVALID ),
.S_AXI_GP0_RLAST ( S_AXI_GP0_RLAST ),
.S_AXI_GP0_RVALID ( S_AXI_GP0_RVALID ),
.S_AXI_GP0_WREADY ( S_AXI_GP0_WREADY ),
.S_AXI_GP0_BRESP ( S_AXI_GP0_BRESP ),
.S_AXI_GP0_RRESP ( S_AXI_GP0_RRESP ),
.S_AXI_GP0_RDATA ( S_AXI_GP0_RDATA ),
.S_AXI_GP0_BID ( S_AXI_GP0_BID ),
.S_AXI_GP0_RID ( S_AXI_GP0_RID ),
.S_AXI_GP0_ACLK ( S_AXI_GP0_ACLK ),
.S_AXI_GP0_ARVALID ( S_AXI_GP0_ARVALID ),
.S_AXI_GP0_AWVALID ( S_AXI_GP0_AWVALID ),
.S_AXI_GP0_BREADY ( S_AXI_GP0_BREADY ),
.S_AXI_GP0_RREADY ( S_AXI_GP0_RREADY ),
.S_AXI_GP0_WLAST ( S_AXI_GP0_WLAST ),
.S_AXI_GP0_WVALID ( S_AXI_GP0_WVALID ),
.S_AXI_GP0_ARBURST ( S_AXI_GP0_ARBURST ),
.S_AXI_GP0_ARLOCK ( S_AXI_GP0_ARLOCK ),
.S_AXI_GP0_ARSIZE ( S_AXI_GP0_ARSIZE ),
.S_AXI_GP0_AWBURST ( S_AXI_GP0_AWBURST ),
.S_AXI_GP0_AWLOCK ( S_AXI_GP0_AWLOCK ),
.S_AXI_GP0_AWSIZE ( S_AXI_GP0_AWSIZE ),
.S_AXI_GP0_ARPROT ( S_AXI_GP0_ARPROT ),
.S_AXI_GP0_AWPROT ( S_AXI_GP0_AWPROT ),
.S_AXI_GP0_ARADDR ( S_AXI_GP0_ARADDR ),
.S_AXI_GP0_AWADDR ( S_AXI_GP0_AWADDR ),
.S_AXI_GP0_WDATA ( S_AXI_GP0_WDATA ),
.S_AXI_GP0_ARCACHE ( S_AXI_GP0_ARCACHE ),
.S_AXI_GP0_ARLEN ( S_AXI_GP0_ARLEN ),
.S_AXI_GP0_ARQOS ( S_AXI_GP0_ARQOS ),
.S_AXI_GP0_AWCACHE ( S_AXI_GP0_AWCACHE ),
.S_AXI_GP0_AWLEN ( S_AXI_GP0_AWLEN ),
.S_AXI_GP0_AWQOS ( S_AXI_GP0_AWQOS ),
.S_AXI_GP0_WSTRB ( S_AXI_GP0_WSTRB ),
.S_AXI_GP0_ARID ( S_AXI_GP0_ARID ),
.S_AXI_GP0_AWID ( S_AXI_GP0_AWID ),
.S_AXI_GP0_WID ( S_AXI_GP0_WID ),
.S_AXI_GP1_ARESETN ( S_AXI_GP1_ARESETN ),
.S_AXI_GP1_ARREADY ( S_AXI_GP1_ARREADY ),
.S_AXI_GP1_AWREADY ( S_AXI_GP1_AWREADY ),
.S_AXI_GP1_BVALID ( S_AXI_GP1_BVALID ),
.S_AXI_GP1_RLAST ( S_AXI_GP1_RLAST ),
.S_AXI_GP1_RVALID ( S_AXI_GP1_RVALID ),
.S_AXI_GP1_WREADY ( S_AXI_GP1_WREADY ),
.S_AXI_GP1_BRESP ( S_AXI_GP1_BRESP ),
.S_AXI_GP1_RRESP ( S_AXI_GP1_RRESP ),
.S_AXI_GP1_RDATA ( S_AXI_GP1_RDATA ),
.S_AXI_GP1_BID ( S_AXI_GP1_BID ),
.S_AXI_GP1_RID ( S_AXI_GP1_RID ),
.S_AXI_GP1_ACLK ( S_AXI_GP1_ACLK ),
.S_AXI_GP1_ARVALID ( S_AXI_GP1_ARVALID ),
.S_AXI_GP1_AWVALID ( S_AXI_GP1_AWVALID ),
.S_AXI_GP1_BREADY ( S_AXI_GP1_BREADY ),
.S_AXI_GP1_RREADY ( S_AXI_GP1_RREADY ),
.S_AXI_GP1_WLAST ( S_AXI_GP1_WLAST ),
.S_AXI_GP1_WVALID ( S_AXI_GP1_WVALID ),
.S_AXI_GP1_ARBURST ( S_AXI_GP1_ARBURST ),
.S_AXI_GP1_ARLOCK ( S_AXI_GP1_ARLOCK ),
.S_AXI_GP1_ARSIZE ( S_AXI_GP1_ARSIZE ),
.S_AXI_GP1_AWBURST ( S_AXI_GP1_AWBURST ),
.S_AXI_GP1_AWLOCK ( S_AXI_GP1_AWLOCK ),
.S_AXI_GP1_AWSIZE ( S_AXI_GP1_AWSIZE ),
.S_AXI_GP1_ARPROT ( S_AXI_GP1_ARPROT ),
.S_AXI_GP1_AWPROT ( S_AXI_GP1_AWPROT ),
.S_AXI_GP1_ARADDR ( S_AXI_GP1_ARADDR ),
.S_AXI_GP1_AWADDR ( S_AXI_GP1_AWADDR ),
.S_AXI_GP1_WDATA ( S_AXI_GP1_WDATA ),
.S_AXI_GP1_ARCACHE ( S_AXI_GP1_ARCACHE ),
.S_AXI_GP1_ARLEN ( S_AXI_GP1_ARLEN ),
.S_AXI_GP1_ARQOS ( S_AXI_GP1_ARQOS ),
.S_AXI_GP1_AWCACHE ( S_AXI_GP1_AWCACHE ),
.S_AXI_GP1_AWLEN ( S_AXI_GP1_AWLEN ),
.S_AXI_GP1_AWQOS ( S_AXI_GP1_AWQOS ),
.S_AXI_GP1_WSTRB ( S_AXI_GP1_WSTRB ),
.S_AXI_GP1_ARID ( S_AXI_GP1_ARID ),
.S_AXI_GP1_AWID ( S_AXI_GP1_AWID ),
.S_AXI_GP1_WID ( S_AXI_GP1_WID ),
.S_AXI_ACP_ARESETN ( S_AXI_ACP_ARESETN ),
.S_AXI_ACP_AWREADY ( S_AXI_ACP_AWREADY ),
.S_AXI_ACP_ARREADY ( S_AXI_ACP_ARREADY ),
.S_AXI_ACP_BVALID ( S_AXI_ACP_BVALID ),
.S_AXI_ACP_RLAST ( S_AXI_ACP_RLAST ),
.S_AXI_ACP_RVALID ( S_AXI_ACP_RVALID ),
.S_AXI_ACP_WREADY ( S_AXI_ACP_WREADY ),
.S_AXI_ACP_BRESP ( S_AXI_ACP_BRESP ),
.S_AXI_ACP_RRESP ( S_AXI_ACP_RRESP ),
.S_AXI_ACP_BID ( S_AXI_ACP_BID ),
.S_AXI_ACP_RID ( S_AXI_ACP_RID ),
.S_AXI_ACP_RDATA ( S_AXI_ACP_RDATA ),
.S_AXI_ACP_ACLK ( S_AXI_ACP_ACLK ),
.S_AXI_ACP_ARVALID ( S_AXI_ACP_ARVALID ),
.S_AXI_ACP_AWVALID ( S_AXI_ACP_AWVALID ),
.S_AXI_ACP_BREADY ( S_AXI_ACP_BREADY ),
.S_AXI_ACP_RREADY ( S_AXI_ACP_RREADY ),
.S_AXI_ACP_WLAST ( S_AXI_ACP_WLAST ),
.S_AXI_ACP_WVALID ( S_AXI_ACP_WVALID ),
.S_AXI_ACP_ARID ( S_AXI_ACP_ARID ),
.S_AXI_ACP_ARPROT ( S_AXI_ACP_ARPROT ),
.S_AXI_ACP_AWID ( S_AXI_ACP_AWID ),
.S_AXI_ACP_AWPROT ( S_AXI_ACP_AWPROT ),
.S_AXI_ACP_WID ( S_AXI_ACP_WID ),
.S_AXI_ACP_ARADDR ( S_AXI_ACP_ARADDR ),
.S_AXI_ACP_AWADDR ( S_AXI_ACP_AWADDR ),
.S_AXI_ACP_ARCACHE ( S_AXI_ACP_ARCACHE ),
.S_AXI_ACP_ARLEN ( S_AXI_ACP_ARLEN ),
.S_AXI_ACP_ARQOS ( S_AXI_ACP_ARQOS ),
.S_AXI_ACP_AWCACHE ( S_AXI_ACP_AWCACHE ),
.S_AXI_ACP_AWLEN ( S_AXI_ACP_AWLEN ),
.S_AXI_ACP_AWQOS ( S_AXI_ACP_AWQOS ),
.S_AXI_ACP_ARBURST ( S_AXI_ACP_ARBURST ),
.S_AXI_ACP_ARLOCK ( S_AXI_ACP_ARLOCK ),
.S_AXI_ACP_ARSIZE ( S_AXI_ACP_ARSIZE ),
.S_AXI_ACP_AWBURST ( S_AXI_ACP_AWBURST ),
.S_AXI_ACP_AWLOCK ( S_AXI_ACP_AWLOCK ),
.S_AXI_ACP_AWSIZE ( S_AXI_ACP_AWSIZE ),
.S_AXI_ACP_ARUSER ( S_AXI_ACP_ARUSER ),
.S_AXI_ACP_AWUSER ( S_AXI_ACP_AWUSER ),
.S_AXI_ACP_WDATA ( S_AXI_ACP_WDATA ),
.S_AXI_ACP_WSTRB ( S_AXI_ACP_WSTRB ),
.S_AXI_HP0_ARESETN ( S_AXI_HP0_ARESETN ),
.S_AXI_HP0_ARREADY ( S_AXI_HP0_ARREADY ),
.S_AXI_HP0_AWREADY ( S_AXI_HP0_AWREADY ),
.S_AXI_HP0_BVALID ( S_AXI_HP0_BVALID ),
.S_AXI_HP0_RLAST ( S_AXI_HP0_RLAST ),
.S_AXI_HP0_RVALID ( S_AXI_HP0_RVALID ),
.S_AXI_HP0_WREADY ( S_AXI_HP0_WREADY ),
.S_AXI_HP0_BRESP ( S_AXI_HP0_BRESP ),
.S_AXI_HP0_RRESP ( S_AXI_HP0_RRESP ),
.S_AXI_HP0_BID ( S_AXI_HP0_BID ),
.S_AXI_HP0_RID ( S_AXI_HP0_RID ),
.S_AXI_HP0_RDATA ( S_AXI_HP0_RDATA ),
.S_AXI_HP0_RCOUNT ( S_AXI_HP0_RCOUNT ),
.S_AXI_HP0_WCOUNT ( S_AXI_HP0_WCOUNT ),
.S_AXI_HP0_RACOUNT ( S_AXI_HP0_RACOUNT ),
.S_AXI_HP0_WACOUNT ( S_AXI_HP0_WACOUNT ),
.S_AXI_HP0_ACLK ( S_AXI_HP0_ACLK ),
.S_AXI_HP0_ARVALID ( S_AXI_HP0_ARVALID ),
.S_AXI_HP0_AWVALID ( S_AXI_HP0_AWVALID ),
.S_AXI_HP0_BREADY ( S_AXI_HP0_BREADY ),
.S_AXI_HP0_RDISSUECAP1_EN ( S_AXI_HP0_RDISSUECAP1_EN ),
.S_AXI_HP0_RREADY ( S_AXI_HP0_RREADY ),
.S_AXI_HP0_WLAST ( S_AXI_HP0_WLAST ),
.S_AXI_HP0_WRISSUECAP1_EN ( S_AXI_HP0_WRISSUECAP1_EN ),
.S_AXI_HP0_WVALID ( S_AXI_HP0_WVALID ),
.S_AXI_HP0_ARBURST ( S_AXI_HP0_ARBURST ),
.S_AXI_HP0_ARLOCK ( S_AXI_HP0_ARLOCK ),
.S_AXI_HP0_ARSIZE ( S_AXI_HP0_ARSIZE ),
.S_AXI_HP0_AWBURST ( S_AXI_HP0_AWBURST ),
.S_AXI_HP0_AWLOCK ( S_AXI_HP0_AWLOCK ),
.S_AXI_HP0_AWSIZE ( S_AXI_HP0_AWSIZE ),
.S_AXI_HP0_ARPROT ( S_AXI_HP0_ARPROT ),
.S_AXI_HP0_AWPROT ( S_AXI_HP0_AWPROT ),
.S_AXI_HP0_ARADDR ( S_AXI_HP0_ARADDR ),
.S_AXI_HP0_AWADDR ( S_AXI_HP0_AWADDR ),
.S_AXI_HP0_ARCACHE ( S_AXI_HP0_ARCACHE ),
.S_AXI_HP0_ARLEN ( S_AXI_HP0_ARLEN ),
.S_AXI_HP0_ARQOS ( S_AXI_HP0_ARQOS ),
.S_AXI_HP0_AWCACHE ( S_AXI_HP0_AWCACHE ),
.S_AXI_HP0_AWLEN ( S_AXI_HP0_AWLEN ),
.S_AXI_HP0_AWQOS ( S_AXI_HP0_AWQOS ),
.S_AXI_HP0_ARID ( S_AXI_HP0_ARID ),
.S_AXI_HP0_AWID ( S_AXI_HP0_AWID ),
.S_AXI_HP0_WID ( S_AXI_HP0_WID ),
.S_AXI_HP0_WDATA ( S_AXI_HP0_WDATA ),
.S_AXI_HP0_WSTRB ( S_AXI_HP0_WSTRB ),
.S_AXI_HP1_ARESETN ( S_AXI_HP1_ARESETN ),
.S_AXI_HP1_ARREADY ( S_AXI_HP1_ARREADY ),
.S_AXI_HP1_AWREADY ( S_AXI_HP1_AWREADY ),
.S_AXI_HP1_BVALID ( S_AXI_HP1_BVALID ),
.S_AXI_HP1_RLAST ( S_AXI_HP1_RLAST ),
.S_AXI_HP1_RVALID ( S_AXI_HP1_RVALID ),
.S_AXI_HP1_WREADY ( S_AXI_HP1_WREADY ),
.S_AXI_HP1_BRESP ( S_AXI_HP1_BRESP ),
.S_AXI_HP1_RRESP ( S_AXI_HP1_RRESP ),
.S_AXI_HP1_BID ( S_AXI_HP1_BID ),
.S_AXI_HP1_RID ( S_AXI_HP1_RID ),
.S_AXI_HP1_RDATA ( S_AXI_HP1_RDATA ),
.S_AXI_HP1_RCOUNT ( S_AXI_HP1_RCOUNT ),
.S_AXI_HP1_WCOUNT ( S_AXI_HP1_WCOUNT ),
.S_AXI_HP1_RACOUNT ( S_AXI_HP1_RACOUNT ),
.S_AXI_HP1_WACOUNT ( S_AXI_HP1_WACOUNT ),
.S_AXI_HP1_ACLK ( S_AXI_HP1_ACLK ),
.S_AXI_HP1_ARVALID ( S_AXI_HP1_ARVALID ),
.S_AXI_HP1_AWVALID ( S_AXI_HP1_AWVALID ),
.S_AXI_HP1_BREADY ( S_AXI_HP1_BREADY ),
.S_AXI_HP1_RDISSUECAP1_EN ( S_AXI_HP1_RDISSUECAP1_EN ),
.S_AXI_HP1_RREADY ( S_AXI_HP1_RREADY ),
.S_AXI_HP1_WLAST ( S_AXI_HP1_WLAST ),
.S_AXI_HP1_WRISSUECAP1_EN ( S_AXI_HP1_WRISSUECAP1_EN ),
.S_AXI_HP1_WVALID ( S_AXI_HP1_WVALID ),
.S_AXI_HP1_ARBURST ( S_AXI_HP1_ARBURST ),
.S_AXI_HP1_ARLOCK ( S_AXI_HP1_ARLOCK ),
.S_AXI_HP1_ARSIZE ( S_AXI_HP1_ARSIZE ),
.S_AXI_HP1_AWBURST ( S_AXI_HP1_AWBURST ),
.S_AXI_HP1_AWLOCK ( S_AXI_HP1_AWLOCK ),
.S_AXI_HP1_AWSIZE ( S_AXI_HP1_AWSIZE ),
.S_AXI_HP1_ARPROT ( S_AXI_HP1_ARPROT ),
.S_AXI_HP1_AWPROT ( S_AXI_HP1_AWPROT ),
.S_AXI_HP1_ARADDR ( S_AXI_HP1_ARADDR ),
.S_AXI_HP1_AWADDR ( S_AXI_HP1_AWADDR ),
.S_AXI_HP1_ARCACHE ( S_AXI_HP1_ARCACHE ),
.S_AXI_HP1_ARLEN ( S_AXI_HP1_ARLEN ),
.S_AXI_HP1_ARQOS ( S_AXI_HP1_ARQOS ),
.S_AXI_HP1_AWCACHE ( S_AXI_HP1_AWCACHE ),
.S_AXI_HP1_AWLEN ( S_AXI_HP1_AWLEN ),
.S_AXI_HP1_AWQOS ( S_AXI_HP1_AWQOS ),
.S_AXI_HP1_ARID ( S_AXI_HP1_ARID ),
.S_AXI_HP1_AWID ( S_AXI_HP1_AWID ),
.S_AXI_HP1_WID ( S_AXI_HP1_WID ),
.S_AXI_HP1_WDATA ( S_AXI_HP1_WDATA ),
.S_AXI_HP1_WSTRB ( S_AXI_HP1_WSTRB ),
.S_AXI_HP2_ARESETN ( S_AXI_HP2_ARESETN ),
.S_AXI_HP2_ARREADY ( S_AXI_HP2_ARREADY ),
.S_AXI_HP2_AWREADY ( S_AXI_HP2_AWREADY ),
.S_AXI_HP2_BVALID ( S_AXI_HP2_BVALID ),
.S_AXI_HP2_RLAST ( S_AXI_HP2_RLAST ),
.S_AXI_HP2_RVALID ( S_AXI_HP2_RVALID ),
.S_AXI_HP2_WREADY ( S_AXI_HP2_WREADY ),
.S_AXI_HP2_BRESP ( S_AXI_HP2_BRESP ),
.S_AXI_HP2_RRESP ( S_AXI_HP2_RRESP ),
.S_AXI_HP2_BID ( S_AXI_HP2_BID ),
.S_AXI_HP2_RID ( S_AXI_HP2_RID ),
.S_AXI_HP2_RDATA ( S_AXI_HP2_RDATA ),
.S_AXI_HP2_RCOUNT ( S_AXI_HP2_RCOUNT ),
.S_AXI_HP2_WCOUNT ( S_AXI_HP2_WCOUNT ),
.S_AXI_HP2_RACOUNT ( S_AXI_HP2_RACOUNT ),
.S_AXI_HP2_WACOUNT ( S_AXI_HP2_WACOUNT ),
.S_AXI_HP2_ACLK ( S_AXI_HP2_ACLK ),
.S_AXI_HP2_ARVALID ( S_AXI_HP2_ARVALID ),
.S_AXI_HP2_AWVALID ( S_AXI_HP2_AWVALID ),
.S_AXI_HP2_BREADY ( S_AXI_HP2_BREADY ),
.S_AXI_HP2_RDISSUECAP1_EN ( S_AXI_HP2_RDISSUECAP1_EN ),
.S_AXI_HP2_RREADY ( S_AXI_HP2_RREADY ),
.S_AXI_HP2_WLAST ( S_AXI_HP2_WLAST ),
.S_AXI_HP2_WRISSUECAP1_EN ( S_AXI_HP2_WRISSUECAP1_EN ),
.S_AXI_HP2_WVALID ( S_AXI_HP2_WVALID ),
.S_AXI_HP2_ARBURST ( S_AXI_HP2_ARBURST ),
.S_AXI_HP2_ARLOCK ( S_AXI_HP2_ARLOCK ),
.S_AXI_HP2_ARSIZE ( S_AXI_HP2_ARSIZE ),
.S_AXI_HP2_AWBURST ( S_AXI_HP2_AWBURST ),
.S_AXI_HP2_AWLOCK ( S_AXI_HP2_AWLOCK ),
.S_AXI_HP2_AWSIZE ( S_AXI_HP2_AWSIZE ),
.S_AXI_HP2_ARPROT ( S_AXI_HP2_ARPROT ),
.S_AXI_HP2_AWPROT ( S_AXI_HP2_AWPROT ),
.S_AXI_HP2_ARADDR ( S_AXI_HP2_ARADDR ),
.S_AXI_HP2_AWADDR ( S_AXI_HP2_AWADDR ),
.S_AXI_HP2_ARCACHE ( S_AXI_HP2_ARCACHE ),
.S_AXI_HP2_ARLEN ( S_AXI_HP2_ARLEN ),
.S_AXI_HP2_ARQOS ( S_AXI_HP2_ARQOS ),
.S_AXI_HP2_AWCACHE ( S_AXI_HP2_AWCACHE ),
.S_AXI_HP2_AWLEN ( S_AXI_HP2_AWLEN ),
.S_AXI_HP2_AWQOS ( S_AXI_HP2_AWQOS ),
.S_AXI_HP2_ARID ( S_AXI_HP2_ARID ),
.S_AXI_HP2_AWID ( S_AXI_HP2_AWID ),
.S_AXI_HP2_WID ( S_AXI_HP2_WID ),
.S_AXI_HP2_WDATA ( S_AXI_HP2_WDATA ),
.S_AXI_HP2_WSTRB ( S_AXI_HP2_WSTRB ),
.S_AXI_HP3_ARESETN ( S_AXI_HP3_ARESETN ),
.S_AXI_HP3_ARREADY ( S_AXI_HP3_ARREADY ),
.S_AXI_HP3_AWREADY ( S_AXI_HP3_AWREADY ),
.S_AXI_HP3_BVALID ( S_AXI_HP3_BVALID ),
.S_AXI_HP3_RLAST ( S_AXI_HP3_RLAST ),
.S_AXI_HP3_RVALID ( S_AXI_HP3_RVALID ),
.S_AXI_HP3_WREADY ( S_AXI_HP3_WREADY ),
.S_AXI_HP3_BRESP ( S_AXI_HP3_BRESP ),
.S_AXI_HP3_RRESP ( S_AXI_HP3_RRESP ),
.S_AXI_HP3_BID ( S_AXI_HP3_BID ),
.S_AXI_HP3_RID ( S_AXI_HP3_RID ),
.S_AXI_HP3_RDATA ( S_AXI_HP3_RDATA ),
.S_AXI_HP3_RCOUNT ( S_AXI_HP3_RCOUNT ),
.S_AXI_HP3_WCOUNT ( S_AXI_HP3_WCOUNT ),
.S_AXI_HP3_RACOUNT ( S_AXI_HP3_RACOUNT ),
.S_AXI_HP3_WACOUNT ( S_AXI_HP3_WACOUNT ),
.S_AXI_HP3_ACLK ( S_AXI_HP3_ACLK ),
.S_AXI_HP3_ARVALID ( S_AXI_HP3_ARVALID ),
.S_AXI_HP3_AWVALID ( S_AXI_HP3_AWVALID ),
.S_AXI_HP3_BREADY ( S_AXI_HP3_BREADY ),
.S_AXI_HP3_RDISSUECAP1_EN ( S_AXI_HP3_RDISSUECAP1_EN ),
.S_AXI_HP3_RREADY ( S_AXI_HP3_RREADY ),
.S_AXI_HP3_WLAST ( S_AXI_HP3_WLAST ),
.S_AXI_HP3_WRISSUECAP1_EN ( S_AXI_HP3_WRISSUECAP1_EN ),
.S_AXI_HP3_WVALID ( S_AXI_HP3_WVALID ),
.S_AXI_HP3_ARBURST ( S_AXI_HP3_ARBURST ),
.S_AXI_HP3_ARLOCK ( S_AXI_HP3_ARLOCK ),
.S_AXI_HP3_ARSIZE ( S_AXI_HP3_ARSIZE ),
.S_AXI_HP3_AWBURST ( S_AXI_HP3_AWBURST ),
.S_AXI_HP3_AWLOCK ( S_AXI_HP3_AWLOCK ),
.S_AXI_HP3_AWSIZE ( S_AXI_HP3_AWSIZE ),
.S_AXI_HP3_ARPROT ( S_AXI_HP3_ARPROT ),
.S_AXI_HP3_AWPROT ( S_AXI_HP3_AWPROT ),
.S_AXI_HP3_ARADDR ( S_AXI_HP3_ARADDR ),
.S_AXI_HP3_AWADDR ( S_AXI_HP3_AWADDR ),
.S_AXI_HP3_ARCACHE ( S_AXI_HP3_ARCACHE ),
.S_AXI_HP3_ARLEN ( S_AXI_HP3_ARLEN ),
.S_AXI_HP3_ARQOS ( S_AXI_HP3_ARQOS ),
.S_AXI_HP3_AWCACHE ( S_AXI_HP3_AWCACHE ),
.S_AXI_HP3_AWLEN ( S_AXI_HP3_AWLEN ),
.S_AXI_HP3_AWQOS ( S_AXI_HP3_AWQOS ),
.S_AXI_HP3_ARID ( S_AXI_HP3_ARID ),
.S_AXI_HP3_AWID ( S_AXI_HP3_AWID ),
.S_AXI_HP3_WID ( S_AXI_HP3_WID ),
.S_AXI_HP3_WDATA ( S_AXI_HP3_WDATA ),
.S_AXI_HP3_WSTRB ( S_AXI_HP3_WSTRB ),
.DMA0_DATYPE ( DMA0_DATYPE ),
.DMA0_DAVALID ( DMA0_DAVALID ),
.DMA0_DRREADY ( DMA0_DRREADY ),
.DMA0_RSTN ( DMA0_RSTN ),
.DMA0_ACLK ( DMA0_ACLK ),
.DMA0_DAREADY ( DMA0_DAREADY ),
.DMA0_DRLAST ( DMA0_DRLAST ),
.DMA0_DRVALID ( DMA0_DRVALID ),
.DMA0_DRTYPE ( DMA0_DRTYPE ),
.DMA1_DATYPE ( DMA1_DATYPE ),
.DMA1_DAVALID ( DMA1_DAVALID ),
.DMA1_DRREADY ( DMA1_DRREADY ),
.DMA1_RSTN ( DMA1_RSTN ),
.DMA1_ACLK ( DMA1_ACLK ),
.DMA1_DAREADY ( DMA1_DAREADY ),
.DMA1_DRLAST ( DMA1_DRLAST ),
.DMA1_DRVALID ( DMA1_DRVALID ),
.DMA1_DRTYPE ( DMA1_DRTYPE ),
.DMA2_DATYPE ( DMA2_DATYPE ),
.DMA2_DAVALID ( DMA2_DAVALID ),
.DMA2_DRREADY ( DMA2_DRREADY ),
.DMA2_RSTN ( DMA2_RSTN ),
.DMA2_ACLK ( DMA2_ACLK ),
.DMA2_DAREADY ( DMA2_DAREADY ),
.DMA2_DRLAST ( DMA2_DRLAST ),
.DMA2_DRVALID ( DMA2_DRVALID ),
.DMA3_DRVALID ( DMA3_DRVALID ),
.DMA3_DATYPE ( DMA3_DATYPE ),
.DMA3_DAVALID ( DMA3_DAVALID ),
.DMA3_DRREADY ( DMA3_DRREADY ),
.DMA3_RSTN ( DMA3_RSTN ),
.DMA3_ACLK ( DMA3_ACLK ),
.DMA3_DAREADY ( DMA3_DAREADY ),
.DMA3_DRLAST ( DMA3_DRLAST ),
.DMA2_DRTYPE ( DMA2_DRTYPE ),
.DMA3_DRTYPE ( DMA3_DRTYPE ),
.FTMD_TRACEIN_DATA ( FTMD_TRACEIN_DATA ),
.FTMD_TRACEIN_VALID ( FTMD_TRACEIN_VALID ),
.FTMD_TRACEIN_CLK ( FTMD_TRACEIN_CLK ),
.FTMD_TRACEIN_ATID ( FTMD_TRACEIN_ATID ),
.FTMT_F2P_TRIG ( FTMT_F2P_TRIG ),
.FTMT_F2P_TRIGACK ( FTMT_F2P_TRIGACK ),
.FTMT_F2P_DEBUG ( FTMT_F2P_DEBUG ),
.FTMT_P2F_TRIGACK ( FTMT_P2F_TRIGACK ),
.FTMT_P2F_TRIG ( FTMT_P2F_TRIG ),
.FTMT_P2F_DEBUG ( FTMT_P2F_DEBUG ),
.FCLK_CLK3 ( FCLK_CLK3 ),
.FCLK_CLK2 ( FCLK_CLK2 ),
.FCLK_CLK1 ( FCLK_CLK1 ),
.FCLK_CLK0 ( FCLK_CLK0 ),
.FCLK_CLKTRIG3_N ( FCLK_CLKTRIG3_N ),
.FCLK_CLKTRIG2_N ( FCLK_CLKTRIG2_N ),
.FCLK_CLKTRIG1_N ( FCLK_CLKTRIG1_N ),
.FCLK_CLKTRIG0_N ( FCLK_CLKTRIG0_N ),
.FCLK_RESET3_N ( FCLK_RESET3_N ),
.FCLK_RESET2_N ( FCLK_RESET2_N ),
.FCLK_RESET1_N ( FCLK_RESET1_N ),
.FCLK_RESET0_N ( FCLK_RESET0_N ),
.FPGA_IDLE_N ( FPGA_IDLE_N ),
.DDR_ARB ( DDR_ARB ),
.IRQ_F2P ( IRQ_F2P ),
.Core0_nFIQ ( Core0_nFIQ ),
.Core0_nIRQ ( Core0_nIRQ ),
.Core1_nFIQ ( Core1_nFIQ ),
.Core1_nIRQ ( Core1_nIRQ ),
.EVENT_EVENTO ( EVENT_EVENTO ),
.EVENT_STANDBYWFE ( EVENT_STANDBYWFE ),
.EVENT_STANDBYWFI ( EVENT_STANDBYWFI ),
.EVENT_EVENTI ( EVENT_EVENTI ),
.MIO ( MIO ),
.DDR_Clk ( DDR_Clk ),
.DDR_Clk_n ( DDR_Clk_n ),
.DDR_CKE ( DDR_CKE ),
.DDR_CS_n ( DDR_CS_n ),
.DDR_RAS_n ( DDR_RAS_n ),
.DDR_CAS_n ( DDR_CAS_n ),
.DDR_WEB ( DDR_WEB ),
.DDR_BankAddr ( DDR_BankAddr ),
.DDR_Addr ( DDR_Addr ),
.DDR_ODT ( DDR_ODT ),
.DDR_DRSTB ( DDR_DRSTB ),
.DDR_DQ ( DDR_DQ ),
.DDR_DM ( DDR_DM ),
.DDR_DQS ( DDR_DQS ),
.DDR_DQS_n ( DDR_DQS_n ),
.DDR_VRN ( DDR_VRN ),
.DDR_VRP ( DDR_VRP ),
.PS_SRSTB ( PS_SRSTB ),
.PS_CLK ( PS_CLK ),
.PS_PORB ( PS_PORB ),
.IRQ_P2F_DMAC_ABORT ( IRQ_P2F_DMAC_ABORT ),
.IRQ_P2F_DMAC0 ( IRQ_P2F_DMAC0 ),
.IRQ_P2F_DMAC1 ( IRQ_P2F_DMAC1 ),
.IRQ_P2F_DMAC2 ( IRQ_P2F_DMAC2 ),
.IRQ_P2F_DMAC3 ( IRQ_P2F_DMAC3 ),
.IRQ_P2F_DMAC4 ( IRQ_P2F_DMAC4 ),
.IRQ_P2F_DMAC5 ( IRQ_P2F_DMAC5 ),
.IRQ_P2F_DMAC6 ( IRQ_P2F_DMAC6 ),
.IRQ_P2F_DMAC7 ( IRQ_P2F_DMAC7 ),
.IRQ_P2F_SMC ( IRQ_P2F_SMC ),
.IRQ_P2F_QSPI ( IRQ_P2F_QSPI ),
.IRQ_P2F_CTI ( IRQ_P2F_CTI ),
.IRQ_P2F_GPIO ( IRQ_P2F_GPIO ),
.IRQ_P2F_USB0 ( IRQ_P2F_USB0 ),
.IRQ_P2F_ENET0 ( IRQ_P2F_ENET0 ),
.IRQ_P2F_ENET_WAKE0 ( IRQ_P2F_ENET_WAKE0 ),
.IRQ_P2F_SDIO0 ( IRQ_P2F_SDIO0 ),
.IRQ_P2F_I2C0 ( IRQ_P2F_I2C0 ),
.IRQ_P2F_SPI0 ( IRQ_P2F_SPI0 ),
.IRQ_P2F_UART0 ( IRQ_P2F_UART0 ),
.IRQ_P2F_CAN0 ( IRQ_P2F_CAN0 ),
.IRQ_P2F_USB1 ( IRQ_P2F_USB1 ),
.IRQ_P2F_ENET1 ( IRQ_P2F_ENET1 ),
.IRQ_P2F_ENET_WAKE1 ( IRQ_P2F_ENET_WAKE1 ),
.IRQ_P2F_SDIO1 ( IRQ_P2F_SDIO1 ),
.IRQ_P2F_I2C1 ( IRQ_P2F_I2C1 ),
.IRQ_P2F_SPI1 ( IRQ_P2F_SPI1 ),
.IRQ_P2F_UART1 ( IRQ_P2F_UART1 ),
.IRQ_P2F_CAN1 ( IRQ_P2F_CAN1 )
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:30 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_0_stub.v
// Design : zynq_design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0, FTMT_P2F_TRIGACK_0, FTMT_P2F_TRIG_0, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,FTMT_F2P_TRIG_0,FTMT_F2P_TRIGACK_0,FTMT_P2F_TRIGACK_0,FTMT_P2F_TRIG_0,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SDFRTP_BEHAVIORAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_BEHAVIORAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_axi (
// reset and clocks
up_rstn,
up_clk,
// axi4 interface
up_axi_awvalid,
up_axi_awaddr,
up_axi_awready,
up_axi_wvalid,
up_axi_wdata,
up_axi_wstrb,
up_axi_wready,
up_axi_bvalid,
up_axi_bresp,
up_axi_bready,
up_axi_arvalid,
up_axi_araddr,
up_axi_arready,
up_axi_rvalid,
up_axi_rresp,
up_axi_rdata,
up_axi_rready,
// pcore interface
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter ADDRESS_WIDTH = 14;
localparam AW = ADDRESS_WIDTH - 1;
// reset and clocks
input up_rstn;
input up_clk;
// axi4 interface
input up_axi_awvalid;
input [31:0] up_axi_awaddr;
output up_axi_awready;
input up_axi_wvalid;
input [31:0] up_axi_wdata;
input [ 3:0] up_axi_wstrb;
output up_axi_wready;
output up_axi_bvalid;
output [ 1:0] up_axi_bresp;
input up_axi_bready;
input up_axi_arvalid;
input [31:0] up_axi_araddr;
output up_axi_arready;
output up_axi_rvalid;
output [ 1:0] up_axi_rresp;
output [31:0] up_axi_rdata;
input up_axi_rready;
// pcore interface
output up_wreq;
output [AW:0] up_waddr;
output [31:0] up_wdata;
input up_wack;
output up_rreq;
output [AW:0] up_raddr;
input [31:0] up_rdata;
input up_rack;
// internal registers
reg up_axi_awready = 'd0;
reg up_axi_wready = 'd0;
reg up_axi_bvalid = 'd0;
reg up_wsel = 'd0;
reg up_wreq = 'd0;
reg [AW:0] up_waddr = 'd0;
reg [31:0] up_wdata = 'd0;
reg [ 2:0] up_wcount = 'd0;
reg up_wack_int = 'd0;
reg up_axi_arready = 'd0;
reg up_axi_rvalid = 'd0;
reg [31:0] up_axi_rdata = 'd0;
reg up_rsel = 'd0;
reg up_rreq = 'd0;
reg [AW:0] up_raddr = 'd0;
reg [ 3:0] up_rcount = 'd0;
reg up_rack_int = 'd0;
reg [31:0] up_rdata_int = 'd0;
reg up_rack_int_d = 'd0;
reg [31:0] up_rdata_int_d = 'd0;
// write channel interface
assign up_axi_bresp = 2'd0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_axi_awready <= 'd0;
up_axi_wready <= 'd0;
up_axi_bvalid <= 'd0;
end else begin
if (up_axi_awready == 1'b1) begin
up_axi_awready <= 1'b0;
end else if (up_wack_int == 1'b1) begin
up_axi_awready <= 1'b1;
end
if (up_axi_wready == 1'b1) begin
up_axi_wready <= 1'b0;
end else if (up_wack_int == 1'b1) begin
up_axi_wready <= 1'b1;
end
if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
up_axi_bvalid <= 1'b0;
end else if (up_wack_int == 1'b1) begin
up_axi_bvalid <= 1'b1;
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_wsel <= 'd0;
up_wreq <= 'd0;
up_waddr <= 'd0;
up_wdata <= 'd0;
up_wcount <= 'd0;
end else begin
if (up_wsel == 1'b1) begin
if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
up_wsel <= 1'b0;
end
up_wreq <= 1'b0;
up_waddr <= up_waddr;
up_wdata <= up_wdata;
up_wcount <= up_wcount + 1'b1;
end else begin
up_wsel <= up_axi_awvalid & up_axi_wvalid;
up_wreq <= up_axi_awvalid & up_axi_wvalid;
up_waddr <= up_axi_awaddr[AW+2:2];
up_wdata <= up_axi_wdata;
up_wcount <= 3'd0;
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack_int <= 'd0;
end else begin
if ((up_wcount == 3'h7) && (up_wack == 1'b0)) begin
up_wack_int <= 1'b1;
end else if (up_wsel == 1'b1) begin
up_wack_int <= up_wack;
end
end
end
// read channel interface
assign up_axi_rresp = 2'd0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_axi_arready <= 'd0;
up_axi_rvalid <= 'd0;
up_axi_rdata <= 'd0;
end else begin
if (up_axi_arready == 1'b1) begin
up_axi_arready <= 1'b0;
end else if (up_rack_int == 1'b1) begin
up_axi_arready <= 1'b1;
end
if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
up_axi_rvalid <= 1'b0;
up_axi_rdata <= 32'd0;
end else if (up_rack_int_d == 1'b1) begin
up_axi_rvalid <= 1'b1;
up_axi_rdata <= up_rdata_int_d;
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rsel <= 'd0;
up_rreq <= 'd0;
up_raddr <= 'd0;
up_rcount <= 'd0;
end else begin
if (up_rsel == 1'b1) begin
if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
up_rsel <= 1'b0;
end
up_rreq <= 1'b0;
up_raddr <= up_raddr;
end else begin
up_rsel <= up_axi_arvalid;
up_rreq <= up_axi_arvalid;
up_raddr <= up_axi_araddr[AW+2:2];
end
if (up_rack_int == 1'b1) begin
up_rcount <= 4'd0;
end else if (up_rcount[3] == 1'b1) begin
up_rcount <= up_rcount + 1'b1;
end else if (up_rreq == 1'b1) begin
up_rcount <= 4'd8;
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack_int <= 'd0;
up_rdata_int <= 'd0;
up_rack_int_d <= 'd0;
up_rdata_int_d <= 'd0;
end else begin
if ((up_rcount == 4'hf) && (up_rack == 1'b0)) begin
up_rack_int <= 1'b1;
up_rdata_int <= {2{16'hdead}};
end else begin
up_rack_int <= up_rack;
up_rdata_int <= up_rdata;
end
up_rack_int_d <= up_rack_int;
up_rdata_int_d <= up_rdata_int;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cclk_inv_64x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// --------------------------------------------------
// File: bw_clk_cclk_inv_64x.behV
// --------------------------------------------------
//
module bw_clk_cclk_inv_64x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule
|
//date:2016/3/16
//engineer: zhaishaomin
//module function :test whether dc_download will behave as what i want it to do ,such as handling coming flit correctly
/*
// test examples
//wbrep 11 flits long
flits_d_m_areg={flits_in[140:139],1'b1,local_id,1'b0,wbrep_cmd,5'b00000,seled_addr,data_read};
//ATflurep 11 flits long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,ATflurep_cmd,5'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],data_read};
//shrep 9 flits long
msg={temp_rep_head_flit,data_read,32'h00000000};
//SHexrep 9 flits long
msg={temp_rep_head_flit,data_read,32'h00000000};
//exrep 9 flits long
msg={temp_rep_head_flit,data_read,32'h00000000};
//wbreq 3 flits long
msg={temp_rep_head_flit,seled_addr,128'h0000};
//flushreq 3 flits long
msg={temp_req_head_flit,seled_addr,128'h0000};
//SCinvreq or invreq 3 flits long
msg={temp_req_head_flit,seled_addr,128'h0000};
//shreq 3 flits long
flits_d_m_areg={seled_addr[12:11],1'b0,local_id,1'b1,shreq_cmd,5'b00000,seled_addr,128'hzzzz};
//exreq 3 flits long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,exreq_cmd,5'b00000,seled_addr,128'hzzzz};
//C2Hinvrep 3 flits long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,C2Hinvrep_cmd,5'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],128'hzzzz};
//flushrep 3 flits long
flits_d_m_areg={flits_in[140:139],1'b1,local_id,1'b0,flushrep_cmd,5'b00000,seled_addr,128'h0000};
//flushfail_rep 3 flits long
flits_d_m_areg={flits_in[140:139],1'b1,flits_in[132:131],1'b0,flushfail_rep_cmd,5'b00000,seled_addr,128'h0000};
//wbfail_rep 3 flits long
flits_d_m_areg={flits_in[140:139],1'b1,flits_in[132:131],1'b0,wbfail_rep_cmd,5'b00000,seled_addr,128'h0000};
//nackrep 1 flit long
msg={temp_rep_head_flit,data_read,32'h00000000};
//C2Cinvrep 1 flit long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,C2Hinvrep_cmd,5'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],128'hzzzz};
//SCflushrep 1 flit long
msg={temp_rep_head_flit,data_read,32'h00000000};
*/
`timescale 1ns/1ps
module tb_dc_download();
//inputs
reg clk;
reg rst;
reg [15:0] IN_flit_dc;
reg v_IN_flit_dc;
reg [1:0] In_flit_ctrl_dc;
reg dc_done_access;
//output
wire v_dc_download;
wire [1:0] dc_downlaod_state;
wire [143:0]dc_download_flits;
//instantiate the uut
dc_download uut(//input
.clk(clk),
.rst(rst),
.IN_flit_dc(IN_flit_dc),
.v_IN_flit_dc(v_IN_flit_dc),
.In_flit_ctrl_dc(In_flit_ctrl_dc),
.dc_done_access(dc_done_access),
//output
.v_dc_download(v_dc_download),
.dc_download_flits(dc_download_flits),
.dc_download_state(dc_download_state)
);
// store the simulation log into log_file
integer logfile;
// Initialize Inputs
initial begin
clk = 1'b0;
rst = 1'b0;
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b0;
In_flit_ctrl_dc=2'b00;
dc_done_access=1'b0;
end
always #20 clk=~clk;
`define step #40;
initial begin
/////// mem_download test /////////
// First reset all //
$display("(%t) Initializing...", $time);
$fdisplay(log_file, "(%t) Initializing...", $time);
rst=1;
`step
rst=0;
`step
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////REP MSG FROM IN_REP_FIFO//////////////////////////////////////////////////////////////////////
//after a few cycles ,a rep msg from IN_local_rep fifo come and dc_download should be ready to receive the flits
// note :here are three kinds of reps and reqs totally,
// including :9 flits long msg : exrep , shrep, sh->exrep
// 3 flits long msg : invreq, wbreq, flushreq, scflushreq,
// 1 flit long msg : C2Cinvrep so far.
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 9 FLITS LONG MSG
//first flit
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b01;
`step
// second flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
`step
// 3rd flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
`step
// 4th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
`step
// 5th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
`step
// 6th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
// just test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
`step
// 7th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
`step
// 8th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
`step
// 9th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) msg todata cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 3 FLITS LONG MSG
//first flit
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b01;
`step
// second flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
`step
// 3rd flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 1 FLITS LONG MSG
//first flit
IN_flit_dc=16'h1234; // condition: IN_flit_dc[9:5]==nackrep_cmd||IN_flit_dc[9:5]==SCflurep_cmd||IN_flit_dc[9:5]==C2Cinvrep_cmd
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b01;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$stop;
end
endmodule |
/* Generated by Yosys 0.9+4052 (git sha1 5c1e6a0e, clang 7.0.1 -fPIC -Os) */
module gcd(clk, req_msg, req_rdy, req_val, reset, resp_msg, resp_rdy, resp_val);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
input clk;
wire \ctrl.state.out[1] ;
wire \ctrl.state.out[2] ;
wire \dpath.a_lt_b$in0[0] ;
wire \dpath.a_lt_b$in0[10] ;
wire \dpath.a_lt_b$in0[11] ;
wire \dpath.a_lt_b$in0[12] ;
wire \dpath.a_lt_b$in0[13] ;
wire \dpath.a_lt_b$in0[14] ;
wire \dpath.a_lt_b$in0[15] ;
wire \dpath.a_lt_b$in0[1] ;
wire \dpath.a_lt_b$in0[2] ;
wire \dpath.a_lt_b$in0[3] ;
wire \dpath.a_lt_b$in0[4] ;
wire \dpath.a_lt_b$in0[5] ;
wire \dpath.a_lt_b$in0[6] ;
wire \dpath.a_lt_b$in0[7] ;
wire \dpath.a_lt_b$in0[8] ;
wire \dpath.a_lt_b$in0[9] ;
wire \dpath.a_lt_b$in1[0] ;
wire \dpath.a_lt_b$in1[10] ;
wire \dpath.a_lt_b$in1[11] ;
wire \dpath.a_lt_b$in1[12] ;
wire \dpath.a_lt_b$in1[13] ;
wire \dpath.a_lt_b$in1[14] ;
wire \dpath.a_lt_b$in1[15] ;
wire \dpath.a_lt_b$in1[1] ;
wire \dpath.a_lt_b$in1[2] ;
wire \dpath.a_lt_b$in1[3] ;
wire \dpath.a_lt_b$in1[4] ;
wire \dpath.a_lt_b$in1[5] ;
wire \dpath.a_lt_b$in1[6] ;
wire \dpath.a_lt_b$in1[7] ;
wire \dpath.a_lt_b$in1[8] ;
wire \dpath.a_lt_b$in1[9] ;
input [31:0] req_msg;
output req_rdy;
input req_val;
input reset;
output [15:0] resp_msg;
input resp_rdy;
output resp_val;
sky130_fd_sc_hd__xnor2_1 _197_ (
.A(\dpath.a_lt_b$in1[14] ),
.B(\dpath.a_lt_b$in0[14] ),
.Y(_035_)
);
sky130_fd_sc_hd__nor2b_1 _198_ (
.A(\dpath.a_lt_b$in0[13] ),
.B_N(\dpath.a_lt_b$in1[13] ),
.Y(_036_)
);
sky130_fd_sc_hd__xnor2_1 _199_ (
.A(\dpath.a_lt_b$in1[12] ),
.B(\dpath.a_lt_b$in0[12] ),
.Y(_037_)
);
sky130_fd_sc_hd__nand2b_1 _200_ (
.A_N(\dpath.a_lt_b$in0[11] ),
.B(\dpath.a_lt_b$in1[11] ),
.Y(_038_)
);
sky130_fd_sc_hd__xnor2_1 _201_ (
.A(\dpath.a_lt_b$in1[10] ),
.B(\dpath.a_lt_b$in0[10] ),
.Y(_039_)
);
sky130_fd_sc_hd__inv_1 _202_ (
.A(_039_),
.Y(_040_)
);
sky130_fd_sc_hd__nor2b_1 _203_ (
.A(\dpath.a_lt_b$in0[9] ),
.B_N(\dpath.a_lt_b$in1[9] ),
.Y(_041_)
);
sky130_fd_sc_hd__xnor2_1 _204_ (
.A(\dpath.a_lt_b$in1[8] ),
.B(\dpath.a_lt_b$in0[8] ),
.Y(_042_)
);
sky130_fd_sc_hd__inv_1 _205_ (
.A(\dpath.a_lt_b$in0[7] ),
.Y(_043_)
);
sky130_fd_sc_hd__nand2_1 _206_ (
.A(\dpath.a_lt_b$in1[7] ),
.B(_043_),
.Y(_044_)
);
sky130_fd_sc_hd__xnor2_1 _207_ (
.A(\dpath.a_lt_b$in1[6] ),
.B(\dpath.a_lt_b$in0[6] ),
.Y(_045_)
);
sky130_fd_sc_hd__inv_1 _208_ (
.A(_045_),
.Y(_046_)
);
sky130_fd_sc_hd__inv_1 _209_ (
.A(\dpath.a_lt_b$in0[5] ),
.Y(_047_)
);
sky130_fd_sc_hd__inv_1 _210_ (
.A(\dpath.a_lt_b$in0[4] ),
.Y(_048_)
);
sky130_fd_sc_hd__inv_1 _211_ (
.A(\dpath.a_lt_b$in0[3] ),
.Y(_049_)
);
sky130_fd_sc_hd__inv_1 _212_ (
.A(\dpath.a_lt_b$in0[2] ),
.Y(_050_)
);
sky130_fd_sc_hd__inv_1 _213_ (
.A(\dpath.a_lt_b$in0[1] ),
.Y(_051_)
);
sky130_fd_sc_hd__nor2b_1 _214_ (
.A(\dpath.a_lt_b$in0[0] ),
.B_N(\dpath.a_lt_b$in1[0] ),
.Y(_052_)
);
sky130_fd_sc_hd__maj3_2 _215_ (
.A(\dpath.a_lt_b$in1[1] ),
.B(_051_),
.C(_052_),
.X(_053_)
);
sky130_fd_sc_hd__maj3_2 _216_ (
.A(\dpath.a_lt_b$in1[2] ),
.B(_050_),
.C(_053_),
.X(_054_)
);
sky130_fd_sc_hd__maj3_2 _217_ (
.A(\dpath.a_lt_b$in1[3] ),
.B(_049_),
.C(_054_),
.X(_055_)
);
sky130_fd_sc_hd__maj3_2 _218_ (
.A(\dpath.a_lt_b$in1[4] ),
.B(_048_),
.C(_055_),
.X(_056_)
);
sky130_fd_sc_hd__maj3_2 _219_ (
.A(\dpath.a_lt_b$in1[5] ),
.B(_047_),
.C(_056_),
.X(_057_)
);
sky130_fd_sc_hd__nand2b_1 _220_ (
.A_N(\dpath.a_lt_b$in1[7] ),
.B(\dpath.a_lt_b$in0[7] ),
.Y(_058_)
);
sky130_fd_sc_hd__nand2b_1 _221_ (
.A_N(\dpath.a_lt_b$in1[6] ),
.B(\dpath.a_lt_b$in0[6] ),
.Y(_059_)
);
sky130_fd_sc_hd__o211ai_2 _222_ (
.A1(_046_),
.A2(_057_),
.B1(_058_),
.C1(_059_),
.Y(_060_)
);
sky130_fd_sc_hd__nor2b_1 _223_ (
.A(\dpath.a_lt_b$in1[8] ),
.B_N(\dpath.a_lt_b$in0[8] ),
.Y(_061_)
);
sky130_fd_sc_hd__nor2b_1 _224_ (
.A(\dpath.a_lt_b$in1[9] ),
.B_N(\dpath.a_lt_b$in0[9] ),
.Y(_062_)
);
sky130_fd_sc_hd__a311oi_2 _225_ (
.A1(_042_),
.A2(_044_),
.A3(_060_),
.B1(_061_),
.C1(_062_),
.Y(_063_)
);
sky130_fd_sc_hd__nand2b_1 _226_ (
.A_N(\dpath.a_lt_b$in1[10] ),
.B(\dpath.a_lt_b$in0[10] ),
.Y(_064_)
);
sky130_fd_sc_hd__nand2b_1 _227_ (
.A_N(\dpath.a_lt_b$in1[11] ),
.B(\dpath.a_lt_b$in0[11] ),
.Y(_065_)
);
sky130_fd_sc_hd__o311ai_4 _228_ (
.A1(_040_),
.A2(_041_),
.A3(_063_),
.B1(_064_),
.C1(_065_),
.Y(_066_)
);
sky130_fd_sc_hd__nor2b_1 _229_ (
.A(\dpath.a_lt_b$in1[12] ),
.B_N(\dpath.a_lt_b$in0[12] ),
.Y(_067_)
);
sky130_fd_sc_hd__nor2b_1 _230_ (
.A(\dpath.a_lt_b$in1[13] ),
.B_N(\dpath.a_lt_b$in0[13] ),
.Y(_068_)
);
sky130_fd_sc_hd__a311oi_1 _231_ (
.A1(_037_),
.A2(_038_),
.A3(_066_),
.B1(_067_),
.C1(_068_),
.Y(_069_)
);
sky130_fd_sc_hd__nor2_1 _232_ (
.A(_036_),
.B(_069_),
.Y(_070_)
);
sky130_fd_sc_hd__nand2b_1 _233_ (
.A_N(\dpath.a_lt_b$in1[14] ),
.B(\dpath.a_lt_b$in0[14] ),
.Y(_071_)
);
sky130_fd_sc_hd__a21boi_0 _234_ (
.A1(_035_),
.A2(_070_),
.B1_N(_071_),
.Y(_072_)
);
sky130_fd_sc_hd__nor2b_1 _235_ (
.A(\dpath.a_lt_b$in0[15] ),
.B_N(\dpath.a_lt_b$in1[15] ),
.Y(_073_)
);
sky130_fd_sc_hd__nand2b_1 _236_ (
.A_N(\dpath.a_lt_b$in1[15] ),
.B(\dpath.a_lt_b$in0[15] ),
.Y(_074_)
);
sky130_fd_sc_hd__nor2b_1 _237_ (
.A(_073_),
.B_N(_074_),
.Y(_075_)
);
sky130_fd_sc_hd__xnor2_1 _238_ (
.A(_072_),
.B(_075_),
.Y(resp_msg[15])
);
sky130_fd_sc_hd__xnor2_1 _239_ (
.A(\dpath.a_lt_b$in1[1] ),
.B(\dpath.a_lt_b$in0[1] ),
.Y(_076_)
);
sky130_fd_sc_hd__xnor2_1 _240_ (
.A(_052_),
.B(_076_),
.Y(resp_msg[1])
);
sky130_fd_sc_hd__xnor2_1 _241_ (
.A(\dpath.a_lt_b$in1[2] ),
.B(\dpath.a_lt_b$in0[2] ),
.Y(_077_)
);
sky130_fd_sc_hd__xnor2_1 _242_ (
.A(_077_),
.B(_053_),
.Y(resp_msg[2])
);
sky130_fd_sc_hd__xnor2_1 _243_ (
.A(\dpath.a_lt_b$in1[3] ),
.B(\dpath.a_lt_b$in0[3] ),
.Y(_078_)
);
sky130_fd_sc_hd__xnor2_1 _244_ (
.A(_054_),
.B(_078_),
.Y(resp_msg[3])
);
sky130_fd_sc_hd__xnor2_1 _245_ (
.A(\dpath.a_lt_b$in1[4] ),
.B(\dpath.a_lt_b$in0[4] ),
.Y(_079_)
);
sky130_fd_sc_hd__xnor2_1 _246_ (
.A(_079_),
.B(_055_),
.Y(resp_msg[4])
);
sky130_fd_sc_hd__xnor2_1 _247_ (
.A(\dpath.a_lt_b$in1[5] ),
.B(\dpath.a_lt_b$in0[5] ),
.Y(_080_)
);
sky130_fd_sc_hd__xnor2_1 _248_ (
.A(_056_),
.B(_080_),
.Y(resp_msg[5])
);
sky130_fd_sc_hd__xnor2_1 _249_ (
.A(_045_),
.B(_057_),
.Y(resp_msg[6])
);
sky130_fd_sc_hd__o21a_1 _250_ (
.A1(_046_),
.A2(_057_),
.B1(_059_),
.X(_081_)
);
sky130_fd_sc_hd__and2_1 _251_ (
.A(_058_),
.B(_044_),
.X(_082_)
);
sky130_fd_sc_hd__xnor2_1 _252_ (
.A(_081_),
.B(_082_),
.Y(resp_msg[7])
);
sky130_fd_sc_hd__nand2_1 _253_ (
.A(_044_),
.B(_060_),
.Y(_083_)
);
sky130_fd_sc_hd__xnor2_1 _254_ (
.A(_042_),
.B(_083_),
.Y(resp_msg[8])
);
sky130_fd_sc_hd__a31o_2 _255_ (
.A1(_042_),
.A2(_044_),
.A3(_060_),
.B1(_061_),
.X(_084_)
);
sky130_fd_sc_hd__nor2_1 _256_ (
.A(_062_),
.B(_041_),
.Y(_085_)
);
sky130_fd_sc_hd__xor2_1 _257_ (
.A(_084_),
.B(_085_),
.X(resp_msg[9])
);
sky130_fd_sc_hd__nor3_1 _258_ (
.A(_040_),
.B(_041_),
.C(_063_),
.Y(_086_)
);
sky130_fd_sc_hd__o21ai_0 _259_ (
.A1(_041_),
.A2(_063_),
.B1(_040_),
.Y(_087_)
);
sky130_fd_sc_hd__nor2b_1 _260_ (
.A(_086_),
.B_N(_087_),
.Y(resp_msg[10])
);
sky130_fd_sc_hd__o31ai_1 _261_ (
.A1(_040_),
.A2(_041_),
.A3(_063_),
.B1(_064_),
.Y(_088_)
);
sky130_fd_sc_hd__nand2_1 _262_ (
.A(_038_),
.B(_065_),
.Y(_089_)
);
sky130_fd_sc_hd__xnor2_1 _263_ (
.A(_088_),
.B(_089_),
.Y(resp_msg[11])
);
sky130_fd_sc_hd__nand2_1 _264_ (
.A(_038_),
.B(_066_),
.Y(_090_)
);
sky130_fd_sc_hd__xnor2_1 _265_ (
.A(_037_),
.B(_090_),
.Y(resp_msg[12])
);
sky130_fd_sc_hd__a31oi_1 _266_ (
.A1(_037_),
.A2(_038_),
.A3(_066_),
.B1(_067_),
.Y(_091_)
);
sky130_fd_sc_hd__nor2_1 _267_ (
.A(_068_),
.B(_036_),
.Y(_092_)
);
sky130_fd_sc_hd__xnor2_1 _268_ (
.A(_091_),
.B(_092_),
.Y(resp_msg[13])
);
sky130_fd_sc_hd__inv_1 _269_ (
.A(_035_),
.Y(_093_)
);
sky130_fd_sc_hd__xnor2_1 _270_ (
.A(_093_),
.B(_070_),
.Y(resp_msg[14])
);
sky130_fd_sc_hd__xor2_1 _271_ (
.A(\dpath.a_lt_b$in0[0] ),
.B(\dpath.a_lt_b$in1[0] ),
.X(resp_msg[0])
);
sky130_fd_sc_hd__nor2_1 _272_ (
.A(\dpath.a_lt_b$in1[13] ),
.B(\dpath.a_lt_b$in1[14] ),
.Y(_094_)
);
sky130_fd_sc_hd__nor4_1 _273_ (
.A(\dpath.a_lt_b$in1[3] ),
.B(\dpath.a_lt_b$in1[4] ),
.C(\dpath.a_lt_b$in1[10] ),
.D(\dpath.a_lt_b$in1[15] ),
.Y(_095_)
);
sky130_fd_sc_hd__nor4_1 _274_ (
.A(\dpath.a_lt_b$in1[6] ),
.B(\dpath.a_lt_b$in1[7] ),
.C(\dpath.a_lt_b$in1[0] ),
.D(\dpath.a_lt_b$in1[1] ),
.Y(_096_)
);
sky130_fd_sc_hd__nand3_1 _275_ (
.A(_094_),
.B(_095_),
.C(_096_),
.Y(_097_)
);
sky130_fd_sc_hd__or4_1 _276_ (
.A(\dpath.a_lt_b$in1[2] ),
.B(\dpath.a_lt_b$in1[5] ),
.C(\dpath.a_lt_b$in1[8] ),
.D(\dpath.a_lt_b$in1[9] ),
.X(_098_)
);
sky130_fd_sc_hd__nor4_1 _277_ (
.A(\dpath.a_lt_b$in1[11] ),
.B(\dpath.a_lt_b$in1[12] ),
.C(_097_),
.D(_098_),
.Y(_099_)
);
sky130_fd_sc_hd__inv_1 _278_ (
.A(reset),
.Y(_100_)
);
sky130_fd_sc_hd__nand2_1 _279_ (
.A(\ctrl.state.out[2] ),
.B(_100_),
.Y(_101_)
);
sky130_fd_sc_hd__buf_1 _280_ (
.A(req_rdy),
.X(_102_)
);
sky130_fd_sc_hd__clkbuf_1 _281_ (
.A(_102_),
.X(_103_)
);
sky130_fd_sc_hd__nand2_1 _282_ (
.A(_103_),
.B(req_val),
.Y(_104_)
);
sky130_fd_sc_hd__o22ai_1 _283_ (
.A1(_099_),
.A2(_101_),
.B1(_104_),
.B2(reset),
.Y(_002_)
);
sky130_fd_sc_hd__nor2_1 _284_ (
.A(\ctrl.state.out[2] ),
.B(req_rdy),
.Y(_105_)
);
sky130_fd_sc_hd__and2_1 _285_ (
.A(\ctrl.state.out[1] ),
.B(_105_),
.X(resp_val)
);
sky130_fd_sc_hd__inv_1 _286_ (
.A(req_rdy),
.Y(_106_)
);
sky130_fd_sc_hd__clkbuf_1 _287_ (
.A(_106_),
.X(_107_)
);
sky130_fd_sc_hd__a21oi_1 _288_ (
.A1(resp_rdy),
.A2(resp_val),
.B1(reset),
.Y(_108_)
);
sky130_fd_sc_hd__o21ai_0 _289_ (
.A1(_107_),
.A2(req_val),
.B1(_108_),
.Y(_000_)
);
sky130_fd_sc_hd__a32o_1 _290_ (
.A1(\ctrl.state.out[2] ),
.A2(_100_),
.A3(_099_),
.B1(_108_),
.B2(\ctrl.state.out[1] ),
.X(_001_)
);
sky130_fd_sc_hd__nand2_1 _291_ (
.A(_103_),
.B(req_msg[0]),
.Y(_109_)
);
sky130_fd_sc_hd__o311a_4 _292_ (
.A1(_093_),
.A2(_036_),
.A3(_069_),
.B1(_074_),
.C1(_071_),
.X(_110_)
);
sky130_fd_sc_hd__or2_2 _293_ (
.A(\ctrl.state.out[2] ),
.B(req_rdy),
.X(_111_)
);
sky130_fd_sc_hd__buf_1 _294_ (
.A(_111_),
.X(_112_)
);
sky130_fd_sc_hd__o31ai_1 _295_ (
.A1(req_rdy),
.A2(_073_),
.A3(_110_),
.B1(_112_),
.Y(_113_)
);
sky130_fd_sc_hd__buf_4 _296_ (
.A(_113_),
.X(_114_)
);
sky130_fd_sc_hd__nand2_1 _297_ (
.A(\ctrl.state.out[2] ),
.B(_106_),
.Y(_115_)
);
sky130_fd_sc_hd__o21ba_1 _298_ (
.A1(_073_),
.A2(_110_),
.B1_N(_115_),
.X(_116_)
);
sky130_fd_sc_hd__buf_2 _299_ (
.A(_116_),
.X(_117_)
);
sky130_fd_sc_hd__buf_2 _300_ (
.A(_117_),
.X(_118_)
);
sky130_fd_sc_hd__a22oi_1 _301_ (
.A1(\dpath.a_lt_b$in1[0] ),
.A2(_114_),
.B1(_118_),
.B2(\dpath.a_lt_b$in0[0] ),
.Y(_119_)
);
sky130_fd_sc_hd__nand2_1 _302_ (
.A(_109_),
.B(_119_),
.Y(_003_)
);
sky130_fd_sc_hd__nand2_1 _303_ (
.A(_103_),
.B(req_msg[1]),
.Y(_120_)
);
sky130_fd_sc_hd__a22oi_1 _304_ (
.A1(\dpath.a_lt_b$in1[1] ),
.A2(_114_),
.B1(_118_),
.B2(\dpath.a_lt_b$in0[1] ),
.Y(_121_)
);
sky130_fd_sc_hd__nand2_1 _305_ (
.A(_120_),
.B(_121_),
.Y(_004_)
);
sky130_fd_sc_hd__buf_2 _306_ (
.A(_113_),
.X(_122_)
);
sky130_fd_sc_hd__nand2_1 _307_ (
.A(\dpath.a_lt_b$in1[2] ),
.B(_122_),
.Y(_123_)
);
sky130_fd_sc_hd__a22oi_1 _308_ (
.A1(_103_),
.A2(req_msg[2]),
.B1(_118_),
.B2(\dpath.a_lt_b$in0[2] ),
.Y(_124_)
);
sky130_fd_sc_hd__nand2_1 _309_ (
.A(_123_),
.B(_124_),
.Y(_005_)
);
sky130_fd_sc_hd__nand2_1 _310_ (
.A(_103_),
.B(req_msg[3]),
.Y(_125_)
);
sky130_fd_sc_hd__a22oi_1 _311_ (
.A1(\dpath.a_lt_b$in1[3] ),
.A2(_114_),
.B1(_118_),
.B2(\dpath.a_lt_b$in0[3] ),
.Y(_126_)
);
sky130_fd_sc_hd__nand2_1 _312_ (
.A(_125_),
.B(_126_),
.Y(_006_)
);
sky130_fd_sc_hd__inv_1 _313_ (
.A(\dpath.a_lt_b$in1[4] ),
.Y(_127_)
);
sky130_fd_sc_hd__buf_6 _314_ (
.A(_117_),
.X(_128_)
);
sky130_fd_sc_hd__nor2_1 _315_ (
.A(_106_),
.B(req_msg[4]),
.Y(_129_)
);
sky130_fd_sc_hd__a221oi_2 _316_ (
.A1(_127_),
.A2(_114_),
.B1(_128_),
.B2(_048_),
.C1(_129_),
.Y(_007_)
);
sky130_fd_sc_hd__mux2i_1 _317_ (
.A0(\dpath.a_lt_b$in0[5] ),
.A1(req_msg[5]),
.S(_102_),
.Y(_130_)
);
sky130_fd_sc_hd__nand2_1 _318_ (
.A(\dpath.a_lt_b$in1[5] ),
.B(_122_),
.Y(_131_)
);
sky130_fd_sc_hd__o21ai_0 _319_ (
.A1(_122_),
.A2(_130_),
.B1(_131_),
.Y(_008_)
);
sky130_fd_sc_hd__nand2_1 _320_ (
.A(_103_),
.B(req_msg[6]),
.Y(_132_)
);
sky130_fd_sc_hd__a22oi_1 _321_ (
.A1(\dpath.a_lt_b$in1[6] ),
.A2(_114_),
.B1(_118_),
.B2(\dpath.a_lt_b$in0[6] ),
.Y(_133_)
);
sky130_fd_sc_hd__nand2_1 _322_ (
.A(_132_),
.B(_133_),
.Y(_009_)
);
sky130_fd_sc_hd__nand2_1 _323_ (
.A(_103_),
.B(req_msg[7]),
.Y(_134_)
);
sky130_fd_sc_hd__a22oi_1 _324_ (
.A1(\dpath.a_lt_b$in1[7] ),
.A2(_114_),
.B1(_118_),
.B2(\dpath.a_lt_b$in0[7] ),
.Y(_135_)
);
sky130_fd_sc_hd__nand2_1 _325_ (
.A(_134_),
.B(_135_),
.Y(_010_)
);
sky130_fd_sc_hd__mux2i_1 _326_ (
.A0(\dpath.a_lt_b$in0[8] ),
.A1(req_msg[8]),
.S(_102_),
.Y(_136_)
);
sky130_fd_sc_hd__nand2_1 _327_ (
.A(\dpath.a_lt_b$in1[8] ),
.B(_122_),
.Y(_137_)
);
sky130_fd_sc_hd__o21ai_0 _328_ (
.A1(_122_),
.A2(_136_),
.B1(_137_),
.Y(_011_)
);
sky130_fd_sc_hd__mux2i_1 _329_ (
.A0(\dpath.a_lt_b$in0[9] ),
.A1(req_msg[9]),
.S(_102_),
.Y(_138_)
);
sky130_fd_sc_hd__nand2_1 _330_ (
.A(\dpath.a_lt_b$in1[9] ),
.B(_122_),
.Y(_139_)
);
sky130_fd_sc_hd__o21ai_0 _331_ (
.A1(_122_),
.A2(_138_),
.B1(_139_),
.Y(_012_)
);
sky130_fd_sc_hd__mux2_2 _332_ (
.A0(\dpath.a_lt_b$in0[10] ),
.A1(req_msg[10]),
.S(_102_),
.X(_140_)
);
sky130_fd_sc_hd__mux2_1 _333_ (
.A0(_140_),
.A1(\dpath.a_lt_b$in1[10] ),
.S(_114_),
.X(_013_)
);
sky130_fd_sc_hd__nand2_1 _334_ (
.A(_103_),
.B(req_msg[11]),
.Y(_141_)
);
sky130_fd_sc_hd__a22oi_1 _335_ (
.A1(\dpath.a_lt_b$in1[11] ),
.A2(_114_),
.B1(_118_),
.B2(\dpath.a_lt_b$in0[11] ),
.Y(_142_)
);
sky130_fd_sc_hd__nand2_1 _336_ (
.A(_141_),
.B(_142_),
.Y(_014_)
);
sky130_fd_sc_hd__nand2_1 _337_ (
.A(\dpath.a_lt_b$in1[12] ),
.B(_122_),
.Y(_143_)
);
sky130_fd_sc_hd__a22oi_1 _338_ (
.A1(_102_),
.A2(req_msg[12]),
.B1(_118_),
.B2(\dpath.a_lt_b$in0[12] ),
.Y(_144_)
);
sky130_fd_sc_hd__nand2_1 _339_ (
.A(_143_),
.B(_144_),
.Y(_015_)
);
sky130_fd_sc_hd__mux2i_1 _340_ (
.A0(\dpath.a_lt_b$in0[13] ),
.A1(req_msg[13]),
.S(_102_),
.Y(_145_)
);
sky130_fd_sc_hd__nand2_1 _341_ (
.A(\dpath.a_lt_b$in1[13] ),
.B(_122_),
.Y(_146_)
);
sky130_fd_sc_hd__o21ai_0 _342_ (
.A1(_122_),
.A2(_145_),
.B1(_146_),
.Y(_016_)
);
sky130_fd_sc_hd__nand2_1 _343_ (
.A(_103_),
.B(req_msg[14]),
.Y(_147_)
);
sky130_fd_sc_hd__a22oi_1 _344_ (
.A1(\dpath.a_lt_b$in1[14] ),
.A2(_114_),
.B1(_118_),
.B2(\dpath.a_lt_b$in0[14] ),
.Y(_148_)
);
sky130_fd_sc_hd__nand2_1 _345_ (
.A(_147_),
.B(_148_),
.Y(_017_)
);
sky130_fd_sc_hd__nand2_1 _346_ (
.A(_103_),
.B(req_msg[15]),
.Y(_149_)
);
sky130_fd_sc_hd__a22oi_1 _347_ (
.A1(\dpath.a_lt_b$in1[15] ),
.A2(_114_),
.B1(_118_),
.B2(\dpath.a_lt_b$in0[15] ),
.Y(_150_)
);
sky130_fd_sc_hd__nand2_1 _348_ (
.A(_149_),
.B(_150_),
.Y(_018_)
);
sky130_fd_sc_hd__clkbuf_1 _349_ (
.A(_115_),
.X(_151_)
);
sky130_fd_sc_hd__o21ai_0 _350_ (
.A1(_106_),
.A2(req_msg[16]),
.B1(_151_),
.Y(_152_)
);
sky130_fd_sc_hd__nor3_4 _351_ (
.A(_073_),
.B(_110_),
.C(_115_),
.Y(_153_)
);
sky130_fd_sc_hd__buf_4 _352_ (
.A(_153_),
.X(_154_)
);
sky130_fd_sc_hd__a22oi_1 _353_ (
.A1(\dpath.a_lt_b$in1[0] ),
.A2(_128_),
.B1(_154_),
.B2(resp_msg[0]),
.Y(_155_)
);
sky130_fd_sc_hd__nor2_1 _354_ (
.A(\dpath.a_lt_b$in0[0] ),
.B(_112_),
.Y(_156_)
);
sky130_fd_sc_hd__a21oi_1 _355_ (
.A1(_152_),
.A2(_155_),
.B1(_156_),
.Y(_019_)
);
sky130_fd_sc_hd__clkbuf_1 _356_ (
.A(_105_),
.X(_157_)
);
sky130_fd_sc_hd__o21ai_0 _357_ (
.A1(_106_),
.A2(req_msg[17]),
.B1(_151_),
.Y(_158_)
);
sky130_fd_sc_hd__a22oi_1 _358_ (
.A1(\dpath.a_lt_b$in1[1] ),
.A2(_117_),
.B1(_154_),
.B2(resp_msg[1]),
.Y(_159_)
);
sky130_fd_sc_hd__a22oi_1 _359_ (
.A1(_051_),
.A2(_157_),
.B1(_158_),
.B2(_159_),
.Y(_020_)
);
sky130_fd_sc_hd__o21ai_0 _360_ (
.A1(req_msg[18]),
.A2(_107_),
.B1(_151_),
.Y(_160_)
);
sky130_fd_sc_hd__a22oi_1 _361_ (
.A1(\dpath.a_lt_b$in1[2] ),
.A2(_117_),
.B1(_153_),
.B2(resp_msg[2]),
.Y(_161_)
);
sky130_fd_sc_hd__a22oi_1 _362_ (
.A1(_050_),
.A2(_157_),
.B1(_160_),
.B2(_161_),
.Y(_021_)
);
sky130_fd_sc_hd__o21ai_0 _363_ (
.A1(req_msg[19]),
.A2(_107_),
.B1(_151_),
.Y(_162_)
);
sky130_fd_sc_hd__a22oi_1 _364_ (
.A1(\dpath.a_lt_b$in1[3] ),
.A2(_117_),
.B1(_153_),
.B2(resp_msg[3]),
.Y(_163_)
);
sky130_fd_sc_hd__a22oi_1 _365_ (
.A1(_049_),
.A2(_157_),
.B1(_162_),
.B2(_163_),
.Y(_022_)
);
sky130_fd_sc_hd__nand2_1 _366_ (
.A(\dpath.a_lt_b$in1[4] ),
.B(_128_),
.Y(_164_)
);
sky130_fd_sc_hd__a221oi_1 _367_ (
.A1(req_msg[20]),
.A2(_102_),
.B1(resp_msg[4]),
.B2(_153_),
.C1(_157_),
.Y(_165_)
);
sky130_fd_sc_hd__a22oi_1 _368_ (
.A1(_048_),
.A2(_157_),
.B1(_164_),
.B2(_165_),
.Y(_023_)
);
sky130_fd_sc_hd__nand2_1 _369_ (
.A(resp_msg[5]),
.B(_154_),
.Y(_166_)
);
sky130_fd_sc_hd__a221oi_1 _370_ (
.A1(req_msg[21]),
.A2(_102_),
.B1(_117_),
.B2(\dpath.a_lt_b$in1[5] ),
.C1(_157_),
.Y(_167_)
);
sky130_fd_sc_hd__a22oi_1 _371_ (
.A1(_047_),
.A2(_157_),
.B1(_166_),
.B2(_167_),
.Y(_024_)
);
sky130_fd_sc_hd__o21ai_0 _372_ (
.A1(req_msg[22]),
.A2(_106_),
.B1(_115_),
.Y(_168_)
);
sky130_fd_sc_hd__a22oi_1 _373_ (
.A1(\dpath.a_lt_b$in1[6] ),
.A2(_128_),
.B1(_154_),
.B2(resp_msg[6]),
.Y(_169_)
);
sky130_fd_sc_hd__a2bb2oi_1 _374_ (
.A1_N(\dpath.a_lt_b$in0[6] ),
.A2_N(_112_),
.B1(_168_),
.B2(_169_),
.Y(_025_)
);
sky130_fd_sc_hd__o21ai_0 _375_ (
.A1(req_msg[23]),
.A2(_107_),
.B1(_115_),
.Y(_170_)
);
sky130_fd_sc_hd__a22oi_1 _376_ (
.A1(\dpath.a_lt_b$in1[7] ),
.A2(_117_),
.B1(_153_),
.B2(resp_msg[7]),
.Y(_171_)
);
sky130_fd_sc_hd__a22oi_1 _377_ (
.A1(_043_),
.A2(_157_),
.B1(_170_),
.B2(_171_),
.Y(_026_)
);
sky130_fd_sc_hd__o21ai_0 _378_ (
.A1(req_msg[24]),
.A2(_107_),
.B1(_151_),
.Y(_172_)
);
sky130_fd_sc_hd__a22oi_1 _379_ (
.A1(\dpath.a_lt_b$in1[8] ),
.A2(_128_),
.B1(_154_),
.B2(resp_msg[8]),
.Y(_173_)
);
sky130_fd_sc_hd__nor2_1 _380_ (
.A(\dpath.a_lt_b$in0[8] ),
.B(_112_),
.Y(_174_)
);
sky130_fd_sc_hd__a21oi_1 _381_ (
.A1(_172_),
.A2(_173_),
.B1(_174_),
.Y(_027_)
);
sky130_fd_sc_hd__o21ai_0 _382_ (
.A1(req_msg[25]),
.A2(_107_),
.B1(_151_),
.Y(_175_)
);
sky130_fd_sc_hd__a22oi_1 _383_ (
.A1(\dpath.a_lt_b$in1[9] ),
.A2(_128_),
.B1(_154_),
.B2(resp_msg[9]),
.Y(_176_)
);
sky130_fd_sc_hd__nor2_1 _384_ (
.A(\dpath.a_lt_b$in0[9] ),
.B(_112_),
.Y(_177_)
);
sky130_fd_sc_hd__a21oi_1 _385_ (
.A1(_175_),
.A2(_176_),
.B1(_177_),
.Y(_028_)
);
sky130_fd_sc_hd__nand2_1 _386_ (
.A(\dpath.a_lt_b$in1[10] ),
.B(_128_),
.Y(_178_)
);
sky130_fd_sc_hd__a221oi_1 _387_ (
.A1(req_msg[26]),
.A2(_102_),
.B1(resp_msg[10]),
.B2(_153_),
.C1(_157_),
.Y(_179_)
);
sky130_fd_sc_hd__nor2_1 _388_ (
.A(\dpath.a_lt_b$in0[10] ),
.B(_112_),
.Y(_180_)
);
sky130_fd_sc_hd__a21oi_1 _389_ (
.A1(_178_),
.A2(_179_),
.B1(_180_),
.Y(_029_)
);
sky130_fd_sc_hd__o21ai_0 _390_ (
.A1(req_msg[27]),
.A2(_107_),
.B1(_151_),
.Y(_181_)
);
sky130_fd_sc_hd__a22oi_1 _391_ (
.A1(\dpath.a_lt_b$in1[11] ),
.A2(_128_),
.B1(_154_),
.B2(resp_msg[11]),
.Y(_182_)
);
sky130_fd_sc_hd__nor2_1 _392_ (
.A(\dpath.a_lt_b$in0[11] ),
.B(_112_),
.Y(_183_)
);
sky130_fd_sc_hd__a21oi_1 _393_ (
.A1(_181_),
.A2(_182_),
.B1(_183_),
.Y(_030_)
);
sky130_fd_sc_hd__o21ai_0 _394_ (
.A1(req_msg[28]),
.A2(_107_),
.B1(_151_),
.Y(_184_)
);
sky130_fd_sc_hd__a22oi_1 _395_ (
.A1(\dpath.a_lt_b$in1[12] ),
.A2(_128_),
.B1(_154_),
.B2(resp_msg[12]),
.Y(_185_)
);
sky130_fd_sc_hd__nor2_1 _396_ (
.A(\dpath.a_lt_b$in0[12] ),
.B(_112_),
.Y(_186_)
);
sky130_fd_sc_hd__a21oi_1 _397_ (
.A1(_184_),
.A2(_185_),
.B1(_186_),
.Y(_031_)
);
sky130_fd_sc_hd__o21ai_0 _398_ (
.A1(req_msg[29]),
.A2(_107_),
.B1(_151_),
.Y(_187_)
);
sky130_fd_sc_hd__a22oi_1 _399_ (
.A1(\dpath.a_lt_b$in1[13] ),
.A2(_117_),
.B1(_154_),
.B2(resp_msg[13]),
.Y(_188_)
);
sky130_fd_sc_hd__nor2_1 _400_ (
.A(\dpath.a_lt_b$in0[13] ),
.B(_112_),
.Y(_189_)
);
sky130_fd_sc_hd__a21oi_1 _401_ (
.A1(_187_),
.A2(_188_),
.B1(_189_),
.Y(_032_)
);
sky130_fd_sc_hd__o21ai_0 _402_ (
.A1(req_msg[30]),
.A2(_107_),
.B1(_151_),
.Y(_190_)
);
sky130_fd_sc_hd__a22oi_1 _403_ (
.A1(\dpath.a_lt_b$in1[14] ),
.A2(_117_),
.B1(_154_),
.B2(resp_msg[14]),
.Y(_191_)
);
sky130_fd_sc_hd__nor2_1 _404_ (
.A(\dpath.a_lt_b$in0[14] ),
.B(_112_),
.Y(_192_)
);
sky130_fd_sc_hd__a21oi_1 _405_ (
.A1(_190_),
.A2(_191_),
.B1(_192_),
.Y(_033_)
);
sky130_fd_sc_hd__nand2_1 _406_ (
.A(\dpath.a_lt_b$in1[15] ),
.B(_128_),
.Y(_193_)
);
sky130_fd_sc_hd__o21ai_0 _407_ (
.A1(req_msg[31]),
.A2(_106_),
.B1(_115_),
.Y(_194_)
);
sky130_fd_sc_hd__inv_1 _408_ (
.A(\dpath.a_lt_b$in0[15] ),
.Y(_195_)
);
sky130_fd_sc_hd__or4_1 _409_ (
.A(\dpath.a_lt_b$in1[15] ),
.B(_195_),
.C(_072_),
.D(_115_),
.X(_196_)
);
sky130_fd_sc_hd__a32oi_1 _410_ (
.A1(_193_),
.A2(_194_),
.A3(_196_),
.B1(_157_),
.B2(_195_),
.Y(_034_)
);
sky130_fd_sc_hd__dfxtp_1 _411_ (
.CLK(clk),
.D(_000_),
.Q(req_rdy)
);
sky130_fd_sc_hd__dfxtp_1 _412_ (
.CLK(clk),
.D(_001_),
.Q(\ctrl.state.out[1] )
);
sky130_fd_sc_hd__dfxtp_1 _413_ (
.CLK(clk),
.D(_002_),
.Q(\ctrl.state.out[2] )
);
sky130_fd_sc_hd__dfxtp_1 _414_ (
.CLK(clk),
.D(_003_),
.Q(\dpath.a_lt_b$in1[0] )
);
sky130_fd_sc_hd__dfxtp_1 _415_ (
.CLK(clk),
.D(_004_),
.Q(\dpath.a_lt_b$in1[1] )
);
sky130_fd_sc_hd__dfxtp_1 _416_ (
.CLK(clk),
.D(_005_),
.Q(\dpath.a_lt_b$in1[2] )
);
sky130_fd_sc_hd__dfxtp_1 _417_ (
.CLK(clk),
.D(_006_),
.Q(\dpath.a_lt_b$in1[3] )
);
sky130_fd_sc_hd__dfxtp_1 _418_ (
.CLK(clk),
.D(_007_),
.Q(\dpath.a_lt_b$in1[4] )
);
sky130_fd_sc_hd__dfxtp_1 _419_ (
.CLK(clk),
.D(_008_),
.Q(\dpath.a_lt_b$in1[5] )
);
sky130_fd_sc_hd__dfxtp_1 _420_ (
.CLK(clk),
.D(_009_),
.Q(\dpath.a_lt_b$in1[6] )
);
sky130_fd_sc_hd__dfxtp_1 _421_ (
.CLK(clk),
.D(_010_),
.Q(\dpath.a_lt_b$in1[7] )
);
sky130_fd_sc_hd__dfxtp_1 _422_ (
.CLK(clk),
.D(_011_),
.Q(\dpath.a_lt_b$in1[8] )
);
sky130_fd_sc_hd__dfxtp_1 _423_ (
.CLK(clk),
.D(_012_),
.Q(\dpath.a_lt_b$in1[9] )
);
sky130_fd_sc_hd__dfxtp_1 _424_ (
.CLK(clk),
.D(_013_),
.Q(\dpath.a_lt_b$in1[10] )
);
sky130_fd_sc_hd__dfxtp_1 _425_ (
.CLK(clk),
.D(_014_),
.Q(\dpath.a_lt_b$in1[11] )
);
sky130_fd_sc_hd__dfxtp_1 _426_ (
.CLK(clk),
.D(_015_),
.Q(\dpath.a_lt_b$in1[12] )
);
sky130_fd_sc_hd__dfxtp_1 _427_ (
.CLK(clk),
.D(_016_),
.Q(\dpath.a_lt_b$in1[13] )
);
sky130_fd_sc_hd__dfxtp_1 _428_ (
.CLK(clk),
.D(_017_),
.Q(\dpath.a_lt_b$in1[14] )
);
sky130_fd_sc_hd__dfxtp_1 _429_ (
.CLK(clk),
.D(_018_),
.Q(\dpath.a_lt_b$in1[15] )
);
sky130_fd_sc_hd__dfxtp_1 _430_ (
.CLK(clk),
.D(_019_),
.Q(\dpath.a_lt_b$in0[0] )
);
sky130_fd_sc_hd__dfxtp_1 _431_ (
.CLK(clk),
.D(_020_),
.Q(\dpath.a_lt_b$in0[1] )
);
sky130_fd_sc_hd__dfxtp_1 _432_ (
.CLK(clk),
.D(_021_),
.Q(\dpath.a_lt_b$in0[2] )
);
sky130_fd_sc_hd__dfxtp_1 _433_ (
.CLK(clk),
.D(_022_),
.Q(\dpath.a_lt_b$in0[3] )
);
sky130_fd_sc_hd__dfxtp_1 _434_ (
.CLK(clk),
.D(_023_),
.Q(\dpath.a_lt_b$in0[4] )
);
sky130_fd_sc_hd__dfxtp_1 _435_ (
.CLK(clk),
.D(_024_),
.Q(\dpath.a_lt_b$in0[5] )
);
sky130_fd_sc_hd__dfxtp_1 _436_ (
.CLK(clk),
.D(_025_),
.Q(\dpath.a_lt_b$in0[6] )
);
sky130_fd_sc_hd__dfxtp_1 _437_ (
.CLK(clk),
.D(_026_),
.Q(\dpath.a_lt_b$in0[7] )
);
sky130_fd_sc_hd__dfxtp_1 _438_ (
.CLK(clk),
.D(_027_),
.Q(\dpath.a_lt_b$in0[8] )
);
sky130_fd_sc_hd__dfxtp_1 _439_ (
.CLK(clk),
.D(_028_),
.Q(\dpath.a_lt_b$in0[9] )
);
sky130_fd_sc_hd__dfxtp_1 _440_ (
.CLK(clk),
.D(_029_),
.Q(\dpath.a_lt_b$in0[10] )
);
sky130_fd_sc_hd__dfxtp_1 _441_ (
.CLK(clk),
.D(_030_),
.Q(\dpath.a_lt_b$in0[11] )
);
sky130_fd_sc_hd__dfxtp_1 _442_ (
.CLK(clk),
.D(_031_),
.Q(\dpath.a_lt_b$in0[12] )
);
sky130_fd_sc_hd__dfxtp_1 _443_ (
.CLK(clk),
.D(_032_),
.Q(\dpath.a_lt_b$in0[13] )
);
sky130_fd_sc_hd__dfxtp_1 _444_ (
.CLK(clk),
.D(_033_),
.Q(\dpath.a_lt_b$in0[14] )
);
sky130_fd_sc_hd__dfxtp_1 _445_ (
.CLK(clk),
.D(_034_),
.Q(\dpath.a_lt_b$in0[15] )
);
endmodule
|
//==================================================================================================
// Filename : musb_idex_register.v
// Created On : 2014-09-27 20:34:32
// Last Modified : 2015-05-31 13:04:35
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Pipeline register: ID -> EX
//==================================================================================================
module musb_idex_register(
input clk, // Main clock
input rst, // Main reset
input [4:0] id_alu_operation, // ALU operation from ID stage
input [31:0] id_data_rs, // Data Rs (forwarded)
input [31:0] id_data_rt, // Data Rt (forwarded)
input id_gpr_we, // GPR write enable
input id_mem_to_gpr_select, // Select MEM/ALU to GPR
input id_mem_write, // write to memory
input [1:0] id_alu_port_a_select, // Select: GPR, shamt, 0x00000004
input [1:0] id_alu_port_b_select, // Select: GPR, Imm16, PCAdd4
input [1:0] id_gpr_wa_select, // Select: direccion: Rt, Rd, $31
input id_mem_byte, // byte access
input id_mem_halfword, // halfword access
input id_mem_data_sign_ext, // Zero/Sign extend
input [4:0] id_rs, // Rs
input [4:0] id_rt, // Rt
input id_imm_sign_ext, // extend the imm16
input [15:0] id_sign_imm16, // sign_ext(imm16)
input [31:0] id_cp0_data, //
input [31:0] id_exception_pc, // Current PC
input id_movn,
input id_movz,
input id_llsc,
input id_kernel_mode,
input id_is_bds,
input id_trap,
input id_trap_condition,
input id_ex_exception_source,
input id_mem_exception_source,
input id_flush, // clean
input id_stall, // Stall ID stage
input ex_stall, // Stall EX stage
output reg [4:0] ex_alu_operation, // Same signals, but on EX stage
output reg [31:0] ex_data_rs, //
output reg [31:0] ex_data_rt, //
output reg ex_gpr_we, //
output reg ex_mem_to_gpr_select, //
output reg ex_mem_write, //
output reg [1:0] ex_alu_port_a_select, //
output reg [1:0] ex_alu_port_b_select, //
output reg [1:0] ex_gpr_wa_select, //
output reg ex_mem_byte, //
output reg ex_mem_halfword, //
output reg ex_mem_data_sign_ext, //
output reg [4:0] ex_rs, //
output reg [4:0] ex_rt, //
output reg [16:0] ex_sign_imm16, //
output reg [31:0] ex_cp0_data,
output reg [31:0] ex_exception_pc,
output reg ex_movn,
output reg ex_movz,
output reg ex_llsc,
output reg ex_kernel_mode,
output reg ex_is_bds,
output reg ex_trap,
output reg ex_trap_condition,
output reg ex_ex_exception_source,
output reg ex_mem_exception_source
);
// sign extend the imm16
wire [16:0] id_imm_extended = (id_imm_sign_ext) ? {id_sign_imm16[15], id_sign_imm16[15:0]} : {1'b0, id_sign_imm16};
//--------------------------------------------------------------------------
// Propagate signals
// Clear only critical signals: op, WE, MEM write and Next PC
//--------------------------------------------------------------------------
always @(posedge clk) begin
ex_alu_operation <= (rst) ? 5'b0 : ((ex_stall) ? ex_alu_operation : ((id_stall | id_flush) ? 5'b0 : id_alu_operation));
ex_data_rs <= (rst) ? 32'b0 : ((ex_stall) ? ex_data_rs : id_data_rs);
ex_data_rt <= (rst) ? 32'b0 : ((ex_stall) ? ex_data_rt : id_data_rt);
ex_gpr_we <= (rst) ? 1'b0 : ((ex_stall) ? ex_gpr_we : ((id_stall | id_flush) ? 1'b0 : id_gpr_we));
ex_mem_to_gpr_select <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_to_gpr_select : ((id_stall | id_flush) ? 1'b0 : id_mem_to_gpr_select));
ex_mem_write <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_write : ((id_stall | id_flush) ? 1'b0 : id_mem_write));
ex_alu_port_a_select <= (rst) ? 2'b0 : ((ex_stall) ? ex_alu_port_a_select : id_alu_port_a_select);
ex_alu_port_b_select <= (rst) ? 2'b0 : ((ex_stall) ? ex_alu_port_b_select : id_alu_port_b_select);
ex_gpr_wa_select <= (rst) ? 2'b0 : ((ex_stall) ? ex_gpr_wa_select : id_gpr_wa_select);
ex_mem_byte <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_byte : id_mem_byte);
ex_mem_halfword <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_halfword : id_mem_halfword);
ex_mem_data_sign_ext <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_data_sign_ext : id_mem_data_sign_ext);
ex_rs <= (rst) ? 5'b0 : ((ex_stall) ? ex_rs : id_rs);
ex_rt <= (rst) ? 5'b0 : ((ex_stall) ? ex_rt : id_rt);
ex_sign_imm16 <= (rst) ? 17'b0 : ((ex_stall) ? ex_sign_imm16 : id_imm_extended);
ex_cp0_data <= (rst) ? 32'b0 : ((ex_stall) ? ex_cp0_data : id_cp0_data);
ex_exception_pc <= (rst) ? 32'b0 : ((ex_stall) ? ex_exception_pc : id_exception_pc);
ex_movn <= (rst) ? 1'b0 : ((ex_stall) ? ex_movn : ((id_stall | id_flush) ? 1'b0 : id_movn));
ex_movz <= (rst) ? 1'b0 : ((ex_stall) ? ex_movz : ((id_stall | id_flush) ? 1'b0 : id_movz));
ex_llsc <= (rst) ? 1'b0 : ((ex_stall) ? ex_llsc : ((id_stall | id_flush) ? 1'b0 : id_llsc));
ex_kernel_mode <= (rst) ? 1'b0 : ((ex_stall) ? ex_kernel_mode : id_kernel_mode);
ex_is_bds <= (rst) ? 1'b0 : ((ex_stall) ? ex_is_bds : id_is_bds);
ex_trap <= (rst) ? 1'b0 : ((ex_stall) ? ex_trap : ((id_stall | id_flush) ? 1'b0 : id_trap));
ex_trap_condition <= (rst) ? 1'b0 : ((ex_stall) ? ex_trap_condition : id_trap_condition);
ex_ex_exception_source <= (rst) ? 1'b0 : ((ex_stall) ? ex_ex_exception_source : ((id_stall | id_flush) ? 1'b0 : id_ex_exception_source));
ex_mem_exception_source <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_exception_source : ((id_stall | id_flush) ? 1'b0 : id_mem_exception_source));
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: franp.com
// Engineer: Fran Pregernik <[email protected]>
//
// Create Date: 12/30/2016 10:48:02 AM
// Design Name:
// Module Name: azimuth_signal_generator
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module asg_ft_generator #
(
parameter SIZE = 3200
)
(
input wire RADAR_TRIG_PE,
// constant microseconds clock
input wire USEC_PE,
// Declare the attributes above the port declaration
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SYS_CLK CLK" *)
// Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
// Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
(* X_INTERFACE_PARAMETER = "FREQ_HZ 100000000" *)
input wire SYS_CLK,
output wire GEN_SIGNAL
);
reg EN = 1;
reg [SIZE-1:0] DATA = 0;
always @* begin
// 3 microsecond pulses
DATA[102:100] <= 3'b111;
DATA[502:500] <= 3'b111;
DATA[902:900] <= 3'b111;
DATA[1302:1300] <= 3'b111;
DATA[1702:1700] <= 3'b111;
DATA[2102:2100] <= 3'b111;
DATA[2502:2500] <= 3'b111;
DATA[2902:2900] <= 3'b111;
end
azimuth_signal_generator #(SIZE) asg (
.EN(EN),
.TRIG(RADAR_TRIG_PE),
.DATA(DATA),
.CLK_PE(USEC_PE),
.SYS_CLK(SYS_CLK),
.GEN_SIGNAL(GEN_SIGNAL)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_4_V
`define SKY130_FD_SC_HD__EINVN_4_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_4_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_Current.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Control_Current
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Control_Current
(
CLK_IN,
reset,
enb_1_2000_0,
Reest,
Err,
param_current_p_gain,
param_current_i_gain,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reest;
input signed [17:0] Err; // sfix18_En14
input signed [17:0] param_current_p_gain; // sfix18_En10
input signed [17:0] param_current_i_gain; // sfix18_En2
output signed [17:0] Out; // sfix18_En12
wire signed [35:0] Product2_out1; // sfix36_En24
wire signed [35:0] Convert_Data_Type1_out1; // sfix36_En23
wire signed [17:0] Constant2_out1; // sfix18_En31
wire signed [35:0] Product_out1; // sfix36_En33
wire signed [17:0] pre_integrator; // sfix18_En15
wire signed [35:0] pre_integrator_1; // sfix36_En29
wire signed [35:0] Constant_out1; // sfix36_En29
wire signed [35:0] u; // sfix36_En23
wire PI_Sat_out2;
wire Clamp_out1;
wire switch_compare_1;
wire signed [35:0] Switch_out1; // sfix36_En29
wire signed [31:0] I_term; // sfix32_En26
wire signed [36:0] Add_add_cast; // sfix37_En29
wire signed [36:0] Add_add_cast_1; // sfix37_En29
wire signed [36:0] Add_add_temp; // sfix37_En29
wire signed [31:0] Add_out1; // sfix32_En26
wire signed [39:0] Sum1_add_cast; // sfix40_En26
wire signed [39:0] Sum1_add_cast_1; // sfix40_En26
wire signed [39:0] Sum1_add_temp; // sfix40_En26
wire signed [35:0] u_sat; // sfix36_En23
wire signed [17:0] D_Data_Type_out1; // sfix18_En12
// Control Current
// <S7>/Product2
assign Product2_out1 = param_current_p_gain * Err;
// <S7>/Convert_Data_Type1
velocityControlHdl_Convert_Data_Type1 u_Convert_Data_Type1 (.In1(Product2_out1), // sfix36_En24
.Out1(Convert_Data_Type1_out1) // sfix36_En23
);
// <S7>/Constant2
assign Constant2_out1 = 18'sb010100111110001011;
// <S7>/Product
assign Product_out1 = param_current_i_gain * Constant2_out1;
// <S7>/Maintain_Range
velocityControlHdl_Maintain_Range u_Maintain_Range (.In1(Product_out1), // sfix36_En33
.Out1(pre_integrator) // sfix18_En15
);
// <S7>/Product1
assign pre_integrator_1 = Err * pre_integrator;
// <S7>/Constant
assign Constant_out1 = 36'sh000000000;
// <S7>/Clamp
velocityControlHdl_Clamp u_Clamp (.preIntegrator(pre_integrator_1), // sfix36_En29
.preSat(u), // sfix36_En23
.saturated(PI_Sat_out2),
.Clamp(Clamp_out1)
);
assign switch_compare_1 = (Clamp_out1 > 1'b0 ? 1'b1 :
1'b0);
// <S7>/Switch
assign Switch_out1 = (switch_compare_1 == 1'b0 ? pre_integrator_1 :
Constant_out1);
// <S7>/Add
assign Add_add_cast = Switch_out1;
assign Add_add_cast_1 = {{2{I_term[31]}}, {I_term, 3'b000}};
assign Add_add_temp = Add_add_cast + Add_add_cast_1;
assign Add_out1 = ((Add_add_temp[36] == 1'b0) && (Add_add_temp[35:34] != 2'b00) ? 32'sb01111111111111111111111111111111 :
((Add_add_temp[36] == 1'b1) && (Add_add_temp[35:34] != 2'b11) ? 32'sb10000000000000000000000000000000 :
$signed(Add_add_temp[34:3])));
// <S7>/Reset_Delay
velocityControlHdl_Reset_Delay u_Reset_Delay (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reest),
.In(Add_out1), // sfix32_En26
.Out(I_term) // sfix32_En26
);
// <S7>/Sum1
assign Sum1_add_cast = {Convert_Data_Type1_out1[35], {Convert_Data_Type1_out1, 3'b000}};
assign Sum1_add_cast_1 = I_term;
assign Sum1_add_temp = Sum1_add_cast + Sum1_add_cast_1;
assign u = Sum1_add_temp[38:3];
// <S7>/PI_Sat
velocityControlHdl_PI_Sat u_PI_Sat (.In1(u), // sfix36_En23
.Out1(u_sat), // sfix36_En23
.saturated(PI_Sat_out2)
);
// <S7>/D_Data_Type
assign D_Data_Type_out1 = u_sat[28:11];
assign Out = D_Data_Type_out1;
endmodule // velocityControlHdl_Control_Current
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 21:06:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0/system_ov7670_vga_1_0_stub.v
// Design : system_ov7670_vga_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_vga,Vivado 2016.4" *)
module system_ov7670_vga_1_0(clk_x2, active, data, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_x2,active,data[7:0],rgb[15:0]" */;
input clk_x2;
input active;
input [7:0]data;
output [15:0]rgb;
endmodule
|
`timescale 1ns / 1ps
module DMA_Controller #(
parameter N = 6,
parameter WIDTH = 16,
parameter ADDR = 12,
parameter M_WIDTH = 2*WIDTH+N-1
)(
input clk,
input start,
// MATRIX MEMORY A
output reg A_rd,
output reg [ADDR-1:0] A_addr,
input [N*WIDTH-1:0] A_dout,
// MATRIX MEMORY B
output reg B_rd,
output reg [ADDR-1:0] B_addr,
input [N*WIDTH-1:0] B_dout,
// MATRIX MEMORY C
output reg C_wr,
output reg [ADDR-1:0] C_addr,
output reg [N*M_WIDTH-1:0] C_din,
// MAC BASE INTERFACE
output reg sof,
output reg [N*WIDTH-1:0] A,
output reg [WIDTH-1:0] B,
input [N*M_WIDTH-1:0] C,
input [N-1:0] valid
);
reg state;
parameter
IDLE = 1'b0,
FETCH = 1'b1;
initial begin
A <= 0;
B <= 0;
sof <= 1'b0;
state <= IDLE;
A_rd <= 1'b0;
B_rd <= 1'b0;
C_wr <= 1'b0;
A_addr <= 0;
B_addr <= 0;
C_addr <= 0;
C_din <= 0;
end
always@(posedge clk) begin
case(state)
IDLE: begin
A_addr <= 0;
B_addr <= 0;
A_rd <= 1'b0;
B_rd <= 1'b0;
sof <= 1'b0;
if(start) begin
A_addr <= 0;
B_addr <= 0;
A_rd <= 1'b1;
B_rd <= 1'b1;
sof <= 1'b0;
state <= FETCH;
end
end
FETCH: begin
if(B_addr!= N) begin
B_rd <= 1'b1;
if(A_addr != N) begin
A_rd <= 1'b1;
A_addr <= A_addr + 1;
A <= A_dout;
B <= (B_dout >> WIDTH*A_addr);
sof <= 1'b1;
if(A_addr == N-1) begin
B_addr <= B_addr + 1;
A_addr <= 0;
end
if(A_addr == 0) begin
// sof <= 1'b0;
end
end
end
else
state <= IDLE;
end
endcase
end
always@(posedge clk) begin
if(&valid) begin
C_wr <= 1'b1;
C_addr <= C_addr + 1;
C_din <= C;
end
else begin
C_wr <= 1'b0;
C_din <= 0;
end
end
/*genvar i;
generate for (i = 0; i < N; i = i + 1) begin
always@(posedge clk) begin
if(valid[i]) begin
C_wr <= 1'b1;
C_addr <= C_addr + 1;
C_din <= C_din && M_WIDTH{1'b1};
end
end endgenerate
*/
endmodule
|
/******************************************************************************/
/* FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
/***** Comparator *****/
/**************************************************************************************************/
module COMPARATOR #(parameter WIDTH = 32)
(input wire [WIDTH-1:0] DIN0,
input wire [WIDTH-1:0] DIN1,
output wire [WIDTH-1:0] DOUT0,
output wire [WIDTH-1:0] DOUT1);
wire comp_rslt = (DIN0 < DIN1);
function [WIDTH-1:0] mux;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT0 = mux(DIN1, DIN0, comp_rslt);
assign DOUT1 = mux(DIN0, DIN1, comp_rslt);
endmodule
/***** FIFO of only two entries *****/
/**************************************************************************************************/
module MRE2 #(parameter FIFO_SIZE = 1, // dummy, just for portability
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule
/***** Sorter cell emitting multiple values at once *****/
/**************************************************************************************************/
module SCELL #(parameter SORTW = 32,
parameter M_LOG = 2)
(input wire CLK,
input wire RST,
input wire valid1,
input wire valid2,
output wire deq1,
output wire deq2,
input wire [(SORTW<<M_LOG)-1:0] din1,
input wire [(SORTW<<M_LOG)-1:0] din2,
input wire full,
output wire [(SORTW<<M_LOG)-1:0] dout,
output wire enq);
function [(SORTW<<M_LOG)-1:0] mux;
input [(SORTW<<M_LOG)-1:0] a;
input [(SORTW<<M_LOG)-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
wire cmp = (din1[SORTW-1:0] < din2[SORTW-1:0]);
wire [(SORTW<<M_LOG)-1:0] cmp_dout = mux(din2, din1, cmp);
wire F_enq;
wire F_deq;
wire F_emp;
wire F_full;
wire [(SORTW<<M_LOG)-1:0] F_dot;
MRE2 #(1,(SORTW<<M_LOG)) F(.CLK(CLK), .RST(RST), .enq(F_enq), .deq(F_deq),
.din(cmp_dout), .dot(F_dot), .emp(F_emp), .full(F_full));
assign F_enq = &{~F_full,valid1,valid2}; // assign F_enq = (!F_full && valid1 && valid2);
assign F_deq = ~|{full,F_emp}; // assign F_deq = !full && !F_emp;
reg [(SORTW<<M_LOG)-1:0] fbdata;
reg [(SORTW<<M_LOG)-1:0] fbdata_a; // duplicated register
reg [(SORTW<<M_LOG)-1:0] fbdata_b; // duplicated register
reg fbinvoke;
assign enq = (F_deq && fbinvoke);
assign deq1 = (F_enq && cmp);
assign deq2 = (F_enq && !cmp);
localparam P_DATAWIDTH = 32;
wire [P_DATAWIDTH-1:0] a, b, c, d, e, f, g, h;
wire [P_DATAWIDTH-1:0] e_a, f_a, g_a, h_a; // for duplicated register
wire [P_DATAWIDTH-1:0] e_b, f_b, g_b, h_b; // for duplicated register
assign a = F_dot[ 31: 0];
assign b = F_dot[ 63:32];
assign c = F_dot[ 95:64];
assign d = F_dot[127:96];
assign e = fbdata[ 31: 0];
assign f = fbdata[ 63:32];
assign g = fbdata[ 95:64];
assign h = fbdata[127:96];
assign e_a = fbdata_a[ 31: 0];
assign f_a = fbdata_a[ 63:32];
assign g_a = fbdata_a[ 95:64];
assign h_a = fbdata_a[127:96];
assign e_b = fbdata_b[ 31: 0];
assign f_b = fbdata_b[ 63:32];
assign g_b = fbdata_b[ 95:64];
assign h_b = fbdata_b[127:96];
wire t0_c0 = (a < h);
wire t0_c1 = (b < g);
wire t0_c2 = (c < f);
wire t0_c3 = (d < e);
wire t0_x0 = t0_c0 ^ t0_c1;
wire t0_x1 = t0_c2 ^ t0_c3;
wire t0 = t0_x0 ^ t0_x1;
wire s2_c0 = (b < e);
wire s2_c1 = (a < f);
wire s3_c0 = (c < h);
wire s3_c1 = (d < g);
wire s4_c0 = (a < g);
wire s4_c1 = (b < f);
wire s4_c2 = (c < e);
wire s5_c0 = (d < f);
wire s5_c1 = (c < g);
wire s5_c2 = (b < h);
wire s0 = (a < e);
wire s1 = (d < h);
wire [1:0] s2 = {s0, (s2_c0 ^ s2_c1)};
wire [1:0] s3 = {s1, (s3_c0 ^ s3_c1)};
wire [2:0] s4 = {s2, (s4_c0 ^ s4_c1 ^ s4_c2)};
wire [2:0] s5 = {s3, (s5_c0 ^ s5_c1 ^ s5_c2)};
wire [3:0] s6 = {s4, t0};
wire [3:0] s7 = {s5, t0};
wire [P_DATAWIDTH-1:0] m0, m1, m2, m3, m4, m5, m6, m7;
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [32-1:0] mux4in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [1:0] sel;
begin
case (sel)
2'b00: mux4in32 = a;
2'b01: mux4in32 = b;
2'b10: mux4in32 = c;
2'b11: mux4in32 = d;
endcase
end
endfunction
function [32-1:0] mux6in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [2:0] sel;
begin
casex (sel)
3'b000: mux6in32 = a;
3'b001: mux6in32 = b;
3'b100: mux6in32 = c;
3'b101: mux6in32 = d;
3'bx10: mux6in32 = e;
3'bx11: mux6in32 = f;
endcase
end
endfunction
function [32-1:0] mux12in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [32-1:0] g;
input [32-1:0] h;
input [32-1:0] i;
input [32-1:0] j;
input [32-1:0] k;
input [32-1:0] l;
input [3:0] sel;
begin
casex (sel)
4'b0000: mux12in32 = a;
4'b0001: mux12in32 = b;
4'b0010: mux12in32 = c;
4'b0011: mux12in32 = d;
4'b1000: mux12in32 = e;
4'b1001: mux12in32 = f;
4'b1010: mux12in32 = g;
4'b1011: mux12in32 = h;
4'bx100: mux12in32 = i;
4'bx101: mux12in32 = j;
4'bx110: mux12in32 = k;
4'bx111: mux12in32 = l;
endcase
end
endfunction
assign m0 = mux32(e, a, s0);
assign m1 = mux32(d, h, s1);
assign m2 = mux4in32(f, a, b, e, s2);
assign m3 = mux4in32(c, h, g, d, s3);
assign m4 = mux6in32(g, a, e, c, b, f, s4);
assign m5 = mux6in32(b, h, d, f, g, c, s5);
// using duplicated registers
assign m6 = mux12in32(h_a, a, b, g_a, f_a, c, d, e_a, f_a, c, b, g_a, s6);
assign m7 = mux12in32(a, h_b, g_b, b, c, f_b, e_b, d, c, f_b, g_b, b, s7);
// output and feedback
//////////////////////////////////////////////////////////
assign dout = {m6,m4,m2,m0}; // output
always @(posedge CLK) begin // feedback
if (RST) begin
fbdata <= 0;
fbdata_a <= 0;
fbdata_b <= 0;
fbinvoke <= 0;
end else begin
if (F_deq) begin
fbdata <= {m1,m3,m5,m7};
fbdata_a <= {m1,m3,m5,m7};
fbdata_b <= {m1,m3,m5,m7};
fbinvoke <= 1;
end
end
end
endmodule
/***** general FIFO (BRAM Version) *****/
/**************************************************************************************************/
module BFIFO #(parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
always @(posedge CLK) dot <= mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule
/***** Input Module Pre *****/
/**************************************************************************************************/
module INMOD2(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] din, // input data
input wire den, // input data enable
input wire IB_full, // the next module is full ?
output wire rx_wait,
output wire [`MERGW-1:0] dot, // this module's data output
output wire IB_enq, // the next module's enqueue signal
output reg [1:0] im_req); // DRAM data request
wire req;
reg deq;
wire [`DRAMW-1:0] im_dot;
(* mark_debug = "true" *) wire [`IB_SIZE:0] im_cnt;
wire im_full, im_emp;
wire im_enq = den;
wire im_deq = (req && !im_emp);
assign rx_wait = im_cnt[`IB_SIZE-1];
always @(posedge CLK) im_req <= (im_cnt==0) ? 3 : (im_cnt<`REQ_THRE);
always @(posedge CLK) deq <= im_deq;
BFIFO #(`IB_SIZE, `DRAMW) // note, using BRAM
imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq), .din(din),
.dot(im_dot), .emp(im_emp), .full(im_full), .cnt(im_cnt));
INMOD inmod(.CLK(CLK), .RST(RST), .d_dout(im_dot), .d_douten(deq),
.IB_full(IB_full), .im_dot(dot), .IB_enq(IB_enq), .im_req(req));
endmodule
/***** Input Module *****/
/**************************************************************************************************/ // todo
module INMOD(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] d_dout, // DRAM output
input wire d_douten, // DRAM output enable
input wire IB_full, // INBUF is full ?
output wire [`MERGW-1:0] im_dot, // this module's data output
output wire IB_enq,
output wire im_req); // DRAM data request
reg [`DRAMW-1:0] dot_t; // shift register to feed 32bit data
reg [1:0] cnte; // the number of enqueued elements in one block
reg cntez; // cnte==0 ?
reg cntef; // cnte==15 ?
wire [`DRAMW-1:0] dot;
wire im_emp, im_full;
wire im_enq = d_douten; // (!im_full && d_douten);
wire im_deq = (IB_enq && cntef); // old version may have a bug here!!
function [`MERGW-1:0] mux;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign IB_enq = (!IB_full && !im_emp); // enqueue signal for the next module
assign im_req = (im_emp || im_deq); // note!!!
assign im_dot = mux(dot_t[`MERGW-1:0], dot[`MERGW-1:0], cntez);
always @(posedge CLK) begin
if (RST) begin
cnte <= 0;
end else begin
if (IB_enq) cnte <= cnte + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
cntez <= 1;
end else begin
case ({IB_enq, (cnte==3)})
2'b10: cntez <= 0;
2'b11: cntez <= 1;
endcase
end
end
always @(posedge CLK) begin
if (RST) begin
cntef <= 0;
end else begin
case ({IB_enq, (cnte==2)})
2'b10: cntef <= 0;
2'b11: cntef <= 1;
endcase
end
end
always @(posedge CLK) begin
case ({IB_enq, cntez})
2'b10: dot_t <= {`MERGW'b0, dot_t[`DRAMW-1:`MERGW]};
2'b11: dot_t <= {`MERGW'b0, dot[`DRAMW-1:`MERGW]};
endcase
end
MRE2 #(1, `DRAMW) imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq),
.din(d_dout), .dot(dot), .emp(im_emp), .full(im_full));
endmodule
/***** input buffer module *****/
/**************************************************************************************************/
module INBUF(input wire CLK,
input wire RST,
output wire ib_full, // this module is full
input wire full, // next moldule's full
output wire enq, // next module's enqueue
input wire [`MERGW-1:0] din, // data in
output wire [`MERGW-1:0] dot, // data out
input wire ib_enq, // this module's enqueue
input wire [`PHASE_W] phase, // current phase
input wire idone); // iteration done, this module's enqueue
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`MERGW-1:0] mux128;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux128 = a;
1'b1: mux128 = b;
endcase
end
endfunction
/*****************************************/
wire [`MERGW-1:0] F_dout;
wire F_deq, F_emp;
reg [31:0] ecnt; // the number of elements in one iteration
reg ecntz; // ecnt==0 ?
wire f_full;
MRE2 #(1,`MERGW) F(.CLK(CLK), .RST(RST), .enq(ib_enq), .deq(F_deq), // input buffer FIFO
.din(din), .dot(F_dout), .emp(F_emp), .full(f_full));
assign ib_full = mux1(f_full, 0, F_deq); // INBUF back_pressure
/*****************************************/
assign enq = !full && (!F_emp || ecntz); // enqueue for the next buffer
assign F_deq = enq && (ecnt!=0); //
assign dot = mux128(F_dout, `MAX_VALUE, ecntz);
always @(posedge CLK) begin
if (RST || idone) begin
ecnt <= (`ELEMS_PER_UNIT << (phase * `WAY_LOG)); /// note
ecntz <= 0;
end else begin
if (ecnt!=0 && enq) ecnt <= ecnt - 4;
if (ecnt==4 && enq) ecntz <= 1; // old version has a bug here!
end
end
endmodule
/**************************************************************************************************/
module STREE(input wire CLK,
input wire RST_in,
input wire irst,
input wire frst,
input wire [`PHASE_W] phase_in,
input wire [`MERGW*`SORT_WAY-1:0] s_din, // sorting-tree input data
input wire [`SORT_WAY-1:0] enq, // enqueue
output wire [`SORT_WAY-1:0] full, // buffer is full ?
input wire deq, // dequeue
output wire [`MERGW-1:0] dot, // output data
output wire emp);
reg RST;
always @(posedge CLK) RST <= RST_in;
reg [`PHASE_W] phase;
always @(posedge CLK) phase <= phase_in;
///////////////// can be parameterized
wire [`MERGW-1:0] d00, d01, d02, d03;
assign {d00, d01, d02, d03} = s_din;
///////////////// can be parameterized
wire F01_enq, F01_deq, F01_emp, F01_full; wire [`MERGW-1:0] F01_din, F01_dot; wire [1:0] F01_cnt;
wire F02_enq, F02_deq, F02_emp, F02_full; wire [`MERGW-1:0] F02_din, F02_dot; wire [1:0] F02_cnt;
wire F03_enq, F03_deq, F03_emp, F03_full; wire [`MERGW-1:0] F03_din, F03_dot; wire [1:0] F03_cnt;
wire F04_enq, F04_deq, F04_emp, F04_full; wire [`MERGW-1:0] F04_din, F04_dot; wire [1:0] F04_cnt;
wire F05_enq, F05_deq, F05_emp, F05_full; wire [`MERGW-1:0] F05_din, F05_dot; wire [1:0] F05_cnt;
wire F06_enq, F06_deq, F06_emp, F06_full; wire [`MERGW-1:0] F06_din, F06_dot; wire [1:0] F06_cnt;
wire F07_enq, F07_deq, F07_emp, F07_full; wire [`MERGW-1:0] F07_din, F07_dot; wire [1:0] F07_cnt;
///////////////// can be parameterized
INBUF IN04(CLK, RST, full[0], F04_full, F04_enq, d00, F04_din, enq[0], phase, irst);
INBUF IN05(CLK, RST, full[1], F05_full, F05_enq, d01, F05_din, enq[1], phase, irst);
INBUF IN06(CLK, RST, full[2], F06_full, F06_enq, d02, F06_din, enq[2], phase, irst);
INBUF IN07(CLK, RST, full[3], F07_full, F07_enq, d03, F07_din, enq[3], phase, irst);
///////////////// can be parameterized
MRE2 #(1, `MERGW) F01(CLK, frst, F01_enq, F01_deq, F01_din, F01_dot, F01_emp, F01_full, F01_cnt);
MRE2 #(1, `MERGW) F02(CLK, frst, F02_enq, F02_deq, F02_din, F02_dot, F02_emp, F02_full, F02_cnt);
MRE2 #(1, `MERGW) F03(CLK, frst, F03_enq, F03_deq, F03_din, F03_dot, F03_emp, F03_full, F03_cnt);
MRE2 #(1, `MERGW) F04(CLK, frst, F04_enq, F04_deq, F04_din, F04_dot, F04_emp, F04_full, F04_cnt);
MRE2 #(1, `MERGW) F05(CLK, frst, F05_enq, F05_deq, F05_din, F05_dot, F05_emp, F05_full, F05_cnt);
MRE2 #(1, `MERGW) F06(CLK, frst, F06_enq, F06_deq, F06_din, F06_dot, F06_emp, F06_full, F06_cnt);
MRE2 #(1, `MERGW) F07(CLK, frst, F07_enq, F07_deq, F07_din, F07_dot, F07_emp, F07_full, F07_cnt);
///////////////// can be parameterized
SCELL #(`SORTW, `M_LOG) S01(CLK, frst, !F02_emp, !F03_emp, F02_deq, F03_deq, F02_dot, F03_dot, F01_full, F01_din, F01_enq);
SCELL #(`SORTW, `M_LOG) S02(CLK, frst, !F04_emp, !F05_emp, F04_deq, F05_deq, F04_dot, F05_dot, F02_full, F02_din, F02_enq);
SCELL #(`SORTW, `M_LOG) S03(CLK, frst, !F06_emp, !F07_emp, F06_deq, F07_deq, F06_dot, F07_dot, F03_full, F03_din, F03_enq);
assign F01_deq = deq;
assign dot = F01_dot;
assign emp = F01_emp;
endmodule
/***** compressor *****/
/**************************************************************************************************/
module COMPRESSOR(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] DIN,
input wire DIN_EN,
input wire P_Z,
input wire BUF_FULL,
output wire [`DRAMW-1:0] DOUT,
output wire DOUT_VALID);
function [`DRAMW-1:0] mux;
input [`DRAMW-1:0] a;
input [`DRAMW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
reg din_en;
always @(posedge CLK) din_en <= DIN_EN;
reg [31:0] block_cnt;
always @(posedge CLK) begin
if (RST) begin
block_cnt <= 0;
end else begin
case ({(block_cnt == ((`SORT_ELM>>4)>>(`P_LOG+`WAY_LOG))), din_en})
2'b10: block_cnt <= 0;
2'b01: block_cnt <= block_cnt + 1;
endcase
end
end
// Base+Delta Compressor /////////////////////////////////////////////////
wire [`SORTW-1:0] base = DIN[31 : 0];
wire [`SORTW-1:0] delta_a = DIN[63 : 32] - DIN[31 : 0];
wire [`SORTW-1:0] delta_b = DIN[95 : 64] - DIN[63 : 32];
wire [`SORTW-1:0] delta_c = DIN[127: 96] - DIN[95 : 64];
wire [`SORTW-1:0] delta_d = DIN[159:128] - DIN[127: 96];
wire [`SORTW-1:0] delta_e = DIN[191:160] - DIN[159:128];
wire [`SORTW-1:0] delta_f = DIN[223:192] - DIN[191:160];
wire [`SORTW-1:0] delta_g = DIN[255:224] - DIN[223:192];
wire [`SORTW-1:0] delta_h = DIN[287:256] - DIN[255:224];
wire [`SORTW-1:0] delta_i = DIN[319:288] - DIN[287:256];
wire [`SORTW-1:0] delta_j = DIN[351:320] - DIN[319:288];
wire [`SORTW-1:0] delta_k = DIN[383:352] - DIN[351:320];
wire [`SORTW-1:0] delta_l = DIN[415:384] - DIN[383:352];
wire [`SORTW-1:0] delta_m = DIN[447:416] - DIN[415:384];
wire [`SORTW-1:0] delta_n = DIN[479:448] - DIN[447:416];
wire [`SORTW-1:0] delta_o = DIN[511:480] - DIN[479:448];
reg c_cnt;
reg c_cflag;
always @(posedge CLK) c_cflag <= (delta_a<=13'h1fff) && (delta_b<=13'h1fff) && (delta_c<=13'h1fff) && (delta_d<=13'h1fff) &&
(delta_e<=13'h1fff) && (delta_f<=13'h1fff) && (delta_g<=13'h1fff) && (delta_h<=13'h1fff) &&
(delta_i<=13'h1fff) && (delta_j<=13'h1fff) && (delta_k<=13'h1fff) && (delta_l<=13'h1fff) &&
(delta_m<=13'h1fff) && (delta_n<=13'h1fff) && (delta_o<=13'h1fff) && !P_Z;
wire c_enable = (din_en && c_cflag);
wire c_cntrst;
reg [226:0] c_data;
always @(posedge CLK) c_data <= {delta_o[12:0], delta_n[12:0], delta_m[12:0], delta_l[12:0], delta_k[12:0], delta_j[12:0], delta_i[12:0],
delta_h[12:0], delta_g[12:0], delta_f[12:0], delta_e[12:0], delta_d[12:0], delta_c[12:0], delta_b[12:0],
delta_a[12:0], base};
always @(posedge CLK) begin
if (RST) begin
c_cnt <= 0;
end else begin
case ({c_enable, c_cntrst})
2'b10: c_cnt <= ~c_cnt;
2'b01: c_cnt <= 0;
endcase
end
end
// Data Packer ///////////////////////////////////////////////////////////
reg [226:0] data_buf;
always @(posedge CLK) if (c_enable) data_buf <= c_data;
reg p_valid; // packed data is valid
reg [`DRAMW-1:0] packed_data;
always @(posedge CLK) p_valid <= c_enable && c_cnt;
always @(posedge CLK) packed_data <= {{32'b0, 1'b1}, 25'b0, c_data, data_buf};
// temp FIFO /////////////////////////////////////////////////////////////
reg deq_req;
wire tmp_emp;
wire tmp_rst = RST || p_valid;
wire tmp_enq = DIN_EN;
wire tmp_deq = !BUF_FULL && deq_req && !tmp_emp;
wire [`DRAMW-1:0] tmp_dout;
wire tmp_full;
MRE2 #(1, `DRAMW) tmp(.CLK(CLK), .RST(tmp_rst), .enq(tmp_enq), .deq(tmp_deq),
.din(DIN), .dot(tmp_dout), .emp(tmp_emp), .full(tmp_full));
assign c_cntrst = tmp_deq;
always @(posedge CLK) begin
if (RST) begin
deq_req <= 0;
end else begin
if ((din_en && !c_cflag) ||
(din_en && (block_cnt==((`SORT_ELM>>4)>>(`P_LOG+`WAY_LOG))-1) && !c_cnt)) deq_req <= 1;
else if (tmp_emp) deq_req <= 0;
end
end
// Output ////////////////////////////////////////////////////////////////
assign DOUT = mux(tmp_dout, packed_data, p_valid);
assign DOUT_VALID = p_valid || tmp_deq;
endmodule
/***** decompressor *****/
/**************************************************************************************************/
module DECOMPRESSOR #(parameter SIZE = 7,
parameter BLOCKS = 8)
(input wire CLK,
input wire RST,
input wire [`SRTP_WAY+`DRAMW-1:0] DIN,
input wire DIN_EN,
output reg [`DRAMW-1:0] DOUT,
output reg [`SRTP_WAY:0] COUT,
output reg DATA_REQ);
function [227-1:0] mux227;
input [227-1:0] a;
input [227-1:0] b;
input sel;
begin
case (sel)
1'b0: mux227 = a;
1'b1: mux227 = b;
endcase
end
endfunction
function [512-1:0] mux512;
input [512-1:0] a;
input [512-1:0] b;
input sel;
begin
case (sel)
1'b0: mux512 = a;
1'b1: mux512 = b;
endcase
end
endfunction
// FIFO (Block RAM) //////////////////////////////////////////////////////
wire dmft_full;
wire dmf_emp;
wire dmf_enq = DIN_EN;
wire dmf_deq = !dmf_emp && !dmft_full;
wire [`SRTP_WAY+`DRAMW-1:0] dmf_din = DIN;
wire dmf_full;
wire [`SRTP_WAY+`DRAMW-1:0] dmf_dout;
wire [SIZE:0] dmf_cnt;
BFIFO #(SIZE, `SRTP_WAY+`DRAMW) dmf(CLK, RST, dmf_enq, dmf_deq, dmf_din, dmf_dout, dmf_emp, dmf_full, dmf_cnt);
reg dmf_dataen;
always @(posedge CLK) dmf_dataen <= dmf_deq;
always @(posedge CLK) DATA_REQ <= (dmf_cnt <= (1<<SIZE)-BLOCKS);
// FIFO (two entries) ///////////////////////////////////////////////////
wire dmft_enq = dmf_dataen;
wire [`SRTP_WAY+`DRAMW-1:0] dmft_din = dmf_dout;
wire [`SRTP_WAY+`DRAMW-1:0] dmft_dout;
wire dmft_emp;
wire c_valid = (dmft_dout[`DRAMW-1:`DRAMW-33]=={32'b0,1'b1}); // check whether the data is compressed or not
reg c_sel;
wire dmft_deq = c_sel || (!c_valid && !dmft_emp);
MRE2 #(1, `SRTP_WAY+`DRAMW) dmft(.CLK(CLK), .RST(RST), .enq(dmft_enq), .deq(dmft_deq),
.din(dmft_din), .dot(dmft_dout), .emp(dmft_emp), .full(dmft_full));
// Base+Delta Decompressor ///////////////////////////////////////////////
always @(posedge CLK) begin
if (RST) begin
c_sel <= 0;
end else begin
if (c_valid && !dmft_emp) c_sel <= ~c_sel;
end
end
wire [226:0] c_data = mux227(dmft_dout[226:0], dmft_dout[453:227], c_sel);
// Stage A
//////////////////////////////////////////////////////////////////////////////
wire [`SORTW-1:0] a00 = c_data[31 : 0];
wire [`SORTW-1:0] a01 = {19'b0, c_data[44 : 32]};
wire [`SORTW-1:0] a02 = {19'b0, c_data[57 : 45]};
wire [`SORTW-1:0] a03 = {19'b0, c_data[70 : 58]};
wire [`SORTW-1:0] a04 = {19'b0, c_data[83 : 71]};
wire [`SORTW-1:0] a05 = {19'b0, c_data[96 : 84]};
wire [`SORTW-1:0] a06 = {19'b0, c_data[109: 97]};
wire [`SORTW-1:0] a07 = {19'b0, c_data[122:110]};
wire [`SORTW-1:0] a08 = {19'b0, c_data[135:123]};
wire [`SORTW-1:0] a09 = {19'b0, c_data[148:136]};
wire [`SORTW-1:0] a10 = {19'b0, c_data[161:149]};
wire [`SORTW-1:0] a11 = {19'b0, c_data[174:162]};
wire [`SORTW-1:0] a12 = {19'b0, c_data[187:175]};
wire [`SORTW-1:0] a13 = {19'b0, c_data[200:188]};
wire [`SORTW-1:0] a14 = {19'b0, c_data[213:201]};
wire [`SORTW-1:0] a15 = {19'b0, c_data[226:214]};
reg [511:0] pdA; // pipeline regester A for data
always @(posedge CLK) pdA <= {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,(a03+a02+a01+a00),(a02+a01+a00),(a01+a00),a00};
reg [`DRAMW-1:0] dmft_dout_A;
always @(posedge CLK) dmft_dout_A <= dmft_dout[`DRAMW-1:0];
reg [(`SRTP_WAY+1+1)-1:0] pcA; // pipeline regester A for control
always @(posedge CLK) pcA <= {dmft_dout[`SRTP_WAY+`DRAMW-1:`DRAMW], (!dmft_emp), c_valid};
// Stage B
//////////////////////////////////////////////////////////////////////////////
wire [`SORTW-1:0] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
reg [511:0] pdB; // pipeline regester B for data
always @(posedge CLK) pdB <= {b15,b14,b13,b12,b11,b10,b09,b08,b07,(b06+b05+b04+b03),(b05+b04+b03),(b04+b03),b03,b02,b01,b00};
reg [`DRAMW-1:0] dmft_dout_B;
always @(posedge CLK) dmft_dout_B <= dmft_dout_A;
reg [(`SRTP_WAY+1+1)-1:0] pcB; // pipeline regester B for control
always @(posedge CLK) pcB <= pcA;
// Stage C
//////////////////////////////////////////////////////////////////////////////
wire [`SORTW-1:0] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
reg [511:0] pdC; // pipeline regester C for data
always @(posedge CLK) pdC <= {c15,c14,c13,c12,c11,c10,(c09+c08+c07+c06),(c08+c07+c06),(c07+c06),c06,c05,c04,c03,c02,c01,c00};
reg [`DRAMW-1:0] dmft_dout_C;
always @(posedge CLK) dmft_dout_C <= dmft_dout_B;
reg [(`SRTP_WAY+1+1)-1:0] pcC; // pipeline regester C for control
always @(posedge CLK) pcC <= pcB;
// Stage D
//////////////////////////////////////////////////////////////////////////////
wire [`SORTW-1:0] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
reg [511:0] pdD; // pipeline regester D for data
always @(posedge CLK) pdD <= {d15,d14,d13,(d12+d11+d10+d09),(d11+d10+d09),(d10+d09),d09,d08,d07,d06,d05,d04,d03,d02,d01,d00};
reg [`DRAMW-1:0] dmft_dout_D;
always @(posedge CLK) dmft_dout_D <= dmft_dout_C;
reg [(`SRTP_WAY+1+1)-1:0] pcD; // pipeline regester D for control
always @(posedge CLK) pcD <= pcC;
// Stage E
//////////////////////////////////////////////////////////////////////////////
wire [`SORTW-1:0] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
reg [511:0] pdE; // pipeline regester E for data
always @(posedge CLK) pdE <= {(e15+e14+e13+e12),(e14+e13+e12),(e13+e12),e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00};
reg [`DRAMW-1:0] dmft_dout_E;
always @(posedge CLK) dmft_dout_E <= dmft_dout_D;
reg [(`SRTP_WAY+1+1)-1:0] pcE; // pipeline regester E for control
always @(posedge CLK) pcE <= pcD;
// Decompression Result
//////////////////////////////////////////////////////////////////////////////
wire [`DRAMW-1:0] dc_data = pdE;
wire [`DRAMW-1:0] dmft_dot = dmft_dout_E;
wire c_vld = pcE[0];
wire dataen = pcE[1];
// Output ////////////////////////////////////////////////////////////////
always @(posedge CLK) if (dataen) DOUT <= mux512(dmft_dot, dc_data, c_vld);
always @(posedge CLK) COUT <= pcE[(`SRTP_WAY+1+1)-1:1];
endmodule
/***** Output Module *****/
/**************************************************************************************************/
module OTMOD(input wire CLK,
input wire RST,
input wire d_busy,
input wire [31:0] w_block,
input wire p_z, // phase zero
input wire F01_deq,
input wire [`MERGW-1:0] F01_dot,
input wire OB_deq,
output wire [`DRAMW-1:0] OB_dot,
output wire buf_t_ful,
output reg OB_req);
reg [1:0] buf_t_cnt; // counter for temporary register
reg buf_t_en;
reg [`DRAMW-1:0] buf_t;
wire buf_t_emp;
wire [`DRAMW-1:0] c_din;
wire c_dinen;
wire [`DRAMW-1:0] c_dout;
wire c_douten;
wire [`DRAMW-1:0] OB_din = c_dout;
wire OB_enq = c_douten;
wire OB_full;
wire [`OB_SIZE:0] OB_cnt;
// 512-bit shift register ////////////////////////////////////////////////
always @(posedge CLK) begin
if (F01_deq) buf_t <= {F01_dot, buf_t[`DRAMW-1:`MERGW]};
end
always @(posedge CLK) begin
if (RST) begin
buf_t_cnt <= 0;
end else begin
if (F01_deq) buf_t_cnt <= buf_t_cnt + 1;
end
end
always @(posedge CLK) buf_t_en <= (F01_deq && buf_t_cnt == 3);
MRE2 #(1, `DRAMW) tmp(.CLK(CLK), .RST(RST), .enq(buf_t_en), .deq(c_dinen),
.din(buf_t), .dot(c_din), .emp(buf_t_emp), .full(buf_t_ful));
// Compressor ////////////////////////////////////////////////////////////
assign c_dinen = (~|{buf_t_emp,OB_full});
COMPRESSOR compressor(CLK, RST, c_din, c_dinen, p_z, OB_full, c_dout, c_douten);
// Output Buffer /////////////////////////////////////////////////////////
BFIFO #(`OB_SIZE, `DRAMW) OB(.CLK(CLK), .RST(RST), .enq(OB_enq), .deq(OB_deq),
.din(OB_din), .dot(OB_dot), .full(OB_full), .cnt(OB_cnt));
always @(posedge CLK) OB_req <= ((OB_cnt>=w_block) && !d_busy);
endmodule
/***** Sorting Network *****/
/**************************************************************************************************/
module SORTINGNETWORK(input wire CLK,
input wire RST_IN,
input wire DATAEN_IN,
input wire [511:0] DIN_T,
output reg [511:0] DOUT,
output reg DATAEN_OUT);
reg RST;
reg [511:0] DIN;
reg DATAEN;
always @(posedge CLK) RST <= RST_IN;
always @(posedge CLK) DIN <= DIN_T;
always @(posedge CLK) DATAEN <= (RST) ? 0 : DATAEN_IN;
// Stage A
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00; // output
wire [`WW] a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00; // input
assign {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00} = DIN;
COMPARATOR comp00(a00, a01, A00, A01);
COMPARATOR comp01(a02, a03, A02, A03);
COMPARATOR comp02(a04, a05, A04, A05);
COMPARATOR comp03(a06, a07, A06, A07);
COMPARATOR comp04(a08, a09, A08, A09);
COMPARATOR comp05(a10, a11, A10, A11);
COMPARATOR comp06(a12, a13, A12, A13);
COMPARATOR comp07(a14, a15, A14, A15);
reg [511:0] pdA; // pipeline regester A for data
reg pcA; // pipeline regester A for control
always @(posedge CLK) pdA <= {A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00};
always @(posedge CLK) pcA <= (RST) ? 0 : DATAEN;
// Stage B
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00; // output
wire [`WW] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
COMPARATOR comp10(b00, b02, B00, B02);
COMPARATOR comp11(b04, b06, B04, B06);
COMPARATOR comp12(b08, b10, B08, B10);
COMPARATOR comp13(b12, b14, B12, B14);
COMPARATOR comp14(b01, b03, B01, B03);
COMPARATOR comp15(b05, b07, B05, B07);
COMPARATOR comp16(b09, b11, B09, B11);
COMPARATOR comp17(b13, b15, B13, B15);
reg [511:0] pdB; // pipeline regester B for data
reg pcB; // pipeline regester B for control
always @(posedge CLK) pdB <= {B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00};
always @(posedge CLK) pcB <= (RST) ? 0 : pcA;
// Stage C
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00; // output
wire [`WW] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
assign {C00,C03,C04,C07,C08,C11,C12,C15} = {c00,c03,c04,c07,c08,c11,c12,c15};
COMPARATOR comp20(c01, c02, C01, C02);
COMPARATOR comp21(c05, c06, C05, C06);
COMPARATOR comp22(c09, c10, C09, C10);
COMPARATOR comp23(c13, c14, C13, C14);
reg [511:0] pdC; // pipeline regester C for data
reg pcC; // pipeline regester C for control
always @(posedge CLK) pdC <= {C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00};
always @(posedge CLK) pcC <= (RST) ? 0 : pcB;
// Stage D
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00; // output
wire [`WW] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
COMPARATOR comp30(d00, d04, D00, D04);
COMPARATOR comp31(d08, d12, D08, D12);
COMPARATOR comp32(d01, d05, D01, D05);
COMPARATOR comp33(d09, d13, D09, D13);
COMPARATOR comp34(d02, d06, D02, D06);
COMPARATOR comp35(d10, d14, D10, D14);
COMPARATOR comp36(d03, d07, D03, D07);
COMPARATOR comp37(d11, d15, D11, D15);
reg [511:0] pdD; // pipeline regester D for data
reg pcD; // pipeline regester D for control
always @(posedge CLK) pdD <= {D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00};
always @(posedge CLK) pcD <= (RST) ? 0 : pcC;
// Stage E
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00; // output
wire [`WW] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
assign {E00,E01,E06,E07,E08,E09,E14,E15} = {e00,e01,e06,e07,e08,e09,e14,e15};
COMPARATOR comp40(e02, e04, E02, E04);
COMPARATOR comp41(e10, e12, E10, E12);
COMPARATOR comp42(e03, e05, E03, E05);
COMPARATOR comp43(e11, e13, E11, E13);
reg [511:0] pdE; // pipeline regester E for data
reg pcE; // pipeline regester E for control
always @(posedge CLK) pdE <= {E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00};
always @(posedge CLK) pcE <= (RST) ? 0 : pcD;
// Stage F
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00; // output
wire [`WW] f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00; // input
assign {f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00} = pdE;
assign {F00,F07,F08,F15} = {f00,f07,f08,f15};
COMPARATOR comp50(f01, f02, F01, F02);
COMPARATOR comp51(f03, f04, F03, F04);
COMPARATOR comp52(f05, f06, F05, F06);
COMPARATOR comp53(f09, f10, F09, F10);
COMPARATOR comp54(f11, f12, F11, F12);
COMPARATOR comp55(f13, f14, F13, F14);
reg [511:0] pdF; // pipeline regester F for data
reg pcF; // pipeline regester F for control
always @(posedge CLK) pdF <= {F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00};
always @(posedge CLK) pcF <= (RST) ? 0 : pcE;
// Stage G
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00; // output
wire [`WW] g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00; // input
assign {g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00} = pdF;
COMPARATOR comp60(g00, g08, G00, G08);
COMPARATOR comp61(g01, g09, G01, G09);
COMPARATOR comp62(g02, g10, G02, G10);
COMPARATOR comp63(g03, g11, G03, G11);
COMPARATOR comp64(g04, g12, G04, G12);
COMPARATOR comp65(g05, g13, G05, G13);
COMPARATOR comp66(g06, g14, G06, G14);
COMPARATOR comp67(g07, g15, G07, G15);
reg [511:0] pdG; // pipeline regester G for data
reg pcG; // pipeline regester G for control
always @(posedge CLK) pdG <= {G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00};
always @(posedge CLK) pcG <= (RST) ? 0 : pcF;
// Stage H
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00; // output
wire [`WW] h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00; // input
assign {h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00} = pdG;
assign {H00,H01,H02,H03,H12,H13,H14,H15} = {h00,h01,h02,h03,h12,h13,h14,h15};
COMPARATOR comp70(h04, h08, H04, H08);
COMPARATOR comp71(h05, h09, H05, H09);
COMPARATOR comp72(h06, h10, H06, H10);
COMPARATOR comp73(h07, h11, H07, H11);
reg [511:0] pdH; // pipeline regester H for data
reg pcH; // pipeline regester H for control
always @(posedge CLK) pdH <= {H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00};
always @(posedge CLK) pcH <= (RST) ? 0 : pcG;
// Stage I
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00; // output
wire [`WW] i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00; // input
assign {i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00} = pdH;
assign {I00,I01,I14,I15} = {i00,i01,i14,i15};
COMPARATOR comp80(i02, i04, I02, I04);
COMPARATOR comp81(i06, i08, I06, I08);
COMPARATOR comp82(i10, i12, I10, I12);
COMPARATOR comp83(i03, i05, I03, I05);
COMPARATOR comp84(i07, i09, I07, I09);
COMPARATOR comp85(i11, i13, I11, I13);
reg [511:0] pdI; // pipeline regester I for data
reg pcI; // pipeline regester I for control
always @(posedge CLK) pdI <= {I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00};
always @(posedge CLK) pcI <= (RST) ? 0 : pcH;
// Stage J
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00; // output
wire [`WW] j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00; // input
assign {j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00} = pdI;
assign {J00,J15} = {j00,j15};
COMPARATOR comp90(j01, j02, J01, J02);
COMPARATOR comp91(j03, j04, J03, J04);
COMPARATOR comp92(j05, j06, J05, J06);
COMPARATOR comp93(j07, j08, J07, J08);
COMPARATOR comp94(j09, j10, J09, J10);
COMPARATOR comp95(j11, j12, J11, J12);
COMPARATOR comp96(j13, j14, J13, J14);
always @(posedge CLK) DOUT <= {J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00};
always @(posedge CLK) DATAEN_OUT <= (RST) ? 0 : pcI;
endmodule
/**************************************************************************************************/
/***** An SRL-based FIFO *****/
/******************************************************************************/
module SRL_FIFO #(parameter FIFO_SIZE = 4, // size in log scale, 4 for 16 entry
parameter FIFO_WIDTH = 64) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) begin
cnt <= 0;
head <= {(FIFO_SIZE){1'b1}};
end else begin
case ({enq, deq})
2'b01: begin cnt <= cnt - 1; head <= head - 1; end
2'b10: begin cnt <= cnt + 1; head <= head + 1; end
endcase
end
end
integer i;
always @(posedge CLK) begin
if (enq) begin
mem[0] <= din;
for (i=1; i<(1<<FIFO_SIZE); i=i+1) mem[i] <= mem[i-1];
end
end
endmodule
/***** request counter manager *****/
/**************************************************************************************************/
module REQCNTMG(input wire CLK,
input wire RST,
input wire DRIVE,
input wire [`SORT_WAY-1:0] req,
input wire [`SORT_WAY-1:0] im_enq,
input wire [`SORT_WAY-1:0] im_emp,
output reg reqcnt_a,
output reg reqcnt_b,
output reg reqcnt_c,
output reg reqcnt_d);
reg reqcnt_rsta;
reg reqcnt_rstb;
reg reqcnt_rstc;
reg reqcnt_rstd;
// request counter manager
always @(posedge CLK) begin
if (RST) begin
{reqcnt_a, reqcnt_b, reqcnt_c, reqcnt_d} <= 0;
{reqcnt_rsta, reqcnt_rstb, reqcnt_rstc, reqcnt_rstd} <= 0;
end else begin
if (DRIVE) begin
case (req)
4'h1: reqcnt_a <= 1;
4'h2: reqcnt_b <= 1;
4'h4: reqcnt_c <= 1;
4'h8: reqcnt_d <= 1;
endcase
end
if (|im_enq) begin
case (im_enq)
4'h1: begin
reqcnt_rsta <= 1;
{reqcnt_rstb, reqcnt_rstc, reqcnt_rstd} <= 0;
end
4'h2: begin
reqcnt_rstb <= 1;
{reqcnt_rsta, reqcnt_rstc, reqcnt_rstd} <= 0;
end
4'h4: begin
reqcnt_rstc <= 1;
{reqcnt_rsta, reqcnt_rstb, reqcnt_rstd} <= 0;
end
4'h8: begin
reqcnt_rstd <= 1;
{reqcnt_rsta, reqcnt_rstb, reqcnt_rstc} <= 0;
end
endcase
end else begin
if (reqcnt_rsta && im_emp[0]) reqcnt_rsta <= 0;
if (reqcnt_rstb && im_emp[1]) reqcnt_rstb <= 0;
if (reqcnt_rstc && im_emp[2]) reqcnt_rstc <= 0;
if (reqcnt_rstd && im_emp[3]) reqcnt_rstd <= 0;
end
if (reqcnt_rsta && ((|im_enq[`SORT_WAY-1:1]) || im_emp[0])) reqcnt_a <= 0;
if (reqcnt_rstb && ((|{im_enq[`SORT_WAY-1:2], im_enq[0]}) || im_emp[1])) reqcnt_b <= 0;
if (reqcnt_rstc && ((|{im_enq[`SORT_WAY-1:3], im_enq[1:0]}) || im_emp[2])) reqcnt_c <= 0;
if (reqcnt_rstd && ((|im_enq[`SORT_WAY-2:0]) || im_emp[3])) reqcnt_d <= 0;
end
end
endmodule
/***** write manager *****/
/**************************************************************************************************/
module WRITEMG #(parameter SORTELM_WAY = (`SORT_ELM>>`WAY_LOG))
(input wire CLK,
input wire RST,
input wire pchange,
input wire p_last,
input wire mgdrive,
input wire [31:0] elem,
input wire [31:0] elem_way,
input wire [31:0] elem_plast,
input wire [31:0] w_addr,
output reg [31:0] w_block,
output reg [31:0] r_endadr_a,
output reg [31:0] r_endadr_b,
output reg [31:0] r_endadr_c,
output reg [31:0] r_endadr_d);
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
reg [31:0] adr_a, adr_b, adr_c, adr_d;
reg reduce_flag;
always @(posedge CLK) begin
if (RST || pchange) begin
if (RST) {adr_a, adr_b, adr_c, adr_d} <= 0;
w_block <= `DRAM_WBLOCKS;
reduce_flag <= 0;
r_endadr_a <= adr_a;
r_endadr_b <= adr_b;
r_endadr_c <= adr_c;
r_endadr_d <= adr_d;
end else begin
case (p_last)
1'b0: begin
if (elem_way >= SORTELM_WAY-(`DRAM_WBLOCKS<<7)) reduce_flag <= 1;
if (mgdrive && reduce_flag) w_block <= mux32((w_block>>1), 1, (w_block==1));
case (elem)
SORTELM_WAY*1: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_a <= w_addr; end
end
SORTELM_WAY*2: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_b <= w_addr; end
end
SORTELM_WAY*3: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_c <= w_addr; end
end
SORTELM_WAY*4: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_d <= w_addr; end
end
endcase
end
1'b1: begin
if (elem_plast >= (SORTELM_WAY*2)-(`DRAM_WBLOCKS<<7)) reduce_flag <= 1;
if (mgdrive && reduce_flag) w_block <= mux32((w_block>>1), 1, (w_block==1));
case (elem)
SORTELM_WAY*2: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_b <= w_addr; end
end
SORTELM_WAY*4: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_d <= w_addr; end
end
endcase
end
endcase
end
end
endmodule
/***** read manager *****/
/**************************************************************************************************/
module READMG(input wire CLK,
input wire RST,
input wire mgdrive,
input wire [`SORT_WAY-1:0] req,
input wire phase_lsb,
input wire [31:0] radr_a,
input wire [31:0] radr_b,
input wire [31:0] radr_c,
input wire [31:0] radr_d,
input wire [31:0] r_endadr_a,
input wire [31:0] r_endadr_b,
input wire [31:0] r_endadr_c,
input wire [31:0] r_endadr_d,
output reg [31:0] r_block_a,
output reg [31:0] r_block_b,
output reg [31:0] r_block_c,
output reg [31:0] r_block_d,
output reg readend_a,
output reg readend_b,
output reg readend_c,
output reg readend_d);
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
wire [31:0] way0_radr = mux32(radr_a, (radr_a + (`SORT_ELM>>1)), phase_lsb);
wire [31:0] way1_radr = mux32(radr_b, (radr_b + (`SORT_ELM>>1)), phase_lsb);
wire [31:0] way2_radr = mux32(radr_c, (radr_c + (`SORT_ELM>>1)), phase_lsb);
wire [31:0] way3_radr = mux32(radr_d, (radr_d + (`SORT_ELM>>1)), phase_lsb);
reg reduce_flag_a, reduce_flag_b, reduce_flag_c, reduce_flag_d;
always @(posedge CLK) begin
if (RST) begin
r_block_a <= `DRAM_RBLOCKS;
r_block_b <= `DRAM_RBLOCKS;
r_block_c <= `DRAM_RBLOCKS;
r_block_d <= `DRAM_RBLOCKS;
{readend_a,readend_b,readend_c,readend_d} <= 0;
{reduce_flag_a,reduce_flag_b,reduce_flag_c,reduce_flag_d} <= 0;
end else begin
readend_a <= (r_endadr_a == way0_radr);
readend_b <= (r_endadr_b == way1_radr);
readend_c <= (r_endadr_c == way2_radr);
readend_d <= (r_endadr_d == way3_radr);
if (r_endadr_a-((`D_RS)<<2) <= way0_radr) reduce_flag_a <= 1;
if (r_endadr_b-((`D_RS)<<2) <= way1_radr) reduce_flag_b <= 1;
if (r_endadr_c-((`D_RS)<<2) <= way2_radr) reduce_flag_c <= 1;
if (r_endadr_d-((`D_RS)<<2) <= way3_radr) reduce_flag_d <= 1;
if (mgdrive) begin
case (req)
4'h1: if (reduce_flag_a) r_block_a <= mux32((r_block_a>>1), 1, (r_block_a==1));
4'h2: if (reduce_flag_b) r_block_b <= mux32((r_block_b>>1), 1, (r_block_b==1));
4'h4: if (reduce_flag_c) r_block_c <= mux32((r_block_c>>1), 1, (r_block_c==1));
4'h8: if (reduce_flag_d) r_block_d <= mux32((r_block_d>>1), 1, (r_block_d==1));
endcase
end
end
end
endmodule
/***** Core User Logic *****/
/**************************************************************************************************/
module CORE(input wire CLK, // clock
input wire RST_IN, // reset
input wire d_busy, // DRAM busy
output wire [`DRAMW-1:0] d_din, // DRAM data in
input wire d_w, // DRAM write flag
input wire [`DRAMW-1:0] d_dout, // DRAM data out
input wire d_douten, // DRAM data out enable
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
input wire [`DRAMW-1:0] rx_data,
input wire rx_data_valid,
output wire rx_wait,
input wire chnl_tx_data_ren,
input wire chnl_tx_data_valid,
output wire [`MERGW-1:0] rslt,
output wire rslt_ready);
function [1-1:0] mux1;
input [1-1:0] a;
input [1-1:0] b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`SORT_WAY-1:0] mux_sortway;
input [`SORT_WAY-1:0] a;
input [`SORT_WAY-1:0] b;
input sel;
begin
case (sel)
1'b0: mux_sortway = a;
1'b1: mux_sortway = b;
endcase
end
endfunction
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [512-1:0] mux512;
input [512-1:0] a;
input [512-1:0] b;
input sel;
begin
case (sel)
1'b0: mux512 = a;
1'b1: mux512 = b;
endcase
end
endfunction
/**********************************************************************************************/
wire [`DRAMW-1:0] OB_dot_a, OB_dot_b;
wire OB_req_a, OB_req_b;
wire OB_full_a, OB_full_b;
reg OB_granted_a, OB_granted_b;
wire OB_deq_a = d_w && OB_granted_a;
wire OB_deq_b = d_w && OB_granted_b;
reg OB_doten_a, OB_doten_b;
assign d_din = mux512(OB_dot_b, OB_dot_a, OB_granted_a);
reg [`DRAMW-1:0] dout_ta;
reg [`DRAMW-1:0] dout_tb;
reg [`DRAMW-1:0] dout_tc;
reg [`DRAMW-1:0] dout_td;
reg [`DRAMW-1:0] dout_te;
reg [`DRAMW-1:0] dout_tf;
reg doen_ta;
reg doen_tb; //
reg doen_tc; //
reg doen_td; //
reg doen_te; //
reg doen_tf; //
reg [`SORT_WAY-1:0] req; // use n-bit for n-way sorting, data read request from ways
reg [`SORT_WAY-1:0] req_a, req_b;
reg [`SORT_WAY-1:0] req_ta;
reg [`SORT_WAY-1:0] req_tb;
reg [`SORT_WAY-1:0] req_taa; //
reg [`SORT_WAY-1:0] req_tab; //
reg [`SORT_WAY-1:0] req_tba; //
reg [`SORT_WAY-1:0] req_tbb; //
reg [`SRTP_WAY-1:0] req_pzero;
wire [`SORT_WAY-1:0] im_req_a;
wire [`SORT_WAY-1:0] im_req_b;
wire [`SRTP_WAY-1:0] rxw;
reg [31:0] elem_a, elem_b; // sorted elements in a phase
reg [31:0] elem_way_a, elem_way_b; // sorted elements in a phase
reg [31:0] elem_plast_a, elem_plast_b; // sorted elements in a phase
reg elem_en_a, elem_en_b;
reg [`PHASE_W] phase_a, phase_b; //
reg pchange_a, pchange_b; // phase_change to reset some registers
reg iter_done_a, iter_done_b; //
reg [31:0] ecnt_a, ecnt_b; // sorted elements in an iteration
reg irst_a, irst_b; // INBUF reset
reg frst_a, frst_b; // sort-tree FIFO reset
reg plast_a, plast_b;
reg phase_zero;
reg last_phase;
reg RSTa, RSTb;
always @(posedge CLK) RSTa <= RST_IN;
always @(posedge CLK) RSTb <= RST_IN;
/**********************************************************************************************/
///////////////// can be parameterized
wire [`MERGW-1:0] d00_a, d01_a, d02_a, d03_a;
wire [1:0] ib00_req_a, ib01_req_a, ib02_req_a, ib03_req_a;
wire [`MERGW-1:0] d00_b, d01_b, d02_b, d03_b;
wire [1:0] ib00_req_b, ib01_req_b, ib02_req_b, ib03_req_b;
(* mark_debug = "true" *) wire rsltbuf_enq;
(* mark_debug = "true" *) wire rsltbuf_deq;
wire rsltbuf_emp;
wire rsltbuf_ful;
(* mark_debug = "true" *) wire [4:0] rsltbuf_cnt;
wire F01_emp_a, F01_emp_b;
wire F01_deq_a = mux1((~|{F01_emp_a,OB_full_a}), (~|{F01_emp_a,rsltbuf_ful}), last_phase);
wire F01_deq_b = (~|{F01_emp_b,OB_full_b});
wire [`MERGW-1:0] F01_dot_a, F01_dot_b;
///////////////// can be parameterized
wire [`MERGW*`SORT_WAY-1:0] s_din_a = {d00_a, d01_a, d02_a, d03_a};
wire [`MERGW*`SORT_WAY-1:0] s_din_b = {d00_b, d01_b, d02_b, d03_b};
wire [`SORT_WAY-1:0] enq_a, enq_b;
wire [`SORT_WAY-1:0] s_ful_a, s_ful_b;
wire [`SRTP_WAY+`DRAMW-1:0] dc_din = {req_tb,req_ta,d_dout};
wire dc_dinen = d_douten;
wire [`DRAMW-1:0] dc_dout; // for data
wire [`SRTP_WAY:0] dc_cout; // for control
wire dc_req;
DECOMPRESSOR #(`IB_SIZE, `DRAM_RBLOCKS)
decompressor(CLK, RSTa, dc_din, dc_dinen, dc_dout, dc_cout, dc_req);
wire [`DRAMW-1:0] stnet_dout;
wire stnet_douten;
SORTINGNETWORK sortingnetwork(CLK, RSTa, rx_data_valid, rx_data, stnet_dout, stnet_douten);
always @(posedge CLK) begin
if (RSTa) req_pzero <= 1;
else if (doen_tc) req_pzero <= {req_pzero[`SRTP_WAY-2:0],req_pzero[`SRTP_WAY-1]};
end
assign im_req_a = mux_sortway(req_tab, req_pzero[`SORT_WAY-1:0], phase_zero);
assign im_req_b = mux_sortway(req_tbb, req_pzero[`SRTP_WAY-1:`SORT_WAY], phase_zero);
///////////////// can be parameterized
wire im00_enq_a = doen_tc & im_req_a[0];
wire im01_enq_a = doen_td & im_req_a[1];
wire im02_enq_a = doen_te & im_req_a[2];
wire im03_enq_a = doen_tf & im_req_a[3];
wire im00_enq_b = doen_tc & im_req_b[0];
wire im01_enq_b = doen_td & im_req_b[1];
wire im02_enq_b = doen_te & im_req_b[2];
wire im03_enq_b = doen_tf & im_req_b[3];
INMOD2 im00_a(CLK, RSTa, dout_tc, im00_enq_a, s_ful_a[0], rxw[0], d00_a, enq_a[0], ib00_req_a);
INMOD2 im01_a(CLK, RSTa, dout_td, im01_enq_a, s_ful_a[1], rxw[1], d01_a, enq_a[1], ib01_req_a);
INMOD2 im02_a(CLK, RSTa, dout_te, im02_enq_a, s_ful_a[2], rxw[2], d02_a, enq_a[2], ib02_req_a);
INMOD2 im03_a(CLK, RSTa, dout_tf, im03_enq_a, s_ful_a[3], rxw[3], d03_a, enq_a[3], ib03_req_a);
INMOD2 im00_b(CLK, RSTb, dout_tc, im00_enq_b, s_ful_b[0], rxw[4], d00_b, enq_b[0], ib00_req_b);
INMOD2 im01_b(CLK, RSTb, dout_td, im01_enq_b, s_ful_b[1], rxw[5], d01_b, enq_b[1], ib01_req_b);
INMOD2 im02_b(CLK, RSTb, dout_te, im02_enq_b, s_ful_b[2], rxw[6], d02_b, enq_b[2], ib02_req_b);
INMOD2 im03_b(CLK, RSTb, dout_tf, im03_enq_b, s_ful_b[3], rxw[7], d03_b, enq_b[3], ib03_req_b);
assign rx_wait = |rxw;
STREE stree_a(CLK, RSTa, irst_a, frst_a, phase_a, s_din_a, enq_a, s_ful_a, F01_deq_a, F01_dot_a, F01_emp_a);
STREE stree_b(CLK, RSTb, irst_b, frst_b, phase_b, s_din_b, enq_b, s_ful_b, F01_deq_b, F01_dot_b, F01_emp_b);
// ----- for dram READ/WRITE controller -----
reg [31:0] w_addr; //
reg [31:0] w_addr_pzero; //
reg [31:0] w_addr_a, w_addr_b;
reg [3:0] state; // state
///////////////// can be parameterized
reg [31:0] radr_a, radr_b, radr_c, radr_d;
reg [31:0] radr_a_a, radr_b_a, radr_c_a, radr_d_a;
reg [31:0] radr_a_b, radr_b_b, radr_c_b, radr_d_b;
reg [27:0] cnt_a, cnt_b, cnt_c, cnt_d;
reg [27:0] cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a;
reg [27:0] cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b;
reg c_a, c_b, c_c, c_d; // counter is full ?
reg c_a_a, c_b_a, c_c_a, c_d_a;
reg c_a_b, c_b_b, c_c_b, c_d_b;
// ----- request counter manager -----
// input
wire mgdrive = (state==3 && d_req!=0);
wire mgdrive_a = (state==6 && d_req!=0 && (|req_ta));
wire mgdrive_b = (state==6 && d_req!=0 && (|req_tb));
wire [`SORT_WAY-1:0] im_enq_a = {im03_enq_a,im02_enq_a,im01_enq_a,im00_enq_a};
wire [`SORT_WAY-1:0] im_enq_b = {im03_enq_b,im02_enq_b,im01_enq_b,im00_enq_b};
wire [`SORT_WAY-1:0] im_emp_a = {ib03_req_a[1],ib02_req_a[1],ib01_req_a[1],ib00_req_a[1]};
wire [`SORT_WAY-1:0] im_emp_b = {ib03_req_b[1],ib02_req_b[1],ib01_req_b[1],ib00_req_b[1]};
// output
wire reqcnt_a, reqcnt_b, reqcnt_c, reqcnt_d;
wire reqcnt_a_a, reqcnt_b_a, reqcnt_c_a, reqcnt_d_a;
wire reqcnt_a_b, reqcnt_b_b, reqcnt_c_b, reqcnt_d_b;
REQCNTMG reqcntmg(CLK, RSTa, mgdrive, req_ta, im_enq_a, im_emp_a, reqcnt_a, reqcnt_b, reqcnt_c, reqcnt_d);
REQCNTMG reqcntmg_a(CLK, RSTa, mgdrive_a, req_ta, im_enq_a, im_emp_a, reqcnt_a_a, reqcnt_b_a, reqcnt_c_a, reqcnt_d_a);
REQCNTMG reqcntmg_b(CLK, RSTb, mgdrive_b, req_tb, im_enq_b, im_emp_b, reqcnt_a_b, reqcnt_b_b, reqcnt_c_b, reqcnt_d_b);
// ----- write manager -----
// output
wire [31:0] w_block_a;
wire [31:0] w_block_b;
wire [31:0] r_endadr_a_a, r_endadr_b_a, r_endadr_c_a, r_endadr_d_a;
wire [31:0] r_endadr_a_b, r_endadr_b_b, r_endadr_c_b, r_endadr_d_b;
WRITEMG #((`SORT_ELM>>(`P_LOG+`WAY_LOG)))
writemg_a(CLK, RSTa, pchange_a, plast_a, (state==7 && d_req!=0), elem_a, elem_way_a, elem_plast_a, w_addr_a,
w_block_a, r_endadr_a_a, r_endadr_b_a, r_endadr_c_a, r_endadr_d_a);
WRITEMG #((`SORT_ELM>>(`P_LOG+`WAY_LOG)))
writemg_b(CLK, RSTb, pchange_b, plast_b, (state==8 && d_req!=0), elem_b, elem_way_b, elem_plast_b, w_addr_b,
w_block_b, r_endadr_a_b, r_endadr_b_b, r_endadr_c_b, r_endadr_d_b);
// ----- read manager -----
// output
wire [31:0] r_block_a, r_block_b, r_block_c, r_block_d;
wire [31:0] r_block_a_a, r_block_b_a, r_block_c_a, r_block_d_a;
wire [31:0] r_block_a_b, r_block_b_b, r_block_c_b, r_block_d_b;
wire readend_a, readend_b, readend_c, readend_d;
wire readend_a_a, readend_b_a, readend_c_a, readend_d_a;
wire readend_a_b, readend_b_b, readend_c_b, readend_d_b;
READMG readmg(CLK, !last_phase, (state==3 && d_req!=0), req_ta, phase_a[0],
radr_a, radr_b, radr_c, radr_d,
r_endadr_b_a, r_endadr_d_a, r_endadr_b_b, r_endadr_d_b,
r_block_a, r_block_b, r_block_c, r_block_d,
readend_a, readend_b, readend_c, readend_d);
READMG readmg_a(CLK, (RSTa || pchange_a), (state==6 && d_req!=0 && (|req_ta)), req_ta, phase_a[0],
radr_a_a, radr_b_a, radr_c_a, radr_d_a,
r_endadr_a_a, r_endadr_b_a, r_endadr_c_a, r_endadr_d_a,
r_block_a_a, r_block_b_a, r_block_c_a, r_block_d_a,
readend_a_a, readend_b_a, readend_c_a, readend_d_a);
READMG readmg_b(CLK, (RSTb || pchange_b), (state==6 && d_req!=0 && (|req_tb)), req_tb, phase_b[0],
radr_a_b, radr_b_b, radr_c_b, radr_d_b,
r_endadr_a_b, r_endadr_b_b, r_endadr_c_b, r_endadr_d_b,
r_block_a_b, r_block_b_b, r_block_c_b, r_block_d_b,
readend_a_b, readend_b_b, readend_c_b, readend_d_b);
// ----- output buffer -----
reg OB_stopreq_a, OB_stopreq_b;
always @(posedge CLK) OB_stopreq_a <= (d_busy || OB_doten_a || elem_en_a || (elem_way_a==(`SORT_ELM>>(`P_LOG+`WAY_LOG))));
always @(posedge CLK) OB_stopreq_b <= (d_busy || OB_doten_b || elem_en_b || (elem_way_b==(`SORT_ELM>>(`P_LOG+`WAY_LOG))));
always @(posedge CLK) OB_doten_a <= OB_deq_a;
always @(posedge CLK) OB_doten_b <= OB_deq_b;
OTMOD ob_a(CLK, RSTa, OB_stopreq_a, w_block_a, phase_zero, (!last_phase && F01_deq_a), F01_dot_a, OB_deq_a, OB_dot_a, OB_full_a, OB_req_a);
OTMOD ob_b(CLK, RSTb, OB_stopreq_b, w_block_b, phase_zero, F01_deq_b, F01_dot_b, OB_deq_b, OB_dot_b, OB_full_b, OB_req_b);
assign rsltbuf_enq = last_phase && F01_deq_a;
assign rsltbuf_deq = chnl_tx_data_ren && chnl_tx_data_valid;
SRL_FIFO #(4, `MERGW) rsltbuf(CLK, RSTa, rsltbuf_enq, rsltbuf_deq, F01_dot_a,
rslt, rsltbuf_emp, rsltbuf_ful, rsltbuf_cnt);
assign rslt_ready = !rsltbuf_emp;
/***** dram READ/WRITE controller *****/
/**********************************************************************************************/
wire reqhalt_a_a = mux1((readend_a_a || (phase_a==`LAST_PHASE)), c_a_a, (phase_a==1));
wire reqhalt_b_a = mux1((readend_b_a || (phase_a==`LAST_PHASE)), c_b_a, (phase_a==1));
wire reqhalt_c_a = mux1((readend_c_a || (phase_a==`LAST_PHASE)), c_c_a, (phase_a==1));
wire reqhalt_d_a = mux1((readend_d_a || (phase_a==`LAST_PHASE)), c_d_a, (phase_a==1));
wire reqhalt_a_b = mux1((readend_a_b || (phase_b==`LAST_PHASE)), c_a_b, (phase_b==1));
wire reqhalt_b_b = mux1((readend_b_b || (phase_b==`LAST_PHASE)), c_b_b, (phase_b==1));
wire reqhalt_c_b = mux1((readend_c_b || (phase_b==`LAST_PHASE)), c_c_b, (phase_b==1));
wire reqhalt_d_b = mux1((readend_d_b || (phase_b==`LAST_PHASE)), c_d_b, (phase_b==1));
always @(posedge CLK) begin
if (RSTa || pchange_a || pchange_b) begin
if (RSTa) state <= 0;
if (RSTa) {d_req, d_initadr, d_blocks} <= 0;
if (RSTa) w_addr_pzero <= (`SORT_ELM>>1);
req <= 0;
w_addr <= mux32((`SORT_ELM>>1), 0, phase_a[0]);
///////////////// can be parameterized
radr_a <= ((`SELM_PER_WAY>>3)*0);
radr_b <= ((`SELM_PER_WAY>>3)*1);
radr_c <= ((`SELM_PER_WAY>>3)*2);
radr_d <= ((`SELM_PER_WAY>>3)*3);
{cnt_a, cnt_b, cnt_c, cnt_d} <= 0;
{c_a, c_b, c_c, c_d} <= 0;
if ((RSTa || pchange_a) && !plast_a) begin
req_a <= 0;
w_addr_a <= mux32((`SORT_ELM>>1), 0, phase_a[0]);
radr_a_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*0);
radr_b_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*1);
radr_c_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*2);
radr_d_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*3);
{cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a} <= 0;
{c_a_a, c_b_a, c_c_a, c_d_a} <= 0;
OB_granted_a <= 0;
end
if ((RSTa || pchange_b) && !plast_b) begin
req_b <= 0;
w_addr_b <= mux32(((`SORT_ELM>>2) | (`SORT_ELM>>1)), (`SORT_ELM>>2), phase_b[0]);
radr_a_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*0) | (`SORT_ELM>>2);
radr_b_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>2);
radr_c_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>2);
radr_d_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>2);
{cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b} <= 0;
{c_a_b, c_b_b, c_c_b, c_d_b} <= 0;
OB_granted_b <= 0;
end
end else begin
case (state)
////////////////////////////////////////////////////////////////////////////////////////
0: begin ///// Initialize memory, write data to DRAM
if (!phase_zero) state <= 4;
if (d_req != 0) d_req <= 0;
else if (!d_busy) begin
if (OB_req_a || OB_req_b) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr_pzero; //
w_addr_pzero <= w_addr_pzero + (`D_WS); // address for the next write
if (OB_req_a) begin OB_granted_a <= 1; OB_granted_b <= 0; end
else if (OB_req_b) begin OB_granted_a <= 0; OB_granted_b <= 1; end
end
end
end
/////////////////////////////////////////////////////////////////////////////////////
1: begin ///// request arbitration
if (!d_busy && dc_req) begin
///////////////// can be parameterized
if (ib00_req_a[1] && !readend_a && ~reqcnt_a) begin req<=4'h1; state<=3; end // first priority
else if (ib01_req_a[1] && !readend_b && ~reqcnt_b) begin req<=4'h2; state<=3; end //
else if (ib02_req_a[1] && !readend_c && ~reqcnt_c) begin req<=4'h4; state<=3; end //
else if (ib03_req_a[1] && !readend_d && ~reqcnt_d) begin req<=4'h8; state<=3; end //
else state<=2;
end
end
/////////////////////////////////////////////////////////////////////////////////////
2: begin ///// request arbitration
if (!d_busy && dc_req) begin // can be removed
///////////////// can be parameterized
if (ib00_req_a[0] && !readend_a && ~reqcnt_a) begin req<=4'h1; state<=3; end // second priority
else if (ib01_req_a[0] && !readend_b && ~reqcnt_b) begin req<=4'h2; state<=3; end //
else if (ib02_req_a[0] && !readend_c && ~reqcnt_c) begin req<=4'h4; state<=3; end //
else if (ib03_req_a[0] && !readend_d && ~reqcnt_d) begin req<=4'h8; state<=3; end //
end
end
/////////////////////////////////////////////////////////////////////////////////////
3: begin ///// READ data from DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
case (req)
///////////////// can be parameterized
4'h1: begin
d_initadr <= mux32(radr_a, (radr_a | (`SORT_ELM>>1)), phase_a[0]);
radr_a <= radr_a+(r_block_a<<3);
d_blocks <= r_block_a;
end
4'h2: begin
d_initadr <= mux32(radr_b, (radr_b | (`SORT_ELM>>1)), phase_a[0]);
radr_b <= radr_b+(r_block_b<<3);
d_blocks <= r_block_b;
end
4'h4: begin
d_initadr <= mux32(radr_c, (radr_c | (`SORT_ELM>>1)), phase_a[0]);
radr_c <= radr_c+(r_block_c<<3);
d_blocks <= r_block_c;
end
4'h8: begin
d_initadr <= mux32(radr_d, (radr_d | (`SORT_ELM>>1)), phase_a[0]);
radr_d <= radr_d+(r_block_d<<3);
d_blocks <= r_block_d;
end
endcase
d_req <= `DRAM_REQ_READ;
req_ta <= req;
req_tb <= 0;
end
end
////////////////////////////////////////////////////////////////////////////////////////
4: begin
if (!d_busy && dc_req) begin
///////////////// can be parameterized
if (ib00_req_a[1] && !reqhalt_a_a && ~reqcnt_a_a) begin req_a<=4'h1; req_b<=0; state<=6; end // first priority
else if (ib01_req_a[1] && !reqhalt_b_a && ~reqcnt_b_a) begin req_a<=4'h2; req_b<=0; state<=6; end //
else if (ib02_req_a[1] && !reqhalt_c_a && ~reqcnt_c_a) begin req_a<=4'h4; req_b<=0; state<=6; end //
else if (ib03_req_a[1] && !reqhalt_d_a && ~reqcnt_d_a) begin req_a<=4'h8; req_b<=0; state<=6; end //
else if (ib00_req_b[1] && !reqhalt_a_b && ~reqcnt_a_b) begin req_b<=4'h1; req_a<=0; state<=6; end // first priority
else if (ib01_req_b[1] && !reqhalt_b_b && ~reqcnt_b_b) begin req_b<=4'h2; req_a<=0; state<=6; end //
else if (ib02_req_b[1] && !reqhalt_c_b && ~reqcnt_c_b) begin req_b<=4'h4; req_a<=0; state<=6; end //
else if (ib03_req_b[1] && !reqhalt_d_b && ~reqcnt_d_b) begin req_b<=4'h8; req_a<=0; state<=6; end //
else state<=5;
end
end
5: begin
///////////////// can be parameterized
case (plast_a)
0: begin
case (elem_a)
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*1: w_addr_a <= mux32(((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>(`P_LOG+3))*1), phase_a[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2: w_addr_a <= mux32(((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>(`P_LOG+3))*2), phase_a[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*3: w_addr_a <= mux32(((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>(`P_LOG+3))*3), phase_a[0]);
endcase
end
1: begin
case (elem_a)
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2: w_addr_a <= mux32(((`SELM_PER_WAY>>3)*1) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>3)*1), phase_a[0]);
endcase
end
endcase
case (plast_b)
0: begin
case (elem_b)
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*1: w_addr_b <= mux32((((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>2)) | (`SORT_ELM>>1), (((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>2)), phase_b[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2: w_addr_b <= mux32((((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>2)) | (`SORT_ELM>>1), (((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>2)), phase_b[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*3: w_addr_b <= mux32((((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>2)) | (`SORT_ELM>>1), (((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>2)), phase_b[0]);
endcase
end
1: begin
case (elem_b)
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2: w_addr_b <= mux32(((`SELM_PER_WAY>>3)*3) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>3)*3), phase_b[0]);
endcase
end
endcase
if (ib00_req_a[0] && !reqhalt_a_a && ~reqcnt_a_a) begin req_a<=4'h1; req_b<=0; state<=6; end // first priority
else if (ib01_req_a[0] && !reqhalt_b_a && ~reqcnt_b_a) begin req_a<=4'h2; req_b<=0; state<=6; end //
else if (ib02_req_a[0] && !reqhalt_c_a && ~reqcnt_c_a) begin req_a<=4'h4; req_b<=0; state<=6; end //
else if (ib03_req_a[0] && !reqhalt_d_a && ~reqcnt_d_a) begin req_a<=4'h8; req_b<=0; state<=6; end //
else if (ib00_req_b[0] && !reqhalt_a_b && ~reqcnt_a_b) begin req_b<=4'h1; req_a<=0; state<=6; end // first priority
else if (ib01_req_b[0] && !reqhalt_b_b && ~reqcnt_b_b) begin req_b<=4'h2; req_a<=0; state<=6; end //
else if (ib02_req_b[0] && !reqhalt_c_b && ~reqcnt_c_b) begin req_b<=4'h4; req_a<=0; state<=6; end //
else if (ib03_req_b[0] && !reqhalt_d_b && ~reqcnt_d_b) begin req_b<=4'h8; req_a<=0; state<=6; end //
else if (OB_req_a) begin OB_granted_a <= 1; OB_granted_b <= 0; state<=7; end
else if (OB_req_b) begin OB_granted_a <= 0; OB_granted_b <= 1; state<=8; end
else if (last_phase) state<=1;
end
6: begin
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
case ({req_b,req_a})
8'h01: begin
d_initadr <= mux32(radr_a_a, (radr_a_a | (`SORT_ELM>>1)), phase_a[0]);
radr_a_a <= mux32((radr_a_a+(r_block_a_a<<3)), radr_a_a+(`D_RS), (phase_a==1));
cnt_a_a <= cnt_a_a+1;
c_a_a <= (cnt_a_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_a_a, `DRAM_RBLOCKS, (phase_a==1));
end
8'h02: begin
d_initadr <= mux32(radr_b_a, (radr_b_a | (`SORT_ELM>>1)), phase_a[0]);
radr_b_a <= mux32((radr_b_a+(r_block_b_a<<3)), radr_b_a+(`D_RS), (phase_a==1));
cnt_b_a <= cnt_b_a+1;
c_b_a <= (cnt_b_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_b_a, `DRAM_RBLOCKS, (phase_a==1));
end
8'h04: begin
d_initadr <= mux32(radr_c_a, (radr_c_a | (`SORT_ELM>>1)), phase_a[0]);
radr_c_a <= mux32((radr_c_a+(r_block_c_a<<3)), radr_c_a+(`D_RS), (phase_a==1));
cnt_c_a <= cnt_c_a+1;
c_c_a <= (cnt_c_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_c_a, `DRAM_RBLOCKS, (phase_a==1));
end
8'h08: begin
d_initadr <= mux32(radr_d_a, (radr_d_a | (`SORT_ELM>>1)), phase_a[0]);
radr_d_a <= mux32((radr_d_a+(r_block_d_a<<3)), radr_d_a+(`D_RS), (phase_a==1));
cnt_d_a <= cnt_d_a+1;
c_d_a <= (cnt_d_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_d_a, `DRAM_RBLOCKS, (phase_a==1));
end
8'h10: begin
d_initadr <= mux32(radr_a_b, (radr_a_b | (`SORT_ELM>>1)), phase_b[0]);
radr_a_b <= mux32((radr_a_b+(r_block_a_b<<3)), radr_a_b+(`D_RS), (phase_b==1));
cnt_a_b <= cnt_a_b+1;
c_a_b <= (cnt_a_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_a_b, `DRAM_RBLOCKS, (phase_b==1));
end
8'h20: begin
d_initadr <= mux32(radr_b_b, (radr_b_b | (`SORT_ELM>>1)), phase_b[0]);
radr_b_b <= mux32((radr_b_b+(r_block_b_b<<3)), radr_b_b+(`D_RS), (phase_b==1));
cnt_b_b <= cnt_b_b+1;
c_b_b <= (cnt_b_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_b_b, `DRAM_RBLOCKS, (phase_b==1));
end
8'h40: begin
d_initadr <= mux32(radr_c_b, (radr_c_b | (`SORT_ELM>>1)), phase_b[0]);
radr_c_b <= mux32((radr_c_b+(r_block_c_b<<3)), radr_c_b+(`D_RS), (phase_b==1));
cnt_c_b <= cnt_c_b+1;
c_c_b <= (cnt_c_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_c_b, `DRAM_RBLOCKS, (phase_b==1));
end
8'h80: begin
d_initadr <= mux32(radr_d_b, (radr_d_b | (`SORT_ELM>>1)), phase_b[0]);
radr_d_b <= mux32((radr_d_b+(r_block_d_b<<3)), radr_d_b+(`D_RS), (phase_b==1));
cnt_d_b <= cnt_d_b+1;
c_d_b <= (cnt_d_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_d_b, `DRAM_RBLOCKS, (phase_b==1));
end
endcase
d_req <= `DRAM_REQ_READ;
req_ta <= req_a;
req_tb <= req_b;
end
end
7: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= w_block_a; //
d_initadr <= w_addr_a; //
w_addr_a <= w_addr_a + (w_block_a<<3); // address for the next write
end
end
8: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= w_block_b; //
d_initadr <= w_addr_b; //
w_addr_b <= w_addr_b + (w_block_b<<3); // address for the next write
end
end
////////////////////////////////////////////////////////////////////////////////////////
endcase
end
end
/**********************************************************************************************/
always @(posedge CLK) begin
// Stage 0
////////////////////////////////////
dout_ta <= mux512(dc_dout, stnet_dout, phase_zero);
dout_tb <= mux512(dc_dout, stnet_dout, phase_zero);
doen_ta <= mux1(dc_cout[0], stnet_douten, phase_zero);
doen_tb <= mux1(dc_cout[0], stnet_douten, phase_zero);
req_taa <= dc_cout[`SORT_WAY:1];
req_tba <= dc_cout[`SORT_WAY*2:`SORT_WAY+1];
// Stage 1
////////////////////////////////////
dout_tc <= dout_ta;
dout_td <= dout_ta;
dout_te <= dout_tb;
dout_tf <= dout_tb;
doen_tc <= doen_ta;
doen_td <= doen_ta;
doen_te <= doen_tb;
doen_tf <= doen_tb;
req_tab <= req_taa;
req_tbb <= req_tba;
end
// for phase
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
phase_a <= 0;
end else begin
if (elem_a==`SRTP_ELM) phase_a <= phase_a+1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
phase_b <= 0;
end else begin
if (elem_b==`SRTP_ELM) phase_b <= phase_b+1;
end
end
// for plast
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
plast_a <= 0;
end else begin
if (phase_a==`LAST_PHASE-1) plast_a <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
plast_b <= 0;
end else begin
if (phase_b==`LAST_PHASE-1) plast_b <= 1;
end
end
// for elem
// ###########################################################################
reg c_valid_a; // check whether the data is compressed or not
always @(posedge CLK) c_valid_a <= (OB_dot_a[`DRAMW-1:`DRAMW-33] == {32'b0,1'b1});
always @(posedge CLK) elem_en_a <= OB_doten_a;
always @(posedge CLK) begin
if (RSTa) begin
elem_a <= 0;
end else begin
case ({elem_en_a, (elem_a==`SRTP_ELM)})
2'b01: elem_a <= 0;
2'b10: elem_a <= mux32(elem_a+16, elem_a+32, c_valid_a);
endcase
end
end
always @(posedge CLK) begin
if (RSTa) begin
elem_way_a <= 0;
end else begin
case ({elem_en_a, (elem_way_a==(`SORT_ELM>>(`P_LOG+`WAY_LOG)))})
2'b01: elem_way_a <= 0;
2'b10: elem_way_a <= mux32(elem_way_a+16, elem_way_a+32, c_valid_a);
endcase
end
end
always @(posedge CLK) begin
if (RSTa) begin
elem_plast_a <= 0;
end else begin
case ({elem_en_a, (elem_plast_a==(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2)})
2'b01: elem_plast_a <= 0;
2'b10: elem_plast_a <= mux32(elem_plast_a+16, elem_plast_a+32, c_valid_a);
endcase
end
end
reg c_valid_b; // check whether the data is compressed or not
always @(posedge CLK) c_valid_b <= (OB_dot_b[`DRAMW-1:`DRAMW-33] == {32'b0,1'b1});
always @(posedge CLK) elem_en_b <= OB_doten_b;
always @(posedge CLK) begin
if (RSTb) begin
elem_b <= 0;
end else begin
case ({elem_en_b, (elem_b==`SRTP_ELM)})
2'b01: elem_b <= 0;
2'b10: elem_b <= mux32(elem_b+16, elem_b+32, c_valid_b);
endcase
end
end
always @(posedge CLK) begin
if (RSTb) begin
elem_way_b <= 0;
end else begin
case ({elem_en_b, (elem_way_b==(`SORT_ELM>>(`P_LOG+`WAY_LOG)))})
2'b01: elem_way_b <= 0;
2'b10: elem_way_b <= mux32(elem_way_b+16, elem_way_b+32, c_valid_b);
endcase
end
end
always @(posedge CLK) begin
if (RSTb) begin
elem_plast_b <= 0;
end else begin
case ({elem_en_b, (elem_plast_b==(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2)})
2'b01: elem_plast_b <= 0;
2'b10: elem_plast_b <= mux32(elem_plast_b+16, elem_plast_b+32, c_valid_b);
endcase
end
end
// for iter_done
// ###########################################################################
always @(posedge CLK) iter_done_a <= (ecnt_a==8);
always @(posedge CLK) iter_done_b <= (ecnt_b==8);
// for pchange
// ###########################################################################
always @(posedge CLK) pchange_a <= (elem_a==`SRTP_ELM);
always @(posedge CLK) pchange_b <= (elem_b==`SRTP_ELM);
// for irst
// ###########################################################################
always @(posedge CLK) irst_a <= (ecnt_a==8) || pchange_a;
always @(posedge CLK) irst_b <= (ecnt_b==8) || pchange_b;
// for frst
// ###########################################################################
always @(posedge CLK) frst_a <= RSTa || (ecnt_a==8) || (elem_a==`SRTP_ELM);
always @(posedge CLK) frst_b <= RSTb || (ecnt_b==8) || (elem_b==`SRTP_ELM);
// for ecnt
// ###########################################################################
always @(posedge CLK) begin
if (RSTa || iter_done_a || pchange_a) begin
ecnt_a <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_a * `WAY_LOG));
end else begin
if (ecnt_a!=0 && F01_deq_a) ecnt_a <= ecnt_a - 4;
end
end
always @(posedge CLK) begin
if (RSTb || iter_done_b || pchange_b) begin
ecnt_b <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_b * `WAY_LOG));
end else begin
if (ecnt_b!=0 && F01_deq_b) ecnt_b <= ecnt_b - 4;
end
end
// for phase zero
// ###########################################################################
always @(posedge CLK) phase_zero <= ((phase_a == 0) || (phase_b == 0));
// for last phase
// ###########################################################################
always @(posedge CLK) last_phase <= ((phase_a == `LAST_PHASE) && (phase_b == `LAST_PHASE));
// for debug
// ###########################################################################
// (* mark_debug = "true" *) reg [31:0] dcnt;
// always @(posedge CLK) begin
// if (RST) begin
// dcnt <= 0;
// end else begin
// case ({F01_deq, (dcnt==`SORT_ELM)})
// 2'b01: dcnt <= 0;
// 2'b10: dcnt <= dcnt + 4;
// endcase
// end
// end
endmodule // CORE
/**************************************************************************************************/
`default_nettype wire
|
module s1494 (
v4,
v3,
CLR,
v5,
v1,
v0,
blif_clk_net,
v2,
v6,
blif_reset_net,
v13_D_7,
v13_D_15,
v13_D_11,
v13_D_23,
v13_D_17,
v13_D_9,
v13_D_22,
v13_D_20,
v13_D_19,
v13_D_12,
v13_D_18,
v13_D_8,
v13_D_21,
v13_D_6,
v13_D_13,
v13_D_10,
v13_D_24,
v13_D_14,
v13_D_16);
// Start PIs
input v4;
input v3;
input CLR;
input v5;
input v1;
input v0;
input blif_clk_net;
input v2;
input v6;
input blif_reset_net;
// Start POs
output v13_D_7;
output v13_D_15;
output v13_D_11;
output v13_D_23;
output v13_D_17;
output v13_D_9;
output v13_D_22;
output v13_D_20;
output v13_D_19;
output v13_D_12;
output v13_D_18;
output v13_D_8;
output v13_D_21;
output v13_D_6;
output v13_D_13;
output v13_D_10;
output v13_D_24;
output v13_D_14;
output v13_D_16;
// Start wires
wire net_568;
wire net_47;
wire net_416;
wire net_215;
wire net_54;
wire net_526;
wire net_429;
wire net_694;
wire net_557;
wire net_129;
wire net_648;
wire net_373;
wire net_119;
wire net_98;
wire net_739;
wire v13_D_19;
wire net_151;
wire net_356;
wire net_53;
wire net_452;
wire net_210;
wire net_545;
wire net_284;
wire net_168;
wire net_560;
wire net_774;
wire net_741;
wire net_477;
wire net_439;
wire net_385;
wire net_259;
wire net_269;
wire net_548;
wire net_469;
wire net_501;
wire net_187;
wire net_111;
wire net_727;
wire net_264;
wire net_90;
wire net_671;
wire net_225;
wire net_283;
wire net_636;
wire net_85;
wire net_263;
wire net_252;
wire net_124;
wire net_778;
wire net_343;
wire net_770;
wire net_404;
wire net_240;
wire net_160;
wire net_322;
wire net_511;
wire net_4;
wire net_420;
wire net_665;
wire net_447;
wire net_295;
wire net_410;
wire net_508;
wire net_390;
wire net_307;
wire net_35;
wire net_586;
wire net_344;
wire v6;
wire net_16;
wire net_703;
wire v13_D_20;
wire net_712;
wire net_239;
wire net_193;
wire net_257;
wire net_310;
wire net_233;
wire net_474;
wire net_120;
wire net_292;
wire net_201;
wire net_472;
wire net_109;
wire net_80;
wire net_65;
wire net_96;
wire net_484;
wire net_167;
wire net_207;
wire net_136;
wire net_651;
wire net_700;
wire net_682;
wire net_280;
wire net_126;
wire net_744;
wire net_495;
wire net_278;
wire net_34;
wire net_458;
wire net_108;
wire net_598;
wire net_685;
wire net_571;
wire net_63;
wire net_593;
wire net_617;
wire net_601;
wire net_274;
wire net_672;
wire net_777;
wire net_554;
wire net_425;
wire net_321;
wire net_287;
wire net_189;
wire v13_D_23;
wire net_490;
wire net_742;
wire net_720;
wire net_99;
wire net_46;
wire net_480;
wire net_216;
wire net_433;
wire net_584;
wire net_717;
wire net_544;
wire net_368;
wire net_224;
wire net_684;
wire net_632;
wire net_52;
wire net_538;
wire net_165;
wire net_608;
wire net_510;
wire net_370;
wire net_464;
wire net_366;
wire net_13;
wire net_413;
wire net_747;
wire net_446;
wire net_716;
wire net_114;
wire v13_D_10;
wire net_248;
wire net_384;
wire net_36;
wire net_198;
wire net_637;
wire net_253;
wire net_311;
wire net_276;
wire net_760;
wire net_494;
wire net_209;
wire net_3;
wire net_547;
wire net_634;
wire net_294;
wire net_154;
wire net_666;
wire net_507;
wire net_616;
wire net_371;
wire net_238;
wire net_529;
wire net_28;
wire net_704;
wire v13_D_24;
wire net_587;
wire net_485;
wire net_97;
wire net_192;
wire net_649;
wire net_503;
wire net_256;
wire net_460;
wire net_82;
wire net_650;
wire net_64;
wire net_457;
wire net_291;
wire net_735;
wire net_726;
wire net_772;
wire net_679;
wire net_121;
wire net_597;
wire net_200;
wire net_308;
wire net_75;
wire net_515;
wire net_743;
wire net_600;
wire net_396;
wire net_757;
wire net_701;
wire net_206;
wire net_195;
wire net_125;
wire net_397;
wire net_107;
wire net_166;
wire net_223;
wire net_715;
wire net_235;
wire v13_D_7;
wire net_530;
wire net_606;
wire net_623;
wire net_663;
wire net_603;
wire net_594;
wire net_320;
wire net_271;
wire net_23;
wire net_117;
wire net_74;
wire net_673;
wire net_642;
wire net_579;
wire net_401;
wire net_250;
wire net_205;
wire net_769;
wire net_699;
wire net_242;
wire net_312;
wire net_130;
wire net_572;
wire net_359;
wire net_440;
wire net_286;
wire net_147;
wire net_481;
wire net_369;
wire net_758;
wire net_470;
wire net_26;
wire net_403;
wire net_334;
wire blif_clk_net;
wire net_32;
wire net_430;
wire net_718;
wire net_365;
wire net_282;
wire net_645;
wire net_426;
wire net_380;
wire net_141;
wire net_780;
wire net_467;
wire v1;
wire net_83;
wire net_609;
wire net_541;
wire net_414;
wire net_372;
wire net_437;
wire net_528;
wire net_56;
wire net_566;
wire net_456;
wire net_155;
wire net_705;
wire net_335;
wire net_506;
wire net_181;
wire net_336;
wire net_624;
wire net_349;
wire net_39;
wire net_555;
wire net_245;
wire net_2;
wire v3;
wire net_9;
wire net_395;
wire net_331;
wire net_298;
wire net_493;
wire net_688;
wire net_697;
wire net_475;
wire net_563;
wire net_386;
wire net_641;
wire net_605;
wire net_277;
wire net_199;
wire net_502;
wire net_431;
wire net_89;
wire net_290;
wire net_680;
wire net_338;
wire net_721;
wire net_638;
wire v13_D_14;
wire net_243;
wire net_400;
wire net_759;
wire net_222;
wire net_602;
wire net_313;
wire net_152;
wire net_489;
wire net_714;
wire net_175;
wire net_657;
wire net_106;
wire net_683;
wire net_607;
wire net_258;
wire net_140;
wire net_740;
wire net_247;
wire net_329;
wire net_279;
wire net_148;
wire net_698;
wire v13_D_8;
wire net_419;
wire net_25;
wire v13_D_13;
wire net_70;
wire net_691;
wire net_251;
wire net_194;
wire net_730;
wire net_615;
wire net_478;
wire net_244;
wire net_664;
wire net_585;
wire net_441;
wire net_128;
wire net_596;
wire v5;
wire net_138;
wire net_749;
wire net_333;
wire net_639;
wire net_728;
wire net_549;
wire net_374;
wire net_719;
wire net_411;
wire net_170;
wire net_531;
wire net_471;
wire net_565;
wire net_499;
wire net_77;
wire net_214;
wire net_249;
wire net_20;
wire net_49;
wire net_518;
wire v4;
wire net_15;
wire net_57;
wire net_706;
wire net_71;
wire net_771;
wire net_156;
wire net_394;
wire net_92;
wire net_1;
wire net_112;
wire net_708;
wire net_139;
wire net_696;
wire net_551;
wire net_537;
wire net_332;
wire net_180;
wire net_409;
wire net_367;
wire net_169;
wire net_51;
wire net_171;
wire net_492;
wire net_463;
wire net_656;
wire net_432;
wire net_88;
wire net_197;
wire net_513;
wire net_204;
wire net_766;
wire net_81;
wire net_232;
wire net_604;
wire net_163;
wire net_402;
wire net_67;
wire v13_D_9;
wire net_202;
wire net_268;
wire net_110;
wire net_722;
wire net_379;
wire net_459;
wire net_483;
wire net_48;
wire net_33;
wire net_8;
wire net_737;
wire net_203;
wire net_450;
wire net_289;
wire net_505;
wire net_621;
wire net_435;
wire net_176;
wire net_137;
wire net_296;
wire net_132;
wire net_613;
wire net_237;
wire net_105;
wire net_782;
wire net_614;
wire net_532;
wire net_12;
wire net_93;
wire net_578;
wire net_302;
wire net_569;
wire v13_D_16;
wire net_768;
wire net_127;
wire net_327;
wire net_357;
wire net_348;
wire net_753;
wire net_630;
wire net_76;
wire net_626;
wire net_101;
wire net_388;
wire net_326;
wire net_353;
wire net_707;
wire net_589;
wire net_519;
wire net_100;
wire net_412;
wire net_655;
wire net_686;
wire net_652;
wire net_536;
wire CLR;
wire net_455;
wire net_221;
wire net_115;
wire net_689;
wire v2;
wire net_751;
wire net_393;
wire net_442;
wire net_17;
wire net_319;
wire net_542;
wire net_453;
wire net_575;
wire net_595;
wire net_581;
wire net_378;
wire net_164;
wire net_408;
wire net_724;
wire net_731;
wire net_377;
wire net_87;
wire net_0;
wire net_288;
wire net_423;
wire net_658;
wire net_328;
wire net_734;
wire net_157;
wire net_540;
wire net_512;
wire net_42;
wire net_779;
wire net_662;
wire blif_reset_net;
wire net_50;
wire net_234;
wire net_38;
wire net_66;
wire net_466;
wire net_765;
wire net_675;
wire net_342;
wire net_612;
wire net_19;
wire net_738;
wire net_443;
wire net_504;
wire net_522;
wire net_270;
wire net_674;
wire net_183;
wire net_668;
wire net_618;
wire v13_D_6;
wire net_150;
wire net_303;
wire net_304;
wire net_352;
wire net_491;
wire net_644;
wire net_30;
wire net_681;
wire net_643;
wire net_783;
wire net_436;
wire net_24;
wire net_392;
wire net_622;
wire net_186;
wire net_118;
wire net_754;
wire net_421;
wire net_146;
wire net_764;
wire net_550;
wire net_122;
wire net_417;
wire net_7;
wire v0;
wire net_172;
wire net_428;
wire net_94;
wire net_246;
wire net_461;
wire net_767;
wire net_219;
wire net_640;
wire net_18;
wire net_309;
wire net_482;
wire net_659;
wire net_131;
wire net_196;
wire net_29;
wire net_775;
wire net_358;
wire net_142;
wire net_149;
wire net_752;
wire net_516;
wire net_654;
wire net_31;
wire net_387;
wire net_330;
wire net_535;
wire net_498;
wire net_158;
wire net_676;
wire net_41;
wire v13_D_15;
wire net_713;
wire net_577;
wire net_693;
wire net_360;
wire net_570;
wire net_525;
wire net_444;
wire net_213;
wire net_325;
wire net_729;
wire net_301;
wire net_260;
wire net_299;
wire net_438;
wire net_732;
wire net_580;
wire net_314;
wire net_182;
wire net_521;
wire net_60;
wire net_590;
wire net_337;
wire net_341;
wire net_267;
wire net_273;
wire net_424;
wire net_468;
wire net_58;
wire net_690;
wire net_576;
wire net_488;
wire net_73;
wire net_465;
wire net_86;
wire net_177;
wire net_523;
wire net_407;
wire net_476;
wire net_564;
wire net_382;
wire net_179;
wire net_725;
wire net_159;
wire net_61;
wire net_583;
wire net_449;
wire net_383;
wire net_62;
wire net_6;
wire net_553;
wire net_534;
wire net_217;
wire net_351;
wire v13_D_12;
wire net_733;
wire net_763;
wire net_427;
wire net_486;
wire net_135;
wire net_340;
wire net_265;
wire net_517;
wire net_628;
wire net_434;
wire net_406;
wire net_473;
wire net_220;
wire net_14;
wire net_633;
wire net_293;
wire net_324;
wire net_113;
wire net_710;
wire net_497;
wire net_454;
wire net_418;
wire net_462;
wire net_40;
wire net_69;
wire net_543;
wire net_709;
wire net_161;
wire net_625;
wire net_300;
wire net_339;
wire net_748;
wire net_677;
wire net_95;
wire net_173;
wire net_361;
wire net_78;
wire net_27;
wire net_317;
wire net_305;
wire v13_D_11;
wire net_514;
wire net_191;
wire net_261;
wire net_22;
wire net_376;
wire net_558;
wire net_354;
wire net_660;
wire net_524;
wire net_144;
wire net_102;
wire net_227;
wire net_59;
wire net_646;
wire net_363;
wire net_445;
wire net_573;
wire net_162;
wire net_776;
wire net_781;
wire net_44;
wire net_230;
wire net_653;
wire net_784;
wire net_520;
wire net_422;
wire net_134;
wire net_678;
wire net_546;
wire net_561;
wire net_567;
wire net_45;
wire net_381;
wire net_702;
wire net_591;
wire net_185;
wire v13_D_22;
wire net_746;
wire net_588;
wire v13_D_18;
wire net_272;
wire net_178;
wire net_667;
wire net_208;
wire net_236;
wire net_487;
wire net_212;
wire net_315;
wire net_762;
wire net_552;
wire net_695;
wire net_415;
wire net_116;
wire net_556;
wire net_347;
wire net_756;
wire net_91;
wire net_297;
wire net_346;
wire net_629;
wire net_55;
wire net_559;
wire net_635;
wire net_255;
wire net_266;
wire net_345;
wire net_104;
wire net_620;
wire net_448;
wire net_619;
wire net_72;
wire net_350;
wire net_229;
wire net_398;
wire net_627;
wire net_306;
wire net_687;
wire net_241;
wire net_5;
wire net_405;
wire net_500;
wire net_355;
wire net_184;
wire net_711;
wire net_599;
wire net_631;
wire net_11;
wire net_610;
wire net_723;
wire net_123;
wire net_527;
wire net_262;
wire net_362;
wire net_389;
wire net_68;
wire net_318;
wire net_451;
wire net_323;
wire net_750;
wire net_736;
wire net_275;
wire net_539;
wire net_399;
wire net_692;
wire net_153;
wire v13_D_17;
wire net_316;
wire net_218;
wire net_84;
wire net_670;
wire net_174;
wire net_611;
wire net_231;
wire net_562;
wire net_103;
wire net_375;
wire net_226;
wire net_364;
wire net_43;
wire v13_D_21;
wire net_10;
wire net_228;
wire net_592;
wire net_21;
wire net_647;
wire net_79;
wire net_143;
wire net_190;
wire net_773;
wire net_391;
wire net_533;
wire net_145;
wire net_285;
wire net_281;
wire net_669;
wire net_254;
wire net_37;
wire net_582;
wire net_188;
wire net_761;
wire net_496;
wire net_755;
wire net_509;
wire net_574;
wire net_479;
wire net_661;
wire net_211;
wire net_133;
wire net_745;
// Start cells
INV_X4 inst_537 ( .A(net_190), .ZN(net_10) );
INV_X4 inst_696 ( .A(net_429), .ZN(net_372) );
NAND2_X2 inst_481 ( .A1(net_638), .A2(net_627), .ZN(v13_D_10) );
INV_X4 inst_551 ( .ZN(net_193), .A(net_48) );
NAND2_X4 inst_228 ( .A2(net_758), .A1(net_706), .ZN(net_606) );
NOR2_X1 inst_125 ( .A2(net_615), .A1(net_446), .ZN(v13_D_18) );
NAND2_X1 inst_486 ( .A1(net_760), .ZN(net_15), .A2(net_0) );
INV_X8 inst_506 ( .ZN(net_57), .A(net_48) );
NAND2_X1 inst_495 ( .ZN(net_475), .A1(net_400), .A2(net_354) );
NAND2_X2 inst_353 ( .ZN(net_400), .A2(net_399), .A1(net_296) );
NAND2_X4 inst_207 ( .A2(net_737), .A1(net_736), .ZN(net_182) );
NAND3_X2 inst_159 ( .A1(net_718), .A3(net_393), .ZN(net_289), .A2(net_148) );
INV_X4 inst_707 ( .ZN(net_458), .A(net_376) );
AND2_X2 inst_779 ( .A1(net_504), .ZN(net_221), .A2(net_220) );
NAND2_X2 inst_395 ( .ZN(net_496), .A1(net_385), .A2(net_285) );
NAND4_X2 inst_134 ( .ZN(net_503), .A1(net_502), .A3(net_501), .A4(net_112), .A2(net_66) );
NAND2_X2 inst_244 ( .A2(net_760), .ZN(net_97), .A1(net_31) );
NAND2_X2 inst_333 ( .ZN(net_345), .A1(net_344), .A2(net_185) );
INV_X4 inst_712 ( .ZN(net_522), .A(net_479) );
NAND2_X2 inst_452 ( .ZN(net_610), .A2(net_582), .A1(net_414) );
INV_X4 inst_689 ( .ZN(net_429), .A(net_390) );
NAND2_X2 inst_430 ( .ZN(net_566), .A1(net_491), .A2(net_485) );
NAND4_X2 inst_131 ( .ZN(net_411), .A2(net_226), .A4(net_222), .A3(net_219), .A1(net_164) );
NAND2_X2 inst_406 ( .ZN(net_521), .A1(net_520), .A2(net_452) );
NAND2_X4 inst_214 ( .ZN(net_719), .A1(net_225), .A2(net_110) );
NAND2_X2 inst_462 ( .ZN(net_623), .A2(net_589), .A1(net_551) );
NAND3_X2 inst_160 ( .ZN(net_291), .A2(net_255), .A1(net_174), .A3(net_105) );
NAND2_X2 inst_328 ( .ZN(net_332), .A2(net_251), .A1(net_139) );
NOR2_X4 inst_47 ( .A1(net_760), .ZN(net_79), .A2(net_1) );
OR2_X2 inst_19 ( .ZN(net_325), .A1(net_324), .A2(net_294) );
INV_X4 inst_548 ( .A(net_760), .ZN(net_58) );
INV_X8 inst_515 ( .ZN(net_363), .A(net_78) );
OR2_X4 inst_8 ( .A1(net_762), .ZN(net_716), .A2(v0) );
AND2_X4 inst_772 ( .ZN(net_216), .A1(net_54), .A2(net_17) );
INV_X2 inst_728 ( .A(net_131), .ZN(net_90) );
DFFR_X2 inst_762 ( .QN(net_762), .RN(net_657), .D(net_653), .CK(net_766) );
NAND2_X2 inst_370 ( .ZN(net_442), .A2(net_313), .A1(net_211) );
INV_X4 inst_573 ( .ZN(net_725), .A(net_40) );
NOR2_X2 inst_100 ( .ZN(net_437), .A1(net_326), .A2(net_312) );
INV_X4 inst_642 ( .A(net_253), .ZN(net_240) );
NAND2_X2 inst_459 ( .ZN(net_620), .A2(net_597), .A1(net_186) );
NAND2_X2 inst_279 ( .A1(net_756), .ZN(net_336), .A2(net_131) );
NAND2_X2 inst_445 ( .ZN(net_595), .A1(net_594), .A2(net_537) );
INV_X4 inst_709 ( .ZN(net_575), .A(net_491) );
NOR2_X2 inst_93 ( .ZN(net_374), .A1(net_257), .A2(net_221) );
INV_X4 inst_700 ( .A(net_603), .ZN(net_416) );
NOR2_X2 inst_81 ( .A1(net_211), .ZN(net_203), .A2(net_10) );
INV_X4 inst_612 ( .ZN(net_119), .A(net_91) );
INV_X4 inst_606 ( .A(net_125), .ZN(net_116) );
NAND2_X2 inst_367 ( .ZN(net_439), .A1(net_299), .A2(net_235) );
INV_X4 inst_525 ( .ZN(net_46), .A(v0) );
NAND4_X2 inst_139 ( .ZN(net_619), .A2(net_586), .A4(net_543), .A3(net_448), .A1(net_223) );
INV_X4 inst_657 ( .ZN(net_412), .A(net_268) );
INV_X4 inst_559 ( .ZN(net_23), .A(net_22) );
INV_X4 inst_584 ( .ZN(net_78), .A(net_31) );
INV_X8 inst_521 ( .ZN(net_316), .A(net_233) );
CLKBUF_X2 inst_790 ( .A(net_770), .Z(net_771) );
NAND2_X2 inst_434 ( .ZN(net_574), .A2(net_513), .A1(net_341) );
NAND2_X2 inst_470 ( .ZN(net_632), .A2(net_612), .A1(net_577) );
INV_X2 inst_751 ( .ZN(net_319), .A(net_249) );
INV_X4 inst_535 ( .A(net_46), .ZN(net_8) );
NAND2_X2 inst_450 ( .ZN(net_607), .A2(net_574), .A1(net_544) );
INV_X2 inst_745 ( .ZN(net_235), .A(net_234) );
INV_X8 inst_520 ( .A(net_535), .ZN(net_314) );
NAND2_X2 inst_237 ( .A1(net_762), .A2(net_761), .ZN(net_29) );
NAND3_X4 inst_148 ( .ZN(net_636), .A3(net_606), .A1(net_536), .A2(net_444) );
INV_X4 inst_554 ( .ZN(net_131), .A(net_58) );
INV_X2 inst_733 ( .ZN(net_110), .A(net_109) );
NAND2_X2 inst_377 ( .ZN(net_465), .A1(net_394), .A2(net_342) );
NAND3_X2 inst_191 ( .A3(net_667), .A1(net_666), .ZN(net_650), .A2(net_529) );
NOR2_X4 inst_51 ( .ZN(net_94), .A2(net_50), .A1(net_31) );
NAND3_X4 inst_142 ( .ZN(net_751), .A2(net_675), .A1(net_674), .A3(net_36) );
NAND2_X2 inst_315 ( .ZN(net_277), .A2(net_200), .A1(net_10) );
NOR2_X2 inst_80 ( .A2(net_747), .A1(net_746), .ZN(net_198) );
NAND2_X4 inst_216 ( .A1(net_710), .ZN(net_691), .A2(net_190) );
NOR2_X2 inst_78 ( .A1(net_425), .ZN(net_173), .A2(net_104) );
NAND2_X2 inst_241 ( .A2(net_760), .ZN(net_77), .A1(net_48) );
NAND3_X2 inst_177 ( .ZN(net_534), .A2(net_501), .A1(net_450), .A3(net_431) );
CLKBUF_X2 inst_783 ( .A(blif_clk_net), .Z(net_764) );
NAND3_X2 inst_183 ( .A2(net_753), .A1(net_752), .ZN(net_682), .A3(net_664) );
NAND3_X2 inst_151 ( .ZN(net_259), .A1(net_135), .A2(net_58), .A3(net_22) );
NOR2_X2 inst_64 ( .ZN(net_24), .A1(net_12), .A2(v1) );
INV_X2 inst_743 ( .A(net_340), .ZN(net_181) );
NAND2_X2 inst_415 ( .A1(net_596), .ZN(net_537), .A2(net_490) );
INV_X4 inst_615 ( .ZN(net_162), .A(net_95) );
NAND2_X2 inst_393 ( .A1(net_526), .ZN(net_493), .A2(net_373) );
NOR2_X2 inst_107 ( .ZN(net_530), .A1(net_455), .A2(net_293) );
NOR2_X2 inst_92 ( .ZN(net_317), .A2(net_303), .A1(net_238) );
NAND2_X2 inst_345 ( .ZN(net_371), .A1(net_275), .A2(net_250) );
NAND2_X4 inst_223 ( .A1(net_748), .ZN(net_700), .A2(net_169) );
NAND2_X2 inst_402 ( .ZN(net_515), .A2(net_441), .A1(net_129) );
NAND2_X2 inst_340 ( .ZN(net_366), .A1(net_349), .A2(net_273) );
INV_X4 inst_643 ( .ZN(net_272), .A(net_157) );
INV_X4 inst_697 ( .ZN(net_550), .A(net_377) );
NAND2_X1 inst_494 ( .ZN(net_452), .A2(net_451), .A1(net_316) );
NAND2_X1 inst_487 ( .A2(net_135), .ZN(net_98), .A1(net_14) );
NAND2_X2 inst_329 ( .ZN(net_335), .A2(net_334), .A1(net_316) );
INV_X4 inst_574 ( .A(net_79), .ZN(net_49) );
NAND2_X2 inst_386 ( .ZN(net_482), .A1(net_481), .A2(net_338) );
NAND3_X2 inst_158 ( .ZN(net_288), .A2(net_287), .A1(net_156), .A3(net_150) );
NAND4_X2 inst_141 ( .A1(net_720), .ZN(net_633), .A3(net_583), .A4(net_467), .A2(net_330) );
NAND2_X4 inst_200 ( .A1(net_725), .ZN(net_118), .A2(net_79) );
INV_X8 inst_507 ( .ZN(net_106), .A(net_31) );
INV_X4 inst_571 ( .A(net_758), .ZN(net_600) );
NOR2_X4 inst_57 ( .ZN(net_150), .A2(net_70), .A1(net_31) );
NAND2_X2 inst_338 ( .ZN(net_361), .A2(net_207), .A1(net_70) );
INV_X4 inst_711 ( .ZN(net_492), .A(net_491) );
INV_X4 inst_552 ( .ZN(net_68), .A(net_55) );
INV_X4 inst_599 ( .A(net_393), .ZN(net_104) );
NAND2_X2 inst_417 ( .ZN(net_539), .A2(net_477), .A1(net_260) );
INV_X4 inst_671 ( .ZN(net_404), .A(net_242) );
INV_X4 inst_579 ( .ZN(net_136), .A(net_30) );
OR2_X2 inst_21 ( .ZN(net_337), .A2(net_336), .A1(net_151) );
NAND2_X2 inst_469 ( .ZN(net_630), .A2(net_610), .A1(net_474) );
NAND2_X2 inst_281 ( .A2(net_245), .ZN(net_195), .A1(net_178) );
INV_X4 inst_585 ( .ZN(net_393), .A(net_84) );
INV_X4 inst_698 ( .ZN(net_489), .A(net_378) );
OR2_X2 inst_18 ( .A2(net_758), .A1(net_544), .ZN(net_307) );
INV_X4 inst_541 ( .ZN(net_542), .A(net_287) );
NAND2_X2 inst_410 ( .ZN(net_527), .A1(net_526), .A2(net_418) );
NAND2_X4 inst_208 ( .ZN(net_740), .A2(net_131), .A1(net_124) );
NOR2_X2 inst_88 ( .A1(net_347), .ZN(net_310), .A2(net_139) );
NAND2_X2 inst_316 ( .ZN(net_278), .A2(net_191), .A1(net_49) );
NAND2_X4 inst_220 ( .A1(net_729), .ZN(net_445), .A2(net_106) );
OR2_X4 inst_9 ( .ZN(net_586), .A1(net_44), .A2(v4) );
NOR2_X2 inst_113 ( .ZN(net_590), .A2(net_561), .A1(net_481) );
INV_X8 inst_505 ( .A(net_761), .ZN(net_48) );
NAND2_X2 inst_356 ( .ZN(net_407), .A2(net_291), .A1(net_126) );
NAND2_X2 inst_383 ( .ZN(net_471), .A2(net_398), .A1(net_114) );
NAND2_X2 inst_360 ( .ZN(net_418), .A2(net_397), .A1(net_381) );
AND2_X4 inst_773 ( .A1(net_762), .ZN(net_747), .A2(net_31) );
NAND2_X4 inst_198 ( .ZN(net_81), .A2(net_50), .A1(net_17) );
NOR2_X4 inst_50 ( .A1(net_193), .ZN(net_178), .A2(net_2) );
NAND2_X2 inst_245 ( .ZN(net_60), .A2(net_26), .A1(net_17) );
INV_X4 inst_569 ( .A(net_303), .ZN(net_37) );
INV_X4 inst_678 ( .ZN(net_385), .A(net_314) );
INV_X4 inst_624 ( .ZN(net_321), .A(net_281) );
NAND2_X2 inst_260 ( .A2(net_718), .A1(net_716), .ZN(net_707) );
CLKBUF_X2 inst_784 ( .A(net_764), .Z(net_765) );
INV_X2 inst_721 ( .ZN(net_28), .A(net_17) );
NAND3_X4 inst_147 ( .ZN(net_631), .A3(net_601), .A1(net_591), .A2(net_493) );
INV_X2 inst_744 ( .A(net_643), .ZN(net_186) );
NAND2_X2 inst_313 ( .ZN(net_275), .A2(net_274), .A1(net_237) );
NAND2_X2 inst_293 ( .A2(net_297), .ZN(net_219), .A1(net_206) );
AND2_X2 inst_778 ( .A2(net_211), .ZN(net_204), .A1(net_115) );
INV_X4 inst_636 ( .ZN(net_149), .A(net_148) );
INV_X4 inst_632 ( .ZN(net_197), .A(net_127) );
INV_X4 inst_549 ( .ZN(net_53), .A(net_48) );
NAND2_X2 inst_234 ( .A1(net_762), .ZN(net_40), .A2(net_17) );
XNOR2_X2 inst_0 ( .ZN(net_495), .A(net_316), .B(net_84) );
INV_X8 inst_522 ( .A(net_520), .ZN(net_456) );
NAND3_X2 inst_184 ( .ZN(net_706), .A3(net_669), .A1(net_668), .A2(net_478) );
INV_X4 inst_690 ( .ZN(net_402), .A(net_316) );
NAND2_X2 inst_236 ( .A2(net_287), .A1(net_54), .ZN(net_20) );
NAND2_X2 inst_433 ( .ZN(net_570), .A1(net_569), .A2(net_531) );
INV_X4 inst_553 ( .ZN(net_56), .A(net_22) );
NAND2_X2 inst_478 ( .ZN(net_645), .A1(net_643), .A2(net_626) );
NOR2_X2 inst_65 ( .A2(net_762), .ZN(net_27), .A1(net_4) );
INV_X4 inst_536 ( .A(net_54), .ZN(net_50) );
NAND2_X2 inst_242 ( .ZN(net_82), .A1(net_55), .A2(net_53) );
INV_X4 inst_688 ( .ZN(net_426), .A(net_306) );
AND2_X2 inst_781 ( .A1(net_451), .ZN(net_422), .A2(net_333) );
INV_X2 inst_732 ( .ZN(net_108), .A(net_107) );
INV_X8 inst_516 ( .ZN(net_686), .A(net_118) );
NOR2_X2 inst_98 ( .ZN(net_433), .A2(net_317), .A1(net_314) );
NAND2_X2 inst_263 ( .ZN(net_140), .A1(net_77), .A2(net_16) );
NAND3_X2 inst_190 ( .A1(net_645), .A3(net_635), .A2(net_599), .ZN(v13_D_24) );
NAND3_X2 inst_185 ( .ZN(net_599), .A1(net_562), .A3(net_443), .A2(net_34) );
OR2_X4 inst_13 ( .ZN(net_401), .A1(net_390), .A2(net_274) );
NOR2_X2 inst_75 ( .A1(net_762), .ZN(net_156), .A2(net_131) );
NAND2_X2 inst_332 ( .A2(net_346), .ZN(net_343), .A1(net_211) );
NAND3_X2 inst_166 ( .A2(net_751), .A1(net_750), .A3(net_698), .ZN(net_384) );
NOR2_X2 inst_116 ( .ZN(net_624), .A2(net_590), .A1(net_405) );
INV_X4 inst_598 ( .A(net_102), .ZN(net_76) );
NAND2_X2 inst_416 ( .ZN(net_538), .A2(net_487), .A1(net_385) );
NAND3_X2 inst_163 ( .A1(net_745), .ZN(net_376), .A2(net_102), .A3(net_31) );
NAND2_X2 inst_471 ( .ZN(net_635), .A2(net_623), .A1(net_603) );
NAND2_X2 inst_394 ( .ZN(net_494), .A2(net_380), .A1(v4) );
NOR2_X2 inst_79 ( .A1(net_730), .ZN(net_234), .A2(net_127) );
CLKBUF_X2 inst_799 ( .A(net_779), .Z(net_780) );
NOR2_X2 inst_106 ( .A2(net_697), .A1(net_696), .ZN(net_689) );
INV_X2 inst_738 ( .ZN(net_146), .A(net_145) );
NAND2_X2 inst_422 ( .ZN(net_553), .A1(net_552), .A2(net_466) );
NAND2_X4 inst_219 ( .A1(net_722), .ZN(net_396), .A2(net_106) );
INV_X2 inst_719 ( .A(net_760), .ZN(net_9) );
NAND2_X4 inst_201 ( .A2(net_542), .A1(net_161), .ZN(net_88) );
INV_X4 inst_605 ( .ZN(net_737), .A(net_82) );
NAND2_X2 inst_304 ( .A1(net_526), .ZN(net_462), .A2(net_255) );
INV_X2 inst_752 ( .A(net_446), .ZN(net_380) );
INV_X4 inst_542 ( .A(net_10), .ZN(net_7) );
NAND2_X2 inst_255 ( .A2(net_758), .ZN(net_114), .A1(net_113) );
NAND2_X2 inst_453 ( .ZN(net_612), .A1(net_611), .A2(net_585) );
NAND4_X2 inst_128 ( .A2(net_499), .A1(net_303), .ZN(net_282), .A4(net_281), .A3(net_253) );
NOR2_X2 inst_73 ( .ZN(net_746), .A1(net_287), .A2(net_128) );
NAND2_X1 inst_493 ( .A2(net_354), .ZN(net_309), .A1(net_308) );
NAND2_X2 inst_378 ( .A1(net_510), .ZN(net_466), .A2(net_170) );
OR2_X2 inst_23 ( .ZN(net_352), .A1(net_347), .A2(net_204) );
NAND2_X2 inst_339 ( .ZN(net_365), .A1(net_364), .A2(net_209) );
NAND2_X2 inst_351 ( .ZN(net_392), .A1(net_391), .A2(net_281) );
NAND2_X2 inst_361 ( .ZN(net_420), .A1(net_419), .A2(net_332) );
NAND2_X2 inst_408 ( .A1(net_542), .ZN(net_523), .A2(net_415) );
NAND2_X2 inst_325 ( .ZN(net_327), .A1(net_326), .A2(net_324) );
NAND2_X2 inst_461 ( .A2(net_758), .A1(net_711), .ZN(net_662) );
NAND2_X2 inst_385 ( .ZN(net_480), .A1(net_456), .A2(net_322) );
NAND2_X4 inst_197 ( .ZN(net_99), .A2(net_42), .A1(net_21) );
INV_X4 inst_659 ( .ZN(net_242), .A(net_240) );
NAND2_X2 inst_250 ( .A2(net_274), .ZN(net_92), .A1(net_28) );
NAND3_X2 inst_179 ( .ZN(net_549), .A2(net_457), .A3(net_451), .A1(net_309) );
OR2_X2 inst_24 ( .ZN(net_490), .A1(net_489), .A2(net_408) );
NOR2_X2 inst_114 ( .ZN(net_608), .A2(net_580), .A1(net_547) );
CLKBUF_X2 inst_786 ( .A(net_765), .Z(net_767) );
INV_X4 inst_617 ( .ZN(net_100), .A(net_99) );
NOR2_X2 inst_76 ( .ZN(net_399), .A2(net_134), .A1(net_131) );
NAND2_X2 inst_397 ( .ZN(net_506), .A2(net_473), .A1(net_306) );
INV_X8 inst_504 ( .ZN(net_17), .A(net_5) );
NAND3_X2 inst_150 ( .A3(net_761), .ZN(net_33), .A2(net_32), .A1(net_12) );
NAND3_X2 inst_172 ( .ZN(net_434), .A2(net_393), .A3(net_262), .A1(net_89) );
NAND2_X2 inst_362 ( .ZN(net_421), .A2(net_345), .A1(net_301) );
NAND2_X2 inst_277 ( .ZN(net_710), .A2(net_92), .A1(net_60) );
NOR2_X2 inst_83 ( .ZN(net_254), .A2(net_253), .A1(net_139) );
NOR2_X2 inst_121 ( .A1(net_690), .A2(net_654), .ZN(net_653) );
INV_X4 inst_534 ( .ZN(net_134), .A(net_54) );
NAND2_X2 inst_440 ( .ZN(net_585), .A1(net_533), .A2(net_523) );
NAND2_X2 inst_306 ( .ZN(net_735), .A2(net_259), .A1(net_155) );
OR3_X2 inst_2 ( .A1(net_368), .ZN(net_228), .A3(net_227), .A2(net_36) );
INV_X4 inst_644 ( .A(net_388), .ZN(net_265) );
INV_X4 inst_596 ( .ZN(net_425), .A(net_75) );
INV_X4 inst_578 ( .ZN(net_210), .A(net_52) );
NOR2_X4 inst_52 ( .ZN(net_176), .A2(net_93), .A1(net_31) );
NOR2_X2 inst_90 ( .A2(net_600), .A1(net_314), .ZN(net_312) );
NAND2_X2 inst_267 ( .ZN(net_155), .A2(net_154), .A1(net_96) );
NAND4_X2 inst_140 ( .ZN(net_621), .A1(net_584), .A3(net_558), .A4(net_519), .A2(net_483) );
INV_X4 inst_668 ( .ZN(net_238), .A(net_237) );
NAND2_X4 inst_221 ( .A1(net_708), .ZN(net_658), .A2(net_134) );
INV_X2 inst_748 ( .ZN(net_280), .A(net_279) );
INV_X2 inst_716 ( .ZN(net_0), .A(v3) );
INV_X4 inst_556 ( .ZN(net_303), .A(net_18) );
INV_X4 inst_650 ( .A(net_643), .ZN(net_594) );
INV_X4 inst_637 ( .ZN(net_196), .A(net_132) );
NAND2_X2 inst_289 ( .ZN(net_596), .A2(net_274), .A1(net_132) );
CLKBUF_X2 inst_792 ( .A(net_772), .Z(net_773) );
INV_X4 inst_547 ( .ZN(net_14), .A(net_13) );
INV_X4 inst_530 ( .ZN(net_190), .A(v3) );
INV_X2 inst_720 ( .ZN(net_62), .A(net_24) );
NAND2_X2 inst_432 ( .ZN(net_568), .A2(net_527), .A1(net_506) );
INV_X4 inst_679 ( .ZN(net_358), .A(net_341) );
NAND2_X2 inst_420 ( .ZN(net_551), .A1(net_550), .A2(net_495) );
NAND2_X2 inst_282 ( .A1(net_707), .ZN(net_705), .A2(net_197) );
NAND2_X2 inst_368 ( .ZN(net_440), .A1(net_316), .A2(net_184) );
INV_X8 inst_513 ( .ZN(net_124), .A(net_69) );
CLKBUF_X2 inst_803 ( .A(net_783), .Z(net_784) );
INV_X2 inst_754 ( .A(net_572), .ZN(net_469) );
AND2_X4 inst_769 ( .A2(net_761), .A1(net_759), .ZN(net_274) );
NOR3_X2 inst_44 ( .A1(net_494), .A3(net_374), .A2(net_67), .ZN(v13_D_15) );
NAND2_X2 inst_274 ( .ZN(net_177), .A2(net_176), .A1(net_59) );
NAND3_X2 inst_174 ( .A3(net_727), .A2(net_726), .ZN(net_680), .A1(net_288) );
NAND2_X2 inst_371 ( .ZN(net_444), .A2(net_443), .A1(net_378) );
INV_X4 inst_701 ( .ZN(net_755), .A(net_369) );
INV_X4 inst_662 ( .ZN(net_263), .A(net_209) );
NAND2_X2 inst_314 ( .A1(net_526), .ZN(net_276), .A2(net_216) );
NAND2_X2 inst_435 ( .ZN(net_576), .A1(net_575), .A2(net_516) );
NAND3_X2 inst_164 ( .ZN(net_382), .A3(net_381), .A1(net_362), .A2(net_210) );
OR2_X4 inst_5 ( .ZN(net_451), .A1(net_3), .A2(v4) );
INV_X4 inst_597 ( .ZN(net_674), .A(net_102) );
INV_X2 inst_729 ( .ZN(net_730), .A(net_95) );
NAND3_X2 inst_157 ( .ZN(net_249), .A3(net_248), .A1(net_121), .A2(net_56) );
INV_X4 inst_687 ( .ZN(net_520), .A(net_435) );
AND2_X4 inst_774 ( .A1(net_758), .ZN(net_340), .A2(net_31) );
INV_X4 inst_621 ( .ZN(net_388), .A(net_103) );
NOR2_X2 inst_68 ( .ZN(net_121), .A2(net_58), .A1(net_17) );
NAND2_X4 inst_213 ( .ZN(net_544), .A1(net_157), .A2(net_132) );
INV_X4 inst_604 ( .ZN(net_168), .A(net_142) );
NOR2_X4 inst_53 ( .A2(net_760), .ZN(net_225), .A1(net_87) );
INV_X4 inst_628 ( .ZN(net_148), .A(net_119) );
INV_X2 inst_753 ( .ZN(net_398), .A(net_397) );
NAND2_X4 inst_205 ( .ZN(net_138), .A2(net_137), .A1(net_136) );
NAND2_X2 inst_472 ( .A1(net_643), .ZN(net_637), .A2(net_621) );
NAND2_X2 inst_447 ( .ZN(net_695), .A2(net_563), .A1(net_548) );
NAND2_X2 inst_380 ( .ZN(net_467), .A2(net_401), .A1(net_358) );
NAND2_X2 inst_457 ( .A2(net_571), .A1(net_500), .ZN(v13_D_19) );
INV_X4 inst_651 ( .A(net_643), .ZN(net_183) );
INV_X4 inst_665 ( .ZN(net_347), .A(net_237) );
NAND2_X2 inst_292 ( .A2(net_542), .ZN(net_218), .A1(net_160) );
NAND2_X2 inst_379 ( .ZN(net_757), .A2(net_407), .A1(net_212) );
NAND4_X2 inst_127 ( .ZN(net_727), .A2(net_287), .A4(net_161), .A1(net_70), .A3(net_31) );
NAND3_X2 inst_186 ( .ZN(net_618), .A2(net_556), .A3(net_534), .A1(net_366) );
OR2_X2 inst_17 ( .A2(net_762), .ZN(net_756), .A1(net_178) );
INV_X4 inst_706 ( .ZN(net_457), .A(net_456) );
INV_X1 inst_759 ( .A(net_546), .ZN(net_508) );
NAND2_X2 inst_413 ( .ZN(net_532), .A2(net_423), .A1(net_419) );
NAND3_X4 inst_146 ( .ZN(net_541), .A3(net_445), .A2(net_410), .A1(net_396) );
NAND2_X2 inst_249 ( .ZN(net_736), .A1(net_704), .A2(net_84) );
NAND2_X2 inst_334 ( .ZN(net_449), .A1(net_347), .A2(net_346) );
NAND3_X2 inst_187 ( .ZN(net_723), .A3(net_663), .A1(net_662), .A2(net_282) );
NAND2_X4 inst_206 ( .ZN(net_175), .A1(net_76), .A2(net_31) );
NOR2_X2 inst_122 ( .A1(net_714), .ZN(net_655), .A2(net_654) );
OR2_X2 inst_25 ( .A1(net_758), .ZN(net_511), .A2(net_510) );
NAND2_X2 inst_354 ( .ZN(net_403), .A2(net_399), .A1(net_290) );
NAND2_X2 inst_405 ( .ZN(net_519), .A1(net_502), .A2(net_432) );
NAND2_X1 inst_492 ( .A1(net_542), .ZN(net_208), .A2(net_152) );
NAND2_X2 inst_240 ( .ZN(net_47), .A1(net_46), .A2(net_36) );
NAND2_X2 inst_326 ( .A2(net_526), .ZN(net_329), .A1(net_211) );
NOR2_X2 inst_110 ( .ZN(net_580), .A1(net_578), .A2(net_517) );
INV_X8 inst_518 ( .ZN(net_297), .A(net_124) );
NOR2_X2 inst_74 ( .A2(net_762), .A1(net_346), .ZN(net_130) );
NAND2_X2 inst_288 ( .ZN(net_212), .A1(net_211), .A2(net_210) );
NAND2_X2 inst_396 ( .A1(net_502), .ZN(net_497), .A2(net_379) );
NAND2_X4 inst_229 ( .ZN(net_744), .A1(net_715), .A2(net_600) );
NOR2_X2 inst_99 ( .ZN(net_436), .A1(net_435), .A2(net_310) );
NOR2_X2 inst_69 ( .A1(net_760), .ZN(net_294), .A2(net_55) );
NAND2_X2 inst_373 ( .A1(net_502), .ZN(net_448), .A2(net_336) );
NOR2_X2 inst_82 ( .A1(net_287), .ZN(net_239), .A2(net_167) );
INV_X4 inst_669 ( .ZN(net_391), .A(net_211) );
NOR2_X2 inst_108 ( .ZN(net_555), .A2(net_505), .A1(net_173) );
INV_X4 inst_664 ( .ZN(net_304), .A(net_215) );
INV_X4 inst_595 ( .A(net_453), .ZN(net_74) );
NAND2_X2 inst_283 ( .ZN(net_199), .A1(net_193), .A2(net_133) );
OR2_X2 inst_22 ( .ZN(net_339), .A2(net_338), .A1(net_227) );
NAND2_X2 inst_311 ( .ZN(net_271), .A2(net_188), .A1(net_7) );
NAND2_X2 inst_460 ( .ZN(net_622), .A2(net_604), .A1(net_565) );
NAND2_X2 inst_372 ( .ZN(net_447), .A2(net_446), .A1(net_128) );
NAND3_X2 inst_169 ( .A2(net_545), .ZN(net_427), .A1(net_426), .A3(net_425) );
NAND2_X4 inst_215 ( .ZN(net_731), .A1(net_665), .A2(net_99) );
NAND2_X2 inst_307 ( .ZN(net_261), .A2(net_260), .A1(net_240) );
AND3_X2 inst_767 ( .A2(net_564), .A3(net_542), .ZN(net_505), .A1(net_504) );
INV_X4 inst_638 ( .ZN(net_202), .A(net_150) );
NAND2_X2 inst_421 ( .ZN(net_667), .A1(net_526), .A2(net_509) );
NAND3_X2 inst_161 ( .ZN(net_664), .A1(net_375), .A3(net_213), .A2(net_137) );
INV_X4 inst_560 ( .A(net_137), .ZN(net_45) );
INV_X2 inst_749 ( .ZN(net_454), .A(net_431) );
INV_X4 inst_586 ( .ZN(net_229), .A(net_59) );
INV_X4 inst_702 ( .ZN(net_572), .A(net_456) );
INV_X4 inst_555 ( .ZN(net_375), .A(net_18) );
OR2_X2 inst_16 ( .ZN(net_128), .A1(net_68), .A2(net_31) );
INV_X2 inst_717 ( .ZN(net_12), .A(v6) );
NAND2_X2 inst_276 ( .ZN(net_185), .A1(net_184), .A2(net_101) );
INV_X2 inst_718 ( .ZN(net_3), .A(v5) );
NAND2_X2 inst_431 ( .ZN(net_567), .A2(net_532), .A1(net_402) );
NAND2_X2 inst_348 ( .A1(net_431), .ZN(net_379), .A2(net_280) );
OR3_X2 inst_3 ( .ZN(net_663), .A1(net_292), .A3(net_153), .A2(net_18) );
NAND3_X2 inst_156 ( .A2(net_762), .ZN(net_247), .A3(net_246), .A1(net_245) );
INV_X4 inst_577 ( .A(net_406), .ZN(net_91) );
CLKBUF_X2 inst_802 ( .A(net_782), .Z(net_783) );
INV_X4 inst_566 ( .ZN(net_206), .A(net_131) );
NAND2_X2 inst_296 ( .ZN(net_226), .A2(net_111), .A1(net_73) );
NOR2_X2 inst_91 ( .ZN(net_378), .A2(net_368), .A1(net_316) );
NAND4_X2 inst_132 ( .A2(net_721), .ZN(net_498), .A1(net_462), .A4(net_348), .A3(net_271) );
NAND2_X2 inst_342 ( .A1(net_735), .ZN(net_369), .A2(net_368) );
INV_X4 inst_526 ( .ZN(net_137), .A(v1) );
NOR3_X2 inst_36 ( .ZN(net_293), .A1(net_292), .A2(net_284), .A3(net_51) );
INV_X4 inst_656 ( .ZN(net_341), .A(net_139) );
INV_X4 inst_645 ( .ZN(net_233), .A(net_160) );
NAND2_X2 inst_463 ( .A2(net_592), .A1(net_424), .ZN(v13_D_22) );
INV_X8 inst_503 ( .ZN(net_31), .A(net_1) );
NOR2_X2 inst_96 ( .ZN(net_405), .A1(net_404), .A2(net_272) );
NOR3_X2 inst_45 ( .A2(net_594), .A3(net_555), .A1(net_460), .ZN(v13_D_21) );
NAND2_X2 inst_451 ( .ZN(net_609), .A2(net_579), .A1(net_549) );
NOR2_X2 inst_101 ( .ZN(net_472), .A2(net_395), .A1(net_350) );
NAND2_X2 inst_319 ( .ZN(net_377), .A2(net_211), .A1(net_11) );
NAND2_X2 inst_269 ( .ZN(net_163), .A1(net_162), .A2(net_161) );
NAND2_X2 inst_458 ( .A2(net_758), .A1(net_695), .ZN(net_688) );
NAND2_X2 inst_444 ( .ZN(net_593), .A2(net_566), .A1(net_550) );
NAND2_X2 inst_400 ( .ZN(net_512), .A2(net_439), .A1(net_263) );
CLKBUF_X2 inst_797 ( .A(net_777), .Z(net_778) );
INV_X4 inst_614 ( .ZN(net_107), .A(net_94) );
INV_X4 inst_686 ( .A(net_552), .ZN(net_300) );
INV_X4 inst_649 ( .ZN(net_174), .A(net_130) );
INV_X2 inst_741 ( .A(net_363), .ZN(net_158) );
NAND2_X2 inst_261 ( .ZN(net_703), .A2(net_125), .A1(net_6) );
INV_X8 inst_514 ( .ZN(net_255), .A(net_102) );
MUX2_X1 inst_500 ( .S(net_613), .A(net_609), .B(net_568), .Z(v13_D_7) );
INV_X8 inst_510 ( .ZN(net_93), .A(net_17) );
NAND2_X2 inst_268 ( .ZN(net_159), .A2(net_120), .A1(net_79) );
INV_X4 inst_685 ( .ZN(net_564), .A(net_552) );
NAND2_X2 inst_369 ( .ZN(net_441), .A1(net_360), .A2(net_298) );
INV_X4 inst_550 ( .ZN(net_44), .A(net_14) );
NOR2_X4 inst_63 ( .ZN(net_701), .A1(net_639), .A2(net_631) );
NOR2_X2 inst_119 ( .A1(net_709), .A2(net_654), .ZN(net_651) );
INV_X4 inst_603 ( .ZN(net_169), .A(net_81) );
NAND2_X2 inst_327 ( .A1(net_431), .ZN(net_331), .A2(net_330) );
INV_X4 inst_676 ( .A(net_316), .ZN(net_286) );
NOR2_X2 inst_85 ( .ZN(net_267), .A2(net_265), .A1(net_86) );
NAND2_X2 inst_291 ( .A1(net_762), .ZN(net_569), .A2(net_189) );
NAND2_X2 inst_266 ( .A2(net_758), .ZN(net_292), .A1(net_90) );
AND2_X4 inst_776 ( .ZN(net_724), .A1(net_550), .A2(net_371) );
NAND2_X2 inst_473 ( .ZN(net_638), .A2(net_622), .A1(net_575) );
NAND2_X4 inst_217 ( .ZN(net_729), .A1(net_719), .A2(net_259) );
INV_X4 inst_572 ( .ZN(net_39), .A(net_38) );
INV_X2 inst_742 ( .ZN(net_167), .A(net_166) );
NOR2_X2 inst_77 ( .A1(net_758), .ZN(net_356), .A2(net_70) );
NAND3_X2 inst_171 ( .ZN(net_432), .A2(net_431), .A1(net_352), .A3(net_297) );
INV_X4 inst_691 ( .ZN(net_502), .A(net_385) );
INV_X4 inst_558 ( .A(net_48), .ZN(net_21) );
NAND2_X2 inst_427 ( .ZN(net_558), .A2(net_468), .A1(net_300) );
NAND2_X2 inst_257 ( .ZN(net_659), .A2(net_294), .A1(net_189) );
INV_X4 inst_594 ( .A(net_102), .ZN(net_73) );
NAND3_X4 inst_145 ( .ZN(net_693), .A3(net_295), .A2(net_217), .A1(net_199) );
NAND2_X2 inst_290 ( .ZN(net_217), .A1(net_216), .A2(net_140) );
NAND2_X2 inst_374 ( .ZN(net_450), .A1(net_449), .A2(net_315) );
NAND2_X2 inst_272 ( .ZN(net_170), .A1(net_169), .A2(net_168) );
INV_X8 inst_502 ( .A(net_763), .ZN(net_5) );
NOR2_X2 inst_103 ( .ZN(net_514), .A2(net_436), .A1(net_402) );
NAND2_X2 inst_485 ( .A2(net_647), .A1(net_383), .ZN(v13_D_17) );
AND2_X4 inst_770 ( .A2(net_542), .ZN(net_141), .A1(net_42) );
INV_X4 inst_565 ( .ZN(net_52), .A(net_29) );
NAND2_X2 inst_248 ( .ZN(net_109), .A2(net_41), .A1(v3) );
INV_X4 inst_672 ( .A(net_338), .ZN(net_244) );
INV_X4 inst_622 ( .ZN(net_230), .A(net_104) );
NAND4_X2 inst_138 ( .ZN(net_711), .A4(net_671), .A1(net_670), .A2(net_569), .A3(net_528) );
NAND2_X2 inst_389 ( .ZN(net_486), .A2(net_367), .A1(net_356) );
CLKBUF_X2 inst_789 ( .A(net_769), .Z(net_770) );
NAND2_X2 inst_357 ( .ZN(net_748), .A2(net_258), .A1(net_202) );
NAND2_X2 inst_409 ( .A1(net_546), .ZN(net_525), .A2(net_429) );
NAND3_X2 inst_180 ( .A3(net_678), .A1(net_677), .ZN(net_661), .A2(net_302) );
INV_X4 inst_703 ( .ZN(net_546), .A(net_402) );
NOR3_X4 inst_33 ( .A3(net_724), .A1(net_723), .ZN(net_690), .A2(net_524) );
NAND2_X2 inst_312 ( .ZN(net_273), .A1(net_272), .A2(net_268) );
INV_X4 inst_660 ( .ZN(net_251), .A(net_202) );
INV_X2 inst_731 ( .ZN(net_355), .A(net_154) );
INV_X4 inst_609 ( .ZN(net_139), .A(net_131) );
INV_X8 inst_517 ( .ZN(net_643), .A(net_613) );
NAND2_X2 inst_309 ( .ZN(net_733), .A2(net_159), .A1(net_122) );
NAND2_X4 inst_232 ( .A2(net_758), .A1(net_694), .ZN(net_666) );
NAND2_X2 inst_347 ( .ZN(net_753), .A1(net_375), .A2(net_278) );
AND3_X2 inst_768 ( .ZN(net_587), .A1(net_586), .A2(net_552), .A3(net_475) );
CLKBUF_X2 inst_795 ( .A(net_775), .Z(net_776) );
INV_X4 inst_663 ( .ZN(net_214), .A(net_213) );
NAND2_X2 inst_301 ( .ZN(net_241), .A1(net_240), .A2(net_98) );
NAND2_X2 inst_363 ( .A1(net_758), .ZN(net_423), .A2(net_351) );
INV_X16 inst_755 ( .ZN(net_102), .A(net_93) );
NOR4_X2 inst_27 ( .ZN(net_696), .A1(net_391), .A3(net_375), .A2(net_292), .A4(net_198) );
NAND2_X2 inst_247 ( .A1(net_762), .A2(net_718), .ZN(net_69) );
NAND2_X2 inst_297 ( .A2(net_703), .ZN(net_702), .A1(net_187) );
NAND2_X2 inst_403 ( .ZN(net_516), .A2(net_438), .A1(net_339) );
NAND2_X2 inst_302 ( .A1(net_526), .A2(net_281), .ZN(net_250) );
NAND2_X2 inst_310 ( .ZN(net_270), .A1(net_269), .A2(net_268) );
NAND2_X2 inst_322 ( .A2(net_758), .ZN(net_446), .A1(net_211) );
INV_X4 inst_673 ( .ZN(net_306), .A(net_251) );
NAND2_X2 inst_253 ( .ZN(net_111), .A1(net_82), .A2(net_33) );
NAND2_X4 inst_211 ( .ZN(net_362), .A2(net_132), .A1(net_70) );
INV_X4 inst_619 ( .ZN(net_269), .A(net_128) );
INV_X4 inst_681 ( .ZN(net_435), .A(net_211) );
NAND3_X2 inst_162 ( .ZN(net_328), .A3(net_246), .A1(net_192), .A2(net_137) );
INV_X4 inst_589 ( .A(net_113), .ZN(net_75) );
INV_X4 inst_561 ( .A(net_303), .ZN(net_113) );
CLKBUF_X2 inst_794 ( .A(net_766), .Z(net_775) );
NAND2_X2 inst_412 ( .ZN(net_531), .A1(net_464), .A2(net_241) );
NAND2_X2 inst_449 ( .A1(net_643), .ZN(net_605), .A2(net_573) );
INV_X4 inst_639 ( .ZN(net_268), .A(net_260) );
NAND3_X2 inst_155 ( .ZN(net_243), .A3(net_145), .A2(net_78), .A1(net_63) );
NAND2_X2 inst_464 ( .ZN(net_625), .A2(net_616), .A1(net_611) );
INV_X4 inst_602 ( .A(net_94), .ZN(net_80) );
NOR2_X4 inst_59 ( .A1(net_762), .ZN(net_349), .A2(net_106) );
NAND4_X2 inst_135 ( .A2(net_643), .ZN(net_571), .A4(net_488), .A1(net_416), .A3(net_229) );
NAND2_X2 inst_341 ( .ZN(net_367), .A2(net_252), .A1(net_205) );
NAND2_X4 inst_196 ( .A1(net_55), .ZN(net_43), .A2(net_42) );
INV_X4 inst_532 ( .ZN(net_13), .A(net_3) );
NOR2_X4 inst_55 ( .A1(net_246), .ZN(net_157), .A2(net_131) );
NOR3_X2 inst_37 ( .A2(net_594), .A1(net_231), .A3(net_146), .ZN(v13_D_20) );
INV_X4 inst_641 ( .ZN(net_419), .A(net_156) );
MUX2_X2 inst_498 ( .S(net_762), .A(net_303), .Z(net_285), .B(net_284) );
INV_X2 inst_740 ( .A(net_363), .ZN(net_151) );
INV_X4 inst_684 ( .A(net_385), .ZN(net_299) );
NAND2_X2 inst_264 ( .ZN(net_692), .A1(net_142), .A2(net_141) );
NOR2_X2 inst_84 ( .ZN(net_256), .A1(net_234), .A2(net_131) );
INV_X2 inst_723 ( .A(net_762), .ZN(net_732) );
NAND3_X2 inst_173 ( .A3(net_758), .A1(net_685), .ZN(net_677), .A2(net_147) );
NAND2_X2 inst_298 ( .ZN(net_750), .A2(net_738), .A1(net_166) );
NAND2_X2 inst_303 ( .A1(net_526), .ZN(net_252), .A2(net_72) );
INV_X4 inst_611 ( .ZN(net_120), .A(net_99) );
NAND2_X4 inst_224 ( .A1(net_734), .ZN(net_669), .A2(net_535) );
NOR3_X2 inst_42 ( .ZN(net_547), .A2(net_546), .A3(net_545), .A1(net_472) );
NAND2_X2 inst_287 ( .A2(net_399), .ZN(net_308), .A1(net_269) );
NAND2_X2 inst_323 ( .ZN(net_742), .A1(net_321), .A2(net_320) );
INV_X4 inst_618 ( .ZN(net_326), .A(net_36) );
NAND2_X2 inst_426 ( .ZN(net_557), .A1(net_510), .A2(net_471) );
INV_X4 inst_588 ( .ZN(net_65), .A(net_64) );
INV_X4 inst_648 ( .ZN(net_215), .A(net_171) );
NAND2_X2 inst_350 ( .A2(net_717), .ZN(net_387), .A1(net_359) );
NAND2_X4 inst_231 ( .A2(net_689), .A1(net_688), .ZN(net_684) );
NAND2_X2 inst_270 ( .ZN(net_164), .A2(net_162), .A1(net_83) );
NAND2_X2 inst_474 ( .ZN(net_640), .A2(net_630), .A1(net_508) );
CLKBUF_X2 inst_793 ( .A(net_773), .Z(net_774) );
AND3_X4 inst_766 ( .ZN(net_681), .A3(net_248), .A2(net_154), .A1(net_35) );
INV_X4 inst_715 ( .ZN(net_714), .A(net_650) );
NOR4_X2 inst_26 ( .ZN(net_455), .A2(net_454), .A3(net_453), .A1(net_425), .A4(net_404) );
NAND2_X2 inst_437 ( .ZN(net_579), .A1(net_578), .A2(net_515) );
NAND2_X1 inst_490 ( .A1(net_346), .A2(net_135), .ZN(net_129) );
CLKBUF_X2 inst_801 ( .A(net_781), .Z(net_782) );
INV_X4 inst_626 ( .ZN(net_253), .A(net_116) );
INV_X4 inst_692 ( .ZN(net_578), .A(net_358) );
NOR2_X2 inst_70 ( .A1(net_732), .ZN(net_85), .A2(net_17) );
NAND4_X2 inst_129 ( .A4(net_340), .ZN(net_283), .A1(net_91), .A3(net_45), .A2(net_37) );
NAND3_X2 inst_189 ( .A3(net_637), .A1(net_595), .A2(net_459), .ZN(v13_D_8) );
OR2_X4 inst_11 ( .A1(net_721), .ZN(net_179), .A2(net_137) );
INV_X4 inst_631 ( .A(net_139), .ZN(net_126) );
NAND3_X2 inst_188 ( .A2(net_634), .A3(net_629), .A1(net_593), .ZN(v13_D_14) );
OR2_X2 inst_14 ( .A1(net_31), .ZN(net_25), .A2(net_24) );
NAND2_X2 inst_475 ( .A1(net_643), .ZN(net_641), .A2(net_632) );
NAND2_X2 inst_441 ( .ZN(net_588), .A1(net_525), .A2(net_484) );
NOR3_X4 inst_31 ( .ZN(net_728), .A3(net_683), .A1(net_682), .A2(net_225) );
INV_X4 inst_528 ( .A(net_759), .ZN(net_1) );
NAND2_X2 inst_252 ( .ZN(net_101), .A2(net_52), .A1(net_23) );
CLKBUF_X2 inst_798 ( .A(net_778), .Z(net_779) );
NOR2_X4 inst_62 ( .A1(net_728), .ZN(net_639), .A2(net_545) );
AND2_X4 inst_777 ( .ZN(net_536), .A2(net_486), .A1(net_307) );
INV_X4 inst_557 ( .A(net_115), .ZN(net_38) );
NAND2_X2 inst_251 ( .ZN(net_721), .A2(net_193), .A1(net_93) );
NAND2_X2 inst_352 ( .A1(net_552), .ZN(net_394), .A2(net_393) );
INV_X4 inst_575 ( .ZN(net_66), .A(net_44) );
NAND2_X2 inst_398 ( .ZN(net_507), .A2(net_382), .A1(net_158) );
NAND2_X2 inst_286 ( .ZN(net_207), .A1(net_206), .A2(net_144) );
NAND2_X2 inst_436 ( .A1(net_578), .ZN(net_577), .A2(net_512) );
NAND2_X2 inst_484 ( .A2(net_713), .A1(net_712), .ZN(net_648) );
INV_X4 inst_627 ( .ZN(net_245), .A(net_88) );
NAND2_X2 inst_300 ( .ZN(net_685), .A1(net_179), .A2(net_165) );
NOR2_X2 inst_102 ( .ZN(net_668), .A2(net_384), .A1(net_319) );
NOR3_X4 inst_32 ( .ZN(net_709), .A1(net_636), .A3(net_389), .A2(net_305) );
NAND2_X2 inst_344 ( .A2(net_692), .A1(net_691), .ZN(net_676) );
NAND2_X2 inst_428 ( .ZN(net_559), .A1(net_511), .A2(net_357) );
NAND2_X2 inst_446 ( .ZN(net_597), .A1(net_596), .A2(net_538) );
NAND2_X2 inst_364 ( .ZN(net_430), .A1(net_429), .A2(net_412) );
NAND3_X4 inst_144 ( .A1(net_731), .ZN(net_410), .A3(net_131), .A2(net_78) );
INV_X4 inst_629 ( .ZN(net_123), .A(net_106) );
NAND2_X4 inst_195 ( .ZN(net_287), .A2(v4), .A1(v5) );
NAND2_X2 inst_407 ( .A1(net_693), .ZN(net_670), .A2(net_106) );
CLKBUF_X2 inst_791 ( .A(net_767), .Z(net_772) );
INV_X4 inst_623 ( .A(net_162), .ZN(net_105) );
NAND2_X2 inst_411 ( .A1(net_550), .ZN(net_529), .A2(net_420) );
NOR2_X2 inst_97 ( .ZN(net_408), .A2(net_254), .A1(net_135) );
INV_X4 inst_616 ( .ZN(net_504), .A(net_97) );
AND2_X4 inst_775 ( .ZN(net_683), .A1(net_176), .A2(net_142) );
NOR2_X1 inst_124 ( .ZN(net_738), .A1(net_190), .A2(net_17) );
INV_X4 inst_533 ( .A(net_12), .ZN(net_6) );
INV_X4 inst_620 ( .ZN(net_613), .A(net_501) );
INV_X4 inst_652 ( .A(net_762), .ZN(net_237) );
INV_X4 inst_680 ( .A(net_431), .ZN(net_364) );
CLKBUF_X2 inst_785 ( .A(net_765), .Z(net_766) );
INV_X2 inst_737 ( .A(net_425), .ZN(net_143) );
NAND4_X2 inst_137 ( .A2(net_659), .A1(net_658), .ZN(net_581), .A4(net_328), .A3(net_247) );
INV_X4 inst_677 ( .A(net_347), .ZN(net_290) );
NAND2_X2 inst_425 ( .ZN(net_556), .A1(net_542), .A2(net_465) );
INV_X4 inst_545 ( .A(net_762), .ZN(net_55) );
NAND4_X2 inst_130 ( .A2(net_758), .ZN(net_409), .A4(net_406), .A3(net_368), .A1(net_203) );
INV_X2 inst_722 ( .A(net_38), .ZN(net_34) );
NAND2_X4 inst_227 ( .A1(net_660), .ZN(net_601), .A2(net_600) );
NAND2_X2 inst_399 ( .ZN(net_509), .A2(net_392), .A1(net_335) );
DFFR_X2 inst_760 ( .QN(net_763), .RN(net_657), .D(net_651), .CK(net_780) );
INV_X2 inst_746 ( .A(net_308), .ZN(net_257) );
INV_X4 inst_527 ( .ZN(net_54), .A(v2) );
NAND2_X4 inst_226 ( .A1(net_661), .ZN(net_591), .A2(net_113) );
NAND3_X2 inst_176 ( .ZN(net_533), .A1(net_440), .A3(net_269), .A2(net_75) );
NOR2_X4 inst_58 ( .A1(net_227), .ZN(net_180), .A2(net_109) );
NAND2_X2 inst_414 ( .ZN(net_634), .A1(net_492), .A2(net_482) );
NOR2_X2 inst_87 ( .ZN(net_305), .A2(net_304), .A1(net_80) );
NOR2_X4 inst_61 ( .A2(net_681), .A1(net_680), .ZN(net_560) );
INV_X4 inst_562 ( .ZN(net_84), .A(net_26) );
INV_X4 inst_531 ( .A(net_46), .ZN(net_2) );
NAND2_X4 inst_203 ( .A1(net_762), .ZN(net_152), .A2(net_106) );
NAND2_X4 inst_212 ( .ZN(net_745), .A1(net_171), .A2(net_138) );
MUX2_X2 inst_499 ( .A(net_388), .B(net_356), .Z(net_353), .S(net_211) );
NAND2_X2 inst_335 ( .ZN(net_726), .A1(net_705), .A2(net_504) );
INV_X4 inst_674 ( .ZN(net_359), .A(net_314) );
CLKBUF_X2 inst_800 ( .A(net_766), .Z(net_781) );
NAND2_X2 inst_466 ( .ZN(net_627), .A2(net_618), .A1(net_572) );
AND2_X2 inst_780 ( .ZN(net_350), .A2(net_349), .A1(net_38) );
INV_X4 inst_658 ( .ZN(net_460), .A(net_200) );
OR2_X4 inst_10 ( .A2(net_762), .ZN(net_224), .A1(net_115) );
OR3_X2 inst_4 ( .ZN(net_357), .A2(net_356), .A3(net_355), .A1(net_13) );
NAND2_X2 inst_456 ( .ZN(net_617), .A2(net_570), .A1(net_504) );
INV_X4 inst_581 ( .A(net_545), .ZN(net_453) );
INV_X4 inst_600 ( .ZN(net_281), .A(net_77) );
NOR3_X4 inst_28 ( .ZN(net_754), .A3(net_718), .A1(net_419), .A2(net_106) );
NAND2_X2 inst_275 ( .A1(net_504), .ZN(net_354), .A2(net_178) );
NOR2_X2 inst_117 ( .A2(net_608), .A1(net_469), .ZN(v13_D_9) );
NAND2_X2 inst_438 ( .ZN(net_582), .A2(net_518), .A1(net_386) );
MUX2_X1 inst_501 ( .A(net_646), .B(net_602), .S(net_385), .Z(v13_D_12) );
NOR2_X4 inst_49 ( .ZN(net_346), .A1(net_54), .A2(net_53) );
NAND2_X4 inst_204 ( .A2(net_760), .ZN(net_171), .A1(net_36) );
INV_X4 inst_587 ( .ZN(net_246), .A(net_70) );
INV_X4 inst_666 ( .ZN(net_431), .A(net_139) );
NAND3_X2 inst_154 ( .ZN(net_232), .A2(net_176), .A3(net_103), .A1(net_10) );
INV_X4 inst_592 ( .ZN(net_71), .A(net_70) );
INV_X4 inst_546 ( .A(net_758), .ZN(net_11) );
NAND2_X2 inst_324 ( .ZN(net_323), .A1(net_322), .A2(net_320) );
NAND2_X2 inst_465 ( .ZN(net_626), .A2(net_617), .A1(net_434) );
INV_X4 inst_704 ( .ZN(net_491), .A(net_385) );
NOR2_X2 inst_109 ( .ZN(net_561), .A2(net_476), .A1(net_311) );
NOR2_X4 inst_54 ( .A2(net_760), .ZN(net_154), .A1(net_93) );
INV_X4 inst_693 ( .ZN(net_414), .A(net_358) );
INV_X4 inst_570 ( .A(net_758), .ZN(net_545) );
NAND2_X2 inst_390 ( .ZN(net_752), .A2(net_411), .A1(net_363) );
INV_X4 inst_640 ( .ZN(net_200), .A(net_153) );
NOR3_X2 inst_43 ( .A2(net_755), .A1(net_754), .A3(net_679), .ZN(net_563) );
NAND2_X2 inst_359 ( .ZN(net_417), .A2(net_327), .A1(net_266) );
DFFR_X1 inst_765 ( .QN(net_758), .RN(net_657), .D(net_648), .CK(net_784) );
NAND2_X2 inst_256 ( .ZN(net_665), .A1(net_81), .A2(net_68) );
INV_X4 inst_694 ( .ZN(net_360), .A(net_359) );
NOR2_X2 inst_94 ( .ZN(net_473), .A2(net_390), .A1(net_236) );
NAND2_X2 inst_454 ( .ZN(net_614), .A1(net_613), .A2(net_588) );
INV_X4 inst_630 ( .ZN(net_368), .A(net_106) );
NAND2_X2 inst_375 ( .ZN(net_459), .A1(net_426), .A2(net_325) );
NAND2_X2 inst_401 ( .A1(net_569), .ZN(net_513), .A2(net_442) );
NAND2_X2 inst_262 ( .ZN(net_133), .A1(net_132), .A2(net_15) );
INV_X8 inst_512 ( .ZN(net_132), .A(net_43) );
NAND2_X2 inst_355 ( .A1(net_733), .ZN(net_671), .A2(net_406) );
NAND2_X2 inst_243 ( .ZN(net_284), .A1(net_56), .A2(net_10) );
NAND2_X2 inst_285 ( .A1(net_499), .ZN(net_302), .A2(net_121) );
INV_X4 inst_591 ( .ZN(net_673), .A(net_545) );
NAND2_X2 inst_424 ( .ZN(net_554), .A1(net_520), .A2(net_470) );
AND2_X2 inst_782 ( .ZN(net_463), .A1(net_462), .A2(net_323) );
NAND2_X1 inst_497 ( .ZN(net_602), .A2(net_553), .A1(net_377) );
NAND2_X4 inst_218 ( .ZN(net_510), .A1(net_286), .A2(net_121) );
OR2_X2 inst_15 ( .A1(net_758), .ZN(net_86), .A2(net_31) );
INV_X1 inst_757 ( .ZN(net_657), .A(blif_reset_net) );
INV_X4 inst_647 ( .ZN(net_213), .A(net_197) );
NAND2_X2 inst_343 ( .A1(net_435), .ZN(net_370), .A2(net_304) );
OR2_X4 inst_6 ( .A2(net_760), .ZN(net_227), .A1(net_42) );
NAND3_X1 inst_194 ( .A2(net_634), .A1(net_605), .A3(net_596), .ZN(v13_D_11) );
INV_X4 inst_543 ( .ZN(net_115), .A(net_8) );
NAND2_X2 inst_337 ( .A1(net_716), .ZN(net_351), .A2(net_201) );
CLKBUF_X2 inst_787 ( .A(net_767), .Z(net_768) );
INV_X4 inst_670 ( .ZN(net_390), .A(net_320) );
NOR2_X2 inst_123 ( .A1(net_687), .ZN(net_656), .A2(net_654) );
INV_X8 inst_509 ( .ZN(net_70), .A(net_57) );
NAND2_X2 inst_299 ( .ZN(net_722), .A1(net_197), .A2(net_172) );
INV_X4 inst_699 ( .ZN(net_481), .A(net_414) );
NAND2_X2 inst_418 ( .ZN(net_540), .A1(net_480), .A2(net_276) );
NAND2_X2 inst_476 ( .ZN(net_642), .A2(net_625), .A1(net_614) );
NOR2_X2 inst_118 ( .A2(net_624), .A1(net_181), .ZN(v13_D_23) );
NOR2_X2 inst_86 ( .ZN(net_697), .A1(net_303), .A2(net_302) );
NAND3_X2 inst_153 ( .ZN(net_231), .A1(net_230), .A2(net_229), .A3(net_62) );
OR2_X2 inst_20 ( .A1(net_399), .A2(net_349), .ZN(net_333) );
NAND2_X2 inst_442 ( .ZN(net_720), .A2(net_554), .A1(net_385) );
INV_X4 inst_613 ( .ZN(net_127), .A(net_61) );
NOR3_X2 inst_38 ( .ZN(net_679), .A1(net_354), .A2(net_287), .A3(net_196) );
INV_X4 inst_714 ( .ZN(net_687), .A(net_649) );
NAND2_X2 inst_381 ( .ZN(net_468), .A1(net_387), .A2(net_343) );
INV_X2 inst_726 ( .A(net_102), .ZN(net_83) );
NAND2_X2 inst_295 ( .ZN(net_279), .A1(net_224), .A2(net_223) );
NAND2_X2 inst_349 ( .ZN(net_386), .A1(net_385), .A2(net_242) );
NAND2_X2 inst_483 ( .ZN(net_647), .A2(net_642), .A1(net_143) );
INV_X4 inst_576 ( .ZN(net_64), .A(net_45) );
NAND2_X4 inst_209 ( .A2(net_749), .ZN(net_192), .A1(net_118) );
NAND2_X2 inst_259 ( .ZN(net_749), .A1(net_125), .A2(net_94) );
NOR3_X2 inst_40 ( .A1(net_520), .ZN(net_476), .A3(net_388), .A2(net_119) );
NAND2_X2 inst_320 ( .ZN(net_313), .A1(net_224), .A2(net_218) );
NAND3_X2 inst_167 ( .ZN(net_413), .A3(net_412), .A2(net_344), .A1(net_149) );
INV_X4 inst_607 ( .A(net_210), .ZN(net_103) );
NAND2_X2 inst_246 ( .A2(net_761), .ZN(net_61), .A1(net_27) );
INV_X16 inst_756 ( .ZN(net_526), .A(net_152) );
INV_X4 inst_635 ( .ZN(net_535), .A(net_363) );
NOR2_X2 inst_95 ( .ZN(net_395), .A1(net_364), .A2(net_107) );
INV_X4 inst_705 ( .ZN(net_611), .A(net_456) );
OR3_X2 inst_1 ( .ZN(net_704), .A2(net_137), .A1(net_31), .A3(net_17) );
NOR2_X2 inst_72 ( .ZN(net_145), .A2(net_87), .A1(net_71) );
INV_X8 inst_519 ( .A(net_255), .ZN(net_211) );
NAND2_X2 inst_439 ( .ZN(net_583), .A1(net_564), .A2(net_521) );
NAND2_X2 inst_331 ( .ZN(net_342), .A1(net_341), .A2(net_340) );
INV_X4 inst_582 ( .ZN(net_117), .A(net_52) );
INV_X2 inst_735 ( .ZN(net_153), .A(net_120) );
INV_X4 inst_683 ( .A(net_314), .ZN(net_296) );
NOR2_X2 inst_115 ( .ZN(net_615), .A2(net_587), .A1(net_239) );
NAND2_X2 inst_235 ( .A2(net_760), .A1(net_42), .ZN(net_19) );
INV_X2 inst_750 ( .A(net_404), .ZN(net_318) );
NAND2_X4 inst_210 ( .ZN(net_739), .A1(net_686), .A2(net_193) );
NAND2_X2 inst_317 ( .ZN(net_298), .A2(net_297), .A1(net_214) );
INV_X4 inst_667 ( .ZN(net_236), .A(net_139) );
NAND2_X2 inst_278 ( .ZN(net_188), .A2(net_187), .A1(net_116) );
NAND2_X2 inst_467 ( .ZN(net_628), .A2(net_607), .A1(net_453) );
DFFR_X2 inst_761 ( .QN(net_759), .RN(net_657), .D(net_652), .CK(net_776) );
NAND2_X2 inst_239 ( .ZN(net_41), .A2(net_24), .A1(v0) );
NOR2_X2 inst_105 ( .ZN(net_524), .A2(net_463), .A1(net_402) );
NAND2_X1 inst_488 ( .ZN(net_220), .A2(net_47), .A1(net_29) );
NAND2_X2 inst_387 ( .ZN(net_484), .A1(net_385), .A2(net_370) );
INV_X2 inst_725 ( .ZN(net_67), .A(net_66) );
INV_X4 inst_593 ( .ZN(net_443), .A(net_72) );
NAND3_X2 inst_175 ( .ZN(net_477), .A1(net_409), .A3(net_329), .A2(net_177) );
INV_X2 inst_747 ( .ZN(net_264), .A(net_263) );
NAND2_X2 inst_254 ( .ZN(net_698), .A2(net_322), .A1(net_36) );
INV_X4 inst_654 ( .ZN(net_344), .A(net_175) );
INV_X4 inst_625 ( .ZN(net_260), .A(net_168) );
NAND2_X4 inst_225 ( .A2(net_742), .A1(net_741), .ZN(net_715) );
INV_X4 inst_601 ( .ZN(net_330), .A(net_189) );
NAND4_X2 inst_133 ( .A1(net_578), .ZN(net_500), .A2(net_499), .A4(net_346), .A3(net_318) );
INV_X8 inst_508 ( .ZN(net_161), .A(net_19) );
INV_X4 inst_568 ( .ZN(net_59), .A(net_10) );
NOR2_X2 inst_112 ( .A2(net_530), .A1(net_489), .ZN(v13_D_16) );
INV_X4 inst_523 ( .A(net_718), .ZN(net_717) );
NAND2_X2 inst_365 ( .ZN(net_734), .A2(net_361), .A1(net_194) );
DFFR_X2 inst_764 ( .QN(net_760), .RN(net_657), .D(net_656), .CK(net_774) );
NOR2_X2 inst_67 ( .ZN(net_189), .A1(net_57), .A2(net_17) );
NAND3_X2 inst_181 ( .ZN(net_565), .A2(net_564), .A3(net_461), .A1(net_74) );
NAND2_X2 inst_305 ( .A2(net_322), .ZN(net_258), .A1(net_233) );
NAND2_X2 inst_479 ( .ZN(net_646), .A2(net_628), .A1(net_430) );
NOR3_X4 inst_29 ( .ZN(net_295), .A2(net_294), .A1(net_180), .A3(net_85) );
AND2_X4 inst_771 ( .A2(net_760), .ZN(net_142), .A1(net_57) );
NAND2_X2 inst_391 ( .ZN(net_487), .A2(net_365), .A1(net_261) );
INV_X4 inst_661 ( .ZN(net_338), .A(net_265) );
INV_X4 inst_590 ( .A(net_545), .ZN(net_501) );
INV_X4 inst_713 ( .ZN(net_598), .A(net_581) );
NAND2_X4 inst_202 ( .ZN(net_187), .A1(net_135), .A2(net_31) );
NAND4_X4 inst_126 ( .ZN(net_672), .A2(net_598), .A1(net_560), .A4(net_232), .A3(net_228) );
NAND2_X2 inst_480 ( .ZN(net_712), .A1(net_684), .A2(CLR) );
INV_X4 inst_634 ( .ZN(net_334), .A(net_121) );
NAND2_X2 inst_419 ( .ZN(net_548), .A2(net_498), .A1(net_139) );
NAND2_X2 inst_477 ( .ZN(net_644), .A1(net_643), .A2(net_633) );
INV_X4 inst_646 ( .A(net_297), .ZN(net_209) );
INV_X4 inst_564 ( .ZN(net_87), .A(net_27) );
INV_X4 inst_538 ( .A(net_5), .ZN(net_4) );
NAND2_X2 inst_423 ( .A1(net_757), .ZN(net_741), .A2(net_535) );
INV_X2 inst_739 ( .A(net_762), .ZN(net_147) );
NOR3_X2 inst_35 ( .ZN(net_675), .A3(net_46), .A2(net_32), .A1(net_25) );
NAND2_X2 inst_382 ( .ZN(net_470), .A1(net_449), .A2(net_403) );
NOR2_X4 inst_48 ( .A2(net_760), .A1(net_31), .ZN(net_26) );
NAND2_X2 inst_358 ( .ZN(net_415), .A2(net_337), .A1(net_308) );
NOR2_X4 inst_46 ( .A1(net_762), .A2(net_761), .ZN(net_36) );
NAND4_X2 inst_136 ( .ZN(net_573), .A1(net_572), .A2(net_497), .A4(net_496), .A3(net_208) );
NOR3_X4 inst_30 ( .ZN(net_699), .A3(net_541), .A2(net_522), .A1(net_421) );
NAND2_X2 inst_330 ( .ZN(net_397), .A1(net_211), .A2(net_168) );
INV_X4 inst_610 ( .A(net_284), .ZN(net_89) );
NAND2_X4 inst_233 ( .ZN(net_743), .A2(net_673), .A1(net_672) );
INV_X4 inst_710 ( .ZN(net_478), .A(net_428) );
NAND3_X2 inst_165 ( .ZN(net_383), .A2(net_340), .A3(net_245), .A1(net_244) );
CLKBUF_X2 inst_796 ( .A(net_775), .Z(net_777) );
NAND2_X2 inst_271 ( .A1(net_542), .A2(net_176), .ZN(net_165) );
NAND2_X2 inst_443 ( .ZN(net_589), .A2(net_559), .A1(net_108) );
INV_X4 inst_633 ( .ZN(net_160), .A(net_70) );
NOR3_X2 inst_34 ( .A2(net_190), .ZN(net_63), .A1(net_62), .A3(net_8) );
OR2_X4 inst_12 ( .ZN(net_678), .A1(net_363), .A2(net_362) );
INV_X4 inst_529 ( .ZN(net_654), .A(CLR) );
INV_X4 inst_524 ( .ZN(net_32), .A(v3) );
NOR2_X4 inst_56 ( .ZN(net_166), .A2(net_117), .A1(net_97) );
NOR2_X2 inst_71 ( .ZN(net_248), .A2(net_117), .A1(net_106) );
INV_X4 inst_655 ( .ZN(net_320), .A(net_196) );
NAND2_X2 inst_308 ( .ZN(net_266), .A2(net_265), .A1(net_139) );
NOR2_X2 inst_104 ( .ZN(net_517), .A1(net_437), .A2(net_267) );
NAND2_X2 inst_448 ( .ZN(net_604), .A1(net_603), .A2(net_557) );
NOR2_X4 inst_60 ( .ZN(net_528), .A2(net_458), .A1(net_256) );
NAND2_X2 inst_455 ( .ZN(net_616), .A2(net_567), .A1(net_270) );
NAND3_X2 inst_168 ( .ZN(net_424), .A3(net_264), .A1(net_230), .A2(net_183) );
INV_X4 inst_695 ( .ZN(net_603), .A(net_564) );
INV_X2 inst_730 ( .ZN(net_96), .A(net_95) );
INV_X2 inst_727 ( .ZN(net_184), .A(net_136) );
INV_X4 inst_675 ( .A(net_263), .ZN(net_262) );
NAND2_X2 inst_384 ( .ZN(net_474), .A2(net_473), .A1(net_65) );
INV_X1 inst_758 ( .A(net_135), .ZN(net_51) );
NAND2_X2 inst_321 ( .ZN(net_315), .A1(net_314), .A2(net_279) );
NAND2_X1 inst_496 ( .ZN(net_483), .A1(net_454), .A2(net_372) );
INV_X4 inst_653 ( .A(net_334), .ZN(net_324) );
INV_X4 inst_608 ( .ZN(net_499), .A(net_86) );
NAND2_X2 inst_336 ( .A1(net_702), .ZN(net_348), .A2(net_137) );
INV_X4 inst_563 ( .ZN(net_406), .A(net_56) );
INV_X4 inst_583 ( .ZN(net_125), .A(net_87) );
INV_X4 inst_580 ( .ZN(net_322), .A(net_49) );
NAND3_X2 inst_170 ( .ZN(net_428), .A3(net_243), .A1(net_195), .A2(net_163) );
NAND2_X2 inst_258 ( .ZN(net_381), .A1(net_246), .A2(net_121) );
NAND2_X2 inst_376 ( .ZN(net_461), .A1(net_460), .A2(net_331) );
NAND2_X4 inst_199 ( .A1(net_762), .ZN(net_95), .A2(net_48) );
NOR3_X2 inst_41 ( .ZN(net_543), .A1(net_542), .A2(net_435), .A3(net_433) );
INV_X8 inst_511 ( .ZN(net_135), .A(net_40) );
NAND3_X4 inst_143 ( .A2(net_740), .A1(net_739), .ZN(net_708), .A3(net_182) );
INV_X4 inst_708 ( .ZN(net_464), .A(net_402) );
NAND3_X2 inst_152 ( .ZN(net_191), .A2(net_190), .A3(net_189), .A1(net_31) );
NAND2_X2 inst_265 ( .ZN(net_144), .A1(net_132), .A2(net_20) );
NAND2_X2 inst_482 ( .A2(net_644), .A1(net_576), .ZN(v13_D_6) );
NAND2_X2 inst_468 ( .A1(net_643), .ZN(net_629), .A2(net_619) );
INV_X4 inst_682 ( .ZN(net_552), .A(net_347) );
INV_X2 inst_736 ( .ZN(net_223), .A(net_162) );
INV_X4 inst_544 ( .A(net_134), .ZN(net_18) );
NAND2_X2 inst_238 ( .A2(net_761), .ZN(net_30), .A1(net_9) );
INV_X4 inst_540 ( .ZN(net_22), .A(net_6) );
INV_X4 inst_539 ( .ZN(net_42), .A(net_5) );
NAND2_X2 inst_429 ( .ZN(net_562), .A2(net_503), .A1(net_427) );
INV_X2 inst_724 ( .A(net_161), .ZN(net_72) );
NAND2_X2 inst_404 ( .ZN(net_518), .A2(net_447), .A1(net_64) );
NAND3_X2 inst_178 ( .ZN(net_660), .A3(net_596), .A2(net_544), .A1(net_507) );
NOR2_X2 inst_89 ( .A2(net_362), .ZN(net_311), .A1(net_39) );
NOR2_X2 inst_111 ( .ZN(net_584), .A1(net_514), .A2(net_422) );
NOR2_X2 inst_66 ( .A1(net_761), .ZN(net_718), .A2(net_5) );
NAND2_X2 inst_388 ( .A1(net_603), .ZN(net_485), .A2(net_321) );
INV_X2 inst_734 ( .A(net_326), .ZN(net_112) );
OR2_X4 inst_7 ( .A1(net_760), .A2(net_287), .ZN(net_16) );
NAND3_X2 inst_182 ( .ZN(net_713), .A1(net_499), .A3(net_417), .A2(CLR) );
NAND2_X2 inst_392 ( .ZN(net_488), .A2(net_413), .A1(net_289) );
NOR2_X2 inst_120 ( .A1(net_701), .A2(net_654), .ZN(net_652) );
NAND2_X2 inst_273 ( .A1(net_287), .ZN(net_172), .A2(net_100) );
CLKBUF_X2 inst_788 ( .A(net_768), .Z(net_769) );
NAND2_X2 inst_294 ( .ZN(net_222), .A2(net_220), .A1(net_141) );
NAND2_X4 inst_222 ( .A2(net_762), .A1(net_676), .ZN(net_479) );
NAND2_X2 inst_284 ( .A1(net_762), .ZN(net_201), .A2(net_131) );
NAND2_X1 inst_489 ( .A1(net_762), .ZN(net_122), .A2(net_121) );
NAND3_X2 inst_192 ( .A1(net_641), .A2(net_640), .A3(net_620), .ZN(v13_D_13) );
NAND2_X2 inst_280 ( .ZN(net_194), .A2(net_136), .A1(net_132) );
DFFR_X2 inst_763 ( .QN(net_761), .RN(net_657), .D(net_655), .CK(net_771) );
NAND2_X2 inst_366 ( .A1(net_578), .ZN(net_438), .A2(net_353) );
NAND2_X2 inst_346 ( .ZN(net_373), .A1(net_334), .A2(net_277) );
NAND2_X1 inst_491 ( .ZN(net_205), .A2(net_132), .A1(net_123) );
INV_X4 inst_567 ( .A(net_56), .ZN(net_35) );
NAND3_X1 inst_193 ( .A3(net_643), .ZN(net_592), .A2(net_546), .A1(net_540) );
NAND3_X4 inst_149 ( .A3(net_744), .A1(net_743), .ZN(net_649), .A2(net_539) );
NAND2_X2 inst_318 ( .A1(net_344), .ZN(net_301), .A2(net_215) );
NOR3_X2 inst_39 ( .ZN(net_389), .A3(net_388), .A2(net_355), .A1(net_283) );
NAND2_X4 inst_230 ( .A2(net_700), .A1(net_699), .ZN(net_694) );
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Connection Bus Top Level ////
//// ////
//// ////
//// Author: Johny Chi ////
//// [email protected] ////
//// skar.Wei ////
//// Just-CJ ////
//// ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// Copyright (C) 2014-2015 skar.Wei<[email protected]> ////
//// Copyright (C) 2015 Just-CJ<[email protected]> ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation;////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// Description
// 1. Up to 8 masters and 8 slaves share bus Wishbone connection
// 2. no priorty arbitor , 8 masters are processed in a round
// robin way,
// 3. if WB_USE_TRISTATE was defined, the share bus is a tristate
// bus, and use less logic resource.
// 4. wb_conbus was synthesis to XC2S100-5-PQ208 using synplify,
// Max speed >60M , and 374 SLICE if using Multiplexor bus
// or 150 SLICE if using tri-state bus.
//
//`define WB_USE_TRISTATE
`include "irq_controller_defines.v"
module irq_controller(
clk_i, rst_i,
i_gnt_arb,
intrrupt_en,
// Master 0 Interface
m0_irq_o, m0_Iack_i,
// Device 0 Interface
d0_irq_i, d0_Iack_o,
// Device 1 Interface
d1_irq_i, d1_Iack_o,
// Device 2 Interface
d2_irq_i, d2_Iack_o,
// Device 3 Interface
d3_irq_i, d3_Iack_o,
// Device 4 Interface
d4_irq_i, d4_Iack_o,
// Device 5 Interface
d5_irq_i, d5_Iack_o,
// Device 6 Interface
d6_irq_i, d6_Iack_o,
// Device 7 Interface
d7_irq_i, d7_Iack_o
);
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk_i, rst_i;
output wire [`irqNum - 1: 0]
i_gnt_arb;
input wire intrrupt_en;
// Master 0 Interface
input m0_Iack_i;
output m0_irq_o;
// Slave 0 Interface
input d0_irq_i;
output d0_Iack_o;
// Slave 1 Interface
input d1_irq_i;
output d1_Iack_o;
// Slave 2 Interface
input d2_irq_i;
output d2_Iack_o;
// Slave 3 Interface
input d3_irq_i;
output d3_Iack_o;
// Slave 4 Interface
input d4_irq_i;
output d4_Iack_o;
// Slave 5 Interface
input d5_irq_i;
output d5_Iack_o;
// Slave 6 Interface
input d6_irq_i;
output d6_Iack_o;
// Slave 7 Interface
input d7_irq_i;
output d7_Iack_o;
////////////////////////////////////////////////////////////////////
//
// Local wires
//
wire [`irqBit - 1: 0]
gnt;
reg i_bus_irq; // internal share bus, master data and control to slave
wire i_bus_ack; // internal share bus , slave control to master
////////////////////////////////////////////////////////////////////
//
// Master output Interfaces
//
// devices
assign d0_Iack_o = i_bus_ack & i_gnt_arb[0];
assign d1_Iack_o = i_bus_ack & i_gnt_arb[1];
assign d2_Iack_o = i_bus_ack & i_gnt_arb[2];
assign d3_Iack_o = i_bus_ack & i_gnt_arb[3];
// TODO: modify i_bus_s to fit number of slaves
assign i_bus_ack = { m0_Iack_i }; //s5_Iack_i | s6_Iack_i | s7_Iack_i};
////////////////////////////////
// Slave output interface
//
// slave1
assign m0_irq_o = i_bus_irq & intrrupt_en;
///////////////////////////////////////
// Master and Slave input interface
//
always @(gnt,
d0_irq_i,
d1_irq_i,
d2_irq_i,
d3_irq_i)
begin
case(gnt)
`irqBit'h0: i_bus_irq = d0_irq_i;
`irqBit'h1: i_bus_irq = d1_irq_i;
`irqBit'h2: i_bus_irq = d2_irq_i;
`irqBit'h3: i_bus_irq = d3_irq_i;
default:i_bus_irq = 0; //{m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i};
endcase
end
//
// arbitor
//
assign i_gnt_arb[0] = (gnt == `irqBit'd0);
assign i_gnt_arb[1] = (gnt == `irqBit'd1);
assign i_gnt_arb[2] = (gnt == `irqBit'd2);
assign i_gnt_arb[3] = (gnt == `irqBit'd3);
irq_arb irq_arb(
.clk(clk_i),
.rst(rst_i),
.req(
{d3_irq_i,
d2_irq_i,
d1_irq_i,
d0_irq_i}
),
.gnt(gnt)
);
endmodule
|
module ECenter(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]wall;
output [7:0]mapData;
reg [7:0]mColor;
//Screen is divided into 20 intervals of 32 pixels each in the x direction
always @(posedge clk_vga) begin
//From x == 0 to 63, inclusive
if((CurrentX >= 0 && CurrentX <=63) && (
(CurrentY <= 39) ||
(CurrentY >= 120 && CurrentY <=199) ||
(CurrentY >= 280 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 64 to 95, inclusive
else if( (CurrentX >= 64 && CurrentX <= 95) && (
(CurrentY <= 39) ||
(CurrentY >= 280 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 96 to 127, inclusive
else if( (CurrentX >= 96 && CurrentX <= 127) && (
(CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 128 to 159, inclusive
else if( (CurrentX >= 128 && CurrentX <= 159) && (
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 160 to 191, inclusive
else if( (CurrentX >= 160 && CurrentX <= 191) && (
(CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 192 to 223, inclusive
else if( (CurrentX >= 192 && CurrentX <= 223) && (
(CurrentY >= 280 && CurrentY <= 360) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 224 to 255, inclusive
else if( (CurrentX >= 224 && CurrentX <= 255) && (
(CurrentY <= 199) ||
(CurrentY >= 280 && CurrentY <= 359)))
mColor[7:0] <= wall;
//From X == 256 to 287, inclusive
else if( (CurrentX >= 256 && CurrentX <= 287) && (
(CurrentY >= 120 && CurrentY <= 199) ||
(CurrentY >= 280 && CurrentY <= 359) ) )
mColor[7:0] <= wall;
//From x == 288 to 351, inclusive
else if( (CurrentX >= 288 && CurrentX <= 351) && (
(CurrentY <= 39) ||
(CurrentY >= 120 && CurrentY <= 199) ||
(CurrentY >= 280 && CurrentY <= 359) ) )
mColor[7:0] <= wall;
//From x == 352 to 383, inclusive
else if( (CurrentX >= 352 && CurrentX <= 383) && (
(CurrentY >= 120 && CurrentY <= 199) ||
(CurrentY >= 280 && CurrentY <= 359) ) )
mColor[7:0] <= wall;
//From x == 384 to 415, inclusive
else if( (CurrentX >= 384 && CurrentX <= 415) && (
(CurrentY <= 199) ||
(CurrentY >= 280 && CurrentY <= 359)))
mColor[7:0] <= wall;
//From x == 416 to 447, inclusive
else if( (CurrentX >= 416 && CurrentX <= 447) && (
(CurrentY >= 280 && CurrentY <= 360) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 448 to 479, inclusive
else if( (CurrentX >= 448 && CurrentX <= 479) && (
(CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 480 to 511, inclusive
else if( (CurrentX >= 480 && CurrentX <= 511) && (
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 512 to 543, inclusive
else if( (CurrentX >= 512 && CurrentX <= 543) && (
(CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 544 to 575, inclusive
else if( (CurrentX >= 544 && CurrentX <= 575) && (
(CurrentY <= 39) ||
(CurrentY >= 280 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//From x == 576 to 640, inclusive
else if((CurrentX >= 576 && CurrentX <= 640) && (
(CurrentY <= 39) ||
(CurrentY >= 120 && CurrentY <=199) ||
(CurrentY >= 280 && CurrentY <= 359) ||
(CurrentY >= 441) ) )
mColor[7:0] <= wall;
//floor area - grey
else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule
|
`include "bsg_defines.v"
`timescale 1ps/1ps
// This module is a behavioral model of the delay line.
// A TSMC 40nm hardened implementation of this module
// can be found at:
//
// basejump_stl/hard/tsmc_40/bsg_clk_gen/bsg_dly_line.v
//
// This module should be replaced by the hardened version
// when being synthesized.
`include "bsg_clk_gen.vh"
module bsg_dly_line
import bsg_tag_pkg::bsg_tag_s;
#(parameter num_adgs_p=1)
(
input async_reset_i
,input bsg_tag_s bsg_tag_i
,input bsg_tag_s bsg_tag_trigger_i
,input clk_i
,output logic clk_o
);
`declare_bsg_clk_gen_osc_tag_payload_s(num_adgs_p)
bsg_clk_gen_osc_tag_payload_s fb_tag_r;
wire fb_we_r;
// note: oscillator has to be already working in order
// for configuration state to pass through here
bsg_tag_client #(.width_p($bits(bsg_clk_gen_osc_tag_payload_s))
,.harden_p(1)
,.default_p(0)
) btc
(.bsg_tag_i (bsg_tag_i)
,.recv_clk_i (clk_o)
,.recv_reset_i (1'b0) // no default value is loaded;
,.recv_new_r_o (fb_we_r) // default is already in OSC flops
,.recv_data_r_o(fb_tag_r)
);
wire [1:0] cdt = fb_tag_r.cdt;
wire [1:0] fdt = fb_tag_r.fdt;
wire [num_adgs_p-1:0] adg_ctrl = fb_tag_r.adg;
logic [4+num_adgs_p-1:0] ctrl_rrr;
always @(clk_o or async_reset_i)
if (async_reset_i)
ctrl_rrr <= '0;
else
if (fb_we_r)
ctrl_rrr <= {adg_ctrl, cdt, fdt};
always
begin
#1000
if (ctrl_rrr !== 'X)
# (
((1 << $bits(ctrl_rrr)) - ctrl_rrr)*100
)
clk_o <= (clk_i | async_reset_i);
end
endmodule
|
//------------------------------------------------------------------------------
// Title : Synchronous Reset generation flip-flop pair
// Project : Tri-Mode ethernet MAC
//------------------------------------------------------------------------------
// File : reset_sync.v
// Author : Xilinx, Inc.
//------------------------------------------------------------------------------
// Description: Both flip-flops have the same asynchronous reset signal.
// Together the flops create a minimum of a 1 clock period
// duration pulse which is used for synchronous reset.
//
// The flops are placed, using RLOCs, into the same slice.
// -----------------------------------------------------------------------------
// (c) Copyright 2006-2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
`timescale 1ps/1ps
module reset_sync #(
parameter INITIALISE = 2'b11
)
(
input reset_in,
input clk,
input enable,
output reset_out
);
wire reset_stage1;
wire reset_stage2;
(* ASYNC_REG = "TRUE", RLOC = "X0Y0", SHREG_EXTRACT = "NO", INIT = "1" *)
FDPE #(
.INIT (INITIALISE[0])
) reset_sync1 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (1'b0),
.Q (reset_stage1)
);
(* ASYNC_REG = "TRUE", RLOC = "X0Y0", SHREG_EXTRACT = "NO", INIT = "1" *)
FDPE #(
.INIT (INITIALISE[1])
) reset_sync2 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (reset_stage1),
.Q (reset_stage2)
);
assign reset_out = reset_stage2;
endmodule
|
// megafunction wizard: %ALTFP_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_add_sub
// ============================================================
// File Name: fp_add_sub.v
// Megafunction Name(s):
// altfp_add_sub
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone V" DIRECTION="VARIABLE" OPTIMIZE="SPEED" PIPELINE=14 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 add_sub clock dataa datab result
//VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_altfp_add_sub 2013:10:23:18:05:48:SJ cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
//VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources = reg 27
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altbarrel_shift_ltd
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [25:0] data;
input [4:0] distance;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [25:0] sbit_piper1d;
wire [5:0] dir_w;
wire direction_w;
wire [15:0] pad_w;
wire [155:0] sbit_w;
wire [4:0] sel_w;
wire [129:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[4]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 26'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[129:104];
assign
dir_w = {dir_pipe[0], dir_w[3:0], direction_w},
direction_w = 1'b0,
pad_w = {16{1'b0}},
result = sbit_w[155:130],
sbit_w = {sbit_piper1d, smux_w[103:0], data},
sel_w = {distance[4:0]},
smux_w = {((({26{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[113:104], pad_w[15:0]}) | ({26{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[129:120]})) | ({26{(~ sel_w[4])}} & sbit_w[129:104])), ((({26{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[95:78], pad_w[7:0]}) | ({26{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[103:86]})) | ({26{(~ sel_w[3])}} & sbit_w[103:78])), ((({26{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[73:52], pad_w[3:0]}) | ({26{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[77:56]})) | ({26{(~ sel_w[2])}} & sbit_w[77:52])), ((({26{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[49:26], pad_w[1:0]}) | ({26{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[51:28]})) | ({26{(~ sel_w[1])}} & sbit_w[51:26])), ((({26{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[24:0], pad_w[0]}) | ({26{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[25:1]})) | ({26{(~ sel_w[0])}} & sbit_w[25:0]))};
endmodule //fp_add_sub_altbarrel_shift_ltd
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" PIPELINE=2 REGISTER_OUTPUT="NO" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
//VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources = reg 58
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altbarrel_shift_s0g
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [25:0] data;
input [4:0] distance;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] dir_pipe;
reg [25:0] sbit_piper1d;
reg [25:0] sbit_piper2d;
reg sel_pipec2r1d;
reg sel_pipec3r1d;
reg sel_pipec4r1d;
reg sel_pipec4r2d;
wire [5:0] dir_w;
wire direction_w;
wire [15:0] pad_w;
wire [155:0] sbit_w;
wire [4:0] sel_w;
wire [129:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 2'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[3], dir_w[1]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 26'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[51:26];
// synopsys translate_off
initial
sbit_piper2d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper2d <= 26'b0;
else if (clk_en == 1'b1) sbit_piper2d <= smux_w[103:78];
// synopsys translate_off
initial
sel_pipec2r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec2r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec2r1d <= distance[2];
// synopsys translate_off
initial
sel_pipec3r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec3r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec3r1d <= distance[3];
// synopsys translate_off
initial
sel_pipec4r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec4r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec4r1d <= distance[4];
// synopsys translate_off
initial
sel_pipec4r2d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec4r2d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec4r2d <= sel_pipec4r1d;
assign
dir_w = {dir_w[4], dir_pipe[1], dir_w[2], dir_pipe[0], dir_w[0], direction_w},
direction_w = 1'b1,
pad_w = {16{1'b0}},
result = sbit_w[155:130],
sbit_w = {smux_w[129:104], sbit_piper2d, smux_w[77:52], sbit_piper1d, smux_w[25:0], data},
sel_w = {sel_pipec4r2d, sel_pipec3r1d, sel_pipec2r1d, distance[1:0]},
smux_w = {((({26{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[113:104], pad_w[15:0]}) | ({26{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[129:120]})) | ({26{(~ sel_w[4])}} & sbit_w[129:104])), ((({26{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[95:78], pad_w[7:0]}) | ({26{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[103:86]})) | ({26{(~ sel_w[3])}} & sbit_w[103:78])), ((({26{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[73:52], pad_w[3:0]}) | ({26{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[77:56]})) | ({26{(~ sel_w[2])}} & sbit_w[77:52])), ((({26{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[49:26], pad_w[1:0]}) | ({26{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[51:28]})) | ({26{(~ sel_w[1])}} & sbit_w[51:26])), ((({26{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[24:0], pad_w[0]}) | ({26{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[25:1]})) | ({26{(~ sel_w[0])}} & sbit_w[25:0]))};
endmodule //fp_add_sub_altbarrel_shift_s0g
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //fp_add_sub_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [0:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
fp_add_sub_altpriority_encoder_3e8 altpriority_encoder13
(
.data(data[1:0]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
fp_add_sub_altpriority_encoder_3e8 altpriority_encoder14
(
.data(data[3:2]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
assign
q = {(~ wire_altpriority_encoder14_zero), ((wire_altpriority_encoder14_zero & wire_altpriority_encoder13_q) | ((~ wire_altpriority_encoder14_zero) & wire_altpriority_encoder14_q))},
zero = (wire_altpriority_encoder13_zero & wire_altpriority_encoder14_zero);
endmodule //fp_add_sub_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [1:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
fp_add_sub_altpriority_encoder_6e8 altpriority_encoder11
(
.data(data[3:0]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
fp_add_sub_altpriority_encoder_6e8 altpriority_encoder12
(
.data(data[7:4]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
assign
q = {(~ wire_altpriority_encoder12_zero), (({2{wire_altpriority_encoder12_zero}} & wire_altpriority_encoder11_q) | ({2{(~ wire_altpriority_encoder12_zero)}} & wire_altpriority_encoder12_q))},
zero = (wire_altpriority_encoder11_zero & wire_altpriority_encoder12_zero);
endmodule //fp_add_sub_altpriority_encoder_be8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //fp_add_sub_altpriority_encoder_3v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder17_q;
wire [0:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
fp_add_sub_altpriority_encoder_3v7 altpriority_encoder17
(
.data(data[1:0]),
.q(wire_altpriority_encoder17_q));
fp_add_sub_altpriority_encoder_3e8 altpriority_encoder18
(
.data(data[3:2]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
assign
q = {(~ wire_altpriority_encoder18_zero), ((wire_altpriority_encoder18_zero & wire_altpriority_encoder17_q) | ((~ wire_altpriority_encoder18_zero) & wire_altpriority_encoder18_q))};
endmodule //fp_add_sub_altpriority_encoder_6v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder15_q;
wire [1:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
fp_add_sub_altpriority_encoder_6v7 altpriority_encoder15
(
.data(data[3:0]),
.q(wire_altpriority_encoder15_q));
fp_add_sub_altpriority_encoder_6e8 altpriority_encoder16
(
.data(data[7:4]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
assign
q = {(~ wire_altpriority_encoder16_zero), (({2{wire_altpriority_encoder16_zero}} & wire_altpriority_encoder15_q) | ({2{(~ wire_altpriority_encoder16_zero)}} & wire_altpriority_encoder16_q))};
endmodule //fp_add_sub_altpriority_encoder_bv7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_uv8
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [2:0] wire_altpriority_encoder9_q;
fp_add_sub_altpriority_encoder_be8 altpriority_encoder10
(
.data(data[15:8]),
.q(wire_altpriority_encoder10_q),
.zero(wire_altpriority_encoder10_zero));
fp_add_sub_altpriority_encoder_bv7 altpriority_encoder9
(
.data(data[7:0]),
.q(wire_altpriority_encoder9_q));
assign
q = {(~ wire_altpriority_encoder10_zero), (({3{wire_altpriority_encoder10_zero}} & wire_altpriority_encoder9_q) | ({3{(~ wire_altpriority_encoder10_zero)}} & wire_altpriority_encoder10_q))};
endmodule //fp_add_sub_altpriority_encoder_uv8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_ue9
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder19_q;
wire wire_altpriority_encoder19_zero;
wire [2:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
fp_add_sub_altpriority_encoder_be8 altpriority_encoder19
(
.data(data[7:0]),
.q(wire_altpriority_encoder19_q),
.zero(wire_altpriority_encoder19_zero));
fp_add_sub_altpriority_encoder_be8 altpriority_encoder20
(
.data(data[15:8]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
assign
q = {(~ wire_altpriority_encoder20_zero), (({3{wire_altpriority_encoder20_zero}} & wire_altpriority_encoder19_q) | ({3{(~ wire_altpriority_encoder20_zero)}} & wire_altpriority_encoder20_q))},
zero = (wire_altpriority_encoder19_zero & wire_altpriority_encoder20_zero);
endmodule //fp_add_sub_altpriority_encoder_ue9
//synthesis_resources = reg 5
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_ou8
(
aclr,
clk_en,
clock,
data,
q) ;
input aclr;
input clk_en;
input clock;
input [31:0] data;
output [4:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] wire_altpriority_encoder7_q;
wire [3:0] wire_altpriority_encoder8_q;
wire wire_altpriority_encoder8_zero;
reg [4:0] pipeline_q_dffe;
wire [4:0] tmp_q_wire;
fp_add_sub_altpriority_encoder_uv8 altpriority_encoder7
(
.data(data[15:0]),
.q(wire_altpriority_encoder7_q));
fp_add_sub_altpriority_encoder_ue9 altpriority_encoder8
(
.data(data[31:16]),
.q(wire_altpriority_encoder8_q),
.zero(wire_altpriority_encoder8_zero));
// synopsys translate_off
initial
pipeline_q_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipeline_q_dffe <= 5'b0;
else if (clk_en == 1'b1) pipeline_q_dffe <= tmp_q_wire;
assign
q = pipeline_q_dffe,
tmp_q_wire = {(~ wire_altpriority_encoder8_zero), (({4{wire_altpriority_encoder8_zero}} & wire_altpriority_encoder7_q) | ({4{(~ wire_altpriority_encoder8_zero)}} & wire_altpriority_encoder8_q))};
endmodule //fp_add_sub_altpriority_encoder_ou8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=2 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=16 WIDTHAD=4 aclr clk_en clock data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_nh8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {(~ data[0])},
zero = (~ (data[0] | data[1]));
endmodule //fp_add_sub_altpriority_encoder_nh8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_qh8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder27_q;
wire wire_altpriority_encoder27_zero;
wire [0:0] wire_altpriority_encoder28_q;
wire wire_altpriority_encoder28_zero;
fp_add_sub_altpriority_encoder_nh8 altpriority_encoder27
(
.data(data[1:0]),
.q(wire_altpriority_encoder27_q),
.zero(wire_altpriority_encoder27_zero));
fp_add_sub_altpriority_encoder_nh8 altpriority_encoder28
(
.data(data[3:2]),
.q(wire_altpriority_encoder28_q),
.zero(wire_altpriority_encoder28_zero));
assign
q = {wire_altpriority_encoder27_zero, ((wire_altpriority_encoder27_zero & wire_altpriority_encoder28_q) | ((~ wire_altpriority_encoder27_zero) & wire_altpriority_encoder27_q))},
zero = (wire_altpriority_encoder27_zero & wire_altpriority_encoder28_zero);
endmodule //fp_add_sub_altpriority_encoder_qh8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_2h9
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder25_q;
wire wire_altpriority_encoder25_zero;
wire [1:0] wire_altpriority_encoder26_q;
wire wire_altpriority_encoder26_zero;
fp_add_sub_altpriority_encoder_qh8 altpriority_encoder25
(
.data(data[3:0]),
.q(wire_altpriority_encoder25_q),
.zero(wire_altpriority_encoder25_zero));
fp_add_sub_altpriority_encoder_qh8 altpriority_encoder26
(
.data(data[7:4]),
.q(wire_altpriority_encoder26_q),
.zero(wire_altpriority_encoder26_zero));
assign
q = {wire_altpriority_encoder25_zero, (({2{wire_altpriority_encoder25_zero}} & wire_altpriority_encoder26_q) | ({2{(~ wire_altpriority_encoder25_zero)}} & wire_altpriority_encoder25_q))},
zero = (wire_altpriority_encoder25_zero & wire_altpriority_encoder26_zero);
endmodule //fp_add_sub_altpriority_encoder_2h9
//synthesis_resources = reg 5
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_d6b
(
aclr,
clk_en,
clock,
data,
q,
zero) ;
input aclr;
input clk_en;
input clock;
input [15:0] data;
output [3:0] q;
output zero;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [2:0] wire_altpriority_encoder23_q;
wire wire_altpriority_encoder23_zero;
wire [2:0] wire_altpriority_encoder24_q;
wire wire_altpriority_encoder24_zero;
reg [3:0] pipeline_q_dffe;
reg pipeline_zero_n_dffe;
wire [3:0] tmp_q_wire;
wire tmp_zero_wire;
fp_add_sub_altpriority_encoder_2h9 altpriority_encoder23
(
.data(data[7:0]),
.q(wire_altpriority_encoder23_q),
.zero(wire_altpriority_encoder23_zero));
fp_add_sub_altpriority_encoder_2h9 altpriority_encoder24
(
.data(data[15:8]),
.q(wire_altpriority_encoder24_q),
.zero(wire_altpriority_encoder24_zero));
// synopsys translate_off
initial
pipeline_q_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipeline_q_dffe <= 4'b0;
else if (clk_en == 1'b1) pipeline_q_dffe <= (~ tmp_q_wire);
// synopsys translate_off
initial
pipeline_zero_n_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipeline_zero_n_dffe <= 1'b0;
else if (clk_en == 1'b1) pipeline_zero_n_dffe <= (~ tmp_zero_wire);
assign
q = (~ pipeline_q_dffe),
tmp_q_wire = {wire_altpriority_encoder23_zero, (({3{wire_altpriority_encoder23_zero}} & wire_altpriority_encoder24_q) | ({3{(~ wire_altpriority_encoder23_zero)}} & wire_altpriority_encoder23_q))},
tmp_zero_wire = (wire_altpriority_encoder23_zero & wire_altpriority_encoder24_zero),
zero = (~ pipeline_zero_n_dffe);
endmodule //fp_add_sub_altpriority_encoder_d6b
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=16 WIDTHAD=4 aclr clk_en clock data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_n28
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {(~ data[0])};
endmodule //fp_add_sub_altpriority_encoder_n28
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_q28
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder33_q;
wire wire_altpriority_encoder33_zero;
wire [0:0] wire_altpriority_encoder34_q;
fp_add_sub_altpriority_encoder_nh8 altpriority_encoder33
(
.data(data[1:0]),
.q(wire_altpriority_encoder33_q),
.zero(wire_altpriority_encoder33_zero));
fp_add_sub_altpriority_encoder_n28 altpriority_encoder34
(
.data(data[3:2]),
.q(wire_altpriority_encoder34_q));
assign
q = {wire_altpriority_encoder33_zero, ((wire_altpriority_encoder33_zero & wire_altpriority_encoder34_q) | ((~ wire_altpriority_encoder33_zero) & wire_altpriority_encoder33_q))};
endmodule //fp_add_sub_altpriority_encoder_q28
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_229
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder31_q;
wire wire_altpriority_encoder31_zero;
wire [1:0] wire_altpriority_encoder32_q;
fp_add_sub_altpriority_encoder_qh8 altpriority_encoder31
(
.data(data[3:0]),
.q(wire_altpriority_encoder31_q),
.zero(wire_altpriority_encoder31_zero));
fp_add_sub_altpriority_encoder_q28 altpriority_encoder32
(
.data(data[7:4]),
.q(wire_altpriority_encoder32_q));
assign
q = {wire_altpriority_encoder31_zero, (({2{wire_altpriority_encoder31_zero}} & wire_altpriority_encoder32_q) | ({2{(~ wire_altpriority_encoder31_zero)}} & wire_altpriority_encoder31_q))};
endmodule //fp_add_sub_altpriority_encoder_229
//synthesis_resources = reg 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_ena
(
aclr,
clk_en,
clock,
data,
q) ;
input aclr;
input clk_en;
input clock;
input [15:0] data;
output [3:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [2:0] wire_altpriority_encoder29_q;
wire wire_altpriority_encoder29_zero;
wire [2:0] wire_altpriority_encoder30_q;
reg [3:0] pipeline_q_dffe;
wire [3:0] tmp_q_wire;
fp_add_sub_altpriority_encoder_2h9 altpriority_encoder29
(
.data(data[7:0]),
.q(wire_altpriority_encoder29_q),
.zero(wire_altpriority_encoder29_zero));
fp_add_sub_altpriority_encoder_229 altpriority_encoder30
(
.data(data[15:8]),
.q(wire_altpriority_encoder30_q));
// synopsys translate_off
initial
pipeline_q_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipeline_q_dffe <= 4'b0;
else if (clk_en == 1'b1) pipeline_q_dffe <= (~ tmp_q_wire);
assign
q = (~ pipeline_q_dffe),
tmp_q_wire = {wire_altpriority_encoder29_zero, (({3{wire_altpriority_encoder29_zero}} & wire_altpriority_encoder30_q) | ({3{(~ wire_altpriority_encoder29_zero)}} & wire_altpriority_encoder29_q))};
endmodule //fp_add_sub_altpriority_encoder_ena
//synthesis_resources = reg 14
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altpriority_encoder_dna
(
aclr,
clk_en,
clock,
data,
q) ;
input aclr;
input clk_en;
input clock;
input [31:0] data;
output [4:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] wire_altpriority_encoder21_q;
wire wire_altpriority_encoder21_zero;
wire [3:0] wire_altpriority_encoder22_q;
reg [4:0] pipeline_q_dffe;
wire [4:0] tmp_q_wire;
fp_add_sub_altpriority_encoder_d6b altpriority_encoder21
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data(data[15:0]),
.q(wire_altpriority_encoder21_q),
.zero(wire_altpriority_encoder21_zero));
fp_add_sub_altpriority_encoder_ena altpriority_encoder22
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data(data[31:16]),
.q(wire_altpriority_encoder22_q));
// synopsys translate_off
initial
pipeline_q_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipeline_q_dffe <= 5'b0;
else if (clk_en == 1'b1) pipeline_q_dffe <= (~ tmp_q_wire);
assign
q = (~ pipeline_q_dffe),
tmp_q_wire = {wire_altpriority_encoder21_zero, (({4{wire_altpriority_encoder21_zero}} & wire_altpriority_encoder22_q) | ({4{(~ wire_altpriority_encoder21_zero)}} & wire_altpriority_encoder21_q))};
endmodule //fp_add_sub_altpriority_encoder_dna
//synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 821
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_add_sub_altfp_add_sub_k7k
(
add_sub,
clock,
dataa,
datab,
result) ;
input add_sub;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 add_sub;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [25:0] wire_lbarrel_shift_result;
wire [25:0] wire_rbarrel_shift_result;
wire [4:0] wire_leading_zeroes_cnt_q;
wire [4:0] wire_trailing_zeros_cnt_q;
reg add_sub_dffe1;
reg add_sub_dffe12;
reg add_sub_dffe13;
reg add_sub_dffe14;
reg add_sub_dffe15;
reg [8:0] aligned_dataa_exp_dffe12;
reg [8:0] aligned_dataa_exp_dffe13;
reg [8:0] aligned_dataa_exp_dffe14;
reg [8:0] aligned_dataa_exp_dffe15;
reg [23:0] aligned_dataa_man_dffe12;
reg [23:0] aligned_dataa_man_dffe13;
reg [23:0] aligned_dataa_man_dffe14;
reg [23:0] aligned_dataa_man_dffe15;
reg aligned_dataa_sign_dffe12;
reg aligned_dataa_sign_dffe13;
reg aligned_dataa_sign_dffe14;
reg aligned_dataa_sign_dffe15;
reg [8:0] aligned_datab_exp_dffe12;
reg [8:0] aligned_datab_exp_dffe13;
reg [8:0] aligned_datab_exp_dffe14;
reg [8:0] aligned_datab_exp_dffe15;
reg [23:0] aligned_datab_man_dffe12;
reg [23:0] aligned_datab_man_dffe13;
reg [23:0] aligned_datab_man_dffe14;
reg [23:0] aligned_datab_man_dffe15;
reg aligned_datab_sign_dffe12;
reg aligned_datab_sign_dffe13;
reg aligned_datab_sign_dffe14;
reg aligned_datab_sign_dffe15;
reg both_inputs_are_infinite_dffe1;
reg [7:0] data_exp_dffe1;
reg [25:0] dataa_man_dffe1;
reg dataa_sign_dffe1;
reg [25:0] datab_man_dffe1;
reg datab_sign_dffe1;
reg denormal_res_dffe3;
reg denormal_res_dffe4;
reg denormal_res_dffe41;
reg [1:0] exp_adj_dffe21;
reg [1:0] exp_adj_dffe23;
reg exp_amb_mux_dffe13;
reg exp_amb_mux_dffe14;
reg exp_amb_mux_dffe15;
reg [7:0] exp_intermediate_res_dffe41;
reg [7:0] exp_out_dffe5;
reg [7:0] exp_res_dffe2;
reg [7:0] exp_res_dffe21;
reg [7:0] exp_res_dffe23;
reg [7:0] exp_res_dffe27;
reg [7:0] exp_res_dffe3;
reg [7:0] exp_res_dffe4;
reg infinite_output_sign_dffe1;
reg infinite_output_sign_dffe2;
reg infinite_output_sign_dffe21;
reg infinite_output_sign_dffe23;
reg infinite_output_sign_dffe27;
reg infinite_output_sign_dffe3;
reg infinite_output_sign_dffe31;
reg infinite_output_sign_dffe4;
reg infinite_output_sign_dffe41;
reg infinite_res_dffe3;
reg infinite_res_dffe4;
reg infinite_res_dffe41;
reg infinity_magnitude_sub_dffe2;
reg infinity_magnitude_sub_dffe21;
reg infinity_magnitude_sub_dffe23;
reg infinity_magnitude_sub_dffe27;
reg infinity_magnitude_sub_dffe3;
reg infinity_magnitude_sub_dffe31;
reg infinity_magnitude_sub_dffe4;
reg infinity_magnitude_sub_dffe41;
reg input_dataa_infinite_dffe12;
reg input_dataa_infinite_dffe13;
reg input_dataa_infinite_dffe14;
reg input_dataa_infinite_dffe15;
reg input_dataa_nan_dffe12;
reg input_datab_infinite_dffe12;
reg input_datab_infinite_dffe13;
reg input_datab_infinite_dffe14;
reg input_datab_infinite_dffe15;
reg input_datab_nan_dffe12;
reg input_is_infinite_dffe1;
reg input_is_infinite_dffe2;
reg input_is_infinite_dffe21;
reg input_is_infinite_dffe23;
reg input_is_infinite_dffe27;
reg input_is_infinite_dffe3;
reg input_is_infinite_dffe31;
reg input_is_infinite_dffe4;
reg input_is_infinite_dffe41;
reg input_is_nan_dffe1;
reg input_is_nan_dffe13;
reg input_is_nan_dffe14;
reg input_is_nan_dffe15;
reg input_is_nan_dffe2;
reg input_is_nan_dffe21;
reg input_is_nan_dffe23;
reg input_is_nan_dffe27;
reg input_is_nan_dffe3;
reg input_is_nan_dffe31;
reg input_is_nan_dffe4;
reg input_is_nan_dffe41;
reg [25:0] man_add_sub_res_mag_dffe21;
reg [25:0] man_add_sub_res_mag_dffe23;
reg [27:0] man_add_sub_res_mag_dffe27;
reg man_add_sub_res_sign_dffe21;
reg man_add_sub_res_sign_dffe23;
reg man_add_sub_res_sign_dffe27;
reg [25:0] man_dffe31;
reg [4:0] man_leading_zeros_dffe31;
reg [22:0] man_out_dffe5;
reg [22:0] man_res_dffe4;
reg man_res_is_not_zero_dffe3;
reg man_res_is_not_zero_dffe31;
reg man_res_is_not_zero_dffe4;
reg man_res_is_not_zero_dffe41;
reg man_res_not_zero_dffe23;
reg [25:0] man_res_rounding_add_sub_result_reg;
reg [23:0] man_smaller_dffe13;
reg need_complement_dffe2;
reg round_bit_dffe21;
reg round_bit_dffe23;
reg round_bit_dffe3;
reg round_bit_dffe31;
reg rounded_res_infinity_dffe4;
reg [4:0] rshift_distance_dffe13;
reg [4:0] rshift_distance_dffe14;
reg [4:0] rshift_distance_dffe15;
reg sign_dffe31;
reg sign_out_dffe5;
reg sign_res_dffe3;
reg sign_res_dffe4;
reg sign_res_dffe41;
reg sticky_bit_dffe1;
reg sticky_bit_dffe2;
reg sticky_bit_dffe21;
reg sticky_bit_dffe23;
reg sticky_bit_dffe27;
reg sticky_bit_dffe3;
reg sticky_bit_dffe31;
reg zero_man_sign_dffe2;
reg zero_man_sign_dffe21;
reg zero_man_sign_dffe23;
reg zero_man_sign_dffe27;
wire [8:0] wire_add_sub1_result;
wire [8:0] wire_add_sub2_result;
wire [5:0] wire_add_sub3_result;
wire [8:0] wire_add_sub4_result;
wire [8:0] wire_add_sub5_result;
wire [8:0] wire_add_sub6_result;
wire wire_man_2comp_res_lower_cout;
wire [13:0] wire_man_2comp_res_lower_result;
wire [13:0] wire_man_2comp_res_upper0_result;
wire [13:0] wire_man_2comp_res_upper1_result;
wire wire_man_add_sub_lower_cout;
wire [13:0] wire_man_add_sub_lower_result;
wire [13:0] wire_man_add_sub_upper0_result;
wire [13:0] wire_man_add_sub_upper1_result;
wire wire_man_res_rounding_add_sub_lower_cout;
wire [12:0] wire_man_res_rounding_add_sub_lower_result;
wire [12:0] wire_man_res_rounding_add_sub_upper1_result;
wire wire_trailing_zeros_limit_comparator_agb;
wire aclr;
wire add_sub_dffe11_wi;
wire add_sub_dffe11_wo;
wire add_sub_dffe12_wi;
wire add_sub_dffe12_wo;
wire add_sub_dffe13_wi;
wire add_sub_dffe13_wo;
wire add_sub_dffe14_wi;
wire add_sub_dffe14_wo;
wire add_sub_dffe15_wi;
wire add_sub_dffe15_wo;
wire add_sub_dffe1_wi;
wire add_sub_dffe1_wo;
wire add_sub_dffe25_wi;
wire add_sub_dffe25_wo;
wire add_sub_w2;
wire [12:0] adder_upper_w;
wire [8:0] aligned_dataa_exp_dffe12_wi;
wire [8:0] aligned_dataa_exp_dffe12_wo;
wire [8:0] aligned_dataa_exp_dffe13_wi;
wire [8:0] aligned_dataa_exp_dffe13_wo;
wire [8:0] aligned_dataa_exp_dffe14_wi;
wire [8:0] aligned_dataa_exp_dffe14_wo;
wire [8:0] aligned_dataa_exp_dffe15_wi;
wire [8:0] aligned_dataa_exp_dffe15_wo;
wire [8:0] aligned_dataa_exp_w;
wire [23:0] aligned_dataa_man_dffe12_wi;
wire [23:0] aligned_dataa_man_dffe12_wo;
wire [23:0] aligned_dataa_man_dffe13_wi;
wire [23:0] aligned_dataa_man_dffe13_wo;
wire [23:0] aligned_dataa_man_dffe14_wi;
wire [23:0] aligned_dataa_man_dffe14_wo;
wire [25:0] aligned_dataa_man_dffe15_w;
wire [23:0] aligned_dataa_man_dffe15_wi;
wire [23:0] aligned_dataa_man_dffe15_wo;
wire [25:0] aligned_dataa_man_w;
wire aligned_dataa_sign_dffe12_wi;
wire aligned_dataa_sign_dffe12_wo;
wire aligned_dataa_sign_dffe13_wi;
wire aligned_dataa_sign_dffe13_wo;
wire aligned_dataa_sign_dffe14_wi;
wire aligned_dataa_sign_dffe14_wo;
wire aligned_dataa_sign_dffe15_wi;
wire aligned_dataa_sign_dffe15_wo;
wire aligned_dataa_sign_w;
wire [8:0] aligned_datab_exp_dffe12_wi;
wire [8:0] aligned_datab_exp_dffe12_wo;
wire [8:0] aligned_datab_exp_dffe13_wi;
wire [8:0] aligned_datab_exp_dffe13_wo;
wire [8:0] aligned_datab_exp_dffe14_wi;
wire [8:0] aligned_datab_exp_dffe14_wo;
wire [8:0] aligned_datab_exp_dffe15_wi;
wire [8:0] aligned_datab_exp_dffe15_wo;
wire [8:0] aligned_datab_exp_w;
wire [23:0] aligned_datab_man_dffe12_wi;
wire [23:0] aligned_datab_man_dffe12_wo;
wire [23:0] aligned_datab_man_dffe13_wi;
wire [23:0] aligned_datab_man_dffe13_wo;
wire [23:0] aligned_datab_man_dffe14_wi;
wire [23:0] aligned_datab_man_dffe14_wo;
wire [25:0] aligned_datab_man_dffe15_w;
wire [23:0] aligned_datab_man_dffe15_wi;
wire [23:0] aligned_datab_man_dffe15_wo;
wire [25:0] aligned_datab_man_w;
wire aligned_datab_sign_dffe12_wi;
wire aligned_datab_sign_dffe12_wo;
wire aligned_datab_sign_dffe13_wi;
wire aligned_datab_sign_dffe13_wo;
wire aligned_datab_sign_dffe14_wi;
wire aligned_datab_sign_dffe14_wo;
wire aligned_datab_sign_dffe15_wi;
wire aligned_datab_sign_dffe15_wo;
wire aligned_datab_sign_w;
wire borrow_w;
wire both_inputs_are_infinite_dffe1_wi;
wire both_inputs_are_infinite_dffe1_wo;
wire both_inputs_are_infinite_dffe25_wi;
wire both_inputs_are_infinite_dffe25_wo;
wire clk_en;
wire [7:0] data_exp_dffe1_wi;
wire [7:0] data_exp_dffe1_wo;
wire [31:0] dataa_dffe11_wi;
wire [31:0] dataa_dffe11_wo;
wire [25:0] dataa_man_dffe1_wi;
wire [25:0] dataa_man_dffe1_wo;
wire dataa_sign_dffe1_wi;
wire dataa_sign_dffe1_wo;
wire dataa_sign_dffe25_wi;
wire dataa_sign_dffe25_wo;
wire [31:0] datab_dffe11_wi;
wire [31:0] datab_dffe11_wo;
wire [25:0] datab_man_dffe1_wi;
wire [25:0] datab_man_dffe1_wo;
wire datab_sign_dffe1_wi;
wire datab_sign_dffe1_wo;
wire denormal_flag_w;
wire denormal_res_dffe32_wi;
wire denormal_res_dffe32_wo;
wire denormal_res_dffe33_wi;
wire denormal_res_dffe33_wo;
wire denormal_res_dffe3_wi;
wire denormal_res_dffe3_wo;
wire denormal_res_dffe41_wi;
wire denormal_res_dffe41_wo;
wire denormal_res_dffe42_wi;
wire denormal_res_dffe42_wo;
wire denormal_res_dffe4_wi;
wire denormal_res_dffe4_wo;
wire denormal_result_w;
wire [7:0] exp_a_all_one_w;
wire [7:0] exp_a_not_zero_w;
wire [6:0] exp_adj_0pads;
wire [1:0] exp_adj_dffe21_wi;
wire [1:0] exp_adj_dffe21_wo;
wire [1:0] exp_adj_dffe23_wi;
wire [1:0] exp_adj_dffe23_wo;
wire [1:0] exp_adj_dffe26_wi;
wire [1:0] exp_adj_dffe26_wo;
wire [1:0] exp_adjust_by_add1;
wire [1:0] exp_adjust_by_add2;
wire [8:0] exp_adjustment2_add_sub_dataa_w;
wire [8:0] exp_adjustment2_add_sub_datab_w;
wire [8:0] exp_adjustment2_add_sub_w;
wire [8:0] exp_adjustment_add_sub_dataa_w;
wire [8:0] exp_adjustment_add_sub_datab_w;
wire [8:0] exp_adjustment_add_sub_w;
wire [7:0] exp_all_ones_w;
wire [7:0] exp_all_zeros_w;
wire exp_amb_mux_dffe13_wi;
wire exp_amb_mux_dffe13_wo;
wire exp_amb_mux_dffe14_wi;
wire exp_amb_mux_dffe14_wo;
wire exp_amb_mux_dffe15_wi;
wire exp_amb_mux_dffe15_wo;
wire exp_amb_mux_w;
wire [8:0] exp_amb_w;
wire [7:0] exp_b_all_one_w;
wire [7:0] exp_b_not_zero_w;
wire [8:0] exp_bma_w;
wire [2:0] exp_diff_abs_exceed_max_w;
wire [4:0] exp_diff_abs_max_w;
wire [7:0] exp_diff_abs_w;
wire [7:0] exp_intermediate_res_dffe41_wi;
wire [7:0] exp_intermediate_res_dffe41_wo;
wire [7:0] exp_intermediate_res_dffe42_wi;
wire [7:0] exp_intermediate_res_dffe42_wo;
wire [7:0] exp_intermediate_res_w;
wire [7:0] exp_out_dffe5_wi;
wire [7:0] exp_out_dffe5_wo;
wire [7:0] exp_res_dffe21_wi;
wire [7:0] exp_res_dffe21_wo;
wire [7:0] exp_res_dffe22_wi;
wire [7:0] exp_res_dffe22_wo;
wire [7:0] exp_res_dffe23_wi;
wire [7:0] exp_res_dffe23_wo;
wire [7:0] exp_res_dffe25_wi;
wire [7:0] exp_res_dffe25_wo;
wire [7:0] exp_res_dffe26_wi;
wire [7:0] exp_res_dffe26_wo;
wire [7:0] exp_res_dffe27_wi;
wire [7:0] exp_res_dffe27_wo;
wire [7:0] exp_res_dffe2_wi;
wire [7:0] exp_res_dffe2_wo;
wire [7:0] exp_res_dffe32_wi;
wire [7:0] exp_res_dffe32_wo;
wire [7:0] exp_res_dffe33_wi;
wire [7:0] exp_res_dffe33_wo;
wire [7:0] exp_res_dffe3_wi;
wire [7:0] exp_res_dffe3_wo;
wire [7:0] exp_res_dffe4_wi;
wire [7:0] exp_res_dffe4_wo;
wire [7:0] exp_res_max_w;
wire [8:0] exp_res_not_zero_w;
wire [8:0] exp_res_rounding_adder_dataa_w;
wire [8:0] exp_res_rounding_adder_w;
wire exp_rounded_res_infinity_w;
wire [7:0] exp_rounded_res_max_w;
wire [7:0] exp_rounded_res_w;
wire [8:0] exp_rounding_adjustment_w;
wire [8:0] exp_value;
wire force_infinity_w;
wire force_nan_w;
wire force_zero_w;
wire guard_bit_dffe3_wo;
wire infinite_output_sign_dffe1_wi;
wire infinite_output_sign_dffe1_wo;
wire infinite_output_sign_dffe21_wi;
wire infinite_output_sign_dffe21_wo;
wire infinite_output_sign_dffe22_wi;
wire infinite_output_sign_dffe22_wo;
wire infinite_output_sign_dffe23_wi;
wire infinite_output_sign_dffe23_wo;
wire infinite_output_sign_dffe25_wi;
wire infinite_output_sign_dffe25_wo;
wire infinite_output_sign_dffe26_wi;
wire infinite_output_sign_dffe26_wo;
wire infinite_output_sign_dffe27_wi;
wire infinite_output_sign_dffe27_wo;
wire infinite_output_sign_dffe2_wi;
wire infinite_output_sign_dffe2_wo;
wire infinite_output_sign_dffe31_wi;
wire infinite_output_sign_dffe31_wo;
wire infinite_output_sign_dffe32_wi;
wire infinite_output_sign_dffe32_wo;
wire infinite_output_sign_dffe33_wi;
wire infinite_output_sign_dffe33_wo;
wire infinite_output_sign_dffe3_wi;
wire infinite_output_sign_dffe3_wo;
wire infinite_output_sign_dffe41_wi;
wire infinite_output_sign_dffe41_wo;
wire infinite_output_sign_dffe42_wi;
wire infinite_output_sign_dffe42_wo;
wire infinite_output_sign_dffe4_wi;
wire infinite_output_sign_dffe4_wo;
wire infinite_res_dff32_wi;
wire infinite_res_dff32_wo;
wire infinite_res_dff33_wi;
wire infinite_res_dff33_wo;
wire infinite_res_dffe3_wi;
wire infinite_res_dffe3_wo;
wire infinite_res_dffe41_wi;
wire infinite_res_dffe41_wo;
wire infinite_res_dffe42_wi;
wire infinite_res_dffe42_wo;
wire infinite_res_dffe4_wi;
wire infinite_res_dffe4_wo;
wire infinity_magnitude_sub_dffe21_wi;
wire infinity_magnitude_sub_dffe21_wo;
wire infinity_magnitude_sub_dffe22_wi;
wire infinity_magnitude_sub_dffe22_wo;
wire infinity_magnitude_sub_dffe23_wi;
wire infinity_magnitude_sub_dffe23_wo;
wire infinity_magnitude_sub_dffe26_wi;
wire infinity_magnitude_sub_dffe26_wo;
wire infinity_magnitude_sub_dffe27_wi;
wire infinity_magnitude_sub_dffe27_wo;
wire infinity_magnitude_sub_dffe2_wi;
wire infinity_magnitude_sub_dffe2_wo;
wire infinity_magnitude_sub_dffe31_wi;
wire infinity_magnitude_sub_dffe31_wo;
wire infinity_magnitude_sub_dffe32_wi;
wire infinity_magnitude_sub_dffe32_wo;
wire infinity_magnitude_sub_dffe33_wi;
wire infinity_magnitude_sub_dffe33_wo;
wire infinity_magnitude_sub_dffe3_wi;
wire infinity_magnitude_sub_dffe3_wo;
wire infinity_magnitude_sub_dffe41_wi;
wire infinity_magnitude_sub_dffe41_wo;
wire infinity_magnitude_sub_dffe42_wi;
wire infinity_magnitude_sub_dffe42_wo;
wire infinity_magnitude_sub_dffe4_wi;
wire infinity_magnitude_sub_dffe4_wo;
wire input_dataa_denormal_dffe11_wi;
wire input_dataa_denormal_dffe11_wo;
wire input_dataa_denormal_w;
wire input_dataa_infinite_dffe11_wi;
wire input_dataa_infinite_dffe11_wo;
wire input_dataa_infinite_dffe12_wi;
wire input_dataa_infinite_dffe12_wo;
wire input_dataa_infinite_dffe13_wi;
wire input_dataa_infinite_dffe13_wo;
wire input_dataa_infinite_dffe14_wi;
wire input_dataa_infinite_dffe14_wo;
wire input_dataa_infinite_dffe15_wi;
wire input_dataa_infinite_dffe15_wo;
wire input_dataa_infinite_w;
wire input_dataa_nan_dffe11_wi;
wire input_dataa_nan_dffe11_wo;
wire input_dataa_nan_dffe12_wi;
wire input_dataa_nan_dffe12_wo;
wire input_dataa_nan_w;
wire input_dataa_zero_dffe11_wi;
wire input_dataa_zero_dffe11_wo;
wire input_dataa_zero_w;
wire input_datab_denormal_dffe11_wi;
wire input_datab_denormal_dffe11_wo;
wire input_datab_denormal_w;
wire input_datab_infinite_dffe11_wi;
wire input_datab_infinite_dffe11_wo;
wire input_datab_infinite_dffe12_wi;
wire input_datab_infinite_dffe12_wo;
wire input_datab_infinite_dffe13_wi;
wire input_datab_infinite_dffe13_wo;
wire input_datab_infinite_dffe14_wi;
wire input_datab_infinite_dffe14_wo;
wire input_datab_infinite_dffe15_wi;
wire input_datab_infinite_dffe15_wo;
wire input_datab_infinite_w;
wire input_datab_nan_dffe11_wi;
wire input_datab_nan_dffe11_wo;
wire input_datab_nan_dffe12_wi;
wire input_datab_nan_dffe12_wo;
wire input_datab_nan_w;
wire input_datab_zero_dffe11_wi;
wire input_datab_zero_dffe11_wo;
wire input_datab_zero_w;
wire input_is_infinite_dffe1_wi;
wire input_is_infinite_dffe1_wo;
wire input_is_infinite_dffe21_wi;
wire input_is_infinite_dffe21_wo;
wire input_is_infinite_dffe22_wi;
wire input_is_infinite_dffe22_wo;
wire input_is_infinite_dffe23_wi;
wire input_is_infinite_dffe23_wo;
wire input_is_infinite_dffe25_wi;
wire input_is_infinite_dffe25_wo;
wire input_is_infinite_dffe26_wi;
wire input_is_infinite_dffe26_wo;
wire input_is_infinite_dffe27_wi;
wire input_is_infinite_dffe27_wo;
wire input_is_infinite_dffe2_wi;
wire input_is_infinite_dffe2_wo;
wire input_is_infinite_dffe31_wi;
wire input_is_infinite_dffe31_wo;
wire input_is_infinite_dffe32_wi;
wire input_is_infinite_dffe32_wo;
wire input_is_infinite_dffe33_wi;
wire input_is_infinite_dffe33_wo;
wire input_is_infinite_dffe3_wi;
wire input_is_infinite_dffe3_wo;
wire input_is_infinite_dffe41_wi;
wire input_is_infinite_dffe41_wo;
wire input_is_infinite_dffe42_wi;
wire input_is_infinite_dffe42_wo;
wire input_is_infinite_dffe4_wi;
wire input_is_infinite_dffe4_wo;
wire input_is_nan_dffe13_wi;
wire input_is_nan_dffe13_wo;
wire input_is_nan_dffe14_wi;
wire input_is_nan_dffe14_wo;
wire input_is_nan_dffe15_wi;
wire input_is_nan_dffe15_wo;
wire input_is_nan_dffe1_wi;
wire input_is_nan_dffe1_wo;
wire input_is_nan_dffe21_wi;
wire input_is_nan_dffe21_wo;
wire input_is_nan_dffe22_wi;
wire input_is_nan_dffe22_wo;
wire input_is_nan_dffe23_wi;
wire input_is_nan_dffe23_wo;
wire input_is_nan_dffe25_wi;
wire input_is_nan_dffe25_wo;
wire input_is_nan_dffe26_wi;
wire input_is_nan_dffe26_wo;
wire input_is_nan_dffe27_wi;
wire input_is_nan_dffe27_wo;
wire input_is_nan_dffe2_wi;
wire input_is_nan_dffe2_wo;
wire input_is_nan_dffe31_wi;
wire input_is_nan_dffe31_wo;
wire input_is_nan_dffe32_wi;
wire input_is_nan_dffe32_wo;
wire input_is_nan_dffe33_wi;
wire input_is_nan_dffe33_wo;
wire input_is_nan_dffe3_wi;
wire input_is_nan_dffe3_wo;
wire input_is_nan_dffe41_wi;
wire input_is_nan_dffe41_wo;
wire input_is_nan_dffe42_wi;
wire input_is_nan_dffe42_wo;
wire input_is_nan_dffe4_wi;
wire input_is_nan_dffe4_wo;
wire [27:0] man_2comp_res_dataa_w;
wire [27:0] man_2comp_res_datab_w;
wire [27:0] man_2comp_res_w;
wire [22:0] man_a_not_zero_w;
wire [27:0] man_add_sub_dataa_w;
wire [27:0] man_add_sub_datab_w;
wire [25:0] man_add_sub_res_mag_dffe21_wi;
wire [25:0] man_add_sub_res_mag_dffe21_wo;
wire [25:0] man_add_sub_res_mag_dffe23_wi;
wire [25:0] man_add_sub_res_mag_dffe23_wo;
wire [25:0] man_add_sub_res_mag_dffe26_wi;
wire [25:0] man_add_sub_res_mag_dffe26_wo;
wire [27:0] man_add_sub_res_mag_dffe27_wi;
wire [27:0] man_add_sub_res_mag_dffe27_wo;
wire [27:0] man_add_sub_res_mag_w2;
wire man_add_sub_res_sign_dffe21_wo;
wire man_add_sub_res_sign_dffe23_wi;
wire man_add_sub_res_sign_dffe23_wo;
wire man_add_sub_res_sign_dffe26_wi;
wire man_add_sub_res_sign_dffe26_wo;
wire man_add_sub_res_sign_dffe27_wi;
wire man_add_sub_res_sign_dffe27_wo;
wire man_add_sub_res_sign_w2;
wire [27:0] man_add_sub_w;
wire [22:0] man_all_zeros_w;
wire [22:0] man_b_not_zero_w;
wire [25:0] man_dffe31_wo;
wire [25:0] man_intermediate_res_w;
wire [4:0] man_leading_zeros_cnt_w;
wire [4:0] man_leading_zeros_dffe31_wi;
wire [4:0] man_leading_zeros_dffe31_wo;
wire [22:0] man_nan_w;
wire [22:0] man_out_dffe5_wi;
wire [22:0] man_out_dffe5_wo;
wire [22:0] man_res_dffe4_wi;
wire [22:0] man_res_dffe4_wo;
wire man_res_is_not_zero_dffe31_wi;
wire man_res_is_not_zero_dffe31_wo;
wire man_res_is_not_zero_dffe32_wi;
wire man_res_is_not_zero_dffe32_wo;
wire man_res_is_not_zero_dffe33_wi;
wire man_res_is_not_zero_dffe33_wo;
wire man_res_is_not_zero_dffe3_wi;
wire man_res_is_not_zero_dffe3_wo;
wire man_res_is_not_zero_dffe41_wi;
wire man_res_is_not_zero_dffe41_wo;
wire man_res_is_not_zero_dffe42_wi;
wire man_res_is_not_zero_dffe42_wo;
wire man_res_is_not_zero_dffe4_wi;
wire man_res_is_not_zero_dffe4_wo;
wire [25:0] man_res_mag_w2;
wire man_res_not_zero_dffe23_wi;
wire man_res_not_zero_dffe23_wo;
wire man_res_not_zero_dffe26_wi;
wire man_res_not_zero_dffe26_wo;
wire [24:0] man_res_not_zero_w2;
wire [25:0] man_res_rounding_add_sub_datab_w;
wire [25:0] man_res_rounding_add_sub_w;
wire [23:0] man_res_w3;
wire [22:0] man_rounded_res_w;
wire man_rounding_add_value_w;
wire [23:0] man_smaller_dffe13_wi;
wire [23:0] man_smaller_dffe13_wo;
wire [23:0] man_smaller_w;
wire need_complement_dffe22_wi;
wire need_complement_dffe22_wo;
wire need_complement_dffe2_wi;
wire need_complement_dffe2_wo;
wire [1:0] pos_sign_bit_ext;
wire [3:0] priority_encoder_1pads_w;
wire round_bit_dffe21_wi;
wire round_bit_dffe21_wo;
wire round_bit_dffe23_wi;
wire round_bit_dffe23_wo;
wire round_bit_dffe26_wi;
wire round_bit_dffe26_wo;
wire round_bit_dffe31_wi;
wire round_bit_dffe31_wo;
wire round_bit_dffe32_wi;
wire round_bit_dffe32_wo;
wire round_bit_dffe33_wi;
wire round_bit_dffe33_wo;
wire round_bit_dffe3_wi;
wire round_bit_dffe3_wo;
wire round_bit_w;
wire rounded_res_infinity_dffe4_wi;
wire rounded_res_infinity_dffe4_wo;
wire [4:0] rshift_distance_dffe13_wi;
wire [4:0] rshift_distance_dffe13_wo;
wire [4:0] rshift_distance_dffe14_wi;
wire [4:0] rshift_distance_dffe14_wo;
wire [4:0] rshift_distance_dffe15_wi;
wire [4:0] rshift_distance_dffe15_wo;
wire [4:0] rshift_distance_w;
wire sign_dffe31_wi;
wire sign_dffe31_wo;
wire sign_dffe32_wi;
wire sign_dffe32_wo;
wire sign_dffe33_wi;
wire sign_dffe33_wo;
wire sign_out_dffe5_wi;
wire sign_out_dffe5_wo;
wire sign_res_dffe3_wi;
wire sign_res_dffe3_wo;
wire sign_res_dffe41_wi;
wire sign_res_dffe41_wo;
wire sign_res_dffe42_wi;
wire sign_res_dffe42_wo;
wire sign_res_dffe4_wi;
wire sign_res_dffe4_wo;
wire [5:0] sticky_bit_cnt_dataa_w;
wire [5:0] sticky_bit_cnt_datab_w;
wire [5:0] sticky_bit_cnt_res_w;
wire sticky_bit_dffe1_wi;
wire sticky_bit_dffe1_wo;
wire sticky_bit_dffe21_wi;
wire sticky_bit_dffe21_wo;
wire sticky_bit_dffe22_wi;
wire sticky_bit_dffe22_wo;
wire sticky_bit_dffe23_wi;
wire sticky_bit_dffe23_wo;
wire sticky_bit_dffe25_wi;
wire sticky_bit_dffe25_wo;
wire sticky_bit_dffe26_wi;
wire sticky_bit_dffe26_wo;
wire sticky_bit_dffe27_wi;
wire sticky_bit_dffe27_wo;
wire sticky_bit_dffe2_wi;
wire sticky_bit_dffe2_wo;
wire sticky_bit_dffe31_wi;
wire sticky_bit_dffe31_wo;
wire sticky_bit_dffe32_wi;
wire sticky_bit_dffe32_wo;
wire sticky_bit_dffe33_wi;
wire sticky_bit_dffe33_wo;
wire sticky_bit_dffe3_wi;
wire sticky_bit_dffe3_wo;
wire sticky_bit_w;
wire [5:0] trailing_zeros_limit_w;
wire zero_man_sign_dffe21_wi;
wire zero_man_sign_dffe21_wo;
wire zero_man_sign_dffe22_wi;
wire zero_man_sign_dffe22_wo;
wire zero_man_sign_dffe23_wi;
wire zero_man_sign_dffe23_wo;
wire zero_man_sign_dffe26_wi;
wire zero_man_sign_dffe26_wo;
wire zero_man_sign_dffe27_wi;
wire zero_man_sign_dffe27_wo;
wire zero_man_sign_dffe2_wi;
wire zero_man_sign_dffe2_wo;
fp_add_sub_altbarrel_shift_ltd lbarrel_shift
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data(man_dffe31_wo),
.distance(man_leading_zeros_cnt_w),
.result(wire_lbarrel_shift_result));
fp_add_sub_altbarrel_shift_s0g rbarrel_shift
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({man_smaller_dffe13_wo, {2{1'b0}}}),
.distance(rshift_distance_dffe13_wo),
.result(wire_rbarrel_shift_result));
fp_add_sub_altpriority_encoder_ou8 leading_zeroes_cnt
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({man_add_sub_res_mag_dffe21_wo[25:1], 1'b1, {6{1'b0}}}),
.q(wire_leading_zeroes_cnt_q));
fp_add_sub_altpriority_encoder_dna trailing_zeros_cnt
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({{9{1'b1}}, man_smaller_dffe13_wo[22:0]}),
.q(wire_trailing_zeros_cnt_q));
// synopsys translate_off
initial
add_sub_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_sub_dffe1 <= 1'b0;
else if (clk_en == 1'b1) add_sub_dffe1 <= add_sub_dffe1_wi;
// synopsys translate_off
initial
add_sub_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_sub_dffe12 <= 1'b0;
else if (clk_en == 1'b1) add_sub_dffe12 <= add_sub_dffe12_wi;
// synopsys translate_off
initial
add_sub_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_sub_dffe13 <= 1'b0;
else if (clk_en == 1'b1) add_sub_dffe13 <= add_sub_dffe13_wi;
// synopsys translate_off
initial
add_sub_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_sub_dffe14 <= 1'b0;
else if (clk_en == 1'b1) add_sub_dffe14 <= add_sub_dffe14_wi;
// synopsys translate_off
initial
add_sub_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_sub_dffe15 <= 1'b0;
else if (clk_en == 1'b1) add_sub_dffe15 <= add_sub_dffe15_wi;
// synopsys translate_off
initial
aligned_dataa_exp_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_exp_dffe12 <= 9'b0;
else if (clk_en == 1'b1) aligned_dataa_exp_dffe12 <= aligned_dataa_exp_dffe12_wi;
// synopsys translate_off
initial
aligned_dataa_exp_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_exp_dffe13 <= 9'b0;
else if (clk_en == 1'b1) aligned_dataa_exp_dffe13 <= aligned_dataa_exp_dffe13_wi;
// synopsys translate_off
initial
aligned_dataa_exp_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_exp_dffe14 <= 9'b0;
else if (clk_en == 1'b1) aligned_dataa_exp_dffe14 <= aligned_dataa_exp_dffe14_wi;
// synopsys translate_off
initial
aligned_dataa_exp_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_exp_dffe15 <= 9'b0;
else if (clk_en == 1'b1) aligned_dataa_exp_dffe15 <= aligned_dataa_exp_dffe15_wi;
// synopsys translate_off
initial
aligned_dataa_man_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_man_dffe12 <= 24'b0;
else if (clk_en == 1'b1) aligned_dataa_man_dffe12 <= aligned_dataa_man_dffe12_wi;
// synopsys translate_off
initial
aligned_dataa_man_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_man_dffe13 <= 24'b0;
else if (clk_en == 1'b1) aligned_dataa_man_dffe13 <= aligned_dataa_man_dffe13_wi;
// synopsys translate_off
initial
aligned_dataa_man_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_man_dffe14 <= 24'b0;
else if (clk_en == 1'b1) aligned_dataa_man_dffe14 <= aligned_dataa_man_dffe14_wi;
// synopsys translate_off
initial
aligned_dataa_man_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_man_dffe15 <= 24'b0;
else if (clk_en == 1'b1) aligned_dataa_man_dffe15 <= aligned_dataa_man_dffe15_wi;
// synopsys translate_off
initial
aligned_dataa_sign_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_sign_dffe12 <= 1'b0;
else if (clk_en == 1'b1) aligned_dataa_sign_dffe12 <= aligned_dataa_sign_dffe12_wi;
// synopsys translate_off
initial
aligned_dataa_sign_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_sign_dffe13 <= 1'b0;
else if (clk_en == 1'b1) aligned_dataa_sign_dffe13 <= aligned_dataa_sign_dffe13_wi;
// synopsys translate_off
initial
aligned_dataa_sign_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_sign_dffe14 <= 1'b0;
else if (clk_en == 1'b1) aligned_dataa_sign_dffe14 <= aligned_dataa_sign_dffe14_wi;
// synopsys translate_off
initial
aligned_dataa_sign_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_sign_dffe15 <= 1'b0;
else if (clk_en == 1'b1) aligned_dataa_sign_dffe15 <= aligned_dataa_sign_dffe15_wi;
// synopsys translate_off
initial
aligned_datab_exp_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_exp_dffe12 <= 9'b0;
else if (clk_en == 1'b1) aligned_datab_exp_dffe12 <= aligned_datab_exp_dffe12_wi;
// synopsys translate_off
initial
aligned_datab_exp_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_exp_dffe13 <= 9'b0;
else if (clk_en == 1'b1) aligned_datab_exp_dffe13 <= aligned_datab_exp_dffe13_wi;
// synopsys translate_off
initial
aligned_datab_exp_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_exp_dffe14 <= 9'b0;
else if (clk_en == 1'b1) aligned_datab_exp_dffe14 <= aligned_datab_exp_dffe14_wi;
// synopsys translate_off
initial
aligned_datab_exp_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_exp_dffe15 <= 9'b0;
else if (clk_en == 1'b1) aligned_datab_exp_dffe15 <= aligned_datab_exp_dffe15_wi;
// synopsys translate_off
initial
aligned_datab_man_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_man_dffe12 <= 24'b0;
else if (clk_en == 1'b1) aligned_datab_man_dffe12 <= aligned_datab_man_dffe12_wi;
// synopsys translate_off
initial
aligned_datab_man_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_man_dffe13 <= 24'b0;
else if (clk_en == 1'b1) aligned_datab_man_dffe13 <= aligned_datab_man_dffe13_wi;
// synopsys translate_off
initial
aligned_datab_man_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_man_dffe14 <= 24'b0;
else if (clk_en == 1'b1) aligned_datab_man_dffe14 <= aligned_datab_man_dffe14_wi;
// synopsys translate_off
initial
aligned_datab_man_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_man_dffe15 <= 24'b0;
else if (clk_en == 1'b1) aligned_datab_man_dffe15 <= aligned_datab_man_dffe15_wi;
// synopsys translate_off
initial
aligned_datab_sign_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_sign_dffe12 <= 1'b0;
else if (clk_en == 1'b1) aligned_datab_sign_dffe12 <= aligned_datab_sign_dffe12_wi;
// synopsys translate_off
initial
aligned_datab_sign_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_sign_dffe13 <= 1'b0;
else if (clk_en == 1'b1) aligned_datab_sign_dffe13 <= aligned_datab_sign_dffe13_wi;
// synopsys translate_off
initial
aligned_datab_sign_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_sign_dffe14 <= 1'b0;
else if (clk_en == 1'b1) aligned_datab_sign_dffe14 <= aligned_datab_sign_dffe14_wi;
// synopsys translate_off
initial
aligned_datab_sign_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_sign_dffe15 <= 1'b0;
else if (clk_en == 1'b1) aligned_datab_sign_dffe15 <= aligned_datab_sign_dffe15_wi;
// synopsys translate_off
initial
both_inputs_are_infinite_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) both_inputs_are_infinite_dffe1 <= 1'b0;
else if (clk_en == 1'b1) both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
// synopsys translate_off
initial
data_exp_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) data_exp_dffe1 <= 8'b0;
else if (clk_en == 1'b1) data_exp_dffe1 <= data_exp_dffe1_wi;
// synopsys translate_off
initial
dataa_man_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_dffe1 <= 26'b0;
else if (clk_en == 1'b1) dataa_man_dffe1 <= dataa_man_dffe1_wi;
// synopsys translate_off
initial
dataa_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
// synopsys translate_off
initial
datab_man_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_dffe1 <= 26'b0;
else if (clk_en == 1'b1) datab_man_dffe1 <= datab_man_dffe1_wi;
// synopsys translate_off
initial
datab_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) datab_sign_dffe1 <= datab_sign_dffe1_wi;
// synopsys translate_off
initial
denormal_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) denormal_res_dffe3 <= 1'b0;
else if (clk_en == 1'b1) denormal_res_dffe3 <= denormal_res_dffe3_wi;
// synopsys translate_off
initial
denormal_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) denormal_res_dffe4 <= 1'b0;
else if (clk_en == 1'b1) denormal_res_dffe4 <= denormal_res_dffe4_wi;
// synopsys translate_off
initial
denormal_res_dffe41 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) denormal_res_dffe41 <= 1'b0;
else if (clk_en == 1'b1) denormal_res_dffe41 <= denormal_res_dffe41_wi;
// synopsys translate_off
initial
exp_adj_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_adj_dffe21 <= 2'b0;
else if (clk_en == 1'b1) exp_adj_dffe21 <= exp_adj_dffe21_wi;
// synopsys translate_off
initial
exp_adj_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_adj_dffe23 <= 2'b0;
else if (clk_en == 1'b1) exp_adj_dffe23 <= exp_adj_dffe23_wi;
// synopsys translate_off
initial
exp_amb_mux_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_amb_mux_dffe13 <= 1'b0;
else if (clk_en == 1'b1) exp_amb_mux_dffe13 <= exp_amb_mux_dffe13_wi;
// synopsys translate_off
initial
exp_amb_mux_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_amb_mux_dffe14 <= 1'b0;
else if (clk_en == 1'b1) exp_amb_mux_dffe14 <= exp_amb_mux_dffe14_wi;
// synopsys translate_off
initial
exp_amb_mux_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_amb_mux_dffe15 <= 1'b0;
else if (clk_en == 1'b1) exp_amb_mux_dffe15 <= exp_amb_mux_dffe15_wi;
// synopsys translate_off
initial
exp_intermediate_res_dffe41 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_intermediate_res_dffe41 <= 8'b0;
else if (clk_en == 1'b1) exp_intermediate_res_dffe41 <= exp_intermediate_res_dffe41_wi;
// synopsys translate_off
initial
exp_out_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_out_dffe5 <= 8'b0;
else if (clk_en == 1'b1) exp_out_dffe5 <= exp_out_dffe5_wi;
// synopsys translate_off
initial
exp_res_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe2 <= 8'b0;
else if (clk_en == 1'b1) exp_res_dffe2 <= exp_res_dffe2_wi;
// synopsys translate_off
initial
exp_res_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe21 <= 8'b0;
else if (clk_en == 1'b1) exp_res_dffe21 <= exp_res_dffe21_wi;
// synopsys translate_off
initial
exp_res_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe23 <= 8'b0;
else if (clk_en == 1'b1) exp_res_dffe23 <= exp_res_dffe23_wi;
// synopsys translate_off
initial
exp_res_dffe27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe27 <= 8'b0;
else if (clk_en == 1'b1) exp_res_dffe27 <= exp_res_dffe27_wi;
// synopsys translate_off
initial
exp_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe3 <= 8'b0;
else if (clk_en == 1'b1) exp_res_dffe3 <= exp_res_dffe3_wi;
// synopsys translate_off
initial
exp_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe4 <= 8'b0;
else if (clk_en == 1'b1) exp_res_dffe4 <= exp_res_dffe4_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe2 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe21 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe23 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe23 <= infinite_output_sign_dffe23_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe27 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe27 <= infinite_output_sign_dffe27_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe3 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe31 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe4 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe41 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe41 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe41 <= infinite_output_sign_dffe41_wi;
// synopsys translate_off
initial
infinite_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_res_dffe3 <= 1'b0;
else if (clk_en == 1'b1) infinite_res_dffe3 <= infinite_res_dffe3_wi;
// synopsys translate_off
initial
infinite_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_res_dffe4 <= 1'b0;
else if (clk_en == 1'b1) infinite_res_dffe4 <= infinite_res_dffe4_wi;
// synopsys translate_off
initial
infinite_res_dffe41 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_res_dffe41 <= 1'b0;
else if (clk_en == 1'b1) infinite_res_dffe41 <= infinite_res_dffe41_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe2 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe21 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe23 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe23 <= infinity_magnitude_sub_dffe23_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe27 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe27 <= infinity_magnitude_sub_dffe27_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe3 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe31 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe4 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe41 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe41 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe41 <= infinity_magnitude_sub_dffe41_wi;
// synopsys translate_off
initial
input_dataa_infinite_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_dataa_infinite_dffe12 <= 1'b0;
else if (clk_en == 1'b1) input_dataa_infinite_dffe12 <= input_dataa_infinite_dffe12_wi;
// synopsys translate_off
initial
input_dataa_infinite_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_dataa_infinite_dffe13 <= 1'b0;
else if (clk_en == 1'b1) input_dataa_infinite_dffe13 <= input_dataa_infinite_dffe13_wi;
// synopsys translate_off
initial
input_dataa_infinite_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_dataa_infinite_dffe14 <= 1'b0;
else if (clk_en == 1'b1) input_dataa_infinite_dffe14 <= input_dataa_infinite_dffe14_wi;
// synopsys translate_off
initial
input_dataa_infinite_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_dataa_infinite_dffe15 <= 1'b0;
else if (clk_en == 1'b1) input_dataa_infinite_dffe15 <= input_dataa_infinite_dffe15_wi;
// synopsys translate_off
initial
input_dataa_nan_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_dataa_nan_dffe12 <= 1'b0;
else if (clk_en == 1'b1) input_dataa_nan_dffe12 <= input_dataa_nan_dffe12_wi;
// synopsys translate_off
initial
input_datab_infinite_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_datab_infinite_dffe12 <= 1'b0;
else if (clk_en == 1'b1) input_datab_infinite_dffe12 <= input_datab_infinite_dffe12_wi;
// synopsys translate_off
initial
input_datab_infinite_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_datab_infinite_dffe13 <= 1'b0;
else if (clk_en == 1'b1) input_datab_infinite_dffe13 <= input_datab_infinite_dffe13_wi;
// synopsys translate_off
initial
input_datab_infinite_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_datab_infinite_dffe14 <= 1'b0;
else if (clk_en == 1'b1) input_datab_infinite_dffe14 <= input_datab_infinite_dffe14_wi;
// synopsys translate_off
initial
input_datab_infinite_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_datab_infinite_dffe15 <= 1'b0;
else if (clk_en == 1'b1) input_datab_infinite_dffe15 <= input_datab_infinite_dffe15_wi;
// synopsys translate_off
initial
input_datab_nan_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_datab_nan_dffe12 <= 1'b0;
else if (clk_en == 1'b1) input_datab_nan_dffe12 <= input_datab_nan_dffe12_wi;
// synopsys translate_off
initial
input_is_infinite_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
// synopsys translate_off
initial
input_is_infinite_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
// synopsys translate_off
initial
input_is_infinite_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe21 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
// synopsys translate_off
initial
input_is_infinite_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe23 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe23 <= input_is_infinite_dffe23_wi;
// synopsys translate_off
initial
input_is_infinite_dffe27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe27 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe27 <= input_is_infinite_dffe27_wi;
// synopsys translate_off
initial
input_is_infinite_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
// synopsys translate_off
initial
input_is_infinite_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe31 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
// synopsys translate_off
initial
input_is_infinite_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
// synopsys translate_off
initial
input_is_infinite_dffe41 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe41 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe41 <= input_is_infinite_dffe41_wi;
// synopsys translate_off
initial
input_is_nan_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
// synopsys translate_off
initial
input_is_nan_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe13 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe13 <= input_is_nan_dffe13_wi;
// synopsys translate_off
initial
input_is_nan_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe14 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe14 <= input_is_nan_dffe14_wi;
// synopsys translate_off
initial
input_is_nan_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe15 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe15 <= input_is_nan_dffe15_wi;
// synopsys translate_off
initial
input_is_nan_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
// synopsys translate_off
initial
input_is_nan_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe21 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
// synopsys translate_off
initial
input_is_nan_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe23 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe23 <= input_is_nan_dffe23_wi;
// synopsys translate_off
initial
input_is_nan_dffe27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe27 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe27 <= input_is_nan_dffe27_wi;
// synopsys translate_off
initial
input_is_nan_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
// synopsys translate_off
initial
input_is_nan_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe31 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
// synopsys translate_off
initial
input_is_nan_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
// synopsys translate_off
initial
input_is_nan_dffe41 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe41 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe41 <= input_is_nan_dffe41_wi;
// synopsys translate_off
initial
man_add_sub_res_mag_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_add_sub_res_mag_dffe21 <= 26'b0;
else if (clk_en == 1'b1) man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
// synopsys translate_off
initial
man_add_sub_res_mag_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_add_sub_res_mag_dffe23 <= 26'b0;
else if (clk_en == 1'b1) man_add_sub_res_mag_dffe23 <= man_add_sub_res_mag_dffe23_wi;
// synopsys translate_off
initial
man_add_sub_res_mag_dffe27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_add_sub_res_mag_dffe27 <= 28'b0;
else if (clk_en == 1'b1) man_add_sub_res_mag_dffe27 <= man_add_sub_res_mag_dffe27_wi;
// synopsys translate_off
initial
man_add_sub_res_sign_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_add_sub_res_sign_dffe21 <= 1'b0;
else if (clk_en == 1'b1) man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
// synopsys translate_off
initial
man_add_sub_res_sign_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_add_sub_res_sign_dffe23 <= 1'b0;
else if (clk_en == 1'b1) man_add_sub_res_sign_dffe23 <= man_add_sub_res_sign_dffe23_wi;
// synopsys translate_off
initial
man_add_sub_res_sign_dffe27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_add_sub_res_sign_dffe27 <= 1'b0;
else if (clk_en == 1'b1) man_add_sub_res_sign_dffe27 <= man_add_sub_res_sign_dffe27_wi;
// synopsys translate_off
initial
man_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_dffe31 <= 26'b0;
else if (clk_en == 1'b1) man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
// synopsys translate_off
initial
man_leading_zeros_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_leading_zeros_dffe31 <= 5'b0;
else if (clk_en == 1'b1) man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
// synopsys translate_off
initial
man_out_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_out_dffe5 <= 23'b0;
else if (clk_en == 1'b1) man_out_dffe5 <= man_out_dffe5_wi;
// synopsys translate_off
initial
man_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_dffe4 <= 23'b0;
else if (clk_en == 1'b1) man_res_dffe4 <= man_res_dffe4_wi;
// synopsys translate_off
initial
man_res_is_not_zero_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_is_not_zero_dffe3 <= 1'b0;
else if (clk_en == 1'b1) man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
// synopsys translate_off
initial
man_res_is_not_zero_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_is_not_zero_dffe31 <= 1'b0;
else if (clk_en == 1'b1) man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
// synopsys translate_off
initial
man_res_is_not_zero_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_is_not_zero_dffe4 <= 1'b0;
else if (clk_en == 1'b1) man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
// synopsys translate_off
initial
man_res_is_not_zero_dffe41 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_is_not_zero_dffe41 <= 1'b0;
else if (clk_en == 1'b1) man_res_is_not_zero_dffe41 <= man_res_is_not_zero_dffe41_wi;
// synopsys translate_off
initial
man_res_not_zero_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_not_zero_dffe23 <= 1'b0;
else if (clk_en == 1'b1) man_res_not_zero_dffe23 <= man_res_not_zero_dffe23_wi;
// synopsys translate_off
initial
man_res_rounding_add_sub_result_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_rounding_add_sub_result_reg <= 26'b0;
else if (clk_en == 1'b1) man_res_rounding_add_sub_result_reg <= {(({13{(~ wire_man_res_rounding_add_sub_lower_cout)}} & adder_upper_w) | ({13{wire_man_res_rounding_add_sub_lower_cout}} & wire_man_res_rounding_add_sub_upper1_result)), wire_man_res_rounding_add_sub_lower_result};
// synopsys translate_off
initial
man_smaller_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_smaller_dffe13 <= 24'b0;
else if (clk_en == 1'b1) man_smaller_dffe13 <= man_smaller_dffe13_wi;
// synopsys translate_off
initial
need_complement_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) need_complement_dffe2 <= 1'b0;
else if (clk_en == 1'b1) need_complement_dffe2 <= need_complement_dffe2_wi;
// synopsys translate_off
initial
round_bit_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_bit_dffe21 <= 1'b0;
else if (clk_en == 1'b1) round_bit_dffe21 <= round_bit_dffe21_wi;
// synopsys translate_off
initial
round_bit_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_bit_dffe23 <= 1'b0;
else if (clk_en == 1'b1) round_bit_dffe23 <= round_bit_dffe23_wi;
// synopsys translate_off
initial
round_bit_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_bit_dffe3 <= 1'b0;
else if (clk_en == 1'b1) round_bit_dffe3 <= round_bit_dffe3_wi;
// synopsys translate_off
initial
round_bit_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_bit_dffe31 <= 1'b0;
else if (clk_en == 1'b1) round_bit_dffe31 <= round_bit_dffe31_wi;
// synopsys translate_off
initial
rounded_res_infinity_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rounded_res_infinity_dffe4 <= 1'b0;
else if (clk_en == 1'b1) rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
// synopsys translate_off
initial
rshift_distance_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rshift_distance_dffe13 <= 5'b0;
else if (clk_en == 1'b1) rshift_distance_dffe13 <= rshift_distance_dffe13_wi;
// synopsys translate_off
initial
rshift_distance_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rshift_distance_dffe14 <= 5'b0;
else if (clk_en == 1'b1) rshift_distance_dffe14 <= rshift_distance_dffe14_wi;
// synopsys translate_off
initial
rshift_distance_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rshift_distance_dffe15 <= 5'b0;
else if (clk_en == 1'b1) rshift_distance_dffe15 <= rshift_distance_dffe15_wi;
// synopsys translate_off
initial
sign_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe31 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe31 <= sign_dffe31_wi;
// synopsys translate_off
initial
sign_out_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_out_dffe5 <= 1'b0;
else if (clk_en == 1'b1) sign_out_dffe5 <= sign_out_dffe5_wi;
// synopsys translate_off
initial
sign_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_res_dffe3 <= 1'b0;
else if (clk_en == 1'b1) sign_res_dffe3 <= sign_res_dffe3_wi;
// synopsys translate_off
initial
sign_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_res_dffe4 <= 1'b0;
else if (clk_en == 1'b1) sign_res_dffe4 <= sign_res_dffe4_wi;
// synopsys translate_off
initial
sign_res_dffe41 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_res_dffe41 <= 1'b0;
else if (clk_en == 1'b1) sign_res_dffe41 <= sign_res_dffe41_wi;
// synopsys translate_off
initial
sticky_bit_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe1 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
// synopsys translate_off
initial
sticky_bit_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe2 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
// synopsys translate_off
initial
sticky_bit_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe21 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
// synopsys translate_off
initial
sticky_bit_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe23 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe23 <= sticky_bit_dffe23_wi;
// synopsys translate_off
initial
sticky_bit_dffe27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe27 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe27 <= sticky_bit_dffe27_wi;
// synopsys translate_off
initial
sticky_bit_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe3 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
// synopsys translate_off
initial
sticky_bit_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe31 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
// synopsys translate_off
initial
zero_man_sign_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_man_sign_dffe2 <= 1'b0;
else if (clk_en == 1'b1) zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
// synopsys translate_off
initial
zero_man_sign_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_man_sign_dffe21 <= 1'b0;
else if (clk_en == 1'b1) zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
// synopsys translate_off
initial
zero_man_sign_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_man_sign_dffe23 <= 1'b0;
else if (clk_en == 1'b1) zero_man_sign_dffe23 <= zero_man_sign_dffe23_wi;
// synopsys translate_off
initial
zero_man_sign_dffe27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_man_sign_dffe27 <= 1'b0;
else if (clk_en == 1'b1) zero_man_sign_dffe27 <= zero_man_sign_dffe27_wi;
lpm_add_sub add_sub1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(aligned_dataa_exp_w),
.datab(aligned_datab_exp_w),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "SUB",
add_sub1.lpm_pipeline = 1,
add_sub1.lpm_representation = "SIGNED",
add_sub1.lpm_width = 9,
add_sub1.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(aligned_datab_exp_w),
.datab(aligned_dataa_exp_w),
.overflow(),
.result(wire_add_sub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub2.lpm_direction = "SUB",
add_sub2.lpm_pipeline = 1,
add_sub2.lpm_representation = "SIGNED",
add_sub2.lpm_width = 9,
add_sub2.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub3
(
.cout(),
.dataa(sticky_bit_cnt_dataa_w),
.datab(sticky_bit_cnt_datab_w),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_representation = "SIGNED",
add_sub3.lpm_width = 6,
add_sub3.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub4
(
.cout(),
.dataa(exp_adjustment_add_sub_dataa_w),
.datab(exp_adjustment_add_sub_datab_w),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "ADD",
add_sub4.lpm_representation = "SIGNED",
add_sub4.lpm_width = 9,
add_sub4.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_adjustment2_add_sub_dataa_w),
.datab(exp_adjustment2_add_sub_datab_w),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_direction = "ADD",
add_sub5.lpm_pipeline = 1,
add_sub5.lpm_representation = "SIGNED",
add_sub5.lpm_width = 9,
add_sub5.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub6
(
.cout(),
.dataa(exp_res_rounding_adder_dataa_w),
.datab(exp_rounding_adjustment_w),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_direction = "ADD",
add_sub6.lpm_representation = "SIGNED",
add_sub6.lpm_width = 9,
add_sub6.lpm_type = "lpm_add_sub";
lpm_add_sub man_2comp_res_lower
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(borrow_w),
.clken(clk_en),
.clock(clock),
.cout(wire_man_2comp_res_lower_cout),
.dataa(man_2comp_res_dataa_w[13:0]),
.datab(man_2comp_res_datab_w[13:0]),
.overflow(),
.result(wire_man_2comp_res_lower_result));
defparam
man_2comp_res_lower.lpm_pipeline = 1,
man_2comp_res_lower.lpm_representation = "SIGNED",
man_2comp_res_lower.lpm_width = 14,
man_2comp_res_lower.lpm_type = "lpm_add_sub";
lpm_add_sub man_2comp_res_upper0
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b0),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_2comp_res_dataa_w[27:14]),
.datab(man_2comp_res_datab_w[27:14]),
.overflow(),
.result(wire_man_2comp_res_upper0_result));
defparam
man_2comp_res_upper0.lpm_pipeline = 1,
man_2comp_res_upper0.lpm_representation = "SIGNED",
man_2comp_res_upper0.lpm_width = 14,
man_2comp_res_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub man_2comp_res_upper1
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b1),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_2comp_res_dataa_w[27:14]),
.datab(man_2comp_res_datab_w[27:14]),
.overflow(),
.result(wire_man_2comp_res_upper1_result));
defparam
man_2comp_res_upper1.lpm_pipeline = 1,
man_2comp_res_upper1.lpm_representation = "SIGNED",
man_2comp_res_upper1.lpm_width = 14,
man_2comp_res_upper1.lpm_type = "lpm_add_sub";
lpm_add_sub man_add_sub_lower
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(borrow_w),
.clken(clk_en),
.clock(clock),
.cout(wire_man_add_sub_lower_cout),
.dataa(man_add_sub_dataa_w[13:0]),
.datab(man_add_sub_datab_w[13:0]),
.overflow(),
.result(wire_man_add_sub_lower_result));
defparam
man_add_sub_lower.lpm_pipeline = 1,
man_add_sub_lower.lpm_representation = "SIGNED",
man_add_sub_lower.lpm_width = 14,
man_add_sub_lower.lpm_type = "lpm_add_sub";
lpm_add_sub man_add_sub_upper0
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b0),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_add_sub_dataa_w[27:14]),
.datab(man_add_sub_datab_w[27:14]),
.overflow(),
.result(wire_man_add_sub_upper0_result));
defparam
man_add_sub_upper0.lpm_pipeline = 1,
man_add_sub_upper0.lpm_representation = "SIGNED",
man_add_sub_upper0.lpm_width = 14,
man_add_sub_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub man_add_sub_upper1
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b1),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_add_sub_dataa_w[27:14]),
.datab(man_add_sub_datab_w[27:14]),
.overflow(),
.result(wire_man_add_sub_upper1_result));
defparam
man_add_sub_upper1.lpm_pipeline = 1,
man_add_sub_upper1.lpm_representation = "SIGNED",
man_add_sub_upper1.lpm_width = 14,
man_add_sub_upper1.lpm_type = "lpm_add_sub";
lpm_add_sub man_res_rounding_add_sub_lower
(
.cout(wire_man_res_rounding_add_sub_lower_cout),
.dataa(man_intermediate_res_w[12:0]),
.datab(man_res_rounding_add_sub_datab_w[12:0]),
.overflow(),
.result(wire_man_res_rounding_add_sub_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_res_rounding_add_sub_lower.lpm_direction = "ADD",
man_res_rounding_add_sub_lower.lpm_representation = "SIGNED",
man_res_rounding_add_sub_lower.lpm_width = 13,
man_res_rounding_add_sub_lower.lpm_type = "lpm_add_sub";
lpm_add_sub man_res_rounding_add_sub_upper1
(
.cin(1'b1),
.cout(),
.dataa(man_intermediate_res_w[25:13]),
.datab(man_res_rounding_add_sub_datab_w[25:13]),
.overflow(),
.result(wire_man_res_rounding_add_sub_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_res_rounding_add_sub_upper1.lpm_direction = "ADD",
man_res_rounding_add_sub_upper1.lpm_representation = "SIGNED",
man_res_rounding_add_sub_upper1.lpm_width = 13,
man_res_rounding_add_sub_upper1.lpm_type = "lpm_add_sub";
lpm_compare trailing_zeros_limit_comparator
(
.aeb(),
.agb(wire_trailing_zeros_limit_comparator_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(sticky_bit_cnt_res_w),
.datab(trailing_zeros_limit_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
trailing_zeros_limit_comparator.lpm_representation = "SIGNED",
trailing_zeros_limit_comparator.lpm_width = 6,
trailing_zeros_limit_comparator.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
add_sub_dffe11_wi = add_sub,
add_sub_dffe11_wo = add_sub_dffe11_wi,
add_sub_dffe12_wi = add_sub_dffe11_wo,
add_sub_dffe12_wo = add_sub_dffe12,
add_sub_dffe13_wi = add_sub_dffe12_wo,
add_sub_dffe13_wo = add_sub_dffe13,
add_sub_dffe14_wi = add_sub_dffe13_wo,
add_sub_dffe14_wo = add_sub_dffe14,
add_sub_dffe15_wi = add_sub_dffe14_wo,
add_sub_dffe15_wo = add_sub_dffe15,
add_sub_dffe1_wi = add_sub_dffe15_wo,
add_sub_dffe1_wo = add_sub_dffe1,
add_sub_dffe25_wi = add_sub_w2,
add_sub_dffe25_wo = add_sub_dffe25_wi,
add_sub_w2 = (((((dataa_sign_dffe1_wo & (~ datab_sign_dffe1_wo)) & (~ add_sub_dffe1_wo)) | (((~ dataa_sign_dffe1_wo) & (~ datab_sign_dffe1_wo)) & add_sub_dffe1_wo)) | (((~ dataa_sign_dffe1_wo) & datab_sign_dffe1_wo) & (~ add_sub_dffe1_wo))) | ((dataa_sign_dffe1_wo & datab_sign_dffe1_wo) & add_sub_dffe1_wo)),
adder_upper_w = man_intermediate_res_w[25:13],
aligned_dataa_exp_dffe12_wi = aligned_dataa_exp_w,
aligned_dataa_exp_dffe12_wo = aligned_dataa_exp_dffe12,
aligned_dataa_exp_dffe13_wi = aligned_dataa_exp_dffe12_wo,
aligned_dataa_exp_dffe13_wo = aligned_dataa_exp_dffe13,
aligned_dataa_exp_dffe14_wi = aligned_dataa_exp_dffe13_wo,
aligned_dataa_exp_dffe14_wo = aligned_dataa_exp_dffe14,
aligned_dataa_exp_dffe15_wi = aligned_dataa_exp_dffe14_wo,
aligned_dataa_exp_dffe15_wo = aligned_dataa_exp_dffe15,
aligned_dataa_exp_w = {1'b0, ({8{(~ input_dataa_denormal_dffe11_wo)}} & dataa_dffe11_wo[30:23])},
aligned_dataa_man_dffe12_wi = aligned_dataa_man_w[25:2],
aligned_dataa_man_dffe12_wo = aligned_dataa_man_dffe12,
aligned_dataa_man_dffe13_wi = aligned_dataa_man_dffe12_wo,
aligned_dataa_man_dffe13_wo = aligned_dataa_man_dffe13,
aligned_dataa_man_dffe14_wi = aligned_dataa_man_dffe13_wo,
aligned_dataa_man_dffe14_wo = aligned_dataa_man_dffe14,
aligned_dataa_man_dffe15_w = {aligned_dataa_man_dffe15_wo, {2{1'b0}}},
aligned_dataa_man_dffe15_wi = aligned_dataa_man_dffe14_wo,
aligned_dataa_man_dffe15_wo = aligned_dataa_man_dffe15,
aligned_dataa_man_w = {(((~ input_dataa_infinite_dffe11_wo) & (~ input_dataa_denormal_dffe11_wo)) & (~ input_dataa_zero_dffe11_wo)), ({23{(~ input_dataa_denormal_dffe11_wo)}} & dataa_dffe11_wo[22:0]), {2{1'b0}}},
aligned_dataa_sign_dffe12_wi = aligned_dataa_sign_w,
aligned_dataa_sign_dffe12_wo = aligned_dataa_sign_dffe12,
aligned_dataa_sign_dffe13_wi = aligned_dataa_sign_dffe12_wo,
aligned_dataa_sign_dffe13_wo = aligned_dataa_sign_dffe13,
aligned_dataa_sign_dffe14_wi = aligned_dataa_sign_dffe13_wo,
aligned_dataa_sign_dffe14_wo = aligned_dataa_sign_dffe14,
aligned_dataa_sign_dffe15_wi = aligned_dataa_sign_dffe14_wo,
aligned_dataa_sign_dffe15_wo = aligned_dataa_sign_dffe15,
aligned_dataa_sign_w = dataa_dffe11_wo[31],
aligned_datab_exp_dffe12_wi = aligned_datab_exp_w,
aligned_datab_exp_dffe12_wo = aligned_datab_exp_dffe12,
aligned_datab_exp_dffe13_wi = aligned_datab_exp_dffe12_wo,
aligned_datab_exp_dffe13_wo = aligned_datab_exp_dffe13,
aligned_datab_exp_dffe14_wi = aligned_datab_exp_dffe13_wo,
aligned_datab_exp_dffe14_wo = aligned_datab_exp_dffe14,
aligned_datab_exp_dffe15_wi = aligned_datab_exp_dffe14_wo,
aligned_datab_exp_dffe15_wo = aligned_datab_exp_dffe15,
aligned_datab_exp_w = {1'b0, ({8{(~ input_datab_denormal_dffe11_wo)}} & datab_dffe11_wo[30:23])},
aligned_datab_man_dffe12_wi = aligned_datab_man_w[25:2],
aligned_datab_man_dffe12_wo = aligned_datab_man_dffe12,
aligned_datab_man_dffe13_wi = aligned_datab_man_dffe12_wo,
aligned_datab_man_dffe13_wo = aligned_datab_man_dffe13,
aligned_datab_man_dffe14_wi = aligned_datab_man_dffe13_wo,
aligned_datab_man_dffe14_wo = aligned_datab_man_dffe14,
aligned_datab_man_dffe15_w = {aligned_datab_man_dffe15_wo, {2{1'b0}}},
aligned_datab_man_dffe15_wi = aligned_datab_man_dffe14_wo,
aligned_datab_man_dffe15_wo = aligned_datab_man_dffe15,
aligned_datab_man_w = {(((~ input_datab_infinite_dffe11_wo) & (~ input_datab_denormal_dffe11_wo)) & (~ input_datab_zero_dffe11_wo)), ({23{(~ input_datab_denormal_dffe11_wo)}} & datab_dffe11_wo[22:0]), {2{1'b0}}},
aligned_datab_sign_dffe12_wi = aligned_datab_sign_w,
aligned_datab_sign_dffe12_wo = aligned_datab_sign_dffe12,
aligned_datab_sign_dffe13_wi = aligned_datab_sign_dffe12_wo,
aligned_datab_sign_dffe13_wo = aligned_datab_sign_dffe13,
aligned_datab_sign_dffe14_wi = aligned_datab_sign_dffe13_wo,
aligned_datab_sign_dffe14_wo = aligned_datab_sign_dffe14,
aligned_datab_sign_dffe15_wi = aligned_datab_sign_dffe14_wo,
aligned_datab_sign_dffe15_wo = aligned_datab_sign_dffe15,
aligned_datab_sign_w = datab_dffe11_wo[31],
borrow_w = ((~ sticky_bit_dffe1_wo) & (~ add_sub_w2)),
both_inputs_are_infinite_dffe1_wi = (input_dataa_infinite_dffe15_wo & input_datab_infinite_dffe15_wo),
both_inputs_are_infinite_dffe1_wo = both_inputs_are_infinite_dffe1,
both_inputs_are_infinite_dffe25_wi = both_inputs_are_infinite_dffe1_wo,
both_inputs_are_infinite_dffe25_wo = both_inputs_are_infinite_dffe25_wi,
clk_en = 1'b1,
data_exp_dffe1_wi = (({8{(~ exp_amb_mux_dffe15_wo)}} & aligned_dataa_exp_dffe15_wo[7:0]) | ({8{exp_amb_mux_dffe15_wo}} & aligned_datab_exp_dffe15_wo[7:0])),
data_exp_dffe1_wo = data_exp_dffe1,
dataa_dffe11_wi = dataa,
dataa_dffe11_wo = dataa_dffe11_wi,
dataa_man_dffe1_wi = (({26{(~ exp_amb_mux_dffe15_wo)}} & aligned_dataa_man_dffe15_w) | ({26{exp_amb_mux_dffe15_wo}} & wire_rbarrel_shift_result)),
dataa_man_dffe1_wo = dataa_man_dffe1,
dataa_sign_dffe1_wi = aligned_dataa_sign_dffe15_wo,
dataa_sign_dffe1_wo = dataa_sign_dffe1,
dataa_sign_dffe25_wi = dataa_sign_dffe1_wo,
dataa_sign_dffe25_wo = dataa_sign_dffe25_wi,
datab_dffe11_wi = datab,
datab_dffe11_wo = datab_dffe11_wi,
datab_man_dffe1_wi = (({26{(~ exp_amb_mux_dffe15_wo)}} & wire_rbarrel_shift_result) | ({26{exp_amb_mux_dffe15_wo}} & aligned_datab_man_dffe15_w)),
datab_man_dffe1_wo = datab_man_dffe1,
datab_sign_dffe1_wi = aligned_datab_sign_dffe15_wo,
datab_sign_dffe1_wo = datab_sign_dffe1,
denormal_flag_w = ((((~ force_nan_w) & (~ force_infinity_w)) & (~ force_zero_w)) & denormal_res_dffe4_wo),
denormal_res_dffe32_wi = denormal_result_w,
denormal_res_dffe32_wo = denormal_res_dffe32_wi,
denormal_res_dffe33_wi = denormal_res_dffe32_wo,
denormal_res_dffe33_wo = denormal_res_dffe33_wi,
denormal_res_dffe3_wi = denormal_res_dffe33_wo,
denormal_res_dffe3_wo = denormal_res_dffe3,
denormal_res_dffe41_wi = denormal_res_dffe42_wo,
denormal_res_dffe41_wo = denormal_res_dffe41,
denormal_res_dffe42_wi = denormal_res_dffe3_wo,
denormal_res_dffe42_wo = denormal_res_dffe42_wi,
denormal_res_dffe4_wi = denormal_res_dffe41_wo,
denormal_res_dffe4_wo = denormal_res_dffe4,
denormal_result_w = ((~ exp_res_not_zero_w[8]) | exp_adjustment2_add_sub_w[8]),
exp_a_all_one_w = {(dataa[30] & exp_a_all_one_w[6]), (dataa[29] & exp_a_all_one_w[5]), (dataa[28] & exp_a_all_one_w[4]), (dataa[27] & exp_a_all_one_w[3]), (dataa[26] & exp_a_all_one_w[2]), (dataa[25] & exp_a_all_one_w[1]), (dataa[24] & exp_a_all_one_w[0]), dataa[23]},
exp_a_not_zero_w = {(dataa[30] | exp_a_not_zero_w[6]), (dataa[29] | exp_a_not_zero_w[5]), (dataa[28] | exp_a_not_zero_w[4]), (dataa[27] | exp_a_not_zero_w[3]), (dataa[26] | exp_a_not_zero_w[2]), (dataa[25] | exp_a_not_zero_w[1]), (dataa[24] | exp_a_not_zero_w[0]), dataa[23]},
exp_adj_0pads = {7{1'b0}},
exp_adj_dffe21_wi = (({2{man_add_sub_res_mag_dffe27_wo[26]}} & exp_adjust_by_add2) | ({2{(~ man_add_sub_res_mag_dffe27_wo[26])}} & exp_adjust_by_add1)),
exp_adj_dffe21_wo = exp_adj_dffe21,
exp_adj_dffe23_wi = exp_adj_dffe21_wo,
exp_adj_dffe23_wo = exp_adj_dffe23,
exp_adj_dffe26_wi = exp_adj_dffe23_wo,
exp_adj_dffe26_wo = exp_adj_dffe26_wi,
exp_adjust_by_add1 = 2'b01,
exp_adjust_by_add2 = 2'b10,
exp_adjustment2_add_sub_dataa_w = exp_value,
exp_adjustment2_add_sub_datab_w = exp_adjustment_add_sub_w,
exp_adjustment2_add_sub_w = wire_add_sub5_result,
exp_adjustment_add_sub_dataa_w = {priority_encoder_1pads_w, wire_leading_zeroes_cnt_q},
exp_adjustment_add_sub_datab_w = {exp_adj_0pads, exp_adj_dffe26_wo},
exp_adjustment_add_sub_w = wire_add_sub4_result,
exp_all_ones_w = {8{1'b1}},
exp_all_zeros_w = {8{1'b0}},
exp_amb_mux_dffe13_wi = exp_amb_mux_w,
exp_amb_mux_dffe13_wo = exp_amb_mux_dffe13,
exp_amb_mux_dffe14_wi = exp_amb_mux_dffe13_wo,
exp_amb_mux_dffe14_wo = exp_amb_mux_dffe14,
exp_amb_mux_dffe15_wi = exp_amb_mux_dffe14_wo,
exp_amb_mux_dffe15_wo = exp_amb_mux_dffe15,
exp_amb_mux_w = exp_amb_w[8],
exp_amb_w = wire_add_sub1_result,
exp_b_all_one_w = {(datab[30] & exp_b_all_one_w[6]), (datab[29] & exp_b_all_one_w[5]), (datab[28] & exp_b_all_one_w[4]), (datab[27] & exp_b_all_one_w[3]), (datab[26] & exp_b_all_one_w[2]), (datab[25] & exp_b_all_one_w[1]), (datab[24] & exp_b_all_one_w[0]), datab[23]},
exp_b_not_zero_w = {(datab[30] | exp_b_not_zero_w[6]), (datab[29] | exp_b_not_zero_w[5]), (datab[28] | exp_b_not_zero_w[4]), (datab[27] | exp_b_not_zero_w[3]), (datab[26] | exp_b_not_zero_w[2]), (datab[25] | exp_b_not_zero_w[1]), (datab[24] | exp_b_not_zero_w[0]), datab[23]},
exp_bma_w = wire_add_sub2_result,
exp_diff_abs_exceed_max_w = {(exp_diff_abs_exceed_max_w[1] | exp_diff_abs_w[7]), (exp_diff_abs_exceed_max_w[0] | exp_diff_abs_w[6]), exp_diff_abs_w[5]},
exp_diff_abs_max_w = {5{1'b1}},
exp_diff_abs_w = (({8{(~ exp_amb_mux_w)}} & exp_amb_w[7:0]) | ({8{exp_amb_mux_w}} & exp_bma_w[7:0])),
exp_intermediate_res_dffe41_wi = exp_intermediate_res_dffe42_wo,
exp_intermediate_res_dffe41_wo = exp_intermediate_res_dffe41,
exp_intermediate_res_dffe42_wi = exp_intermediate_res_w,
exp_intermediate_res_dffe42_wo = exp_intermediate_res_dffe42_wi,
exp_intermediate_res_w = exp_res_dffe3_wo,
exp_out_dffe5_wi = (({8{force_nan_w}} & exp_all_ones_w) | ({8{(~ force_nan_w)}} & (({8{force_infinity_w}} & exp_all_ones_w) | ({8{(~ force_infinity_w)}} & (({8{(force_zero_w | denormal_flag_w)}} & exp_all_zeros_w) | ({8{(~ (force_zero_w | denormal_flag_w))}} & exp_res_dffe4_wo)))))),
exp_out_dffe5_wo = exp_out_dffe5,
exp_res_dffe21_wi = exp_res_dffe27_wo,
exp_res_dffe21_wo = exp_res_dffe21,
exp_res_dffe22_wi = exp_res_dffe2_wo,
exp_res_dffe22_wo = exp_res_dffe22_wi,
exp_res_dffe23_wi = exp_res_dffe21_wo,
exp_res_dffe23_wo = exp_res_dffe23,
exp_res_dffe25_wi = data_exp_dffe1_wo,
exp_res_dffe25_wo = exp_res_dffe25_wi,
exp_res_dffe26_wi = exp_res_dffe23_wo,
exp_res_dffe26_wo = exp_res_dffe26_wi,
exp_res_dffe27_wi = exp_res_dffe22_wo,
exp_res_dffe27_wo = exp_res_dffe27,
exp_res_dffe2_wi = exp_res_dffe25_wo,
exp_res_dffe2_wo = exp_res_dffe2,
exp_res_dffe32_wi = ({8{(~ denormal_result_w)}} & exp_adjustment2_add_sub_w[7:0]),
exp_res_dffe32_wo = exp_res_dffe32_wi,
exp_res_dffe33_wi = exp_res_dffe32_wo,
exp_res_dffe33_wo = exp_res_dffe33_wi,
exp_res_dffe3_wi = exp_res_dffe33_wo,
exp_res_dffe3_wo = exp_res_dffe3,
exp_res_dffe4_wi = exp_rounded_res_w,
exp_res_dffe4_wo = exp_res_dffe4,
exp_res_max_w = {(exp_res_max_w[6] & exp_adjustment2_add_sub_w[7]), (exp_res_max_w[5] & exp_adjustment2_add_sub_w[6]), (exp_res_max_w[4] & exp_adjustment2_add_sub_w[5]), (exp_res_max_w[3] & exp_adjustment2_add_sub_w[4]), (exp_res_max_w[2] & exp_adjustment2_add_sub_w[3]), (exp_res_max_w[1] & exp_adjustment2_add_sub_w[2]), (exp_res_max_w[0] & exp_adjustment2_add_sub_w[1]), exp_adjustment2_add_sub_w[0]},
exp_res_not_zero_w = {(exp_res_not_zero_w[7] | exp_adjustment2_add_sub_w[8]), (exp_res_not_zero_w[6] | exp_adjustment2_add_sub_w[7]), (exp_res_not_zero_w[5] | exp_adjustment2_add_sub_w[6]), (exp_res_not_zero_w[4] | exp_adjustment2_add_sub_w[5]), (exp_res_not_zero_w[3] | exp_adjustment2_add_sub_w[4]), (exp_res_not_zero_w[2] | exp_adjustment2_add_sub_w[3]), (exp_res_not_zero_w[1] | exp_adjustment2_add_sub_w[2]), (exp_res_not_zero_w[0] | exp_adjustment2_add_sub_w[1]), exp_adjustment2_add_sub_w[0]},
exp_res_rounding_adder_dataa_w = {1'b0, exp_intermediate_res_dffe41_wo},
exp_res_rounding_adder_w = wire_add_sub6_result,
exp_rounded_res_infinity_w = exp_rounded_res_max_w[7],
exp_rounded_res_max_w = {(exp_rounded_res_max_w[6] & exp_rounded_res_w[7]), (exp_rounded_res_max_w[5] & exp_rounded_res_w[6]), (exp_rounded_res_max_w[4] & exp_rounded_res_w[5]), (exp_rounded_res_max_w[3] & exp_rounded_res_w[4]), (exp_rounded_res_max_w[2] & exp_rounded_res_w[3]), (exp_rounded_res_max_w[1] & exp_rounded_res_w[2]), (exp_rounded_res_max_w[0] & exp_rounded_res_w[1]), exp_rounded_res_w[0]},
exp_rounded_res_w = exp_res_rounding_adder_w[7:0],
exp_rounding_adjustment_w = {{8{1'b0}}, man_res_rounding_add_sub_w[24]},
exp_value = {1'b0, exp_res_dffe26_wo},
force_infinity_w = ((input_is_infinite_dffe4_wo | rounded_res_infinity_dffe4_wo) | infinite_res_dffe4_wo),
force_nan_w = (infinity_magnitude_sub_dffe4_wo | input_is_nan_dffe4_wo),
force_zero_w = (~ man_res_is_not_zero_dffe4_wo),
guard_bit_dffe3_wo = man_res_w3[0],
infinite_output_sign_dffe1_wi = (((~ input_datab_infinite_dffe15_wo) & aligned_dataa_sign_dffe15_wo) | (input_datab_infinite_dffe15_wo & (~ (aligned_datab_sign_dffe15_wo ^ add_sub_dffe15_wo)))),
infinite_output_sign_dffe1_wo = infinite_output_sign_dffe1,
infinite_output_sign_dffe21_wi = infinite_output_sign_dffe27_wo,
infinite_output_sign_dffe21_wo = infinite_output_sign_dffe21,
infinite_output_sign_dffe22_wi = infinite_output_sign_dffe2_wo,
infinite_output_sign_dffe22_wo = infinite_output_sign_dffe22_wi,
infinite_output_sign_dffe23_wi = infinite_output_sign_dffe21_wo,
infinite_output_sign_dffe23_wo = infinite_output_sign_dffe23,
infinite_output_sign_dffe25_wi = infinite_output_sign_dffe1_wo,
infinite_output_sign_dffe25_wo = infinite_output_sign_dffe25_wi,
infinite_output_sign_dffe26_wi = infinite_output_sign_dffe23_wo,
infinite_output_sign_dffe26_wo = infinite_output_sign_dffe26_wi,
infinite_output_sign_dffe27_wi = infinite_output_sign_dffe22_wo,
infinite_output_sign_dffe27_wo = infinite_output_sign_dffe27,
infinite_output_sign_dffe2_wi = infinite_output_sign_dffe25_wo,
infinite_output_sign_dffe2_wo = infinite_output_sign_dffe2,
infinite_output_sign_dffe31_wi = infinite_output_sign_dffe26_wo,
infinite_output_sign_dffe31_wo = infinite_output_sign_dffe31,
infinite_output_sign_dffe32_wi = infinite_output_sign_dffe31_wo,
infinite_output_sign_dffe32_wo = infinite_output_sign_dffe32_wi,
infinite_output_sign_dffe33_wi = infinite_output_sign_dffe32_wo,
infinite_output_sign_dffe33_wo = infinite_output_sign_dffe33_wi,
infinite_output_sign_dffe3_wi = infinite_output_sign_dffe33_wo,
infinite_output_sign_dffe3_wo = infinite_output_sign_dffe3,
infinite_output_sign_dffe41_wi = infinite_output_sign_dffe42_wo,
infinite_output_sign_dffe41_wo = infinite_output_sign_dffe41,
infinite_output_sign_dffe42_wi = infinite_output_sign_dffe3_wo,
infinite_output_sign_dffe42_wo = infinite_output_sign_dffe42_wi,
infinite_output_sign_dffe4_wi = infinite_output_sign_dffe41_wo,
infinite_output_sign_dffe4_wo = infinite_output_sign_dffe4,
infinite_res_dff32_wi = (exp_res_max_w[7] & (~ exp_adjustment2_add_sub_w[8])),
infinite_res_dff32_wo = infinite_res_dff32_wi,
infinite_res_dff33_wi = infinite_res_dff32_wo,
infinite_res_dff33_wo = infinite_res_dff33_wi,
infinite_res_dffe3_wi = infinite_res_dff33_wo,
infinite_res_dffe3_wo = infinite_res_dffe3,
infinite_res_dffe41_wi = infinite_res_dffe42_wo,
infinite_res_dffe41_wo = infinite_res_dffe41,
infinite_res_dffe42_wi = infinite_res_dffe3_wo,
infinite_res_dffe42_wo = infinite_res_dffe42_wi,
infinite_res_dffe4_wi = infinite_res_dffe41_wo,
infinite_res_dffe4_wo = infinite_res_dffe4,
infinity_magnitude_sub_dffe21_wi = infinity_magnitude_sub_dffe27_wo,
infinity_magnitude_sub_dffe21_wo = infinity_magnitude_sub_dffe21,
infinity_magnitude_sub_dffe22_wi = infinity_magnitude_sub_dffe2_wo,
infinity_magnitude_sub_dffe22_wo = infinity_magnitude_sub_dffe22_wi,
infinity_magnitude_sub_dffe23_wi = infinity_magnitude_sub_dffe21_wo,
infinity_magnitude_sub_dffe23_wo = infinity_magnitude_sub_dffe23,
infinity_magnitude_sub_dffe26_wi = infinity_magnitude_sub_dffe23_wo,
infinity_magnitude_sub_dffe26_wo = infinity_magnitude_sub_dffe26_wi,
infinity_magnitude_sub_dffe27_wi = infinity_magnitude_sub_dffe22_wo,
infinity_magnitude_sub_dffe27_wo = infinity_magnitude_sub_dffe27,
infinity_magnitude_sub_dffe2_wi = ((~ add_sub_dffe25_wo) & both_inputs_are_infinite_dffe25_wo),
infinity_magnitude_sub_dffe2_wo = infinity_magnitude_sub_dffe2,
infinity_magnitude_sub_dffe31_wi = infinity_magnitude_sub_dffe26_wo,
infinity_magnitude_sub_dffe31_wo = infinity_magnitude_sub_dffe31,
infinity_magnitude_sub_dffe32_wi = infinity_magnitude_sub_dffe31_wo,
infinity_magnitude_sub_dffe32_wo = infinity_magnitude_sub_dffe32_wi,
infinity_magnitude_sub_dffe33_wi = infinity_magnitude_sub_dffe32_wo,
infinity_magnitude_sub_dffe33_wo = infinity_magnitude_sub_dffe33_wi,
infinity_magnitude_sub_dffe3_wi = infinity_magnitude_sub_dffe33_wo,
infinity_magnitude_sub_dffe3_wo = infinity_magnitude_sub_dffe3,
infinity_magnitude_sub_dffe41_wi = infinity_magnitude_sub_dffe42_wo,
infinity_magnitude_sub_dffe41_wo = infinity_magnitude_sub_dffe41,
infinity_magnitude_sub_dffe42_wi = infinity_magnitude_sub_dffe3_wo,
infinity_magnitude_sub_dffe42_wo = infinity_magnitude_sub_dffe42_wi,
infinity_magnitude_sub_dffe4_wi = infinity_magnitude_sub_dffe41_wo,
infinity_magnitude_sub_dffe4_wo = infinity_magnitude_sub_dffe4,
input_dataa_denormal_dffe11_wi = input_dataa_denormal_w,
input_dataa_denormal_dffe11_wo = input_dataa_denormal_dffe11_wi,
input_dataa_denormal_w = ((~ exp_a_not_zero_w[7]) & man_a_not_zero_w[22]),
input_dataa_infinite_dffe11_wi = input_dataa_infinite_w,
input_dataa_infinite_dffe11_wo = input_dataa_infinite_dffe11_wi,
input_dataa_infinite_dffe12_wi = input_dataa_infinite_dffe11_wo,
input_dataa_infinite_dffe12_wo = input_dataa_infinite_dffe12,
input_dataa_infinite_dffe13_wi = input_dataa_infinite_dffe12_wo,
input_dataa_infinite_dffe13_wo = input_dataa_infinite_dffe13,
input_dataa_infinite_dffe14_wi = input_dataa_infinite_dffe13_wo,
input_dataa_infinite_dffe14_wo = input_dataa_infinite_dffe14,
input_dataa_infinite_dffe15_wi = input_dataa_infinite_dffe14_wo,
input_dataa_infinite_dffe15_wo = input_dataa_infinite_dffe15,
input_dataa_infinite_w = (exp_a_all_one_w[7] & (~ man_a_not_zero_w[22])),
input_dataa_nan_dffe11_wi = input_dataa_nan_w,
input_dataa_nan_dffe11_wo = input_dataa_nan_dffe11_wi,
input_dataa_nan_dffe12_wi = input_dataa_nan_dffe11_wo,
input_dataa_nan_dffe12_wo = input_dataa_nan_dffe12,
input_dataa_nan_w = (exp_a_all_one_w[7] & man_a_not_zero_w[22]),
input_dataa_zero_dffe11_wi = input_dataa_zero_w,
input_dataa_zero_dffe11_wo = input_dataa_zero_dffe11_wi,
input_dataa_zero_w = ((~ exp_a_not_zero_w[7]) & (~ man_a_not_zero_w[22])),
input_datab_denormal_dffe11_wi = input_datab_denormal_w,
input_datab_denormal_dffe11_wo = input_datab_denormal_dffe11_wi,
input_datab_denormal_w = ((~ exp_b_not_zero_w[7]) & man_b_not_zero_w[22]),
input_datab_infinite_dffe11_wi = input_datab_infinite_w,
input_datab_infinite_dffe11_wo = input_datab_infinite_dffe11_wi,
input_datab_infinite_dffe12_wi = input_datab_infinite_dffe11_wo,
input_datab_infinite_dffe12_wo = input_datab_infinite_dffe12,
input_datab_infinite_dffe13_wi = input_datab_infinite_dffe12_wo,
input_datab_infinite_dffe13_wo = input_datab_infinite_dffe13,
input_datab_infinite_dffe14_wi = input_datab_infinite_dffe13_wo,
input_datab_infinite_dffe14_wo = input_datab_infinite_dffe14,
input_datab_infinite_dffe15_wi = input_datab_infinite_dffe14_wo,
input_datab_infinite_dffe15_wo = input_datab_infinite_dffe15,
input_datab_infinite_w = (exp_b_all_one_w[7] & (~ man_b_not_zero_w[22])),
input_datab_nan_dffe11_wi = input_datab_nan_w,
input_datab_nan_dffe11_wo = input_datab_nan_dffe11_wi,
input_datab_nan_dffe12_wi = input_datab_nan_dffe11_wo,
input_datab_nan_dffe12_wo = input_datab_nan_dffe12,
input_datab_nan_w = (exp_b_all_one_w[7] & man_b_not_zero_w[22]),
input_datab_zero_dffe11_wi = input_datab_zero_w,
input_datab_zero_dffe11_wo = input_datab_zero_dffe11_wi,
input_datab_zero_w = ((~ exp_b_not_zero_w[7]) & (~ man_b_not_zero_w[22])),
input_is_infinite_dffe1_wi = (input_dataa_infinite_dffe15_wo | input_datab_infinite_dffe15_wo),
input_is_infinite_dffe1_wo = input_is_infinite_dffe1,
input_is_infinite_dffe21_wi = input_is_infinite_dffe27_wo,
input_is_infinite_dffe21_wo = input_is_infinite_dffe21,
input_is_infinite_dffe22_wi = input_is_infinite_dffe2_wo,
input_is_infinite_dffe22_wo = input_is_infinite_dffe22_wi,
input_is_infinite_dffe23_wi = input_is_infinite_dffe21_wo,
input_is_infinite_dffe23_wo = input_is_infinite_dffe23,
input_is_infinite_dffe25_wi = input_is_infinite_dffe1_wo,
input_is_infinite_dffe25_wo = input_is_infinite_dffe25_wi,
input_is_infinite_dffe26_wi = input_is_infinite_dffe23_wo,
input_is_infinite_dffe26_wo = input_is_infinite_dffe26_wi,
input_is_infinite_dffe27_wi = input_is_infinite_dffe22_wo,
input_is_infinite_dffe27_wo = input_is_infinite_dffe27,
input_is_infinite_dffe2_wi = input_is_infinite_dffe25_wo,
input_is_infinite_dffe2_wo = input_is_infinite_dffe2,
input_is_infinite_dffe31_wi = input_is_infinite_dffe26_wo,
input_is_infinite_dffe31_wo = input_is_infinite_dffe31,
input_is_infinite_dffe32_wi = input_is_infinite_dffe31_wo,
input_is_infinite_dffe32_wo = input_is_infinite_dffe32_wi,
input_is_infinite_dffe33_wi = input_is_infinite_dffe32_wo,
input_is_infinite_dffe33_wo = input_is_infinite_dffe33_wi,
input_is_infinite_dffe3_wi = input_is_infinite_dffe33_wo,
input_is_infinite_dffe3_wo = input_is_infinite_dffe3,
input_is_infinite_dffe41_wi = input_is_infinite_dffe42_wo,
input_is_infinite_dffe41_wo = input_is_infinite_dffe41,
input_is_infinite_dffe42_wi = input_is_infinite_dffe3_wo,
input_is_infinite_dffe42_wo = input_is_infinite_dffe42_wi,
input_is_infinite_dffe4_wi = input_is_infinite_dffe41_wo,
input_is_infinite_dffe4_wo = input_is_infinite_dffe4,
input_is_nan_dffe13_wi = (input_dataa_nan_dffe12_wo | input_datab_nan_dffe12_wo),
input_is_nan_dffe13_wo = input_is_nan_dffe13,
input_is_nan_dffe14_wi = input_is_nan_dffe13_wo,
input_is_nan_dffe14_wo = input_is_nan_dffe14,
input_is_nan_dffe15_wi = input_is_nan_dffe14_wo,
input_is_nan_dffe15_wo = input_is_nan_dffe15,
input_is_nan_dffe1_wi = input_is_nan_dffe15_wo,
input_is_nan_dffe1_wo = input_is_nan_dffe1,
input_is_nan_dffe21_wi = input_is_nan_dffe27_wo,
input_is_nan_dffe21_wo = input_is_nan_dffe21,
input_is_nan_dffe22_wi = input_is_nan_dffe2_wo,
input_is_nan_dffe22_wo = input_is_nan_dffe22_wi,
input_is_nan_dffe23_wi = input_is_nan_dffe21_wo,
input_is_nan_dffe23_wo = input_is_nan_dffe23,
input_is_nan_dffe25_wi = input_is_nan_dffe1_wo,
input_is_nan_dffe25_wo = input_is_nan_dffe25_wi,
input_is_nan_dffe26_wi = input_is_nan_dffe23_wo,
input_is_nan_dffe26_wo = input_is_nan_dffe26_wi,
input_is_nan_dffe27_wi = input_is_nan_dffe22_wo,
input_is_nan_dffe27_wo = input_is_nan_dffe27,
input_is_nan_dffe2_wi = input_is_nan_dffe25_wo,
input_is_nan_dffe2_wo = input_is_nan_dffe2,
input_is_nan_dffe31_wi = input_is_nan_dffe26_wo,
input_is_nan_dffe31_wo = input_is_nan_dffe31,
input_is_nan_dffe32_wi = input_is_nan_dffe31_wo,
input_is_nan_dffe32_wo = input_is_nan_dffe32_wi,
input_is_nan_dffe33_wi = input_is_nan_dffe32_wo,
input_is_nan_dffe33_wo = input_is_nan_dffe33_wi,
input_is_nan_dffe3_wi = input_is_nan_dffe33_wo,
input_is_nan_dffe3_wo = input_is_nan_dffe3,
input_is_nan_dffe41_wi = input_is_nan_dffe42_wo,
input_is_nan_dffe41_wo = input_is_nan_dffe41,
input_is_nan_dffe42_wi = input_is_nan_dffe3_wo,
input_is_nan_dffe42_wo = input_is_nan_dffe42_wi,
input_is_nan_dffe4_wi = input_is_nan_dffe41_wo,
input_is_nan_dffe4_wo = input_is_nan_dffe4,
man_2comp_res_dataa_w = {pos_sign_bit_ext, datab_man_dffe1_wo},
man_2comp_res_datab_w = {pos_sign_bit_ext, dataa_man_dffe1_wo},
man_2comp_res_w = {(({14{(~ wire_man_2comp_res_lower_cout)}} & wire_man_2comp_res_upper0_result) | ({14{wire_man_2comp_res_lower_cout}} & wire_man_2comp_res_upper1_result)), wire_man_2comp_res_lower_result},
man_a_not_zero_w = {(dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), (dataa[12] | man_a_not_zero_w[11]), (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_add_sub_dataa_w = {pos_sign_bit_ext, dataa_man_dffe1_wo},
man_add_sub_datab_w = {pos_sign_bit_ext, datab_man_dffe1_wo},
man_add_sub_res_mag_dffe21_wi = man_res_mag_w2,
man_add_sub_res_mag_dffe21_wo = man_add_sub_res_mag_dffe21,
man_add_sub_res_mag_dffe23_wi = man_add_sub_res_mag_dffe21_wo,
man_add_sub_res_mag_dffe23_wo = man_add_sub_res_mag_dffe23,
man_add_sub_res_mag_dffe26_wi = man_add_sub_res_mag_dffe23_wo,
man_add_sub_res_mag_dffe26_wo = man_add_sub_res_mag_dffe26_wi,
man_add_sub_res_mag_dffe27_wi = man_add_sub_res_mag_w2,
man_add_sub_res_mag_dffe27_wo = man_add_sub_res_mag_dffe27,
man_add_sub_res_mag_w2 = (({28{man_add_sub_w[27]}} & man_2comp_res_w) | ({28{(~ man_add_sub_w[27])}} & man_add_sub_w)),
man_add_sub_res_sign_dffe21_wo = man_add_sub_res_sign_dffe21,
man_add_sub_res_sign_dffe23_wi = man_add_sub_res_sign_dffe21_wo,
man_add_sub_res_sign_dffe23_wo = man_add_sub_res_sign_dffe23,
man_add_sub_res_sign_dffe26_wi = man_add_sub_res_sign_dffe23_wo,
man_add_sub_res_sign_dffe26_wo = man_add_sub_res_sign_dffe26_wi,
man_add_sub_res_sign_dffe27_wi = man_add_sub_res_sign_w2,
man_add_sub_res_sign_dffe27_wo = man_add_sub_res_sign_dffe27,
man_add_sub_res_sign_w2 = ((need_complement_dffe22_wo & (~ man_add_sub_w[27])) | ((~ need_complement_dffe22_wo) & man_add_sub_w[27])),
man_add_sub_w = {(({14{(~ wire_man_add_sub_lower_cout)}} & wire_man_add_sub_upper0_result) | ({14{wire_man_add_sub_lower_cout}} & wire_man_add_sub_upper1_result)), wire_man_add_sub_lower_result},
man_all_zeros_w = {23{1'b0}},
man_b_not_zero_w = {(datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), (datab[12] | man_b_not_zero_w[11]), (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
man_dffe31_wo = man_dffe31,
man_intermediate_res_w = {{2{1'b0}}, man_res_w3},
man_leading_zeros_cnt_w = man_leading_zeros_dffe31_wo,
man_leading_zeros_dffe31_wi = (~ wire_leading_zeroes_cnt_q),
man_leading_zeros_dffe31_wo = man_leading_zeros_dffe31,
man_nan_w = 23'b10000000000000000000000,
man_out_dffe5_wi = (({23{force_nan_w}} & man_nan_w) | ({23{(~ force_nan_w)}} & (({23{force_infinity_w}} & man_all_zeros_w) | ({23{(~ force_infinity_w)}} & (({23{(force_zero_w | denormal_flag_w)}} & man_all_zeros_w) | ({23{(~ (force_zero_w | denormal_flag_w))}} & man_res_dffe4_wo)))))),
man_out_dffe5_wo = man_out_dffe5,
man_res_dffe4_wi = man_rounded_res_w,
man_res_dffe4_wo = man_res_dffe4,
man_res_is_not_zero_dffe31_wi = man_res_not_zero_dffe26_wo,
man_res_is_not_zero_dffe31_wo = man_res_is_not_zero_dffe31,
man_res_is_not_zero_dffe32_wi = man_res_is_not_zero_dffe31_wo,
man_res_is_not_zero_dffe32_wo = man_res_is_not_zero_dffe32_wi,
man_res_is_not_zero_dffe33_wi = man_res_is_not_zero_dffe32_wo,
man_res_is_not_zero_dffe33_wo = man_res_is_not_zero_dffe33_wi,
man_res_is_not_zero_dffe3_wi = man_res_is_not_zero_dffe33_wo,
man_res_is_not_zero_dffe3_wo = man_res_is_not_zero_dffe3,
man_res_is_not_zero_dffe41_wi = man_res_is_not_zero_dffe42_wo,
man_res_is_not_zero_dffe41_wo = man_res_is_not_zero_dffe41,
man_res_is_not_zero_dffe42_wi = man_res_is_not_zero_dffe3_wo,
man_res_is_not_zero_dffe42_wo = man_res_is_not_zero_dffe42_wi,
man_res_is_not_zero_dffe4_wi = man_res_is_not_zero_dffe41_wo,
man_res_is_not_zero_dffe4_wo = man_res_is_not_zero_dffe4,
man_res_mag_w2 = (({26{man_add_sub_res_mag_dffe27_wo[26]}} & man_add_sub_res_mag_dffe27_wo[26:1]) | ({26{(~ man_add_sub_res_mag_dffe27_wo[26])}} & man_add_sub_res_mag_dffe27_wo[25:0])),
man_res_not_zero_dffe23_wi = man_res_not_zero_w2[24],
man_res_not_zero_dffe23_wo = man_res_not_zero_dffe23,
man_res_not_zero_dffe26_wi = man_res_not_zero_dffe23_wo,
man_res_not_zero_dffe26_wo = man_res_not_zero_dffe26_wi,
man_res_not_zero_w2 = {(man_res_not_zero_w2[23] | man_add_sub_res_mag_dffe21_wo[25]), (man_res_not_zero_w2[22] | man_add_sub_res_mag_dffe21_wo[24]), (man_res_not_zero_w2[21] | man_add_sub_res_mag_dffe21_wo[23]), (man_res_not_zero_w2[20] | man_add_sub_res_mag_dffe21_wo[22]), (man_res_not_zero_w2[19] | man_add_sub_res_mag_dffe21_wo[21]), (man_res_not_zero_w2[18] | man_add_sub_res_mag_dffe21_wo[20]), (man_res_not_zero_w2[17] | man_add_sub_res_mag_dffe21_wo[19]), (man_res_not_zero_w2[16] | man_add_sub_res_mag_dffe21_wo[18]), (man_res_not_zero_w2[15] | man_add_sub_res_mag_dffe21_wo[17]), (man_res_not_zero_w2[14] | man_add_sub_res_mag_dffe21_wo[16]), (man_res_not_zero_w2[13] | man_add_sub_res_mag_dffe21_wo[15]), (man_res_not_zero_w2[12] | man_add_sub_res_mag_dffe21_wo[14]), (man_res_not_zero_w2[11] | man_add_sub_res_mag_dffe21_wo[13]), (man_res_not_zero_w2[10] | man_add_sub_res_mag_dffe21_wo[12]), (man_res_not_zero_w2[9] | man_add_sub_res_mag_dffe21_wo[11]), (man_res_not_zero_w2[8] | man_add_sub_res_mag_dffe21_wo[10]), (man_res_not_zero_w2[7] | man_add_sub_res_mag_dffe21_wo[9]), (man_res_not_zero_w2[6] | man_add_sub_res_mag_dffe21_wo[8]), (man_res_not_zero_w2[5] | man_add_sub_res_mag_dffe21_wo[7]), (man_res_not_zero_w2[4] | man_add_sub_res_mag_dffe21_wo[6]), (man_res_not_zero_w2[3] | man_add_sub_res_mag_dffe21_wo[5]), (man_res_not_zero_w2[2] | man_add_sub_res_mag_dffe21_wo[4]), (man_res_not_zero_w2[1] | man_add_sub_res_mag_dffe21_wo[3]), (man_res_not_zero_w2[0] | man_add_sub_res_mag_dffe21_wo[2]), man_add_sub_res_mag_dffe21_wo[1]},
man_res_rounding_add_sub_datab_w = {{25{1'b0}}, man_rounding_add_value_w},
man_res_rounding_add_sub_w = man_res_rounding_add_sub_result_reg,
man_res_w3 = wire_lbarrel_shift_result[25:2],
man_rounded_res_w = (({23{man_res_rounding_add_sub_w[24]}} & man_res_rounding_add_sub_w[23:1]) | ({23{(~ man_res_rounding_add_sub_w[24])}} & man_res_rounding_add_sub_w[22:0])),
man_rounding_add_value_w = (round_bit_dffe3_wo & (sticky_bit_dffe3_wo | guard_bit_dffe3_wo)),
man_smaller_dffe13_wi = man_smaller_w,
man_smaller_dffe13_wo = man_smaller_dffe13,
man_smaller_w = (({24{exp_amb_mux_w}} & aligned_dataa_man_dffe12_wo) | ({24{(~ exp_amb_mux_w)}} & aligned_datab_man_dffe12_wo)),
need_complement_dffe22_wi = need_complement_dffe2_wo,
need_complement_dffe22_wo = need_complement_dffe22_wi,
need_complement_dffe2_wi = dataa_sign_dffe25_wo,
need_complement_dffe2_wo = need_complement_dffe2,
pos_sign_bit_ext = {2{1'b0}},
priority_encoder_1pads_w = {4{1'b1}},
result = {sign_out_dffe5_wo, exp_out_dffe5_wo, man_out_dffe5_wo},
round_bit_dffe21_wi = round_bit_w,
round_bit_dffe21_wo = round_bit_dffe21,
round_bit_dffe23_wi = round_bit_dffe21_wo,
round_bit_dffe23_wo = round_bit_dffe23,
round_bit_dffe26_wi = round_bit_dffe23_wo,
round_bit_dffe26_wo = round_bit_dffe26_wi,
round_bit_dffe31_wi = round_bit_dffe26_wo,
round_bit_dffe31_wo = round_bit_dffe31,
round_bit_dffe32_wi = round_bit_dffe31_wo,
round_bit_dffe32_wo = round_bit_dffe32_wi,
round_bit_dffe33_wi = round_bit_dffe32_wo,
round_bit_dffe33_wo = round_bit_dffe33_wi,
round_bit_dffe3_wi = round_bit_dffe33_wo,
round_bit_dffe3_wo = round_bit_dffe3,
round_bit_w = ((((((~ man_add_sub_res_mag_dffe27_wo[26]) & (~ man_add_sub_res_mag_dffe27_wo[25])) & man_add_sub_res_mag_dffe27_wo[0]) | (((~ man_add_sub_res_mag_dffe27_wo[26]) & man_add_sub_res_mag_dffe27_wo[25]) & man_add_sub_res_mag_dffe27_wo[1])) | ((man_add_sub_res_mag_dffe27_wo[26] & (~ man_add_sub_res_mag_dffe27_wo[25])) & man_add_sub_res_mag_dffe27_wo[2])) | ((man_add_sub_res_mag_dffe27_wo[26] & man_add_sub_res_mag_dffe27_wo[25]) & man_add_sub_res_mag_dffe27_wo[2])),
rounded_res_infinity_dffe4_wi = exp_rounded_res_infinity_w,
rounded_res_infinity_dffe4_wo = rounded_res_infinity_dffe4,
rshift_distance_dffe13_wi = rshift_distance_w,
rshift_distance_dffe13_wo = rshift_distance_dffe13,
rshift_distance_dffe14_wi = rshift_distance_dffe13_wo,
rshift_distance_dffe14_wo = rshift_distance_dffe14,
rshift_distance_dffe15_wi = rshift_distance_dffe14_wo,
rshift_distance_dffe15_wo = rshift_distance_dffe15,
rshift_distance_w = (({5{exp_diff_abs_exceed_max_w[2]}} & exp_diff_abs_max_w) | ({5{(~ exp_diff_abs_exceed_max_w[2])}} & exp_diff_abs_w[4:0])),
sign_dffe31_wi = ((man_res_not_zero_dffe26_wo & man_add_sub_res_sign_dffe26_wo) | ((~ man_res_not_zero_dffe26_wo) & zero_man_sign_dffe26_wo)),
sign_dffe31_wo = sign_dffe31,
sign_dffe32_wi = sign_dffe31_wo,
sign_dffe32_wo = sign_dffe32_wi,
sign_dffe33_wi = sign_dffe32_wo,
sign_dffe33_wo = sign_dffe33_wi,
sign_out_dffe5_wi = ((~ force_nan_w) & ((force_infinity_w & infinite_output_sign_dffe4_wo) | ((~ force_infinity_w) & sign_res_dffe4_wo))),
sign_out_dffe5_wo = sign_out_dffe5,
sign_res_dffe3_wi = sign_dffe33_wo,
sign_res_dffe3_wo = sign_res_dffe3,
sign_res_dffe41_wi = sign_res_dffe42_wo,
sign_res_dffe41_wo = sign_res_dffe41,
sign_res_dffe42_wi = sign_res_dffe3_wo,
sign_res_dffe42_wo = sign_res_dffe42_wi,
sign_res_dffe4_wi = sign_res_dffe41_wo,
sign_res_dffe4_wo = sign_res_dffe4,
sticky_bit_cnt_dataa_w = {1'b0, rshift_distance_dffe15_wo},
sticky_bit_cnt_datab_w = {1'b0, wire_trailing_zeros_cnt_q},
sticky_bit_cnt_res_w = wire_add_sub3_result,
sticky_bit_dffe1_wi = wire_trailing_zeros_limit_comparator_agb,
sticky_bit_dffe1_wo = sticky_bit_dffe1,
sticky_bit_dffe21_wi = sticky_bit_w,
sticky_bit_dffe21_wo = sticky_bit_dffe21,
sticky_bit_dffe22_wi = sticky_bit_dffe2_wo,
sticky_bit_dffe22_wo = sticky_bit_dffe22_wi,
sticky_bit_dffe23_wi = sticky_bit_dffe21_wo,
sticky_bit_dffe23_wo = sticky_bit_dffe23,
sticky_bit_dffe25_wi = sticky_bit_dffe1_wo,
sticky_bit_dffe25_wo = sticky_bit_dffe25_wi,
sticky_bit_dffe26_wi = sticky_bit_dffe23_wo,
sticky_bit_dffe26_wo = sticky_bit_dffe26_wi,
sticky_bit_dffe27_wi = sticky_bit_dffe22_wo,
sticky_bit_dffe27_wo = sticky_bit_dffe27,
sticky_bit_dffe2_wi = sticky_bit_dffe25_wo,
sticky_bit_dffe2_wo = sticky_bit_dffe2,
sticky_bit_dffe31_wi = sticky_bit_dffe26_wo,
sticky_bit_dffe31_wo = sticky_bit_dffe31,
sticky_bit_dffe32_wi = sticky_bit_dffe31_wo,
sticky_bit_dffe32_wo = sticky_bit_dffe32_wi,
sticky_bit_dffe33_wi = sticky_bit_dffe32_wo,
sticky_bit_dffe33_wo = sticky_bit_dffe33_wi,
sticky_bit_dffe3_wi = sticky_bit_dffe33_wo,
sticky_bit_dffe3_wo = sticky_bit_dffe3,
sticky_bit_w = ((((((~ man_add_sub_res_mag_dffe27_wo[26]) & (~ man_add_sub_res_mag_dffe27_wo[25])) & sticky_bit_dffe27_wo) | (((~ man_add_sub_res_mag_dffe27_wo[26]) & man_add_sub_res_mag_dffe27_wo[25]) & (sticky_bit_dffe27_wo | man_add_sub_res_mag_dffe27_wo[0]))) | ((man_add_sub_res_mag_dffe27_wo[26] & (~ man_add_sub_res_mag_dffe27_wo[25])) & ((sticky_bit_dffe27_wo | man_add_sub_res_mag_dffe27_wo[0]) | man_add_sub_res_mag_dffe27_wo[1]))) | ((man_add_sub_res_mag_dffe27_wo[26] & man_add_sub_res_mag_dffe27_wo[25]) & ((sticky_bit_dffe27_wo | man_add_sub_res_mag_dffe27_wo[0]) | man_add_sub_res_mag_dffe27_wo[1]))),
trailing_zeros_limit_w = 6'b000010,
zero_man_sign_dffe21_wi = zero_man_sign_dffe27_wo,
zero_man_sign_dffe21_wo = zero_man_sign_dffe21,
zero_man_sign_dffe22_wi = zero_man_sign_dffe2_wo,
zero_man_sign_dffe22_wo = zero_man_sign_dffe22_wi,
zero_man_sign_dffe23_wi = zero_man_sign_dffe21_wo,
zero_man_sign_dffe23_wo = zero_man_sign_dffe23,
zero_man_sign_dffe26_wi = zero_man_sign_dffe23_wo,
zero_man_sign_dffe26_wo = zero_man_sign_dffe26_wi,
zero_man_sign_dffe27_wi = zero_man_sign_dffe22_wo,
zero_man_sign_dffe27_wo = zero_man_sign_dffe27,
zero_man_sign_dffe2_wi = (dataa_sign_dffe25_wo & add_sub_dffe25_wo),
zero_man_sign_dffe2_wo = zero_man_sign_dffe2;
endmodule //fp_add_sub_altfp_add_sub_k7k
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fp_add_sub (
add_sub,
clock,
dataa,
datab,
result);
input add_sub;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_add_sub_altfp_add_sub_k7k fp_add_sub_altfp_add_sub_k7k_component (
.add_sub (add_sub),
.clock (clock),
.datab (datab),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: DIRECTION STRING "VARIABLE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "14"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL "add_sub"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_add_sub.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_add_sub.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_add_sub.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_add_sub.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_add_sub_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_add_sub_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:06:29 02/27/2016
// Design Name: Register
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab5/test_Reg_with_reset.v
// Project Name: lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_Reg_with_reset;
// Inputs
reg clock_in;
reg regWrite;
reg [4:0] readReg1;
reg [4:0] readReg2;
reg [4:0] writeReg;
reg [31:0] writeData;
reg reset;
parameter PERIOD = 200;
// Outputs
wire [31:0] readData1;
wire [31:0] readData2;
// Instantiate the Unit Under Test (UUT)
Register uut (
.clock_in(clock_in),
.regWrite(regWrite),
.readReg1(readReg1),
.readReg2(readReg2),
.writeReg(writeReg),
.writeData(writeData),
.reset(reset),
.readData1(readData1),
.readData2(readData2)
);
always #(PERIOD/2) clock_in = ~clock_in;
initial begin
// Initialize Inputs
clock_in = 0;
regWrite = 0;
readReg1 = 0;
readReg2 = 0;
writeReg = 0;
writeData = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#285;
regWrite = 'b1;
writeReg = 5'b10101;
writeData = 32'b11111111111111110000000000000000;
#200;
writeReg = 5'b01010;
writeData = 32'b00000000000000001111111111111111;
#200;
regWrite = 'b0;
writeReg = 'b00000;
writeData = 32'b00000000000000000000000000000000;
#50;
readReg1 = 'b10101;
readReg2 = 'b01010;
#100;
reset = 1;
end
endmodule
|
`define WIDTH_P 3
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
WIDTH_P is the width of the number of wait cycles needed. So each test
monitors the output for 2**WIDTH_P cycles.
2. PARAMETERIZATION
The parameter WIDTH_P has little influence on the way DUT synthesizes. So
a minimum set of tests might be WIDTH_P = 1,2,3,4. Tests with large
WIDTH_P may take long to finish because the number of cycles the test runs
grows exponentially with it.
***************************************************************************/
module test_bsg
#(parameter lg_wait_cycles_p = `WIDTH_P, // width of the timer
parameter cycle_time_p = 20,
parameter reset_cycles_lo_p = 1,
parameter reset_cycles_hi_p = 5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("===========================================================");
$display("testing with ...");
$display("WIDTH_P: %d\n", `WIDTH_P);
end
logic test_output, test_output_r, ref_test_output;
time reset_time, ready_time;
assign ref_test_output = ((ready_time-reset_time)/cycle_time_p)
== (2**`WIDTH_P); // checks correctness
// of ready timing
always_ff @(negedge reset)
begin
reset_time <= $time - (cycle_time_p / 2); // the test reset becomes 0
// on negedge
ready_time <= 0;
end
always_ff @(posedge test_output)
ready_time <= $time;
always_ff @(posedge clk)
begin
test_output_r <= test_output;
/*$display("\ntest_output: %b @ time: %d", test_output, $time);*/
if(!reset)
assert (test_output == ref_test_output)
else $error("mismatch at time = %d", $time);
if(test_output_r)
begin
$display("=============================================================\n");
$finish;
end
end
bsg_wait_after_reset #( .lg_wait_cycles_p(lg_wait_cycles_p)
) DUT
( .clk_i (clk)
, .reset_i (reset)
, .ready_r_o(test_output)
);
/*//log test results
logic [(3*lg_wait_cycles_p)-1:0] log;
assign log = { `BSG_SAFE_CLOG2(lg_wait_cycles_p+1)'(test_output)
, `BSG_SAFE_CLOG2(lg_wait_cycles_p+1)'(ref_test_output)
, `BSG_SAFE_CLOG2(lg_wait_cycles_p+1)'(lg_wait_cycles_p)};
bsg_nonsynth_ascii_writer #( .width_p (`BSG_SAFE_CLOG2(
lg_wait_cycles_p+1))
, .values_p (3)
, .filename_p ("output.log")
, .fopen_param_p("a+")
, .format_p ("%x")
) ascii_writer
( .clk (clk)
, .reset_i(reset)
, .valid_i(1'b1)
, .data_i (log)
);*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DFSBP_PP_SYMBOL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSBP_PP_SYMBOL_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 11:10:35 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/multi_QI/multi_QI_funcsim.v
// Design : multi_QI
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.1" *) (* CHECK_LICENSE_TYPE = "multi_QI,mult_gen_v12_0,{}" *)
(* core_generation_info = "multi_QI,mult_gen_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=7,C_A_WIDTH=16,C_A_TYPE=0,C_B_WIDTH=16,C_B_TYPE=0,C_OUT_HIGH=31,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module multi_QI
(CLK,
A,
B,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [15:0]A;
input [15:0]B;
output [31:0]P;
wire [15:0]A;
wire [15:0]B;
wire CLK;
wire [31:0]P;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "0" *)
(* C_A_WIDTH = "16" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "7" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "31" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
multi_QImult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *) (* C_LATENCY = "7" *) (* C_A_WIDTH = "16" *)
(* C_A_TYPE = "0" *) (* C_B_WIDTH = "16" *) (* C_B_TYPE = "0" *)
(* C_OUT_HIGH = "31" *) (* C_OUT_LOW = "0" *) (* C_MULT_TYPE = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module multi_QImult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [15:0]A;
input [15:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [31:0]P;
output [47:0]PCASC;
wire [15:0]A;
wire [15:0]B;
wire CE;
wire CLK;
wire [31:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "0" *)
(* C_A_WIDTH = "16" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "7" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "31" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* secure_extras = "A" *)
multi_QImult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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LeVqKxvarw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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LYvzs92V+0bNZbbueyA=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 435472)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//==================================================================================================
// Filename : musb_shifter.v
// Created On : 2014-10-11 19:22:43
// Last Modified : 2015-05-24 20:59:31
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Arithmetic/Logic shifter
// WARNING: shamnt range is 0 -> 31
//==================================================================================================
`include "musb_defines.v"
module musb_shifter(
input [31:0] input_data, // input data
input [4:0] shamnt, // shift amount
input direction, // 0: right, 1: left
input sign_extend, // signed operation
output [31:0] shift_result // result
);
///-------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [31:0] input_inv; // invert input for shift left
reg [31:0] result_shift_temp; // shift result
reg [31:0] result_inv; // invert output for shift left
///-------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire sign;
wire [31:0] operand;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign sign = (sign_extend) ? input_data[31] : 1'b0; // set if SRA
assign operand = (direction) ? input_inv : input_data; // set if SLL
assign shift_result = (direction) ? result_inv : result_shift_temp; // set if SLL
//--------------------------------------------------------------------------
// invert data if operation is SLL
//--------------------------------------------------------------------------
integer index0;
integer index1;
// first inversion: input
always @(*) begin
for (index0 = 0; index0 < 32; index0 = index0 + 1)
input_inv[31-index0] <= input_data[index0];
end
// second inversion : output
always @(*) begin
for (index1 = 0; index1 < 32; index1 = index1 + 1)
result_inv[31-index1] <= result_shift_temp[index1];
end
//--------------------------------------------------------------------------
// the BIG multiplexer
// Perform SRA. Sign depends if operation is SRA or SRL (sign_extend)
//--------------------------------------------------------------------------
always @(*) begin
case(shamnt)
5'd0 : result_shift_temp <= operand[31:0];
5'd1 : result_shift_temp <= { {1 {sign}}, operand[31:1] };
5'd2 : result_shift_temp <= { {2 {sign}}, operand[31:2] };
5'd3 : result_shift_temp <= { {3 {sign}}, operand[31:3] };
5'd4 : result_shift_temp <= { {4 {sign}}, operand[31:4] };
5'd5 : result_shift_temp <= { {5 {sign}}, operand[31:5] };
5'd6 : result_shift_temp <= { {6 {sign}}, operand[31:6] };
5'd7 : result_shift_temp <= { {7 {sign}}, operand[31:7] };
5'd8 : result_shift_temp <= { {8 {sign}}, operand[31:8] };
5'd9 : result_shift_temp <= { {9 {sign}}, operand[31:9] };
5'd10 : result_shift_temp <= { {10{sign}}, operand[31:10] };
5'd11 : result_shift_temp <= { {11{sign}}, operand[31:11] };
5'd12 : result_shift_temp <= { {12{sign}}, operand[31:12] };
5'd13 : result_shift_temp <= { {13{sign}}, operand[31:13] };
5'd14 : result_shift_temp <= { {14{sign}}, operand[31:14] };
5'd15 : result_shift_temp <= { {15{sign}}, operand[31:15] };
5'd16 : result_shift_temp <= { {16{sign}}, operand[31:16] };
5'd17 : result_shift_temp <= { {17{sign}}, operand[31:17] };
5'd18 : result_shift_temp <= { {18{sign}}, operand[31:18] };
5'd19 : result_shift_temp <= { {19{sign}}, operand[31:19] };
5'd20 : result_shift_temp <= { {20{sign}}, operand[31:20] };
5'd21 : result_shift_temp <= { {21{sign}}, operand[31:21] };
5'd22 : result_shift_temp <= { {22{sign}}, operand[31:22] };
5'd23 : result_shift_temp <= { {23{sign}}, operand[31:23] };
5'd24 : result_shift_temp <= { {24{sign}}, operand[31:24] };
5'd25 : result_shift_temp <= { {25{sign}}, operand[31:25] };
5'd26 : result_shift_temp <= { {26{sign}}, operand[31:26] };
5'd27 : result_shift_temp <= { {27{sign}}, operand[31:27] };
5'd28 : result_shift_temp <= { {28{sign}}, operand[31:28] };
5'd29 : result_shift_temp <= { {29{sign}}, operand[31:29] };
5'd30 : result_shift_temp <= { {30{sign}}, operand[31:30] };
5'd31 : result_shift_temp <= { {31{sign}}, operand[31:31] };
default : result_shift_temp <= 32'bx; // I don't BLOODY CARE.
endcase
end
endmodule
|
module VIDEO_OUT
(
pixel_clock,
reset,
vga_red_data,
vga_green_data,
vga_blue_data,
h_synch,
v_synch,
blank,
VGA_HSYNCH,
VGA_VSYNCH,
VGA_OUT_RED,
VGA_OUT_GREEN,
VGA_OUT_BLUE
);
input pixel_clock;
input reset;
input vga_red_data;
input vga_green_data;
input vga_blue_data;
input h_synch;
input v_synch;
input blank;
output VGA_HSYNCH;
output VGA_VSYNCH;
output VGA_OUT_RED;
output VGA_OUT_GREEN;
output VGA_OUT_BLUE;
reg VGA_HSYNCH;
reg VGA_VSYNCH;
reg VGA_OUT_RED;
reg VGA_OUT_GREEN;
reg VGA_OUT_BLUE;
// make the external video connections
always @ (posedge pixel_clock or posedge reset) begin
if (reset) begin
// shut down the video output during reset
VGA_HSYNCH <= 1'b1;
VGA_VSYNCH <= 1'b1;
VGA_OUT_RED <= 1'b0;
VGA_OUT_GREEN <= 1'b0;
VGA_OUT_BLUE <= 1'b0;
end
else if (blank) begin
// output black during the blank signal
VGA_HSYNCH <= h_synch;
VGA_VSYNCH <= v_synch;
VGA_OUT_RED <= 1'b0;
VGA_OUT_GREEN <= 1'b0;
VGA_OUT_BLUE <= 1'b0;
end
else begin
// output color data otherwise
VGA_HSYNCH <= h_synch;
VGA_VSYNCH <= v_synch;
VGA_OUT_RED <= vga_red_data;
VGA_OUT_GREEN <= vga_green_data;
VGA_OUT_BLUE <= vga_blue_data;
end
end
endmodule // VIDEO_OUT |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22O_1_V
`define SKY130_FD_SC_HD__A22O_1_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22o_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22O_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_dds_1 #(
// parameters
parameter DDS_TYPE = 1,
parameter DDS_D_DW = 16,
parameter DDS_P_DW = 16) (
// interface
input clk,
input [DDS_P_DW-1:0] angle,
input [ 15:0] scale,
output reg [DDS_D_DW-1:0] dds_data);
// local parameters
localparam DDS_CORDIC_TYPE = 1;
localparam DDS_POLINOMIAL_TYPE = 2;
// internal signals
wire [ DDS_D_DW-1:0] sine_s;
wire [DDS_D_DW+17:0] s1_data_s;
// sine
generate
if (DDS_TYPE == DDS_CORDIC_TYPE) begin
ad_dds_sine_cordic #(
.CORDIC_DW(DDS_D_DW),
.PHASE_DW(DDS_P_DW),
.DELAY_DW(1))
i_dds_sine (
.clk (clk),
.angle (angle),
.sine (sine_s),
.cosine (),
.ddata_in (1'b0),
.ddata_out ());
end else begin
ad_dds_sine i_dds_sine (
.clk (clk),
.angle (angle),
.sine (sine_s),
.ddata_in (1'b0),
.ddata_out ());
end
endgenerate
// scale for a sine generator
ad_mul #(
.A_DATA_WIDTH(DDS_D_DW + 1),
.B_DATA_WIDTH(17),
.DELAY_DATA_WIDTH(1))
i_dds_scale (
.clk (clk),
.data_a ({sine_s[DDS_D_DW-1], sine_s}),
.data_b ({scale[15], scale}),
.data_p (s1_data_s),
.ddata_in (1'b0),
.ddata_out ());
// dds data
always @(posedge clk) begin
//15'h8000 is the maximum scale
dds_data <= s1_data_s[DDS_D_DW+13:14];
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
// Date : Tue Oct 4 14:53:42 2016
// Host : jorge-pc running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -mode funcsim -nolib -force -file
// /home/jorge/Documents/Karatsuba_FPU/Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.sim/tb_CORDIC_Arch3_single/synth/func/testbench_CORDIC_Arch3_func_synth.v
// Design : CORDIC_Arch3
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* EW = "8" *) (* EWR = "5" *) (* SW = "23" *)
(* SWR = "26" *) (* W = "32" *) (* iter_bits = "4" *)
(* mode = "1'b0" *)
(* NotValidForBitStream *)
module CORDIC_Arch3
(clk,
rst,
beg_fsm_cordic,
ack_cordic,
operation,
data_in,
shift_region_flag,
ready_cordic,
overflow_flag,
underflow_flag,
zero_flag,
busy,
data_output);
input clk;
input rst;
input beg_fsm_cordic;
input ack_cordic;
input operation;
input [31:0]data_in;
input [1:0]shift_region_flag;
output ready_cordic;
output overflow_flag;
output underflow_flag;
output zero_flag;
output busy;
output [31:0]data_output;
wire [7:0]A;
wire ITER_CONT_n_10;
wire ITER_CONT_n_100;
wire ITER_CONT_n_104;
wire ITER_CONT_n_107;
wire ITER_CONT_n_108;
wire ITER_CONT_n_109;
wire ITER_CONT_n_11;
wire ITER_CONT_n_118;
wire ITER_CONT_n_119;
wire ITER_CONT_n_12;
wire ITER_CONT_n_13;
wire ITER_CONT_n_14;
wire ITER_CONT_n_15;
wire ITER_CONT_n_16;
wire ITER_CONT_n_17;
wire ITER_CONT_n_18;
wire ITER_CONT_n_19;
wire ITER_CONT_n_20;
wire ITER_CONT_n_21;
wire ITER_CONT_n_22;
wire ITER_CONT_n_23;
wire ITER_CONT_n_24;
wire ITER_CONT_n_25;
wire ITER_CONT_n_26;
wire ITER_CONT_n_27;
wire ITER_CONT_n_28;
wire ITER_CONT_n_29;
wire ITER_CONT_n_30;
wire ITER_CONT_n_31;
wire ITER_CONT_n_32;
wire ITER_CONT_n_33;
wire ITER_CONT_n_34;
wire ITER_CONT_n_35;
wire ITER_CONT_n_36;
wire ITER_CONT_n_37;
wire ITER_CONT_n_38;
wire ITER_CONT_n_39;
wire ITER_CONT_n_40;
wire ITER_CONT_n_41;
wire ITER_CONT_n_42;
wire ITER_CONT_n_43;
wire ITER_CONT_n_44;
wire ITER_CONT_n_45;
wire ITER_CONT_n_46;
wire ITER_CONT_n_47;
wire ITER_CONT_n_48;
wire ITER_CONT_n_49;
wire ITER_CONT_n_5;
wire ITER_CONT_n_50;
wire ITER_CONT_n_51;
wire ITER_CONT_n_52;
wire ITER_CONT_n_53;
wire ITER_CONT_n_54;
wire ITER_CONT_n_55;
wire ITER_CONT_n_56;
wire ITER_CONT_n_57;
wire ITER_CONT_n_58;
wire ITER_CONT_n_59;
wire ITER_CONT_n_6;
wire ITER_CONT_n_60;
wire ITER_CONT_n_61;
wire ITER_CONT_n_62;
wire ITER_CONT_n_63;
wire ITER_CONT_n_64;
wire ITER_CONT_n_65;
wire ITER_CONT_n_66;
wire ITER_CONT_n_67;
wire ITER_CONT_n_68;
wire ITER_CONT_n_69;
wire ITER_CONT_n_7;
wire ITER_CONT_n_70;
wire ITER_CONT_n_71;
wire ITER_CONT_n_72;
wire ITER_CONT_n_73;
wire ITER_CONT_n_74;
wire ITER_CONT_n_75;
wire ITER_CONT_n_76;
wire ITER_CONT_n_77;
wire ITER_CONT_n_78;
wire ITER_CONT_n_79;
wire ITER_CONT_n_8;
wire ITER_CONT_n_80;
wire ITER_CONT_n_81;
wire ITER_CONT_n_82;
wire ITER_CONT_n_83;
wire ITER_CONT_n_84;
wire ITER_CONT_n_85;
wire ITER_CONT_n_86;
wire ITER_CONT_n_87;
wire ITER_CONT_n_88;
wire ITER_CONT_n_89;
wire ITER_CONT_n_9;
wire ITER_CONT_n_90;
wire ITER_CONT_n_91;
wire ITER_CONT_n_92;
wire ITER_CONT_n_93;
wire ITER_CONT_n_94;
wire ITER_CONT_n_95;
wire ITER_CONT_n_96;
wire ITER_CONT_n_97;
wire ITER_CONT_n_98;
wire ITER_CONT_n_99;
wire VAR_CONT_n_10;
wire VAR_CONT_n_11;
wire VAR_CONT_n_12;
wire VAR_CONT_n_13;
wire VAR_CONT_n_14;
wire VAR_CONT_n_15;
wire VAR_CONT_n_16;
wire VAR_CONT_n_17;
wire VAR_CONT_n_18;
wire VAR_CONT_n_19;
wire VAR_CONT_n_20;
wire VAR_CONT_n_21;
wire VAR_CONT_n_22;
wire VAR_CONT_n_23;
wire VAR_CONT_n_24;
wire VAR_CONT_n_25;
wire VAR_CONT_n_26;
wire VAR_CONT_n_27;
wire VAR_CONT_n_28;
wire VAR_CONT_n_29;
wire VAR_CONT_n_3;
wire VAR_CONT_n_30;
wire VAR_CONT_n_31;
wire VAR_CONT_n_32;
wire VAR_CONT_n_33;
wire VAR_CONT_n_34;
wire VAR_CONT_n_35;
wire VAR_CONT_n_36;
wire VAR_CONT_n_37;
wire VAR_CONT_n_38;
wire VAR_CONT_n_39;
wire VAR_CONT_n_40;
wire VAR_CONT_n_41;
wire VAR_CONT_n_42;
wire VAR_CONT_n_43;
wire VAR_CONT_n_44;
wire VAR_CONT_n_45;
wire VAR_CONT_n_46;
wire VAR_CONT_n_47;
wire VAR_CONT_n_48;
wire VAR_CONT_n_49;
wire VAR_CONT_n_5;
wire VAR_CONT_n_50;
wire VAR_CONT_n_51;
wire VAR_CONT_n_52;
wire VAR_CONT_n_53;
wire VAR_CONT_n_54;
wire VAR_CONT_n_55;
wire VAR_CONT_n_56;
wire VAR_CONT_n_57;
wire VAR_CONT_n_58;
wire VAR_CONT_n_59;
wire VAR_CONT_n_6;
wire VAR_CONT_n_60;
wire VAR_CONT_n_61;
wire VAR_CONT_n_62;
wire VAR_CONT_n_63;
wire VAR_CONT_n_64;
wire VAR_CONT_n_65;
wire VAR_CONT_n_66;
wire VAR_CONT_n_67;
wire VAR_CONT_n_68;
wire VAR_CONT_n_7;
wire VAR_CONT_n_8;
wire VAR_CONT_n_9;
wire [7:0]Y;
wire ack_cordic;
wire ack_cordic_IBUF;
wire beg_fsm_cordic;
wire beg_fsm_cordic_IBUF;
wire busy;
wire busy_OBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire [3:0]cont_iter_out;
wire [1:0]cont_var_out;
wire d_ff1_operation_out;
wire [31:31]d_ff2_Y;
wire [31:31]d_ff2_Z;
wire d_ff3_sign_out;
wire d_ff4_Xn_n_0;
wire d_ff4_Xn_n_1;
wire d_ff4_Xn_n_10;
wire d_ff4_Xn_n_11;
wire d_ff4_Xn_n_12;
wire d_ff4_Xn_n_13;
wire d_ff4_Xn_n_14;
wire d_ff4_Xn_n_15;
wire d_ff4_Xn_n_16;
wire d_ff4_Xn_n_17;
wire d_ff4_Xn_n_18;
wire d_ff4_Xn_n_19;
wire d_ff4_Xn_n_2;
wire d_ff4_Xn_n_20;
wire d_ff4_Xn_n_21;
wire d_ff4_Xn_n_22;
wire d_ff4_Xn_n_23;
wire d_ff4_Xn_n_24;
wire d_ff4_Xn_n_25;
wire d_ff4_Xn_n_26;
wire d_ff4_Xn_n_27;
wire d_ff4_Xn_n_28;
wire d_ff4_Xn_n_29;
wire d_ff4_Xn_n_3;
wire d_ff4_Xn_n_30;
wire d_ff4_Xn_n_31;
wire d_ff4_Xn_n_4;
wire d_ff4_Xn_n_5;
wire d_ff4_Xn_n_6;
wire d_ff4_Xn_n_7;
wire d_ff4_Xn_n_8;
wire d_ff4_Xn_n_9;
wire d_ff4_Yn_n_0;
wire d_ff4_Yn_n_1;
wire d_ff4_Yn_n_10;
wire d_ff4_Yn_n_11;
wire d_ff4_Yn_n_12;
wire d_ff4_Yn_n_13;
wire d_ff4_Yn_n_14;
wire d_ff4_Yn_n_15;
wire d_ff4_Yn_n_16;
wire d_ff4_Yn_n_17;
wire d_ff4_Yn_n_18;
wire d_ff4_Yn_n_19;
wire d_ff4_Yn_n_2;
wire d_ff4_Yn_n_20;
wire d_ff4_Yn_n_21;
wire d_ff4_Yn_n_22;
wire d_ff4_Yn_n_23;
wire d_ff4_Yn_n_24;
wire d_ff4_Yn_n_25;
wire d_ff4_Yn_n_26;
wire d_ff4_Yn_n_27;
wire d_ff4_Yn_n_28;
wire d_ff4_Yn_n_29;
wire d_ff4_Yn_n_3;
wire d_ff4_Yn_n_30;
wire d_ff4_Yn_n_31;
wire d_ff4_Yn_n_4;
wire d_ff4_Yn_n_5;
wire d_ff4_Yn_n_6;
wire d_ff4_Yn_n_7;
wire d_ff4_Yn_n_8;
wire d_ff4_Yn_n_9;
wire d_ff4_Zn_n_0;
wire d_ff4_Zn_n_1;
wire d_ff4_Zn_n_10;
wire d_ff4_Zn_n_11;
wire d_ff4_Zn_n_12;
wire d_ff4_Zn_n_13;
wire d_ff4_Zn_n_14;
wire d_ff4_Zn_n_15;
wire d_ff4_Zn_n_16;
wire d_ff4_Zn_n_17;
wire d_ff4_Zn_n_18;
wire d_ff4_Zn_n_19;
wire d_ff4_Zn_n_2;
wire d_ff4_Zn_n_20;
wire d_ff4_Zn_n_21;
wire d_ff4_Zn_n_22;
wire d_ff4_Zn_n_23;
wire d_ff4_Zn_n_24;
wire d_ff4_Zn_n_25;
wire d_ff4_Zn_n_26;
wire d_ff4_Zn_n_27;
wire d_ff4_Zn_n_28;
wire d_ff4_Zn_n_29;
wire d_ff4_Zn_n_3;
wire d_ff4_Zn_n_30;
wire d_ff4_Zn_n_31;
wire d_ff4_Zn_n_4;
wire d_ff4_Zn_n_5;
wire d_ff4_Zn_n_6;
wire d_ff4_Zn_n_7;
wire d_ff4_Zn_n_8;
wire d_ff4_Zn_n_9;
wire [31:0]data_in;
wire [31:0]data_in_IBUF;
wire [26:0]data_out_LUT;
wire [31:0]data_output;
wire [31:0]data_output_OBUF;
wire enab_RB3;
wire enab_cont_iter;
wire enab_d_ff4_Yn;
wire enab_d_ff4_Zn;
wire enab_d_ff5_data_out;
wire enab_d_ff_RB1;
wire inst_CORDIC_FSM_v3_n_0;
wire inst_CORDIC_FSM_v3_n_1;
wire inst_CORDIC_FSM_v3_n_3;
wire inst_CORDIC_FSM_v3_n_4;
wire inst_CORDIC_FSM_v3_n_5;
wire inst_CORDIC_FSM_v3_n_6;
wire inst_CORDIC_FSM_v3_n_7;
wire inst_CORDIC_FSM_v3_n_8;
wire inst_CORDIC_FSM_v3_n_9;
wire inst_FPU_PIPELINED_FPADDSUB_n_10;
wire inst_FPU_PIPELINED_FPADDSUB_n_11;
wire inst_FPU_PIPELINED_FPADDSUB_n_12;
wire inst_FPU_PIPELINED_FPADDSUB_n_13;
wire inst_FPU_PIPELINED_FPADDSUB_n_14;
wire inst_FPU_PIPELINED_FPADDSUB_n_15;
wire inst_FPU_PIPELINED_FPADDSUB_n_16;
wire inst_FPU_PIPELINED_FPADDSUB_n_17;
wire inst_FPU_PIPELINED_FPADDSUB_n_18;
wire inst_FPU_PIPELINED_FPADDSUB_n_19;
wire inst_FPU_PIPELINED_FPADDSUB_n_2;
wire inst_FPU_PIPELINED_FPADDSUB_n_20;
wire inst_FPU_PIPELINED_FPADDSUB_n_21;
wire inst_FPU_PIPELINED_FPADDSUB_n_22;
wire inst_FPU_PIPELINED_FPADDSUB_n_23;
wire inst_FPU_PIPELINED_FPADDSUB_n_24;
wire inst_FPU_PIPELINED_FPADDSUB_n_25;
wire inst_FPU_PIPELINED_FPADDSUB_n_26;
wire inst_FPU_PIPELINED_FPADDSUB_n_27;
wire inst_FPU_PIPELINED_FPADDSUB_n_28;
wire inst_FPU_PIPELINED_FPADDSUB_n_29;
wire inst_FPU_PIPELINED_FPADDSUB_n_3;
wire inst_FPU_PIPELINED_FPADDSUB_n_30;
wire inst_FPU_PIPELINED_FPADDSUB_n_31;
wire inst_FPU_PIPELINED_FPADDSUB_n_32;
wire inst_FPU_PIPELINED_FPADDSUB_n_33;
wire inst_FPU_PIPELINED_FPADDSUB_n_37;
wire inst_FPU_PIPELINED_FPADDSUB_n_4;
wire inst_FPU_PIPELINED_FPADDSUB_n_5;
wire inst_FPU_PIPELINED_FPADDSUB_n_6;
wire inst_FPU_PIPELINED_FPADDSUB_n_7;
wire inst_FPU_PIPELINED_FPADDSUB_n_8;
wire inst_FPU_PIPELINED_FPADDSUB_n_9;
wire max_tick_iter;
wire op_add_subt;
wire operation;
wire operation_IBUF;
wire overflow_flag;
wire overflow_flag_OBUF;
wire [2:2]p_1_out;
wire ready_add_subt;
wire ready_cordic;
wire ready_cordic_OBUF;
wire reg_LUT_n_0;
wire reg_LUT_n_1;
wire reg_LUT_n_10;
wire reg_LUT_n_11;
wire reg_LUT_n_12;
wire reg_LUT_n_13;
wire reg_LUT_n_14;
wire reg_LUT_n_15;
wire reg_LUT_n_16;
wire reg_LUT_n_17;
wire reg_LUT_n_18;
wire reg_LUT_n_19;
wire reg_LUT_n_2;
wire reg_LUT_n_20;
wire reg_LUT_n_3;
wire reg_LUT_n_4;
wire reg_LUT_n_5;
wire reg_LUT_n_6;
wire reg_LUT_n_7;
wire reg_LUT_n_8;
wire reg_LUT_n_9;
wire reg_Z0_n_0;
wire reg_Z0_n_1;
wire reg_Z0_n_10;
wire reg_Z0_n_11;
wire reg_Z0_n_12;
wire reg_Z0_n_13;
wire reg_Z0_n_14;
wire reg_Z0_n_15;
wire reg_Z0_n_16;
wire reg_Z0_n_17;
wire reg_Z0_n_18;
wire reg_Z0_n_19;
wire reg_Z0_n_2;
wire reg_Z0_n_20;
wire reg_Z0_n_21;
wire reg_Z0_n_22;
wire reg_Z0_n_23;
wire reg_Z0_n_24;
wire reg_Z0_n_25;
wire reg_Z0_n_26;
wire reg_Z0_n_27;
wire reg_Z0_n_28;
wire reg_Z0_n_29;
wire reg_Z0_n_3;
wire reg_Z0_n_30;
wire reg_Z0_n_31;
wire reg_Z0_n_4;
wire reg_Z0_n_5;
wire reg_Z0_n_6;
wire reg_Z0_n_7;
wire reg_Z0_n_8;
wire reg_Z0_n_9;
wire reg_region_flag_n_0;
wire reg_region_flag_n_1;
wire reg_region_flag_n_10;
wire reg_region_flag_n_11;
wire reg_region_flag_n_12;
wire reg_region_flag_n_13;
wire reg_region_flag_n_14;
wire reg_region_flag_n_15;
wire reg_region_flag_n_16;
wire reg_region_flag_n_17;
wire reg_region_flag_n_18;
wire reg_region_flag_n_19;
wire reg_region_flag_n_2;
wire reg_region_flag_n_20;
wire reg_region_flag_n_21;
wire reg_region_flag_n_22;
wire reg_region_flag_n_23;
wire reg_region_flag_n_24;
wire reg_region_flag_n_25;
wire reg_region_flag_n_26;
wire reg_region_flag_n_27;
wire reg_region_flag_n_28;
wire reg_region_flag_n_29;
wire reg_region_flag_n_3;
wire reg_region_flag_n_30;
wire reg_region_flag_n_31;
wire reg_region_flag_n_4;
wire reg_region_flag_n_5;
wire reg_region_flag_n_6;
wire reg_region_flag_n_7;
wire reg_region_flag_n_8;
wire reg_region_flag_n_9;
wire reg_shift_x_n_0;
wire reg_shift_x_n_1;
wire reg_shift_x_n_10;
wire reg_shift_x_n_11;
wire reg_shift_x_n_12;
wire reg_shift_x_n_13;
wire reg_shift_x_n_14;
wire reg_shift_x_n_15;
wire reg_shift_x_n_16;
wire reg_shift_x_n_17;
wire reg_shift_x_n_18;
wire reg_shift_x_n_19;
wire reg_shift_x_n_2;
wire reg_shift_x_n_20;
wire reg_shift_x_n_21;
wire reg_shift_x_n_22;
wire reg_shift_x_n_23;
wire reg_shift_x_n_24;
wire reg_shift_x_n_25;
wire reg_shift_x_n_26;
wire reg_shift_x_n_27;
wire reg_shift_x_n_28;
wire reg_shift_x_n_29;
wire reg_shift_x_n_3;
wire reg_shift_x_n_30;
wire reg_shift_x_n_31;
wire reg_shift_x_n_4;
wire reg_shift_x_n_5;
wire reg_shift_x_n_6;
wire reg_shift_x_n_7;
wire reg_shift_x_n_8;
wire reg_shift_x_n_9;
wire reg_shift_y_n_0;
wire reg_shift_y_n_1;
wire reg_shift_y_n_10;
wire reg_shift_y_n_11;
wire reg_shift_y_n_12;
wire reg_shift_y_n_13;
wire reg_shift_y_n_14;
wire reg_shift_y_n_15;
wire reg_shift_y_n_16;
wire reg_shift_y_n_17;
wire reg_shift_y_n_18;
wire reg_shift_y_n_19;
wire reg_shift_y_n_2;
wire reg_shift_y_n_20;
wire reg_shift_y_n_21;
wire reg_shift_y_n_22;
wire reg_shift_y_n_23;
wire reg_shift_y_n_24;
wire reg_shift_y_n_25;
wire reg_shift_y_n_26;
wire reg_shift_y_n_27;
wire reg_shift_y_n_28;
wire reg_shift_y_n_29;
wire reg_shift_y_n_3;
wire reg_shift_y_n_30;
wire reg_shift_y_n_31;
wire reg_shift_y_n_4;
wire reg_shift_y_n_5;
wire reg_shift_y_n_6;
wire reg_shift_y_n_7;
wire reg_shift_y_n_8;
wire reg_shift_y_n_9;
wire reg_val_muxX_2stage_n_0;
wire reg_val_muxX_2stage_n_1;
wire reg_val_muxX_2stage_n_13;
wire reg_val_muxX_2stage_n_14;
wire reg_val_muxX_2stage_n_15;
wire reg_val_muxX_2stage_n_16;
wire reg_val_muxX_2stage_n_17;
wire reg_val_muxX_2stage_n_18;
wire reg_val_muxX_2stage_n_19;
wire reg_val_muxX_2stage_n_2;
wire reg_val_muxX_2stage_n_20;
wire reg_val_muxX_2stage_n_21;
wire reg_val_muxX_2stage_n_22;
wire reg_val_muxX_2stage_n_23;
wire reg_val_muxX_2stage_n_24;
wire reg_val_muxX_2stage_n_25;
wire reg_val_muxX_2stage_n_26;
wire reg_val_muxX_2stage_n_27;
wire reg_val_muxX_2stage_n_28;
wire reg_val_muxX_2stage_n_29;
wire reg_val_muxX_2stage_n_3;
wire reg_val_muxX_2stage_n_30;
wire reg_val_muxX_2stage_n_31;
wire reg_val_muxX_2stage_n_32;
wire reg_val_muxX_2stage_n_33;
wire reg_val_muxX_2stage_n_34;
wire reg_val_muxX_2stage_n_35;
wire reg_val_muxX_2stage_n_36;
wire reg_val_muxX_2stage_n_37;
wire reg_val_muxX_2stage_n_38;
wire reg_val_muxX_2stage_n_39;
wire reg_val_muxX_2stage_n_4;
wire reg_val_muxY_2stage_n_1;
wire reg_val_muxY_2stage_n_10;
wire reg_val_muxY_2stage_n_11;
wire reg_val_muxY_2stage_n_12;
wire reg_val_muxY_2stage_n_13;
wire reg_val_muxY_2stage_n_14;
wire reg_val_muxY_2stage_n_15;
wire reg_val_muxY_2stage_n_16;
wire reg_val_muxY_2stage_n_17;
wire reg_val_muxY_2stage_n_18;
wire reg_val_muxY_2stage_n_19;
wire reg_val_muxY_2stage_n_2;
wire reg_val_muxY_2stage_n_20;
wire reg_val_muxY_2stage_n_21;
wire reg_val_muxY_2stage_n_22;
wire reg_val_muxY_2stage_n_23;
wire reg_val_muxY_2stage_n_24;
wire reg_val_muxY_2stage_n_25;
wire reg_val_muxY_2stage_n_26;
wire reg_val_muxY_2stage_n_27;
wire reg_val_muxY_2stage_n_28;
wire reg_val_muxY_2stage_n_29;
wire reg_val_muxY_2stage_n_3;
wire reg_val_muxY_2stage_n_30;
wire reg_val_muxY_2stage_n_31;
wire reg_val_muxY_2stage_n_32;
wire reg_val_muxY_2stage_n_33;
wire reg_val_muxY_2stage_n_34;
wire reg_val_muxY_2stage_n_35;
wire reg_val_muxY_2stage_n_36;
wire reg_val_muxY_2stage_n_37;
wire reg_val_muxY_2stage_n_38;
wire reg_val_muxY_2stage_n_39;
wire reg_val_muxY_2stage_n_4;
wire reg_val_muxY_2stage_n_5;
wire reg_val_muxY_2stage_n_6;
wire reg_val_muxY_2stage_n_7;
wire reg_val_muxY_2stage_n_8;
wire reg_val_muxY_2stage_n_9;
wire reg_val_muxZ_2stage_n_1;
wire reg_val_muxZ_2stage_n_10;
wire reg_val_muxZ_2stage_n_11;
wire reg_val_muxZ_2stage_n_12;
wire reg_val_muxZ_2stage_n_13;
wire reg_val_muxZ_2stage_n_14;
wire reg_val_muxZ_2stage_n_15;
wire reg_val_muxZ_2stage_n_16;
wire reg_val_muxZ_2stage_n_17;
wire reg_val_muxZ_2stage_n_18;
wire reg_val_muxZ_2stage_n_19;
wire reg_val_muxZ_2stage_n_2;
wire reg_val_muxZ_2stage_n_20;
wire reg_val_muxZ_2stage_n_21;
wire reg_val_muxZ_2stage_n_22;
wire reg_val_muxZ_2stage_n_23;
wire reg_val_muxZ_2stage_n_24;
wire reg_val_muxZ_2stage_n_25;
wire reg_val_muxZ_2stage_n_26;
wire reg_val_muxZ_2stage_n_27;
wire reg_val_muxZ_2stage_n_28;
wire reg_val_muxZ_2stage_n_29;
wire reg_val_muxZ_2stage_n_3;
wire reg_val_muxZ_2stage_n_30;
wire reg_val_muxZ_2stage_n_31;
wire reg_val_muxZ_2stage_n_4;
wire reg_val_muxZ_2stage_n_5;
wire reg_val_muxZ_2stage_n_6;
wire reg_val_muxZ_2stage_n_7;
wire reg_val_muxZ_2stage_n_8;
wire reg_val_muxZ_2stage_n_9;
wire reset_reg_cordic;
wire rst;
wire rst0;
wire rst_IBUF;
wire [1:0]shift_region_flag;
wire [1:0]shift_region_flag_IBUF;
wire underflow_flag;
wire underflow_flag_OBUF;
wire zero_flag;
wire zero_flag_OBUF;
Up_counter ITER_CONT
(.CLK(clk_IBUF_BUFG),
.D({ITER_CONT_n_5,ITER_CONT_n_6,ITER_CONT_n_7,ITER_CONT_n_8,ITER_CONT_n_9,ITER_CONT_n_10,ITER_CONT_n_11,ITER_CONT_n_12,ITER_CONT_n_13,ITER_CONT_n_14,ITER_CONT_n_15,ITER_CONT_n_16,ITER_CONT_n_17,ITER_CONT_n_18,ITER_CONT_n_19,ITER_CONT_n_20,ITER_CONT_n_21,ITER_CONT_n_22,ITER_CONT_n_23,ITER_CONT_n_24,ITER_CONT_n_25,ITER_CONT_n_26,ITER_CONT_n_27,ITER_CONT_n_28,ITER_CONT_n_29,ITER_CONT_n_30,ITER_CONT_n_31,ITER_CONT_n_32,ITER_CONT_n_33,ITER_CONT_n_34,ITER_CONT_n_35,ITER_CONT_n_36}),
.E(enab_cont_iter),
.Q(cont_iter_out),
.\Q_reg[26] ({data_out_LUT[26:24],ITER_CONT_n_104,data_out_LUT[22:21],ITER_CONT_n_107,ITER_CONT_n_108,ITER_CONT_n_109,data_out_LUT[14],data_out_LUT[12:9],p_1_out,data_out_LUT[6],data_out_LUT[4],ITER_CONT_n_118,ITER_CONT_n_119,data_out_LUT[0]}),
.\Q_reg[31] ({ITER_CONT_n_37,ITER_CONT_n_38,ITER_CONT_n_39,ITER_CONT_n_40,ITER_CONT_n_41,ITER_CONT_n_42,ITER_CONT_n_43,ITER_CONT_n_44,ITER_CONT_n_45,ITER_CONT_n_46,ITER_CONT_n_47,ITER_CONT_n_48,ITER_CONT_n_49,ITER_CONT_n_50,ITER_CONT_n_51,ITER_CONT_n_52,ITER_CONT_n_53,ITER_CONT_n_54,ITER_CONT_n_55,ITER_CONT_n_56,ITER_CONT_n_57,ITER_CONT_n_58,ITER_CONT_n_59,ITER_CONT_n_60,ITER_CONT_n_61,ITER_CONT_n_62,ITER_CONT_n_63,ITER_CONT_n_64,ITER_CONT_n_65,ITER_CONT_n_66,ITER_CONT_n_67,ITER_CONT_n_68}),
.\Q_reg[31]_0 ({ITER_CONT_n_69,ITER_CONT_n_70,ITER_CONT_n_71,ITER_CONT_n_72,ITER_CONT_n_73,ITER_CONT_n_74,ITER_CONT_n_75,ITER_CONT_n_76,ITER_CONT_n_77,ITER_CONT_n_78,ITER_CONT_n_79,ITER_CONT_n_80,ITER_CONT_n_81,ITER_CONT_n_82,ITER_CONT_n_83,ITER_CONT_n_84,ITER_CONT_n_85,ITER_CONT_n_86,ITER_CONT_n_87,ITER_CONT_n_88,ITER_CONT_n_89,ITER_CONT_n_90,ITER_CONT_n_91,ITER_CONT_n_92,ITER_CONT_n_93,ITER_CONT_n_94,ITER_CONT_n_95,ITER_CONT_n_96,ITER_CONT_n_97,ITER_CONT_n_98,ITER_CONT_n_99,ITER_CONT_n_100}),
.\Q_reg[31]_1 ({d_ff4_Zn_n_0,d_ff4_Zn_n_1,d_ff4_Zn_n_2,d_ff4_Zn_n_3,d_ff4_Zn_n_4,d_ff4_Zn_n_5,d_ff4_Zn_n_6,d_ff4_Zn_n_7,d_ff4_Zn_n_8,d_ff4_Zn_n_9,d_ff4_Zn_n_10,d_ff4_Zn_n_11,d_ff4_Zn_n_12,d_ff4_Zn_n_13,d_ff4_Zn_n_14,d_ff4_Zn_n_15,d_ff4_Zn_n_16,d_ff4_Zn_n_17,d_ff4_Zn_n_18,d_ff4_Zn_n_19,d_ff4_Zn_n_20,d_ff4_Zn_n_21,d_ff4_Zn_n_22,d_ff4_Zn_n_23,d_ff4_Zn_n_24,d_ff4_Zn_n_25,d_ff4_Zn_n_26,d_ff4_Zn_n_27,d_ff4_Zn_n_28,d_ff4_Zn_n_29,d_ff4_Zn_n_30,d_ff4_Zn_n_31}),
.\Q_reg[31]_2 ({reg_Z0_n_0,reg_Z0_n_1,reg_Z0_n_2,reg_Z0_n_3,reg_Z0_n_4,reg_Z0_n_5,reg_Z0_n_6,reg_Z0_n_7,reg_Z0_n_8,reg_Z0_n_9,reg_Z0_n_10,reg_Z0_n_11,reg_Z0_n_12,reg_Z0_n_13,reg_Z0_n_14,reg_Z0_n_15,reg_Z0_n_16,reg_Z0_n_17,reg_Z0_n_18,reg_Z0_n_19,reg_Z0_n_20,reg_Z0_n_21,reg_Z0_n_22,reg_Z0_n_23,reg_Z0_n_24,reg_Z0_n_25,reg_Z0_n_26,reg_Z0_n_27,reg_Z0_n_28,reg_Z0_n_29,reg_Z0_n_30,reg_Z0_n_31}),
.\Q_reg[31]_3 ({d_ff4_Xn_n_0,d_ff4_Xn_n_1,d_ff4_Xn_n_2,d_ff4_Xn_n_3,d_ff4_Xn_n_4,d_ff4_Xn_n_5,d_ff4_Xn_n_6,d_ff4_Xn_n_7,d_ff4_Xn_n_8,d_ff4_Xn_n_9,d_ff4_Xn_n_10,d_ff4_Xn_n_11,d_ff4_Xn_n_12,d_ff4_Xn_n_13,d_ff4_Xn_n_14,d_ff4_Xn_n_15,d_ff4_Xn_n_16,d_ff4_Xn_n_17,d_ff4_Xn_n_18,d_ff4_Xn_n_19,d_ff4_Xn_n_20,d_ff4_Xn_n_21,d_ff4_Xn_n_22,d_ff4_Xn_n_23,d_ff4_Xn_n_24,d_ff4_Xn_n_25,d_ff4_Xn_n_26,d_ff4_Xn_n_27,d_ff4_Xn_n_28,d_ff4_Xn_n_29,d_ff4_Xn_n_30,d_ff4_Xn_n_31}),
.\Q_reg[31]_4 ({d_ff4_Yn_n_0,d_ff4_Yn_n_1,d_ff4_Yn_n_2,d_ff4_Yn_n_3,d_ff4_Yn_n_4,d_ff4_Yn_n_5,d_ff4_Yn_n_6,d_ff4_Yn_n_7,d_ff4_Yn_n_8,d_ff4_Yn_n_9,d_ff4_Yn_n_10,d_ff4_Yn_n_11,d_ff4_Yn_n_12,d_ff4_Yn_n_13,d_ff4_Yn_n_14,d_ff4_Yn_n_15,d_ff4_Yn_n_16,d_ff4_Yn_n_17,d_ff4_Yn_n_18,d_ff4_Yn_n_19,d_ff4_Yn_n_20,d_ff4_Yn_n_21,d_ff4_Yn_n_22,d_ff4_Yn_n_23,d_ff4_Yn_n_24,d_ff4_Yn_n_25,d_ff4_Yn_n_26,d_ff4_Yn_n_27,d_ff4_Yn_n_28,d_ff4_Yn_n_29,d_ff4_Yn_n_30,d_ff4_Yn_n_31}),
.SR(reset_reg_cordic),
.max_tick_iter(max_tick_iter));
Up_counter__parameterized0 VAR_CONT
(.CLK(clk_IBUF_BUFG),
.D({VAR_CONT_n_5,VAR_CONT_n_6,VAR_CONT_n_7,VAR_CONT_n_8,VAR_CONT_n_9,VAR_CONT_n_10,VAR_CONT_n_11,VAR_CONT_n_12,VAR_CONT_n_13,VAR_CONT_n_14,VAR_CONT_n_15,VAR_CONT_n_16,VAR_CONT_n_17,VAR_CONT_n_18,VAR_CONT_n_19,VAR_CONT_n_20,VAR_CONT_n_21,VAR_CONT_n_22,VAR_CONT_n_23,VAR_CONT_n_24,VAR_CONT_n_25,VAR_CONT_n_26,VAR_CONT_n_27,VAR_CONT_n_28,VAR_CONT_n_29,VAR_CONT_n_30,VAR_CONT_n_31,VAR_CONT_n_32,VAR_CONT_n_33,VAR_CONT_n_34,VAR_CONT_n_35,VAR_CONT_n_36}),
.E(enab_d_ff4_Zn),
.Q({reg_shift_y_n_0,reg_shift_y_n_1,reg_shift_y_n_2,reg_shift_y_n_3,reg_shift_y_n_4,reg_shift_y_n_5,reg_shift_y_n_6,reg_shift_y_n_7,reg_shift_y_n_8,reg_shift_y_n_9,reg_shift_y_n_10,reg_shift_y_n_11,reg_shift_y_n_12,reg_shift_y_n_13,reg_shift_y_n_14,reg_shift_y_n_15,reg_shift_y_n_16,reg_shift_y_n_17,reg_shift_y_n_18,reg_shift_y_n_19,reg_shift_y_n_20,reg_shift_y_n_21,reg_shift_y_n_22,reg_shift_y_n_23,reg_shift_y_n_24,reg_shift_y_n_25,reg_shift_y_n_26,reg_shift_y_n_27,reg_shift_y_n_28,reg_shift_y_n_29,reg_shift_y_n_30,reg_shift_y_n_31}),
.\Q_reg[29] ({reg_LUT_n_0,reg_LUT_n_1,reg_LUT_n_2,reg_LUT_n_3,reg_LUT_n_4,reg_LUT_n_5,reg_LUT_n_6,reg_LUT_n_7,reg_LUT_n_8,reg_LUT_n_9,reg_LUT_n_10,reg_LUT_n_11,reg_LUT_n_12,reg_LUT_n_13,reg_LUT_n_14,reg_LUT_n_15,reg_LUT_n_16,reg_LUT_n_17,reg_LUT_n_18,reg_LUT_n_19,reg_LUT_n_20}),
.\Q_reg[31] (VAR_CONT_n_3),
.\Q_reg[31]_0 (enab_d_ff4_Yn),
.\Q_reg[31]_1 ({VAR_CONT_n_37,VAR_CONT_n_38,VAR_CONT_n_39,VAR_CONT_n_40,VAR_CONT_n_41,VAR_CONT_n_42,VAR_CONT_n_43,VAR_CONT_n_44,VAR_CONT_n_45,VAR_CONT_n_46,VAR_CONT_n_47,VAR_CONT_n_48,VAR_CONT_n_49,VAR_CONT_n_50,VAR_CONT_n_51,VAR_CONT_n_52,VAR_CONT_n_53,VAR_CONT_n_54,VAR_CONT_n_55,VAR_CONT_n_56,VAR_CONT_n_57,VAR_CONT_n_58,VAR_CONT_n_59,VAR_CONT_n_60,VAR_CONT_n_61,VAR_CONT_n_62,VAR_CONT_n_63,VAR_CONT_n_64,VAR_CONT_n_65,VAR_CONT_n_66,VAR_CONT_n_67,VAR_CONT_n_68}),
.\Q_reg[31]_2 ({reg_shift_x_n_0,reg_shift_x_n_1,reg_shift_x_n_2,reg_shift_x_n_3,reg_shift_x_n_4,reg_shift_x_n_5,reg_shift_x_n_6,reg_shift_x_n_7,reg_shift_x_n_8,reg_shift_x_n_9,reg_shift_x_n_10,reg_shift_x_n_11,reg_shift_x_n_12,reg_shift_x_n_13,reg_shift_x_n_14,reg_shift_x_n_15,reg_shift_x_n_16,reg_shift_x_n_17,reg_shift_x_n_18,reg_shift_x_n_19,reg_shift_x_n_20,reg_shift_x_n_21,reg_shift_x_n_22,reg_shift_x_n_23,reg_shift_x_n_24,reg_shift_x_n_25,reg_shift_x_n_26,reg_shift_x_n_27,reg_shift_x_n_28,reg_shift_x_n_29,reg_shift_x_n_30,reg_shift_x_n_31}),
.\Q_reg[31]_3 ({d_ff2_Z,reg_val_muxZ_2stage_n_1,reg_val_muxZ_2stage_n_2,reg_val_muxZ_2stage_n_3,reg_val_muxZ_2stage_n_4,reg_val_muxZ_2stage_n_5,reg_val_muxZ_2stage_n_6,reg_val_muxZ_2stage_n_7,reg_val_muxZ_2stage_n_8,reg_val_muxZ_2stage_n_9,reg_val_muxZ_2stage_n_10,reg_val_muxZ_2stage_n_11,reg_val_muxZ_2stage_n_12,reg_val_muxZ_2stage_n_13,reg_val_muxZ_2stage_n_14,reg_val_muxZ_2stage_n_15,reg_val_muxZ_2stage_n_16,reg_val_muxZ_2stage_n_17,reg_val_muxZ_2stage_n_18,reg_val_muxZ_2stage_n_19,reg_val_muxZ_2stage_n_20,reg_val_muxZ_2stage_n_21,reg_val_muxZ_2stage_n_22,reg_val_muxZ_2stage_n_23,reg_val_muxZ_2stage_n_24,reg_val_muxZ_2stage_n_25,reg_val_muxZ_2stage_n_26,reg_val_muxZ_2stage_n_27,reg_val_muxZ_2stage_n_28,reg_val_muxZ_2stage_n_29,reg_val_muxZ_2stage_n_30,reg_val_muxZ_2stage_n_31}),
.\Q_reg[31]_4 ({reg_val_muxX_2stage_n_4,A,reg_val_muxX_2stage_n_13,reg_val_muxX_2stage_n_14,reg_val_muxX_2stage_n_15,reg_val_muxX_2stage_n_16,reg_val_muxX_2stage_n_17,reg_val_muxX_2stage_n_18,reg_val_muxX_2stage_n_19,reg_val_muxX_2stage_n_20,reg_val_muxX_2stage_n_21,reg_val_muxX_2stage_n_22,reg_val_muxX_2stage_n_23,reg_val_muxX_2stage_n_24,reg_val_muxX_2stage_n_25,reg_val_muxX_2stage_n_26,reg_val_muxX_2stage_n_27,reg_val_muxX_2stage_n_28,reg_val_muxX_2stage_n_29,reg_val_muxX_2stage_n_30,reg_val_muxX_2stage_n_31,reg_val_muxX_2stage_n_32,reg_val_muxX_2stage_n_33,reg_val_muxX_2stage_n_34,reg_val_muxX_2stage_n_35}),
.\Q_reg[31]_5 ({d_ff2_Y,reg_val_muxY_2stage_n_1,reg_val_muxY_2stage_n_2,reg_val_muxY_2stage_n_3,reg_val_muxY_2stage_n_4,reg_val_muxY_2stage_n_5,reg_val_muxY_2stage_n_6,reg_val_muxY_2stage_n_7,reg_val_muxY_2stage_n_8,reg_val_muxY_2stage_n_9,reg_val_muxY_2stage_n_10,reg_val_muxY_2stage_n_11,reg_val_muxY_2stage_n_12,reg_val_muxY_2stage_n_13,reg_val_muxY_2stage_n_14,reg_val_muxY_2stage_n_15,reg_val_muxY_2stage_n_16,reg_val_muxY_2stage_n_17,reg_val_muxY_2stage_n_18,reg_val_muxY_2stage_n_19,reg_val_muxY_2stage_n_20,reg_val_muxY_2stage_n_21,reg_val_muxY_2stage_n_22,reg_val_muxY_2stage_n_23,reg_val_muxY_2stage_n_24,reg_val_muxY_2stage_n_25,reg_val_muxY_2stage_n_26,reg_val_muxY_2stage_n_27,reg_val_muxY_2stage_n_28,reg_val_muxY_2stage_n_29,reg_val_muxY_2stage_n_30,reg_val_muxY_2stage_n_31}),
.cont_var_out(cont_var_out),
.d_ff3_sign_out(d_ff3_sign_out),
.op_add_subt(op_add_subt),
.out({inst_CORDIC_FSM_v3_n_4,inst_CORDIC_FSM_v3_n_6}),
.ready_add_subt(ready_add_subt),
.rst_IBUF(rst_IBUF));
IBUF ack_cordic_IBUF_inst
(.I(ack_cordic),
.O(ack_cordic_IBUF));
IBUF beg_fsm_cordic_IBUF_inst
(.I(beg_fsm_cordic),
.O(beg_fsm_cordic_IBUF));
OBUF busy_OBUF_inst
(.I(busy_OBUF),
.O(busy));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
d_ff_en__parameterized8 d_ff4_Xn
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.E(VAR_CONT_n_3),
.Q({d_ff4_Xn_n_0,d_ff4_Xn_n_1,d_ff4_Xn_n_2,d_ff4_Xn_n_3,d_ff4_Xn_n_4,d_ff4_Xn_n_5,d_ff4_Xn_n_6,d_ff4_Xn_n_7,d_ff4_Xn_n_8,d_ff4_Xn_n_9,d_ff4_Xn_n_10,d_ff4_Xn_n_11,d_ff4_Xn_n_12,d_ff4_Xn_n_13,d_ff4_Xn_n_14,d_ff4_Xn_n_15,d_ff4_Xn_n_16,d_ff4_Xn_n_17,d_ff4_Xn_n_18,d_ff4_Xn_n_19,d_ff4_Xn_n_20,d_ff4_Xn_n_21,d_ff4_Xn_n_22,d_ff4_Xn_n_23,d_ff4_Xn_n_24,d_ff4_Xn_n_25,d_ff4_Xn_n_26,d_ff4_Xn_n_27,d_ff4_Xn_n_28,d_ff4_Xn_n_29,d_ff4_Xn_n_30,d_ff4_Xn_n_31}),
.\Q_reg[31]_0 ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}));
d_ff_en__parameterized9 d_ff4_Yn
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.E(enab_d_ff4_Yn),
.Q({d_ff4_Yn_n_0,d_ff4_Yn_n_1,d_ff4_Yn_n_2,d_ff4_Yn_n_3,d_ff4_Yn_n_4,d_ff4_Yn_n_5,d_ff4_Yn_n_6,d_ff4_Yn_n_7,d_ff4_Yn_n_8,d_ff4_Yn_n_9,d_ff4_Yn_n_10,d_ff4_Yn_n_11,d_ff4_Yn_n_12,d_ff4_Yn_n_13,d_ff4_Yn_n_14,d_ff4_Yn_n_15,d_ff4_Yn_n_16,d_ff4_Yn_n_17,d_ff4_Yn_n_18,d_ff4_Yn_n_19,d_ff4_Yn_n_20,d_ff4_Yn_n_21,d_ff4_Yn_n_22,d_ff4_Yn_n_23,d_ff4_Yn_n_24,d_ff4_Yn_n_25,d_ff4_Yn_n_26,d_ff4_Yn_n_27,d_ff4_Yn_n_28,d_ff4_Yn_n_29,d_ff4_Yn_n_30,d_ff4_Yn_n_31}),
.\Q_reg[31]_0 ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}));
d_ff_en__parameterized10 d_ff4_Zn
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.E(enab_d_ff4_Zn),
.Q({d_ff4_Zn_n_0,d_ff4_Zn_n_1,d_ff4_Zn_n_2,d_ff4_Zn_n_3,d_ff4_Zn_n_4,d_ff4_Zn_n_5,d_ff4_Zn_n_6,d_ff4_Zn_n_7,d_ff4_Zn_n_8,d_ff4_Zn_n_9,d_ff4_Zn_n_10,d_ff4_Zn_n_11,d_ff4_Zn_n_12,d_ff4_Zn_n_13,d_ff4_Zn_n_14,d_ff4_Zn_n_15,d_ff4_Zn_n_16,d_ff4_Zn_n_17,d_ff4_Zn_n_18,d_ff4_Zn_n_19,d_ff4_Zn_n_20,d_ff4_Zn_n_21,d_ff4_Zn_n_22,d_ff4_Zn_n_23,d_ff4_Zn_n_24,d_ff4_Zn_n_25,d_ff4_Zn_n_26,d_ff4_Zn_n_27,d_ff4_Zn_n_28,d_ff4_Zn_n_29,d_ff4_Zn_n_30,d_ff4_Zn_n_31}),
.\Q_reg[31]_0 ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}));
d_ff_en__parameterized11 d_ff5_data_out
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.D({reg_region_flag_n_0,reg_region_flag_n_1,reg_region_flag_n_2,reg_region_flag_n_3,reg_region_flag_n_4,reg_region_flag_n_5,reg_region_flag_n_6,reg_region_flag_n_7,reg_region_flag_n_8,reg_region_flag_n_9,reg_region_flag_n_10,reg_region_flag_n_11,reg_region_flag_n_12,reg_region_flag_n_13,reg_region_flag_n_14,reg_region_flag_n_15,reg_region_flag_n_16,reg_region_flag_n_17,reg_region_flag_n_18,reg_region_flag_n_19,reg_region_flag_n_20,reg_region_flag_n_21,reg_region_flag_n_22,reg_region_flag_n_23,reg_region_flag_n_24,reg_region_flag_n_25,reg_region_flag_n_26,reg_region_flag_n_27,reg_region_flag_n_28,reg_region_flag_n_29,reg_region_flag_n_30,reg_region_flag_n_31}),
.E(enab_d_ff5_data_out),
.Q(data_output_OBUF));
IBUF \data_in_IBUF[0]_inst
(.I(data_in[0]),
.O(data_in_IBUF[0]));
IBUF \data_in_IBUF[10]_inst
(.I(data_in[10]),
.O(data_in_IBUF[10]));
IBUF \data_in_IBUF[11]_inst
(.I(data_in[11]),
.O(data_in_IBUF[11]));
IBUF \data_in_IBUF[12]_inst
(.I(data_in[12]),
.O(data_in_IBUF[12]));
IBUF \data_in_IBUF[13]_inst
(.I(data_in[13]),
.O(data_in_IBUF[13]));
IBUF \data_in_IBUF[14]_inst
(.I(data_in[14]),
.O(data_in_IBUF[14]));
IBUF \data_in_IBUF[15]_inst
(.I(data_in[15]),
.O(data_in_IBUF[15]));
IBUF \data_in_IBUF[16]_inst
(.I(data_in[16]),
.O(data_in_IBUF[16]));
IBUF \data_in_IBUF[17]_inst
(.I(data_in[17]),
.O(data_in_IBUF[17]));
IBUF \data_in_IBUF[18]_inst
(.I(data_in[18]),
.O(data_in_IBUF[18]));
IBUF \data_in_IBUF[19]_inst
(.I(data_in[19]),
.O(data_in_IBUF[19]));
IBUF \data_in_IBUF[1]_inst
(.I(data_in[1]),
.O(data_in_IBUF[1]));
IBUF \data_in_IBUF[20]_inst
(.I(data_in[20]),
.O(data_in_IBUF[20]));
IBUF \data_in_IBUF[21]_inst
(.I(data_in[21]),
.O(data_in_IBUF[21]));
IBUF \data_in_IBUF[22]_inst
(.I(data_in[22]),
.O(data_in_IBUF[22]));
IBUF \data_in_IBUF[23]_inst
(.I(data_in[23]),
.O(data_in_IBUF[23]));
IBUF \data_in_IBUF[24]_inst
(.I(data_in[24]),
.O(data_in_IBUF[24]));
IBUF \data_in_IBUF[25]_inst
(.I(data_in[25]),
.O(data_in_IBUF[25]));
IBUF \data_in_IBUF[26]_inst
(.I(data_in[26]),
.O(data_in_IBUF[26]));
IBUF \data_in_IBUF[27]_inst
(.I(data_in[27]),
.O(data_in_IBUF[27]));
IBUF \data_in_IBUF[28]_inst
(.I(data_in[28]),
.O(data_in_IBUF[28]));
IBUF \data_in_IBUF[29]_inst
(.I(data_in[29]),
.O(data_in_IBUF[29]));
IBUF \data_in_IBUF[2]_inst
(.I(data_in[2]),
.O(data_in_IBUF[2]));
IBUF \data_in_IBUF[30]_inst
(.I(data_in[30]),
.O(data_in_IBUF[30]));
IBUF \data_in_IBUF[31]_inst
(.I(data_in[31]),
.O(data_in_IBUF[31]));
IBUF \data_in_IBUF[3]_inst
(.I(data_in[3]),
.O(data_in_IBUF[3]));
IBUF \data_in_IBUF[4]_inst
(.I(data_in[4]),
.O(data_in_IBUF[4]));
IBUF \data_in_IBUF[5]_inst
(.I(data_in[5]),
.O(data_in_IBUF[5]));
IBUF \data_in_IBUF[6]_inst
(.I(data_in[6]),
.O(data_in_IBUF[6]));
IBUF \data_in_IBUF[7]_inst
(.I(data_in[7]),
.O(data_in_IBUF[7]));
IBUF \data_in_IBUF[8]_inst
(.I(data_in[8]),
.O(data_in_IBUF[8]));
IBUF \data_in_IBUF[9]_inst
(.I(data_in[9]),
.O(data_in_IBUF[9]));
OBUF \data_output_OBUF[0]_inst
(.I(data_output_OBUF[0]),
.O(data_output[0]));
OBUF \data_output_OBUF[10]_inst
(.I(data_output_OBUF[10]),
.O(data_output[10]));
OBUF \data_output_OBUF[11]_inst
(.I(data_output_OBUF[11]),
.O(data_output[11]));
OBUF \data_output_OBUF[12]_inst
(.I(data_output_OBUF[12]),
.O(data_output[12]));
OBUF \data_output_OBUF[13]_inst
(.I(data_output_OBUF[13]),
.O(data_output[13]));
OBUF \data_output_OBUF[14]_inst
(.I(data_output_OBUF[14]),
.O(data_output[14]));
OBUF \data_output_OBUF[15]_inst
(.I(data_output_OBUF[15]),
.O(data_output[15]));
OBUF \data_output_OBUF[16]_inst
(.I(data_output_OBUF[16]),
.O(data_output[16]));
OBUF \data_output_OBUF[17]_inst
(.I(data_output_OBUF[17]),
.O(data_output[17]));
OBUF \data_output_OBUF[18]_inst
(.I(data_output_OBUF[18]),
.O(data_output[18]));
OBUF \data_output_OBUF[19]_inst
(.I(data_output_OBUF[19]),
.O(data_output[19]));
OBUF \data_output_OBUF[1]_inst
(.I(data_output_OBUF[1]),
.O(data_output[1]));
OBUF \data_output_OBUF[20]_inst
(.I(data_output_OBUF[20]),
.O(data_output[20]));
OBUF \data_output_OBUF[21]_inst
(.I(data_output_OBUF[21]),
.O(data_output[21]));
OBUF \data_output_OBUF[22]_inst
(.I(data_output_OBUF[22]),
.O(data_output[22]));
OBUF \data_output_OBUF[23]_inst
(.I(data_output_OBUF[23]),
.O(data_output[23]));
OBUF \data_output_OBUF[24]_inst
(.I(data_output_OBUF[24]),
.O(data_output[24]));
OBUF \data_output_OBUF[25]_inst
(.I(data_output_OBUF[25]),
.O(data_output[25]));
OBUF \data_output_OBUF[26]_inst
(.I(data_output_OBUF[26]),
.O(data_output[26]));
OBUF \data_output_OBUF[27]_inst
(.I(data_output_OBUF[27]),
.O(data_output[27]));
OBUF \data_output_OBUF[28]_inst
(.I(data_output_OBUF[28]),
.O(data_output[28]));
OBUF \data_output_OBUF[29]_inst
(.I(data_output_OBUF[29]),
.O(data_output[29]));
OBUF \data_output_OBUF[2]_inst
(.I(data_output_OBUF[2]),
.O(data_output[2]));
OBUF \data_output_OBUF[30]_inst
(.I(data_output_OBUF[30]),
.O(data_output[30]));
OBUF \data_output_OBUF[31]_inst
(.I(data_output_OBUF[31]),
.O(data_output[31]));
OBUF \data_output_OBUF[3]_inst
(.I(data_output_OBUF[3]),
.O(data_output[3]));
OBUF \data_output_OBUF[4]_inst
(.I(data_output_OBUF[4]),
.O(data_output[4]));
OBUF \data_output_OBUF[5]_inst
(.I(data_output_OBUF[5]),
.O(data_output[5]));
OBUF \data_output_OBUF[6]_inst
(.I(data_output_OBUF[6]),
.O(data_output[6]));
OBUF \data_output_OBUF[7]_inst
(.I(data_output_OBUF[7]),
.O(data_output[7]));
OBUF \data_output_OBUF[8]_inst
(.I(data_output_OBUF[8]),
.O(data_output[8]));
OBUF \data_output_OBUF[9]_inst
(.I(data_output_OBUF[9]),
.O(data_output[9]));
CORDIC_FSM_v3 inst_CORDIC_FSM_v3
(.AR({inst_CORDIC_FSM_v3_n_0,inst_CORDIC_FSM_v3_n_1,rst0,inst_CORDIC_FSM_v3_n_3}),
.CLK(clk_IBUF_BUFG),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[0]_0 (inst_CORDIC_FSM_v3_n_7),
.\FSM_sequential_state_reg_reg[2]_0 (inst_FPU_PIPELINED_FPADDSUB_n_37),
.\Q_reg[0] (enab_RB3),
.\Q_reg[1] (enab_d_ff_RB1),
.\Q_reg[31] (inst_CORDIC_FSM_v3_n_9),
.\Q_reg[31]_0 (enab_d_ff5_data_out),
.\Q_reg[31]_1 (reset_reg_cordic),
.ack_cordic_IBUF(ack_cordic_IBUF),
.beg_fsm_cordic_IBUF(beg_fsm_cordic_IBUF),
.cont_var_out(cont_var_out),
.max_tick_iter(max_tick_iter),
.out({inst_CORDIC_FSM_v3_n_4,inst_CORDIC_FSM_v3_n_5,inst_CORDIC_FSM_v3_n_6}),
.ready_cordic_OBUF(ready_cordic_OBUF),
.rst_IBUF(rst_IBUF),
.\temp_reg[0] (enab_cont_iter),
.\temp_reg[1] (enab_d_ff4_Zn));
FPU_PIPELINED_FPADDSUB inst_FPU_PIPELINED_FPADDSUB
(.AR({inst_CORDIC_FSM_v3_n_0,inst_CORDIC_FSM_v3_n_1,rst0,inst_CORDIC_FSM_v3_n_3}),
.CLK(clk_IBUF_BUFG),
.D({VAR_CONT_n_5,VAR_CONT_n_6,VAR_CONT_n_7,VAR_CONT_n_8,VAR_CONT_n_9,VAR_CONT_n_10,VAR_CONT_n_11,VAR_CONT_n_12,VAR_CONT_n_13,VAR_CONT_n_14,VAR_CONT_n_15,VAR_CONT_n_16,VAR_CONT_n_17,VAR_CONT_n_18,VAR_CONT_n_19,VAR_CONT_n_20,VAR_CONT_n_21,VAR_CONT_n_22,VAR_CONT_n_23,VAR_CONT_n_24,VAR_CONT_n_25,VAR_CONT_n_26,VAR_CONT_n_27,VAR_CONT_n_28,VAR_CONT_n_29,VAR_CONT_n_30,VAR_CONT_n_31,VAR_CONT_n_32,VAR_CONT_n_33,VAR_CONT_n_34,VAR_CONT_n_35,VAR_CONT_n_36}),
.E(inst_CORDIC_FSM_v3_n_9),
.\FSM_sequential_state_reg_reg[1] (inst_CORDIC_FSM_v3_n_7),
.\FSM_sequential_state_reg_reg[2] ({inst_CORDIC_FSM_v3_n_4,inst_CORDIC_FSM_v3_n_5}),
.Q(busy_OBUF),
.\Q_reg[31] ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}),
.\Q_reg[31]_0 ({VAR_CONT_n_37,VAR_CONT_n_38,VAR_CONT_n_39,VAR_CONT_n_40,VAR_CONT_n_41,VAR_CONT_n_42,VAR_CONT_n_43,VAR_CONT_n_44,VAR_CONT_n_45,VAR_CONT_n_46,VAR_CONT_n_47,VAR_CONT_n_48,VAR_CONT_n_49,VAR_CONT_n_50,VAR_CONT_n_51,VAR_CONT_n_52,VAR_CONT_n_53,VAR_CONT_n_54,VAR_CONT_n_55,VAR_CONT_n_56,VAR_CONT_n_57,VAR_CONT_n_58,VAR_CONT_n_59,VAR_CONT_n_60,VAR_CONT_n_61,VAR_CONT_n_62,VAR_CONT_n_63,VAR_CONT_n_64,VAR_CONT_n_65,VAR_CONT_n_66,VAR_CONT_n_67,VAR_CONT_n_68}),
.op_add_subt(op_add_subt),
.out(inst_FPU_PIPELINED_FPADDSUB_n_37),
.overflow_flag({overflow_flag_OBUF,underflow_flag_OBUF,zero_flag_OBUF}),
.ready_add_subt(ready_add_subt));
IBUF operation_IBUF_inst
(.I(operation),
.O(operation_IBUF));
OBUF overflow_flag_OBUF_inst
(.I(overflow_flag_OBUF),
.O(overflow_flag));
OBUF ready_cordic_OBUF_inst
(.I(ready_cordic_OBUF),
.O(ready_cordic));
d_ff_en__parameterized7 reg_LUT
(.CLK(clk_IBUF_BUFG),
.D({data_out_LUT[26:24],ITER_CONT_n_104,data_out_LUT[22:21],ITER_CONT_n_107,ITER_CONT_n_108,ITER_CONT_n_109,data_out_LUT[14],data_out_LUT[12:9],p_1_out,data_out_LUT[6],data_out_LUT[4],ITER_CONT_n_118,ITER_CONT_n_119,data_out_LUT[0]}),
.E(enab_RB3),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_LUT_n_0,reg_LUT_n_1,reg_LUT_n_2,reg_LUT_n_3,reg_LUT_n_4,reg_LUT_n_5,reg_LUT_n_6,reg_LUT_n_7,reg_LUT_n_8,reg_LUT_n_9,reg_LUT_n_10,reg_LUT_n_11,reg_LUT_n_12,reg_LUT_n_13,reg_LUT_n_14,reg_LUT_n_15,reg_LUT_n_16,reg_LUT_n_17,reg_LUT_n_18,reg_LUT_n_19,reg_LUT_n_20}));
d_ff_en__parameterized1 reg_Z0
(.CLK(clk_IBUF_BUFG),
.D(data_in_IBUF),
.E(enab_d_ff_RB1),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_Z0_n_0,reg_Z0_n_1,reg_Z0_n_2,reg_Z0_n_3,reg_Z0_n_4,reg_Z0_n_5,reg_Z0_n_6,reg_Z0_n_7,reg_Z0_n_8,reg_Z0_n_9,reg_Z0_n_10,reg_Z0_n_11,reg_Z0_n_12,reg_Z0_n_13,reg_Z0_n_14,reg_Z0_n_15,reg_Z0_n_16,reg_Z0_n_17,reg_Z0_n_18,reg_Z0_n_19,reg_Z0_n_20,reg_Z0_n_21,reg_Z0_n_22,reg_Z0_n_23,reg_Z0_n_24,reg_Z0_n_25,reg_Z0_n_26,reg_Z0_n_27,reg_Z0_n_28,reg_Z0_n_29,reg_Z0_n_30,reg_Z0_n_31}));
d_ff_en reg_operation
(.CLK(clk_IBUF_BUFG),
.E(enab_d_ff_RB1),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.d_ff1_operation_out(d_ff1_operation_out),
.operation_IBUF(operation_IBUF));
d_ff_en__parameterized0 reg_region_flag
(.CLK(clk_IBUF_BUFG),
.D({reg_region_flag_n_0,reg_region_flag_n_1,reg_region_flag_n_2,reg_region_flag_n_3,reg_region_flag_n_4,reg_region_flag_n_5,reg_region_flag_n_6,reg_region_flag_n_7,reg_region_flag_n_8,reg_region_flag_n_9,reg_region_flag_n_10,reg_region_flag_n_11,reg_region_flag_n_12,reg_region_flag_n_13,reg_region_flag_n_14,reg_region_flag_n_15,reg_region_flag_n_16,reg_region_flag_n_17,reg_region_flag_n_18,reg_region_flag_n_19,reg_region_flag_n_20,reg_region_flag_n_21,reg_region_flag_n_22,reg_region_flag_n_23,reg_region_flag_n_24,reg_region_flag_n_25,reg_region_flag_n_26,reg_region_flag_n_27,reg_region_flag_n_28,reg_region_flag_n_29,reg_region_flag_n_30,reg_region_flag_n_31}),
.E(enab_d_ff_RB1),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({d_ff4_Yn_n_0,d_ff4_Yn_n_1,d_ff4_Yn_n_2,d_ff4_Yn_n_3,d_ff4_Yn_n_4,d_ff4_Yn_n_5,d_ff4_Yn_n_6,d_ff4_Yn_n_7,d_ff4_Yn_n_8,d_ff4_Yn_n_9,d_ff4_Yn_n_10,d_ff4_Yn_n_11,d_ff4_Yn_n_12,d_ff4_Yn_n_13,d_ff4_Yn_n_14,d_ff4_Yn_n_15,d_ff4_Yn_n_16,d_ff4_Yn_n_17,d_ff4_Yn_n_18,d_ff4_Yn_n_19,d_ff4_Yn_n_20,d_ff4_Yn_n_21,d_ff4_Yn_n_22,d_ff4_Yn_n_23,d_ff4_Yn_n_24,d_ff4_Yn_n_25,d_ff4_Yn_n_26,d_ff4_Yn_n_27,d_ff4_Yn_n_28,d_ff4_Yn_n_29,d_ff4_Yn_n_30,d_ff4_Yn_n_31}),
.\Q_reg[31] ({d_ff4_Xn_n_0,d_ff4_Xn_n_1,d_ff4_Xn_n_2,d_ff4_Xn_n_3,d_ff4_Xn_n_4,d_ff4_Xn_n_5,d_ff4_Xn_n_6,d_ff4_Xn_n_7,d_ff4_Xn_n_8,d_ff4_Xn_n_9,d_ff4_Xn_n_10,d_ff4_Xn_n_11,d_ff4_Xn_n_12,d_ff4_Xn_n_13,d_ff4_Xn_n_14,d_ff4_Xn_n_15,d_ff4_Xn_n_16,d_ff4_Xn_n_17,d_ff4_Xn_n_18,d_ff4_Xn_n_19,d_ff4_Xn_n_20,d_ff4_Xn_n_21,d_ff4_Xn_n_22,d_ff4_Xn_n_23,d_ff4_Xn_n_24,d_ff4_Xn_n_25,d_ff4_Xn_n_26,d_ff4_Xn_n_27,d_ff4_Xn_n_28,d_ff4_Xn_n_29,d_ff4_Xn_n_30,d_ff4_Xn_n_31}),
.d_ff1_operation_out(d_ff1_operation_out),
.\shift_region_flag[1] (shift_region_flag_IBUF));
d_ff_en__parameterized5 reg_shift_x
(.CLK(clk_IBUF_BUFG),
.D({reg_val_muxX_2stage_n_4,Y,reg_val_muxX_2stage_n_13,reg_val_muxX_2stage_n_14,reg_val_muxX_2stage_n_15,reg_val_muxX_2stage_n_16,reg_val_muxX_2stage_n_17,reg_val_muxX_2stage_n_18,reg_val_muxX_2stage_n_19,reg_val_muxX_2stage_n_20,reg_val_muxX_2stage_n_21,reg_val_muxX_2stage_n_22,reg_val_muxX_2stage_n_23,reg_val_muxX_2stage_n_24,reg_val_muxX_2stage_n_25,reg_val_muxX_2stage_n_26,reg_val_muxX_2stage_n_27,reg_val_muxX_2stage_n_28,reg_val_muxX_2stage_n_29,reg_val_muxX_2stage_n_30,reg_val_muxX_2stage_n_31,reg_val_muxX_2stage_n_32,reg_val_muxX_2stage_n_33,reg_val_muxX_2stage_n_34,reg_val_muxX_2stage_n_35}),
.E(enab_RB3),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_shift_x_n_0,reg_shift_x_n_1,reg_shift_x_n_2,reg_shift_x_n_3,reg_shift_x_n_4,reg_shift_x_n_5,reg_shift_x_n_6,reg_shift_x_n_7,reg_shift_x_n_8,reg_shift_x_n_9,reg_shift_x_n_10,reg_shift_x_n_11,reg_shift_x_n_12,reg_shift_x_n_13,reg_shift_x_n_14,reg_shift_x_n_15,reg_shift_x_n_16,reg_shift_x_n_17,reg_shift_x_n_18,reg_shift_x_n_19,reg_shift_x_n_20,reg_shift_x_n_21,reg_shift_x_n_22,reg_shift_x_n_23,reg_shift_x_n_24,reg_shift_x_n_25,reg_shift_x_n_26,reg_shift_x_n_27,reg_shift_x_n_28,reg_shift_x_n_29,reg_shift_x_n_30,reg_shift_x_n_31}));
d_ff_en__parameterized6 reg_shift_y
(.CLK(clk_IBUF_BUFG),
.D({d_ff2_Y,reg_val_muxY_2stage_n_32,reg_val_muxY_2stage_n_33,reg_val_muxY_2stage_n_34,reg_val_muxY_2stage_n_35,reg_val_muxY_2stage_n_36,reg_val_muxY_2stage_n_37,reg_val_muxY_2stage_n_38,reg_val_muxY_2stage_n_39,reg_val_muxY_2stage_n_9,reg_val_muxY_2stage_n_10,reg_val_muxY_2stage_n_11,reg_val_muxY_2stage_n_12,reg_val_muxY_2stage_n_13,reg_val_muxY_2stage_n_14,reg_val_muxY_2stage_n_15,reg_val_muxY_2stage_n_16,reg_val_muxY_2stage_n_17,reg_val_muxY_2stage_n_18,reg_val_muxY_2stage_n_19,reg_val_muxY_2stage_n_20,reg_val_muxY_2stage_n_21,reg_val_muxY_2stage_n_22,reg_val_muxY_2stage_n_23,reg_val_muxY_2stage_n_24,reg_val_muxY_2stage_n_25,reg_val_muxY_2stage_n_26,reg_val_muxY_2stage_n_27,reg_val_muxY_2stage_n_28,reg_val_muxY_2stage_n_29,reg_val_muxY_2stage_n_30,reg_val_muxY_2stage_n_31}),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.\FSM_sequential_state_reg_reg[2] (enab_RB3),
.Q({reg_shift_y_n_0,reg_shift_y_n_1,reg_shift_y_n_2,reg_shift_y_n_3,reg_shift_y_n_4,reg_shift_y_n_5,reg_shift_y_n_6,reg_shift_y_n_7,reg_shift_y_n_8,reg_shift_y_n_9,reg_shift_y_n_10,reg_shift_y_n_11,reg_shift_y_n_12,reg_shift_y_n_13,reg_shift_y_n_14,reg_shift_y_n_15,reg_shift_y_n_16,reg_shift_y_n_17,reg_shift_y_n_18,reg_shift_y_n_19,reg_shift_y_n_20,reg_shift_y_n_21,reg_shift_y_n_22,reg_shift_y_n_23,reg_shift_y_n_24,reg_shift_y_n_25,reg_shift_y_n_26,reg_shift_y_n_27,reg_shift_y_n_28,reg_shift_y_n_29,reg_shift_y_n_30,reg_shift_y_n_31}));
d_ff_en_0 reg_sign
(.CLK(clk_IBUF_BUFG),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.\FSM_sequential_state_reg_reg[2] (enab_RB3),
.Q(d_ff2_Z),
.d_ff3_sign_out(d_ff3_sign_out));
d_ff_en__parameterized2 reg_val_muxX_2stage
(.CLK(clk_IBUF_BUFG),
.D({ITER_CONT_n_37,ITER_CONT_n_38,ITER_CONT_n_39,ITER_CONT_n_40,ITER_CONT_n_41,ITER_CONT_n_42,ITER_CONT_n_43,ITER_CONT_n_44,ITER_CONT_n_45,ITER_CONT_n_46,ITER_CONT_n_47,ITER_CONT_n_48,ITER_CONT_n_49,ITER_CONT_n_50,ITER_CONT_n_51,ITER_CONT_n_52,ITER_CONT_n_53,ITER_CONT_n_54,ITER_CONT_n_55,ITER_CONT_n_56,ITER_CONT_n_57,ITER_CONT_n_58,ITER_CONT_n_59,ITER_CONT_n_60,ITER_CONT_n_61,ITER_CONT_n_62,ITER_CONT_n_63,ITER_CONT_n_64,ITER_CONT_n_65,ITER_CONT_n_66,ITER_CONT_n_67,ITER_CONT_n_68}),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_val_muxX_2stage_n_4,A,reg_val_muxX_2stage_n_13,reg_val_muxX_2stage_n_14,reg_val_muxX_2stage_n_15,reg_val_muxX_2stage_n_16,reg_val_muxX_2stage_n_17,reg_val_muxX_2stage_n_18,reg_val_muxX_2stage_n_19,reg_val_muxX_2stage_n_20,reg_val_muxX_2stage_n_21,reg_val_muxX_2stage_n_22,reg_val_muxX_2stage_n_23,reg_val_muxX_2stage_n_24,reg_val_muxX_2stage_n_25,reg_val_muxX_2stage_n_26,reg_val_muxX_2stage_n_27,reg_val_muxX_2stage_n_28,reg_val_muxX_2stage_n_29,reg_val_muxX_2stage_n_30,reg_val_muxX_2stage_n_31,reg_val_muxX_2stage_n_32,reg_val_muxX_2stage_n_33,reg_val_muxX_2stage_n_34,reg_val_muxX_2stage_n_35}),
.\Q_reg[26]_0 ({reg_val_muxX_2stage_n_36,reg_val_muxX_2stage_n_37,reg_val_muxX_2stage_n_38,reg_val_muxX_2stage_n_39}),
.S({reg_val_muxX_2stage_n_0,reg_val_muxX_2stage_n_1,reg_val_muxX_2stage_n_2,reg_val_muxX_2stage_n_3}),
.\temp_reg[3] (cont_iter_out));
d_ff_en__parameterized3 reg_val_muxY_2stage
(.CLK(clk_IBUF_BUFG),
.D({reg_val_muxY_2stage_n_32,reg_val_muxY_2stage_n_33,reg_val_muxY_2stage_n_34,reg_val_muxY_2stage_n_35,reg_val_muxY_2stage_n_36,reg_val_muxY_2stage_n_37,reg_val_muxY_2stage_n_38,reg_val_muxY_2stage_n_39}),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({d_ff2_Y,reg_val_muxY_2stage_n_1,reg_val_muxY_2stage_n_2,reg_val_muxY_2stage_n_3,reg_val_muxY_2stage_n_4,reg_val_muxY_2stage_n_5,reg_val_muxY_2stage_n_6,reg_val_muxY_2stage_n_7,reg_val_muxY_2stage_n_8,reg_val_muxY_2stage_n_9,reg_val_muxY_2stage_n_10,reg_val_muxY_2stage_n_11,reg_val_muxY_2stage_n_12,reg_val_muxY_2stage_n_13,reg_val_muxY_2stage_n_14,reg_val_muxY_2stage_n_15,reg_val_muxY_2stage_n_16,reg_val_muxY_2stage_n_17,reg_val_muxY_2stage_n_18,reg_val_muxY_2stage_n_19,reg_val_muxY_2stage_n_20,reg_val_muxY_2stage_n_21,reg_val_muxY_2stage_n_22,reg_val_muxY_2stage_n_23,reg_val_muxY_2stage_n_24,reg_val_muxY_2stage_n_25,reg_val_muxY_2stage_n_26,reg_val_muxY_2stage_n_27,reg_val_muxY_2stage_n_28,reg_val_muxY_2stage_n_29,reg_val_muxY_2stage_n_30,reg_val_muxY_2stage_n_31}),
.\temp_reg[3] (cont_iter_out),
.\temp_reg[3]_0 ({ITER_CONT_n_69,ITER_CONT_n_70,ITER_CONT_n_71,ITER_CONT_n_72,ITER_CONT_n_73,ITER_CONT_n_74,ITER_CONT_n_75,ITER_CONT_n_76,ITER_CONT_n_77,ITER_CONT_n_78,ITER_CONT_n_79,ITER_CONT_n_80,ITER_CONT_n_81,ITER_CONT_n_82,ITER_CONT_n_83,ITER_CONT_n_84,ITER_CONT_n_85,ITER_CONT_n_86,ITER_CONT_n_87,ITER_CONT_n_88,ITER_CONT_n_89,ITER_CONT_n_90,ITER_CONT_n_91,ITER_CONT_n_92,ITER_CONT_n_93,ITER_CONT_n_94,ITER_CONT_n_95,ITER_CONT_n_96,ITER_CONT_n_97,ITER_CONT_n_98,ITER_CONT_n_99,ITER_CONT_n_100}));
d_ff_en__parameterized4 reg_val_muxZ_2stage
(.CLK(clk_IBUF_BUFG),
.D({ITER_CONT_n_5,ITER_CONT_n_6,ITER_CONT_n_7,ITER_CONT_n_8,ITER_CONT_n_9,ITER_CONT_n_10,ITER_CONT_n_11,ITER_CONT_n_12,ITER_CONT_n_13,ITER_CONT_n_14,ITER_CONT_n_15,ITER_CONT_n_16,ITER_CONT_n_17,ITER_CONT_n_18,ITER_CONT_n_19,ITER_CONT_n_20,ITER_CONT_n_21,ITER_CONT_n_22,ITER_CONT_n_23,ITER_CONT_n_24,ITER_CONT_n_25,ITER_CONT_n_26,ITER_CONT_n_27,ITER_CONT_n_28,ITER_CONT_n_29,ITER_CONT_n_30,ITER_CONT_n_31,ITER_CONT_n_32,ITER_CONT_n_33,ITER_CONT_n_34,ITER_CONT_n_35,ITER_CONT_n_36}),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({d_ff2_Z,reg_val_muxZ_2stage_n_1,reg_val_muxZ_2stage_n_2,reg_val_muxZ_2stage_n_3,reg_val_muxZ_2stage_n_4,reg_val_muxZ_2stage_n_5,reg_val_muxZ_2stage_n_6,reg_val_muxZ_2stage_n_7,reg_val_muxZ_2stage_n_8,reg_val_muxZ_2stage_n_9,reg_val_muxZ_2stage_n_10,reg_val_muxZ_2stage_n_11,reg_val_muxZ_2stage_n_12,reg_val_muxZ_2stage_n_13,reg_val_muxZ_2stage_n_14,reg_val_muxZ_2stage_n_15,reg_val_muxZ_2stage_n_16,reg_val_muxZ_2stage_n_17,reg_val_muxZ_2stage_n_18,reg_val_muxZ_2stage_n_19,reg_val_muxZ_2stage_n_20,reg_val_muxZ_2stage_n_21,reg_val_muxZ_2stage_n_22,reg_val_muxZ_2stage_n_23,reg_val_muxZ_2stage_n_24,reg_val_muxZ_2stage_n_25,reg_val_muxZ_2stage_n_26,reg_val_muxZ_2stage_n_27,reg_val_muxZ_2stage_n_28,reg_val_muxZ_2stage_n_29,reg_val_muxZ_2stage_n_30,reg_val_muxZ_2stage_n_31}));
IBUF rst_IBUF_inst
(.I(rst),
.O(rst_IBUF));
IBUF \shift_region_flag_IBUF[0]_inst
(.I(shift_region_flag[0]),
.O(shift_region_flag_IBUF[0]));
IBUF \shift_region_flag_IBUF[1]_inst
(.I(shift_region_flag[1]),
.O(shift_region_flag_IBUF[1]));
Simple_Subt shift_x
(.D(Y),
.Q(A[6:0]),
.\Q_reg[26] ({reg_val_muxX_2stage_n_36,reg_val_muxX_2stage_n_37,reg_val_muxX_2stage_n_38,reg_val_muxX_2stage_n_39}),
.S({reg_val_muxX_2stage_n_0,reg_val_muxX_2stage_n_1,reg_val_muxX_2stage_n_2,reg_val_muxX_2stage_n_3}));
OBUF underflow_flag_OBUF_inst
(.I(underflow_flag_OBUF),
.O(underflow_flag));
OBUF zero_flag_OBUF_inst
(.I(zero_flag_OBUF),
.O(zero_flag));
endmodule
module CORDIC_FSM_v3
(AR,
out,
\FSM_sequential_state_reg_reg[0]_0 ,
E,
\Q_reg[31] ,
\Q_reg[31]_0 ,
\Q_reg[0] ,
\Q_reg[1] ,
\temp_reg[0] ,
ready_cordic_OBUF,
\Q_reg[31]_1 ,
rst_IBUF,
\FSM_sequential_state_reg_reg[2]_0 ,
CLK,
max_tick_iter,
\temp_reg[1] ,
ack_cordic_IBUF,
cont_var_out,
beg_fsm_cordic_IBUF);
output [3:0]AR;
output [2:0]out;
output [0:0]\FSM_sequential_state_reg_reg[0]_0 ;
output [0:0]E;
output [0:0]\Q_reg[31] ;
output [0:0]\Q_reg[31]_0 ;
output [0:0]\Q_reg[0] ;
output [0:0]\Q_reg[1] ;
output [0:0]\temp_reg[0] ;
output ready_cordic_OBUF;
output [0:0]\Q_reg[31]_1 ;
input rst_IBUF;
input [0:0]\FSM_sequential_state_reg_reg[2]_0 ;
input CLK;
input max_tick_iter;
input [0:0]\temp_reg[1] ;
input ack_cordic_IBUF;
input [1:0]cont_var_out;
input beg_fsm_cordic_IBUF;
wire [3:0]AR;
wire CLK;
wire [0:0]E;
wire \FSM_sequential_state_reg[0]_i_1_n_0 ;
wire \FSM_sequential_state_reg[0]_i_2_n_0 ;
wire \FSM_sequential_state_reg[1]_i_1_n_0 ;
wire \FSM_sequential_state_reg[2]_i_1_n_0 ;
wire [0:0]\FSM_sequential_state_reg_reg[0]_0 ;
wire [0:0]\FSM_sequential_state_reg_reg[2]_0 ;
wire [0:0]\Q_reg[0] ;
wire [0:0]\Q_reg[1] ;
wire [0:0]\Q_reg[31] ;
wire [0:0]\Q_reg[31]_0 ;
wire [0:0]\Q_reg[31]_1 ;
wire ack_cordic_IBUF;
wire beg_fsm_cordic_IBUF;
wire [1:0]cont_var_out;
wire max_tick_iter;
(* RTL_KEEP = "yes" *) wire [2:0]out;
wire ready_cordic_OBUF;
wire rst_IBUF;
wire [0:0]\temp_reg[0] ;
wire [0:0]\temp_reg[1] ;
LUT6 #(
.INIT(64'h02A2FFFF02A20000))
\FSM_sequential_state_reg[0]_i_1
(.I0(out[2]),
.I1(\temp_reg[1] ),
.I2(out[1]),
.I3(ack_cordic_IBUF),
.I4(out[0]),
.I5(\FSM_sequential_state_reg[0]_i_2_n_0 ),
.O(\FSM_sequential_state_reg[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB888FFFFB888CCCC))
\FSM_sequential_state_reg[0]_i_2
(.I0(max_tick_iter),
.I1(out[1]),
.I2(cont_var_out[1]),
.I3(cont_var_out[0]),
.I4(out[2]),
.I5(beg_fsm_cordic_IBUF),
.O(\FSM_sequential_state_reg[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h7C3C4C3C))
\FSM_sequential_state_reg[1]_i_1
(.I0(ack_cordic_IBUF),
.I1(out[1]),
.I2(out[0]),
.I3(out[2]),
.I4(\temp_reg[1] ),
.O(\FSM_sequential_state_reg[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'h74FFCC00))
\FSM_sequential_state_reg[2]_i_1
(.I0(ack_cordic_IBUF),
.I1(out[0]),
.I2(max_tick_iter),
.I3(out[1]),
.I4(out[2]),
.O(\FSM_sequential_state_reg[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFF08))
\FSM_sequential_state_reg[2]_i_2__0
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(\FSM_sequential_state_reg_reg[0]_0 ));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(rst_IBUF),
.D(\FSM_sequential_state_reg[0]_i_1_n_0 ),
.Q(out[0]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(rst_IBUF),
.D(\FSM_sequential_state_reg[1]_i_1_n_0 ),
.Q(out[1]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[2]
(.C(CLK),
.CE(1'b1),
.CLR(rst_IBUF),
.D(\FSM_sequential_state_reg[2]_i_1_n_0 ),
.Q(out[2]));
LUT4 #(
.INIT(16'hFF08))
\Q[0]_i_1__7
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[2]));
LUT4 #(
.INIT(16'hFF08))
\Q[14]_i_2
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[3]));
LUT3 #(
.INIT(8'h02))
\Q[1]_i_1
(.I0(out[0]),
.I1(out[2]),
.I2(out[1]),
.O(\Q_reg[1] ));
LUT3 #(
.INIT(8'h01))
\Q[1]_i_2
(.I0(out[1]),
.I1(out[0]),
.I2(out[2]),
.O(\Q_reg[31]_1 ));
LUT3 #(
.INIT(8'h40))
\Q[29]_i_1
(.I0(out[2]),
.I1(out[0]),
.I2(out[1]),
.O(\Q_reg[0] ));
LUT4 #(
.INIT(16'hA800))
\Q[31]_i_1
(.I0(out[2]),
.I1(out[0]),
.I2(max_tick_iter),
.I3(out[1]),
.O(\Q_reg[31]_0 ));
LUT3 #(
.INIT(8'h02))
\Q[31]_i_1__7
(.I0(out[1]),
.I1(out[0]),
.I2(out[2]),
.O(E));
LUT3 #(
.INIT(8'h04))
\Q[31]_i_1__8
(.I0(out[1]),
.I1(out[2]),
.I2(\FSM_sequential_state_reg_reg[2]_0 ),
.O(\Q_reg[31] ));
LUT4 #(
.INIT(16'hFF08))
\Q[31]_i_2
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[1]));
LUT4 #(
.INIT(16'hFF08))
\Q[6]_i_2
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[0]));
LUT3 #(
.INIT(8'h80))
ready_cordic_OBUF_inst_i_1
(.I0(out[1]),
.I1(out[0]),
.I2(out[2]),
.O(ready_cordic_OBUF));
LUT3 #(
.INIT(8'h40))
\temp[3]_i_1
(.I0(out[0]),
.I1(out[2]),
.I2(out[1]),
.O(\temp_reg[0] ));
endmodule
module Comparator
(CO,
\Q_reg[2] ,
\Q_reg[6] ,
S,
\Q_reg[14] ,
\Q_reg[14]_0 ,
\Q_reg[22] ,
\Q_reg[22]_0 ,
DI,
\Q_reg[30] ,
\Q_reg[9] ,
\Q_reg[21] ,
\Q_reg[30]_0 );
output [0:0]CO;
output [0:0]\Q_reg[2] ;
input [3:0]\Q_reg[6] ;
input [3:0]S;
input [3:0]\Q_reg[14] ;
input [3:0]\Q_reg[14]_0 ;
input [3:0]\Q_reg[22] ;
input [3:0]\Q_reg[22]_0 ;
input [3:0]DI;
input [3:0]\Q_reg[30] ;
input [3:0]\Q_reg[9] ;
input [3:0]\Q_reg[21] ;
input [2:0]\Q_reg[30]_0 ;
wire [0:0]CO;
wire [3:0]DI;
wire [3:0]\Q_reg[14] ;
wire [3:0]\Q_reg[14]_0 ;
wire [3:0]\Q_reg[21] ;
wire [3:0]\Q_reg[22] ;
wire [3:0]\Q_reg[22]_0 ;
wire [0:0]\Q_reg[2] ;
wire [3:0]\Q_reg[30] ;
wire [2:0]\Q_reg[30]_0 ;
wire [3:0]\Q_reg[6] ;
wire [3:0]\Q_reg[9] ;
wire [3:0]S;
wire eqXY_o_carry__0_n_0;
wire eqXY_o_carry__0_n_1;
wire eqXY_o_carry__0_n_2;
wire eqXY_o_carry__0_n_3;
wire eqXY_o_carry__1_n_2;
wire eqXY_o_carry__1_n_3;
wire eqXY_o_carry_n_0;
wire eqXY_o_carry_n_1;
wire eqXY_o_carry_n_2;
wire eqXY_o_carry_n_3;
wire gtXY_o_carry__0_n_0;
wire gtXY_o_carry__0_n_1;
wire gtXY_o_carry__0_n_2;
wire gtXY_o_carry__0_n_3;
wire gtXY_o_carry__1_n_0;
wire gtXY_o_carry__1_n_1;
wire gtXY_o_carry__1_n_2;
wire gtXY_o_carry__1_n_3;
wire gtXY_o_carry__2_n_1;
wire gtXY_o_carry__2_n_2;
wire gtXY_o_carry__2_n_3;
wire gtXY_o_carry_n_0;
wire gtXY_o_carry_n_1;
wire gtXY_o_carry_n_2;
wire gtXY_o_carry_n_3;
wire [3:0]NLW_eqXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__0_O_UNCONNECTED;
wire [3:3]NLW_eqXY_o_carry__1_CO_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__0_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__2_O_UNCONNECTED;
CARRY4 eqXY_o_carry
(.CI(1'b0),
.CO({eqXY_o_carry_n_0,eqXY_o_carry_n_1,eqXY_o_carry_n_2,eqXY_o_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry_O_UNCONNECTED[3:0]),
.S(\Q_reg[9] ));
CARRY4 eqXY_o_carry__0
(.CI(eqXY_o_carry_n_0),
.CO({eqXY_o_carry__0_n_0,eqXY_o_carry__0_n_1,eqXY_o_carry__0_n_2,eqXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[21] ));
CARRY4 eqXY_o_carry__1
(.CI(eqXY_o_carry__0_n_0),
.CO({NLW_eqXY_o_carry__1_CO_UNCONNECTED[3],\Q_reg[2] ,eqXY_o_carry__1_n_2,eqXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__1_O_UNCONNECTED[3:0]),
.S({1'b0,\Q_reg[30]_0 }));
CARRY4 gtXY_o_carry
(.CI(1'b0),
.CO({gtXY_o_carry_n_0,gtXY_o_carry_n_1,gtXY_o_carry_n_2,gtXY_o_carry_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[6] ),
.O(NLW_gtXY_o_carry_O_UNCONNECTED[3:0]),
.S(S));
CARRY4 gtXY_o_carry__0
(.CI(gtXY_o_carry_n_0),
.CO({gtXY_o_carry__0_n_0,gtXY_o_carry__0_n_1,gtXY_o_carry__0_n_2,gtXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[14] ),
.O(NLW_gtXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[14]_0 ));
CARRY4 gtXY_o_carry__1
(.CI(gtXY_o_carry__0_n_0),
.CO({gtXY_o_carry__1_n_0,gtXY_o_carry__1_n_1,gtXY_o_carry__1_n_2,gtXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[22] ),
.O(NLW_gtXY_o_carry__1_O_UNCONNECTED[3:0]),
.S(\Q_reg[22]_0 ));
CARRY4 gtXY_o_carry__2
(.CI(gtXY_o_carry__1_n_0),
.CO({CO,gtXY_o_carry__2_n_1,gtXY_o_carry__2_n_2,gtXY_o_carry__2_n_3}),
.CYINIT(1'b0),
.DI(DI),
.O(NLW_gtXY_o_carry__2_O_UNCONNECTED[3:0]),
.S(\Q_reg[30] ));
endmodule
module FPU_PIPELINED_FPADDSUB
(ready_add_subt,
Q,
\Q_reg[31] ,
overflow_flag,
out,
CLK,
AR,
E,
op_add_subt,
\FSM_sequential_state_reg_reg[1] ,
D,
\Q_reg[31]_0 ,
\FSM_sequential_state_reg_reg[2] );
output ready_add_subt;
output [0:0]Q;
output [31:0]\Q_reg[31] ;
output [2:0]overflow_flag;
output [0:0]out;
input CLK;
input [3:0]AR;
input [0:0]E;
input op_add_subt;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [31:0]D;
input [31:0]\Q_reg[31]_0 ;
input [1:0]\FSM_sequential_state_reg_reg[2] ;
wire ADD_OVRFLW_NRM;
wire ADD_OVRFLW_NRM2;
wire [3:0]AR;
wire CLK;
wire [31:0]D;
wire [24:2]DMP_mant_SFG_SWR;
wire [25:0]\Data_array_SWR[2]_1 ;
wire [25:18]\Data_array_SWR[3]_0 ;
wire [15:14]\Data_array_SWR[4]_5 ;
wire [17:2]\Data_array_SWR[5]_3 ;
wire [25:1]\Data_array_SWR[6]_4 ;
wire [0:0]E;
wire EXP_STAGE_DMP_n_1;
wire EXP_STAGE_DMP_n_10;
wire EXP_STAGE_DMP_n_11;
wire EXP_STAGE_DMP_n_12;
wire EXP_STAGE_DMP_n_13;
wire EXP_STAGE_DMP_n_14;
wire EXP_STAGE_DMP_n_15;
wire EXP_STAGE_DMP_n_16;
wire EXP_STAGE_DMP_n_17;
wire EXP_STAGE_DMP_n_18;
wire EXP_STAGE_DMP_n_19;
wire EXP_STAGE_DMP_n_2;
wire EXP_STAGE_DMP_n_20;
wire EXP_STAGE_DMP_n_21;
wire EXP_STAGE_DMP_n_22;
wire EXP_STAGE_DMP_n_23;
wire EXP_STAGE_DMP_n_24;
wire EXP_STAGE_DMP_n_25;
wire EXP_STAGE_DMP_n_26;
wire EXP_STAGE_DMP_n_27;
wire EXP_STAGE_DMP_n_28;
wire EXP_STAGE_DMP_n_29;
wire EXP_STAGE_DMP_n_3;
wire EXP_STAGE_DMP_n_30;
wire EXP_STAGE_DMP_n_31;
wire EXP_STAGE_DMP_n_32;
wire EXP_STAGE_DMP_n_4;
wire EXP_STAGE_DmP_n_10;
wire EXP_STAGE_DmP_n_11;
wire EXP_STAGE_DmP_n_12;
wire EXP_STAGE_DmP_n_13;
wire EXP_STAGE_DmP_n_14;
wire EXP_STAGE_DmP_n_15;
wire EXP_STAGE_DmP_n_16;
wire EXP_STAGE_DmP_n_17;
wire EXP_STAGE_DmP_n_18;
wire EXP_STAGE_DmP_n_19;
wire EXP_STAGE_DmP_n_20;
wire EXP_STAGE_DmP_n_21;
wire EXP_STAGE_DmP_n_22;
wire EXP_STAGE_DmP_n_23;
wire EXP_STAGE_DmP_n_24;
wire EXP_STAGE_DmP_n_25;
wire EXP_STAGE_DmP_n_26;
wire EXP_STAGE_DmP_n_27;
wire EXP_STAGE_DmP_n_28;
wire EXP_STAGE_DmP_n_3;
wire EXP_STAGE_DmP_n_4;
wire EXP_STAGE_DmP_n_5;
wire EXP_STAGE_DmP_n_6;
wire EXP_STAGE_DmP_n_7;
wire EXP_STAGE_DmP_n_8;
wire EXP_STAGE_DmP_n_9;
wire EXP_STAGE_FLAGS_n_0;
wire EXP_STAGE_FLAGS_n_1;
wire EXP_STAGE_FLAGS_n_2;
wire FSM_enable_input_internal;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [1:0]\FSM_sequential_state_reg_reg[2] ;
wire INPUT_STAGE_FLAGS_n_1;
wire INPUT_STAGE_OPERANDX_n_0;
wire INPUT_STAGE_OPERANDX_n_1;
wire INPUT_STAGE_OPERANDX_n_10;
wire INPUT_STAGE_OPERANDX_n_11;
wire INPUT_STAGE_OPERANDX_n_12;
wire INPUT_STAGE_OPERANDX_n_13;
wire INPUT_STAGE_OPERANDX_n_14;
wire INPUT_STAGE_OPERANDX_n_15;
wire INPUT_STAGE_OPERANDX_n_16;
wire INPUT_STAGE_OPERANDX_n_17;
wire INPUT_STAGE_OPERANDX_n_18;
wire INPUT_STAGE_OPERANDX_n_19;
wire INPUT_STAGE_OPERANDX_n_2;
wire INPUT_STAGE_OPERANDX_n_20;
wire INPUT_STAGE_OPERANDX_n_21;
wire INPUT_STAGE_OPERANDX_n_22;
wire INPUT_STAGE_OPERANDX_n_23;
wire INPUT_STAGE_OPERANDX_n_24;
wire INPUT_STAGE_OPERANDX_n_25;
wire INPUT_STAGE_OPERANDX_n_26;
wire INPUT_STAGE_OPERANDX_n_27;
wire INPUT_STAGE_OPERANDX_n_28;
wire INPUT_STAGE_OPERANDX_n_29;
wire INPUT_STAGE_OPERANDX_n_3;
wire INPUT_STAGE_OPERANDX_n_30;
wire INPUT_STAGE_OPERANDX_n_31;
wire INPUT_STAGE_OPERANDX_n_32;
wire INPUT_STAGE_OPERANDX_n_33;
wire INPUT_STAGE_OPERANDX_n_34;
wire INPUT_STAGE_OPERANDX_n_35;
wire INPUT_STAGE_OPERANDX_n_36;
wire INPUT_STAGE_OPERANDX_n_37;
wire INPUT_STAGE_OPERANDX_n_38;
wire INPUT_STAGE_OPERANDX_n_39;
wire INPUT_STAGE_OPERANDX_n_40;
wire INPUT_STAGE_OPERANDX_n_41;
wire INPUT_STAGE_OPERANDX_n_42;
wire INPUT_STAGE_OPERANDX_n_43;
wire INPUT_STAGE_OPERANDX_n_44;
wire INPUT_STAGE_OPERANDX_n_45;
wire INPUT_STAGE_OPERANDX_n_46;
wire INPUT_STAGE_OPERANDX_n_47;
wire INPUT_STAGE_OPERANDX_n_48;
wire INPUT_STAGE_OPERANDX_n_49;
wire INPUT_STAGE_OPERANDX_n_5;
wire INPUT_STAGE_OPERANDX_n_50;
wire INPUT_STAGE_OPERANDX_n_51;
wire INPUT_STAGE_OPERANDX_n_52;
wire INPUT_STAGE_OPERANDX_n_53;
wire INPUT_STAGE_OPERANDX_n_54;
wire INPUT_STAGE_OPERANDX_n_55;
wire INPUT_STAGE_OPERANDX_n_56;
wire INPUT_STAGE_OPERANDX_n_57;
wire INPUT_STAGE_OPERANDX_n_58;
wire INPUT_STAGE_OPERANDX_n_59;
wire INPUT_STAGE_OPERANDX_n_6;
wire INPUT_STAGE_OPERANDX_n_60;
wire INPUT_STAGE_OPERANDX_n_61;
wire INPUT_STAGE_OPERANDX_n_62;
wire INPUT_STAGE_OPERANDX_n_63;
wire INPUT_STAGE_OPERANDX_n_64;
wire INPUT_STAGE_OPERANDX_n_65;
wire INPUT_STAGE_OPERANDX_n_66;
wire INPUT_STAGE_OPERANDX_n_67;
wire INPUT_STAGE_OPERANDX_n_68;
wire INPUT_STAGE_OPERANDX_n_69;
wire INPUT_STAGE_OPERANDX_n_7;
wire INPUT_STAGE_OPERANDX_n_70;
wire INPUT_STAGE_OPERANDX_n_71;
wire INPUT_STAGE_OPERANDX_n_72;
wire INPUT_STAGE_OPERANDX_n_8;
wire INPUT_STAGE_OPERANDX_n_9;
wire INPUT_STAGE_OPERANDY_n_0;
wire INPUT_STAGE_OPERANDY_n_10;
wire INPUT_STAGE_OPERANDY_n_11;
wire INPUT_STAGE_OPERANDY_n_12;
wire INPUT_STAGE_OPERANDY_n_13;
wire INPUT_STAGE_OPERANDY_n_14;
wire INPUT_STAGE_OPERANDY_n_15;
wire INPUT_STAGE_OPERANDY_n_16;
wire INPUT_STAGE_OPERANDY_n_17;
wire INPUT_STAGE_OPERANDY_n_18;
wire INPUT_STAGE_OPERANDY_n_19;
wire INPUT_STAGE_OPERANDY_n_2;
wire INPUT_STAGE_OPERANDY_n_20;
wire INPUT_STAGE_OPERANDY_n_21;
wire INPUT_STAGE_OPERANDY_n_22;
wire INPUT_STAGE_OPERANDY_n_23;
wire INPUT_STAGE_OPERANDY_n_24;
wire INPUT_STAGE_OPERANDY_n_25;
wire INPUT_STAGE_OPERANDY_n_26;
wire INPUT_STAGE_OPERANDY_n_27;
wire INPUT_STAGE_OPERANDY_n_28;
wire INPUT_STAGE_OPERANDY_n_29;
wire INPUT_STAGE_OPERANDY_n_3;
wire INPUT_STAGE_OPERANDY_n_30;
wire INPUT_STAGE_OPERANDY_n_31;
wire INPUT_STAGE_OPERANDY_n_32;
wire INPUT_STAGE_OPERANDY_n_33;
wire INPUT_STAGE_OPERANDY_n_4;
wire INPUT_STAGE_OPERANDY_n_5;
wire INPUT_STAGE_OPERANDY_n_6;
wire INPUT_STAGE_OPERANDY_n_7;
wire INPUT_STAGE_OPERANDY_n_8;
wire INPUT_STAGE_OPERANDY_n_9;
wire [4:0]LZD_raw_out_EWR;
wire MuxXY_n_0;
wire MuxXY_n_1;
wire MuxXY_n_10;
wire MuxXY_n_11;
wire MuxXY_n_12;
wire MuxXY_n_13;
wire MuxXY_n_14;
wire MuxXY_n_15;
wire MuxXY_n_16;
wire MuxXY_n_17;
wire MuxXY_n_18;
wire MuxXY_n_19;
wire MuxXY_n_2;
wire MuxXY_n_20;
wire MuxXY_n_21;
wire MuxXY_n_22;
wire MuxXY_n_23;
wire MuxXY_n_24;
wire MuxXY_n_25;
wire MuxXY_n_26;
wire MuxXY_n_27;
wire MuxXY_n_28;
wire MuxXY_n_29;
wire MuxXY_n_3;
wire MuxXY_n_30;
wire MuxXY_n_31;
wire MuxXY_n_32;
wire MuxXY_n_33;
wire MuxXY_n_34;
wire MuxXY_n_35;
wire MuxXY_n_36;
wire MuxXY_n_37;
wire MuxXY_n_38;
wire MuxXY_n_39;
wire MuxXY_n_4;
wire MuxXY_n_40;
wire MuxXY_n_41;
wire MuxXY_n_42;
wire MuxXY_n_43;
wire MuxXY_n_44;
wire MuxXY_n_45;
wire MuxXY_n_46;
wire MuxXY_n_47;
wire MuxXY_n_48;
wire MuxXY_n_49;
wire MuxXY_n_5;
wire MuxXY_n_50;
wire MuxXY_n_51;
wire MuxXY_n_52;
wire MuxXY_n_53;
wire MuxXY_n_54;
wire MuxXY_n_55;
wire MuxXY_n_56;
wire MuxXY_n_57;
wire MuxXY_n_58;
wire MuxXY_n_6;
wire MuxXY_n_7;
wire MuxXY_n_8;
wire MuxXY_n_9;
wire NRM_STAGE_DMP_exp_n_0;
wire NRM_STAGE_DMP_exp_n_1;
wire NRM_STAGE_DMP_exp_n_2;
wire NRM_STAGE_DMP_exp_n_3;
wire NRM_STAGE_DMP_exp_n_4;
wire NRM_STAGE_DMP_exp_n_5;
wire NRM_STAGE_DMP_exp_n_6;
wire NRM_STAGE_DMP_exp_n_7;
wire NRM_STAGE_FLAGS_n_2;
wire NRM_STAGE_FLAGS_n_3;
wire NRM_STAGE_FLAGS_n_4;
wire NRM_STAGE_Raw_mant_n_30;
wire OP_FLAG_INIT;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire \Q[12]_i_10_n_0 ;
wire \Q[12]_i_11_n_0 ;
wire \Q[12]_i_8_n_0 ;
wire \Q[12]_i_9_n_0 ;
wire \Q[16]_i_10_n_0 ;
wire \Q[16]_i_11_n_0 ;
wire \Q[16]_i_8_n_0 ;
wire \Q[16]_i_9_n_0 ;
wire \Q[20]_i_10_n_0 ;
wire \Q[20]_i_11_n_0 ;
wire \Q[20]_i_8_n_0 ;
wire \Q[20]_i_9_n_0 ;
wire \Q[24]_i_10_n_0 ;
wire \Q[24]_i_11_n_0 ;
wire \Q[24]_i_8_n_0 ;
wire \Q[24]_i_9_n_0 ;
wire \Q[4]_i_10_n_0 ;
wire \Q[4]_i_11_n_0 ;
wire \Q[4]_i_9_n_0 ;
wire \Q[8]_i_10_n_0 ;
wire \Q[8]_i_11_n_0 ;
wire \Q[8]_i_8__0_n_0 ;
wire \Q[8]_i_9__0_n_0 ;
wire [31:0]\Q_reg[31] ;
wire [31:0]\Q_reg[31]_0 ;
wire [25:0]Raw_mant_SGF;
wire SFT2FRMT_STAGE_FLAGS_n_1;
wire SFT2FRMT_STAGE_FLAGS_n_3;
wire SFT2FRMT_STAGE_VARS_n_0;
wire SFT2FRMT_STAGE_VARS_n_1;
wire SFT2FRMT_STAGE_VARS_n_10;
wire SFT2FRMT_STAGE_VARS_n_11;
wire SFT2FRMT_STAGE_VARS_n_12;
wire SFT2FRMT_STAGE_VARS_n_13;
wire SFT2FRMT_STAGE_VARS_n_14;
wire SFT2FRMT_STAGE_VARS_n_15;
wire SFT2FRMT_STAGE_VARS_n_16;
wire SFT2FRMT_STAGE_VARS_n_17;
wire SFT2FRMT_STAGE_VARS_n_18;
wire SFT2FRMT_STAGE_VARS_n_19;
wire SFT2FRMT_STAGE_VARS_n_2;
wire SFT2FRMT_STAGE_VARS_n_20;
wire SFT2FRMT_STAGE_VARS_n_21;
wire SFT2FRMT_STAGE_VARS_n_22;
wire SFT2FRMT_STAGE_VARS_n_23;
wire SFT2FRMT_STAGE_VARS_n_3;
wire SFT2FRMT_STAGE_VARS_n_4;
wire SFT2FRMT_STAGE_VARS_n_5;
wire SFT2FRMT_STAGE_VARS_n_6;
wire SFT2FRMT_STAGE_VARS_n_7;
wire SFT2FRMT_STAGE_VARS_n_8;
wire SFT2FRMT_STAGE_VARS_n_9;
wire SGF_STAGE_DMP_n_0;
wire SGF_STAGE_DMP_n_1;
wire SGF_STAGE_DMP_n_10;
wire SGF_STAGE_DMP_n_11;
wire SGF_STAGE_DMP_n_2;
wire SGF_STAGE_DMP_n_3;
wire SGF_STAGE_DMP_n_35;
wire SGF_STAGE_DMP_n_36;
wire SGF_STAGE_DMP_n_37;
wire SGF_STAGE_DMP_n_38;
wire SGF_STAGE_DMP_n_39;
wire SGF_STAGE_DMP_n_4;
wire SGF_STAGE_DMP_n_40;
wire SGF_STAGE_DMP_n_41;
wire SGF_STAGE_DMP_n_42;
wire SGF_STAGE_DMP_n_43;
wire SGF_STAGE_DMP_n_44;
wire SGF_STAGE_DMP_n_45;
wire SGF_STAGE_DMP_n_46;
wire SGF_STAGE_DMP_n_47;
wire SGF_STAGE_DMP_n_48;
wire SGF_STAGE_DMP_n_49;
wire SGF_STAGE_DMP_n_5;
wire SGF_STAGE_DMP_n_50;
wire SGF_STAGE_DMP_n_51;
wire SGF_STAGE_DMP_n_52;
wire SGF_STAGE_DMP_n_53;
wire SGF_STAGE_DMP_n_54;
wire SGF_STAGE_DMP_n_55;
wire SGF_STAGE_DMP_n_6;
wire SGF_STAGE_DMP_n_7;
wire SGF_STAGE_DMP_n_8;
wire SGF_STAGE_DMP_n_9;
wire SGF_STAGE_DmP_mant_n_0;
wire SGF_STAGE_DmP_mant_n_1;
wire SGF_STAGE_DmP_mant_n_10;
wire SGF_STAGE_DmP_mant_n_11;
wire SGF_STAGE_DmP_mant_n_12;
wire SGF_STAGE_DmP_mant_n_13;
wire SGF_STAGE_DmP_mant_n_14;
wire SGF_STAGE_DmP_mant_n_15;
wire SGF_STAGE_DmP_mant_n_16;
wire SGF_STAGE_DmP_mant_n_17;
wire SGF_STAGE_DmP_mant_n_18;
wire SGF_STAGE_DmP_mant_n_19;
wire SGF_STAGE_DmP_mant_n_2;
wire SGF_STAGE_DmP_mant_n_20;
wire SGF_STAGE_DmP_mant_n_21;
wire SGF_STAGE_DmP_mant_n_22;
wire SGF_STAGE_DmP_mant_n_24;
wire SGF_STAGE_DmP_mant_n_25;
wire SGF_STAGE_DmP_mant_n_26;
wire SGF_STAGE_DmP_mant_n_27;
wire SGF_STAGE_DmP_mant_n_28;
wire SGF_STAGE_DmP_mant_n_29;
wire SGF_STAGE_DmP_mant_n_3;
wire SGF_STAGE_DmP_mant_n_30;
wire SGF_STAGE_DmP_mant_n_31;
wire SGF_STAGE_DmP_mant_n_32;
wire SGF_STAGE_DmP_mant_n_33;
wire SGF_STAGE_DmP_mant_n_34;
wire SGF_STAGE_DmP_mant_n_35;
wire SGF_STAGE_DmP_mant_n_36;
wire SGF_STAGE_DmP_mant_n_37;
wire SGF_STAGE_DmP_mant_n_38;
wire SGF_STAGE_DmP_mant_n_39;
wire SGF_STAGE_DmP_mant_n_4;
wire SGF_STAGE_DmP_mant_n_40;
wire SGF_STAGE_DmP_mant_n_41;
wire SGF_STAGE_DmP_mant_n_42;
wire SGF_STAGE_DmP_mant_n_43;
wire SGF_STAGE_DmP_mant_n_44;
wire SGF_STAGE_DmP_mant_n_45;
wire SGF_STAGE_DmP_mant_n_46;
wire SGF_STAGE_DmP_mant_n_47;
wire SGF_STAGE_DmP_mant_n_48;
wire SGF_STAGE_DmP_mant_n_49;
wire SGF_STAGE_DmP_mant_n_5;
wire SGF_STAGE_DmP_mant_n_51;
wire SGF_STAGE_DmP_mant_n_6;
wire SGF_STAGE_DmP_mant_n_7;
wire SGF_STAGE_DmP_mant_n_8;
wire SGF_STAGE_DmP_mant_n_9;
wire SGF_STAGE_FLAGS_n_0;
wire SHT1_STAGE_DMP_n_0;
wire SHT1_STAGE_DMP_n_1;
wire SHT1_STAGE_DMP_n_10;
wire SHT1_STAGE_DMP_n_11;
wire SHT1_STAGE_DMP_n_12;
wire SHT1_STAGE_DMP_n_13;
wire SHT1_STAGE_DMP_n_14;
wire SHT1_STAGE_DMP_n_15;
wire SHT1_STAGE_DMP_n_16;
wire SHT1_STAGE_DMP_n_17;
wire SHT1_STAGE_DMP_n_18;
wire SHT1_STAGE_DMP_n_19;
wire SHT1_STAGE_DMP_n_2;
wire SHT1_STAGE_DMP_n_20;
wire SHT1_STAGE_DMP_n_21;
wire SHT1_STAGE_DMP_n_22;
wire SHT1_STAGE_DMP_n_23;
wire SHT1_STAGE_DMP_n_24;
wire SHT1_STAGE_DMP_n_25;
wire SHT1_STAGE_DMP_n_26;
wire SHT1_STAGE_DMP_n_27;
wire SHT1_STAGE_DMP_n_28;
wire SHT1_STAGE_DMP_n_29;
wire SHT1_STAGE_DMP_n_3;
wire SHT1_STAGE_DMP_n_30;
wire SHT1_STAGE_DMP_n_4;
wire SHT1_STAGE_DMP_n_5;
wire SHT1_STAGE_DMP_n_6;
wire SHT1_STAGE_DMP_n_7;
wire SHT1_STAGE_DMP_n_8;
wire SHT1_STAGE_DMP_n_9;
wire SHT1_STAGE_DmP_mant_n_0;
wire SHT1_STAGE_DmP_mant_n_1;
wire SHT1_STAGE_DmP_mant_n_10;
wire SHT1_STAGE_DmP_mant_n_11;
wire SHT1_STAGE_DmP_mant_n_12;
wire SHT1_STAGE_DmP_mant_n_13;
wire SHT1_STAGE_DmP_mant_n_14;
wire SHT1_STAGE_DmP_mant_n_15;
wire SHT1_STAGE_DmP_mant_n_16;
wire SHT1_STAGE_DmP_mant_n_17;
wire SHT1_STAGE_DmP_mant_n_18;
wire SHT1_STAGE_DmP_mant_n_19;
wire SHT1_STAGE_DmP_mant_n_2;
wire SHT1_STAGE_DmP_mant_n_20;
wire SHT1_STAGE_DmP_mant_n_21;
wire SHT1_STAGE_DmP_mant_n_22;
wire SHT1_STAGE_DmP_mant_n_3;
wire SHT1_STAGE_DmP_mant_n_4;
wire SHT1_STAGE_DmP_mant_n_5;
wire SHT1_STAGE_DmP_mant_n_6;
wire SHT1_STAGE_DmP_mant_n_7;
wire SHT1_STAGE_DmP_mant_n_8;
wire SHT1_STAGE_DmP_mant_n_9;
wire SHT1_STAGE_FLAGS_n_0;
wire SHT1_STAGE_FLAGS_n_1;
wire SHT1_STAGE_FLAGS_n_2;
wire SHT1_STAGE_sft_amount_n_0;
wire SHT2_SHIFT_DATA_n_0;
wire SHT2_SHIFT_DATA_n_1;
wire SHT2_SHIFT_DATA_n_2;
wire SHT2_STAGE_DMP_n_0;
wire SHT2_STAGE_DMP_n_1;
wire SHT2_STAGE_DMP_n_10;
wire SHT2_STAGE_DMP_n_11;
wire SHT2_STAGE_DMP_n_12;
wire SHT2_STAGE_DMP_n_13;
wire SHT2_STAGE_DMP_n_14;
wire SHT2_STAGE_DMP_n_15;
wire SHT2_STAGE_DMP_n_16;
wire SHT2_STAGE_DMP_n_17;
wire SHT2_STAGE_DMP_n_18;
wire SHT2_STAGE_DMP_n_19;
wire SHT2_STAGE_DMP_n_2;
wire SHT2_STAGE_DMP_n_20;
wire SHT2_STAGE_DMP_n_21;
wire SHT2_STAGE_DMP_n_22;
wire SHT2_STAGE_DMP_n_23;
wire SHT2_STAGE_DMP_n_24;
wire SHT2_STAGE_DMP_n_25;
wire SHT2_STAGE_DMP_n_26;
wire SHT2_STAGE_DMP_n_27;
wire SHT2_STAGE_DMP_n_28;
wire SHT2_STAGE_DMP_n_29;
wire SHT2_STAGE_DMP_n_3;
wire SHT2_STAGE_DMP_n_30;
wire SHT2_STAGE_DMP_n_4;
wire SHT2_STAGE_DMP_n_5;
wire SHT2_STAGE_DMP_n_6;
wire SHT2_STAGE_DMP_n_7;
wire SHT2_STAGE_DMP_n_8;
wire SHT2_STAGE_DMP_n_9;
wire SHT2_STAGE_FLAGS_n_0;
wire SHT2_STAGE_FLAGS_n_1;
wire SHT2_STAGE_FLAGS_n_2;
wire SHT2_STAGE_SHFTVARS1_n_0;
wire SHT2_STAGE_SHFTVARS1_n_1;
wire SHT2_STAGE_SHFTVARS1_n_10;
wire SHT2_STAGE_SHFTVARS1_n_11;
wire SHT2_STAGE_SHFTVARS1_n_12;
wire SHT2_STAGE_SHFTVARS1_n_13;
wire SHT2_STAGE_SHFTVARS1_n_2;
wire SHT2_STAGE_SHFTVARS1_n_3;
wire SHT2_STAGE_SHFTVARS1_n_4;
wire SHT2_STAGE_SHFTVARS1_n_5;
wire SHT2_STAGE_SHFTVARS1_n_6;
wire SHT2_STAGE_SHFTVARS1_n_7;
wire SHT2_STAGE_SHFTVARS1_n_8;
wire SHT2_STAGE_SHFTVARS1_n_9;
wire SHT2_STAGE_SHFTVARS2_n_0;
wire SHT2_STAGE_SHFTVARS2_n_1;
wire SHT2_STAGE_SHFTVARS2_n_2;
wire SHT2_STAGE_SHFTVARS2_n_3;
wire SHT2_STAGE_SHFTVARS2_n_4;
wire SHT2_STAGE_SHFTVARS2_n_5;
wire SIGN_FLAG_INIT;
wire [4:1]Shift_amount_EXP_EW;
wire [2:0]Shift_amount_SHT1_EWR;
wire [1:1]Shift_reg_FLAGS_7;
wire UNDRFLW_FLAG_FRMT;
wire [2:0]ZERO_FLAG_SFG;
wire _inferred__1_carry__0_n_0;
wire _inferred__1_carry__0_n_1;
wire _inferred__1_carry__0_n_2;
wire _inferred__1_carry__0_n_3;
wire _inferred__1_carry_n_0;
wire _inferred__1_carry_n_1;
wire _inferred__1_carry_n_2;
wire _inferred__1_carry_n_3;
wire bit_shift_SHT1;
wire bit_shift_SHT2;
wire enable_shift_reg;
wire eqXY;
wire [8:0]exp_rslt_NRM2_EW1;
wire [31:31]formatted_number_W;
wire gtXY;
wire inst_FSM_INPUT_ENABLE_n_1;
wire inst_FSM_INPUT_ENABLE_n_2;
wire inst_ShiftRegister_n_1;
wire inst_ShiftRegister_n_2;
wire inst_ShiftRegister_n_4;
wire inst_ShiftRegister_n_6;
wire inst_ShiftRegister_n_7;
wire intAS;
wire [31:31]intDX_EWSW;
wire [31:31]intDY_EWSW;
wire left_right_SHT1;
wire left_right_SHT2;
wire load0;
wire op_add_subt;
wire [0:0]out;
wire [2:0]overflow_flag;
wire [4:0]p_1_in;
wire p_1_in_2;
wire ready_add_subt;
wire [25:0]sftr_odat_SHT2_SWR;
wire [4:2]shft_value_mux_o_EWR;
wire [4:2]shift_value_SHT2_EWR;
wire [3:0]NLW__inferred__1_carry__1_CO_UNCONNECTED;
wire [3:1]NLW__inferred__1_carry__1_O_UNCONNECTED;
RegisterAdd__parameterized1 EXP_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.D({Shift_amount_EXP_EW[2],EXP_STAGE_DMP_n_1}),
.Q({EXP_STAGE_DMP_n_2,EXP_STAGE_DMP_n_3,EXP_STAGE_DMP_n_4,p_1_in,EXP_STAGE_DMP_n_10,EXP_STAGE_DMP_n_11,EXP_STAGE_DMP_n_12,EXP_STAGE_DMP_n_13,EXP_STAGE_DMP_n_14,EXP_STAGE_DMP_n_15,EXP_STAGE_DMP_n_16,EXP_STAGE_DMP_n_17,EXP_STAGE_DMP_n_18,EXP_STAGE_DMP_n_19,EXP_STAGE_DMP_n_20,EXP_STAGE_DMP_n_21,EXP_STAGE_DMP_n_22,EXP_STAGE_DMP_n_23,EXP_STAGE_DMP_n_24,EXP_STAGE_DMP_n_25,EXP_STAGE_DMP_n_26,EXP_STAGE_DMP_n_27,EXP_STAGE_DMP_n_28,EXP_STAGE_DMP_n_29,EXP_STAGE_DMP_n_30,EXP_STAGE_DMP_n_31,EXP_STAGE_DMP_n_32}),
.\Q_reg[25]_0 ({EXP_STAGE_DmP_n_3,EXP_STAGE_DmP_n_4,EXP_STAGE_DmP_n_5}),
.\Q_reg[30]_0 ({MuxXY_n_0,MuxXY_n_1,MuxXY_n_2,MuxXY_n_3,MuxXY_n_4,MuxXY_n_5,MuxXY_n_6,MuxXY_n_7,MuxXY_n_8,MuxXY_n_9,MuxXY_n_10,MuxXY_n_11,MuxXY_n_12,MuxXY_n_13,MuxXY_n_14,MuxXY_n_15,MuxXY_n_16,MuxXY_n_17,MuxXY_n_18,MuxXY_n_19,MuxXY_n_20,MuxXY_n_21,MuxXY_n_22,MuxXY_n_23,MuxXY_n_24,MuxXY_n_25,MuxXY_n_26,MuxXY_n_27,MuxXY_n_28,MuxXY_n_29,MuxXY_n_30}),
.\Q_reg[6]_0 (inst_ShiftRegister_n_1));
RegisterAdd__parameterized2 EXP_STAGE_DmP
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({Shift_amount_EXP_EW[4:3],Shift_amount_EXP_EW[1]}),
.Q({EXP_STAGE_DmP_n_3,EXP_STAGE_DmP_n_4,EXP_STAGE_DmP_n_5,EXP_STAGE_DmP_n_6,EXP_STAGE_DmP_n_7,EXP_STAGE_DmP_n_8,EXP_STAGE_DmP_n_9,EXP_STAGE_DmP_n_10,EXP_STAGE_DmP_n_11,EXP_STAGE_DmP_n_12,EXP_STAGE_DmP_n_13,EXP_STAGE_DmP_n_14,EXP_STAGE_DmP_n_15,EXP_STAGE_DmP_n_16,EXP_STAGE_DmP_n_17,EXP_STAGE_DmP_n_18,EXP_STAGE_DmP_n_19,EXP_STAGE_DmP_n_20,EXP_STAGE_DmP_n_21,EXP_STAGE_DmP_n_22,EXP_STAGE_DmP_n_23,EXP_STAGE_DmP_n_24,EXP_STAGE_DmP_n_25,EXP_STAGE_DmP_n_26,EXP_STAGE_DmP_n_27,EXP_STAGE_DmP_n_28}),
.\Q_reg[27]_0 (p_1_in),
.\Q_reg[27]_1 ({MuxXY_n_31,MuxXY_n_32,MuxXY_n_33,MuxXY_n_34,MuxXY_n_35,MuxXY_n_36,MuxXY_n_37,MuxXY_n_38,MuxXY_n_39,MuxXY_n_40,MuxXY_n_41,MuxXY_n_42,MuxXY_n_43,MuxXY_n_44,MuxXY_n_45,MuxXY_n_46,MuxXY_n_47,MuxXY_n_48,MuxXY_n_49,MuxXY_n_50,MuxXY_n_51,MuxXY_n_52,MuxXY_n_53,MuxXY_n_54,MuxXY_n_55,MuxXY_n_56,MuxXY_n_57,MuxXY_n_58}),
.\Q_reg[6]_0 (inst_ShiftRegister_n_1));
RegisterAdd__parameterized3 EXP_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({SIGN_FLAG_INIT,OP_FLAG_INIT,INPUT_STAGE_FLAGS_n_1}),
.Q({EXP_STAGE_FLAGS_n_0,EXP_STAGE_FLAGS_n_1,EXP_STAGE_FLAGS_n_2}),
.\Q_reg[6] (inst_ShiftRegister_n_1));
RegisterAdd FRMT_STAGE_DATAOUT
(.AR({AR[3],AR[1]}),
.CLK(CLK),
.D({formatted_number_W,SFT2FRMT_STAGE_VARS_n_15,SFT2FRMT_STAGE_VARS_n_16,SFT2FRMT_STAGE_VARS_n_17,SFT2FRMT_STAGE_VARS_n_18,SFT2FRMT_STAGE_VARS_n_19,SFT2FRMT_STAGE_VARS_n_20,SFT2FRMT_STAGE_VARS_n_21,SFT2FRMT_STAGE_VARS_n_22,SHT2_SHIFT_DATA_n_0,SHT2_STAGE_SHFTVARS1_n_0,SHT2_STAGE_SHFTVARS1_n_1,SHT2_STAGE_SHFTVARS1_n_2,SHT2_STAGE_SHFTVARS1_n_3,SHT2_STAGE_SHFTVARS1_n_4,SHT2_STAGE_SHFTVARS1_n_5,SHT2_STAGE_SHFTVARS1_n_6,SHT2_STAGE_SHFTVARS1_n_7,SHT2_STAGE_SHFTVARS2_n_0,SHT2_STAGE_SHFTVARS2_n_1,SHT2_SHIFT_DATA_n_1,SHT2_SHIFT_DATA_n_2,SHT2_STAGE_SHFTVARS2_n_2,SHT2_STAGE_SHFTVARS2_n_3,SHT2_STAGE_SHFTVARS2_n_4,SHT2_STAGE_SHFTVARS2_n_5,SHT2_STAGE_SHFTVARS1_n_8,SHT2_STAGE_SHFTVARS1_n_9,SHT2_STAGE_SHFTVARS1_n_10,SHT2_STAGE_SHFTVARS1_n_11,SHT2_STAGE_SHFTVARS1_n_12,SHT2_STAGE_SHFTVARS1_n_13}),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q(inst_ShiftRegister_n_6),
.\Q_reg[31]_0 (\Q_reg[31] ),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT),
.exp_rslt_NRM2_EW1(exp_rslt_NRM2_EW1));
RegisterAdd__parameterized21 FRMT_STAGE_FLAGS
(.AR(AR[2:1]),
.CLK(CLK),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q(inst_ShiftRegister_n_6),
.\Q_reg[0]_0 (SFT2FRMT_STAGE_FLAGS_n_3),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT),
.overflow_flag(overflow_flag));
RegisterAdd__parameterized0 INPUT_STAGE_FLAGS
(.CLK(CLK),
.CO(eqXY),
.D(INPUT_STAGE_FLAGS_n_1),
.E(E),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.Q(intDY_EWSW),
.\Q_reg[31] (intDX_EWSW),
.intAS(intAS),
.op_add_subt(op_add_subt));
RegisterAdd_1 INPUT_STAGE_OPERANDX
(.AR(AR[0]),
.CLK(CLK),
.D(OP_FLAG_INIT),
.DI({INPUT_STAGE_OPERANDX_n_0,INPUT_STAGE_OPERANDX_n_1,INPUT_STAGE_OPERANDX_n_2,INPUT_STAGE_OPERANDX_n_3}),
.E(E),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.Q({intDX_EWSW,INPUT_STAGE_OPERANDX_n_5,INPUT_STAGE_OPERANDX_n_6,INPUT_STAGE_OPERANDX_n_7,INPUT_STAGE_OPERANDX_n_8,INPUT_STAGE_OPERANDX_n_9,INPUT_STAGE_OPERANDX_n_10,INPUT_STAGE_OPERANDX_n_11,INPUT_STAGE_OPERANDX_n_12,INPUT_STAGE_OPERANDX_n_13,INPUT_STAGE_OPERANDX_n_14,INPUT_STAGE_OPERANDX_n_15,INPUT_STAGE_OPERANDX_n_16,INPUT_STAGE_OPERANDX_n_17,INPUT_STAGE_OPERANDX_n_18,INPUT_STAGE_OPERANDX_n_19,INPUT_STAGE_OPERANDX_n_20,INPUT_STAGE_OPERANDX_n_21,INPUT_STAGE_OPERANDX_n_22,INPUT_STAGE_OPERANDX_n_23,INPUT_STAGE_OPERANDX_n_24,INPUT_STAGE_OPERANDX_n_25,INPUT_STAGE_OPERANDX_n_26,INPUT_STAGE_OPERANDX_n_27,INPUT_STAGE_OPERANDX_n_28,INPUT_STAGE_OPERANDX_n_29,INPUT_STAGE_OPERANDX_n_30,INPUT_STAGE_OPERANDX_n_31,INPUT_STAGE_OPERANDX_n_32,INPUT_STAGE_OPERANDX_n_33,INPUT_STAGE_OPERANDX_n_34,INPUT_STAGE_OPERANDX_n_35}),
.\Q_reg[2]_0 ({INPUT_STAGE_OPERANDX_n_36,INPUT_STAGE_OPERANDX_n_37,INPUT_STAGE_OPERANDX_n_38,INPUT_STAGE_OPERANDX_n_39}),
.\Q_reg[2]_1 ({INPUT_STAGE_OPERANDX_n_44,INPUT_STAGE_OPERANDX_n_45,INPUT_STAGE_OPERANDX_n_46,INPUT_STAGE_OPERANDX_n_47}),
.\Q_reg[2]_2 ({INPUT_STAGE_OPERANDX_n_48,INPUT_STAGE_OPERANDX_n_49,INPUT_STAGE_OPERANDX_n_50,INPUT_STAGE_OPERANDX_n_51}),
.\Q_reg[2]_3 ({INPUT_STAGE_OPERANDX_n_52,INPUT_STAGE_OPERANDX_n_53,INPUT_STAGE_OPERANDX_n_54,INPUT_STAGE_OPERANDX_n_55}),
.\Q_reg[2]_4 ({INPUT_STAGE_OPERANDX_n_56,INPUT_STAGE_OPERANDX_n_57,INPUT_STAGE_OPERANDX_n_58,INPUT_STAGE_OPERANDX_n_59}),
.\Q_reg[2]_5 ({INPUT_STAGE_OPERANDX_n_60,INPUT_STAGE_OPERANDX_n_61,INPUT_STAGE_OPERANDX_n_62,INPUT_STAGE_OPERANDX_n_63}),
.\Q_reg[2]_6 ({INPUT_STAGE_OPERANDX_n_64,INPUT_STAGE_OPERANDX_n_65,INPUT_STAGE_OPERANDX_n_66,INPUT_STAGE_OPERANDX_n_67}),
.\Q_reg[2]_7 ({INPUT_STAGE_OPERANDX_n_68,INPUT_STAGE_OPERANDX_n_69,INPUT_STAGE_OPERANDX_n_70}),
.\Q_reg[2]_8 ({INPUT_STAGE_OPERANDX_n_71,INPUT_STAGE_OPERANDX_n_72}),
.\Q_reg[31]_0 ({intDY_EWSW,INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}),
.\Q_reg[31]_1 (\Q_reg[31]_0 ),
.S({INPUT_STAGE_OPERANDX_n_40,INPUT_STAGE_OPERANDX_n_41,INPUT_STAGE_OPERANDX_n_42,INPUT_STAGE_OPERANDX_n_43}),
.intAS(intAS));
RegisterAdd_2 INPUT_STAGE_OPERANDY
(.CLK(CLK),
.D(D),
.E(E),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.Q({intDY_EWSW,INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}),
.\Q_reg[2]_0 (INPUT_STAGE_OPERANDY_n_33),
.\Q_reg[30]_0 (INPUT_STAGE_OPERANDX_n_5),
.S(INPUT_STAGE_OPERANDY_n_0));
Comparator Magnitude_Comparator
(.CO(gtXY),
.DI({INPUT_STAGE_OPERANDX_n_0,INPUT_STAGE_OPERANDX_n_1,INPUT_STAGE_OPERANDX_n_2,INPUT_STAGE_OPERANDX_n_3}),
.\Q_reg[14] ({INPUT_STAGE_OPERANDX_n_44,INPUT_STAGE_OPERANDX_n_45,INPUT_STAGE_OPERANDX_n_46,INPUT_STAGE_OPERANDX_n_47}),
.\Q_reg[14]_0 ({INPUT_STAGE_OPERANDX_n_48,INPUT_STAGE_OPERANDX_n_49,INPUT_STAGE_OPERANDX_n_50,INPUT_STAGE_OPERANDX_n_51}),
.\Q_reg[21] ({INPUT_STAGE_OPERANDX_n_60,INPUT_STAGE_OPERANDX_n_61,INPUT_STAGE_OPERANDX_n_62,INPUT_STAGE_OPERANDX_n_63}),
.\Q_reg[22] ({INPUT_STAGE_OPERANDX_n_56,INPUT_STAGE_OPERANDX_n_57,INPUT_STAGE_OPERANDX_n_58,INPUT_STAGE_OPERANDX_n_59}),
.\Q_reg[22]_0 ({INPUT_STAGE_OPERANDX_n_64,INPUT_STAGE_OPERANDX_n_65,INPUT_STAGE_OPERANDX_n_66,INPUT_STAGE_OPERANDX_n_67}),
.\Q_reg[2] (eqXY),
.\Q_reg[30] ({INPUT_STAGE_OPERANDY_n_33,INPUT_STAGE_OPERANDX_n_68,INPUT_STAGE_OPERANDX_n_69,INPUT_STAGE_OPERANDX_n_70}),
.\Q_reg[30]_0 ({INPUT_STAGE_OPERANDY_n_0,INPUT_STAGE_OPERANDX_n_71,INPUT_STAGE_OPERANDX_n_72}),
.\Q_reg[6] ({INPUT_STAGE_OPERANDX_n_36,INPUT_STAGE_OPERANDX_n_37,INPUT_STAGE_OPERANDX_n_38,INPUT_STAGE_OPERANDX_n_39}),
.\Q_reg[9] ({INPUT_STAGE_OPERANDX_n_52,INPUT_STAGE_OPERANDX_n_53,INPUT_STAGE_OPERANDX_n_54,INPUT_STAGE_OPERANDX_n_55}),
.S({INPUT_STAGE_OPERANDX_n_40,INPUT_STAGE_OPERANDX_n_41,INPUT_STAGE_OPERANDX_n_42,INPUT_STAGE_OPERANDX_n_43}));
MultiplexTxT MuxXY
(.CO(gtXY),
.Q({INPUT_STAGE_OPERANDX_n_5,INPUT_STAGE_OPERANDX_n_6,INPUT_STAGE_OPERANDX_n_7,INPUT_STAGE_OPERANDX_n_8,INPUT_STAGE_OPERANDX_n_9,INPUT_STAGE_OPERANDX_n_10,INPUT_STAGE_OPERANDX_n_11,INPUT_STAGE_OPERANDX_n_12,INPUT_STAGE_OPERANDX_n_13,INPUT_STAGE_OPERANDX_n_14,INPUT_STAGE_OPERANDX_n_15,INPUT_STAGE_OPERANDX_n_16,INPUT_STAGE_OPERANDX_n_17,INPUT_STAGE_OPERANDX_n_18,INPUT_STAGE_OPERANDX_n_19,INPUT_STAGE_OPERANDX_n_20,INPUT_STAGE_OPERANDX_n_21,INPUT_STAGE_OPERANDX_n_22,INPUT_STAGE_OPERANDX_n_23,INPUT_STAGE_OPERANDX_n_24,INPUT_STAGE_OPERANDX_n_25,INPUT_STAGE_OPERANDX_n_26,INPUT_STAGE_OPERANDX_n_27,INPUT_STAGE_OPERANDX_n_28,INPUT_STAGE_OPERANDX_n_29,INPUT_STAGE_OPERANDX_n_30,INPUT_STAGE_OPERANDX_n_31,INPUT_STAGE_OPERANDX_n_32,INPUT_STAGE_OPERANDX_n_33,INPUT_STAGE_OPERANDX_n_34,INPUT_STAGE_OPERANDX_n_35}),
.\Q_reg[27] ({MuxXY_n_31,MuxXY_n_32,MuxXY_n_33,MuxXY_n_34,MuxXY_n_35,MuxXY_n_36,MuxXY_n_37,MuxXY_n_38,MuxXY_n_39,MuxXY_n_40,MuxXY_n_41,MuxXY_n_42,MuxXY_n_43,MuxXY_n_44,MuxXY_n_45,MuxXY_n_46,MuxXY_n_47,MuxXY_n_48,MuxXY_n_49,MuxXY_n_50,MuxXY_n_51,MuxXY_n_52,MuxXY_n_53,MuxXY_n_54,MuxXY_n_55,MuxXY_n_56,MuxXY_n_57,MuxXY_n_58}),
.\Q_reg[30] ({MuxXY_n_0,MuxXY_n_1,MuxXY_n_2,MuxXY_n_3,MuxXY_n_4,MuxXY_n_5,MuxXY_n_6,MuxXY_n_7,MuxXY_n_8,MuxXY_n_9,MuxXY_n_10,MuxXY_n_11,MuxXY_n_12,MuxXY_n_13,MuxXY_n_14,MuxXY_n_15,MuxXY_n_16,MuxXY_n_17,MuxXY_n_18,MuxXY_n_19,MuxXY_n_20,MuxXY_n_21,MuxXY_n_22,MuxXY_n_23,MuxXY_n_24,MuxXY_n_25,MuxXY_n_26,MuxXY_n_27,MuxXY_n_28,MuxXY_n_29,MuxXY_n_30}),
.\Q_reg[30]_0 ({INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}));
RegisterAdd__parameterized19 NRM_STAGE_DMP_exp
(.AR(AR[0]),
.CLK(CLK),
.Q({NRM_STAGE_DMP_exp_n_0,NRM_STAGE_DMP_exp_n_1,NRM_STAGE_DMP_exp_n_2,NRM_STAGE_DMP_exp_n_3,NRM_STAGE_DMP_exp_n_4,NRM_STAGE_DMP_exp_n_5,NRM_STAGE_DMP_exp_n_6,NRM_STAGE_DMP_exp_n_7}),
.\Q_reg[2]_0 (inst_ShiftRegister_n_4),
.\Q_reg[30] ({SGF_STAGE_DMP_n_4,SGF_STAGE_DMP_n_5,SGF_STAGE_DMP_n_6,SGF_STAGE_DMP_n_7,SGF_STAGE_DMP_n_8,SGF_STAGE_DMP_n_9,SGF_STAGE_DMP_n_10,SGF_STAGE_DMP_n_11}));
RegisterAdd__parameterized20 NRM_STAGE_FLAGS
(.AR(AR[0]),
.CLK(CLK),
.D(shft_value_mux_o_EWR[2]),
.Q({ADD_OVRFLW_NRM,NRM_STAGE_FLAGS_n_2,NRM_STAGE_FLAGS_n_3}),
.\Q_reg[0]_0 (NRM_STAGE_Raw_mant_n_30),
.\Q_reg[1]_0 (SHT1_STAGE_sft_amount_n_0),
.\Q_reg[1]_1 ({SGF_STAGE_FLAGS_n_0,ZERO_FLAG_SFG[2],ZERO_FLAG_SFG[0]}),
.\Q_reg[22] ({LZD_raw_out_EWR[2],LZD_raw_out_EWR[0]}),
.\Q_reg[25] (NRM_STAGE_FLAGS_n_4),
.\Q_reg[25]_0 (\Data_array_SWR[2]_1 [25]),
.\Q_reg[2]_0 ({inst_ShiftRegister_n_4,Shift_reg_FLAGS_7}),
.\Q_reg[2]_1 ({Shift_amount_SHT1_EWR[2],Shift_amount_SHT1_EWR[0]}));
RegisterAdd__parameterized18 NRM_STAGE_Raw_mant
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D(\Data_array_SWR[2]_1 [24:0]),
.Q({inst_ShiftRegister_n_4,Shift_reg_FLAGS_7}),
.\Q_reg[12]_0 (LZD_raw_out_EWR),
.\Q_reg[12]_1 (NRM_STAGE_Raw_mant_n_30),
.\Q_reg[1]_0 (bit_shift_SHT1),
.\Q_reg[1]_1 (SHT1_STAGE_sft_amount_n_0),
.\Q_reg[1]_2 (Raw_mant_SGF),
.\Q_reg[22]_0 ({SHT1_STAGE_DmP_mant_n_0,SHT1_STAGE_DmP_mant_n_1,SHT1_STAGE_DmP_mant_n_2,SHT1_STAGE_DmP_mant_n_3,SHT1_STAGE_DmP_mant_n_4,SHT1_STAGE_DmP_mant_n_5,SHT1_STAGE_DmP_mant_n_6,SHT1_STAGE_DmP_mant_n_7,SHT1_STAGE_DmP_mant_n_8,SHT1_STAGE_DmP_mant_n_9,SHT1_STAGE_DmP_mant_n_10,SHT1_STAGE_DmP_mant_n_11,SHT1_STAGE_DmP_mant_n_12,SHT1_STAGE_DmP_mant_n_13,SHT1_STAGE_DmP_mant_n_14,SHT1_STAGE_DmP_mant_n_15,SHT1_STAGE_DmP_mant_n_16,SHT1_STAGE_DmP_mant_n_17,SHT1_STAGE_DmP_mant_n_18,SHT1_STAGE_DmP_mant_n_19,SHT1_STAGE_DmP_mant_n_20,SHT1_STAGE_DmP_mant_n_21,SHT1_STAGE_DmP_mant_n_22}),
.\Q_reg[2]_0 (NRM_STAGE_FLAGS_n_4),
.\Q_reg[2]_1 (ADD_OVRFLW_NRM));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1
(.I0(SGF_STAGE_DmP_mant_n_35),
.I1(SGF_STAGE_DMP_n_41),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[10]));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1
(.I0(SGF_STAGE_DmP_mant_n_34),
.I1(SGF_STAGE_DMP_n_40),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[11]));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1
(.I0(SGF_STAGE_DmP_mant_n_33),
.I1(SGF_STAGE_DMP_n_39),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[12]));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_10
(.I0(DMP_mant_SFG_SWR[10]),
.I1(SGF_STAGE_DmP_mant_n_14),
.O(\Q[12]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_11
(.I0(DMP_mant_SFG_SWR[9]),
.I1(SGF_STAGE_DmP_mant_n_15),
.O(\Q[12]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_8
(.I0(DMP_mant_SFG_SWR[12]),
.I1(SGF_STAGE_DmP_mant_n_12),
.O(\Q[12]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_9
(.I0(DMP_mant_SFG_SWR[11]),
.I1(SGF_STAGE_DmP_mant_n_13),
.O(\Q[12]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1
(.I0(SGF_STAGE_DmP_mant_n_40),
.I1(SGF_STAGE_DMP_n_46),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[13]));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1
(.I0(SGF_STAGE_DmP_mant_n_39),
.I1(SGF_STAGE_DMP_n_45),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[14]));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1
(.I0(SGF_STAGE_DmP_mant_n_38),
.I1(SGF_STAGE_DMP_n_44),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[15]));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1
(.I0(SGF_STAGE_DmP_mant_n_37),
.I1(SGF_STAGE_DMP_n_43),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[16]));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_10
(.I0(DMP_mant_SFG_SWR[14]),
.I1(SGF_STAGE_DmP_mant_n_10),
.O(\Q[16]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_11
(.I0(DMP_mant_SFG_SWR[13]),
.I1(SGF_STAGE_DmP_mant_n_11),
.O(\Q[16]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_8
(.I0(DMP_mant_SFG_SWR[16]),
.I1(SGF_STAGE_DmP_mant_n_8),
.O(\Q[16]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_9
(.I0(DMP_mant_SFG_SWR[15]),
.I1(SGF_STAGE_DmP_mant_n_9),
.O(\Q[16]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1
(.I0(SGF_STAGE_DmP_mant_n_44),
.I1(SGF_STAGE_DMP_n_50),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[17]));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1
(.I0(SGF_STAGE_DmP_mant_n_43),
.I1(SGF_STAGE_DMP_n_49),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[18]));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1
(.I0(SGF_STAGE_DmP_mant_n_42),
.I1(SGF_STAGE_DMP_n_48),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[19]));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1
(.I0(SGF_STAGE_DmP_mant_n_28),
.I1(SGF_STAGE_DMP_n_3),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[1]));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1
(.I0(SGF_STAGE_DmP_mant_n_41),
.I1(SGF_STAGE_DMP_n_47),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[20]));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_10
(.I0(DMP_mant_SFG_SWR[18]),
.I1(SGF_STAGE_DmP_mant_n_6),
.O(\Q[20]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_11
(.I0(DMP_mant_SFG_SWR[17]),
.I1(SGF_STAGE_DmP_mant_n_7),
.O(\Q[20]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_8
(.I0(DMP_mant_SFG_SWR[20]),
.I1(SGF_STAGE_DmP_mant_n_4),
.O(\Q[20]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_9
(.I0(DMP_mant_SFG_SWR[19]),
.I1(SGF_STAGE_DmP_mant_n_5),
.O(\Q[20]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1
(.I0(SGF_STAGE_DmP_mant_n_48),
.I1(SGF_STAGE_DMP_n_55),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[21]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1
(.I0(SGF_STAGE_DmP_mant_n_47),
.I1(SGF_STAGE_DMP_n_54),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[22]));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1
(.I0(SGF_STAGE_DmP_mant_n_46),
.I1(SGF_STAGE_DMP_n_53),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[23]));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1
(.I0(SGF_STAGE_DmP_mant_n_45),
.I1(SGF_STAGE_DMP_n_52),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[24]));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_10
(.I0(DMP_mant_SFG_SWR[22]),
.I1(SGF_STAGE_DmP_mant_n_2),
.O(\Q[24]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_11
(.I0(DMP_mant_SFG_SWR[21]),
.I1(SGF_STAGE_DmP_mant_n_3),
.O(\Q[24]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_8
(.I0(DMP_mant_SFG_SWR[24]),
.I1(SGF_STAGE_DmP_mant_n_0),
.O(\Q[24]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_9
(.I0(DMP_mant_SFG_SWR[23]),
.I1(SGF_STAGE_DmP_mant_n_1),
.O(\Q[24]_i_9_n_0 ));
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1
(.I0(SGF_STAGE_DmP_mant_n_49),
.I1(SGF_STAGE_DmP_mant_n_51),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[25]));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1
(.I0(SGF_STAGE_DmP_mant_n_27),
.I1(SGF_STAGE_DMP_n_2),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[2]));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1
(.I0(SGF_STAGE_DmP_mant_n_26),
.I1(SGF_STAGE_DMP_n_1),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[3]));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1
(.I0(SGF_STAGE_DmP_mant_n_25),
.I1(SGF_STAGE_DMP_n_0),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[4]));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_10
(.I0(DMP_mant_SFG_SWR[3]),
.I1(SGF_STAGE_DmP_mant_n_21),
.O(\Q[4]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_11
(.I0(DMP_mant_SFG_SWR[2]),
.I1(SGF_STAGE_DmP_mant_n_22),
.O(\Q[4]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_9
(.I0(DMP_mant_SFG_SWR[4]),
.I1(SGF_STAGE_DmP_mant_n_20),
.O(\Q[4]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1
(.I0(SGF_STAGE_DmP_mant_n_32),
.I1(SGF_STAGE_DMP_n_38),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[5]));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1
(.I0(SGF_STAGE_DmP_mant_n_31),
.I1(SGF_STAGE_DMP_n_37),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[6]));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1
(.I0(SGF_STAGE_DmP_mant_n_30),
.I1(SGF_STAGE_DMP_n_36),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[7]));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1
(.I0(SGF_STAGE_DmP_mant_n_29),
.I1(SGF_STAGE_DMP_n_35),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[8]));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_10
(.I0(DMP_mant_SFG_SWR[6]),
.I1(SGF_STAGE_DmP_mant_n_18),
.O(\Q[8]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_11
(.I0(DMP_mant_SFG_SWR[5]),
.I1(SGF_STAGE_DmP_mant_n_19),
.O(\Q[8]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_8__0
(.I0(DMP_mant_SFG_SWR[8]),
.I1(SGF_STAGE_DmP_mant_n_16),
.O(\Q[8]_i_8__0_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_9__0
(.I0(DMP_mant_SFG_SWR[7]),
.I1(SGF_STAGE_DmP_mant_n_17),
.O(\Q[8]_i_9__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1
(.I0(SGF_STAGE_DmP_mant_n_36),
.I1(SGF_STAGE_DMP_n_42),
.I2(ZERO_FLAG_SFG[1]),
.O(Raw_mant_SGF[9]));
RegisterAdd__parameterized22 Ready_reg
(.AR(AR[1]),
.CLK(CLK),
.Q(inst_ShiftRegister_n_6),
.ready_add_subt(ready_add_subt));
RegisterAdd__parameterized14 SFT2FRMT_STAGE_FLAGS
(.AR(AR[2]),
.CLK(CLK),
.D(formatted_number_W),
.DI(SFT2FRMT_STAGE_FLAGS_n_1),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({ADD_OVRFLW_NRM2,SFT2FRMT_STAGE_FLAGS_n_3}),
.\Q_reg[1]_0 (Shift_reg_FLAGS_7),
.\Q_reg[2]_0 ({ADD_OVRFLW_NRM,NRM_STAGE_FLAGS_n_2,NRM_STAGE_FLAGS_n_3}),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
RegisterAdd__parameterized13 SFT2FRMT_STAGE_VARS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({SFT2FRMT_STAGE_VARS_n_15,SFT2FRMT_STAGE_VARS_n_16,SFT2FRMT_STAGE_VARS_n_17,SFT2FRMT_STAGE_VARS_n_18,SFT2FRMT_STAGE_VARS_n_19,SFT2FRMT_STAGE_VARS_n_20,SFT2FRMT_STAGE_VARS_n_21,SFT2FRMT_STAGE_VARS_n_22}),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q(ADD_OVRFLW_NRM2),
.\Q_reg[1]_0 (SFT2FRMT_STAGE_VARS_n_23),
.\Q_reg[1]_1 (Shift_reg_FLAGS_7),
.\Q_reg[1]_2 ({LZD_raw_out_EWR,NRM_STAGE_DMP_exp_n_0,NRM_STAGE_DMP_exp_n_1,NRM_STAGE_DMP_exp_n_2,NRM_STAGE_DMP_exp_n_3,NRM_STAGE_DMP_exp_n_4,NRM_STAGE_DMP_exp_n_5,NRM_STAGE_DMP_exp_n_6,NRM_STAGE_DMP_exp_n_7}),
.\Q_reg[30] ({SFT2FRMT_STAGE_VARS_n_4,SFT2FRMT_STAGE_VARS_n_5,SFT2FRMT_STAGE_VARS_n_6,SFT2FRMT_STAGE_VARS_n_7}),
.\Q_reg[30]_0 ({SFT2FRMT_STAGE_VARS_n_8,SFT2FRMT_STAGE_VARS_n_9,SFT2FRMT_STAGE_VARS_n_10,SFT2FRMT_STAGE_VARS_n_11,SFT2FRMT_STAGE_VARS_n_12,SFT2FRMT_STAGE_VARS_n_13,SFT2FRMT_STAGE_VARS_n_14}),
.S({SFT2FRMT_STAGE_VARS_n_0,SFT2FRMT_STAGE_VARS_n_1,SFT2FRMT_STAGE_VARS_n_2,SFT2FRMT_STAGE_VARS_n_3}),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT),
.exp_rslt_NRM2_EW1(exp_rslt_NRM2_EW1[7:0]));
RegisterAdd__parameterized15 SGF_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.CO(SGF_STAGE_DMP_n_51),
.E(load0),
.O({SGF_STAGE_DMP_n_0,SGF_STAGE_DMP_n_1,SGF_STAGE_DMP_n_2,SGF_STAGE_DMP_n_3}),
.Q({SGF_STAGE_DMP_n_4,SGF_STAGE_DMP_n_5,SGF_STAGE_DMP_n_6,SGF_STAGE_DMP_n_7,SGF_STAGE_DMP_n_8,SGF_STAGE_DMP_n_9,SGF_STAGE_DMP_n_10,SGF_STAGE_DMP_n_11,DMP_mant_SFG_SWR}),
.\Q_reg[10]_0 ({\Q[12]_i_8_n_0 ,\Q[12]_i_9_n_0 ,\Q[12]_i_10_n_0 ,\Q[12]_i_11_n_0 }),
.\Q_reg[12]_0 ({SGF_STAGE_DMP_n_39,SGF_STAGE_DMP_n_40,SGF_STAGE_DMP_n_41,SGF_STAGE_DMP_n_42}),
.\Q_reg[14]_0 ({\Q[16]_i_8_n_0 ,\Q[16]_i_9_n_0 ,\Q[16]_i_10_n_0 ,\Q[16]_i_11_n_0 }),
.\Q_reg[16]_0 ({SGF_STAGE_DMP_n_43,SGF_STAGE_DMP_n_44,SGF_STAGE_DMP_n_45,SGF_STAGE_DMP_n_46}),
.\Q_reg[18]_0 ({\Q[20]_i_8_n_0 ,\Q[20]_i_9_n_0 ,\Q[20]_i_10_n_0 ,\Q[20]_i_11_n_0 }),
.\Q_reg[20]_0 ({SGF_STAGE_DMP_n_47,SGF_STAGE_DMP_n_48,SGF_STAGE_DMP_n_49,SGF_STAGE_DMP_n_50}),
.\Q_reg[22]_0 ({\Q[24]_i_8_n_0 ,\Q[24]_i_9_n_0 ,\Q[24]_i_10_n_0 ,\Q[24]_i_11_n_0 }),
.\Q_reg[24]_0 ({SGF_STAGE_DMP_n_52,SGF_STAGE_DMP_n_53,SGF_STAGE_DMP_n_54,SGF_STAGE_DMP_n_55}),
.\Q_reg[30]_0 ({SHT2_STAGE_DMP_n_0,SHT2_STAGE_DMP_n_1,SHT2_STAGE_DMP_n_2,SHT2_STAGE_DMP_n_3,SHT2_STAGE_DMP_n_4,SHT2_STAGE_DMP_n_5,SHT2_STAGE_DMP_n_6,SHT2_STAGE_DMP_n_7,SHT2_STAGE_DMP_n_8,SHT2_STAGE_DMP_n_9,SHT2_STAGE_DMP_n_10,SHT2_STAGE_DMP_n_11,SHT2_STAGE_DMP_n_12,SHT2_STAGE_DMP_n_13,SHT2_STAGE_DMP_n_14,SHT2_STAGE_DMP_n_15,SHT2_STAGE_DMP_n_16,SHT2_STAGE_DMP_n_17,SHT2_STAGE_DMP_n_18,SHT2_STAGE_DMP_n_19,SHT2_STAGE_DMP_n_20,SHT2_STAGE_DMP_n_21,SHT2_STAGE_DMP_n_22,SHT2_STAGE_DMP_n_23,SHT2_STAGE_DMP_n_24,SHT2_STAGE_DMP_n_25,SHT2_STAGE_DMP_n_26,SHT2_STAGE_DMP_n_27,SHT2_STAGE_DMP_n_28,SHT2_STAGE_DMP_n_29,SHT2_STAGE_DMP_n_30}),
.\Q_reg[6]_0 ({\Q[8]_i_8__0_n_0 ,\Q[8]_i_9__0_n_0 ,\Q[8]_i_10_n_0 ,\Q[8]_i_11_n_0 }),
.\Q_reg[8]_0 ({SGF_STAGE_DMP_n_35,SGF_STAGE_DMP_n_36,SGF_STAGE_DMP_n_37,SGF_STAGE_DMP_n_38}),
.S({\Q[4]_i_9_n_0 ,\Q[4]_i_10_n_0 ,\Q[4]_i_11_n_0 ,SGF_STAGE_DmP_mant_n_24}));
RegisterAdd__parameterized16 SGF_STAGE_DmP_mant
(.AR(AR),
.CLK(CLK),
.CO(p_1_in_2),
.D(sftr_odat_SHT2_SWR),
.E(load0),
.O({SGF_STAGE_DmP_mant_n_25,SGF_STAGE_DmP_mant_n_26,SGF_STAGE_DmP_mant_n_27,SGF_STAGE_DmP_mant_n_28}),
.Q({SGF_STAGE_DmP_mant_n_0,SGF_STAGE_DmP_mant_n_1,SGF_STAGE_DmP_mant_n_2,SGF_STAGE_DmP_mant_n_3,SGF_STAGE_DmP_mant_n_4,SGF_STAGE_DmP_mant_n_5,SGF_STAGE_DmP_mant_n_6,SGF_STAGE_DmP_mant_n_7,SGF_STAGE_DmP_mant_n_8,SGF_STAGE_DmP_mant_n_9,SGF_STAGE_DmP_mant_n_10,SGF_STAGE_DmP_mant_n_11,SGF_STAGE_DmP_mant_n_12,SGF_STAGE_DmP_mant_n_13,SGF_STAGE_DmP_mant_n_14,SGF_STAGE_DmP_mant_n_15,SGF_STAGE_DmP_mant_n_16,SGF_STAGE_DmP_mant_n_17,SGF_STAGE_DmP_mant_n_18,SGF_STAGE_DmP_mant_n_19,SGF_STAGE_DmP_mant_n_20,SGF_STAGE_DmP_mant_n_21,SGF_STAGE_DmP_mant_n_22,Raw_mant_SGF[0]}),
.\Q_reg[12]_0 ({SGF_STAGE_DmP_mant_n_33,SGF_STAGE_DmP_mant_n_34,SGF_STAGE_DmP_mant_n_35,SGF_STAGE_DmP_mant_n_36}),
.\Q_reg[16]_0 ({SGF_STAGE_DmP_mant_n_37,SGF_STAGE_DmP_mant_n_38,SGF_STAGE_DmP_mant_n_39,SGF_STAGE_DmP_mant_n_40}),
.\Q_reg[20]_0 ({SGF_STAGE_DmP_mant_n_41,SGF_STAGE_DmP_mant_n_42,SGF_STAGE_DmP_mant_n_43,SGF_STAGE_DmP_mant_n_44}),
.\Q_reg[22]_0 (DMP_mant_SFG_SWR),
.\Q_reg[22]_1 (SGF_STAGE_DMP_n_51),
.\Q_reg[24]_0 ({SGF_STAGE_DmP_mant_n_45,SGF_STAGE_DmP_mant_n_46,SGF_STAGE_DmP_mant_n_47,SGF_STAGE_DmP_mant_n_48}),
.\Q_reg[25]_0 (SGF_STAGE_DmP_mant_n_49),
.\Q_reg[25]_1 (SGF_STAGE_DmP_mant_n_51),
.\Q_reg[8]_0 ({SGF_STAGE_DmP_mant_n_29,SGF_STAGE_DmP_mant_n_30,SGF_STAGE_DmP_mant_n_31,SGF_STAGE_DmP_mant_n_32}),
.S(SGF_STAGE_DmP_mant_n_24));
RegisterAdd__parameterized17 SGF_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.CO(p_1_in_2),
.E(load0),
.Q(ZERO_FLAG_SFG[1]),
.\Q_reg[2]_0 ({SGF_STAGE_FLAGS_n_0,ZERO_FLAG_SFG[2],ZERO_FLAG_SFG[0]}),
.\Q_reg[2]_1 ({SHT2_STAGE_FLAGS_n_0,SHT2_STAGE_FLAGS_n_1,SHT2_STAGE_FLAGS_n_2}));
RegisterAdd__parameterized4 SHT1_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.D({EXP_STAGE_DMP_n_2,EXP_STAGE_DMP_n_3,EXP_STAGE_DMP_n_4,p_1_in,EXP_STAGE_DMP_n_10,EXP_STAGE_DMP_n_11,EXP_STAGE_DMP_n_12,EXP_STAGE_DMP_n_13,EXP_STAGE_DMP_n_14,EXP_STAGE_DMP_n_15,EXP_STAGE_DMP_n_16,EXP_STAGE_DMP_n_17,EXP_STAGE_DMP_n_18,EXP_STAGE_DMP_n_19,EXP_STAGE_DMP_n_20,EXP_STAGE_DMP_n_21,EXP_STAGE_DMP_n_22,EXP_STAGE_DMP_n_23,EXP_STAGE_DMP_n_24,EXP_STAGE_DMP_n_25,EXP_STAGE_DMP_n_26,EXP_STAGE_DMP_n_27,EXP_STAGE_DMP_n_28,EXP_STAGE_DMP_n_29,EXP_STAGE_DMP_n_30,EXP_STAGE_DMP_n_31,EXP_STAGE_DMP_n_32}),
.Q({SHT1_STAGE_DMP_n_0,SHT1_STAGE_DMP_n_1,SHT1_STAGE_DMP_n_2,SHT1_STAGE_DMP_n_3,SHT1_STAGE_DMP_n_4,SHT1_STAGE_DMP_n_5,SHT1_STAGE_DMP_n_6,SHT1_STAGE_DMP_n_7,SHT1_STAGE_DMP_n_8,SHT1_STAGE_DMP_n_9,SHT1_STAGE_DMP_n_10,SHT1_STAGE_DMP_n_11,SHT1_STAGE_DMP_n_12,SHT1_STAGE_DMP_n_13,SHT1_STAGE_DMP_n_14,SHT1_STAGE_DMP_n_15,SHT1_STAGE_DMP_n_16,SHT1_STAGE_DMP_n_17,SHT1_STAGE_DMP_n_18,SHT1_STAGE_DMP_n_19,SHT1_STAGE_DMP_n_20,SHT1_STAGE_DMP_n_21,SHT1_STAGE_DMP_n_22,SHT1_STAGE_DMP_n_23,SHT1_STAGE_DMP_n_24,SHT1_STAGE_DMP_n_25,SHT1_STAGE_DMP_n_26,SHT1_STAGE_DMP_n_27,SHT1_STAGE_DMP_n_28,SHT1_STAGE_DMP_n_29,SHT1_STAGE_DMP_n_30}),
.\Q_reg[5]_0 (inst_ShiftRegister_n_2));
RegisterAdd__parameterized5 SHT1_STAGE_DmP_mant
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({EXP_STAGE_DmP_n_6,EXP_STAGE_DmP_n_7,EXP_STAGE_DmP_n_8,EXP_STAGE_DmP_n_9,EXP_STAGE_DmP_n_10,EXP_STAGE_DmP_n_11,EXP_STAGE_DmP_n_12,EXP_STAGE_DmP_n_13,EXP_STAGE_DmP_n_14,EXP_STAGE_DmP_n_15,EXP_STAGE_DmP_n_16,EXP_STAGE_DmP_n_17,EXP_STAGE_DmP_n_18,EXP_STAGE_DmP_n_19,EXP_STAGE_DmP_n_20,EXP_STAGE_DmP_n_21,EXP_STAGE_DmP_n_22,EXP_STAGE_DmP_n_23,EXP_STAGE_DmP_n_24,EXP_STAGE_DmP_n_25,EXP_STAGE_DmP_n_26,EXP_STAGE_DmP_n_27,EXP_STAGE_DmP_n_28}),
.Q({SHT1_STAGE_DmP_mant_n_0,SHT1_STAGE_DmP_mant_n_1,SHT1_STAGE_DmP_mant_n_2,SHT1_STAGE_DmP_mant_n_3,SHT1_STAGE_DmP_mant_n_4,SHT1_STAGE_DmP_mant_n_5,SHT1_STAGE_DmP_mant_n_6,SHT1_STAGE_DmP_mant_n_7,SHT1_STAGE_DmP_mant_n_8,SHT1_STAGE_DmP_mant_n_9,SHT1_STAGE_DmP_mant_n_10,SHT1_STAGE_DmP_mant_n_11,SHT1_STAGE_DmP_mant_n_12,SHT1_STAGE_DmP_mant_n_13,SHT1_STAGE_DmP_mant_n_14,SHT1_STAGE_DmP_mant_n_15,SHT1_STAGE_DmP_mant_n_16,SHT1_STAGE_DmP_mant_n_17,SHT1_STAGE_DmP_mant_n_18,SHT1_STAGE_DmP_mant_n_19,SHT1_STAGE_DmP_mant_n_20,SHT1_STAGE_DmP_mant_n_21,SHT1_STAGE_DmP_mant_n_22}),
.\Q_reg[5]_0 (inst_ShiftRegister_n_2));
RegisterAdd__parameterized7 SHT1_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({EXP_STAGE_FLAGS_n_0,EXP_STAGE_FLAGS_n_1,EXP_STAGE_FLAGS_n_2}),
.Q({SHT1_STAGE_FLAGS_n_0,SHT1_STAGE_FLAGS_n_1,SHT1_STAGE_FLAGS_n_2}),
.\Q_reg[5] (inst_ShiftRegister_n_2));
RegisterAdd__parameterized6 SHT1_STAGE_sft_amount
(.AR(AR[2]),
.CLK(CLK),
.D(shft_value_mux_o_EWR[4:3]),
.Q({Shift_amount_SHT1_EWR[2],Shift_amount_SHT1_EWR[0]}),
.\Q_reg[1]_0 ({LZD_raw_out_EWR[4:3],LZD_raw_out_EWR[1]}),
.\Q_reg[23] (SHT1_STAGE_sft_amount_n_0),
.\Q_reg[26] ({Shift_amount_EXP_EW,EXP_STAGE_DMP_n_1}),
.\Q_reg[2]_0 (ADD_OVRFLW_NRM),
.\Q_reg[5] ({inst_ShiftRegister_n_2,Shift_reg_FLAGS_7}));
RegisterAdd__parameterized9 SHT2_SHIFT_DATA
(.CLK(CLK),
.D({SHT2_SHIFT_DATA_n_0,SHT2_SHIFT_DATA_n_1,SHT2_SHIFT_DATA_n_2}),
.\Data_array_SWR[4]_5 (\Data_array_SWR[4]_5 ),
.\Data_array_SWR[6]_4 (\Data_array_SWR[6]_4 [1]),
.E(inst_ShiftRegister_n_7),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({left_right_SHT2,bit_shift_SHT2}),
.\Q_reg[13]_0 (\Data_array_SWR[3]_0 ),
.\Q_reg[25]_0 ({sftr_odat_SHT2_SWR[25:24],sftr_odat_SHT2_SWR[13:12],sftr_odat_SHT2_SWR[0]}),
.\Q_reg[2]_0 (\Data_array_SWR[2]_1 ),
.\Q_reg[4]_0 (\Data_array_SWR[6]_4 [25:24]),
.\Q_reg[4]_1 (shift_value_SHT2_EWR),
.\Q_reg[8]_0 ({\Data_array_SWR[5]_3 [17:16],\Data_array_SWR[5]_3 [11:2]}),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
RegisterAdd__parameterized8 SHT2_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.D({SHT1_STAGE_DMP_n_0,SHT1_STAGE_DMP_n_1,SHT1_STAGE_DMP_n_2,SHT1_STAGE_DMP_n_3,SHT1_STAGE_DMP_n_4,SHT1_STAGE_DMP_n_5,SHT1_STAGE_DMP_n_6,SHT1_STAGE_DMP_n_7,SHT1_STAGE_DMP_n_8,SHT1_STAGE_DMP_n_9,SHT1_STAGE_DMP_n_10,SHT1_STAGE_DMP_n_11,SHT1_STAGE_DMP_n_12,SHT1_STAGE_DMP_n_13,SHT1_STAGE_DMP_n_14,SHT1_STAGE_DMP_n_15,SHT1_STAGE_DMP_n_16,SHT1_STAGE_DMP_n_17,SHT1_STAGE_DMP_n_18,SHT1_STAGE_DMP_n_19,SHT1_STAGE_DMP_n_20,SHT1_STAGE_DMP_n_21,SHT1_STAGE_DMP_n_22,SHT1_STAGE_DMP_n_23,SHT1_STAGE_DMP_n_24,SHT1_STAGE_DMP_n_25,SHT1_STAGE_DMP_n_26,SHT1_STAGE_DMP_n_27,SHT1_STAGE_DMP_n_28,SHT1_STAGE_DMP_n_29,SHT1_STAGE_DMP_n_30}),
.Q({SHT2_STAGE_DMP_n_0,SHT2_STAGE_DMP_n_1,SHT2_STAGE_DMP_n_2,SHT2_STAGE_DMP_n_3,SHT2_STAGE_DMP_n_4,SHT2_STAGE_DMP_n_5,SHT2_STAGE_DMP_n_6,SHT2_STAGE_DMP_n_7,SHT2_STAGE_DMP_n_8,SHT2_STAGE_DMP_n_9,SHT2_STAGE_DMP_n_10,SHT2_STAGE_DMP_n_11,SHT2_STAGE_DMP_n_12,SHT2_STAGE_DMP_n_13,SHT2_STAGE_DMP_n_14,SHT2_STAGE_DMP_n_15,SHT2_STAGE_DMP_n_16,SHT2_STAGE_DMP_n_17,SHT2_STAGE_DMP_n_18,SHT2_STAGE_DMP_n_19,SHT2_STAGE_DMP_n_20,SHT2_STAGE_DMP_n_21,SHT2_STAGE_DMP_n_22,SHT2_STAGE_DMP_n_23,SHT2_STAGE_DMP_n_24,SHT2_STAGE_DMP_n_25,SHT2_STAGE_DMP_n_26,SHT2_STAGE_DMP_n_27,SHT2_STAGE_DMP_n_28,SHT2_STAGE_DMP_n_29,SHT2_STAGE_DMP_n_30}),
.\Q_reg[4]_0 (Q));
RegisterAdd__parameterized12 SHT2_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({SHT1_STAGE_FLAGS_n_0,SHT1_STAGE_FLAGS_n_1,SHT1_STAGE_FLAGS_n_2}),
.Q({SHT2_STAGE_FLAGS_n_0,SHT2_STAGE_FLAGS_n_1,SHT2_STAGE_FLAGS_n_2}),
.\Q_reg[4] (Q));
RegisterAdd__parameterized10 SHT2_STAGE_SHFTVARS1
(.CLK(CLK),
.D({SHT2_STAGE_SHFTVARS1_n_0,SHT2_STAGE_SHFTVARS1_n_1,SHT2_STAGE_SHFTVARS1_n_2,SHT2_STAGE_SHFTVARS1_n_3,SHT2_STAGE_SHFTVARS1_n_4,SHT2_STAGE_SHFTVARS1_n_5,SHT2_STAGE_SHFTVARS1_n_6,SHT2_STAGE_SHFTVARS1_n_7,SHT2_STAGE_SHFTVARS1_n_8,SHT2_STAGE_SHFTVARS1_n_9,SHT2_STAGE_SHFTVARS1_n_10,SHT2_STAGE_SHFTVARS1_n_11,SHT2_STAGE_SHFTVARS1_n_12,SHT2_STAGE_SHFTVARS1_n_13}),
.\Data_array_SWR[4]_5 (\Data_array_SWR[4]_5 ),
.E(inst_ShiftRegister_n_7),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({left_right_SHT2,bit_shift_SHT2}),
.\Q_reg[0] ({\Data_array_SWR[5]_3 [17:16],\Data_array_SWR[5]_3 [9:2]}),
.\Q_reg[16] (shift_value_SHT2_EWR),
.\Q_reg[23] ({sftr_odat_SHT2_SWR[23:16],sftr_odat_SHT2_SWR[7:1]}),
.\Q_reg[25] ({\Data_array_SWR[6]_4 [25:24],\Data_array_SWR[6]_4 [15:14],\Data_array_SWR[6]_4 [9:8]}),
.\Q_reg[25]_0 (\Data_array_SWR[3]_0 ),
.\Q_reg[4]_0 (\Data_array_SWR[6]_4 [1]),
.\Q_reg[4]_1 (shft_value_mux_o_EWR),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
RegisterAdd__parameterized11 SHT2_STAGE_SHFTVARS2
(.CLK(CLK),
.D({SHT2_STAGE_SHFTVARS2_n_0,SHT2_STAGE_SHFTVARS2_n_1,SHT2_STAGE_SHFTVARS2_n_2,SHT2_STAGE_SHFTVARS2_n_3,SHT2_STAGE_SHFTVARS2_n_4,SHT2_STAGE_SHFTVARS2_n_5}),
.E(inst_ShiftRegister_n_7),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({left_right_SHT2,bit_shift_SHT2}),
.\Q_reg[0]_0 ({\Data_array_SWR[5]_3 [17:16],\Data_array_SWR[5]_3 [11:10]}),
.\Q_reg[15] ({sftr_odat_SHT2_SWR[15:14],sftr_odat_SHT2_SWR[11:8]}),
.\Q_reg[1]_0 ({left_right_SHT1,bit_shift_SHT1}),
.\Q_reg[4] ({\Data_array_SWR[6]_4 [15:14],\Data_array_SWR[6]_4 [9:8]}),
.\Q_reg[4]_0 (shift_value_SHT2_EWR[4]),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _inferred__1_carry
(.CI(1'b0),
.CO({_inferred__1_carry_n_0,_inferred__1_carry_n_1,_inferred__1_carry_n_2,_inferred__1_carry_n_3}),
.CYINIT(SFT2FRMT_STAGE_VARS_n_14),
.DI({SFT2FRMT_STAGE_VARS_n_11,SFT2FRMT_STAGE_VARS_n_12,SFT2FRMT_STAGE_VARS_n_13,SFT2FRMT_STAGE_FLAGS_n_1}),
.O(exp_rslt_NRM2_EW1[3:0]),
.S({SFT2FRMT_STAGE_VARS_n_0,SFT2FRMT_STAGE_VARS_n_1,SFT2FRMT_STAGE_VARS_n_2,SFT2FRMT_STAGE_VARS_n_3}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _inferred__1_carry__0
(.CI(_inferred__1_carry_n_0),
.CO({_inferred__1_carry__0_n_0,_inferred__1_carry__0_n_1,_inferred__1_carry__0_n_2,_inferred__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({SFT2FRMT_STAGE_VARS_n_8,SFT2FRMT_STAGE_VARS_n_9,ADD_OVRFLW_NRM2,SFT2FRMT_STAGE_VARS_n_10}),
.O(exp_rslt_NRM2_EW1[7:4]),
.S({SFT2FRMT_STAGE_VARS_n_4,SFT2FRMT_STAGE_VARS_n_5,SFT2FRMT_STAGE_VARS_n_6,SFT2FRMT_STAGE_VARS_n_7}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _inferred__1_carry__1
(.CI(_inferred__1_carry__0_n_0),
.CO(NLW__inferred__1_carry__1_CO_UNCONNECTED[3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW__inferred__1_carry__1_O_UNCONNECTED[3:1],exp_rslt_NRM2_EW1[8]}),
.S({1'b0,1'b0,1'b0,SFT2FRMT_STAGE_VARS_n_23}));
FSM_INPUT_ENABLE inst_FSM_INPUT_ENABLE
(.CLK(CLK),
.D(FSM_enable_input_internal),
.\FSM_sequential_state_reg_reg[1]_0 (\FSM_sequential_state_reg_reg[1] ),
.\FSM_sequential_state_reg_reg[2]_0 (\FSM_sequential_state_reg_reg[2] ),
.out({out,inst_FSM_INPUT_ENABLE_n_1,inst_FSM_INPUT_ENABLE_n_2}));
LUT3 #(
.INIT(8'h7E))
\inst_FSM_INPUT_ENABLE/
(.I0(inst_FSM_INPUT_ENABLE_n_2),
.I1(out),
.I2(inst_FSM_INPUT_ENABLE_n_1),
.O(enable_shift_reg));
ShiftRegister inst_ShiftRegister
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D(FSM_enable_input_internal),
.E(load0),
.\FSM_sequential_state_reg_reg[0] (enable_shift_reg),
.Q({inst_ShiftRegister_n_1,inst_ShiftRegister_n_2,Q,inst_ShiftRegister_n_4,Shift_reg_FLAGS_7,inst_ShiftRegister_n_6}),
.\Q_reg[1]_0 (inst_ShiftRegister_n_7),
.\Q_reg[1]_1 ({left_right_SHT1,bit_shift_SHT1}),
.\Q_reg[2]_0 (ADD_OVRFLW_NRM));
sgn_result result_sign_bit
(.CO(gtXY),
.D(SIGN_FLAG_INIT),
.Q(intDY_EWSW),
.\Q_reg[30] (eqXY),
.\Q_reg[31] (intDX_EWSW),
.intAS(intAS));
endmodule
module FSM_INPUT_ENABLE
(out,
D,
CLK,
\FSM_sequential_state_reg_reg[1]_0 ,
\FSM_sequential_state_reg_reg[2]_0 );
output [2:0]out;
output [0:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1]_0 ;
input [1:0]\FSM_sequential_state_reg_reg[2]_0 ;
wire CLK;
wire [0:0]D;
wire \FSM_sequential_state_reg[0]_i_1_n_0 ;
wire \FSM_sequential_state_reg[1]_i_1_n_0 ;
wire \FSM_sequential_state_reg[2]_i_1_n_0 ;
wire [0:0]\FSM_sequential_state_reg_reg[1]_0 ;
wire [1:0]\FSM_sequential_state_reg_reg[2]_0 ;
(* RTL_KEEP = "yes" *) wire [2:0]out;
LUT5 #(
.INIT(32'h14145514))
\FSM_sequential_state_reg[0]_i_1
(.I0(out[0]),
.I1(out[1]),
.I2(out[2]),
.I3(\FSM_sequential_state_reg_reg[2]_0 [1]),
.I4(\FSM_sequential_state_reg_reg[2]_0 [0]),
.O(\FSM_sequential_state_reg[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'h26))
\FSM_sequential_state_reg[1]_i_1
(.I0(out[0]),
.I1(out[1]),
.I2(out[2]),
.O(\FSM_sequential_state_reg[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'h38))
\FSM_sequential_state_reg[2]_i_1
(.I0(out[0]),
.I1(out[1]),
.I2(out[2]),
.O(\FSM_sequential_state_reg[2]_i_1_n_0 ));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[1]_0 ),
.D(\FSM_sequential_state_reg[0]_i_1_n_0 ),
.Q(out[0]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[1]_0 ),
.D(\FSM_sequential_state_reg[1]_i_1_n_0 ),
.Q(out[1]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[2]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[1]_0 ),
.D(\FSM_sequential_state_reg[2]_i_1_n_0 ),
.Q(out[2]));
LUT1 #(
.INIT(2'h1))
\Q[6]_i_1__0
(.I0(out[2]),
.O(D));
endmodule
module MultiplexTxT
(\Q_reg[30] ,
\Q_reg[27] ,
Q,
\Q_reg[30]_0 ,
CO);
output [30:0]\Q_reg[30] ;
output [27:0]\Q_reg[27] ;
input [30:0]Q;
input [30:0]\Q_reg[30]_0 ;
input [0:0]CO;
wire [0:0]CO;
wire [30:0]Q;
wire [27:0]\Q_reg[27] ;
wire [30:0]\Q_reg[30] ;
wire [30:0]\Q_reg[30]_0 ;
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\Q[0]_i_1
(.I0(Q[0]),
.I1(\Q_reg[30]_0 [0]),
.I2(CO),
.O(\Q_reg[30] [0]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\Q[0]_i_1__0
(.I0(\Q_reg[30]_0 [0]),
.I1(Q[0]),
.I2(CO),
.O(\Q_reg[27] [0]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1
(.I0(Q[10]),
.I1(\Q_reg[30]_0 [10]),
.I2(CO),
.O(\Q_reg[30] [10]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1__0
(.I0(\Q_reg[30]_0 [10]),
.I1(Q[10]),
.I2(CO),
.O(\Q_reg[27] [10]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1
(.I0(Q[11]),
.I1(\Q_reg[30]_0 [11]),
.I2(CO),
.O(\Q_reg[30] [11]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1__0
(.I0(\Q_reg[30]_0 [11]),
.I1(Q[11]),
.I2(CO),
.O(\Q_reg[27] [11]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1
(.I0(Q[12]),
.I1(\Q_reg[30]_0 [12]),
.I2(CO),
.O(\Q_reg[30] [12]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1__0
(.I0(\Q_reg[30]_0 [12]),
.I1(Q[12]),
.I2(CO),
.O(\Q_reg[27] [12]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1
(.I0(Q[13]),
.I1(\Q_reg[30]_0 [13]),
.I2(CO),
.O(\Q_reg[30] [13]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1__0
(.I0(\Q_reg[30]_0 [13]),
.I1(Q[13]),
.I2(CO),
.O(\Q_reg[27] [13]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1
(.I0(Q[14]),
.I1(\Q_reg[30]_0 [14]),
.I2(CO),
.O(\Q_reg[30] [14]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1__0
(.I0(\Q_reg[30]_0 [14]),
.I1(Q[14]),
.I2(CO),
.O(\Q_reg[27] [14]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1
(.I0(Q[15]),
.I1(\Q_reg[30]_0 [15]),
.I2(CO),
.O(\Q_reg[30] [15]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1__0
(.I0(\Q_reg[30]_0 [15]),
.I1(Q[15]),
.I2(CO),
.O(\Q_reg[27] [15]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1
(.I0(Q[16]),
.I1(\Q_reg[30]_0 [16]),
.I2(CO),
.O(\Q_reg[30] [16]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1__0
(.I0(\Q_reg[30]_0 [16]),
.I1(Q[16]),
.I2(CO),
.O(\Q_reg[27] [16]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1
(.I0(Q[17]),
.I1(\Q_reg[30]_0 [17]),
.I2(CO),
.O(\Q_reg[30] [17]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1__0
(.I0(\Q_reg[30]_0 [17]),
.I1(Q[17]),
.I2(CO),
.O(\Q_reg[27] [17]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1
(.I0(Q[18]),
.I1(\Q_reg[30]_0 [18]),
.I2(CO),
.O(\Q_reg[30] [18]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1__0
(.I0(\Q_reg[30]_0 [18]),
.I1(Q[18]),
.I2(CO),
.O(\Q_reg[27] [18]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1
(.I0(Q[19]),
.I1(\Q_reg[30]_0 [19]),
.I2(CO),
.O(\Q_reg[30] [19]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1__0
(.I0(\Q_reg[30]_0 [19]),
.I1(Q[19]),
.I2(CO),
.O(\Q_reg[27] [19]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1
(.I0(Q[1]),
.I1(\Q_reg[30]_0 [1]),
.I2(CO),
.O(\Q_reg[30] [1]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1__0
(.I0(\Q_reg[30]_0 [1]),
.I1(Q[1]),
.I2(CO),
.O(\Q_reg[27] [1]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1
(.I0(Q[20]),
.I1(\Q_reg[30]_0 [20]),
.I2(CO),
.O(\Q_reg[30] [20]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1__0
(.I0(\Q_reg[30]_0 [20]),
.I1(Q[20]),
.I2(CO),
.O(\Q_reg[27] [20]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1
(.I0(Q[21]),
.I1(\Q_reg[30]_0 [21]),
.I2(CO),
.O(\Q_reg[30] [21]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1__0
(.I0(\Q_reg[30]_0 [21]),
.I1(Q[21]),
.I2(CO),
.O(\Q_reg[27] [21]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1
(.I0(Q[22]),
.I1(\Q_reg[30]_0 [22]),
.I2(CO),
.O(\Q_reg[30] [22]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1__0
(.I0(\Q_reg[30]_0 [22]),
.I1(Q[22]),
.I2(CO),
.O(\Q_reg[27] [22]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1
(.I0(Q[23]),
.I1(\Q_reg[30]_0 [23]),
.I2(CO),
.O(\Q_reg[30] [23]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1__0
(.I0(\Q_reg[30]_0 [23]),
.I1(Q[23]),
.I2(CO),
.O(\Q_reg[27] [23]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1
(.I0(Q[24]),
.I1(\Q_reg[30]_0 [24]),
.I2(CO),
.O(\Q_reg[30] [24]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1__0
(.I0(\Q_reg[30]_0 [24]),
.I1(Q[24]),
.I2(CO),
.O(\Q_reg[27] [24]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1
(.I0(Q[25]),
.I1(\Q_reg[30]_0 [25]),
.I2(CO),
.O(\Q_reg[30] [25]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1__0
(.I0(\Q_reg[30]_0 [25]),
.I1(Q[25]),
.I2(CO),
.O(\Q_reg[27] [25]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hAC))
\Q[26]_i_1
(.I0(Q[26]),
.I1(\Q_reg[30]_0 [26]),
.I2(CO),
.O(\Q_reg[30] [26]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hAC))
\Q[26]_i_1__0
(.I0(\Q_reg[30]_0 [26]),
.I1(Q[26]),
.I2(CO),
.O(\Q_reg[27] [26]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hAC))
\Q[27]_i_1
(.I0(Q[27]),
.I1(\Q_reg[30]_0 [27]),
.I2(CO),
.O(\Q_reg[30] [27]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hAC))
\Q[27]_i_1__0
(.I0(\Q_reg[30]_0 [27]),
.I1(Q[27]),
.I2(CO),
.O(\Q_reg[27] [27]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hAC))
\Q[28]_i_1
(.I0(Q[28]),
.I1(\Q_reg[30]_0 [28]),
.I2(CO),
.O(\Q_reg[30] [28]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hAC))
\Q[29]_i_1
(.I0(Q[29]),
.I1(\Q_reg[30]_0 [29]),
.I2(CO),
.O(\Q_reg[30] [29]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1
(.I0(Q[2]),
.I1(\Q_reg[30]_0 [2]),
.I2(CO),
.O(\Q_reg[30] [2]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1__0
(.I0(\Q_reg[30]_0 [2]),
.I1(Q[2]),
.I2(CO),
.O(\Q_reg[27] [2]));
LUT3 #(
.INIT(8'hAC))
\Q[30]_i_1
(.I0(Q[30]),
.I1(\Q_reg[30]_0 [30]),
.I2(CO),
.O(\Q_reg[30] [30]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1
(.I0(Q[3]),
.I1(\Q_reg[30]_0 [3]),
.I2(CO),
.O(\Q_reg[30] [3]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1__0
(.I0(\Q_reg[30]_0 [3]),
.I1(Q[3]),
.I2(CO),
.O(\Q_reg[27] [3]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1
(.I0(Q[4]),
.I1(\Q_reg[30]_0 [4]),
.I2(CO),
.O(\Q_reg[30] [4]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1__0
(.I0(\Q_reg[30]_0 [4]),
.I1(Q[4]),
.I2(CO),
.O(\Q_reg[27] [4]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1
(.I0(Q[5]),
.I1(\Q_reg[30]_0 [5]),
.I2(CO),
.O(\Q_reg[30] [5]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1__0
(.I0(\Q_reg[30]_0 [5]),
.I1(Q[5]),
.I2(CO),
.O(\Q_reg[27] [5]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1
(.I0(Q[6]),
.I1(\Q_reg[30]_0 [6]),
.I2(CO),
.O(\Q_reg[30] [6]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1__0
(.I0(\Q_reg[30]_0 [6]),
.I1(Q[6]),
.I2(CO),
.O(\Q_reg[27] [6]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1
(.I0(Q[7]),
.I1(\Q_reg[30]_0 [7]),
.I2(CO),
.O(\Q_reg[30] [7]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1__0
(.I0(\Q_reg[30]_0 [7]),
.I1(Q[7]),
.I2(CO),
.O(\Q_reg[27] [7]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1
(.I0(Q[8]),
.I1(\Q_reg[30]_0 [8]),
.I2(CO),
.O(\Q_reg[30] [8]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1__0
(.I0(\Q_reg[30]_0 [8]),
.I1(Q[8]),
.I2(CO),
.O(\Q_reg[27] [8]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1
(.I0(Q[9]),
.I1(\Q_reg[30]_0 [9]),
.I2(CO),
.O(\Q_reg[30] [9]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1__0
(.I0(\Q_reg[30]_0 [9]),
.I1(Q[9]),
.I2(CO),
.O(\Q_reg[27] [9]));
endmodule
module RegisterAdd
(UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[31]_0 ,
exp_rslt_NRM2_EW1,
Q,
D,
CLK,
AR);
output UNDRFLW_FLAG_FRMT;
output OVRFLW_FLAG_FRMT;
output [31:0]\Q_reg[31]_0 ;
input [8:0]exp_rslt_NRM2_EW1;
input [0:0]Q;
input [31:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [31:0]D;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire \Q[1]_i_2__1_n_0 ;
wire \Q[2]_i_2__0_n_0 ;
wire [31:0]\Q_reg[31]_0 ;
wire UNDRFLW_FLAG_FRMT;
wire [8:0]exp_rslt_NRM2_EW1;
LUT5 #(
.INIT(32'h00000001))
\Q[1]_i_1__9
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(exp_rslt_NRM2_EW1[6]),
.I2(exp_rslt_NRM2_EW1[8]),
.I3(exp_rslt_NRM2_EW1[7]),
.I4(\Q[1]_i_2__1_n_0 ),
.O(UNDRFLW_FLAG_FRMT));
LUT5 #(
.INIT(32'hFFFFFFFE))
\Q[1]_i_2__1
(.I0(exp_rslt_NRM2_EW1[2]),
.I1(exp_rslt_NRM2_EW1[0]),
.I2(exp_rslt_NRM2_EW1[1]),
.I3(exp_rslt_NRM2_EW1[4]),
.I4(exp_rslt_NRM2_EW1[3]),
.O(\Q[1]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hEAAAAAAAAAAAAAAA))
\Q[2]_i_1__7
(.I0(exp_rslt_NRM2_EW1[8]),
.I1(\Q[2]_i_2__0_n_0 ),
.I2(exp_rslt_NRM2_EW1[1]),
.I3(exp_rslt_NRM2_EW1[0]),
.I4(exp_rslt_NRM2_EW1[3]),
.I5(exp_rslt_NRM2_EW1[2]),
.O(OVRFLW_FLAG_FRMT));
LUT4 #(
.INIT(16'h8000))
\Q[2]_i_2__0
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(exp_rslt_NRM2_EW1[4]),
.I2(exp_rslt_NRM2_EW1[6]),
.I3(exp_rslt_NRM2_EW1[7]),
.O(\Q[2]_i_2__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[0]),
.Q(\Q_reg[31]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[10]),
.Q(\Q_reg[31]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[11]),
.Q(\Q_reg[31]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[12]),
.Q(\Q_reg[31]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[13]),
.Q(\Q_reg[31]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[14]),
.Q(\Q_reg[31]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[15]),
.Q(\Q_reg[31]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[16]),
.Q(\Q_reg[31]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[17]),
.Q(\Q_reg[31]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[18]),
.Q(\Q_reg[31]_0 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[19]),
.Q(\Q_reg[31]_0 [19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[1]),
.Q(\Q_reg[31]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[20]),
.Q(\Q_reg[31]_0 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[21]),
.Q(\Q_reg[31]_0 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[22]),
.Q(\Q_reg[31]_0 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[23]),
.Q(\Q_reg[31]_0 [23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[24]),
.Q(\Q_reg[31]_0 [24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[25]),
.Q(\Q_reg[31]_0 [25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[26]),
.Q(\Q_reg[31]_0 [26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[27]),
.Q(\Q_reg[31]_0 [27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[28]),
.Q(\Q_reg[31]_0 [28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[29]),
.Q(\Q_reg[31]_0 [29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[2]),
.Q(\Q_reg[31]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[30]),
.Q(\Q_reg[31]_0 [30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[31]),
.Q(\Q_reg[31]_0 [31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[3]),
.Q(\Q_reg[31]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[4]),
.Q(\Q_reg[31]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[5]),
.Q(\Q_reg[31]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[6]),
.Q(\Q_reg[31]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[7]),
.Q(\Q_reg[31]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[8]),
.Q(\Q_reg[31]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[9]),
.Q(\Q_reg[31]_0 [9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_1
(DI,
Q,
\Q_reg[2]_0 ,
S,
\Q_reg[2]_1 ,
\Q_reg[2]_2 ,
\Q_reg[2]_3 ,
\Q_reg[2]_4 ,
\Q_reg[2]_5 ,
\Q_reg[2]_6 ,
\Q_reg[2]_7 ,
\Q_reg[2]_8 ,
D,
\Q_reg[31]_0 ,
intAS,
E,
\Q_reg[31]_1 ,
CLK,
\FSM_sequential_state_reg_reg[1] ,
AR);
output [3:0]DI;
output [31:0]Q;
output [3:0]\Q_reg[2]_0 ;
output [3:0]S;
output [3:0]\Q_reg[2]_1 ;
output [3:0]\Q_reg[2]_2 ;
output [3:0]\Q_reg[2]_3 ;
output [3:0]\Q_reg[2]_4 ;
output [3:0]\Q_reg[2]_5 ;
output [3:0]\Q_reg[2]_6 ;
output [2:0]\Q_reg[2]_7 ;
output [1:0]\Q_reg[2]_8 ;
output [0:0]D;
input [31:0]\Q_reg[31]_0 ;
input intAS;
input [0:0]E;
input [31:0]\Q_reg[31]_1 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [3:0]DI;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [3:0]\Q_reg[2]_0 ;
wire [3:0]\Q_reg[2]_1 ;
wire [3:0]\Q_reg[2]_2 ;
wire [3:0]\Q_reg[2]_3 ;
wire [3:0]\Q_reg[2]_4 ;
wire [3:0]\Q_reg[2]_5 ;
wire [3:0]\Q_reg[2]_6 ;
wire [2:0]\Q_reg[2]_7 ;
wire [1:0]\Q_reg[2]_8 ;
wire [31:0]\Q_reg[31]_0 ;
wire [31:0]\Q_reg[31]_1 ;
wire [3:0]S;
wire intAS;
LUT3 #(
.INIT(8'h96))
\Q[1]_i_1__8
(.I0(Q[31]),
.I1(\Q_reg[31]_0 [31]),
.I2(intAS),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_1 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [9]),
.Q(Q[9]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_1
(.I0(Q[21]),
.I1(\Q_reg[31]_0 [21]),
.I2(\Q_reg[31]_0 [23]),
.I3(Q[23]),
.I4(\Q_reg[31]_0 [22]),
.I5(Q[22]),
.O(\Q_reg[2]_5 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_2
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(\Q_reg[31]_0 [20]),
.I3(Q[20]),
.I4(\Q_reg[31]_0 [19]),
.I5(Q[19]),
.O(\Q_reg[2]_5 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_3
(.I0(Q[15]),
.I1(\Q_reg[31]_0 [15]),
.I2(\Q_reg[31]_0 [17]),
.I3(Q[17]),
.I4(\Q_reg[31]_0 [16]),
.I5(Q[16]),
.O(\Q_reg[2]_5 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_4
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(\Q_reg[31]_0 [14]),
.I3(Q[14]),
.I4(\Q_reg[31]_0 [13]),
.I5(Q[13]),
.O(\Q_reg[2]_5 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_2
(.I0(Q[27]),
.I1(\Q_reg[31]_0 [27]),
.I2(\Q_reg[31]_0 [29]),
.I3(Q[29]),
.I4(\Q_reg[31]_0 [28]),
.I5(Q[28]),
.O(\Q_reg[2]_8 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_3
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(\Q_reg[31]_0 [26]),
.I3(Q[26]),
.I4(\Q_reg[31]_0 [25]),
.I5(Q[25]),
.O(\Q_reg[2]_8 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_1
(.I0(Q[9]),
.I1(\Q_reg[31]_0 [9]),
.I2(\Q_reg[31]_0 [11]),
.I3(Q[11]),
.I4(\Q_reg[31]_0 [10]),
.I5(Q[10]),
.O(\Q_reg[2]_3 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_2
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(\Q_reg[31]_0 [8]),
.I3(Q[8]),
.I4(\Q_reg[31]_0 [7]),
.I5(Q[7]),
.O(\Q_reg[2]_3 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_3
(.I0(Q[3]),
.I1(\Q_reg[31]_0 [3]),
.I2(\Q_reg[31]_0 [5]),
.I3(Q[5]),
.I4(\Q_reg[31]_0 [4]),
.I5(Q[4]),
.O(\Q_reg[2]_3 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(\Q_reg[31]_0 [2]),
.I3(Q[2]),
.I4(\Q_reg[31]_0 [1]),
.I5(Q[1]),
.O(\Q_reg[2]_3 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_1
(.I0(Q[14]),
.I1(\Q_reg[31]_0 [14]),
.I2(\Q_reg[31]_0 [15]),
.I3(Q[15]),
.O(\Q_reg[2]_1 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_2
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(\Q_reg[31]_0 [13]),
.I3(Q[13]),
.O(\Q_reg[2]_1 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_3
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(\Q_reg[31]_0 [11]),
.I3(Q[11]),
.O(\Q_reg[2]_1 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_4
(.I0(Q[8]),
.I1(\Q_reg[31]_0 [8]),
.I2(\Q_reg[31]_0 [9]),
.I3(Q[9]),
.O(\Q_reg[2]_1 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_5
(.I0(Q[14]),
.I1(\Q_reg[31]_0 [14]),
.I2(Q[15]),
.I3(\Q_reg[31]_0 [15]),
.O(\Q_reg[2]_2 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_6
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(Q[13]),
.I3(\Q_reg[31]_0 [13]),
.O(\Q_reg[2]_2 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_7
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(Q[11]),
.I3(\Q_reg[31]_0 [11]),
.O(\Q_reg[2]_2 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_8
(.I0(Q[8]),
.I1(\Q_reg[31]_0 [8]),
.I2(Q[9]),
.I3(\Q_reg[31]_0 [9]),
.O(\Q_reg[2]_2 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_1
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(\Q_reg[31]_0 [23]),
.I3(Q[23]),
.O(\Q_reg[2]_4 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_2
(.I0(Q[20]),
.I1(\Q_reg[31]_0 [20]),
.I2(\Q_reg[31]_0 [21]),
.I3(Q[21]),
.O(\Q_reg[2]_4 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_3
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(\Q_reg[31]_0 [19]),
.I3(Q[19]),
.O(\Q_reg[2]_4 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_4
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(\Q_reg[31]_0 [17]),
.I3(Q[17]),
.O(\Q_reg[2]_4 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_5
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(Q[23]),
.I3(\Q_reg[31]_0 [23]),
.O(\Q_reg[2]_6 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_6
(.I0(Q[20]),
.I1(\Q_reg[31]_0 [20]),
.I2(Q[21]),
.I3(\Q_reg[31]_0 [21]),
.O(\Q_reg[2]_6 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_7
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(Q[19]),
.I3(\Q_reg[31]_0 [19]),
.O(\Q_reg[2]_6 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_8
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(Q[17]),
.I3(\Q_reg[31]_0 [17]),
.O(\Q_reg[2]_6 [0]));
LUT2 #(
.INIT(4'h2))
gtXY_o_carry__2_i_1
(.I0(Q[30]),
.I1(\Q_reg[31]_0 [30]),
.O(DI[3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_2
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(\Q_reg[31]_0 [29]),
.I3(Q[29]),
.O(DI[2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_3
(.I0(Q[26]),
.I1(\Q_reg[31]_0 [26]),
.I2(\Q_reg[31]_0 [27]),
.I3(Q[27]),
.O(DI[1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_4
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(\Q_reg[31]_0 [25]),
.I3(Q[25]),
.O(DI[0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_6
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(Q[29]),
.I3(\Q_reg[31]_0 [29]),
.O(\Q_reg[2]_7 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_7
(.I0(Q[26]),
.I1(\Q_reg[31]_0 [26]),
.I2(Q[27]),
.I3(\Q_reg[31]_0 [27]),
.O(\Q_reg[2]_7 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_8
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(Q[25]),
.I3(\Q_reg[31]_0 [25]),
.O(\Q_reg[2]_7 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_1
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(\Q_reg[31]_0 [7]),
.I3(Q[7]),
.O(\Q_reg[2]_0 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_2
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(\Q_reg[31]_0 [5]),
.I3(Q[5]),
.O(\Q_reg[2]_0 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_3
(.I0(Q[2]),
.I1(\Q_reg[31]_0 [2]),
.I2(\Q_reg[31]_0 [3]),
.I3(Q[3]),
.O(\Q_reg[2]_0 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(\Q_reg[31]_0 [1]),
.I3(Q[1]),
.O(\Q_reg[2]_0 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_5
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(Q[7]),
.I3(\Q_reg[31]_0 [7]),
.O(S[3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_6
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(Q[5]),
.I3(\Q_reg[31]_0 [5]),
.O(S[2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_7
(.I0(Q[2]),
.I1(\Q_reg[31]_0 [2]),
.I2(Q[3]),
.I3(\Q_reg[31]_0 [3]),
.O(S[1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_8
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(Q[1]),
.I3(\Q_reg[31]_0 [1]),
.O(S[0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_2
(S,
Q,
\Q_reg[2]_0 ,
\Q_reg[30]_0 ,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [0:0]S;
output [31:0]Q;
output [0:0]\Q_reg[2]_0 ;
input [0:0]\Q_reg[30]_0 ;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [0:0]\Q_reg[2]_0 ;
wire [0:0]\Q_reg[30]_0 ;
wire [0:0]S;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
LUT2 #(
.INIT(4'h9))
eqXY_o_carry__1_i_1
(.I0(Q[30]),
.I1(\Q_reg[30]_0 ),
.O(S));
LUT2 #(
.INIT(4'h9))
gtXY_o_carry__2_i_5
(.I0(Q[30]),
.I1(\Q_reg[30]_0 ),
.O(\Q_reg[2]_0 ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized0
(intAS,
D,
E,
op_add_subt,
CLK,
\FSM_sequential_state_reg_reg[1] ,
Q,
\Q_reg[31] ,
CO);
output intAS;
output [0:0]D;
input [0:0]E;
input op_add_subt;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [0:0]Q;
input [0:0]\Q_reg[31] ;
input [0:0]CO;
wire CLK;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [0:0]Q;
wire [0:0]\Q_reg[31] ;
wire intAS;
wire op_add_subt;
LUT4 #(
.INIT(16'h9600))
\Q[0]_i_1__10
(.I0(intAS),
.I1(Q),
.I2(\Q_reg[31] ),
.I3(CO),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(op_add_subt),
.Q(intAS));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized1
(D,
Q,
\Q_reg[25]_0 ,
\Q_reg[6]_0 ,
\Q_reg[30]_0 ,
CLK,
AR);
output [1:0]D;
output [30:0]Q;
input [2:0]\Q_reg[25]_0 ;
input [0:0]\Q_reg[6]_0 ;
input [30:0]\Q_reg[30]_0 ;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [1:0]D;
wire [30:0]Q;
wire [2:0]\Q_reg[25]_0 ;
wire [30:0]\Q_reg[30]_0 ;
wire [0:0]\Q_reg[6]_0 ;
LUT2 #(
.INIT(4'h6))
\Q[0]_i_1__11
(.I0(Q[23]),
.I1(\Q_reg[25]_0 [0]),
.O(D[0]));
LUT6 #(
.INIT(64'h4F04B0FBB0FB4F04))
\Q[2]_i_1__9
(.I0(Q[23]),
.I1(\Q_reg[25]_0 [0]),
.I2(Q[24]),
.I3(\Q_reg[25]_0 [1]),
.I4(\Q_reg[25]_0 [2]),
.I5(Q[25]),
.O(D[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized10
(D,
\Q_reg[25] ,
\Q_reg[23] ,
\Q_reg[16] ,
\Q_reg[4]_0 ,
Q,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[0] ,
\Q_reg[25]_0 ,
\Data_array_SWR[4]_5 ,
E,
\Q_reg[4]_1 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [13:0]D;
output [5:0]\Q_reg[25] ;
output [14:0]\Q_reg[23] ;
output [2:0]\Q_reg[16] ;
input [0:0]\Q_reg[4]_0 ;
input [1:0]Q;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [9:0]\Q_reg[0] ;
input [7:0]\Q_reg[25]_0 ;
input [1:0]\Data_array_SWR[4]_5 ;
input [0:0]E;
input [2:0]\Q_reg[4]_1 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [13:0]D;
wire [1:0]\Data_array_SWR[4]_5 ;
wire [21:18]\Data_array_SWR[5]_3 ;
wire [23:2]\Data_array_SWR[6]_4 ;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [9:0]\Q_reg[0] ;
wire [2:0]\Q_reg[16] ;
wire [14:0]\Q_reg[23] ;
wire [5:0]\Q_reg[25] ;
wire [7:0]\Q_reg[25]_0 ;
wire [0:0]\Q_reg[4]_0 ;
wire [2:0]\Q_reg[4]_1 ;
wire UNDRFLW_FLAG_FRMT;
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[0]_i_1__12
(.I0(\Data_array_SWR[6]_4 [23]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [2]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[0]));
LUT6 #(
.INIT(64'hCDC8DDDDCDC88888))
\Q[12]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [1]),
.I5(\Data_array_SWR[4]_5 [0]),
.O(\Q_reg[25] [2]));
LUT6 #(
.INIT(64'hCDC8DDDDCDC88888))
\Q[13]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [1]),
.I5(\Data_array_SWR[4]_5 [1]),
.O(\Q_reg[25] [3]));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'h02))
\Q[14]_i_1__7
(.I0(\Q_reg[23] [7]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'h02))
\Q[15]_i_1__6
(.I0(\Q_reg[23] [8]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[7]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[16]_i_1__6
(.I0(\Q_reg[25] [1]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[16] [2]),
.I4(\Q_reg[0] [8]),
.O(\Q_reg[23] [7]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[16]_i_1__8
(.I0(\Data_array_SWR[6]_4 [7]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [18]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[8]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[16]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [5]),
.O(\Data_array_SWR[6]_4 [7]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[16]_i_2__1
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [7]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [7]),
.O(\Q_reg[25] [1]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[16]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [0]),
.O(\Data_array_SWR[6]_4 [18]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[17]_i_1__6
(.I0(\Q_reg[25] [0]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[16] [2]),
.I4(\Q_reg[0] [9]),
.O(\Q_reg[23] [8]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[17]_i_1__7
(.I0(\Data_array_SWR[6]_4 [6]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [19]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[9]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[17]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [4]),
.O(\Data_array_SWR[6]_4 [6]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[17]_i_2__1
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [6]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [6]),
.O(\Q_reg[25] [0]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[17]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [1]),
.O(\Data_array_SWR[6]_4 [19]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_1__6
(.I0(\Data_array_SWR[6]_4 [7]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [18]),
.O(\Q_reg[23] [9]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[18]_i_1__8
(.I0(\Data_array_SWR[6]_4 [5]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [20]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_2__0
(.I0(\Data_array_SWR[5]_3 [21]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [3]),
.O(\Data_array_SWR[6]_4 [5]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[18]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [6]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [2]),
.O(\Data_array_SWR[6]_4 [20]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[18]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [7]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [3]),
.O(\Data_array_SWR[5]_3 [21]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_1__6
(.I0(\Data_array_SWR[6]_4 [6]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [19]),
.O(\Q_reg[23] [10]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[19]_i_1__7
(.I0(\Data_array_SWR[6]_4 [4]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [21]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_2__0
(.I0(\Data_array_SWR[5]_3 [20]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [2]),
.O(\Data_array_SWR[6]_4 [4]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[19]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [7]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [3]),
.O(\Data_array_SWR[6]_4 [21]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[19]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [6]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [2]),
.O(\Data_array_SWR[5]_3 [20]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\Q[1]_i_1__10
(.I0(\Q_reg[25] [4]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 ),
.O(\Q_reg[23] [0]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[1]_i_1__13
(.I0(\Data_array_SWR[6]_4 [22]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [3]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_1__6
(.I0(\Data_array_SWR[6]_4 [5]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [20]),
.O(\Q_reg[23] [11]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[20]_i_1__8
(.I0(\Data_array_SWR[6]_4 [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [22]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_2__0
(.I0(\Data_array_SWR[5]_3 [19]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [1]),
.O(\Data_array_SWR[6]_4 [3]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[20]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [4]),
.O(\Data_array_SWR[6]_4 [22]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[20]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [5]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [1]),
.O(\Data_array_SWR[5]_3 [19]));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_1__7
(.I0(\Data_array_SWR[6]_4 [4]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [21]),
.O(\Q_reg[23] [12]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[21]_i_1__8
(.I0(\Data_array_SWR[6]_4 [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [23]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_2__0
(.I0(\Data_array_SWR[5]_3 [18]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [0]),
.O(\Data_array_SWR[6]_4 [2]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[21]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [5]),
.O(\Data_array_SWR[6]_4 [23]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[21]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [4]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [0]),
.O(\Data_array_SWR[5]_3 [18]));
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_1__7
(.I0(\Data_array_SWR[6]_4 [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [22]),
.O(\Q_reg[23] [13]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[22]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [6]),
.O(\Q_reg[25] [4]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\Q[23]_i_1__7
(.I0(\Data_array_SWR[6]_4 [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [23]),
.O(\Q_reg[23] [14]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[25]_i_4__0
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [7]),
.O(\Q_reg[25] [5]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[2]_i_1__12
(.I0(\Data_array_SWR[6]_4 [21]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [4]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\Q[2]_i_1__8
(.I0(\Data_array_SWR[6]_4 [23]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [2]),
.O(\Q_reg[23] [1]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_1__7
(.I0(\Data_array_SWR[6]_4 [22]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [3]),
.O(\Q_reg[23] [2]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[3]_i_1__9
(.I0(\Data_array_SWR[6]_4 [20]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [5]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[4]_i_1__10
(.I0(\Data_array_SWR[6]_4 [19]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [6]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\Q[4]_i_1__8
(.I0(\Data_array_SWR[6]_4 [21]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [4]),
.O(\Q_reg[23] [3]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\Q[5]_i_1__6
(.I0(\Data_array_SWR[6]_4 [20]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [5]),
.O(\Q_reg[23] [4]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[5]_i_1__7
(.I0(\Data_array_SWR[6]_4 [18]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [7]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\Q[6]_i_1__9
(.I0(\Data_array_SWR[6]_4 [19]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [6]),
.O(\Q_reg[23] [5]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\Q[7]_i_1__7
(.I0(\Data_array_SWR[6]_4 [18]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [7]),
.O(\Q_reg[23] [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[4]_1 [0]),
.Q(\Q_reg[16] [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[4]_1 [1]),
.Q(\Q_reg[16] [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[4]_1 [2]),
.Q(\Q_reg[16] [2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized11
(D,
Q,
\Q_reg[15] ,
\Q_reg[4] ,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[4]_0 ,
\Q_reg[0]_0 ,
E,
\Q_reg[1]_0 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [5:0]D;
output [1:0]Q;
output [5:0]\Q_reg[15] ;
input [3:0]\Q_reg[4] ;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [0:0]\Q_reg[4]_0 ;
input [3:0]\Q_reg[0]_0 ;
input [0:0]E;
input [1:0]\Q_reg[1]_0 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [5:0]D;
wire [11:10]\Data_array_SWR[6]_4 ;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [3:0]\Q_reg[0]_0 ;
wire [5:0]\Q_reg[15] ;
wire [1:0]\Q_reg[1]_0 ;
wire [3:0]\Q_reg[4] ;
wire [0:0]\Q_reg[4]_0 ;
wire UNDRFLW_FLAG_FRMT;
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\Q[10]_i_1__9
(.I0(\Q_reg[4] [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [10]),
.O(\Q_reg[15] [2]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\Q[11]_i_1__9
(.I0(\Q_reg[4] [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [11]),
.O(\Q_reg[15] [3]));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[12]_i_1__9
(.I0(\Data_array_SWR[6]_4 [11]),
.I1(Q[1]),
.I2(\Q_reg[4] [2]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_2__1
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [1]),
.O(\Data_array_SWR[6]_4 [11]));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[13]_i_1__7
(.I0(\Data_array_SWR[6]_4 [10]),
.I1(Q[1]),
.I2(\Q_reg[4] [3]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [0]),
.O(\Data_array_SWR[6]_4 [10]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_1__8
(.I0(\Data_array_SWR[6]_4 [11]),
.I1(Q[1]),
.I2(\Q_reg[4] [2]),
.O(\Q_reg[15] [4]));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_1__7
(.I0(\Data_array_SWR[6]_4 [10]),
.I1(Q[1]),
.I2(\Q_reg[4] [3]),
.O(\Q_reg[15] [5]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'h02))
\Q[6]_i_1__8
(.I0(\Q_reg[15] [0]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'h02))
\Q[7]_i_1__6
(.I0(\Q_reg[15] [1]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\Q[8]_i_1__8
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [3]),
.I3(Q[1]),
.I4(\Q_reg[4] [0]),
.O(\Q_reg[15] [0]));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[8]_i_1__9
(.I0(\Q_reg[4] [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [10]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[2]));
LUT5 #(
.INIT(32'hB8FFB800))
\Q[9]_i_1__8
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [2]),
.I3(Q[1]),
.I4(\Q_reg[4] [1]),
.O(\Q_reg[15] [1]));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[9]_i_1__9
(.I0(\Q_reg[4] [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_4 [11]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[1]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[1]_0 [1]),
.Q(Q[1]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized12
(Q,
\Q_reg[4] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[4] ;
input [2:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[4] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR[0]),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized13
(S,
\Q_reg[30] ,
\Q_reg[30]_0 ,
D,
\Q_reg[1]_0 ,
Q,
exp_rslt_NRM2_EW1,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[1]_1 ,
\Q_reg[1]_2 ,
CLK,
AR);
output [3:0]S;
output [3:0]\Q_reg[30] ;
output [6:0]\Q_reg[30]_0 ;
output [7:0]D;
output [0:0]\Q_reg[1]_0 ;
input [0:0]Q;
input [7:0]exp_rslt_NRM2_EW1;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [0:0]\Q_reg[1]_1 ;
input [12:0]\Q_reg[1]_2 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [7:0]D;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire [0:0]\Q_reg[1]_0 ;
wire [0:0]\Q_reg[1]_1 ;
wire [12:0]\Q_reg[1]_2 ;
wire [3:0]\Q_reg[30] ;
wire [6:0]\Q_reg[30]_0 ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
wire [3:0]S;
wire UNDRFLW_FLAG_FRMT;
wire [7:0]exp_rslt_NRM2_EW1;
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hFE))
\Q[23]_i_1__6
(.I0(exp_rslt_NRM2_EW1[0]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hFE))
\Q[24]_i_1__7
(.I0(exp_rslt_NRM2_EW1[1]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hFE))
\Q[25]_i_1__7
(.I0(exp_rslt_NRM2_EW1[2]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hFE))
\Q[26]_i_1__6
(.I0(exp_rslt_NRM2_EW1[3]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hFE))
\Q[27]_i_1__5
(.I0(exp_rslt_NRM2_EW1[4]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hFE))
\Q[28]_i_1__5
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hFE))
\Q[29]_i_1__6
(.I0(exp_rslt_NRM2_EW1[6]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hFE))
\Q[30]_i_1__5
(.I0(exp_rslt_NRM2_EW1[7]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [0]),
.Q(\Q_reg[30]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [1]),
.Q(\Q_reg[30]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [2]),
.Q(\Q_reg[30]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [3]),
.Q(\Q_reg[30]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [4]),
.Q(\Q_reg[30]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [5]),
.Q(\Q_reg[30]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [6]),
.Q(\Q_reg[30]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [9]),
.Q(\Q_reg_n_0_[9] ));
LUT2 #(
.INIT(4'h9))
_inferred__1_carry__0_i_1
(.I0(\Q_reg[30]_0 [6]),
.I1(\Q_reg_n_0_[7] ),
.O(\Q_reg[30] [3]));
LUT2 #(
.INIT(4'h9))
_inferred__1_carry__0_i_2
(.I0(\Q_reg[30]_0 [5]),
.I1(\Q_reg[30]_0 [6]),
.O(\Q_reg[30] [2]));
LUT2 #(
.INIT(4'h9))
_inferred__1_carry__0_i_3
(.I0(\Q_reg[30]_0 [5]),
.I1(Q),
.O(\Q_reg[30] [1]));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry__0_i_4
(.I0(Q),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q_reg[30]_0 [4]),
.O(\Q_reg[30] [0]));
LUT1 #(
.INIT(2'h1))
_inferred__1_carry__1_i_1
(.I0(\Q_reg_n_0_[7] ),
.O(\Q_reg[1]_0 ));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry_i_2
(.I0(Q),
.I1(\Q_reg_n_0_[11] ),
.I2(\Q_reg[30]_0 [3]),
.O(S[3]));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry_i_3
(.I0(Q),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg[30]_0 [2]),
.O(S[2]));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry_i_4
(.I0(Q),
.I1(\Q_reg_n_0_[9] ),
.I2(\Q_reg[30]_0 [1]),
.O(S[1]));
LUT2 #(
.INIT(4'hE))
_inferred__1_carry_i_5
(.I0(\Q_reg_n_0_[8] ),
.I1(Q),
.O(S[0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized14
(D,
DI,
Q,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[1]_0 ,
\Q_reg[2]_0 ,
CLK,
AR);
output [0:0]D;
output [0:0]DI;
output [1:0]Q;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [0:0]\Q_reg[1]_0 ;
input [2:0]\Q_reg[2]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]DI;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [0:0]\Q_reg[1]_0 ;
wire [2:0]\Q_reg[2]_0 ;
wire SIGN_FLAG_SHT1SHT2;
wire UNDRFLW_FLAG_FRMT;
LUT3 #(
.INIT(8'h0E))
\Q[31]_i_1__6
(.I0(UNDRFLW_FLAG_FRMT),
.I1(SIGN_FLAG_SHT1SHT2),
.I2(OVRFLW_FLAG_FRMT),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[2]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[2]_0 [1]),
.Q(SIGN_FLAG_SHT1SHT2));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[2]_0 [2]),
.Q(Q[1]));
LUT1 #(
.INIT(2'h1))
_inferred__1_carry_i_1
(.I0(Q[1]),
.O(DI));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized15
(O,
Q,
\Q_reg[8]_0 ,
\Q_reg[12]_0 ,
\Q_reg[16]_0 ,
\Q_reg[20]_0 ,
CO,
\Q_reg[24]_0 ,
S,
\Q_reg[6]_0 ,
\Q_reg[10]_0 ,
\Q_reg[14]_0 ,
\Q_reg[18]_0 ,
\Q_reg[22]_0 ,
E,
\Q_reg[30]_0 ,
CLK,
AR);
output [3:0]O;
output [30:0]Q;
output [3:0]\Q_reg[8]_0 ;
output [3:0]\Q_reg[12]_0 ;
output [3:0]\Q_reg[16]_0 ;
output [3:0]\Q_reg[20]_0 ;
output [0:0]CO;
output [3:0]\Q_reg[24]_0 ;
input [3:0]S;
input [3:0]\Q_reg[6]_0 ;
input [3:0]\Q_reg[10]_0 ;
input [3:0]\Q_reg[14]_0 ;
input [3:0]\Q_reg[18]_0 ;
input [3:0]\Q_reg[22]_0 ;
input [0:0]E;
input [30:0]\Q_reg[30]_0 ;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire [3:0]O;
wire [30:0]Q;
wire [3:0]\Q_reg[10]_0 ;
wire [3:0]\Q_reg[12]_0 ;
wire \Q_reg[12]_i_3_n_0 ;
wire \Q_reg[12]_i_3_n_1 ;
wire \Q_reg[12]_i_3_n_2 ;
wire \Q_reg[12]_i_3_n_3 ;
wire [3:0]\Q_reg[14]_0 ;
wire [3:0]\Q_reg[16]_0 ;
wire \Q_reg[16]_i_3_n_0 ;
wire \Q_reg[16]_i_3_n_1 ;
wire \Q_reg[16]_i_3_n_2 ;
wire \Q_reg[16]_i_3_n_3 ;
wire [3:0]\Q_reg[18]_0 ;
wire [3:0]\Q_reg[20]_0 ;
wire \Q_reg[20]_i_3_n_0 ;
wire \Q_reg[20]_i_3_n_1 ;
wire \Q_reg[20]_i_3_n_2 ;
wire \Q_reg[20]_i_3_n_3 ;
wire [3:0]\Q_reg[22]_0 ;
wire [3:0]\Q_reg[24]_0 ;
wire \Q_reg[24]_i_3_n_1 ;
wire \Q_reg[24]_i_3_n_2 ;
wire \Q_reg[24]_i_3_n_3 ;
wire [30:0]\Q_reg[30]_0 ;
wire \Q_reg[4]_i_3_n_0 ;
wire \Q_reg[4]_i_3_n_1 ;
wire \Q_reg[4]_i_3_n_2 ;
wire \Q_reg[4]_i_3_n_3 ;
wire [3:0]\Q_reg[6]_0 ;
wire [3:0]\Q_reg[8]_0 ;
wire \Q_reg[8]_i_3_n_0 ;
wire \Q_reg[8]_i_3_n_1 ;
wire \Q_reg[8]_i_3_n_2 ;
wire \Q_reg[8]_i_3_n_3 ;
wire [3:0]S;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [12]),
.Q(Q[12]));
CARRY4 \Q_reg[12]_i_3
(.CI(\Q_reg[8]_i_3_n_0 ),
.CO({\Q_reg[12]_i_3_n_0 ,\Q_reg[12]_i_3_n_1 ,\Q_reg[12]_i_3_n_2 ,\Q_reg[12]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[10:7]),
.O(\Q_reg[12]_0 ),
.S(\Q_reg[10]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [16]),
.Q(Q[16]));
CARRY4 \Q_reg[16]_i_3
(.CI(\Q_reg[12]_i_3_n_0 ),
.CO({\Q_reg[16]_i_3_n_0 ,\Q_reg[16]_i_3_n_1 ,\Q_reg[16]_i_3_n_2 ,\Q_reg[16]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[14:11]),
.O(\Q_reg[16]_0 ),
.S(\Q_reg[14]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [20]),
.Q(Q[20]));
CARRY4 \Q_reg[20]_i_3
(.CI(\Q_reg[16]_i_3_n_0 ),
.CO({\Q_reg[20]_i_3_n_0 ,\Q_reg[20]_i_3_n_1 ,\Q_reg[20]_i_3_n_2 ,\Q_reg[20]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[18:15]),
.O(\Q_reg[20]_0 ),
.S(\Q_reg[18]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [24]),
.Q(Q[24]));
CARRY4 \Q_reg[24]_i_3
(.CI(\Q_reg[20]_i_3_n_0 ),
.CO({CO,\Q_reg[24]_i_3_n_1 ,\Q_reg[24]_i_3_n_2 ,\Q_reg[24]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[22:19]),
.O(\Q_reg[24]_0 ),
.S(\Q_reg[22]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [4]),
.Q(Q[4]));
CARRY4 \Q_reg[4]_i_3
(.CI(1'b0),
.CO({\Q_reg[4]_i_3_n_0 ,\Q_reg[4]_i_3_n_1 ,\Q_reg[4]_i_3_n_2 ,\Q_reg[4]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({Q[2:0],1'b0}),
.O(O),
.S(S));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [8]),
.Q(Q[8]));
CARRY4 \Q_reg[8]_i_3
(.CI(\Q_reg[4]_i_3_n_0 ),
.CO({\Q_reg[8]_i_3_n_0 ,\Q_reg[8]_i_3_n_1 ,\Q_reg[8]_i_3_n_2 ,\Q_reg[8]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[6:3]),
.O(\Q_reg[8]_0 ),
.S(\Q_reg[6]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized16
(Q,
S,
O,
\Q_reg[8]_0 ,
\Q_reg[12]_0 ,
\Q_reg[16]_0 ,
\Q_reg[20]_0 ,
\Q_reg[24]_0 ,
\Q_reg[25]_0 ,
CO,
\Q_reg[25]_1 ,
\Q_reg[22]_0 ,
\Q_reg[22]_1 ,
E,
D,
CLK,
AR);
output [23:0]Q;
output [0:0]S;
output [3:0]O;
output [3:0]\Q_reg[8]_0 ;
output [3:0]\Q_reg[12]_0 ;
output [3:0]\Q_reg[16]_0 ;
output [3:0]\Q_reg[20]_0 ;
output [3:0]\Q_reg[24]_0 ;
output [0:0]\Q_reg[25]_0 ;
output [0:0]CO;
output [0:0]\Q_reg[25]_1 ;
input [22:0]\Q_reg[22]_0 ;
input [0:0]\Q_reg[22]_1 ;
input [0:0]E;
input [25:0]D;
input CLK;
input [3:0]AR;
wire [3:0]AR;
wire CLK;
wire [0:0]CO;
wire [25:0]D;
wire [0:0]E;
wire [3:0]O;
wire [23:0]Q;
wire \Q[12]_i_4__1_n_0 ;
wire \Q[12]_i_5__1_n_0 ;
wire \Q[12]_i_6__0_n_0 ;
wire \Q[12]_i_7__0_n_0 ;
wire \Q[16]_i_4__0_n_0 ;
wire \Q[16]_i_5_n_0 ;
wire \Q[16]_i_6_n_0 ;
wire \Q[16]_i_7_n_0 ;
wire \Q[20]_i_4__0_n_0 ;
wire \Q[20]_i_5__0_n_0 ;
wire \Q[20]_i_6_n_0 ;
wire \Q[20]_i_7_n_0 ;
wire \Q[24]_i_4_n_0 ;
wire \Q[24]_i_5_n_0 ;
wire \Q[24]_i_6_n_0 ;
wire \Q[24]_i_7_n_0 ;
wire \Q[2]_i_3_n_0 ;
wire \Q[4]_i_4_n_0 ;
wire \Q[4]_i_5_n_0 ;
wire \Q[4]_i_6_n_0 ;
wire \Q[4]_i_7_n_0 ;
wire \Q[4]_i_8_n_0 ;
wire \Q[8]_i_4__0_n_0 ;
wire \Q[8]_i_5__0_n_0 ;
wire \Q[8]_i_6__0_n_0 ;
wire \Q[8]_i_7__0_n_0 ;
wire [3:0]\Q_reg[12]_0 ;
wire \Q_reg[12]_i_2_n_0 ;
wire \Q_reg[12]_i_2_n_1 ;
wire \Q_reg[12]_i_2_n_2 ;
wire \Q_reg[12]_i_2_n_3 ;
wire [3:0]\Q_reg[16]_0 ;
wire \Q_reg[16]_i_2_n_0 ;
wire \Q_reg[16]_i_2_n_1 ;
wire \Q_reg[16]_i_2_n_2 ;
wire \Q_reg[16]_i_2_n_3 ;
wire [3:0]\Q_reg[20]_0 ;
wire \Q_reg[20]_i_2_n_0 ;
wire \Q_reg[20]_i_2_n_1 ;
wire \Q_reg[20]_i_2_n_2 ;
wire \Q_reg[20]_i_2_n_3 ;
wire [22:0]\Q_reg[22]_0 ;
wire [0:0]\Q_reg[22]_1 ;
wire [3:0]\Q_reg[24]_0 ;
wire \Q_reg[24]_i_2_n_0 ;
wire \Q_reg[24]_i_2_n_1 ;
wire \Q_reg[24]_i_2_n_2 ;
wire \Q_reg[24]_i_2_n_3 ;
wire [0:0]\Q_reg[25]_0 ;
wire [0:0]\Q_reg[25]_1 ;
wire \Q_reg[4]_i_2_n_0 ;
wire \Q_reg[4]_i_2_n_1 ;
wire \Q_reg[4]_i_2_n_2 ;
wire \Q_reg[4]_i_2_n_3 ;
wire [3:0]\Q_reg[8]_0 ;
wire \Q_reg[8]_i_2_n_0 ;
wire \Q_reg[8]_i_2_n_1 ;
wire \Q_reg[8]_i_2_n_2 ;
wire \Q_reg[8]_i_2_n_3 ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[25] ;
wire [3:0]\NLW_Q_reg[25]_i_2_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[25]_i_2_O_UNCONNECTED ;
wire [3:0]\NLW_Q_reg[2]_i_2_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[2]_i_2_O_UNCONNECTED ;
assign S[0] = \Q_reg_n_0_[1] ;
LUT2 #(
.INIT(4'h9))
\Q[12]_i_4__1
(.I0(Q[11]),
.I1(\Q_reg[22]_0 [10]),
.O(\Q[12]_i_4__1_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_5__1
(.I0(Q[10]),
.I1(\Q_reg[22]_0 [9]),
.O(\Q[12]_i_5__1_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_6__0
(.I0(Q[9]),
.I1(\Q_reg[22]_0 [8]),
.O(\Q[12]_i_6__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_7__0
(.I0(Q[8]),
.I1(\Q_reg[22]_0 [7]),
.O(\Q[12]_i_7__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_4__0
(.I0(Q[15]),
.I1(\Q_reg[22]_0 [14]),
.O(\Q[16]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_5
(.I0(Q[14]),
.I1(\Q_reg[22]_0 [13]),
.O(\Q[16]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_6
(.I0(Q[13]),
.I1(\Q_reg[22]_0 [12]),
.O(\Q[16]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_7
(.I0(Q[12]),
.I1(\Q_reg[22]_0 [11]),
.O(\Q[16]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_4__0
(.I0(Q[19]),
.I1(\Q_reg[22]_0 [18]),
.O(\Q[20]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_5__0
(.I0(Q[18]),
.I1(\Q_reg[22]_0 [17]),
.O(\Q[20]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_6
(.I0(Q[17]),
.I1(\Q_reg[22]_0 [16]),
.O(\Q[20]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_7
(.I0(Q[16]),
.I1(\Q_reg[22]_0 [15]),
.O(\Q[20]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_4
(.I0(Q[23]),
.I1(\Q_reg[22]_0 [22]),
.O(\Q[24]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_5
(.I0(Q[22]),
.I1(\Q_reg[22]_0 [21]),
.O(\Q[24]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_6
(.I0(Q[21]),
.I1(\Q_reg[22]_0 [20]),
.O(\Q[24]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_7
(.I0(Q[20]),
.I1(\Q_reg[22]_0 [19]),
.O(\Q[24]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[2]_i_3
(.I0(\Q_reg_n_0_[25] ),
.O(\Q[2]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_4
(.I0(Q[0]),
.O(\Q[4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_5
(.I0(Q[3]),
.I1(\Q_reg[22]_0 [2]),
.O(\Q[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_6
(.I0(Q[2]),
.I1(\Q_reg[22]_0 [1]),
.O(\Q[4]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_7
(.I0(Q[1]),
.I1(\Q_reg[22]_0 [0]),
.O(\Q[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_8
(.I0(\Q_reg_n_0_[1] ),
.O(\Q[4]_i_8_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_4__0
(.I0(Q[7]),
.I1(\Q_reg[22]_0 [6]),
.O(\Q[8]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_5__0
(.I0(Q[6]),
.I1(\Q_reg[22]_0 [5]),
.O(\Q[8]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_6__0
(.I0(Q[5]),
.I1(\Q_reg[22]_0 [4]),
.O(\Q[8]_i_6__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_7__0
(.I0(Q[4]),
.I1(\Q_reg[22]_0 [3]),
.O(\Q[8]_i_7__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[10]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[11]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[12]),
.Q(Q[11]));
CARRY4 \Q_reg[12]_i_2
(.CI(\Q_reg[8]_i_2_n_0 ),
.CO({\Q_reg[12]_i_2_n_0 ,\Q_reg[12]_i_2_n_1 ,\Q_reg[12]_i_2_n_2 ,\Q_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [10:7]),
.O(\Q_reg[12]_0 ),
.S({\Q[12]_i_4__1_n_0 ,\Q[12]_i_5__1_n_0 ,\Q[12]_i_6__0_n_0 ,\Q[12]_i_7__0_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[13]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[14]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[15]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[16]),
.Q(Q[15]));
CARRY4 \Q_reg[16]_i_2
(.CI(\Q_reg[12]_i_2_n_0 ),
.CO({\Q_reg[16]_i_2_n_0 ,\Q_reg[16]_i_2_n_1 ,\Q_reg[16]_i_2_n_2 ,\Q_reg[16]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [14:11]),
.O(\Q_reg[16]_0 ),
.S({\Q[16]_i_4__0_n_0 ,\Q[16]_i_5_n_0 ,\Q[16]_i_6_n_0 ,\Q[16]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[17]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[18]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[19]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(D[1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[20]),
.Q(Q[19]));
CARRY4 \Q_reg[20]_i_2
(.CI(\Q_reg[16]_i_2_n_0 ),
.CO({\Q_reg[20]_i_2_n_0 ,\Q_reg[20]_i_2_n_1 ,\Q_reg[20]_i_2_n_2 ,\Q_reg[20]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [18:15]),
.O(\Q_reg[20]_0 ),
.S({\Q[20]_i_4__0_n_0 ,\Q[20]_i_5__0_n_0 ,\Q[20]_i_6_n_0 ,\Q[20]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[21]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[22]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[23]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[24]),
.Q(Q[23]));
CARRY4 \Q_reg[24]_i_2
(.CI(\Q_reg[20]_i_2_n_0 ),
.CO({\Q_reg[24]_i_2_n_0 ,\Q_reg[24]_i_2_n_1 ,\Q_reg[24]_i_2_n_2 ,\Q_reg[24]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [22:19]),
.O(\Q_reg[24]_0 ),
.S({\Q[24]_i_4_n_0 ,\Q[24]_i_5_n_0 ,\Q[24]_i_6_n_0 ,\Q[24]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[25]),
.Q(\Q_reg_n_0_[25] ));
CARRY4 \Q_reg[25]_i_2
(.CI(\Q_reg[24]_i_2_n_0 ),
.CO(\NLW_Q_reg[25]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_Q_reg[25]_i_2_O_UNCONNECTED [3:1],\Q_reg[25]_0 }),
.S({1'b0,1'b0,1'b0,\Q_reg_n_0_[25] }));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[2]),
.Q(Q[1]));
CARRY4 \Q_reg[2]_i_2
(.CI(\Q_reg[22]_1 ),
.CO({\NLW_Q_reg[2]_i_2_CO_UNCONNECTED [3:2],CO,\NLW_Q_reg[2]_i_2_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\Q_reg_n_0_[25] }),
.O({\NLW_Q_reg[2]_i_2_O_UNCONNECTED [3:1],\Q_reg[25]_1 }),
.S({1'b0,1'b0,1'b1,\Q[2]_i_3_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[3]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[4]),
.Q(Q[3]));
CARRY4 \Q_reg[4]_i_2
(.CI(1'b0),
.CO({\Q_reg[4]_i_2_n_0 ,\Q_reg[4]_i_2_n_1 ,\Q_reg[4]_i_2_n_2 ,\Q_reg[4]_i_2_n_3 }),
.CYINIT(\Q[4]_i_4_n_0 ),
.DI({\Q_reg[22]_0 [2:0],1'b0}),
.O(O),
.S({\Q[4]_i_5_n_0 ,\Q[4]_i_6_n_0 ,\Q[4]_i_7_n_0 ,\Q[4]_i_8_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[5]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[6]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[7]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[8]),
.Q(Q[7]));
CARRY4 \Q_reg[8]_i_2
(.CI(\Q_reg[4]_i_2_n_0 ),
.CO({\Q_reg[8]_i_2_n_0 ,\Q_reg[8]_i_2_n_1 ,\Q_reg[8]_i_2_n_2 ,\Q_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [6:3]),
.O(\Q_reg[8]_0 ),
.S({\Q[8]_i_4__0_n_0 ,\Q[8]_i_5__0_n_0 ,\Q[8]_i_6__0_n_0 ,\Q[8]_i_7__0_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[9]),
.Q(Q[8]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized17
(\Q_reg[2]_0 ,
Q,
CO,
E,
\Q_reg[2]_1 ,
CLK,
AR);
output [2:0]\Q_reg[2]_0 ;
output [0:0]Q;
input [0:0]CO;
input [0:0]E;
input [2:0]\Q_reg[2]_1 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire [0:0]Q;
wire [2:0]\Q_reg[2]_0 ;
wire [2:0]\Q_reg[2]_1 ;
LUT2 #(
.INIT(4'h2))
\Q[2]_i_1__11
(.I0(CO),
.I1(Q),
.O(\Q_reg[2]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[2]_1 [0]),
.Q(\Q_reg[2]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[2]_1 [1]),
.Q(Q));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[2]_1 [2]),
.Q(\Q_reg[2]_0 [1]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized18
(D,
\Q_reg[12]_0 ,
\Q_reg[12]_1 ,
\Q_reg[1]_0 ,
\Q_reg[1]_1 ,
\Q_reg[2]_0 ,
Q,
\Q_reg[2]_1 ,
\Q_reg[22]_0 ,
\Q_reg[1]_2 ,
CLK,
AR);
output [24:0]D;
output [4:0]\Q_reg[12]_0 ;
output [0:0]\Q_reg[12]_1 ;
input [0:0]\Q_reg[1]_0 ;
input \Q_reg[1]_1 ;
input \Q_reg[2]_0 ;
input [1:0]Q;
input [0:0]\Q_reg[2]_1 ;
input [22:0]\Q_reg[22]_0 ;
input [25:0]\Q_reg[1]_2 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [24:0]D;
wire [1:0]Q;
wire \Q[0]_i_2_n_0 ;
wire \Q[10]_i_2__0_n_0 ;
wire \Q[10]_i_2_n_0 ;
wire \Q[10]_i_3_n_0 ;
wire \Q[10]_i_4_n_0 ;
wire \Q[11]_i_2_n_0 ;
wire \Q[12]_i_2__0_n_0 ;
wire \Q[12]_i_2_n_0 ;
wire \Q[12]_i_3_n_0 ;
wire \Q[12]_i_4_n_0 ;
wire \Q[12]_i_5_n_0 ;
wire \Q[12]_i_6_n_0 ;
wire \Q[12]_i_7_n_0 ;
wire \Q[13]_i_2_n_0 ;
wire \Q[14]_i_2__0_n_0 ;
wire \Q[15]_i_2_n_0 ;
wire \Q[16]_i_2_n_0 ;
wire \Q[17]_i_2_n_0 ;
wire \Q[18]_i_2_n_0 ;
wire \Q[19]_i_2_n_0 ;
wire \Q[1]_i_2__0_n_0 ;
wire \Q[20]_i_2_n_0 ;
wire \Q[21]_i_2_n_0 ;
wire \Q[22]_i_2_n_0 ;
wire \Q[23]_i_2_n_0 ;
wire \Q[24]_i_2_n_0 ;
wire \Q[24]_i_3_n_0 ;
wire \Q[2]_i_2_n_0 ;
wire \Q[3]_i_2_n_0 ;
wire \Q[4]_i_2_n_0 ;
wire \Q[5]_i_2_n_0 ;
wire \Q[6]_i_2__0_n_0 ;
wire \Q[7]_i_2_n_0 ;
wire \Q[8]_i_2__0_n_0 ;
wire \Q[8]_i_2_n_0 ;
wire \Q[8]_i_3_n_0 ;
wire \Q[8]_i_4_n_0 ;
wire \Q[8]_i_5_n_0 ;
wire \Q[8]_i_6_n_0 ;
wire \Q[8]_i_7_n_0 ;
wire \Q[8]_i_8_n_0 ;
wire \Q[8]_i_9_n_0 ;
wire \Q[9]_i_10_n_0 ;
wire \Q[9]_i_11_n_0 ;
wire \Q[9]_i_2__0_n_0 ;
wire \Q[9]_i_2_n_0 ;
wire \Q[9]_i_3_n_0 ;
wire \Q[9]_i_4_n_0 ;
wire \Q[9]_i_5_n_0 ;
wire \Q[9]_i_6_n_0 ;
wire \Q[9]_i_7_n_0 ;
wire \Q[9]_i_8_n_0 ;
wire \Q[9]_i_9_n_0 ;
wire [4:0]\Q_reg[12]_0 ;
wire [0:0]\Q_reg[12]_1 ;
wire [0:0]\Q_reg[1]_0 ;
wire \Q_reg[1]_1 ;
wire [25:0]\Q_reg[1]_2 ;
wire [22:0]\Q_reg[22]_0 ;
wire \Q_reg[2]_0 ;
wire [0:0]\Q_reg[2]_1 ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[13] ;
wire \Q_reg_n_0_[14] ;
wire \Q_reg_n_0_[15] ;
wire \Q_reg_n_0_[16] ;
wire \Q_reg_n_0_[17] ;
wire \Q_reg_n_0_[18] ;
wire \Q_reg_n_0_[19] ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[20] ;
wire \Q_reg_n_0_[21] ;
wire \Q_reg_n_0_[22] ;
wire \Q_reg_n_0_[23] ;
wire \Q_reg_n_0_[24] ;
wire \Q_reg_n_0_[25] ;
wire \Q_reg_n_0_[2] ;
wire \Q_reg_n_0_[3] ;
wire \Q_reg_n_0_[4] ;
wire \Q_reg_n_0_[5] ;
wire \Q_reg_n_0_[6] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
LUT6 #(
.INIT(64'hFFFFFFC0FFA0FFC0))
\Q[0]_i_1__8
(.I0(\Q[3]_i_2_n_0 ),
.I1(\Q[2]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[0]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[1]_i_2__0_n_0 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'h20))
\Q[0]_i_2
(.I0(\Q_reg_n_0_[25] ),
.I1(\Q_reg[2]_1 ),
.I2(Q[0]),
.O(\Q[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[10]_i_1__6
(.I0(\Q[13]_i_2_n_0 ),
.I1(\Q[12]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[11]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[10]_i_2__0_n_0 ),
.O(D[10]));
LUT6 #(
.INIT(64'h0001000000010001))
\Q[10]_i_1__7
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg_n_0_[23] ),
.I2(\Q_reg_n_0_[24] ),
.I3(\Q_reg_n_0_[25] ),
.I4(\Q[10]_i_2_n_0 ),
.I5(\Q[10]_i_3_n_0 ),
.O(\Q_reg[12]_0 [2]));
LUT6 #(
.INIT(64'h00808888AAAAAAAA))
\Q[10]_i_2
(.I0(\Q[12]_i_6_n_0 ),
.I1(\Q[12]_i_3_n_0 ),
.I2(\Q_reg[12]_1 ),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q[12]_i_2_n_0 ),
.I5(\Q[10]_i_4_n_0 ),
.O(\Q[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[10]_i_2__0
(.I0(\Q_reg_n_0_[15] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[10] ),
.I4(\Q_reg[22]_0 [8]),
.O(\Q[10]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT4 #(
.INIT(16'h0001))
\Q[10]_i_3
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg_n_0_[20] ),
.I2(\Q_reg_n_0_[19] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[10]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT4 #(
.INIT(16'h0001))
\Q[10]_i_4
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q_reg_n_0_[12] ),
.O(\Q[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[11]_i_1__6
(.I0(\Q[14]_i_2__0_n_0 ),
.I1(\Q[13]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[12]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[11]_i_2_n_0 ),
.O(D[11]));
LUT5 #(
.INIT(32'h8000AAAA))
\Q[11]_i_1__7
(.I0(\Q[12]_i_5_n_0 ),
.I1(\Q[12]_i_3_n_0 ),
.I2(\Q[12]_i_2_n_0 ),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q[12]_i_4_n_0 ),
.O(\Q_reg[12]_0 [3]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[11]_i_2
(.I0(\Q_reg_n_0_[14] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q_reg[22]_0 [9]),
.O(\Q[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[12]_i_1__6
(.I0(\Q[15]_i_2_n_0 ),
.I1(\Q[14]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[13]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[12]_i_2__0_n_0 ),
.O(D[12]));
LUT6 #(
.INIT(64'hFDFF000000000000))
\Q[12]_i_1__7
(.I0(\Q[12]_i_2_n_0 ),
.I1(\Q_reg_n_0_[1] ),
.I2(\Q_reg[12]_1 ),
.I3(\Q[12]_i_3_n_0 ),
.I4(\Q[12]_i_4_n_0 ),
.I5(\Q[12]_i_5_n_0 ),
.O(\Q_reg[12]_0 [4]));
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_2
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg_n_0_[2] ),
.I2(\Q_reg_n_0_[5] ),
.I3(\Q_reg_n_0_[4] ),
.O(\Q[12]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[12]_i_2__0
(.I0(\Q_reg_n_0_[13] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[12] ),
.I4(\Q_reg[22]_0 [10]),
.O(\Q[12]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_3
(.I0(\Q_reg_n_0_[9] ),
.I1(\Q_reg_n_0_[8] ),
.I2(\Q_reg_n_0_[6] ),
.I3(\Q_reg_n_0_[7] ),
.O(\Q[12]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT5 #(
.INIT(32'h00010000))
\Q[12]_i_4
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[13] ),
.I2(\Q_reg_n_0_[10] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q[12]_i_6_n_0 ),
.O(\Q[12]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT5 #(
.INIT(32'h00010000))
\Q[12]_i_5
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg_n_0_[19] ),
.I2(\Q_reg_n_0_[20] ),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q[12]_i_7_n_0 ),
.O(\Q[12]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_6
(.I0(\Q_reg_n_0_[17] ),
.I1(\Q_reg_n_0_[16] ),
.I2(\Q_reg_n_0_[15] ),
.I3(\Q_reg_n_0_[14] ),
.O(\Q[12]_i_6_n_0 ));
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_7
(.I0(\Q_reg_n_0_[25] ),
.I1(\Q_reg_n_0_[24] ),
.I2(\Q_reg_n_0_[23] ),
.I3(\Q_reg_n_0_[22] ),
.O(\Q[12]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_1__5
(.I0(\Q[16]_i_2_n_0 ),
.I1(\Q[15]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[14]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[13]_i_2_n_0 ),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'hFB3BC808))
\Q[13]_i_2
(.I0(\Q_reg_n_0_[12] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[13] ),
.I4(\Q_reg[22]_0 [11]),
.O(\Q[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[14]_i_1__6
(.I0(\Q[17]_i_2_n_0 ),
.I1(\Q[16]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[15]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[14]_i_2__0_n_0 ),
.O(D[14]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[14]_i_2__0
(.I0(\Q_reg_n_0_[11] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[14] ),
.I4(\Q_reg[22]_0 [12]),
.O(\Q[14]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[15]_i_1__5
(.I0(\Q[18]_i_2_n_0 ),
.I1(\Q[17]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[16]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[15]_i_2_n_0 ),
.O(D[15]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[15]_i_2
(.I0(\Q_reg_n_0_[10] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[15] ),
.I4(\Q_reg[22]_0 [13]),
.O(\Q[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_1__5
(.I0(\Q[19]_i_2_n_0 ),
.I1(\Q[18]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[17]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[16]_i_2_n_0 ),
.O(D[16]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[16]_i_2
(.I0(\Q_reg_n_0_[9] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[16] ),
.I4(\Q_reg[22]_0 [14]),
.O(\Q[16]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_1__5
(.I0(\Q[20]_i_2_n_0 ),
.I1(\Q[19]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[18]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[17]_i_2_n_0 ),
.O(D[17]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[17]_i_2
(.I0(\Q_reg_n_0_[8] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[17] ),
.I4(\Q_reg[22]_0 [15]),
.O(\Q[17]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_1__5
(.I0(\Q[21]_i_2_n_0 ),
.I1(\Q[20]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[19]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[18]_i_2_n_0 ),
.O(D[18]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[18]_i_2
(.I0(\Q_reg_n_0_[7] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[18] ),
.I4(\Q_reg[22]_0 [16]),
.O(\Q[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_1__5
(.I0(\Q[22]_i_2_n_0 ),
.I1(\Q[21]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[20]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[19]_i_2_n_0 ),
.O(D[19]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[19]_i_2
(.I0(\Q_reg_n_0_[6] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[19] ),
.I4(\Q_reg[22]_0 [17]),
.O(\Q[19]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[1]_i_1__6
(.I0(\Q[4]_i_2_n_0 ),
.I1(\Q[3]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[2]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[1]_i_2__0_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT4 #(
.INIT(16'h8C80))
\Q[1]_i_2__0
(.I0(\Q_reg_n_0_[1] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[24] ),
.O(\Q[1]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_1__5
(.I0(\Q[23]_i_2_n_0 ),
.I1(\Q[22]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[21]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[20]_i_2_n_0 ),
.O(D[20]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[20]_i_2
(.I0(\Q_reg_n_0_[5] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg[22]_0 [18]),
.O(\Q[20]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_1__6
(.I0(\Q[24]_i_2_n_0 ),
.I1(\Q[23]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[22]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[21]_i_2_n_0 ),
.O(D[21]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[21]_i_2
(.I0(\Q_reg_n_0_[4] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q_reg[22]_0 [19]),
.O(\Q[21]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_1__6
(.I0(\Q[24]_i_3_n_0 ),
.I1(\Q[24]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[23]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[22]_i_2_n_0 ),
.O(D[22]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[22]_i_2
(.I0(\Q_reg_n_0_[3] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[22] ),
.I4(\Q_reg[22]_0 [20]),
.O(\Q[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0EFEFAFA0E0E0))
\Q[23]_i_1__5
(.I0(\Q_reg[1]_0 ),
.I1(\Q[24]_i_3_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[24]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[23]_i_2_n_0 ),
.O(D[23]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[23]_i_2
(.I0(\Q_reg_n_0_[2] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[23] ),
.I4(\Q_reg[22]_0 [21]),
.O(\Q[23]_i_2_n_0 ));
LUT4 #(
.INIT(16'h00E2))
\Q[24]_i_1__6
(.I0(\Q[24]_i_2_n_0 ),
.I1(\Q_reg[2]_0 ),
.I2(\Q[24]_i_3_n_0 ),
.I3(\Q_reg[1]_1 ),
.O(D[24]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'hFB3BC808))
\Q[24]_i_2
(.I0(\Q_reg_n_0_[1] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[24] ),
.I4(\Q_reg[22]_0 [22]),
.O(\Q[24]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT4 #(
.INIT(16'hFB3B))
\Q[24]_i_3
(.I0(\Q_reg[12]_1 ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[25] ),
.O(\Q[24]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[2]_i_1__5
(.I0(\Q[5]_i_2_n_0 ),
.I1(\Q[4]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[3]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[2]_i_2_n_0 ),
.O(D[2]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[2]_i_2
(.I0(\Q_reg_n_0_[23] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[2] ),
.I4(\Q_reg[22]_0 [0]),
.O(\Q[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[3]_i_1__5
(.I0(\Q[6]_i_2__0_n_0 ),
.I1(\Q[5]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[4]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[3]_i_2_n_0 ),
.O(D[3]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[3]_i_2
(.I0(\Q_reg_n_0_[22] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[3] ),
.I4(\Q_reg[22]_0 [1]),
.O(\Q[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[4]_i_1__6
(.I0(\Q[7]_i_2_n_0 ),
.I1(\Q[6]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[5]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[4]_i_2_n_0 ),
.O(D[4]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[4]_i_2
(.I0(\Q_reg_n_0_[21] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[4] ),
.I4(\Q_reg[22]_0 [2]),
.O(\Q[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[5]_i_1__5
(.I0(\Q[8]_i_2__0_n_0 ),
.I1(\Q[7]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[6]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[5]_i_2_n_0 ),
.O(D[5]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[5]_i_2
(.I0(\Q_reg_n_0_[20] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg[22]_0 [3]),
.O(\Q[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[6]_i_1__7
(.I0(\Q[9]_i_2__0_n_0 ),
.I1(\Q[8]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[7]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[6]_i_2__0_n_0 ),
.O(D[6]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[6]_i_2__0
(.I0(\Q_reg_n_0_[19] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[6] ),
.I4(\Q_reg[22]_0 [4]),
.O(\Q[6]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[7]_i_1__5
(.I0(\Q[10]_i_2__0_n_0 ),
.I1(\Q[9]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[8]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[7]_i_2_n_0 ),
.O(D[7]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[7]_i_2
(.I0(\Q_reg_n_0_[18] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[7] ),
.I4(\Q_reg[22]_0 [5]),
.O(\Q[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[8]_i_1__6
(.I0(\Q[11]_i_2_n_0 ),
.I1(\Q[10]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[9]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[8]_i_2__0_n_0 ),
.O(D[8]));
LUT6 #(
.INIT(64'h00000000FFFF00AE))
\Q[8]_i_1__7
(.I0(\Q[8]_i_2_n_0 ),
.I1(\Q[8]_i_3_n_0 ),
.I2(\Q[8]_i_4_n_0 ),
.I3(\Q[8]_i_5_n_0 ),
.I4(\Q_reg_n_0_[24] ),
.I5(\Q_reg_n_0_[25] ),
.O(\Q_reg[12]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[8]_i_2
(.I0(\Q[8]_i_6_n_0 ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[20] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[8]_i_2__0
(.I0(\Q_reg_n_0_[17] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[8] ),
.I4(\Q_reg[22]_0 [6]),
.O(\Q[8]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF55045555))
\Q[8]_i_3
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q_reg_n_0_[4] ),
.I2(\Q_reg_n_0_[5] ),
.I3(\Q_reg_n_0_[6] ),
.I4(\Q[8]_i_7_n_0 ),
.I5(\Q[8]_i_8_n_0 ),
.O(\Q[8]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT4 #(
.INIT(16'hFEFF))
\Q[8]_i_4
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[17] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q[8]_i_9_n_0 ),
.O(\Q[8]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT5 #(
.INIT(32'hBABBBABA))
\Q[8]_i_5
(.I0(\Q_reg_n_0_[23] ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[21] ),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg_n_0_[19] ),
.O(\Q[8]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT4 #(
.INIT(16'h00F2))
\Q[8]_i_6
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[15] ),
.I2(\Q_reg_n_0_[16] ),
.I3(\Q_reg_n_0_[17] ),
.O(\Q[8]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFFBABB))
\Q[8]_i_7
(.I0(\Q_reg_n_0_[5] ),
.I1(\Q_reg_n_0_[2] ),
.I2(\Q_reg_n_0_[1] ),
.I3(\Q_reg[12]_1 ),
.I4(\Q_reg_n_0_[3] ),
.O(\Q[8]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT4 #(
.INIT(16'hEFEE))
\Q[8]_i_8
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[8] ),
.I2(\Q_reg_n_0_[11] ),
.I3(\Q_reg_n_0_[10] ),
.O(\Q[8]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT4 #(
.INIT(16'hFF0B))
\Q[8]_i_9
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg_n_0_[9] ),
.I2(\Q_reg_n_0_[11] ),
.I3(\Q_reg_n_0_[12] ),
.O(\Q[8]_i_9_n_0 ));
LUT2 #(
.INIT(4'h1))
\Q[9]_i_10
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg_n_0_[11] ),
.O(\Q[9]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_11
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[15] ),
.O(\Q[9]_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[9]_i_1__6
(.I0(\Q[12]_i_2__0_n_0 ),
.I1(\Q[11]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[10]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[9]_i_2__0_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'h1111111110001010))
\Q[9]_i_1__7
(.I0(\Q_reg_n_0_[25] ),
.I1(\Q_reg_n_0_[24] ),
.I2(\Q[9]_i_2_n_0 ),
.I3(\Q[9]_i_3_n_0 ),
.I4(\Q[9]_i_4_n_0 ),
.I5(\Q[9]_i_5_n_0 ),
.O(\Q_reg[12]_0 [1]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_2
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg_n_0_[21] ),
.O(\Q[9]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[9]_i_2__0
(.I0(\Q_reg_n_0_[16] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[9] ),
.I4(\Q_reg[22]_0 [7]),
.O(\Q[9]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h00808888AAAAAAAA))
\Q[9]_i_3
(.I0(\Q[9]_i_6_n_0 ),
.I1(\Q[9]_i_7_n_0 ),
.I2(\Q[9]_i_8_n_0 ),
.I3(\Q[9]_i_9_n_0 ),
.I4(\Q[9]_i_10_n_0 ),
.I5(\Q[9]_i_11_n_0 ),
.O(\Q[9]_i_3_n_0 ));
LUT2 #(
.INIT(4'h1))
\Q[9]_i_4
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg_n_0_[19] ),
.O(\Q[9]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT2 #(
.INIT(4'hE))
\Q[9]_i_5
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg_n_0_[23] ),
.O(\Q[9]_i_5_n_0 ));
LUT2 #(
.INIT(4'h1))
\Q[9]_i_6
(.I0(\Q_reg_n_0_[16] ),
.I1(\Q_reg_n_0_[17] ),
.O(\Q[9]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_7
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[13] ),
.O(\Q[9]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_8
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg_n_0_[9] ),
.O(\Q[9]_i_8_n_0 ));
LUT6 #(
.INIT(64'h1110111011101111))
\Q[9]_i_9
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg_n_0_[7] ),
.I2(\Q_reg_n_0_[4] ),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg_n_0_[2] ),
.I5(\Q_reg_n_0_[3] ),
.O(\Q[9]_i_9_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [0]),
.Q(\Q_reg[12]_1 ));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [13]),
.Q(\Q_reg_n_0_[13] ));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [14]),
.Q(\Q_reg_n_0_[14] ));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [15]),
.Q(\Q_reg_n_0_[15] ));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [16]),
.Q(\Q_reg_n_0_[16] ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [17]),
.Q(\Q_reg_n_0_[17] ));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [18]),
.Q(\Q_reg_n_0_[18] ));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [19]),
.Q(\Q_reg_n_0_[19] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [20]),
.Q(\Q_reg_n_0_[20] ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [21]),
.Q(\Q_reg_n_0_[21] ));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [22]),
.Q(\Q_reg_n_0_[22] ));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [23]),
.Q(\Q_reg_n_0_[23] ));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [24]),
.Q(\Q_reg_n_0_[24] ));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [25]),
.Q(\Q_reg_n_0_[25] ));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [2]),
.Q(\Q_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [4]),
.Q(\Q_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [5]),
.Q(\Q_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [6]),
.Q(\Q_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [9]),
.Q(\Q_reg_n_0_[9] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized19
(Q,
\Q_reg[2]_0 ,
\Q_reg[30] ,
CLK,
AR);
output [7:0]Q;
input [0:0]\Q_reg[2]_0 ;
input [7:0]\Q_reg[30] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [7:0]Q;
wire [0:0]\Q_reg[2]_0 ;
wire [7:0]\Q_reg[30] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [7]),
.Q(Q[7]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized2
(D,
Q,
\Q_reg[27]_0 ,
\Q_reg[6]_0 ,
\Q_reg[27]_1 ,
CLK,
AR);
output [2:0]D;
output [25:0]Q;
input [4:0]\Q_reg[27]_0 ;
input [0:0]\Q_reg[6]_0 ;
input [27:0]\Q_reg[27]_1 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [25:0]Q;
wire \Q[4]_i_2__0_n_0 ;
wire [4:0]\Q_reg[27]_0 ;
wire [27:0]\Q_reg[27]_1 ;
wire [0:0]\Q_reg[6]_0 ;
wire \Q_reg_n_0_[26] ;
wire \Q_reg_n_0_[27] ;
LUT4 #(
.INIT(16'h2DD2))
\Q[1]_i_1__11
(.I0(Q[23]),
.I1(\Q_reg[27]_0 [0]),
.I2(Q[24]),
.I3(\Q_reg[27]_0 [1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h69))
\Q[3]_i_1__8
(.I0(\Q[4]_i_2__0_n_0 ),
.I1(\Q_reg_n_0_[26] ),
.I2(\Q_reg[27]_0 [3]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT5 #(
.INIT(32'h718E8E71))
\Q[4]_i_1__9
(.I0(\Q[4]_i_2__0_n_0 ),
.I1(\Q_reg[27]_0 [3]),
.I2(\Q_reg_n_0_[26] ),
.I3(\Q_reg_n_0_[27] ),
.I4(\Q_reg[27]_0 [4]),
.O(D[2]));
LUT6 #(
.INIT(64'hD4DD4444DDDDD4DD))
\Q[4]_i_2__0
(.I0(Q[25]),
.I1(\Q_reg[27]_0 [2]),
.I2(\Q_reg[27]_0 [0]),
.I3(Q[23]),
.I4(\Q_reg[27]_0 [1]),
.I5(Q[24]),
.O(\Q[4]_i_2__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [26]),
.Q(\Q_reg_n_0_[26] ));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [27]),
.Q(\Q_reg_n_0_[27] ));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized20
(D,
Q,
\Q_reg[25] ,
\Q_reg[25]_0 ,
\Q_reg[22] ,
\Q_reg[2]_0 ,
\Q_reg[2]_1 ,
\Q_reg[0]_0 ,
\Q_reg[1]_0 ,
\Q_reg[1]_1 ,
CLK,
AR);
output [0:0]D;
output [2:0]Q;
output \Q_reg[25] ;
output [0:0]\Q_reg[25]_0 ;
input [1:0]\Q_reg[22] ;
input [1:0]\Q_reg[2]_0 ;
input [1:0]\Q_reg[2]_1 ;
input [0:0]\Q_reg[0]_0 ;
input \Q_reg[1]_0 ;
input [2:0]\Q_reg[1]_1 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[0]_0 ;
wire \Q_reg[1]_0 ;
wire [2:0]\Q_reg[1]_1 ;
wire [1:0]\Q_reg[22] ;
wire \Q_reg[25] ;
wire [0:0]\Q_reg[25]_0 ;
wire [1:0]\Q_reg[2]_0 ;
wire [1:0]\Q_reg[2]_1 ;
LUT5 #(
.INIT(32'h000088FB))
\Q[25]_i_2
(.I0(Q[2]),
.I1(\Q_reg[2]_0 [0]),
.I2(\Q_reg[0]_0 ),
.I3(\Q_reg[25] ),
.I4(\Q_reg[1]_0 ),
.O(\Q_reg[25]_0 ));
LUT4 #(
.INIT(16'hEEF0))
\Q[25]_i_3
(.I0(Q[2]),
.I1(\Q_reg[22] [0]),
.I2(\Q_reg[2]_1 [0]),
.I3(\Q_reg[2]_0 [0]),
.O(\Q_reg[25] ));
LUT4 #(
.INIT(16'h4F40))
\Q[2]_i_1__6
(.I0(Q[2]),
.I1(\Q_reg[22] [1]),
.I2(\Q_reg[2]_0 [0]),
.I3(\Q_reg[2]_1 [1]),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_1 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_1 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_1 [2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized21
(overflow_flag,
Q,
OVRFLW_FLAG_FRMT,
CLK,
AR,
UNDRFLW_FLAG_FRMT,
\Q_reg[0]_0 );
output [2:0]overflow_flag;
input [0:0]Q;
input OVRFLW_FLAG_FRMT;
input CLK;
input [1:0]AR;
input UNDRFLW_FLAG_FRMT;
input [0:0]\Q_reg[0]_0 ;
wire [1:0]AR;
wire CLK;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire [0:0]\Q_reg[0]_0 ;
wire UNDRFLW_FLAG_FRMT;
wire [2:0]overflow_flag;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(\Q_reg[0]_0 ),
.Q(overflow_flag[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(UNDRFLW_FLAG_FRMT),
.Q(overflow_flag[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(OVRFLW_FLAG_FRMT),
.Q(overflow_flag[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized22
(ready_add_subt,
Q,
CLK,
AR);
output ready_add_subt;
input [0:0]Q;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]Q;
wire ready_add_subt;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(Q),
.Q(ready_add_subt));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized3
(Q,
\Q_reg[6] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[6] ;
input [2:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[6] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR[0]),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized4
(Q,
\Q_reg[5]_0 ,
D,
CLK,
AR);
output [30:0]Q;
input [0:0]\Q_reg[5]_0 ;
input [30:0]D;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [30:0]D;
wire [30:0]Q;
wire [0:0]\Q_reg[5]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized5
(Q,
\Q_reg[5]_0 ,
D,
CLK,
AR);
output [22:0]Q;
input [0:0]\Q_reg[5]_0 ;
input [22:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [22:0]D;
wire [22:0]Q;
wire [0:0]\Q_reg[5]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized6
(\Q_reg[23] ,
Q,
D,
\Q_reg[5] ,
\Q_reg[2]_0 ,
\Q_reg[1]_0 ,
\Q_reg[26] ,
CLK,
AR);
output \Q_reg[23] ;
output [1:0]Q;
output [1:0]D;
input [1:0]\Q_reg[5] ;
input [0:0]\Q_reg[2]_0 ;
input [2:0]\Q_reg[1]_0 ;
input [4:0]\Q_reg[26] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [1:0]D;
wire [1:0]Q;
wire [2:0]\Q_reg[1]_0 ;
wire \Q_reg[23] ;
wire [4:0]\Q_reg[26] ;
wire [0:0]\Q_reg[2]_0 ;
wire [1:0]\Q_reg[5] ;
wire [4:1]Shift_amount_SHT1_EWR;
LUT4 #(
.INIT(16'h2E22))
\Q[25]_i_4
(.I0(Shift_amount_SHT1_EWR[1]),
.I1(\Q_reg[5] [0]),
.I2(\Q_reg[2]_0 ),
.I3(\Q_reg[1]_0 [0]),
.O(\Q_reg[23] ));
LUT4 #(
.INIT(16'h2E22))
\Q[3]_i_1__6
(.I0(Shift_amount_SHT1_EWR[3]),
.I1(\Q_reg[5] [0]),
.I2(\Q_reg[2]_0 ),
.I3(\Q_reg[1]_0 [1]),
.O(D[0]));
LUT4 #(
.INIT(16'h2E22))
\Q[4]_i_1__7
(.I0(Shift_amount_SHT1_EWR[4]),
.I1(\Q_reg[5] [0]),
.I2(\Q_reg[2]_0 ),
.I3(\Q_reg[1]_0 [2]),
.O(D[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [1]),
.Q(Shift_amount_SHT1_EWR[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [2]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [3]),
.Q(Shift_amount_SHT1_EWR[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [4]),
.Q(Shift_amount_SHT1_EWR[4]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized7
(Q,
\Q_reg[5] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[5] ;
input [2:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[5] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR[0]),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized8
(Q,
\Q_reg[4]_0 ,
D,
CLK,
AR);
output [30:0]Q;
input [0:0]\Q_reg[4]_0 ;
input [30:0]D;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [30:0]D;
wire [30:0]Q;
wire [0:0]\Q_reg[4]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized9
(D,
\Data_array_SWR[6]_4 ,
\Q_reg[25]_0 ,
\Q_reg[8]_0 ,
\Q_reg[13]_0 ,
\Data_array_SWR[4]_5 ,
Q,
\Q_reg[4]_0 ,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[4]_1 ,
E,
\Q_reg[2]_0 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [2:0]D;
output [0:0]\Data_array_SWR[6]_4 ;
output [4:0]\Q_reg[25]_0 ;
output [11:0]\Q_reg[8]_0 ;
output [7:0]\Q_reg[13]_0 ;
output [1:0]\Data_array_SWR[4]_5 ;
input [1:0]Q;
input [1:0]\Q_reg[4]_0 ;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [2:0]\Q_reg[4]_1 ;
input [0:0]E;
input [25:0]\Q_reg[2]_0 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [2:0]D;
wire [17:0]\Data_array_SWR[3]_0 ;
wire [1:0]\Data_array_SWR[4]_5 ;
wire [13:0]\Data_array_SWR[5]_3 ;
wire [0:0]\Data_array_SWR[6]_4 ;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [7:0]\Q_reg[13]_0 ;
wire [4:0]\Q_reg[25]_0 ;
wire [25:0]\Q_reg[2]_0 ;
wire [1:0]\Q_reg[4]_0 ;
wire [2:0]\Q_reg[4]_1 ;
wire [11:0]\Q_reg[8]_0 ;
wire UNDRFLW_FLAG_FRMT;
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT5 #(
.INIT(32'hFF00B8B8))
\Q[0]_i_1__13
(.I0(\Q_reg[8]_0 [10]),
.I1(\Q_reg[4]_1 [2]),
.I2(\Data_array_SWR[5]_3 [0]),
.I3(\Q_reg[4]_0 [1]),
.I4(Q[1]),
.O(\Q_reg[25]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'h02))
\Q[10]_i_1__8
(.I0(\Q_reg[25]_0 [1]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'h02))
\Q[11]_i_1__8
(.I0(\Q_reg[25]_0 [2]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT5 #(
.INIT(32'hF0BBF088))
\Q[12]_i_1__8
(.I0(\Data_array_SWR[5]_3 [13]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[4]_1 [2]),
.I4(\Data_array_SWR[5]_3 [12]),
.O(\Q_reg[25]_0 [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[12]_i_4__0
(.I0(\Q_reg[13]_0 [5]),
.I1(\Q_reg[13]_0 [1]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [15]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [11]),
.O(\Q_reg[8]_0 [9]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_5__0
(.I0(\Q_reg[13]_0 [0]),
.I1(\Q_reg[4]_1 [0]),
.I2(\Data_array_SWR[3]_0 [14]),
.O(\Data_array_SWR[4]_5 [0]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT5 #(
.INIT(32'hF0BBF088))
\Q[13]_i_1__6
(.I0(\Data_array_SWR[5]_3 [12]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[4]_1 [2]),
.I4(\Data_array_SWR[5]_3 [13]),
.O(\Q_reg[25]_0 [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_2__1
(.I0(\Q_reg[13]_0 [6]),
.I1(\Q_reg[13]_0 [2]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [16]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [12]),
.O(\Data_array_SWR[5]_3 [12]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_3
(.I0(\Q_reg[13]_0 [7]),
.I1(\Q_reg[13]_0 [3]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [17]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [13]),
.O(\Data_array_SWR[5]_3 [13]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_4
(.I0(\Q_reg[13]_0 [4]),
.I1(\Q_reg[13]_0 [0]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [14]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [10]),
.O(\Q_reg[8]_0 [8]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_5
(.I0(\Q_reg[13]_0 [1]),
.I1(\Q_reg[4]_1 [0]),
.I2(\Data_array_SWR[3]_0 [15]),
.O(\Data_array_SWR[4]_5 [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_3
(.I0(\Q_reg[13]_0 [3]),
.I1(\Data_array_SWR[3]_0 [17]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [13]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [9]),
.O(\Q_reg[8]_0 [7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_4
(.I0(\Q_reg[13]_0 [1]),
.I1(\Data_array_SWR[3]_0 [15]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [11]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [7]),
.O(\Q_reg[8]_0 [5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_3
(.I0(Q[0]),
.I1(\Q_reg[13]_0 [7]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Q_reg[13]_0 [3]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [17]),
.O(\Q_reg[8]_0 [11]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_4
(.I0(\Q_reg[13]_0 [0]),
.I1(\Data_array_SWR[3]_0 [14]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [10]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [6]),
.O(\Q_reg[8]_0 [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_4__0
(.I0(\Q_reg[13]_0 [2]),
.I1(\Data_array_SWR[3]_0 [16]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [12]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [8]),
.O(\Q_reg[8]_0 [6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_5
(.I0(\Data_array_SWR[3]_0 [17]),
.I1(\Data_array_SWR[3]_0 [13]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [9]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [5]),
.O(\Q_reg[8]_0 [3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_5
(.I0(\Data_array_SWR[3]_0 [16]),
.I1(\Data_array_SWR[3]_0 [12]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [8]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [4]),
.O(\Q_reg[8]_0 [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_5
(.I0(\Data_array_SWR[3]_0 [15]),
.I1(\Data_array_SWR[3]_0 [11]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [7]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [3]),
.O(\Q_reg[8]_0 [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_5
(.I0(\Data_array_SWR[3]_0 [14]),
.I1(\Data_array_SWR[3]_0 [10]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [6]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [2]),
.O(\Q_reg[8]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[22]_i_1__8
(.I0(\Data_array_SWR[6]_4 ),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [0]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[2]));
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_2__0
(.I0(\Q_reg[8]_0 [11]),
.I1(\Q_reg[4]_1 [2]),
.I2(\Data_array_SWR[5]_3 [1]),
.O(\Data_array_SWR[6]_4 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_4
(.I0(\Data_array_SWR[3]_0 [13]),
.I1(\Data_array_SWR[3]_0 [9]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [5]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [1]),
.O(\Data_array_SWR[5]_3 [1]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\Q[24]_i_1__8
(.I0(\Data_array_SWR[6]_4 ),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [0]),
.O(\Q_reg[25]_0 [3]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT5 #(
.INIT(32'hB8FFB800))
\Q[25]_i_1__8
(.I0(\Q_reg[8]_0 [10]),
.I1(\Q_reg[4]_1 [2]),
.I2(\Data_array_SWR[5]_3 [0]),
.I3(Q[1]),
.I4(\Q_reg[4]_0 [1]),
.O(\Q_reg[25]_0 [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[13]_0 [6]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Q_reg[13]_0 [2]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [16]),
.O(\Q_reg[8]_0 [10]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_3__0
(.I0(\Data_array_SWR[3]_0 [12]),
.I1(\Data_array_SWR[3]_0 [8]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [4]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [0]),
.O(\Data_array_SWR[5]_3 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [0]),
.Q(\Data_array_SWR[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [10]),
.Q(\Data_array_SWR[3]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [11]),
.Q(\Data_array_SWR[3]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [12]),
.Q(\Data_array_SWR[3]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [13]),
.Q(\Data_array_SWR[3]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [14]),
.Q(\Data_array_SWR[3]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [15]),
.Q(\Data_array_SWR[3]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [16]),
.Q(\Data_array_SWR[3]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [17]),
.Q(\Data_array_SWR[3]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [18]),
.Q(\Q_reg[13]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [19]),
.Q(\Q_reg[13]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [1]),
.Q(\Data_array_SWR[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [20]),
.Q(\Q_reg[13]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [21]),
.Q(\Q_reg[13]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [22]),
.Q(\Q_reg[13]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [23]),
.Q(\Q_reg[13]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [24]),
.Q(\Q_reg[13]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [25]),
.Q(\Q_reg[13]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [2]),
.Q(\Data_array_SWR[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [3]),
.Q(\Data_array_SWR[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [4]),
.Q(\Data_array_SWR[3]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [5]),
.Q(\Data_array_SWR[3]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [6]),
.Q(\Data_array_SWR[3]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [7]),
.Q(\Data_array_SWR[3]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [8]),
.Q(\Data_array_SWR[3]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [9]),
.Q(\Data_array_SWR[3]_0 [9]));
endmodule
module ShiftRegister
(E,
Q,
\Q_reg[1]_0 ,
\Q_reg[1]_1 ,
\Q_reg[2]_0 ,
\FSM_sequential_state_reg_reg[0] ,
D,
CLK,
AR);
output [0:0]E;
output [5:0]Q;
output [0:0]\Q_reg[1]_0 ;
output [1:0]\Q_reg[1]_1 ;
input [0:0]\Q_reg[2]_0 ;
input [0:0]\FSM_sequential_state_reg_reg[0] ;
input [0:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[0] ;
wire [5:0]Q;
wire [0:0]\Q_reg[1]_0 ;
wire [1:0]\Q_reg[1]_1 ;
wire [0:0]\Q_reg[2]_0 ;
wire \Q_reg_n_0_[3] ;
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT2 #(
.INIT(4'h8))
\Q[0]_i_1__9
(.I0(Q[1]),
.I1(\Q_reg[2]_0 ),
.O(\Q_reg[1]_1 [0]));
LUT2 #(
.INIT(4'h2))
\Q[1]_i_1__7
(.I0(Q[1]),
.I1(\Q_reg[2]_0 ),
.O(\Q_reg[1]_1 [1]));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT2 #(
.INIT(4'hE))
\Q[25]_i_1__6
(.I0(Q[1]),
.I1(Q[3]),
.O(\Q_reg[1]_0 ));
LUT2 #(
.INIT(4'h2))
\Q[30]_i_1__6
(.I0(\Q_reg_n_0_[3] ),
.I1(Q[0]),
.O(E));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[1]),
.D(Q[1]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[2]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(\Q_reg_n_0_[3] ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[4]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[5]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(D),
.Q(Q[5]));
endmodule
module Simple_Subt
(D,
Q,
\Q_reg[26] ,
S);
output [7:0]D;
input [6:0]Q;
input [3:0]\Q_reg[26] ;
input [3:0]S;
wire [7:0]D;
wire [6:0]Q;
wire [3:0]\Q_reg[26] ;
wire [3:0]S;
wire Y_carry__0_n_1;
wire Y_carry__0_n_2;
wire Y_carry__0_n_3;
wire Y_carry_n_0;
wire Y_carry_n_1;
wire Y_carry_n_2;
wire Y_carry_n_3;
wire [3:3]NLW_Y_carry__0_CO_UNCONNECTED;
CARRY4 Y_carry
(.CI(1'b0),
.CO({Y_carry_n_0,Y_carry_n_1,Y_carry_n_2,Y_carry_n_3}),
.CYINIT(1'b1),
.DI(Q[3:0]),
.O(D[3:0]),
.S(\Q_reg[26] ));
CARRY4 Y_carry__0
(.CI(Y_carry_n_0),
.CO({NLW_Y_carry__0_CO_UNCONNECTED[3],Y_carry__0_n_1,Y_carry__0_n_2,Y_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Q[6:4]}),
.O(D[7:4]),
.S(S));
endmodule
module Up_counter
(Q,
max_tick_iter,
D,
\Q_reg[31] ,
\Q_reg[31]_0 ,
\Q_reg[26] ,
\Q_reg[31]_1 ,
\Q_reg[31]_2 ,
\Q_reg[31]_3 ,
\Q_reg[31]_4 ,
SR,
E,
CLK);
output [3:0]Q;
output max_tick_iter;
output [31:0]D;
output [31:0]\Q_reg[31] ;
output [31:0]\Q_reg[31]_0 ;
output [19:0]\Q_reg[26] ;
input [31:0]\Q_reg[31]_1 ;
input [31:0]\Q_reg[31]_2 ;
input [31:0]\Q_reg[31]_3 ;
input [31:0]\Q_reg[31]_4 ;
input [0:0]SR;
input [0:0]E;
input CLK;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [19:0]\Q_reg[26] ;
wire [31:0]\Q_reg[31] ;
wire [31:0]\Q_reg[31]_0 ;
wire [31:0]\Q_reg[31]_1 ;
wire [31:0]\Q_reg[31]_2 ;
wire [31:0]\Q_reg[31]_3 ;
wire [31:0]\Q_reg[31]_4 ;
wire [0:0]SR;
wire max_tick_iter;
wire [3:0]p_0_in;
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h8000))
\FSM_sequential_state_reg[2]_i_2
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(max_tick_iter));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7465))
\Q[0]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.O(\Q_reg[26] [0]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[0]_i_1__0
(.I0(\Q_reg[31]_1 [0]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [0]),
.O(D[0]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[0]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [0]),
.O(\Q_reg[31]_0 [0]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[0]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [0]),
.O(\Q_reg[31] [0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h7445))
\Q[10]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[1]),
.O(\Q_reg[26] [7]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[10]_i_1__0
(.I0(\Q_reg[31]_1 [10]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [10]),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[10]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [10]),
.O(\Q_reg[31] [10]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[10]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [10]),
.O(\Q_reg[31]_0 [10]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h55EF))
\Q[11]_i_1
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[3]),
.O(\Q_reg[26] [8]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[11]_i_1__0
(.I0(\Q_reg[31]_1 [11]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [11]),
.O(D[11]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[11]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [11]),
.O(\Q_reg[31]_0 [11]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[11]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [11]),
.O(\Q_reg[31] [11]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h6474))
\Q[12]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.O(\Q_reg[26] [9]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[12]_i_1__0
(.I0(\Q_reg[31]_1 [12]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [12]),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[12]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [12]),
.O(\Q_reg[31] [12]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[12]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [12]),
.O(\Q_reg[31]_0 [12]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[13]_i_1
(.I0(\Q_reg[31]_1 [13]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [13]),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[13]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [13]),
.O(\Q_reg[31] [13]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[13]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [13]),
.O(\Q_reg[31]_0 [13]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h54BE))
\Q[14]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.O(\Q_reg[26] [10]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[14]_i_1__0
(.I0(\Q_reg[31]_1 [14]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [14]),
.O(D[14]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[14]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [14]),
.O(\Q_reg[31] [14]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[14]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [14]),
.O(\Q_reg[31]_0 [14]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[15]_i_1
(.I0(\Q_reg[31]_1 [15]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [15]),
.O(D[15]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[15]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [15]),
.O(\Q_reg[31]_0 [15]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[15]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [15]),
.O(\Q_reg[31] [15]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[16]_i_1
(.I0(\Q_reg[31]_1 [16]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [16]),
.O(D[16]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[16]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [16]),
.O(\Q_reg[31] [16]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[16]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [16]),
.O(\Q_reg[31]_0 [16]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h5B))
\Q[16]_i_1__7
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[2]),
.O(\Q_reg[26] [11]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[17]_i_1
(.I0(\Q_reg[31]_1 [17]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [17]),
.O(D[17]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[17]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [17]),
.O(\Q_reg[31] [17]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[17]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [17]),
.O(\Q_reg[31]_0 [17]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[18]_i_1
(.I0(\Q_reg[31]_1 [18]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [18]),
.O(D[18]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[18]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [18]),
.O(\Q_reg[31]_0 [18]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[18]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [18]),
.O(\Q_reg[31] [18]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h5E))
\Q[18]_i_1__7
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.O(\Q_reg[26] [12]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[19]_i_1
(.I0(\Q_reg[31]_1 [19]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [19]),
.O(D[19]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[19]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [19]),
.O(\Q_reg[31] [19]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[19]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [19]),
.O(\Q_reg[31]_0 [19]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[1]_i_1__0
(.I0(\Q_reg[31]_1 [1]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[1]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [1]),
.O(\Q_reg[31] [1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h55AB))
\Q[1]_i_1__12
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[2]),
.O(\Q_reg[26] [1]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[1]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [1]),
.O(\Q_reg[31]_0 [1]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[20]_i_1
(.I0(\Q_reg[31]_1 [20]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [20]),
.O(D[20]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[20]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [20]),
.O(\Q_reg[31] [20]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[20]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [20]),
.O(\Q_reg[31]_0 [20]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h5E))
\Q[20]_i_1__7
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[2]),
.O(\Q_reg[26] [13]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h55FE))
\Q[21]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(\Q_reg[26] [14]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[21]_i_1__0
(.I0(\Q_reg[31]_1 [21]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [21]),
.O(D[21]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[21]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [21]),
.O(\Q_reg[31]_0 [21]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[21]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [21]),
.O(\Q_reg[31] [21]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h7))
\Q[22]_i_1
(.I0(Q[3]),
.I1(Q[2]),
.O(\Q_reg[26] [15]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[22]_i_1__0
(.I0(\Q_reg[31]_1 [22]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [22]),
.O(D[22]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[22]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [22]),
.O(\Q_reg[31]_0 [22]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[22]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [22]),
.O(\Q_reg[31] [22]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[23]_i_1
(.I0(\Q_reg[31]_1 [23]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [23]),
.O(D[23]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[23]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [23]),
.O(\Q_reg[31]_0 [23]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[23]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [23]),
.O(\Q_reg[31] [23]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h6A))
\Q[23]_i_1__8
(.I0(Q[0]),
.I1(Q[2]),
.I2(Q[3]),
.O(\Q_reg[26] [16]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h708F))
\Q[24]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[1]),
.O(\Q_reg[26] [17]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[24]_i_1__0
(.I0(\Q_reg[31]_1 [24]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [24]),
.O(D[24]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[24]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [24]),
.O(\Q_reg[31] [24]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[24]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [24]),
.O(\Q_reg[31]_0 [24]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h0787))
\Q[25]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\Q_reg[26] [18]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[25]_i_1__0
(.I0(\Q_reg[31]_1 [25]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [25]),
.O(D[25]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[25]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [25]),
.O(\Q_reg[31] [25]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[25]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [25]),
.O(\Q_reg[31]_0 [25]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h007F))
\Q[26]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[3]),
.O(\Q_reg[26] [19]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[26]_i_1__0
(.I0(\Q_reg[31]_1 [26]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [26]),
.O(D[26]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[26]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [26]),
.O(\Q_reg[31] [26]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[26]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [26]),
.O(\Q_reg[31]_0 [26]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[27]_i_1
(.I0(\Q_reg[31]_1 [27]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [27]),
.O(D[27]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[27]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [27]),
.O(\Q_reg[31] [27]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[27]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [27]),
.O(\Q_reg[31]_0 [27]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[28]_i_1
(.I0(\Q_reg[31]_1 [28]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [28]),
.O(D[28]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[28]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [28]),
.O(\Q_reg[31] [28]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[28]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [28]),
.O(\Q_reg[31]_0 [28]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[29]_i_1__0
(.I0(\Q_reg[31]_1 [29]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [29]),
.O(D[29]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[29]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [29]),
.O(\Q_reg[31] [29]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[29]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [29]),
.O(\Q_reg[31]_0 [29]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[2]_i_1
(.I0(\Q_reg[31]_1 [2]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [2]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[2]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [2]),
.O(\Q_reg[31] [2]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[2]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [2]),
.O(\Q_reg[31]_0 [2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0858))
\Q[2]_i_1__10
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\Q_reg[26] [2]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[30]_i_1
(.I0(\Q_reg[31]_1 [30]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [30]),
.O(D[30]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[30]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [30]),
.O(\Q_reg[31]_0 [30]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[30]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [30]),
.O(\Q_reg[31] [30]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[31]_i_1__3
(.I0(\Q_reg[31]_1 [31]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [31]),
.O(D[31]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[31]_i_1__4
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(\Q_reg[31]_4 [31]),
.O(\Q_reg[31]_0 [31]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[31]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(\Q_reg[31]_3 [31]),
.O(\Q_reg[31] [31]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[3]_i_1
(.I0(\Q_reg[31]_1 [3]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[3]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [3]),
.O(\Q_reg[31] [3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[3]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [3]),
.O(\Q_reg[31]_0 [3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h01F3))
\Q[4]_i_1
(.I0(Q[0]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[2]),
.O(\Q_reg[26] [3]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[4]_i_1__0
(.I0(\Q_reg[31]_1 [4]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [4]),
.O(D[4]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[4]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [4]),
.O(\Q_reg[31]_0 [4]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[4]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [4]),
.O(\Q_reg[31] [4]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[5]_i_1
(.I0(\Q_reg[31]_1 [5]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[5]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [5]),
.O(\Q_reg[31] [5]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[5]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [5]),
.O(\Q_reg[31]_0 [5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h5443))
\Q[6]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(\Q_reg[26] [4]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[6]_i_1__1
(.I0(\Q_reg[31]_1 [6]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[6]_i_1__2
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [6]),
.O(\Q_reg[31] [6]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[6]_i_1__3
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [6]),
.O(\Q_reg[31]_0 [6]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[7]_i_1
(.I0(\Q_reg[31]_1 [7]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[7]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [7]),
.O(\Q_reg[31] [7]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[7]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [7]),
.O(\Q_reg[31]_0 [7]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT1 #(
.INIT(2'h1))
\Q[8]_i_1
(.I0(Q[2]),
.O(\Q_reg[26] [5]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[8]_i_1__0
(.I0(\Q_reg[31]_1 [8]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [8]),
.O(D[8]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[8]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [8]),
.O(\Q_reg[31]_0 [8]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[8]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [8]),
.O(\Q_reg[31] [8]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h55BF))
\Q[9]_i_1
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[3]),
.O(\Q_reg[26] [6]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[9]_i_1__0
(.I0(\Q_reg[31]_1 [9]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [9]),
.O(D[9]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[9]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [9]),
.O(\Q_reg[31]_0 [9]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[9]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [9]),
.O(\Q_reg[31] [9]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT1 #(
.INIT(2'h1))
\temp[0]_i_1
(.I0(Q[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h6))
\temp[1]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h78))
\temp[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6AAA))
\temp[3]_i_2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.O(p_0_in[3]));
FDRE #(
.INIT(1'b0))
\temp_reg[0]
(.C(CLK),
.CE(E),
.D(p_0_in[0]),
.Q(Q[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\temp_reg[1]
(.C(CLK),
.CE(E),
.D(p_0_in[1]),
.Q(Q[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\temp_reg[2]
(.C(CLK),
.CE(E),
.D(p_0_in[2]),
.Q(Q[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\temp_reg[3]
(.C(CLK),
.CE(E),
.D(p_0_in[3]),
.Q(Q[3]),
.R(SR));
endmodule
(* ORIG_REF_NAME = "Up_counter" *)
module Up_counter__parameterized0
(E,
cont_var_out,
\Q_reg[31] ,
\Q_reg[31]_0 ,
D,
\Q_reg[31]_1 ,
op_add_subt,
ready_add_subt,
Q,
\Q_reg[31]_2 ,
\Q_reg[29] ,
\Q_reg[31]_3 ,
\Q_reg[31]_4 ,
\Q_reg[31]_5 ,
d_ff3_sign_out,
out,
rst_IBUF,
CLK);
output [0:0]E;
output [1:0]cont_var_out;
output [0:0]\Q_reg[31] ;
output [0:0]\Q_reg[31]_0 ;
output [31:0]D;
output [31:0]\Q_reg[31]_1 ;
output op_add_subt;
input ready_add_subt;
input [31:0]Q;
input [31:0]\Q_reg[31]_2 ;
input [20:0]\Q_reg[29] ;
input [31:0]\Q_reg[31]_3 ;
input [31:0]\Q_reg[31]_4 ;
input [31:0]\Q_reg[31]_5 ;
input d_ff3_sign_out;
input [1:0]out;
input rst_IBUF;
input CLK;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
wire [20:0]\Q_reg[29] ;
wire [0:0]\Q_reg[31] ;
wire [0:0]\Q_reg[31]_0 ;
wire [31:0]\Q_reg[31]_1 ;
wire [31:0]\Q_reg[31]_2 ;
wire [31:0]\Q_reg[31]_3 ;
wire [31:0]\Q_reg[31]_4 ;
wire [31:0]\Q_reg[31]_5 ;
wire [1:0]cont_var_out;
wire d_ff3_sign_out;
wire op_add_subt;
wire [1:0]out;
wire ready_add_subt;
wire rst_IBUF;
wire \temp[0]_i_1_n_0 ;
wire \temp[1]_i_1_n_0 ;
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[0]_i_1__3
(.I0(\Q_reg[29] [0]),
.I1(Q[0]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [0]),
.I4(cont_var_out[1]),
.O(D[0]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[0]_i_1__4
(.I0(\Q_reg[31]_3 [0]),
.I1(\Q_reg[31]_4 [0]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [0]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [0]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h6))
\Q[0]_i_1__6
(.I0(cont_var_out[0]),
.I1(d_ff3_sign_out),
.O(op_add_subt));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[10]_i_1__3
(.I0(\Q_reg[29] [7]),
.I1(Q[10]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [10]),
.I4(cont_var_out[1]),
.O(D[10]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[10]_i_1__4
(.I0(\Q_reg[31]_3 [10]),
.I1(\Q_reg[31]_4 [10]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [10]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [10]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[11]_i_1__3
(.I0(\Q_reg[29] [8]),
.I1(Q[11]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [11]),
.I4(cont_var_out[1]),
.O(D[11]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[11]_i_1__4
(.I0(\Q_reg[31]_3 [11]),
.I1(\Q_reg[31]_4 [11]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [11]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [11]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[12]_i_1__3
(.I0(\Q_reg[29] [9]),
.I1(Q[12]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [12]),
.I4(cont_var_out[1]),
.O(D[12]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[12]_i_1__4
(.I0(\Q_reg[31]_3 [12]),
.I1(\Q_reg[31]_4 [12]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [12]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [12]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[13]_i_1__2
(.I0(\Q_reg[29] [12]),
.I1(Q[13]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [13]),
.I4(cont_var_out[1]),
.O(D[13]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[13]_i_1__3
(.I0(\Q_reg[31]_3 [13]),
.I1(\Q_reg[31]_4 [13]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [13]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [13]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[14]_i_1__3
(.I0(\Q_reg[29] [10]),
.I1(Q[14]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [14]),
.I4(cont_var_out[1]),
.O(D[14]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[14]_i_1__4
(.I0(\Q_reg[31]_3 [14]),
.I1(\Q_reg[31]_4 [14]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [14]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [14]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[15]_i_1__2
(.I0(\Q_reg[29] [13]),
.I1(Q[15]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [15]),
.I4(cont_var_out[1]),
.O(D[15]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[15]_i_1__3
(.I0(\Q_reg[31]_3 [15]),
.I1(\Q_reg[31]_4 [15]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [15]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [15]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[16]_i_1__2
(.I0(\Q_reg[29] [11]),
.I1(Q[16]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [16]),
.I4(cont_var_out[1]),
.O(D[16]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[16]_i_1__3
(.I0(\Q_reg[31]_3 [16]),
.I1(\Q_reg[31]_4 [16]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [16]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [16]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[17]_i_1__2
(.I0(\Q_reg[29] [13]),
.I1(Q[17]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [17]),
.I4(cont_var_out[1]),
.O(D[17]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[17]_i_1__3
(.I0(\Q_reg[31]_3 [17]),
.I1(\Q_reg[31]_4 [17]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [17]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [17]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[18]_i_1__2
(.I0(\Q_reg[29] [12]),
.I1(Q[18]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [18]),
.I4(cont_var_out[1]),
.O(D[18]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[18]_i_1__3
(.I0(\Q_reg[31]_3 [18]),
.I1(\Q_reg[31]_4 [18]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [18]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [18]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[19]_i_1__2
(.I0(\Q_reg[29] [15]),
.I1(Q[19]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [19]),
.I4(cont_var_out[1]),
.O(D[19]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[19]_i_1__3
(.I0(\Q_reg[31]_3 [19]),
.I1(\Q_reg[31]_4 [19]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [19]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [19]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[1]_i_1__3
(.I0(\Q_reg[29] [1]),
.I1(Q[1]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [1]),
.I4(cont_var_out[1]),
.O(D[1]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[1]_i_1__4
(.I0(\Q_reg[31]_3 [1]),
.I1(\Q_reg[31]_4 [1]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [1]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [1]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[20]_i_1__2
(.I0(\Q_reg[29] [13]),
.I1(Q[20]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [20]),
.I4(cont_var_out[1]),
.O(D[20]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[20]_i_1__3
(.I0(\Q_reg[31]_3 [20]),
.I1(\Q_reg[31]_4 [20]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [20]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [20]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[21]_i_1__3
(.I0(\Q_reg[29] [14]),
.I1(Q[21]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [21]),
.I4(cont_var_out[1]),
.O(D[21]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[21]_i_1__4
(.I0(\Q_reg[31]_3 [21]),
.I1(\Q_reg[31]_4 [21]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [21]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [21]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[22]_i_1__3
(.I0(\Q_reg[29] [15]),
.I1(Q[22]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [22]),
.I4(cont_var_out[1]),
.O(D[22]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[22]_i_1__4
(.I0(\Q_reg[31]_3 [22]),
.I1(\Q_reg[31]_4 [22]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [22]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [22]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[23]_i_1__2
(.I0(\Q_reg[29] [16]),
.I1(Q[23]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [23]),
.I4(cont_var_out[1]),
.O(D[23]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[23]_i_1__3
(.I0(\Q_reg[31]_3 [23]),
.I1(\Q_reg[31]_4 [23]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [23]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [23]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[24]_i_1__3
(.I0(\Q_reg[29] [17]),
.I1(Q[24]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [24]),
.I4(cont_var_out[1]),
.O(D[24]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[24]_i_1__4
(.I0(\Q_reg[31]_3 [24]),
.I1(\Q_reg[31]_4 [24]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [24]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [24]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[25]_i_1__3
(.I0(\Q_reg[29] [18]),
.I1(Q[25]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [25]),
.I4(cont_var_out[1]),
.O(D[25]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[25]_i_1__4
(.I0(\Q_reg[31]_3 [25]),
.I1(\Q_reg[31]_4 [25]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [25]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [25]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[26]_i_1__3
(.I0(\Q_reg[29] [19]),
.I1(Q[26]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [26]),
.I4(cont_var_out[1]),
.O(D[26]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[26]_i_1__4
(.I0(\Q_reg[31]_3 [26]),
.I1(\Q_reg[31]_4 [26]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [26]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [26]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[27]_i_1__2
(.I0(\Q_reg[29] [20]),
.I1(Q[27]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [27]),
.I4(cont_var_out[1]),
.O(D[27]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[27]_i_1__3
(.I0(\Q_reg[31]_3 [27]),
.I1(\Q_reg[31]_4 [27]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [27]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [27]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[28]_i_1__2
(.I0(\Q_reg[29] [20]),
.I1(Q[28]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [28]),
.I4(cont_var_out[1]),
.O(D[28]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[28]_i_1__3
(.I0(\Q_reg[31]_3 [28]),
.I1(\Q_reg[31]_4 [28]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [28]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [28]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[29]_i_1__3
(.I0(\Q_reg[29] [20]),
.I1(Q[29]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [29]),
.I4(cont_var_out[1]),
.O(D[29]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[29]_i_1__4
(.I0(\Q_reg[31]_3 [29]),
.I1(\Q_reg[31]_4 [29]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [29]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [29]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[2]_i_1__2
(.I0(\Q_reg[29] [2]),
.I1(Q[2]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [2]),
.I4(cont_var_out[1]),
.O(D[2]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[2]_i_1__3
(.I0(\Q_reg[31]_3 [2]),
.I1(\Q_reg[31]_4 [2]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [2]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [2]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h3088))
\Q[30]_i_1__2
(.I0(Q[30]),
.I1(cont_var_out[0]),
.I2(\Q_reg[31]_2 [30]),
.I3(cont_var_out[1]),
.O(D[30]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[30]_i_1__3
(.I0(\Q_reg[31]_3 [30]),
.I1(\Q_reg[31]_4 [30]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [30]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [30]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'h08))
\Q[31]_i_1__0
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(cont_var_out[0]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'h04))
\Q[31]_i_1__1
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(cont_var_out[0]),
.O(\Q_reg[31] ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'h40))
\Q[31]_i_1__2
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(cont_var_out[0]),
.O(\Q_reg[31]_0 ));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[31]_i_1__5
(.I0(\Q_reg[31]_3 [31]),
.I1(\Q_reg[31]_4 [31]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [31]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [31]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h3088))
\Q[31]_i_2__1
(.I0(Q[31]),
.I1(cont_var_out[0]),
.I2(\Q_reg[31]_2 [31]),
.I3(cont_var_out[1]),
.O(D[31]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[3]_i_1__2
(.I0(\Q_reg[29] [11]),
.I1(Q[3]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [3]),
.I4(cont_var_out[1]),
.O(D[3]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[3]_i_1__3
(.I0(\Q_reg[31]_3 [3]),
.I1(\Q_reg[31]_4 [3]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [3]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [3]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[4]_i_1__3
(.I0(\Q_reg[29] [3]),
.I1(Q[4]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [4]),
.I4(cont_var_out[1]),
.O(D[4]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[4]_i_1__4
(.I0(\Q_reg[31]_3 [4]),
.I1(\Q_reg[31]_4 [4]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [4]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [4]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[5]_i_1__2
(.I0(\Q_reg[29] [10]),
.I1(Q[5]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [5]),
.I4(cont_var_out[1]),
.O(D[5]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[5]_i_1__3
(.I0(\Q_reg[31]_3 [5]),
.I1(\Q_reg[31]_4 [5]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [5]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [5]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[6]_i_1__4
(.I0(\Q_reg[29] [4]),
.I1(Q[6]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [6]),
.I4(cont_var_out[1]),
.O(D[6]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[6]_i_1__5
(.I0(\Q_reg[31]_3 [6]),
.I1(\Q_reg[31]_4 [6]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [6]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [6]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[7]_i_1__2
(.I0(\Q_reg[29] [8]),
.I1(Q[7]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [7]),
.I4(cont_var_out[1]),
.O(D[7]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[7]_i_1__3
(.I0(\Q_reg[31]_3 [7]),
.I1(\Q_reg[31]_4 [7]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [7]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [7]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[8]_i_1__3
(.I0(\Q_reg[29] [5]),
.I1(Q[8]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [8]),
.I4(cont_var_out[1]),
.O(D[8]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[8]_i_1__4
(.I0(\Q_reg[31]_3 [8]),
.I1(\Q_reg[31]_4 [8]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [8]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [8]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[9]_i_1__3
(.I0(\Q_reg[29] [6]),
.I1(Q[9]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [9]),
.I4(cont_var_out[1]),
.O(D[9]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[9]_i_1__4
(.I0(\Q_reg[31]_3 [9]),
.I1(\Q_reg[31]_4 [9]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [9]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [9]));
LUT5 #(
.INIT(32'h0000559A))
\temp[0]_i_1
(.I0(cont_var_out[0]),
.I1(out[0]),
.I2(out[1]),
.I3(ready_add_subt),
.I4(rst_IBUF),
.O(\temp[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000006656AAAA))
\temp[1]_i_1
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(out[1]),
.I3(out[0]),
.I4(cont_var_out[0]),
.I5(rst_IBUF),
.O(\temp[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\temp_reg[0]
(.C(CLK),
.CE(1'b1),
.D(\temp[0]_i_1_n_0 ),
.Q(cont_var_out[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_reg[1]
(.C(CLK),
.CE(1'b1),
.D(\temp[1]_i_1_n_0 ),
.Q(cont_var_out[1]),
.R(1'b0));
endmodule
module d_ff_en
(d_ff1_operation_out,
E,
operation_IBUF,
CLK,
\FSM_sequential_state_reg_reg[1] );
output d_ff1_operation_out;
input [0:0]E;
input operation_IBUF;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire d_ff1_operation_out;
wire operation_IBUF;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(operation_IBUF),
.Q(d_ff1_operation_out));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en_0
(d_ff3_sign_out,
\FSM_sequential_state_reg_reg[2] ,
Q,
CLK,
\FSM_sequential_state_reg_reg[1] );
output d_ff3_sign_out;
input [0:0]\FSM_sequential_state_reg_reg[2] ;
input [0:0]Q;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [0:0]\FSM_sequential_state_reg_reg[2] ;
wire [0:0]Q;
wire d_ff3_sign_out;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(Q),
.Q(d_ff3_sign_out));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized0
(D,
d_ff1_operation_out,
Q,
\Q_reg[31] ,
E,
\shift_region_flag[1] ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]D;
input d_ff1_operation_out;
input [31:0]Q;
input [31:0]\Q_reg[31] ;
input [0:0]E;
input [1:0]\shift_region_flag[1] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [31:0]\Q_reg[31] ;
wire d_ff1_operation_out;
wire [1:0]d_ff1_shift_region_flag_out;
wire [1:0]\shift_region_flag[1] ;
LUT5 #(
.INIT(32'hACCACAAC))
\Q[0]_i_1__5
(.I0(Q[0]),
.I1(\Q_reg[31] [0]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[0]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[10]_i_1__5
(.I0(Q[10]),
.I1(\Q_reg[31] [10]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[10]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[11]_i_1__5
(.I0(Q[11]),
.I1(\Q_reg[31] [11]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[11]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[12]_i_1__5
(.I0(Q[12]),
.I1(\Q_reg[31] [12]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[12]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[13]_i_1__4
(.I0(Q[13]),
.I1(\Q_reg[31] [13]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[13]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[14]_i_1__5
(.I0(Q[14]),
.I1(\Q_reg[31] [14]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[14]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[15]_i_1__4
(.I0(Q[15]),
.I1(\Q_reg[31] [15]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[15]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[16]_i_1__4
(.I0(Q[16]),
.I1(\Q_reg[31] [16]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[16]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[17]_i_1__4
(.I0(Q[17]),
.I1(\Q_reg[31] [17]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[17]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[18]_i_1__4
(.I0(Q[18]),
.I1(\Q_reg[31] [18]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[18]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[19]_i_1__4
(.I0(Q[19]),
.I1(\Q_reg[31] [19]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[19]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[1]_i_1__5
(.I0(Q[1]),
.I1(\Q_reg[31] [1]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[1]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[20]_i_1__4
(.I0(Q[20]),
.I1(\Q_reg[31] [20]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[20]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[21]_i_1__5
(.I0(Q[21]),
.I1(\Q_reg[31] [21]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[21]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[22]_i_1__5
(.I0(Q[22]),
.I1(\Q_reg[31] [22]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[22]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[23]_i_1__4
(.I0(Q[23]),
.I1(\Q_reg[31] [23]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[23]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[24]_i_1__5
(.I0(Q[24]),
.I1(\Q_reg[31] [24]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[24]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[25]_i_1__5
(.I0(Q[25]),
.I1(\Q_reg[31] [25]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[25]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[26]_i_1__5
(.I0(Q[26]),
.I1(\Q_reg[31] [26]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[26]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[27]_i_1__4
(.I0(Q[27]),
.I1(\Q_reg[31] [27]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[27]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[28]_i_1__4
(.I0(Q[28]),
.I1(\Q_reg[31] [28]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[28]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[29]_i_1__5
(.I0(Q[29]),
.I1(\Q_reg[31] [29]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[29]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[2]_i_1__4
(.I0(Q[2]),
.I1(\Q_reg[31] [2]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[2]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[30]_i_1__4
(.I0(Q[30]),
.I1(\Q_reg[31] [30]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[30]));
LUT5 #(
.INIT(32'hE77181E8))
\Q[31]_i_2__2
(.I0(d_ff1_operation_out),
.I1(d_ff1_shift_region_flag_out[1]),
.I2(Q[31]),
.I3(d_ff1_shift_region_flag_out[0]),
.I4(\Q_reg[31] [31]),
.O(D[31]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[3]_i_1__4
(.I0(Q[3]),
.I1(\Q_reg[31] [3]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[3]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[4]_i_1__5
(.I0(Q[4]),
.I1(\Q_reg[31] [4]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[4]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[5]_i_1__4
(.I0(Q[5]),
.I1(\Q_reg[31] [5]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[5]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[6]_i_1__6
(.I0(Q[6]),
.I1(\Q_reg[31] [6]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[6]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[7]_i_1__4
(.I0(Q[7]),
.I1(\Q_reg[31] [7]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[7]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[8]_i_1__5
(.I0(Q[8]),
.I1(\Q_reg[31] [8]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[8]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[9]_i_1__5
(.I0(Q[9]),
.I1(\Q_reg[31] [9]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\shift_region_flag[1] [0]),
.Q(d_ff1_shift_region_flag_out[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\shift_region_flag[1] [1]),
.Q(d_ff1_shift_region_flag_out[1]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized1
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized10
(Q,
E,
\Q_reg[31]_0 ,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]\Q_reg[31]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire [31:0]Q;
wire [31:0]\Q_reg[31]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized11
(Q,
E,
D,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized2
(S,
Q,
\Q_reg[26]_0 ,
\temp_reg[3] ,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [3:0]S;
output [31:0]Q;
output [3:0]\Q_reg[26]_0 ;
input [3:0]\temp_reg[3] ;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [3:0]\Q_reg[26]_0 ;
wire [3:0]S;
wire [3:0]\temp_reg[3] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_1
(.I0(Q[30]),
.O(S[3]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_2
(.I0(Q[29]),
.O(S[2]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_3
(.I0(Q[28]),
.O(S[1]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_4
(.I0(Q[27]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_1
(.I0(Q[26]),
.I1(\temp_reg[3] [3]),
.O(\Q_reg[26]_0 [3]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_2
(.I0(Q[25]),
.I1(\temp_reg[3] [2]),
.O(\Q_reg[26]_0 [2]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_3
(.I0(Q[24]),
.I1(\temp_reg[3] [1]),
.O(\Q_reg[26]_0 [1]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_4
(.I0(Q[23]),
.I1(\temp_reg[3] [0]),
.O(\Q_reg[26]_0 [0]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized3
(Q,
D,
\temp_reg[3] ,
E,
\temp_reg[3]_0 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
output [7:0]D;
input [3:0]\temp_reg[3] ;
input [0:0]E;
input [31:0]\temp_reg[3]_0 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [7:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire \Q[26]_i_2_n_0 ;
wire \Q[26]_i_3_n_0 ;
wire \Q[26]_i_4_n_0 ;
wire \Q[26]_i_5_n_0 ;
wire \Q[30]_i_2_n_0 ;
wire \Q[30]_i_3_n_0 ;
wire \Q[30]_i_4_n_0 ;
wire \Q[30]_i_5_n_0 ;
wire \Q_reg[26]_i_1_n_0 ;
wire \Q_reg[26]_i_1_n_1 ;
wire \Q_reg[26]_i_1_n_2 ;
wire \Q_reg[26]_i_1_n_3 ;
wire \Q_reg[30]_i_1_n_1 ;
wire \Q_reg[30]_i_1_n_2 ;
wire \Q_reg[30]_i_1_n_3 ;
wire [3:0]\temp_reg[3] ;
wire [31:0]\temp_reg[3]_0 ;
wire [3:3]\NLW_Q_reg[30]_i_1_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h9))
\Q[26]_i_2
(.I0(Q[26]),
.I1(\temp_reg[3] [3]),
.O(\Q[26]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[26]_i_3
(.I0(Q[25]),
.I1(\temp_reg[3] [2]),
.O(\Q[26]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[26]_i_4
(.I0(Q[24]),
.I1(\temp_reg[3] [1]),
.O(\Q[26]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[26]_i_5
(.I0(Q[23]),
.I1(\temp_reg[3] [0]),
.O(\Q[26]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_2
(.I0(Q[30]),
.O(\Q[30]_i_2_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_3
(.I0(Q[29]),
.O(\Q[30]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_4
(.I0(Q[28]),
.O(\Q[30]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_5
(.I0(Q[27]),
.O(\Q[30]_i_5_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [26]),
.Q(Q[26]));
CARRY4 \Q_reg[26]_i_1
(.CI(1'b0),
.CO({\Q_reg[26]_i_1_n_0 ,\Q_reg[26]_i_1_n_1 ,\Q_reg[26]_i_1_n_2 ,\Q_reg[26]_i_1_n_3 }),
.CYINIT(1'b1),
.DI(Q[26:23]),
.O(D[3:0]),
.S({\Q[26]_i_2_n_0 ,\Q[26]_i_3_n_0 ,\Q[26]_i_4_n_0 ,\Q[26]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [30]),
.Q(Q[30]));
CARRY4 \Q_reg[30]_i_1
(.CI(\Q_reg[26]_i_1_n_0 ),
.CO({\NLW_Q_reg[30]_i_1_CO_UNCONNECTED [3],\Q_reg[30]_i_1_n_1 ,\Q_reg[30]_i_1_n_2 ,\Q_reg[30]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,Q[29:27]}),
.O(D[7:4]),
.S({\Q[30]_i_2_n_0 ,\Q[30]_i_3_n_0 ,\Q[30]_i_4_n_0 ,\Q[30]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized4
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized5
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized6
(Q,
\FSM_sequential_state_reg_reg[2] ,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]\FSM_sequential_state_reg_reg[2] ;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [0:0]\FSM_sequential_state_reg_reg[2] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized7
(Q,
E,
CLK,
\FSM_sequential_state_reg_reg[1] ,
D);
output [20:0]Q;
input [0:0]E;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [19:0]D;
wire CLK;
wire [19:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [20:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(1'b1),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized8
(Q,
E,
\Q_reg[31]_0 ,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]\Q_reg[31]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire [31:0]Q;
wire [31:0]\Q_reg[31]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized9
(Q,
E,
\Q_reg[31]_0 ,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]\Q_reg[31]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire [31:0]Q;
wire [31:0]\Q_reg[31]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [9]),
.Q(Q[9]));
endmodule
module sgn_result
(D,
\Q_reg[30] ,
Q,
intAS,
CO,
\Q_reg[31] );
output [0:0]D;
input [0:0]\Q_reg[30] ;
input [0:0]Q;
input intAS;
input [0:0]CO;
input [0:0]\Q_reg[31] ;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]Q;
wire [0:0]\Q_reg[30] ;
wire [0:0]\Q_reg[31] ;
wire intAS;
LUT5 #(
.INIT(32'hFF3C0014))
sgn_result_o
(.I0(\Q_reg[30] ),
.I1(Q),
.I2(intAS),
.I3(CO),
.I4(\Q_reg[31] ),
.O(D));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* File: reg_sprs.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Description:
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[OV]£º±íʾÒç³ö£¬ÔËËã½á¹û³¬³ö·¶Î§¡£XER[OV] = 1 indicates overflow. For arithmetic operations,
this occurs when an operation has a carry-in to the most-significant bit of the result that
does not equal the carry-out of the most-significant bit (that is, the exclusive-or of the
carry-in and the carry-out is 1).
Multiply and divide instructions (mullwo, mullwo., divwo, divwo., divwuo, divwuo)䶨Òå
[CA]£º±íʾ½øλ¡£
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c£©¼ì²éSPRs·ÃÎÊÏà¹ØµÄ´¦ÀíÆ÷״̬£¬·¢³öÏìÓ¦ÖжÏÇëÇósig_svm_check
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Original ppc405 register sets excluding GPRs including:
a. MSR/CR
b. SPRs:
b.1) Branch Control
CTR, LR - User
b.2) Fixed-point Exception
XER - User
b.3) Interrupts and Exceptions (implemented at except module)
DEAR, ESR, EVPR, MCSR, SRR0, SRR1, SRR2, SRR3 - Privileged
b.4) General-Purpose SPR
USPRG0 - User
SPRG0, SPRG1, SPRG2, SPRG3 - Privileged
SPRG4, SPRG5, SPRG6, SPRG7 - User read, privileged write
b.5) Timer Facilities at timer units
TBL, TBU - Privileged, write only
PIT, TCR, TSR - Priveleged
Currently, pippo core implemented SPRs above.
* Following SPRs are implemented by core-out units
b.6) Processor Version (Read only)
PVR - Privileged, read-only
* c.7) Configuration (MMU/Cache)
* CCR0, CCR1 - Privileged
* c.8) Storage Attributes Control Registers at mmu and cache units, for memory access at real-address mode
* DCCR, DCWR, ICCR, SGR, SLER, SU0R
* c.9) Zone Protection at mmu/mpu units
* ZPR
* c.10) Debug at debug unit
* DAC1, DAC2
* DBCR0, DBCR1
* DBSR
* DVC1, DVC2
* IAC1, IAC2, IAC3, IAC4
* ICDBDR
* Task.I
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*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module pippo_sprs(
// Clk & Rst
clk, rst,
reg_uops, reg_addr, dat_i, spr_wb_dat,
carry, so,
so_new, so_we,
ov_new, ov_we,
ca_new, ca_we,
cr_addr,
cr,
cr_alu, cr_alu_we,
cr0_lsu, cr0_lsu_we,
msr,
msr_except, msr_expwe,
sig_svm_check,
dear, esr, evpr, mcsr, srr0, srr1, srr2, srr3,
dear_we, esr_we, evpr_we, mcsr_we, srr0_we, srr1_we, srr2_we, srr3_we,
eir, eir_we,
lr, ctr,
lr_we, ctr_we,
tbl, tbu, pit, tsr, tcr,
tbl_we, tbu_we, pit_we, tsr_we, tcr_we,
dsurx, dsutx, dsuctrl, dsusta,
dsurx_we, dsutx_we, dsuctrl_we, dsusta_we,
spr_dat_wr_o
);
parameter width = `OPERAND_WIDTH;
//
// I/O Ports
//
input clk;
input rst;
//
// Pipeline interface
//
input [`REGOP_WIDTH-1:0] reg_uops;
input [9:0] reg_addr;
input [31:0] dat_i;
input [14:0] cr_addr; // cr source selector, connect from ex_inst
output [31:0] spr_wb_dat; // write-back data for mfspr-class instructions
//
// CR output for bpu, alu
//
output [31:0] cr;
//
// ALU Interface
//
input so_new;
input so_we;
input ov_new;
input ov_we;
input ca_new;
input ca_we;
//
// LSU Interface
//
// cr0 update for atomic instructions
input [3:0] cr0_lsu;
input cr0_lsu_we;
//
// ALU Interface
//
// CR
input [31:0] cr_alu;
input [7:0] cr_alu_we;
// XER/CR update information for ALU
output carry; // XER[CY]
output so;
//
// Interface with LR/CTR at BPU
//
input [31:0] lr;
input [31:0] ctr;
output lr_we;
output ctr_we;
//
// Interface with Exception Unit: expception request, SPRs access
//
output sig_svm_check;
input msr_expwe;
input [31:0] msr_except;
output [31:0] msr;
output dear_we;
output esr_we;
output srr0_we;
output srr1_we;
output srr2_we;
output srr3_we;
output evpr_we;
output mcsr_we;
input [width-1:0] dear;
input [width-1:0] esr;
input [width-1:0] srr0;
input [width-1:0] srr1;
input [width-1:0] srr2;
input [width-1:0] srr3;
input [width-1:0] evpr;
input [width-1:0] mcsr;
//
output eir_we;
input [width-1:0] eir;
//
// timer
//
input [31:0] tbl, tbu, pit, tsr, tcr;
output tbl_we, tbu_we, pit_we, tsr_we, tcr_we;
//
// interface with dsu
//
input [7:0] dsurx, dsutx, dsuctrl, dsusta;
output dsurx_we, dsutx_we, dsuctrl_we, dsusta_we;
//
// To/from SPRs at core-out building blocks
//
output [31:0] spr_dat_wr_o;
//
// Internal regs & wires
//
reg [width-1:0] msr;
reg [width-1:0] xer;
wire [31:0] cr;
reg [3:0] cr0;
reg [3:0] cr1;
reg [3:0] cr2;
reg [3:0] cr3;
reg [3:0] cr4;
reg [3:0] cr5;
reg [3:0] cr6;
reg [3:0] cr7;
wire [31:0] pvr;
reg write_spr;
reg read_spr;
reg [width-1:0] spr_wb_dat;
wire [`REGOP_WIDTH-1:0] reg_uops;
wire [9:0] spr_addr;
wire pvr_sel;
wire cr_we;
wire xer_we;
wire carry;
wire so;
wire [31:0] xer_new;
wire [3:0] cr0_new;
wire [3:0] cr1_new;
wire [3:0] cr2_new;
wire [3:0] cr3_new;
wire [3:0] cr4_new;
wire [3:0] cr5_new;
wire [3:0] cr6_new;
wire [3:0] cr7_new;
wire [3:0] cr0_alu;
wire [3:0] cr1_alu;
wire [3:0] cr2_alu;
wire [3:0] cr3_alu;
wire [3:0] cr4_alu;
wire [3:0] cr5_alu;
wire [3:0] cr6_alu;
wire [3:0] cr7_alu;
wire so_new;
wire ov_new;
wire lr_sel;
wire lr_we;
wire ctr_sel;
wire ctr_we;
wire [31:0] spr_dat_i;
wire [31:0] msr_new;
//
wire [7:0] dsurx, dsutx, dsuctrl, dsusta;
//
wire [31:0] tbl, tbu, pit, tsr, tcr;
//
// Generate sprs opcode
//
assign spr_addr = reg_addr;
assign spr_dat_i = dat_i; // write data to SPRs, send out by DSS or mtspr-class instructions
assign spr_dat_wr_o = dat_i; // bypass the write data to other SPRs, from GPRs via operandmux
//
// supervisor model check
// svm instructions£ºmfmsr/mtmsr, rfi/rfci, wrtee/wrteei, mfdcr/mtdcr
// msb of spr_addr must be 1'b0 under mfspr/mtspr case
// rfi/rfci is check at except module
assign sig_svm_check = msr[`pippo_MSR_PR_BITS] &
(((reg_uops == `REGOP_MTMSR) | (reg_uops == `REGOP_WRTEE) | (reg_uops == `REGOP_MFMSR)) |
(spr_addr[9] & (reg_uops == `REGOP_MFSPR) | (reg_uops == `REGOP_MFSPR)));
//
// MSR
//
// Note: 1, MSR of pippo only implemented: [PR][ME][CE][EE]
// 2, other unimplemented fields are keep to 1'b0;
// 3, reserved field operate as 405
assign msr_we = msr_expwe | (!sig_svm_check & (reg_uops == `REGOP_MTMSR) | (reg_uops == `REGOP_WRTEE));
// [TBV] msr_new logic's coding style: mux should be inferred, not priority decoder
assign msr_new[`pippo_MSR_PR_BITS] =
(reg_uops == `REGOP_MTMSR)? spr_dat_i[`pippo_MSR_PR_BITS]:
msr[`pippo_MSR_PR_BITS];
assign msr_new[`pippo_MSR_ME_BITS] =
(reg_uops == `REGOP_MTMSR)? spr_dat_i[`pippo_MSR_ME_BITS]:
msr[`pippo_MSR_ME_BITS];
assign msr_new[`pippo_MSR_CE_BITS] =
(reg_uops == `REGOP_MTMSR)? spr_dat_i[`pippo_MSR_CE_BITS]:
msr[`pippo_MSR_CE_BITS];
// wrtee/wrteei
assign msr_new[`pippo_MSR_EE_BITS] =
(reg_uops == `REGOP_MTMSR)? spr_dat_i[`pippo_MSR_EE_BITS]:
(reg_uops == `REGOP_WRTEE)? spr_dat_i[`pippo_MSR_EE_BITS]:
msr[`pippo_MSR_EE_BITS];
always @(posedge clk or posedge rst)
if (rst)
msr <= #1 `pippo_MSR_RESET;
else if (msr_expwe)
msr <= #1 msr_except;
else if (msr_we)
msr <= #1 msr_new;
//
// GP SPR
//
reg [31:0] usprg0;
reg [31:0] sprg0, sprg1, sprg2, sprg3, sprg4, sprg5, sprg6, sprg7;
// USPRG0 - User
assign usprg0_sel = (spr_addr == `pippo_SPR_USPRG0);
assign usprg0_we = write_spr & usprg0_sel;
always @(posedge clk or posedge rst) begin
if (rst)
usprg0 <= #1 `pippo_SPR_USPRG0_RESET;
else if (usprg0_we)
usprg0 <= #1 spr_dat_i;
end
// SPRG0, SPRG1, SPRG2, SPRG3 - Privileged
assign sprg0_sel = (spr_addr == `pippo_SPR_SPRG0);
assign sprg1_sel = (spr_addr == `pippo_SPR_SPRG1);
assign sprg2_sel = (spr_addr == `pippo_SPR_SPRG2);
assign sprg3_sel = (spr_addr == `pippo_SPR_SPRG3);
assign sprg0_we = write_spr & sprg0_sel;
assign sprg1_we = write_spr & sprg1_sel;
assign sprg2_we = write_spr & sprg2_sel;
assign sprg3_we = write_spr & sprg3_sel;
always @(posedge clk or posedge rst) begin
if (rst)
sprg0 <= #1 `pippo_SPR_SPRG0_RESET;
else if (sprg0_we)
sprg0 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
sprg1 <= #1 `pippo_SPR_SPRG1_RESET;
else if (sprg1_we)
sprg1 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
sprg2 <= #1 `pippo_SPR_SPRG2_RESET;
else if (sprg2_we)
sprg2 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
sprg3 <= #1 `pippo_SPR_SPRG3_RESET;
else if (sprg3_we)
sprg3 <= #1 spr_dat_i;
end
// SPRG4, SPRG5, SPRG6, SPRG7 - User read, privileged write
assign sprg4_selu = (spr_addr == `pippo_SPR_SPRG4U);
assign sprg5_selu = (spr_addr == `pippo_SPR_SPRG5U);
assign sprg6_selu = (spr_addr == `pippo_SPR_SPRG6U);
assign sprg7_selu = (spr_addr == `pippo_SPR_SPRG7U);
assign sprg4_sel = (spr_addr == `pippo_SPR_SPRG4);
assign sprg5_sel = (spr_addr == `pippo_SPR_SPRG5);
assign sprg6_sel = (spr_addr == `pippo_SPR_SPRG6);
assign sprg7_sel = (spr_addr == `pippo_SPR_SPRG7);
assign sprg4_we = write_spr & sprg4_sel;
assign sprg5_we = write_spr & sprg5_sel;
assign sprg6_we = write_spr & sprg6_sel;
assign sprg7_we = write_spr & sprg7_sel;
always @(posedge clk or posedge rst) begin
if (rst)
sprg4 <= #1 `pippo_SPR_SPRG4_RESET;
else if (sprg4_we)
sprg4 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
sprg5 <= #1 `pippo_SPR_SPRG5_RESET;
else if (sprg5_we)
sprg5 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
sprg6 <= #1 `pippo_SPR_SPRG6_RESET;
else if (sprg6_we)
sprg6 <= #1 spr_dat_i;
end
always @(posedge clk or posedge rst) begin
if (rst)
sprg7 <= #1 `pippo_SPR_SPRG7_RESET;
else if (sprg7_we)
sprg7 <= #1 spr_dat_i;
end
//
// CR
//
//[TBD] weºÍwrÂß¼¼ò»¯
wire [2:0] crf_d;
wire [2:0] crf_s;
wire [7:0] fxm;
assign crf_d = cr_addr[14:12];
assign crf_s = cr_addr[9:7];
assign fxm = cr_addr[8:1];
assign cr0_rd = ((reg_uops == `REGOP_MCRF) & crf_s == 3'b000);
assign cr1_rd = ((reg_uops == `REGOP_MCRF) & crf_s == 3'b001);
assign cr2_rd = ((reg_uops == `REGOP_MCRF) & crf_s == 3'b010);
assign cr3_rd = ((reg_uops == `REGOP_MCRF) & crf_s == 3'b011);
assign cr4_rd = ((reg_uops == `REGOP_MCRF) & crf_s == 3'b100);
assign cr5_rd = ((reg_uops == `REGOP_MCRF) & crf_s == 3'b101);
assign cr6_rd = ((reg_uops == `REGOP_MCRF) & crf_s == 3'b110);
assign cr7_rd = ((reg_uops == `REGOP_MCRF) & crf_s == 3'b111);
assign cr0_wr = ((reg_uops == `REGOP_MCRF) & crf_d == 3'b000) |
((reg_uops == `REGOP_MTCRF) & fxm[7]) |
((reg_uops == `REGOP_MCRXR) & crf_d == 3'b000);
assign cr1_wr = ((reg_uops == `REGOP_MCRF) & crf_d == 3'b001) |
((reg_uops == `REGOP_MTCRF) & fxm[6]) |
((reg_uops == `REGOP_MCRXR) & crf_d == 3'b001);
assign cr2_wr = ((reg_uops == `REGOP_MCRF) & crf_d == 3'b010) |
((reg_uops == `REGOP_MTCRF) & fxm[5]) |
((reg_uops == `REGOP_MCRXR) & crf_d == 3'b010);
assign cr3_wr = ((reg_uops == `REGOP_MCRF) & crf_d == 3'b011) |
((reg_uops == `REGOP_MTCRF) & fxm[4]) |
((reg_uops == `REGOP_MCRXR) & crf_d == 3'b011);
assign cr4_wr = ((reg_uops == `REGOP_MCRF) & crf_d == 3'b100) |
((reg_uops == `REGOP_MTCRF) & fxm[3]) |
((reg_uops == `REGOP_MCRXR) & crf_d == 3'b100);
assign cr5_wr = ((reg_uops == `REGOP_MCRF) & crf_d == 3'b101) |
((reg_uops == `REGOP_MTCRF) & fxm[2]) |
((reg_uops == `REGOP_MCRXR) & crf_d == 3'b101);
assign cr6_wr = ((reg_uops == `REGOP_MCRF) & crf_d == 3'b110) |
((reg_uops == `REGOP_MTCRF) & fxm[1]) |
((reg_uops == `REGOP_MCRXR) & crf_d == 3'b110);
assign cr7_wr = ((reg_uops == `REGOP_MCRF) & crf_d == 3'b111) |
((reg_uops == `REGOP_MTCRF) & fxm[0]) |
((reg_uops == `REGOP_MCRXR) & crf_d == 3'b111);
assign cr0_alu_we = cr_alu_we[7];
assign cr1_alu_we = cr_alu_we[6];
assign cr2_alu_we = cr_alu_we[5];
assign cr3_alu_we = cr_alu_we[4];
assign cr4_alu_we = cr_alu_we[3];
assign cr5_alu_we = cr_alu_we[2];
assign cr6_alu_we = cr_alu_we[1];
assign cr7_alu_we = cr_alu_we[0];
assign cr0_alu = cr_alu[31:28];
assign cr1_alu = cr_alu[27:24];
assign cr2_alu = cr_alu[23:20];
assign cr3_alu = cr_alu[19:16];
assign cr4_alu = cr_alu[15:12];
assign cr5_alu = cr_alu[11:8];
assign cr6_alu = cr_alu[7:4];
assign cr7_alu = cr_alu[3:0];
assign cr0_we = cr0_alu_we |
cr0_lsu_we |
((reg_uops == `REGOP_MTCRF) & cr0_wr) |
((reg_uops == `REGOP_MCRXR) & cr0_wr) |
((reg_uops == `REGOP_MCRF) & cr0_wr);
assign cr0_new =
cr0_alu_we ? cr0_alu :
cr0_lsu_we ? cr0_lsu :
((reg_uops == `REGOP_MCRXR) & cr0_wr) ? xer[31:28]:
((reg_uops == `REGOP_MTCRF) & cr0_wr) ? spr_dat_i[31:28]:
((reg_uops == `REGOP_MCRF) & cr0_wr) ?
(cr0_rd ? cr0 :
cr1_rd ? cr1 :
cr2_rd ? cr2 :
cr3_rd ? cr3 :
cr4_rd ? cr4 :
cr5_rd ? cr5 :
cr6_rd ? cr6 :
cr7) :
cr0;
assign cr1_we = cr1_alu_we |
((reg_uops == `REGOP_MTCRF) & cr1_wr) |
((reg_uops == `REGOP_MCRXR) & cr1_wr) |
((reg_uops == `REGOP_MCRF) & cr1_wr);
assign cr1_new =
cr1_alu_we ? cr1_alu :
((reg_uops == `REGOP_MCRXR) & cr1_wr) ? xer[31:28]:
((reg_uops == `REGOP_MTCRF) & cr1_wr) ? spr_dat_i[27:24]:
((reg_uops == `REGOP_MCRF) & cr1_wr) ?
(cr0_rd ? cr0 :
cr1_rd ? cr1 :
cr2_rd ? cr2 :
cr3_rd ? cr3 :
cr4_rd ? cr4 :
cr5_rd ? cr5 :
cr6_rd ? cr6 :
cr7) :
cr1;
assign cr2_we = cr2_alu_we |
((reg_uops == `REGOP_MTCRF) & cr2_wr) |
((reg_uops == `REGOP_MCRXR) & cr2_wr) |
((reg_uops == `REGOP_MCRF) & cr2_wr);
assign cr2_new =
cr2_alu_we ? cr2_alu :
((reg_uops == `REGOP_MCRXR) & cr2_wr) ? xer[31:28]:
((reg_uops == `REGOP_MTCRF) & cr2_wr) ? spr_dat_i[23:20]:
((reg_uops == `REGOP_MCRF) & cr2_wr) ?
(cr0_rd ? cr0 :
cr1_rd ? cr1 :
cr2_rd ? cr2 :
cr3_rd ? cr3 :
cr4_rd ? cr4 :
cr5_rd ? cr5 :
cr6_rd ? cr6 :
cr7) :
cr2;
assign cr3_we = cr3_alu_we |
((reg_uops == `REGOP_MTCRF) & cr3_wr) |
((reg_uops == `REGOP_MCRXR) & cr3_wr) |
((reg_uops == `REGOP_MCRF) & cr3_wr);
assign cr3_new =
cr3_alu_we ? cr3_alu :
((reg_uops == `REGOP_MCRXR) & cr3_wr) ? xer[31:28]:
((reg_uops == `REGOP_MTCRF) & cr3_wr) ? spr_dat_i[19:16]:
((reg_uops == `REGOP_MCRF) & cr3_wr) ?
(cr0_rd ? cr0 :
cr1_rd ? cr1 :
cr2_rd ? cr2 :
cr3_rd ? cr3 :
cr4_rd ? cr4 :
cr5_rd ? cr5 :
cr6_rd ? cr6 :
cr7) :
cr3;
assign cr4_we = cr4_alu_we |
((reg_uops == `REGOP_MTCRF) & cr4_wr) |
((reg_uops == `REGOP_MCRXR) & cr4_wr) |
((reg_uops == `REGOP_MCRF) & cr4_wr);
assign cr4_new =
cr4_alu_we ? cr4_alu :
((reg_uops == `REGOP_MCRXR) & cr4_wr) ? xer[31:28]:
((reg_uops == `REGOP_MTCRF) & cr4_wr) ? spr_dat_i[15:12]:
((reg_uops == `REGOP_MCRF) & cr4_wr) ?
(cr0_rd ? cr0 :
cr1_rd ? cr1 :
cr2_rd ? cr2 :
cr3_rd ? cr3 :
cr4_rd ? cr4 :
cr5_rd ? cr5 :
cr6_rd ? cr6 :
cr7) :
cr4;
assign cr5_we = cr5_alu_we |
((reg_uops == `REGOP_MTCRF) & cr5_wr) |
((reg_uops == `REGOP_MCRXR) & cr5_wr) |
((reg_uops == `REGOP_MCRF) & cr5_wr);
assign cr5_new =
cr5_alu_we ? cr5_alu :
((reg_uops == `REGOP_MCRXR) & cr5_wr) ? xer[31:28]:
((reg_uops == `REGOP_MTCRF) & cr5_wr) ? spr_dat_i[11:8]:
((reg_uops == `REGOP_MCRF) & cr5_wr) ?
(cr0_rd ? cr0 :
cr1_rd ? cr1 :
cr2_rd ? cr2 :
cr3_rd ? cr3 :
cr4_rd ? cr4 :
cr5_rd ? cr5 :
cr6_rd ? cr6 :
cr7) :
cr5;
assign cr6_we = cr6_alu_we |
((reg_uops == `REGOP_MTCRF) & cr6_wr) |
((reg_uops == `REGOP_MCRXR) & cr6_wr) |
((reg_uops == `REGOP_MCRF) & cr6_wr);
assign cr6_new =
cr6_alu_we ? cr6_alu :
((reg_uops == `REGOP_MCRXR) & cr6_wr) ? xer[31:28]:
((reg_uops == `REGOP_MTCRF) & cr6_wr) ? spr_dat_i[7:4]:
((reg_uops == `REGOP_MCRF) & cr6_wr) ?
(cr0_rd ? cr0 :
cr1_rd ? cr1 :
cr2_rd ? cr2 :
cr3_rd ? cr3 :
cr4_rd ? cr4 :
cr5_rd ? cr5 :
cr6_rd ? cr6 :
cr7) :
cr6;
assign cr7_we = cr7_alu_we |
((reg_uops == `REGOP_MTCRF) & cr7_wr) |
((reg_uops == `REGOP_MCRXR) & cr7_wr) |
((reg_uops == `REGOP_MCRF) & cr7_wr);
assign cr7_new =
cr7_alu_we ? cr7_alu :
((reg_uops == `REGOP_MCRXR) & cr7_wr) ? xer[31:28]:
((reg_uops == `REGOP_MTCRF) & cr7_wr) ? spr_dat_i[3:0]:
((reg_uops == `REGOP_MCRF) & cr7_wr) ?
(cr0_rd ? cr0 :
cr1_rd ? cr1 :
cr2_rd ? cr2 :
cr3_rd ? cr3 :
cr4_rd ? cr4 :
cr5_rd ? cr5 :
cr6_rd ? cr6 :
cr7) :
cr7;
assign cr_we = cr0_we | cr1_we | cr2_we | cr3_we | cr4_we | cr5_we | cr6_we | cr7_we;
always @(posedge clk or posedge rst) begin
if (rst) begin
cr0 <= #1 4'b0000;
cr1 <= #1 4'b0000;
cr2 <= #1 4'b0000;
cr3 <= #1 4'b0000;
cr4 <= #1 4'b0000;
cr5 <= #1 4'b0000;
cr6 <= #1 4'b0000;
cr7 <= #1 4'b0000;
end
else if (cr_we) begin
cr0 <= #1 cr0_new;
cr1 <= #1 cr1_new;
cr2 <= #1 cr2_new;
cr3 <= #1 cr3_new;
cr4 <= #1 cr4_new;
cr5 <= #1 cr5_new;
cr6 <= #1 cr6_new;
cr7 <= #1 cr7_new;
end
end
// CR output
assign cr = {cr0, cr1, cr2, cr3, cr4, cr5, cr6, cr7};
//
// XER
//
// xer_weΪÖظ´Âß¼£¬²¢ÎÞÓÃ
assign xer_sel = (spr_addr == `pippo_SPR_XER);
assign xer_we = (write_spr && xer_sel) | ca_we | ov_we | so_we | (reg_uops == `REGOP_MCRXR);
assign xer_new[`pippo_SPR_XER_SO_BITS] =
(reg_uops == `REGOP_MCRXR)? 1'b0 :
so_we ? so_new :
(write_spr && xer_sel) ? spr_dat_i[`pippo_SPR_XER_SO_BITS] :
xer[`pippo_SPR_XER_CA_BITS];
assign xer_new[`pippo_SPR_XER_OV_BITS] =
(reg_uops == `REGOP_MCRXR)? 1'b0 :
ov_we ? ov_new :
(write_spr && xer_sel) ? spr_dat_i[`pippo_SPR_XER_OV_BITS] :
xer[`pippo_SPR_XER_OV_BITS];
assign xer_new[`pippo_SPR_XER_CA_BITS] =
(reg_uops == `REGOP_MCRXR)? 1'b0 :
ca_we ? ca_new :
(write_spr && xer_sel) ? spr_dat_i[`pippo_SPR_XER_CA_BITS] :
xer[`pippo_SPR_XER_CA_BITS];
always @(posedge clk or posedge rst)
if (rst)
xer <= #1 `pippo_SPR_XER_RESET;
else if (xer_we)
xer <= #1 xer_new;
// output to ALU
assign carry = xer[`pippo_SPR_XER_CA_BITS];
assign so = xer[`pippo_SPR_XER_SO_BITS];
//
// PVR: Read Only
// Implemented as combinational logic only
// [TBD] coding style, to check
assign pvr_sel = (spr_addr == `pippo_SPR_PVR);
assign pvr[`pippo_SPR_PVR_OWN_BITS] = `pippo_SPR_PVR_OWN;
assign pvr[`pippo_SPR_PVR_PCF_BITS] = `pippo_SPR_PVR_PCF;
assign pvr[`pippo_SPR_PVR_CAS_BITS] = `pippo_SPR_PVR_CAS;
assign pvr[`pippo_SPR_PVR_PCV_BITS] = `pippo_SPR_PVR_PCV;
assign pvr[`pippo_SPR_PVR_AID_BITS] = `pippo_SPR_PVR_AID;
//
// Exception SPRs Interface
//
assign dear_sel = (spr_addr == `pippo_SPR_DEAR);
assign esr_sel = (spr_addr == `pippo_SPR_ESR);
assign evpr_sel = (spr_addr == `pippo_SPR_EVPR);
assign mcsr_sel = (spr_addr == `pippo_SPR_MCSR);
assign srr0_sel = (spr_addr == `pippo_SPR_SRR0);
assign srr1_sel = (spr_addr == `pippo_SPR_SRR1);
assign srr2_sel = (spr_addr == `pippo_SPR_SRR2);
assign srr3_sel = (spr_addr == `pippo_SPR_SRR3);
assign dear_we = (write_spr && dear_sel);
assign esr_we = (write_spr && esr_sel);
assign evpr_we = (write_spr && evpr_sel);
assign mcsr_we = (write_spr && mcsr_sel);
assign srr0_we = (write_spr && srr0_sel);
assign srr1_we = (write_spr && srr1_sel);
assign srr2_we = (write_spr && srr2_sel);
assign srr3_we = (write_spr && srr3_sel);
// Emulation SPRs
assign eir_sel = (spr_addr == `pippo_SPR_EIR);
assign eir_we = (write_spr && eir_sel);
//
// LR/CTR Interface
//
assign lr_sel = (spr_addr == `pippo_SPR_LR);
assign lr_we = (write_spr && lr_sel);
assign ctr_sel = (spr_addr == `pippo_SPR_CTR);
assign ctr_we = (write_spr && ctr_sel);
//
// timer interface
//
assign tbl_selu = (spr_addr == `pippo_SPR_TBLU);
assign tbu_selu = (spr_addr == `pippo_SPR_TBUU);
assign tbl_sel = (spr_addr == `pippo_SPR_TBL);
assign tbl_we = (write_spr && tbl_sel);
assign tbu_sel = (spr_addr == `pippo_SPR_TBU);
assign tbu_we = (write_spr && tbu_sel);
assign pit_sel = (spr_addr == `pippo_SPR_PIT);
assign pit_we = (write_spr && pit_sel);
assign tsr_sel = (spr_addr == `pippo_SPR_TSR);
assign tsr_we = (write_spr && tsr_sel);
assign tcr_sel = (spr_addr == `pippo_SPR_TCR);
assign tcr_we = (write_spr && tcr_sel);
//
// DSU interface
//
assign dsurx_sel = (spr_addr == `pippo_SPR_DSURX);
assign dsurx_we = (write_spr && dsurx_sel);
assign dsutx_sel = (spr_addr == `pippo_SPR_DSUTX);
assign dsutx_we = (write_spr && dsutx_sel);
assign dsuctrl_sel = (spr_addr == `pippo_SPR_DSUCTRL);
assign dsuctrl_we = (write_spr && dsuctrl_sel);
assign dsusta_sel = (spr_addr == `pippo_SPR_DSUSTA);
assign dsusta_we = (write_spr && dsusta_sel);
//
// MTSPR/MFSPR interface
//
always @(reg_uops or spr_addr or msr or cr or pvr or xer or ctr or lr or
dear or esr or evpr or mcsr or srr0 or srr1 or srr2 or srr3 or
usprg0 or sprg0 or sprg1 or sprg2 or sprg3 or sprg4 or sprg5 or
sprg6 or sprg7 or dsurx or dsutx or dsuctrl or dsusta or
tbl or tbu or pit or tsr or tcr or
dear_sel or esr_sel or evpr_sel or mcsr_sel or srr0_sel or srr1_sel or
srr2_sel or srr3_sel or ctr_sel or pvr_sel or xer_sel or lr_sel or
usprg0_sel or sprg0_sel or sprg1_sel or sprg2_sel or sprg3_sel or
sprg4_sel or sprg5_sel or sprg6_sel or sprg7_sel or
sprg4_selu or sprg5_selu or sprg6_selu or sprg7_selu or
tbl_sel or tbl_selu or tbu_sel or tbu_selu or pit_sel or tsr_sel or tcr_sel or
eir or eir_sel or
dsurx_sel or dsutx_sel or dsuctrl_sel or dsusta_sel) begin
write_spr = 1'b0;
read_spr = 1'b0;
spr_wb_dat = 32'b0;
case (reg_uops) // synopsys parallel_case
`REGOP_MFMSR : begin
write_spr = 1'b0;
read_spr = 1'b1;
spr_wb_dat = msr;
end
`REGOP_MFCR : begin
write_spr = 1'b0;
read_spr = 1'b0;
spr_wb_dat = cr;
end
`REGOP_MFSPR : begin
write_spr = 1'b0;
read_spr = 1'b1;
casex (1) // synopsys parallel_case
pvr_sel:
spr_wb_dat = pvr;
xer_sel:
spr_wb_dat = xer;
ctr_sel:
spr_wb_dat = ctr;
lr_sel:
spr_wb_dat = lr;
usprg0_sel:
spr_wb_dat = usprg0;
sprg0_sel:
spr_wb_dat = sprg0;
sprg1_sel:
spr_wb_dat = sprg1;
sprg2_sel:
spr_wb_dat = sprg2;
sprg3_sel:
spr_wb_dat = sprg3;
sprg4_sel, sprg4_selu:
spr_wb_dat = sprg4;
sprg5_sel, sprg5_selu:
spr_wb_dat = sprg5;
sprg6_sel, sprg6_selu:
spr_wb_dat = sprg6;
sprg7_sel, sprg7_sel:
spr_wb_dat = sprg7;
dear_sel:
spr_wb_dat = dear;
esr_sel:
spr_wb_dat = esr;
evpr_sel:
spr_wb_dat = evpr;
mcsr_sel:
spr_wb_dat = mcsr;
srr0_sel:
spr_wb_dat = srr0;
srr1_sel:
spr_wb_dat = srr1;
srr2_sel:
spr_wb_dat = srr2;
srr3_sel:
spr_wb_dat = srr3;
eir_sel:
spr_wb_dat = eir;
tbl_sel, tbl_selu:
spr_wb_dat = tbl;
tbu_sel, tbu_selu:
spr_wb_dat = tbu;
pit_sel:
spr_wb_dat = pit;
tsr_sel:
spr_wb_dat = tsr;
tcr_sel:
spr_wb_dat = tcr;
dsurx_sel:
spr_wb_dat = {24'd0, dsurx};
dsutx_sel:
spr_wb_dat = {24'd0, dsutx};
dsuctrl_sel:
spr_wb_dat = {24'd0, dsuctrl};
dsusta_sel:
spr_wb_dat = {24'd0, dsusta};
default:
spr_wb_dat = 32'd0; // how to deal with CCR0/CCR1 access, to support legacy binary
endcase
end
`REGOP_MTSPR : begin
write_spr = 1'b1;
read_spr = 1'b0;
spr_wb_dat = 32'b0;
end
default : begin
write_spr = 1'b0;
read_spr = 1'b0;
spr_wb_dat = 32'b0;
end
endcase
end
endmodule
|
/*
* Copyright (C) 2015 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
// 4 cycle pipe
module complex_mult
(
input clock,
input ce,
input signed [24:0] a_re, a_im,
input signed [17:0] b_re, b_im,
output signed [47:0] p_re, p_im
);
dual_mult_add m_re
(
.clock(clock),
.ce(ce),
.sub(1'b1),
.a(a_re),
.b(b_re),
.c(a_im),
.d(b_im),
.p(p_re)
);
dual_mult_add m_im
(
.clock(clock),
.ce(ce),
.sub(1'b0),
.a(a_im),
.b(b_re),
.c(a_re),
.d(b_im),
.p(p_im)
);
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: DAS_RF.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module DAS_RF (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [15:0] data;
input [13:0] rdaddress;
input [13:0] wraddress;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "262144"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdaddress 0 0 14 0 INPUT NODEFVAL rdaddress[13..0]
// Retrieval info: USED_PORT: wraddress 0 0 14 0 INPUT NODEFVAL wraddress[13..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: CONNECT: @address_a 0 0 14 0 wraddress 0 0 14 0
// Retrieval info: CONNECT: @address_b 0 0 14 0 rdaddress 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL DAS_RF.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DAS_RF.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DAS_RF.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DAS_RF.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DAS_RF_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DAS_RF_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DAS_RF_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DAS_RF_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_2_V
`define SKY130_FD_SC_HD__NAND3_2_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_2_V
|
`timescale 1ns/1ps
module tb_cocotb (
//Virtual Host Interface Signals
input clk,
input rst,
output master_ready,
input in_ready,
input [31:0] in_command,
input [31:0] in_address,
input [31:0] in_data,
input [27:0] in_data_count,
input out_ready,
output out_en,
output [31:0] out_status,
output [31:0] out_address,
output [31:0] out_data,
output [27:0] out_data_count,
input [31:0] test_id,
input ih_reset,
output device_interrupt
);
localparam CONTROL_FIFO_DEPTH = 7;
//Parameters
//Registers/Wires
reg r_rst;
reg r_in_ready;
reg [31:0] r_in_command;
reg [31:0] r_in_address;
reg [31:0] r_in_data;
reg [27:0] r_in_data_count;
reg r_out_ready;
reg r_ih_reset;
reg w_clk_100mhz_clk_p;
reg w_clk_100mhz_clk_n;
reg r_pcie_reset_n = 0;
wire w_sys_rst;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
always @ (*) r_in_ready = in_ready;
always @ (*) r_in_command = in_command;
always @ (*) r_in_address = in_address;
always @ (*) r_in_data = in_data;
always @ (*) r_in_data_count = in_data_count;
always @ (*) r_out_ready = out_ready;
always @ (*) r_ih_reset = ih_reset;
always @ (*) w_clk_100mhz_clk_p = clk;
always @ (*) w_clk_100mhz_clk_n = !clk;
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Memory Interface
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
wire mem_o_we;
wire mem_o_stb;
wire mem_o_cyc;
wire [3:0] mem_o_sel;
wire [31:0] mem_o_adr;
wire [31:0] mem_o_dat;
wire [31:0] mem_i_dat;
wire mem_i_ack;
wire mem_i_int;
//Artemis PCIE Interface
wire w_pcie_reset;
wire w_pcie_per_fifo_sel;
wire w_pcie_mem_fifo_sel;
wire w_pcie_dma_fifo_sel;
wire w_pcie_write_fin;
wire w_pcie_read_fin;
wire [31:0] w_pcie_data_size;
wire [31:0] w_pcie_data_address;
wire w_pcie_data_fifo_flg;
wire w_pcie_data_read_flg;
wire w_pcie_data_write_flg;
wire w_pcie_interrupt_stb;
wire [31:0] w_pcie_interrupt_value;
wire w_pcie_data_clk;
wire w_pcie_ingress_fifo_rdy;
wire w_pcie_ingress_fifo_act;
wire [23:0] w_pcie_ingress_fifo_size;
wire w_pcie_ingress_fifo_stb;
wire [31:0] w_pcie_ingress_fifo_data;
wire w_pcie_ingress_fifo_idle;
wire [1:0] w_pcie_egress_fifo_rdy;
wire [1:0] w_pcie_egress_fifo_act;
wire [23:0] w_pcie_egress_fifo_size;
wire w_pcie_egress_fifo_stb;
wire [31:0] w_pcie_egress_fifo_data;
//Master Interface
wire w_master_ready;
wire w_ih_reset;
wire w_ih_ready;
wire [31:0] w_in_command;
wire [31:0] w_in_address;
wire [31:0] w_in_data;
wire [27:0] w_in_data_count;
wire w_out_ready;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
wire [31:0] w_usr_interrupt_value;
//Memorce
wire w_ddr3_cmd_clk;
wire w_ddr3_cmd_en;
wire [2:0] w_ddr3_cmd_instr;
wire [5:0] w_ddr3_cmd_bl;
wire [29:0] w_ddr3_cmd_byte_addr;
wire w_ddr3_cmd_empty;
wire w_ddr3_cmd_full;
wire w_ddr3_wr_clk;
wire w_ddr3_wr_en;
wire [3:0] w_ddr3_wr_mask;
wire [31:0] w_ddr3_wr_data;
wire w_ddr3_wr_full;
wire w_ddr3_wr_empty;
wire [6:0] w_ddr3_wr_count;
wire w_ddr3_wr_underrun;
wire w_ddr3_wr_error;
wire w_ddr3_rd_clk;
wire w_ddr3_rd_en;
wire [31:0] w_ddr3_rd_data;
wire w_ddr3_rd_full;
wire w_ddr3_rd_empty;
wire [6:0] w_ddr3_rd_count;
wire w_ddr3_rd_overflow;
wire w_ddr3_rd_error;
//DMA I
wire w_idma_activate;
wire w_idma_ready;
wire w_idma_stb;
wire [23:0] w_idma_size;
wire [31:0] w_idma_data;
wire [1:0] w_odma_ready;
wire [1:0] w_odma_activate;
wire w_odma_stb;
wire [23:0] w_odma_size;
wire [31:0] w_odma_data;
wire [31:0] w_debug;
reg r_cancel_write_stb;
wire [31:0] w_num_reads;
wire w_read_idle;
reg [31:0] r_per_data;
wire w_per_stb;
wire w_per_cyc;
reg r_per_ack;
reg r_bram_we;
wire [6:0] w_bram_addr;
reg [31:0] r_bram_din;
wire [31:0] w_bram_dout;
wire w_bram_valid;
wire [1:0] w_mem_gen_rdy;
wire [23:0] w_mem_gen_size;
wire [1:0] w_mem_gen_act;
wire w_mem_gen_stb;
wire [31:0] w_mem_gen_data;
wire w_mem_sink_rdy;
wire [23:0] w_mem_sink_size;
wire w_mem_sink_act;
wire w_mem_sink_stb;
wire [31:0] w_mem_sink_data;
wire w_odma_flush;
wire w_idma_flush;
wire [1:0] w_dma_gen_rdy;
wire [23:0] w_dma_gen_size;
wire [1:0] w_dma_gen_act;
wire w_dma_gen_stb;
wire [31:0] w_dma_gen_data;
wire w_dma_sink_rdy;
wire [23:0] w_dma_sink_size;
wire w_dma_sink_act;
wire w_dma_sink_stb;
wire [31:0] w_dma_sink_data;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (r_rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count),
.i_out_ready (r_out_ready ),
.o_en (out_en ),
.o_status (out_status ),
.o_address (out_address ),
.o_data (out_data ),
.o_data_count (out_data_count ),
.o_master_ready (master_ready ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_msk (w_wbp_msk ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
//slave 1
wb_artemis_pcie_platform #(
.CONTROL_FIFO_DEPTH (CONTROL_FIFO_DEPTH )
) s1 (
.clk (clk ),
.rst (r_rst ),
.o_sys_rst (w_sys_rst ),
//Artemis PCIE Interface
.o_pcie_reset (w_pcie_reset ),
.o_pcie_per_fifo_sel (w_pcie_per_fifo_sel ),
.o_pcie_mem_fifo_sel (w_pcie_mem_fifo_sel ),
.o_pcie_dma_fifo_sel (w_pcie_dma_fifo_sel ),
.i_pcie_write_fin (w_pcie_write_fin ),
.i_pcie_read_fin (w_pcie_read_fin ),
.o_pcie_data_size (w_pcie_data_size ),
.o_pcie_data_address (w_pcie_data_address ),
.o_pcie_data_fifo_flg (w_pcie_data_fifo_flg ),
.o_pcie_data_read_flg (w_pcie_data_read_flg ),
.o_pcie_data_write_flg (w_pcie_data_write_flg ),
.i_pcie_interrupt_stb (w_pcie_interrupt_stb ),
.i_pcie_interrupt_value (w_pcie_interrupt_value ),
.i_pcie_data_clk (w_pcie_data_clk ),
.o_pcie_ingress_fifo_rdy (w_pcie_ingress_fifo_rdy ),
.i_pcie_ingress_fifo_act (w_pcie_ingress_fifo_act ),
.o_pcie_ingress_fifo_size (w_pcie_ingress_fifo_size ),
.i_pcie_ingress_fifo_stb (w_pcie_ingress_fifo_stb ),
.o_pcie_ingress_fifo_data (w_pcie_ingress_fifo_data ),
.o_pcie_ingress_fifo_idle (w_pcie_ingress_fifo_idle ),
.o_pcie_egress_fifo_rdy (w_pcie_egress_fifo_rdy ),
.i_pcie_egress_fifo_act (w_pcie_egress_fifo_act ),
.o_pcie_egress_fifo_size (w_pcie_egress_fifo_size ),
.i_pcie_egress_fifo_stb (w_pcie_egress_fifo_stb ),
.i_pcie_egress_fifo_data (w_pcie_egress_fifo_data ),
//PCIE Phy Interface
.i_clk_100mhz_gtp_p (w_clk_100mhz_clk_p ),
.i_clk_100mhz_gtp_n (w_clk_100mhz_clk_n ),
.i_pcie_reset_n (r_pcie_reset_n ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_sel (4'b1111 ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
artemis_pcie_host_interface host_interface (
.clk (clk ),
.rst (r_rst ),
//Artemis PCIE Interface
.i_sys_rst (w_sys_rst ),
.i_pcie_reset (w_pcie_reset ),
.i_pcie_per_fifo_sel (w_pcie_per_fifo_sel ),
.i_pcie_mem_fifo_sel (w_pcie_mem_fifo_sel ),
.i_pcie_dma_fifo_sel (w_pcie_dma_fifo_sel ),
.o_pcie_write_fin (w_pcie_write_fin ),
.o_pcie_read_fin (w_pcie_read_fin ),
.i_pcie_data_size (w_pcie_data_size ),
.i_pcie_data_address (w_pcie_data_address ),
.i_pcie_data_fifo_flg (w_pcie_data_fifo_flg ),
.i_pcie_data_read_flg (w_pcie_data_read_flg ),
.i_pcie_data_write_flg (w_pcie_data_write_flg ),
.o_pcie_interrupt_stb (w_pcie_interrupt_stb ),
.o_pcie_interrupt_value (w_pcie_interrupt_value ),
.o_pcie_data_clk (w_pcie_data_clk ),
.i_pcie_ingress_fifo_rdy (w_pcie_ingress_fifo_rdy ),
.o_pcie_ingress_fifo_act (w_pcie_ingress_fifo_act ),
.i_pcie_ingress_fifo_size (w_pcie_ingress_fifo_size ),
.o_pcie_ingress_fifo_stb (w_pcie_ingress_fifo_stb ),
.i_pcie_ingress_fifo_data (w_pcie_ingress_fifo_data ),
.i_pcie_ingress_fifo_idle (w_pcie_ingress_fifo_idle ),
.i_pcie_egress_fifo_rdy (w_pcie_egress_fifo_rdy ),
.o_pcie_egress_fifo_act (w_pcie_egress_fifo_act ),
.i_pcie_egress_fifo_size (w_pcie_egress_fifo_size ),
.o_pcie_egress_fifo_stb (w_pcie_egress_fifo_stb ),
.o_pcie_egress_fifo_data (w_pcie_egress_fifo_data ),
//Master Interface
.i_master_ready (w_master_ready ),
.o_ih_reset (w_ih_reset ),
.o_ih_ready (w_ih_ready ),
.o_in_command (w_in_command ),
.o_in_address (w_in_address ),
.o_in_data (w_in_data ),
.o_in_data_count (w_in_data_count ),
.o_oh_ready (w_out_ready ),
.i_oh_en (w_out_en ),
.i_out_status (w_out_status ),
.i_out_address (w_out_address ),
.i_out_data (w_out_data ),
.i_out_data_count (w_out_data_count ),
.i_usr_interrupt_value (w_usr_interrupt_value ),
//Memory Interface
.o_ddr3_cmd_clk (w_ddr3_cmd_clk ),
.o_ddr3_cmd_en (w_ddr3_cmd_en ),
.o_ddr3_cmd_instr (w_ddr3_cmd_instr ),
.o_ddr3_cmd_bl (w_ddr3_cmd_bl ),
.o_ddr3_cmd_byte_addr (w_ddr3_cmd_byte_addr ),
.i_ddr3_cmd_empty (w_ddr3_cmd_empty ),
.i_ddr3_cmd_full (w_ddr3_cmd_full ),
.o_ddr3_wr_clk (w_ddr3_wr_clk ),
.o_ddr3_wr_en (w_ddr3_wr_en ),
.o_ddr3_wr_mask (w_ddr3_wr_mask ),
.o_ddr3_wr_data (w_ddr3_wr_data ),
.i_ddr3_wr_full (w_ddr3_wr_full ),
.i_ddr3_wr_empty (w_ddr3_wr_empty ),
.i_ddr3_wr_count (w_ddr3_wr_count ),
.i_ddr3_wr_underrun (w_ddr3_wr_underrun ),
.i_ddr3_wr_error (w_ddr3_wr_error ),
.o_ddr3_rd_clk (w_ddr3_rd_clk ),
.o_ddr3_rd_en (w_ddr3_rd_en ),
.i_ddr3_rd_data (w_ddr3_rd_data ),
.i_ddr3_rd_full (w_ddr3_rd_full ),
.i_ddr3_rd_empty (w_ddr3_rd_empty ),
.i_ddr3_rd_count (w_ddr3_rd_count ),
.i_ddr3_rd_overflow (w_ddr3_rd_overflow ),
.i_ddr3_rd_error (w_ddr3_rd_error ),
//DMA Interface
.i_idma_flush (w_idma_flush ),
.i_idma_activate (w_idma_activate ),
.o_idma_ready (w_idma_ready ),
.i_idma_stb (w_idma_stb ),
.o_idma_size (w_idma_size ),
.o_idma_data (w_idma_data ),
.i_odma_flush (w_odma_flush ),
.o_odma_ready (w_odma_ready ),
.i_odma_activate (w_odma_activate ),
.i_odma_stb (w_odma_stb ),
.o_odma_size (w_odma_size ),
.i_odma_data (w_odma_data ),
.o_debug (w_debug )
);
wishbone_master wm_sim (
.clk (clk ),
.rst (rst ),
.i_ih_rst (w_ih_reset ),
.i_ready (w_ih_ready ),
.i_command (w_in_command ),
.i_address (w_in_address ),
.i_data (w_in_data ),
.i_data_count (w_in_data_count ),
.i_out_ready (w_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
// .o_per_we (w_wbp_we ),
// .o_per_adr (w_wbp_adr ),
// .o_per_dat (w_wbp_dat_i ),
.i_per_dat (r_per_data ),
.o_per_stb (w_per_stb ),
.o_per_cyc (w_per_cyc ),
// .o_per_msk (w_wbp_msk ),
// .o_per_sel (w_wbp_sel ),
.i_per_ack (r_per_ack ),
.i_per_int (1'b0 ), //Try this out later on
//memory interconnect signals
// .o_mem_we (w_mem_we_o ),
// .o_mem_adr (w_mem_adr_o ),
// .o_mem_dat (w_mem_dat_o ),
// .i_mem_dat (w_mem_dat_i ),
// .o_mem_stb (w_mem_stb_o ),
// .o_mem_cyc (w_mem_cyc_o ),
// .o_mem_sel (w_mem_sel_o ),
.i_mem_ack (1'b0 ), //Nothing should be on the memory bus
.i_mem_int (1'b0 )
);
//DMA Sink and Source
adapter_dpb_ppfifo #(
.MEM_DEPTH (CONTROL_FIFO_DEPTH ),
.DATA_WIDTH (32 )
) dma_bram (
.clk (clk ),
.rst (rst ),
.i_ppfifo_2_mem_en (r_snk_en ),
.i_mem_2_ppfifo_stb (r_mem_2_ppfifo_stb ),
.i_cancel_write_stb (r_cancel_write_stb ),
.o_num_reads (w_num_reads ),
.o_idle (w_read_idle ),
//User Memory Interface
.i_bram_we (r_bram_we ),
.i_bram_addr (w_bram_addr ),
.i_bram_din (r_bram_din ),
.o_bram_dout (w_bram_dout ),
.o_bram_valid (w_bram_valid ),
//Ping Pong FIFO Interface
.ppfifo_clk (clk ),
.i_write_ready (w_dma_gen_rdy ),
.o_write_activate (w_dma_gen_act ),
.i_write_size (w_dma_gen_size ),
.o_write_stb (w_dma_gen_stb ),
.o_write_data (w_dma_gen_data ),
.i_read_ready (w_dma_sink_rdy ),
.o_read_activate (w_dma_sink_act ),
.i_read_size (w_dma_sink_size ),
.o_read_stb (w_dma_sink_stb ),
.i_read_data (w_dma_sink_data )
);
localparam CONTROL_BUFFER_SIZE = 2 ** CONTROL_FIFO_DEPTH;
assign i_ddr3_cmd_empty = 1;
assign i_ddr3_cmd_full = 0;
assign i_ddr3_wr_full = 0;
assign i_ddr3_wr_empty = 1;
assign i_ddr3_wr_count = 0;
assign i_ddr3_wr_underrun = 0;
assign i_ddr3_wr_error = 0;
assign i_ddr3_rd_data = 32'h01234567;
assign i_ddr3_rd_full = 1;
assign i_ddr3_rd_empty = 0;
assign i_ddr3_rd_count = 63;
assign i_ddr3_rd_overflow = 0;
assign i_ddr3_rd_error = 0;
//Asynchronous Logic
assign w_odma_flush = 0;
assign w_idma_flush = 0;
assign w_usr_interrupt_value = 32'h0;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
r_per_data <= 0;
r_per_ack <= 0;
end
else begin
if (!w_per_stb && r_per_ack) begin
r_per_ack <= 0;
end
if (w_per_cyc && w_per_stb && !r_per_ack) begin
r_per_ack <= 1;
r_per_data <= r_per_data + 1;
end
end
end
wishbone_interconnect wi (
.clk (clk ),
.rst (r_rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (r_rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (r_rst ),
//masters
.i_m1_we (mem_o_we ),
.i_m1_stb (mem_o_stb ),
.i_m1_cyc (mem_o_cyc ),
.i_m1_sel (mem_o_sel ),
.i_m1_dat (mem_o_dat ),
.i_m1_adr (mem_o_adr ),
.o_m1_dat (mem_i_dat ),
.o_m1_ack (mem_i_ack ),
.o_m1_int (mem_i_int ),
.i_m0_we (w_sm0_i_wbs_we ),
.i_m0_stb (w_sm0_i_wbs_stb ),
.i_m0_cyc (w_sm0_i_wbs_cyc ),
.i_m0_sel (w_sm0_i_wbs_sel ),
.i_m0_dat (w_sm0_i_wbs_dat ),
.i_m0_adr (w_sm0_i_wbs_adr ),
.o_m0_dat (w_sm0_o_wbs_dat ),
.o_m0_ack (w_sm0_o_wbs_ack ),
.o_m0_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
wb_bram #(
.DATA_WIDTH (32 ),
.ADDR_WIDTH (10 )
)bram(
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int )
);
//Disable Slave 0
assign w_wbs0_int = 0;
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign device_interrupt = w_wbp_int;
/*
READ ME IF YOUR MODULE WILL INTERFACE WITH MEMORY
If you want to talk to memory over the wishbone bus directly, your module must control the following signals:
(Your module will be a wishbone master)
mem_o_we
mem_o_stb
mem_o_cyc
mem_o_sel
mem_o_adr
mem_o_dat
mem_i_dat
mem_i_ack
mem_i_int
Currently this bus is disabled so if will not interface with memory these signals can be left
For a reference check out wb_sd_host
*/
assign mem_o_we = 0;
assign mem_o_stb = 0;
assign mem_o_cyc = 0;
assign mem_o_sel = 0;
assign mem_o_adr = 0;
assign mem_o_dat = 0;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
always @ (posedge clk) begin
if (r_rst) begin
r_pcie_reset_n <= 0;
end
else begin
r_pcie_reset_n <= 1;
end
end
endmodule
|
`timescale 1ns/10ps
`include "pipeconnect.h"
/*
Notation:
_ low, 0
~ high, 1
/ posedge
\ negedge
. unknown,undetermined,unimportant
# valid data (held stable)
< changing
> --
*/
/*
Fasttarget presents the request address as the result data after one
cycle. Wait is never asserted.
WISHBONE - no wait states
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata _____________<#### D1 ####><#### D2 ####>____________________
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata ___________________________<#### D1 ####><#### D2 ####>______
PIPECONNECT - some wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_______________________________________
wait _____________/~~~~~~~~~~~~\________________________________________________
readdata _________________________________________<#### D1 ####><#### D2 ####>______
*/
module fasttarget // PIPECONNECT, no wait
(input wire clk,
input wire rst,
input wire `REQ req,
output reg `RES res);
always @(posedge clk) begin
res`WAIT <= 0;
res`RD <= ~rst && req`R ? req`A : 0;
end
endmodule
/*
PIPECONNECT - 1 wait state
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ##################>...........
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\/~~~~~~~~~~~~~~~~~~~~~~~~~~\___________
wait _____________/~~~~~~~~~~~~\______________/~~~~~~~~~~~~\____________________
readdata _________________________________________<#### D1 ####>______________<#### D2 ####>______
_~_~_~_~_~_
.AAAABBBB..
_~~~~~~~~__
_~~__~~____
_____aa__bb
*/
module slowtarget // PIPECONNECT, 1 wait
(input wire clk,
input wire rst,
input wire `REQ req,
output wire `RES res);
reg [31:0] readData;
reg ready;
assign res`RD = readData;
assign res`WAIT = req`R & ~ready;
always @(posedge clk)
if (rst) begin
readData <= 0;
ready <= 0;
//$display("target in reset");
end else begin
readData <= ready ? req`A : 0;
ready <= req`R & ~ready;
//$display("target %d %d", ready, res`WAIT);
end
endmodule
/*
Simple master waits for a result before issuing new request
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock /~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ...<#####req 1###>...........................<#####req 2
read ___/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait ________________________________________________________
readdata ______________________<#############>___________________
*/
/*
Streaming master keeps one outstanding command
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#####req 1###>.............<#####req 2
read ________/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait _____________________________________________________________
readdata ___________________________<#############>___________________
*/
module initiator
(input wire clk,
input wire rst,
output reg `REQ req,
input wire `RES res);
reg [31:0] counter;
reg [31:0] dataExpect;
reg dataValid;
parameter name = 1;
always @(posedge clk)
if (rst) begin
counter <= 0;
req <= 0;
dataValid <= 0;
dataExpect <= 0;
end else begin
dataValid <= req`R & ~res`WAIT;
if (dataValid) begin
if (dataExpect != res`RD)
$display("%6d init%d got %x !!! BAD!", $time, name, res`RD);
else
$display("%6d init%d got %x as expected", $time, name, res`RD);
end
if (~res`WAIT) begin
req`R <= 1;
req`A <= counter;
dataExpect <= req`A;
counter <= counter + 1;
$display("%6d init%d requests %x", $time, name, counter);
end
end
endmodule
module main();
reg rst, clk;
wire `REQ req;
wire `RES res;
wire [31:0] addr = req`A;
wire read = req`R;
wire wai = res`WAIT;
wire [31:0] data = res`RD;
initiator initiator1(clk, rst, req1, res1);
initiator initiator2(clk, rst, req2, res2);
mux2 mux_init(clk, req1, res1, req2, res2, req, res);
slowtarget target(clk, rst, req, res);
always # 5 clk = ~clk;
initial begin
$monitor("%d%d %4d %x %d %d %x", rst, clk, $time, addr, read, wai, data);
clk = 1;
rst = 1;
#15 rst = 0;
#200 $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_TB_V
`define SKY130_FD_SC_HS__A41OI_TB_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a41oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 A4 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 A3 = 1'b0;
#360 A4 = 1'b0;
#380 B1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 B1 = 1'b1;
#500 A4 = 1'b1;
#520 A3 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 B1 = 1'bx;
#640 A4 = 1'bx;
#660 A3 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__a41oi dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_TB_V
|
/****************************************
MIST1032ISA - Fetch Stage
****************************************/
`default_nettype none
`include "core.h"
`include "processor.h"
`include "common.h"
module fetch(
//System
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//System Register
input wire [31:0] iSYSREG_PSR,
input wire [31:0] iSYSREG_PDTR,
input wire [31:0] iSYSREG_KPDTR,
input wire [31:0] iSYSREG_TIDR,
//Exception
input wire iEVENT_HOLD,
input wire iEVENT_START,
input wire iEVENT_END,
//Pipeline Control - Register Set
input wire iEVENT_SETREG_PCR_SET,
input wire [31:0] iEVENT_SETREG_PCR,
input wire iEXCEPTION_ADDR_SET,
input wire [31:0] iEXCEPTION_ADDR,
//Branch Predict
output wire oBRANCH_PREDICT_FETCH_FLUSH,
input wire iBRANCH_PREDICT_RESULT_JUMP_INST,
input wire iBRANCH_PREDICT_RESULT_PREDICT,
input wire iBRANCH_PREDICT_RESULT_HIT,
input wire iBRANCH_PREDICT_RESULT_JUMP,
input wire [31:0] iBRANCH_PREDICT_RESULT_JUMP_ADDR,
input wire [31:0] iBRANCH_PREDICT_RESULT_INST_ADDR,
//Previous
input wire iPREVIOUS_INST_VALID,
input wire [11:0] iPREVIOUS_MMU_FLAGS,
input wire [31:0] iPREVIOUS_INST,
output wire oPREVIOUS_LOCK,
//Fetch
output wire oPREVIOUS_FETCH_REQ,
input wire iPREVIOUS_FETCH_LOCK,
output wire [1:0] oPREVIOUS_MMUMOD,
output wire [2:0] oPREVIOUS_MMUPS,
output wire [13:0] oPREVIOUS_ASID,
output wire [31:0] oPREVIOUS_PDT,
output wire [31:0] oPREVIOUS_FETCH_ADDR,
//Next
output wire oNEXT_INST_VALID,
output wire [11:0] oNEXT_MMU_FLAGS,
output wire oNEXT_PAGING_ENA,
output wire oNEXT_KERNEL_ACCESS,
output wire oNEXT_BRANCH_PREDICT,
output wire [31:0] oNEXT_BRANCH_PREDICT_ADDR,
output wire [31:0] oNEXT_INST,
output wire [31:0] oNEXT_PC,
input wire iNEXT_FETCH_STOP,
input wire iNEXT_LOCK
);
/****************************************
Register and Wire
****************************************/
//Fetch Address Queue
wire fetch_queue_full;
wire [31:0] fetch_queue_addr;
wire fetch_queue_paging_ena;
wire fetch_queue_kernel_access;
//PC Request
reg [31:0] b_fetch_addr;
reg [1:0] b_fetch_state;
//Next Output Buffer
reg [31:0] b_next_inst;
reg b_next_inst_valid;
reg [11:0] b_next_mmu_flags;
reg b_next_paging_ena;
reg b_next_kernel_access;
reg [31:0] b_pc_out;
//Branch Predict
wire branch_predictor_valid;
wire branch_predictor_predict_branch;
wire [31:0] branch_predictor_addr;
wire branch_predictor_flush;
//Req Control
wire inst_matching_queue_full;
wire inst_matching_queue_valid;
/****************************************
State
****************************************/
localparam PL_STT_IDLE = 2'h0;
localparam PL_STT_READ = 2'h1;
reg [1:0] state;
reg [1:0] b_state;
always@*begin
if(iRESET_SYNC)begin
state = PL_STT_IDLE;
end
else if(iEVENT_END && iEVENT_SETREG_PCR_SET)begin //Jump
state = PL_STT_READ;
end
else if(iEVENT_START)begin
state = PL_STT_IDLE;
end
else if(iEVENT_HOLD)begin
state = PL_STT_IDLE;
end
else if(branch_predictor_flush)begin //Branch Predictor - Predict Branch
state = PL_STT_IDLE;
end
else begin
case(b_state)
PL_STT_IDLE:
begin
state = PL_STT_READ;
end
PL_STT_READ:
begin
state = b_state;
end
default:
begin
state = PL_STT_IDLE;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= 32'h0;
end
else if(iRESET_SYNC)begin
b_state <= 32'h0;
end
else begin
b_state <= state;
end
end //always
wire fetch_valid = b_state == PL_STT_READ;
wire fetch_request_condition = !iEVENT_START && !branch_predictor_flush && fetch_valid && !inst_matching_queue_full && !fetch_queue_full && !iPREVIOUS_FETCH_LOCK && !iNEXT_FETCH_STOP;
/****************************************
Program Counter for Fetch
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_fetch_addr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_fetch_addr <= 32'h0;
end
else if(iEVENT_END && iEVENT_SETREG_PCR_SET)begin //Jump
b_fetch_addr <= {iEVENT_SETREG_PCR[31:1], 1'b0};
end
else if(iEVENT_START)begin
b_fetch_addr<= 32'h0;
end
else if(iEVENT_HOLD)begin
b_fetch_addr <= b_fetch_addr;
end
else if(branch_predictor_flush)begin //Branch Predict
b_fetch_addr <= branch_predictor_addr;
end
else begin
if(fetch_request_condition)begin
b_fetch_addr <= b_fetch_addr + 32'h4;
end
end
end //always
/****************************************
Branch Predictor
****************************************/
//Branch pick up
function func_branch_inst_check;
input [31:0] func_inst;
begin
case(func_inst[30:21])
`OC_BUR,
`OC_BR,
`OC_B : func_branch_inst_check = 1'b1;
default : func_branch_inst_check = 1'b0;
endcase
end
endfunction
`ifdef MIST1032ISA_BRANCH_PREDICT
assign branch_predictor_flush = !iNEXT_LOCK && branch_predictor_valid && branch_predictor_predict_branch && !iEVENT_HOLD;
`else
assign branch_predictor_flush = 1'b0;
`endif
branch_predictor BRANCH_PREDICTOR(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
.iFLUSH(1'b0),
//Search
.iSEARCH_STB(func_branch_inst_check(iPREVIOUS_INST) && iPREVIOUS_INST_VALID),
.iSEARCH_INST_ADDR(fetch_queue_addr),
.oSEARCH_VALID(branch_predictor_valid),
.iSEARCH_LOCK(iNEXT_LOCK),
.oSRARCH_PREDICT_BRANCH(branch_predictor_predict_branch),
.oSEARCH_ADDR(branch_predictor_addr),
//Jump
.iJUMP_STB(iBRANCH_PREDICT_RESULT_JUMP_INST),
.iJUMP_PREDICT(iBRANCH_PREDICT_RESULT_PREDICT),
.iJUMP_HIT(iBRANCH_PREDICT_RESULT_HIT), //hit address (if not predict or not correct addr is 0)
.iJUMP_JUMP(iBRANCH_PREDICT_RESULT_JUMP), //enable predict, if predict miss or not predict is 1
.iJUMP_ADDR(iBRANCH_PREDICT_RESULT_JUMP_ADDR),
.iJUMP_INST_ADDR(iBRANCH_PREDICT_RESULT_INST_ADDR) //Tag[31:5]| Cell Address[4:2] | Byte Order[1:0]
);
/****************************************
Issue & Fetch control
****************************************/
//Matching Queue
mist1032isa_arbiter_matching_queue #(16, 4, 1) INST_MATCHING_QUEUE(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Flash
.iFLASH(iRESET_SYNC || iEVENT_START || branch_predictor_flush),
//Write
.iWR_REQ(oPREVIOUS_FETCH_REQ),
.iWR_FLAG(1'b0),
.oWR_FULL(inst_matching_queue_full),
//Read
.iRD_REQ(iPREVIOUS_INST_VALID && !iNEXT_LOCK),
.oRD_VALID(inst_matching_queue_valid),
.oRD_FLAG(),
.oRD_EMPTY()
);
/****************************************
Fetch Address & Flag Queue
****************************************/
`ifdef MIST1032ISA_ALTERA_PRIMITIVE
//FIFO Mode : Show Ahead Synchronous FIFO Mode
//Width : 34bit
//Depth : 8Word
//Asynchronous Reset : Use
//Synchronous Reset : Use
//Usedw : Use
//Full : Use
//Empty : Use
//Almost Full : Use(Value=2)
//Almost Empty : Use(Value=6)
//Overflow Checking : Disable
//Undesflow Checking : Disable
altera_primitive_sync_fifo_34in_34out_8depth FETCH_REQ_ADDR_QUEUE(
.aclr(!inRESET), //Asynchronous Reset
.clock(iCLOCK), //Clock
.data(
{
!(iSYSREG_PSR[6] || iSYSREG_PSR[5])/*User mode Test 1'b1*/,
(iSYSREG_PSR[1] || iSYSREG_PSR[0]),
b_fetch_addr
}
), //Data-In
.rdreq(iPREVIOUS_INST_VALID && !iNEXT_LOCK), //Read Data Request
.sclr(iRESET_SYNC || iEVENT_START || branch_predictor_flush), //Synchthronous Reset
.wrreq(fetch_request_condition), //Write Req
.almost_empty(),
.almost_full(),
.empty(),
.full(fetch_queue_full),
.q(
{
fetch_queue_kernel_access,
fetch_queue_paging_ena,
fetch_queue_addr
}
), //Dataout
.usedw()
);
`elsif MIST1032ISA_XILINX_PRIMITIVE
`else
mist1032isa_sync_fifo #(34, 8, 3) FETCH_REQ_ADDR_QUEUE(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iREMOVE(iRESET_SYNC || iEVENT_START || branch_predictor_flush),
.oCOUNT(),
.iWR_EN(fetch_request_condition),
.iWR_DATA({!(iSYSREG_PSR[6] || iSYSREG_PSR[5]), (iSYSREG_PSR[1] || iSYSREG_PSR[0]), b_fetch_addr}),
.oWR_FULL(fetch_queue_full),
.iRD_EN(iPREVIOUS_INST_VALID && !iNEXT_LOCK && inst_matching_queue_valid),
.oRD_DATA({fetch_queue_kernel_access, fetch_queue_paging_ena, fetch_queue_addr}),
.oRD_EMPTY()
);
`endif
/****************************************
Fetch
****************************************/
assign oBRANCH_PREDICT_FETCH_FLUSH = branch_predictor_flush;
assign oPREVIOUS_LOCK = iNEXT_LOCK;
assign oPREVIOUS_FETCH_REQ = fetch_request_condition;
assign oPREVIOUS_MMUMOD = iSYSREG_PSR[1:0];
assign oPREVIOUS_MMUPS = iSYSREG_PSR[9:7];
assign oPREVIOUS_ASID = iSYSREG_TIDR[31:18];
assign oPREVIOUS_PDT = (iSYSREG_PSR[6:5] == 2'h0)? iSYSREG_KPDTR : iSYSREG_PDTR;
assign oPREVIOUS_FETCH_ADDR = b_fetch_addr;
/****************************************
Previous -> Next
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_next_inst <= {32{1'b0}};
b_next_inst_valid <= 1'b0;
b_next_mmu_flags <= 12'h0;
b_next_paging_ena <= 1'b0;
b_next_kernel_access <= 1'b0;
b_pc_out <= {32{1'b0}};
end
else if(iRESET_SYNC || iEVENT_START || branch_predictor_flush)begin
b_next_inst <= {32{1'b0}};
b_next_inst_valid <= 1'b0;
b_next_mmu_flags <= 12'h0;
b_next_paging_ena <= 1'b0;
b_next_kernel_access <= 1'b0;
b_pc_out <= {32{1'b0}};
end
else begin
if(!iNEXT_LOCK)begin
b_next_inst <= iPREVIOUS_INST;
b_next_inst_valid <= iPREVIOUS_INST_VALID && inst_matching_queue_valid;
b_next_mmu_flags <= iPREVIOUS_MMU_FLAGS;
b_next_paging_ena <= fetch_queue_paging_ena;
b_next_kernel_access <= fetch_queue_kernel_access;
b_pc_out <= fetch_queue_addr + 32'h4;
end
end
end //always
assign oNEXT_INST_VALID = b_next_inst_valid;
assign oNEXT_INST = b_next_inst;
assign oNEXT_MMU_FLAGS = b_next_mmu_flags;
assign oNEXT_PAGING_ENA = b_next_paging_ena;
assign oNEXT_KERNEL_ACCESS = b_next_kernel_access;
`ifdef MIST1032ISA_BRANCH_PREDICT
assign oNEXT_BRANCH_PREDICT = branch_predictor_valid && branch_predictor_predict_branch;
assign oNEXT_BRANCH_PREDICT_ADDR = branch_predictor_addr;
`else
assign oNEXT_BRANCH_PREDICT = 1'b0;
assign oNEXT_BRANCH_PREDICT_ADDR = 32'h0;
`endif
assign oNEXT_PC = b_pc_out;
endmodule
`default_nettype wire
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The top level of clint module
//
// ====================================================================
module sirv_clint_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_tiles_0_mtip,
output io_tiles_0_msip,
input io_rtcToggle
);
wire io_rtcToggle_r;
sirv_gnrl_dffr #(1) io_rtcToggle_dffr (io_rtcToggle, io_rtcToggle_r, clk, rst_n);
wire io_rtcToggle_edge = io_rtcToggle ^ io_rtcToggle_r;
wire io_rtcTick = io_rtcToggle_edge;
wire io_in_0_a_ready;
assign i_icb_cmd_ready = io_in_0_a_ready;
wire io_in_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_in_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_in_0_a_bits_param = 3'b0;
wire [2:0] io_in_0_a_bits_size = 3'd2;
wire [4:0] io_in_0_a_bits_source = 5'b0;
wire [25:0] io_in_0_a_bits_address = i_icb_cmd_addr[25:0];
wire [3:0] io_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_in_0_a_bits_data = i_icb_cmd_wdata;
wire io_in_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [4:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire [1:0] io_in_0_d_bits_addr_lo;
wire [31:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_d_valid;
assign i_icb_rsp_valid = io_in_0_d_valid;
assign i_icb_rsp_rdata = io_in_0_d_bits_data;
// Not used
wire io_in_0_b_ready = 1'b0;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [4:0] io_in_0_b_bits_source;
wire [25:0] io_in_0_b_bits_address;
wire [3:0] io_in_0_b_bits_mask;
wire [31:0] io_in_0_b_bits_data;
// Not used
wire io_in_0_c_ready;
wire io_in_0_c_valid = 1'b0;
wire [2:0] io_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_in_0_c_bits_param = 3'b0;
wire [2:0] io_in_0_c_bits_size = 3'd2;
wire [4:0] io_in_0_c_bits_source = 5'b0;
wire [25:0] io_in_0_c_bits_address = 26'b0;
wire [31:0] io_in_0_c_bits_data = 32'b0;
wire io_in_0_c_bits_error = 1'b0;
// Not used
wire io_in_0_e_ready;
wire io_in_0_e_valid = 1'b0;
wire io_in_0_e_bits_sink = 1'b0;
sirv_clint u_sirv_clint(
.clock (clk ),
.reset (~rst_n ),
.io_in_0_a_ready (io_in_0_a_ready ),
.io_in_0_a_valid (io_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_in_0_a_bits_data ),
.io_in_0_b_ready (io_in_0_b_ready ),
.io_in_0_b_valid (io_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_in_0_b_bits_data ),
.io_in_0_c_ready (io_in_0_c_ready ),
.io_in_0_c_valid (io_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_in_0_c_bits_error ),
.io_in_0_d_ready (io_in_0_d_ready ),
.io_in_0_d_valid (io_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_in_0_d_bits_error ),
.io_in_0_e_ready (io_in_0_e_ready ),
.io_in_0_e_valid (io_in_0_e_valid ),
.io_in_0_e_bits_sink (io_in_0_e_bits_sink ),
.io_tiles_0_mtip (io_tiles_0_mtip),
.io_tiles_0_msip (io_tiles_0_msip),
.io_rtcTick (io_rtcTick )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s25 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:22:41 03/11/2015
// Design Name: Immediate_Extend
// Module Name: F:/ISE/work/cpu/cpu/Imm_Test.v
// Project Name: cpu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Immediate_Extend
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Imm_Test;
// Inputs
reg [2:0] load;
reg [15:0] data_in;
// Outputs
wire [15:0] data_out;
// Instantiate the Unit Under Test (UUT)
Immediate_Extend uut (
.data_out(data_out),
.load(load),
.data_in(data_in)
);
initial begin
// Initialize Inputs
load = 0;
data_in = 16'b1010101010101010;
// Wait 100 ns for global reset to finish
#50;
// Add stimulus here
load = 1;
#50;
load = 2;
#50;
load = 3;
#50;
load = 4;
#50;
load = 5;
#50;
load = 6;
#50;
load = 0;
data_in = 16'b0101010101010101;
// Wait 100 ns for global reset to finish
#50;
// Add stimulus here
load = 1;
#50;
load = 2;
#50;
load = 3;
#50;
load = 4;
#50;
load = 5;
#50;
load = 6;
#50;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A221O_BEHAVIORAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_BEHAVIORAL_V |
`timescale 1ns / 1ps
module EXMEM
(
// Input
input Clk,
input Reset,
input [31:0] PCIn,
input [2:0] WBIn,
input [1:0] MIn,
input [31:0] ALUResultIn,
// input ALUZeroIn,
input [31:0] MemDataIn,
input [4:0] DstMuxIn,
// Output
output reg [31:0] PCOut,
(* equivalent_register_removal = "no" *) output reg [2:0] WBOut,
(* equivalent_register_removal = "no" *) output reg [1:0] MOut,
output reg [31:0] ALUResultOut,
// output reg ALUZeroOut,
output reg [31:0] MemDataOut,
output reg [4:0] DstMuxOut
);
always @( posedge Clk or posedge Reset )
begin
if ( Reset )
begin
PCOut <= 32'b0;
WBOut <= 2'b0;
MOut <= 2'b0;
ALUResultOut <= 32'b0;
// ALUZeroOut <= 1'b0;
MemDataOut <= 32'b0;
DstMuxOut <= 5'b0;
end
else
begin
PCOut <= PCIn;
WBOut <= WBIn;
MOut <= MIn;
ALUResultOut <= ALUResultIn;
// ALUZeroOut <= ALUZeroIn;
MemDataOut <= MemDataIn;
DstMuxOut <= DstMuxIn;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_mul_cntl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sparc_mul_cntl(
ecl_mul_req_vld,
spu_mul_req_vld,
spu_mul_acc,
spu_mul_areg_shf,
spu_mul_areg_rst,
spu_mul_mulres_lshft,
c0_act,
spick,
byp_sel,
byp_imm,
acc_imm,
acc_actc2,
acc_actc3,
acc_actc5,
acc_reg_enb,
acc_reg_rst,
acc_reg_shf,
x2,
mul_ecl_ack,
mul_spu_ack,
mul_spu_shf_ack,
rst_l,
rclk
);
input rclk;
input rst_l; // System rest
input ecl_mul_req_vld; // Input request from EXU to MUL
input spu_mul_req_vld; // Input request from SPU to MUL
input spu_mul_acc; // 1: SPU mul op req will accumulate the ACCUM register
input spu_mul_areg_shf; // ACCUM shift right 64-bit
input spu_mul_areg_rst; // ACCUM reset; initialization of modular multiplication
input spu_mul_mulres_lshft; // For x2 of op1*op2*2 left shift
output c0_act; // cycle-0 of muliplier operation
output spick;
output byp_sel; // Bypass mux control
output byp_imm;
output acc_imm;
output acc_actc2, acc_actc3; // accumulate enable for LSB-32 and All-96
output acc_actc5; // accumulate enable for LSB-32 and All-96
output acc_reg_enb; // ACCUM register enable
output acc_reg_rst; // ACCUM register reset
output acc_reg_shf; // ACCUM register shift select
output x2;
output mul_ecl_ack; // Ack EXU multiplier operation is accepted.
output mul_spu_ack; // Ack SPU multiplier operation is accepted.
output mul_spu_shf_ack; // Ack SPU shift operation is accepted.
reg mul_ecl_ack_d;
reg mul_spu_ack_d;
reg c1_act; // Squash all mul requests from EXU and SPU if c1_act = 1
reg c2_act; // Squash bypass ACCUM mul request from SPU if c2_act = 1
reg c3_act; // Enable >>32 results back to CSA2 if c3_act = 1
reg favor_e; // Flag for alternate picker, favor to EXU if f_state = 1
reg acc_actc1, acc_actc2, acc_actc3, acc_actc4, acc_actc5;
reg acc_reg_shf, acc_reg_rst;
wire exu_req_vld, spu_req_vld;
wire epick; // Internal pick signals of exu, spu multiplier
wire nobyps; // Squash SPU bypass mul requests nobyps = 1
wire noshft; // Squash SPU bypass mul requests noshft = 1
wire acc_reg_shf_in;
wire spu_mul_byp = ~spu_mul_acc ;
wire clk;
/////////////////////////////////////////
// Requests picker and general control //
/////////////////////////////////////////
assign clk = rclk ;
assign c0_act = epick | spick ; // Cycle0 of multiplier operation
//assign c1_act = mul_ecl_ack_d | mul_spu_ack_d ; // Cycle1 of multiplier operation
assign nobyps = c1_act | acc_actc2 | acc_actc3 | acc_actc4 ; // Cycles prevent the SPU bypass
assign x2 = spick & spu_mul_mulres_lshft;
assign exu_req_vld = ecl_mul_req_vld & ~c1_act ;
assign spu_req_vld = spu_mul_req_vld & ~c1_act & ~(nobyps & spu_mul_byp);
assign epick = exu_req_vld & ( favor_e | ~spu_req_vld) ;
assign spick = spu_req_vld & (~favor_e | ~exu_req_vld) ;
// moved this one cycle earlier
assign mul_spu_ack = rst_l & spick ;
assign mul_ecl_ack = rst_l & epick ;
always @(posedge clk)
begin
mul_ecl_ack_d <= rst_l & epick ;
mul_spu_ack_d <= rst_l & spick ;
c1_act <= rst_l & c0_act ;
c2_act <= rst_l & c1_act ;
c3_act <= rst_l & c2_act ;
favor_e <= rst_l & (mul_spu_ack_d & ~mul_ecl_ack_d);
end
/////////////////////////////////////////////////
// SPU accumulate and bypass and shift control //
/////////////////////////////////////////////////
assign byp_sel = spick & spu_mul_byp ; // SPU bypass operand is picked
//////////////////////////////////////////////////////////////////////////
// No ACCUM >>= 64 allow if there are //
// 1) accumulate mul before cycle4 which need to updated ACCUM //
// 2) Any mul at cyc3 which will use the same output mux at cyc-5 //
//////////////////////////////////////////////////////////////////////////
assign noshft = acc_actc1 | acc_actc2 | c3_act | acc_actc4 ;
// Squash shifr if:
assign acc_reg_shf_in = spu_mul_areg_shf & // No shift request
~noshft & // SPU accum mul in cycle1~4 or EXU mul in cycle3
~acc_reg_shf ; // reset SPU shift request for 1-cycle for signal upate
always @(posedge clk)
begin
acc_reg_shf <= rst_l & acc_reg_shf_in ; // latch ACCUM reg shift control
acc_reg_rst <= spu_mul_areg_rst ; // latch input control of ACCUM reg reset
acc_actc1 <= rst_l & (spick & spu_mul_acc) ; // SPU MAC in cycle 1
acc_actc2 <= rst_l & acc_actc1 ; // SPU MAC in cycle 2
acc_actc3 <= rst_l & acc_actc2 ; // SPU MAC in cycle 3
acc_actc4 <= rst_l & acc_actc3 ; // SPU MAC in cycle 4
acc_actc5 <= rst_l & acc_actc4 ; // SPU MAC in cycle 5
end
assign mul_spu_shf_ack = acc_reg_shf;
assign byp_imm = acc_actc5 ;
assign acc_imm = (acc_actc2 & acc_actc4) | ((acc_actc2 | acc_actc3) & acc_actc5) ;
assign acc_reg_enb = acc_actc5 | acc_reg_shf; // enable of ACCUM registers
endmodule // sparc_mul_cntl
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_1_n,
ddr3_1_p,
ddr3_reset_n,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ras_n,
ddr3_we_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
mdio_mdc,
mdio_mdio,
mii_rst_n,
mii_col,
mii_crs,
mii_rx_clk,
mii_rx_er,
mii_rx_dv,
mii_rxd,
mii_tx_clk,
mii_tx_en,
mii_txd,
linear_flash_addr,
linear_flash_adv_ldn,
linear_flash_ce_n,
linear_flash_dq_io,
linear_flash_oen,
linear_flash_wen,
fan_pwm,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif,
adc_clk_in_n,
adc_clk_in_p,
adc_data_in_n,
adc_data_in_p,
adc_data_or_n,
adc_data_or_p,
spi_clk,
spi_csn_adc,
spi_csn_clk,
spi_sdio
);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [ 2:0] ddr3_1_n;
output [ 1:0] ddr3_1_p;
output ddr3_reset_n;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output ddr3_ras_n;
output ddr3_we_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output mdio_mdc;
inout mdio_mdio;
output mii_rst_n;
input mii_col;
input mii_crs;
input mii_rx_clk;
input mii_rx_er;
input mii_rx_dv;
input [ 3:0] mii_rxd;
input mii_tx_clk;
output mii_tx_en;
output [ 3:0] mii_txd;
output [26:1] linear_flash_addr;
output linear_flash_adv_ldn;
output linear_flash_ce_n;
inout [15:0] linear_flash_dq_io;
output linear_flash_oen;
output linear_flash_wen;
output fan_pwm;
inout [ 6:0] gpio_lcd;
inout [16:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
input adc_clk_in_n;
input adc_clk_in_p;
input [ 7:0] adc_data_in_n;
input [ 7:0] adc_data_in_p;
input adc_data_or_n;
input adc_data_or_p;
output spi_clk;
output spi_csn_adc;
output spi_csn_clk;
inout spi_sdio;
// internal signals
wire [ 1:0] spi_csn;
wire spi_miso;
wire spi_mosi;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
assign ddr3_1_p = 2'b11;
assign ddr3_1_n = 3'b000;
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
assign spi_csn_adc = spi_csn[0];
assign spi_csn_clk = spi_csn[1];
ad9467_spi i_spi (
.spi_csn(spi_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_sdio)
);
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_sw_led (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
.dio_o (gpio_i[16:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio_lcd_tri_io (gpio_lcd),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio0_i (gpio_i[31:0]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio1_i (gpio_i[63:32]),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mb_intr_02 (1'b0),
.mb_intr_03 (1'b0),
.mb_intr_06 (1'b0),
.mb_intr_07 (1'b0),
.mb_intr_08 (1'b0),
.mb_intr_13 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rst_n (mii_rst_n),
.mii_rx_clk (mii_rx_clk),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rxd (mii_rxd),
.mii_tx_clk (mii_tx_clk),
.mii_tx_en (mii_tx_en),
.mii_txd (mii_txd),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_dq_io (linear_flash_dq_io),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.adc_clk_in_n(adc_clk_in_n),
.adc_clk_in_p(adc_clk_in_p),
.adc_data_in_n(adc_data_in_n),
.adc_data_in_p(adc_data_in_p),
.adc_data_or_n(adc_data_or_n),
.adc_data_or_p(adc_data_or_p),
.spi_clk_i(1'b0),
.spi_clk_o(spi_clk),
.spi_csn_i(1'b1),
.spi_csn_o(spi_csn),
.spi_sdi_i(spi_miso),
.spi_sdo_i(1'b0),
.spi_sdo_o(spi_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_1_V
`define SKY130_FD_SC_HDLL__OR3_1_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:50:37 03/16/2014
// Design Name:
// Module Name: Core_TB
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Core_TB(
);
reg clk;
reg nrst;
wire[31:0] instr;
wire[31:0] IFID_instr;
wire[31:0] IDEX_instr;
wire[31:0] EXMEM_instr;
wire[31:0] MEMWB_instr;
wire[31:0] iaddr;
wire[5:0] daddr;
wire[31:0] dout;
wire[31:0] MEMWB_dout;
wire[3:0] wr;
wire[3:0] EXMEM_wr;
wire[31:0] pc;
wire[31:0] IFID_pc;
wire[31:0] IDEX_pc;
wire[31:0] EXMEM_pc;
wire[31:0] reg_din;
wire[4:0] reg_raddr1;
wire[31:0] reg_dout1;
wire[31:0] IDEX_reg_dout1;
wire[4:0] reg_raddr2;
wire[31:0] reg_dout2;
wire[31:0] IDEX_reg_dout2;
wire[31:0] EXMEM_reg_dout2;
wire wr_reg;
wire EXMEM_wr_reg;
wire MEMWB_wr_reg;
wire[4:0] reg_wr_addr;
wire[31:0] ALUOut;
wire[31:0] EXMEM_ALUOut;
wire[31:0] MEMWB_ALUOut;
wire[3:0] ALUOp;
wire ALUSrc;
wire[31:0] ALUIn2;
wire MemToReg;
wire EXMEM_MemToReg;
wire MEMWB_MemToReg;
wire RegDst;
wire EXMEM_RegDst;
wire MEMWB_RegDst;
wire PCSrc;
wire[31:0] ram1;
wire[31:0] ram2;
wire[31:0] ram3;
wire Zero;
wire Branch;
wire Jump;
wire[1:0] M2_Select;
wire[1:0] M3_Select;
wire M7_Select;
wire[31:0] F4F8;
wire[31:0] F2F6;
wire[31:0] F1F5;
wire[31:0] F3F7;
wire[31:0] F9;
wire[31:0] F10;
wire[4:0] IFID_RegisterRd;
wire[4:0] IFID_RegisterRt;
wire[4:0] IFID_RegisterRs;
wire[4:0] IDEX_RegisterRd;
wire[4:0] IDEX_RegisterRt;
wire[4:0] IDEX_RegisterRs;
wire[4:0] EXMEM_RegisterRd;
wire[4:0] EXMEM_RegisterRt;
wire[4:0] EXMEM_RegisterRs;
wire[4:0] MEMWB_RegisterRd;
wire[4:0] MEMWB_RegisterRt;
wire[4:0] MEMWB_RegisterRs;
Core c (
clk,
nrst,
instr,
IFID_instr,
IDEX_instr,
EXMEM_instr,
MEMWB_instr,
//iaddr,
daddr,
dout,
MEMWB_dout,
wr,
EXMEM_wr,
pc,
IFID_pc,
IDEX_pc,
EXMEM_pc,
reg_din,
reg_raddr1,
reg_dout1,
IDEX_reg_dout1,
reg_raddr2,
reg_dout2,
IDEX_reg_dout2,
EXMEM_reg_dout2,
wr_reg,
EXMEM_wr_reg,
MEMWB_wr_reg,
reg_wr_addr,
ALUOut,
EXMEM_ALUOut,
MEMWB_ALUOut,
ALUOp,
ALUSrc,
ALUIn2,
MemToReg,
EXMEM_MemToReg,
MEMWB_MemToReg,
RegDst,
EXMEM_RegDst,
MEMWB_RegDst,
PCSrc,
ram1,
ram2,
ram3,
Zero,
Branch,
Jump,
M3_Select,
M2_Select,
M7_Select,
F4F8,
F2F6,
F1F5,
F3F7,
F9,
F10,
IFID_RegisterRd,
IFID_RegisterRt,
IFID_RegisterRs,
IDEX_RegisterRd,
IDEX_RegisterRt,
IDEX_RegisterRs,
EXMEM_RegisterRd,
EXMEM_RegisterRt,
EXMEM_RegisterRs,
MEMWB_RegisterRd,
MEMWB_RegisterRt,
MEMWB_RegisterRs
);
initial
begin
clk = 0;
forever begin
#20 clk = ~clk;
end
end
initial
begin
nrst = 0;
#75
nrst = 1;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_aluor32.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_aluor32
// Description: This block performs a 32 bit OR of the input source.
// The result is the output nonzero.
*/
module sparc_exu_aluor32
(/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in; // input to be compared to zero
output out; // or of input bits
wire nor1_1;
wire nor1_2;
wire nor1_3;
wire nor1_4;
wire nor1_5;
wire nor1_6;
wire nor1_7;
wire nor1_8;
wire nor1_9;
wire nor1_10;
wire nor1_11;
wire nor1_12;
wire nor1_13;
wire nor1_14;
wire nor1_15;
wire nor1_16;
wire nand2_1;
wire nand2_2;
wire nand2_3;
wire nand2_4;
wire inv3_1;
wire inv3_2;
wire inv3_3;
wire inv3_4;
assign nor1_1 = ~(in[1] | in[0]);
assign nor1_2 = ~(in[3] | in[2]);
assign nor1_3 = ~(in[5] | in[4]);
assign nor1_4 = ~(in[7] | in[6]);
assign nor1_5 = ~(in[9] | in[8]);
assign nor1_6 = ~(in[11] | in[10]);
assign nor1_7 = ~(in[13] | in[12]);
assign nor1_8 = ~(in[15] | in[14]);
assign nor1_9 = ~(in[17] | in[16]);
assign nor1_10 = ~(in[19] | in[18]);
assign nor1_11 = ~(in[21] | in[20]);
assign nor1_12 = ~(in[23] | in[22]);
assign nor1_13 = ~(in[25] | in[24]);
assign nor1_14 = ~(in[27] | in[26]);
assign nor1_15 = ~(in[29] | in[28]);
assign nor1_16 = ~(in[31] | in[30]);
assign nand2_1 = ~(nor1_1 & nor1_2 & nor1_3 & nor1_4);
assign nand2_2 = ~(nor1_5 & nor1_6 & nor1_7 & nor1_8);
assign nand2_3 = ~(nor1_9 & nor1_10 & nor1_11 & nor1_12);
assign nand2_4 = ~(nor1_13 & nor1_14 & nor1_15 & nor1_16);
assign inv3_1 = ~nand2_1;
assign inv3_2 = ~nand2_2;
assign inv3_3 = ~nand2_3;
assign inv3_4 = ~nand2_4;
assign out = ~(inv3_1 & inv3_2 & inv3_3 & inv3_4);
endmodule // sparc_exu_aluor32
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_RESET_EDGE_HEAD or `BSV_RESET_EDGE dRST
`else
`define BSV_RESET_EDGE_HEAD
`endif
// A clock synchronization FIFO where the enqueue and dequeue sides are in
// different clock domains.
// There are no restrictions w.r.t. clock frequencies
// The depth of the FIFO must be a power of 2 (2,4,8,...) since the
// indexing uses a Gray code counter.
// FULL and EMPTY signal are pessimistic, that is, they are asserted
// immediately when the FIFO becomes FULL or EMPTY, but their deassertion
// is delayed due to synchronization latency.
// dCount and sCount are also delayed and may differ because of latency
// from the synchronization logic
module SyncFIFOLevel(
sCLK,
sRST,
dCLK,
sENQ,
sD_IN,
sFULL_N,
dDEQ,
dD_OUT,
dEMPTY_N,
dCOUNT,
sCOUNT,
sCLR,
sCLR_RDY,
dCLR,
dCLR_RDY
) ;
parameter dataWidth = 1 ;
parameter depth = 2 ; // minimum 2
parameter indxWidth = 1 ; // minimum 1
// input clock domain ports
input sCLK ;
input sRST ;
input sENQ ;
input [dataWidth -1 : 0] sD_IN ;
output sFULL_N ;
// destination clock domain ports
input dCLK ;
input dDEQ ;
output dEMPTY_N ;
output [dataWidth -1 : 0] dD_OUT ;
// Counts of capacity need extra bit to show full, e.g., range is 0 to 32
output [indxWidth : 0] dCOUNT;
output [indxWidth : 0] sCOUNT;
// Clear signals on both domains
input sCLR;
output sCLR_RDY;
input dCLR;
output dCLR_RDY;
// constants for bit masking of the gray code
wire [indxWidth : 0] msbset = ~({(indxWidth + 1){1'b1}} >> 1) ;
wire [indxWidth - 1 : 0] msb2set = ~({(indxWidth + 0){1'b1}} >> 1) ;
wire [indxWidth : 0] msb12set = msbset | {1'b0, msb2set} ; // 'b11000...
// FIFO Memory
reg [dataWidth -1 : 0] fifoMem [0: depth -1 ] ;
reg [dataWidth -1 : 0] dDoutReg ;
// Enqueue Pointer
reg [indxWidth : 0] sGEnqPtr, sBEnqPtr ; // Flops
reg sNotFullReg ;
wire [indxWidth : 0] sNextGEnqPtr, sNextBEnqPtr ;
wire [indxWidth : 0] sNextCnt, sFutureCnt ;
wire sNextNotFull, sFutureNotFull ;
// Dequeue Pointer
reg [indxWidth : 0] dGDeqPtr, dBDeqPtr ; // Flops
reg dNotEmptyReg ;
wire [indxWidth : 0] dNextGDeqPtr, dNextBDeqPtr ;
wire [indxWidth : 0] dNextCnt ;
wire dNextNotEmpty;
// Rgisters needed for capacity counts
reg [indxWidth : 0] sCountReg, dCountReg ;
// Note for Timing improvement:
// These signals can be registers to improve a long path from the
// second stage of the synchronizer to the input of the
// CountReg. The path includes a Gray to Binary conversion and a
// subtraction, which can easily be a long path.
// The effect is that the count is delayed one additional cycle.
wire [indxWidth : 0] sBDeqPtr, dBEnqPtr ;
// flops to sychronize enqueue and dequeue point across domains
reg [indxWidth : 0] dSyncReg1, dEnqPtr ;
reg [indxWidth : 0] sSyncReg1, sDeqPtr ;
// Indexes for fifo memory is one bit smaller than indexes
wire [indxWidth - 1 :0] sEnqPtrIndx, dDeqPtrIndx ;
// wires needed for clear processing
wire dRST;
wire sCLRSynced; // dCLR synced to sCLK
wire sCLR_RDY_int;
wire dCLRSynced; // sCLR synced to dCLK
wire dCLR_RDY_int;
wire sClear;
wire dClear;
// Clear processing requires the use of 2 handshake synchronizers
SyncHandshake #(.delayreturn(1))
sClrSync ( .sCLK(sCLK),
.sRST(sRST),
.dCLK(dCLK),
.sEN(sCLR),
.sRDY(sCLR_RDY_int),
.dPulse(dCLRSynced));
SyncHandshake #(.delayreturn(1))
dClrSync ( .sCLK(dCLK),
.sRST(sRST),
.dCLK(sCLK),
.sEN(dCLR),
.sRDY(dCLR_RDY_int),
.dPulse(sCLRSynced));
// Outputs
assign dD_OUT = dDoutReg;
assign dEMPTY_N = dNotEmptyReg ;
assign sFULL_N = sNotFullReg ;
assign sCOUNT = sCountReg;
assign dCOUNT = dCountReg;
assign sCLR_RDY = sCLR_RDY_int;
assign dCLR_RDY = dCLR_RDY_int;
// Indexes are truncated from the Binary counter
assign sEnqPtrIndx = sBEnqPtr[indxWidth-1:0] ;
assign dDeqPtrIndx = dBDeqPtr[indxWidth-1:0] ;
// clear signals
assign sClear = sCLR || !sCLR_RDY_int || sCLRSynced;
assign dClear = dCLR || !dCLR_RDY_int || dCLRSynced;
assign dRST = sRST;
// Fifo memory write
always @(posedge sCLK)
begin
if ( sENQ )
fifoMem[sEnqPtrIndx] <= `BSV_ASSIGNMENT_DELAY sD_IN ;
end // always @ (posedge sCLK)
////////////////////////////////////////////////////////////////////////
// Enqueue Pointer and increment logic
assign sNextBEnqPtr = sBEnqPtr + 1'b1 ;
assign sNextGEnqPtr = sNextBEnqPtr ^ (sNextBEnqPtr >> 1) ;
assign sNextNotFull = (sGEnqPtr ^ msb12set) != sDeqPtr ;
assign sFutureNotFull = (sNextGEnqPtr ^ msb12set) != sDeqPtr ;
assign sNextCnt = sBEnqPtr - sBDeqPtr ;
assign sFutureCnt = sNextBEnqPtr - sBDeqPtr ;
assign sBDeqPtr = grayToBinary( sDeqPtr ) ;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sBEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
sGEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
sNotFullReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ; // Mark as full during reset
sCountReg <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
if (sClear)
begin
sBEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
sGEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
sNotFullReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
sCountReg <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
end
else if ( sENQ )
begin
sBEnqPtr <= `BSV_ASSIGNMENT_DELAY sNextBEnqPtr ;
sGEnqPtr <= `BSV_ASSIGNMENT_DELAY sNextGEnqPtr ;
sNotFullReg <= `BSV_ASSIGNMENT_DELAY sFutureNotFull ;
sCountReg <= `BSV_ASSIGNMENT_DELAY sFutureCnt ;
end
else
begin
sNotFullReg <= `BSV_ASSIGNMENT_DELAY sNextNotFull ;
sCountReg <= `BSV_ASSIGNMENT_DELAY sNextCnt ;
end // else: !if( sENQ )
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
// Enqueue pointer synchronizer to dCLK
always @(posedge dCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
dEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sGEnqPtr ; // Clock domain crossing
dEnqPtr <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Enqueue Pointer and increment logic
assign dNextBDeqPtr = dBDeqPtr + 1'b1 ;
assign dNextGDeqPtr = dNextBDeqPtr ^ (dNextBDeqPtr >> 1) ;
assign dNextNotEmpty = dGDeqPtr != dEnqPtr ;
assign dNextCnt = dBEnqPtr - dBDeqPtr ;
assign dBEnqPtr = grayToBinary( dEnqPtr ) ;
always @(posedge dCLK or `BSV_RESET_EDGE dRST)
begin
if (dRST == `BSV_RESET_VALUE)
begin
dBDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
dGDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ; // Mark as empty to avoid dequeues until after reset
dCountReg <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
if (dClear) begin
dBDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
dGDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
dCountReg <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
end
else if (!dNotEmptyReg && dNextNotEmpty) begin
dBDeqPtr <= `BSV_ASSIGNMENT_DELAY dNextBDeqPtr ;
dGDeqPtr <= `BSV_ASSIGNMENT_DELAY dNextGDeqPtr ;
dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b1 ;
dCountReg <= `BSV_ASSIGNMENT_DELAY dNextCnt ;
end
else if (dDEQ && dNextNotEmpty) begin
dBDeqPtr <= `BSV_ASSIGNMENT_DELAY dNextBDeqPtr ;
dGDeqPtr <= `BSV_ASSIGNMENT_DELAY dNextGDeqPtr ;
dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b1 ;
dCountReg <= `BSV_ASSIGNMENT_DELAY dNextCnt ;
end
else if (dDEQ && !dNextNotEmpty) begin
dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
dCountReg <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
end
else begin
dCountReg <= `BSV_ASSIGNMENT_DELAY dNextCnt ;
end
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
always @(posedge dCLK `BSV_RESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (dRST == `BSV_RESET_VALUE)
begin
dDoutReg <= `BSV_ASSIGNMENT_DELAY { dataWidth { 1'b0 }} ;
end // if (dRST == `BSV_RESET_VALUE)
else
`endif
begin
if ((!dNotEmptyReg || dDEQ) && dNextNotEmpty) begin
dDoutReg <= `BSV_ASSIGNMENT_DELAY fifoMem[dDeqPtrIndx] ;
end
end
end
// Dequeue pointer synchronized to sCLK
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
sDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY dGDeqPtr ; // clock domain crossing
sDeqPtr <= `BSV_ASSIGNMENT_DELAY sSyncReg1 ;
// sBDeqPtr <= `BSV_ASSIGNMENT_DELAY grayToBinary( sDeqPtr ) ;
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
////////////////////////////////////////////////////////////////////////
// synopsys translate_off
// Run time assertion check
always @(posedge sCLK)
begin
if ( sENQ && ! sNotFullReg ) $display ("Warning: SyncFIFOLevel: %m -- Enqueing to a full fifo");
end
always @(posedge dCLK)
begin
if ( dDEQ && ! dNotEmptyReg ) $display ("Warning: SyncFIFOLevel: %m -- Dequeuing from empty fifo");
end
// synopsys translate_on
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initBlock
integer i ;
// initialize the FIFO memory with aa's
for (i = 0; i < depth; i = i + 1)
begin
fifoMem[i] = {((dataWidth + 1)/2){2'b10}} ;
end
dDoutReg = {((dataWidth + 1)/2){2'b10}} ;
// initialize the pointer
sGEnqPtr = {((indxWidth + 1)/2){2'b10}} ;
sBEnqPtr = sGEnqPtr ;
sNotFullReg = 1'b0 ;
dGDeqPtr = sGEnqPtr ;
dBDeqPtr = sGEnqPtr ;
dNotEmptyReg = 1'b0;
// initialize other registers
sSyncReg1 = sGEnqPtr ;
sDeqPtr = sGEnqPtr ;
dSyncReg1 = sGEnqPtr ;
dEnqPtr = sGEnqPtr ;
end // initial begin
// synopsys translate_on
// synopsys translate_off
initial
begin : parameter_assertions
integer ok ;
integer i, expDepth ;
ok = 1;
expDepth = 1 ;
// calculate x = 2 ** (indxWidth - 1)
for( i = 0 ; i < indxWidth ; i = i + 1 )
begin
expDepth = expDepth * 2 ;
end
if ( expDepth != depth )
begin
ok = 0;
$display ( "ERROR SyncFiFOLevel.v: index size and depth do not match;" ) ;
$display ( "\tdepth must equal 2 ** index size. expected %0d", expDepth );
end
#0
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
function [indxWidth:0] grayToBinary ;
input [indxWidth:0] grayin;
begin: grayToBinary_block
reg [indxWidth:0] binary ;
integer i ;
for ( i = 0 ; i <= indxWidth ; i = i+1 )
begin
binary[i] = ^( grayin >> i ) ;
end
grayToBinary = binary ;
end
endfunction
endmodule // FIFOSync
`ifdef testBluespec
module testSyncFIFOLevel() ;
parameter dsize = 8;
parameter fifodepth = 32;
parameter fifoidx = 5;
wire sCLK, dCLK, dRST ;
wire sENQ, dDEQ;
wire sFULL_N, dEMPTY_N ;
wire [dsize -1:0] sDIN, dDOUT ;
reg [dsize -1:0] sCNT, dCNT ;
reg sRST ;
wire [fifoidx:0] dItemCnt, sItemCnt ;
wire sCLR_RDY;
wire dCLR_RDY;
wire sCLR;
wire dCLR;
reg [31:0] count ;
reg started ;
reg ddeq ;
ClockGen#(14,15,10) sc( sCLK );
ClockGen#(11,12,2600) dc( dCLK ); // Pause the generation of the destination side clock
initial
begin
sCNT = 0;
dCNT = 0;
sRST = `BSV_RESET_VALUE ;
count = 0;
started = 0;
ddeq = 0;
$display( "running test" ) ;
$dumpfile("SyncFIFOLevel.vcd");
$dumpvars(10,testSyncFIFOLevel) ;
#1
$dumpon ;
#200 ;
sRST = !`BSV_RESET_VALUE ;
#50000 $finish ;
end
SyncFIFOLevel #(dsize,fifodepth,fifoidx)
dut( sCLK, sRST, dCLK, sENQ, sDIN,
sFULL_N, dDEQ, dDOUT, dEMPTY_N, dItemCnt, sItemCnt,
sCLR, sCLR_RDY, dCLR, dCLR_RDY );
assign sDIN = sCNT ;
assign sENQ = sFULL_N ;
assign dCLR = ((count[7:0] == 8'b0010_0011) && dCLR_RDY);
assign sCLR = ((count[7:0] == 8'b0000_0001) && sCLR_RDY);
always @(posedge sCLK)
begin
count <= count + 1 ;
$display( "scount is %d", sItemCnt ) ;
if (sENQ )
begin
sCNT <= `BSV_ASSIGNMENT_DELAY sCNT + 1;
$display( "enqueuing is %d", sCNT ) ;
end // if (sENQ )
end // always @ (posedge sCLK)
assign dDEQ = ddeq ;
always @(dItemCnt or dEMPTY_N or started or count)
begin
ddeq = (count > 40) && dEMPTY_N && (started || dItemCnt > 4);
end // always @ (dItemCnt or dEMPTY_N or started)
always @(posedge dCLK)
begin
$display( "dcount is %d", dItemCnt ) ;
if (ddeq)
begin
started <= 1;
$display( "dequeing %d", dDOUT ) ;
end // if (dDEQ )
else
begin
started <= 0;
end
end // always @ (posedge dCLK)
endmodule // testSyncFIFO
`endif
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