text
stringlengths 938
1.05M
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module Mod_Teste_LCD (
// Parte 1
//////////////////// LCD Module 16X2 ////////////////
LCD_ON, // LCD Power ON/OFF
LCD_BLON, // LCD Back Light ON/OFF
LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN, // LCD Enable
LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA, // LCD Data bus 8 bits
GPIO_0, // GPIO
GPIO_1,
);
// Parte 2
//////////////////// LCD Module 16X2 ////////////////////////////
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
////////////////////////////////////////////////////////////////////
// All inout port turn to tri-state
assign GPIO_1 = 36'hzzzzzzzzz;
assign GPIO_0 = 36'hzzzzzzzzz;
// LCD
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
LCD_TEST u5 (
// Host Side
.iCLK ( CLOCK_50 ),
.iRST_N ( KEY[0] ),
// Data to display
.d0 (16'h0000), // 4 dígitos canto superior esquerdo
.d1 (16'h1111), // 4 dígitos superior meio
.d2 (16'h2222), // 4 dígitos canto superior direito
.d3 (16'h3333), // 4 dígitos canto inferior esquerdo
.d4 (16'h4444), // 4 dígitos inferior meio
.d5 (16'h5555), // 4 dígitos canto inferior direito
// LCD Side
.LCD_DATA( LCD_DATA ),
.LCD_RW ( LCD_RW ),
.LCD_EN ( LCD_EN ),
.LCD_RS ( LCD_RS )
);
endmodule
|
module mojo_top(
input clk,
input rst_n,
input cclk,
output[7:0]led,
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
output [3:0] spi_channel,
input avr_tx,
output avr_rx,
input avr_rx_busy,
output sdram_clk,
output sdram_cle,
output sdram_dqm,
output sdram_cs,
output sdram_we,
output sdram_cas,
output sdram_ras,
output [1:0] sdram_ba,
output [12:0] sdram_a,
inout [7:0] sdram_dq
);
wire rst = ~rst_n;
wire fclk;
wire pllLock;
wire pllFeedbackClk;
PLL_BASE#(
.BANDWIDTH ("OPTIMIZED"),
.CLKFBOUT_MULT (10),
.CLKFBOUT_PHASE (0.0),
.CLKIN_PERIOD ("20"),
.CLKOUT0_DIVIDE (5),
.CLKOUT0_DUTY_CYCLE (0.5),
.CLKOUT0_PHASE (0.0),
.CLK_FEEDBACK ("CLKFBOUT"),
//.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (1),
.REF_JITTER (0.1),
.RESET_ON_LOSS_OF_LOCK ("FALSE")
)
PLL_BASE_inst(
.CLKFBOUT (pllFeedbackClk),
.CLKOUT0 (fclk),
.LOCKED (pllLock),
.CLKFBIN (pllFeedbackClk),
.CLKIN (clk),
.RST (rst)
);
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
wire [22:0] addr;
wire rw;
wire [31:0] data_in, data_out;
wire busy;
wire in_valid, out_valid;
//sdram_clk_gen clkram_clk_gen (
// .clk_in(clk),
// .clk_out(fclk)
// );
sdram sdram (
.clk(fclk),
.rst(rst),
.sdram_clk(sdram_clk),
.sdram_cle(sdram_cle),
.sdram_cs(sdram_cs),
.sdram_cas(sdram_cas),
.sdram_ras(sdram_ras),
.sdram_we(sdram_we),
.sdram_dqm(sdram_dqm),
.sdram_ba(sdram_ba),
.sdram_a(sdram_a),
.sdram_dq(sdram_dq),
.addr(addr),
.rw(rw),
.data_in(data_in),
.data_out(data_out),
.busy(busy),
.in_valid(in_valid),
.out_valid(out_valid)
);
ram_test ram_test (
.clk(fclk),
.rst(rst),
.addr(addr),
.rw(rw),
.data_in(data_in),
.data_out(data_out),
.busy(busy),
.in_valid(in_valid),
.out_valid(out_valid),
.leds(led)
);
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:58:11 11/03/2014
// Design Name:
// Module Name: FSM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM(
input [31:0] x, // x Input to FSM from Mux
input [31:0] y, // y Input to FSM from Mux
input [31:0] z, // z Input to FSM from Mux
input [31:0] k, // k Input to FSM from Mux
input [31:0] kappa_LUTRot,
input [31:0] theta_LUTRot,
input [31:0] delta_LUTRot,
input [31:0] kappa_LUTVec,
input [31:0] theta_LUTVec,
input [31:0] delta_LUTVec,
input [31:0] theta_LUT, // theta Input to FSM from LUT
input [31:0] kappa_LUT, // kappa Input to FSM from LUT
input [31:0] delta_LUT, // delta Input to FSM from LUT
input [1:0] mode, // Linear: 00 Hyperbolic: 11 Circular: 01
input operation, // operation = 1 is rotation. operation = 0 is vectoring
input clock,
input done_LUTRot,
input done_LUTVec,
input done_LUT, // Done bit set by LUT after look up
output reg enable_LUT, // Enable bit set by FSM to enable LUT
output reg [7:0] address, // Address field to LUT
output reg [31:0] theta_out, // theta Output to ALU
output reg [31:0] kappa_out, // kappa Output to ALU
output reg [31:0] delta_out, // delta Output to ALU
output reg done_FSM,
output reg [31:0] x_final,
output reg [31:0] y_final,
output reg [31:0] z_final,
output reg [31:0] k_final,
//output reg converge,
input done_ALU
);
// In rotation operation if this is from 0 to -12, a look up operation is performed (look up condition).
// In vectoring operation, this is used to check look up conditions and to decide exponent of theta and delta.
reg [7:0] exponent;
reg converge;
always @ (*)
begin
// If rotation operation, calculate exponent by subtracting 127 from Ze
if (operation == 1'b1)
begin
exponent <= 8'b01111111 - z[30:23];
end
// If vectoring operation, calculatr exponent by subtracting Xe and Ye
else if (operation == 1'b0)
begin
exponent <= x[30:23] - y[30:23];
end
/* // If LUT was enabled and if LUT has performed its operation, store the LUT values into output registers.
if ((done_LUT == 1'b1 || done_LUTRot == 1'b1 || done_LUTVec == 1'b1) && enable_LUT == 1'b1)
begin
// In vectoring operation, if it is linear mode or if the exponent value is less than -12,
// replace the exponent of theta and delta.
if ( (operation == 1'b0) && (mode == 2'b00 || (exponent <= 8'b11110011 && exponent > 8'b10000000)))
begin
delta_out <= delta_LUT;
delta_out[30:23] <= exponent + 8'b01111111;
theta_out <= theta_LUT;
theta_out[30:23] <= exponent + 8'b01111111;
enable_LUT <= 1'b0;
done_FSM <= 1'b1;
end
else if (operation == 1'b1)
begin
theta_out[31] <= ~z[31];
delta_out[31] <= ~z[31];
theta_out[30:0] <= theta_LUTRot[30:0];
delta_out[30:0] <= delta_LUTRot[30:0];
kappa_out <= kappa_LUTRot;
enable_LUT <= 1'b0;
done_FSM <= 1'b1;
end
// In all other conditions just transfer. This means vectoring operation for circular and hyperbolic mode
else
begin
theta_out <= theta_LUTVec;
delta_out <= delta_LUTVec;
kappa_out <= kappa_LUTVec;
enable_LUT <= 1'b0;
done_FSM <= 1'b1;
end
end*/
end
always @ (posedge clock)
begin
// If LUT was enabled and if LUT has performed its operation, store the LUT values into output registers.
if ((done_LUT == 1'b1 || done_LUTRot == 1'b1 || done_LUTVec == 1'b1) && enable_LUT == 1'b1)
begin
// In vectoring operation, if it is linear mode or if the exponent value is less than -12,
// replace the exponent of theta and delta.
if ((operation == 1'b0) && (mode == 2'b00 || (exponent <= 8'b11110011 && exponent > 8'b10000000)))
begin
delta_out <= delta_LUT;
delta_out[30:23] <= exponent + 8'b01111111;
theta_out <= theta_LUT;
theta_out[30:23] <= exponent + 8'b01111111;
enable_LUT <= 1'b0;
done_FSM <= 1'b1;
end
else if (operation == 1'b1)
begin
theta_out[31] <= ~z[31];
delta_out[31] <= ~z[31];
theta_out[30:0] <= theta_LUTRot[30:0];
delta_out[30:0] <= delta_LUTRot[30:0];
kappa_out <= kappa_LUTRot;
enable_LUT <= 1'b0;
done_FSM <= 1'b1;
end
// In all other conditions just transfer. This means vectoring operation for circular and hyperbolic mode
else
begin
theta_out <= theta_LUTVec;
delta_out <= delta_LUTVec;
kappa_out <= kappa_LUTVec;
enable_LUT <= 1'b0;
done_FSM <= 1'b1;
end
end
// If ALU has finished work, disable it.
if (done_ALU == 1'b1)
begin
done_FSM <= 1'b0;
end
// Rotation Operation
if (operation == 1'b1)
begin
if (z[30:23] <= 8'b01110000)
begin
converge <= 1'b1;
x_final <= x;
y_final <= y;
z_final <= z;
k_final <= k;
end
// Linear mode
else if (mode == 2'b00)
begin
theta_out[30:0] <= z[30:0];
delta_out[30:0] <= z[30:0];
theta_out[31] <= ~z[31];
delta_out[31] <= ~z[31];
kappa_out <= 32'h3F800000;
done_FSM <= 1'b1;
end
// Hyperbolic mode and Ze > 127
// No look up is required.
else if (mode == 2'b11 && z[30:23] >= 8'b01111111)
begin
theta_out <= 32'hBF800000;
delta_out <= 32'hBF42F7D6;
//kappa_out <= 32'h3F25E6E3;
kappa_out <= 32'h3FC583AB;
done_FSM <= 1'b1;
end
// Circular Rotation and Ze > 127
// No look up is required.
else if (mode == 2'b01 && z[30:23] >= 8'b01111111)
begin
theta_out <= 32'hBF800000;
delta_out <= 32'hBFC75923;
kappa_out <= 32'h3FECE788;
done_FSM <= 1'b1;
end
// If Ze > 114 and Ze < 127 and not Linear mode
// Here look up is needed. The address is generated by taking 4 bits of the exponent (0-12)
// The next 4 bits are the first 4 bits of the mantissa.
else if (mode != 2'b00 && z[30:23] < 8'b01111111 && z[30:23] > 8'b01110011)
begin
address[7:4] <= exponent[3:0];
address[3:0] <= z[22:19];
enable_LUT <= 1'b1;
end
// If Ze < 114 and not in linear mode
// No look up is needed. The negative value of z is fed as theta and delta.
else if (mode != 2'b00 && z[30:23] <= 8'b01110011)
begin
theta_out[30:0] <= z[30:0];
delta_out[30:0] <= z[30:0];
theta_out[31] <= ~z[31];
delta_out[31] <= ~z[31];
kappa_out <= 32'h3F800000;
done_FSM <= 1'b1;
end
end
// Vectoring operation
else if (operation == 1'b0)
begin
if (z[30:23] <= 8'b01110000)
begin
converge <= 1'b1;
end
// In linear mode the address is formed by 4 bits of Mx (mantissa of x) and 4 bits of My.
// The exponent of the theta and delta is decided by the exponent reg value. ie Xe - Ye.
else if (mode == 2'b00)
begin
address[7:4] <= x[22:19];
address[3:0] <= y[22:19];
kappa_out <= 32'h3F8;
enable_LUT <= 1'b1;
end
// If it is not linear mode and exponent is between 0 and -12, LUT is performed.
// The first 4 bits of exponent are to determine (0-12). The next 4 bits are 2 bits of Mx and 2 bits of My each
else if (mode != 2'b00 && exponent > 8'b11110011 && exponent <= 8'b11111111)
begin
address[7:4] <= exponent[3:0];
address[3:2] <= x[22:21];
address[1:0] <= y[22:21];
enable_LUT <= 1'b1;
end
// If not linear and exponent is less than -12, then the look up is performed same as in linear mode.
// ie address has only 4 bits of My and 4 bits of Mx.
else if (mode != 2'b00 && exponent <= 8'b11110011 && exponent > 8'b10000000)
begin
address[7:4] <= x[22:19];
address[3:0] <= y[22:19];
kappa_out <= 32'h3F8;
enable_LUT <= 1'b1;
end
// In case of Hyperbolic and greater than 0 no look up table is needed.
else if (mode == 2'b11 && exponent <= 8'b10000000)
begin
delta_out <= 32'h3F733333;
theta_out <= 32'h3FEA77CB;
kappa_out <= 32'h3E9FDF38; // wrong value. Redo
done_FSM <= 1'b1;
end
// In case of Circular and greater than 0 no look up table is needed.
else if (mode == 2'b01 && exponent <= 8'b10000000)
begin
delta_out <= 32'h3F8; //wrong value. Redo
theta_out <= 32'h3F490FDB;
kappa_out <= 32'h3FB504F4;
done_FSM <= 1'b1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_PS_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_DFF_PS_SYMBOL_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$PS (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_PS_SYMBOL_V
|
/*******************************************************************************
* Module: simul_axi_read
* Date:2014-04-06
* Author: Andrey Filippov
* Description: simulation of read data through maxi channel
*
* Copyright (c) 2014 Elphel, Inc.
* simul_axi_read.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_axi_read.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module simul_axi_read #(
parameter ADDRESS_WIDTH=10
)(
input clk,
input reset,
input last, // last data word in burst
input data_stb, // data strobe (RVALID & RREADY) genearted externally
input [ADDRESS_WIDTH-1:0] raddr, // read burst address as written by axi master, 10 significant bits [11:2], valid at rcmd
input [ 3:0] rlen, // burst length as written by axi master, valid at rcmd
input rcmd, // read command (address+length) strobe
output [ADDRESS_WIDTH-1:0] addr_out, // output address
output burst, // burst in progress
output reg err_out); // data last does not match predicted or FIFO over/under run
wire [ADDRESS_WIDTH-1:0] raddr_fifo; // raddr after fifo
wire [ 3:0] rlen_fifo; // rlen after fifo
wire fifo_valid; // fifo out valid
reg burst_r=0;
reg [ 3:0] left_plus_1;
wire start_burst=fifo_valid && data_stb && !burst_r;
wire generated_last= burst?(left_plus_1==1): ( fifo_valid && (rlen_fifo==0)) ;
wire fifo_in_rdy;
wire error_w= (data_stb && (last != generated_last)) || (rcmd && !fifo_in_rdy) || (start_burst && !fifo_valid);
reg [ADDRESS_WIDTH-1:0] adr_out_r;
assign burst=burst_r || start_burst;
assign addr_out=start_burst?raddr_fifo:adr_out_r;
always @ (posedge reset or posedge clk) begin
if (reset) burst_r <= 0;
else if (start_burst) burst_r <= rlen_fifo!=0;
// else if (last && data_stb) burst_r <= 0;
else if (generated_last && data_stb) burst_r <= 0;
if (reset) left_plus_1 <= 0;
else if (start_burst) left_plus_1 <= rlen_fifo;
else if (data_stb) left_plus_1 <= left_plus_1-1;
if (reset) err_out <= 0;
else err_out <= error_w;
// if (reset) was_last <= 0;
// else if (data_stb) was_last <= last;
end
always @ (posedge clk) begin
if (start_burst) adr_out_r <= raddr_fifo+1; // simulating only address incremental mode
else if (data_stb) adr_out_r <= adr_out_r + 1;
end
simul_fifo
#(
.WIDTH(ADDRESS_WIDTH+4),
.DEPTH(64)
)simmul_fifo_i(
.clk(clk),
.reset(reset),
// .data_in({rlen[3:0],raddr[11:2]}), // did not detect raddr[11:2] for input [ 9:0] raddr
.data_in({rlen[3:0],raddr}),
.load(rcmd),
.input_ready(fifo_in_rdy),
.data_out({rlen_fifo, raddr_fifo}),
.valid(fifo_valid),
.ready(start_burst));
endmodule
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module dcache
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter AXI_ID = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input axi_awready_i
,input axi_wready_i
,input axi_bvalid_i
,input [ 1:0] axi_bresp_i
,input [ 3:0] axi_bid_i
,input axi_arready_i
,input axi_rvalid_i
,input [ 31:0] axi_rdata_i
,input [ 1:0] axi_rresp_i
,input [ 3:0] axi_rid_i
,input axi_rlast_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output axi_awvalid_o
,output [ 31:0] axi_awaddr_o
,output [ 3:0] axi_awid_o
,output [ 7:0] axi_awlen_o
,output [ 1:0] axi_awburst_o
,output axi_wvalid_o
,output [ 31:0] axi_wdata_o
,output [ 3:0] axi_wstrb_o
,output axi_wlast_o
,output axi_bready_o
,output axi_arvalid_o
,output [ 31:0] axi_araddr_o
,output [ 3:0] axi_arid_o
,output [ 7:0] axi_arlen_o
,output [ 1:0] axi_arburst_o
,output axi_rready_o
);
wire mem_uncached_invalidate_w;
wire pmem_cache_accept_w;
wire mem_uncached_accept_w;
wire [ 7:0] pmem_cache_len_w;
wire [ 3:0] mem_cached_wr_w;
wire [ 31:0] pmem_cache_read_data_w;
wire mem_cached_invalidate_w;
wire pmem_uncached_ack_w;
wire [ 7:0] pmem_len_w;
wire pmem_uncached_accept_w;
wire mem_cached_accept_w;
wire pmem_cache_ack_w;
wire [ 31:0] pmem_cache_addr_w;
wire pmem_cache_rd_w;
wire pmem_error_w;
wire [ 31:0] pmem_addr_w;
wire [ 10:0] mem_cached_req_tag_w;
wire mem_uncached_ack_w;
wire pmem_ack_w;
wire [ 31:0] mem_uncached_data_wr_w;
wire [ 31:0] pmem_uncached_addr_w;
wire [ 31:0] mem_cached_data_rd_w;
wire [ 31:0] pmem_uncached_read_data_w;
wire mem_uncached_flush_w;
wire pmem_uncached_error_w;
wire [ 31:0] mem_uncached_data_rd_w;
wire [ 31:0] pmem_write_data_w;
wire [ 3:0] pmem_uncached_wr_w;
wire mem_cached_rd_w;
wire [ 10:0] mem_cached_resp_tag_w;
wire [ 7:0] pmem_uncached_len_w;
wire [ 31:0] mem_cached_data_wr_w;
wire [ 3:0] pmem_wr_w;
wire pmem_select_w;
wire mem_cached_flush_w;
wire mem_uncached_cacheable_w;
wire [ 31:0] mem_cached_addr_w;
wire mem_uncached_writeback_w;
wire [ 3:0] pmem_cache_wr_w;
wire pmem_cache_error_w;
wire [ 10:0] mem_uncached_req_tag_w;
wire [ 31:0] pmem_uncached_write_data_w;
wire [ 10:0] mem_uncached_resp_tag_w;
wire pmem_rd_w;
wire mem_cached_cacheable_w;
wire [ 3:0] mem_uncached_wr_w;
wire mem_uncached_error_w;
wire mem_uncached_rd_w;
wire pmem_accept_w;
wire [ 31:0] pmem_cache_write_data_w;
wire mem_cached_error_w;
wire [ 31:0] mem_uncached_addr_w;
wire pmem_uncached_rd_w;
wire [ 31:0] pmem_read_data_w;
wire mem_cached_ack_w;
wire mem_cached_writeback_w;
dcache_if_pmem
u_uncached
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(mem_uncached_addr_w)
,.mem_data_wr_i(mem_uncached_data_wr_w)
,.mem_rd_i(mem_uncached_rd_w)
,.mem_wr_i(mem_uncached_wr_w)
,.mem_cacheable_i(mem_uncached_cacheable_w)
,.mem_req_tag_i(mem_uncached_req_tag_w)
,.mem_invalidate_i(mem_uncached_invalidate_w)
,.mem_writeback_i(mem_uncached_writeback_w)
,.mem_flush_i(mem_uncached_flush_w)
,.outport_accept_i(pmem_uncached_accept_w)
,.outport_ack_i(pmem_uncached_ack_w)
,.outport_error_i(pmem_uncached_error_w)
,.outport_read_data_i(pmem_uncached_read_data_w)
// Outputs
,.mem_data_rd_o(mem_uncached_data_rd_w)
,.mem_accept_o(mem_uncached_accept_w)
,.mem_ack_o(mem_uncached_ack_w)
,.mem_error_o(mem_uncached_error_w)
,.mem_resp_tag_o(mem_uncached_resp_tag_w)
,.outport_wr_o(pmem_uncached_wr_w)
,.outport_rd_o(pmem_uncached_rd_w)
,.outport_len_o(pmem_uncached_len_w)
,.outport_addr_o(pmem_uncached_addr_w)
,.outport_write_data_o(pmem_uncached_write_data_w)
);
dcache_pmem_mux
u_pmem_mux
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.outport_accept_i(pmem_accept_w)
,.outport_ack_i(pmem_ack_w)
,.outport_error_i(pmem_error_w)
,.outport_read_data_i(pmem_read_data_w)
,.select_i(pmem_select_w)
,.inport0_wr_i(pmem_uncached_wr_w)
,.inport0_rd_i(pmem_uncached_rd_w)
,.inport0_len_i(pmem_uncached_len_w)
,.inport0_addr_i(pmem_uncached_addr_w)
,.inport0_write_data_i(pmem_uncached_write_data_w)
,.inport1_wr_i(pmem_cache_wr_w)
,.inport1_rd_i(pmem_cache_rd_w)
,.inport1_len_i(pmem_cache_len_w)
,.inport1_addr_i(pmem_cache_addr_w)
,.inport1_write_data_i(pmem_cache_write_data_w)
// Outputs
,.outport_wr_o(pmem_wr_w)
,.outport_rd_o(pmem_rd_w)
,.outport_len_o(pmem_len_w)
,.outport_addr_o(pmem_addr_w)
,.outport_write_data_o(pmem_write_data_w)
,.inport0_accept_o(pmem_uncached_accept_w)
,.inport0_ack_o(pmem_uncached_ack_w)
,.inport0_error_o(pmem_uncached_error_w)
,.inport0_read_data_o(pmem_uncached_read_data_w)
,.inport1_accept_o(pmem_cache_accept_w)
,.inport1_ack_o(pmem_cache_ack_w)
,.inport1_error_o(pmem_cache_error_w)
,.inport1_read_data_o(pmem_cache_read_data_w)
);
dcache_mux
u_mux
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(mem_addr_i)
,.mem_data_wr_i(mem_data_wr_i)
,.mem_rd_i(mem_rd_i)
,.mem_wr_i(mem_wr_i)
,.mem_cacheable_i(mem_cacheable_i)
,.mem_req_tag_i(mem_req_tag_i)
,.mem_invalidate_i(mem_invalidate_i)
,.mem_writeback_i(mem_writeback_i)
,.mem_flush_i(mem_flush_i)
,.mem_cached_data_rd_i(mem_cached_data_rd_w)
,.mem_cached_accept_i(mem_cached_accept_w)
,.mem_cached_ack_i(mem_cached_ack_w)
,.mem_cached_error_i(mem_cached_error_w)
,.mem_cached_resp_tag_i(mem_cached_resp_tag_w)
,.mem_uncached_data_rd_i(mem_uncached_data_rd_w)
,.mem_uncached_accept_i(mem_uncached_accept_w)
,.mem_uncached_ack_i(mem_uncached_ack_w)
,.mem_uncached_error_i(mem_uncached_error_w)
,.mem_uncached_resp_tag_i(mem_uncached_resp_tag_w)
// Outputs
,.mem_data_rd_o(mem_data_rd_o)
,.mem_accept_o(mem_accept_o)
,.mem_ack_o(mem_ack_o)
,.mem_error_o(mem_error_o)
,.mem_resp_tag_o(mem_resp_tag_o)
,.mem_cached_addr_o(mem_cached_addr_w)
,.mem_cached_data_wr_o(mem_cached_data_wr_w)
,.mem_cached_rd_o(mem_cached_rd_w)
,.mem_cached_wr_o(mem_cached_wr_w)
,.mem_cached_cacheable_o(mem_cached_cacheable_w)
,.mem_cached_req_tag_o(mem_cached_req_tag_w)
,.mem_cached_invalidate_o(mem_cached_invalidate_w)
,.mem_cached_writeback_o(mem_cached_writeback_w)
,.mem_cached_flush_o(mem_cached_flush_w)
,.mem_uncached_addr_o(mem_uncached_addr_w)
,.mem_uncached_data_wr_o(mem_uncached_data_wr_w)
,.mem_uncached_rd_o(mem_uncached_rd_w)
,.mem_uncached_wr_o(mem_uncached_wr_w)
,.mem_uncached_cacheable_o(mem_uncached_cacheable_w)
,.mem_uncached_req_tag_o(mem_uncached_req_tag_w)
,.mem_uncached_invalidate_o(mem_uncached_invalidate_w)
,.mem_uncached_writeback_o(mem_uncached_writeback_w)
,.mem_uncached_flush_o(mem_uncached_flush_w)
,.cache_active_o(pmem_select_w)
);
dcache_core
u_core
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(mem_cached_addr_w)
,.mem_data_wr_i(mem_cached_data_wr_w)
,.mem_rd_i(mem_cached_rd_w)
,.mem_wr_i(mem_cached_wr_w)
,.mem_cacheable_i(mem_cached_cacheable_w)
,.mem_req_tag_i(mem_cached_req_tag_w)
,.mem_invalidate_i(mem_cached_invalidate_w)
,.mem_writeback_i(mem_cached_writeback_w)
,.mem_flush_i(mem_cached_flush_w)
,.outport_accept_i(pmem_cache_accept_w)
,.outport_ack_i(pmem_cache_ack_w)
,.outport_error_i(pmem_cache_error_w)
,.outport_read_data_i(pmem_cache_read_data_w)
// Outputs
,.mem_data_rd_o(mem_cached_data_rd_w)
,.mem_accept_o(mem_cached_accept_w)
,.mem_ack_o(mem_cached_ack_w)
,.mem_error_o(mem_cached_error_w)
,.mem_resp_tag_o(mem_cached_resp_tag_w)
,.outport_wr_o(pmem_cache_wr_w)
,.outport_rd_o(pmem_cache_rd_w)
,.outport_len_o(pmem_cache_len_w)
,.outport_addr_o(pmem_cache_addr_w)
,.outport_write_data_o(pmem_cache_write_data_w)
);
dcache_axi
#(
.AXI_ID(AXI_ID)
)
u_axi
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.outport_awready_i(axi_awready_i)
,.outport_wready_i(axi_wready_i)
,.outport_bvalid_i(axi_bvalid_i)
,.outport_bresp_i(axi_bresp_i)
,.outport_bid_i(axi_bid_i)
,.outport_arready_i(axi_arready_i)
,.outport_rvalid_i(axi_rvalid_i)
,.outport_rdata_i(axi_rdata_i)
,.outport_rresp_i(axi_rresp_i)
,.outport_rid_i(axi_rid_i)
,.outport_rlast_i(axi_rlast_i)
,.inport_wr_i(pmem_wr_w)
,.inport_rd_i(pmem_rd_w)
,.inport_len_i(pmem_len_w)
,.inport_addr_i(pmem_addr_w)
,.inport_write_data_i(pmem_write_data_w)
// Outputs
,.outport_awvalid_o(axi_awvalid_o)
,.outport_awaddr_o(axi_awaddr_o)
,.outport_awid_o(axi_awid_o)
,.outport_awlen_o(axi_awlen_o)
,.outport_awburst_o(axi_awburst_o)
,.outport_wvalid_o(axi_wvalid_o)
,.outport_wdata_o(axi_wdata_o)
,.outport_wstrb_o(axi_wstrb_o)
,.outport_wlast_o(axi_wlast_o)
,.outport_bready_o(axi_bready_o)
,.outport_arvalid_o(axi_arvalid_o)
,.outport_araddr_o(axi_araddr_o)
,.outport_arid_o(axi_arid_o)
,.outport_arlen_o(axi_arlen_o)
,.outport_arburst_o(axi_arburst_o)
,.outport_rready_o(axi_rready_o)
,.inport_accept_o(pmem_accept_w)
,.inport_ack_o(pmem_ack_w)
,.inport_error_o(pmem_error_w)
,.inport_read_data_o(pmem_read_data_w)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NOR3B_FUNCTIONAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_FUNCTIONAL_PP_V |
/*
* AGrises.v
*
* Created on: 09/10/2012
* Author: Lord_Rafa
*/
`timescale 1 ps / 1 ps
module AGrises (
input clk,
input rst,
output [DATA_WIDTH-1:0] data_fifo_out,
output data_valid_fifo_out,
input wire [FIFO_DEPTH_LOG2:0] usedw_fifo_out,
input wire [DATA_WIDTH-1:0] data_fifo_in,
output read_fifo_in,
input wire [FIFO_DEPTH_LOG2:0] usedw_fifo_in,
input start,
output endf
);
parameter DATA_WIDTH=32;
parameter FIFO_DEPTH = 256;
parameter FIFO_DEPTH_LOG2 = 8;
reg [1:0] stages;
wire stages_init;
reg [1:0] run;
reg [14:0] grey_aux;
reg [7:0] grey;
reg [18:0] pixel_counter;
always @ (posedge clk or posedge rst) begin
if (rst == 1) begin
run <= 0;
end else begin
if (start == 1) begin
run <= 1;
end else begin
if (pixel_counter == 0) begin
run <= 2;
end
if (endf == 1) begin
run <= 0;
end
end
end
end
always @ (posedge clk) begin
if (start == 1) begin
pixel_counter <= 384000;
end else begin
if (data_valid_fifo_out) begin
pixel_counter <= pixel_counter - 1;
end
end
end
always @ (posedge clk) begin
if (start == 1) begin
stages <= 0;
end else begin
if (stages_init == 1) begin
stages <= 1;
grey_aux = data_fifo_in[23:16]*8'd30 + data_fifo_in[15:8]*8'd59 + data_fifo_in[7:0]*8'd11;
grey = 8'd2 * grey_aux[14:8];
grey = grey + (grey_aux[14:8] / 8'd2);
end else begin
if (stages == 1) begin
stages <= 2;
grey = grey + (grey_aux[14:8] / 8'd19);
grey = grey + (grey_aux[7:0] / 8'd64);
end else begin
if (stages == 2) begin
stages <= 0;
end
end
end
end
end
assign stages_init = ((usedw_fifo_in > 32)|(pixel_counter < 33)) & (usedw_fifo_out < FIFO_DEPTH) & (run == 1) & (stages == 0);
assign read_fifo_in = (run == 1) & (stages == 1);
assign data_fifo_out = {8'd0,{3{grey}}};
assign data_valid_fifo_out = (run == 1) & (stages == 2);
assign endf = (run == 2);
endmodule
|
/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY serdes watchdog
*/
module eth_phy_10g_rx_watchdog #
(
parameter HDR_WIDTH = 2,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_reset_req,
/*
* Monitor inputs
*/
input wire rx_bad_block,
input wire rx_sequence_error,
input wire rx_block_lock,
input wire rx_high_ber
);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
parameter COUNT_WIDTH = $clog2(COUNT_125US);
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [COUNT_WIDTH-1:0] time_count_reg = 0, time_count_next;
reg [3:0] error_count_reg = 0, error_count_next;
reg saw_ctrl_sh_reg = 1'b0, saw_ctrl_sh_next;
reg [9:0] block_error_count_reg = 0, block_error_count_next;
reg serdes_rx_reset_req_reg = 1'b0, serdes_rx_reset_req_next;
assign serdes_rx_reset_req = serdes_rx_reset_req_reg;
always @* begin
error_count_next = error_count_reg;
saw_ctrl_sh_next = saw_ctrl_sh_reg;
block_error_count_next = block_error_count_reg;
serdes_rx_reset_req_next = 1'b0;
if (rx_block_lock) begin
if (serdes_rx_hdr == SYNC_CTRL) begin
saw_ctrl_sh_next = 1'b1;
end
if ((rx_bad_block || rx_sequence_error) && !(&block_error_count_reg)) begin
block_error_count_next = block_error_count_reg + 1;
end
end
if (time_count_reg != 0) begin
time_count_next = time_count_reg-1;
end else begin
time_count_next = COUNT_125US;
if (!saw_ctrl_sh_reg || &block_error_count_reg) begin
error_count_next = error_count_reg + 1;
end else begin
error_count_next = 0;
end
if (&error_count_reg) begin
error_count_next = 0;
serdes_rx_reset_req_next = 1'b1;
end
saw_ctrl_sh_next = 1'b0;
block_error_count_next = 0;
end
end
always @(posedge clk) begin
time_count_reg <= time_count_next;
error_count_reg <= error_count_next;
saw_ctrl_sh_reg <= saw_ctrl_sh_next;
block_error_count_reg <= block_error_count_next;
if (rst) begin
time_count_reg <= COUNT_125US;
error_count_reg <= 0;
saw_ctrl_sh_reg <= 1'b0;
block_error_count_reg <= 0;
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
serdes_rx_reset_req_reg <= 1'b0;
end else begin
serdes_rx_reset_req_reg <= serdes_rx_reset_req_next;
end
end
endmodule
`resetall
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: lsu_dc_parity_gen.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
//
// Module Name: lsu_dc_parity_gen.v
// Description: Parity Generator based on odd parity
module lsu_dc_parity_gen (parity_out, data_in);
// Changed the default to match that of dcache width
parameter WIDTH = 8 ;
parameter NUM = 16 ;
input [WIDTH * NUM - 1 : 0] data_in ; // data in
output [NUM - 1 : 0] parity_out ; // parity output
reg [NUM - 1 : 0] parity ; // parity output
integer i ;
integer j ;
always @(data_in)
for (i = 0; i <= NUM - 1 ; i = i + 1) begin
parity[i] = 1'b0 ;
for (j = WIDTH * i; j <= WIDTH * (i + 1) - 1 ; j = j + 1) begin
parity[i] = parity[i] ^ data_in[j] ;
end
end
assign parity_out[NUM - 1 : 0] = parity[NUM - 1 : 0];
endmodule
|
`timescale 1ns / 1ps
/* All files are owned by Kris Kalavantavanich.
* Feel free to use/modify/distribute in the condition that this copyright header is kept unmodified.
* Github: https://github.com/kkalavantavanich/SD2017 */
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 05/19/2017 10:23:10 PM
// Design Name: SPI_SEND
// Module Name: spiSend
// Project Name: SD_2017
// Target Devices: Xilinx Basys3
// Description: Submodule of main.v. Send 48-bit cmd command `CMD`. Output is in `bitout`.
// Sending process will start on `start` HIGH (synchronous with negedge)
// Process finish is notified by `finish` HIGH (synchronous with negedge)
// Dependencies: main.v
// Revision: 1.00
// Revision 1.00 - Finished Read Operation
// Revision 0.01 - File Created
// Additional Comments: SET ON NEGEDGE!!!!
//////////////////////////////////////////////////////////////////////////////////
module spiSend(
spiClock,
start,
cmd,
bitout,
finish
);
parameter byteSize = 6;
// 'public' variables
input spiClock;
input start;
input [(byteSize * 8) - 1:0] cmd;
output bitout;
output reg finish;
// 'private' variables
wire _start;
assign _start = start;
reg _running = 0, _waiting = 0;
reg [(byteSize * 8) - 1:0] _cmdBuffer;
reg [byteSize - 1:0] _i;
assign bitout = _running ? _cmdBuffer[47] : 1'b1; /// active low
reg _error = 0;
// main //
always @ (negedge spiClock) begin
if (_start && ~_running && ~_waiting) begin
// initial
finish <= 0;
_cmdBuffer <= cmd; // cmd always start with 0
_running <= 1;
_i <= 47; // this loop sends a `0`
end else if (_start && _running && ~_waiting) begin
// looping
_i = _i - 1;
_cmdBuffer = _cmdBuffer << 1;
if (_i == 0) begin
// end
_running <= 0;
_waiting <= 1;
end
end else if (_start && _waiting) begin
finish <= 1;
end else if (~_start) begin
finish <= 0;
_waiting <= 0;
end else begin
_error = 1;
end
end
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: small_fifo_test.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module small_fifo_test (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [31:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [31:0] q;
output [4:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: usedw 0 0 5 0 OUTPUT NODEFVAL "usedw[4..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: usedw 0 0 5 0 @usedw 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22O_4_V
`define SKY130_FD_SC_MS__A22O_4_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a22o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a22o_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22O_4_V
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module RegTwoA(CLK, RST, Q_OUT, D_INA, ENA, D_INB, ENB);
parameter width = 1;
parameter init = { width {1'b0 }} ;
input CLK;
input RST;
input ENA ;
input ENB;
input [width - 1 : 0] D_INA;
input [width - 1 : 0] D_INB;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] Q_OUT;
always@(posedge CLK or `BSV_RESET_EDGE RST)
begin
if (RST == `BSV_RESET_VALUE)
Q_OUT <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if (ENA)
Q_OUT <= `BSV_ASSIGNMENT_DELAY D_INA;
else if (ENB)
Q_OUT <= `BSV_ASSIGNMENT_DELAY D_INB;
end // else: !if(RST == `BSV_RESET_VALUE)
end
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
Q_OUT = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_TB_V
`define SKY130_FD_SC_MS__FILL_TB_V
/**
* fill: Fill cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fill.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ms__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_TB_V
|
/*
-- ============================================================================
-- FILE NAME : mem_stage.v
-- DESCRIPTION : MEMXe[W
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "isa.h"
`include "cpu.h"
/********** W
[ **********/
module mem_stage (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** pCvC§äM **********/
input wire stall, // Xg[
input wire flush, // tbV
output wire busy, // rW[M
/********** tH[fBO **********/
output wire [`WordDataBus] fwd_data, // tH[fBOf[^
/********** SPMC^tF[X **********/
input wire [`WordDataBus] spm_rd_data, // ÇÝoµf[^
output wire [`WordAddrBus] spm_addr, // AhX
output wire spm_as_, // AhXXg[u
output wire spm_rw, // ÇÝ^«
output wire [`WordDataBus] spm_wr_data, // «Ýf[^
/********** oXC^tF[X **********/
input wire [`WordDataBus] bus_rd_data, // ÇÝoµf[^
input wire bus_rdy_, // fB
input wire bus_grnt_, // oXOg
output wire bus_req_, // oXNGXg
output wire [`WordAddrBus] bus_addr, // AhX
output wire bus_as_, // AhXXg[u
output wire bus_rw, // ÇÝ^«
output wire [`WordDataBus] bus_wr_data, // «Ýf[^
/********** EX/MEMpCvCWX^ **********/
input wire [`WordAddrBus] ex_pc, // vOJE^
input wire ex_en, // pCvCf[^ÌLø
input wire ex_br_flag, // ªòtO
input wire [`MemOpBus] ex_mem_op, // Iy[V
input wire [`WordDataBus] ex_mem_wr_data, // «Ýf[^
input wire [`CtrlOpBus] ex_ctrl_op, // §äWX^Iy[V
input wire [`RegAddrBus] ex_dst_addr, // ÄpWX^«ÝAhX
input wire ex_gpr_we_, // ÄpWX^«ÝLø
input wire [`IsaExpBus] ex_exp_code, // áOR[h
input wire [`WordDataBus] ex_out, // Ê
/********** MEM/WBpCvCWX^ **********/
output wire [`WordAddrBus] mem_pc, // vOJE^
output wire mem_en, // pCvCf[^ÌLø
output wire mem_br_flag, // ªòtO
output wire [`CtrlOpBus] mem_ctrl_op, // §äWX^Iy[V
output wire [`RegAddrBus] mem_dst_addr, // ÄpWX^«ÝAhX
output wire mem_gpr_we_, // ÄpWX^«ÝLø
output wire [`IsaExpBus] mem_exp_code, // áOR[h
output wire [`WordDataBus] mem_out // Ê
);
/********** àM **********/
wire [`WordDataBus] rd_data; // ÇÝoµf[^
wire [`WordAddrBus] addr; // AhX
wire as_; // AhXLø
wire rw; // ÇÝ^«
wire [`WordDataBus] wr_data; // «Ýf[^
wire [`WordDataBus] out; // ANZXÊ
wire miss_align; // ~XAC
/********** ÊÌtH[fBO **********/
assign fwd_data = out;
/********** ANZX§äjbg **********/
mem_ctrl mem_ctrl (
/********** EX/MEMpCvCWX^ **********/
.ex_en (ex_en), // pCvCf[^ÌLø
.ex_mem_op (ex_mem_op), // Iy[V
.ex_mem_wr_data (ex_mem_wr_data), // «Ýf[^
.ex_out (ex_out), // Ê
/********** ANZXC^tF[X **********/
.rd_data (rd_data), // ÇÝoµf[^
.addr (addr), // AhX
.as_ (as_), // AhXLø
.rw (rw), // ÇÝ^«
.wr_data (wr_data), // «Ýf[^
/********** ANZXÊ **********/
.out (out), // ANZXÊ
.miss_align (miss_align) // ~XAC
);
/********** oXC^tF[X **********/
bus_if bus_if (
/********** NbN & Zbg **********/
.clk (clk), // NbN
.reset (reset), // ñ¯úZbg
/********** pCvC§äM **********/
.stall (stall), // Xg[
.flush (flush), // tbV
M
.busy (busy), // rW[M
/********** CPUC^tF[X **********/
.addr (addr), // AhX
.as_ (as_), // AhXLø
.rw (rw), // ÇÝ^«
.wr_data (wr_data), // «Ýf[^
.rd_data (rd_data), // ÇÝoµf[^
/********** XNb`pbhC^tF[X **********/
.spm_rd_data (spm_rd_data), // ÇÝoµf[^
.spm_addr (spm_addr), // AhX
.spm_as_ (spm_as_), // AhXXg[u
.spm_rw (spm_rw), // ÇÝ^«
.spm_wr_data (spm_wr_data), // «Ýf[^
/********** oXC^tF[X **********/
.bus_rd_data (bus_rd_data), // ÇÝoµf[^
.bus_rdy_ (bus_rdy_), // fB
.bus_grnt_ (bus_grnt_), // oXOg
.bus_req_ (bus_req_), // oXNGXg
.bus_addr (bus_addr), // AhX
.bus_as_ (bus_as_), // AhXXg[u
.bus_rw (bus_rw), // ÇÝ^«
.bus_wr_data (bus_wr_data) // «Ýf[^
);
/********** MEMXe[WpCvCWX^ **********/
mem_reg mem_reg (
/********** NbN & Zbg **********/
.clk (clk), // NbN
.reset (reset), // ñ¯úZbg
/********** ANZXÊ **********/
.out (out), // Ê
.miss_align (miss_align), // ~XAC
/********** pCvC§äM **********/
.stall (stall), // Xg[
.flush (flush), // tbV
/********** EX/MEMpCvCWX^ **********/
.ex_pc (ex_pc), // vOJE^
.ex_en (ex_en), // pCvCf[^ÌLø
.ex_br_flag (ex_br_flag), // ªòtO
.ex_ctrl_op (ex_ctrl_op), // §äWX^Iy[V
.ex_dst_addr (ex_dst_addr), // ÄpWX^«ÝAhX
.ex_gpr_we_ (ex_gpr_we_), // ÄpWX^«ÝLø
.ex_exp_code (ex_exp_code), // áOR[h
/********** MEM/WBpCvCWX^ **********/
.mem_pc (mem_pc), // vOJE^
.mem_en (mem_en), // pCvCf[^ÌLø
.mem_br_flag (mem_br_flag), // ªòtO
.mem_ctrl_op (mem_ctrl_op), // §äWX^Iy[V
.mem_dst_addr (mem_dst_addr), // ÄpWX^«ÝAhX
.mem_gpr_we_ (mem_gpr_we_), // ÄpWX^«ÝLø
.mem_exp_code (mem_exp_code), // áOR[h
.mem_out (mem_out) // Ê
);
endmodule
|
// =======================================================================
// Department of Electrical and Computer Engineering
// Portland State University
//
// Course name: ECE 510 - Pre-Silicon Validation
// Term & Year: Spring 2015
// Instructor : Tareque Ahmad
//
// Project: PDP8 Hardware Simulator top level testbench
//
//
// Filename: top.sv
// Description: TBD
// Created by: Tareque Ahmad
// Date: May 03, 2015
//
// Copyright: Tareque Ahmad
// =======================================================================
`include "pdp8_pkg.sv"
import pdp8_pkg::*;
module top ();
wire clk;
wire reset_n;
wire stall;
wire [`ADDR_WIDTH-1:0] PC_value;
wire ifu_rd_req;
wire [`ADDR_WIDTH-1:0] ifu_rd_addr;
wire [`DATA_WIDTH-1:0] ifu_rd_data;
wire exec_rd_req;
wire [`ADDR_WIDTH-1:0] exec_rd_addr;
wire [`DATA_WIDTH-1:0] exec_rd_data;
wire exec_wr_req;
wire [`ADDR_WIDTH-1:0] exec_wr_addr;
wire [`DATA_WIDTH-1:0] exec_wr_data;
wire [`ADDR_WIDTH-1:0] base_addr;
pdp_mem_opcode_s pdp_mem_opcode;
pdp_op7_opcode_s pdp_op7_opcode;
clkgen_driver #(
.CLOCK_PERIOD(10),
.RESET_DURATION(500)) clkgen_driver (
.clk (clk),
.reset_n (reset_n));
// memory_pdp memory_pdp (.*); //for determinsitic
instr_decode instr_decode(.*);
test_instr_decode test_instr_decode(.*);
endmodule |
`default_nettype none
module comparator_counter(
input wire iCLOCK,
input wire inRESET,
//Main Counter
input wire iMTIMER_WORKING,
input wire [63:0] iMTIMER_COUNT,
//Timmer Settings
input wire iCONF_WRITE,
input wire iCONF_ENA,
input wire iCONF_IRQENA,
input wire iCONF_64MODE,
input wire iCONF_PERIODIC, //Non Periodic mode = 0 | Periodic mode = 1
//Counter
input wire iCOUNT_WRITE,
input wire [1:0] inCOUNT_DQM,
input wire [63:0] iCOUNT_COUNTER,
//Interrupt
output wire oIRQ
);
reg enable;
reg irqena;
reg [63:0] ini_counter;
reg [63:0] counter;
reg bitmode;
reg periodic;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
enable <= 1'b0;
irqena <= 1'b0;
ini_counter <= 64'h0;
counter <= 64'h0;
bitmode <= 1'b0;
periodic <= 1'b0;
end
else begin
///Counter Setting
if(iCONF_WRITE)begin
enable <= iCONF_ENA;
irqena <= iCONF_IRQENA;
bitmode <= iCONF_64MODE;
periodic <= iCONF_PERIODIC;
//Counter Write
if(iCOUNT_WRITE)begin
ini_counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
ini_counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
end
end
else begin
//Counter Write
if(iCOUNT_WRITE)begin
ini_counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
ini_counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
counter[31:0] <= (!inCOUNT_DQM[0])? iCOUNT_COUNTER[31:0] : ini_counter[31:0];
counter[63:32] <= (!inCOUNT_DQM[1])? iCOUNT_COUNTER[63:32] : ini_counter[63:32];
end
else if(enable)begin
if(periodic)begin
if(bitmode)begin
//64bit Mode
if(counter == iMTIMER_COUNT)begin
counter <= counter + ini_counter;
end
end
else begin
//32bit Mode
if(counter[31:0] == iMTIMER_COUNT[31:0])begin
counter <= counter + ini_counter;
end
end
end
end
end
end
end
assign oIRQ = irqena && iMTIMER_WORKING && (bitmode)? (counter == iMTIMER_COUNT && ini_counter != 64'h0) : (counter[31:0] == iMTIMER_COUNT[31:0] && ini_counter[31:0] != 32'h0);
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32A_4_V
`define SKY130_FD_SC_MS__O32A_4_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32a_4 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32A_4_V
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Depth 2 FIFO
module FIFO2(CLK,
RST_N,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
parameter width = 1;
parameter guarded = 1;
input CLK ;
input RST_N ;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg full_reg;
reg empty_reg;
reg [width - 1 : 0] data0_reg;
reg [width - 1 : 0] data1_reg;
assign FULL_N = full_reg ;
assign EMPTY_N = empty_reg ;
assign D_OUT = data0_reg ;
// Optimize the loading logic since state encoding is not power of 2!
wire d0di = (ENQ && ! empty_reg ) || ( ENQ && DEQ && full_reg ) ;
wire d0d1 = DEQ && ! full_reg ;
wire d0h = ((! DEQ) && (! ENQ )) || (!DEQ && empty_reg ) || ( ! ENQ &&full_reg) ;
wire d1di = ENQ & empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
data0_reg = {((width + 1)/2) {2'b10}} ;
data1_reg = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0;
full_reg = 1'b1;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK /* or negedge RST_N */)
begin
if (!RST_N)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (RST_N == 0)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (CLR)
else if ( ENQ && ! DEQ ) // just enq
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg ;
end
else if ( DEQ && ! ENQ )
begin
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg;
end // if ( DEQ && ! ENQ )
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
always@(posedge CLK /* or negedge RST_N */ )
begin
// Following section initializes the data registers which
// may be desired only in some situations.
// Uncomment to initialize array
/*
if (!RST_N)
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
data1_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
*/
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY
{width{d0di}} & D_IN | {width{d0d1}} & data1_reg | {width{d0h}} & data0_reg ;
data1_reg <= `BSV_ASSIGNMENT_DELAY
d1di ? D_IN : data1_reg ;
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( RST_N )
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1;
$display( "Warning: FIFO2: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! full_reg && ENQ && (!DEQ || guarded) )
begin
enqerror = 1;
$display( "Warning: FIFO2: %m -- Enqueuing to a full fifo" ) ;
end
end
end // always@ (posedge CLK)
// synopsys translate_on
endmodule
|
//#############################################################################
//# Purpose: SPI top (configurable as master or slave) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module spi #( parameter AW = 32, // address width
parameter PW = 104, // packet size
parameter UREGS = 13 // number of user slave regs
)
(//clk, reset, irq
input nreset, // asynch active low reset
input clk, // core clock
input hw_en, // block enable pin
output spi_irq, // interrupt output
//packet from core
input access_in, // access from core
input [PW-1:0] packet_in, // packet from core
input wait_in, // pushback from io
//packet to core
output access_out, // access to core
output [PW-1:0] packet_out, // packet to core
output wait_out, // pushback from core
//master io interface
output m_sclk, // master clock
output m_mosi, // master output
output m_ss, // slave select
input m_miso, // master input
//slave io interface
input s_sclk, // slave clock
input s_mosi, // slave input
input s_ss, // slave select
output s_miso // slave output
);
//1. set manual_CS mode
//2. assert ss (0000)
//4. write to tx fifo
//6. deassert ss (1111)
//###############
//# LOCAL WIRES
//###############
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire m_access_out; // From spi_master of spi_master.v
wire [PW-1:0] m_packet_out; // From spi_master of spi_master.v
wire m_wait_out; // From spi_master of spi_master.v
wire s_access_out; // From spi_slave of spi_slave.v
wire [PW-1:0] s_packet_out; // From spi_slave of spi_slave.v
wire [511:0] s_spi_regs; // From spi_slave of spi_slave.v
wire s_wait_out; // From spi_slave of spi_slave.v
// End of automatics
//###########################################################
//# SPI SLACE
//###########################################################
/*spi_master AUTO_TEMPLATE (.clk (clk),
.nreset (nreset),
.hw_en (hw_en),
.\(.*\)_in (\1_in[]),
.\(.*\) (m_\1[]),
);
*/
spi_master #(.AW(AW),
.PW(PW))
spi_master (/*AUTOINST*/
// Outputs
.sclk (m_sclk), // Templated
.mosi (m_mosi), // Templated
.ss (m_ss), // Templated
.wait_out (m_wait_out), // Templated
.access_out (m_access_out), // Templated
.packet_out (m_packet_out[PW-1:0]), // Templated
// Inputs
.clk (clk), // Templated
.nreset (nreset), // Templated
.hw_en (hw_en), // Templated
.miso (m_miso), // Templated
.access_in (access_in), // Templated
.packet_in (packet_in[PW-1:0]), // Templated
.wait_in (wait_in)); // Templated
//###########################################################
//# SPI SLAVE
//###########################################################
/*spi_slave AUTO_TEMPLATE (.clk (clk),
.spi_irq (spi_irq),
.nreset (nreset),
.hw_en (hw_en),
.\(.*\)_in (\1_in[]),
.\(.*\) (s_\1[]),
);
*/
spi_slave #(.AW(AW),
.PW(PW),
.UREGS(UREGS))
spi_slave (/*AUTOINST*/
// Outputs
.spi_regs (s_spi_regs[511:0]), // Templated
.spi_irq (spi_irq), // Templated
.miso (s_miso), // Templated
.access_out (s_access_out), // Templated
.packet_out (s_packet_out[PW-1:0]), // Templated
.wait_out (s_wait_out), // Templated
// Inputs
.clk (clk), // Templated
.nreset (nreset), // Templated
.hw_en (hw_en), // Templated
.sclk (s_sclk), // Templated
.mosi (s_mosi), // Templated
.ss (s_ss), // Templated
.wait_in (wait_in), // Templated
.access_in (access_in), // Templated
.packet_in (packet_in[PW-1:0])); // Templated
//###########################################################
//# EMESH MUX
//###########################################################
assign wait_out = s_wait_out | m_wait_out;
emesh_mux #(.N(2),
.AW(AW),
.PW(PW))
emesh_mux (// Outputs
.wait_out (),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
// Inputs
.access_in ({s_access_out,m_access_out}),
.packet_in ({s_packet_out[PW-1:0],m_packet_out[PW-1:0]}),
.wait_in (wait_in)
);
endmodule // spi
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../emesh/hdl")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0N_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__INPUTISO0N_FUNCTIONAL_PP_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, SLEEP_B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0N_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_PP_SYMBOL_V
`define SKY130_FD_SC_LS__CLKINV_PP_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkinv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_PP_SYMBOL_V
|
// MBT 7/7/2016
//
// 1 read-port, 1 write-port ram
//
// reads are synchronous
//
// although we could merge this with normal bsg_mem_1r1w
// and select with a parameter, we do not do this because
// it's typically a very big change to the instantiating code
// to move to/from sync/async, and we want to reflect this.
//
// NOTE: Users of BaseJump STL should not instantiate this module directly
// they should use bsg_mem_1r1w_sync.
`include "bsg_defines.v"
module bsg_mem_1r1w_sync_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, w_v_i, w_addr_i, r_v_i, r_addr_i};
assign r_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
// this treats the ram as an array of registers for which the
// read addr is latched on the clock, the write
// is done on the clock edge, and actually multiplexing
// of the registers for reading is done after the clock edge.
// logically, this means that reads happen in time after
// the writes, and "simultaneous" reads and writes to the
// register file are allowed -- IF read_write_same_addr is set.
// note that this behavior is generally incompatible with
// hardened 1r1w rams, so it's better not to take advantage
// of it if not necessary
// we explicitly 'X out the read address if valid is not set
// to avoid accidental use of data when the valid signal was not
// asserted. without this, the output of the register file would
// "auto-update" based on new writes to the ram, a spooky behavior
// that would never correspond to that of a hardened ram.
logic [addr_width_lp-1:0] r_addr_r;
always_ff @(posedge clk_i)
if (r_v_i)
r_addr_r <= r_addr_i;
else
r_addr_r <= 'X;
assign r_data_o = mem[r_addr_r];
always_ff @(posedge clk_i)
if (w_v_i)
mem[w_addr_i] <= w_data_i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync_synth)
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 00:37:18 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire n5287, NaN_reg, ready_add_subt, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_d_ff3_sign_out, FPSENCOS_d_ff1_operation_out,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_exp_operation_A_S, FPMULT_FSM_add_overflow_flag,
FPMULT_zero_flag, FPADDSUB_OP_FLAG_SFG, FPADDSUB_SIGN_FLAG_SFG,
FPADDSUB_SIGN_FLAG_NRM, FPADDSUB_SIGN_FLAG_SHT1SHT2,
FPADDSUB_ADD_OVRFLW_NRM2, FPADDSUB_OP_FLAG_SHT2,
FPADDSUB_SIGN_FLAG_SHT2, FPADDSUB_bit_shift_SHT2,
FPADDSUB_left_right_SHT2, FPADDSUB_ADD_OVRFLW_NRM,
FPADDSUB_OP_FLAG_SHT1, FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP,
FPADDSUB_SIGN_FLAG_EXP, FPADDSUB_intAS, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_,
FPMULT_Sgf_operation_EVEN1_left_N23,
FPMULT_Sgf_operation_EVEN1_left_N22,
FPMULT_Sgf_operation_EVEN1_left_N21,
FPMULT_Sgf_operation_EVEN1_left_N20,
FPMULT_Sgf_operation_EVEN1_left_N19,
FPMULT_Sgf_operation_EVEN1_left_N18,
FPMULT_Sgf_operation_EVEN1_left_N17,
FPMULT_Sgf_operation_EVEN1_left_N16,
FPMULT_Sgf_operation_EVEN1_left_N15,
FPMULT_Sgf_operation_EVEN1_left_N14,
FPMULT_Sgf_operation_EVEN1_left_N13,
FPMULT_Sgf_operation_EVEN1_left_N12,
FPMULT_Sgf_operation_EVEN1_left_N11,
FPMULT_Sgf_operation_EVEN1_left_N10,
FPMULT_Sgf_operation_EVEN1_left_N9,
FPMULT_Sgf_operation_EVEN1_left_N8,
FPMULT_Sgf_operation_EVEN1_left_N7,
FPMULT_Sgf_operation_EVEN1_left_N6,
FPMULT_Sgf_operation_EVEN1_left_N5,
FPMULT_Sgf_operation_EVEN1_left_N4,
FPMULT_Sgf_operation_EVEN1_left_N3,
FPMULT_Sgf_operation_EVEN1_left_N2,
FPMULT_Sgf_operation_EVEN1_left_N1,
FPMULT_Sgf_operation_EVEN1_left_N0,
FPMULT_Sgf_operation_EVEN1_middle_N25,
FPMULT_Sgf_operation_EVEN1_middle_N24,
FPMULT_Sgf_operation_EVEN1_middle_N23,
FPMULT_Sgf_operation_EVEN1_middle_N22,
FPMULT_Sgf_operation_EVEN1_middle_N21,
FPMULT_Sgf_operation_EVEN1_middle_N20,
FPMULT_Sgf_operation_EVEN1_middle_N19,
FPMULT_Sgf_operation_EVEN1_middle_N18,
FPMULT_Sgf_operation_EVEN1_middle_N17,
FPMULT_Sgf_operation_EVEN1_middle_N16,
FPMULT_Sgf_operation_EVEN1_middle_N15,
FPMULT_Sgf_operation_EVEN1_middle_N14,
FPMULT_Sgf_operation_EVEN1_middle_N13,
FPMULT_Sgf_operation_EVEN1_middle_N12,
FPMULT_Sgf_operation_EVEN1_middle_N11,
FPMULT_Sgf_operation_EVEN1_middle_N10,
FPMULT_Sgf_operation_EVEN1_middle_N9,
FPMULT_Sgf_operation_EVEN1_middle_N8,
FPMULT_Sgf_operation_EVEN1_middle_N7,
FPMULT_Sgf_operation_EVEN1_middle_N6,
FPMULT_Sgf_operation_EVEN1_middle_N5,
FPMULT_Sgf_operation_EVEN1_middle_N4,
FPMULT_Sgf_operation_EVEN1_middle_N3,
FPMULT_Sgf_operation_EVEN1_middle_N2,
FPMULT_Sgf_operation_EVEN1_middle_N1,
FPMULT_Sgf_operation_EVEN1_middle_N0,
FPMULT_Sgf_operation_EVEN1_right_N23,
FPMULT_Sgf_operation_EVEN1_right_N22,
FPMULT_Sgf_operation_EVEN1_right_N21,
FPMULT_Sgf_operation_EVEN1_right_N20,
FPMULT_Sgf_operation_EVEN1_right_N19,
FPMULT_Sgf_operation_EVEN1_right_N18,
FPMULT_Sgf_operation_EVEN1_right_N17,
FPMULT_Sgf_operation_EVEN1_right_N16,
FPMULT_Sgf_operation_EVEN1_right_N15,
FPMULT_Sgf_operation_EVEN1_right_N14,
FPMULT_Sgf_operation_EVEN1_right_N13,
FPMULT_Sgf_operation_EVEN1_right_N12,
FPMULT_Sgf_operation_EVEN1_right_N11,
FPMULT_Sgf_operation_EVEN1_right_N10,
FPMULT_Sgf_operation_EVEN1_right_N9,
FPMULT_Sgf_operation_EVEN1_right_N8,
FPMULT_Sgf_operation_EVEN1_right_N7,
FPMULT_Sgf_operation_EVEN1_right_N6,
FPMULT_Sgf_operation_EVEN1_right_N5,
FPMULT_Sgf_operation_EVEN1_right_N4,
FPMULT_Sgf_operation_EVEN1_right_N3,
FPMULT_Sgf_operation_EVEN1_right_N2,
FPMULT_Sgf_operation_EVEN1_right_N1,
FPMULT_Sgf_operation_EVEN1_right_N0, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1237, n1238, n1239, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1289, n1290, n1291, n1292, n1293, n1294, n1296, n1297, n1298, n1299,
n1300, n1301, n1303, n1304, n1305, n1306, n1307, n1308, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412,
n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1482, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962,
n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2192,
DP_OP_454J1_123_2743_n252, DP_OP_454J1_123_2743_n251,
DP_OP_454J1_123_2743_n250, DP_OP_454J1_123_2743_n249,
DP_OP_454J1_123_2743_n248, DP_OP_454J1_123_2743_n247,
DP_OP_454J1_123_2743_n246, DP_OP_454J1_123_2743_n245,
DP_OP_454J1_123_2743_n240, DP_OP_454J1_123_2743_n236,
DP_OP_454J1_123_2743_n235, DP_OP_454J1_123_2743_n234,
DP_OP_454J1_123_2743_n233, DP_OP_454J1_123_2743_n232,
DP_OP_454J1_123_2743_n231, DP_OP_454J1_123_2743_n227,
DP_OP_454J1_123_2743_n223, DP_OP_454J1_123_2743_n219,
DP_OP_454J1_123_2743_n218, DP_OP_454J1_123_2743_n217,
DP_OP_454J1_123_2743_n216, DP_OP_454J1_123_2743_n214,
DP_OP_454J1_123_2743_n213, DP_OP_454J1_123_2743_n212,
DP_OP_454J1_123_2743_n210, DP_OP_454J1_123_2743_n204,
DP_OP_454J1_123_2743_n203, DP_OP_454J1_123_2743_n202,
DP_OP_454J1_123_2743_n200, DP_OP_454J1_123_2743_n199,
DP_OP_454J1_123_2743_n198, DP_OP_454J1_123_2743_n197,
DP_OP_454J1_123_2743_n196, DP_OP_454J1_123_2743_n195,
DP_OP_454J1_123_2743_n191, DP_OP_454J1_123_2743_n188,
DP_OP_454J1_123_2743_n187, DP_OP_454J1_123_2743_n186,
DP_OP_454J1_123_2743_n185, DP_OP_454J1_123_2743_n184,
DP_OP_454J1_123_2743_n183, DP_OP_454J1_123_2743_n182,
DP_OP_454J1_123_2743_n181, DP_OP_454J1_123_2743_n180,
DP_OP_454J1_123_2743_n179, DP_OP_454J1_123_2743_n178,
DP_OP_454J1_123_2743_n177, DP_OP_454J1_123_2743_n176,
DP_OP_454J1_123_2743_n175, DP_OP_454J1_123_2743_n172,
DP_OP_454J1_123_2743_n171, DP_OP_454J1_123_2743_n170,
DP_OP_454J1_123_2743_n169, DP_OP_454J1_123_2743_n168,
DP_OP_454J1_123_2743_n167, DP_OP_454J1_123_2743_n166,
DP_OP_454J1_123_2743_n165, DP_OP_454J1_123_2743_n164,
DP_OP_454J1_123_2743_n163, DP_OP_454J1_123_2743_n162,
DP_OP_454J1_123_2743_n156, DP_OP_454J1_123_2743_n155,
DP_OP_454J1_123_2743_n148, DP_OP_454J1_123_2743_n145,
DP_OP_454J1_123_2743_n144, DP_OP_454J1_123_2743_n143,
DP_OP_454J1_123_2743_n142, DP_OP_454J1_123_2743_n140,
DP_OP_454J1_123_2743_n139, DP_OP_454J1_123_2743_n138,
DP_OP_454J1_123_2743_n137, DP_OP_454J1_123_2743_n135,
DP_OP_454J1_123_2743_n134, DP_OP_454J1_123_2743_n133,
DP_OP_454J1_123_2743_n131, DP_OP_454J1_123_2743_n130,
DP_OP_454J1_123_2743_n129, DP_OP_454J1_123_2743_n128,
DP_OP_454J1_123_2743_n127, DP_OP_454J1_123_2743_n126,
DP_OP_454J1_123_2743_n125, DP_OP_454J1_123_2743_n124,
DP_OP_454J1_123_2743_n123, DP_OP_454J1_123_2743_n122,
DP_OP_454J1_123_2743_n121, DP_OP_454J1_123_2743_n120,
DP_OP_454J1_123_2743_n119, DP_OP_454J1_123_2743_n117,
DP_OP_454J1_123_2743_n116, DP_OP_454J1_123_2743_n115,
DP_OP_454J1_123_2743_n114, DP_OP_454J1_123_2743_n113,
DP_OP_454J1_123_2743_n112, DP_OP_454J1_123_2743_n111,
DP_OP_454J1_123_2743_n109, DP_OP_454J1_123_2743_n108,
DP_OP_454J1_123_2743_n107, DP_OP_454J1_123_2743_n106,
DP_OP_454J1_123_2743_n105, DP_OP_454J1_123_2743_n104,
DP_OP_454J1_123_2743_n103, DP_OP_454J1_123_2743_n102,
DP_OP_454J1_123_2743_n101, DP_OP_454J1_123_2743_n100,
DP_OP_454J1_123_2743_n99, DP_OP_454J1_123_2743_n98,
DP_OP_454J1_123_2743_n97, DP_OP_454J1_123_2743_n96,
DP_OP_454J1_123_2743_n94, DP_OP_454J1_123_2743_n93,
DP_OP_454J1_123_2743_n92, DP_OP_454J1_123_2743_n91,
DP_OP_454J1_123_2743_n90, DP_OP_454J1_123_2743_n89,
DP_OP_454J1_123_2743_n88, DP_OP_454J1_123_2743_n87,
DP_OP_454J1_123_2743_n84, DP_OP_454J1_123_2743_n83,
DP_OP_454J1_123_2743_n82, DP_OP_454J1_123_2743_n81,
DP_OP_454J1_123_2743_n80, DP_OP_454J1_123_2743_n79,
DP_OP_454J1_123_2743_n78, DP_OP_454J1_123_2743_n77,
DP_OP_454J1_123_2743_n76, DP_OP_454J1_123_2743_n75,
DP_OP_454J1_123_2743_n74, DP_OP_454J1_123_2743_n73,
DP_OP_454J1_123_2743_n72, DP_OP_454J1_123_2743_n71,
DP_OP_454J1_123_2743_n70, DP_OP_454J1_123_2743_n69,
DP_OP_454J1_123_2743_n68, DP_OP_454J1_123_2743_n67,
DP_OP_454J1_123_2743_n66, DP_OP_454J1_123_2743_n65,
DP_OP_454J1_123_2743_n64, DP_OP_454J1_123_2743_n63,
DP_OP_454J1_123_2743_n62, DP_OP_454J1_123_2743_n61,
DP_OP_454J1_123_2743_n60, DP_OP_454J1_123_2743_n59,
DP_OP_454J1_123_2743_n58, DP_OP_454J1_123_2743_n57,
DP_OP_454J1_123_2743_n56, DP_OP_454J1_123_2743_n55,
DP_OP_454J1_123_2743_n52, DP_OP_454J1_123_2743_n51,
DP_OP_454J1_123_2743_n50, DP_OP_454J1_123_2743_n49,
DP_OP_454J1_123_2743_n48, DP_OP_454J1_123_2743_n47,
DP_OP_454J1_123_2743_n46, DP_OP_454J1_123_2743_n45,
DP_OP_454J1_123_2743_n44, DP_OP_454J1_123_2743_n43,
DP_OP_454J1_123_2743_n42, DP_OP_454J1_123_2743_n41,
DP_OP_454J1_123_2743_n40, DP_OP_454J1_123_2743_n39,
DP_OP_454J1_123_2743_n38, DP_OP_454J1_123_2743_n37,
DP_OP_454J1_123_2743_n36, DP_OP_454J1_123_2743_n35, mult_x_254_n232,
mult_x_254_n228, mult_x_254_n225, mult_x_254_n220, mult_x_254_n219,
mult_x_254_n216, mult_x_254_n215, mult_x_254_n213, mult_x_254_n212,
mult_x_254_n211, mult_x_254_n208, mult_x_254_n207, mult_x_254_n206,
mult_x_254_n205, mult_x_254_n204, mult_x_254_n203, mult_x_254_n202,
mult_x_254_n200, mult_x_254_n199, mult_x_254_n198, mult_x_254_n197,
mult_x_254_n196, mult_x_254_n195, mult_x_254_n194, mult_x_254_n192,
mult_x_254_n191, mult_x_254_n190, mult_x_254_n189, mult_x_254_n186,
mult_x_254_n185, mult_x_254_n180, mult_x_254_n179, mult_x_254_n178,
mult_x_254_n176, mult_x_254_n175, mult_x_254_n174, mult_x_254_n173,
mult_x_254_n170, mult_x_254_n169, mult_x_254_n168, mult_x_254_n167,
mult_x_254_n166, mult_x_254_n165, mult_x_254_n164, mult_x_254_n163,
mult_x_254_n162, mult_x_254_n161, mult_x_254_n160, mult_x_254_n159,
mult_x_254_n158, mult_x_254_n157, mult_x_254_n151, mult_x_254_n149,
mult_x_254_n136, mult_x_254_n133, mult_x_254_n132, mult_x_254_n131,
mult_x_254_n130, mult_x_254_n129, mult_x_254_n128, mult_x_254_n127,
mult_x_254_n126, mult_x_254_n125, mult_x_254_n124, mult_x_254_n123,
mult_x_254_n122, mult_x_254_n121, mult_x_254_n120, mult_x_254_n119,
mult_x_254_n118, mult_x_254_n117, mult_x_254_n116, mult_x_254_n115,
mult_x_254_n114, mult_x_254_n113, mult_x_254_n112, mult_x_254_n111,
mult_x_254_n110, mult_x_254_n109, mult_x_254_n108, mult_x_254_n107,
mult_x_254_n106, mult_x_254_n105, mult_x_254_n104, mult_x_254_n103,
mult_x_254_n102, mult_x_254_n101, mult_x_254_n100, mult_x_254_n99,
mult_x_254_n98, mult_x_254_n97, mult_x_254_n96, mult_x_254_n95,
mult_x_254_n94, mult_x_254_n93, mult_x_254_n92, mult_x_254_n90,
mult_x_254_n89, mult_x_254_n88, mult_x_254_n87, mult_x_254_n86,
mult_x_254_n85, mult_x_254_n84, mult_x_254_n83, mult_x_254_n80,
mult_x_254_n79, mult_x_254_n78, mult_x_254_n77, mult_x_254_n76,
mult_x_254_n75, mult_x_254_n74, mult_x_254_n73, mult_x_254_n72,
mult_x_254_n71, mult_x_254_n70, mult_x_254_n69, mult_x_254_n68,
mult_x_254_n67, mult_x_254_n66, mult_x_254_n65, mult_x_254_n64,
mult_x_254_n63, mult_x_254_n62, mult_x_254_n61, mult_x_254_n60,
mult_x_254_n59, mult_x_254_n58, mult_x_254_n57, mult_x_254_n56,
mult_x_254_n55, mult_x_254_n54, mult_x_254_n53, mult_x_254_n52,
mult_x_254_n51, mult_x_254_n48, mult_x_254_n47, mult_x_254_n46,
mult_x_254_n45, mult_x_254_n44, mult_x_254_n43, mult_x_254_n42,
mult_x_254_n41, mult_x_254_n40, mult_x_254_n39, mult_x_254_n38,
mult_x_254_n37, mult_x_254_n36, mult_x_254_n35, mult_x_254_n34,
mult_x_254_n33, mult_x_254_n32, mult_x_254_n31, mult_x_219_n226,
mult_x_219_n222, mult_x_219_n214, mult_x_219_n213, mult_x_219_n210,
mult_x_219_n209, mult_x_219_n207, mult_x_219_n206, mult_x_219_n205,
mult_x_219_n202, mult_x_219_n201, mult_x_219_n200, mult_x_219_n199,
mult_x_219_n198, mult_x_219_n197, mult_x_219_n196, mult_x_219_n194,
mult_x_219_n193, mult_x_219_n192, mult_x_219_n191, mult_x_219_n190,
mult_x_219_n189, mult_x_219_n188, mult_x_219_n186, mult_x_219_n185,
mult_x_219_n184, mult_x_219_n183, mult_x_219_n180, mult_x_219_n179,
mult_x_219_n177, mult_x_219_n174, mult_x_219_n173, mult_x_219_n172,
mult_x_219_n170, mult_x_219_n169, mult_x_219_n168, mult_x_219_n167,
mult_x_219_n164, mult_x_219_n163, mult_x_219_n162, mult_x_219_n161,
mult_x_219_n160, mult_x_219_n159, mult_x_219_n158, mult_x_219_n157,
mult_x_219_n156, mult_x_219_n155, mult_x_219_n154, mult_x_219_n153,
mult_x_219_n152, mult_x_219_n151, mult_x_219_n136, mult_x_219_n133,
mult_x_219_n132, mult_x_219_n131, mult_x_219_n130, mult_x_219_n129,
mult_x_219_n128, mult_x_219_n127, mult_x_219_n126, mult_x_219_n125,
mult_x_219_n124, mult_x_219_n123, mult_x_219_n122, mult_x_219_n121,
mult_x_219_n120, mult_x_219_n119, mult_x_219_n118, mult_x_219_n117,
mult_x_219_n116, mult_x_219_n115, mult_x_219_n114, mult_x_219_n113,
mult_x_219_n112, mult_x_219_n111, mult_x_219_n110, mult_x_219_n109,
mult_x_219_n108, mult_x_219_n107, mult_x_219_n106, mult_x_219_n105,
mult_x_219_n104, mult_x_219_n103, mult_x_219_n102, mult_x_219_n101,
mult_x_219_n100, mult_x_219_n99, mult_x_219_n98, mult_x_219_n97,
mult_x_219_n96, mult_x_219_n95, mult_x_219_n94, mult_x_219_n93,
mult_x_219_n92, mult_x_219_n90, mult_x_219_n89, mult_x_219_n88,
mult_x_219_n87, mult_x_219_n86, mult_x_219_n85, mult_x_219_n84,
mult_x_219_n83, mult_x_219_n80, mult_x_219_n79, mult_x_219_n78,
mult_x_219_n77, mult_x_219_n76, mult_x_219_n75, mult_x_219_n74,
mult_x_219_n73, mult_x_219_n72, mult_x_219_n71, mult_x_219_n70,
mult_x_219_n69, mult_x_219_n68, mult_x_219_n67, mult_x_219_n66,
mult_x_219_n65, mult_x_219_n62, mult_x_219_n61, mult_x_219_n60,
mult_x_219_n59, mult_x_219_n58, mult_x_219_n57, mult_x_219_n56,
mult_x_219_n55, mult_x_219_n54, mult_x_219_n53, mult_x_219_n52,
mult_x_219_n51, mult_x_219_n48, mult_x_219_n47, mult_x_219_n46,
mult_x_219_n45, mult_x_219_n44, mult_x_219_n43, mult_x_219_n42,
mult_x_219_n41, mult_x_219_n40, mult_x_219_n39, mult_x_219_n36,
mult_x_219_n35, mult_x_219_n34, mult_x_219_n33, mult_x_219_n32,
mult_x_219_n31, DP_OP_26J1_124_9022_n18, DP_OP_26J1_124_9022_n17,
DP_OP_26J1_124_9022_n16, DP_OP_26J1_124_9022_n15,
DP_OP_26J1_124_9022_n14, DP_OP_26J1_124_9022_n8,
DP_OP_26J1_124_9022_n7, DP_OP_26J1_124_9022_n6,
DP_OP_26J1_124_9022_n5, DP_OP_26J1_124_9022_n4,
DP_OP_26J1_124_9022_n3, DP_OP_26J1_124_9022_n2,
DP_OP_26J1_124_9022_n1, DP_OP_234J1_127_8543_n22,
DP_OP_234J1_127_8543_n21, DP_OP_234J1_127_8543_n20,
DP_OP_234J1_127_8543_n19, DP_OP_234J1_127_8543_n18,
DP_OP_234J1_127_8543_n17, DP_OP_234J1_127_8543_n16,
DP_OP_234J1_127_8543_n15, DP_OP_234J1_127_8543_n9,
DP_OP_234J1_127_8543_n8, DP_OP_234J1_127_8543_n7,
DP_OP_234J1_127_8543_n6, DP_OP_234J1_127_8543_n5,
DP_OP_234J1_127_8543_n4, DP_OP_234J1_127_8543_n3,
DP_OP_234J1_127_8543_n2, DP_OP_234J1_127_8543_n1, intadd_0_A_24_,
intadd_0_A_23_, intadd_0_A_22_, intadd_0_A_21_, intadd_0_A_20_,
intadd_0_A_19_, intadd_0_A_18_, intadd_0_A_17_, intadd_0_A_16_,
intadd_0_A_15_, intadd_0_A_14_, intadd_0_A_13_, intadd_0_A_12_,
intadd_0_A_11_, intadd_0_A_10_, intadd_0_A_9_, intadd_0_A_8_,
intadd_0_A_7_, intadd_0_A_6_, intadd_0_A_5_, intadd_0_A_4_,
intadd_0_A_3_, intadd_0_A_2_, intadd_0_B_24_, intadd_0_B_23_,
intadd_0_B_22_, intadd_0_B_21_, intadd_0_B_20_, intadd_0_B_19_,
intadd_0_B_18_, intadd_0_B_17_, intadd_0_B_16_, intadd_0_B_15_,
intadd_0_B_14_, intadd_0_B_13_, intadd_0_B_12_, intadd_0_B_11_,
intadd_0_B_10_, intadd_0_B_9_, intadd_0_B_8_, intadd_0_B_7_,
intadd_0_B_6_, intadd_0_B_5_, intadd_0_B_4_, intadd_0_B_3_,
intadd_0_B_2_, intadd_0_B_1_, intadd_0_B_0_, intadd_0_SUM_24_,
intadd_0_SUM_23_, intadd_0_SUM_22_, intadd_0_SUM_21_,
intadd_0_SUM_20_, intadd_0_SUM_19_, intadd_0_SUM_18_,
intadd_0_SUM_17_, intadd_0_SUM_16_, intadd_0_SUM_15_,
intadd_0_SUM_14_, intadd_0_SUM_13_, intadd_0_SUM_12_,
intadd_0_SUM_11_, intadd_0_SUM_10_, intadd_0_SUM_9_, intadd_0_SUM_8_,
intadd_0_SUM_7_, intadd_0_SUM_6_, intadd_0_SUM_5_, intadd_0_SUM_4_,
intadd_0_SUM_3_, intadd_0_SUM_2_, intadd_0_SUM_1_, intadd_0_SUM_0_,
intadd_0_n25, intadd_0_n24, intadd_0_n23, intadd_0_n22, intadd_0_n21,
intadd_0_n20, intadd_0_n19, intadd_0_n18, intadd_0_n17, intadd_0_n16,
intadd_0_n15, intadd_0_n14, intadd_0_n13, intadd_0_n12, intadd_0_n11,
intadd_0_n10, intadd_0_n9, intadd_0_n8, intadd_0_n7, intadd_0_n6,
intadd_0_n5, intadd_0_n4, intadd_0_n3, intadd_0_n2, intadd_0_n1,
intadd_1_A_19_, intadd_1_A_0_, intadd_1_B_19_, intadd_1_B_18_,
intadd_1_B_6_, intadd_1_B_1_, intadd_1_B_0_, intadd_1_CI,
intadd_1_n20, intadd_1_n19, intadd_1_n18, intadd_1_n17, intadd_1_n16,
intadd_1_n15, intadd_1_n14, intadd_1_n13, intadd_1_n12, intadd_1_n11,
intadd_1_n10, intadd_1_n9, intadd_1_n8, intadd_1_n7, intadd_1_n6,
intadd_1_n5, intadd_1_n4, intadd_1_n3, intadd_1_n2, intadd_1_n1,
intadd_2_A_18_, intadd_2_A_17_, intadd_2_A_16_, intadd_2_A_15_,
intadd_2_A_14_, intadd_2_A_13_, intadd_2_A_12_, intadd_2_A_11_,
intadd_2_A_10_, intadd_2_A_9_, intadd_2_A_8_, intadd_2_A_7_,
intadd_2_A_6_, intadd_2_A_5_, intadd_2_A_4_, intadd_2_A_3_,
intadd_2_A_2_, intadd_2_A_1_, intadd_2_A_0_, intadd_2_B_18_,
intadd_2_B_17_, intadd_2_B_16_, intadd_2_B_15_, intadd_2_B_14_,
intadd_2_B_13_, intadd_2_B_12_, intadd_2_B_11_, intadd_2_B_10_,
intadd_2_B_9_, intadd_2_B_8_, intadd_2_B_7_, intadd_2_B_6_,
intadd_2_B_5_, intadd_2_B_4_, intadd_2_B_3_, intadd_2_B_2_,
intadd_2_B_1_, intadd_2_B_0_, intadd_2_CI, intadd_2_SUM_18_,
intadd_2_SUM_17_, intadd_2_SUM_16_, intadd_2_SUM_15_,
intadd_2_SUM_14_, intadd_2_SUM_13_, intadd_2_SUM_12_,
intadd_2_SUM_11_, intadd_2_SUM_10_, intadd_2_SUM_9_, intadd_2_SUM_8_,
intadd_2_SUM_7_, intadd_2_SUM_6_, intadd_2_SUM_5_, intadd_2_SUM_4_,
intadd_2_SUM_3_, intadd_2_SUM_2_, intadd_2_SUM_1_, intadd_2_SUM_0_,
intadd_2_n19, intadd_2_n18, intadd_2_n17, intadd_2_n16, intadd_2_n15,
intadd_2_n14, intadd_2_n13, intadd_2_n12, intadd_2_n11, intadd_2_n10,
intadd_2_n9, intadd_2_n8, intadd_2_n7, intadd_2_n6, intadd_2_n5,
intadd_2_n4, intadd_2_n3, intadd_2_n2, intadd_2_n1, intadd_3_A_18_,
intadd_3_A_17_, intadd_3_A_16_, intadd_3_A_15_, intadd_3_A_14_,
intadd_3_A_13_, intadd_3_A_12_, intadd_3_A_11_, intadd_3_A_10_,
intadd_3_A_9_, intadd_3_A_8_, intadd_3_A_7_, intadd_3_A_6_,
intadd_3_A_5_, intadd_3_A_4_, intadd_3_A_3_, intadd_3_A_2_,
intadd_3_A_1_, intadd_3_A_0_, intadd_3_B_18_, intadd_3_B_17_,
intadd_3_B_16_, intadd_3_B_15_, intadd_3_B_14_, intadd_3_B_13_,
intadd_3_B_12_, intadd_3_B_11_, intadd_3_B_10_, intadd_3_B_9_,
intadd_3_B_8_, intadd_3_B_7_, intadd_3_B_6_, intadd_3_B_5_,
intadd_3_B_4_, intadd_3_B_3_, intadd_3_B_2_, intadd_3_B_1_,
intadd_3_B_0_, intadd_3_CI, intadd_3_SUM_18_, intadd_3_SUM_17_,
intadd_3_SUM_16_, intadd_3_SUM_15_, intadd_3_SUM_14_,
intadd_3_SUM_13_, intadd_3_SUM_12_, intadd_3_SUM_11_,
intadd_3_SUM_10_, intadd_3_SUM_9_, intadd_3_SUM_8_, intadd_3_SUM_7_,
intadd_3_SUM_6_, intadd_3_SUM_5_, intadd_3_SUM_4_, intadd_3_SUM_3_,
intadd_3_SUM_2_, intadd_3_SUM_1_, intadd_3_SUM_0_, intadd_3_n19,
intadd_3_n18, intadd_3_n17, intadd_3_n16, intadd_3_n15, intadd_3_n14,
intadd_3_n13, intadd_3_n12, intadd_3_n11, intadd_3_n10, intadd_3_n9,
intadd_3_n8, intadd_3_n7, intadd_3_n6, intadd_3_n5, intadd_3_n4,
intadd_3_n3, intadd_3_n2, intadd_3_n1, intadd_4_CI, intadd_4_SUM_9_,
intadd_4_SUM_8_, intadd_4_SUM_7_, intadd_4_SUM_6_, intadd_4_SUM_5_,
intadd_4_SUM_4_, intadd_4_SUM_3_, intadd_4_SUM_2_, intadd_4_SUM_1_,
intadd_4_SUM_0_, intadd_4_n10, intadd_4_n9, intadd_4_n8, intadd_4_n7,
intadd_4_n6, intadd_4_n5, intadd_4_n4, intadd_4_n3, intadd_4_n2,
intadd_4_n1, intadd_5_CI, intadd_5_SUM_9_, intadd_5_SUM_8_,
intadd_5_SUM_7_, intadd_5_SUM_6_, intadd_5_SUM_5_, intadd_5_SUM_4_,
intadd_5_SUM_3_, intadd_5_SUM_2_, intadd_5_SUM_1_, intadd_5_SUM_0_,
intadd_5_n10, intadd_5_n9, intadd_5_n8, intadd_5_n7, intadd_5_n6,
intadd_5_n5, intadd_5_n4, intadd_5_n3, intadd_5_n2, intadd_5_n1,
intadd_6_CI, intadd_6_SUM_2_, intadd_6_SUM_1_, intadd_6_SUM_0_,
intadd_6_n3, intadd_6_n2, intadd_6_n1, intadd_7_CI, intadd_7_SUM_2_,
intadd_7_SUM_1_, intadd_7_SUM_0_, intadd_7_n3, intadd_7_n2,
intadd_7_n1, intadd_8_CI, intadd_8_SUM_2_, intadd_8_SUM_1_,
intadd_8_SUM_0_, intadd_8_n3, intadd_8_n2, intadd_8_n1, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865,
n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875,
n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885,
n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895,
n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995,
n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005,
n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015,
n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025,
n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035,
n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045,
n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055,
n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065,
n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075,
n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085,
n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095,
n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105,
n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115,
n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125,
n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135,
n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145,
n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155,
n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165,
n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175,
n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185,
n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195,
n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205,
n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215,
n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225,
n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235,
n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245,
n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255,
n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265,
n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275,
n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285,
n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295,
n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305,
n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315,
n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325,
n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335,
n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345,
n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355,
n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365,
n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375,
n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385,
n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395,
n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405,
n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415,
n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425,
n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435,
n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445,
n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455,
n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465,
n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475,
n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485,
n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495,
n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505,
n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515,
n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525,
n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535,
n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545,
n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555,
n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565,
n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575,
n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585,
n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595,
n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605,
n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615,
n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625,
n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635,
n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645,
n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655,
n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665,
n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675,
n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685,
n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695,
n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705,
n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715,
n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725,
n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735,
n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745,
n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755,
n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765,
n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775,
n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905,
n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915,
n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925,
n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995,
n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005,
n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015,
n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025,
n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035,
n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045,
n4046, n4047, n4048, n4049, n4051, n4052, n4053, n4054, n4055, n4056,
n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066,
n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076,
n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086,
n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096,
n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106,
n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116,
n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126,
n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136,
n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146,
n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156,
n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166,
n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176,
n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186,
n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196,
n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206,
n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216,
n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226,
n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236,
n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246,
n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256,
n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265, n4266,
n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275, n4276,
n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285, n4286,
n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295, n4296,
n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305, n4306,
n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315, n4316,
n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325, n4326,
n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335, n4336,
n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345, n4346,
n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355, n4356,
n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365, n4366,
n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375, n4376,
n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385, n4386,
n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395, n4396,
n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405, n4406,
n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415, n4416,
n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425, n4426,
n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435, n4436,
n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445, n4446,
n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455, n4456,
n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465, n4466,
n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475, n4476,
n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485, n4486,
n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495, n4496,
n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505, n4506,
n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515, n4516,
n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525, n4526,
n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535, n4536,
n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545, n4546,
n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555, n4556,
n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565, n4566,
n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575, n4576,
n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585, n4586,
n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595, n4596,
n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606,
n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615, n4616,
n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626,
n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635, n4636,
n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646,
n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656,
n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666,
n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676,
n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686,
n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696,
n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706,
n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716,
n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725, n4726,
n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735, n4736,
n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745, n4746,
n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756,
n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766,
n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775, n4776,
n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785, n4786,
n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795, n4796,
n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805, n4806,
n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815, n4816,
n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825, n4826,
n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835, n4836,
n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845, n4846,
n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855, n4856,
n4857, n4858, n4860, n4861, n4862, n4863, n4864, n4865, n4866, n4867,
n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875, n4876, n4877,
n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885, n4886, n4887,
n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895, n4896, n4897,
n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905, n4906, n4907,
n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915, n4916, n4917,
n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925, n4926, n4927,
n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935, n4936, n4937,
n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945, n4946, n4947,
n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955, n4956, n4957,
n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965, n4966, n4967,
n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975, n4976, n4977,
n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985, n4986, n4987,
n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995, n4996, n4997,
n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005, n5006, n5007,
n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015, n5016, n5017,
n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025, n5026, n5027,
n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035, n5036, n5037,
n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045, n5046, n5047,
n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055, n5056, n5057,
n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065, n5066, n5067,
n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075, n5076, n5077,
n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085, n5086, n5087,
n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095, n5096, n5097,
n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105, n5106, n5107,
n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115, n5116, n5117,
n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125, n5126, n5127,
n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135, n5136, n5137,
n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145, n5146, n5147,
n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155, n5156, n5157,
n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165, n5166, n5167,
n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5176, n5177, n5178,
n5179, n5180, n5181, n5182, n5183, n5184, n5185, n5186, n5187, n5188,
n5189, n5190, n5191, n5192, n5193, n5194, n5195, n5196, n5197, n5198,
n5199, n5200, n5201, n5202, n5203, n5204, n5205, n5206, n5207, n5208,
n5209, n5210, n5211, n5212, n5213, n5214, n5215, n5216, n5217, n5218,
n5219, n5220, n5221, n5222, n5223, n5224, n5225, n5226, n5227, n5228,
n5229, n5230, n5231, n5232, n5233, n5234, n5235, n5236, n5237, n5238,
n5239, n5240, n5241, n5242, n5243, n5244, n5245, n5246, n5247, n5248,
n5249, n5250, n5251, n5252, n5253, n5254, n5255, n5256, n5257, n5258,
n5259, n5260, n5261, n5262, n5263, n5264, n5265, n5266, n5267, n5268,
n5269, n5270, n5271, n5272, n5273, n5274, n5275, n5276, n5277, n5278,
n5279, n5280, n5282, n5283, n5284, n5285, n5286;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:3] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:0] FPMULT_P_Sgf;
wire [25:1] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [25:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [11:0] FPMULT_Sgf_operation_Result;
wire [25:0] FPMULT_Sgf_operation_EVEN1_Q_middle;
wire [23:12] FPMULT_Sgf_operation_EVEN1_Q_right;
wire [23:0] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n5261), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n5248), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n5261), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n5247), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n5247), .Q(
dataB[31]) );
DFFRXLTS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2142), .CK(clk), .RN(n5246),
.Q(FPSENCOS_cont_iter_out[0]), .QN(n4995) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2148), .CK(clk), .RN(
n5178), .Q(FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n5095) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2146), .CK(clk), .RN(
n5215), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2143), .CK(clk), .RN(
n5217), .Q(FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n5091) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2136), .CK(clk), .RN(n5245),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2133), .CK(clk), .RN(n5245), .Q(
FPSENCOS_d_ff3_LUT_out[1]), .QN(n5135) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2131), .CK(clk), .RN(n5245), .Q(
FPSENCOS_d_ff3_LUT_out[3]), .QN(n5139) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2128), .CK(clk), .RN(n5244), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2127), .CK(clk), .RN(n5244), .Q(
FPSENCOS_d_ff3_LUT_out[7]), .QN(n5140) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2126), .CK(clk), .RN(n5244), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2125), .CK(clk), .RN(n5244), .Q(
FPSENCOS_d_ff3_LUT_out[9]), .QN(n5136) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2123), .CK(clk), .RN(n5244), .Q(
FPSENCOS_d_ff3_LUT_out[12]), .QN(n5137) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2122), .CK(clk), .RN(n5244), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2121), .CK(clk), .RN(n5244), .Q(
FPSENCOS_d_ff3_LUT_out[15]), .QN(n5141) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2120), .CK(clk), .RN(n5244), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2119), .CK(clk), .RN(n5244), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2118), .CK(clk), .RN(n5243), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2115), .CK(clk), .RN(n5243), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2114), .CK(clk), .RN(n5243), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1854), .CK(clk), .RN(n5243),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1853), .CK(clk), .RN(n5243),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1852), .CK(clk), .RN(n5243),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1851), .CK(clk), .RN(n5243),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1850), .CK(clk), .RN(n5243),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1849), .CK(clk), .RN(n5242),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1848), .CK(clk), .RN(n5242),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1952), .CK(clk), .RN(n5242),
.Q(FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1951), .CK(clk), .RN(n5242),
.QN(n2392) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1950), .CK(clk), .RN(n5242),
.QN(n2401) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1949), .CK(clk), .RN(n5242),
.QN(n2402) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1948), .CK(clk), .RN(n5242),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1947), .CK(clk), .RN(n5242),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1946), .CK(clk), .RN(n5242),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1945), .CK(clk), .RN(n5241),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2113), .CK(clk), .RN(n5247), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2112), .CK(clk), .RN(n5260), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2111), .CK(clk), .RN(n5260), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2110), .CK(clk), .RN(n5260), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2109), .CK(clk), .RN(n5260), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2108), .CK(clk), .RN(n5260), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2107), .CK(clk), .RN(n5260), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2106), .CK(clk), .RN(n5260), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2105), .CK(clk), .RN(n5259), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2104), .CK(clk), .RN(n5259), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2103), .CK(clk), .RN(n5259), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2102), .CK(clk), .RN(n5259), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2101), .CK(clk), .RN(n5259), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2100), .CK(clk), .RN(n5259), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2099), .CK(clk), .RN(n5259), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2098), .CK(clk), .RN(n5259), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2097), .CK(clk), .RN(n5259), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2096), .CK(clk), .RN(n5259), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2095), .CK(clk), .RN(n5258), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2094), .CK(clk), .RN(n5258), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2093), .CK(clk), .RN(n5258), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2092), .CK(clk), .RN(n5258), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2091), .CK(clk), .RN(n5258), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2090), .CK(clk), .RN(n5258), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2089), .CK(clk), .RN(n5258), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2088), .CK(clk), .RN(n5258), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2087), .CK(clk), .RN(n5258), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2086), .CK(clk), .RN(n5258), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2085), .CK(clk), .RN(n5257), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2084), .CK(clk), .RN(n5257), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2083), .CK(clk), .RN(n5257), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2082), .CK(clk), .RN(n5257), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1787), .CK(clk), .RN(n5257), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1742), .CK(clk), .RN(
n5257), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1784), .CK(clk), .RN(n5256), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1741), .CK(clk), .RN(
n5256), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1781), .CK(clk), .RN(n5256), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1740), .CK(clk), .RN(
n5255), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1778), .CK(clk), .RN(n5255), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1739), .CK(clk), .RN(
n5255), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1775), .CK(clk), .RN(n5254), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1738), .CK(clk), .RN(
n5254), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1772), .CK(clk), .RN(n5253), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1737), .CK(clk), .RN(
n5253), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1699), .CK(clk), .RN(n5253),
.Q(cordic_result[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1769), .CK(clk), .RN(n5253), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1736), .CK(clk), .RN(
n5253), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1766), .CK(clk), .RN(n5252), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1735), .CK(clk), .RN(
n5252), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2009), .CK(clk), .RN(n5251), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1743), .CK(clk), .RN(
n5251), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1864), .CK(clk), .RN(
n5251), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1863), .CK(clk), .RN(n5251),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1961), .CK(clk), .RN(n5251),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2030), .CK(clk), .RN(n5250), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1750), .CK(clk), .RN(
n5250), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1877), .CK(clk), .RN(n5250),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1975), .CK(clk), .RN(n5250),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2021), .CK(clk), .RN(n5250), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1747), .CK(clk), .RN(
n5250), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1872), .CK(clk), .RN(
n5249), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1871), .CK(clk), .RN(n5249),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1969), .CK(clk), .RN(n5249),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1790), .CK(clk), .RN(n5181),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2012), .CK(clk), .RN(n5249), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1744), .CK(clk), .RN(
n5249), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1866), .CK(clk), .RN(
n5249), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1865), .CK(clk), .RN(n5248),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1963), .CK(clk), .RN(n5229),
.QN(n2390) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2018), .CK(clk), .RN(n5229), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1746), .CK(clk), .RN(
n5229), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1870), .CK(clk), .RN(
n5229), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1869), .CK(clk), .RN(n5229),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1967), .CK(clk), .RN(n5229),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1791), .CK(clk), .RN(n5181),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2015), .CK(clk), .RN(n5229), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1745), .CK(clk), .RN(
n5228), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1868), .CK(clk), .RN(
n5228), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1867), .CK(clk), .RN(n5228),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1965), .CK(clk), .RN(n5228),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2024), .CK(clk), .RN(n5228), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1748), .CK(clk), .RN(
n5228), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1874), .CK(clk), .RN(
n5227), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1873), .CK(clk), .RN(n5227),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1971), .CK(clk), .RN(n5227),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2063), .CK(clk), .RN(n5227), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1761), .CK(clk), .RN(
n5227), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1900), .CK(clk), .RN(
n5227), .Q(FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1899), .CK(clk), .RN(n5227),
.Q(FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1997), .CK(clk), .RN(n5226),
.QN(n2397) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2057), .CK(clk), .RN(n5226), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1759), .CK(clk), .RN(
n5226), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1896), .CK(clk), .RN(
n5226), .Q(FPSENCOS_d_ff2_Y[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1895), .CK(clk), .RN(n5226),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1993), .CK(clk), .RN(n5225),
.QN(n2399) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2036), .CK(clk), .RN(n5225), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1752), .CK(clk), .RN(
n5225), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1882), .CK(clk), .RN(
n5225), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1881), .CK(clk), .RN(n5225),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1979), .CK(clk), .RN(n5225),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2027), .CK(clk), .RN(n5225), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1749), .CK(clk), .RN(
n5224), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1876), .CK(clk), .RN(
n5224), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1875), .CK(clk), .RN(n5224),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1973), .CK(clk), .RN(n5224),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2051), .CK(clk), .RN(n5224), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1757), .CK(clk), .RN(
n5224), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1891), .CK(clk), .RN(n5223),
.Q(FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1989), .CK(clk), .RN(n5223),
.QN(n2388) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2042), .CK(clk), .RN(n5223), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1754), .CK(clk), .RN(
n5223), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1886), .CK(clk), .RN(
n5223), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1885), .CK(clk), .RN(n5222),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1983), .CK(clk), .RN(n5222),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2033), .CK(clk), .RN(n5222), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1751), .CK(clk), .RN(
n5222), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1880), .CK(clk), .RN(
n5222), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1879), .CK(clk), .RN(n5222),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1977), .CK(clk), .RN(n5221),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2045), .CK(clk), .RN(n5221), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1755), .CK(clk), .RN(
n5221), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1888), .CK(clk), .RN(
n5221), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1887), .CK(clk), .RN(n5221),
.Q(FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1985), .CK(clk), .RN(n5221),
.QN(n2389) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2039), .CK(clk), .RN(n5220), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1753), .CK(clk), .RN(
n5220), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1884), .CK(clk), .RN(
n5220), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1883), .CK(clk), .RN(n5220),
.Q(FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1981), .CK(clk), .RN(n5220),
.QN(n2391) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(n5220), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1846), .CK(clk), .RN(
n5219), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1845), .CK(clk), .RN(n5219),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1943), .CK(clk), .RN(n5219),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2066), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1762), .CK(clk), .RN(
n5219), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1902), .CK(clk), .RN(
n5218), .Q(FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1901), .CK(clk), .RN(n5218),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n1999), .CK(clk), .RN(n5218),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1724), .CK(clk), .RN(n5218),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2069), .CK(clk), .RN(n5218), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1763), .CK(clk), .RN(
n5218), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1904), .CK(clk), .RN(
n5223), .Q(FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1903), .CK(clk), .RN(n5241),
.Q(FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2001), .CK(clk), .RN(n5241),
.QN(n2403) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1725), .CK(clk), .RN(n5241),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2054), .CK(clk), .RN(n5241), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1758), .CK(clk), .RN(
n5241), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1894), .CK(clk), .RN(
n2618), .Q(FPSENCOS_d_ff2_Y[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1893), .CK(clk), .RN(n5262),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1991), .CK(clk), .RN(n5231),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1720), .CK(clk), .RN(n5233),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2075), .CK(clk), .RN(n2616), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1908), .CK(clk), .RN(
n5234), .Q(FPSENCOS_d_ff2_Y[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1907), .CK(clk), .RN(n5239),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2005), .CK(clk), .RN(n5239),
.QN(n2393) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1727), .CK(clk), .RN(n5239),
.Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2072), .CK(clk), .RN(n5239), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1764), .CK(clk), .RN(
n5239), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1905), .CK(clk), .RN(n5239),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2003), .CK(clk), .RN(n5238),
.QN(n2396) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2048), .CK(clk), .RN(n5238), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1756), .CK(clk), .RN(
n5238), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1890), .CK(clk), .RN(
n5238), .Q(FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1889), .CK(clk), .RN(n5238),
.Q(FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1987), .CK(clk), .RN(n5237),
.QN(n2398) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1718), .CK(clk), .RN(n5237),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2060), .CK(clk), .RN(n5237), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1760), .CK(clk), .RN(
n5237), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1898), .CK(clk), .RN(
n5237), .Q(FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1897), .CK(clk), .RN(n5237),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1995), .CK(clk), .RN(n5236),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1722), .CK(clk), .RN(n5236),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1696), .CK(clk), .RN(n5236),
.Q(cordic_result[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1715), .CK(clk), .RN(n5236),
.Q(cordic_result[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1717), .CK(clk), .RN(n5236),
.Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1713), .CK(clk), .RN(n5236),
.Q(cordic_result[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1716), .CK(clk), .RN(n5236),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1719), .CK(clk), .RN(n5236),
.Q(cordic_result[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1711), .CK(clk), .RN(n5236),
.Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1714), .CK(clk), .RN(n5236),
.Q(cordic_result[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1721), .CK(clk), .RN(n5235),
.Q(cordic_result[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1723), .CK(clk), .RN(n5235),
.Q(cordic_result[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1710), .CK(clk), .RN(n5235),
.Q(cordic_result[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1707), .CK(clk), .RN(n5235),
.Q(cordic_result[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1708), .CK(clk), .RN(n5235),
.Q(cordic_result[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1706), .CK(clk), .RN(n5235),
.Q(cordic_result[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1709), .CK(clk), .RN(n5235),
.Q(cordic_result[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1712), .CK(clk), .RN(n5235),
.Q(cordic_result[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1705), .CK(clk), .RN(n5235),
.Q(cordic_result[22]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1625), .CK(clk),
.RN(n5270), .Q(FPMULT_Op_MY[31]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1680), .CK(clk),
.RN(n5277), .Q(FPMULT_Op_MX[21]), .QN(n2206) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1678), .CK(clk),
.RN(n5276), .Q(FPMULT_Op_MX[19]), .QN(n2209) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1676), .CK(clk),
.RN(n5276), .Q(FPMULT_Op_MX[17]), .QN(n2201) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1668), .CK(clk),
.RN(n5275), .Q(FPMULT_Op_MX[9]), .QN(n2227) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1666), .CK(clk),
.RN(n5275), .Q(FPMULT_Op_MX[7]), .QN(n2225) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1664), .CK(clk),
.RN(n5275), .Q(FPMULT_Op_MX[5]), .QN(n2228) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n1662), .CK(clk),
.RN(n5275), .Q(FPMULT_Op_MX[3]), .QN(n2229) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n1660), .CK(clk),
.RN(n5275), .Q(FPMULT_Op_MX[1]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1658), .CK(clk),
.RN(n5274), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n1639), .CK(clk),
.RN(n5270), .Q(FPMULT_Op_MY[12]), .QN(n2204) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n1576), .CK(clk),
.RN(n5234), .Q(FPMULT_P_Sgf[46]), .QN(n5131) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n1575), .CK(clk),
.RN(n2618), .Q(FPMULT_P_Sgf[45]), .QN(n5154) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n1574), .CK(clk),
.RN(n5262), .Q(FPMULT_P_Sgf[44]), .QN(n5150) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n1573), .CK(clk),
.RN(n2609), .Q(FPMULT_P_Sgf[43]), .QN(n5155) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n1570), .CK(clk),
.RN(n5233), .Q(FPMULT_P_Sgf[40]), .QN(n5148) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n1569), .CK(clk),
.RN(n2616), .Q(FPMULT_P_Sgf[39]), .QN(n5149) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n1568), .CK(clk),
.RN(n5234), .Q(FPMULT_P_Sgf[38]), .QN(n5151) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n1567), .CK(clk),
.RN(n2609), .Q(FPMULT_P_Sgf[37]), .QN(n5156) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n1566), .CK(clk),
.RN(n5231), .Q(FPMULT_P_Sgf[36]), .QN(n5157) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n1565), .CK(clk),
.RN(n5233), .Q(FPMULT_P_Sgf[35]), .QN(n5152) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n1564), .CK(clk),
.RN(n2616), .Q(FPMULT_P_Sgf[34]), .QN(n5158) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n1563), .CK(clk),
.RN(n5234), .Q(FPMULT_P_Sgf[33]), .QN(n5159) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n1562), .CK(clk),
.RN(n2618), .Q(FPMULT_P_Sgf[32]), .QN(n5142) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n1561), .CK(clk),
.RN(n5262), .Q(FPMULT_P_Sgf[31]), .QN(n5153) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n1560), .CK(clk),
.RN(n2609), .Q(FPMULT_P_Sgf[30]), .QN(n5160) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n1559), .CK(clk),
.RN(n5231), .Q(FPMULT_P_Sgf[29]), .QN(n5143) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n1558), .CK(clk),
.RN(n5233), .Q(FPMULT_P_Sgf[28]), .QN(n5144) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n1557), .CK(clk),
.RN(n5232), .Q(FPMULT_P_Sgf[27]), .QN(n5145) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n1556), .CK(clk),
.RN(n5232), .Q(FPMULT_P_Sgf[26]), .QN(n5146) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n1555), .CK(clk),
.RN(n5232), .Q(FPMULT_P_Sgf[25]), .QN(n5147) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n1553), .CK(clk),
.RN(n5232), .Q(FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n1552), .CK(clk),
.RN(n5232), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n1551), .CK(clk),
.RN(n5232), .Q(FPMULT_P_Sgf[21]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n1550), .CK(clk),
.RN(n5232), .Q(FPMULT_P_Sgf[20]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n1549), .CK(clk),
.RN(n5232), .Q(FPMULT_P_Sgf[19]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n1548), .CK(clk),
.RN(n5232), .Q(FPMULT_P_Sgf[18]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n1547), .CK(clk),
.RN(n5234), .Q(FPMULT_P_Sgf[17]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n1546), .CK(clk),
.RN(n2609), .Q(FPMULT_P_Sgf[16]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n1545), .CK(clk),
.RN(n5231), .Q(FPMULT_P_Sgf[15]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n1544), .CK(clk),
.RN(n5233), .Q(FPMULT_P_Sgf[14]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n1543), .CK(clk),
.RN(n5234), .Q(FPMULT_P_Sgf[13]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n1542), .CK(clk),
.RN(n2609), .Q(FPMULT_P_Sgf[12]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n1541), .CK(clk),
.RN(n5231), .Q(FPMULT_P_Sgf[11]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n1540), .CK(clk),
.RN(n5233), .Q(FPMULT_P_Sgf[10]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n1539), .CK(clk),
.RN(n5234), .Q(FPMULT_P_Sgf[9]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n1538), .CK(clk),
.RN(n2609), .Q(FPMULT_P_Sgf[8]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n1537), .CK(clk),
.RN(n5233), .Q(FPMULT_P_Sgf[7]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n1536), .CK(clk),
.RN(n2616), .Q(FPMULT_P_Sgf[6]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n1535), .CK(clk),
.RN(n5234), .Q(FPMULT_P_Sgf[5]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n1534), .CK(clk),
.RN(n2618), .Q(FPMULT_P_Sgf[4]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n1533), .CK(clk),
.RN(n2609), .Q(FPMULT_P_Sgf[3]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n1532), .CK(clk),
.RN(n5231), .Q(FPMULT_P_Sgf[2]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n1531), .CK(clk),
.RN(n5233), .Q(FPMULT_P_Sgf[1]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n1530), .CK(clk),
.RN(n2616), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1622), .CK(
clk), .RN(n5267), .Q(FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1577), .CK(clk), .RN(n5265), .Q(mult_result[31]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1585), .CK(clk), .RN(n5265), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1584), .CK(clk), .RN(n5265), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1583), .CK(clk), .RN(n5264), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1582), .CK(clk), .RN(n5264), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1581), .CK(clk), .RN(n5264), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1580), .CK(clk), .RN(n5264), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1579), .CK(clk), .RN(n5264), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1578), .CK(clk), .RN(n5264), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1505), .CK(clk), .RN(n5264), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1504), .CK(clk), .RN(n5264), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1503), .CK(clk), .RN(n5264), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1502), .CK(clk), .RN(n5264), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1501), .CK(clk), .RN(n5263), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1500), .CK(clk), .RN(n5263), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1499), .CK(clk), .RN(n5263), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1498), .CK(clk), .RN(n5263), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1497), .CK(clk), .RN(n5263), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1496), .CK(clk), .RN(n5263), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1495), .CK(clk), .RN(n5263), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1494), .CK(clk), .RN(n5263), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1493), .CK(clk), .RN(n5263), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1492), .CK(clk), .RN(n5263), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1491), .CK(clk), .RN(n2352), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1490), .CK(clk), .RN(n2352), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1489), .CK(clk), .RN(n2352), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1488), .CK(clk), .RN(n2613), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1487), .CK(clk), .RN(n2613), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1486), .CK(clk), .RN(n2352), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1485), .CK(clk), .RN(n2352), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1484), .CK(clk), .RN(n5278), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1482), .CK(clk), .RN(n5278), .Q(mult_result[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1479), .CK(clk), .RN(
n5188), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1478), .CK(clk), .RN(
n5188), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1475), .CK(clk), .RN(
n5188), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1474), .CK(clk), .RN(
n5206), .Q(result_add_subt[23]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1473), .CK(clk), .RN(
n5206), .Q(result_add_subt[24]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1472), .CK(clk), .RN(
n5206), .Q(result_add_subt[25]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1471), .CK(clk), .RN(
n5206), .Q(result_add_subt[26]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1470), .CK(clk), .RN(
n5207), .Q(result_add_subt[27]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1469), .CK(clk), .RN(
n5207), .Q(result_add_subt[28]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1468), .CK(clk), .RN(
n5207), .Q(result_add_subt[29]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1467), .CK(clk), .RN(
n5207), .Q(result_add_subt[30]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1461), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1460), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1459), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1458), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1456), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1455), .CK(clk), .RN(
n5215), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1453), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1451), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1450), .CK(clk), .RN(
n5216), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1448), .CK(clk), .RN(n5190),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n5190),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(clk), .RN(n5190),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1445), .CK(clk), .RN(
n5216), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n5190),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n5190),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(clk), .RN(n5190),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1440), .CK(clk), .RN(
n5216), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n5190),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n5190),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1436), .CK(clk), .RN(n5190),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1435), .CK(clk), .RN(
n5216), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1433), .CK(clk), .RN(n5190),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n5191),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1431), .CK(clk), .RN(n5191),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1430), .CK(clk), .RN(
n5216), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1428), .CK(clk), .RN(n5191),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n5191),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1426), .CK(clk), .RN(n5191),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1425), .CK(clk), .RN(
n5217), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1423), .CK(clk), .RN(n5191),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n5191),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1421), .CK(clk), .RN(n5191),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1417), .CK(clk), .RN(n5191),
.Q(FPADDSUB_DmP_EXP_EWSW[24]), .QN(n5086) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1416), .CK(clk), .RN(n5192),
.Q(FPADDSUB_DmP_EXP_EWSW[25]), .QN(n5085) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1415), .CK(clk), .RN(n5192),
.Q(FPADDSUB_DmP_EXP_EWSW[26]), .QN(n5123) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1413), .CK(clk), .RN(n5192), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1412), .CK(clk), .RN(n5207), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1410), .CK(clk), .RN(
n5207), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1409), .CK(clk), .RN(
n5192), .Q(result_add_subt[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(n5192),
.Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1407), .CK(clk), .RN(
n5203), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1406), .CK(clk), .RN(
n5192), .Q(result_add_subt[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(n5192),
.Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1404), .CK(clk), .RN(
n5203), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1403), .CK(clk), .RN(
n5192), .Q(result_add_subt[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(n5192),
.Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1401), .CK(clk), .RN(
n5203), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1400), .CK(clk), .RN(
n5193), .Q(result_add_subt[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(n5193),
.Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1398), .CK(clk), .RN(
n5203), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1397), .CK(clk), .RN(
n5193), .Q(result_add_subt[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(n5193),
.Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1395), .CK(clk), .RN(
n5203), .QN(n5099) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1394), .CK(clk), .RN(
n5193), .Q(result_add_subt[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(n5193),
.Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1392), .CK(clk), .RN(
n5203), .QN(n5100) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1391), .CK(clk), .RN(
n5193), .Q(result_add_subt[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(n5193),
.Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1389), .CK(clk), .RN(
n5203), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1388), .CK(clk), .RN(
n5193), .Q(result_add_subt[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(n5193),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1386), .CK(clk), .RN(
n5202), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(
n5194), .Q(result_add_subt[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(n5194),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1383), .CK(clk), .RN(
n5202), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1382), .CK(clk), .RN(
n5194), .Q(result_add_subt[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(n5194),
.Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1380), .CK(clk), .RN(
n5194), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1379), .CK(clk), .RN(
n5194), .Q(result_add_subt[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(n5194),
.Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1377), .CK(clk), .RN(
n5203), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1376), .CK(clk), .RN(
n5194), .Q(result_add_subt[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(n5194),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1374), .CK(clk), .RN(
n5203), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1373), .CK(clk), .RN(
n5194), .Q(result_add_subt[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(n5195),
.Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1371), .CK(clk), .RN(
n5195), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1370), .CK(clk), .RN(
n5195), .Q(result_add_subt[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(n5195),
.Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1368), .CK(clk), .RN(
n5195), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1367), .CK(clk), .RN(
n5195), .Q(result_add_subt[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(n5195),
.Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1365), .CK(clk), .RN(
n5195), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1364), .CK(clk), .RN(
n5195), .Q(result_add_subt[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1363), .CK(clk), .RN(n5195),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n5196), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n5196), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1360), .CK(clk), .RN(n5196),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1359), .CK(clk), .RN(n5196),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1358), .CK(clk), .RN(
n5202), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1357), .CK(clk), .RN(
n5196), .Q(result_add_subt[31]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n5196),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n5196), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n5196), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1352), .CK(clk), .RN(n5208),
.Q(FPADDSUB_ADD_OVRFLW_NRM), .QN(n5056) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1336), .CK(clk), .RN(
n5205), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1335), .CK(clk), .RN(
n5205), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1334), .CK(clk), .RN(
n5205), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1332), .CK(clk), .RN(
n5205), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n5096) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1331), .CK(clk), .RN(
n5215), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1330), .CK(clk), .RN(
n5196), .Q(result_add_subt[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(n5196),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1328), .CK(clk), .RN(
n5202), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(n5197),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n5197),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n5168), .CK(clk), .RN(n5211),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1323), .CK(clk), .RN(
n5207), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1321), .CK(clk), .RN(
n5205), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n5124) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1319), .CK(clk), .RN(
n5207), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1314), .CK(clk), .RN(
n5197), .Q(result_add_subt[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(n5197),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1312), .CK(clk), .RN(
n5202), .QN(n5101) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(n5197),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n5197),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n5167), .CK(clk), .RN(n5211),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1307), .CK(clk), .RN(
n5197), .Q(result_add_subt[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(n5197),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1305), .CK(clk), .RN(
n5203), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n5197),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n5197),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n5166), .CK(clk), .RN(n5212),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1300), .CK(clk), .RN(
n5217), .Q(result_add_subt[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(n5217),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1298), .CK(clk), .RN(
n5202), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n5217),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n2614),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n5165), .CK(clk), .RN(n5211),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1293), .CK(clk), .RN(
n2784), .Q(result_add_subt[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(n2614),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1291), .CK(clk), .RN(
n5202), .QN(n5102) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(n2612),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n2619),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n5164), .CK(clk), .RN(n5211),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1286), .CK(clk), .RN(
n2611), .Q(result_add_subt[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(n2612),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1284), .CK(clk), .RN(
n5198), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(n5198),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n5198),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n5212),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1279), .CK(clk), .RN(
n5198), .Q(result_add_subt[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(n5198),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1277), .CK(clk), .RN(
n5202), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(n5198),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n5198),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n5163), .CK(clk), .RN(n5212),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1272), .CK(clk), .RN(n5198),
.Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1271), .CK(clk), .RN(
n5198), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(n5198),
.Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n5199),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n5213),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1266), .CK(clk), .RN(n5199),
.Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n5199),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n5213),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1262), .CK(clk), .RN(n5199),
.Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n5199),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n5213),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n5199),
.Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n5199),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n5213),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1254), .CK(clk), .RN(n5199),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n5199),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n5212),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1250), .CK(clk), .RN(n5199),
.Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n5200),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n5214),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1246), .CK(clk), .RN(n5200),
.Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n5200),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n5213),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1242), .CK(clk), .RN(n5200),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n5200),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n5162), .CK(clk), .RN(n5212),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1238), .CK(clk), .RN(n5200),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n5200),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n5161), .CK(clk), .RN(n5211),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1234), .CK(clk), .RN(n5200),
.Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n5200),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n5214),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1230), .CK(clk), .RN(n5200),
.Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n5201),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n5215),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1226), .CK(clk), .RN(n5201),
.Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n5201),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n5214),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1222), .CK(clk), .RN(n5201),
.Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n5201),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n5215),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1218), .CK(clk), .RN(n5201),
.Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n5201),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n5214),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1214), .CK(clk), .RN(n5201),
.Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n5201),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n5214),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1210), .CK(clk), .RN(n5201),
.Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n5202),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n5215),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1181), .CK(clk), .RN(
n5210), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n5121) );
CMPR42X1TS DP_OP_454J1_123_2743_U75 ( .A(DP_OP_454J1_123_2743_n240), .B(
DP_OP_454J1_123_2743_n227), .C(DP_OP_454J1_123_2743_n148), .D(
DP_OP_454J1_123_2743_n252), .ICI(DP_OP_454J1_123_2743_n214), .S(
DP_OP_454J1_123_2743_n145), .ICO(DP_OP_454J1_123_2743_n143), .CO(
DP_OP_454J1_123_2743_n144) );
CMPR42X1TS DP_OP_454J1_123_2743_U73 ( .A(DP_OP_454J1_123_2743_n143), .B(
DP_OP_454J1_123_2743_n251), .C(DP_OP_454J1_123_2743_n142), .D(
DP_OP_454J1_123_2743_n213), .ICI(DP_OP_454J1_123_2743_n156), .S(
DP_OP_454J1_123_2743_n140), .ICO(DP_OP_454J1_123_2743_n138), .CO(
DP_OP_454J1_123_2743_n139) );
CMPR42X1TS DP_OP_454J1_123_2743_U71 ( .A(DP_OP_454J1_123_2743_n212), .B(
DP_OP_454J1_123_2743_n137), .C(DP_OP_454J1_123_2743_n138), .D(
DP_OP_454J1_123_2743_n250), .ICI(DP_OP_454J1_123_2743_n200), .S(
DP_OP_454J1_123_2743_n135), .ICO(DP_OP_454J1_123_2743_n133), .CO(
DP_OP_454J1_123_2743_n134) );
CMPR42X1TS DP_OP_454J1_123_2743_U68 ( .A(DP_OP_454J1_123_2743_n133), .B(
DP_OP_454J1_123_2743_n249), .C(DP_OP_454J1_123_2743_n130), .D(
DP_OP_454J1_123_2743_n199), .ICI(DP_OP_454J1_123_2743_n155), .S(
DP_OP_454J1_123_2743_n128), .ICO(DP_OP_454J1_123_2743_n126), .CO(
DP_OP_454J1_123_2743_n127) );
CMPR42X1TS DP_OP_454J1_123_2743_U67 ( .A(DP_OP_454J1_123_2743_n223), .B(
DP_OP_454J1_123_2743_n210), .C(DP_OP_454J1_123_2743_n131), .D(
DP_OP_454J1_123_2743_n236), .ICI(DP_OP_454J1_123_2743_n129), .S(
DP_OP_454J1_123_2743_n125), .ICO(DP_OP_454J1_123_2743_n123), .CO(
DP_OP_454J1_123_2743_n124) );
CMPR42X1TS DP_OP_454J1_123_2743_U66 ( .A(DP_OP_454J1_123_2743_n198), .B(
DP_OP_454J1_123_2743_n248), .C(DP_OP_454J1_123_2743_n187), .D(
DP_OP_454J1_123_2743_n126), .ICI(DP_OP_454J1_123_2743_n125), .S(
DP_OP_454J1_123_2743_n122), .ICO(DP_OP_454J1_123_2743_n120), .CO(
DP_OP_454J1_123_2743_n121) );
CMPR42X1TS DP_OP_454J1_123_2743_U64 ( .A(DP_OP_454J1_123_2743_n123), .B(
DP_OP_454J1_123_2743_n235), .C(DP_OP_454J1_123_2743_n119), .D(
DP_OP_454J1_123_2743_n197), .ICI(DP_OP_454J1_123_2743_n124), .S(
DP_OP_454J1_123_2743_n117), .ICO(DP_OP_454J1_123_2743_n115), .CO(
DP_OP_454J1_123_2743_n116) );
CMPR42X1TS DP_OP_454J1_123_2743_U63 ( .A(DP_OP_454J1_123_2743_n120), .B(
DP_OP_454J1_123_2743_n117), .C(DP_OP_454J1_123_2743_n247), .D(
DP_OP_454J1_123_2743_n121), .ICI(DP_OP_454J1_123_2743_n186), .S(
DP_OP_454J1_123_2743_n114), .ICO(DP_OP_454J1_123_2743_n112), .CO(
DP_OP_454J1_123_2743_n113) );
CMPR42X1TS DP_OP_454J1_123_2743_U61 ( .A(DP_OP_454J1_123_2743_n196), .B(
DP_OP_454J1_123_2743_n111), .C(DP_OP_454J1_123_2743_n115), .D(
DP_OP_454J1_123_2743_n234), .ICI(DP_OP_454J1_123_2743_n116), .S(
DP_OP_454J1_123_2743_n109), .ICO(DP_OP_454J1_123_2743_n107), .CO(
DP_OP_454J1_123_2743_n108) );
CMPR42X1TS DP_OP_454J1_123_2743_U60 ( .A(DP_OP_454J1_123_2743_n246), .B(
DP_OP_454J1_123_2743_n172), .C(DP_OP_454J1_123_2743_n185), .D(
DP_OP_454J1_123_2743_n109), .ICI(DP_OP_454J1_123_2743_n112), .S(
DP_OP_454J1_123_2743_n106), .ICO(DP_OP_454J1_123_2743_n104), .CO(
DP_OP_454J1_123_2743_n105) );
CMPR42X1TS DP_OP_454J1_123_2743_U58 ( .A(DP_OP_454J1_123_2743_n195), .B(
DP_OP_454J1_123_2743_n245), .C(DP_OP_454J1_123_2743_n103), .D(
DP_OP_454J1_123_2743_n107), .ICI(DP_OP_454J1_123_2743_n233), .S(
DP_OP_454J1_123_2743_n101), .ICO(DP_OP_454J1_123_2743_n99), .CO(
DP_OP_454J1_123_2743_n100) );
CMPR42X1TS DP_OP_454J1_123_2743_U57 ( .A(DP_OP_454J1_123_2743_n108), .B(
DP_OP_454J1_123_2743_n171), .C(DP_OP_454J1_123_2743_n184), .D(
DP_OP_454J1_123_2743_n101), .ICI(DP_OP_454J1_123_2743_n104), .S(
DP_OP_454J1_123_2743_n98), .ICO(DP_OP_454J1_123_2743_n96), .CO(
DP_OP_454J1_123_2743_n97) );
CMPR42X1TS DP_OP_454J1_123_2743_U54 ( .A(DP_OP_454J1_123_2743_n219), .B(
DP_OP_454J1_123_2743_n102), .C(DP_OP_454J1_123_2743_n94), .D(
DP_OP_454J1_123_2743_n99), .ICI(DP_OP_454J1_123_2743_n232), .S(
DP_OP_454J1_123_2743_n92), .ICO(DP_OP_454J1_123_2743_n90), .CO(
DP_OP_454J1_123_2743_n91) );
CMPR42X1TS DP_OP_454J1_123_2743_U53 ( .A(DP_OP_454J1_123_2743_n170), .B(
DP_OP_454J1_123_2743_n183), .C(DP_OP_454J1_123_2743_n100), .D(
DP_OP_454J1_123_2743_n96), .ICI(DP_OP_454J1_123_2743_n92), .S(
DP_OP_454J1_123_2743_n89), .ICO(DP_OP_454J1_123_2743_n87), .CO(
DP_OP_454J1_123_2743_n88) );
CMPR42X1TS DP_OP_454J1_123_2743_U50 ( .A(DP_OP_454J1_123_2743_n231), .B(
DP_OP_454J1_123_2743_n93), .C(DP_OP_454J1_123_2743_n84), .D(
DP_OP_454J1_123_2743_n90), .ICI(DP_OP_454J1_123_2743_n218), .S(
DP_OP_454J1_123_2743_n82), .ICO(DP_OP_454J1_123_2743_n80), .CO(
DP_OP_454J1_123_2743_n81) );
CMPR42X1TS DP_OP_454J1_123_2743_U49 ( .A(DP_OP_454J1_123_2743_n169), .B(
DP_OP_454J1_123_2743_n182), .C(DP_OP_454J1_123_2743_n91), .D(
DP_OP_454J1_123_2743_n87), .ICI(DP_OP_454J1_123_2743_n82), .S(
DP_OP_454J1_123_2743_n79), .ICO(DP_OP_454J1_123_2743_n77), .CO(
DP_OP_454J1_123_2743_n78) );
CMPR42X1TS DP_OP_454J1_123_2743_U47 ( .A(DP_OP_454J1_123_2743_n204), .B(
DP_OP_454J1_123_2743_n83), .C(DP_OP_454J1_123_2743_n76), .D(
DP_OP_454J1_123_2743_n80), .ICI(DP_OP_454J1_123_2743_n217), .S(
DP_OP_454J1_123_2743_n74), .ICO(DP_OP_454J1_123_2743_n72), .CO(
DP_OP_454J1_123_2743_n73) );
CMPR42X1TS DP_OP_454J1_123_2743_U46 ( .A(DP_OP_454J1_123_2743_n168), .B(
DP_OP_454J1_123_2743_n181), .C(DP_OP_454J1_123_2743_n81), .D(
DP_OP_454J1_123_2743_n74), .ICI(DP_OP_454J1_123_2743_n77), .S(
DP_OP_454J1_123_2743_n71), .ICO(DP_OP_454J1_123_2743_n69), .CO(
DP_OP_454J1_123_2743_n70) );
CMPR42X1TS DP_OP_454J1_123_2743_U44 ( .A(DP_OP_454J1_123_2743_n68), .B(
DP_OP_454J1_123_2743_n216), .C(DP_OP_454J1_123_2743_n75), .D(
DP_OP_454J1_123_2743_n72), .ICI(DP_OP_454J1_123_2743_n203), .S(
DP_OP_454J1_123_2743_n66), .ICO(DP_OP_454J1_123_2743_n64), .CO(
DP_OP_454J1_123_2743_n65) );
CMPR42X1TS DP_OP_454J1_123_2743_U43 ( .A(DP_OP_454J1_123_2743_n167), .B(
DP_OP_454J1_123_2743_n180), .C(DP_OP_454J1_123_2743_n73), .D(
DP_OP_454J1_123_2743_n66), .ICI(DP_OP_454J1_123_2743_n69), .S(
DP_OP_454J1_123_2743_n63), .ICO(DP_OP_454J1_123_2743_n61), .CO(
DP_OP_454J1_123_2743_n62) );
CMPR42X1TS DP_OP_454J1_123_2743_U42 ( .A(n2233), .B(DP_OP_454J1_123_2743_n67), .C(DP_OP_454J1_123_2743_n191), .D(DP_OP_454J1_123_2743_n64), .ICI(
DP_OP_454J1_123_2743_n202), .S(DP_OP_454J1_123_2743_n60), .ICO(
DP_OP_454J1_123_2743_n58), .CO(DP_OP_454J1_123_2743_n59) );
CMPR42X1TS DP_OP_454J1_123_2743_U41 ( .A(DP_OP_454J1_123_2743_n166), .B(
DP_OP_454J1_123_2743_n179), .C(DP_OP_454J1_123_2743_n65), .D(
DP_OP_454J1_123_2743_n60), .ICI(DP_OP_454J1_123_2743_n61), .S(
DP_OP_454J1_123_2743_n57), .ICO(DP_OP_454J1_123_2743_n55), .CO(
DP_OP_454J1_123_2743_n56) );
CMPR42X1TS DP_OP_454J1_123_2743_U38 ( .A(DP_OP_454J1_123_2743_n165), .B(
DP_OP_454J1_123_2743_n178), .C(DP_OP_454J1_123_2743_n52), .D(
DP_OP_454J1_123_2743_n59), .ICI(DP_OP_454J1_123_2743_n55), .S(
DP_OP_454J1_123_2743_n50), .ICO(DP_OP_454J1_123_2743_n48), .CO(
DP_OP_454J1_123_2743_n49) );
CMPR42X1TS DP_OP_454J1_123_2743_U36 ( .A(DP_OP_454J1_123_2743_n164), .B(
DP_OP_454J1_123_2743_n177), .C(DP_OP_454J1_123_2743_n51), .D(
DP_OP_454J1_123_2743_n47), .ICI(DP_OP_454J1_123_2743_n48), .S(
DP_OP_454J1_123_2743_n45), .ICO(DP_OP_454J1_123_2743_n43), .CO(
DP_OP_454J1_123_2743_n44) );
CMPR42X1TS DP_OP_454J1_123_2743_U34 ( .A(DP_OP_454J1_123_2743_n42), .B(
DP_OP_454J1_123_2743_n163), .C(DP_OP_454J1_123_2743_n176), .D(
DP_OP_454J1_123_2743_n46), .ICI(DP_OP_454J1_123_2743_n43), .S(
DP_OP_454J1_123_2743_n40), .ICO(DP_OP_454J1_123_2743_n38), .CO(
DP_OP_454J1_123_2743_n39) );
CMPR42X1TS DP_OP_454J1_123_2743_U33 ( .A(DP_OP_454J1_123_2743_n188), .B(
DP_OP_454J1_123_2743_n41), .C(DP_OP_454J1_123_2743_n162), .D(
DP_OP_454J1_123_2743_n175), .ICI(DP_OP_454J1_123_2743_n38), .S(
DP_OP_454J1_123_2743_n37), .ICO(DP_OP_454J1_123_2743_n35), .CO(
DP_OP_454J1_123_2743_n36) );
CMPR42X1TS mult_x_254_U69 ( .A(mult_x_254_n196), .B(mult_x_254_n232), .C(
mult_x_254_n220), .D(mult_x_254_n208), .ICI(mult_x_254_n136), .S(
mult_x_254_n133), .ICO(mult_x_254_n131), .CO(mult_x_254_n132) );
CMPR42X1TS mult_x_254_U67 ( .A(mult_x_254_n219), .B(mult_x_254_n195), .C(
mult_x_254_n207), .D(mult_x_254_n131), .ICI(mult_x_254_n130), .S(
mult_x_254_n128), .ICO(mult_x_254_n126), .CO(mult_x_254_n127) );
CMPR42X1TS mult_x_254_U65 ( .A(mult_x_254_n206), .B(mult_x_254_n194), .C(
mult_x_254_n129), .D(mult_x_254_n126), .ICI(mult_x_254_n125), .S(
mult_x_254_n123), .ICO(mult_x_254_n121), .CO(mult_x_254_n122) );
CMPR42X1TS mult_x_254_U62 ( .A(mult_x_254_n205), .B(mult_x_254_n124), .C(
mult_x_254_n120), .D(mult_x_254_n118), .ICI(mult_x_254_n121), .S(
mult_x_254_n116), .ICO(mult_x_254_n114), .CO(mult_x_254_n115) );
CMPR42X1TS mult_x_254_U61 ( .A(mult_x_254_n168), .B(mult_x_254_n228), .C(
mult_x_254_n216), .D(mult_x_254_n204), .ICI(mult_x_254_n180), .S(
mult_x_254_n113), .ICO(mult_x_254_n111), .CO(mult_x_254_n112) );
CMPR42X1TS mult_x_254_U60 ( .A(mult_x_254_n192), .B(mult_x_254_n119), .C(
mult_x_254_n117), .D(mult_x_254_n114), .ICI(mult_x_254_n113), .S(
mult_x_254_n110), .ICO(mult_x_254_n108), .CO(mult_x_254_n109) );
CMPR42X1TS mult_x_254_U58 ( .A(mult_x_254_n215), .B(mult_x_254_n167), .C(
mult_x_254_n203), .D(mult_x_254_n179), .ICI(mult_x_254_n107), .S(
mult_x_254_n105), .ICO(mult_x_254_n103), .CO(mult_x_254_n104) );
CMPR42X1TS mult_x_254_U57 ( .A(mult_x_254_n191), .B(mult_x_254_n111), .C(
mult_x_254_n108), .D(mult_x_254_n112), .ICI(mult_x_254_n105), .S(
mult_x_254_n102), .ICO(mult_x_254_n100), .CO(mult_x_254_n101) );
CMPR42X1TS mult_x_254_U55 ( .A(mult_x_254_n202), .B(mult_x_254_n166), .C(
mult_x_254_n190), .D(mult_x_254_n178), .ICI(mult_x_254_n99), .S(
mult_x_254_n97), .ICO(mult_x_254_n95), .CO(mult_x_254_n96) );
CMPR42X1TS mult_x_254_U54 ( .A(mult_x_254_n106), .B(mult_x_254_n103), .C(
mult_x_254_n104), .D(mult_x_254_n97), .ICI(mult_x_254_n100), .S(
mult_x_254_n94), .ICO(mult_x_254_n92), .CO(mult_x_254_n93) );
CMPR42X1TS mult_x_254_U51 ( .A(mult_x_254_n189), .B(mult_x_254_n165), .C(
mult_x_254_n213), .D(mult_x_254_n225), .ICI(mult_x_254_n90), .S(
mult_x_254_n88), .ICO(mult_x_254_n86), .CO(mult_x_254_n87) );
CMPR42X1TS mult_x_254_U50 ( .A(mult_x_254_n95), .B(mult_x_254_n98), .C(
mult_x_254_n96), .D(mult_x_254_n88), .ICI(mult_x_254_n92), .S(
mult_x_254_n85), .ICO(mult_x_254_n83), .CO(mult_x_254_n84) );
CMPR42X1TS mult_x_254_U47 ( .A(mult_x_254_n176), .B(mult_x_254_n212), .C(
mult_x_254_n200), .D(mult_x_254_n164), .ICI(mult_x_254_n89), .S(
mult_x_254_n78), .ICO(mult_x_254_n76), .CO(mult_x_254_n77) );
CMPR42X1TS mult_x_254_U46 ( .A(mult_x_254_n86), .B(mult_x_254_n80), .C(
mult_x_254_n87), .D(mult_x_254_n78), .ICI(mult_x_254_n83), .S(
mult_x_254_n75), .ICO(mult_x_254_n73), .CO(mult_x_254_n74) );
CMPR42X1TS mult_x_254_U44 ( .A(mult_x_254_n175), .B(mult_x_254_n163), .C(
mult_x_254_n199), .D(mult_x_254_n211), .ICI(mult_x_254_n72), .S(
mult_x_254_n70), .ICO(mult_x_254_n68), .CO(mult_x_254_n69) );
CMPR42X1TS mult_x_254_U43 ( .A(mult_x_254_n76), .B(mult_x_254_n79), .C(
mult_x_254_n77), .D(mult_x_254_n70), .ICI(mult_x_254_n73), .S(
mult_x_254_n67), .ICO(mult_x_254_n65), .CO(mult_x_254_n66) );
CMPR42X1TS mult_x_254_U41 ( .A(mult_x_254_n64), .B(mult_x_254_n174), .C(
mult_x_254_n186), .D(mult_x_254_n162), .ICI(mult_x_254_n198), .S(
mult_x_254_n62), .ICO(mult_x_254_n60), .CO(mult_x_254_n61) );
CMPR42X1TS mult_x_254_U40 ( .A(mult_x_254_n68), .B(mult_x_254_n71), .C(
mult_x_254_n69), .D(mult_x_254_n62), .ICI(mult_x_254_n65), .S(
mult_x_254_n59), .ICO(mult_x_254_n57), .CO(mult_x_254_n58) );
CMPR42X1TS mult_x_254_U39 ( .A(mult_x_254_n63), .B(mult_x_254_n151), .C(
mult_x_254_n185), .D(mult_x_254_n173), .ICI(mult_x_254_n161), .S(
mult_x_254_n56), .ICO(mult_x_254_n54), .CO(mult_x_254_n55) );
CMPR42X1TS mult_x_254_U38 ( .A(mult_x_254_n197), .B(mult_x_254_n60), .C(
mult_x_254_n61), .D(mult_x_254_n56), .ICI(mult_x_254_n57), .S(
mult_x_254_n53), .ICO(mult_x_254_n51), .CO(mult_x_254_n52) );
CMPR42X1TS mult_x_254_U35 ( .A(mult_x_254_n160), .B(mult_x_254_n54), .C(
mult_x_254_n48), .D(mult_x_254_n55), .ICI(mult_x_254_n51), .S(
mult_x_254_n46), .ICO(mult_x_254_n44), .CO(mult_x_254_n45) );
CMPR42X1TS mult_x_254_U33 ( .A(mult_x_254_n159), .B(n2230), .C(
mult_x_254_n43), .D(mult_x_254_n47), .ICI(mult_x_254_n44), .S(
mult_x_254_n41), .ICO(mult_x_254_n39), .CO(mult_x_254_n40) );
CMPR42X1TS mult_x_254_U31 ( .A(mult_x_254_n38), .B(mult_x_254_n170), .C(
mult_x_254_n158), .D(mult_x_254_n42), .ICI(mult_x_254_n39), .S(
mult_x_254_n36), .ICO(mult_x_254_n34), .CO(mult_x_254_n35) );
CMPR42X1TS mult_x_254_U30 ( .A(mult_x_254_n37), .B(mult_x_254_n149), .C(
mult_x_254_n157), .D(mult_x_254_n169), .ICI(mult_x_254_n34), .S(
mult_x_254_n33), .ICO(mult_x_254_n31), .CO(mult_x_254_n32) );
CMPR42X1TS mult_x_219_U69 ( .A(mult_x_219_n190), .B(mult_x_219_n226), .C(
mult_x_219_n214), .D(mult_x_219_n202), .ICI(mult_x_219_n136), .S(
mult_x_219_n133), .ICO(mult_x_219_n131), .CO(mult_x_219_n132) );
CMPR42X1TS mult_x_219_U67 ( .A(mult_x_219_n213), .B(mult_x_219_n189), .C(
mult_x_219_n201), .D(mult_x_219_n131), .ICI(mult_x_219_n130), .S(
mult_x_219_n128), .ICO(mult_x_219_n126), .CO(mult_x_219_n127) );
CMPR42X1TS mult_x_219_U65 ( .A(mult_x_219_n200), .B(mult_x_219_n188), .C(
n2351), .D(mult_x_219_n126), .ICI(mult_x_219_n125), .S(mult_x_219_n123), .ICO(mult_x_219_n121), .CO(mult_x_219_n122) );
CMPR42X1TS mult_x_219_U62 ( .A(mult_x_219_n199), .B(mult_x_219_n124), .C(
mult_x_219_n120), .D(mult_x_219_n118), .ICI(mult_x_219_n121), .S(
mult_x_219_n116), .ICO(mult_x_219_n114), .CO(mult_x_219_n115) );
CMPR42X1TS mult_x_219_U61 ( .A(mult_x_219_n162), .B(mult_x_219_n222), .C(
mult_x_219_n210), .D(mult_x_219_n198), .ICI(mult_x_219_n174), .S(
mult_x_219_n113), .ICO(mult_x_219_n111), .CO(mult_x_219_n112) );
CMPR42X1TS mult_x_219_U60 ( .A(mult_x_219_n186), .B(mult_x_219_n119), .C(
mult_x_219_n117), .D(mult_x_219_n114), .ICI(mult_x_219_n113), .S(
mult_x_219_n110), .ICO(mult_x_219_n108), .CO(mult_x_219_n109) );
CMPR42X1TS mult_x_219_U58 ( .A(mult_x_219_n209), .B(mult_x_219_n161), .C(
mult_x_219_n197), .D(mult_x_219_n173), .ICI(mult_x_219_n107), .S(
mult_x_219_n105), .ICO(mult_x_219_n103), .CO(mult_x_219_n104) );
CMPR42X1TS mult_x_219_U57 ( .A(mult_x_219_n185), .B(mult_x_219_n111), .C(
mult_x_219_n108), .D(mult_x_219_n112), .ICI(mult_x_219_n105), .S(
mult_x_219_n102), .ICO(mult_x_219_n100), .CO(mult_x_219_n101) );
CMPR42X1TS mult_x_219_U55 ( .A(mult_x_219_n196), .B(mult_x_219_n160), .C(
mult_x_219_n184), .D(mult_x_219_n172), .ICI(mult_x_219_n99), .S(
mult_x_219_n97), .ICO(mult_x_219_n95), .CO(mult_x_219_n96) );
CMPR42X1TS mult_x_219_U54 ( .A(mult_x_219_n106), .B(mult_x_219_n103), .C(
mult_x_219_n104), .D(mult_x_219_n97), .ICI(mult_x_219_n100), .S(
mult_x_219_n94), .ICO(mult_x_219_n92), .CO(mult_x_219_n93) );
CMPR42X1TS mult_x_219_U51 ( .A(mult_x_219_n183), .B(mult_x_219_n159), .C(
mult_x_219_n207), .D(n4999), .ICI(mult_x_219_n90), .S(mult_x_219_n88),
.ICO(mult_x_219_n86), .CO(mult_x_219_n87) );
CMPR42X1TS mult_x_219_U50 ( .A(mult_x_219_n95), .B(mult_x_219_n98), .C(
mult_x_219_n96), .D(mult_x_219_n88), .ICI(mult_x_219_n92), .S(
mult_x_219_n85), .ICO(mult_x_219_n83), .CO(mult_x_219_n84) );
CMPR42X1TS mult_x_219_U47 ( .A(mult_x_219_n170), .B(mult_x_219_n206), .C(
mult_x_219_n194), .D(mult_x_219_n158), .ICI(mult_x_219_n89), .S(
mult_x_219_n78), .ICO(mult_x_219_n76), .CO(mult_x_219_n77) );
CMPR42X1TS mult_x_219_U46 ( .A(mult_x_219_n86), .B(mult_x_219_n80), .C(
mult_x_219_n87), .D(mult_x_219_n78), .ICI(mult_x_219_n83), .S(
mult_x_219_n75), .ICO(mult_x_219_n73), .CO(mult_x_219_n74) );
CMPR42X1TS mult_x_219_U44 ( .A(mult_x_219_n169), .B(mult_x_219_n157), .C(
mult_x_219_n193), .D(mult_x_219_n205), .ICI(mult_x_219_n72), .S(
mult_x_219_n70), .ICO(mult_x_219_n68), .CO(mult_x_219_n69) );
CMPR42X1TS mult_x_219_U43 ( .A(mult_x_219_n76), .B(mult_x_219_n79), .C(
mult_x_219_n77), .D(mult_x_219_n70), .ICI(mult_x_219_n73), .S(
mult_x_219_n67), .ICO(mult_x_219_n65), .CO(mult_x_219_n66) );
CMPR42X1TS mult_x_219_U41 ( .A(n5023), .B(mult_x_219_n168), .C(
mult_x_219_n180), .D(mult_x_219_n156), .ICI(mult_x_219_n192), .S(
mult_x_219_n62), .ICO(mult_x_219_n60), .CO(mult_x_219_n61) );
CMPR42X1TS mult_x_219_U40 ( .A(mult_x_219_n68), .B(mult_x_219_n71), .C(
mult_x_219_n69), .D(mult_x_219_n62), .ICI(mult_x_219_n65), .S(
mult_x_219_n59), .ICO(mult_x_219_n57), .CO(mult_x_219_n58) );
CMPR42X1TS mult_x_219_U39 ( .A(n2243), .B(n2245), .C(mult_x_219_n179), .D(
mult_x_219_n167), .ICI(mult_x_219_n155), .S(mult_x_219_n56), .ICO(
mult_x_219_n54), .CO(mult_x_219_n55) );
CMPR42X1TS mult_x_219_U38 ( .A(mult_x_219_n191), .B(mult_x_219_n60), .C(
mult_x_219_n61), .D(mult_x_219_n56), .ICI(mult_x_219_n57), .S(
mult_x_219_n53), .ICO(mult_x_219_n51), .CO(mult_x_219_n52) );
CMPR42X1TS mult_x_219_U35 ( .A(mult_x_219_n154), .B(mult_x_219_n54), .C(
mult_x_219_n48), .D(mult_x_219_n55), .ICI(mult_x_219_n51), .S(
mult_x_219_n46), .ICO(mult_x_219_n44), .CO(mult_x_219_n45) );
CMPR42X1TS mult_x_219_U33 ( .A(mult_x_219_n153), .B(mult_x_219_n177), .C(
mult_x_219_n43), .D(mult_x_219_n47), .ICI(mult_x_219_n44), .S(
mult_x_219_n41), .ICO(mult_x_219_n39), .CO(mult_x_219_n40) );
CMPR42X1TS mult_x_219_U31 ( .A(n5022), .B(mult_x_219_n164), .C(
mult_x_219_n152), .D(mult_x_219_n42), .ICI(mult_x_219_n39), .S(
mult_x_219_n36), .ICO(mult_x_219_n34), .CO(mult_x_219_n35) );
CMPR42X1TS mult_x_219_U30 ( .A(n2242), .B(FPMULT_Op_MY[21]), .C(
mult_x_219_n151), .D(mult_x_219_n163), .ICI(mult_x_219_n34), .S(
mult_x_219_n33), .ICO(mult_x_219_n31), .CO(mult_x_219_n32) );
CMPR32X2TS DP_OP_234J1_127_8543_U9 ( .A(DP_OP_234J1_127_8543_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J1_127_8543_n9), .CO(
DP_OP_234J1_127_8543_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J1_127_8543_U8 ( .A(DP_OP_234J1_127_8543_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J1_127_8543_n8), .CO(
DP_OP_234J1_127_8543_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J1_127_8543_U7 ( .A(DP_OP_234J1_127_8543_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J1_127_8543_n7), .CO(
DP_OP_234J1_127_8543_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J1_127_8543_U6 ( .A(DP_OP_234J1_127_8543_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J1_127_8543_n6), .CO(
DP_OP_234J1_127_8543_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J1_127_8543_U5 ( .A(DP_OP_234J1_127_8543_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J1_127_8543_n5), .CO(
DP_OP_234J1_127_8543_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J1_127_8543_U4 ( .A(DP_OP_234J1_127_8543_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J1_127_8543_n4), .CO(
DP_OP_234J1_127_8543_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J1_127_8543_U3 ( .A(DP_OP_234J1_127_8543_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J1_127_8543_n3), .CO(
DP_OP_234J1_127_8543_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS intadd_7_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n5006), .C(intadd_7_CI), .CO(intadd_7_n3), .S(intadd_7_SUM_0_) );
CMPR32X2TS intadd_7_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n4991), .C(intadd_7_n3), .CO(intadd_7_n2), .S(intadd_7_SUM_1_) );
CMPR32X2TS intadd_8_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n5054), .C(intadd_8_n2), .CO(intadd_8_n1), .S(intadd_8_SUM_2_) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_0_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N0), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[0]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_1_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N1), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_2_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N2), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_3_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N3), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_4_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N4), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_5_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N5), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_6_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N6), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_7_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N7), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_8_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N8), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_9_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N9), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_10_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N10), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_11_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N11), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_12_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N12), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[12]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_13_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N13), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[13]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_14_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N14), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[14]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_15_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N15), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[15]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_16_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N16), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[16]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_17_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N17), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[17]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_18_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N18), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[18]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_19_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N19), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[19]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_20_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N20), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[20]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_21_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N21), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[21]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_22_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N22), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[22]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_Data_S_o_reg_23_ ( .D(
FPMULT_Sgf_operation_EVEN1_left_N23), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[23]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_0_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N0), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[0]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_1_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N1), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_2_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N2), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_3_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N3), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_4_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N4), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_5_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N5), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_6_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N6), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_7_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N7), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_8_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N8), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_9_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N9), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_10_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N10), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_11_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N11), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_12_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N12), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[12]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_13_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N13), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[13]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_14_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N14), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[14]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_15_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N15), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[15]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_16_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N16), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[16]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_17_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N17), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[17]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_18_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N18), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[18]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_19_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N19), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[19]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_20_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N20), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[20]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_21_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N21), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[21]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_22_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N22), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[22]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_23_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N23), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[23]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_24_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N24), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[24]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_Data_S_o_reg_25_ ( .D(
FPMULT_Sgf_operation_EVEN1_middle_N25), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_middle[25]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_0_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N0), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[0]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_1_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N1), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_2_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N2), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_3_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N3), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_4_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N4), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_5_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N5), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_6_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N6), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_7_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N7), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_8_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N8), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_9_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N9), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_10_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N10), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_11_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N11), .CK(1'b0), .Q(
FPMULT_Sgf_operation_Result[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_12_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N12), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[12]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_13_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N13), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[13]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_14_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N14), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[14]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_15_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N15), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[15]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_16_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N16), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[16]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_17_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N17), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[17]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_18_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N18), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[18]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_19_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N19), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[19]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_20_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N20), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[20]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_21_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N21), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[21]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_22_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N22), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[22]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_Data_S_o_reg_23_ ( .D(
FPMULT_Sgf_operation_EVEN1_right_N23), .CK(1'b0), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1688), .CK(clk),
.RN(n5277), .Q(FPMULT_Op_MX[29]), .QN(n5138) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n1554), .CK(clk),
.RN(n5232), .Q(FPMULT_P_Sgf[24]), .QN(n5134) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1604), .CK(clk),
.RN(n5274), .Q(FPMULT_Add_result[17]), .QN(n5133) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1529), .CK(clk), .RN(n5267), .Q(
FPMULT_FSM_selector_C), .QN(n5132) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1859), .CK(clk), .RN(
n5255), .Q(FPSENCOS_d_ff2_Y[26]), .QN(n5128) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1861), .CK(clk), .RN(
n5256), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n5126) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1855), .CK(clk), .RN(
n5252), .QN(n5125) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1525), .CK(
clk), .RN(n5267), .Q(FPMULT_Sgf_normalized_result[19]), .QN(n5122) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1513), .CK(
clk), .RN(n5266), .Q(FPMULT_Sgf_normalized_result[7]), .QN(n5120) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1516), .CK(
clk), .RN(n5266), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n5119) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1512), .CK(
clk), .RN(n5266), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n5093) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1858), .CK(clk), .RN(
n5254), .Q(FPSENCOS_d_ff2_Y[27]), .QN(n5092) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1669), .CK(clk),
.RN(n5276), .Q(FPMULT_Op_MX[10]), .QN(n5090) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1857), .CK(clk), .RN(
n5253), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n5089) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1856), .CK(clk), .RN(
n5252), .QN(n5088) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1510), .CK(
clk), .RN(n5265), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n5081) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1955), .CK(clk), .RN(
n5253), .Q(FPSENCOS_d_ff2_X[28]), .QN(n5078) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1667), .CK(clk),
.RN(n5275), .Q(FPMULT_Op_MX[8]), .QN(n5077) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n1661), .CK(clk),
.RN(n5275), .Q(FPMULT_Op_MX[2]), .QN(n5076) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1665), .CK(clk),
.RN(n5275), .Q(FPMULT_Op_MX[6]), .QN(n5075) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n1673), .CK(clk),
.RN(n5276), .Q(FPMULT_Op_MX[14]), .QN(n5074) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2081), .CK(clk), .RN(n5257),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n5072) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1628), .CK(clk),
.RN(n5269), .Q(FPMULT_Op_MY[1]), .QN(n5065) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1679), .CK(clk),
.RN(n5277), .Q(FPMULT_Op_MX[20]), .QN(n5063) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1677), .CK(clk),
.RN(n5276), .Q(FPMULT_Op_MX[18]), .QN(n5058) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1675), .CK(clk),
.RN(n5276), .Q(FPMULT_Op_MX[16]), .QN(n5057) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2139), .CK(clk), .RN(n5246),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n5054) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2137), .CK(clk), .RN(n5245),
.Q(FPSENCOS_cont_var_out[1]), .QN(n5049) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1633), .CK(clk),
.RN(n5269), .Q(FPMULT_Op_MY[6]), .QN(n5048) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1635), .CK(clk),
.RN(n5270), .Q(FPMULT_Op_MY[8]), .QN(n5047) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1630), .CK(clk),
.RN(n5269), .Q(FPMULT_Op_MY[3]), .QN(n5046) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1631), .CK(clk),
.RN(n5269), .Q(FPMULT_Op_MY[4]), .QN(n5045) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1634), .CK(clk),
.RN(n5269), .Q(FPMULT_Op_MY[7]), .QN(n5044) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1637), .CK(clk),
.RN(n5270), .Q(FPMULT_Op_MY[10]), .QN(n5043) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1632), .CK(clk),
.RN(n5269), .Q(FPMULT_Op_MY[5]), .QN(n5042) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1636), .CK(clk),
.RN(n5270), .Q(FPMULT_Op_MY[9]), .QN(n5041) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1511), .CK(
clk), .RN(n5265), .Q(FPMULT_Sgf_normalized_result[5]), .QN(n5037) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1509), .CK(
clk), .RN(n5265), .Q(FPMULT_Sgf_normalized_result[3]), .QN(n5035) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1690), .CK(clk), .RN(n5278), .Q(
FPMULT_FSM_selector_A), .QN(n5083) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1692), .CK(clk), .RN(n5231),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n5033) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1623), .CK(clk), .RN(n5268), .Q(
FPMULT_FSM_selector_B[1]), .QN(n5032) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n1640), .CK(clk),
.RN(n5270), .Q(FPMULT_Op_MY[13]), .QN(n5021) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1351), .CK(clk), .RN(
n5207), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n5008) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1670), .CK(clk),
.RN(n5276), .Q(FPMULT_Op_MX[11]), .QN(n5170) );
DFFRX1TS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1626), .CK(
clk), .RN(n5269), .Q(FPMULT_zero_flag), .QN(n5005) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1663), .CK(clk),
.RN(n5275), .Q(FPMULT_Op_MX[4]), .QN(n5002) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1596), .CK(clk), .RN(
n5268), .Q(FPMULT_exp_oper_result[8]), .QN(n5000) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1862), .CK(clk), .RN(
n5257), .QN(n4996) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1514), .CK(
clk), .RN(n5266), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n4994) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2140), .CK(clk), .RN(n5246),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n4991) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1693), .CK(clk), .RN(n5241),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n4989) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2138), .CK(clk), .RN(n5245),
.Q(FPSENCOS_cont_var_out[0]), .QN(n4988) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n5247), .Q(NaN_flag)
);
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1587), .CK(clk), .RN(
n5265), .Q(underflow_flag_mult), .QN(n5104) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1691), .CK(clk), .RN(n5235),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n4992) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1694), .CK(clk), .RN(n2609),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n5052) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n5246), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n5009) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2141), .CK(clk), .RN(n5246),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n5006) );
CMPR32X2TS intadd_7_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n5054), .C(intadd_7_n2), .CO(intadd_7_n1), .S(intadd_7_SUM_2_) );
CMPR32X2TS intadd_0_U26 ( .A(FPMULT_Sgf_operation_Result[0]), .B(
intadd_0_B_0_), .C(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .CO(
intadd_0_n25), .S(intadd_0_SUM_0_) );
CMPR32X2TS intadd_0_U25 ( .A(FPMULT_Sgf_operation_Result[1]), .B(
intadd_0_B_1_), .C(intadd_0_n25), .CO(intadd_0_n24), .S(
intadd_0_SUM_1_) );
CMPR32X2TS intadd_0_U24 ( .A(intadd_0_A_2_), .B(intadd_0_B_2_), .C(
intadd_0_n24), .CO(intadd_0_n23), .S(intadd_0_SUM_2_) );
CMPR32X2TS intadd_0_U23 ( .A(intadd_0_A_3_), .B(intadd_0_B_3_), .C(
intadd_0_n23), .CO(intadd_0_n22), .S(intadd_0_SUM_3_) );
CMPR32X2TS intadd_0_U22 ( .A(intadd_0_A_4_), .B(intadd_0_B_4_), .C(
intadd_0_n22), .CO(intadd_0_n21), .S(intadd_0_SUM_4_) );
CMPR32X2TS intadd_0_U21 ( .A(intadd_0_A_5_), .B(intadd_0_B_5_), .C(
intadd_0_n21), .CO(intadd_0_n20), .S(intadd_0_SUM_5_) );
CMPR32X2TS intadd_0_U20 ( .A(intadd_0_A_6_), .B(intadd_0_B_6_), .C(
intadd_0_n20), .CO(intadd_0_n19), .S(intadd_0_SUM_6_) );
CMPR32X2TS intadd_0_U19 ( .A(intadd_0_A_7_), .B(intadd_0_B_7_), .C(
intadd_0_n19), .CO(intadd_0_n18), .S(intadd_0_SUM_7_) );
CMPR32X2TS intadd_0_U18 ( .A(intadd_0_A_8_), .B(intadd_0_B_8_), .C(
intadd_0_n18), .CO(intadd_0_n17), .S(intadd_0_SUM_8_) );
CMPR32X2TS intadd_0_U17 ( .A(intadd_0_A_9_), .B(intadd_0_B_9_), .C(
intadd_0_n17), .CO(intadd_0_n16), .S(intadd_0_SUM_9_) );
CMPR32X2TS intadd_0_U16 ( .A(intadd_0_A_10_), .B(intadd_0_B_10_), .C(
intadd_0_n16), .CO(intadd_0_n15), .S(intadd_0_SUM_10_) );
CMPR32X2TS intadd_0_U15 ( .A(intadd_0_A_11_), .B(intadd_0_B_11_), .C(
intadd_0_n15), .CO(intadd_0_n14), .S(intadd_0_SUM_11_) );
CMPR32X2TS intadd_0_U14 ( .A(intadd_0_A_12_), .B(intadd_0_B_12_), .C(
intadd_0_n14), .CO(intadd_0_n13), .S(intadd_0_SUM_12_) );
CMPR32X2TS intadd_0_U13 ( .A(intadd_0_A_13_), .B(intadd_0_B_13_), .C(
intadd_0_n13), .CO(intadd_0_n12), .S(intadd_0_SUM_13_) );
CMPR32X2TS intadd_0_U12 ( .A(intadd_0_A_14_), .B(intadd_0_B_14_), .C(
intadd_0_n12), .CO(intadd_0_n11), .S(intadd_0_SUM_14_) );
CMPR32X2TS intadd_0_U11 ( .A(intadd_0_A_15_), .B(intadd_0_B_15_), .C(
intadd_0_n11), .CO(intadd_0_n10), .S(intadd_0_SUM_15_) );
CMPR32X2TS intadd_0_U10 ( .A(intadd_0_A_16_), .B(intadd_0_B_16_), .C(
intadd_0_n10), .CO(intadd_0_n9), .S(intadd_0_SUM_16_) );
CMPR32X2TS intadd_0_U9 ( .A(intadd_0_A_17_), .B(intadd_0_B_17_), .C(
intadd_0_n9), .CO(intadd_0_n8), .S(intadd_0_SUM_17_) );
CMPR32X2TS intadd_0_U8 ( .A(intadd_0_A_18_), .B(intadd_0_B_18_), .C(
intadd_0_n8), .CO(intadd_0_n7), .S(intadd_0_SUM_18_) );
CMPR32X2TS intadd_0_U7 ( .A(intadd_0_A_19_), .B(intadd_0_B_19_), .C(
intadd_0_n7), .CO(intadd_0_n6), .S(intadd_0_SUM_19_) );
CMPR32X2TS intadd_0_U6 ( .A(intadd_0_A_20_), .B(intadd_0_B_20_), .C(
intadd_0_n6), .CO(intadd_0_n5), .S(intadd_0_SUM_20_) );
CMPR32X2TS intadd_0_U5 ( .A(intadd_0_A_21_), .B(intadd_0_B_21_), .C(
intadd_0_n5), .CO(intadd_0_n4), .S(intadd_0_SUM_21_) );
CMPR32X2TS intadd_0_U4 ( .A(intadd_0_A_22_), .B(intadd_0_B_22_), .C(
intadd_0_n4), .CO(intadd_0_n3), .S(intadd_0_SUM_22_) );
CMPR32X2TS intadd_0_U3 ( .A(intadd_0_A_23_), .B(intadd_0_B_23_), .C(
intadd_0_n3), .CO(intadd_0_n2), .S(intadd_0_SUM_23_) );
CMPR32X2TS intadd_0_U2 ( .A(intadd_0_A_24_), .B(intadd_0_B_24_), .C(
intadd_0_n2), .CO(intadd_0_n1), .S(intadd_0_SUM_24_) );
CMPR32X2TS intadd_2_U20 ( .A(intadd_2_A_0_), .B(intadd_2_B_0_), .C(
intadd_2_CI), .CO(intadd_2_n19), .S(intadd_2_SUM_0_) );
CMPR32X2TS intadd_2_U19 ( .A(intadd_2_A_1_), .B(intadd_2_B_1_), .C(
intadd_2_n19), .CO(intadd_2_n18), .S(intadd_2_SUM_1_) );
CMPR32X2TS intadd_2_U18 ( .A(intadd_2_A_2_), .B(intadd_2_B_2_), .C(
intadd_2_n18), .CO(intadd_2_n17), .S(intadd_2_SUM_2_) );
CMPR32X2TS intadd_2_U17 ( .A(intadd_2_A_3_), .B(intadd_2_B_3_), .C(
intadd_2_n17), .CO(intadd_2_n16), .S(intadd_2_SUM_3_) );
CMPR32X2TS intadd_2_U16 ( .A(intadd_2_A_4_), .B(intadd_2_B_4_), .C(
intadd_2_n16), .CO(intadd_2_n15), .S(intadd_2_SUM_4_) );
CMPR32X2TS intadd_2_U15 ( .A(intadd_2_A_5_), .B(intadd_2_B_5_), .C(
intadd_2_n15), .CO(intadd_2_n14), .S(intadd_2_SUM_5_) );
CMPR32X2TS intadd_2_U14 ( .A(intadd_2_A_6_), .B(intadd_2_B_6_), .C(
intadd_2_n14), .CO(intadd_2_n13), .S(intadd_2_SUM_6_) );
CMPR32X2TS intadd_2_U13 ( .A(intadd_2_A_7_), .B(intadd_2_B_7_), .C(
intadd_2_n13), .CO(intadd_2_n12), .S(intadd_2_SUM_7_) );
CMPR32X2TS intadd_2_U12 ( .A(intadd_2_A_8_), .B(intadd_2_B_8_), .C(
intadd_2_n12), .CO(intadd_2_n11), .S(intadd_2_SUM_8_) );
CMPR32X2TS intadd_2_U11 ( .A(intadd_2_A_9_), .B(intadd_2_B_9_), .C(
intadd_2_n11), .CO(intadd_2_n10), .S(intadd_2_SUM_9_) );
CMPR32X2TS intadd_2_U10 ( .A(intadd_2_A_10_), .B(intadd_2_B_10_), .C(
intadd_2_n10), .CO(intadd_2_n9), .S(intadd_2_SUM_10_) );
CMPR32X2TS intadd_2_U9 ( .A(intadd_2_A_11_), .B(intadd_2_B_11_), .C(
intadd_2_n9), .CO(intadd_2_n8), .S(intadd_2_SUM_11_) );
CMPR32X2TS intadd_2_U8 ( .A(intadd_2_A_12_), .B(intadd_2_B_12_), .C(
intadd_2_n8), .CO(intadd_2_n7), .S(intadd_2_SUM_12_) );
CMPR32X2TS intadd_2_U7 ( .A(intadd_2_A_13_), .B(intadd_2_B_13_), .C(
intadd_2_n7), .CO(intadd_2_n6), .S(intadd_2_SUM_13_) );
CMPR32X2TS intadd_2_U6 ( .A(intadd_2_A_14_), .B(intadd_2_B_14_), .C(
intadd_2_n6), .CO(intadd_2_n5), .S(intadd_2_SUM_14_) );
CMPR32X2TS intadd_2_U5 ( .A(intadd_2_A_15_), .B(intadd_2_B_15_), .C(
intadd_2_n5), .CO(intadd_2_n4), .S(intadd_2_SUM_15_) );
CMPR32X2TS intadd_2_U4 ( .A(intadd_2_A_16_), .B(intadd_2_B_16_), .C(
intadd_2_n4), .CO(intadd_2_n3), .S(intadd_2_SUM_16_) );
CMPR32X2TS intadd_2_U3 ( .A(intadd_2_A_17_), .B(intadd_2_B_17_), .C(
intadd_2_n3), .CO(intadd_2_n2), .S(intadd_2_SUM_17_) );
CMPR32X2TS intadd_2_U2 ( .A(intadd_2_A_18_), .B(intadd_2_B_18_), .C(
intadd_2_n2), .CO(intadd_2_n1), .S(intadd_2_SUM_18_) );
CMPR32X2TS intadd_1_U21 ( .A(intadd_1_A_0_), .B(intadd_1_B_0_), .C(
intadd_1_CI), .CO(intadd_1_n20), .S(
FPMULT_Sgf_operation_EVEN1_middle_N5) );
CMPR32X2TS intadd_1_U20 ( .A(DP_OP_454J1_123_2743_n145), .B(intadd_1_B_1_),
.C(intadd_1_n20), .CO(intadd_1_n19), .S(
FPMULT_Sgf_operation_EVEN1_middle_N6) );
CMPR32X2TS intadd_1_U19 ( .A(DP_OP_454J1_123_2743_n140), .B(
DP_OP_454J1_123_2743_n144), .C(intadd_1_n19), .CO(intadd_1_n18), .S(
FPMULT_Sgf_operation_EVEN1_middle_N7) );
CMPR32X2TS intadd_1_U18 ( .A(DP_OP_454J1_123_2743_n139), .B(
DP_OP_454J1_123_2743_n135), .C(intadd_1_n18), .CO(intadd_1_n17), .S(
FPMULT_Sgf_operation_EVEN1_middle_N8) );
CMPR32X2TS intadd_1_U17 ( .A(DP_OP_454J1_123_2743_n134), .B(
DP_OP_454J1_123_2743_n128), .C(intadd_1_n17), .CO(intadd_1_n16), .S(
FPMULT_Sgf_operation_EVEN1_middle_N9) );
CMPR32X2TS intadd_1_U16 ( .A(DP_OP_454J1_123_2743_n127), .B(
DP_OP_454J1_123_2743_n122), .C(intadd_1_n16), .CO(intadd_1_n15), .S(
FPMULT_Sgf_operation_EVEN1_middle_N10) );
CMPR32X2TS intadd_1_U15 ( .A(DP_OP_454J1_123_2743_n114), .B(intadd_1_B_6_),
.C(intadd_1_n15), .CO(intadd_1_n14), .S(
FPMULT_Sgf_operation_EVEN1_middle_N11) );
CMPR32X2TS intadd_1_U14 ( .A(DP_OP_454J1_123_2743_n113), .B(
DP_OP_454J1_123_2743_n106), .C(intadd_1_n14), .CO(intadd_1_n13), .S(
FPMULT_Sgf_operation_EVEN1_middle_N12) );
CMPR32X2TS intadd_1_U13 ( .A(DP_OP_454J1_123_2743_n105), .B(
DP_OP_454J1_123_2743_n98), .C(intadd_1_n13), .CO(intadd_1_n12), .S(
FPMULT_Sgf_operation_EVEN1_middle_N13) );
CMPR32X2TS intadd_1_U12 ( .A(DP_OP_454J1_123_2743_n97), .B(
DP_OP_454J1_123_2743_n89), .C(intadd_1_n12), .CO(intadd_1_n11), .S(
FPMULT_Sgf_operation_EVEN1_middle_N14) );
CMPR32X2TS intadd_1_U11 ( .A(DP_OP_454J1_123_2743_n88), .B(
DP_OP_454J1_123_2743_n79), .C(intadd_1_n11), .CO(intadd_1_n10), .S(
FPMULT_Sgf_operation_EVEN1_middle_N15) );
CMPR32X2TS intadd_1_U10 ( .A(DP_OP_454J1_123_2743_n78), .B(
DP_OP_454J1_123_2743_n71), .C(intadd_1_n10), .CO(intadd_1_n9), .S(
FPMULT_Sgf_operation_EVEN1_middle_N16) );
CMPR32X2TS intadd_1_U9 ( .A(DP_OP_454J1_123_2743_n70), .B(
DP_OP_454J1_123_2743_n63), .C(intadd_1_n9), .CO(intadd_1_n8), .S(
FPMULT_Sgf_operation_EVEN1_middle_N17) );
CMPR32X2TS intadd_1_U8 ( .A(DP_OP_454J1_123_2743_n62), .B(
DP_OP_454J1_123_2743_n57), .C(intadd_1_n8), .CO(intadd_1_n7), .S(
FPMULT_Sgf_operation_EVEN1_middle_N18) );
CMPR32X2TS intadd_1_U7 ( .A(DP_OP_454J1_123_2743_n56), .B(
DP_OP_454J1_123_2743_n50), .C(intadd_1_n7), .CO(intadd_1_n6), .S(
FPMULT_Sgf_operation_EVEN1_middle_N19) );
CMPR32X2TS intadd_1_U6 ( .A(DP_OP_454J1_123_2743_n45), .B(
DP_OP_454J1_123_2743_n49), .C(intadd_1_n6), .CO(intadd_1_n5), .S(
FPMULT_Sgf_operation_EVEN1_middle_N20) );
CMPR32X2TS intadd_1_U5 ( .A(DP_OP_454J1_123_2743_n44), .B(
DP_OP_454J1_123_2743_n40), .C(intadd_1_n5), .CO(intadd_1_n4), .S(
FPMULT_Sgf_operation_EVEN1_middle_N21) );
CMPR32X2TS intadd_1_U4 ( .A(DP_OP_454J1_123_2743_n39), .B(
DP_OP_454J1_123_2743_n37), .C(intadd_1_n4), .CO(intadd_1_n3), .S(
FPMULT_Sgf_operation_EVEN1_middle_N22) );
CMPR32X2TS intadd_1_U3 ( .A(DP_OP_454J1_123_2743_n36), .B(intadd_1_B_18_),
.C(intadd_1_n3), .CO(intadd_1_n2), .S(
FPMULT_Sgf_operation_EVEN1_middle_N23) );
CMPR32X2TS intadd_3_U20 ( .A(intadd_3_A_0_), .B(intadd_3_B_0_), .C(
intadd_3_CI), .CO(intadd_3_n19), .S(intadd_3_SUM_0_) );
CMPR32X2TS intadd_3_U19 ( .A(intadd_3_A_1_), .B(intadd_3_B_1_), .C(
intadd_3_n19), .CO(intadd_3_n18), .S(intadd_3_SUM_1_) );
CMPR32X2TS intadd_3_U18 ( .A(intadd_3_A_2_), .B(intadd_3_B_2_), .C(
intadd_3_n18), .CO(intadd_3_n17), .S(intadd_3_SUM_2_) );
CMPR32X2TS intadd_3_U17 ( .A(intadd_3_A_3_), .B(intadd_3_B_3_), .C(
intadd_3_n17), .CO(intadd_3_n16), .S(intadd_3_SUM_3_) );
CMPR32X2TS intadd_3_U16 ( .A(intadd_3_A_4_), .B(intadd_3_B_4_), .C(
intadd_3_n16), .CO(intadd_3_n15), .S(intadd_3_SUM_4_) );
CMPR32X2TS intadd_3_U15 ( .A(intadd_3_A_5_), .B(intadd_3_B_5_), .C(
intadd_3_n15), .CO(intadd_3_n14), .S(intadd_3_SUM_5_) );
CMPR32X2TS intadd_3_U14 ( .A(intadd_3_A_6_), .B(intadd_3_B_6_), .C(
intadd_3_n14), .CO(intadd_3_n13), .S(intadd_3_SUM_6_) );
CMPR32X2TS intadd_3_U13 ( .A(intadd_3_A_7_), .B(intadd_3_B_7_), .C(
intadd_3_n13), .CO(intadd_3_n12), .S(intadd_3_SUM_7_) );
CMPR32X2TS intadd_3_U12 ( .A(intadd_3_A_8_), .B(intadd_3_B_8_), .C(
intadd_3_n12), .CO(intadd_3_n11), .S(intadd_3_SUM_8_) );
CMPR32X2TS intadd_3_U11 ( .A(intadd_3_A_9_), .B(intadd_3_B_9_), .C(
intadd_3_n11), .CO(intadd_3_n10), .S(intadd_3_SUM_9_) );
CMPR32X2TS intadd_3_U10 ( .A(intadd_3_A_10_), .B(intadd_3_B_10_), .C(
intadd_3_n10), .CO(intadd_3_n9), .S(intadd_3_SUM_10_) );
CMPR32X2TS intadd_3_U9 ( .A(intadd_3_A_11_), .B(intadd_3_B_11_), .C(
intadd_3_n9), .CO(intadd_3_n8), .S(intadd_3_SUM_11_) );
CMPR32X2TS intadd_3_U8 ( .A(intadd_3_A_12_), .B(intadd_3_B_12_), .C(
intadd_3_n8), .CO(intadd_3_n7), .S(intadd_3_SUM_12_) );
CMPR32X2TS intadd_3_U7 ( .A(intadd_3_A_13_), .B(intadd_3_B_13_), .C(
intadd_3_n7), .CO(intadd_3_n6), .S(intadd_3_SUM_13_) );
CMPR32X2TS intadd_3_U6 ( .A(intadd_3_A_14_), .B(intadd_3_B_14_), .C(
intadd_3_n6), .CO(intadd_3_n5), .S(intadd_3_SUM_14_) );
CMPR32X2TS intadd_3_U5 ( .A(intadd_3_A_15_), .B(intadd_3_B_15_), .C(
intadd_3_n5), .CO(intadd_3_n4), .S(intadd_3_SUM_15_) );
CMPR32X2TS intadd_3_U4 ( .A(intadd_3_A_16_), .B(intadd_3_B_16_), .C(
intadd_3_n4), .CO(intadd_3_n3), .S(intadd_3_SUM_16_) );
CMPR32X2TS intadd_3_U3 ( .A(intadd_3_A_17_), .B(intadd_3_B_17_), .C(
intadd_3_n3), .CO(intadd_3_n2), .S(intadd_3_SUM_17_) );
CMPR32X2TS intadd_5_U10 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .C(
intadd_5_n10), .CO(intadd_5_n9), .S(intadd_5_SUM_1_) );
CMPR32X2TS intadd_5_U4 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[20]), .C(
intadd_5_n4), .CO(intadd_5_n3), .S(intadd_5_SUM_7_) );
CMPR32X2TS intadd_5_U6 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .C(
intadd_5_n6), .CO(intadd_5_n5), .S(intadd_5_SUM_5_) );
CMPR32X2TS intadd_4_U4 ( .A(FPMULT_Op_MY[8]), .B(n2242), .C(intadd_4_n4),
.CO(intadd_4_n3), .S(intadd_4_SUM_7_) );
CMPR32X2TS intadd_4_U3 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[21]), .C(
intadd_4_n3), .CO(intadd_4_n2), .S(intadd_4_SUM_8_) );
CMPR32X2TS intadd_4_U2 ( .A(FPMULT_Op_MY[10]), .B(n2241), .C(intadd_4_n2),
.CO(intadd_4_n1), .S(intadd_4_SUM_9_) );
CMPR32X2TS intadd_1_U2 ( .A(intadd_1_A_19_), .B(intadd_1_B_19_), .C(
intadd_1_n2), .CO(intadd_1_n1), .S(
FPMULT_Sgf_operation_EVEN1_middle_N24) );
CMPR32X2TS intadd_3_U2 ( .A(intadd_3_A_18_), .B(intadd_3_B_18_), .C(
intadd_3_n2), .CO(intadd_3_n1), .S(intadd_3_SUM_18_) );
CMPR32X2TS DP_OP_26J1_124_9022_U3 ( .A(n5008), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J1_124_9022_n3), .CO(
DP_OP_26J1_124_9022_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2077), .CK(clk), .RN(
n5185), .Q(FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n5260), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1411), .CK(clk), .RN(
n5206), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1317), .CK(clk), .RN(
n5206), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRXLTS R_12 ( .D(n5171), .CK(clk), .RN(n5248), .Q(n5283) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1515), .CK(
clk), .RN(n5266), .Q(FPMULT_Sgf_normalized_result[9]), .QN(n5036) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1828), .CK(clk), .RN(
n5183), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1832), .CK(clk), .RN(
n5184), .Q(FPADDSUB_intDY_EWSW[12]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1840), .CK(clk), .RN(
n5182), .Q(FPADDSUB_intDY_EWSW[4]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1821), .CK(clk), .RN(
n5179), .Q(FPADDSUB_intDY_EWSW[23]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1830), .CK(clk), .RN(
n5184), .Q(FPADDSUB_intDY_EWSW[14]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1825), .CK(clk), .RN(
n5181), .Q(FPADDSUB_intDY_EWSW[19]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1823), .CK(clk), .RN(
n5181), .Q(FPADDSUB_intDY_EWSW[21]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1834), .CK(clk), .RN(
n5184), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1815), .CK(clk), .RN(
n5180), .Q(FPADDSUB_intDY_EWSW[29]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n1659), .CK(clk),
.RN(n5275), .Q(FPMULT_Op_MX[0]), .QN(n4993) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1820), .CK(clk), .RN(
n5179), .Q(FPADDSUB_intDY_EWSW[24]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1831), .CK(clk), .RN(
n5183), .Q(FPADDSUB_intDY_EWSW[13]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1839), .CK(clk), .RN(
n5187), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1841), .CK(clk), .RN(
n5185), .Q(FPADDSUB_intDY_EWSW[3]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1833), .CK(clk), .RN(
n5184), .Q(FPADDSUB_intDY_EWSW[11]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1829), .CK(clk), .RN(
n5180), .Q(FPADDSUB_intDY_EWSW[15]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2144), .CK(clk), .RN(
n5217), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n5003) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1337), .CK(clk), .RN(
n5205), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]), .QN(n5087) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2192), .CK(
clk), .RN(n5178), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1506), .CK(
clk), .RN(n5265), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1255), .CK(clk), .RN(n5213),
.Q(FPADDSUB_DMP_SFG[11]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1263), .CK(clk), .RN(n5213),
.Q(FPADDSUB_DMP_SFG[10]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1808), .CK(clk), .RN(n5181), .Q(FPADDSUB_Data_array_SWR[20]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1805), .CK(clk), .RN(n5187), .Q(FPADDSUB_Data_array_SWR[17]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1807), .CK(clk), .RN(n5182), .Q(FPADDSUB_Data_array_SWR[19]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1810), .CK(clk), .RN(n5186), .Q(FPADDSUB_Data_array_SWR[22]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1508), .CK(
clk), .RN(n5265), .Q(FPMULT_Sgf_normalized_result[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1211), .CK(clk), .RN(n5214),
.Q(FPADDSUB_DMP_SFG[15]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1219), .CK(clk), .RN(n5215),
.Q(FPADDSUB_DMP_SFG[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1223), .CK(clk), .RN(n5214),
.Q(FPADDSUB_DMP_SFG[19]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1231), .CK(clk), .RN(n5214),
.Q(FPADDSUB_DMP_SFG[17]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1243), .CK(clk), .RN(n5213),
.Q(FPADDSUB_DMP_SFG[13]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1267), .CK(clk), .RN(n5213),
.Q(FPADDSUB_DMP_SFG[12]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1348), .CK(clk), .RN(
n5204), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1227), .CK(clk), .RN(n5215),
.Q(FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1247), .CK(clk), .RN(n5214),
.Q(FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1259), .CK(clk), .RN(n5213),
.Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n5247), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1215), .CK(clk), .RN(n5214),
.Q(FPADDSUB_DMP_SFG[18]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1816), .CK(clk), .RN(
n5180), .Q(FPADDSUB_intDY_EWSW[28]), .QN(n4998) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1207), .CK(clk), .RN(n5215),
.Q(FPADDSUB_DMP_SFG[22]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2078), .CK(clk), .RN(
n5185), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n2202) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n5246), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2076), .CK(clk), .RN(
n5185), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2213) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n5246), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1343), .CK(clk), .RN(
n5204), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n5071) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1797), .CK(clk), .RN(n5184),
.Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1956), .CK(clk), .RN(
n5254), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1796), .CK(clk), .RN(n5187),
.Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1799), .CK(clk), .RN(n5184), .Q(FPADDSUB_Data_array_SWR[11]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1954), .CK(clk), .RN(
n5252), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1586), .CK(clk), .RN(
n5267), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1953), .CK(clk), .RN(
n5251), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1960), .CK(clk), .RN(
n5256), .Q(FPSENCOS_d_ff2_X[23]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2149), .CK(clk), .RN(
n5178), .Q(FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n5073) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1681), .CK(clk),
.RN(n5277), .Q(FPMULT_Op_MX[22]), .QN(n2422) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1339), .CK(clk), .RN(
n5205), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n5001) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1521), .CK(
clk), .RN(n5266), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1523), .CK(
clk), .RN(n5267), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1527), .CK(
clk), .RN(n5267), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1517), .CK(
clk), .RN(n5266), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1519), .CK(
clk), .RN(n5266), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1518), .CK(
clk), .RN(n5266), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1522), .CK(
clk), .RN(n5267), .Q(FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1524), .CK(
clk), .RN(n5267), .Q(FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1526), .CK(
clk), .RN(n5267), .Q(FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1528), .CK(
clk), .RN(n5267), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1520), .CK(
clk), .RN(n5266), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1916), .CK(clk), .RN(
n5179), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n5051) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1689), .CK(clk),
.RN(n5278), .Q(FPMULT_Op_MX[30]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1917), .CK(clk), .RN(
n5178), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n4997) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1201), .CK(clk), .RN(
n5208), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n5015) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1202), .CK(clk), .RN(
n5208), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n5012) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1957), .CK(clk), .RN(
n5254), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1958), .CK(clk), .RN(
n5255), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1959), .CK(clk), .RN(
n5256), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1463), .CK(clk), .RN(n5188),
.Q(FPADDSUB_DMP_EXP_EWSW[26]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1464), .CK(clk), .RN(n5188),
.Q(FPADDSUB_DMP_EXP_EWSW[25]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1650), .CK(clk),
.RN(n5271), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1620), .CK(clk), .RN(
n5272), .Q(FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1618), .CK(clk), .RN(
n5272), .Q(FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1607), .CK(clk),
.RN(n5274), .Q(FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1601), .CK(clk),
.RN(n5274), .Q(FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1599), .CK(clk),
.RN(n5274), .Q(FPMULT_Add_result[22]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1418), .CK(clk), .RN(n5191),
.Q(FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n2221), .CK(clk),
.RN(n5277), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1811), .CK(clk), .RN(n5186), .Q(FPADDSUB_Data_array_SWR[23]), .QN(n2436) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1812), .CK(clk), .RN(n5186), .Q(FPADDSUB_Data_array_SWR[24]), .QN(n5062) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1913), .CK(clk), .RN(
n5179), .Q(FPADDSUB_intDX_EWSW[29]), .QN(n5059) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n5218),
.Q(operation_reg[0]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1349), .CK(clk), .RN(
n5205), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n5017) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1813), .CK(clk), .RN(n5186), .Q(FPADDSUB_Data_array_SWR[25]), .QN(n2438) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1347), .CK(clk), .RN(
n5204), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n5082) );
DFFRX1TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1353), .CK(clk), .RN(n5208),
.Q(FPADDSUB_OP_FLAG_SFG) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n2220), .CK(clk),
.RN(n5277), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1734), .CK(clk), .RN(
n5220), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1912), .CK(clk), .RN(
n5179), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n5061) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n2219), .CK(clk),
.RN(n5277), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1656), .CK(clk),
.RN(n5272), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1589), .CK(clk), .RN(
n5268), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1590), .CK(clk), .RN(
n5268), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1592), .CK(clk), .RN(
n5268), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1593), .CK(clk), .RN(
n5268), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1462), .CK(clk), .RN(n5189),
.Q(FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1197), .CK(clk), .RN(
n5209), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n5013) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1198), .CK(clk), .RN(
n5209), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n5010) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1199), .CK(clk), .RN(
n5209), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n5014) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1200), .CK(clk), .RN(
n5208), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n5011) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1203), .CK(clk), .RN(
n5208), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n5016) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1770), .CK(clk), .RN(n5253), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2058), .CK(clk), .RN(n5237), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2070), .CK(clk), .RN(n5238), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2052), .CK(clk), .RN(n2618), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2067), .CK(clk), .RN(n5241), .Q(
FPSENCOS_d_ff_Xn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2064), .CK(clk), .RN(n5218), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2037), .CK(clk), .RN(n5220), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2043), .CK(clk), .RN(n5221), .Q(
FPSENCOS_d_ff_Xn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2031), .CK(clk), .RN(n5222), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2025), .CK(clk), .RN(n5224), .Q(
FPSENCOS_d_ff_Xn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2034), .CK(clk), .RN(n5225), .Q(
FPSENCOS_d_ff_Xn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2055), .CK(clk), .RN(n5226), .Q(
FPSENCOS_d_ff_Xn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2022), .CK(clk), .RN(n5227), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2013), .CK(clk), .RN(n5228), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2016), .CK(clk), .RN(n5229), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1906), .CK(clk), .RN(
n5239), .QN(n2395) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1892), .CK(clk), .RN(
n5223), .QN(n2385) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1878), .CK(clk), .RN(
n5250), .QN(n2380) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n5237), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n5238), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n5234), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n5241), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n5218), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n5220), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n5221), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n5222), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n5223), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n5224), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n5225), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n5226), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n5227), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n5228), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n5228), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n5229), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n5249), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n5249), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n5251), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1731), .CK(clk), .RN(n5252), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n5252), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n5253), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n5254), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n5255), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n5255), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n5256), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n5257), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1911), .CK(clk), .RN(
n5185), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2046), .CK(clk), .RN(n5238), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2073), .CK(clk), .RN(n5239), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2040), .CK(clk), .RN(n5222), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2049), .CK(clk), .RN(n5223), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2061), .CK(clk), .RN(n5226), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2010), .CK(clk), .RN(n5248), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2019), .CK(clk), .RN(n5249), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2028), .CK(clk), .RN(n5250), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2007), .CK(clk), .RN(n5251), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1728), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff_Xn[31]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1204), .CK(clk), .RN(
n5208), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n5018) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1419), .CK(clk), .RN(
n5217), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
ADDFX2TS DP_OP_26J1_124_9022_U2 ( .A(n5008), .B(FPADDSUB_DMP_exp_NRM2_EW[7]),
.CI(DP_OP_26J1_124_9022_n2), .CO(DP_OP_26J1_124_9022_n1), .S(
FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1251), .CK(clk), .RN(n5212),
.Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1280), .CK(clk), .RN(n5212),
.Q(FPADDSUB_DMP_SFG[9]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1476), .CK(clk), .RN(
n5188), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1638), .CK(clk),
.RN(n5270), .Q(FPMULT_Op_MY[11]), .QN(n5028) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2080), .CK(clk), .RN(
n5185), .Q(FPADDSUB_bit_shift_SHT2), .QN(n2222) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1836), .CK(clk), .RN(
n5183), .Q(FPADDSUB_intDY_EWSW[8]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1434), .CK(clk), .RN(
n5216), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1444), .CK(clk), .RN(
n5216), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1477), .CK(clk), .RN(
n5188), .QN(n5069) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1346), .CK(clk), .RN(
n5204), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1937), .CK(clk), .RN(
n5187), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n2428) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1933), .CK(clk), .RN(
n5187), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n2427) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1941), .CK(clk), .RN(
n5187), .Q(FPADDSUB_intDX_EWSW[1]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1935), .CK(clk), .RN(
n5186), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n2426) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1940), .CK(clk), .RN(
n5186), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n2411) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1939), .CK(clk), .RN(
n5185), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n2421) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1930), .CK(clk), .RN(
n5185), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n2425) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1932), .CK(clk), .RN(
n5184), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n2430) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1928), .CK(clk), .RN(
n5184), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n2405) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1931), .CK(clk), .RN(
n5184), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n2406) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1926), .CK(clk), .RN(
n5183), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n2415) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1929), .CK(clk), .RN(
n5183), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n2424) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1936), .CK(clk), .RN(
n5182), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n2429) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1938), .CK(clk), .RN(
n5182), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n2423) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1925), .CK(clk), .RN(
n5182), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n2416) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1922), .CK(clk), .RN(
n5182), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n2407) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1923), .CK(clk), .RN(
n5181), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n2414) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1921), .CK(clk), .RN(
n5181), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n2417) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1924), .CK(clk), .RN(
n5181), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n2412) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1927), .CK(clk), .RN(
n5180), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n2434) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1920), .CK(clk), .RN(
n5180), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n2431) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1915), .CK(clk), .RN(
n5179), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n2413) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1729), .CK(clk), .RN(
n5185), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1726), .CK(clk), .RN(n5238),
.Q(cordic_result[1]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1765), .CK(clk), .RN(
n2616), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1697), .CK(clk), .RN(n5251),
.Q(cordic_result[30]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1698), .CK(clk), .RN(n5252),
.Q(cordic_result[29]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1700), .CK(clk), .RN(n5253),
.Q(cordic_result[27]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1701), .CK(clk), .RN(n5254),
.Q(cordic_result[26]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1702), .CK(clk), .RN(n5255),
.Q(cordic_result[25]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1703), .CK(clk), .RN(n5256),
.Q(cordic_result[24]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1704), .CK(clk), .RN(n5256),
.Q(cordic_result[23]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2116), .CK(clk), .RN(n5243), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2117), .CK(clk), .RN(n5243), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2130), .CK(clk), .RN(n5245), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n5247), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n5261), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n5262), .Q(
dataA[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n1571), .CK(clk),
.RN(n5262), .Q(FPMULT_P_Sgf[41]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2124), .CK(clk), .RN(n5244), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRX1TS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n5247), .Q(
dataB[29]) );
DFFRX1TS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1847), .CK(clk), .RN(n5242),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1597), .CK(clk),
.RN(n5272), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2129), .CK(clk), .RN(n5245), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2132), .CK(clk), .RN(n5245), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1788), .CK(clk), .RN(n5202),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRX1TS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n5247), .Q(
dataB[27]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1838), .CK(clk), .RN(
n5182), .Q(FPADDSUB_intDY_EWSW[6]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1824), .CK(clk), .RN(
n5181), .Q(FPADDSUB_intDY_EWSW[20]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1842), .CK(clk), .RN(
n5186), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1837), .CK(clk), .RN(
n5186), .Q(FPADDSUB_intDY_EWSW[7]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1822), .CK(clk), .RN(
n5180), .Q(FPADDSUB_intDY_EWSW[22]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1835), .CK(clk), .RN(
n5187), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1817), .CK(clk), .RN(
n5179), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1826), .CK(clk), .RN(
n5181), .Q(FPADDSUB_intDY_EWSW[18]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1843), .CK(clk), .RN(
n5187), .Q(FPADDSUB_intDY_EWSW[1]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1827), .CK(clk), .RN(
n5182), .Q(FPADDSUB_intDY_EWSW[17]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1819), .CK(clk), .RN(
n5179), .Q(FPADDSUB_intDY_EWSW[25]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1818), .CK(clk), .RN(
n5179), .Q(FPADDSUB_intDY_EWSW[26]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1844), .CK(clk), .RN(
n5186), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1814), .CK(clk), .RN(
n5180), .Q(FPADDSUB_intDY_EWSW[30]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1338), .CK(clk), .RN(
n5204), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n5007) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1803), .CK(clk), .RN(n5183), .Q(FPADDSUB_Data_array_SWR[15]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1806), .CK(clk), .RN(n5187), .Q(FPADDSUB_Data_array_SWR[18]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1942), .CK(clk), .RN(
n5186), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n2420) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1800), .CK(clk), .RN(n5183), .Q(FPADDSUB_Data_array_SWR[12]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1801), .CK(clk), .RN(n5184), .Q(FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1804), .CK(clk), .RN(n5182), .Q(FPADDSUB_Data_array_SWR[16]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1919), .CK(clk), .RN(
n5178), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n5053) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1350), .CK(clk), .RN(
n5205), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n5094) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1341), .CK(clk), .RN(
n5204), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n5070) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n5246), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1507), .CK(
clk), .RN(n5265), .Q(FPMULT_Sgf_normalized_result[1]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1449), .CK(clk), .RN(
n5216), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1439), .CK(clk), .RN(
n5216), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1429), .CK(clk), .RN(
n5216), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1340), .CK(clk), .RN(
n5204), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n5019) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1344), .CK(clk), .RN(
n5204), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n5084) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1345), .CK(clk), .RN(
n5204), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n5039) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1918), .CK(clk), .RN(
n5178), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n5060) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1342), .CK(clk), .RN(
n5204), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n5038) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n5178),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n5079) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1914), .CK(clk), .RN(
n5179), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n5068) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n2218), .CK(clk),
.RN(n5277), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1465), .CK(clk), .RN(n5188),
.Q(FPADDSUB_DMP_EXP_EWSW[24]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1802), .CK(clk), .RN(n5183), .Q(FPADDSUB_Data_array_SWR[14]), .QN(n2400) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1602), .CK(clk),
.RN(n5274), .Q(FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n2217), .CK(clk),
.RN(n5277), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1809), .CK(clk), .RN(n5180), .Q(FPADDSUB_Data_array_SWR[21]), .QN(n5067) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1194), .CK(clk), .RN(
n5209), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n5111) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1191), .CK(clk), .RN(
n5209), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n5109) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n5280), .CK(clk), .RN(n5178), .Q(
ready_add_subt), .QN(n5064) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1655), .CK(clk),
.RN(n5272), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1183), .CK(clk), .RN(
n5210), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n5105) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n5248),
.Q(operation_reg[1]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2004), .CK(clk), .RN(
n5238), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1193), .CK(clk), .RN(
n5209), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n5110) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1767), .CK(clk), .RN(n5252), .Q(
FPSENCOS_d_ff_Xn[29]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1962), .CK(clk), .RN(
n5251), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1776), .CK(clk), .RN(n5254), .Q(
FPSENCOS_d_ff_Xn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1773), .CK(clk), .RN(n5254), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1782), .CK(clk), .RN(n5256), .Q(
FPSENCOS_d_ff_Xn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1779), .CK(clk), .RN(n5255), .Q(
FPSENCOS_d_ff_Xn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1730), .CK(clk), .RN(n5252), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1785), .CK(clk), .RN(n5257), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n5239), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1733), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1648), .CK(clk),
.RN(n5271), .Q(FPMULT_Op_MY[21]), .QN(n5026) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1235), .CK(clk), .RN(n5211),
.Q(FPADDSUB_DMP_SFG[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1424), .CK(clk), .RN(
n5217), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n1642), .CK(clk),
.RN(n5270), .Q(FPMULT_Op_MY[15]), .QN(n5030) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1646), .CK(clk),
.RN(n5271), .Q(FPMULT_Op_MY[19]), .QN(n5027) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n1672), .CK(clk),
.RN(n5276), .Q(FPMULT_Op_MX[13]), .QN(n4999) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1454), .CK(clk), .RN(
n5215), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1934), .CK(clk), .RN(
n5183), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n2404) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2135), .CK(clk), .RN(n5245),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n2223) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2150), .CK(
clk), .RN(n5178), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n2212) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1466), .CK(clk), .RN(n5188),
.Q(FPADDSUB_DMP_EXP_EWSW[23]), .QN(n2224) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n5247), .Q(
dataB[28]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1732), .CK(clk), .RN(
n5185), .Q(FPADDSUB_intAS) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1798), .CK(clk), .RN(n5187), .Q(FPADDSUB_Data_array_SWR[10]), .QN(n5080) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1205), .CK(clk), .RN(
n5208), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n5004) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1789), .CK(clk), .RN(n5180),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1621), .CK(clk), .RN(
n5272), .Q(FPMULT_Add_result[0]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n5262), .Q(
dataB[23]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2134), .CK(clk), .RN(n5245), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n5261), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n5261), .Q(
dataA[28]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n5247), .Q(
dataB[26]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n5261), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n5260), .Q(
dataA[27]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n2618), .Q(
dataB[24]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1414), .CK(clk), .RN(n5192),
.Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1795), .CK(clk), .RN(n5183),
.Q(FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1600), .CK(clk),
.RN(n5274), .Q(FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1605), .CK(clk),
.RN(n5274), .Q(FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1606), .CK(clk),
.RN(n5274), .Q(FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1608), .CK(clk),
.RN(n5273), .Q(FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1609), .CK(clk),
.RN(n5273), .Q(FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1610), .CK(clk),
.RN(n5273), .Q(FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1611), .CK(clk),
.RN(n5273), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1619), .CK(clk), .RN(
n5272), .Q(FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1617), .CK(clk), .RN(
n5273), .Q(FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1616), .CK(clk), .RN(
n5273), .Q(FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1615), .CK(clk), .RN(
n5273), .Q(FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1614), .CK(clk), .RN(
n5273), .Q(FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1613), .CK(clk), .RN(
n5273), .Q(FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1612), .CK(clk), .RN(
n5273), .Q(FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1598), .CK(clk),
.RN(n5272), .Q(FPMULT_Add_result[23]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1603), .CK(clk),
.RN(n5274), .Q(FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n2216), .CK(clk),
.RN(n5277), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1794), .CK(clk), .RN(n5182),
.Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1185), .CK(clk), .RN(
n5210), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n5106) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1187), .CK(clk), .RN(
n5210), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n5107) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1189), .CK(clk), .RN(
n5210), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n5108) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1196), .CK(clk), .RN(
n5209), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n5103) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1792), .CK(clk), .RN(n5188),
.Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1652), .CK(clk),
.RN(n5271), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1657), .CK(clk),
.RN(n5272), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1793), .CK(clk), .RN(n5180),
.Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1654), .CK(clk),
.RN(n5272), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1595), .CK(clk), .RN(
n5268), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1594), .CK(clk), .RN(
n5268), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1591), .CK(clk), .RN(
n5268), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1588), .CK(clk), .RN(
n5268), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1651), .CK(clk),
.RN(n5271), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n1572), .CK(clk),
.RN(n5231), .Q(FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1653), .CK(clk),
.RN(n5271), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1994), .CK(clk), .RN(
n5226), .Q(FPSENCOS_d_ff2_X[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1986), .CK(clk), .RN(
n5221), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1982), .CK(clk), .RN(
n5220), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2002), .CK(clk), .RN(
n5241), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1964), .CK(clk), .RN(
n5254), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1998), .CK(clk), .RN(
n5226), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1990), .CK(clk), .RN(
n5223), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2006), .CK(clk), .RN(
n5239), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1988), .CK(clk), .RN(
n5237), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1968), .CK(clk), .RN(
n5229), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1966), .CK(clk), .RN(
n5228), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1972), .CK(clk), .RN(
n5227), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1980), .CK(clk), .RN(
n5225), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1974), .CK(clk), .RN(
n5224), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1978), .CK(clk), .RN(
n5221), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n2000), .CK(clk), .RN(
n5218), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1992), .CK(clk), .RN(
n2609), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1996), .CK(clk), .RN(
n5237), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1195), .CK(clk), .RN(
n5209), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n5118) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1192), .CK(clk), .RN(
n5209), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n5117) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1190), .CK(clk), .RN(
n5210), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n5116) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1188), .CK(clk), .RN(
n5210), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n5115) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1186), .CK(clk), .RN(
n5210), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n5114) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1184), .CK(clk), .RN(
n5210), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n5113) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1182), .CK(clk), .RN(
n5210), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n5112) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1909), .CK(clk), .RN(n5219), .Q(
FPSENCOS_d_ff_Yn[31]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1976), .CK(clk), .RN(
n5250), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1970), .CK(clk), .RN(
n5249), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1984), .CK(clk), .RN(
n5222), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1944), .CK(clk), .RN(
n5219), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n5250), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n5224), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1324), .CK(clk), .RN(n5211),
.Q(FPADDSUB_DMP_SFG[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1308), .CK(clk), .RN(n5211),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1301), .CK(clk), .RN(n5212),
.Q(FPADDSUB_DMP_SFG[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1273), .CK(clk), .RN(n5212),
.Q(FPADDSUB_DMP_SFG[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1239), .CK(clk), .RN(n5212),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1287), .CK(clk), .RN(n5211),
.Q(FPADDSUB_DMP_SFG[1]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1294), .CK(clk), .RN(n5211),
.Q(FPADDSUB_DMP_SFG[0]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1629), .CK(clk),
.RN(n5269), .Q(FPMULT_Op_MY[2]), .QN(n5050) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1649), .CK(clk),
.RN(n5271), .Q(n2210), .QN(n5024) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1627), .CK(clk),
.RN(n5269), .Q(FPMULT_Op_MY[0]), .QN(n4990) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1647), .CK(clk),
.RN(n5271), .Q(FPMULT_Op_MY[20]), .QN(n5022) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1645), .CK(clk),
.RN(n5271), .Q(FPMULT_Op_MY[18]), .QN(n5025) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1641), .CK(clk),
.RN(n5270), .Q(n2199), .QN(n5031) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1643), .CK(clk),
.RN(n5270), .Q(n2207), .QN(n5023) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1644), .CK(clk),
.RN(n5271), .Q(n2200), .QN(n5029) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1333), .CK(clk), .RN(
n5205), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n5055) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1322), .CK(clk), .RN(
n5206), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]), .QN(n5097) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1320), .CK(clk), .RN(
n5206), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n5040) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1318), .CK(clk), .RN(
n5206), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n5098) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1316), .CK(clk), .RN(
n5206), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFSX1TS R_3 ( .D(n5174), .CK(clk), .SN(n5261), .Q(n5285) );
DFFSX1TS R_4 ( .D(n5173), .CK(clk), .SN(n5230), .Q(n5286) );
DFFSX1TS R_11 ( .D(n5172), .CK(clk), .SN(n2608), .Q(n5284) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n1695), .CK(clk),
.RN(n5233), .Q(FPMULT_P_Sgf[47]), .QN(n5129) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1860), .CK(clk), .RN(
n5255), .Q(FPSENCOS_d_ff2_Y[25]), .QN(n5127) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n5246), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .QN(n5034) );
DFFSX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n5282), .CK(clk), .SN(n5269), .Q(n5020),
.QN(FPMULT_FSM_selector_B[0]) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2147), .CK(clk), .RN(
n5178), .Q(n5287), .QN(n5169) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1420), .CK(clk), .RN(
n5217), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n5279), .CK(clk),
.RN(n5246), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1206), .CK(clk), .RN(
n5208), .QN(n5130) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1315), .CK(clk), .RN(
n5207), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n1671), .CK(clk),
.RN(n5276), .Q(FPMULT_Op_MX[12]), .QN(n5066) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n1674), .CK(clk),
.RN(n5276), .Q(FPMULT_Op_MX[15]), .QN(n2226) );
CMPR32X2TS intadd_5_U8 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .C(
intadd_5_n8), .CO(intadd_5_n7), .S(intadd_5_SUM_3_) );
CMPR32X2TS intadd_4_U10 ( .A(FPMULT_Op_MY[2]), .B(n2240), .C(intadd_4_n10),
.CO(intadd_4_n9), .S(intadd_4_SUM_1_) );
CMPR32X2TS intadd_5_U2 ( .A(FPMULT_Op_MX[10]), .B(n5177), .C(intadd_5_n2),
.CO(intadd_5_n1), .S(intadd_5_SUM_9_) );
CMPR32X2TS intadd_4_U6 ( .A(FPMULT_Op_MY[6]), .B(n2244), .C(intadd_4_n6),
.CO(intadd_4_n5), .S(intadd_4_SUM_5_) );
CMPR32X2TS intadd_4_U5 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[19]), .C(
intadd_4_n5), .CO(intadd_4_n4), .S(intadd_4_SUM_6_) );
CMPR32X2TS DP_OP_26J1_124_9022_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n5008), .C(DP_OP_26J1_124_9022_n18), .CO(DP_OP_26J1_124_9022_n8), .S(
FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J1_124_9022_U8 ( .A(DP_OP_26J1_124_9022_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J1_124_9022_n8), .CO(
DP_OP_26J1_124_9022_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J1_124_9022_U7 ( .A(DP_OP_26J1_124_9022_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J1_124_9022_n7), .CO(
DP_OP_26J1_124_9022_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_234J1_127_8543_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(
FPMULT_FSM_exp_operation_A_S), .C(DP_OP_234J1_127_8543_n22), .CO(
DP_OP_234J1_127_8543_n9), .S(FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_26J1_124_9022_U6 ( .A(DP_OP_26J1_124_9022_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J1_124_9022_n6), .CO(
DP_OP_26J1_124_9022_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J1_124_9022_U5 ( .A(DP_OP_26J1_124_9022_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J1_124_9022_n5), .CO(
DP_OP_26J1_124_9022_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J1_124_9022_U4 ( .A(n5008), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J1_124_9022_n4), .CO(
DP_OP_26J1_124_9022_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2079), .CK(clk), .RN(
n5209), .Q(FPADDSUB_left_right_SHT2), .QN(n2205) );
CMPR32X2TS intadd_8_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n5006), .C(intadd_8_CI), .CO(intadd_8_n3), .S(intadd_8_SUM_0_) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2145), .CK(clk), .RN(
n5208), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n2410) );
CMPR32X2TS intadd_8_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n4991), .C(intadd_8_n3), .CO(intadd_8_n2), .S(intadd_8_SUM_1_) );
CMPR32X2TS intadd_6_U4 ( .A(n5086), .B(FPADDSUB_DMP_EXP_EWSW[24]), .C(
intadd_6_CI), .CO(intadd_6_n3), .S(intadd_6_SUM_0_) );
CMPR32X2TS intadd_6_U3 ( .A(n5085), .B(FPADDSUB_DMP_EXP_EWSW[25]), .C(
intadd_6_n3), .CO(intadd_6_n2), .S(intadd_6_SUM_1_) );
CMPR32X2TS intadd_6_U2 ( .A(n5123), .B(FPADDSUB_DMP_EXP_EWSW[26]), .C(
intadd_6_n2), .CO(intadd_6_n1), .S(intadd_6_SUM_2_) );
CMPR32X2TS DP_OP_234J1_127_8543_U2 ( .A(n2361), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_234J1_127_8543_n2), .CO(DP_OP_234J1_127_8543_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
INVX3TS U2217 ( .A(n2197), .Y(n2272) );
AOI222X1TS U2218 ( .A0(n3397), .A1(cordic_result[4]), .B0(n3398), .B1(
FPSENCOS_d_ff_Xn[4]), .C0(n3399), .C1(FPSENCOS_d_ff_Yn[4]), .Y(n3403)
);
AOI222X1TS U2219 ( .A0(n3397), .A1(cordic_result[3]), .B0(n3398), .B1(
FPSENCOS_d_ff_Xn[3]), .C0(n3399), .C1(FPSENCOS_d_ff_Yn[3]), .Y(n3407)
);
AOI222X1TS U2220 ( .A0(n3397), .A1(cordic_result[5]), .B0(n3398), .B1(
FPSENCOS_d_ff_Xn[5]), .C0(n3399), .C1(FPSENCOS_d_ff_Yn[5]), .Y(n3401)
);
AOI222X1TS U2221 ( .A0(n3495), .A1(cordic_result[8]), .B0(n3398), .B1(
FPSENCOS_d_ff_Xn[8]), .C0(n3399), .C1(FPSENCOS_d_ff_Yn[8]), .Y(n3404)
);
AOI222X1TS U2222 ( .A0(n3495), .A1(cordic_result[9]), .B0(n3398), .B1(
FPSENCOS_d_ff_Xn[9]), .C0(n3399), .C1(FPSENCOS_d_ff_Yn[9]), .Y(n3402)
);
AOI222X1TS U2223 ( .A0(n3495), .A1(cordic_result[6]), .B0(n3398), .B1(
FPSENCOS_d_ff_Xn[6]), .C0(n3399), .C1(FPSENCOS_d_ff_Yn[6]), .Y(n3405)
);
AOI222X1TS U2224 ( .A0(n3495), .A1(cordic_result[7]), .B0(n3398), .B1(
FPSENCOS_d_ff_Xn[7]), .C0(n3399), .C1(FPSENCOS_d_ff_Yn[7]), .Y(n3408)
);
AOI222X1TS U2225 ( .A0(n3503), .A1(cordic_result[28]), .B0(n3502), .B1(
FPSENCOS_d_ff_Xn[28]), .C0(n3501), .C1(FPSENCOS_d_ff_Yn[28]), .Y(n3492) );
AOI222X1TS U2226 ( .A0(n3397), .A1(cordic_result[2]), .B0(n3411), .B1(
FPSENCOS_d_ff_Xn[2]), .C0(n3412), .C1(FPSENCOS_d_ff_Yn[2]), .Y(n3409)
);
AOI222X1TS U2227 ( .A0(n3499), .A1(cordic_result[15]), .B0(n3498), .B1(
FPSENCOS_d_ff_Xn[15]), .C0(n3497), .C1(FPSENCOS_d_ff_Yn[15]), .Y(n3416) );
AOI222X1TS U2228 ( .A0(n3499), .A1(cordic_result[18]), .B0(n3498), .B1(
FPSENCOS_d_ff_Xn[18]), .C0(n3497), .C1(FPSENCOS_d_ff_Yn[18]), .Y(n3410) );
AOI222X1TS U2229 ( .A0(n3495), .A1(cordic_result[11]), .B0(n3498), .B1(
FPSENCOS_d_ff_Xn[11]), .C0(n3497), .C1(FPSENCOS_d_ff_Yn[11]), .Y(n3484) );
AOI222X1TS U2230 ( .A0(n3499), .A1(cordic_result[19]), .B0(n3498), .B1(
FPSENCOS_d_ff_Xn[19]), .C0(n3497), .C1(FPSENCOS_d_ff_Yn[19]), .Y(n3415) );
AOI222X1TS U2231 ( .A0(n3499), .A1(cordic_result[17]), .B0(n3498), .B1(
FPSENCOS_d_ff_Xn[17]), .C0(n3497), .C1(FPSENCOS_d_ff_Yn[17]), .Y(n3490) );
AOI222X1TS U2232 ( .A0(n3495), .A1(cordic_result[13]), .B0(n3498), .B1(
FPSENCOS_d_ff_Xn[13]), .C0(n3497), .C1(FPSENCOS_d_ff_Yn[13]), .Y(n3486) );
AOI222X1TS U2233 ( .A0(n3499), .A1(cordic_result[16]), .B0(n3498), .B1(
FPSENCOS_d_ff_Xn[16]), .C0(n3497), .C1(FPSENCOS_d_ff_Yn[16]), .Y(n3500) );
AOI222X1TS U2234 ( .A0(n3499), .A1(cordic_result[14]), .B0(n3498), .B1(
FPSENCOS_d_ff_Xn[14]), .C0(n3497), .C1(FPSENCOS_d_ff_Yn[14]), .Y(n3493) );
AOI222X1TS U2235 ( .A0(n3495), .A1(cordic_result[10]), .B0(n3498), .B1(
FPSENCOS_d_ff_Xn[10]), .C0(n3497), .C1(FPSENCOS_d_ff_Yn[10]), .Y(n3487) );
AOI222X1TS U2236 ( .A0(n3495), .A1(cordic_result[12]), .B0(n3498), .B1(
FPSENCOS_d_ff_Xn[12]), .C0(n3497), .C1(FPSENCOS_d_ff_Yn[12]), .Y(n3496) );
AOI222X1TS U2237 ( .A0(n3499), .A1(cordic_result[22]), .B0(n3502), .B1(
FPSENCOS_d_ff_Xn[22]), .C0(n3501), .C1(FPSENCOS_d_ff_Yn[22]), .Y(n3413) );
AOI222X1TS U2238 ( .A0(n3499), .A1(cordic_result[21]), .B0(n3502), .B1(
FPSENCOS_d_ff_Xn[21]), .C0(n3501), .C1(FPSENCOS_d_ff_Yn[21]), .Y(n3414) );
AOI222X1TS U2239 ( .A0(n3499), .A1(cordic_result[20]), .B0(n3502), .B1(
FPSENCOS_d_ff_Xn[20]), .C0(n3501), .C1(FPSENCOS_d_ff_Yn[20]), .Y(n3491) );
AOI32X1TS U2240 ( .A0(n3218), .A1(n4604), .A2(n5054), .B0(
FPSENCOS_d_ff3_LUT_out[6]), .B1(n4603), .Y(n3205) );
AOI222X1TS U2241 ( .A0(n4564), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4607), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n3238), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n3221)
);
AOI222X1TS U2242 ( .A0(n3374), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n3379), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n3378), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n3368) );
AOI222X1TS U2243 ( .A0(n3374), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n3379), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n3378), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n3359) );
AOI222X1TS U2244 ( .A0(n3374), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n3379), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n3371), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n3362) );
AOI222X1TS U2245 ( .A0(n3374), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n3379), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n3378), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n3373) );
AOI222X1TS U2246 ( .A0(n3374), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n3379), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n3371), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n3360) );
AOI222X1TS U2247 ( .A0(n3374), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n3379), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n3378), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n3375) );
AOI222X1TS U2248 ( .A0(n4564), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n3231), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n3238), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n3223)
);
AOI222X1TS U2249 ( .A0(n3381), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n3231), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n3238), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n3230)
);
AOI222X1TS U2250 ( .A0(n3381), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n3379), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n3378), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n3377) );
AOI222X1TS U2251 ( .A0(n3374), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n3379), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n3378), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n3369) );
AOI222X1TS U2252 ( .A0(n3381), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n3231), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n3238), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n3232)
);
AOI222X1TS U2253 ( .A0(n3381), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n3231), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n3378), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n3227) );
AOI222X1TS U2254 ( .A0(n3374), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n3379), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n3378), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n3365) );
AOI222X1TS U2255 ( .A0(n3381), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n3231), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n3378), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n3226) );
AOI222X1TS U2256 ( .A0(n3381), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n3379), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n3378), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n3380) );
AOI222X1TS U2257 ( .A0(n4564), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n3231), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n3238), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n3225)
);
AOI222X1TS U2258 ( .A0(n4564), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n3231), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n3238), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n3222)
);
AOI222X1TS U2259 ( .A0(n3381), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n3231), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n3238), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n3228)
);
AOI222X1TS U2260 ( .A0(n3381), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n3231), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n3238), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n3229)
);
AOI222X1TS U2261 ( .A0(n3381), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n3231), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n3238), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n3224)
);
AOI222X1TS U2262 ( .A0(n4551), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n3384), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n3383), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n3376) );
AOI222X1TS U2263 ( .A0(n4551), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n3384), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n3383), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n3367) );
AOI222X1TS U2264 ( .A0(n4551), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n3384), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n3383), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n3385) );
AOI222X1TS U2265 ( .A0(n4551), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n3384), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n3383), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n3361) );
AOI222X1TS U2266 ( .A0(n4551), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n3384), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n3383), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n3370) );
AOI222X1TS U2267 ( .A0(n3374), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n3384), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n3371), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n3372) );
AOI222X1TS U2268 ( .A0(n4551), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n3384), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n3371), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n3366) );
AOI222X1TS U2269 ( .A0(n4551), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n3384), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n3383), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n3363) );
AOI222X1TS U2270 ( .A0(n3374), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n3384), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n3371), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n3364) );
INVX2TS U2271 ( .A(n3626), .Y(n3764) );
INVX2TS U2272 ( .A(n2211), .Y(n2329) );
INVX2TS U2273 ( .A(n2211), .Y(n2330) );
NAND3X1TS U2274 ( .A(n4602), .B(FPSENCOS_cont_iter_out[1]), .C(n2777), .Y(
n3235) );
INVX2TS U2275 ( .A(n2194), .Y(n2197) );
NAND2BX1TS U2276 ( .AN(n2481), .B(n2480), .Y(n4861) );
BUFX3TS U2277 ( .A(n2435), .Y(n3759) );
BUFX3TS U2278 ( .A(n2776), .Y(n4567) );
AND4X1TS U2279 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n2454), .Y(n2455) );
INVX2TS U2280 ( .A(n2536), .Y(n2776) );
BUFX6TS U2281 ( .A(n3279), .Y(n3319) );
CMPR32X2TS U2282 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[19]), .C(n3841),
.CO(mult_x_219_n42), .S(mult_x_219_n43) );
BUFX3TS U2283 ( .A(n4598), .Y(n4608) );
NAND2X1TS U2284 ( .A(n3219), .B(n3218), .Y(n4521) );
OAI2BB2X2TS U2285 ( .B0(n4484), .B1(n3147), .A0N(operation[1]), .A1N(n4482),
.Y(n4501) );
BUFX3TS U2286 ( .A(n2535), .Y(n4598) );
AOI21X2TS U2287 ( .A0(n4143), .A1(n2511), .B0(n2510), .Y(n4134) );
NAND2BX2TS U2288 ( .AN(n2607), .B(n3136), .Y(n4515) );
OAI21X2TS U2289 ( .A0(n4153), .A1(n2509), .B0(n2508), .Y(n4143) );
CMPR32X2TS U2290 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[15]), .C(n4279),
.CO(mult_x_219_n71), .S(mult_x_219_n72) );
CMPR32X2TS U2291 ( .A(n2240), .B(n5021), .C(n3861), .CO(mult_x_219_n79), .S(
mult_x_219_n80) );
NOR2X1TS U2292 ( .A(n3594), .B(n3576), .Y(n3596) );
NOR2X1TS U2293 ( .A(FPADDSUB_intDY_EWSW[19]), .B(n3586), .Y(n3588) );
NAND2X1TS U2294 ( .A(n2376), .B(n2378), .Y(n3607) );
NAND2X2TS U2295 ( .A(n2541), .B(n5019), .Y(n2568) );
OAI21X2TS U2296 ( .A0(n4185), .A1(n4179), .B0(n4180), .Y(n4166) );
AOI221X4TS U2297 ( .A0(n5075), .A1(n2299), .B0(FPMULT_Op_MX[6]), .B1(n2301),
.C0(n3848), .Y(n4357) );
AOI221X4TS U2298 ( .A0(n5058), .A1(n2318), .B0(FPMULT_Op_MX[18]), .B1(n2319),
.C0(n2840), .Y(n3860) );
CMPR32X2TS U2299 ( .A(FPMULT_Op_MY[5]), .B(n2245), .C(intadd_4_n7), .CO(
intadd_4_n6), .S(intadd_4_SUM_4_) );
CMPR32X2TS U2300 ( .A(n2312), .B(n2325), .C(intadd_5_n3), .CO(intadd_5_n2),
.S(intadd_5_SUM_8_) );
CMPR32X2TS U2301 ( .A(FPMULT_Op_MY[4]), .B(n2243), .C(intadd_4_n8), .CO(
intadd_4_n7), .S(intadd_4_SUM_3_) );
CMPR32X2TS U2302 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MY[15]), .C(intadd_4_n9), .CO(intadd_4_n8), .S(intadd_4_SUM_2_) );
CMPR32X2TS U2303 ( .A(n2307), .B(n2292), .C(intadd_5_n7), .CO(intadd_5_n6),
.S(intadd_5_SUM_4_) );
CMPR32X2TS U2304 ( .A(n2304), .B(FPMULT_Op_MX[15]), .C(intadd_5_n9), .CO(
intadd_5_n8), .S(intadd_5_SUM_2_) );
CMPR32X2TS U2305 ( .A(n2338), .B(FPMULT_Op_MX[13]), .C(intadd_5_CI), .CO(
intadd_5_n10), .S(intadd_5_SUM_0_) );
OAI21XLTS U2306 ( .A0(n3607), .A1(n3606), .B0(n3605), .Y(n3608) );
OAI21XLTS U2307 ( .A0(n3613), .A1(n3612), .B0(n3611), .Y(n3615) );
NOR2XLTS U2308 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n2548) );
NOR2XLTS U2309 ( .A(n3898), .B(n3938), .Y(n3899) );
OAI211XLTS U2310 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n2565), .B0(n2564), .C0(n2563), .Y(n2566) );
NOR2XLTS U2311 ( .A(n4040), .B(n4008), .Y(n4002) );
INVX2TS U2312 ( .A(n4552), .Y(n2344) );
OAI21X1TS U2313 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n4062), .Y(n4481) );
NOR2XLTS U2314 ( .A(n4971), .B(n4970), .Y(n4973) );
NOR2XLTS U2315 ( .A(n4971), .B(n4964), .Y(n4965) );
NOR2XLTS U2316 ( .A(n4971), .B(n4955), .Y(n4956) );
NOR2XLTS U2317 ( .A(n4971), .B(n4884), .Y(n4885) );
OR2X1TS U2318 ( .A(n3092), .B(n4798), .Y(n2203) );
OAI211XLTS U2319 ( .A0(n3705), .A1(n3696), .B0(n3635), .C0(n3634), .Y(n1793)
);
OAI211XLTS U2320 ( .A0(n4519), .A1(n3235), .B0(n3196), .C0(n3195), .Y(n2134)
);
OAI211XLTS U2321 ( .A0(n3356), .A1(n5126), .B0(n3337), .C0(n3336), .Y(n1918)
);
OAI21XLTS U2322 ( .A0(n3199), .A1(n3202), .B0(n3198), .Y(n2130) );
OAI211XLTS U2323 ( .A0(n3356), .A1(n4596), .B0(n3348), .C0(n3347), .Y(n1920)
);
OAI211XLTS U2324 ( .A0(n3328), .A1(n4572), .B0(n3308), .C0(n3307), .Y(n1939)
);
OAI211XLTS U2325 ( .A0(n3311), .A1(n4610), .B0(n3310), .C0(n3309), .Y(n1911)
);
OAI21XLTS U2326 ( .A0(n3614), .A1(n3747), .B0(n3727), .Y(n1462) );
OAI211XLTS U2327 ( .A0(n3356), .A1(n5088), .B0(n3344), .C0(n3343), .Y(n1913)
);
OAI211XLTS U2328 ( .A0(n3124), .A1(n5150), .B0(n3098), .C0(n3097), .Y(n1526)
);
OAI211XLTS U2329 ( .A0(n3705), .A1(n3758), .B0(n3659), .C0(n3658), .Y(n1799)
);
OAI211XLTS U2330 ( .A0(n2342), .A1(n5159), .B0(n3071), .C0(n3070), .Y(n1515)
);
OAI211XLTS U2331 ( .A0(n2342), .A1(n5142), .B0(n3074), .C0(n3073), .Y(n1514)
);
OAI211XLTS U2332 ( .A0(n2343), .A1(n5144), .B0(n3069), .C0(n3068), .Y(n1510)
);
OAI211XLTS U2333 ( .A0(n2342), .A1(n5155), .B0(n3100), .C0(n3099), .Y(n1525)
);
OAI21XLTS U2334 ( .A0(n3585), .A1(n3743), .B0(n3723), .Y(n1218) );
OAI21XLTS U2335 ( .A0(n3584), .A1(n3743), .B0(n3725), .Y(n1234) );
OAI21XLTS U2336 ( .A0(n3527), .A1(n3751), .B0(n3722), .Y(n1254) );
OAI21XLTS U2337 ( .A0(n3550), .A1(n3751), .B0(n3737), .Y(n1270) );
OAI21XLTS U2338 ( .A0(n2420), .A1(n3751), .B0(n3724), .Y(n1297) );
OAI21XLTS U2339 ( .A0(n3505), .A1(n3655), .B0(n3639), .Y(n1313) );
OAI21XLTS U2340 ( .A0(n3545), .A1(n3655), .B0(n3645), .Y(n1366) );
OAI21XLTS U2341 ( .A0(n3563), .A1(n3655), .B0(n3654), .Y(n1378) );
OAI21XLTS U2342 ( .A0(n3584), .A1(n3667), .B0(n3632), .Y(n1390) );
OAI21XLTS U2343 ( .A0(n3562), .A1(n3667), .B0(n3663), .Y(n1405) );
OAI21XLTS U2344 ( .A0(n5061), .A1(n3747), .B0(n3714), .Y(n1459) );
OAI211XLTS U2345 ( .A0(n4604), .A1(n5137), .B0(n3206), .C0(n3203), .Y(n2123)
);
OR2X2TS U2346 ( .A(n4658), .B(n3394), .Y(n2194) );
OR2X2TS U2347 ( .A(n3711), .B(n3701), .Y(n2195) );
INVX2TS U2348 ( .A(n2195), .Y(n2196) );
CLKBUFX3TS U2349 ( .A(n4416), .Y(n2268) );
OAI21X1TS U2350 ( .A0(n4659), .A1(n3711), .B0(n3710), .Y(n1811) );
OAI211X1TS U2351 ( .A0(n3683), .A1(n2272), .B0(n3682), .C0(n3681), .Y(n1789)
);
OAI211X1TS U2352 ( .A0(n2272), .A1(n3462), .B0(n3461), .C0(n3460), .Y(n1795)
);
OAI21X1TS U2353 ( .A0(n3706), .A1(n2272), .B0(n3396), .Y(n1812) );
OAI211X1TS U2354 ( .A0(n3706), .A1(n2195), .B0(n3700), .C0(n3699), .Y(n1809)
);
OAI211X1TS U2355 ( .A0(n2194), .A1(n3480), .B0(n3469), .C0(n3468), .Y(n1801)
);
OAI211X1TS U2356 ( .A0(n2211), .A1(n3758), .B0(n3676), .C0(n3675), .Y(n1798)
);
OAI211X1TS U2357 ( .A0(n2195), .A1(n3758), .B0(n3757), .C0(n3756), .Y(n1797)
);
OAI211X1TS U2358 ( .A0(n2211), .A1(n3696), .B0(n3673), .C0(n3672), .Y(n1792)
);
OAI211X1TS U2359 ( .A0(n3706), .A1(n2211), .B0(n3679), .C0(n3678), .Y(n1810)
);
OAI211X1TS U2360 ( .A0(n2211), .A1(n3689), .B0(n3670), .C0(n3669), .Y(n1803)
);
OAI211X1TS U2361 ( .A0(n2194), .A1(n3758), .B0(n3481), .C0(n3482), .Y(n1800)
);
OAI211X1TS U2362 ( .A0(n2194), .A1(n3689), .B0(n3441), .C0(n3440), .Y(n1805)
);
OAI211X1TS U2363 ( .A0(n2272), .A1(n3650), .B0(n3649), .C0(n3648), .Y(n1796)
);
OAI211X1TS U2364 ( .A0(n3705), .A1(n3689), .B0(n3638), .C0(n3637), .Y(n1804)
);
OAI211X1TS U2365 ( .A0(n3680), .A1(n2272), .B0(n3448), .C0(n3447), .Y(n1790)
);
OAI211X1TS U2366 ( .A0(n2272), .A1(n3696), .B0(n3458), .C0(n3457), .Y(n1794)
);
OAI211X1TS U2367 ( .A0(n2194), .A1(n3438), .B0(n3430), .C0(n3429), .Y(n1806)
);
OAI211X1TS U2368 ( .A0(n2194), .A1(n3478), .B0(n3477), .C0(n3476), .Y(n1808)
);
OAI211X1TS U2369 ( .A0(n2195), .A1(n3689), .B0(n3688), .C0(n3687), .Y(n1802)
);
NAND3X1TS U2370 ( .A(n3683), .B(n2576), .C(n2575), .Y(n1788) );
OAI211X1TS U2371 ( .A0(n2195), .A1(n3696), .B0(n3695), .C0(n3694), .Y(n1791)
);
AOI22X2TS U2372 ( .A0(n4088), .A1(n2693), .B0(FPADDSUB_Raw_mant_NRM_SWR[25]),
.B1(n4505), .Y(n4089) );
INVX3TS U2373 ( .A(n2195), .Y(n2334) );
AOI21X2TS U2374 ( .A0(n4085), .A1(n4084), .B0(n4083), .Y(n4086) );
OAI21X1TS U2375 ( .A0(n3526), .A1(n3747), .B0(n3746), .Y(n1304) );
OAI21X1TS U2376 ( .A0(n3563), .A1(n3751), .B0(n3740), .Y(n1250) );
OAI21X1TS U2377 ( .A0(n3557), .A1(n3743), .B0(n3739), .Y(n1246) );
OAI21X1TS U2378 ( .A0(n3522), .A1(n3743), .B0(n3738), .Y(n1242) );
OAI21X1TS U2379 ( .A0(n3598), .A1(n3743), .B0(n3735), .Y(n1210) );
OAI21X1TS U2380 ( .A0(n2420), .A1(n3759), .B0(n3631), .Y(n1299) );
OAI21X1TS U2381 ( .A0(n3558), .A1(n3751), .B0(n3731), .Y(n1262) );
OAI21X1TS U2382 ( .A0(n3544), .A1(n3751), .B0(n3728), .Y(n1283) );
OAI21X1TS U2383 ( .A0(n3562), .A1(n3743), .B0(n3720), .Y(n1214) );
OAI21X1TS U2384 ( .A0(n3545), .A1(n3751), .B0(n3736), .Y(n1266) );
OAI21X1TS U2385 ( .A0(n2423), .A1(n3743), .B0(n3742), .Y(n1238) );
OAI21X1TS U2386 ( .A0(n3549), .A1(n3751), .B0(n3721), .Y(n1258) );
OAI21X1TS U2387 ( .A0(n3591), .A1(n3743), .B0(n3732), .Y(n1222) );
OAI21X1TS U2388 ( .A0(n3510), .A1(n3747), .B0(n3719), .Y(n1327) );
OAI21X1TS U2389 ( .A0(n3510), .A1(n3655), .B0(n3628), .Y(n1329) );
OAI21X1TS U2390 ( .A0(n5068), .A1(n3747), .B0(n3713), .Y(n1461) );
OAI21X1TS U2391 ( .A0(n3505), .A1(n3747), .B0(n3729), .Y(n1311) );
OAI21X1TS U2392 ( .A0(n3591), .A1(n3667), .B0(n3643), .Y(n1399) );
OAI21X1TS U2393 ( .A0(n3590), .A1(n3743), .B0(n3730), .Y(n1230) );
OAI21X1TS U2394 ( .A0(n3521), .A1(n3751), .B0(n3750), .Y(n1276) );
OAI21X1TS U2395 ( .A0(n3550), .A1(n3655), .B0(n3652), .Y(n1272) );
OAI21X1TS U2396 ( .A0(n4906), .A1(n3751), .B0(n3718), .Y(n1290) );
OAI21X1TS U2397 ( .A0(n5059), .A1(n3747), .B0(n3715), .Y(n1460) );
OAI21X1TS U2398 ( .A0(n3557), .A1(n3655), .B0(n3653), .Y(n1381) );
OAI21X1TS U2399 ( .A0(n3527), .A1(n3655), .B0(n3629), .Y(n1375) );
OAI21X1TS U2400 ( .A0(n3549), .A1(n3655), .B0(n3630), .Y(n1372) );
OAI21X1TS U2401 ( .A0(n3522), .A1(n3655), .B0(n3651), .Y(n1384) );
OAI21X1TS U2402 ( .A0(n3558), .A1(n3655), .B0(n3642), .Y(n1369) );
OAI21X1TS U2403 ( .A0(n3511), .A1(n3667), .B0(n3657), .Y(n1387) );
OAI21X1TS U2404 ( .A0(n5051), .A1(n3747), .B0(n3716), .Y(n1463) );
OAI21X1TS U2405 ( .A0(n4997), .A1(n3747), .B0(n3717), .Y(n1464) );
OAI21X1TS U2406 ( .A0(n5060), .A1(n3747), .B0(n3726), .Y(n1465) );
OAI21X1TS U2407 ( .A0(n3586), .A1(n3667), .B0(n3644), .Y(n1396) );
OAI21X1TS U2408 ( .A0(n3590), .A1(n3667), .B0(n3641), .Y(n1393) );
OAI21X1TS U2409 ( .A0(n3586), .A1(n3743), .B0(n3734), .Y(n1226) );
OAI21X1TS U2410 ( .A0(n3598), .A1(n3667), .B0(n3666), .Y(n1408) );
OAI21X1TS U2411 ( .A0(n3585), .A1(n3667), .B0(n3664), .Y(n1402) );
OAI21X1TS U2412 ( .A0(n5280), .A1(n4566), .B0(n3358), .Y(n1357) );
INVX3TS U2413 ( .A(n3759), .Y(n3749) );
OAI21X1TS U2414 ( .A0(n3357), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n4862),
.Y(n3358) );
INVX3TS U2415 ( .A(n3626), .Y(n3661) );
INVX3TS U2416 ( .A(n3759), .Y(n3745) );
INVX3TS U2417 ( .A(n3759), .Y(n3741) );
XNOR2X1TS U2418 ( .A(DP_OP_234J1_127_8543_n1), .B(n3960), .Y(n3962) );
OAI21X1TS U2419 ( .A0(n3146), .A1(n2538), .B0(n3145), .Y(n2076) );
NAND2X4TS U2420 ( .A(FPMULT_Op_MX[11]), .B(intadd_5_n1), .Y(n2624) );
OAI21X1TS U2421 ( .A0(n3146), .A1(n4507), .B0(n3144), .Y(n1331) );
INVX3TS U2422 ( .A(n3626), .Y(n3656) );
OAI211X1TS U2423 ( .A0(n3297), .A1(n4592), .B0(n3244), .C0(n3243), .Y(n1923)
);
OAI211X1TS U2424 ( .A0(n3297), .A1(n4588), .B0(n3256), .C0(n3255), .Y(n1925)
);
OAI211X1TS U2425 ( .A0(n3297), .A1(n4590), .B0(n3258), .C0(n3257), .Y(n1924)
);
OAI21X1TS U2426 ( .A0(n3133), .A1(n2538), .B0(n3131), .Y(n2077) );
OAI211X1TS U2427 ( .A0(n3311), .A1(n5125), .B0(n3296), .C0(n3295), .Y(n1912)
);
INVX2TS U2428 ( .A(n2456), .Y(n4862) );
NAND3BX1TS U2429 ( .AN(FPMULT_Exp_module_Data_S[7]), .B(n4743), .C(n4068),
.Y(n4069) );
OAI211X1TS U2430 ( .A0(n3329), .A1(n4585), .B0(n3260), .C0(n3259), .Y(n1929)
);
OAI211X1TS U2431 ( .A0(n3328), .A1(n4575), .B0(n3313), .C0(n3312), .Y(n1936)
);
OAI211X1TS U2432 ( .A0(n3329), .A1(n4582), .B0(n3254), .C0(n3253), .Y(n1931)
);
OAI211X1TS U2433 ( .A0(n3328), .A1(n4573), .B0(n3321), .C0(n3320), .Y(n1938)
);
OAI211X1TS U2434 ( .A0(n3297), .A1(n4586), .B0(n3246), .C0(n3245), .Y(n1928)
);
OAI211X1TS U2435 ( .A0(n3329), .A1(n4581), .B0(n3248), .C0(n3247), .Y(n1932)
);
OAI211X1TS U2436 ( .A0(n3328), .A1(n2395), .B0(n3318), .C0(n3317), .Y(n1941)
);
OAI211X1TS U2437 ( .A0(n3328), .A1(n4570), .B0(n3304), .C0(n3303), .Y(n1940)
);
OAI211X1TS U2438 ( .A0(n3328), .A1(n2385), .B0(n3300), .C0(n3299), .Y(n1934)
);
OAI211X1TS U2439 ( .A0(n3297), .A1(n2380), .B0(n3263), .C0(n3262), .Y(n1927)
);
OAI211X1TS U2440 ( .A0(n3328), .A1(n4576), .B0(n3302), .C0(n3301), .Y(n1935)
);
OAI211X1TS U2441 ( .A0(n3328), .A1(n4579), .B0(n3327), .C0(n3326), .Y(n1933)
);
OAI211X1TS U2442 ( .A0(n3328), .A1(n4574), .B0(n3306), .C0(n3305), .Y(n1937)
);
NAND3X1TS U2443 ( .A(n4644), .B(n4643), .C(n4642), .Y(n1824) );
NAND3X1TS U2444 ( .A(n4618), .B(n4617), .C(n4620), .Y(n1837) );
NAND3X1TS U2445 ( .A(n4648), .B(n4647), .C(n4646), .Y(n1822) );
NAND3X1TS U2446 ( .A(n4651), .B(n4650), .C(n4655), .Y(n1817) );
NAND3X1TS U2447 ( .A(n4638), .B(n4637), .C(n4636), .Y(n1826) );
OAI211X1TS U2448 ( .A0(n3328), .A1(n4568), .B0(n3315), .C0(n3314), .Y(n1942)
);
OAI211X1TS U2449 ( .A0(n3311), .A1(n2393), .B0(n3291), .C0(n3290), .Y(n1844)
);
NAND3X1TS U2450 ( .A(n4635), .B(n4634), .C(n4642), .Y(n1827) );
OAI211X1TS U2451 ( .A0(n3297), .A1(n4587), .B0(n3252), .C0(n3251), .Y(n1926)
);
OAI211X1TS U2452 ( .A0(n3329), .A1(n4583), .B0(n3250), .C0(n3249), .Y(n1930)
);
OAI211X1TS U2453 ( .A0(n3311), .A1(n2389), .B0(n3294), .C0(n3293), .Y(n1834)
);
NAND3X1TS U2454 ( .A(n4640), .B(n4639), .C(n4646), .Y(n1825) );
NAND3X1TS U2455 ( .A(n4622), .B(n4621), .C(n4620), .Y(n1833) );
NAND3X1TS U2456 ( .A(n4627), .B(n4626), .C(n4625), .Y(n1830) );
AOI222X1TS U2457 ( .A0(n4564), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n3238), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n4607), .Y(n3239)
);
NAND3X1TS U2458 ( .A(n4629), .B(n4628), .C(n4642), .Y(n1829) );
NAND3X1TS U2459 ( .A(n4657), .B(n4656), .C(n4655), .Y(n1815) );
NAND3X1TS U2460 ( .A(n4632), .B(n4631), .C(n4630), .Y(n1828) );
NAND3X1TS U2461 ( .A(n4613), .B(n4612), .C(n4630), .Y(n1841) );
NAND3X1TS U2462 ( .A(n4653), .B(n4652), .C(n4655), .Y(n1816) );
NAND3X1TS U2463 ( .A(n4615), .B(n4614), .C(n4625), .Y(n1839) );
NAND3X1TS U2464 ( .A(n4624), .B(n4623), .C(n4636), .Y(n1831) );
OAI21X1TS U2465 ( .A0(n4507), .A1(n3133), .B0(n3132), .Y(n1323) );
OAI211X1TS U2466 ( .A0(n3297), .A1(n2402), .B0(n3265), .C0(n3264), .Y(n1818)
);
OAI211X1TS U2467 ( .A0(n3356), .A1(n5092), .B0(n3335), .C0(n3334), .Y(n1915)
);
AOI22X1TS U2468 ( .A0(Data_2[10]), .A1(n4633), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n4619), .Y(n3294) );
OAI211X1TS U2469 ( .A0(n3329), .A1(n2401), .B0(n3268), .C0(n3267), .Y(n1819)
);
OAI211X2TS U2470 ( .A0(n3138), .A1(n3209), .B0(n2551), .C0(n2550), .Y(n2552)
);
OAI211X1TS U2471 ( .A0(n3356), .A1(n4593), .B0(n3355), .C0(n3354), .Y(n1922)
);
OAI211X1TS U2472 ( .A0(n3356), .A1(n5127), .B0(n3339), .C0(n3338), .Y(n1917)
);
OAI211X1TS U2473 ( .A0(n3356), .A1(n4996), .B0(n3346), .C0(n3345), .Y(n1919)
);
OR2X4TS U2474 ( .A(n4942), .B(n4904), .Y(n2435) );
NAND2X2TS U2475 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .B(n4942), .Y(n3626) );
OAI211X1TS U2476 ( .A0(n3356), .A1(n5128), .B0(n3333), .C0(n3332), .Y(n1916)
);
OAI211X1TS U2477 ( .A0(n3329), .A1(n4555), .B0(n3270), .C0(n3269), .Y(n1821)
);
OAI211X1TS U2478 ( .A0(n3356), .A1(n5089), .B0(n3331), .C0(n3330), .Y(n1914)
);
OAI211X1TS U2479 ( .A0(n3356), .A1(n4594), .B0(n3350), .C0(n3349), .Y(n1921)
);
OAI211X1TS U2480 ( .A0(n3329), .A1(n2392), .B0(n3272), .C0(n3271), .Y(n1820)
);
OAI211X1TS U2481 ( .A0(n3329), .A1(n2390), .B0(n3274), .C0(n3273), .Y(n1823)
);
OAI211X1TS U2482 ( .A0(n2342), .A1(n5158), .B0(n3052), .C0(n3051), .Y(n1516)
);
OAI211X1TS U2483 ( .A0(n2343), .A1(n5134), .B0(n3082), .C0(n3081), .Y(n1506)
);
OAI211X1TS U2484 ( .A0(n2343), .A1(n5160), .B0(n3057), .C0(n3056), .Y(n1512)
);
OAI211X1TS U2485 ( .A0(n2343), .A1(n5153), .B0(n3103), .C0(n3102), .Y(n1513)
);
OAI211X1TS U2486 ( .A0(n2342), .A1(n5146), .B0(n3110), .C0(n3109), .Y(n1508)
);
OAI21X1TS U2487 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n2549), .Y(n2550) );
OAI211X1TS U2488 ( .A0(n2342), .A1(n5145), .B0(n3118), .C0(n3117), .Y(n1509)
);
OAI211X1TS U2489 ( .A0(n2342), .A1(n5143), .B0(n3123), .C0(n3122), .Y(n1511)
);
OAI211X1TS U2490 ( .A0(n2343), .A1(n5131), .B0(n3067), .C0(n3066), .Y(n1528)
);
OAI211X1TS U2491 ( .A0(n3124), .A1(n5151), .B0(n3090), .C0(n3089), .Y(n1520)
);
AOI222X1TS U2492 ( .A0(n3381), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n3384), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n3383), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n3382) );
OAI211X1TS U2493 ( .A0(n4765), .A1(n3061), .B0(n3060), .C0(n3059), .Y(n1524)
);
OAI211X1TS U2494 ( .A0(n3124), .A1(n5148), .B0(n3106), .C0(n3105), .Y(n1522)
);
OAI211X1TS U2495 ( .A0(n3124), .A1(n5157), .B0(n3055), .C0(n3054), .Y(n1518)
);
OAI211X1TS U2496 ( .A0(n3124), .A1(n5156), .B0(n3064), .C0(n3063), .Y(n1519)
);
OAI211X1TS U2497 ( .A0(n2343), .A1(n5152), .B0(n3095), .C0(n3094), .Y(n1517)
);
OAI211X1TS U2498 ( .A0(n2342), .A1(n5154), .B0(n3116), .C0(n3115), .Y(n1527)
);
OAI211X1TS U2499 ( .A0(n2343), .A1(n5149), .B0(n3087), .C0(n3086), .Y(n1521)
);
OAI211X1TS U2500 ( .A0(n2343), .A1(n5147), .B0(n3084), .C0(n3083), .Y(n1507)
);
OAI211X1TS U2501 ( .A0(n4604), .A1(n5135), .B0(n3237), .C0(n3236), .Y(n2133)
);
BUFX6TS U2502 ( .A(n3397), .Y(n3503) );
OAI211X1TS U2503 ( .A0(n4604), .A1(n5140), .B0(n3236), .C0(n3235), .Y(n2127)
);
AOI21X2TS U2504 ( .A0(n4145), .A1(n4141), .B0(n2468), .Y(n4136) );
ADDFX1TS U2505 ( .A(FPMULT_Op_MY[13]), .B(n2794), .CI(n2793), .CO(n2795),
.S(n2788) );
INVX3TS U2506 ( .A(n2603), .Y(n3297) );
OAI211X1TS U2507 ( .A0(n4991), .A1(n3202), .B0(n3204), .C0(n3201), .Y(n2132)
);
OAI211X1TS U2508 ( .A0(n3218), .A1(n3206), .B0(n3205), .C0(n3204), .Y(n2128)
);
NAND2BX1TS U2509 ( .AN(n3234), .B(n3233), .Y(n3236) );
INVX2TS U2510 ( .A(n4532), .Y(n4531) );
NOR2X1TS U2511 ( .A(n4971), .B(n4952), .Y(n4953) );
NOR2X1TS U2512 ( .A(n4971), .B(n4958), .Y(n4959) );
NAND3X1TS U2513 ( .A(n3197), .B(n4991), .C(n3233), .Y(n3196) );
NOR2X1TS U2514 ( .A(n4971), .B(n4961), .Y(n4962) );
OAI2BB2XLTS U2515 ( .B0(n4611), .B1(n2380), .A0N(n4591), .A1N(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1877) );
NOR2X1TS U2516 ( .A(n4971), .B(n4881), .Y(n4882) );
OAI21X1TS U2517 ( .A0(n3618), .A1(n3617), .B0(n3616), .Y(n3619) );
NOR2X4TS U2518 ( .A(n2260), .B(n4448), .Y(n2638) );
INVX3TS U2519 ( .A(n4608), .Y(n4551) );
INVX3TS U2520 ( .A(n4578), .Y(n3381) );
INVX3TS U2521 ( .A(n4608), .Y(n3374) );
NOR2X4TS U2522 ( .A(n4798), .B(n4743), .Y(n3957) );
AOI21X2TS U2523 ( .A0(n4164), .A1(n2507), .B0(n2506), .Y(n4153) );
AOI21X2TS U2524 ( .A0(n4166), .A1(n4162), .B0(n2467), .Y(n4155) );
BUFX3TS U2525 ( .A(n4527), .Y(n4529) );
NAND3X1TS U2526 ( .A(n3452), .B(n3451), .C(n3450), .Y(n3462) );
NAND3X1TS U2527 ( .A(n3419), .B(n3418), .C(n3417), .Y(n3438) );
NAND3X1TS U2528 ( .A(n3422), .B(n3421), .C(n3420), .Y(n3436) );
NAND3X1TS U2529 ( .A(n3455), .B(n3454), .C(n3453), .Y(n3650) );
NAND3X1TS U2530 ( .A(n3425), .B(n3424), .C(n3423), .Y(n3478) );
NOR2X1TS U2531 ( .A(n3582), .B(n3612), .Y(n3583) );
OAI222X1TS U2532 ( .A0(n2538), .A1(FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n3479), .B1(FPADDSUB_Raw_mant_NRM_SWR[13]), .C0(FPADDSUB_DmP_mant_SHT1_SW[11]), .C1(
n3646), .Y(n3480) );
NAND2X4TS U2533 ( .A(n4501), .B(n4481), .Y(n3279) );
INVX3TS U2534 ( .A(n4567), .Y(n4611) );
INVX3TS U2535 ( .A(n4567), .Y(n4603) );
NOR2X1TS U2536 ( .A(n4033), .B(n4053), .Y(n4054) );
NOR2X1TS U2537 ( .A(n4033), .B(n4057), .Y(n4059) );
INVX3TS U2538 ( .A(n4811), .Y(n3961) );
INVX3TS U2539 ( .A(n4713), .Y(n3959) );
CLKBUFX2TS U2540 ( .A(n2627), .Y(n2248) );
NAND3X1TS U2541 ( .A(FPSENCOS_cont_iter_out[1]), .B(n4602), .C(n3199), .Y(
n4523) );
INVX3TS U2542 ( .A(n3392), .Y(n3753) );
INVX3TS U2543 ( .A(n3702), .Y(n3471) );
NOR2X1TS U2544 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n2476) );
INVX3TS U2545 ( .A(n3470), .Y(n3479) );
NOR2X1TS U2546 ( .A(n4053), .B(n4008), .Y(n3975) );
OAI21X1TS U2547 ( .A0(n3572), .A1(n3571), .B0(n3570), .Y(n3573) );
CLKBUFX2TS U2548 ( .A(mult_x_219_n129), .Y(n2351) );
INVX2TS U2549 ( .A(n4746), .Y(n4707) );
INVX3TS U2550 ( .A(n3702), .Y(n3467) );
INVX3TS U2551 ( .A(n3960), .Y(n2361) );
INVX3TS U2552 ( .A(n3923), .Y(n3946) );
NAND3X1TS U2553 ( .A(n2588), .B(FPMULT_FS_Module_state_reg[1]), .C(
FPMULT_FSM_add_overflow_flag), .Y(n2590) );
AND2X2TS U2554 ( .A(n2770), .B(FPMULT_FS_Module_state_reg[1]), .Y(n3049) );
NAND2X4TS U2555 ( .A(n2327), .B(n2281), .Y(n4033) );
AND2X2TS U2556 ( .A(n2265), .B(FPADDSUB_OP_FLAG_SFG), .Y(n4160) );
NOR2X4TS U2557 ( .A(n4259), .B(FPADDSUB_OP_FLAG_SFG), .Y(n2693) );
OAI33X4TS U2558 ( .A0(n2309), .A1(FPMULT_Op_MX[16]), .A2(n2289), .B0(n2308),
.B1(n5057), .B2(n2292), .Y(n2628) );
NAND3X1TS U2559 ( .A(n2562), .B(FPADDSUB_Raw_mant_NRM_SWR[16]), .C(n5055),
.Y(n2563) );
INVX3TS U2560 ( .A(n3392), .Y(n3691) );
INVX3TS U2561 ( .A(n3923), .Y(n3920) );
NAND2BX1TS U2562 ( .AN(FPSENCOS_d_ff2_X[23]), .B(n4553), .Y(intadd_8_CI) );
NAND4BX1TS U2563 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(n3080), .D(n5034), .Y(
n2536) );
INVX3TS U2564 ( .A(n2326), .Y(n2327) );
NOR2X1TS U2565 ( .A(n3580), .B(n3600), .Y(n3581) );
OAI32X1TS U2566 ( .A0(n4948), .A1(FPADDSUB_intDX_EWSW[31]), .A2(n4951), .B0(
FPADDSUB_Shift_reg_FLAGS_7_6), .B1(FPADDSUB_OP_FLAG_EXP), .Y(n4949) );
INVX2TS U2567 ( .A(n2264), .Y(n2265) );
OR2X4TS U2568 ( .A(n4855), .B(n3646), .Y(n3392) );
CLKBUFX3TS U2569 ( .A(n2613), .Y(n2352) );
INVX3TS U2570 ( .A(n4856), .Y(n4858) );
AND2X2TS U2571 ( .A(n4072), .B(n4071), .Y(n4747) );
INVX3TS U2572 ( .A(n4947), .Y(n4507) );
INVX3TS U2573 ( .A(n4947), .Y(n3472) );
INVX1TS U2574 ( .A(n4072), .Y(n2594) );
INVX3TS U2575 ( .A(n4554), .Y(n4553) );
AND2X2TS U2576 ( .A(FPADDSUB_intDY_EWSW[30]), .B(n3624), .Y(n2386) );
OR2X2TS U2577 ( .A(FPADDSUB_intDY_EWSW[30]), .B(n3624), .Y(n2387) );
INVX3TS U2578 ( .A(n4871), .Y(n4975) );
INVX3TS U2579 ( .A(FPADDSUB_left_right_SHT2), .Y(n2326) );
INVX3TS U2580 ( .A(n4871), .Y(n4901) );
NAND3X1TS U2581 ( .A(n4464), .B(n4463), .C(n4462), .Y(n5171) );
CLKINVX3TS U2582 ( .A(n2318), .Y(n2198) );
INVX3TS U2583 ( .A(n5091), .Y(n4070) );
NOR2X1TS U2584 ( .A(n5000), .B(n5083), .Y(FPMULT_S_Oper_A_exp[8]) );
NAND3X2TS U2585 ( .A(n5049), .B(FPSENCOS_cont_var_out[0]), .C(ready_add_subt), .Y(n4534) );
NOR2X2TS U2586 ( .A(n5048), .B(n5170), .Y(n2232) );
INVX3TS U2587 ( .A(n5287), .Y(n4976) );
CLKINVX2TS U2588 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n4063) );
INVX1TS U2589 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n4687) );
AND3X2TS U2590 ( .A(n4988), .B(FPSENCOS_cont_var_out[1]), .C(ready_add_subt),
.Y(n4533) );
NAND2X4TS U2591 ( .A(n4485), .B(n4496), .Y(n3147) );
AND2X4TS U2592 ( .A(n4862), .B(n4861), .Y(n4866) );
OAI2BB1X2TS U2593 ( .A0N(n4159), .A1N(n4090), .B0(n4089), .Y(n1411) );
OAI22X4TS U2594 ( .A0(n3646), .A1(FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(
n3702), .B1(n4066), .Y(n3701) );
AOI21X4TS U2595 ( .A0(n2530), .A1(n2527), .B0(n2472), .Y(n4087) );
OAI21X4TS U2596 ( .A0(n4097), .A1(n4091), .B0(n4092), .Y(n2530) );
OAI21X2TS U2597 ( .A0(n2681), .A1(n2462), .B0(n2461), .Y(n4197) );
MX2X1TS U2598 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
CLKAND2X2TS U2599 ( .A(n5113), .B(FPADDSUB_DMP_SFG[20]), .Y(n2522) );
MX2X1TS U2600 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U2601 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
OAI21X1TS U2602 ( .A0(n3951), .A1(n5035), .B0(n3897), .Y(n3937) );
NOR2X1TS U2603 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n2554), .Y(n3140) );
NOR2BX2TS U2604 ( .AN(n2600), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n3080) );
BUFX3TS U2605 ( .A(n3266), .Y(n4682) );
BUFX3TS U2606 ( .A(n3319), .Y(n4679) );
MX2X1TS U2607 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U2608 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
MX2X1TS U2609 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
CLKAND2X2TS U2610 ( .A(n5114), .B(FPADDSUB_DMP_SFG[18]), .Y(n2518) );
CLKAND2X2TS U2611 ( .A(n5116), .B(FPADDSUB_DMP_SFG[14]), .Y(n2510) );
INVX2TS U2612 ( .A(n3759), .Y(n3765) );
NOR2X1TS U2613 ( .A(FPADDSUB_intDY_EWSW[8]), .B(n3527), .Y(n3529) );
NOR2X1TS U2614 ( .A(n3519), .B(n3529), .Y(n3533) );
NOR2XLTS U2615 ( .A(FPADDSUB_intDY_EWSW[7]), .B(n3526), .Y(n3519) );
NOR2X1TS U2616 ( .A(FPADDSUB_intDY_EWSW[16]), .B(n3563), .Y(n3566) );
NOR2X1TS U2617 ( .A(FPADDSUB_intDY_EWSW[12]), .B(n3550), .Y(n3553) );
NOR2X1TS U2618 ( .A(FPADDSUB_intDY_EWSW[14]), .B(n3558), .Y(n3561) );
NOR2X1TS U2619 ( .A(n3566), .B(n3541), .Y(n3568) );
NOR2XLTS U2620 ( .A(FPADDSUB_intDY_EWSW[15]), .B(n3562), .Y(n3541) );
NOR2X1TS U2621 ( .A(FPADDSUB_intDY_EWSW[10]), .B(n3545), .Y(n3548) );
NOR2X1TS U2622 ( .A(n3553), .B(n3537), .Y(n3556) );
NOR2XLTS U2623 ( .A(FPADDSUB_intDY_EWSW[11]), .B(n3549), .Y(n3537) );
AOI21X1TS U2624 ( .A0(n2378), .A1(n2377), .B0(n2379), .Y(n3605) );
CLKAND2X2TS U2625 ( .A(FPADDSUB_intDY_EWSW[26]), .B(n3604), .Y(n2379) );
CLKAND2X2TS U2626 ( .A(FPADDSUB_intDY_EWSW[25]), .B(n3603), .Y(n2377) );
NOR2X1TS U2627 ( .A(FPADDSUB_intDY_EWSW[21]), .B(n3591), .Y(n3594) );
NOR2X1TS U2628 ( .A(FPADDSUB_intDY_EWSW[23]), .B(n5053), .Y(n3600) );
NOR2X1TS U2629 ( .A(n3607), .B(n3579), .Y(n3610) );
NOR2XLTS U2630 ( .A(FPADDSUB_intDY_EWSW[24]), .B(n3602), .Y(n3579) );
OAI21XLTS U2631 ( .A0(n2758), .A1(n2762), .B0(n2759), .Y(n2459) );
AOI21X1TS U2632 ( .A0(n2690), .A1(n2458), .B0(n2457), .Y(n2681) );
NOR2XLTS U2633 ( .A(n4226), .B(n2686), .Y(n2458) );
OAI21XLTS U2634 ( .A0(n2686), .A1(n4227), .B0(n2687), .Y(n2457) );
AOI21X1TS U2635 ( .A0(n3575), .A1(n3574), .B0(n3573), .Y(n3618) );
NOR2XLTS U2636 ( .A(n3543), .B(n3571), .Y(n3574) );
OAI21XLTS U2637 ( .A0(n3536), .A1(n3535), .B0(n3534), .Y(n3575) );
AOI21X1TS U2638 ( .A0(n3615), .A1(n2382), .B0(n2381), .Y(n3616) );
CLKAND2X2TS U2639 ( .A(FPADDSUB_intDY_EWSW[27]), .B(n3614), .Y(n2381) );
AOI21X1TS U2640 ( .A0(n3597), .A1(n3596), .B0(n3595), .Y(n3613) );
NAND2X1TS U2641 ( .A(n3583), .B(n2382), .Y(n3617) );
NAND2X1TS U2642 ( .A(n3596), .B(n3578), .Y(n3582) );
NOR2XLTS U2643 ( .A(n3577), .B(n3588), .Y(n3578) );
AOI21X1TS U2644 ( .A0(n3900), .A1(n3937), .B0(n3899), .Y(n3929) );
NOR2XLTS U2645 ( .A(n3898), .B(n5037), .Y(n3900) );
INVX2TS U2646 ( .A(n2690), .Y(n4232) );
OAI21XLTS U2647 ( .A0(n2491), .A1(n2700), .B0(n2490), .Y(n2492) );
INVX2TS U2648 ( .A(operation[1]), .Y(n4485) );
AO22XLTS U2649 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n2273), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n2287), .Y(n4007) );
AO22XLTS U2650 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n2287), .B0(
FPADDSUB_Data_array_SWR[18]), .B1(n2257), .Y(n3997) );
AO22XLTS U2651 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n2273), .B0(
FPADDSUB_Data_array_SWR[3]), .B1(n2278), .Y(n3984) );
AO22XLTS U2652 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2257), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n2278), .Y(n3991) );
AO22XLTS U2653 ( .A0(FPADDSUB_Data_array_SWR[6]), .A1(n2287), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n2278), .Y(n3978) );
AO22XLTS U2654 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n2257), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n2278), .Y(n3994) );
AO22XLTS U2655 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2258), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n2287), .Y(n4004) );
INVX2TS U2656 ( .A(n3974), .Y(n4010) );
INVX2TS U2657 ( .A(n2534), .Y(n2606) );
NAND4BX1TS U2658 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(n3080),
.C(n5034), .D(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n4500) );
OR2X2TS U2659 ( .A(n3279), .B(n4485), .Y(n3241) );
CLKBUFX2TS U2660 ( .A(n4598), .Y(n4578) );
OAI21XLTS U2661 ( .A0(n2764), .A1(n2763), .B0(n2762), .Y(n2766) );
AOI2BB2XLTS U2662 ( .B0(n3471), .B1(n5038), .A0N(
FPADDSUB_Shift_reg_FLAGS_7[1]), .A1N(FPADDSUB_DmP_mant_SHT1_SW[15]),
.Y(n3437) );
INVX2TS U2663 ( .A(n4179), .Y(n4181) );
NOR3XLTS U2664 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n4460) );
CLKAND2X2TS U2665 ( .A(n5112), .B(FPADDSUB_DMP_SFG[22]), .Y(n4083) );
NAND2X1TS U2666 ( .A(n4516), .B(n4494), .Y(n4482) );
NAND3XLTS U2667 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[29]), .Y(n4475) );
AOI31XLTS U2668 ( .A0(n4473), .A1(n4472), .A2(n4471), .B0(n4478), .Y(n4476)
);
NAND4BXLTS U2669 ( .AN(n4734), .B(n4733), .C(n2316), .D(n5066), .Y(n4735) );
NAND4XLTS U2670 ( .A(n4731), .B(n4730), .C(n4729), .D(n4728), .Y(n4736) );
NAND3XLTS U2671 ( .A(n4715), .B(n2373), .C(n5024), .Y(n4721) );
BUFX3TS U2672 ( .A(n3626), .Y(n3751) );
OAI21X2TS U2673 ( .A0(n4107), .A1(n4101), .B0(n4102), .Y(n4079) );
OAI21X2TS U2674 ( .A0(n4117), .A1(n4111), .B0(n4112), .Y(n4126) );
CLKAND2X2TS U2675 ( .A(n5115), .B(FPADDSUB_DMP_SFG[16]), .Y(n2514) );
NAND4XLTS U2676 ( .A(n3139), .B(n3138), .C(n3442), .D(n5017), .Y(n3143) );
OAI21X2TS U2677 ( .A0(n4136), .A1(n4130), .B0(n4131), .Y(n4175) );
INVX2TS U2678 ( .A(n4130), .Y(n4132) );
CLKAND2X2TS U2679 ( .A(n5117), .B(FPADDSUB_DMP_SFG[12]), .Y(n2506) );
NOR2BX1TS U2680 ( .AN(n2479), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n2480)
);
AOI21X2TS U2681 ( .A0(n3625), .A1(n2387), .B0(n2386), .Y(n4942) );
OAI21X1TS U2682 ( .A0(n3623), .A1(n3622), .B0(n3621), .Y(n3625) );
INVX4TS U2683 ( .A(n4866), .Y(n4967) );
CLKBUFX2TS U2684 ( .A(n4747), .Y(n4847) );
INVX2TS U2685 ( .A(n4847), .Y(n4849) );
AND3X1TS U2686 ( .A(n2574), .B(n2573), .C(n2572), .Y(n3680) );
AND3X1TS U2687 ( .A(n2571), .B(n2570), .C(n2569), .Y(n3693) );
AO22XLTS U2688 ( .A0(FPSENCOS_d_ff2_X[0]), .A1(n4549), .B0(
FPSENCOS_d_ff_Xn[0]), .B1(n2344), .Y(n2006) );
MX2X1TS U2689 ( .A(FPMULT_Add_result[23]), .B(n3902), .S0(n3920), .Y(n1598)
);
AOI222X1TS U2690 ( .A0(n3765), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DMP_EXP_EWSW[23]), .B1(n4944), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n3764), .Y(n3766) );
MX2X1TS U2691 ( .A(FPMULT_Add_result[20]), .B(n3908), .S0(n3920), .Y(n1601)
);
MX2X1TS U2692 ( .A(n3962), .B(FPMULT_Exp_module_Overflow_flag_A), .S0(n3961),
.Y(n1586) );
NAND4BXLTS U2693 ( .AN(n4067), .B(FPMULT_Exp_module_Data_S[6]), .C(
FPMULT_Exp_module_Data_S[5]), .D(FPMULT_Exp_module_Data_S[4]), .Y(
n4068) );
NAND4XLTS U2694 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n4067) );
MX2X1TS U2695 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_exp_oper_result[8]), .S0(n3957), .Y(n1596) );
AO21XLTS U2696 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[25]), .A1(n4945), .B0(n3969),
.Y(n1181) );
AOI2BB2XLTS U2697 ( .B0(FPADDSUB_left_right_SHT2), .B1(n4060), .A0N(n4057),
.A1N(n4008), .Y(n3968) );
NOR2XLTS U2698 ( .A(FPADDSUB_intDY_EWSW[2]), .B(n3505), .Y(n3507) );
NOR2XLTS U2699 ( .A(FPADDSUB_intDY_EWSW[3]), .B(n3510), .Y(n3509) );
NOR2X1TS U2700 ( .A(FPADDSUB_intDY_EWSW[4]), .B(n3511), .Y(n3514) );
AOI32X1TS U2701 ( .A0(FPMULT_Op_MX[0]), .A1(mult_x_254_n225), .A2(
FPMULT_Op_MY[9]), .B0(n2643), .B1(n2339), .Y(n4333) );
NAND2BXLTS U2702 ( .AN(mult_x_219_n162), .B(n4280), .Y(n4281) );
OAI33X1TS U2703 ( .A0(n2283), .A1(FPMULT_Op_MX[20]), .A2(n2349), .B0(n2374),
.B1(n5063), .B2(n2325), .Y(n2841) );
AOI21X1TS U2704 ( .A0(n3517), .A1(n3516), .B0(n3515), .Y(n3536) );
OAI21XLTS U2705 ( .A0(n3514), .A1(n3513), .B0(n3512), .Y(n3515) );
NOR2XLTS U2706 ( .A(n3514), .B(n3509), .Y(n3516) );
OAI21XLTS U2707 ( .A0(n3508), .A1(n3507), .B0(n3506), .Y(n3517) );
AOI21X1TS U2708 ( .A0(n3533), .A1(n3532), .B0(n3531), .Y(n3534) );
OAI21XLTS U2709 ( .A0(n3530), .A1(n3529), .B0(n3528), .Y(n3531) );
OAI21XLTS U2710 ( .A0(n3525), .A1(n3524), .B0(n3523), .Y(n3532) );
NAND2X1TS U2711 ( .A(n3520), .B(n3533), .Y(n3535) );
NOR2XLTS U2712 ( .A(n3518), .B(n3524), .Y(n3520) );
NOR2XLTS U2713 ( .A(FPADDSUB_intDY_EWSW[5]), .B(n3521), .Y(n3518) );
AOI21X1TS U2714 ( .A0(n3569), .A1(n3568), .B0(n3567), .Y(n3570) );
OAI21XLTS U2715 ( .A0(n3561), .A1(n3560), .B0(n3559), .Y(n3569) );
OAI21XLTS U2716 ( .A0(n3566), .A1(n3565), .B0(n3564), .Y(n3567) );
AOI21X1TS U2717 ( .A0(n3556), .A1(n3555), .B0(n3554), .Y(n3572) );
OAI21XLTS U2718 ( .A0(n3548), .A1(n3547), .B0(n3546), .Y(n3555) );
OAI21XLTS U2719 ( .A0(n3553), .A1(n3552), .B0(n3551), .Y(n3554) );
NAND2X1TS U2720 ( .A(n3542), .B(n3568), .Y(n3571) );
NOR2XLTS U2721 ( .A(n3540), .B(n3561), .Y(n3542) );
NOR2XLTS U2722 ( .A(FPADDSUB_intDY_EWSW[13]), .B(n3557), .Y(n3540) );
NAND2X1TS U2723 ( .A(n3556), .B(n3539), .Y(n3543) );
NOR2XLTS U2724 ( .A(n3548), .B(n3538), .Y(n3539) );
NOR2XLTS U2725 ( .A(FPADDSUB_intDY_EWSW[9]), .B(n3544), .Y(n3538) );
OAI21X1TS U2726 ( .A0(n3589), .A1(n3588), .B0(n3587), .Y(n3597) );
AOI21X1TS U2727 ( .A0(n2433), .A1(n2408), .B0(n2432), .Y(n3589) );
OAI21X1TS U2728 ( .A0(n3594), .A1(n3593), .B0(n3592), .Y(n3595) );
AOI21X1TS U2729 ( .A0(n3610), .A1(n3609), .B0(n3608), .Y(n3611) );
OAI21XLTS U2730 ( .A0(n3601), .A1(n3600), .B0(n3599), .Y(n3609) );
NAND2X1TS U2731 ( .A(n2409), .B(n2433), .Y(n3577) );
NAND2X1TS U2732 ( .A(n3610), .B(n3581), .Y(n3612) );
NOR2XLTS U2733 ( .A(FPADDSUB_intDY_EWSW[22]), .B(n3598), .Y(n3580) );
NAND2BXLTS U2734 ( .AN(mult_x_254_n169), .B(n4331), .Y(n4332) );
AOI32X1TS U2735 ( .A0(FPMULT_Op_MX[0]), .A1(mult_x_254_n225), .A2(
FPMULT_Op_MY[8]), .B0(n2340), .B1(n2796), .Y(n2940) );
AO21XLTS U2736 ( .A0(FPMULT_Op_MX[4]), .A1(n2303), .B0(n4727), .Y(n2238) );
NAND2BXLTS U2737 ( .AN(mult_x_219_n163), .B(n4283), .Y(n4284) );
AOI221X1TS U2738 ( .A0(FPMULT_Op_MY[19]), .A1(FPMULT_Op_MX[12]), .B0(
FPMULT_Op_MY[18]), .B1(n5066), .C0(n4999), .Y(n3768) );
OR3X1TS U2739 ( .A(n2542), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .C(
FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n2539) );
NOR2X2TS U2740 ( .A(n2202), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n3976)
);
NOR2XLTS U2741 ( .A(n4224), .B(n2485), .Y(n2487) );
OAI21XLTS U2742 ( .A0(n2485), .A1(n4223), .B0(n2484), .Y(n2486) );
CLKAND2X2TS U2743 ( .A(n5118), .B(FPADDSUB_DMP_SFG[9]), .Y(n2498) );
OAI21XLTS U2744 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n2444), .Y(n2445) );
OAI32X1TS U2745 ( .A0(mult_x_254_n129), .A1(mult_x_254_n196), .A2(n2230),
.B0(n3772), .B1(mult_x_254_n129), .Y(mult_x_254_n130) );
AO22XLTS U2746 ( .A0(n3848), .A1(n3846), .B0(n4359), .B1(n2641), .Y(
mult_x_254_n195) );
AO22XLTS U2747 ( .A0(n2840), .A1(n2644), .B0(n2267), .B1(n2642), .Y(
mult_x_219_n189) );
AND3X1TS U2748 ( .A(n2541), .B(n5007), .C(FPADDSUB_Raw_mant_NRM_SWR[10]),
.Y(n3129) );
NAND2X1TS U2749 ( .A(n2540), .B(n2539), .Y(n3130) );
NAND4BXLTS U2750 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n2476), .C(n2475),
.D(n2474), .Y(n2477) );
NAND4XLTS U2751 ( .A(n4933), .B(n4932), .C(n4931), .D(n4930), .Y(n4934) );
OAI221X1TS U2752 ( .A0(n5060), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n4906),
.B1(FPADDSUB_intDY_EWSW[1]), .C0(n4905), .Y(n4913) );
AOI21X1TS U2753 ( .A0(n3619), .A1(n2383), .B0(n2384), .Y(n3623) );
CLKAND2X2TS U2754 ( .A(FPADDSUB_intDY_EWSW[28]), .B(n5068), .Y(n2384) );
NOR3XLTS U2755 ( .A(n2546), .B(FPADDSUB_Raw_mant_NRM_SWR[25]), .C(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n2547) );
AO21XLTS U2756 ( .A0(n2543), .A1(FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n2545) );
NAND4XLTS U2757 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[3]), .C(n4989), .D(n5033), .Y(n4498) );
INVX2TS U2758 ( .A(operation[2]), .Y(n4496) );
NOR2X1TS U2759 ( .A(n3929), .B(n3901), .Y(n3927) );
OR2X1TS U2760 ( .A(n3963), .B(FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n3450) );
OAI21XLTS U2761 ( .A0(n2715), .A1(n2701), .B0(n2700), .Y(n2704) );
OAI21XLTS U2762 ( .A0(n4232), .A1(n4226), .B0(n4227), .Y(n2692) );
OAI21XLTS U2763 ( .A0(n4256), .A1(n4255), .B0(n4254), .Y(n4258) );
INVX2TS U2764 ( .A(n4249), .Y(n4251) );
OAI21XLTS U2765 ( .A0(n4248), .A1(n4247), .B0(n4246), .Y(n4253) );
OAI21XLTS U2766 ( .A0(n4225), .A1(n4224), .B0(n4223), .Y(n4230) );
OR2X2TS U2767 ( .A(n3393), .B(n3709), .Y(n4658) );
OAI21XLTS U2768 ( .A0(n4248), .A1(n4192), .B0(n4191), .Y(n4196) );
OR2X1TS U2769 ( .A(n3963), .B(FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n3453) );
OR2X1TS U2770 ( .A(n4947), .B(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n3420) );
OR2X1TS U2771 ( .A(n3963), .B(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n3423) );
AND3X1TS U2772 ( .A(n3433), .B(n3432), .C(n3431), .Y(n3697) );
AND3X1TS U2773 ( .A(n3428), .B(n3427), .C(n3426), .Y(n3698) );
INVX2TS U2774 ( .A(n4502), .Y(n4497) );
NAND3XLTS U2775 ( .A(n2212), .B(n5079), .C(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n4503) );
BUFX3TS U2776 ( .A(n3298), .Y(n4616) );
BUFX3TS U2777 ( .A(n3298), .Y(n4633) );
BUFX3TS U2778 ( .A(n3319), .Y(n4645) );
BUFX3TS U2779 ( .A(n3266), .Y(n4641) );
AOI2BB1XLTS U2780 ( .A0N(n2560), .A1N(FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n2565) );
MX2X1TS U2781 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
OAI21XLTS U2782 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n3891), .B0(n3890), .Y(
n3892) );
MX2X1TS U2783 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
NOR2X2TS U2784 ( .A(n4515), .B(n3164), .Y(n4511) );
NAND2X1TS U2785 ( .A(n4072), .B(n4989), .Y(n3882) );
AOI32X1TS U2786 ( .A0(FPMULT_Op_MX[0]), .A1(mult_x_254_n225), .A2(
FPMULT_Op_MY[5]), .B0(n2872), .B1(n2339), .Y(n2874) );
OAI32X1TS U2787 ( .A0(n4990), .A1(n2306), .A2(n5002), .B0(FPMULT_Op_MY[0]),
.B1(mult_x_254_n197), .Y(n4324) );
OAI32X1TS U2788 ( .A0(FPMULT_Op_MY[0]), .A1(n2234), .A2(mult_x_254_n225),
.B0(n4373), .B1(n2276), .Y(n3829) );
NAND2X1TS U2789 ( .A(n2370), .B(n4036), .Y(n3974) );
NOR2X1TS U2790 ( .A(n4010), .B(n3998), .Y(n4878) );
NOR2X1TS U2791 ( .A(n4010), .B(n3985), .Y(n4876) );
NOR2X1TS U2792 ( .A(n4010), .B(n3980), .Y(n4872) );
NOR2X1TS U2793 ( .A(n4010), .B(n4005), .Y(n4867) );
AOI222X4TS U2794 ( .A0(n2972), .A1(intadd_0_SUM_24_), .B0(n2972), .B1(n3029),
.C0(intadd_0_SUM_24_), .C1(n3029), .Y(n2975) );
BUFX3TS U2795 ( .A(n3412), .Y(n3497) );
BUFX3TS U2796 ( .A(n3411), .Y(n3498) );
CLKINVX3TS U2797 ( .A(rst), .Y(n2610) );
INVX2TS U2798 ( .A(n4500), .Y(n3386) );
BUFX3TS U2799 ( .A(n4547), .Y(n3231) );
BUFX3TS U2800 ( .A(n3371), .Y(n3238) );
AOI2BB2XLTS U2801 ( .B0(n3467), .B1(n5097), .A0N(n3646), .A1N(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n3449) );
AND3X1TS U2802 ( .A(n3445), .B(n3444), .C(n3443), .Y(n3690) );
BUFX3TS U2803 ( .A(n2344), .Y(n3379) );
BUFX3TS U2804 ( .A(n3371), .Y(n3378) );
BUFX3TS U2805 ( .A(n3412), .Y(n3501) );
BUFX3TS U2806 ( .A(n3411), .Y(n3502) );
CLKBUFX2TS U2807 ( .A(n3371), .Y(n3383) );
BUFX3TS U2808 ( .A(n2344), .Y(n3384) );
NOR2X4TS U2809 ( .A(n4551), .B(n4521), .Y(n3371) );
INVX2TS U2810 ( .A(FPSENCOS_cont_iter_out[0]), .Y(n4554) );
INVX2TS U2811 ( .A(FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n4871) );
MX2X1TS U2812 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DMP_SHT2_EWSW[0]), .S0(
n4064), .Y(n1294) );
MX2X1TS U2813 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DMP_SHT2_EWSW[1]), .S0(
n4064), .Y(n1287) );
MX2X1TS U2814 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DMP_SHT2_EWSW[6]), .S0(
n3964), .Y(n1239) );
MX2X1TS U2815 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DMP_SHT2_EWSW[5]), .S0(
n3964), .Y(n1273) );
MX2X1TS U2816 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DMP_SHT2_EWSW[7]), .S0(
n3964), .Y(n1301) );
MX2X1TS U2817 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DMP_SHT2_EWSW[2]), .S0(
n4064), .Y(n1308) );
MX2X1TS U2818 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DMP_SHT2_EWSW[3]), .S0(
n4064), .Y(n1324) );
AO22XLTS U2819 ( .A0(FPSENCOS_d_ff2_X[31]), .A1(n4564), .B0(
FPSENCOS_d_ff_Xn[31]), .B1(n4571), .Y(n1944) );
AO22XLTS U2820 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n4549), .B0(
FPSENCOS_d_ff_Xn[11]), .B1(n4547), .Y(n1984) );
AO22XLTS U2821 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n4549), .B0(
FPSENCOS_d_ff_Xn[18]), .B1(n4571), .Y(n1970) );
AO22XLTS U2822 ( .A0(FPSENCOS_d_ff2_X[15]), .A1(n4549), .B0(
FPSENCOS_d_ff_Xn[15]), .B1(n4547), .Y(n1976) );
AO22XLTS U2823 ( .A0(FPSENCOS_d_ff2_X[9]), .A1(n4549), .B0(
FPSENCOS_d_ff_Xn[9]), .B1(n4547), .Y(n1988) );
AO22XLTS U2824 ( .A0(FPSENCOS_d_ff2_X[8]), .A1(n4549), .B0(
FPSENCOS_d_ff_Xn[8]), .B1(n4547), .Y(n1990) );
AO22XLTS U2825 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n4549), .B0(
FPSENCOS_d_ff_Xn[4]), .B1(n4547), .Y(n1998) );
AO22XLTS U2826 ( .A0(FPSENCOS_d_ff2_X[21]), .A1(n4564), .B0(
FPSENCOS_d_ff_Xn[21]), .B1(n4571), .Y(n1964) );
MX2X1TS U2827 ( .A(Data_2[26]), .B(FPMULT_Op_MY[26]), .S0(n4707), .Y(n1653)
);
AO22XLTS U2828 ( .A0(n4845), .A1(FPMULT_P_Sgf[42]), .B0(n4783), .B1(n4763),
.Y(n1572) );
MX2X1TS U2829 ( .A(Data_2[24]), .B(FPMULT_Op_MY[24]), .S0(n4707), .Y(n1651)
);
MX2X1TS U2830 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_exp_oper_result[7]), .S0(n3957), .Y(n1588) );
MX2X1TS U2831 ( .A(FPMULT_Exp_module_Data_S[4]), .B(
FPMULT_exp_oper_result[4]), .S0(n3957), .Y(n1591) );
MX2X1TS U2832 ( .A(FPMULT_Exp_module_Data_S[1]), .B(
FPMULT_exp_oper_result[1]), .S0(n3957), .Y(n1594) );
MX2X1TS U2833 ( .A(FPMULT_Exp_module_Data_S[0]), .B(
FPMULT_exp_oper_result[0]), .S0(n3957), .Y(n1595) );
MX2X1TS U2834 ( .A(Data_2[27]), .B(FPMULT_Op_MY[27]), .S0(n4702), .Y(n1654)
);
MX2X1TS U2835 ( .A(Data_2[30]), .B(FPMULT_Op_MY[30]), .S0(n3959), .Y(n1657)
);
MX2X1TS U2836 ( .A(Data_2[25]), .B(FPMULT_Op_MY[25]), .S0(n4706), .Y(n1652)
);
MX2X1TS U2837 ( .A(Data_1[25]), .B(FPMULT_Op_MX[25]), .S0(n3959), .Y(n2216)
);
MX2X1TS U2838 ( .A(FPMULT_Add_result[18]), .B(n3912), .S0(n3920), .Y(n1603)
);
MX2X1TS U2839 ( .A(FPMULT_Add_result[9]), .B(n3934), .S0(n3946), .Y(n1612)
);
MX2X1TS U2840 ( .A(FPMULT_Add_result[8]), .B(n3936), .S0(n3946), .Y(n1613)
);
MX2X1TS U2841 ( .A(FPMULT_Add_result[7]), .B(n3940), .S0(n3946), .Y(n1614)
);
MX2X1TS U2842 ( .A(FPMULT_Add_result[6]), .B(n3942), .S0(n3946), .Y(n1615)
);
MX2X1TS U2843 ( .A(FPMULT_Add_result[5]), .B(n3944), .S0(n3946), .Y(n1616)
);
MX2X1TS U2844 ( .A(FPMULT_Add_result[4]), .B(n3947), .S0(n3946), .Y(n1617)
);
MX2X1TS U2845 ( .A(FPMULT_Add_result[2]), .B(n3952), .S0(n3955), .Y(n1619)
);
MX2X1TS U2846 ( .A(FPMULT_Add_result[10]), .B(n3932), .S0(n3946), .Y(n1611)
);
MX2X1TS U2847 ( .A(FPMULT_Add_result[11]), .B(n3928), .S0(n3946), .Y(n1610)
);
MX2X1TS U2848 ( .A(FPMULT_Add_result[12]), .B(n3926), .S0(n3946), .Y(n1609)
);
MX2X1TS U2849 ( .A(FPMULT_Add_result[13]), .B(n3924), .S0(n3946), .Y(n1608)
);
MX2X1TS U2850 ( .A(FPMULT_Add_result[15]), .B(n3918), .S0(n3920), .Y(n1606)
);
MX2X1TS U2851 ( .A(FPMULT_Add_result[16]), .B(n3916), .S0(n3920), .Y(n1605)
);
MX2X1TS U2852 ( .A(FPMULT_Add_result[21]), .B(n3906), .S0(n3920), .Y(n1600)
);
AOI2BB2XLTS U2853 ( .B0(n4501), .B1(n5079), .A0N(n5079), .A1N(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n4504) );
MX2X1TS U2854 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1454) );
AOI2BB2XLTS U2855 ( .B0(n4999), .B1(n4707), .A0N(n4706), .A1N(Data_1[13]),
.Y(n1672) );
AO22XLTS U2856 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[30]), .B0(n2264), .B1(FPADDSUB_DMP_exp_NRM_EW[7]),
.Y(n1420) );
MX2X1TS U2857 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1424) );
MX2X1TS U2858 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DMP_SHT2_EWSW[4]), .S0(
n3964), .Y(n1235) );
AO22XLTS U2859 ( .A0(n4675), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4674), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1733) );
AO22XLTS U2860 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n4564), .B0(
FPSENCOS_d_ff_Xn[22]), .B1(n4571), .Y(n1962) );
MX2X1TS U2861 ( .A(Data_2[28]), .B(FPMULT_Op_MY[28]), .S0(n3959), .Y(n1655)
);
MX2X1TS U2862 ( .A(Data_1[26]), .B(FPMULT_Op_MX[26]), .S0(n3959), .Y(n2217)
);
MX2X1TS U2863 ( .A(FPMULT_Add_result[19]), .B(n3910), .S0(n3920), .Y(n1602)
);
MX2X1TS U2864 ( .A(Data_1[28]), .B(FPMULT_Op_MX[28]), .S0(n3959), .Y(n2218)
);
CLKAND2X2TS U2865 ( .A(n4481), .B(n4508), .Y(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
XOR2XLTS U2866 ( .A(n2680), .B(n2679), .Y(n2685) );
MX2X1TS U2867 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1429) );
MX2X1TS U2868 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1439) );
MX2X1TS U2869 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1449) );
XOR2XLTS U2870 ( .A(n4248), .B(n2761), .Y(n2769) );
AOI2BB2XLTS U2871 ( .B0(n2196), .B1(n3693), .A0N(n3680), .A1N(n2211), .Y(
n2575) );
MX2X1TS U2872 ( .A(FPMULT_FSM_add_overflow_flag), .B(n3956), .S0(n3955), .Y(
n1597) );
MX2X1TS U2873 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n3963), .Y(n1444) );
MX2X1TS U2874 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n4947), .Y(n1434) );
AO22XLTS U2875 ( .A0(n4865), .A1(n4852), .B0(n4857), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1476) );
MX2X1TS U2876 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DMP_SHT2_EWSW[9]), .S0(
n3964), .Y(n1280) );
MX2X1TS U2877 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DMP_SHT2_EWSW[8]), .S0(
n3964), .Y(n1251) );
MX2X1TS U2878 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n3963), .Y(n1419) );
MX2X1TS U2879 ( .A(FPMULT_Exp_module_Data_S[2]), .B(
FPMULT_exp_oper_result[2]), .S0(n3957), .Y(n1593) );
MX2X1TS U2880 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_exp_oper_result[3]), .S0(n3957), .Y(n1592) );
MX2X1TS U2881 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_exp_oper_result[5]), .S0(n3957), .Y(n1590) );
MX2X1TS U2882 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_exp_oper_result[6]), .S0(n3957), .Y(n1589) );
MX2X1TS U2883 ( .A(Data_2[29]), .B(FPMULT_Op_MY[29]), .S0(n3959), .Y(n1656)
);
MX2X1TS U2884 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n3959), .Y(n2219)
);
MX2X1TS U2885 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n3959), .Y(n2220)
);
MX2X1TS U2886 ( .A(FPADDSUB_OP_FLAG_SFG), .B(FPADDSUB_OP_FLAG_SHT2), .S0(
n4064), .Y(n1353) );
XOR2XLTS U2887 ( .A(n4225), .B(n4216), .Y(n4222) );
MX2X1TS U2888 ( .A(Data_1[23]), .B(FPMULT_Op_MX[23]), .S0(n3959), .Y(n2221)
);
MX2X1TS U2889 ( .A(FPMULT_Add_result[22]), .B(n3904), .S0(n3920), .Y(n1599)
);
MX2X1TS U2890 ( .A(FPMULT_Add_result[14]), .B(n3921), .S0(n3920), .Y(n1607)
);
MX2X1TS U2891 ( .A(FPMULT_Add_result[3]), .B(n3950), .S0(n3955), .Y(n1618)
);
INVX2TS U2892 ( .A(n3951), .Y(n3948) );
MX2X1TS U2893 ( .A(FPMULT_Add_result[1]), .B(n3953), .S0(n3955), .Y(n1620)
);
MX2X1TS U2894 ( .A(Data_2[23]), .B(FPMULT_Op_MY[23]), .S0(n4745), .Y(n1650)
);
MX2X1TS U2895 ( .A(FPMULT_Op_MX[30]), .B(Data_1[30]), .S0(n4713), .Y(n1689)
);
AOI2BB2XLTS U2896 ( .B0(FPMULT_Sgf_normalized_result[14]), .B1(n3093), .A0N(
n3092), .A1N(n3088), .Y(n3089) );
AOI2BB2XLTS U2897 ( .B0(FPMULT_Sgf_normalized_result[13]), .B1(n3093), .A0N(
n3092), .A1N(n3062), .Y(n3063) );
AOI2BB2XLTS U2898 ( .B0(FPMULT_Sgf_normalized_result[11]), .B1(n3093), .A0N(
n3092), .A1N(n3091), .Y(n3094) );
AOI2BB2XLTS U2899 ( .B0(n5066), .B1(n4707), .A0N(n4707), .A1N(Data_1[12]),
.Y(n1671) );
AO21XLTS U2900 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_6), .A1(n4506), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .Y(n2149) );
AO22XLTS U2901 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n4564), .B0(
FPSENCOS_d_ff_Xn[23]), .B1(n4571), .Y(n1960) );
AO22XLTS U2902 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n4564), .B0(
FPSENCOS_d_ff_Xn[30]), .B1(n4571), .Y(n1953) );
XOR2XLTS U2903 ( .A(n2715), .B(n2714), .Y(n2724) );
OR2X1TS U2904 ( .A(n4512), .B(n4487), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
AOI32X1TS U2905 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n3392), .A2(
n5003), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n3691), .Y(n3145)
);
MX2X1TS U2906 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DMP_SHT2_EWSW[22]),
.S0(n4064), .Y(n1207) );
MX2X1TS U2907 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DMP_SHT2_EWSW[18]),
.S0(n4064), .Y(n1215) );
MX2X1TS U2908 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DMP_SHT2_EWSW[14]),
.S0(n4064), .Y(n1259) );
MX2X1TS U2909 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DMP_SHT2_EWSW[16]),
.S0(n4064), .Y(n1247) );
MX2X1TS U2910 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DMP_SHT2_EWSW[20]),
.S0(n4052), .Y(n1227) );
XOR2XLTS U2911 ( .A(n4209), .B(n4208), .Y(n4211) );
CLKAND2X2TS U2912 ( .A(n4207), .B(n4217), .Y(n4209) );
MX2X1TS U2913 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DMP_SHT2_EWSW[12]),
.S0(n4856), .Y(n1267) );
MX2X1TS U2914 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DMP_SHT2_EWSW[13]),
.S0(n4946), .Y(n1243) );
MX2X1TS U2915 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DMP_SHT2_EWSW[17]),
.S0(n3964), .Y(n1231) );
MX2X1TS U2916 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DMP_SHT2_EWSW[19]),
.S0(n3964), .Y(n1223) );
MX2X1TS U2917 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DMP_SHT2_EWSW[21]),
.S0(n4052), .Y(n1219) );
MX2X1TS U2918 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DMP_SHT2_EWSW[15]),
.S0(n3964), .Y(n1211) );
MX2X1TS U2919 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DMP_SHT2_EWSW[10]),
.S0(n3964), .Y(n1263) );
MX2X1TS U2920 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DMP_SHT2_EWSW[11]),
.S0(n4052), .Y(n1255) );
XOR2XLTS U2921 ( .A(n4183), .B(n4182), .Y(n4188) );
AOI2BB2XLTS U2922 ( .B0(n2316), .B1(n4705), .A0N(n4702), .A1N(Data_1[0]),
.Y(n1659) );
XOR2XLTS U2923 ( .A(n4095), .B(n4094), .Y(n4100) );
XOR2XLTS U2924 ( .A(n4086), .B(n5121), .Y(n4090) );
NAND3XLTS U2925 ( .A(n4483), .B(n4551), .C(n4515), .Y(n4486) );
AOI211XLTS U2926 ( .A0(n3769), .A1(FPMULT_FSM_selector_B[0]), .B0(n4743),
.C0(n3955), .Y(n5282) );
MX2X1TS U2927 ( .A(n4066), .B(FPADDSUB_LZD_output_NRM2_EW[0]), .S0(n4507),
.Y(n1315) );
OR2X1TS U2928 ( .A(n3047), .B(n3046), .Y(n1691) );
NAND4XLTS U2929 ( .A(n5286), .B(n5285), .C(n5284), .D(n4477), .Y(n4479) );
XOR2XLTS U2930 ( .A(FPSENCOS_cont_var_out[0]), .B(n4514), .Y(n2138) );
NAND3XLTS U2931 ( .A(n4516), .B(n4515), .C(n5064), .Y(n4514) );
AOI2BB2XLTS U2932 ( .B0(n5002), .B1(n4745), .A0N(n4702), .A1N(Data_1[4]),
.Y(n1663) );
NAND4XLTS U2933 ( .A(n4724), .B(n4723), .C(n4722), .D(n5027), .Y(n4744) );
NAND4XLTS U2934 ( .A(n4740), .B(n4739), .C(n4738), .D(n4737), .Y(n4742) );
AOI2BB2XLTS U2935 ( .B0(n4698), .B1(n4745), .A0N(n4705), .A1N(Data_1[11]),
.Y(n1670) );
OAI21XLTS U2936 ( .A0(n3963), .A1(n5008), .B0(n3479), .Y(n1351) );
AOI2BB2XLTS U2937 ( .B0(n5057), .B1(n4707), .A0N(n4700), .A1N(Data_1[16]),
.Y(n1675) );
AOI2BB2XLTS U2938 ( .B0(n5058), .B1(n4706), .A0N(n4700), .A1N(Data_1[18]),
.Y(n1677) );
AOI2BB2XLTS U2939 ( .B0(n5063), .B1(n4705), .A0N(n4700), .A1N(Data_1[20]),
.Y(n1679) );
AOI2BB2XLTS U2940 ( .B0(n5074), .B1(n4705), .A0N(n4700), .A1N(Data_1[14]),
.Y(n1673) );
AOI2BB2XLTS U2941 ( .B0(n5075), .B1(n4705), .A0N(n4700), .A1N(Data_1[6]),
.Y(n1665) );
AOI2BB2XLTS U2942 ( .B0(n5076), .B1(n4745), .A0N(n4705), .A1N(Data_1[2]),
.Y(n1661) );
AOI2BB2XLTS U2943 ( .B0(n5077), .B1(n4702), .A0N(n4700), .A1N(Data_1[8]),
.Y(n1667) );
AOI2BB2XLTS U2944 ( .B0(n5078), .B1(n4551), .A0N(FPSENCOS_d_ff_Xn[28]),
.A1N(n4552), .Y(n1955) );
AOI2BB2XLTS U2945 ( .B0(n5090), .B1(n4706), .A0N(n4745), .A1N(Data_1[10]),
.Y(n1669) );
MX2X1TS U2946 ( .A(FPMULT_Add_result[17]), .B(n3914), .S0(n3920), .Y(n1604)
);
OAI31X1TS U2947 ( .A0(n4990), .A1(n2234), .A2(mult_x_254_n225), .B0(n2626),
.Y(FPMULT_Sgf_operation_EVEN1_right_N1) );
OAI31X1TS U2948 ( .A0(n2255), .A1(intadd_1_n1), .A2(n2624), .B0(n4455), .Y(
n4456) );
OAI31X1TS U2949 ( .A0(n2825), .A1(n2818), .A2(n2362), .B0(n2817), .Y(
FPMULT_Sgf_operation_EVEN1_left_N3) );
NAND3XLTS U2950 ( .A(n2452), .B(n2451), .C(n2450), .Y(n2453) );
AO22XLTS U2951 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n5169),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1208) );
AO22XLTS U2952 ( .A0(n4987), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n4986),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1209) );
AO22XLTS U2953 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n5169),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1212) );
AO22XLTS U2954 ( .A0(n4985), .A1(FPADDSUB_DMP_EXP_EWSW[15]), .B0(n4984),
.B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1213) );
AO22XLTS U2955 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n5169),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1216) );
AO22XLTS U2956 ( .A0(n4983), .A1(FPADDSUB_DMP_EXP_EWSW[18]), .B0(n4982),
.B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1217) );
AO22XLTS U2957 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n5169),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1220) );
AO22XLTS U2958 ( .A0(n4981), .A1(FPADDSUB_DMP_EXP_EWSW[21]), .B0(n4982),
.B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1221) );
AO22XLTS U2959 ( .A0(n4980), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n5169),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1224) );
AO22XLTS U2960 ( .A0(n4985), .A1(FPADDSUB_DMP_EXP_EWSW[19]), .B0(n4982),
.B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1225) );
AO22XLTS U2961 ( .A0(n4980), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n4979),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1228) );
AO22XLTS U2962 ( .A0(n4985), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n4982),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1229) );
AO22XLTS U2963 ( .A0(n4980), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n5169),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1232) );
AO22XLTS U2964 ( .A0(n4985), .A1(FPADDSUB_DMP_EXP_EWSW[17]), .B0(n4978),
.B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1233) );
AO22XLTS U2965 ( .A0(n4855), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(
FPADDSUB_DMP_SHT2_EWSW[4]), .B1(n4976), .Y(n5161) );
AO22XLTS U2966 ( .A0(n4983), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n4978), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1237) );
AO22XLTS U2967 ( .A0(n4855), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(
FPADDSUB_DMP_SHT2_EWSW[6]), .B1(n4976), .Y(n5162) );
AO22XLTS U2968 ( .A0(n4983), .A1(FPADDSUB_DMP_EXP_EWSW[6]), .B0(n4978), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1241) );
AO22XLTS U2969 ( .A0(n4980), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n5169),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1244) );
AO22XLTS U2970 ( .A0(n4983), .A1(FPADDSUB_DMP_EXP_EWSW[13]), .B0(n4978),
.B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1245) );
AO22XLTS U2971 ( .A0(n4980), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n5169),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1248) );
AO22XLTS U2972 ( .A0(n4983), .A1(FPADDSUB_DMP_EXP_EWSW[16]), .B0(n4978),
.B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1249) );
AO22XLTS U2973 ( .A0(n4980), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n5169),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1252) );
AO22XLTS U2974 ( .A0(n4983), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n4978), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1253) );
AO22XLTS U2975 ( .A0(n4980), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n4979),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1256) );
AO22XLTS U2976 ( .A0(n4983), .A1(FPADDSUB_DMP_EXP_EWSW[11]), .B0(n4978),
.B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1257) );
AO22XLTS U2977 ( .A0(n4980), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n5169),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1260) );
AO22XLTS U2978 ( .A0(n4981), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n4978),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1261) );
AO22XLTS U2979 ( .A0(n4980), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n4977),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1264) );
AO22XLTS U2980 ( .A0(n4983), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n4978),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1265) );
AO22XLTS U2981 ( .A0(n4980), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n4977),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1268) );
AO22XLTS U2982 ( .A0(n4983), .A1(FPADDSUB_DMP_EXP_EWSW[12]), .B0(n4978),
.B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1269) );
AO22XLTS U2983 ( .A0(n4983), .A1(FPADDSUB_DmP_EXP_EWSW[12]), .B0(n2661),
.B1(FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n1271) );
AO22XLTS U2984 ( .A0(n4855), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(
FPADDSUB_DMP_SHT2_EWSW[5]), .B1(n4976), .Y(n5163) );
AO22XLTS U2985 ( .A0(n4981), .A1(FPADDSUB_DMP_EXP_EWSW[5]), .B0(n2661), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1275) );
AO22XLTS U2986 ( .A0(n4981), .A1(FPADDSUB_DmP_EXP_EWSW[5]), .B0(n2661), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1277) );
OAI21XLTS U2987 ( .A0(n3521), .A1(n2435), .B0(n3660), .Y(n1278) );
AO22XLTS U2988 ( .A0(n5287), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n4977),
.B1(FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1281) );
AO22XLTS U2989 ( .A0(n4981), .A1(FPADDSUB_DMP_EXP_EWSW[9]), .B0(n2661), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1282) );
AO22XLTS U2990 ( .A0(n4981), .A1(FPADDSUB_DmP_EXP_EWSW[9]), .B0(n2661), .B1(
FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n1284) );
OAI21XLTS U2991 ( .A0(n3544), .A1(n2435), .B0(n3640), .Y(n1285) );
AO22XLTS U2992 ( .A0(n4855), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(
FPADDSUB_DMP_SHT2_EWSW[1]), .B1(n4979), .Y(n5164) );
AO22XLTS U2993 ( .A0(n4981), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n2661), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1289) );
OAI21XLTS U2994 ( .A0(n4906), .A1(n2435), .B0(n3627), .Y(n1292) );
AO22XLTS U2995 ( .A0(n4855), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(
FPADDSUB_DMP_SHT2_EWSW[0]), .B1(n4979), .Y(n5165) );
AO22XLTS U2996 ( .A0(n4981), .A1(FPADDSUB_DMP_EXP_EWSW[0]), .B0(n2661), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1296) );
AO22XLTS U2997 ( .A0(n4981), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n2661), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1298) );
AO22XLTS U2998 ( .A0(n4855), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(
FPADDSUB_DMP_SHT2_EWSW[7]), .B1(n4976), .Y(n5166) );
AO22XLTS U2999 ( .A0(n4981), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n4984), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1303) );
AO22XLTS U3000 ( .A0(n4987), .A1(FPADDSUB_DmP_EXP_EWSW[7]), .B0(n5095), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1305) );
AO22XLTS U3001 ( .A0(n4855), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(
FPADDSUB_DMP_SHT2_EWSW[2]), .B1(n4979), .Y(n5167) );
AO22XLTS U3002 ( .A0(n4987), .A1(FPADDSUB_DMP_EXP_EWSW[2]), .B0(n4986), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1310) );
XOR2XLTS U3003 ( .A(n4105), .B(n4104), .Y(n4110) );
XOR2XLTS U3004 ( .A(n4115), .B(n4114), .Y(n4120) );
AO22XLTS U3005 ( .A0(n4855), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(
FPADDSUB_DMP_SHT2_EWSW[3]), .B1(n4979), .Y(n5168) );
AO22XLTS U3006 ( .A0(n4987), .A1(FPADDSUB_DMP_EXP_EWSW[3]), .B0(n4986), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1326) );
AO22XLTS U3007 ( .A0(n4987), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n4986), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1328) );
XOR2XLTS U3008 ( .A(n4134), .B(n4133), .Y(n4139) );
XOR2XLTS U3009 ( .A(n4153), .B(n4152), .Y(n4158) );
AO22XLTS U3010 ( .A0(n2473), .A1(n2693), .B0(FPADDSUB_ADD_OVRFLW_NRM), .B1(
n4505), .Y(n1352) );
AO22XLTS U3011 ( .A0(n5287), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n4977), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1354) );
AO22XLTS U3012 ( .A0(n4987), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n4986), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1355) );
AO22XLTS U3013 ( .A0(n4947), .A1(FPADDSUB_SIGN_FLAG_NRM), .B0(n5003), .B1(
FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n1358) );
AO22XLTS U3014 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_SIGN_FLAG_SFG), .B0(n4505), .B1(FPADDSUB_SIGN_FLAG_NRM), .Y(
n1359) );
AO22XLTS U3015 ( .A0(n4946), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n4858), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1360) );
AO22XLTS U3016 ( .A0(n5287), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n4977), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1361) );
AO22XLTS U3017 ( .A0(n4987), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n4986), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1362) );
AOI31XLTS U3018 ( .A0(n4940), .A1(n4939), .A2(n4938), .B0(n2435), .Y(n4941)
);
AO22XLTS U3019 ( .A0(n4987), .A1(FPADDSUB_DmP_EXP_EWSW[10]), .B0(n4986),
.B1(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1365) );
AO22XLTS U3020 ( .A0(n4987), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n4986),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1368) );
AO22XLTS U3021 ( .A0(n4987), .A1(FPADDSUB_DmP_EXP_EWSW[11]), .B0(n4986),
.B1(FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1371) );
AO22XLTS U3022 ( .A0(n4894), .A1(FPADDSUB_DmP_EXP_EWSW[8]), .B0(n4986), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1374) );
AO22XLTS U3023 ( .A0(n4894), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n4891),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1377) );
AO22XLTS U3024 ( .A0(n4894), .A1(FPADDSUB_DmP_EXP_EWSW[13]), .B0(n4891),
.B1(FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1380) );
AO22XLTS U3025 ( .A0(n4894), .A1(FPADDSUB_DmP_EXP_EWSW[6]), .B0(n4891), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1383) );
AO22XLTS U3026 ( .A0(n4894), .A1(FPADDSUB_DmP_EXP_EWSW[4]), .B0(n4891), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1386) );
AO22XLTS U3027 ( .A0(n4894), .A1(FPADDSUB_DmP_EXP_EWSW[17]), .B0(n4891),
.B1(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1389) );
AO22XLTS U3028 ( .A0(n4894), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n4891),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1398) );
AO22XLTS U3029 ( .A0(n4894), .A1(FPADDSUB_DmP_EXP_EWSW[18]), .B0(n4891),
.B1(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1401) );
AO22XLTS U3030 ( .A0(n4894), .A1(FPADDSUB_DmP_EXP_EWSW[15]), .B0(n4891),
.B1(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1404) );
AO22XLTS U3031 ( .A0(n4865), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n4891),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1407) );
AOI2BB1XLTS U3032 ( .A0N(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1N(
FPADDSUB_LZD_output_NRM2_EW[1]), .B0(n4065), .Y(n1410) );
AOI2BB1XLTS U3033 ( .A0N(n4070), .A1N(overflow_flag_addsubt), .B0(n4862),
.Y(n1412) );
AOI222X1TS U3034 ( .A0(n3764), .A1(FPADDSUB_intDY_EWSW[26]), .B0(
FPADDSUB_DmP_EXP_EWSW[26]), .B1(n4944), .C0(FPADDSUB_intDX_EWSW[26]),
.C1(n3765), .Y(n3760) );
AOI222X1TS U3035 ( .A0(n3764), .A1(FPADDSUB_intDY_EWSW[25]), .B0(
FPADDSUB_DmP_EXP_EWSW[25]), .B1(n4904), .C0(FPADDSUB_intDX_EWSW[25]),
.C1(n3765), .Y(n3763) );
AO22XLTS U3036 ( .A0(n4946), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n4945),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1421) );
AO22XLTS U3037 ( .A0(n5287), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n4977),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1422) );
AO22XLTS U3038 ( .A0(n4865), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n4891),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1423) );
AO22XLTS U3039 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[29]), .B0(n2264), .B1(FPADDSUB_DMP_exp_NRM_EW[6]),
.Y(n1425) );
AO22XLTS U3040 ( .A0(n4946), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n4945),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1426) );
AO22XLTS U3041 ( .A0(n5287), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n4977),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1427) );
AO22XLTS U3042 ( .A0(n4865), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n4857),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1428) );
AO22XLTS U3043 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[28]), .B0(n2264), .B1(FPADDSUB_DMP_exp_NRM_EW[5]),
.Y(n1430) );
AO22XLTS U3044 ( .A0(n4946), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n4945),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1431) );
AO22XLTS U3045 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n4977),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1432) );
AO22XLTS U3046 ( .A0(n4865), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n4857),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1433) );
AO22XLTS U3047 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[27]), .B0(n2264), .B1(FPADDSUB_DMP_exp_NRM_EW[4]),
.Y(n1435) );
AO22XLTS U3048 ( .A0(n4946), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n4945),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1436) );
AO22XLTS U3049 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n4977),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1437) );
AO22XLTS U3050 ( .A0(n4865), .A1(FPADDSUB_DMP_EXP_EWSW[27]), .B0(n4857),
.B1(FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1438) );
AO22XLTS U3051 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[26]), .B0(n2264), .B1(FPADDSUB_DMP_exp_NRM_EW[3]),
.Y(n1440) );
AO22XLTS U3052 ( .A0(n4946), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n4945),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1441) );
AO22XLTS U3053 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n4977),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1442) );
AO22XLTS U3054 ( .A0(n4894), .A1(FPADDSUB_DMP_EXP_EWSW[26]), .B0(n4857),
.B1(FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1443) );
AO22XLTS U3055 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[25]), .B0(n2264), .B1(FPADDSUB_DMP_exp_NRM_EW[2]),
.Y(n1445) );
AO22XLTS U3056 ( .A0(n4946), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n4945),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1446) );
AO22XLTS U3057 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n4979),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1447) );
AO22XLTS U3058 ( .A0(n4865), .A1(FPADDSUB_DMP_EXP_EWSW[25]), .B0(n4857),
.B1(FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1448) );
AO22XLTS U3059 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[24]), .B0(n2410), .B1(FPADDSUB_DMP_exp_NRM_EW[1]),
.Y(n1450) );
AO22XLTS U3060 ( .A0(n4946), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n4945),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1451) );
AO22XLTS U3061 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n4979),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1452) );
AO22XLTS U3062 ( .A0(n4865), .A1(FPADDSUB_DMP_EXP_EWSW[24]), .B0(n4857),
.B1(FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1453) );
AO22XLTS U3063 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[23]), .B0(n2410), .B1(FPADDSUB_DMP_exp_NRM_EW[0]),
.Y(n1455) );
AO22XLTS U3064 ( .A0(n4856), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n4858),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1456) );
AO22XLTS U3065 ( .A0(n4855), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n4976),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1457) );
OAI2BB2XLTS U3066 ( .B0(n4070), .B1(n4677), .A0N(
FPADDSUB_exp_rslt_NRM2_EW1[7]), .A1N(n4862), .Y(n1467) );
AO22XLTS U3067 ( .A0(n4865), .A1(n4854), .B0(n4857), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1475) );
AO22XLTS U3068 ( .A0(n4865), .A1(intadd_6_SUM_1_), .B0(n4857), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1478) );
AO22XLTS U3069 ( .A0(n4985), .A1(intadd_6_SUM_2_), .B0(n4982), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1479) );
AO22XLTS U3070 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n2348), .B0(
mult_result[22]), .B1(n4850), .Y(n1482) );
AO22XLTS U3071 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n2348), .B0(
mult_result[21]), .B1(n4849), .Y(n1484) );
AO22XLTS U3072 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n4851), .B0(
mult_result[20]), .B1(n4849), .Y(n1485) );
AO22XLTS U3073 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n2348), .B0(
mult_result[18]), .B1(n4849), .Y(n1487) );
AO22XLTS U3074 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4851), .B0(
mult_result[17]), .B1(n4850), .Y(n1488) );
AO22XLTS U3075 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n2348), .B0(
mult_result[16]), .B1(n4850), .Y(n1489) );
AO22XLTS U3076 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4851), .B0(
mult_result[15]), .B1(n4850), .Y(n1490) );
AO22XLTS U3077 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n2348), .B0(
mult_result[14]), .B1(n4850), .Y(n1491) );
AO22XLTS U3078 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4851), .B0(
mult_result[13]), .B1(n4850), .Y(n1492) );
AO22XLTS U3079 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n2348), .B0(
mult_result[12]), .B1(n4850), .Y(n1493) );
AO22XLTS U3080 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4851), .B0(
mult_result[11]), .B1(n4850), .Y(n1494) );
AO22XLTS U3081 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n2348), .B0(
mult_result[10]), .B1(n4850), .Y(n1495) );
AO22XLTS U3082 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4851), .B0(
mult_result[9]), .B1(n4850), .Y(n1496) );
AO22XLTS U3083 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n2348), .B0(
mult_result[8]), .B1(n4846), .Y(n1497) );
AO22XLTS U3084 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4851), .B0(
mult_result[7]), .B1(n4846), .Y(n1498) );
AO22XLTS U3085 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n2348), .B0(
mult_result[5]), .B1(n4846), .Y(n1500) );
AO22XLTS U3086 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n2347), .B0(
mult_result[4]), .B1(n4846), .Y(n1501) );
AO22XLTS U3087 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n2347), .B0(
mult_result[3]), .B1(n4846), .Y(n1502) );
AO22XLTS U3088 ( .A0(n4851), .A1(FPMULT_Sgf_normalized_result[2]), .B0(
mult_result[2]), .B1(n4849), .Y(n1503) );
AO22XLTS U3089 ( .A0(n2348), .A1(FPMULT_Sgf_normalized_result[1]), .B0(
mult_result[1]), .B1(n4849), .Y(n1504) );
AO22XLTS U3090 ( .A0(n4851), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
mult_result[0]), .B1(n4849), .Y(n1505) );
OAI21XLTS U3091 ( .A0(n4749), .A1(underflow_flag_mult), .B0(n4748), .Y(n4750) );
AOI2BB1XLTS U3092 ( .A0N(n2203), .A1N(FPMULT_P_Sgf[46]), .B0(n2772), .Y(
n1622) );
AO22XLTS U3093 ( .A0(n4845), .A1(FPMULT_P_Sgf[0]), .B0(n4844), .B1(
FPMULT_Sgf_operation_Result[0]), .Y(n1530) );
AO22XLTS U3094 ( .A0(n4843), .A1(FPMULT_P_Sgf[1]), .B0(n4811), .B1(
FPMULT_Sgf_operation_Result[1]), .Y(n1531) );
AO22XLTS U3095 ( .A0(n4843), .A1(FPMULT_P_Sgf[12]), .B0(n4830), .B1(n4829),
.Y(n1542) );
AO22XLTS U3096 ( .A0(n4843), .A1(FPMULT_P_Sgf[13]), .B0(n4830), .B1(n4826),
.Y(n1543) );
AO22XLTS U3097 ( .A0(n4843), .A1(FPMULT_P_Sgf[14]), .B0(n4830), .B1(n4821),
.Y(n1544) );
AO22XLTS U3098 ( .A0(n4843), .A1(FPMULT_P_Sgf[15]), .B0(n4830), .B1(n4816),
.Y(n1545) );
AO22XLTS U3099 ( .A0(n4843), .A1(FPMULT_P_Sgf[16]), .B0(n4811), .B1(n4810),
.Y(n1546) );
AO22XLTS U3100 ( .A0(n4843), .A1(FPMULT_P_Sgf[17]), .B0(n4830), .B1(n4806),
.Y(n1547) );
AO22XLTS U3101 ( .A0(n2756), .A1(FPMULT_P_Sgf[18]), .B0(n4830), .B1(n2730),
.Y(n1548) );
AO22XLTS U3102 ( .A0(n2756), .A1(FPMULT_P_Sgf[19]), .B0(n4830), .B1(n2752),
.Y(n1549) );
AO22XLTS U3103 ( .A0(n2756), .A1(FPMULT_P_Sgf[20]), .B0(n4830), .B1(n2736),
.Y(n1550) );
AO22XLTS U3104 ( .A0(n2756), .A1(FPMULT_P_Sgf[21]), .B0(n4798), .B1(n2739),
.Y(n1551) );
AO22XLTS U3105 ( .A0(n2756), .A1(FPMULT_P_Sgf[22]), .B0(n4798), .B1(n2727),
.Y(n1552) );
AO22XLTS U3106 ( .A0(n2756), .A1(FPMULT_P_Sgf[23]), .B0(n4798), .B1(n2733),
.Y(n1553) );
AO22XLTS U3107 ( .A0(n2756), .A1(FPMULT_P_Sgf[25]), .B0(n4844), .B1(n2755),
.Y(n1555) );
AO22XLTS U3108 ( .A0(n2756), .A1(FPMULT_P_Sgf[26]), .B0(n4844), .B1(n2742),
.Y(n1556) );
AO22XLTS U3109 ( .A0(n4845), .A1(FPMULT_P_Sgf[27]), .B0(n4844), .B1(n4795),
.Y(n1557) );
AO22XLTS U3110 ( .A0(n2756), .A1(FPMULT_P_Sgf[28]), .B0(n4844), .B1(n2748),
.Y(n1558) );
AO22XLTS U3111 ( .A0(n4845), .A1(FPMULT_P_Sgf[29]), .B0(n4844), .B1(n4790),
.Y(n1559) );
AO21XLTS U3112 ( .A0(n2591), .A1(n4783), .B0(n3101), .Y(n1560) );
AO22XLTS U3113 ( .A0(n4845), .A1(FPMULT_P_Sgf[31]), .B0(n4844), .B1(n4787),
.Y(n1561) );
AO22XLTS U3114 ( .A0(n2756), .A1(FPMULT_P_Sgf[32]), .B0(n4783), .B1(n2745),
.Y(n1562) );
AO21XLTS U3115 ( .A0(n2667), .A1(n4783), .B0(n3050), .Y(n1563) );
OAI21XLTS U3116 ( .A0(n2971), .A1(n3961), .B0(n3091), .Y(n1564) );
AO22XLTS U3117 ( .A0(n4845), .A1(FPMULT_P_Sgf[35]), .B0(n4783), .B1(n4782),
.Y(n1565) );
OAI21XLTS U3118 ( .A0(n2978), .A1(n3961), .B0(n3088), .Y(n1567) );
AO22XLTS U3119 ( .A0(n4845), .A1(FPMULT_P_Sgf[38]), .B0(n4783), .B1(n4776),
.Y(n1568) );
AO22XLTS U3120 ( .A0(n4845), .A1(FPMULT_P_Sgf[40]), .B0(n4783), .B1(n4770),
.Y(n1570) );
AO22XLTS U3121 ( .A0(n4845), .A1(FPMULT_P_Sgf[44]), .B0(n4783), .B1(n4758),
.Y(n1574) );
AO22XLTS U3122 ( .A0(n4708), .A1(Data_1[31]), .B0(n4702), .B1(
FPMULT_Op_MX[31]), .Y(n1658) );
AOI2BB2XLTS U3123 ( .B0(mult_x_254_n225), .B1(n4707), .A0N(n4705), .A1N(
Data_1[1]), .Y(n1660) );
AOI2BB2XLTS U3124 ( .B0(n4704), .B1(n4745), .A0N(n4706), .A1N(Data_1[3]),
.Y(n1662) );
AOI2BB2XLTS U3125 ( .B0(n4703), .B1(n4707), .A0N(n4702), .A1N(Data_1[5]),
.Y(n1664) );
AOI2BB2XLTS U3126 ( .B0(n4701), .B1(n4707), .A0N(n4745), .A1N(Data_1[7]),
.Y(n1666) );
AOI2BB2XLTS U3127 ( .B0(n4699), .B1(n4702), .A0N(n4702), .A1N(Data_1[9]),
.Y(n1668) );
AOI2BB2XLTS U3128 ( .B0(n4697), .B1(n4702), .A0N(n4745), .A1N(Data_1[15]),
.Y(n1674) );
AOI2BB2XLTS U3129 ( .B0(n2290), .B1(n4705), .A0N(n4706), .A1N(Data_1[17]),
.Y(n1676) );
AOI2BB2XLTS U3130 ( .B0(n2286), .B1(n4706), .A0N(n4706), .A1N(Data_1[19]),
.Y(n1678) );
AOI2BB2XLTS U3131 ( .B0(n2206), .B1(n4706), .A0N(n4745), .A1N(Data_1[21]),
.Y(n1680) );
AO22XLTS U3132 ( .A0(n4746), .A1(Data_2[31]), .B0(n4707), .B1(
FPMULT_Op_MY[31]), .Y(n1625) );
AO22XLTS U3133 ( .A0(n4675), .A1(FPSENCOS_d_ff2_X[5]), .B0(n4580), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1995) );
AO22XLTS U3134 ( .A0(n4546), .A1(FPSENCOS_d_ff2_X[7]), .B0(n4548), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1991) );
AO22XLTS U3135 ( .A0(n4546), .A1(FPSENCOS_d_ff2_X[3]), .B0(n4580), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1999) );
OAI21XLTS U3136 ( .A0(n3392), .A1(n2370), .B0(n2538), .Y(n2079) );
AO22XLTS U3137 ( .A0(n4675), .A1(FPSENCOS_d_ff2_X[31]), .B0(n4674), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1943) );
AO22XLTS U3138 ( .A0(n4546), .A1(FPSENCOS_d_ff2_X[14]), .B0(n4548), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1977) );
AO22XLTS U3139 ( .A0(n4675), .A1(FPSENCOS_d_ff2_X[11]), .B0(n4548), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1983) );
AO22XLTS U3140 ( .A0(n4546), .A1(FPSENCOS_d_ff2_X[16]), .B0(n4548), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1973) );
AO22XLTS U3141 ( .A0(n4546), .A1(FPSENCOS_d_ff2_X[13]), .B0(n4548), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1979) );
AO22XLTS U3142 ( .A0(n2776), .A1(FPSENCOS_d_ff2_X[17]), .B0(n4548), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1971) );
AO22XLTS U3143 ( .A0(n4546), .A1(FPSENCOS_d_ff2_X[20]), .B0(n4548), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1965) );
AO22XLTS U3144 ( .A0(n4546), .A1(FPSENCOS_d_ff2_X[19]), .B0(n4674), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1967) );
AO22XLTS U3145 ( .A0(n4546), .A1(FPSENCOS_d_ff2_X[18]), .B0(n4674), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1969) );
AO22XLTS U3146 ( .A0(n4569), .A1(FPSENCOS_d_ff2_X[15]), .B0(n4548), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1975) );
AO22XLTS U3147 ( .A0(n4546), .A1(FPSENCOS_d_ff2_X[22]), .B0(n4674), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1961) );
AO22XLTS U3148 ( .A0(n4532), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n4531), .B1(
Data_1[31]), .Y(n2082) );
AO22XLTS U3149 ( .A0(n4532), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n4531), .B1(
Data_1[30]), .Y(n2083) );
AO22XLTS U3150 ( .A0(n4532), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n4531), .B1(
Data_1[29]), .Y(n2084) );
AO22XLTS U3151 ( .A0(n4532), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n4531), .B1(
Data_1[28]), .Y(n2085) );
AO22XLTS U3152 ( .A0(n4532), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n4530), .B1(
Data_1[27]), .Y(n2086) );
AO22XLTS U3153 ( .A0(n4532), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n4531), .B1(
Data_1[26]), .Y(n2087) );
AO22XLTS U3154 ( .A0(n4529), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n4531), .B1(
Data_1[25]), .Y(n2088) );
AO22XLTS U3155 ( .A0(n4527), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n4528), .B1(
Data_1[24]), .Y(n2089) );
AO22XLTS U3156 ( .A0(n4527), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n4530), .B1(
Data_1[23]), .Y(n2090) );
AO22XLTS U3157 ( .A0(n4527), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n4530), .B1(
Data_1[22]), .Y(n2091) );
AO22XLTS U3158 ( .A0(n4529), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n4530), .B1(
Data_1[21]), .Y(n2092) );
AO22XLTS U3159 ( .A0(n4529), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n4530), .B1(
Data_1[20]), .Y(n2093) );
AO22XLTS U3160 ( .A0(n4529), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n4530), .B1(
Data_1[19]), .Y(n2094) );
AO22XLTS U3161 ( .A0(n4529), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n4530), .B1(
Data_1[18]), .Y(n2095) );
AO22XLTS U3162 ( .A0(n4529), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n4530), .B1(
Data_1[17]), .Y(n2096) );
AO22XLTS U3163 ( .A0(n4527), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n4530), .B1(
Data_1[16]), .Y(n2097) );
AO22XLTS U3164 ( .A0(n4526), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n4530), .B1(
Data_1[15]), .Y(n2098) );
AO22XLTS U3165 ( .A0(n4526), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n4528), .B1(
Data_1[14]), .Y(n2099) );
AO22XLTS U3166 ( .A0(n4526), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n4528), .B1(
Data_1[13]), .Y(n2100) );
AO22XLTS U3167 ( .A0(n4526), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n4528), .B1(
Data_1[12]), .Y(n2101) );
AO22XLTS U3168 ( .A0(n4526), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n4528), .B1(
Data_1[11]), .Y(n2102) );
AO22XLTS U3169 ( .A0(n4526), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n4528), .B1(
Data_1[10]), .Y(n2103) );
AO22XLTS U3170 ( .A0(n4526), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n4528), .B1(
Data_1[9]), .Y(n2104) );
AO22XLTS U3171 ( .A0(n4526), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n4528), .B1(
Data_1[8]), .Y(n2105) );
AO22XLTS U3172 ( .A0(n4526), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n4528), .B1(
Data_1[7]), .Y(n2106) );
AO22XLTS U3173 ( .A0(n4526), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n4528), .B1(
Data_1[6]), .Y(n2107) );
AO22XLTS U3174 ( .A0(n4527), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n4525), .B1(
Data_1[5]), .Y(n2108) );
AO22XLTS U3175 ( .A0(n4527), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n4525), .B1(
Data_1[4]), .Y(n2109) );
AO22XLTS U3176 ( .A0(n4527), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n4525), .B1(
Data_1[3]), .Y(n2110) );
AO22XLTS U3177 ( .A0(n4532), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n4525), .B1(
Data_1[2]), .Y(n2111) );
AO22XLTS U3178 ( .A0(n4532), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n4525), .B1(
Data_1[1]), .Y(n2112) );
AO22XLTS U3179 ( .A0(n4527), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n4525), .B1(
Data_1[0]), .Y(n2113) );
AO22XLTS U3180 ( .A0(n4675), .A1(n2781), .B0(n4674), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1945) );
AOI2BB2XLTS U3181 ( .B0(FPSENCOS_d_ff2_X[30]), .B1(n4561), .A0N(n4561),
.A1N(FPSENCOS_d_ff2_X[30]), .Y(n2781) );
AOI2BB2XLTS U3182 ( .B0(n4602), .B1(n4563), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n4569), .Y(n1946) );
AO22XLTS U3183 ( .A0(n4546), .A1(n2780), .B0(n4548), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1947) );
AOI2BB2XLTS U3184 ( .B0(n4602), .B1(n4560), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n4569), .Y(n1948) );
OAI21XLTS U3185 ( .A0(n2782), .A1(n5088), .B0(n4605), .Y(n2783) );
AO22XLTS U3186 ( .A0(n4675), .A1(n2775), .B0(n4674), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1849) );
OAI21XLTS U3187 ( .A0(n4600), .A1(n5089), .B0(n2774), .Y(n2775) );
AOI2BB2XLTS U3188 ( .B0(n4602), .B1(n4601), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n2776), .Y(n1850) );
AO22XLTS U3189 ( .A0(n2776), .A1(intadd_7_SUM_2_), .B0(n4674), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1851) );
AO22XLTS U3190 ( .A0(n4675), .A1(intadd_7_SUM_1_), .B0(n4599), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1852) );
AO22XLTS U3191 ( .A0(n4567), .A1(intadd_7_SUM_0_), .B0(n4674), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1853) );
AO22XLTS U3192 ( .A0(n2776), .A1(n2779), .B0(n4674), .B1(
FPSENCOS_d_ff3_sh_y_out[23]), .Y(n1854) );
OAI21XLTS U3193 ( .A0(n4553), .A1(n4996), .B0(intadd_7_CI), .Y(n2779) );
AO22XLTS U3194 ( .A0(n4675), .A1(n2778), .B0(n4548), .B1(
FPSENCOS_d_ff3_LUT_out[23]), .Y(n2118) );
OAI21XLTS U3195 ( .A0(n4553), .A1(n2777), .B0(n3162), .Y(n2778) );
AO22XLTS U3196 ( .A0(FPSENCOS_d_ff3_LUT_out[21]), .A1(n4580), .B0(n4522),
.B1(n4521), .Y(n2119) );
OAI211XLTS U3197 ( .A0(n4604), .A1(n5141), .B0(n3237), .C0(n3235), .Y(n2121)
);
OAI211XLTS U3198 ( .A0(n4604), .A1(n5136), .B0(n3234), .C0(n3203), .Y(n2125)
);
AO21XLTS U3199 ( .A0(FPSENCOS_d_ff3_LUT_out[8]), .A1(n4609), .B0(n4518), .Y(
n2126) );
OAI211XLTS U3200 ( .A0(n4604), .A1(n5139), .B0(n3237), .C0(n3234), .Y(n2131)
);
INVX2TS U3201 ( .A(n2211), .Y(n2328) );
BUFX3TS U3202 ( .A(n3220), .Y(n4552) );
AO21X2TS U3203 ( .A0(FPMULT_Op_MX[8]), .A1(n2301), .B0(n4726), .Y(n2208) );
INVX2TS U3204 ( .A(n2624), .Y(n2938) );
CLKBUFX2TS U3205 ( .A(n2938), .Y(n4451) );
CLKBUFX2TS U3206 ( .A(n2646), .Y(n4377) );
INVX2TS U3207 ( .A(n3823), .Y(n4411) );
INVX2TS U3208 ( .A(n2320), .Y(n2322) );
OR2X2TS U3209 ( .A(n3711), .B(n3394), .Y(n2211) );
INVX2TS U3210 ( .A(n4681), .Y(n2331) );
CLKBUFX2TS U3211 ( .A(n2603), .Y(n4681) );
INVX2TS U3212 ( .A(n3075), .Y(n3124) );
INVX2TS U3213 ( .A(n2345), .Y(n4547) );
OR2X1TS U3214 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n2214) );
OR2X1TS U3215 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n3988), .Y(n2215)
);
BUFX3TS U3216 ( .A(n4073), .Y(n4851) );
INVX2TS U3217 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n2264) );
CLKBUFX2TS U3218 ( .A(FPMULT_Op_MX[21]), .Y(n5176) );
INVX2TS U3219 ( .A(n2300), .Y(n4701) );
INVX2TS U3220 ( .A(FPMULT_Op_MX[15]), .Y(n4697) );
INVX2TS U3221 ( .A(n2311), .Y(n4699) );
BUFX3TS U3222 ( .A(n5240), .Y(n5261) );
INVX2TS U3223 ( .A(n2306), .Y(n4703) );
INVX2TS U3224 ( .A(n2303), .Y(n4704) );
INVX2TS U3225 ( .A(n4315), .Y(n2627) );
OAI21X2TS U3226 ( .A0(n2228), .A1(n5075), .B0(n2300), .Y(n2230) );
AOI21X2TS U3227 ( .A0(n2283), .A1(n4725), .B0(mult_x_219_n205), .Y(n2231) );
OAI21X2TS U3228 ( .A0(n2314), .A1(n2366), .B0(n2298), .Y(n2233) );
NOR2X2TS U3229 ( .A(n2317), .B(n5065), .Y(n2234) );
OA21XLTS U3230 ( .A0(n5058), .A1(n2290), .B0(n4734), .Y(n2235) );
OR2X1TS U3231 ( .A(FPMULT_Op_MY[11]), .B(intadd_4_n1), .Y(n2236) );
NAND2X1TS U3232 ( .A(n2936), .B(n2866), .Y(n2237) );
OR2X1TS U3233 ( .A(n4730), .B(n4381), .Y(n2239) );
NAND2X4TS U3234 ( .A(n2282), .B(n2205), .Y(n4008) );
INVX2TS U3235 ( .A(n5031), .Y(n2240) );
INVX2TS U3236 ( .A(n5024), .Y(n2241) );
INVX2TS U3237 ( .A(n5022), .Y(n2242) );
INVX2TS U3238 ( .A(n5023), .Y(n2243) );
INVX2TS U3239 ( .A(n5025), .Y(n2244) );
INVX2TS U3240 ( .A(n5029), .Y(n2245) );
INVX2TS U3241 ( .A(n2239), .Y(n2246) );
INVX2TS U3242 ( .A(n2239), .Y(n2247) );
INVX2TS U3243 ( .A(n4412), .Y(n2249) );
INVX2TS U3244 ( .A(n4412), .Y(n2250) );
INVX2TS U3245 ( .A(n2238), .Y(n2251) );
INVX2TS U3246 ( .A(n2238), .Y(n2252) );
INVX2TS U3247 ( .A(n4377), .Y(n2253) );
INVX2TS U3248 ( .A(n2236), .Y(n2254) );
INVX2TS U3249 ( .A(n2236), .Y(n2255) );
INVX2TS U3250 ( .A(n2194), .Y(n2256) );
INVX2TS U3251 ( .A(n4018), .Y(n2257) );
INVX2TS U3252 ( .A(n4018), .Y(n2258) );
INVX2TS U3253 ( .A(intadd_5_SUM_0_), .Y(n2259) );
INVX2TS U3254 ( .A(n2259), .Y(n2260) );
INVX2TS U3255 ( .A(n2214), .Y(n2261) );
CLKINVX3TS U3256 ( .A(n2214), .Y(n2262) );
INVX2TS U3257 ( .A(n2357), .Y(n2263) );
INVX2TS U3258 ( .A(n2235), .Y(n2266) );
INVX2TS U3259 ( .A(n2235), .Y(n2267) );
INVX2TS U3260 ( .A(n2553), .Y(n3702) );
INVX2TS U3261 ( .A(n2203), .Y(n2269) );
INVX2TS U3262 ( .A(n2203), .Y(n2270) );
INVX2TS U3263 ( .A(n4451), .Y(n2271) );
INVX2TS U3264 ( .A(n4015), .Y(n2273) );
INVX2TS U3265 ( .A(n4015), .Y(n2274) );
INVX2TS U3266 ( .A(n4990), .Y(n2275) );
INVX2TS U3267 ( .A(n2275), .Y(n2276) );
INVX2TS U3268 ( .A(intadd_5_SUM_6_), .Y(n2277) );
INVX2TS U3269 ( .A(n4021), .Y(n2278) );
CLKINVX3TS U3270 ( .A(n4021), .Y(n2279) );
INVX2TS U3271 ( .A(n2213), .Y(n2280) );
INVX2TS U3272 ( .A(n2280), .Y(n2281) );
INVX2TS U3273 ( .A(n2280), .Y(n2282) );
INVX2TS U3274 ( .A(n2204), .Y(n2283) );
INVX2TS U3275 ( .A(n4411), .Y(n2284) );
INVX2TS U3276 ( .A(n2284), .Y(n2285) );
INVX2TS U3277 ( .A(n2319), .Y(n2286) );
INVX2TS U3278 ( .A(n2215), .Y(n2287) );
INVX2TS U3279 ( .A(n2215), .Y(n2288) );
INVX2TS U3280 ( .A(n2291), .Y(n2289) );
INVX2TS U3281 ( .A(FPMULT_Op_MX[17]), .Y(n2290) );
INVX2TS U3282 ( .A(n2290), .Y(n2291) );
INVX2TS U3283 ( .A(n2290), .Y(n2292) );
INVX2TS U3284 ( .A(intadd_5_SUM_2_), .Y(n2293) );
INVX2TS U3285 ( .A(n2293), .Y(n2294) );
INVX2TS U3286 ( .A(n2293), .Y(n2295) );
INVX2TS U3287 ( .A(intadd_5_SUM_4_), .Y(n2296) );
INVX2TS U3288 ( .A(n2296), .Y(n2297) );
INVX2TS U3289 ( .A(n2296), .Y(n2298) );
INVX2TS U3290 ( .A(FPMULT_Op_MX[7]), .Y(n2299) );
INVX2TS U3291 ( .A(n2299), .Y(n2300) );
INVX2TS U3292 ( .A(n2299), .Y(n2301) );
INVX2TS U3293 ( .A(FPMULT_Op_MX[3]), .Y(n2302) );
INVX2TS U3294 ( .A(n2302), .Y(n2303) );
INVX2TS U3295 ( .A(n2302), .Y(n2304) );
INVX2TS U3296 ( .A(FPMULT_Op_MX[5]), .Y(n2305) );
INVX2TS U3297 ( .A(n2305), .Y(n2306) );
INVX2TS U3298 ( .A(n2305), .Y(n2307) );
INVX2TS U3299 ( .A(FPMULT_Op_MX[15]), .Y(n2308) );
INVX2TS U3300 ( .A(n2308), .Y(n2309) );
INVX2TS U3301 ( .A(FPMULT_Op_MX[9]), .Y(n2310) );
INVX2TS U3302 ( .A(n2310), .Y(n2311) );
INVX2TS U3303 ( .A(n2310), .Y(n2312) );
INVX2TS U3304 ( .A(intadd_5_SUM_2_), .Y(n2313) );
INVX2TS U3305 ( .A(intadd_5_SUM_2_), .Y(n2314) );
INVX2TS U3306 ( .A(n4993), .Y(n2315) );
INVX2TS U3307 ( .A(n2315), .Y(n2316) );
INVX2TS U3308 ( .A(n2315), .Y(n2317) );
INVX2TS U3309 ( .A(FPMULT_Op_MX[19]), .Y(n2318) );
INVX2TS U3310 ( .A(n2318), .Y(n2319) );
INVX2TS U3311 ( .A(intadd_5_SUM_8_), .Y(n2320) );
INVX2TS U3312 ( .A(n2320), .Y(n2321) );
INVX2TS U3313 ( .A(n5176), .Y(n2323) );
INVX2TS U3314 ( .A(n2323), .Y(n2324) );
INVX2TS U3315 ( .A(n2323), .Y(n2325) );
INVX2TS U3316 ( .A(n2331), .Y(n2332) );
INVX2TS U3317 ( .A(n2331), .Y(n2333) );
INVX2TS U3318 ( .A(n3705), .Y(n2335) );
INVX2TS U3319 ( .A(n3705), .Y(n2336) );
INVX2TS U3320 ( .A(FPMULT_Op_MX[1]), .Y(n2337) );
INVX2TS U3321 ( .A(n2337), .Y(n2338) );
INVX2TS U3322 ( .A(n2337), .Y(n2339) );
INVX2TS U3323 ( .A(n2337), .Y(n2340) );
INVX2TS U3324 ( .A(n3124), .Y(n2341) );
INVX2TS U3325 ( .A(n2341), .Y(n2342) );
INVX2TS U3326 ( .A(n2341), .Y(n2343) );
INVX2TS U3327 ( .A(n2344), .Y(n2345) );
INVX2TS U3328 ( .A(n4851), .Y(n2346) );
INVX2TS U3329 ( .A(n2346), .Y(n2347) );
INVX2TS U3330 ( .A(n2346), .Y(n2348) );
CLKINVX3TS U3331 ( .A(n5176), .Y(n2349) );
CLKINVX3TS U3332 ( .A(n5176), .Y(n2350) );
AOI21X2TS U3333 ( .A0(n3467), .A1(n5001), .B0(n3463), .Y(n3686) );
OAI21XLTS U3334 ( .A0(n2974), .A1(n3961), .B0(n3062), .Y(n1566) );
NOR2X1TS U3335 ( .A(n2210), .B(n4297), .Y(mult_x_219_n151) );
OAI21XLTS U3336 ( .A0(n3614), .A1(n2435), .B0(n3665), .Y(n1414) );
OAI2BB2X1TS U3337 ( .B0(n4365), .B1(n4364), .A0N(n4363), .A1N(n4362), .Y(
mult_x_254_n200) );
OAI2BB2X1TS U3338 ( .B0(n4420), .B1(n4418), .A0N(n2905), .A1N(n2894), .Y(
DP_OP_454J1_123_2743_n204) );
OAI2BB2X1TS U3339 ( .B0(n4359), .B1(n4358), .A0N(n4357), .A1N(n4356), .Y(
mult_x_254_n192) );
OAI2BB2X1TS U3340 ( .B0(n4428), .B1(n4424), .A0N(n2897), .A1N(n2898), .Y(
DP_OP_454J1_123_2743_n219) );
OAI2BB2X1TS U3341 ( .B0(n4428), .B1(n2656), .A0N(n2897), .A1N(n2655), .Y(
DP_OP_454J1_123_2743_n223) );
INVX1TS U3342 ( .A(n4732), .Y(n4733) );
OAI21XLTS U3343 ( .A0(n3241), .A1(n3194), .B0(n3193), .Y(n1732) );
OAI21XLTS U3344 ( .A0(n4507), .A1(n3217), .B0(n3216), .Y(n1319) );
NAND2X2TS U3345 ( .A(n3781), .B(intadd_5_SUM_0_), .Y(n3793) );
AOI211XLTS U3346 ( .A0(n4714), .A1(n4734), .B0(n4287), .C0(mult_x_219_n177),
.Y(mult_x_219_n129) );
OAI2BB2X1TS U3347 ( .B0(n4320), .B1(n2308), .A0N(n4320), .A1N(n2812), .Y(
mult_x_219_n206) );
NOR2X2TS U3348 ( .A(n5054), .B(n4513), .Y(n4512) );
OAI33X1TS U3349 ( .A0(n4714), .A1(FPMULT_Op_MX[18]), .A2(n2318), .B0(n2373),
.B1(n5058), .B2(n2198), .Y(n2642) );
OAI33X1TS U3350 ( .A0(FPMULT_Op_MY[0]), .A1(FPMULT_Op_MX[6]), .A2(n2225),
.B0(n4990), .B1(n5075), .B2(n2301), .Y(n2641) );
AOI222X1TS U3351 ( .A0(n3013), .A1(n2664), .B0(n3013), .B1(n2587), .C0(n2663), .C1(n2586), .Y(n2591) );
INVX2TS U3352 ( .A(n4746), .Y(n4705) );
NOR2X2TS U3353 ( .A(n4780), .B(n4778), .Y(n2972) );
AOI222X1TS U3354 ( .A0(n4781), .A1(n4780), .B0(n4781), .B1(n4779), .C0(n4778), .C1(n4777), .Y(n4782) );
INVX2TS U3355 ( .A(n4780), .Y(n4777) );
NOR2X2TS U3356 ( .A(intadd_0_SUM_23_), .B(n2671), .Y(n4780) );
NOR2X2TS U3357 ( .A(n4771), .B(n4769), .Y(n4768) );
NOR2X2TS U3358 ( .A(n2301), .B(FPMULT_Op_MX[8]), .Y(n4726) );
OAI33X4TS U3359 ( .A0(FPMULT_Op_MY[0]), .A1(FPMULT_Op_MX[8]), .A2(n2227),
.B0(n4990), .B1(n5077), .B2(n2312), .Y(n2844) );
NOR2X2TS U3360 ( .A(n2303), .B(FPMULT_Op_MX[4]), .Y(n4727) );
NAND2X4TS U3361 ( .A(n4064), .B(n4880), .Y(n4058) );
OAI211XLTS U3362 ( .A0(n4761), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[19]),
.B0(n4798), .C0(n4759), .Y(n4760) );
NOR2X2TS U3363 ( .A(n4764), .B(n4762), .Y(n4761) );
NAND3X2TS U3364 ( .A(n3475), .B(n3474), .C(n3473), .Y(n3704) );
AOI32X1TS U3365 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n3392), .A2(
n5003), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n3691), .Y(n3215)
);
NOR2X2TS U3366 ( .A(n2307), .B(FPMULT_Op_MX[6]), .Y(n4729) );
INVX2TS U3367 ( .A(n2593), .Y(n3182) );
NOR3BX2TS U3368 ( .AN(n4280), .B(n4282), .C(mult_x_219_n162), .Y(
mult_x_219_n106) );
NOR2X2TS U3369 ( .A(n2373), .B(n2263), .Y(mult_x_219_n162) );
NOR2X2TS U3370 ( .A(n4999), .B(FPMULT_Op_MX[12]), .Y(n3865) );
INVX2TS U3371 ( .A(n3148), .Y(n3186) );
AOI211X1TS U3372 ( .A0(n2283), .A1(n4732), .B0(n2820), .C0(mult_x_219_n191),
.Y(mult_x_219_n136) );
OAI21X2TS U3373 ( .A0(n4697), .A1(n5057), .B0(n2291), .Y(mult_x_219_n191) );
CLKBUFX3TS U3374 ( .A(n5261), .Y(n5248) );
NOR2X2TS U3375 ( .A(n5047), .B(n5170), .Y(mult_x_254_n37) );
NOR2X2TS U3376 ( .A(n5045), .B(n5170), .Y(mult_x_254_n63) );
NOR2X2TS U3377 ( .A(n2276), .B(n4338), .Y(mult_x_254_n168) );
BUFX3TS U3378 ( .A(n2614), .Y(n5217) );
CLKBUFX3TS U3379 ( .A(n2610), .Y(n2608) );
AOI222X1TS U3380 ( .A0(n3397), .A1(cordic_result[1]), .B0(n3398), .B1(
FPSENCOS_d_ff_Xn[1]), .C0(n3399), .C1(FPSENCOS_d_ff_Yn[1]), .Y(n3400)
);
AOI222X1TS U3381 ( .A0(n3503), .A1(cordic_result[23]), .B0(n3502), .B1(
FPSENCOS_d_ff_Xn[23]), .C0(n3501), .C1(FPSENCOS_d_ff_Yn[23]), .Y(n3504) );
CLKBUFX3TS U3382 ( .A(n2784), .Y(n2612) );
AOI222X1TS U3383 ( .A0(n3503), .A1(cordic_result[30]), .B0(n3411), .B1(
FPSENCOS_d_ff_Xn[30]), .C0(n3412), .C1(FPSENCOS_d_ff_Yn[30]), .Y(n3388) );
AOI222X1TS U3384 ( .A0(n3503), .A1(cordic_result[25]), .B0(n3502), .B1(
FPSENCOS_d_ff_Xn[25]), .C0(n3501), .C1(FPSENCOS_d_ff_Yn[25]), .Y(n3485) );
AOI222X1TS U3385 ( .A0(n3499), .A1(cordic_result[24]), .B0(n3502), .B1(
FPSENCOS_d_ff_Xn[24]), .C0(n3501), .C1(FPSENCOS_d_ff_Yn[24]), .Y(n3483) );
AOI222X1TS U3386 ( .A0(n3503), .A1(cordic_result[27]), .B0(n3502), .B1(
FPSENCOS_d_ff_Xn[27]), .C0(n3501), .C1(FPSENCOS_d_ff_Yn[27]), .Y(n3494) );
AOI222X1TS U3387 ( .A0(n3503), .A1(cordic_result[26]), .B0(n3502), .B1(
FPSENCOS_d_ff_Xn[26]), .C0(n3501), .C1(FPSENCOS_d_ff_Yn[26]), .Y(n3488) );
AOI222X1TS U3388 ( .A0(n3503), .A1(cordic_result[29]), .B0(n3502), .B1(
FPSENCOS_d_ff_Xn[29]), .C0(n3501), .C1(FPSENCOS_d_ff_Yn[29]), .Y(n3489) );
NOR2X1TS U3389 ( .A(n5110), .B(FPADDSUB_DMP_SFG[11]), .Y(n2505) );
NOR2X1TS U3390 ( .A(n5105), .B(FPADDSUB_DMP_SFG[21]), .Y(n2525) );
AOI21X2TS U3391 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2262), .B0(n3986),
.Y(n4045) );
OAI221X1TS U3392 ( .A0(FPADDSUB_intDX_EWSW[28]), .A1(n4998), .B0(n5068),
.B1(FPADDSUB_intDY_EWSW[28]), .C0(n4925), .Y(n4935) );
OAI21X2TS U3393 ( .A0(n3479), .A1(FPADDSUB_Raw_mant_NRM_SWR[17]), .B0(n3437),
.Y(n3689) );
NAND2X1TS U3394 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B(n4497),
.Y(n4062) );
INVX2TS U3395 ( .A(n4411), .Y(n2353) );
AOI21X2TS U3396 ( .A0(n3703), .A1(n5001), .B0(n3647), .Y(n3754) );
INVX2TS U3397 ( .A(FPADDSUB_intDX_EWSW[24]), .Y(n3602) );
AOI22X2TS U3398 ( .A0(n3467), .A1(n5070), .B0(n3466), .B1(n2538), .Y(n3685)
);
INVX2TS U3399 ( .A(n2237), .Y(n2354) );
INVX2TS U3400 ( .A(n2237), .Y(n2355) );
INVX2TS U3401 ( .A(n2208), .Y(n2356) );
NOR4X2TS U3402 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .C(FPADDSUB_Raw_mant_NRM_SWR[7]), .D(
FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n3139) );
INVX2TS U3403 ( .A(n4298), .Y(n2357) );
OAI21X2TS U3404 ( .A0(mult_x_254_n225), .A1(n5076), .B0(n2303), .Y(
mult_x_254_n211) );
CLKINVX3TS U3405 ( .A(n2338), .Y(mult_x_254_n225) );
NAND2X1TS U3406 ( .A(n4297), .B(n4280), .Y(n4298) );
AOI21X2TS U3407 ( .A0(n3470), .A1(n5019), .B0(n3459), .Y(n3752) );
NOR2X2TS U3408 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n3951) );
NOR3X2TS U3409 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n3134) );
NOR2X1TS U3410 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n2537) );
NOR2X2TS U3411 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n2606),
.Y(n3136) );
NOR4BX1TS U3412 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .D(n2606), .Y(n2535) );
NOR4X2TS U3413 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n2600) );
NOR3X1TS U3414 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3135) );
OAI32X4TS U3415 ( .A0(n3470), .A1(FPADDSUB_Raw_mant_NRM_SWR[0]), .A2(n2538),
.B0(n3701), .B1(n3703), .Y(n4659) );
AOI222X1TS U3416 ( .A0(n3764), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DmP_EXP_EWSW[23]), .B1(n4904), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n3765), .Y(n3761) );
AOI221X1TS U3417 ( .A0(n2420), .A1(FPADDSUB_intDY_EWSW[0]), .B0(
FPADDSUB_intDY_EWSW[16]), .B1(n3563), .C0(n4929), .Y(n4930) );
NOR2X2TS U3418 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(n2568), .Y(n3141) );
OAI221X1TS U3419 ( .A0(n5061), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n2428),
.B1(FPADDSUB_intDY_EWSW[5]), .C0(n4922), .Y(n4937) );
AOI221X1TS U3420 ( .A0(n3511), .A1(FPADDSUB_intDY_EWSW[4]), .B0(
FPADDSUB_intDY_EWSW[26]), .B1(n5051), .C0(n4927), .Y(n4932) );
AOI221X1TS U3421 ( .A0(n4997), .A1(FPADDSUB_intDY_EWSW[25]), .B0(
FPADDSUB_intDY_EWSW[29]), .B1(n5059), .C0(n4928), .Y(n4931) );
AOI221X1TS U3422 ( .A0(n3550), .A1(FPADDSUB_intDY_EWSW[12]), .B0(
FPADDSUB_intDY_EWSW[17]), .B1(n3584), .C0(n4926), .Y(n4933) );
OAI221XLTS U3423 ( .A0(n2412), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n2434),
.B1(FPADDSUB_intDY_EWSW[15]), .C0(n4917), .Y(n4918) );
OAI221XLTS U3424 ( .A0(n2413), .A1(FPADDSUB_intDY_EWSW[27]), .B0(n2406),
.B1(FPADDSUB_intDY_EWSW[11]), .C0(n4915), .Y(n4920) );
OAI221X1TS U3425 ( .A0(n2427), .A1(FPADDSUB_intDY_EWSW[9]), .B0(n2421), .B1(
FPADDSUB_intDY_EWSW[3]), .C0(n4907), .Y(n4912) );
AOI221X1TS U3426 ( .A0(n2424), .A1(FPADDSUB_intDY_EWSW[13]), .B0(
FPADDSUB_intDY_EWSW[22]), .B1(n2431), .C0(n4924), .Y(n4925) );
OAI221XLTS U3427 ( .A0(n2405), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n2426),
.B1(FPADDSUB_intDY_EWSW[7]), .C0(n4923), .Y(n4936) );
OAI221XLTS U3428 ( .A0(n2414), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n2411),
.B1(FPADDSUB_intDY_EWSW[2]), .C0(n4909), .Y(n4910) );
NOR2X1TS U3429 ( .A(FPADDSUB_intDY_EWSW[20]), .B(n3590), .Y(n3576) );
OAI221X1TS U3430 ( .A0(n2407), .A1(FPADDSUB_intDY_EWSW[20]), .B0(n2430),
.B1(FPADDSUB_intDY_EWSW[10]), .C0(n4914), .Y(n4921) );
NOR2X1TS U3431 ( .A(FPADDSUB_intDY_EWSW[6]), .B(n3522), .Y(n3524) );
OAI221X1TS U3432 ( .A0(n2417), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2429),
.B1(FPADDSUB_intDY_EWSW[6]), .C0(n4916), .Y(n4919) );
INVX2TS U3433 ( .A(intadd_5_SUM_6_), .Y(n2358) );
INVX2TS U3434 ( .A(n2358), .Y(n2359) );
INVX2TS U3435 ( .A(n4866), .Y(n2360) );
INVX2TS U3436 ( .A(n4866), .Y(n4972) );
NOR2X2TS U3437 ( .A(n2589), .B(FPMULT_FS_Module_state_reg[1]), .Y(
FPMULT_FSM_exp_operation_A_S) );
AOI31XLTS U3438 ( .A0(n4469), .A1(n4468), .A2(n4467), .B0(dataB[27]), .Y(
n4480) );
OAI2BB2X1TS U3439 ( .B0(n4320), .B1(n4317), .A0N(n4266), .A1N(n2837), .Y(
mult_x_219_n210) );
OAI2BB2X1TS U3440 ( .B0(n4373), .B1(n4372), .A0N(n4371), .A1N(n4370), .Y(
mult_x_254_n216) );
OAI21XLTS U3441 ( .A0(FPSENCOS_d_ff3_LUT_out[26]), .A1(n4602), .B0(n4523),
.Y(n4524) );
OAI2BB2X1TS U3442 ( .B0(n4304), .B1(n4301), .A0N(n3806), .A1N(n2787), .Y(
mult_x_219_n170) );
OAI2BB2X1TS U3443 ( .B0(n4444), .B1(n4443), .A0N(n4442), .A1N(n4441), .Y(
DP_OP_454J1_123_2743_n240) );
OAI2BB2X1TS U3444 ( .B0(n2267), .B1(n4309), .A0N(n3860), .A1N(n2839), .Y(
mult_x_219_n186) );
OAI2BB2X1TS U3445 ( .B0(n2208), .B1(n4348), .A0N(n4347), .A1N(n4346), .Y(
mult_x_254_n176) );
OAI21XLTS U3446 ( .A0(n4520), .A1(n3164), .B0(n3163), .Y(n2117) );
NOR4BX2TS U3447 ( .AN(n3130), .B(n3129), .C(n3213), .D(n3128), .Y(n3133) );
OAI2BB2X1TS U3448 ( .B0(n2253), .B1(n4336), .A0N(n2246), .A1N(n3830), .Y(
mult_x_254_n165) );
OAI2BB2X1TS U3449 ( .B0(n4420), .B1(n2645), .A0N(n2905), .A1N(n2802), .Y(
DP_OP_454J1_123_2743_n210) );
BUFX3TS U3450 ( .A(n2776), .Y(n4602) );
NOR2X1TS U3451 ( .A(n3472), .B(FPADDSUB_ADD_OVRFLW_NRM), .Y(n2553) );
OR2X1TS U3452 ( .A(n2816), .B(n2815), .Y(n2823) );
INVX2TS U3453 ( .A(n2823), .Y(n2362) );
NOR2X2TS U3454 ( .A(FPMULT_Op_MX[15]), .B(n5074), .Y(n2812) );
NOR2X2TS U3455 ( .A(n4429), .B(n3822), .Y(n3789) );
OAI33X4TS U3456 ( .A0(FPSENCOS_d_ff1_shift_region_flag_out[1]), .A1(
FPSENCOS_d_ff1_operation_out), .A2(n4687), .B0(n2223), .B1(n5072),
.B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n4688) );
NOR2X2TS U3457 ( .A(n3787), .B(n3786), .Y(n3816) );
OAI211XLTS U3458 ( .A0(n4773), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[15]),
.B0(n4798), .C0(n4771), .Y(n4772) );
NOR2X2TS U3459 ( .A(n4775), .B(n4774), .Y(n4773) );
OAI211XLTS U3460 ( .A0(n4756), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[21]),
.B0(n4798), .C0(n4754), .Y(n4755) );
NOR2X2TS U3461 ( .A(n4759), .B(n4757), .Y(n4756) );
NOR2X2TS U3462 ( .A(n2338), .B(FPMULT_Op_MX[2]), .Y(n4731) );
NOR2X2TS U3463 ( .A(n2664), .B(n2663), .Y(n4784) );
NOR3BX2TS U3464 ( .AN(n4283), .B(n4285), .C(mult_x_219_n163), .Y(
mult_x_219_n119) );
OAI21X2TS U3465 ( .A0(n2286), .A1(n5063), .B0(n2325), .Y(mult_x_219_n163) );
AOI21X2TS U3466 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_right[15]), .A1(n4812),
.B0(n4813), .Y(n4807) );
OAI21X2TS U3467 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_right[19]), .A1(n2750),
.B0(n2749), .Y(n2734) );
OAI21X2TS U3468 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .A1(n4792),
.B0(n4791), .Y(n2746) );
NOR2X2TS U3469 ( .A(FPSENCOS_cont_iter_out[3]), .B(FPSENCOS_cont_iter_out[2]), .Y(n3219) );
NAND2X2TS U3470 ( .A(n2363), .B(n2364), .Y(n3795) );
INVX2TS U3471 ( .A(n4422), .Y(n2365) );
INVX2TS U3472 ( .A(intadd_5_SUM_3_), .Y(n2366) );
NAND2X1TS U3473 ( .A(n2365), .B(n2293), .Y(n2363) );
NAND2X1TS U3474 ( .A(n2365), .B(n2366), .Y(n2364) );
OAI21X2TS U3475 ( .A0(n2290), .A1(n5058), .B0(n2198), .Y(mult_x_219_n177) );
CLKBUFX2TS U3476 ( .A(n4413), .Y(n2367) );
OR2X1TS U3477 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n4194) );
OR2X1TS U3478 ( .A(n5118), .B(FPADDSUB_DMP_SFG[9]), .Y(n2499) );
NOR2X2TS U3479 ( .A(n2276), .B(n4359), .Y(mult_x_254_n196) );
NOR4X2TS U3480 ( .A(n4381), .B(mult_x_254_n168), .C(n4330), .D(n4335), .Y(
mult_x_254_n106) );
OAI33X4TS U3481 ( .A0(FPMULT_Op_MX[10]), .A1(n2311), .A2(n4335), .B0(n5090),
.B1(n2310), .B2(FPMULT_Op_MX[11]), .Y(n2646) );
CLKBUFX3TS U3482 ( .A(n5170), .Y(n4335) );
BUFX3TS U3483 ( .A(n2610), .Y(n2609) );
XOR2XLTS U3484 ( .A(n2976), .B(n2975), .Y(n2977) );
AOI222X4TS U3485 ( .A0(n2976), .A1(n2975), .B0(n2976), .B1(
FPMULT_Sgf_operation_EVEN1_Q_left[13]), .C0(n2975), .C1(
FPMULT_Sgf_operation_EVEN1_Q_left[13]), .Y(n4775) );
AOI222X4TS U3486 ( .A0(n3503), .A1(cordic_result[0]), .B0(n3398), .B1(
FPSENCOS_d_ff_Xn[0]), .C0(n3399), .C1(FPSENCOS_d_ff_Yn[0]), .Y(n3406)
);
NOR2X2TS U3487 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n2711) );
NOR2X2TS U3488 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n2763) );
NOR2X2TS U3489 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n2758) );
NOR4X1TS U3490 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_Op_MX[26]), .C(
FPMULT_Op_MX[11]), .D(FPMULT_Op_MX[24]), .Y(n4739) );
AOI21X2TS U3491 ( .A0(n2262), .A1(FPADDSUB_Data_array_SWR[25]), .B0(n3981),
.Y(n4057) );
INVX2TS U3492 ( .A(FPADDSUB_intDX_EWSW[29]), .Y(n3620) );
AOI21X2TS U3493 ( .A0(n2262), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n3981),
.Y(n4053) );
OAI21XLTS U3494 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n2224), .B0(
intadd_6_CI), .Y(n4852) );
NOR2XLTS U3495 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n3891) );
OAI2BB1X1TS U3496 ( .A0N(n2439), .A1N(n2481), .B0(n4070), .Y(n2456) );
NAND2X2TS U3497 ( .A(n4861), .B(n4070), .Y(n4860) );
INVX2TS U3498 ( .A(FPADDSUB_intDX_EWSW[25]), .Y(n3603) );
OAI21X2TS U3499 ( .A0(n3479), .A1(FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n3449),
.Y(n3696) );
OAI21X2TS U3500 ( .A0(n3479), .A1(n5039), .B0(n3446), .Y(n3692) );
AOI21X2TS U3501 ( .A0(n3703), .A1(n5070), .B0(n3456), .Y(n3755) );
BUFX3TS U3502 ( .A(n3043), .Y(n3703) );
NOR3BX2TS U3503 ( .AN(n4331), .B(n4333), .C(mult_x_254_n169), .Y(
mult_x_254_n119) );
OAI21X2TS U3504 ( .A0(n2299), .A1(n5077), .B0(n2311), .Y(mult_x_254_n169) );
CLKBUFX2TS U3505 ( .A(n4447), .Y(n2368) );
AOI22X2TS U3506 ( .A0(n3467), .A1(n5019), .B0(n3465), .B1(n3464), .Y(n3684)
);
OAI211XLTS U3507 ( .A0(n5133), .A1(n3079), .B0(n3078), .C0(n3077), .Y(n1523)
);
INVX2TS U3508 ( .A(n5021), .Y(n2369) );
CMPR32X4TS U3509 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[13]), .C(intadd_4_CI), .CO(intadd_4_n10), .S(intadd_4_SUM_0_) );
INVX2TS U3510 ( .A(n2327), .Y(n2370) );
INVX2TS U3511 ( .A(intadd_5_SUM_8_), .Y(n2371) );
AOI31XLTS U3512 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n2556), .A2(n5007),
.B0(n2547), .Y(n2551) );
NOR2X4TS U3513 ( .A(FPMULT_Op_MX[13]), .B(n5066), .Y(n3864) );
INVX2TS U3514 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .Y(n3733) );
NOR3X1TS U3515 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n4849), .Y(n4748) );
NOR2X2TS U3516 ( .A(FPSENCOS_d_ff2_X[29]), .B(n4562), .Y(n4561) );
CLKINVX3TS U3517 ( .A(n3848), .Y(n4359) );
AOI21X2TS U3518 ( .A0(FPMULT_Op_MX[6]), .A1(n2307), .B0(n4729), .Y(n3848) );
INVX2TS U3519 ( .A(n2866), .Y(n2372) );
OAI21X2TS U3520 ( .A0(n2359), .A1(intadd_5_SUM_7_), .B0(n2865), .Y(n2866) );
AOI211X1TS U3521 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n2288), .B0(n3991),
.C0(n3990), .Y(n4046) );
OAI2BB2X1TS U3522 ( .B0(n4315), .B1(n4314), .A0N(n4313), .A1N(n2628), .Y(
mult_x_219_n194) );
OAI32X1TS U3523 ( .A0(n2292), .A1(n2248), .A2(n5057), .B0(n4315), .B1(n2289),
.Y(mult_x_219_n192) );
OAI21X2TS U3524 ( .A0(n5057), .A1(n2226), .B0(n4732), .Y(n4315) );
CLKBUFX2TS U3525 ( .A(n2283), .Y(n4714) );
INVX2TS U3526 ( .A(n4714), .Y(n2373) );
INVX2TS U3527 ( .A(n4714), .Y(n2374) );
AOI21X4TS U3528 ( .A0(n2276), .A1(n2373), .B0(intadd_4_CI), .Y(n4412) );
OAI33X4TS U3529 ( .A0(n2283), .A1(FPMULT_Op_MX[16]), .A2(n2201), .B0(n2373),
.B1(n5057), .B2(n2291), .Y(n4269) );
AOI32X1TS U3530 ( .A0(n2309), .A1(n2374), .A2(n5074), .B0(n2812), .B1(n2283),
.Y(n2813) );
INVX2TS U3531 ( .A(intadd_5_SUM_4_), .Y(n2375) );
NOR2X4TS U3532 ( .A(n4509), .B(rst), .Y(n2784) );
NOR3BX1TS U3533 ( .AN(n3134), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .Y(n2534) );
OAI32X1TS U3534 ( .A0(n4990), .A1(n2303), .A2(n5076), .B0(FPMULT_Op_MY[0]),
.B1(mult_x_254_n211), .Y(n2847) );
OR2X1TS U3535 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n2527) );
OR2X1TS U3536 ( .A(n5114), .B(FPADDSUB_DMP_SFG[18]), .Y(n2519) );
OR2X1TS U3537 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]),
.Y(n4141) );
OR2X1TS U3538 ( .A(n5116), .B(FPADDSUB_DMP_SFG[14]), .Y(n2511) );
OR2X1TS U3539 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]),
.Y(n4171) );
OR2X1TS U3540 ( .A(n5115), .B(FPADDSUB_DMP_SFG[16]), .Y(n2515) );
OR2X1TS U3541 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]),
.Y(n4075) );
OR2X1TS U3542 ( .A(n5113), .B(FPADDSUB_DMP_SFG[20]), .Y(n2523) );
NOR2X2TS U3543 ( .A(FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n3138) );
OR2X1TS U3544 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]),
.Y(n4162) );
NAND2X1TS U3545 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n4161) );
NAND2X1TS U3546 ( .A(FPMULT_Sgf_normalized_result[3]), .B(
FPMULT_Sgf_normalized_result[2]), .Y(n3897) );
NOR2XLTS U3547 ( .A(n3948), .B(FPMULT_Sgf_normalized_result[2]), .Y(n3949)
);
AOI21X2TS U3548 ( .A0(n2262), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n3981),
.Y(n4047) );
AOI21X2TS U3549 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2261), .B0(n3982),
.Y(n4041) );
NOR2X1TS U3550 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]),
.Y(n4179) );
NAND2X1TS U3551 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n4180) );
OAI21XLTS U3552 ( .A0(n3923), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
n2966), .Y(n1621) );
NOR2X1TS U3553 ( .A(n2212), .B(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.Y(n4502) );
NOR3X2TS U3554 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .C(n3125), .Y(n2541) );
NOR2X1TS U3555 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n3125), .Y(n2556) );
NOR2X1TS U3556 ( .A(FPADDSUB_intDY_EWSW[29]), .B(n3620), .Y(n3622) );
NAND2X1TS U3557 ( .A(FPADDSUB_intDY_EWSW[29]), .B(n3620), .Y(n3621) );
OR2X1TS U3558 ( .A(FPADDSUB_intDY_EWSW[25]), .B(n3603), .Y(n2376) );
OR2X1TS U3559 ( .A(FPADDSUB_intDY_EWSW[26]), .B(n3604), .Y(n2378) );
OR2X1TS U3560 ( .A(FPADDSUB_intDY_EWSW[27]), .B(n3614), .Y(n2382) );
OR2X1TS U3561 ( .A(FPADDSUB_intDY_EWSW[28]), .B(n5068), .Y(n2383) );
OR2X1TS U3562 ( .A(FPADDSUB_intDY_EWSW[0]), .B(n2420), .Y(n2394) );
INVX2TS U3563 ( .A(FPADDSUB_intDX_EWSW[8]), .Y(n3527) );
INVX2TS U3564 ( .A(FPADDSUB_intDX_EWSW[14]), .Y(n3558) );
INVX2TS U3565 ( .A(FPADDSUB_intDX_EWSW[11]), .Y(n3549) );
INVX2TS U3566 ( .A(FPADDSUB_intDX_EWSW[20]), .Y(n3590) );
CLKAND2X2TS U3567 ( .A(FPADDSUB_intDY_EWSW[17]), .B(n3584), .Y(n2408) );
OR2X1TS U3568 ( .A(FPADDSUB_intDY_EWSW[17]), .B(n3584), .Y(n2409) );
INVX2TS U3569 ( .A(FPADDSUB_intDX_EWSW[2]), .Y(n3505) );
INVX2TS U3570 ( .A(FPADDSUB_intDX_EWSW[18]), .Y(n3585) );
INVX2TS U3571 ( .A(FPADDSUB_intDX_EWSW[27]), .Y(n3614) );
INVX2TS U3572 ( .A(FPADDSUB_intDX_EWSW[19]), .Y(n3586) );
BUFX3TS U3573 ( .A(n3397), .Y(n3495) );
CLKBUFX2TS U3574 ( .A(n3399), .Y(n3412) );
CLKBUFX2TS U3575 ( .A(n3398), .Y(n3411) );
INVX2TS U3576 ( .A(FPADDSUB_intDX_EWSW[16]), .Y(n3563) );
INVX2TS U3577 ( .A(FPADDSUB_intDX_EWSW[17]), .Y(n3584) );
INVX2TS U3578 ( .A(FPADDSUB_intDX_EWSW[21]), .Y(n3591) );
CLKAND2X2TS U3579 ( .A(FPADDSUB_intDY_EWSW[1]), .B(n4906), .Y(n2418) );
OR2X1TS U3580 ( .A(FPADDSUB_intDY_EWSW[1]), .B(n4906), .Y(n2419) );
INVX2TS U3581 ( .A(FPADDSUB_intDX_EWSW[3]), .Y(n3510) );
INVX2TS U3582 ( .A(FPADDSUB_intDX_EWSW[4]), .Y(n3511) );
INVX2TS U3583 ( .A(FPADDSUB_intDX_EWSW[12]), .Y(n3550) );
INVX2TS U3584 ( .A(FPADDSUB_intDX_EWSW[7]), .Y(n3526) );
INVX2TS U3585 ( .A(FPADDSUB_intDX_EWSW[9]), .Y(n3544) );
INVX2TS U3586 ( .A(FPADDSUB_intDX_EWSW[5]), .Y(n3521) );
INVX2TS U3587 ( .A(FPADDSUB_intDX_EWSW[6]), .Y(n3522) );
INVX2TS U3588 ( .A(FPADDSUB_intDX_EWSW[10]), .Y(n3545) );
INVX2TS U3589 ( .A(FPADDSUB_intDX_EWSW[22]), .Y(n3598) );
CLKAND2X2TS U3590 ( .A(FPADDSUB_intDY_EWSW[18]), .B(n3585), .Y(n2432) );
OR2X1TS U3591 ( .A(FPADDSUB_intDY_EWSW[18]), .B(n3585), .Y(n2433) );
INVX2TS U3592 ( .A(FPADDSUB_intDX_EWSW[15]), .Y(n3562) );
BUFX3TS U3593 ( .A(n4680), .Y(n3298) );
BUFX3TS U3594 ( .A(n2601), .Y(n4680) );
NOR2X2TS U3595 ( .A(operation[1]), .B(n3319), .Y(n2601) );
AND2X2TS U3596 ( .A(n4488), .B(n4491), .Y(n4527) );
OR2X1TS U3597 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n2437) );
AND2X2TS U3598 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n2455), .Y(n2439) );
BUFX3TS U3599 ( .A(n2602), .Y(n3266) );
INVX2TS U3600 ( .A(FPADDSUB_intDX_EWSW[26]), .Y(n3604) );
INVX2TS U3601 ( .A(FPADDSUB_intDX_EWSW[13]), .Y(n3557) );
NAND2X1TS U3602 ( .A(FPADDSUB_intDY_EWSW[23]), .B(n5053), .Y(n3599) );
NAND2X1TS U3603 ( .A(FPADDSUB_intDY_EWSW[15]), .B(n3562), .Y(n3565) );
NAND2X1TS U3604 ( .A(FPADDSUB_intDY_EWSW[8]), .B(n3527), .Y(n3528) );
OAI211XLTS U3605 ( .A0(n5042), .A1(FPMULT_Op_MX[0]), .B0(n2959), .C0(n2340),
.Y(n2958) );
INVX2TS U3606 ( .A(FPADDSUB_intDX_EWSW[30]), .Y(n3624) );
INVX2TS U3607 ( .A(DP_OP_454J1_123_2743_n58), .Y(n2892) );
INVX2TS U3608 ( .A(n3976), .Y(n3988) );
OR2X1TS U3609 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]),
.Y(n4122) );
INVX2TS U3610 ( .A(n4149), .Y(n4151) );
NOR2XLTS U3611 ( .A(n5018), .B(FPADDSUB_DMP_SFG[0]), .Y(n2483) );
OAI21XLTS U3612 ( .A0(n2832), .A1(n3775), .B0(n2357), .Y(n2831) );
NOR2XLTS U3613 ( .A(n2822), .B(n2821), .Y(n2826) );
OAI21X2TS U3614 ( .A0(n4155), .A1(n4149), .B0(n4150), .Y(n4145) );
OAI21XLTS U3615 ( .A0(n4256), .A1(n4198), .B0(n4238), .Y(n4200) );
OR2X1TS U3616 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n4207) );
NOR2XLTS U3617 ( .A(n2753), .B(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(
n2583) );
NOR2X1TS U3618 ( .A(n3472), .B(n5056), .Y(n3043) );
INVX2TS U3619 ( .A(mult_x_254_n33), .Y(intadd_2_A_17_) );
INVX2TS U3620 ( .A(mult_x_254_n85), .Y(intadd_2_B_9_) );
INVX2TS U3621 ( .A(mult_x_254_n133), .Y(intadd_2_A_2_) );
OAI21XLTS U3622 ( .A0(n2255), .A1(n2271), .B0(intadd_1_n1), .Y(n4455) );
INVX2TS U3623 ( .A(mult_x_219_n41), .Y(intadd_3_A_15_) );
INVX2TS U3624 ( .A(mult_x_219_n102), .Y(intadd_3_B_7_) );
OAI21XLTS U3625 ( .A0(n4248), .A1(n4237), .B0(n4236), .Y(n4241) );
INVX2TS U3626 ( .A(begin_operation), .Y(n4484) );
NOR2XLTS U3627 ( .A(intadd_0_SUM_0_), .B(n4828), .Y(n4827) );
OR2X1TS U3628 ( .A(n3963), .B(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n3417) );
BUFX3TS U3629 ( .A(n3242), .Y(n4649) );
BUFX3TS U3630 ( .A(n3495), .Y(n3499) );
INVX2TS U3631 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n2661) );
CLKBUFX2TS U3632 ( .A(n2773), .Y(n4709) );
NAND2X1TS U3633 ( .A(FPSENCOS_cont_iter_out[2]), .B(n4511), .Y(n4513) );
NOR2XLTS U3634 ( .A(DP_OP_454J1_123_2743_n187), .B(n4454), .Y(intadd_1_B_6_)
);
BUFX3TS U3635 ( .A(n3626), .Y(n3743) );
NAND2X1TS U3636 ( .A(n4087), .B(n5121), .Y(n2473) );
NOR2X1TS U3637 ( .A(n4010), .B(n4009), .Y(n4897) );
BUFX3TS U3638 ( .A(n2435), .Y(n3655) );
NOR2X1TS U3639 ( .A(n4010), .B(n3992), .Y(n4874) );
BUFX3TS U3640 ( .A(n2435), .Y(n3667) );
CLKBUFX2TS U3641 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n4947) );
NAND2X1TS U3642 ( .A(n3961), .B(n2771), .Y(n3079) );
AND3X1TS U3643 ( .A(n3391), .B(n3390), .C(n3389), .Y(n3706) );
OAI21XLTS U3644 ( .A0(n4559), .A1(n5078), .B0(n4562), .Y(n2780) );
OAI21XLTS U3645 ( .A0(n3526), .A1(n2435), .B0(n3662), .Y(n1306) );
OAI21XLTS U3646 ( .A0(n3217), .A1(n2538), .B0(n3215), .Y(n2078) );
OAI21XLTS U3647 ( .A0(n3392), .A1(n2222), .B0(n3479), .Y(n2080) );
OAI21XLTS U3648 ( .A0(n4499), .A1(n4963), .B0(n3151), .Y(op_result[0]) );
OAI21XLTS U3649 ( .A0(n4499), .A1(n4957), .B0(n3158), .Y(op_result[2]) );
OAI21XLTS U3650 ( .A0(n3188), .A1(n4879), .B0(n3184), .Y(op_result[17]) );
NOR4X1TS U3651 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n5174) );
NOR4X1TS U3652 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n5173) );
NOR4X1TS U3653 ( .A(FPMULT_P_Sgf[17]), .B(FPMULT_P_Sgf[16]), .C(
FPMULT_P_Sgf[15]), .D(FPMULT_P_Sgf[13]), .Y(n2448) );
NOR4X1TS U3654 ( .A(FPMULT_P_Sgf[21]), .B(FPMULT_P_Sgf[20]), .C(
FPMULT_P_Sgf[18]), .D(FPMULT_P_Sgf[19]), .Y(n2447) );
NOR4X1TS U3655 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_P_Sgf[5]), .C(
FPMULT_P_Sgf[3]), .D(FPMULT_P_Sgf[4]), .Y(n2443) );
NOR3XLTS U3656 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[2]), .C(
FPMULT_P_Sgf[0]), .Y(n2442) );
NOR4X1TS U3657 ( .A(FPMULT_P_Sgf[14]), .B(FPMULT_P_Sgf[9]), .C(
FPMULT_P_Sgf[10]), .D(FPMULT_P_Sgf[12]), .Y(n2441) );
NOR4X1TS U3658 ( .A(FPMULT_P_Sgf[8]), .B(FPMULT_P_Sgf[6]), .C(
FPMULT_P_Sgf[7]), .D(FPMULT_P_Sgf[11]), .Y(n2440) );
AND4X1TS U3659 ( .A(n2443), .B(n2442), .C(n2441), .D(n2440), .Y(n2446) );
XOR2X1TS U3660 ( .A(FPMULT_Op_MY[31]), .B(FPMULT_Op_MX[31]), .Y(n4749) );
MXI2X1TS U3661 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n4749), .Y(n2444) );
AOI31X1TS U3662 ( .A0(n2448), .A1(n2447), .A2(n2446), .B0(n2445), .Y(n3881)
);
INVX2TS U3663 ( .A(n3881), .Y(n2449) );
NOR2X2TS U3664 ( .A(n5052), .B(FPMULT_FS_Module_state_reg[2]), .Y(n4072) );
NAND2X1TS U3665 ( .A(n4072), .B(n5033), .Y(n2965) );
OAI31X1TS U3666 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(n2449), .A2(n2965),
.B0(n5132), .Y(n1529) );
NOR4X1TS U3667 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n2452) );
NOR4X1TS U3668 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n2451) );
NOR4X1TS U3669 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n2450) );
NOR4X1TS U3670 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n2453),
.Y(n5172) );
INVX2TS U3671 ( .A(result_add_subt[30]), .Y(n4677) );
AND4X1TS U3672 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n2454) );
XNOR2X2TS U3673 ( .A(DP_OP_26J1_124_9022_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n2481) );
NOR2X1TS U3674 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n4213) );
NAND2X1TS U3675 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n4217) );
NAND2X1TS U3676 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n4214) );
OAI21X1TS U3677 ( .A0(n4213), .A1(n4217), .B0(n4214), .Y(n2690) );
NOR2X2TS U3678 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4226) );
NOR2X2TS U3679 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n2686) );
NAND2X1TS U3680 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4227) );
NAND2X1TS U3681 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n2687) );
NOR2X1TS U3682 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n2678) );
NOR2X1TS U3683 ( .A(n2678), .B(n2711), .Y(n2706) );
NOR2X1TS U3684 ( .A(n2763), .B(n2758), .Y(n2460) );
NAND2X1TS U3685 ( .A(n2706), .B(n2460), .Y(n2462) );
NAND2X1TS U3686 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n2716) );
NAND2X1TS U3687 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n2712) );
OAI21X1TS U3688 ( .A0(n2711), .A1(n2716), .B0(n2712), .Y(n2705) );
NAND2X1TS U3689 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n2762) );
NAND2X1TS U3690 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n2759) );
AOI21X1TS U3691 ( .A0(n2705), .A1(n2460), .B0(n2459), .Y(n2461) );
NOR2X1TS U3692 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n4198) );
INVX2TS U3693 ( .A(n4198), .Y(n4239) );
NAND2X1TS U3694 ( .A(n4239), .B(n4194), .Y(n4255) );
NOR2X2TS U3695 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]),
.Y(n4249) );
NOR2X1TS U3696 ( .A(n4255), .B(n4249), .Y(n2466) );
NAND2X1TS U3697 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n4238) );
INVX2TS U3698 ( .A(n4238), .Y(n2464) );
NAND2X1TS U3699 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n4193) );
INVX2TS U3700 ( .A(n4193), .Y(n2463) );
AOI21X1TS U3701 ( .A0(n4194), .A1(n2464), .B0(n2463), .Y(n4254) );
NAND2X1TS U3702 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n4250) );
OAI21X1TS U3703 ( .A0(n4254), .A1(n4249), .B0(n4250), .Y(n2465) );
AOI21X2TS U3704 ( .A0(n4197), .A1(n2466), .B0(n2465), .Y(n4185) );
INVX2TS U3705 ( .A(n4161), .Y(n2467) );
NOR2X1TS U3706 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]),
.Y(n4149) );
NAND2X1TS U3707 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n4150) );
NAND2X1TS U3708 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n4140) );
INVX2TS U3709 ( .A(n4140), .Y(n2468) );
NOR2X1TS U3710 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]),
.Y(n4130) );
NAND2X1TS U3711 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n4131) );
NAND2X1TS U3712 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n4170) );
INVX2TS U3713 ( .A(n4170), .Y(n2469) );
AOI21X4TS U3714 ( .A0(n4175), .A1(n4171), .B0(n2469), .Y(n4117) );
NOR2X1TS U3715 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]),
.Y(n4111) );
NAND2X1TS U3716 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n4112) );
NAND2X1TS U3717 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n4121) );
INVX2TS U3718 ( .A(n4121), .Y(n2470) );
AOI21X4TS U3719 ( .A0(n4126), .A1(n4122), .B0(n2470), .Y(n4107) );
NOR2X1TS U3720 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]),
.Y(n4101) );
NAND2X1TS U3721 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n4102) );
NAND2X1TS U3722 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n4074) );
INVX2TS U3723 ( .A(n4074), .Y(n2471) );
AOI21X4TS U3724 ( .A0(n4079), .A1(n4075), .B0(n2471), .Y(n4097) );
NOR2X1TS U3725 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]),
.Y(n4091) );
NAND2X1TS U3726 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n4092) );
NAND2X1TS U3727 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n2526) );
INVX2TS U3728 ( .A(n2526), .Y(n2472) );
BUFX3TS U3729 ( .A(n2264), .Y(n4259) );
BUFX3TS U3730 ( .A(n2264), .Y(n4505) );
NOR2X2TS U3731 ( .A(n4992), .B(FPMULT_FS_Module_state_reg[3]), .Y(n2592) );
NAND2X2TS U3732 ( .A(n2592), .B(n4989), .Y(n2589) );
INVX2TS U3733 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n2475) );
INVX2TS U3734 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n2474) );
NOR2X1TS U3735 ( .A(n2477), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n2478) );
NOR2BX1TS U3736 ( .AN(n2478), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n2479)
);
OA22X1TS U3737 ( .A0(n4860), .A1(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B0(n4070),
.B1(result_add_subt[27]), .Y(n1470) );
OA22X1TS U3738 ( .A0(n4860), .A1(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B0(n4070),
.B1(result_add_subt[26]), .Y(n1471) );
OA22X1TS U3739 ( .A0(n4860), .A1(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B0(n4070),
.B1(result_add_subt[25]), .Y(n1472) );
BUFX3TS U3740 ( .A(n4160), .Y(n4159) );
NAND2X1TS U3741 ( .A(n5004), .B(n5130), .Y(n4208) );
NAND2X1TS U3742 ( .A(n5018), .B(FPADDSUB_DMP_SFG[0]), .Y(n2482) );
OAI21X1TS U3743 ( .A0(n4208), .A1(n2483), .B0(n2482), .Y(n4212) );
NOR2X1TS U3744 ( .A(n5016), .B(FPADDSUB_DMP_SFG[1]), .Y(n4224) );
NOR2X1TS U3745 ( .A(n5012), .B(FPADDSUB_DMP_SFG[2]), .Y(n2485) );
NAND2X1TS U3746 ( .A(n5016), .B(FPADDSUB_DMP_SFG[1]), .Y(n4223) );
NAND2X1TS U3747 ( .A(n5012), .B(FPADDSUB_DMP_SFG[2]), .Y(n2484) );
AOI21X1TS U3748 ( .A0(n4212), .A1(n2487), .B0(n2486), .Y(n2673) );
NOR2X1TS U3749 ( .A(n5015), .B(FPADDSUB_DMP_SFG[3]), .Y(n2674) );
NOR2X1TS U3750 ( .A(n5011), .B(FPADDSUB_DMP_SFG[4]), .Y(n2489) );
NOR2X1TS U3751 ( .A(n2674), .B(n2489), .Y(n2698) );
NOR2X1TS U3752 ( .A(n5014), .B(FPADDSUB_DMP_SFG[5]), .Y(n2701) );
NOR2X1TS U3753 ( .A(n5010), .B(FPADDSUB_DMP_SFG[6]), .Y(n2491) );
NOR2X1TS U3754 ( .A(n2701), .B(n2491), .Y(n2493) );
NAND2X1TS U3755 ( .A(n2698), .B(n2493), .Y(n2495) );
NAND2X1TS U3756 ( .A(n5015), .B(FPADDSUB_DMP_SFG[3]), .Y(n2675) );
NAND2X1TS U3757 ( .A(n5011), .B(FPADDSUB_DMP_SFG[4]), .Y(n2488) );
OAI21X1TS U3758 ( .A0(n2489), .A1(n2675), .B0(n2488), .Y(n2697) );
NAND2X1TS U3759 ( .A(n5014), .B(FPADDSUB_DMP_SFG[5]), .Y(n2700) );
NAND2X1TS U3760 ( .A(n5010), .B(FPADDSUB_DMP_SFG[6]), .Y(n2490) );
AOI21X1TS U3761 ( .A0(n2697), .A1(n2493), .B0(n2492), .Y(n2494) );
OAI21X1TS U3762 ( .A0(n2673), .A1(n2495), .B0(n2494), .Y(n2757) );
NOR2X1TS U3763 ( .A(n5013), .B(FPADDSUB_DMP_SFG[7]), .Y(n4237) );
NOR2X1TS U3764 ( .A(n5103), .B(FPADDSUB_DMP_SFG[8]), .Y(n2497) );
NOR2X1TS U3765 ( .A(n4237), .B(n2497), .Y(n4189) );
NAND2X1TS U3766 ( .A(n4189), .B(n2499), .Y(n4247) );
NOR2X1TS U3767 ( .A(n5111), .B(FPADDSUB_DMP_SFG[10]), .Y(n2501) );
NOR2X1TS U3768 ( .A(n4247), .B(n2501), .Y(n2503) );
NAND2X1TS U3769 ( .A(n5013), .B(FPADDSUB_DMP_SFG[7]), .Y(n4236) );
NAND2X1TS U3770 ( .A(n5103), .B(FPADDSUB_DMP_SFG[8]), .Y(n2496) );
OAI21X1TS U3771 ( .A0(n2497), .A1(n4236), .B0(n2496), .Y(n4190) );
AOI21X1TS U3772 ( .A0(n4190), .A1(n2499), .B0(n2498), .Y(n4246) );
NAND2X1TS U3773 ( .A(n5111), .B(FPADDSUB_DMP_SFG[10]), .Y(n2500) );
OAI21X1TS U3774 ( .A0(n4246), .A1(n2501), .B0(n2500), .Y(n2502) );
AOI21X2TS U3775 ( .A0(n2757), .A1(n2503), .B0(n2502), .Y(n4183) );
NAND2X1TS U3776 ( .A(n5110), .B(FPADDSUB_DMP_SFG[11]), .Y(n2504) );
OAI21X2TS U3777 ( .A0(n4183), .A1(n2505), .B0(n2504), .Y(n4164) );
OR2X1TS U3778 ( .A(n5117), .B(FPADDSUB_DMP_SFG[12]), .Y(n2507) );
NOR2X1TS U3779 ( .A(n5109), .B(FPADDSUB_DMP_SFG[13]), .Y(n2509) );
NAND2X1TS U3780 ( .A(n5109), .B(FPADDSUB_DMP_SFG[13]), .Y(n2508) );
NOR2X1TS U3781 ( .A(n5108), .B(FPADDSUB_DMP_SFG[15]), .Y(n2513) );
NAND2X1TS U3782 ( .A(n5108), .B(FPADDSUB_DMP_SFG[15]), .Y(n2512) );
OAI21X4TS U3783 ( .A0(n4134), .A1(n2513), .B0(n2512), .Y(n4173) );
AOI21X4TS U3784 ( .A0(n4173), .A1(n2515), .B0(n2514), .Y(n4115) );
NOR2X1TS U3785 ( .A(n5107), .B(FPADDSUB_DMP_SFG[17]), .Y(n2517) );
NAND2X1TS U3786 ( .A(n5107), .B(FPADDSUB_DMP_SFG[17]), .Y(n2516) );
OAI21X4TS U3787 ( .A0(n4115), .A1(n2517), .B0(n2516), .Y(n4124) );
AOI21X4TS U3788 ( .A0(n4124), .A1(n2519), .B0(n2518), .Y(n4105) );
NOR2X1TS U3789 ( .A(n5106), .B(FPADDSUB_DMP_SFG[19]), .Y(n2521) );
NAND2X1TS U3790 ( .A(n5106), .B(FPADDSUB_DMP_SFG[19]), .Y(n2520) );
OAI21X4TS U3791 ( .A0(n4105), .A1(n2521), .B0(n2520), .Y(n4077) );
AOI21X4TS U3792 ( .A0(n4077), .A1(n2523), .B0(n2522), .Y(n4095) );
NAND2X1TS U3793 ( .A(n5105), .B(FPADDSUB_DMP_SFG[21]), .Y(n2524) );
OAI21X2TS U3794 ( .A0(n4095), .A1(n2525), .B0(n2524), .Y(n4085) );
NAND2X1TS U3795 ( .A(n2527), .B(n2526), .Y(n2529) );
INVX2TS U3796 ( .A(n2529), .Y(n2528) );
XNOR2X1TS U3797 ( .A(n4085), .B(n2528), .Y(n2533) );
XNOR2X1TS U3798 ( .A(n2530), .B(n2529), .Y(n2531) );
AOI22X1TS U3799 ( .A0(n2531), .A1(n2693), .B0(FPADDSUB_Raw_mant_NRM_SWR[24]),
.B1(n4505), .Y(n2532) );
OAI2BB1X1TS U3800 ( .A0N(n4159), .A1N(n2533), .B0(n2532), .Y(n1316) );
BUFX3TS U3801 ( .A(n4578), .Y(n5279) );
OR2X1TS U3802 ( .A(FPSENCOS_d_ff3_LUT_out[27]), .B(n2776), .Y(n2114) );
NOR2X1TS U3803 ( .A(n4988), .B(n5049), .Y(n3240) );
NAND3X2TS U3804 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n2537),
.C(n3080), .Y(n4516) );
OAI21XLTS U3805 ( .A0(n3240), .A1(n4516), .B0(n4603), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
INVX2TS U3806 ( .A(n2553), .Y(n2538) );
AOI22X1TS U3807 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n3467), .B0(n3470),
.B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n3683) );
INVX2TS U3808 ( .A(n4976), .Y(n4855) );
BUFX3TS U3809 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n3646) );
AOI22X1TS U3810 ( .A0(n3467), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n3691),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n2576) );
NOR2X2TS U3811 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n2544) );
NOR2BX2TS U3812 ( .AN(n2544), .B(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n3207)
);
NOR4X2TS U3813 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .C(FPADDSUB_Raw_mant_NRM_SWR[23]), .D(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n3208) );
AND2X4TS U3814 ( .A(n3207), .B(n3208), .Y(n2562) );
OR2X2TS U3815 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n2542) );
NOR2BX4TS U3816 ( .AN(n2562), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n2540)
);
NAND2BX4TS U3817 ( .AN(n2539), .B(n2540), .Y(n3125) );
AOI21X1TS U3818 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[18]), .A1(n2562), .B0(n3129),
.Y(n2557) );
NOR3X2TS U3819 ( .A(n3130), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .C(n2542),
.Y(n2561) );
NAND3X2TS U3820 ( .A(n3141), .B(n3139), .C(n5039), .Y(n2558) );
INVX2TS U3821 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n3442) );
NAND2BX2TS U3822 ( .AN(n2558), .B(n3442), .Y(n3209) );
INVX2TS U3823 ( .A(n2542), .Y(n2543) );
AOI211X1TS U3824 ( .A0(n2545), .A1(n2544), .B0(FPADDSUB_Raw_mant_NRM_SWR[23]), .C0(FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n2546) );
NAND2X2TS U3825 ( .A(n2548), .B(n3141), .Y(n2554) );
INVX2TS U3826 ( .A(n2554), .Y(n2549) );
NOR4BX2TS U3827 ( .AN(n2557), .B(n2561), .C(n4507), .D(n2552), .Y(n4065) );
AOI211X2TS U3828 ( .A0(n4507), .A1(n5069), .B0(n4065), .C0(n3703), .Y(n3393)
);
NAND2X2TS U3829 ( .A(n3393), .B(n3392), .Y(n3711) );
AOI21X1TS U3830 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n5017), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n2555) );
OA21XLTS U3831 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(n2555), .B0(n3442),
.Y(n2559) );
NAND2X1TS U3832 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(n2556), .Y(n3126) );
OAI211X1TS U3833 ( .A0(n2559), .A1(n2558), .B0(n2557), .C0(n3126), .Y(n3212)
);
AOI21X1TS U3834 ( .A0(n5040), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n2560) );
INVX2TS U3835 ( .A(n2561), .Y(n2564) );
AOI211X1TS U3836 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(n3140), .B0(n3212),
.C0(n2566), .Y(n2567) );
OAI31X4TS U3837 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n5038), .A2(n2568),
.B0(n2567), .Y(n4066) );
NAND2X1TS U3838 ( .A(n3470), .B(n5082), .Y(n2571) );
NAND2X1TS U3839 ( .A(n3467), .B(n5098), .Y(n2570) );
NAND2X1TS U3840 ( .A(n3472), .B(n5102), .Y(n2569) );
NAND2X1TS U3841 ( .A(n3470), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n2574) );
NAND2X1TS U3842 ( .A(n3471), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n2573) );
NAND2X1TS U3843 ( .A(n3472), .B(FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n2572) );
INVX2TS U3844 ( .A(n3701), .Y(n3394) );
INVX2TS U3845 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .Y(n3013) );
INVX2TS U3846 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(n3035) );
INVX2TS U3847 ( .A(intadd_0_SUM_11_), .Y(n2732) );
INVX2TS U3848 ( .A(intadd_0_SUM_6_), .Y(n2729) );
INVX2TS U3849 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[12]), .Y(n4828) );
NOR3X1TS U3850 ( .A(intadd_0_SUM_0_), .B(intadd_0_SUM_1_), .C(n4828), .Y(
n4823) );
OAI21X1TS U3851 ( .A0(intadd_0_SUM_0_), .A1(n4828), .B0(intadd_0_SUM_1_),
.Y(n4822) );
OAI21X1TS U3852 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_right[13]), .A1(n4823),
.B0(n4822), .Y(n2577) );
NAND2X1TS U3853 ( .A(intadd_0_SUM_2_), .B(n2577), .Y(n4817) );
NOR2X1TS U3854 ( .A(intadd_0_SUM_2_), .B(n2577), .Y(n4818) );
AOI21X1TS U3855 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_right[14]), .A1(n4817),
.B0(n4818), .Y(n2578) );
NAND2X1TS U3856 ( .A(n2578), .B(intadd_0_SUM_3_), .Y(n4812) );
NOR2X1TS U3857 ( .A(n2578), .B(intadd_0_SUM_3_), .Y(n4813) );
INVX2TS U3858 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[16]), .Y(n4809) );
AOI222X1TS U3859 ( .A0(intadd_0_SUM_4_), .A1(n4807), .B0(intadd_0_SUM_4_),
.B1(n4809), .C0(n4807), .C1(n4809), .Y(n2579) );
INVX2TS U3860 ( .A(n2579), .Y(n4803) );
INVX2TS U3861 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[17]), .Y(n4805) );
AOI222X1TS U3862 ( .A0(n4803), .A1(intadd_0_SUM_5_), .B0(n4803), .B1(n4805),
.C0(intadd_0_SUM_5_), .C1(n4805), .Y(n2728) );
NOR2BX1TS U3863 ( .AN(n2580), .B(intadd_0_SUM_7_), .Y(n2750) );
NAND2BXLTS U3864 ( .AN(n2580), .B(intadd_0_SUM_7_), .Y(n2749) );
INVX2TS U3865 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[20]), .Y(n2992) );
AOI222X1TS U3866 ( .A0(intadd_0_SUM_8_), .A1(n2734), .B0(intadd_0_SUM_8_),
.B1(n2992), .C0(n2734), .C1(n2992), .Y(n2581) );
INVX2TS U3867 ( .A(n2581), .Y(n2737) );
INVX2TS U3868 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[21]), .Y(n2982) );
AOI222X1TS U3869 ( .A0(intadd_0_SUM_9_), .A1(n2737), .B0(intadd_0_SUM_9_),
.B1(n2982), .C0(n2737), .C1(n2982), .Y(n2726) );
INVX2TS U3870 ( .A(intadd_0_SUM_10_), .Y(n2725) );
NAND2BX1TS U3871 ( .AN(intadd_0_SUM_12_), .B(n2582), .Y(n4800) );
NAND2BXLTS U3872 ( .AN(n2582), .B(intadd_0_SUM_12_), .Y(n4797) );
NAND2X1TS U3873 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .B(n4797), .Y(
n4796) );
NAND2X1TS U3874 ( .A(n4800), .B(n4796), .Y(n2753) );
OAI2BB2XLTS U3875 ( .B0(intadd_0_SUM_13_), .B1(n2583), .A0N(n2753), .A1N(
FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(n2741) );
INVX2TS U3876 ( .A(intadd_0_SUM_14_), .Y(n2740) );
NOR2BX1TS U3877 ( .AN(n2584), .B(intadd_0_SUM_15_), .Y(n4792) );
NAND2BXLTS U3878 ( .AN(n2584), .B(intadd_0_SUM_15_), .Y(n4791) );
AOI222X1TS U3879 ( .A0(intadd_0_SUM_16_), .A1(n3035), .B0(intadd_0_SUM_16_),
.B1(n2746), .C0(n3035), .C1(n2746), .Y(n4789) );
INVX2TS U3880 ( .A(intadd_0_SUM_17_), .Y(n4788) );
NAND2BXLTS U3881 ( .AN(intadd_0_SUM_18_), .B(n2585), .Y(n2586) );
INVX2TS U3882 ( .A(n2586), .Y(n2664) );
NOR2BX1TS U3883 ( .AN(intadd_0_SUM_18_), .B(n2585), .Y(n2587) );
NOR2X1TS U3884 ( .A(n2587), .B(n3013), .Y(n2663) );
INVX2TS U3885 ( .A(n3882), .Y(n2588) );
NAND2X4TS U3886 ( .A(n2590), .B(n2589), .Y(n4811) );
BUFX3TS U3887 ( .A(n4811), .Y(n4783) );
BUFX3TS U3888 ( .A(n4811), .Y(n4767) );
NOR2BX1TS U3889 ( .AN(FPMULT_P_Sgf[30]), .B(n4767), .Y(n3101) );
INVX2TS U3890 ( .A(n2422), .Y(n5177) );
BUFX3TS U3891 ( .A(n2776), .Y(n4558) );
OAI2BB2XLTS U3892 ( .B0(n4558), .B1(n2401), .A0N(n4569), .A1N(
intadd_8_SUM_1_), .Y(n1950) );
INVX2TS U3893 ( .A(n2592), .Y(n3045) );
OR2X2TS U3894 ( .A(n4496), .B(operation[1]), .Y(n2593) );
INVX2TS U3895 ( .A(n2593), .Y(n4693) );
AOI21X1TS U3896 ( .A0(ack_operation), .A1(n4693), .B0(n4498), .Y(n3047) );
AOI21X1TS U3897 ( .A0(FPMULT_zero_flag), .A1(n2361), .B0(n3047), .Y(n2595)
);
OAI211XLTS U3898 ( .A0(n3045), .A1(n5033), .B0(n2595), .C0(n2594), .Y(n1694)
);
NOR2X2TS U3899 ( .A(FPSENCOS_cont_iter_out[1]), .B(n4611), .Y(n3197) );
NOR2X1TS U3900 ( .A(n5054), .B(n4991), .Y(n4490) );
INVX2TS U3901 ( .A(n4490), .Y(n2777) );
NAND2X1TS U3902 ( .A(n4553), .B(n2777), .Y(n3162) );
OAI21X1TS U3903 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n5054), .B0(n3162),
.Y(n2597) );
AOI22X1TS U3904 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n4603), .B0(n3197),
.B1(n2597), .Y(n2596) );
NAND2X1TS U3905 ( .A(n4553), .B(n3219), .Y(n3233) );
NAND2BX1TS U3906 ( .AN(n3235), .B(n3233), .Y(n3203) );
NAND2X1TS U3907 ( .A(n2596), .B(n3203), .Y(n2129) );
AOI32X1TS U3908 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n4602), .A2(n2597),
.B0(FPSENCOS_d_ff3_LUT_out[10]), .B1(n4603), .Y(n2598) );
NAND2X1TS U3909 ( .A(n2598), .B(n3196), .Y(n2124) );
NOR2X2TS U3910 ( .A(FPSENCOS_cont_iter_out[2]), .B(n4611), .Y(n4518) );
NOR2X2TS U3911 ( .A(n5006), .B(n4995), .Y(n4492) );
INVX2TS U3912 ( .A(n4492), .Y(n3164) );
AOI22X1TS U3913 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n4603), .B0(n4518),
.B1(n3164), .Y(n2599) );
NOR2X1TS U3914 ( .A(n4991), .B(n3162), .Y(n3199) );
NAND2X1TS U3915 ( .A(n2599), .B(n4523), .Y(n2116) );
NAND3X1TS U3916 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n2600),
.C(n3134), .Y(n4494) );
AOI22X1TS U3917 ( .A0(Data_2[30]), .A1(n4680), .B0(FPADDSUB_intDY_EWSW[30]),
.B1(n4679), .Y(n2605) );
NOR3X2TS U3918 ( .A(FPSENCOS_cont_var_out[1]), .B(n4988), .C(n3241), .Y(
n2602) );
NOR3X2TS U3919 ( .A(n3241), .B(n5049), .C(FPSENCOS_cont_var_out[0]), .Y(
n2603) );
AOI22X1TS U3920 ( .A0(n4682), .A1(FPSENCOS_d_ff3_sh_y_out[30]), .B0(n2333),
.B1(FPSENCOS_d_ff3_sh_x_out[30]), .Y(n2604) );
NAND2X1TS U3921 ( .A(n2605), .B(n2604), .Y(n1814) );
OA22X1TS U3922 ( .A0(n4860), .A1(FPADDSUB_exp_rslt_NRM2_EW1[1]), .B0(n4975),
.B1(result_add_subt[24]), .Y(n1473) );
INVX2TS U3923 ( .A(n4871), .Y(n5280) );
BUFX3TS U3924 ( .A(n2610), .Y(n5231) );
BUFX3TS U3925 ( .A(n2610), .Y(n5233) );
NOR2X1TS U3926 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n2967) );
NAND3X1TS U3927 ( .A(n2967), .B(n4989), .C(n5033), .Y(n2613) );
BUFX3TS U3928 ( .A(n2352), .Y(n5272) );
CLKBUFX2TS U3929 ( .A(n2352), .Y(n2615) );
BUFX3TS U3930 ( .A(n2615), .Y(n5273) );
BUFX3TS U3931 ( .A(n2608), .Y(n5236) );
CLKBUFX2TS U3932 ( .A(n2610), .Y(n2618) );
BUFX3TS U3933 ( .A(n5231), .Y(n5237) );
NAND2X1TS U3934 ( .A(n5009), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]),
.Y(n2607) );
INVX2TS U3935 ( .A(n4515), .Y(n4509) );
CLKBUFX3TS U3936 ( .A(n2784), .Y(n2614) );
BUFX3TS U3937 ( .A(n2614), .Y(n5187) );
CLKBUFX2TS U3938 ( .A(n2610), .Y(n5262) );
BUFX3TS U3939 ( .A(n5240), .Y(n5238) );
BUFX3TS U3940 ( .A(n5248), .Y(n5239) );
CLKBUFX3TS U3941 ( .A(n2610), .Y(n5240) );
BUFX3TS U3942 ( .A(n2612), .Y(n5196) );
CLKBUFX3TS U3943 ( .A(n2784), .Y(n2611) );
BUFX3TS U3944 ( .A(n2611), .Y(n5193) );
CLKBUFX3TS U3945 ( .A(n2784), .Y(n2619) );
BUFX3TS U3946 ( .A(n2619), .Y(n5192) );
BUFX3TS U3947 ( .A(n2614), .Y(n5191) );
BUFX3TS U3948 ( .A(n2614), .Y(n5216) );
BUFX3TS U3949 ( .A(n2619), .Y(n5188) );
BUFX3TS U3950 ( .A(n2615), .Y(n5263) );
BUFX3TS U3951 ( .A(n2615), .Y(n5264) );
BUFX3TS U3952 ( .A(n2611), .Y(n5180) );
BUFX3TS U3953 ( .A(n2608), .Y(n5251) );
BUFX3TS U3954 ( .A(n2611), .Y(n5179) );
BUFX3TS U3955 ( .A(n5230), .Y(n5250) );
BUFX3TS U3956 ( .A(n5231), .Y(n5258) );
BUFX3TS U3957 ( .A(n5233), .Y(n5259) );
CLKBUFX3TS U3958 ( .A(n5240), .Y(n5260) );
CLKBUFX2TS U3959 ( .A(n2610), .Y(n2616) );
BUFX3TS U3960 ( .A(n2608), .Y(n5242) );
BUFX3TS U3961 ( .A(n5230), .Y(n5243) );
BUFX3TS U3962 ( .A(n5240), .Y(n5244) );
BUFX3TS U3963 ( .A(n2619), .Y(n5186) );
BUFX3TS U3964 ( .A(n5230), .Y(n5218) );
BUFX3TS U3965 ( .A(n2608), .Y(n5219) );
BUFX3TS U3966 ( .A(n2612), .Y(n5185) );
BUFX3TS U3967 ( .A(n5230), .Y(n5220) );
BUFX3TS U3968 ( .A(n5240), .Y(n5221) );
BUFX3TS U3969 ( .A(n2611), .Y(n5184) );
BUFX3TS U3970 ( .A(n2608), .Y(n5222) );
BUFX3TS U3971 ( .A(n5230), .Y(n5223) );
BUFX3TS U3972 ( .A(n5234), .Y(n5224) );
BUFX3TS U3973 ( .A(n2611), .Y(n5183) );
BUFX3TS U3974 ( .A(n5240), .Y(n5225) );
BUFX3TS U3975 ( .A(n5248), .Y(n5226) );
BUFX3TS U3976 ( .A(n5240), .Y(n5227) );
BUFX3TS U3977 ( .A(n2611), .Y(n5182) );
BUFX3TS U3978 ( .A(n5248), .Y(n5228) );
BUFX3TS U3979 ( .A(n5261), .Y(n5229) );
BUFX3TS U3980 ( .A(n2611), .Y(n5181) );
BUFX3TS U3981 ( .A(n2608), .Y(n5249) );
BUFX3TS U3982 ( .A(n5230), .Y(n5253) );
BUFX3TS U3983 ( .A(n5240), .Y(n5254) );
BUFX3TS U3984 ( .A(n2608), .Y(n5252) );
BUFX3TS U3985 ( .A(n2609), .Y(n5256) );
BUFX3TS U3986 ( .A(n2608), .Y(n5255) );
BUFX3TS U3987 ( .A(n2610), .Y(n5234) );
CLKBUFX2TS U3988 ( .A(n2615), .Y(n2617) );
BUFX3TS U3989 ( .A(n2617), .Y(n5267) );
BUFX3TS U3990 ( .A(n2352), .Y(n5274) );
BUFX3TS U3991 ( .A(n5230), .Y(n5232) );
BUFX3TS U3992 ( .A(n2611), .Y(n5199) );
BUFX3TS U3993 ( .A(n2614), .Y(n5213) );
BUFX3TS U3994 ( .A(n2612), .Y(n5200) );
BUFX3TS U3995 ( .A(n2614), .Y(n5214) );
BUFX3TS U3996 ( .A(n2612), .Y(n5201) );
BUFX3TS U3997 ( .A(n2614), .Y(n5215) );
BUFX3TS U3998 ( .A(n2619), .Y(n5208) );
BUFX3TS U3999 ( .A(n2619), .Y(n5209) );
BUFX3TS U4000 ( .A(n2619), .Y(n5210) );
BUFX3TS U4001 ( .A(n2612), .Y(n5204) );
BUFX3TS U4002 ( .A(n2612), .Y(n5203) );
CLKBUFX3TS U4003 ( .A(n2610), .Y(n5230) );
CLKBUFX2TS U4004 ( .A(n2617), .Y(n5278) );
BUFX3TS U4005 ( .A(n2608), .Y(n5235) );
BUFX3TS U4006 ( .A(n2617), .Y(n5271) );
BUFX3TS U4007 ( .A(n2612), .Y(n5205) );
BUFX3TS U4008 ( .A(n2611), .Y(n5178) );
BUFX3TS U4009 ( .A(n2614), .Y(n5212) );
BUFX3TS U4010 ( .A(n2617), .Y(n5265) );
BUFX3TS U4011 ( .A(n5230), .Y(n5247) );
BUFX3TS U4012 ( .A(n2617), .Y(n5270) );
BUFX3TS U4013 ( .A(n2617), .Y(n5277) );
BUFX3TS U4014 ( .A(n2615), .Y(n5266) );
BUFX3TS U4015 ( .A(n2612), .Y(n5202) );
BUFX3TS U4016 ( .A(n5240), .Y(n5246) );
BUFX3TS U4017 ( .A(n5261), .Y(n5241) );
BUFX3TS U4018 ( .A(n2619), .Y(n5206) );
BUFX3TS U4019 ( .A(n2352), .Y(n5268) );
BUFX3TS U4020 ( .A(n2615), .Y(n5275) );
BUFX3TS U4021 ( .A(n2619), .Y(n5207) );
BUFX3TS U4022 ( .A(n2615), .Y(n5276) );
BUFX3TS U4023 ( .A(n5240), .Y(n5245) );
BUFX3TS U4024 ( .A(n2617), .Y(n5269) );
BUFX3TS U4025 ( .A(n5230), .Y(n5257) );
BUFX3TS U4026 ( .A(n2619), .Y(n5211) );
NOR2X1TS U4027 ( .A(FPMULT_Op_MX[10]), .B(n2311), .Y(n4730) );
NOR2X2TS U4028 ( .A(n5090), .B(n2310), .Y(n4381) );
INVX2TS U4029 ( .A(n2246), .Y(n4338) );
NOR2XLTS U4030 ( .A(n5066), .B(n2374), .Y(FPMULT_Sgf_operation_EVEN1_left_N0) );
INVX2TS U4031 ( .A(mult_x_219_n40), .Y(intadd_3_B_16_) );
INVX2TS U4032 ( .A(mult_x_219_n36), .Y(intadd_3_A_16_) );
INVX2TS U4033 ( .A(mult_x_219_n35), .Y(intadd_3_B_17_) );
INVX2TS U4034 ( .A(mult_x_219_n33), .Y(intadd_3_A_17_) );
INVX2TS U4035 ( .A(mult_x_219_n32), .Y(intadd_3_A_18_) );
NAND2X1TS U4036 ( .A(n4697), .B(n5057), .Y(n4732) );
INVX2TS U4037 ( .A(n3865), .Y(n4322) );
NAND2X2TS U4038 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[13]), .Y(n3857) );
OAI22X1TS U4039 ( .A0(n2207), .A1(n4322), .B0(n2200), .B1(n3857), .Y(n2620)
);
AOI21X1TS U4040 ( .A0(n3864), .A1(n2200), .B0(n2620), .Y(n2820) );
OAI21X1TS U4041 ( .A0(n4999), .A1(n5074), .B0(FPMULT_Op_MX[15]), .Y(
mult_x_219_n205) );
INVX2TS U4042 ( .A(mult_x_219_n133), .Y(intadd_3_A_2_) );
INVX2TS U4043 ( .A(mult_x_219_n128), .Y(intadd_3_B_3_) );
INVX2TS U4044 ( .A(mult_x_219_n132), .Y(intadd_3_A_3_) );
INVX2TS U4045 ( .A(mult_x_219_n123), .Y(intadd_3_B_4_) );
INVX2TS U4046 ( .A(mult_x_219_n127), .Y(intadd_3_A_4_) );
INVX2TS U4047 ( .A(mult_x_219_n116), .Y(intadd_3_B_5_) );
INVX2TS U4048 ( .A(mult_x_219_n122), .Y(intadd_3_A_5_) );
INVX2TS U4049 ( .A(mult_x_219_n110), .Y(intadd_3_B_6_) );
INVX2TS U4050 ( .A(mult_x_219_n115), .Y(intadd_3_A_6_) );
INVX2TS U4051 ( .A(mult_x_219_n109), .Y(intadd_3_A_7_) );
INVX2TS U4052 ( .A(mult_x_219_n94), .Y(intadd_3_B_8_) );
INVX2TS U4053 ( .A(mult_x_219_n101), .Y(intadd_3_A_8_) );
INVX2TS U4054 ( .A(mult_x_219_n85), .Y(intadd_3_B_9_) );
INVX2TS U4055 ( .A(mult_x_219_n93), .Y(intadd_3_A_9_) );
INVX2TS U4056 ( .A(mult_x_219_n75), .Y(intadd_3_B_10_) );
INVX2TS U4057 ( .A(mult_x_219_n84), .Y(intadd_3_A_10_) );
INVX2TS U4058 ( .A(mult_x_219_n67), .Y(intadd_3_B_11_) );
INVX2TS U4059 ( .A(mult_x_219_n74), .Y(intadd_3_A_11_) );
INVX2TS U4060 ( .A(mult_x_219_n59), .Y(intadd_3_B_12_) );
INVX2TS U4061 ( .A(mult_x_219_n66), .Y(intadd_3_A_12_) );
INVX2TS U4062 ( .A(mult_x_219_n53), .Y(intadd_3_B_13_) );
INVX2TS U4063 ( .A(mult_x_219_n58), .Y(intadd_3_A_13_) );
INVX2TS U4064 ( .A(mult_x_219_n46), .Y(intadd_3_B_14_) );
INVX2TS U4065 ( .A(mult_x_219_n52), .Y(intadd_3_A_14_) );
INVX2TS U4066 ( .A(mult_x_219_n45), .Y(intadd_3_B_15_) );
NOR2X1TS U4067 ( .A(n4990), .B(n2373), .Y(intadd_4_CI) );
NAND2X1TS U4068 ( .A(n2298), .B(intadd_5_SUM_5_), .Y(n2622) );
OAI21XLTS U4069 ( .A0(n2298), .A1(intadd_5_SUM_5_), .B0(n2622), .Y(n2621) );
CLKBUFX3TS U4070 ( .A(n2621), .Y(n4420) );
AOI21X1TS U4071 ( .A0(n2298), .A1(intadd_5_SUM_5_), .B0(n2277), .Y(n2870) );
INVX2TS U4072 ( .A(n2870), .Y(n2789) );
OAI21X1TS U4073 ( .A0(intadd_5_SUM_6_), .A1(n2622), .B0(n2789), .Y(n2864) );
NAND2X2TS U4074 ( .A(n4420), .B(n2864), .Y(n4419) );
AOI22X1TS U4075 ( .A0(n4412), .A1(n2358), .B0(intadd_5_SUM_6_), .B1(n2250),
.Y(n3837) );
INVX2TS U4076 ( .A(n4420), .Y(n2907) );
INVX2TS U4077 ( .A(intadd_4_SUM_0_), .Y(n4409) );
AOI22X1TS U4078 ( .A0(intadd_4_SUM_0_), .A1(n2359), .B0(n2277), .B1(n4409),
.Y(n2654) );
OAI2BB2XLTS U4079 ( .B0(n4419), .B1(n3837), .A0N(n2907), .A1N(n2654), .Y(
DP_OP_454J1_123_2743_n213) );
NAND2X1TS U4080 ( .A(n2322), .B(intadd_5_SUM_9_), .Y(n2625) );
OAI21XLTS U4081 ( .A0(n2322), .A1(intadd_5_SUM_9_), .B0(n2625), .Y(n2623) );
CLKBUFX3TS U4082 ( .A(n2623), .Y(n4413) );
NOR2X1TS U4083 ( .A(n2249), .B(n2367), .Y(DP_OP_454J1_123_2743_n187) );
OAI21X1TS U4084 ( .A0(FPMULT_Op_MX[11]), .A1(intadd_5_n1), .B0(n2271), .Y(
n3823) );
NAND2X1TS U4085 ( .A(n2284), .B(n2625), .Y(n4454) );
NOR2XLTS U4086 ( .A(n2317), .B(n4990), .Y(
FPMULT_Sgf_operation_EVEN1_right_N0) );
OAI21XLTS U4087 ( .A0(n2276), .A1(mult_x_254_n225), .B0(n2234), .Y(n2626) );
AOI22X1TS U4088 ( .A0(FPMULT_Op_MY[6]), .A1(n2306), .B0(n4703), .B1(n5048),
.Y(n2640) );
INVX2TS U4089 ( .A(n2251), .Y(n4365) );
OAI221X4TS U4090 ( .A0(n2305), .A1(n5002), .B0(n2307), .B1(FPMULT_Op_MX[4]),
.C0(n4365), .Y(n4360) );
INVX2TS U4091 ( .A(n4360), .Y(n4362) );
AOI22X1TS U4092 ( .A0(FPMULT_Op_MY[5]), .A1(n2307), .B0(n2305), .B1(n5042),
.Y(n2659) );
AO22XLTS U4093 ( .A0(n2251), .A1(n2640), .B0(n4362), .B1(n2659), .Y(
mult_x_254_n204) );
AOI22X1TS U4094 ( .A0(FPMULT_Op_MY[2]), .A1(n2306), .B0(n4703), .B1(n5050),
.Y(n2629) );
AOI22X1TS U4095 ( .A0(FPMULT_Op_MY[1]), .A1(n2307), .B0(n4703), .B1(n5065),
.Y(n4325) );
AO22XLTS U4096 ( .A0(n2252), .A1(n2629), .B0(n4325), .B1(n4362), .Y(
mult_x_254_n208) );
NAND2X1TS U4097 ( .A(FPMULT_Op_MY[0]), .B(n2251), .Y(intadd_2_A_0_) );
INVX2TS U4098 ( .A(mult_x_254_n128), .Y(intadd_2_B_3_) );
INVX2TS U4099 ( .A(mult_x_254_n132), .Y(intadd_2_A_3_) );
INVX2TS U4100 ( .A(mult_x_254_n123), .Y(intadd_2_B_4_) );
INVX2TS U4101 ( .A(mult_x_254_n127), .Y(intadd_2_A_4_) );
INVX2TS U4102 ( .A(mult_x_254_n116), .Y(intadd_2_B_5_) );
INVX2TS U4103 ( .A(mult_x_254_n122), .Y(intadd_2_A_5_) );
INVX2TS U4104 ( .A(mult_x_254_n110), .Y(intadd_2_B_6_) );
INVX2TS U4105 ( .A(mult_x_254_n115), .Y(intadd_2_A_6_) );
INVX2TS U4106 ( .A(mult_x_254_n102), .Y(intadd_2_B_7_) );
INVX2TS U4107 ( .A(mult_x_254_n109), .Y(intadd_2_A_7_) );
INVX2TS U4108 ( .A(mult_x_254_n94), .Y(intadd_2_B_8_) );
INVX2TS U4109 ( .A(mult_x_254_n101), .Y(intadd_2_A_8_) );
INVX2TS U4110 ( .A(mult_x_254_n93), .Y(intadd_2_A_9_) );
INVX2TS U4111 ( .A(mult_x_254_n75), .Y(intadd_2_B_10_) );
INVX2TS U4112 ( .A(mult_x_254_n84), .Y(intadd_2_A_10_) );
INVX2TS U4113 ( .A(mult_x_254_n67), .Y(intadd_2_B_11_) );
INVX2TS U4114 ( .A(mult_x_254_n74), .Y(intadd_2_A_11_) );
INVX2TS U4115 ( .A(mult_x_254_n59), .Y(intadd_2_B_12_) );
INVX2TS U4116 ( .A(mult_x_254_n66), .Y(intadd_2_A_12_) );
INVX2TS U4117 ( .A(mult_x_254_n53), .Y(intadd_2_B_13_) );
INVX2TS U4118 ( .A(mult_x_254_n58), .Y(intadd_2_A_13_) );
INVX2TS U4119 ( .A(mult_x_254_n46), .Y(intadd_2_B_14_) );
INVX2TS U4120 ( .A(mult_x_254_n52), .Y(intadd_2_A_14_) );
INVX2TS U4121 ( .A(mult_x_254_n45), .Y(intadd_2_B_15_) );
INVX2TS U4122 ( .A(mult_x_254_n41), .Y(intadd_2_A_15_) );
INVX2TS U4123 ( .A(mult_x_254_n40), .Y(intadd_2_B_16_) );
INVX2TS U4124 ( .A(mult_x_254_n36), .Y(intadd_2_A_16_) );
INVX2TS U4125 ( .A(mult_x_254_n35), .Y(intadd_2_B_17_) );
INVX2TS U4126 ( .A(mult_x_254_n32), .Y(intadd_2_A_18_) );
AOI22X1TS U4127 ( .A0(FPMULT_Op_MY[19]), .A1(n2291), .B0(n2289), .B1(n5027),
.Y(n3862) );
AOI22X1TS U4128 ( .A0(FPMULT_Op_MY[18]), .A1(n2292), .B0(n2289), .B1(n5025),
.Y(n3778) );
AO22XLTS U4129 ( .A0(n2248), .A1(n3862), .B0(n2628), .B1(n3778), .Y(
mult_x_219_n197) );
AOI22X1TS U4130 ( .A0(FPMULT_Op_MY[15]), .A1(n2291), .B0(n2289), .B1(n5030),
.Y(n2649) );
AOI22X1TS U4131 ( .A0(n2199), .A1(n2292), .B0(n2289), .B1(n5031), .Y(n3802)
);
AO22XLTS U4132 ( .A0(n2627), .A1(n2649), .B0(n2628), .B1(n3802), .Y(
mult_x_219_n201) );
AOI22X1TS U4133 ( .A0(FPMULT_Op_MY[3]), .A1(n2306), .B0(n4703), .B1(n5046),
.Y(n2657) );
AO22XLTS U4134 ( .A0(n2252), .A1(n2657), .B0(n4362), .B1(n2629), .Y(
mult_x_254_n207) );
NAND2X1TS U4135 ( .A(n4999), .B(n5074), .Y(n4725) );
OAI21XLTS U4136 ( .A0(n5074), .A1(n4999), .B0(n4725), .Y(n2630) );
CLKBUFX3TS U4137 ( .A(n2630), .Y(n4320) );
AOI22X1TS U4138 ( .A0(n2309), .A1(n5022), .B0(FPMULT_Op_MY[20]), .B1(n4697),
.Y(n4317) );
AOI32X4TS U4139 ( .A0(FPMULT_Op_MX[15]), .A1(n4320), .A2(n5074), .B0(n2812),
.B1(n4320), .Y(n4318) );
INVX2TS U4140 ( .A(n4318), .Y(n4266) );
AOI22X1TS U4141 ( .A0(FPMULT_Op_MX[15]), .A1(FPMULT_Op_MY[19]), .B0(n5027),
.B1(n2308), .Y(n2837) );
INVX2TS U4142 ( .A(intadd_4_SUM_4_), .Y(n4401) );
AOI22X1TS U4143 ( .A0(intadd_4_SUM_4_), .A1(n2358), .B0(n2359), .B1(n4401),
.Y(n2901) );
INVX2TS U4144 ( .A(intadd_4_SUM_3_), .Y(n4403) );
AOI22X1TS U4145 ( .A0(intadd_4_SUM_3_), .A1(n2358), .B0(intadd_5_SUM_6_),
.B1(n4403), .Y(n2645) );
OAI22X1TS U4146 ( .A0(n4420), .A1(n2901), .B0(n4419), .B1(n2645), .Y(n2633)
);
NOR2X1TS U4147 ( .A(n2295), .B(intadd_5_SUM_3_), .Y(n4422) );
INVX2TS U4148 ( .A(n3795), .Y(n4428) );
INVX2TS U4149 ( .A(intadd_4_SUM_6_), .Y(n4397) );
AOI22X1TS U4150 ( .A0(n2297), .A1(n4397), .B0(intadd_4_SUM_6_), .B1(n2375),
.Y(n2899) );
OAI33X4TS U4151 ( .A0(n2314), .A1(n2366), .A2(n2298), .B0(n2375), .B1(
intadd_5_SUM_3_), .B2(n2295), .Y(n2897) );
INVX2TS U4152 ( .A(n2897), .Y(n2631) );
INVX2TS U4153 ( .A(intadd_4_SUM_5_), .Y(n4399) );
AOI22X1TS U4154 ( .A0(n2297), .A1(n4399), .B0(intadd_4_SUM_5_), .B1(n2296),
.Y(n2656) );
OAI22X1TS U4155 ( .A0(n4428), .A1(n2899), .B0(n2631), .B1(n2656), .Y(n2632)
);
NAND2X1TS U4156 ( .A(n2632), .B(n2633), .Y(n2934) );
OA21XLTS U4157 ( .A0(n2633), .A1(n2632), .B0(n2934), .Y(
DP_OP_454J1_123_2743_n119) );
NOR2X2TS U4158 ( .A(n2324), .B(n5177), .Y(n4728) );
INVX2TS U4159 ( .A(n4728), .Y(n4297) );
INVX2TS U4160 ( .A(intadd_4_SUM_2_), .Y(n4405) );
AOI22X1TS U4161 ( .A0(intadd_4_SUM_2_), .A1(n2296), .B0(n2298), .B1(n4405),
.Y(n2807) );
INVX2TS U4162 ( .A(intadd_4_SUM_1_), .Y(n4407) );
AOI22X1TS U4163 ( .A0(intadd_4_SUM_1_), .A1(n2375), .B0(n2298), .B1(n4407),
.Y(n4427) );
OAI22X1TS U4164 ( .A0(n4428), .A1(n2807), .B0(n2631), .B1(n4427), .Y(n2637)
);
NAND2X1TS U4165 ( .A(n2260), .B(intadd_5_SUM_1_), .Y(n2634) );
OAI32X4TS U4166 ( .A0(n2314), .A1(n2260), .A2(intadd_5_SUM_1_), .B0(n2295),
.B1(n2634), .Y(n4441) );
INVX2TS U4167 ( .A(n4441), .Y(n4438) );
AOI22X1TS U4168 ( .A0(n2294), .A1(n4403), .B0(intadd_4_SUM_3_), .B1(n2313),
.Y(n4443) );
OAI21XLTS U4169 ( .A0(n2260), .A1(intadd_5_SUM_1_), .B0(n2634), .Y(n2635) );
CLKBUFX3TS U4170 ( .A(n2635), .Y(n4444) );
AOI22X1TS U4171 ( .A0(n2294), .A1(n4401), .B0(intadd_4_SUM_4_), .B1(n2313),
.Y(n2805) );
OAI22X1TS U4172 ( .A0(n4438), .A1(n4443), .B0(n4444), .B1(n2805), .Y(n2636)
);
NAND2X1TS U4173 ( .A(n2636), .B(n2637), .Y(n2930) );
OA21XLTS U4174 ( .A0(n2637), .A1(n2636), .B0(n2930), .Y(
DP_OP_454J1_123_2743_n142) );
NOR2X1TS U4175 ( .A(n2317), .B(n5066), .Y(intadd_5_CI) );
INVX2TS U4176 ( .A(n4444), .Y(n3798) );
AOI22X1TS U4177 ( .A0(intadd_4_SUM_2_), .A1(n2295), .B0(n2313), .B1(n4405),
.Y(n4442) );
AOI22X1TS U4178 ( .A0(intadd_4_SUM_1_), .A1(n2295), .B0(n2313), .B1(n4407),
.Y(n3797) );
AOI22X1TS U4179 ( .A0(n3798), .A1(n4442), .B0(n3797), .B1(n4441), .Y(n4388)
);
AOI21X2TS U4180 ( .A0(n2316), .A1(n5066), .B0(intadd_5_CI), .Y(n3781) );
INVX2TS U4181 ( .A(n3781), .Y(n4448) );
NAND2X2TS U4182 ( .A(intadd_5_SUM_0_), .B(n4448), .Y(n4447) );
OAI22X1TS U4183 ( .A0(intadd_4_SUM_3_), .A1(n4447), .B0(intadd_4_SUM_4_),
.B1(n3793), .Y(n2639) );
AOI21X1TS U4184 ( .A0(n2638), .A1(intadd_4_SUM_4_), .B0(n2639), .Y(n4389) );
NOR2X1TS U4185 ( .A(n4388), .B(n4389), .Y(DP_OP_454J1_123_2743_n148) );
AOI22X1TS U4186 ( .A0(n2297), .A1(intadd_4_SUM_4_), .B0(n4401), .B1(n2375),
.Y(n2655) );
AOI22X1TS U4187 ( .A0(n2297), .A1(intadd_4_SUM_3_), .B0(n4403), .B1(n2375),
.Y(n2808) );
AOI22X1TS U4188 ( .A0(n3795), .A1(n2655), .B0(n2897), .B1(n2808), .Y(n2803)
);
AOI22X1TS U4189 ( .A0(n2294), .A1(intadd_4_SUM_6_), .B0(n4397), .B1(n2313),
.Y(n4439) );
AOI22X1TS U4190 ( .A0(n2294), .A1(intadd_4_SUM_5_), .B0(n4399), .B1(n2313),
.Y(n2806) );
AOI22X1TS U4191 ( .A0(n3798), .A1(n4439), .B0(n2806), .B1(n4441), .Y(n2804)
);
NOR2X1TS U4192 ( .A(n2803), .B(n2804), .Y(DP_OP_454J1_123_2743_n131) );
AOI22X1TS U4193 ( .A0(FPMULT_Op_MY[7]), .A1(n2307), .B0(n4703), .B1(n5044),
.Y(n2653) );
AO22XLTS U4194 ( .A0(n2252), .A1(n2653), .B0(n4362), .B1(n2640), .Y(
mult_x_254_n203) );
AOI22X1TS U4195 ( .A0(FPMULT_Op_MY[1]), .A1(n2300), .B0(n2299), .B1(n5065),
.Y(n3846) );
NAND2X1TS U4196 ( .A(n2290), .B(n5058), .Y(n4734) );
INVX2TS U4197 ( .A(n2266), .Y(n2840) );
AOI22X1TS U4198 ( .A0(FPMULT_Op_MY[13]), .A1(n2198), .B0(n2286), .B1(n5021),
.Y(n2644) );
NAND2X1TS U4199 ( .A(FPMULT_Op_MY[0]), .B(n2356), .Y(n4331) );
AOI22X1TS U4200 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[9]), .B0(
FPMULT_Op_MY[8]), .B1(n2317), .Y(n2643) );
AOI22X1TS U4201 ( .A0(n2199), .A1(n2319), .B0(n2318), .B1(n5031), .Y(n2838)
);
AO22XLTS U4202 ( .A0(n2840), .A1(n2838), .B0(n3860), .B1(n2644), .Y(
mult_x_219_n188) );
INVX2TS U4203 ( .A(n4419), .Y(n2905) );
AOI22X1TS U4204 ( .A0(intadd_4_SUM_2_), .A1(intadd_5_SUM_6_), .B0(n2358),
.B1(n4405), .Y(n2802) );
NAND2X1TS U4205 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MX[11]), .Y(n2963) );
OAI21X1TS U4206 ( .A0(FPMULT_Op_MY[2]), .A1(FPMULT_Op_MX[11]), .B0(n2963),
.Y(n4336) );
BUFX3TS U4207 ( .A(n4335), .Y(n4698) );
NOR2X1TS U4208 ( .A(n5046), .B(n5170), .Y(n3853) );
AOI21X1TS U4209 ( .A0(n5046), .A1(n4698), .B0(n3853), .Y(n3830) );
OAI22X1TS U4210 ( .A0(n2318), .A1(n5063), .B0(FPMULT_Op_MX[20]), .B1(n2319),
.Y(n2647) );
CLKBUFX3TS U4211 ( .A(n2647), .Y(n4304) );
INVX2TS U4212 ( .A(n4304), .Y(n3854) );
NAND2X1TS U4213 ( .A(FPMULT_Op_MY[12]), .B(n3854), .Y(n4283) );
OAI22X1TS U4214 ( .A0(FPMULT_Op_MY[20]), .A1(n4322), .B0(FPMULT_Op_MY[21]),
.B1(n3857), .Y(n2648) );
AOI21X1TS U4215 ( .A0(n3864), .A1(FPMULT_Op_MY[21]), .B0(n2648), .Y(n4285)
);
INVX2TS U4216 ( .A(intadd_4_SUM_9_), .Y(n4432) );
AOI22X1TS U4217 ( .A0(n2359), .A1(n4432), .B0(intadd_4_SUM_9_), .B1(n2277),
.Y(n4418) );
INVX2TS U4218 ( .A(intadd_4_SUM_8_), .Y(n4434) );
AOI22X1TS U4219 ( .A0(n2359), .A1(intadd_4_SUM_8_), .B0(n4434), .B1(n2277),
.Y(n2894) );
NAND2X1TS U4220 ( .A(n2324), .B(n5177), .Y(n4280) );
AOI22X1TS U4221 ( .A0(FPMULT_Op_MY[18]), .A1(n2323), .B0(n2325), .B1(n5025),
.Y(n4301) );
AOI221X4TS U4222 ( .A0(n5063), .A1(n2350), .B0(FPMULT_Op_MX[20]), .B1(
FPMULT_Op_MX[21]), .C0(n3854), .Y(n3806) );
AOI22X1TS U4223 ( .A0(n2200), .A1(n2325), .B0(n2349), .B1(n5029), .Y(n2787)
);
AOI22X1TS U4224 ( .A0(n2200), .A1(n2291), .B0(n2289), .B1(n5029), .Y(n3777)
);
AOI22X1TS U4225 ( .A0(n2207), .A1(n2292), .B0(n2290), .B1(n5023), .Y(n2650)
);
AO22XLTS U4226 ( .A0(n2627), .A1(n3777), .B0(n2628), .B1(n2650), .Y(
mult_x_219_n199) );
AOI22X1TS U4227 ( .A0(n2207), .A1(n2286), .B0(n2198), .B1(n5023), .Y(n4309)
);
AOI22X1TS U4228 ( .A0(FPMULT_Op_MY[15]), .A1(n2198), .B0(n2318), .B1(n5030),
.Y(n2839) );
AO22XLTS U4229 ( .A0(n2627), .A1(n2650), .B0(n2628), .B1(n2649), .Y(
mult_x_219_n200) );
NOR2X1TS U4230 ( .A(n4993), .B(n5028), .Y(n2652) );
AOI22X1TS U4231 ( .A0(FPMULT_Op_MY[10]), .A1(n4993), .B0(n2652), .B1(n2340),
.Y(n2651) );
OAI21X1TS U4232 ( .A0(n2652), .A1(n2339), .B0(n2651), .Y(n4330) );
AOI22X1TS U4233 ( .A0(n2297), .A1(n4432), .B0(intadd_4_SUM_9_), .B1(n2375),
.Y(n4424) );
AOI22X1TS U4234 ( .A0(n2297), .A1(intadd_4_SUM_8_), .B0(n4434), .B1(n2296),
.Y(n2898) );
AOI22X1TS U4235 ( .A0(FPMULT_Op_MY[8]), .A1(n2306), .B0(n4703), .B1(n5047),
.Y(n2785) );
AO22XLTS U4236 ( .A0(n2252), .A1(n2785), .B0(n4362), .B1(n2653), .Y(
mult_x_254_n202) );
AOI22X1TS U4237 ( .A0(intadd_4_SUM_1_), .A1(intadd_5_SUM_6_), .B0(n2358),
.B1(n4407), .Y(n2801) );
AO22XLTS U4238 ( .A0(n2907), .A1(n2801), .B0(n2905), .B1(n2654), .Y(
DP_OP_454J1_123_2743_n212) );
AOI22X1TS U4239 ( .A0(FPMULT_Op_MY[4]), .A1(n2307), .B0(n4703), .B1(n5045),
.Y(n2658) );
AO22XLTS U4240 ( .A0(n2252), .A1(n2658), .B0(n4362), .B1(n2657), .Y(
mult_x_254_n206) );
NAND2X1TS U4241 ( .A(n2359), .B(intadd_5_SUM_7_), .Y(n2865) );
NAND2X1TS U4242 ( .A(n2322), .B(n2865), .Y(DP_OP_454J1_123_2743_n188) );
AO22XLTS U4243 ( .A0(n2252), .A1(n2659), .B0(n4362), .B1(n2658), .Y(
mult_x_254_n205) );
BUFX3TS U4244 ( .A(n2661), .Y(n4982) );
BUFX3TS U4245 ( .A(n5095), .Y(n4857) );
OAI2BB2XLTS U4246 ( .B0(n4982), .B1(n2224), .A0N(n4857), .A1N(
FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1458) );
INVX2TS U4247 ( .A(n4982), .Y(n4985) );
INVX2TS U4248 ( .A(n4982), .Y(n2660) );
OAI2BB2XLTS U4249 ( .B0(n4985), .B1(n5101), .A0N(n2660), .A1N(
FPADDSUB_DmP_EXP_EWSW[2]), .Y(n1312) );
OAI2BB2XLTS U4250 ( .B0(n4985), .B1(n5100), .A0N(n2660), .A1N(
FPADDSUB_DmP_EXP_EWSW[20]), .Y(n1392) );
OAI2BB2XLTS U4251 ( .B0(n4985), .B1(n5102), .A0N(n2660), .A1N(
FPADDSUB_DmP_EXP_EWSW[1]), .Y(n1291) );
OAI2BB2XLTS U4252 ( .B0(n4985), .B1(n5099), .A0N(n2660), .A1N(
FPADDSUB_DmP_EXP_EWSW[19]), .Y(n1395) );
OAI2BB2XLTS U4253 ( .B0(n4985), .B1(n5069), .A0N(n2660), .A1N(
intadd_6_SUM_0_), .Y(n1477) );
INVX2TS U4254 ( .A(n4533), .Y(n4669) );
NOR2XLTS U4255 ( .A(n4494), .B(n4669), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
BUFX3TS U4256 ( .A(n2661), .Y(n4984) );
INVX2TS U4257 ( .A(n4984), .Y(n4865) );
NAND3X1TS U4258 ( .A(n4988), .B(n5049), .C(ready_add_subt), .Y(n2662) );
BUFX3TS U4259 ( .A(n2662), .Y(n4544) );
BUFX3TS U4260 ( .A(n4544), .Y(n4542) );
INVX2TS U4261 ( .A(result_add_subt[31]), .Y(n4566) );
CLKBUFX2TS U4262 ( .A(n4544), .Y(n4676) );
OAI2BB2XLTS U4263 ( .B0(n4542), .B1(n4566), .A0N(n4676), .A1N(
FPSENCOS_d_ff_Xn[31]), .Y(n1728) );
BUFX3TS U4264 ( .A(n4544), .Y(n4540) );
INVX2TS U4265 ( .A(result_add_subt[0]), .Y(n4963) );
OAI2BB2XLTS U4266 ( .B0(n4540), .B1(n4963), .A0N(n4676), .A1N(
FPSENCOS_d_ff_Xn[0]), .Y(n2073) );
INVX2TS U4267 ( .A(n4533), .Y(n4543) );
INVX2TS U4268 ( .A(result_add_subt[12]), .Y(n4903) );
INVX2TS U4269 ( .A(n4533), .Y(n4536) );
OAI2BB2XLTS U4270 ( .B0(n4543), .B1(n4903), .A0N(n4536), .A1N(
FPSENCOS_d_ff_Zn[12]), .Y(n2039) );
INVX2TS U4271 ( .A(result_add_subt[14]), .Y(n4898) );
OAI2BB2XLTS U4272 ( .B0(n4543), .B1(n4898), .A0N(n4536), .A1N(
FPSENCOS_d_ff_Zn[14]), .Y(n2033) );
INVX2TS U4273 ( .A(result_add_subt[16]), .Y(n4890) );
OAI2BB2XLTS U4274 ( .B0(n4543), .B1(n4890), .A0N(n4536), .A1N(
FPSENCOS_d_ff_Zn[16]), .Y(n2027) );
INVX2TS U4275 ( .A(n4533), .Y(n4673) );
INVX2TS U4276 ( .A(result_add_subt[11]), .Y(n4896) );
OAI2BB2XLTS U4277 ( .B0(n4673), .B1(n4896), .A0N(n4536), .A1N(
FPSENCOS_d_ff_Zn[11]), .Y(n2042) );
INVX2TS U4278 ( .A(result_add_subt[10]), .Y(n4900) );
OAI2BB2XLTS U4279 ( .B0(n4673), .B1(n4900), .A0N(n4536), .A1N(
FPSENCOS_d_ff_Zn[10]), .Y(n2045) );
INVX2TS U4280 ( .A(result_add_subt[8]), .Y(n4893) );
OAI2BB2XLTS U4281 ( .B0(n4673), .B1(n4893), .A0N(n4536), .A1N(
FPSENCOS_d_ff_Zn[8]), .Y(n2051) );
INVX2TS U4282 ( .A(result_add_subt[13]), .Y(n4888) );
OAI2BB2XLTS U4283 ( .B0(n4543), .B1(n4888), .A0N(n4536), .A1N(
FPSENCOS_d_ff_Zn[13]), .Y(n2036) );
INVX2TS U4284 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .Y(n4786) );
AOI222X1TS U4285 ( .A0(n4784), .A1(intadd_0_SUM_19_), .B0(n4784), .B1(n4786),
.C0(intadd_0_SUM_19_), .C1(n4786), .Y(n2744) );
INVX2TS U4286 ( .A(intadd_0_SUM_20_), .Y(n2743) );
NOR2BX1TS U4287 ( .AN(n2665), .B(intadd_0_SUM_21_), .Y(n2669) );
NAND2BXLTS U4288 ( .AN(n2665), .B(intadd_0_SUM_21_), .Y(n2668) );
NAND2BXLTS U4289 ( .AN(n2669), .B(n2668), .Y(n2666) );
INVX2TS U4290 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .Y(n3021) );
XOR2XLTS U4291 ( .A(n2666), .B(n3021), .Y(n2667) );
NOR2BX1TS U4292 ( .AN(FPMULT_P_Sgf[33]), .B(n4767), .Y(n3050) );
BUFX3TS U4293 ( .A(n4811), .Y(n4830) );
CLKXOR2X2TS U4294 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[25]), .B(
intadd_0_n1), .Y(n2976) );
OAI21X1TS U4295 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .A1(n2669),
.B0(n2668), .Y(n2670) );
NOR2X1TS U4296 ( .A(intadd_0_SUM_22_), .B(n2670), .Y(n2968) );
NAND2X1TS U4297 ( .A(intadd_0_SUM_22_), .B(n2670), .Y(n2969) );
OAI21X1TS U4298 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .A1(n2968),
.B0(n2969), .Y(n2671) );
CLKAND2X2TS U4299 ( .A(intadd_0_SUM_23_), .B(n2671), .Y(n4779) );
INVX2TS U4300 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .Y(n4781) );
NOR2X1TS U4301 ( .A(n4779), .B(n4781), .Y(n4778) );
INVX2TS U4302 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .Y(n3029) );
INVX2TS U4303 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[14]), .Y(n4774) );
NAND2X1TS U4304 ( .A(n4773), .B(FPMULT_Sgf_operation_EVEN1_Q_left[15]), .Y(
n4771) );
INVX2TS U4305 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[16]), .Y(n4769) );
NAND2X1TS U4306 ( .A(n4768), .B(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .Y(
n4764) );
INVX2TS U4307 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[18]), .Y(n4762) );
NAND2X1TS U4308 ( .A(n4761), .B(FPMULT_Sgf_operation_EVEN1_Q_left[19]), .Y(
n4759) );
INVX2TS U4309 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[20]), .Y(n4757) );
NAND2X1TS U4310 ( .A(n4756), .B(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .Y(
n4754) );
INVX2TS U4311 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[22]), .Y(n4752) );
NOR2X1TS U4312 ( .A(n4754), .B(n4752), .Y(n4751) );
XOR2XLTS U4313 ( .A(n4751), .B(FPMULT_Sgf_operation_EVEN1_Q_left[23]), .Y(
n2672) );
OAI2BB2XLTS U4314 ( .B0(n4830), .B1(n5129), .A0N(n4783), .A1N(n2672), .Y(
n1695) );
INVX2TS U4315 ( .A(n2673), .Y(n2699) );
INVX2TS U4316 ( .A(n2674), .Y(n2677) );
INVX2TS U4317 ( .A(n2675), .Y(n2676) );
AOI21X1TS U4318 ( .A0(n2699), .A1(n2677), .B0(n2676), .Y(n2680) );
INVX2TS U4319 ( .A(n2678), .Y(n2718) );
NAND2X1TS U4320 ( .A(n2718), .B(n2716), .Y(n2682) );
INVX2TS U4321 ( .A(n2682), .Y(n2679) );
INVX2TS U4322 ( .A(n2681), .Y(n2719) );
XNOR2X1TS U4323 ( .A(n2719), .B(n2682), .Y(n2683) );
BUFX3TS U4324 ( .A(n2693), .Y(n4260) );
AOI22X1TS U4325 ( .A0(n2683), .A1(n4260), .B0(FPADDSUB_Raw_mant_NRM_SWR[6]),
.B1(n4259), .Y(n2684) );
OAI2BB1X1TS U4326 ( .A0N(n4160), .A1N(n2685), .B0(n2684), .Y(n1344) );
BUFX3TS U4327 ( .A(n4534), .Y(n4667) );
INVX1TS U4328 ( .A(result_add_subt[29]), .Y(n4671) );
CLKBUFX2TS U4329 ( .A(n4534), .Y(n4535) );
OAI2BB2XLTS U4330 ( .B0(n4667), .B1(n4671), .A0N(n4535), .A1N(
FPSENCOS_d_ff_Yn[29]), .Y(n1768) );
BUFX3TS U4331 ( .A(n4534), .Y(n4541) );
OAI2BB2XLTS U4332 ( .B0(n4541), .B1(n4677), .A0N(n4535), .A1N(
FPSENCOS_d_ff_Yn[30]), .Y(n1731) );
BUFX3TS U4333 ( .A(n4534), .Y(n4537) );
INVX2TS U4334 ( .A(result_add_subt[1]), .Y(n4966) );
OAI2BB2XLTS U4335 ( .B0(n4537), .B1(n4966), .A0N(n4535), .A1N(
FPSENCOS_d_ff_Yn[1]), .Y(n2071) );
INVX2TS U4336 ( .A(n2686), .Y(n2688) );
NAND2X1TS U4337 ( .A(n2688), .B(n2687), .Y(n2691) );
INVX2TS U4338 ( .A(n2691), .Y(n2689) );
XNOR2X1TS U4339 ( .A(n2699), .B(n2689), .Y(n2696) );
XNOR2X1TS U4340 ( .A(n2692), .B(n2691), .Y(n2694) );
BUFX3TS U4341 ( .A(n2693), .Y(n4201) );
AOI22X1TS U4342 ( .A0(n2694), .A1(n4201), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.B1(n4259), .Y(n2695) );
OAI2BB1X1TS U4343 ( .A0N(n4160), .A1N(n2696), .B0(n2695), .Y(n1345) );
AOI21X1TS U4344 ( .A0(n2699), .A1(n2698), .B0(n2697), .Y(n2715) );
INVX2TS U4345 ( .A(n2763), .Y(n2702) );
NAND2X1TS U4346 ( .A(n2702), .B(n2762), .Y(n2707) );
INVX2TS U4347 ( .A(n2707), .Y(n2703) );
XNOR2X1TS U4348 ( .A(n2704), .B(n2703), .Y(n2710) );
AOI21X1TS U4349 ( .A0(n2719), .A1(n2706), .B0(n2705), .Y(n2764) );
XOR2X1TS U4350 ( .A(n2764), .B(n2707), .Y(n2708) );
AOI22X1TS U4351 ( .A0(n2708), .A1(n4260), .B0(FPADDSUB_Raw_mant_NRM_SWR[8]),
.B1(n4259), .Y(n2709) );
OAI2BB1X1TS U4352 ( .A0N(n4160), .A1N(n2710), .B0(n2709), .Y(n1342) );
INVX2TS U4353 ( .A(n2711), .Y(n2713) );
NAND2X1TS U4354 ( .A(n2713), .B(n2712), .Y(n2720) );
INVX2TS U4355 ( .A(n2720), .Y(n2714) );
INVX2TS U4356 ( .A(n2716), .Y(n2717) );
AOI21X1TS U4357 ( .A0(n2719), .A1(n2718), .B0(n2717), .Y(n2721) );
XOR2X1TS U4358 ( .A(n2721), .B(n2720), .Y(n2722) );
AOI22X1TS U4359 ( .A0(n2722), .A1(n4260), .B0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.B1(n4259), .Y(n2723) );
OAI2BB1X1TS U4360 ( .A0N(n4160), .A1N(n2724), .B0(n2723), .Y(n1343) );
BUFX3TS U4361 ( .A(n4811), .Y(n4844) );
INVX2TS U4362 ( .A(n4844), .Y(n2756) );
BUFX3TS U4363 ( .A(n4811), .Y(n4798) );
CMPR32X2TS U4364 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[22]), .B(n2726),
.C(n2725), .CO(n2731), .S(n2727) );
CMPR32X2TS U4365 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[18]), .B(n2729),
.C(n2728), .CO(n2580), .S(n2730) );
CMPR32X2TS U4366 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[23]), .B(n2732),
.C(n2731), .CO(n2582), .S(n2733) );
XNOR2X1TS U4367 ( .A(intadd_0_SUM_8_), .B(n2734), .Y(n2735) );
XOR2XLTS U4368 ( .A(n2992), .B(n2735), .Y(n2736) );
XNOR2X1TS U4369 ( .A(n2737), .B(intadd_0_SUM_9_), .Y(n2738) );
XOR2XLTS U4370 ( .A(n2982), .B(n2738), .Y(n2739) );
CMPR32X2TS U4371 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .B(n2741), .C(
n2740), .CO(n2584), .S(n2742) );
CMPR32X2TS U4372 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .B(n2744), .C(
n2743), .CO(n2665), .S(n2745) );
XNOR2X1TS U4373 ( .A(intadd_0_SUM_16_), .B(n2746), .Y(n2747) );
XOR2XLTS U4374 ( .A(n3035), .B(n2747), .Y(n2748) );
INVX2TS U4375 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[19]), .Y(n2996) );
NAND2BXLTS U4376 ( .AN(n2750), .B(n2749), .Y(n2751) );
XOR2XLTS U4377 ( .A(n2996), .B(n2751), .Y(n2752) );
INVX2TS U4378 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(n4691) );
XOR2XLTS U4379 ( .A(intadd_0_SUM_13_), .B(n2753), .Y(n2754) );
XOR2XLTS U4380 ( .A(n4691), .B(n2754), .Y(n2755) );
INVX2TS U4381 ( .A(n4976), .Y(busy) );
INVX2TS U4382 ( .A(n2757), .Y(n4248) );
INVX2TS U4383 ( .A(n2758), .Y(n2760) );
NAND2X1TS U4384 ( .A(n2760), .B(n2759), .Y(n2765) );
INVX2TS U4385 ( .A(n2765), .Y(n2761) );
XNOR2X1TS U4386 ( .A(n2766), .B(n2765), .Y(n2767) );
AOI22X1TS U4387 ( .A0(n2767), .A1(n4260), .B0(FPADDSUB_Raw_mant_NRM_SWR[9]),
.B1(n4259), .Y(n2768) );
OAI2BB1X1TS U4388 ( .A0N(n4160), .A1N(n2769), .B0(n2768), .Y(n1341) );
NAND2X1TS U4389 ( .A(n3882), .B(n3045), .Y(n2770) );
NAND2BX2TS U4390 ( .AN(FPMULT_FSM_selector_C), .B(n3049), .Y(n3092) );
NAND2X1TS U4391 ( .A(n3049), .B(FPMULT_FSM_selector_C), .Y(n3048) );
INVX2TS U4392 ( .A(n3048), .Y(n2771) );
OAI22X1TS U4393 ( .A0(n3079), .A1(FPMULT_Add_result[23]), .B0(n3049), .B1(
FPMULT_Sgf_normalized_result[23]), .Y(n2772) );
NAND2X1TS U4394 ( .A(FPMULT_FS_Module_state_reg[0]), .B(n5033), .Y(n3880) );
NOR3X1TS U4395 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[3]), .C(n3880), .Y(n2773) );
BUFX3TS U4396 ( .A(n4709), .Y(n4746) );
BUFX3TS U4397 ( .A(n4746), .Y(n4711) );
CLKBUFX2TS U4398 ( .A(n4709), .Y(n4708) );
BUFX3TS U4399 ( .A(n4708), .Y(n4710) );
OAI2BB2XLTS U4400 ( .B0(n4711), .B1(n2374), .A0N(n4710), .A1N(Data_2[12]),
.Y(n1639) );
INVX2TS U4401 ( .A(n4567), .Y(n4674) );
BUFX3TS U4402 ( .A(n4567), .Y(n4675) );
NOR2X1TS U4403 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_7_n1), .Y(n4600) );
NOR3X2TS U4404 ( .A(FPSENCOS_d_ff2_Y[27]), .B(FPSENCOS_d_ff2_Y[28]), .C(
intadd_7_n1), .Y(n2782) );
INVX2TS U4405 ( .A(n2782), .Y(n2774) );
BUFX3TS U4406 ( .A(n2776), .Y(n4546) );
INVX2TS U4407 ( .A(n4567), .Y(n4548) );
NAND2X1TS U4408 ( .A(n4553), .B(n4996), .Y(intadd_7_CI) );
NOR2X2TS U4409 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_8_n1), .Y(n4559) );
NAND2X1TS U4410 ( .A(n4559), .B(n5078), .Y(n4562) );
BUFX3TS U4411 ( .A(n4567), .Y(n4557) );
OAI2BB2XLTS U4412 ( .B0(n4675), .B1(n2392), .A0N(n4557), .A1N(
intadd_8_SUM_0_), .Y(n1951) );
AOI21X1TS U4413 ( .A0(n2782), .A1(n5088), .B0(n4603), .Y(n4605) );
OA21XLTS U4414 ( .A0(FPSENCOS_d_ff3_sh_y_out[29]), .A1(n2776), .B0(n2783),
.Y(n1848) );
OA22X1TS U4415 ( .A0(n4860), .A1(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B0(n4975),
.B1(result_add_subt[23]), .Y(n1474) );
BUFX3TS U4416 ( .A(n2784), .Y(n5195) );
BUFX3TS U4417 ( .A(n2784), .Y(n5194) );
BUFX3TS U4418 ( .A(n2784), .Y(n5190) );
BUFX3TS U4419 ( .A(n2784), .Y(n5189) );
BUFX3TS U4420 ( .A(n5217), .Y(n5198) );
BUFX3TS U4421 ( .A(n2784), .Y(n5197) );
NOR2X2TS U4422 ( .A(n5065), .B(n5170), .Y(n4334) );
AOI22X1TS U4423 ( .A0(FPMULT_Op_MY[5]), .A1(n2312), .B0(n4699), .B1(n5042),
.Y(n4346) );
AOI221X4TS U4424 ( .A0(n4699), .A1(n5077), .B0(n2311), .B1(FPMULT_Op_MX[8]),
.C0(n2356), .Y(n4347) );
AOI22X1TS U4425 ( .A0(FPMULT_Op_MY[4]), .A1(n2312), .B0(n4699), .B1(n5045),
.Y(n3833) );
AOI22X1TS U4426 ( .A0(n2356), .A1(n4346), .B0(n4347), .B1(n3833), .Y(n2791)
);
AOI22X1TS U4427 ( .A0(FPMULT_Op_MY[9]), .A1(n2306), .B0(n4703), .B1(n5041),
.Y(n4363) );
AOI22X1TS U4428 ( .A0(n2251), .A1(n4363), .B0(n4362), .B1(n2785), .Y(n2790)
);
INVX2TS U4429 ( .A(n2786), .Y(mult_x_254_n90) );
AOI22X1TS U4430 ( .A0(n2207), .A1(n5176), .B0(n2350), .B1(n5023), .Y(n3803)
);
AOI22X1TS U4431 ( .A0(n3854), .A1(n2787), .B0(n3806), .B1(n3803), .Y(n2794)
);
AOI22X1TS U4432 ( .A0(FPMULT_Op_MY[21]), .A1(n2291), .B0(n2289), .B1(n5026),
.Y(n4313) );
AOI22X1TS U4433 ( .A0(FPMULT_Op_MY[20]), .A1(n2292), .B0(n2290), .B1(n5022),
.Y(n3863) );
AOI22X1TS U4434 ( .A0(n2248), .A1(n4313), .B0(n2628), .B1(n3863), .Y(n2793)
);
INVX2TS U4435 ( .A(n2788), .Y(mult_x_219_n90) );
NOR2X1TS U4436 ( .A(n2249), .B(n4420), .Y(DP_OP_454J1_123_2743_n214) );
NOR2XLTS U4437 ( .A(DP_OP_454J1_123_2743_n214), .B(n2789), .Y(
DP_OP_454J1_123_2743_n156) );
CMPR32X2TS U4438 ( .A(n4334), .B(n2791), .C(n2790), .CO(n2792), .S(n2786) );
INVX2TS U4439 ( .A(n2792), .Y(mult_x_254_n89) );
NOR2X1TS U4440 ( .A(n2249), .B(n2866), .Y(DP_OP_454J1_123_2743_n200) );
NOR2XLTS U4441 ( .A(DP_OP_454J1_123_2743_n200), .B(DP_OP_454J1_123_2743_n188), .Y(DP_OP_454J1_123_2743_n155) );
INVX2TS U4442 ( .A(n2795), .Y(mult_x_219_n89) );
AOI22X1TS U4443 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[8]), .B0(
FPMULT_Op_MY[7]), .B1(n4993), .Y(n2796) );
AOI21X1TS U4444 ( .A0(FPMULT_Op_MX[2]), .A1(n2340), .B0(n4731), .Y(n2797) );
CLKBUFX3TS U4445 ( .A(n2797), .Y(n4328) );
AOI22X1TS U4446 ( .A0(n2304), .A1(FPMULT_Op_MY[6]), .B0(n5048), .B1(n2302),
.Y(n2843) );
AOI221X4TS U4447 ( .A0(n5076), .A1(n4704), .B0(FPMULT_Op_MX[2]), .B1(n2304),
.C0(n4328), .Y(n4371) );
AOI22X1TS U4448 ( .A0(n2303), .A1(FPMULT_Op_MY[5]), .B0(n5042), .B1(n4704),
.Y(n3870) );
AOI22X1TS U4449 ( .A0(n4328), .A1(n2843), .B0(n4371), .B1(n3870), .Y(n2939)
);
INVX2TS U4450 ( .A(n2798), .Y(mult_x_254_n125) );
OAI22X1TS U4451 ( .A0(FPMULT_Op_MY[19]), .A1(n4322), .B0(FPMULT_Op_MY[20]),
.B1(n3857), .Y(n2799) );
AOI21X1TS U4452 ( .A0(n3864), .A1(FPMULT_Op_MY[20]), .B0(n2799), .Y(n2943)
);
INVX2TS U4453 ( .A(n4320), .Y(n4268) );
AOI22X1TS U4454 ( .A0(n2309), .A1(FPMULT_Op_MY[18]), .B0(n5025), .B1(n4697),
.Y(n2836) );
AOI22X1TS U4455 ( .A0(FPMULT_Op_MX[15]), .A1(n2200), .B0(n5029), .B1(n2308),
.Y(n3867) );
AOI22X1TS U4456 ( .A0(n4268), .A1(n2836), .B0(n4266), .B1(n3867), .Y(n2942)
);
INVX2TS U4457 ( .A(n2800), .Y(mult_x_219_n125) );
AOI22X1TS U4458 ( .A0(n2907), .A1(n2802), .B0(n2905), .B1(n2801), .Y(n2922)
);
AO21XLTS U4459 ( .A0(n2804), .A1(n2803), .B0(DP_OP_454J1_123_2743_n131), .Y(
n2921) );
AOI2BB2XLTS U4460 ( .B0(n3798), .B1(n2806), .A0N(n4438), .A1N(n2805), .Y(
n2929) );
AOI2BB2XLTS U4461 ( .B0(n3795), .B1(n2808), .A0N(n2631), .A1N(n2807), .Y(
n2928) );
INVX2TS U4462 ( .A(n2809), .Y(DP_OP_454J1_123_2743_n129) );
INVX2TS U4463 ( .A(intadd_3_SUM_5_), .Y(FPMULT_Sgf_operation_EVEN1_left_N9)
);
INVX2TS U4464 ( .A(intadd_3_SUM_10_), .Y(FPMULT_Sgf_operation_EVEN1_left_N14) );
INVX2TS U4465 ( .A(intadd_3_SUM_4_), .Y(FPMULT_Sgf_operation_EVEN1_left_N8)
);
INVX2TS U4466 ( .A(intadd_3_SUM_3_), .Y(FPMULT_Sgf_operation_EVEN1_left_N7)
);
INVX2TS U4467 ( .A(intadd_3_SUM_12_), .Y(FPMULT_Sgf_operation_EVEN1_left_N16) );
INVX2TS U4468 ( .A(intadd_3_SUM_9_), .Y(FPMULT_Sgf_operation_EVEN1_left_N13)
);
NAND2X1TS U4469 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MY[15]), .Y(n2810) );
INVX2TS U4470 ( .A(n2810), .Y(n2811) );
AOI222X1TS U4471 ( .A0(FPMULT_Op_MX[13]), .A1(n2811), .B0(n2199), .B1(n5066),
.C0(n4999), .C1(n2810), .Y(n2816) );
AOI22X1TS U4472 ( .A0(n2309), .A1(n5021), .B0(n2369), .B1(n4697), .Y(n3808)
);
AOI22X1TS U4473 ( .A0(n4268), .A1(n3808), .B0(n2813), .B1(n4320), .Y(n2815)
);
NAND2X1TS U4474 ( .A(n2816), .B(n2815), .Y(n2822) );
INVX2TS U4475 ( .A(n2822), .Y(n2825) );
NAND2X1TS U4476 ( .A(FPMULT_Op_MX[12]), .B(n2369), .Y(n4276) );
AOI32X1TS U4477 ( .A0(FPMULT_Op_MX[13]), .A1(n2374), .A2(n4276), .B0(n4268),
.B1(n4714), .Y(n4274) );
OAI22X1TS U4478 ( .A0(n2199), .A1(n3857), .B0(FPMULT_Op_MY[13]), .B1(n4322),
.Y(n2814) );
AOI21X1TS U4479 ( .A0(n2199), .A1(n3864), .B0(n2814), .Y(n4275) );
NOR2X2TS U4480 ( .A(n4274), .B(n4275), .Y(n4273) );
NAND2X1TS U4481 ( .A(n4273), .B(n2231), .Y(n2821) );
OA21XLTS U4482 ( .A0(n4273), .A1(n2231), .B0(n2821), .Y(n2818) );
OAI21XLTS U4483 ( .A0(n2825), .A1(n2362), .B0(n2818), .Y(n2817) );
AO21XLTS U4484 ( .A0(n4732), .A1(FPMULT_Op_MY[12]), .B0(mult_x_219_n191),
.Y(n2819) );
AO21XLTS U4485 ( .A0(n2820), .A1(n2819), .B0(mult_x_219_n136), .Y(n2828) );
AOI31XLTS U4486 ( .A0(n4273), .A1(n2825), .A2(n2231), .B0(n2362), .Y(n2824)
);
OAI31X1TS U4487 ( .A0(n4273), .A1(n2825), .A2(n2231), .B0(n2824), .Y(n4272)
);
NOR2X1TS U4488 ( .A(intadd_3_SUM_0_), .B(n4272), .Y(n4271) );
NOR2XLTS U4489 ( .A(n2826), .B(n4271), .Y(n2827) );
CMPR32X2TS U4490 ( .A(n2828), .B(n2827), .C(intadd_3_SUM_1_), .CO(
intadd_3_B_2_), .S(n2829) );
INVX2TS U4491 ( .A(n2829), .Y(FPMULT_Sgf_operation_EVEN1_left_N5) );
INVX2TS U4492 ( .A(intadd_3_SUM_7_), .Y(FPMULT_Sgf_operation_EVEN1_left_N11)
);
INVX2TS U4493 ( .A(intadd_3_SUM_16_), .Y(FPMULT_Sgf_operation_EVEN1_left_N20) );
INVX2TS U4494 ( .A(intadd_3_SUM_17_), .Y(FPMULT_Sgf_operation_EVEN1_left_N21) );
INVX2TS U4495 ( .A(intadd_3_SUM_2_), .Y(FPMULT_Sgf_operation_EVEN1_left_N6)
);
INVX2TS U4496 ( .A(intadd_3_SUM_18_), .Y(FPMULT_Sgf_operation_EVEN1_left_N22) );
AOI22X1TS U4497 ( .A0(FPMULT_Op_MY[10]), .A1(n2310), .B0(n2311), .B1(n5043),
.Y(n3843) );
INVX2TS U4498 ( .A(n4347), .Y(n4344) );
AOI22X1TS U4499 ( .A0(FPMULT_Op_MY[9]), .A1(n4699), .B0(n2312), .B1(n5041),
.Y(n4342) );
OA22X1TS U4500 ( .A0(n2208), .A1(n3843), .B0(n4344), .B1(n4342), .Y(n2925)
);
AOI22X1TS U4501 ( .A0(FPMULT_Op_MY[11]), .A1(n2299), .B0(n2301), .B1(n5028),
.Y(n4349) );
INVX2TS U4502 ( .A(n4357), .Y(n4354) );
OA22X1TS U4503 ( .A0(n4729), .A1(n2230), .B0(n4349), .B1(n4354), .Y(n2924)
);
INVX2TS U4504 ( .A(n2830), .Y(mult_x_254_n47) );
NAND2X1TS U4505 ( .A(n2210), .B(mult_x_219_n31), .Y(n3773) );
INVX2TS U4506 ( .A(n3773), .Y(n2832) );
NOR2X2TS U4507 ( .A(n2241), .B(mult_x_219_n31), .Y(n3775) );
OAI31X1TS U4508 ( .A0(n2832), .A1(n2357), .A2(n3775), .B0(n2831), .Y(
intadd_3_B_18_) );
NOR2XLTS U4509 ( .A(n4448), .B(n2250), .Y(
FPMULT_Sgf_operation_EVEN1_middle_N0) );
AOI32X1TS U4510 ( .A0(FPMULT_Op_MX[18]), .A1(n2318), .A2(n2267), .B0(n2840),
.B1(n2319), .Y(n2911) );
AOI22X1TS U4511 ( .A0(n2241), .A1(n2323), .B0(n2324), .B1(n5024), .Y(n3840)
);
INVX2TS U4512 ( .A(n3806), .Y(n4302) );
AOI22X1TS U4513 ( .A0(FPMULT_Op_MY[21]), .A1(n2349), .B0(n2325), .B1(n5026),
.Y(n4299) );
OA22X1TS U4514 ( .A0(n4304), .A1(n3840), .B0(n4302), .B1(n4299), .Y(n2910)
);
INVX2TS U4515 ( .A(n2833), .Y(mult_x_219_n47) );
INVX2TS U4516 ( .A(intadd_3_SUM_14_), .Y(FPMULT_Sgf_operation_EVEN1_left_N18) );
NOR2XLTS U4517 ( .A(n2259), .B(n2250), .Y(n2835) );
AOI22X1TS U4518 ( .A0(n3781), .A1(intadd_4_SUM_0_), .B0(n2260), .B1(n4412),
.Y(n2834) );
AOI31XLTS U4519 ( .A0(intadd_4_SUM_0_), .A1(n3781), .A2(n2835), .B0(n2834),
.Y(FPMULT_Sgf_operation_EVEN1_middle_N1) );
INVX2TS U4520 ( .A(intadd_3_SUM_8_), .Y(FPMULT_Sgf_operation_EVEN1_left_N12)
);
INVX2TS U4521 ( .A(intadd_3_SUM_11_), .Y(FPMULT_Sgf_operation_EVEN1_left_N15) );
INVX2TS U4522 ( .A(intadd_3_SUM_13_), .Y(FPMULT_Sgf_operation_EVEN1_left_N17) );
INVX2TS U4523 ( .A(intadd_3_SUM_6_), .Y(FPMULT_Sgf_operation_EVEN1_left_N10)
);
INVX2TS U4524 ( .A(intadd_3_SUM_15_), .Y(FPMULT_Sgf_operation_EVEN1_left_N19) );
AOI22X1TS U4525 ( .A0(n4268), .A1(n2837), .B0(n4266), .B1(n2836), .Y(n2886)
);
AOI22X1TS U4526 ( .A0(n2840), .A1(n2839), .B0(n3860), .B1(n2838), .Y(n2885)
);
AOI22X1TS U4527 ( .A0(FPMULT_Op_MY[13]), .A1(n2325), .B0(n2349), .B1(n5021),
.Y(n3770) );
AOI22X1TS U4528 ( .A0(n3854), .A1(n3770), .B0(n2841), .B1(n4304), .Y(n2884)
);
INVX2TS U4529 ( .A(n2842), .Y(mult_x_219_n118) );
INVX2TS U4530 ( .A(intadd_2_SUM_12_), .Y(
FPMULT_Sgf_operation_EVEN1_right_N16) );
AOI22X1TS U4531 ( .A0(n2304), .A1(FPMULT_Op_MY[7]), .B0(n5044), .B1(n4704),
.Y(n4370) );
AOI22X1TS U4532 ( .A0(n4328), .A1(n4370), .B0(n4371), .B1(n2843), .Y(n2918)
);
AOI22X1TS U4533 ( .A0(FPMULT_Op_MY[3]), .A1(n2301), .B0(n4701), .B1(n5046),
.Y(n4356) );
AOI22X1TS U4534 ( .A0(FPMULT_Op_MY[2]), .A1(n2300), .B0(n2299), .B1(n5050),
.Y(n3847) );
AOI22X1TS U4535 ( .A0(n3848), .A1(n4356), .B0(n4357), .B1(n3847), .Y(n2917)
);
AOI22X1TS U4536 ( .A0(FPMULT_Op_MY[1]), .A1(n2312), .B0(n2310), .B1(n5065),
.Y(n3771) );
AOI22X1TS U4537 ( .A0(n2356), .A1(n3771), .B0(n2844), .B1(n2208), .Y(n2916)
);
INVX2TS U4538 ( .A(n2845), .Y(mult_x_254_n118) );
INVX2TS U4539 ( .A(intadd_2_SUM_17_), .Y(
FPMULT_Sgf_operation_EVEN1_right_N21) );
INVX2TS U4540 ( .A(n3793), .Y(n3782) );
AOI22X1TS U4541 ( .A0(intadd_4_SUM_5_), .A1(n2638), .B0(n3782), .B1(n4399),
.Y(n2846) );
OAI21XLTS U4542 ( .A0(intadd_4_SUM_4_), .A1(n2368), .B0(n2846), .Y(
DP_OP_454J1_123_2743_n252) );
AOI22X1TS U4543 ( .A0(n2303), .A1(FPMULT_Op_MY[1]), .B0(n5065), .B1(n2302),
.Y(n4323) );
INVX2TS U4544 ( .A(n4328), .Y(n4373) );
AOI22X1TS U4545 ( .A0(n4328), .A1(n4323), .B0(n2847), .B1(n4373), .Y(n2854)
);
NOR2X1TS U4546 ( .A(n2317), .B(n5046), .Y(n2849) );
AOI22X1TS U4547 ( .A0(FPMULT_Op_MY[2]), .A1(n2317), .B0(n2849), .B1(n2339),
.Y(n2848) );
OAI21X1TS U4548 ( .A0(n2849), .A1(n2339), .B0(n2848), .Y(n2853) );
NAND2X1TS U4549 ( .A(n2854), .B(n2853), .Y(n2858) );
INVX2TS U4550 ( .A(n2858), .Y(n2857) );
NAND2X1TS U4551 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MY[2]), .Y(n2851) );
OAI211XLTS U4552 ( .A0(n5065), .A1(n2315), .B0(n2851), .C0(n2340), .Y(n2850)
);
OAI21X1TS U4553 ( .A0(n2339), .A1(n2851), .B0(n2850), .Y(n3828) );
NAND2X1TS U4554 ( .A(n3828), .B(n3829), .Y(n3827) );
AO21XLTS U4555 ( .A0(n2275), .A1(n4328), .B0(mult_x_254_n211), .Y(n2852) );
NAND2X1TS U4556 ( .A(n3827), .B(n2852), .Y(n2859) );
NOR3X1TS U4557 ( .A(n3827), .B(FPMULT_Op_MY[0]), .C(mult_x_254_n211), .Y(
n2860) );
NOR2BX1TS U4558 ( .AN(n2859), .B(n2860), .Y(n2856) );
NOR2X2TS U4559 ( .A(n2854), .B(n2853), .Y(n2861) );
OAI21XLTS U4560 ( .A0(n2857), .A1(n2861), .B0(n2856), .Y(n2855) );
OAI31X1TS U4561 ( .A0(n2857), .A1(n2856), .A2(n2861), .B0(n2855), .Y(
FPMULT_Sgf_operation_EVEN1_right_N3) );
INVX2TS U4562 ( .A(intadd_2_SUM_10_), .Y(
FPMULT_Sgf_operation_EVEN1_right_N14) );
OAI21X1TS U4563 ( .A0(n2861), .A1(n2859), .B0(n2858), .Y(n2875) );
AOI21X1TS U4564 ( .A0(n2861), .A1(n2860), .B0(n2875), .Y(n2862) );
NAND2X1TS U4565 ( .A(intadd_2_SUM_0_), .B(n2862), .Y(n2876) );
OAI21XLTS U4566 ( .A0(intadd_2_SUM_0_), .A1(n2862), .B0(n2876), .Y(
FPMULT_Sgf_operation_EVEN1_right_N4) );
INVX2TS U4567 ( .A(intadd_4_SUM_7_), .Y(n4436) );
AOI22X1TS U4568 ( .A0(intadd_4_SUM_7_), .A1(n2638), .B0(n3782), .B1(n4436),
.Y(n2863) );
OAI21XLTS U4569 ( .A0(intadd_4_SUM_6_), .A1(n2368), .B0(n2863), .Y(
DP_OP_454J1_123_2743_n250) );
INVX2TS U4570 ( .A(intadd_2_SUM_2_), .Y(FPMULT_Sgf_operation_EVEN1_right_N6)
);
INVX2TS U4571 ( .A(intadd_2_SUM_3_), .Y(FPMULT_Sgf_operation_EVEN1_right_N7)
);
INVX2TS U4572 ( .A(intadd_2_SUM_4_), .Y(FPMULT_Sgf_operation_EVEN1_right_N8)
);
INVX2TS U4573 ( .A(intadd_2_SUM_5_), .Y(FPMULT_Sgf_operation_EVEN1_right_N9)
);
INVX2TS U4574 ( .A(n2254), .Y(n4445) );
AOI22X1TS U4575 ( .A0(n2359), .A1(n2254), .B0(n4445), .B1(n2277), .Y(n4417)
);
OAI2BB1X1TS U4576 ( .A0N(n4417), .A1N(n4420), .B0(n2864), .Y(n2882) );
INVX2TS U4577 ( .A(n2866), .Y(n3876) );
AOI22X1TS U4578 ( .A0(n2321), .A1(n4445), .B0(n2255), .B1(n2371), .Y(n2937)
);
OAI21X1TS U4579 ( .A0(n2322), .A1(n2865), .B0(DP_OP_454J1_123_2743_n188),
.Y(n2936) );
AOI21X1TS U4580 ( .A0(intadd_4_n1), .A1(FPMULT_Op_MY[11]), .B0(n2255), .Y(
n2867) );
CLKBUFX3TS U4581 ( .A(n2867), .Y(n4450) );
INVX2TS U4582 ( .A(n4450), .Y(n4446) );
AOI22X1TS U4583 ( .A0(n2321), .A1(n4446), .B0(n4450), .B1(n2320), .Y(n2881)
);
AOI22X1TS U4584 ( .A0(n3876), .A1(n2937), .B0(n2354), .B1(n2881), .Y(n2869)
);
INVX2TS U4585 ( .A(n2868), .Y(DP_OP_454J1_123_2743_n47) );
INVX2TS U4586 ( .A(intadd_2_SUM_6_), .Y(FPMULT_Sgf_operation_EVEN1_right_N10) );
INVX2TS U4587 ( .A(intadd_2_SUM_7_), .Y(FPMULT_Sgf_operation_EVEN1_right_N11) );
INVX2TS U4588 ( .A(intadd_2_SUM_8_), .Y(FPMULT_Sgf_operation_EVEN1_right_N12) );
INVX2TS U4589 ( .A(intadd_2_SUM_9_), .Y(FPMULT_Sgf_operation_EVEN1_right_N13) );
INVX2TS U4590 ( .A(intadd_2_SUM_11_), .Y(
FPMULT_Sgf_operation_EVEN1_right_N15) );
INVX2TS U4591 ( .A(intadd_2_SUM_15_), .Y(
FPMULT_Sgf_operation_EVEN1_right_N19) );
INVX2TS U4592 ( .A(intadd_2_SUM_16_), .Y(
FPMULT_Sgf_operation_EVEN1_right_N20) );
INVX2TS U4593 ( .A(intadd_2_SUM_13_), .Y(
FPMULT_Sgf_operation_EVEN1_right_N17) );
CMPR32X2TS U4594 ( .A(n2870), .B(n2882), .C(n2869), .CO(n2871), .S(n2868) );
INVX2TS U4595 ( .A(n2871), .Y(DP_OP_454J1_123_2743_n46) );
INVX2TS U4596 ( .A(intadd_2_SUM_14_), .Y(
FPMULT_Sgf_operation_EVEN1_right_N18) );
INVX2TS U4597 ( .A(intadd_2_SUM_18_), .Y(
FPMULT_Sgf_operation_EVEN1_right_N22) );
OAI21X2TS U4598 ( .A0(n2302), .A1(n5002), .B0(n2306), .Y(mult_x_254_n197) );
AOI22X1TS U4599 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[5]), .B0(
FPMULT_Op_MY[4]), .B1(n2317), .Y(n2872) );
NOR3BX1TS U4600 ( .AN(intadd_2_A_0_), .B(n2874), .C(mult_x_254_n197), .Y(
mult_x_254_n136) );
NAND2BXLTS U4601 ( .AN(mult_x_254_n197), .B(intadd_2_A_0_), .Y(n2873) );
AOI21X1TS U4602 ( .A0(n2874), .A1(n2873), .B0(mult_x_254_n136), .Y(n3836) );
NOR2BX1TS U4603 ( .AN(n2876), .B(n2875), .Y(n3835) );
INVX2TS U4604 ( .A(intadd_2_SUM_1_), .Y(n3834) );
INVX2TS U4605 ( .A(n2877), .Y(intadd_2_B_2_) );
NOR2X1TS U4606 ( .A(n4993), .B(n5045), .Y(n2879) );
AOI22X1TS U4607 ( .A0(n2317), .A1(FPMULT_Op_MY[3]), .B0(n2340), .B1(n2879),
.Y(n2878) );
OAI21XLTS U4608 ( .A0(n2339), .A1(n2879), .B0(n2878), .Y(intadd_2_CI) );
AOI21X1TS U4609 ( .A0(n2260), .A1(intadd_5_SUM_1_), .B0(n2314), .Y(n3780) );
AOI22X1TS U4610 ( .A0(n2321), .A1(intadd_4_SUM_7_), .B0(n4436), .B1(n2371),
.Y(n2961) );
AOI22X1TS U4611 ( .A0(intadd_4_SUM_6_), .A1(n2321), .B0(n2320), .B1(n4397),
.Y(n2895) );
AOI22X1TS U4612 ( .A0(n3876), .A1(n2961), .B0(n2354), .B1(n2895), .Y(n2888)
);
INVX2TS U4613 ( .A(n2880), .Y(DP_OP_454J1_123_2743_n75) );
AOI22X1TS U4614 ( .A0(n2321), .A1(intadd_4_SUM_9_), .B0(n4432), .B1(n2371),
.Y(n3839) );
AOI22X1TS U4615 ( .A0(n3876), .A1(n2881), .B0(n2354), .B1(n3839), .Y(n2891)
);
INVX2TS U4616 ( .A(n2882), .Y(n2890) );
INVX2TS U4617 ( .A(n2883), .Y(DP_OP_454J1_123_2743_n52) );
CMPR32X2TS U4618 ( .A(n2886), .B(n2885), .C(n2884), .CO(n2887), .S(n2842) );
INVX2TS U4619 ( .A(n2887), .Y(mult_x_219_n117) );
CMPR32X2TS U4620 ( .A(intadd_5_SUM_0_), .B(n3780), .C(n2888), .CO(n2880),
.S(n2889) );
INVX2TS U4621 ( .A(n2889), .Y(DP_OP_454J1_123_2743_n76) );
CMPR32X2TS U4622 ( .A(n2892), .B(n2891), .C(n2890), .CO(n2893), .S(n2883) );
INVX2TS U4623 ( .A(n2893), .Y(DP_OP_454J1_123_2743_n51) );
AOI22X1TS U4624 ( .A0(n2359), .A1(intadd_4_SUM_7_), .B0(n4436), .B1(n2277),
.Y(n2906) );
AOI22X1TS U4625 ( .A0(n2907), .A1(n2894), .B0(n2905), .B1(n2906), .Y(n2956)
);
AOI22X1TS U4626 ( .A0(intadd_4_SUM_5_), .A1(n2322), .B0(n2371), .B1(n4399),
.Y(n2908) );
AOI22X1TS U4627 ( .A0(n3876), .A1(n2895), .B0(n2354), .B1(n2908), .Y(n2955)
);
INVX2TS U4628 ( .A(n2896), .Y(DP_OP_454J1_123_2743_n84) );
AOI22X1TS U4629 ( .A0(n2297), .A1(intadd_4_SUM_7_), .B0(n4436), .B1(n2375),
.Y(n2900) );
AOI22X1TS U4630 ( .A0(n3795), .A1(n2898), .B0(n2897), .B1(n2900), .Y(n2952)
);
AOI22X1TS U4631 ( .A0(intadd_4_SUM_6_), .A1(intadd_5_SUM_6_), .B0(n2358),
.B1(n4397), .Y(n2904) );
AOI22X1TS U4632 ( .A0(intadd_4_SUM_5_), .A1(intadd_5_SUM_6_), .B0(n2277),
.B1(n4399), .Y(n2902) );
AOI22X1TS U4633 ( .A0(n2907), .A1(n2904), .B0(n2905), .B1(n2902), .Y(n2951)
);
AOI2BB2XLTS U4634 ( .B0(n3795), .B1(n2900), .A0N(n2631), .A1N(n2899), .Y(
n2933) );
AOI2BB2XLTS U4635 ( .B0(n2907), .B1(n2902), .A0N(n2901), .A1N(n4419), .Y(
n2932) );
INVX2TS U4636 ( .A(n2903), .Y(DP_OP_454J1_123_2743_n103) );
AOI22X1TS U4637 ( .A0(n2907), .A1(n2906), .B0(n2905), .B1(n2904), .Y(n2948)
);
AOI22X1TS U4638 ( .A0(intadd_4_SUM_4_), .A1(n2322), .B0(n2320), .B1(n4401),
.Y(n3868) );
AOI22X1TS U4639 ( .A0(n3876), .A1(n2908), .B0(n2354), .B1(n3868), .Y(n2947)
);
INVX2TS U4640 ( .A(n2909), .Y(DP_OP_454J1_123_2743_n94) );
CMPR32X2TS U4641 ( .A(n2244), .B(n2911), .C(n2910), .CO(n2833), .S(n2912) );
INVX2TS U4642 ( .A(n2912), .Y(mult_x_219_n48) );
NOR2X1TS U4643 ( .A(n2317), .B(n5044), .Y(n2914) );
AOI22X1TS U4644 ( .A0(FPMULT_Op_MY[6]), .A1(n4993), .B0(n2914), .B1(n2340),
.Y(n2913) );
OAI21X1TS U4645 ( .A0(n2914), .A1(n2340), .B0(n2913), .Y(n3772) );
NOR3X2TS U4646 ( .A(mult_x_254_n196), .B(n3772), .C(n2230), .Y(
mult_x_254_n129) );
AOI22X1TS U4647 ( .A0(n4450), .A1(n3782), .B0(n2638), .B1(n4446), .Y(n2915)
);
OAI21X1TS U4648 ( .A0(intadd_4_SUM_9_), .A1(n4447), .B0(n2915), .Y(
DP_OP_454J1_123_2743_n247) );
CMPR32X2TS U4649 ( .A(n2918), .B(n2917), .C(n2916), .CO(n2919), .S(n2845) );
INVX2TS U4650 ( .A(n2919), .Y(mult_x_254_n117) );
CMPR32X2TS U4651 ( .A(n2922), .B(n2921), .C(n2920), .CO(n2809), .S(n2923) );
INVX2TS U4652 ( .A(n2923), .Y(DP_OP_454J1_123_2743_n130) );
CMPR32X2TS U4653 ( .A(n2232), .B(n2925), .C(n2924), .CO(n2830), .S(n2926) );
INVX2TS U4654 ( .A(n2926), .Y(mult_x_254_n48) );
AOI22X1TS U4655 ( .A0(intadd_4_SUM_9_), .A1(n2638), .B0(n3782), .B1(n4432),
.Y(n2927) );
OAI21X1TS U4656 ( .A0(intadd_4_SUM_8_), .A1(n4447), .B0(n2927), .Y(
DP_OP_454J1_123_2743_n248) );
CMPR32X2TS U4657 ( .A(n2930), .B(n2929), .C(n2928), .CO(n2920), .S(n2931) );
INVX2TS U4658 ( .A(n2931), .Y(DP_OP_454J1_123_2743_n137) );
CMPR32X2TS U4659 ( .A(n2934), .B(n2933), .C(n2932), .CO(n2950), .S(n2935) );
INVX2TS U4660 ( .A(n2935), .Y(DP_OP_454J1_123_2743_n111) );
OAI21X1TS U4661 ( .A0(n3876), .A1(n2937), .B0(n2936), .Y(
DP_OP_454J1_123_2743_n42) );
INVX2TS U4662 ( .A(DP_OP_454J1_123_2743_n42), .Y(DP_OP_454J1_123_2743_n41)
);
NOR2X1TS U4663 ( .A(n4451), .B(n2250), .Y(DP_OP_454J1_123_2743_n172) );
CMPR32X2TS U4664 ( .A(n2940), .B(n4331), .C(n2939), .CO(n2941), .S(n2798) );
INVX2TS U4665 ( .A(n2941), .Y(mult_x_254_n124) );
CMPR32X2TS U4666 ( .A(n2943), .B(n4283), .C(n2942), .CO(n2944), .S(n2800) );
INVX2TS U4667 ( .A(n2944), .Y(mult_x_219_n124) );
AOI22X1TS U4668 ( .A0(intadd_4_SUM_6_), .A1(n2638), .B0(n3782), .B1(n4397),
.Y(n2945) );
OAI21X1TS U4669 ( .A0(intadd_4_SUM_5_), .A1(n4447), .B0(n2945), .Y(
DP_OP_454J1_123_2743_n251) );
AOI22X1TS U4670 ( .A0(n3864), .A1(n2210), .B0(n3865), .B1(n5026), .Y(n2946)
);
OAI21X1TS U4671 ( .A0(n2210), .A1(n3857), .B0(n2946), .Y(mult_x_219_n222) );
CMPR32X2TS U4672 ( .A(n2259), .B(n2948), .C(n2947), .CO(n2949), .S(n2909) );
INVX2TS U4673 ( .A(n2949), .Y(DP_OP_454J1_123_2743_n93) );
CMPR32X2TS U4674 ( .A(n2952), .B(n2951), .C(n2950), .CO(n2953), .S(n2903) );
INVX2TS U4675 ( .A(n2953), .Y(DP_OP_454J1_123_2743_n102) );
AOI22X1TS U4676 ( .A0(intadd_4_SUM_8_), .A1(n2638), .B0(n3782), .B1(n4434),
.Y(n2954) );
OAI21X1TS U4677 ( .A0(intadd_4_SUM_7_), .A1(n2368), .B0(n2954), .Y(
DP_OP_454J1_123_2743_n249) );
CMPR32X2TS U4678 ( .A(n2259), .B(n2956), .C(n2955), .CO(n2957), .S(n2896) );
INVX2TS U4679 ( .A(n2957), .Y(DP_OP_454J1_123_2743_n83) );
NAND2X1TS U4680 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MY[6]), .Y(n2959) );
OAI21X1TS U4681 ( .A0(n2339), .A1(n2959), .B0(n2958), .Y(mult_x_254_n232) );
AOI22X1TS U4682 ( .A0(FPMULT_Op_MY[8]), .A1(n4701), .B0(n2300), .B1(n5047),
.Y(n3851) );
AOI22X1TS U4683 ( .A0(FPMULT_Op_MY[7]), .A1(n4701), .B0(n2301), .B1(n5044),
.Y(n4352) );
OA22X1TS U4684 ( .A0(n4359), .A1(n3851), .B0(n4354), .B1(n4352), .Y(n2962)
);
INVX2TS U4685 ( .A(n2960), .Y(mult_x_254_n80) );
AOI22X1TS U4686 ( .A0(n2321), .A1(intadd_4_SUM_8_), .B0(n4434), .B1(n2371),
.Y(n3838) );
AOI22X1TS U4687 ( .A0(n3876), .A1(n3838), .B0(n2354), .B1(n2961), .Y(
DP_OP_454J1_123_2743_n68) );
INVX2TS U4688 ( .A(DP_OP_454J1_123_2743_n68), .Y(DP_OP_454J1_123_2743_n67)
);
CMPR32X2TS U4689 ( .A(n4334), .B(n2963), .C(n2962), .CO(n2964), .S(n2960) );
INVX2TS U4690 ( .A(n2964), .Y(mult_x_254_n79) );
NOR2X1TS U4691 ( .A(n5042), .B(n5170), .Y(mult_x_254_n151) );
NOR2X1TS U4692 ( .A(n2374), .B(n2267), .Y(mult_x_219_n190) );
INVX2TS U4693 ( .A(mult_x_254_n37), .Y(mult_x_254_n38) );
NOR2X1TS U4694 ( .A(n5041), .B(n5170), .Y(mult_x_254_n149) );
INVX2TS U4695 ( .A(mult_x_254_n63), .Y(mult_x_254_n64) );
OR2X2TS U4696 ( .A(n2965), .B(n4989), .Y(n3923) );
NAND2X1TS U4697 ( .A(n3923), .B(FPMULT_Add_result[0]), .Y(n2966) );
NAND2X1TS U4698 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n2224), .Y(intadd_6_CI)
);
NAND2X1TS U4699 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .Y(n3044) );
INVX2TS U4700 ( .A(n3044), .Y(n4071) );
NAND2X1TS U4701 ( .A(n4071), .B(n2967), .Y(n4741) );
INVX2TS U4702 ( .A(n4741), .Y(n4743) );
INVX2TS U4703 ( .A(n3923), .Y(n3955) );
NOR2X1TS U4704 ( .A(n3045), .B(n3880), .Y(n4692) );
NAND2X1TS U4705 ( .A(FPMULT_P_Sgf[47]), .B(n4692), .Y(n3769) );
OAI31X1TS U4706 ( .A0(n4743), .A1(n3955), .A2(n5032), .B0(n3769), .Y(n1623)
);
INVX2TS U4707 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .Y(n3024) );
NOR2BX1TS U4708 ( .AN(n2969), .B(n2968), .Y(n2970) );
XOR2XLTS U4709 ( .A(n3024), .B(n2970), .Y(n2971) );
NAND2X1TS U4710 ( .A(n3961), .B(FPMULT_P_Sgf[34]), .Y(n3091) );
XOR2XLTS U4711 ( .A(n2972), .B(intadd_0_SUM_24_), .Y(n2973) );
XOR2XLTS U4712 ( .A(n3029), .B(n2973), .Y(n2974) );
NAND2X1TS U4713 ( .A(n3961), .B(FPMULT_P_Sgf[36]), .Y(n3062) );
INVX2TS U4714 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .Y(n3031) );
XOR2XLTS U4715 ( .A(n3031), .B(n2977), .Y(n2978) );
NAND2X1TS U4716 ( .A(n3961), .B(FPMULT_P_Sgf[37]), .Y(n3088) );
INVX2TS U4717 ( .A(n2979), .Y(intadd_0_B_21_) );
INVX2TS U4718 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .Y(n2981) );
INVX2TS U4719 ( .A(n2980), .Y(intadd_0_A_21_) );
CMPR32X2TS U4720 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[21]), .B(n2982),
.C(n2981), .CO(n2983), .S(n2980) );
INVX2TS U4721 ( .A(n2983), .Y(intadd_0_B_22_) );
INVX2TS U4722 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[22]), .Y(n2985) );
INVX2TS U4723 ( .A(n2984), .Y(intadd_0_A_22_) );
CMPR32X2TS U4724 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[22]), .B(n2985),
.C(n4752), .CO(n2986), .S(n2984) );
INVX2TS U4725 ( .A(n2986), .Y(intadd_0_B_23_) );
INVX2TS U4726 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[23]), .Y(n2989) );
INVX2TS U4727 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[23]), .Y(n2988) );
INVX2TS U4728 ( .A(n2987), .Y(intadd_0_A_23_) );
CMPR32X2TS U4729 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[23]), .B(n2989),
.C(n2988), .CO(n2990), .S(n2987) );
INVX2TS U4730 ( .A(n2990), .Y(intadd_0_B_24_) );
INVX2TS U4731 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[24]), .Y(
intadd_0_A_24_) );
INVX2TS U4732 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[19]), .Y(n2995) );
INVX2TS U4733 ( .A(n2991), .Y(intadd_0_B_20_) );
CMPR32X2TS U4734 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[20]), .B(n2992),
.C(n4757), .CO(n2979), .S(n2993) );
INVX2TS U4735 ( .A(n2993), .Y(intadd_0_A_20_) );
INVX2TS U4736 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[18]), .Y(n3002) );
INVX2TS U4737 ( .A(n2994), .Y(intadd_0_B_19_) );
CMPR32X2TS U4738 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[19]), .B(n2996),
.C(n2995), .CO(n2991), .S(n2997) );
INVX2TS U4739 ( .A(n2997), .Y(intadd_0_A_19_) );
INVX2TS U4740 ( .A(n2998), .Y(intadd_0_B_17_) );
INVX2TS U4741 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .Y(n3000) );
INVX2TS U4742 ( .A(n2999), .Y(intadd_0_A_17_) );
CMPR32X2TS U4743 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[17]), .B(n4805),
.C(n3000), .CO(n3001), .S(n2999) );
INVX2TS U4744 ( .A(n3001), .Y(intadd_0_B_18_) );
CMPR32X2TS U4745 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[18]), .B(n3002),
.C(n4762), .CO(n2994), .S(n3003) );
INVX2TS U4746 ( .A(n3003), .Y(intadd_0_A_18_) );
INVX2TS U4747 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[13]), .Y(n4825) );
INVX2TS U4748 ( .A(n3004), .Y(intadd_0_B_14_) );
INVX2TS U4749 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[14]), .Y(n4820) );
INVX2TS U4750 ( .A(n3005), .Y(intadd_0_A_14_) );
CMPR32X2TS U4751 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[14]), .B(n4820),
.C(n4774), .CO(n3006), .S(n3005) );
INVX2TS U4752 ( .A(n3006), .Y(intadd_0_B_15_) );
INVX2TS U4753 ( .A(FPMULT_Sgf_operation_EVEN1_Q_right[15]), .Y(n4815) );
INVX2TS U4754 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[15]), .Y(n3008) );
INVX2TS U4755 ( .A(n3007), .Y(intadd_0_A_15_) );
CMPR32X2TS U4756 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[15]), .B(n4815),
.C(n3008), .CO(n3009), .S(n3007) );
INVX2TS U4757 ( .A(n3009), .Y(intadd_0_B_16_) );
CMPR32X2TS U4758 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[16]), .B(n4809),
.C(n4769), .CO(n2998), .S(n3010) );
INVX2TS U4759 ( .A(n3010), .Y(intadd_0_A_16_) );
INVX2TS U4760 ( .A(FPMULT_Sgf_operation_Result[5]), .Y(n4837) );
INVX2TS U4761 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(n3037) );
INVX2TS U4762 ( .A(n3011), .Y(intadd_0_B_6_) );
INVX2TS U4763 ( .A(FPMULT_Sgf_operation_Result[6]), .Y(n4836) );
INVX2TS U4764 ( .A(n3012), .Y(intadd_0_A_6_) );
CMPR32X2TS U4765 ( .A(n4836), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[6]),
.C(n3013), .CO(n3014), .S(n3012) );
INVX2TS U4766 ( .A(n3014), .Y(intadd_0_B_7_) );
INVX2TS U4767 ( .A(FPMULT_Sgf_operation_Result[7]), .Y(n4835) );
INVX2TS U4768 ( .A(n3015), .Y(intadd_0_A_7_) );
CMPR32X2TS U4769 ( .A(n4835), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[7]),
.C(n4786), .CO(n3016), .S(n3015) );
INVX2TS U4770 ( .A(n3016), .Y(intadd_0_B_8_) );
INVX2TS U4771 ( .A(FPMULT_Sgf_operation_Result[8]), .Y(n4834) );
INVX2TS U4772 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .Y(n3018) );
INVX2TS U4773 ( .A(n3017), .Y(intadd_0_A_8_) );
CMPR32X2TS U4774 ( .A(n4834), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[8]),
.C(n3018), .CO(n3019), .S(n3017) );
INVX2TS U4775 ( .A(n3019), .Y(intadd_0_B_9_) );
INVX2TS U4776 ( .A(FPMULT_Sgf_operation_Result[9]), .Y(n4833) );
INVX2TS U4777 ( .A(n3020), .Y(intadd_0_A_9_) );
CMPR32X2TS U4778 ( .A(n4833), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[9]),
.C(n3021), .CO(n3022), .S(n3020) );
INVX2TS U4779 ( .A(n3022), .Y(intadd_0_B_10_) );
INVX2TS U4780 ( .A(FPMULT_Sgf_operation_Result[10]), .Y(n4832) );
INVX2TS U4781 ( .A(n3023), .Y(intadd_0_A_10_) );
CMPR32X2TS U4782 ( .A(n4832), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[10]),
.C(n3024), .CO(n3025), .S(n3023) );
INVX2TS U4783 ( .A(n3025), .Y(intadd_0_B_11_) );
INVX2TS U4784 ( .A(FPMULT_Sgf_operation_Result[11]), .Y(n4831) );
INVX2TS U4785 ( .A(n3026), .Y(intadd_0_A_11_) );
CMPR32X2TS U4786 ( .A(n4831), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[11]),
.C(n4781), .CO(n3027), .S(n3026) );
INVX2TS U4787 ( .A(n3027), .Y(intadd_0_B_12_) );
INVX2TS U4788 ( .A(n3028), .Y(intadd_0_A_12_) );
CMPR32X2TS U4789 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[12]), .B(n4828),
.C(n3029), .CO(n3030), .S(n3028) );
INVX2TS U4790 ( .A(n3030), .Y(intadd_0_B_13_) );
CMPR32X2TS U4791 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[13]), .B(n4825),
.C(n3031), .CO(n3004), .S(n3032) );
INVX2TS U4792 ( .A(n3032), .Y(intadd_0_A_13_) );
INVX2TS U4793 ( .A(FPMULT_Sgf_operation_Result[3]), .Y(n4839) );
INVX2TS U4794 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(n4794) );
INVX2TS U4795 ( .A(n3033), .Y(intadd_0_B_4_) );
INVX2TS U4796 ( .A(FPMULT_Sgf_operation_Result[4]), .Y(n4838) );
INVX2TS U4797 ( .A(n3034), .Y(intadd_0_A_4_) );
CMPR32X2TS U4798 ( .A(n4838), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[4]),
.C(n3035), .CO(n3036), .S(n3034) );
INVX2TS U4799 ( .A(n3036), .Y(intadd_0_B_5_) );
CMPR32X2TS U4800 ( .A(n4837), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[5]),
.C(n3037), .CO(n3011), .S(n3038) );
INVX2TS U4801 ( .A(n3038), .Y(intadd_0_A_5_) );
INVX2TS U4802 ( .A(FPMULT_Sgf_operation_Result[2]), .Y(n4841) );
INVX2TS U4803 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(n3041) );
INVX2TS U4804 ( .A(n3039), .Y(intadd_0_B_3_) );
CMPR32X2TS U4805 ( .A(n4839), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[3]),
.C(n4794), .CO(n3033), .S(n3040) );
INVX2TS U4806 ( .A(n3040), .Y(intadd_0_A_3_) );
INVX2TS U4807 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[0]), .Y(intadd_0_B_0_) );
CMPR32X2TS U4808 ( .A(n4841), .B(FPMULT_Sgf_operation_EVEN1_Q_middle[2]),
.C(n3041), .CO(n3039), .S(n3042) );
INVX2TS U4809 ( .A(n3042), .Y(intadd_0_B_2_) );
BUFX3TS U4810 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n3963) );
BUFX3TS U4811 ( .A(n3043), .Y(n3470) );
BUFX3TS U4812 ( .A(n4746), .Y(n4713) );
AOI22X1TS U4813 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(
FPMULT_FS_Module_state_reg[1]), .B0(n3045), .B1(n3044), .Y(n3046) );
NOR2X1TS U4814 ( .A(n3092), .B(n3961), .Y(n3075) );
INVX2TS U4815 ( .A(n3079), .Y(n3111) );
BUFX3TS U4816 ( .A(n3111), .Y(n3108) );
NOR2X2TS U4817 ( .A(n3961), .B(n3048), .Y(n3058) );
AOI22X1TS U4818 ( .A0(n3108), .A1(FPMULT_Add_result[10]), .B0(n3058), .B1(
FPMULT_Add_result[11]), .Y(n3052) );
INVX2TS U4819 ( .A(n3092), .Y(n3114) );
INVX2TS U4820 ( .A(n3049), .Y(n3093) );
BUFX3TS U4821 ( .A(n3093), .Y(n3112) );
AOI22X1TS U4822 ( .A0(n3114), .A1(n3050), .B0(
FPMULT_Sgf_normalized_result[10]), .B1(n3112), .Y(n3051) );
AOI22X1TS U4823 ( .A0(n3108), .A1(FPMULT_Add_result[12]), .B0(n3058), .B1(
FPMULT_Add_result[13]), .Y(n3055) );
NOR2BX1TS U4824 ( .AN(FPMULT_P_Sgf[35]), .B(n4767), .Y(n3053) );
BUFX3TS U4825 ( .A(n3093), .Y(n3120) );
AOI22X1TS U4826 ( .A0(n3114), .A1(n3053), .B0(
FPMULT_Sgf_normalized_result[12]), .B1(n3120), .Y(n3054) );
AOI22X1TS U4827 ( .A0(n2269), .A1(FPMULT_P_Sgf[29]), .B0(n3058), .B1(
FPMULT_Add_result[7]), .Y(n3057) );
AOI22X1TS U4828 ( .A0(n3108), .A1(FPMULT_Add_result[6]), .B0(
FPMULT_Sgf_normalized_result[6]), .B1(n3112), .Y(n3056) );
NOR2X1TS U4829 ( .A(FPMULT_P_Sgf[41]), .B(n4767), .Y(n4765) );
AOI21X1TS U4830 ( .A0(n3114), .A1(FPMULT_P_Sgf[42]), .B0(n2269), .Y(n3061)
);
INVX2TS U4831 ( .A(n3058), .Y(n3107) );
INVX2TS U4832 ( .A(n3107), .Y(n3076) );
AOI22X1TS U4833 ( .A0(n3076), .A1(FPMULT_Add_result[19]), .B0(
FPMULT_Sgf_normalized_result[18]), .B1(n3120), .Y(n3060) );
BUFX3TS U4834 ( .A(n3111), .Y(n3121) );
NAND2X1TS U4835 ( .A(n3121), .B(FPMULT_Add_result[18]), .Y(n3059) );
AOI22X1TS U4836 ( .A0(n3121), .A1(FPMULT_Add_result[13]), .B0(n3076), .B1(
FPMULT_Add_result[14]), .Y(n3064) );
AOI22X1TS U4837 ( .A0(n3111), .A1(FPMULT_Add_result[22]), .B0(n3076), .B1(
FPMULT_Add_result[23]), .Y(n3067) );
NOR2BX1TS U4838 ( .AN(FPMULT_P_Sgf[45]), .B(n4767), .Y(n3065) );
AOI22X1TS U4839 ( .A0(n3114), .A1(n3065), .B0(
FPMULT_Sgf_normalized_result[22]), .B1(n3112), .Y(n3066) );
AOI22X1TS U4840 ( .A0(n2270), .A1(FPMULT_P_Sgf[27]), .B0(n3076), .B1(
FPMULT_Add_result[5]), .Y(n3069) );
AOI22X1TS U4841 ( .A0(n3108), .A1(FPMULT_Add_result[4]), .B0(
FPMULT_Sgf_normalized_result[4]), .B1(n3112), .Y(n3068) );
AOI22X1TS U4842 ( .A0(n2269), .A1(FPMULT_P_Sgf[32]), .B0(n3076), .B1(
FPMULT_Add_result[10]), .Y(n3071) );
AOI22X1TS U4843 ( .A0(n3121), .A1(FPMULT_Add_result[9]), .B0(
FPMULT_Sgf_normalized_result[9]), .B1(n3120), .Y(n3070) );
AOI22X1TS U4844 ( .A0(n3108), .A1(FPMULT_Add_result[8]), .B0(n3076), .B1(
FPMULT_Add_result[9]), .Y(n3074) );
NOR2BX1TS U4845 ( .AN(FPMULT_P_Sgf[31]), .B(n4767), .Y(n3072) );
AOI22X1TS U4846 ( .A0(n3114), .A1(n3072), .B0(
FPMULT_Sgf_normalized_result[8]), .B1(n3112), .Y(n3073) );
AOI22X1TS U4847 ( .A0(FPMULT_P_Sgf[41]), .A1(n3075), .B0(FPMULT_P_Sgf[40]),
.B1(n2269), .Y(n3078) );
AOI22X1TS U4848 ( .A0(n3076), .A1(FPMULT_Add_result[18]), .B0(
FPMULT_Sgf_normalized_result[17]), .B1(n3112), .Y(n3077) );
AOI21X1TS U4849 ( .A0(operation[1]), .A1(ack_operation), .B0(n4500), .Y(
n4487) );
INVX2TS U4850 ( .A(n3107), .Y(n3104) );
AOI22X1TS U4851 ( .A0(n2270), .A1(FPMULT_P_Sgf[23]), .B0(n3104), .B1(
FPMULT_Add_result[1]), .Y(n3082) );
AOI22X1TS U4852 ( .A0(n3108), .A1(FPMULT_Add_result[0]), .B0(
FPMULT_Sgf_normalized_result[0]), .B1(n3112), .Y(n3081) );
AOI22X1TS U4853 ( .A0(n2270), .A1(FPMULT_P_Sgf[24]), .B0(n3104), .B1(
FPMULT_Add_result[2]), .Y(n3084) );
AOI22X1TS U4854 ( .A0(n3121), .A1(FPMULT_Add_result[1]), .B0(
FPMULT_Sgf_normalized_result[1]), .B1(n3120), .Y(n3083) );
AOI22X1TS U4855 ( .A0(n3108), .A1(FPMULT_Add_result[15]), .B0(n3104), .B1(
FPMULT_Add_result[16]), .Y(n3087) );
NOR2BX1TS U4856 ( .AN(FPMULT_P_Sgf[38]), .B(n4767), .Y(n3085) );
AOI22X1TS U4857 ( .A0(n3114), .A1(n3085), .B0(
FPMULT_Sgf_normalized_result[15]), .B1(n3112), .Y(n3086) );
AOI22X1TS U4858 ( .A0(n3108), .A1(FPMULT_Add_result[14]), .B0(n3104), .B1(
FPMULT_Add_result[15]), .Y(n3090) );
AOI22X1TS U4859 ( .A0(n3121), .A1(FPMULT_Add_result[11]), .B0(n3104), .B1(
FPMULT_Add_result[12]), .Y(n3095) );
AOI22X1TS U4860 ( .A0(n3111), .A1(FPMULT_Add_result[20]), .B0(n3104), .B1(
FPMULT_Add_result[21]), .Y(n3098) );
NOR2BX1TS U4861 ( .AN(FPMULT_P_Sgf[43]), .B(n4767), .Y(n3096) );
AOI22X1TS U4862 ( .A0(n3114), .A1(n3096), .B0(
FPMULT_Sgf_normalized_result[20]), .B1(n3120), .Y(n3097) );
AOI22X1TS U4863 ( .A0(n2270), .A1(FPMULT_P_Sgf[42]), .B0(n3104), .B1(
FPMULT_Add_result[20]), .Y(n3100) );
AOI22X1TS U4864 ( .A0(n3121), .A1(FPMULT_Add_result[19]), .B0(
FPMULT_Sgf_normalized_result[19]), .B1(n3120), .Y(n3099) );
AOI22X1TS U4865 ( .A0(n3121), .A1(FPMULT_Add_result[7]), .B0(n3104), .B1(
FPMULT_Add_result[8]), .Y(n3103) );
AOI22X1TS U4866 ( .A0(n3114), .A1(n3101), .B0(
FPMULT_Sgf_normalized_result[7]), .B1(n3120), .Y(n3102) );
AOI22X1TS U4867 ( .A0(n2269), .A1(FPMULT_P_Sgf[39]), .B0(
FPMULT_Add_result[17]), .B1(n3104), .Y(n3106) );
AOI22X1TS U4868 ( .A0(n3121), .A1(FPMULT_Add_result[16]), .B0(
FPMULT_Sgf_normalized_result[16]), .B1(n3120), .Y(n3105) );
INVX2TS U4869 ( .A(n3107), .Y(n3119) );
AOI22X1TS U4870 ( .A0(n2269), .A1(FPMULT_P_Sgf[25]), .B0(n3119), .B1(
FPMULT_Add_result[3]), .Y(n3110) );
AOI22X1TS U4871 ( .A0(n3108), .A1(FPMULT_Add_result[2]), .B0(
FPMULT_Sgf_normalized_result[2]), .B1(n3112), .Y(n3109) );
AOI22X1TS U4872 ( .A0(n3111), .A1(FPMULT_Add_result[21]), .B0(n3119), .B1(
FPMULT_Add_result[22]), .Y(n3116) );
NOR2BX1TS U4873 ( .AN(FPMULT_P_Sgf[44]), .B(n4767), .Y(n3113) );
AOI22X1TS U4874 ( .A0(n3114), .A1(n3113), .B0(
FPMULT_Sgf_normalized_result[21]), .B1(n3112), .Y(n3115) );
AOI22X1TS U4875 ( .A0(n2270), .A1(FPMULT_P_Sgf[26]), .B0(n3119), .B1(
FPMULT_Add_result[4]), .Y(n3118) );
AOI22X1TS U4876 ( .A0(n3121), .A1(FPMULT_Add_result[3]), .B0(
FPMULT_Sgf_normalized_result[3]), .B1(n3120), .Y(n3117) );
AOI22X1TS U4877 ( .A0(n2270), .A1(FPMULT_P_Sgf[28]), .B0(n3119), .B1(
FPMULT_Add_result[6]), .Y(n3123) );
AOI22X1TS U4878 ( .A0(n3121), .A1(FPMULT_Add_result[5]), .B0(
FPMULT_Sgf_normalized_result[5]), .B1(n3120), .Y(n3122) );
AOI21X1TS U4879 ( .A0(n5087), .A1(n5001), .B0(n3125), .Y(n3213) );
INVX2TS U4880 ( .A(n3138), .Y(n3127) );
OAI31X1TS U4881 ( .A0(n3127), .A1(n3209), .A2(n5017), .B0(n3126), .Y(n3128)
);
AOI32X1TS U4882 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n3392), .A2(
n5003), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n3691), .Y(n3131)
);
NAND2X1TS U4883 ( .A(n3472), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n3132)
);
NAND4BX1TS U4884 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(n3135), .D(n3134), .Y(
n4488) );
NAND3BX1TS U4885 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n3136), .Y(n4491) );
BUFX3TS U4886 ( .A(n4527), .Y(n4532) );
AOI32X1TS U4887 ( .A0(n4531), .A1(operation[0]), .A2(operation[1]), .B0(
FPSENCOS_d_ff1_operation_out), .B1(n4532), .Y(n3137) );
INVX2TS U4888 ( .A(n3137), .Y(n2081) );
NAND2X1TS U4889 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(n3140), .Y(n3210) );
INVX2TS U4890 ( .A(n3210), .Y(n3142) );
OAI31X1TS U4891 ( .A0(n3143), .A1(n3142), .A2(FPADDSUB_Raw_mant_NRM_SWR[0]),
.B0(n3141), .Y(n3146) );
NAND2X1TS U4892 ( .A(n3472), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n3144)
);
BUFX3TS U4893 ( .A(n3147), .Y(n4499) );
OR2X2TS U4894 ( .A(n4485), .B(operation[2]), .Y(n3148) );
INVX2TS U4895 ( .A(n3148), .Y(n3150) );
AOI22X1TS U4896 ( .A0(cordic_result[1]), .A1(n3150), .B0(n4693), .B1(
mult_result[1]), .Y(n3149) );
OAI21XLTS U4897 ( .A0(n4499), .A1(n4966), .B0(n3149), .Y(op_result[1]) );
AOI22X1TS U4898 ( .A0(n3183), .A1(cordic_result[0]), .B0(n3189), .B1(
mult_result[0]), .Y(n3151) );
INVX2TS U4899 ( .A(result_add_subt[4]), .Y(n4883) );
INVX2TS U4900 ( .A(n2593), .Y(n3185) );
AOI22X1TS U4901 ( .A0(n3190), .A1(cordic_result[4]), .B0(n3182), .B1(
mult_result[4]), .Y(n3152) );
OAI21XLTS U4902 ( .A0(n4499), .A1(n4883), .B0(n3152), .Y(op_result[4]) );
AOI22X1TS U4903 ( .A0(n3190), .A1(cordic_result[8]), .B0(n3182), .B1(
mult_result[8]), .Y(n3153) );
OAI21XLTS U4904 ( .A0(n4499), .A1(n4893), .B0(n3153), .Y(op_result[8]) );
INVX2TS U4905 ( .A(n3148), .Y(n3190) );
INVX2TS U4906 ( .A(n2593), .Y(n3189) );
AOI22X1TS U4907 ( .A0(cordic_result[29]), .A1(n3186), .B0(n3189), .B1(
mult_result[29]), .Y(n3154) );
OAI21XLTS U4908 ( .A0(n3147), .A1(n4671), .B0(n3154), .Y(op_result[29]) );
INVX2TS U4909 ( .A(result_add_subt[3]), .Y(n4954) );
AOI22X1TS U4910 ( .A0(n3190), .A1(cordic_result[3]), .B0(n3189), .B1(
mult_result[3]), .Y(n3155) );
OAI21XLTS U4911 ( .A0(n4499), .A1(n4954), .B0(n3155), .Y(op_result[3]) );
AOI22X1TS U4912 ( .A0(cordic_result[30]), .A1(n3186), .B0(n4693), .B1(
mult_result[30]), .Y(n3156) );
OAI21XLTS U4913 ( .A0(n3147), .A1(n4677), .B0(n3156), .Y(op_result[30]) );
INVX2TS U4914 ( .A(result_add_subt[5]), .Y(n4974) );
AOI22X1TS U4915 ( .A0(n3190), .A1(cordic_result[5]), .B0(n4693), .B1(
mult_result[5]), .Y(n3157) );
OAI21XLTS U4916 ( .A0(n4499), .A1(n4974), .B0(n3157), .Y(op_result[5]) );
INVX2TS U4917 ( .A(result_add_subt[2]), .Y(n4957) );
AOI22X1TS U4918 ( .A0(n3190), .A1(cordic_result[2]), .B0(n3182), .B1(
mult_result[2]), .Y(n3158) );
INVX2TS U4919 ( .A(result_add_subt[7]), .Y(n4960) );
AOI22X1TS U4920 ( .A0(n3190), .A1(cordic_result[7]), .B0(n3189), .B1(
mult_result[7]), .Y(n3159) );
OAI21XLTS U4921 ( .A0(n4499), .A1(n4960), .B0(n3159), .Y(op_result[7]) );
INVX1TS U4922 ( .A(result_add_subt[28]), .Y(n4668) );
AOI22X1TS U4923 ( .A0(n3150), .A1(cordic_result[28]), .B0(n3182), .B1(
mult_result[28]), .Y(n3160) );
OAI21XLTS U4924 ( .A0(n3147), .A1(n4668), .B0(n3160), .Y(op_result[28]) );
AOI22X1TS U4925 ( .A0(cordic_result[31]), .A1(n3183), .B0(n3189), .B1(
mult_result[31]), .Y(n3161) );
OAI21XLTS U4926 ( .A0(n4499), .A1(n4566), .B0(n3161), .Y(op_result[31]) );
OAI21X2TS U4927 ( .A0(n4991), .A1(n5054), .B0(n4602), .Y(n4520) );
AOI22X1TS U4928 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n4603), .B0(n3197),
.B1(n3162), .Y(n3163) );
BUFX3TS U4929 ( .A(n3147), .Y(n3192) );
INVX2TS U4930 ( .A(result_add_subt[18]), .Y(n4870) );
INVX2TS U4931 ( .A(n3148), .Y(n3183) );
AOI22X1TS U4932 ( .A0(n3186), .A1(cordic_result[18]), .B0(n3185), .B1(
mult_result[18]), .Y(n3165) );
OAI21XLTS U4933 ( .A0(n3192), .A1(n4870), .B0(n3165), .Y(op_result[18]) );
BUFX3TS U4934 ( .A(n3147), .Y(n3188) );
AOI22X1TS U4935 ( .A0(n3150), .A1(cordic_result[16]), .B0(n3185), .B1(
mult_result[16]), .Y(n3166) );
OAI21XLTS U4936 ( .A0(n3188), .A1(n4890), .B0(n3166), .Y(op_result[16]) );
INVX1TS U4937 ( .A(result_add_subt[24]), .Y(n4661) );
AOI22X1TS U4938 ( .A0(cordic_result[24]), .A1(n3183), .B0(n4693), .B1(
mult_result[24]), .Y(n3167) );
OAI21XLTS U4939 ( .A0(n3192), .A1(n4661), .B0(n3167), .Y(op_result[24]) );
INVX2TS U4940 ( .A(result_add_subt[15]), .Y(n4868) );
AOI22X1TS U4941 ( .A0(n3183), .A1(cordic_result[15]), .B0(n3185), .B1(
mult_result[15]), .Y(n3168) );
OAI21XLTS U4942 ( .A0(n3188), .A1(n4868), .B0(n3168), .Y(op_result[15]) );
INVX1TS U4943 ( .A(result_add_subt[27]), .Y(n4665) );
AOI22X1TS U4944 ( .A0(cordic_result[27]), .A1(n3186), .B0(n3182), .B1(
mult_result[27]), .Y(n3169) );
OAI21XLTS U4945 ( .A0(n3192), .A1(n4665), .B0(n3169), .Y(op_result[27]) );
INVX2TS U4946 ( .A(result_add_subt[19]), .Y(n4875) );
AOI22X1TS U4947 ( .A0(n3186), .A1(cordic_result[19]), .B0(n3185), .B1(
mult_result[19]), .Y(n3170) );
OAI21XLTS U4948 ( .A0(n3192), .A1(n4875), .B0(n3170), .Y(op_result[19]) );
INVX1TS U4949 ( .A(result_add_subt[25]), .Y(n4662) );
AOI22X1TS U4950 ( .A0(cordic_result[25]), .A1(n3150), .B0(n3189), .B1(
mult_result[25]), .Y(n3171) );
OAI21XLTS U4951 ( .A0(n3192), .A1(n4662), .B0(n3171), .Y(op_result[25]) );
INVX2TS U4952 ( .A(result_add_subt[20]), .Y(n4877) );
AOI22X1TS U4953 ( .A0(n3150), .A1(cordic_result[20]), .B0(n3185), .B1(
mult_result[20]), .Y(n3172) );
OAI21XLTS U4954 ( .A0(n3192), .A1(n4877), .B0(n3172), .Y(op_result[20]) );
AOI22X1TS U4955 ( .A0(n3183), .A1(cordic_result[13]), .B0(n3185), .B1(
mult_result[13]), .Y(n3173) );
OAI21XLTS U4956 ( .A0(n3188), .A1(n4888), .B0(n3173), .Y(op_result[13]) );
AOI22X1TS U4957 ( .A0(n3186), .A1(cordic_result[14]), .B0(n3185), .B1(
mult_result[14]), .Y(n3174) );
OAI21XLTS U4958 ( .A0(n3188), .A1(n4898), .B0(n3174), .Y(op_result[14]) );
INVX1TS U4959 ( .A(result_add_subt[23]), .Y(n4660) );
AOI22X1TS U4960 ( .A0(cordic_result[23]), .A1(n3183), .B0(n4693), .B1(
mult_result[23]), .Y(n3175) );
OAI21XLTS U4961 ( .A0(n3192), .A1(n4660), .B0(n3175), .Y(op_result[23]) );
INVX2TS U4962 ( .A(result_add_subt[22]), .Y(n4864) );
AOI22X1TS U4963 ( .A0(n3186), .A1(cordic_result[22]), .B0(n3182), .B1(
mult_result[22]), .Y(n3176) );
OAI21XLTS U4964 ( .A0(n3192), .A1(n4864), .B0(n3176), .Y(op_result[22]) );
INVX2TS U4965 ( .A(result_add_subt[21]), .Y(n4873) );
AOI22X1TS U4966 ( .A0(n3150), .A1(cordic_result[21]), .B0(n3185), .B1(
mult_result[21]), .Y(n3177) );
OAI21XLTS U4967 ( .A0(n3192), .A1(n4873), .B0(n3177), .Y(op_result[21]) );
AOI22X1TS U4968 ( .A0(n3190), .A1(cordic_result[11]), .B0(n4693), .B1(
mult_result[11]), .Y(n3178) );
OAI21XLTS U4969 ( .A0(n3188), .A1(n4896), .B0(n3178), .Y(op_result[11]) );
AOI22X1TS U4970 ( .A0(n3190), .A1(cordic_result[10]), .B0(n3189), .B1(
mult_result[10]), .Y(n3179) );
OAI21XLTS U4971 ( .A0(n3188), .A1(n4900), .B0(n3179), .Y(op_result[10]) );
INVX2TS U4972 ( .A(result_add_subt[6]), .Y(n4886) );
AOI22X1TS U4973 ( .A0(n3150), .A1(cordic_result[6]), .B0(n4693), .B1(
mult_result[6]), .Y(n3180) );
OAI21XLTS U4974 ( .A0(n3188), .A1(n4886), .B0(n3180), .Y(op_result[6]) );
AOI22X1TS U4975 ( .A0(n3183), .A1(cordic_result[12]), .B0(n3185), .B1(
mult_result[12]), .Y(n3181) );
OAI21XLTS U4976 ( .A0(n3188), .A1(n4903), .B0(n3181), .Y(op_result[12]) );
INVX2TS U4977 ( .A(result_add_subt[17]), .Y(n4879) );
AOI22X1TS U4978 ( .A0(n3186), .A1(cordic_result[17]), .B0(n4693), .B1(
mult_result[17]), .Y(n3184) );
INVX2TS U4979 ( .A(result_add_subt[9]), .Y(n4969) );
AOI22X1TS U4980 ( .A0(n3183), .A1(cordic_result[9]), .B0(n3182), .B1(
mult_result[9]), .Y(n3187) );
OAI21XLTS U4981 ( .A0(n3188), .A1(n4969), .B0(n3187), .Y(op_result[9]) );
INVX1TS U4982 ( .A(result_add_subt[26]), .Y(n4663) );
AOI22X1TS U4983 ( .A0(cordic_result[26]), .A1(n3150), .B0(n3189), .B1(
mult_result[26]), .Y(n3191) );
OAI21XLTS U4984 ( .A0(n3192), .A1(n4663), .B0(n3191), .Y(op_result[26]) );
AOI2BB2XLTS U4985 ( .B0(FPSENCOS_d_ff3_sign_out), .B1(n4988), .A0N(n4988),
.A1N(FPSENCOS_d_ff3_sign_out), .Y(n3194) );
AOI22X1TS U4986 ( .A0(operation[0]), .A1(n4680), .B0(FPADDSUB_intAS), .B1(
n4679), .Y(n3193) );
INVX2TS U4987 ( .A(n3219), .Y(n3200) );
NOR2X1TS U4988 ( .A(n4553), .B(n3200), .Y(n4519) );
NAND2X1TS U4989 ( .A(FPSENCOS_d_ff3_LUT_out[0]), .B(n4611), .Y(n3195) );
NAND2X1TS U4990 ( .A(n3197), .B(n5054), .Y(n3202) );
AOI22X1TS U4991 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n4603), .B0(
FPSENCOS_cont_iter_out[1]), .B1(n4518), .Y(n3198) );
BUFX3TS U4992 ( .A(n4567), .Y(n4604) );
INVX2TS U4993 ( .A(n4520), .Y(n4522) );
NAND2X1TS U4994 ( .A(n5006), .B(n4522), .Y(n3234) );
NAND2X1TS U4995 ( .A(n3200), .B(n4522), .Y(n3237) );
NAND2X1TS U4996 ( .A(n4492), .B(n4518), .Y(n3204) );
NAND2X1TS U4997 ( .A(FPSENCOS_d_ff3_LUT_out[2]), .B(n4611), .Y(n3201) );
NAND2X1TS U4998 ( .A(FPSENCOS_cont_iter_out[3]), .B(n4518), .Y(n3206) );
NOR2X2TS U4999 ( .A(FPSENCOS_cont_iter_out[1]), .B(n4553), .Y(n3218) );
NOR2BX1TS U5000 ( .AN(n3208), .B(n3207), .Y(n3214) );
OAI22X1TS U5001 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(n3210), .B0(n5082),
.B1(n3209), .Y(n3211) );
NOR4X1TS U5002 ( .A(n3214), .B(n3213), .C(n3212), .D(n3211), .Y(n3217) );
NAND2X1TS U5003 ( .A(n4507), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n3216)
);
INVX2TS U5004 ( .A(n4578), .Y(n4564) );
NAND2X4TS U5005 ( .A(n4608), .B(n4521), .Y(n3220) );
BUFX3TS U5006 ( .A(n4547), .Y(n4607) );
INVX2TS U5007 ( .A(n3221), .Y(n1764) );
INVX2TS U5008 ( .A(n3222), .Y(n1763) );
INVX2TS U5009 ( .A(n3223), .Y(n1761) );
INVX2TS U5010 ( .A(n3224), .Y(n1760) );
INVX2TS U5011 ( .A(n3225), .Y(n1762) );
INVX2TS U5012 ( .A(n3226), .Y(n1755) );
INVX2TS U5013 ( .A(n3227), .Y(n1754) );
INVX2TS U5014 ( .A(n3228), .Y(n1758) );
INVX2TS U5015 ( .A(n3229), .Y(n1756) );
INVX2TS U5016 ( .A(n3230), .Y(n1759) );
INVX2TS U5017 ( .A(n3232), .Y(n1757) );
INVX2TS U5018 ( .A(n3239), .Y(n1765) );
INVX2TS U5019 ( .A(FPSENCOS_d_ff2_Y[19]), .Y(n4592) );
BUFX3TS U5020 ( .A(n4680), .Y(n4654) );
BUFX3TS U5021 ( .A(n4654), .Y(n3261) );
BUFX3TS U5022 ( .A(n3279), .Y(n3351) );
AOI22X1TS U5023 ( .A0(Data_1[19]), .A1(n3261), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n3351), .Y(n3244) );
INVX2TS U5024 ( .A(n3240), .Y(n4493) );
NOR2X4TS U5025 ( .A(n3241), .B(n4493), .Y(n3242) );
BUFX3TS U5026 ( .A(n4649), .Y(n3353) );
BUFX3TS U5027 ( .A(n3266), .Y(n3352) );
AOI22X1TS U5028 ( .A0(n3353), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n3352), .B1(
FPSENCOS_d_ff2_X[19]), .Y(n3243) );
INVX2TS U5029 ( .A(FPSENCOS_d_ff2_Y[14]), .Y(n4586) );
BUFX3TS U5030 ( .A(n3319), .Y(n3322) );
AOI22X1TS U5031 ( .A0(Data_1[14]), .A1(n3261), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n3322), .Y(n3246) );
BUFX3TS U5032 ( .A(n4649), .Y(n3325) );
BUFX3TS U5033 ( .A(n3266), .Y(n3324) );
AOI22X1TS U5034 ( .A0(n3325), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n3324), .B1(
FPSENCOS_d_ff2_X[14]), .Y(n3245) );
BUFX3TS U5035 ( .A(n3297), .Y(n3329) );
INVX2TS U5036 ( .A(FPSENCOS_d_ff2_Y[10]), .Y(n4581) );
AOI22X1TS U5037 ( .A0(Data_1[10]), .A1(n3261), .B0(FPADDSUB_intDX_EWSW[10]),
.B1(n3322), .Y(n3248) );
AOI22X1TS U5038 ( .A0(n3325), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n3324), .B1(
FPSENCOS_d_ff2_X[10]), .Y(n3247) );
INVX2TS U5039 ( .A(FPSENCOS_d_ff2_Y[12]), .Y(n4583) );
AOI22X1TS U5040 ( .A0(Data_1[12]), .A1(n3261), .B0(FPADDSUB_intDX_EWSW[12]),
.B1(n3322), .Y(n3250) );
AOI22X1TS U5041 ( .A0(n3353), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n3324), .B1(
FPSENCOS_d_ff2_X[12]), .Y(n3249) );
INVX2TS U5042 ( .A(FPSENCOS_d_ff2_Y[16]), .Y(n4587) );
AOI22X1TS U5043 ( .A0(Data_1[16]), .A1(n3261), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n3351), .Y(n3252) );
AOI22X1TS U5044 ( .A0(n3325), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n3352), .B1(
FPSENCOS_d_ff2_X[16]), .Y(n3251) );
INVX2TS U5045 ( .A(FPSENCOS_d_ff2_Y[11]), .Y(n4582) );
AOI22X1TS U5046 ( .A0(Data_1[11]), .A1(n3261), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n3322), .Y(n3254) );
AOI22X1TS U5047 ( .A0(n3325), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n3324), .B1(
FPSENCOS_d_ff2_X[11]), .Y(n3253) );
INVX2TS U5048 ( .A(FPSENCOS_d_ff2_Y[17]), .Y(n4588) );
AOI22X1TS U5049 ( .A0(Data_1[17]), .A1(n3261), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n3351), .Y(n3256) );
AOI22X1TS U5050 ( .A0(n3353), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n3352), .B1(
FPSENCOS_d_ff2_X[17]), .Y(n3255) );
INVX2TS U5051 ( .A(FPSENCOS_d_ff2_Y[18]), .Y(n4590) );
AOI22X1TS U5052 ( .A0(Data_1[18]), .A1(n3261), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n3351), .Y(n3258) );
AOI22X1TS U5053 ( .A0(n3353), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n3352), .B1(
FPSENCOS_d_ff2_X[18]), .Y(n3257) );
INVX2TS U5054 ( .A(FPSENCOS_d_ff2_Y[13]), .Y(n4585) );
AOI22X1TS U5055 ( .A0(Data_1[13]), .A1(n3261), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n3322), .Y(n3260) );
AOI22X1TS U5056 ( .A0(n3325), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n3324), .B1(
FPSENCOS_d_ff2_X[13]), .Y(n3259) );
AOI22X1TS U5057 ( .A0(Data_1[15]), .A1(n3261), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n3351), .Y(n3263) );
AOI22X1TS U5058 ( .A0(n3325), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n3324), .B1(
FPSENCOS_d_ff2_X[15]), .Y(n3262) );
AOI22X1TS U5059 ( .A0(Data_2[26]), .A1(n3298), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n4679), .Y(n3265) );
BUFX3TS U5060 ( .A(n4649), .Y(n3292) );
AOI22X1TS U5061 ( .A0(n3292), .A1(FPSENCOS_d_ff3_LUT_out[26]), .B0(n4641),
.B1(FPSENCOS_d_ff3_sh_y_out[26]), .Y(n3264) );
AOI22X1TS U5062 ( .A0(Data_2[25]), .A1(n3298), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n4679), .Y(n3268) );
BUFX3TS U5063 ( .A(n3266), .Y(n3316) );
AOI22X1TS U5064 ( .A0(n3292), .A1(FPSENCOS_d_ff3_LUT_out[25]), .B0(n3316),
.B1(FPSENCOS_d_ff3_sh_y_out[25]), .Y(n3267) );
INVX2TS U5065 ( .A(FPSENCOS_d_ff3_sh_x_out[23]), .Y(n4555) );
AOI22X1TS U5066 ( .A0(Data_2[23]), .A1(n3298), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n4679), .Y(n3270) );
AOI22X1TS U5067 ( .A0(n3292), .A1(FPSENCOS_d_ff3_LUT_out[23]), .B0(n3316),
.B1(FPSENCOS_d_ff3_sh_y_out[23]), .Y(n3269) );
AOI22X1TS U5068 ( .A0(Data_2[24]), .A1(n3298), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n4679), .Y(n3272) );
AOI22X1TS U5069 ( .A0(n3292), .A1(FPSENCOS_d_ff3_LUT_out[24]), .B0(n4641),
.B1(FPSENCOS_d_ff3_sh_y_out[24]), .Y(n3271) );
AOI22X1TS U5070 ( .A0(Data_2[21]), .A1(n3298), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n4645), .Y(n3274) );
AOI22X1TS U5071 ( .A0(n3292), .A1(FPSENCOS_d_ff3_LUT_out[21]), .B0(n3316),
.B1(FPSENCOS_d_ff3_sh_y_out[21]), .Y(n3273) );
BUFX3TS U5072 ( .A(n3319), .Y(n4619) );
AOI22X1TS U5073 ( .A0(Data_2[12]), .A1(n4633), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n4619), .Y(n3276) );
AOI22X1TS U5074 ( .A0(n3292), .A1(FPSENCOS_d_ff3_LUT_out[12]), .B0(n3316),
.B1(FPSENCOS_d_ff3_sh_y_out[12]), .Y(n3275) );
OAI211X1TS U5075 ( .A0(n3329), .A1(n2391), .B0(n3276), .C0(n3275), .Y(n1832)
);
BUFX3TS U5076 ( .A(n3297), .Y(n3311) );
AOI22X1TS U5077 ( .A0(Data_2[8]), .A1(n4633), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n4619), .Y(n3278) );
AOI22X1TS U5078 ( .A0(n3292), .A1(FPSENCOS_d_ff3_LUT_out[8]), .B0(n3316),
.B1(FPSENCOS_d_ff3_sh_y_out[8]), .Y(n3277) );
OAI211X1TS U5079 ( .A0(n3311), .A1(n2388), .B0(n3278), .C0(n3277), .Y(n1836)
);
BUFX3TS U5080 ( .A(n3279), .Y(n3340) );
AOI22X1TS U5081 ( .A0(Data_2[1]), .A1(n4616), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n3340), .Y(n3281) );
BUFX3TS U5082 ( .A(n4649), .Y(n3342) );
BUFX3TS U5083 ( .A(n3266), .Y(n3341) );
AOI22X1TS U5084 ( .A0(n3342), .A1(FPSENCOS_d_ff3_LUT_out[1]), .B0(n3341),
.B1(FPSENCOS_d_ff3_sh_y_out[1]), .Y(n3280) );
OAI211X1TS U5085 ( .A0(n3311), .A1(n2396), .B0(n3281), .C0(n3280), .Y(n1843)
);
AOI22X1TS U5086 ( .A0(Data_2[2]), .A1(n4616), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n3340), .Y(n3283) );
AOI22X1TS U5087 ( .A0(n3342), .A1(FPSENCOS_d_ff3_LUT_out[2]), .B0(n3341),
.B1(FPSENCOS_d_ff3_sh_y_out[2]), .Y(n3282) );
OAI211X1TS U5088 ( .A0(n3311), .A1(n2403), .B0(n3283), .C0(n3282), .Y(n1842)
);
AOI22X1TS U5089 ( .A0(Data_2[4]), .A1(n4616), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n4619), .Y(n3285) );
AOI22X1TS U5090 ( .A0(n3342), .A1(FPSENCOS_d_ff3_LUT_out[4]), .B0(n3316),
.B1(FPSENCOS_d_ff3_sh_y_out[4]), .Y(n3284) );
OAI211X1TS U5091 ( .A0(n3311), .A1(n2397), .B0(n3285), .C0(n3284), .Y(n1840)
);
AOI22X1TS U5092 ( .A0(Data_2[9]), .A1(n4633), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n4619), .Y(n3287) );
AOI22X1TS U5093 ( .A0(n3292), .A1(FPSENCOS_d_ff3_LUT_out[9]), .B0(n3316),
.B1(FPSENCOS_d_ff3_sh_y_out[9]), .Y(n3286) );
OAI211X1TS U5094 ( .A0(n3311), .A1(n2398), .B0(n3287), .C0(n3286), .Y(n1835)
);
AOI22X1TS U5095 ( .A0(Data_2[6]), .A1(n4616), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n4619), .Y(n3289) );
AOI22X1TS U5096 ( .A0(n3292), .A1(FPSENCOS_d_ff3_LUT_out[6]), .B0(n3316),
.B1(FPSENCOS_d_ff3_sh_y_out[6]), .Y(n3288) );
OAI211X1TS U5097 ( .A0(n3311), .A1(n2399), .B0(n3289), .C0(n3288), .Y(n1838)
);
AOI22X1TS U5098 ( .A0(Data_2[0]), .A1(n4616), .B0(FPADDSUB_intDY_EWSW[0]),
.B1(n3340), .Y(n3291) );
AOI22X1TS U5099 ( .A0(n3342), .A1(FPSENCOS_d_ff3_LUT_out[0]), .B0(n3341),
.B1(FPSENCOS_d_ff3_sh_y_out[0]), .Y(n3290) );
AOI22X1TS U5100 ( .A0(n3292), .A1(FPSENCOS_d_ff3_LUT_out[10]), .B0(n3316),
.B1(FPSENCOS_d_ff3_sh_y_out[10]), .Y(n3293) );
AOI22X1TS U5101 ( .A0(Data_1[30]), .A1(n4616), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n3340), .Y(n3296) );
AOI22X1TS U5102 ( .A0(n3342), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n3341), .B1(
FPSENCOS_d_ff2_X[30]), .Y(n3295) );
BUFX3TS U5103 ( .A(n3297), .Y(n3328) );
BUFX3TS U5104 ( .A(n3298), .Y(n3323) );
AOI22X1TS U5105 ( .A0(Data_1[8]), .A1(n3323), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n3322), .Y(n3300) );
AOI22X1TS U5106 ( .A0(n3325), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n3324), .B1(
FPSENCOS_d_ff2_X[8]), .Y(n3299) );
INVX2TS U5107 ( .A(FPSENCOS_d_ff2_Y[7]), .Y(n4576) );
AOI22X1TS U5108 ( .A0(Data_1[7]), .A1(n3323), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n3322), .Y(n3302) );
AOI22X1TS U5109 ( .A0(n3325), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n3324), .B1(
FPSENCOS_d_ff2_X[7]), .Y(n3301) );
INVX2TS U5110 ( .A(FPSENCOS_d_ff2_Y[2]), .Y(n4570) );
AOI22X1TS U5111 ( .A0(Data_1[2]), .A1(n3323), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n3319), .Y(n3304) );
AOI22X1TS U5112 ( .A0(n3242), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n2602), .B1(
FPSENCOS_d_ff2_X[2]), .Y(n3303) );
INVX2TS U5113 ( .A(FPSENCOS_d_ff2_Y[5]), .Y(n4574) );
AOI22X1TS U5114 ( .A0(Data_1[5]), .A1(n3323), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n3322), .Y(n3306) );
AOI22X1TS U5115 ( .A0(n3325), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n3266), .B1(
FPSENCOS_d_ff2_X[5]), .Y(n3305) );
INVX2TS U5116 ( .A(FPSENCOS_d_ff2_Y[3]), .Y(n4572) );
AOI22X1TS U5117 ( .A0(Data_1[3]), .A1(n3323), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n3319), .Y(n3308) );
AOI22X1TS U5118 ( .A0(n3242), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n3266), .B1(
FPSENCOS_d_ff2_X[3]), .Y(n3307) );
INVX2TS U5119 ( .A(FPSENCOS_d_ff2_Y[31]), .Y(n4610) );
AOI22X1TS U5120 ( .A0(Data_1[31]), .A1(n4616), .B0(FPADDSUB_intDX_EWSW[31]),
.B1(n3340), .Y(n3310) );
AOI22X1TS U5121 ( .A0(n3342), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n3341), .B1(
FPSENCOS_d_ff2_X[31]), .Y(n3309) );
INVX2TS U5122 ( .A(FPSENCOS_d_ff2_Y[6]), .Y(n4575) );
AOI22X1TS U5123 ( .A0(Data_1[6]), .A1(n3323), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n3322), .Y(n3313) );
AOI22X1TS U5124 ( .A0(n3242), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n3324), .B1(
FPSENCOS_d_ff2_X[6]), .Y(n3312) );
INVX2TS U5125 ( .A(FPSENCOS_d_ff2_Y[0]), .Y(n4568) );
AOI22X1TS U5126 ( .A0(n3323), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n3319), .Y(n3315) );
AOI22X1TS U5127 ( .A0(FPSENCOS_d_ff2_Z[0]), .A1(n3242), .B0(n3341), .B1(
FPSENCOS_d_ff2_X[0]), .Y(n3314) );
AOI22X1TS U5128 ( .A0(Data_1[1]), .A1(n3323), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n3319), .Y(n3318) );
AOI22X1TS U5129 ( .A0(n3242), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n3316), .B1(
FPSENCOS_d_ff2_X[1]), .Y(n3317) );
INVX2TS U5130 ( .A(FPSENCOS_d_ff2_Y[4]), .Y(n4573) );
AOI22X1TS U5131 ( .A0(Data_1[4]), .A1(n3323), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n3319), .Y(n3321) );
AOI22X1TS U5132 ( .A0(n3242), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n2602), .B1(
FPSENCOS_d_ff2_X[4]), .Y(n3320) );
INVX2TS U5133 ( .A(FPSENCOS_d_ff2_Y[9]), .Y(n4579) );
AOI22X1TS U5134 ( .A0(Data_1[9]), .A1(n3323), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n3322), .Y(n3327) );
AOI22X1TS U5135 ( .A0(n3325), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n3324), .B1(
FPSENCOS_d_ff2_X[9]), .Y(n3326) );
BUFX3TS U5136 ( .A(n3329), .Y(n3356) );
AOI22X1TS U5137 ( .A0(Data_1[28]), .A1(n2601), .B0(FPADDSUB_intDX_EWSW[28]),
.B1(n3340), .Y(n3331) );
AOI22X1TS U5138 ( .A0(n3342), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n3341), .B1(
FPSENCOS_d_ff2_X[28]), .Y(n3330) );
AOI22X1TS U5139 ( .A0(Data_1[26]), .A1(n4680), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n3340), .Y(n3333) );
AOI22X1TS U5140 ( .A0(n3342), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n3341), .B1(
FPSENCOS_d_ff2_X[26]), .Y(n3332) );
AOI22X1TS U5141 ( .A0(Data_1[27]), .A1(n4654), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n3340), .Y(n3335) );
AOI22X1TS U5142 ( .A0(n3342), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n3341), .B1(
FPSENCOS_d_ff2_X[27]), .Y(n3334) );
AOI22X1TS U5143 ( .A0(Data_1[24]), .A1(n4654), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n3351), .Y(n3337) );
AOI22X1TS U5144 ( .A0(n3353), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n3352), .B1(
FPSENCOS_d_ff2_X[24]), .Y(n3336) );
AOI22X1TS U5145 ( .A0(Data_1[25]), .A1(n4654), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n3340), .Y(n3339) );
AOI22X1TS U5146 ( .A0(n3353), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n3352), .B1(
FPSENCOS_d_ff2_X[25]), .Y(n3338) );
AOI22X1TS U5147 ( .A0(Data_1[29]), .A1(n4654), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n3340), .Y(n3344) );
AOI22X1TS U5148 ( .A0(n3342), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n3341), .B1(
FPSENCOS_d_ff2_X[29]), .Y(n3343) );
AOI22X1TS U5149 ( .A0(Data_1[23]), .A1(n4654), .B0(FPADDSUB_intDX_EWSW[23]),
.B1(n3351), .Y(n3346) );
AOI22X1TS U5150 ( .A0(n3353), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n3352), .B1(
FPSENCOS_d_ff2_X[23]), .Y(n3345) );
INVX2TS U5151 ( .A(FPSENCOS_d_ff2_Y[22]), .Y(n4596) );
AOI22X1TS U5152 ( .A0(Data_1[22]), .A1(n4654), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n3351), .Y(n3348) );
AOI22X1TS U5153 ( .A0(n3353), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n3352), .B1(
FPSENCOS_d_ff2_X[22]), .Y(n3347) );
INVX2TS U5154 ( .A(FPSENCOS_d_ff2_Y[21]), .Y(n4594) );
AOI22X1TS U5155 ( .A0(Data_1[21]), .A1(n4654), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n3351), .Y(n3350) );
AOI22X1TS U5156 ( .A0(n3353), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n3352), .B1(
FPSENCOS_d_ff2_X[21]), .Y(n3349) );
INVX2TS U5157 ( .A(FPSENCOS_d_ff2_Y[20]), .Y(n4593) );
AOI22X1TS U5158 ( .A0(Data_1[20]), .A1(n4654), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n3351), .Y(n3355) );
AOI22X1TS U5159 ( .A0(n3353), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n3352), .B1(
FPSENCOS_d_ff2_X[20]), .Y(n3354) );
INVX2TS U5160 ( .A(n4861), .Y(n3357) );
INVX2TS U5161 ( .A(n3359), .Y(n1747) );
INVX2TS U5162 ( .A(n3360), .Y(n1745) );
INVX2TS U5163 ( .A(n3361), .Y(n1739) );
INVX2TS U5164 ( .A(n3362), .Y(n1744) );
INVX2TS U5165 ( .A(n3363), .Y(n1737) );
INVX2TS U5166 ( .A(n3364), .Y(n1743) );
INVX2TS U5167 ( .A(n3365), .Y(n1751) );
INVX2TS U5168 ( .A(n3366), .Y(n1742) );
INVX2TS U5169 ( .A(n3367), .Y(n1736) );
INVX2TS U5170 ( .A(n3368), .Y(n1750) );
INVX2TS U5171 ( .A(n3369), .Y(n1749) );
INVX2TS U5172 ( .A(n3370), .Y(n1740) );
INVX2TS U5173 ( .A(n3372), .Y(n1741) );
INVX2TS U5174 ( .A(n3373), .Y(n1746) );
INVX2TS U5175 ( .A(n3375), .Y(n1748) );
INVX2TS U5176 ( .A(n3376), .Y(n1735) );
INVX2TS U5177 ( .A(n3377), .Y(n1752) );
INVX2TS U5178 ( .A(n3380), .Y(n1753) );
INVX2TS U5179 ( .A(n3382), .Y(n1734) );
INVX2TS U5180 ( .A(n3385), .Y(n1738) );
NOR2X4TS U5181 ( .A(n3386), .B(n4512), .Y(n3397) );
XNOR2X1TS U5182 ( .A(n2223), .B(FPSENCOS_d_ff1_operation_out), .Y(n3387) );
CLKXOR2X2TS U5183 ( .A(n4687), .B(n3387), .Y(n4686) );
INVX2TS U5184 ( .A(n4686), .Y(n4685) );
NOR2X4TS U5185 ( .A(n3503), .B(n4685), .Y(n3398) );
NOR2X4TS U5186 ( .A(n3503), .B(n4686), .Y(n3399) );
INVX2TS U5187 ( .A(n3388), .Y(n1697) );
NAND2X1TS U5188 ( .A(n3471), .B(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n3391) );
NAND2X1TS U5189 ( .A(n3703), .B(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n3390) );
NAND2X1TS U5190 ( .A(n4507), .B(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n3389) );
INVX2TS U5191 ( .A(n3392), .Y(n3709) );
NOR2X2TS U5192 ( .A(n3701), .B(n4658), .Y(n3395) );
OA22X1TS U5193 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n3479), .B0(n2538),
.B1(FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n3677) );
AOI22X1TS U5194 ( .A0(n3709), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n2335),
.B1(n3677), .Y(n3396) );
INVX2TS U5195 ( .A(n3400), .Y(n1726) );
INVX2TS U5196 ( .A(n3401), .Y(n1722) );
INVX2TS U5197 ( .A(n3402), .Y(n1718) );
INVX2TS U5198 ( .A(n3403), .Y(n1723) );
INVX2TS U5199 ( .A(n3404), .Y(n1719) );
INVX2TS U5200 ( .A(n3405), .Y(n1721) );
INVX2TS U5201 ( .A(n3406), .Y(n1727) );
INVX2TS U5202 ( .A(n3407), .Y(n1724) );
INVX2TS U5203 ( .A(n3408), .Y(n1720) );
INVX2TS U5204 ( .A(n3409), .Y(n1725) );
INVX2TS U5205 ( .A(n3410), .Y(n1709) );
INVX2TS U5206 ( .A(n3413), .Y(n1705) );
INVX2TS U5207 ( .A(n3414), .Y(n1706) );
INVX2TS U5208 ( .A(n3415), .Y(n1708) );
INVX2TS U5209 ( .A(n3416), .Y(n1712) );
NAND2X1TS U5210 ( .A(n3703), .B(n5096), .Y(n3419) );
NAND2X1TS U5211 ( .A(n3471), .B(n5071), .Y(n3418) );
NAND2X1TS U5212 ( .A(n3703), .B(n5097), .Y(n3422) );
NAND2X1TS U5213 ( .A(n3471), .B(n5084), .Y(n3421) );
INVX2TS U5214 ( .A(n3436), .Y(n3636) );
AOI22X1TS U5215 ( .A0(n3709), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n2336),
.B1(n3636), .Y(n3430) );
NAND2X1TS U5216 ( .A(n3470), .B(n5124), .Y(n3425) );
NAND2X1TS U5217 ( .A(n3471), .B(n5039), .Y(n3424) );
INVX2TS U5218 ( .A(n3478), .Y(n3439) );
NAND2X1TS U5219 ( .A(n3467), .B(n3442), .Y(n3428) );
NAND2X1TS U5220 ( .A(n3703), .B(n5040), .Y(n3427) );
NAND2X1TS U5221 ( .A(n3472), .B(n5099), .Y(n3426) );
AOI22X1TS U5222 ( .A0(n2328), .A1(n3439), .B0(n2334), .B1(n3698), .Y(n3429)
);
AOI22X1TS U5223 ( .A0(n3709), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n2336),
.B1(n3439), .Y(n3435) );
NAND2X1TS U5224 ( .A(n3467), .B(n5082), .Y(n3433) );
NAND2X1TS U5225 ( .A(n3470), .B(n5098), .Y(n3432) );
NAND2X1TS U5226 ( .A(n3472), .B(n5100), .Y(n3431) );
AOI22X1TS U5227 ( .A0(n2329), .A1(n3698), .B0(n3697), .B1(n2334), .Y(n3434)
);
OAI211X1TS U5228 ( .A0(n2272), .A1(n3436), .B0(n3435), .C0(n3434), .Y(n1807)
);
INVX2TS U5229 ( .A(n3438), .Y(n3668) );
AOI22X1TS U5230 ( .A0(n3753), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n2336),
.B1(n3668), .Y(n3441) );
AOI22X1TS U5231 ( .A0(n2328), .A1(n3636), .B0(n2196), .B1(n3439), .Y(n3440)
);
AOI22X1TS U5232 ( .A0(n3691), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n2335),
.B1(n3693), .Y(n3448) );
NAND2X1TS U5233 ( .A(n3703), .B(n3442), .Y(n3445) );
NAND2X1TS U5234 ( .A(n3467), .B(n5040), .Y(n3444) );
NAND2X1TS U5235 ( .A(n3472), .B(n5101), .Y(n3443) );
AOI22X1TS U5236 ( .A0(n3471), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[3]), .B1(n4507), .Y(n3446) );
AOI22X1TS U5237 ( .A0(n2330), .A1(n3690), .B0(n2334), .B1(n3692), .Y(n3447)
);
NAND2X1TS U5238 ( .A(n3470), .B(n5071), .Y(n3452) );
NAND2X1TS U5239 ( .A(n3471), .B(n5096), .Y(n3451) );
INVX2TS U5240 ( .A(n3462), .Y(n3671) );
AOI22X1TS U5241 ( .A0(n3691), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n2335),
.B1(n3671), .Y(n3458) );
NAND2X1TS U5242 ( .A(n3703), .B(n5038), .Y(n3455) );
NAND2X1TS U5243 ( .A(n3471), .B(n5055), .Y(n3454) );
INVX2TS U5244 ( .A(n3650), .Y(n3633) );
OAI22X1TS U5245 ( .A0(n3702), .A1(FPADDSUB_Raw_mant_NRM_SWR[16]), .B0(n3963),
.B1(FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n3456) );
AOI22X1TS U5246 ( .A0(n2330), .A1(n3633), .B0(n2196), .B1(n3755), .Y(n3457)
);
AOI22X1TS U5247 ( .A0(n3753), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n2335),
.B1(n3633), .Y(n3461) );
OAI22X1TS U5248 ( .A0(n3702), .A1(FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(n3963),
.B1(FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n3459) );
AOI22X1TS U5249 ( .A0(n2329), .A1(n3755), .B0(n2196), .B1(n3752), .Y(n3460)
);
OAI22X1TS U5250 ( .A0(n3646), .A1(FPADDSUB_DmP_mant_SHT1_SW[12]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .B1(n3479), .Y(n3463) );
AOI22X1TS U5251 ( .A0(n3753), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n2336),
.B1(n3686), .Y(n3469) );
NAND2X1TS U5252 ( .A(n3646), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(n3465) );
OAI21X1TS U5253 ( .A0(n3646), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n3479),
.Y(n3464) );
AOI22X1TS U5254 ( .A0(n3646), .A1(FPADDSUB_Raw_mant_NRM_SWR[16]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[14]), .B1(n5003), .Y(n3466) );
AOI22X1TS U5255 ( .A0(n2328), .A1(n3684), .B0(n2334), .B1(n3685), .Y(n3468)
);
AOI22X1TS U5256 ( .A0(n3709), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n2335),
.B1(n3698), .Y(n3477) );
NAND2X1TS U5257 ( .A(n3470), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3475) );
NAND2X1TS U5258 ( .A(n3471), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n3474) );
NAND2X1TS U5259 ( .A(n3472), .B(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n3473) );
AOI22X1TS U5260 ( .A0(n3697), .A1(n2329), .B0(n2334), .B1(n3704), .Y(n3476)
);
OAI222X4TS U5261 ( .A0(n2538), .A1(FPADDSUB_Raw_mant_NRM_SWR[13]), .B0(n3479), .B1(FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(FPADDSUB_DmP_mant_SHT1_SW[10]), .C1(
n3646), .Y(n3758) );
INVX2TS U5262 ( .A(n3480), .Y(n3674) );
AOI22X1TS U5263 ( .A0(n3753), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n2335),
.B1(n3674), .Y(n3482) );
AOI22X1TS U5264 ( .A0(n2328), .A1(n3686), .B0(n2196), .B1(n3684), .Y(n3481)
);
INVX2TS U5265 ( .A(n3483), .Y(n1703) );
INVX2TS U5266 ( .A(n3484), .Y(n1716) );
INVX2TS U5267 ( .A(n3485), .Y(n1702) );
INVX2TS U5268 ( .A(n3486), .Y(n1714) );
INVX2TS U5269 ( .A(n3487), .Y(n1717) );
INVX2TS U5270 ( .A(n3488), .Y(n1701) );
INVX2TS U5271 ( .A(n3489), .Y(n1698) );
INVX2TS U5272 ( .A(n3490), .Y(n1710) );
INVX2TS U5273 ( .A(n3491), .Y(n1707) );
INVX2TS U5274 ( .A(n3492), .Y(n1699) );
INVX2TS U5275 ( .A(n3493), .Y(n1713) );
INVX2TS U5276 ( .A(n3494), .Y(n1700) );
INVX2TS U5277 ( .A(n3496), .Y(n1715) );
INVX2TS U5278 ( .A(n3500), .Y(n1711) );
INVX2TS U5279 ( .A(n3504), .Y(n1704) );
INVX2TS U5280 ( .A(FPADDSUB_intDX_EWSW[1]), .Y(n4906) );
AOI21X1TS U5281 ( .A0(n2394), .A1(n2419), .B0(n2418), .Y(n3508) );
NAND2X1TS U5282 ( .A(FPADDSUB_intDY_EWSW[2]), .B(n3505), .Y(n3506) );
NAND2X1TS U5283 ( .A(FPADDSUB_intDY_EWSW[3]), .B(n3510), .Y(n3513) );
NAND2X1TS U5284 ( .A(FPADDSUB_intDY_EWSW[4]), .B(n3511), .Y(n3512) );
NAND2X1TS U5285 ( .A(FPADDSUB_intDY_EWSW[5]), .B(n3521), .Y(n3525) );
NAND2X1TS U5286 ( .A(FPADDSUB_intDY_EWSW[6]), .B(n3522), .Y(n3523) );
NAND2X1TS U5287 ( .A(FPADDSUB_intDY_EWSW[7]), .B(n3526), .Y(n3530) );
NAND2X1TS U5288 ( .A(FPADDSUB_intDY_EWSW[9]), .B(n3544), .Y(n3547) );
NAND2X1TS U5289 ( .A(FPADDSUB_intDY_EWSW[10]), .B(n3545), .Y(n3546) );
NAND2X1TS U5290 ( .A(FPADDSUB_intDY_EWSW[11]), .B(n3549), .Y(n3552) );
NAND2X1TS U5291 ( .A(FPADDSUB_intDY_EWSW[12]), .B(n3550), .Y(n3551) );
NAND2X1TS U5292 ( .A(FPADDSUB_intDY_EWSW[13]), .B(n3557), .Y(n3560) );
NAND2X1TS U5293 ( .A(FPADDSUB_intDY_EWSW[14]), .B(n3558), .Y(n3559) );
NAND2X1TS U5294 ( .A(FPADDSUB_intDY_EWSW[16]), .B(n3563), .Y(n3564) );
NAND2X1TS U5295 ( .A(FPADDSUB_intDY_EWSW[19]), .B(n3586), .Y(n3587) );
NAND2X1TS U5296 ( .A(FPADDSUB_intDY_EWSW[20]), .B(n3590), .Y(n3593) );
NAND2X1TS U5297 ( .A(FPADDSUB_intDY_EWSW[21]), .B(n3591), .Y(n3592) );
NAND2X1TS U5298 ( .A(FPADDSUB_intDY_EWSW[22]), .B(n3598), .Y(n3601) );
NAND2X1TS U5299 ( .A(FPADDSUB_intDY_EWSW[24]), .B(n3602), .Y(n3606) );
BUFX3TS U5300 ( .A(n3733), .Y(n4904) );
BUFX3TS U5301 ( .A(n3733), .Y(n3744) );
AOI22X1TS U5302 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3661), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n3744), .Y(n3627) );
BUFX3TS U5303 ( .A(n5073), .Y(n4944) );
BUFX3TS U5304 ( .A(n4944), .Y(n4948) );
BUFX3TS U5305 ( .A(n4948), .Y(n3748) );
AOI22X1TS U5306 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n3661), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n3748), .Y(n3628) );
AOI22X1TS U5307 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n3656), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n3748), .Y(n3629) );
AOI22X1TS U5308 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n3656), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n3748), .Y(n3630) );
AOI22X1TS U5309 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n3661), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n3744), .Y(n3631) );
BUFX3TS U5310 ( .A(n4948), .Y(n3712) );
AOI22X1TS U5311 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n3656), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n3712), .Y(n3632) );
INVX2TS U5312 ( .A(n3395), .Y(n3705) );
AOI22X1TS U5313 ( .A0(n3691), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n2334),
.B1(n3633), .Y(n3635) );
AOI22X1TS U5314 ( .A0(n2197), .A1(n3692), .B0(n2330), .B1(n3671), .Y(n3634)
);
AOI22X1TS U5315 ( .A0(n3753), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n2196),
.B1(n3636), .Y(n3638) );
AOI22X1TS U5316 ( .A0(n2197), .A1(n3685), .B0(n2330), .B1(n3668), .Y(n3637)
);
AOI22X1TS U5317 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n3661), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n3744), .Y(n3639) );
AOI22X1TS U5318 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n3661), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n3744), .Y(n3640) );
AOI22X1TS U5319 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n3656), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n3712), .Y(n3641) );
AOI22X1TS U5320 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n3661), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n3748), .Y(n3642) );
AOI22X1TS U5321 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n3656), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n3712), .Y(n3643) );
AOI22X1TS U5322 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n3656), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n3748), .Y(n3644) );
AOI22X1TS U5323 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3661), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n3748), .Y(n3645) );
AOI22X1TS U5324 ( .A0(n3691), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n2330),
.B1(n3752), .Y(n3649) );
OAI22X1TS U5325 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[14]), .A1(n3702), .B0(n3646),
.B1(FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n3647) );
AOI22X1TS U5326 ( .A0(n3395), .A1(n3755), .B0(n2334), .B1(n3754), .Y(n3648)
);
AOI22X1TS U5327 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3656), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n3712), .Y(n3651) );
AOI22X1TS U5328 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n3661), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n4944), .Y(n3652) );
AOI22X1TS U5329 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n3656), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n3748), .Y(n3653) );
AOI22X1TS U5330 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3656), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n3748), .Y(n3654) );
AOI22X1TS U5331 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3656), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n3712), .Y(n3657) );
AOI22X1TS U5332 ( .A0(n3753), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n2196),
.B1(n3686), .Y(n3659) );
AOI22X1TS U5333 ( .A0(n2256), .A1(n3754), .B0(n2330), .B1(n3674), .Y(n3658)
);
AOI22X1TS U5334 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n3661), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n4948), .Y(n3660) );
AOI22X1TS U5335 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3661), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n3744), .Y(n3662) );
AOI22X1TS U5336 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n3764), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n3712), .Y(n3663) );
AOI22X1TS U5337 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n3764), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n3712), .Y(n3664) );
AOI22X1TS U5338 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n3764), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n3712), .Y(n3665) );
AOI22X1TS U5339 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n3764), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n3712), .Y(n3666) );
AOI22X1TS U5340 ( .A0(n3753), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n2335),
.B1(n3685), .Y(n3670) );
AOI22X1TS U5341 ( .A0(n2197), .A1(n3684), .B0(n2196), .B1(n3668), .Y(n3669)
);
AOI22X1TS U5342 ( .A0(n3691), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n2336),
.B1(n3692), .Y(n3673) );
AOI22X1TS U5343 ( .A0(n2197), .A1(n3690), .B0(n2334), .B1(n3671), .Y(n3672)
);
AOI22X1TS U5344 ( .A0(n3753), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n2336),
.B1(n3754), .Y(n3676) );
AOI22X1TS U5345 ( .A0(n2256), .A1(n3752), .B0(n2334), .B1(n3674), .Y(n3675)
);
AOI22X1TS U5346 ( .A0(n3709), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n2336),
.B1(n3704), .Y(n3679) );
AOI22X1TS U5347 ( .A0(n2197), .A1(n3697), .B0(n2334), .B1(n3677), .Y(n3678)
);
AOI2BB2X1TS U5348 ( .B0(n3709), .B1(FPADDSUB_Data_array_SWR[1]), .A0N(n3680),
.A1N(n3705), .Y(n3682) );
AOI22X1TS U5349 ( .A0(n2329), .A1(n3693), .B0(n2196), .B1(n3690), .Y(n3681)
);
AOI22X1TS U5350 ( .A0(n3753), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n2335),
.B1(n3684), .Y(n3688) );
AOI22X1TS U5351 ( .A0(n2256), .A1(n3686), .B0(n2329), .B1(n3685), .Y(n3687)
);
AOI22X1TS U5352 ( .A0(n3691), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n2336),
.B1(n3690), .Y(n3695) );
AOI22X1TS U5353 ( .A0(n2256), .A1(n3693), .B0(n2329), .B1(n3692), .Y(n3694)
);
AOI22X1TS U5354 ( .A0(n3709), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n2336),
.B1(n3697), .Y(n3700) );
AOI22X1TS U5355 ( .A0(n2256), .A1(n3698), .B0(n2330), .B1(n3704), .Y(n3699)
);
INVX2TS U5356 ( .A(n3704), .Y(n3707) );
OAI22X1TS U5357 ( .A0(n3707), .A1(n2194), .B0(n3706), .B1(n3705), .Y(n3708)
);
AOI21X1TS U5358 ( .A0(n3709), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n3708),
.Y(n3710) );
BUFX3TS U5359 ( .A(n3626), .Y(n3747) );
AOI22X1TS U5360 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n3745), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n3712), .Y(n3713) );
AOI22X1TS U5361 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n3745), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n4904), .Y(n3714) );
AOI22X1TS U5362 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n3745), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n4904), .Y(n3715) );
AOI22X1TS U5363 ( .A0(FPADDSUB_intDY_EWSW[26]), .A1(n3745), .B0(
FPADDSUB_DMP_EXP_EWSW[26]), .B1(n4904), .Y(n3716) );
AOI22X1TS U5364 ( .A0(FPADDSUB_intDY_EWSW[25]), .A1(n3745), .B0(
FPADDSUB_DMP_EXP_EWSW[25]), .B1(n4904), .Y(n3717) );
AOI22X1TS U5365 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3749), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n3744), .Y(n3718) );
AOI22X1TS U5366 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n3745), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n3744), .Y(n3719) );
AOI22X1TS U5367 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n3741), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n4948), .Y(n3720) );
AOI22X1TS U5368 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n3749), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n4944), .Y(n3721) );
AOI22X1TS U5369 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n3749), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n4948), .Y(n3722) );
AOI22X1TS U5370 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n3741), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n3733), .Y(n3723) );
AOI22X1TS U5371 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n3749), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n3744), .Y(n3724) );
AOI22X1TS U5372 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n3741), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n3733), .Y(n3725) );
AOI22X1TS U5373 ( .A0(FPADDSUB_intDY_EWSW[24]), .A1(n3745), .B0(
FPADDSUB_DMP_EXP_EWSW[24]), .B1(n4904), .Y(n3726) );
AOI22X1TS U5374 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n3745), .B0(
FPADDSUB_DMP_EXP_EWSW[27]), .B1(n4904), .Y(n3727) );
AOI22X1TS U5375 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n3749), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n4948), .Y(n3728) );
AOI22X1TS U5376 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n3745), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n3744), .Y(n3729) );
AOI22X1TS U5377 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n3741), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n3733), .Y(n3730) );
AOI22X1TS U5378 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n3749), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n4948), .Y(n3731) );
AOI22X1TS U5379 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n3741), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n4948), .Y(n3732) );
AOI22X1TS U5380 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n3741), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n3733), .Y(n3734) );
AOI22X1TS U5381 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n3749), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n3748), .Y(n3735) );
AOI22X1TS U5382 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3749), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n4944), .Y(n3736) );
AOI22X1TS U5383 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n3749), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n4944), .Y(n3737) );
AOI22X1TS U5384 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3741), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n3733), .Y(n3738) );
AOI22X1TS U5385 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n3741), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n5073), .Y(n3739) );
AOI22X1TS U5386 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3741), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n4944), .Y(n3740) );
AOI22X1TS U5387 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3741), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n5073), .Y(n3742) );
AOI22X1TS U5388 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3745), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n3744), .Y(n3746) );
AOI22X1TS U5389 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n3749), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n3748), .Y(n3750) );
AOI22X1TS U5390 ( .A0(n3753), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n2335),
.B1(n3752), .Y(n3757) );
AOI22X1TS U5391 ( .A0(n2256), .A1(n3755), .B0(n2329), .B1(n3754), .Y(n3756)
);
INVX2TS U5392 ( .A(n3760), .Y(n1415) );
INVX2TS U5393 ( .A(n3761), .Y(n1418) );
AOI222X1TS U5394 ( .A0(n3764), .A1(FPADDSUB_intDY_EWSW[24]), .B0(
FPADDSUB_DmP_EXP_EWSW[24]), .B1(n4944), .C0(FPADDSUB_intDX_EWSW[24]),
.C1(n3765), .Y(n3762) );
INVX2TS U5395 ( .A(n3762), .Y(n1417) );
INVX2TS U5396 ( .A(n3763), .Y(n1416) );
INVX2TS U5397 ( .A(n3766), .Y(n1466) );
OAI22X1TS U5398 ( .A0(FPMULT_Op_MY[15]), .A1(n4322), .B0(n2207), .B1(n3857),
.Y(n3767) );
AOI21X1TS U5399 ( .A0(n3864), .A1(n2207), .B0(n3767), .Y(intadd_3_CI) );
AOI21X1TS U5400 ( .A0(FPMULT_Op_MY[19]), .A1(n3864), .B0(n3768), .Y(n4287)
);
NOR2X1TS U5401 ( .A(FPMULT_Sgf_operation_EVEN1_Q_middle[1]), .B(n4691), .Y(
intadd_0_A_2_) );
AOI22X1TS U5402 ( .A0(n2199), .A1(n5176), .B0(n2350), .B1(n5031), .Y(n3805)
);
AO22XLTS U5403 ( .A0(n3854), .A1(n3805), .B0(n3806), .B1(n3770), .Y(
mult_x_219_n174) );
NOR2X1TS U5404 ( .A(n5044), .B(n4335), .Y(n3845) );
AOI21X1TS U5405 ( .A0(n5044), .A1(n4698), .B0(n3845), .Y(n3877) );
AOI21X1TS U5406 ( .A0(n5048), .A1(n4698), .B0(n2232), .Y(n3804) );
AO22XLTS U5407 ( .A0(n2246), .A1(n3877), .B0(n4377), .B1(n3804), .Y(
mult_x_254_n161) );
AOI22X1TS U5408 ( .A0(FPMULT_Op_MY[2]), .A1(n2311), .B0(n4699), .B1(n5050),
.Y(n3831) );
AO22XLTS U5409 ( .A0(n2356), .A1(n3831), .B0(n4347), .B1(n3771), .Y(
mult_x_254_n180) );
OAI22X1TS U5410 ( .A0(n3775), .A1(n4280), .B0(n4728), .B1(n3773), .Y(n3774)
);
AOI21X1TS U5411 ( .A0(n3775), .A1(n4728), .B0(n3774), .Y(n3776) );
XOR2XLTS U5412 ( .A(n3776), .B(intadd_3_n1), .Y(
FPMULT_Sgf_operation_EVEN1_left_N23) );
AO22XLTS U5413 ( .A0(n2627), .A1(n3778), .B0(n2628), .B1(n3777), .Y(
mult_x_219_n198) );
OAI22X1TS U5414 ( .A0(intadd_4_SUM_2_), .A1(n3793), .B0(intadd_4_SUM_1_),
.B1(n4447), .Y(n3779) );
AOI21X1TS U5415 ( .A0(intadd_4_SUM_2_), .A1(n2638), .B0(n3779), .Y(n3787) );
AOI22X1TS U5416 ( .A0(n2294), .A1(intadd_4_SUM_0_), .B0(n4409), .B1(n2313),
.Y(n3796) );
AOI22X1TS U5417 ( .A0(n2294), .A1(n4412), .B0(n2249), .B1(n2313), .Y(n3809)
);
AOI22X1TS U5418 ( .A0(n3798), .A1(n3796), .B0(n3809), .B1(n4441), .Y(n3786)
);
XOR2X1TS U5419 ( .A(n3787), .B(n3786), .Y(n3785) );
INVX2TS U5420 ( .A(n3780), .Y(n4429) );
NOR2X1TS U5421 ( .A(n4444), .B(n2250), .Y(n3822) );
AOI211X1TS U5422 ( .A0(n3781), .A1(intadd_4_SUM_0_), .B0(n4412), .C0(n2259),
.Y(n3821) );
AOI22X1TS U5423 ( .A0(intadd_4_SUM_1_), .A1(n2638), .B0(n3782), .B1(n4407),
.Y(n3783) );
OAI21X1TS U5424 ( .A0(intadd_4_SUM_0_), .A1(n2368), .B0(n3783), .Y(n3820) );
NAND3X1TS U5425 ( .A(n3789), .B(n3821), .C(n3820), .Y(n3817) );
OAI21X1TS U5426 ( .A0(n3789), .A1(n3788), .B0(n3817), .Y(n3784) );
NOR2X1TS U5427 ( .A(n3785), .B(n3784), .Y(n3792) );
AO21XLTS U5428 ( .A0(n3785), .A1(n3784), .B0(n3792), .Y(
FPMULT_Sgf_operation_EVEN1_middle_N3) );
NOR2XLTS U5429 ( .A(n3789), .B(n3788), .Y(n3791) );
NAND2X1TS U5430 ( .A(n3816), .B(n3817), .Y(n3790) );
OAI31X1TS U5431 ( .A0(n3792), .A1(n3816), .A2(n3791), .B0(n3790), .Y(n3801)
);
OAI22X1TS U5432 ( .A0(intadd_4_SUM_2_), .A1(n4447), .B0(intadd_4_SUM_3_),
.B1(n3793), .Y(n3794) );
AOI21X1TS U5433 ( .A0(n2638), .A1(intadd_4_SUM_3_), .B0(n3794), .Y(n3813) );
NAND2X1TS U5434 ( .A(n4412), .B(n3795), .Y(n3810) );
AOI22X1TS U5435 ( .A0(n3798), .A1(n3797), .B0(n3796), .B1(n4441), .Y(n3812)
);
INVX2TS U5436 ( .A(n3799), .Y(n3800) );
NAND2X1TS U5437 ( .A(n3800), .B(n3801), .Y(n3818) );
OA21XLTS U5438 ( .A0(n3801), .A1(n3800), .B0(n3818), .Y(
FPMULT_Sgf_operation_EVEN1_middle_N4) );
AOI22X1TS U5439 ( .A0(FPMULT_Op_MY[13]), .A1(n2291), .B0(n2289), .B1(n5021),
.Y(n4270) );
AO22XLTS U5440 ( .A0(n2627), .A1(n3802), .B0(n2628), .B1(n4270), .Y(
mult_x_219_n202) );
AOI22X1TS U5441 ( .A0(FPMULT_Op_MY[15]), .A1(n2325), .B0(n2349), .B1(n5030),
.Y(n3807) );
AO22XLTS U5442 ( .A0(n3854), .A1(n3803), .B0(n3806), .B1(n3807), .Y(
mult_x_219_n172) );
AOI21X1TS U5443 ( .A0(n5042), .A1(n4698), .B0(mult_x_254_n151), .Y(n3856) );
AO22XLTS U5444 ( .A0(n2246), .A1(n3804), .B0(n2646), .B1(n3856), .Y(
mult_x_254_n162) );
AO22XLTS U5445 ( .A0(n3854), .A1(n3807), .B0(n3806), .B1(n3805), .Y(
mult_x_219_n173) );
AOI22X1TS U5446 ( .A0(FPMULT_Op_MX[15]), .A1(n2199), .B0(n5031), .B1(n2308),
.Y(n4265) );
AOI2BB2XLTS U5447 ( .B0(n4268), .B1(n4265), .A0N(n3808), .A1N(n4318), .Y(
intadd_3_B_0_) );
NAND2X1TS U5448 ( .A(n4714), .B(n2248), .Y(intadd_3_A_0_) );
AOI22X1TS U5449 ( .A0(intadd_4_SUM_0_), .A1(n2296), .B0(n2298), .B1(n4409),
.Y(n4426) );
OAI22X1TS U5450 ( .A0(n3809), .A1(n2631), .B0(n4426), .B1(n4428), .Y(n3815)
);
NAND2BX1TS U5451 ( .AN(n2233), .B(n3810), .Y(n4391) );
CMPR32X2TS U5452 ( .A(n3813), .B(n3810), .C(n3812), .CO(n4392), .S(n3799) );
NAND2X1TS U5453 ( .A(n4392), .B(n4391), .Y(n3811) );
OAI31X1TS U5454 ( .A0(n3813), .A1(n3812), .A2(n4391), .B0(n3811), .Y(n3814)
);
NOR2X1TS U5455 ( .A(n3815), .B(n3814), .Y(n4390) );
AO21XLTS U5456 ( .A0(n3815), .A1(n3814), .B0(n4390), .Y(intadd_1_CI) );
NAND2BXLTS U5457 ( .AN(n3817), .B(n3816), .Y(n3819) );
NAND2X1TS U5458 ( .A(n3819), .B(n3818), .Y(intadd_1_A_0_) );
CMPR32X2TS U5459 ( .A(n3822), .B(n3821), .C(n3820), .CO(n3788), .S(
FPMULT_Sgf_operation_EVEN1_middle_N2) );
OAI22X1TS U5460 ( .A0(n2624), .A1(n4432), .B0(n4450), .B1(n2938), .Y(n4452)
);
INVX2TS U5461 ( .A(n4452), .Y(n3826) );
NOR2XLTS U5462 ( .A(n2322), .B(intadd_5_SUM_9_), .Y(n3824) );
AOI32X4TS U5463 ( .A0(intadd_5_SUM_9_), .A1(n2285), .A2(n2322), .B0(n3824),
.B1(n2353), .Y(n4416) );
AOI22X1TS U5464 ( .A0(n2254), .A1(n2353), .B0(n4411), .B1(n4445), .Y(n4393)
);
OAI22X1TS U5465 ( .A0(n4416), .A1(n4393), .B0(n2285), .B1(n4413), .Y(n3825)
);
CMPR32X2TS U5466 ( .A(DP_OP_454J1_123_2743_n35), .B(n3826), .C(n3825), .CO(
intadd_1_B_19_), .S(intadd_1_B_18_) );
OA21XLTS U5467 ( .A0(n3829), .A1(n3828), .B0(n3827), .Y(
FPMULT_Sgf_operation_EVEN1_right_N2) );
AOI21X1TS U5468 ( .A0(n5045), .A1(n4698), .B0(mult_x_254_n63), .Y(n3855) );
AO22XLTS U5469 ( .A0(n2247), .A1(n3855), .B0(n2646), .B1(n3830), .Y(
mult_x_254_n164) );
AOI22X1TS U5470 ( .A0(intadd_4_SUM_2_), .A1(n2321), .B0(n2371), .B1(n4405),
.Y(n3874) );
AOI22X1TS U5471 ( .A0(intadd_4_SUM_1_), .A1(n2321), .B0(n2320), .B1(n4407),
.Y(n3872) );
AO22XLTS U5472 ( .A0(n3876), .A1(n3874), .B0(n2355), .B1(n3872), .Y(
DP_OP_454J1_123_2743_n197) );
AOI22X1TS U5473 ( .A0(FPMULT_Op_MY[3]), .A1(n2312), .B0(n2310), .B1(n5046),
.Y(n3832) );
AO22XLTS U5474 ( .A0(n2356), .A1(n3832), .B0(n4347), .B1(n3831), .Y(
mult_x_254_n179) );
AO22XLTS U5475 ( .A0(n2356), .A1(n3833), .B0(n4347), .B1(n3832), .Y(
mult_x_254_n178) );
CMPR32X2TS U5476 ( .A(n3836), .B(n3835), .C(n3834), .CO(n2877), .S(
FPMULT_Sgf_operation_EVEN1_right_N5) );
AOI22X1TS U5477 ( .A0(intadd_4_SUM_0_), .A1(n2321), .B0(n2371), .B1(n4409),
.Y(n3871) );
AO22XLTS U5478 ( .A0(n3876), .A1(n3871), .B0(n2355), .B1(n3837), .Y(
DP_OP_454J1_123_2743_n199) );
AO22XLTS U5479 ( .A0(n2372), .A1(n3839), .B0(n2355), .B1(n3838), .Y(
DP_OP_454J1_123_2743_n191) );
AOI22X1TS U5480 ( .A0(n2304), .A1(FPMULT_Op_MY[4]), .B0(n5045), .B1(n4704),
.Y(n3869) );
AOI22X1TS U5481 ( .A0(n2303), .A1(FPMULT_Op_MY[3]), .B0(n5046), .B1(n4704),
.Y(n4327) );
AO22XLTS U5482 ( .A0(n4328), .A1(n3869), .B0(n4371), .B1(n4327), .Y(
mult_x_254_n220) );
OAI22X1TS U5483 ( .A0(n5176), .A1(n4304), .B0(n3840), .B1(n4302), .Y(n3841)
);
AOI22X1TS U5484 ( .A0(n2309), .A1(n2207), .B0(n5023), .B1(n4697), .Y(n3866)
);
AOI22X1TS U5485 ( .A0(FPMULT_Op_MX[15]), .A1(FPMULT_Op_MY[15]), .B0(n5030),
.B1(n4697), .Y(n4267) );
AO22XLTS U5486 ( .A0(n4268), .A1(n3866), .B0(n4266), .B1(n4267), .Y(
mult_x_219_n214) );
AOI22X1TS U5487 ( .A0(FPMULT_Op_MY[11]), .A1(FPMULT_Op_MX[11]), .B0(n4698),
.B1(n5028), .Y(n4376) );
NOR2X1TS U5488 ( .A(n5043), .B(n4335), .Y(n4378) );
AOI21X1TS U5489 ( .A0(n5043), .A1(n4335), .B0(n4378), .Y(n3842) );
AO22XLTS U5490 ( .A0(n2247), .A1(n4376), .B0(n2646), .B1(n3842), .Y(
mult_x_254_n157) );
AOI21X1TS U5491 ( .A0(n5041), .A1(n4698), .B0(mult_x_254_n149), .Y(n3873) );
AO22XLTS U5492 ( .A0(n2247), .A1(n3842), .B0(n4377), .B1(n3873), .Y(
mult_x_254_n158) );
AOI22X1TS U5493 ( .A0(FPMULT_Op_MY[11]), .A1(n4699), .B0(n2311), .B1(n5028),
.Y(n4341) );
OAI22X1TS U5494 ( .A0(n2208), .A1(n4341), .B0(n4344), .B1(n3843), .Y(n3844)
);
CMPR32X2TS U5495 ( .A(n2232), .B(n3845), .C(n3844), .CO(mult_x_254_n42), .S(
mult_x_254_n43) );
AO22XLTS U5496 ( .A0(n3848), .A1(n3847), .B0(n4357), .B1(n3846), .Y(
mult_x_254_n194) );
NOR2X1TS U5497 ( .A(n4990), .B(n5170), .Y(n4340) );
AOI21X1TS U5498 ( .A0(FPMULT_Op_MY[11]), .A1(n4993), .B0(mult_x_254_n225),
.Y(n3850) );
AOI22X1TS U5499 ( .A0(n2304), .A1(n5043), .B0(FPMULT_Op_MY[10]), .B1(n4704),
.Y(n4366) );
INVX2TS U5500 ( .A(n4371), .Y(n4368) );
AOI22X1TS U5501 ( .A0(n2303), .A1(n5041), .B0(FPMULT_Op_MY[9]), .B1(n4704),
.Y(n4369) );
OAI22X1TS U5502 ( .A0(n4373), .A1(n4366), .B0(n4368), .B1(n4369), .Y(n3849)
);
CMPR32X2TS U5503 ( .A(n4340), .B(n3850), .C(n3849), .CO(mult_x_254_n98), .S(
mult_x_254_n99) );
AOI22X1TS U5504 ( .A0(FPMULT_Op_MY[9]), .A1(n4701), .B0(n2300), .B1(n5041),
.Y(n4350) );
OAI22X1TS U5505 ( .A0(n4359), .A1(n4350), .B0(n4354), .B1(n3851), .Y(n3852)
);
CMPR32X2TS U5506 ( .A(n4334), .B(n3853), .C(n3852), .CO(mult_x_254_n71), .S(
mult_x_254_n72) );
OAI32X1TS U5507 ( .A0(n2324), .A1(n3854), .A2(n5063), .B0(n4304), .B1(n2350),
.Y(mult_x_219_n164) );
AO22XLTS U5508 ( .A0(n2247), .A1(n3856), .B0(n2646), .B1(n3855), .Y(
mult_x_254_n163) );
INVX2TS U5509 ( .A(n3857), .Y(n3859) );
AOI22X1TS U5510 ( .A0(n2309), .A1(n5024), .B0(n2210), .B1(n2308), .Y(n4316)
);
AOI22X1TS U5511 ( .A0(n2309), .A1(n5026), .B0(FPMULT_Op_MY[21]), .B1(n4697),
.Y(n4319) );
OAI22X1TS U5512 ( .A0(n4320), .A1(n4316), .B0(n4318), .B1(n4319), .Y(n3858)
);
CMPR32X2TS U5513 ( .A(n2283), .B(n3859), .C(n3858), .CO(mult_x_219_n98), .S(
mult_x_219_n99) );
AOI22X1TS U5514 ( .A0(FPMULT_Op_MY[20]), .A1(n2286), .B0(n2319), .B1(n5022),
.Y(n4278) );
INVX2TS U5515 ( .A(n3860), .Y(n4310) );
AOI22X1TS U5516 ( .A0(FPMULT_Op_MY[19]), .A1(n2286), .B0(n2198), .B1(n5027),
.Y(n4307) );
OAI22X1TS U5517 ( .A0(n2266), .A1(n4278), .B0(n4310), .B1(n4307), .Y(n3861)
);
AO22XLTS U5518 ( .A0(n2248), .A1(n3863), .B0(n2628), .B1(n3862), .Y(
mult_x_219_n196) );
AOI21X1TS U5519 ( .A0(n3865), .A1(n5024), .B0(n3864), .Y(n4282) );
AO22XLTS U5520 ( .A0(n4268), .A1(n3867), .B0(n4266), .B1(n3866), .Y(
mult_x_219_n213) );
AOI22X1TS U5521 ( .A0(intadd_4_SUM_3_), .A1(n2322), .B0(n2320), .B1(n4403),
.Y(n3875) );
AO22XLTS U5522 ( .A0(n2372), .A1(n3868), .B0(n2355), .B1(n3875), .Y(
DP_OP_454J1_123_2743_n195) );
AO22XLTS U5523 ( .A0(n4328), .A1(n3870), .B0(n4371), .B1(n3869), .Y(
mult_x_254_n219) );
AO22XLTS U5524 ( .A0(n2372), .A1(n3872), .B0(n2355), .B1(n3871), .Y(
DP_OP_454J1_123_2743_n198) );
AOI21X1TS U5525 ( .A0(n5047), .A1(n4698), .B0(mult_x_254_n37), .Y(n3878) );
AO22XLTS U5526 ( .A0(n2247), .A1(n3873), .B0(n4377), .B1(n3878), .Y(
mult_x_254_n159) );
AO22XLTS U5527 ( .A0(n2372), .A1(n3875), .B0(n2355), .B1(n3874), .Y(
DP_OP_454J1_123_2743_n196) );
AO22XLTS U5528 ( .A0(n2247), .A1(n3878), .B0(n4377), .B1(n3877), .Y(
mult_x_254_n160) );
NAND2X1TS U5529 ( .A(n4989), .B(n4992), .Y(n4695) );
NOR2XLTS U5530 ( .A(n4992), .B(n5052), .Y(n3879) );
OAI222X1TS U5531 ( .A0(n5033), .A1(n4695), .B0(n3882), .B1(n3881), .C0(n3880), .C1(n3879), .Y(n1692) );
BUFX3TS U5532 ( .A(n4976), .Y(n4979) );
NOR3BX1TS U5533 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[0]), .C(
FPMULT_FSM_selector_B[1]), .Y(n3883) );
XOR2X1TS U5534 ( .A(n2361), .B(n3883), .Y(DP_OP_234J1_127_8543_n15) );
OR2X2TS U5535 ( .A(FPMULT_FSM_selector_B[1]), .B(n5020), .Y(n3890) );
OAI2BB1X1TS U5536 ( .A0N(FPMULT_Op_MY[29]), .A1N(n5032), .B0(n3890), .Y(
n3884) );
XOR2X1TS U5537 ( .A(n2361), .B(n3884), .Y(DP_OP_234J1_127_8543_n16) );
OAI2BB1X1TS U5538 ( .A0N(FPMULT_Op_MY[28]), .A1N(n5032), .B0(n3890), .Y(
n3885) );
XOR2X1TS U5539 ( .A(n2361), .B(n3885), .Y(DP_OP_234J1_127_8543_n17) );
OAI2BB1X1TS U5540 ( .A0N(FPMULT_Op_MY[27]), .A1N(n5032), .B0(n3890), .Y(
n3886) );
XOR2X1TS U5541 ( .A(n2361), .B(n3886), .Y(DP_OP_234J1_127_8543_n18) );
OAI2BB1X1TS U5542 ( .A0N(FPMULT_Op_MY[26]), .A1N(n5032), .B0(n3890), .Y(
n3887) );
XOR2X1TS U5543 ( .A(n2361), .B(n3887), .Y(DP_OP_234J1_127_8543_n19) );
OAI2BB1X1TS U5544 ( .A0N(FPMULT_Op_MY[25]), .A1N(n5032), .B0(n3890), .Y(
n3888) );
XOR2X1TS U5545 ( .A(n2361), .B(n3888), .Y(DP_OP_234J1_127_8543_n20) );
OAI2BB1X1TS U5546 ( .A0N(FPMULT_Op_MY[24]), .A1N(n5032), .B0(n3890), .Y(
n3889) );
XOR2X1TS U5547 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n3889), .Y(
DP_OP_234J1_127_8543_n21) );
XOR2X1TS U5548 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n3892), .Y(
DP_OP_234J1_127_8543_n22) );
NOR2BX1TS U5549 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3893) );
XOR2X1TS U5550 ( .A(n5008), .B(n3893), .Y(DP_OP_26J1_124_9022_n14) );
NOR2BX1TS U5551 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3894) );
XOR2X1TS U5552 ( .A(n5008), .B(n3894), .Y(DP_OP_26J1_124_9022_n15) );
NOR2BX1TS U5553 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3895) );
XOR2X1TS U5554 ( .A(n5008), .B(n3895), .Y(DP_OP_26J1_124_9022_n16) );
NOR2BX1TS U5555 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3896) );
XOR2X1TS U5556 ( .A(n5008), .B(n3896), .Y(DP_OP_26J1_124_9022_n17) );
XOR2X1TS U5557 ( .A(n5008), .B(n2437), .Y(DP_OP_26J1_124_9022_n18) );
NAND2X1TS U5558 ( .A(n4741), .B(n5083), .Y(n1690) );
NAND2X1TS U5559 ( .A(FPMULT_Sgf_normalized_result[6]), .B(
FPMULT_Sgf_normalized_result[7]), .Y(n3898) );
NAND2X1TS U5560 ( .A(FPMULT_Sgf_normalized_result[5]), .B(
FPMULT_Sgf_normalized_result[4]), .Y(n3938) );
NOR2X1TS U5561 ( .A(n4994), .B(n5036), .Y(n3930) );
NAND2X1TS U5562 ( .A(n3930), .B(FPMULT_Sgf_normalized_result[10]), .Y(n3901)
);
AHHCINX2TS U5563 ( .A(FPMULT_Sgf_normalized_result[22]), .CIN(n3903), .S(
n3904), .CO(n3954) );
AHHCONX2TS U5564 ( .A(FPMULT_Sgf_normalized_result[21]), .CI(n3905), .CON(
n3903), .S(n3906) );
AHHCINX2TS U5565 ( .A(FPMULT_Sgf_normalized_result[20]), .CIN(n3907), .S(
n3908), .CO(n3905) );
AHHCONX2TS U5566 ( .A(FPMULT_Sgf_normalized_result[19]), .CI(n3909), .CON(
n3907), .S(n3910) );
AHHCINX2TS U5567 ( .A(FPMULT_Sgf_normalized_result[18]), .CIN(n3911), .S(
n3912), .CO(n3909) );
AHHCONX2TS U5568 ( .A(FPMULT_Sgf_normalized_result[17]), .CI(n3913), .CON(
n3911), .S(n3914) );
AHHCINX2TS U5569 ( .A(FPMULT_Sgf_normalized_result[16]), .CIN(n3915), .S(
n3916), .CO(n3913) );
AHHCONX2TS U5570 ( .A(FPMULT_Sgf_normalized_result[15]), .CI(n3917), .CON(
n3915), .S(n3918) );
AHHCINX2TS U5571 ( .A(FPMULT_Sgf_normalized_result[14]), .CIN(n3919), .S(
n3921), .CO(n3917) );
AHHCONX2TS U5572 ( .A(FPMULT_Sgf_normalized_result[13]), .CI(n3922), .CON(
n3919), .S(n3924) );
AHHCINX2TS U5573 ( .A(FPMULT_Sgf_normalized_result[12]), .CIN(n3925), .S(
n3926), .CO(n3922) );
AHHCONX2TS U5574 ( .A(FPMULT_Sgf_normalized_result[11]), .CI(n3927), .CON(
n3925), .S(n3928) );
INVX2TS U5575 ( .A(n3929), .Y(n3935) );
NAND2X1TS U5576 ( .A(n3935), .B(n3930), .Y(n3931) );
XOR2X1TS U5577 ( .A(n3931), .B(n5119), .Y(n3932) );
NAND2X1TS U5578 ( .A(n3935), .B(FPMULT_Sgf_normalized_result[8]), .Y(n3933)
);
XOR2X1TS U5579 ( .A(n3933), .B(n5036), .Y(n3934) );
XNOR2X1TS U5580 ( .A(n3935), .B(n4994), .Y(n3936) );
INVX2TS U5581 ( .A(n3937), .Y(n3945) );
OAI21X1TS U5582 ( .A0(n3945), .A1(n5037), .B0(n3938), .Y(n3941) );
NAND2X1TS U5583 ( .A(n3941), .B(FPMULT_Sgf_normalized_result[6]), .Y(n3939)
);
XOR2X1TS U5584 ( .A(n3939), .B(n5120), .Y(n3940) );
XNOR2X1TS U5585 ( .A(n3941), .B(n5093), .Y(n3942) );
NAND2X1TS U5586 ( .A(n3945), .B(n5081), .Y(n3943) );
XNOR2X1TS U5587 ( .A(n3943), .B(n5037), .Y(n3944) );
XOR2X1TS U5588 ( .A(n3945), .B(FPMULT_Sgf_normalized_result[4]), .Y(n3947)
);
XOR2X1TS U5589 ( .A(n3949), .B(n5035), .Y(n3950) );
XOR2X1TS U5590 ( .A(n3951), .B(FPMULT_Sgf_normalized_result[2]), .Y(n3952)
);
XNOR2X1TS U5591 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n3953) );
ADDHXLTS U5592 ( .A(FPMULT_Sgf_normalized_result[23]), .B(n3954), .CO(n3956),
.S(n3902) );
INVX2TS U5593 ( .A(Data_1[29]), .Y(n3958) );
MXI2X1TS U5594 ( .A(n3958), .B(n5138), .S0(n3959), .Y(n1688) );
INVX2TS U5595 ( .A(FPMULT_FSM_exp_operation_A_S), .Y(n3960) );
NOR2X4TS U5596 ( .A(n4063), .B(n4070), .Y(n4856) );
BUFX3TS U5597 ( .A(n4856), .Y(n4064) );
BUFX3TS U5598 ( .A(n4856), .Y(n4052) );
BUFX3TS U5599 ( .A(n4856), .Y(n3964) );
BUFX3TS U5600 ( .A(n4856), .Y(n4946) );
INVX2TS U5601 ( .A(n4856), .Y(n4945) );
NAND2X2TS U5602 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n3987) );
NOR2X2TS U5603 ( .A(n2202), .B(n3987), .Y(n4013) );
NAND2X1TS U5604 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n2202), .Y(n3970)
);
OAI2BB2XLTS U5605 ( .B0(n5062), .B1(n3970), .A0N(FPADDSUB_Data_array_SWR[16]), .A1N(n2262), .Y(n3965) );
AOI211X4TS U5606 ( .A0(n3976), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n4013),
.C0(n3965), .Y(n4034) );
NAND3X2TS U5607 ( .A(n2281), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .C(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n4018) );
NAND3X2TS U5608 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n2202), .C(n2281),
.Y(n4015) );
AOI22X1TS U5609 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2258), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n2274), .Y(n3967) );
NAND2X2TS U5610 ( .A(n2281), .B(n2261), .Y(n4021) );
AOI22X1TS U5611 ( .A0(FPADDSUB_Data_array_SWR[4]), .A1(n2287), .B0(
FPADDSUB_Data_array_SWR[0]), .B1(n2279), .Y(n3966) );
OAI211X1TS U5612 ( .A0(n4034), .A1(n2213), .B0(n3967), .C0(n3966), .Y(n4060)
);
NOR2X2TS U5613 ( .A(n2261), .B(n2222), .Y(n3981) );
NOR2X4TS U5614 ( .A(n2282), .B(n2222), .Y(n4036) );
AOI21X1TS U5615 ( .A0(n3968), .A1(n3974), .B0(n4858), .Y(n3969) );
OAI22X1TS U5616 ( .A0(n5067), .A1(n3988), .B0(n2438), .B1(n3970), .Y(n3971)
);
AOI211X2TS U5617 ( .A0(n2262), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n4013),
.C0(n3971), .Y(n4037) );
AOI22X1TS U5618 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2274), .B0(
FPADDSUB_Data_array_SWR[1]), .B1(n2279), .Y(n3973) );
AOI22X1TS U5619 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2258), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n2288), .Y(n3972) );
OAI211X1TS U5620 ( .A0(n4037), .A1(n2282), .B0(n3973), .C0(n3972), .Y(n4055)
);
AOI211X1TS U5621 ( .A0(n2327), .A1(n4055), .B0(n4010), .C0(n3975), .Y(n4863)
);
MXI2X1TS U5622 ( .A(n4863), .B(n5112), .S0(n4858), .Y(n1182) );
AOI22X1TS U5623 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n3976), .B0(
FPADDSUB_Data_array_SWR[18]), .B1(n2262), .Y(n3977) );
NAND2X1TS U5624 ( .A(n3977), .B(n3987), .Y(n4001) );
OAI22X1TS U5625 ( .A0(n2400), .A1(n4018), .B0(n5080), .B1(n4015), .Y(n3979)
);
AOI211X1TS U5626 ( .A0(FPADDSUB_shift_value_SHT2_EWR[4]), .A1(n4001), .B0(
n3979), .C0(n3978), .Y(n4051) );
AOI21X2TS U5627 ( .A0(n2262), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n3981),
.Y(n4049) );
OAI22X1TS U5628 ( .A0(n4051), .A1(n2326), .B0(n4049), .B1(n4008), .Y(n3980)
);
MXI2X1TS U5629 ( .A(n4872), .B(n5105), .S0(n4858), .Y(n1183) );
OAI21X1TS U5630 ( .A0(n3988), .A1(n2436), .B0(n3987), .Y(n3982) );
OAI2BB2XLTS U5631 ( .B0(n4041), .B1(n2282), .A0N(FPADDSUB_Data_array_SWR[15]), .A1N(n2257), .Y(n3983) );
AOI211X1TS U5632 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n2287), .B0(n3984),
.C0(n3983), .Y(n4048) );
OAI22X1TS U5633 ( .A0(n4047), .A1(n4008), .B0(n4048), .B1(n2370), .Y(n3985)
);
MXI2X1TS U5634 ( .A(n4876), .B(n5113), .S0(n4858), .Y(n1184) );
OAI21X1TS U5635 ( .A0(n3988), .A1(n2438), .B0(n3987), .Y(n3986) );
OAI21X1TS U5636 ( .A0(n3988), .A1(n5062), .B0(n3987), .Y(n3989) );
AOI21X2TS U5637 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2262), .B0(n3989),
.Y(n4043) );
OAI2BB2XLTS U5638 ( .B0(n4043), .B1(n2282), .A0N(FPADDSUB_Data_array_SWR[12]), .A1N(n2273), .Y(n3990) );
OAI22X1TS U5639 ( .A0(n4045), .A1(n4008), .B0(n4046), .B1(n2326), .Y(n3992)
);
MXI2X1TS U5640 ( .A(n4874), .B(n5106), .S0(n4858), .Y(n1185) );
OAI2BB2XLTS U5641 ( .B0(n4045), .B1(n2282), .A0N(FPADDSUB_Data_array_SWR[13]), .A1N(n2273), .Y(n3993) );
AOI211X1TS U5642 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2288), .B0(n3994),
.C0(n3993), .Y(n4044) );
OAI22X1TS U5643 ( .A0(n4044), .A1(n2370), .B0(n4043), .B1(n4008), .Y(n3995)
);
NOR2X1TS U5644 ( .A(n4010), .B(n3995), .Y(n4869) );
BUFX3TS U5645 ( .A(n4858), .Y(n4032) );
MXI2X1TS U5646 ( .A(n4869), .B(n5114), .S0(n4032), .Y(n1186) );
OAI22X1TS U5647 ( .A0(n4047), .A1(n2282), .B0(n2400), .B1(n4015), .Y(n3996)
);
AOI211X1TS U5648 ( .A0(FPADDSUB_Data_array_SWR[6]), .A1(n2279), .B0(n3997),
.C0(n3996), .Y(n4042) );
OAI22X1TS U5649 ( .A0(n4042), .A1(n2370), .B0(n4041), .B1(n4008), .Y(n3998)
);
MXI2X1TS U5650 ( .A(n4878), .B(n5107), .S0(n4858), .Y(n1187) );
AOI22X1TS U5651 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n2274), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2287), .Y(n4000) );
AOI22X1TS U5652 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2258), .B0(
FPADDSUB_Data_array_SWR[7]), .B1(n2279), .Y(n3999) );
OAI211X1TS U5653 ( .A0(n4049), .A1(n2213), .B0(n4000), .C0(n3999), .Y(n4039)
);
INVX2TS U5654 ( .A(n4001), .Y(n4040) );
AOI211X1TS U5655 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4039), .B0(n4010),
.C0(n4002), .Y(n4889) );
MXI2X1TS U5656 ( .A(n4889), .B(n5115), .S0(n4858), .Y(n1188) );
OAI2BB2XLTS U5657 ( .B0(n4053), .B1(n2282), .A0N(FPADDSUB_Data_array_SWR[16]), .A1N(n2273), .Y(n4003) );
AOI211X1TS U5658 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n2279), .B0(n4004),
.C0(n4003), .Y(n4038) );
OAI22X1TS U5659 ( .A0(n4038), .A1(n2326), .B0(n4037), .B1(n4008), .Y(n4005)
);
MXI2X1TS U5660 ( .A(n4867), .B(n5108), .S0(n4032), .Y(n1189) );
OAI22X1TS U5661 ( .A0(n4057), .A1(n2281), .B0(n5067), .B1(n4018), .Y(n4006)
);
AOI211X1TS U5662 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2279), .B0(n4007),
.C0(n4006), .Y(n4035) );
OAI22X1TS U5663 ( .A0(n4035), .A1(n2326), .B0(n4034), .B1(n4008), .Y(n4009)
);
MXI2X1TS U5664 ( .A(n4897), .B(n5116), .S0(n4032), .Y(n1190) );
AOI21X1TS U5665 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2288), .B0(n4036),
.Y(n4012) );
AOI22X1TS U5666 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n2258), .B0(
FPADDSUB_Data_array_SWR[18]), .B1(n2274), .Y(n4011) );
OAI211X1TS U5667 ( .A0(n5080), .A1(n4021), .B0(n4012), .C0(n4011), .Y(n4030)
);
NOR2X1TS U5668 ( .A(n4036), .B(n4013), .Y(n4020) );
AOI22X1TS U5669 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2288), .B0(
FPADDSUB_Data_array_SWR[15]), .B1(n2279), .Y(n4014) );
OAI211X1TS U5670 ( .A0(n2436), .A1(n4015), .B0(n4020), .C0(n4014), .Y(n4031)
);
AOI22X1TS U5671 ( .A0(n2327), .A1(n4030), .B0(n4031), .B1(n2326), .Y(n4887)
);
MXI2X1TS U5672 ( .A(n4887), .B(n5109), .S0(n4032), .Y(n1191) );
AOI21X1TS U5673 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n2279), .B0(n4036),
.Y(n4017) );
AOI22X1TS U5674 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2274), .B0(
FPADDSUB_Data_array_SWR[15]), .B1(n2288), .Y(n4016) );
OAI211X1TS U5675 ( .A0(n2436), .A1(n4018), .B0(n4017), .C0(n4016), .Y(n4028)
);
AOI22X1TS U5676 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n2274), .B0(
FPADDSUB_Data_array_SWR[18]), .B1(n2288), .Y(n4019) );
OAI211X1TS U5677 ( .A0(n2400), .A1(n4021), .B0(n4020), .C0(n4019), .Y(n4029)
);
AOI22X1TS U5678 ( .A0(n2327), .A1(n4028), .B0(n4029), .B1(n2370), .Y(n4902)
);
MXI2X1TS U5679 ( .A(n4902), .B(n5117), .S0(n4032), .Y(n1192) );
AOI22X1TS U5680 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2274), .B0(
FPADDSUB_Data_array_SWR[16]), .B1(n2288), .Y(n4023) );
AOI22X1TS U5681 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2279), .B0(
FPADDSUB_Data_array_SWR[24]), .B1(n2258), .Y(n4022) );
NAND2X1TS U5682 ( .A(n4023), .B(n4022), .Y(n4026) );
AOI22X1TS U5683 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2279), .B0(
FPADDSUB_Data_array_SWR[25]), .B1(n2258), .Y(n4025) );
AOI22X1TS U5684 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2274), .B0(
FPADDSUB_Data_array_SWR[17]), .B1(n2288), .Y(n4024) );
NAND2X1TS U5685 ( .A(n4025), .B(n4024), .Y(n4027) );
AOI221X1TS U5686 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4026), .B0(n2326),
.B1(n4027), .C0(n4036), .Y(n4895) );
MXI2X1TS U5687 ( .A(n4895), .B(n5110), .S0(n4032), .Y(n1193) );
AOI221X1TS U5688 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4027), .B0(n2370),
.B1(n4026), .C0(n4036), .Y(n4899) );
MXI2X1TS U5689 ( .A(n4899), .B(n5111), .S0(n4032), .Y(n1194) );
AOI22X1TS U5690 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4029), .B0(n4028),
.B1(n2326), .Y(n4968) );
MXI2X1TS U5691 ( .A(n4968), .B(n5118), .S0(n4032), .Y(n1195) );
AOI22X1TS U5692 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4031), .B0(n4030),
.B1(n2370), .Y(n4892) );
MXI2X1TS U5693 ( .A(n4892), .B(n5103), .S0(n4032), .Y(n1196) );
OAI22X1TS U5694 ( .A0(n4035), .A1(FPADDSUB_left_right_SHT2), .B0(n4033),
.B1(n4034), .Y(n4958) );
NAND2X1TS U5695 ( .A(n2327), .B(n4036), .Y(n4880) );
OA22X1TS U5696 ( .A0(n4958), .A1(n4058), .B0(n4052), .B1(
FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n1197) );
OAI22X1TS U5697 ( .A0(n4038), .A1(n2327), .B0(n4033), .B1(n4037), .Y(n4884)
);
OA22X1TS U5698 ( .A0(n4884), .A1(n4058), .B0(n4052), .B1(
FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n1198) );
OAI2BB2X1TS U5699 ( .B0(n4033), .B1(n4040), .A0N(n2326), .A1N(n4039), .Y(
n4970) );
OA22X1TS U5700 ( .A0(n4970), .A1(n4058), .B0(n4052), .B1(
FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n1199) );
OAI22X1TS U5701 ( .A0(n4042), .A1(FPADDSUB_left_right_SHT2), .B0(n4033),
.B1(n4041), .Y(n4881) );
OA22X1TS U5702 ( .A0(n4881), .A1(n4058), .B0(n4052), .B1(
FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n1200) );
OAI22X1TS U5703 ( .A0(n4044), .A1(n2327), .B0(n4033), .B1(n4043), .Y(n4952)
);
OA22X1TS U5704 ( .A0(n4952), .A1(n4058), .B0(n4052), .B1(
FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n1201) );
OAI22X1TS U5705 ( .A0(n4046), .A1(FPADDSUB_left_right_SHT2), .B0(n4033),
.B1(n4045), .Y(n4955) );
OA22X1TS U5706 ( .A0(n4955), .A1(n4058), .B0(n4946), .B1(
FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n1202) );
OAI22X1TS U5707 ( .A0(n4048), .A1(n2327), .B0(n4033), .B1(n4047), .Y(n4964)
);
OA22X1TS U5708 ( .A0(n4964), .A1(n4058), .B0(n4052), .B1(
FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n1203) );
OAI22X1TS U5709 ( .A0(n4051), .A1(n2327), .B0(n4033), .B1(n4049), .Y(n4961)
);
OA22X1TS U5710 ( .A0(n4961), .A1(n4058), .B0(n4052), .B1(
FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n1204) );
AOI211X1TS U5711 ( .A0(n4055), .A1(n2370), .B0(n4054), .C0(n4058), .Y(n4056)
);
AOI21X1TS U5712 ( .A0(n4945), .A1(n5004), .B0(n4056), .Y(n1205) );
AOI211X1TS U5713 ( .A0(n4060), .A1(n2326), .B0(n4059), .C0(n4058), .Y(n4061)
);
AOI21X1TS U5714 ( .A0(n4945), .A1(n5130), .B0(n4061), .Y(n1206) );
OAI32X4TS U5715 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n4062), .B1(n2212),
.Y(n4506) );
MXI2X1TS U5716 ( .A(n4063), .B(n4259), .S0(n4506), .Y(n2145) );
OAI22X1TS U5717 ( .A0(FPMULT_Exp_module_Data_S[8]), .A1(n4069), .B0(n4743),
.B1(n5104), .Y(n1587) );
OA22X1TS U5718 ( .A0(n4860), .A1(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B0(n4070),
.B1(result_add_subt[29]), .Y(n1468) );
OA22X1TS U5719 ( .A0(n4860), .A1(FPADDSUB_exp_rslt_NRM2_EW1[5]), .B0(n4070),
.B1(result_add_subt[28]), .Y(n1469) );
NOR4X1TS U5720 ( .A(n4849), .B(FPMULT_Exp_module_Overflow_flag_A), .C(
FPMULT_exp_oper_result[8]), .D(underflow_flag_mult), .Y(n4073) );
NAND2X1TS U5721 ( .A(n4075), .B(n4074), .Y(n4078) );
INVX2TS U5722 ( .A(n4078), .Y(n4076) );
XNOR2X1TS U5723 ( .A(n4077), .B(n4076), .Y(n4082) );
XNOR2X1TS U5724 ( .A(n4079), .B(n4078), .Y(n4080) );
AOI22X1TS U5725 ( .A0(n4080), .A1(n2693), .B0(FPADDSUB_Raw_mant_NRM_SWR[22]),
.B1(n4505), .Y(n4081) );
OAI2BB1X1TS U5726 ( .A0N(n4159), .A1N(n4082), .B0(n4081), .Y(n1318) );
OR2X1TS U5727 ( .A(n5112), .B(FPADDSUB_DMP_SFG[22]), .Y(n4084) );
XOR2X1TS U5728 ( .A(n4087), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n4088) );
INVX2TS U5729 ( .A(n4091), .Y(n4093) );
NAND2X1TS U5730 ( .A(n4093), .B(n4092), .Y(n4096) );
INVX2TS U5731 ( .A(n4096), .Y(n4094) );
XOR2X1TS U5732 ( .A(n4097), .B(n4096), .Y(n4098) );
AOI22X1TS U5733 ( .A0(n4098), .A1(n2693), .B0(FPADDSUB_Raw_mant_NRM_SWR[23]),
.B1(n4505), .Y(n4099) );
OAI2BB1X1TS U5734 ( .A0N(n4159), .A1N(n4100), .B0(n4099), .Y(n1317) );
INVX2TS U5735 ( .A(n4101), .Y(n4103) );
NAND2X1TS U5736 ( .A(n4103), .B(n4102), .Y(n4106) );
INVX2TS U5737 ( .A(n4106), .Y(n4104) );
XOR2X1TS U5738 ( .A(n4107), .B(n4106), .Y(n4108) );
AOI22X1TS U5739 ( .A0(n4108), .A1(n2693), .B0(FPADDSUB_Raw_mant_NRM_SWR[21]),
.B1(n4505), .Y(n4109) );
OAI2BB1X1TS U5740 ( .A0N(n4159), .A1N(n4110), .B0(n4109), .Y(n1320) );
INVX2TS U5741 ( .A(n4111), .Y(n4113) );
NAND2X1TS U5742 ( .A(n4113), .B(n4112), .Y(n4116) );
INVX2TS U5743 ( .A(n4116), .Y(n4114) );
XOR2X1TS U5744 ( .A(n4117), .B(n4116), .Y(n4118) );
BUFX3TS U5745 ( .A(n2264), .Y(n4219) );
AOI22X1TS U5746 ( .A0(n4118), .A1(n4201), .B0(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B1(n4219), .Y(n4119) );
OAI2BB1X1TS U5747 ( .A0N(n4159), .A1N(n4120), .B0(n4119), .Y(n1322) );
NAND2X1TS U5748 ( .A(n4122), .B(n4121), .Y(n4125) );
INVX2TS U5749 ( .A(n4125), .Y(n4123) );
XNOR2X1TS U5750 ( .A(n4124), .B(n4123), .Y(n4129) );
XNOR2X1TS U5751 ( .A(n4126), .B(n4125), .Y(n4127) );
AOI22X1TS U5752 ( .A0(n4127), .A1(n4201), .B0(FPADDSUB_Raw_mant_NRM_SWR[20]),
.B1(n4505), .Y(n4128) );
OAI2BB1X1TS U5753 ( .A0N(n4159), .A1N(n4129), .B0(n4128), .Y(n1321) );
NAND2X1TS U5754 ( .A(n4132), .B(n4131), .Y(n4135) );
INVX2TS U5755 ( .A(n4135), .Y(n4133) );
XOR2X1TS U5756 ( .A(n4136), .B(n4135), .Y(n4137) );
AOI22X1TS U5757 ( .A0(n4137), .A1(n4201), .B0(FPADDSUB_Raw_mant_NRM_SWR[17]),
.B1(n4505), .Y(n4138) );
OAI2BB1X1TS U5758 ( .A0N(n4159), .A1N(n4139), .B0(n4138), .Y(n1333) );
NAND2X1TS U5759 ( .A(n4141), .B(n4140), .Y(n4144) );
INVX2TS U5760 ( .A(n4144), .Y(n4142) );
XNOR2X1TS U5761 ( .A(n4143), .B(n4142), .Y(n4148) );
XNOR2X1TS U5762 ( .A(n4145), .B(n4144), .Y(n4146) );
AOI22X1TS U5763 ( .A0(n4146), .A1(n4201), .B0(FPADDSUB_Raw_mant_NRM_SWR[16]),
.B1(n4219), .Y(n4147) );
OAI2BB1X1TS U5764 ( .A0N(n4159), .A1N(n4148), .B0(n4147), .Y(n1334) );
NAND2X1TS U5765 ( .A(n4151), .B(n4150), .Y(n4154) );
INVX2TS U5766 ( .A(n4154), .Y(n4152) );
XOR2X1TS U5767 ( .A(n4155), .B(n4154), .Y(n4156) );
AOI22X1TS U5768 ( .A0(n4156), .A1(n4201), .B0(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B1(n4219), .Y(n4157) );
OAI2BB1X1TS U5769 ( .A0N(n4159), .A1N(n4158), .B0(n4157), .Y(n1335) );
BUFX3TS U5770 ( .A(n4160), .Y(n4264) );
NAND2X1TS U5771 ( .A(n4162), .B(n4161), .Y(n4165) );
INVX2TS U5772 ( .A(n4165), .Y(n4163) );
XNOR2X1TS U5773 ( .A(n4164), .B(n4163), .Y(n4169) );
XNOR2X1TS U5774 ( .A(n4166), .B(n4165), .Y(n4167) );
AOI22X1TS U5775 ( .A0(n4167), .A1(n4201), .B0(FPADDSUB_Raw_mant_NRM_SWR[14]),
.B1(n4219), .Y(n4168) );
OAI2BB1X1TS U5776 ( .A0N(n4264), .A1N(n4169), .B0(n4168), .Y(n1336) );
NAND2X1TS U5777 ( .A(n4171), .B(n4170), .Y(n4174) );
INVX2TS U5778 ( .A(n4174), .Y(n4172) );
XNOR2X1TS U5779 ( .A(n4173), .B(n4172), .Y(n4178) );
XNOR2X1TS U5780 ( .A(n4175), .B(n4174), .Y(n4176) );
AOI22X1TS U5781 ( .A0(n4176), .A1(n4201), .B0(FPADDSUB_Raw_mant_NRM_SWR[18]),
.B1(n4219), .Y(n4177) );
OAI2BB1X1TS U5782 ( .A0N(n4264), .A1N(n4178), .B0(n4177), .Y(n1332) );
NAND2X1TS U5783 ( .A(n4181), .B(n4180), .Y(n4184) );
INVX2TS U5784 ( .A(n4184), .Y(n4182) );
XOR2X1TS U5785 ( .A(n4185), .B(n4184), .Y(n4186) );
AOI22X1TS U5786 ( .A0(n4186), .A1(n4201), .B0(FPADDSUB_Raw_mant_NRM_SWR[13]),
.B1(n4219), .Y(n4187) );
OAI2BB1X1TS U5787 ( .A0N(n4264), .A1N(n4188), .B0(n4187), .Y(n1337) );
INVX2TS U5788 ( .A(n4189), .Y(n4192) );
INVX2TS U5789 ( .A(n4190), .Y(n4191) );
NAND2X1TS U5790 ( .A(n4194), .B(n4193), .Y(n4199) );
INVX2TS U5791 ( .A(n4199), .Y(n4195) );
XNOR2X1TS U5792 ( .A(n4196), .B(n4195), .Y(n4204) );
INVX2TS U5793 ( .A(n4197), .Y(n4256) );
XNOR2X1TS U5794 ( .A(n4200), .B(n4199), .Y(n4202) );
AOI22X1TS U5795 ( .A0(n4202), .A1(n4201), .B0(FPADDSUB_Raw_mant_NRM_SWR[11]),
.B1(n4219), .Y(n4203) );
OAI2BB1X1TS U5796 ( .A0N(n4264), .A1N(n4204), .B0(n4203), .Y(n1339) );
MXI2X1TS U5797 ( .A(n5094), .B(n5130), .S0(n2265), .Y(n1350) );
XNOR2X1TS U5798 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(n5130), .Y(n4206) );
AOI22X1TS U5799 ( .A0(n4260), .A1(FPADDSUB_DmP_mant_SFG_SWR[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n4219), .Y(n4205) );
OAI2BB1X1TS U5800 ( .A0N(n4264), .A1N(n4206), .B0(n4205), .Y(n1349) );
AOI22X1TS U5801 ( .A0(n4209), .A1(n4260), .B0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.B1(n4219), .Y(n4210) );
OAI2BB1X1TS U5802 ( .A0N(n4264), .A1N(n4211), .B0(n4210), .Y(n1348) );
INVX2TS U5803 ( .A(n4212), .Y(n4225) );
INVX2TS U5804 ( .A(n4213), .Y(n4215) );
NAND2X1TS U5805 ( .A(n4215), .B(n4214), .Y(n4218) );
INVX2TS U5806 ( .A(n4218), .Y(n4216) );
XOR2X1TS U5807 ( .A(n4218), .B(n4217), .Y(n4220) );
AOI22X1TS U5808 ( .A0(n4220), .A1(n4260), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.B1(n4219), .Y(n4221) );
OAI2BB1X1TS U5809 ( .A0N(n4264), .A1N(n4222), .B0(n4221), .Y(n1347) );
INVX2TS U5810 ( .A(n4226), .Y(n4228) );
NAND2X1TS U5811 ( .A(n4228), .B(n4227), .Y(n4231) );
INVX2TS U5812 ( .A(n4231), .Y(n4229) );
XNOR2X1TS U5813 ( .A(n4230), .B(n4229), .Y(n4235) );
XOR2X1TS U5814 ( .A(n4232), .B(n4231), .Y(n4233) );
AOI22X1TS U5815 ( .A0(n4233), .A1(n4260), .B0(FPADDSUB_Raw_mant_NRM_SWR[4]),
.B1(n4259), .Y(n4234) );
OAI2BB1X1TS U5816 ( .A0N(n4264), .A1N(n4235), .B0(n4234), .Y(n1346) );
NAND2X1TS U5817 ( .A(n4239), .B(n4238), .Y(n4242) );
INVX2TS U5818 ( .A(n4242), .Y(n4240) );
XNOR2X1TS U5819 ( .A(n4241), .B(n4240), .Y(n4245) );
XOR2X1TS U5820 ( .A(n4256), .B(n4242), .Y(n4243) );
AOI22X1TS U5821 ( .A0(n4243), .A1(n4260), .B0(FPADDSUB_Raw_mant_NRM_SWR[10]),
.B1(n4259), .Y(n4244) );
OAI2BB1X1TS U5822 ( .A0N(n4264), .A1N(n4245), .B0(n4244), .Y(n1340) );
NAND2X1TS U5823 ( .A(n4251), .B(n4250), .Y(n4257) );
INVX2TS U5824 ( .A(n4257), .Y(n4252) );
XNOR2X1TS U5825 ( .A(n4253), .B(n4252), .Y(n4263) );
XNOR2X1TS U5826 ( .A(n4258), .B(n4257), .Y(n4261) );
AOI22X1TS U5827 ( .A0(n4261), .A1(n4260), .B0(FPADDSUB_Raw_mant_NRM_SWR[12]),
.B1(n4259), .Y(n4262) );
OAI2BB1X1TS U5828 ( .A0N(n4264), .A1N(n4263), .B0(n4262), .Y(n1338) );
AOI22X1TS U5829 ( .A0(n4268), .A1(n4267), .B0(n4266), .B1(n4265), .Y(
intadd_3_A_1_) );
AOI22X1TS U5830 ( .A0(n2248), .A1(n4270), .B0(n4269), .B1(n4315), .Y(
intadd_3_B_1_) );
AOI21X1TS U5831 ( .A0(intadd_3_SUM_0_), .A1(n4272), .B0(n4271), .Y(
FPMULT_Sgf_operation_EVEN1_left_N4) );
AOI21X1TS U5832 ( .A0(n4275), .A1(n4274), .B0(n4273), .Y(
FPMULT_Sgf_operation_EVEN1_left_N2) );
NOR2XLTS U5833 ( .A(n4999), .B(n2373), .Y(n4277) );
XNOR2X1TS U5834 ( .A(n4277), .B(n4276), .Y(
FPMULT_Sgf_operation_EVEN1_left_N1) );
AOI22X1TS U5835 ( .A0(FPMULT_Op_MY[21]), .A1(n2286), .B0(n2319), .B1(n5026),
.Y(n4305) );
OAI22X1TS U5836 ( .A0(n2266), .A1(n4305), .B0(n4310), .B1(n4278), .Y(n4279)
);
AOI21X1TS U5837 ( .A0(n4282), .A1(n4281), .B0(mult_x_219_n106), .Y(
mult_x_219_n107) );
AOI21X1TS U5838 ( .A0(n4285), .A1(n4284), .B0(mult_x_219_n119), .Y(
mult_x_219_n120) );
AO21XLTS U5839 ( .A0(n4734), .A1(n2283), .B0(mult_x_219_n177), .Y(n4286) );
AOI21X1TS U5840 ( .A0(n4287), .A1(n4286), .B0(n2351), .Y(mult_x_219_n130) );
NAND2X1TS U5841 ( .A(n5026), .B(n2350), .Y(n4288) );
OAI22X1TS U5842 ( .A0(n5177), .A1(n4288), .B0(n2241), .B1(n2263), .Y(
mult_x_219_n152) );
NAND2X1TS U5843 ( .A(n5022), .B(n2349), .Y(n4289) );
OAI22X1TS U5844 ( .A0(n5177), .A1(n4289), .B0(FPMULT_Op_MY[21]), .B1(n2263),
.Y(mult_x_219_n153) );
NAND2X1TS U5845 ( .A(n5027), .B(n2350), .Y(n4290) );
OAI22X1TS U5846 ( .A0(n5177), .A1(n4290), .B0(FPMULT_Op_MY[20]), .B1(n2263),
.Y(mult_x_219_n154) );
NAND2X1TS U5847 ( .A(n5025), .B(n2349), .Y(n4291) );
OAI22X1TS U5848 ( .A0(n5177), .A1(n4291), .B0(FPMULT_Op_MY[19]), .B1(n2263),
.Y(mult_x_219_n155) );
NAND2X1TS U5849 ( .A(n5029), .B(n2350), .Y(n4292) );
OAI22X1TS U5850 ( .A0(n5177), .A1(n4292), .B0(FPMULT_Op_MY[18]), .B1(n2263),
.Y(mult_x_219_n156) );
NAND2X1TS U5851 ( .A(n5023), .B(n2349), .Y(n4293) );
OAI22X1TS U5852 ( .A0(n5177), .A1(n4293), .B0(n2200), .B1(n4298), .Y(
mult_x_219_n157) );
NAND2X1TS U5853 ( .A(n5030), .B(n2350), .Y(n4294) );
OAI22X1TS U5854 ( .A0(FPMULT_Op_MX[22]), .A1(n4294), .B0(n2207), .B1(n4298),
.Y(mult_x_219_n158) );
NAND2X1TS U5855 ( .A(n5031), .B(n2349), .Y(n4295) );
OAI22X1TS U5856 ( .A0(FPMULT_Op_MX[22]), .A1(n4295), .B0(FPMULT_Op_MY[15]),
.B1(n2263), .Y(mult_x_219_n159) );
NAND2X1TS U5857 ( .A(n5021), .B(n2350), .Y(n4296) );
OAI22X1TS U5858 ( .A0(FPMULT_Op_MX[22]), .A1(n4296), .B0(n2199), .B1(n2263),
.Y(mult_x_219_n160) );
OAI22X1TS U5859 ( .A0(n2369), .A1(n2263), .B0(n2283), .B1(n4297), .Y(
mult_x_219_n161) );
AOI22X1TS U5860 ( .A0(FPMULT_Op_MY[20]), .A1(n2350), .B0(n2324), .B1(n5022),
.Y(n4300) );
OAI22X1TS U5861 ( .A0(n4304), .A1(n4299), .B0(n4302), .B1(n4300), .Y(
mult_x_219_n167) );
AOI22X1TS U5862 ( .A0(FPMULT_Op_MY[19]), .A1(n2349), .B0(n2325), .B1(n5027),
.Y(n4303) );
OAI22X1TS U5863 ( .A0(n4304), .A1(n4300), .B0(n4302), .B1(n4303), .Y(
mult_x_219_n168) );
OAI22X1TS U5864 ( .A0(n4304), .A1(n4303), .B0(n4302), .B1(n4301), .Y(
mult_x_219_n169) );
AOI22X1TS U5865 ( .A0(n2241), .A1(n2286), .B0(n2198), .B1(n5024), .Y(n4306)
);
OAI22X1TS U5866 ( .A0(n2319), .A1(n2266), .B0(n4306), .B1(n4310), .Y(
mult_x_219_n179) );
OAI22X1TS U5867 ( .A0(n2266), .A1(n4306), .B0(n4305), .B1(n4310), .Y(
mult_x_219_n180) );
AOI22X1TS U5868 ( .A0(FPMULT_Op_MY[18]), .A1(n2209), .B0(n2319), .B1(n5025),
.Y(n4308) );
OAI22X1TS U5869 ( .A0(n2266), .A1(n4307), .B0(n4310), .B1(n4308), .Y(
mult_x_219_n183) );
AOI22X1TS U5870 ( .A0(n2200), .A1(n2286), .B0(n2198), .B1(n5029), .Y(n4311)
);
OAI22X1TS U5871 ( .A0(n2267), .A1(n4308), .B0(n4310), .B1(n4311), .Y(
mult_x_219_n184) );
OAI22X1TS U5872 ( .A0(n2267), .A1(n4311), .B0(n4310), .B1(n4309), .Y(
mult_x_219_n185) );
AOI22X1TS U5873 ( .A0(n2210), .A1(n2201), .B0(n2291), .B1(n5024), .Y(n4314)
);
INVX2TS U5874 ( .A(n2628), .Y(n4312) );
OAI22X1TS U5875 ( .A0(n2292), .A1(n4315), .B0(n4314), .B1(n4312), .Y(
mult_x_219_n193) );
OAI22X1TS U5876 ( .A0(n2309), .A1(n4320), .B0(n4316), .B1(n4318), .Y(
mult_x_219_n207) );
OAI22X1TS U5877 ( .A0(n4320), .A1(n4319), .B0(n4318), .B1(n4317), .Y(
mult_x_219_n209) );
AOI22X1TS U5878 ( .A0(FPMULT_Op_MX[13]), .A1(n5025), .B0(FPMULT_Op_MY[18]),
.B1(n4999), .Y(n4321) );
OAI22X1TS U5879 ( .A0(n2200), .A1(n4322), .B0(n4321), .B1(n5066), .Y(
mult_x_219_n226) );
AOI22X1TS U5880 ( .A0(n2304), .A1(FPMULT_Op_MY[2]), .B0(n5050), .B1(n4704),
.Y(n4326) );
AOI22X1TS U5881 ( .A0(n4328), .A1(n4326), .B0(n4323), .B1(n4371), .Y(
intadd_2_B_0_) );
AOI22X1TS U5882 ( .A0(n2251), .A1(n4325), .B0(n4324), .B1(n4365), .Y(
intadd_2_A_1_) );
AOI22X1TS U5883 ( .A0(n4328), .A1(n4327), .B0(n4371), .B1(n4326), .Y(
intadd_2_B_1_) );
OR3X1TS U5884 ( .A(mult_x_254_n168), .B(n4335), .C(n4381), .Y(n4329) );
AOI21X1TS U5885 ( .A0(n4330), .A1(n4329), .B0(mult_x_254_n106), .Y(
mult_x_254_n107) );
AOI21X1TS U5886 ( .A0(n4333), .A1(n4332), .B0(mult_x_254_n119), .Y(
mult_x_254_n120) );
AO21XLTS U5887 ( .A0(n5065), .A1(n4335), .B0(n4334), .Y(n4337) );
OAI22X1TS U5888 ( .A0(n4338), .A1(n4336), .B0(n2253), .B1(n4337), .Y(
mult_x_254_n166) );
OAI21XLTS U5889 ( .A0(n2275), .A1(FPMULT_Op_MX[11]), .B0(n4377), .Y(n4339)
);
OAI22X1TS U5890 ( .A0(n4340), .A1(n4339), .B0(n4338), .B1(n4337), .Y(
mult_x_254_n167) );
OAI22X1TS U5891 ( .A0(n4726), .A1(mult_x_254_n169), .B0(n4344), .B1(n4341),
.Y(mult_x_254_n170) );
AOI22X1TS U5892 ( .A0(FPMULT_Op_MY[8]), .A1(n4699), .B0(n2312), .B1(n5047),
.Y(n4343) );
OAI22X1TS U5893 ( .A0(n2208), .A1(n4342), .B0(n4344), .B1(n4343), .Y(
mult_x_254_n173) );
AOI22X1TS U5894 ( .A0(FPMULT_Op_MY[7]), .A1(n4699), .B0(n2311), .B1(n5044),
.Y(n4345) );
OAI22X1TS U5895 ( .A0(n2208), .A1(n4343), .B0(n4344), .B1(n4345), .Y(
mult_x_254_n174) );
AOI22X1TS U5896 ( .A0(FPMULT_Op_MY[6]), .A1(n2227), .B0(n2312), .B1(n5048),
.Y(n4348) );
OAI22X1TS U5897 ( .A0(n2208), .A1(n4345), .B0(n4344), .B1(n4348), .Y(
mult_x_254_n175) );
AOI22X1TS U5898 ( .A0(FPMULT_Op_MY[10]), .A1(n4701), .B0(n2301), .B1(n5043),
.Y(n4351) );
OAI22X1TS U5899 ( .A0(n4359), .A1(n4349), .B0(n4354), .B1(n4351), .Y(
mult_x_254_n185) );
OAI22X1TS U5900 ( .A0(n4359), .A1(n4351), .B0(n4354), .B1(n4350), .Y(
mult_x_254_n186) );
AOI22X1TS U5901 ( .A0(FPMULT_Op_MY[6]), .A1(n4701), .B0(n2300), .B1(n5048),
.Y(n4353) );
OAI22X1TS U5902 ( .A0(n4359), .A1(n4352), .B0(n4354), .B1(n4353), .Y(
mult_x_254_n189) );
AOI22X1TS U5903 ( .A0(FPMULT_Op_MY[5]), .A1(n4701), .B0(n2301), .B1(n5042),
.Y(n4355) );
OAI22X1TS U5904 ( .A0(n4359), .A1(n4353), .B0(n4354), .B1(n4355), .Y(
mult_x_254_n190) );
AOI22X1TS U5905 ( .A0(FPMULT_Op_MY[4]), .A1(n4701), .B0(n2300), .B1(n5045),
.Y(n4358) );
OAI22X1TS U5906 ( .A0(n4359), .A1(n4355), .B0(n4354), .B1(n4358), .Y(
mult_x_254_n191) );
AOI22X1TS U5907 ( .A0(FPMULT_Op_MY[11]), .A1(n2305), .B0(n2307), .B1(n5028),
.Y(n4361) );
OAI22X1TS U5908 ( .A0(n4727), .A1(mult_x_254_n197), .B0(n4361), .B1(n4360),
.Y(mult_x_254_n198) );
AOI22X1TS U5909 ( .A0(FPMULT_Op_MY[10]), .A1(n2305), .B0(n2306), .B1(n5043),
.Y(n4364) );
OAI22X1TS U5910 ( .A0(n4365), .A1(n4361), .B0(n4360), .B1(n4364), .Y(
mult_x_254_n199) );
AOI22X1TS U5911 ( .A0(n2304), .A1(n5028), .B0(FPMULT_Op_MY[11]), .B1(n2229),
.Y(n4367) );
OAI22X1TS U5912 ( .A0(n4731), .A1(mult_x_254_n211), .B0(n4367), .B1(n4368),
.Y(mult_x_254_n212) );
OAI22X1TS U5913 ( .A0(n4373), .A1(n4367), .B0(n4366), .B1(n4368), .Y(
mult_x_254_n213) );
AOI22X1TS U5914 ( .A0(n2304), .A1(n5047), .B0(FPMULT_Op_MY[8]), .B1(n2302),
.Y(n4372) );
OAI22X1TS U5915 ( .A0(n4373), .A1(n4369), .B0(n4368), .B1(n4372), .Y(
mult_x_254_n215) );
NOR2X1TS U5916 ( .A(n4993), .B(n5043), .Y(n4375) );
OAI22X1TS U5917 ( .A0(n5041), .A1(FPMULT_Op_MX[0]), .B0(n4375), .B1(n2340),
.Y(n4374) );
AOI21X1TS U5918 ( .A0(n4375), .A1(n2339), .B0(n4374), .Y(mult_x_254_n228) );
INVX2TS U5919 ( .A(mult_x_254_n31), .Y(n4380) );
AOI22X1TS U5920 ( .A0(FPMULT_Op_MX[11]), .A1(n2246), .B0(n2646), .B1(n4376),
.Y(n4379) );
CMPR32X2TS U5921 ( .A(n4380), .B(n4379), .C(n4378), .CO(n4386), .S(
intadd_2_B_18_) );
INVX2TS U5922 ( .A(n4381), .Y(n4384) );
NOR2X1TS U5923 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[11]), .Y(n4724) );
AOI21X1TS U5924 ( .A0(FPMULT_Op_MY[11]), .A1(FPMULT_Op_MY[10]), .B0(n4724),
.Y(n4383) );
NOR2XLTS U5925 ( .A(n4384), .B(n4383), .Y(n4382) );
AOI211XLTS U5926 ( .A0(n4384), .A1(n4383), .B0(n4698), .C0(n4382), .Y(n4385)
);
XOR2XLTS U5927 ( .A(n4386), .B(n4385), .Y(n4387) );
XNOR2X1TS U5928 ( .A(intadd_2_n1), .B(n4387), .Y(
FPMULT_Sgf_operation_EVEN1_right_N23) );
AOI21X1TS U5929 ( .A0(n4389), .A1(n4388), .B0(DP_OP_454J1_123_2743_n148),
.Y(intadd_1_B_0_) );
AOI21X1TS U5930 ( .A0(n4392), .A1(n4391), .B0(n4390), .Y(intadd_1_B_1_) );
AOI22X1TS U5931 ( .A0(n4451), .A1(n4434), .B0(n4432), .B1(n2624), .Y(
DP_OP_454J1_123_2743_n162) );
AOI22X1TS U5932 ( .A0(n2938), .A1(n4436), .B0(n4434), .B1(n2271), .Y(
DP_OP_454J1_123_2743_n163) );
AOI22X1TS U5933 ( .A0(n4451), .A1(n4397), .B0(n4436), .B1(n2624), .Y(
DP_OP_454J1_123_2743_n164) );
AOI22X1TS U5934 ( .A0(n2938), .A1(n4399), .B0(n4397), .B1(n2271), .Y(
DP_OP_454J1_123_2743_n165) );
AOI22X1TS U5935 ( .A0(n2938), .A1(n4401), .B0(n4399), .B1(n2624), .Y(
DP_OP_454J1_123_2743_n166) );
AOI22X1TS U5936 ( .A0(n2938), .A1(n4403), .B0(n4401), .B1(n2271), .Y(
DP_OP_454J1_123_2743_n167) );
AOI22X1TS U5937 ( .A0(n4451), .A1(n4405), .B0(n4403), .B1(n2624), .Y(
DP_OP_454J1_123_2743_n168) );
AOI22X1TS U5938 ( .A0(n2938), .A1(n4407), .B0(n4405), .B1(n2624), .Y(
DP_OP_454J1_123_2743_n169) );
AOI22X1TS U5939 ( .A0(n4451), .A1(n4409), .B0(n4407), .B1(n2624), .Y(
DP_OP_454J1_123_2743_n170) );
AOI22X1TS U5940 ( .A0(n2938), .A1(n2249), .B0(n4409), .B1(n2271), .Y(
DP_OP_454J1_123_2743_n171) );
AOI22X1TS U5941 ( .A0(n4450), .A1(n2353), .B0(n2285), .B1(n4446), .Y(n4394)
);
OAI22X1TS U5942 ( .A0(n4416), .A1(n4394), .B0(n4413), .B1(n4393), .Y(
DP_OP_454J1_123_2743_n175) );
AOI22X1TS U5943 ( .A0(intadd_4_SUM_9_), .A1(n2285), .B0(n2353), .B1(n4432),
.Y(n4395) );
OAI22X1TS U5944 ( .A0(n4416), .A1(n4395), .B0(n4394), .B1(n4413), .Y(
DP_OP_454J1_123_2743_n176) );
AOI22X1TS U5945 ( .A0(intadd_4_SUM_8_), .A1(n2285), .B0(n2353), .B1(n4434),
.Y(n4396) );
OAI22X1TS U5946 ( .A0(n4416), .A1(n4396), .B0(n4395), .B1(n4413), .Y(
DP_OP_454J1_123_2743_n177) );
AOI22X1TS U5947 ( .A0(intadd_4_SUM_7_), .A1(n2285), .B0(n2353), .B1(n4436),
.Y(n4398) );
OAI22X1TS U5948 ( .A0(n2268), .A1(n4398), .B0(n4396), .B1(n4413), .Y(
DP_OP_454J1_123_2743_n178) );
AOI22X1TS U5949 ( .A0(intadd_4_SUM_6_), .A1(n2285), .B0(n2353), .B1(n4397),
.Y(n4400) );
OAI22X1TS U5950 ( .A0(n4416), .A1(n4400), .B0(n4398), .B1(n4413), .Y(
DP_OP_454J1_123_2743_n179) );
AOI22X1TS U5951 ( .A0(intadd_4_SUM_5_), .A1(n2285), .B0(n2353), .B1(n4399),
.Y(n4402) );
OAI22X1TS U5952 ( .A0(n4416), .A1(n4402), .B0(n4400), .B1(n4413), .Y(
DP_OP_454J1_123_2743_n180) );
AOI22X1TS U5953 ( .A0(intadd_4_SUM_4_), .A1(n2285), .B0(n2284), .B1(n4401),
.Y(n4404) );
OAI22X1TS U5954 ( .A0(n2268), .A1(n4404), .B0(n4402), .B1(n4413), .Y(
DP_OP_454J1_123_2743_n181) );
AOI22X1TS U5955 ( .A0(intadd_4_SUM_3_), .A1(n4411), .B0(n2284), .B1(n4403),
.Y(n4406) );
OAI22X1TS U5956 ( .A0(n2268), .A1(n4406), .B0(n4404), .B1(n4413), .Y(
DP_OP_454J1_123_2743_n182) );
AOI22X1TS U5957 ( .A0(intadd_4_SUM_2_), .A1(n4411), .B0(n2284), .B1(n4405),
.Y(n4408) );
OAI22X1TS U5958 ( .A0(n2268), .A1(n4408), .B0(n4406), .B1(n2367), .Y(
DP_OP_454J1_123_2743_n183) );
AOI22X1TS U5959 ( .A0(intadd_4_SUM_1_), .A1(n4411), .B0(n2284), .B1(n4407),
.Y(n4410) );
OAI22X1TS U5960 ( .A0(n2268), .A1(n4410), .B0(n4408), .B1(n2367), .Y(
DP_OP_454J1_123_2743_n184) );
AOI22X1TS U5961 ( .A0(intadd_4_SUM_0_), .A1(n4411), .B0(n3823), .B1(n4409),
.Y(n4414) );
OAI22X1TS U5962 ( .A0(n2268), .A1(n4414), .B0(n4410), .B1(n2367), .Y(
DP_OP_454J1_123_2743_n185) );
AOI22X1TS U5963 ( .A0(n4412), .A1(n4411), .B0(n2284), .B1(n2250), .Y(n4415)
);
OAI22X1TS U5964 ( .A0(n2268), .A1(n4415), .B0(n4414), .B1(n2367), .Y(
DP_OP_454J1_123_2743_n186) );
AOI22X1TS U5965 ( .A0(n2359), .A1(n4450), .B0(n4446), .B1(n2277), .Y(n4421)
);
OAI22X1TS U5966 ( .A0(n4417), .A1(n4420), .B0(n4421), .B1(n4419), .Y(
DP_OP_454J1_123_2743_n202) );
OAI22X1TS U5967 ( .A0(n4421), .A1(n4420), .B0(n4419), .B1(n4418), .Y(
DP_OP_454J1_123_2743_n203) );
AOI22X1TS U5968 ( .A0(n2297), .A1(n2254), .B0(n4445), .B1(n2296), .Y(n4423)
);
OAI22X1TS U5969 ( .A0(n4422), .A1(n2233), .B0(n4423), .B1(n2631), .Y(
DP_OP_454J1_123_2743_n216) );
AOI22X1TS U5970 ( .A0(n2297), .A1(n4450), .B0(n4446), .B1(n2375), .Y(n4425)
);
OAI22X1TS U5971 ( .A0(n4423), .A1(n4428), .B0(n4425), .B1(n2631), .Y(
DP_OP_454J1_123_2743_n217) );
OAI22X1TS U5972 ( .A0(n4425), .A1(n4428), .B0(n2631), .B1(n4424), .Y(
DP_OP_454J1_123_2743_n218) );
OAI22X1TS U5973 ( .A0(n4428), .A1(n4427), .B0(n4426), .B1(n2631), .Y(
DP_OP_454J1_123_2743_n227) );
AOI22X1TS U5974 ( .A0(n2294), .A1(n2254), .B0(n4445), .B1(n2313), .Y(n4431)
);
NAND3XLTS U5975 ( .A(intadd_5_SUM_1_), .B(n2260), .C(n2314), .Y(n4430) );
AOI22X1TS U5976 ( .A0(n4431), .A1(n4444), .B0(n4430), .B1(n4429), .Y(
DP_OP_454J1_123_2743_n231) );
AOI22X1TS U5977 ( .A0(n2294), .A1(n4450), .B0(n4446), .B1(n2314), .Y(n4433)
);
OAI22X1TS U5978 ( .A0(n4438), .A1(n4433), .B0(n4431), .B1(n4444), .Y(
DP_OP_454J1_123_2743_n232) );
AOI22X1TS U5979 ( .A0(n2295), .A1(n4432), .B0(intadd_4_SUM_9_), .B1(n2314),
.Y(n4435) );
OAI22X1TS U5980 ( .A0(n4438), .A1(n4435), .B0(n4433), .B1(n4444), .Y(
DP_OP_454J1_123_2743_n233) );
AOI22X1TS U5981 ( .A0(n2295), .A1(n4434), .B0(intadd_4_SUM_8_), .B1(n2314),
.Y(n4437) );
OAI22X1TS U5982 ( .A0(n4438), .A1(n4437), .B0(n4444), .B1(n4435), .Y(
DP_OP_454J1_123_2743_n234) );
AOI22X1TS U5983 ( .A0(n2295), .A1(n4436), .B0(intadd_4_SUM_7_), .B1(n2314),
.Y(n4440) );
OAI22X1TS U5984 ( .A0(n4438), .A1(n4440), .B0(n4444), .B1(n4437), .Y(
DP_OP_454J1_123_2743_n235) );
OAI2BB2XLTS U5985 ( .B0(n4444), .B1(n4440), .A0N(n4439), .A1N(n4441), .Y(
DP_OP_454J1_123_2743_n236) );
AOI21X1TS U5986 ( .A0(n4448), .A1(n4445), .B0(n2259), .Y(
DP_OP_454J1_123_2743_n245) );
AOI22X1TS U5987 ( .A0(intadd_5_SUM_0_), .A1(n2255), .B0(n4445), .B1(n2259),
.Y(n4449) );
OAI22X1TS U5988 ( .A0(n4449), .A1(n4448), .B0(n4447), .B1(n4446), .Y(
DP_OP_454J1_123_2743_n246) );
AOI22X1TS U5989 ( .A0(n2938), .A1(n4450), .B0(n2255), .B1(n2624), .Y(n4453)
);
CMPR32X2TS U5990 ( .A(n4454), .B(n4453), .C(n4452), .CO(n4457), .S(
intadd_1_A_19_) );
XNOR2X1TS U5991 ( .A(n4457), .B(n4456), .Y(
FPMULT_Sgf_operation_EVEN1_middle_N25) );
NOR4X1TS U5992 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n4464) );
NOR4X1TS U5993 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n4463) );
NOR4X1TS U5994 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n4461) );
NOR4X1TS U5995 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n4459) );
NOR4X1TS U5996 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n4458) );
AND4X1TS U5997 ( .A(n4461), .B(n4460), .C(n4459), .D(n4458), .Y(n4462) );
NOR4BX1TS U5998 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n4469) );
NOR4X1TS U5999 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n4468) );
NAND4XLTS U6000 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n4466) );
NAND4XLTS U6001 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n4465) );
OR3X1TS U6002 ( .A(n5283), .B(n4466), .C(n4465), .Y(n4470) );
NOR3X1TS U6003 ( .A(dataB[29]), .B(dataB[31]), .C(n4470), .Y(n4467) );
NOR4X1TS U6004 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n4473) );
NOR4X1TS U6005 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n4472) );
NOR4BX1TS U6006 ( .AN(operation_reg[1]), .B(operation_reg[0]), .C(dataA[31]),
.D(n5283), .Y(n4471) );
NOR2X1TS U6007 ( .A(operation_reg[1]), .B(n4470), .Y(n4478) );
NAND4XLTS U6008 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n4474) );
OAI31X1TS U6009 ( .A0(n4476), .A1(n4475), .A2(n4474), .B0(dataB[27]), .Y(
n4477) );
OAI2BB2XLTS U6010 ( .B0(n4480), .B1(n4479), .A0N(n4478), .A1N(
operation_reg[0]), .Y(NaN_reg) );
INVX2TS U6011 ( .A(n4506), .Y(n4508) );
NOR3X1TS U6012 ( .A(n4604), .B(n4482), .C(n4531), .Y(n4483) );
NOR2X1TS U6013 ( .A(n4485), .B(n4484), .Y(n4489) );
OAI22X1TS U6014 ( .A0(n4487), .A1(n4486), .B0(n4489), .B1(n4488), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U6015 ( .AN(n4489), .B(n4488), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
AOI32X1TS U6016 ( .A0(n4492), .A1(n4491), .A2(n4490), .B0(n4515), .B1(n4491),
.Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
OAI22X1TS U6017 ( .A0(n4533), .A1(n4494), .B0(n4516), .B1(n4493), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
OR2X1TS U6018 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .Y(n4495) );
AO22XLTS U6019 ( .A0(operation[2]), .A1(n4495), .B0(n4496), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U6020 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n4496),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
NAND2X1TS U6021 ( .A(n4497), .B(n4503), .Y(n2192) );
OAI222X1TS U6022 ( .A0(n3148), .A1(n4500), .B0(n5064), .B1(n4499), .C0(n2593), .C1(n4498), .Y(operation_ready) );
AOI21X1TS U6023 ( .A0(n4504), .A1(n4503), .B0(n4502), .Y(n2150) );
AOI22X1TS U6024 ( .A0(n4508), .A1(n4948), .B0(n4982), .B1(n4506), .Y(n2148)
);
AOI22X1TS U6025 ( .A0(n4508), .A1(n4982), .B0(n4979), .B1(n4506), .Y(n2147)
);
OAI2BB2XLTS U6026 ( .B0(n4506), .B1(n4979), .A0N(n4506), .A1N(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2146) );
AOI22X1TS U6027 ( .A0(n4508), .A1(n4505), .B0(n5003), .B1(n4506), .Y(n2144)
);
AOI22X1TS U6028 ( .A0(n4508), .A1(n4507), .B0(n4871), .B1(n4506), .Y(n2143)
);
NAND2X1TS U6029 ( .A(n4509), .B(n4553), .Y(n4510) );
OA21XLTS U6030 ( .A0(n4509), .A1(n4553), .B0(n4510), .Y(n2142) );
AOI21X1TS U6031 ( .A0(n5006), .A1(n4510), .B0(n4511), .Y(n2141) );
OA21XLTS U6032 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n4511), .B0(n4513), .Y(
n2140) );
AOI21X1TS U6033 ( .A0(n5054), .A1(n4513), .B0(n4512), .Y(n2139) );
AOI31XLTS U6034 ( .A0(n4516), .A1(n4515), .A2(n5064), .B0(n4988), .Y(n4517)
);
XNOR2X1TS U6035 ( .A(n5049), .B(n4517), .Y(n2137) );
INVX2TS U6036 ( .A(n4529), .Y(n4525) );
OAI2BB2XLTS U6037 ( .B0(n4531), .B1(n4687), .A0N(n4525), .A1N(region_flag[0]), .Y(n2136) );
OAI2BB2XLTS U6038 ( .B0(n4531), .B1(n2223), .A0N(n4525), .A1N(region_flag[1]), .Y(n2135) );
BUFX3TS U6039 ( .A(n4567), .Y(n4569) );
INVX2TS U6040 ( .A(n4569), .Y(n4609) );
INVX2TS U6041 ( .A(n4569), .Y(n4599) );
OAI2BB2XLTS U6042 ( .B0(n4520), .B1(n4519), .A0N(FPSENCOS_d_ff3_LUT_out[13]),
.A1N(n4599), .Y(n2122) );
OAI2BB1X1TS U6043 ( .A0N(FPSENCOS_d_ff3_LUT_out[19]), .A1N(n4609), .B0(n4520), .Y(n2120) );
INVX2TS U6044 ( .A(n4569), .Y(n4580) );
AOI21X1TS U6045 ( .A0(n4602), .A1(FPSENCOS_cont_iter_out[3]), .B0(n4524),
.Y(n2115) );
BUFX3TS U6046 ( .A(n4529), .Y(n4526) );
INVX2TS U6047 ( .A(n4529), .Y(n4528) );
INVX2TS U6048 ( .A(n4529), .Y(n4530) );
INVX2TS U6049 ( .A(n4533), .Y(n4672) );
OAI2BB2XLTS U6050 ( .B0(n4536), .B1(n4963), .A0N(n4672), .A1N(
FPSENCOS_d_ff_Zn[0]), .Y(n2075) );
BUFX3TS U6051 ( .A(n4534), .Y(n4539) );
OAI2BB2XLTS U6052 ( .B0(n4539), .B1(n4963), .A0N(n4535), .A1N(
FPSENCOS_d_ff_Yn[0]), .Y(n2074) );
OAI2BB2XLTS U6053 ( .B0(n4673), .B1(n4966), .A0N(n4672), .A1N(
FPSENCOS_d_ff_Zn[1]), .Y(n2072) );
BUFX3TS U6054 ( .A(n4676), .Y(n4538) );
OAI2BB2XLTS U6055 ( .B0(n4538), .B1(n4966), .A0N(n4676), .A1N(
FPSENCOS_d_ff_Xn[1]), .Y(n2070) );
INVX2TS U6056 ( .A(n4533), .Y(n4664) );
OAI2BB2XLTS U6057 ( .B0(n4536), .B1(n4957), .A0N(n4664), .A1N(
FPSENCOS_d_ff_Zn[2]), .Y(n2069) );
BUFX3TS U6058 ( .A(n4534), .Y(n4666) );
OAI2BB2XLTS U6059 ( .B0(n4539), .B1(n4957), .A0N(n4666), .A1N(
FPSENCOS_d_ff_Yn[2]), .Y(n2068) );
BUFX3TS U6060 ( .A(n4544), .Y(n4670) );
OAI2BB2XLTS U6061 ( .B0(n4540), .B1(n4957), .A0N(n4670), .A1N(
FPSENCOS_d_ff_Xn[2]), .Y(n2067) );
OAI2BB2XLTS U6062 ( .B0(n4536), .B1(n4954), .A0N(n4664), .A1N(
FPSENCOS_d_ff_Zn[3]), .Y(n2066) );
OAI2BB2XLTS U6063 ( .B0(n4537), .B1(n4954), .A0N(n4666), .A1N(
FPSENCOS_d_ff_Yn[3]), .Y(n2065) );
OAI2BB2XLTS U6064 ( .B0(n4538), .B1(n4954), .A0N(n4670), .A1N(
FPSENCOS_d_ff_Xn[3]), .Y(n2064) );
OAI2BB2XLTS U6065 ( .B0(n4673), .B1(n4883), .A0N(n4664), .A1N(
FPSENCOS_d_ff_Zn[4]), .Y(n2063) );
OAI2BB2XLTS U6066 ( .B0(n4537), .B1(n4883), .A0N(n4666), .A1N(
FPSENCOS_d_ff_Yn[4]), .Y(n2062) );
OAI2BB2XLTS U6067 ( .B0(n4538), .B1(n4883), .A0N(n4670), .A1N(
FPSENCOS_d_ff_Xn[4]), .Y(n2061) );
INVX2TS U6068 ( .A(n4533), .Y(n4545) );
OAI2BB2XLTS U6069 ( .B0(n4673), .B1(n4974), .A0N(n4545), .A1N(
FPSENCOS_d_ff_Zn[5]), .Y(n2060) );
BUFX3TS U6070 ( .A(n4534), .Y(n4565) );
OAI2BB2XLTS U6071 ( .B0(n4537), .B1(n4974), .A0N(n4565), .A1N(
FPSENCOS_d_ff_Yn[5]), .Y(n2059) );
OAI2BB2XLTS U6072 ( .B0(n4538), .B1(n4974), .A0N(n4544), .A1N(
FPSENCOS_d_ff_Xn[5]), .Y(n2058) );
OAI2BB2XLTS U6073 ( .B0(n4673), .B1(n4886), .A0N(n4545), .A1N(
FPSENCOS_d_ff_Zn[6]), .Y(n2057) );
OAI2BB2XLTS U6074 ( .B0(n4537), .B1(n4886), .A0N(n4565), .A1N(
FPSENCOS_d_ff_Yn[6]), .Y(n2056) );
OAI2BB2XLTS U6075 ( .B0(n4538), .B1(n4886), .A0N(n4544), .A1N(
FPSENCOS_d_ff_Xn[6]), .Y(n2055) );
OAI2BB2XLTS U6076 ( .B0(n4673), .B1(n4960), .A0N(n4545), .A1N(
FPSENCOS_d_ff_Zn[7]), .Y(n2054) );
OAI2BB2XLTS U6077 ( .B0(n4537), .B1(n4960), .A0N(n4565), .A1N(
FPSENCOS_d_ff_Yn[7]), .Y(n2053) );
OAI2BB2XLTS U6078 ( .B0(n4538), .B1(n4960), .A0N(n2662), .A1N(
FPSENCOS_d_ff_Xn[7]), .Y(n2052) );
OAI2BB2XLTS U6079 ( .B0(n4537), .B1(n4893), .A0N(n4539), .A1N(
FPSENCOS_d_ff_Yn[8]), .Y(n2050) );
OAI2BB2XLTS U6080 ( .B0(n4538), .B1(n4893), .A0N(n4540), .A1N(
FPSENCOS_d_ff_Xn[8]), .Y(n2049) );
OAI2BB2XLTS U6081 ( .B0(n4673), .B1(n4969), .A0N(n4545), .A1N(
FPSENCOS_d_ff_Zn[9]), .Y(n2048) );
OAI2BB2XLTS U6082 ( .B0(n4537), .B1(n4969), .A0N(n4565), .A1N(
FPSENCOS_d_ff_Yn[9]), .Y(n2047) );
OAI2BB2XLTS U6083 ( .B0(n4538), .B1(n4969), .A0N(n2662), .A1N(
FPSENCOS_d_ff_Xn[9]), .Y(n2046) );
OAI2BB2XLTS U6084 ( .B0(n4537), .B1(n4900), .A0N(n4539), .A1N(
FPSENCOS_d_ff_Yn[10]), .Y(n2044) );
OAI2BB2XLTS U6085 ( .B0(n4538), .B1(n4900), .A0N(n4540), .A1N(
FPSENCOS_d_ff_Xn[10]), .Y(n2043) );
OAI2BB2XLTS U6086 ( .B0(n4541), .B1(n4896), .A0N(n4539), .A1N(
FPSENCOS_d_ff_Yn[11]), .Y(n2041) );
OAI2BB2XLTS U6087 ( .B0(n4542), .B1(n4896), .A0N(n4540), .A1N(
FPSENCOS_d_ff_Xn[11]), .Y(n2040) );
OAI2BB2XLTS U6088 ( .B0(n4541), .B1(n4903), .A0N(n4539), .A1N(
FPSENCOS_d_ff_Yn[12]), .Y(n2038) );
OAI2BB2XLTS U6089 ( .B0(n4542), .B1(n4903), .A0N(n4540), .A1N(
FPSENCOS_d_ff_Xn[12]), .Y(n2037) );
OAI2BB2XLTS U6090 ( .B0(n4541), .B1(n4888), .A0N(n4539), .A1N(
FPSENCOS_d_ff_Yn[13]), .Y(n2035) );
OAI2BB2XLTS U6091 ( .B0(n4542), .B1(n4888), .A0N(n4540), .A1N(
FPSENCOS_d_ff_Xn[13]), .Y(n2034) );
OAI2BB2XLTS U6092 ( .B0(n4541), .B1(n4898), .A0N(n4539), .A1N(
FPSENCOS_d_ff_Yn[14]), .Y(n2032) );
OAI2BB2XLTS U6093 ( .B0(n4542), .B1(n4898), .A0N(n4540), .A1N(
FPSENCOS_d_ff_Xn[14]), .Y(n2031) );
OAI2BB2XLTS U6094 ( .B0(n4543), .B1(n4868), .A0N(n4545), .A1N(
FPSENCOS_d_ff_Zn[15]), .Y(n2030) );
OAI2BB2XLTS U6095 ( .B0(n4537), .B1(n4868), .A0N(n4565), .A1N(
FPSENCOS_d_ff_Yn[15]), .Y(n2029) );
OAI2BB2XLTS U6096 ( .B0(n4538), .B1(n4868), .A0N(n2662), .A1N(
FPSENCOS_d_ff_Xn[15]), .Y(n2028) );
OAI2BB2XLTS U6097 ( .B0(n4541), .B1(n4890), .A0N(n4539), .A1N(
FPSENCOS_d_ff_Yn[16]), .Y(n2026) );
OAI2BB2XLTS U6098 ( .B0(n4542), .B1(n4890), .A0N(n4540), .A1N(
FPSENCOS_d_ff_Xn[16]), .Y(n2025) );
OAI2BB2XLTS U6099 ( .B0(n4543), .B1(n4879), .A0N(n4545), .A1N(
FPSENCOS_d_ff_Zn[17]), .Y(n2024) );
OAI2BB2XLTS U6100 ( .B0(n4541), .B1(n4879), .A0N(n4539), .A1N(
FPSENCOS_d_ff_Yn[17]), .Y(n2023) );
OAI2BB2XLTS U6101 ( .B0(n4542), .B1(n4879), .A0N(n4540), .A1N(
FPSENCOS_d_ff_Xn[17]), .Y(n2022) );
OAI2BB2XLTS U6102 ( .B0(n4543), .B1(n4870), .A0N(n4545), .A1N(
FPSENCOS_d_ff_Zn[18]), .Y(n2021) );
OAI2BB2XLTS U6103 ( .B0(n4541), .B1(n4870), .A0N(n4565), .A1N(
FPSENCOS_d_ff_Yn[18]), .Y(n2020) );
OAI2BB2XLTS U6104 ( .B0(n4542), .B1(n4870), .A0N(n4544), .A1N(
FPSENCOS_d_ff_Xn[18]), .Y(n2019) );
OAI2BB2XLTS U6105 ( .B0(n4543), .B1(n4875), .A0N(n4545), .A1N(
FPSENCOS_d_ff_Zn[19]), .Y(n2018) );
OAI2BB2XLTS U6106 ( .B0(n4541), .B1(n4875), .A0N(n4565), .A1N(
FPSENCOS_d_ff_Yn[19]), .Y(n2017) );
OAI2BB2XLTS U6107 ( .B0(n4542), .B1(n4875), .A0N(n4544), .A1N(
FPSENCOS_d_ff_Xn[19]), .Y(n2016) );
OAI2BB2XLTS U6108 ( .B0(n4543), .B1(n4877), .A0N(n4545), .A1N(
FPSENCOS_d_ff_Zn[20]), .Y(n2015) );
OAI2BB2XLTS U6109 ( .B0(n4541), .B1(n4877), .A0N(n4565), .A1N(
FPSENCOS_d_ff_Yn[20]), .Y(n2014) );
OAI2BB2XLTS U6110 ( .B0(n4542), .B1(n4877), .A0N(n4544), .A1N(
FPSENCOS_d_ff_Xn[20]), .Y(n2013) );
OAI2BB2XLTS U6111 ( .B0(n4543), .B1(n4873), .A0N(n4664), .A1N(
FPSENCOS_d_ff_Zn[21]), .Y(n2012) );
OAI2BB2XLTS U6112 ( .B0(n4667), .B1(n4873), .A0N(n4666), .A1N(
FPSENCOS_d_ff_Yn[21]), .Y(n2011) );
BUFX3TS U6113 ( .A(n4544), .Y(n4678) );
OAI2BB2XLTS U6114 ( .B0(n4678), .B1(n4873), .A0N(n4670), .A1N(
FPSENCOS_d_ff_Xn[21]), .Y(n2010) );
OAI2BB2XLTS U6115 ( .B0(n4669), .B1(n4864), .A0N(n4545), .A1N(
FPSENCOS_d_ff_Zn[22]), .Y(n2009) );
OAI2BB2XLTS U6116 ( .B0(n4667), .B1(n4864), .A0N(n4565), .A1N(
FPSENCOS_d_ff_Yn[22]), .Y(n2008) );
OAI2BB2XLTS U6117 ( .B0(n4678), .B1(n4864), .A0N(n4676), .A1N(
FPSENCOS_d_ff_Xn[22]), .Y(n2007) );
INVX2TS U6118 ( .A(n5279), .Y(n4549) );
OAI2BB2XLTS U6119 ( .B0(n4558), .B1(n2393), .A0N(n4557), .A1N(
FPSENCOS_d_ff2_X[0]), .Y(n2005) );
BUFX3TS U6120 ( .A(n4578), .Y(n4550) );
OA22X1TS U6121 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n4552), .B0(
FPSENCOS_d_ff2_X[1]), .B1(n4550), .Y(n2004) );
OAI2BB2XLTS U6122 ( .B0(n4602), .B1(n2396), .A0N(n4569), .A1N(
FPSENCOS_d_ff2_X[1]), .Y(n2003) );
OA22X1TS U6123 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n2345), .B0(
FPSENCOS_d_ff2_X[2]), .B1(n5279), .Y(n2002) );
OAI2BB2XLTS U6124 ( .B0(n4558), .B1(n2403), .A0N(n4557), .A1N(
FPSENCOS_d_ff2_X[2]), .Y(n2001) );
OA22X1TS U6125 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n3220), .B0(
FPSENCOS_d_ff2_X[3]), .B1(n5279), .Y(n2000) );
OAI2BB2XLTS U6126 ( .B0(n4558), .B1(n2397), .A0N(n4557), .A1N(
FPSENCOS_d_ff2_X[4]), .Y(n1997) );
OA22X1TS U6127 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n3220), .B0(
FPSENCOS_d_ff2_X[5]), .B1(n5279), .Y(n1996) );
OA22X1TS U6128 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n2345), .B0(
FPSENCOS_d_ff2_X[6]), .B1(n5279), .Y(n1994) );
OAI2BB2XLTS U6129 ( .B0(n4558), .B1(n2399), .A0N(n4557), .A1N(
FPSENCOS_d_ff2_X[6]), .Y(n1993) );
OA22X1TS U6130 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n3220), .B0(
FPSENCOS_d_ff2_X[7]), .B1(n5279), .Y(n1992) );
OAI2BB2XLTS U6131 ( .B0(n4558), .B1(n2388), .A0N(n4557), .A1N(
FPSENCOS_d_ff2_X[8]), .Y(n1989) );
OAI2BB2XLTS U6132 ( .B0(n4558), .B1(n2398), .A0N(n4557), .A1N(
FPSENCOS_d_ff2_X[9]), .Y(n1987) );
OA22X1TS U6133 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n4552), .B0(
FPSENCOS_d_ff2_X[10]), .B1(n5279), .Y(n1986) );
OAI2BB2XLTS U6134 ( .B0(n4558), .B1(n2389), .A0N(n4569), .A1N(
FPSENCOS_d_ff2_X[10]), .Y(n1985) );
OA22X1TS U6135 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n3220), .B0(
FPSENCOS_d_ff2_X[12]), .B1(n5279), .Y(n1982) );
OAI2BB2XLTS U6136 ( .B0(n4558), .B1(n2391), .A0N(n4557), .A1N(
FPSENCOS_d_ff2_X[12]), .Y(n1981) );
OA22X1TS U6137 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n3220), .B0(
FPSENCOS_d_ff2_X[13]), .B1(n4550), .Y(n1980) );
OA22X1TS U6138 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n3220), .B0(
FPSENCOS_d_ff2_X[14]), .B1(n4550), .Y(n1978) );
OA22X1TS U6139 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n3220), .B0(
FPSENCOS_d_ff2_X[16]), .B1(n4550), .Y(n1974) );
OA22X1TS U6140 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n3220), .B0(
FPSENCOS_d_ff2_X[17]), .B1(n5279), .Y(n1972) );
BUFX3TS U6141 ( .A(n2344), .Y(n4571) );
OA22X1TS U6142 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n3220), .B0(
FPSENCOS_d_ff2_X[19]), .B1(n4550), .Y(n1968) );
OA22X1TS U6143 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n4552), .B0(
FPSENCOS_d_ff2_X[20]), .B1(n4550), .Y(n1966) );
OAI2BB2XLTS U6144 ( .B0(n4675), .B1(n2390), .A0N(n4557), .A1N(
FPSENCOS_d_ff2_X[21]), .Y(n1963) );
OA22X1TS U6145 ( .A0(FPSENCOS_d_ff_Xn[24]), .A1(n4552), .B0(
FPSENCOS_d_ff2_X[24]), .B1(n4550), .Y(n1959) );
OA22X1TS U6146 ( .A0(FPSENCOS_d_ff_Xn[25]), .A1(n4552), .B0(
FPSENCOS_d_ff2_X[25]), .B1(n4550), .Y(n1958) );
OA22X1TS U6147 ( .A0(FPSENCOS_d_ff_Xn[26]), .A1(n4552), .B0(
FPSENCOS_d_ff2_X[26]), .B1(n4550), .Y(n1957) );
OA22X1TS U6148 ( .A0(FPSENCOS_d_ff_Xn[27]), .A1(n4552), .B0(
FPSENCOS_d_ff2_X[27]), .B1(n4550), .Y(n1956) );
BUFX3TS U6149 ( .A(n4578), .Y(n4577) );
OA22X1TS U6150 ( .A0(FPSENCOS_d_ff_Xn[29]), .A1(n4552), .B0(
FPSENCOS_d_ff2_X[29]), .B1(n4577), .Y(n1954) );
NAND2X1TS U6151 ( .A(FPSENCOS_d_ff2_X[23]), .B(n4554), .Y(n4556) );
AOI32X1TS U6152 ( .A0(intadd_8_CI), .A1(n4604), .A2(n4556), .B0(n4555), .B1(
n4603), .Y(n1952) );
OAI2BB2XLTS U6153 ( .B0(n4558), .B1(n2402), .A0N(n4557), .A1N(
intadd_8_SUM_2_), .Y(n1949) );
AOI21X1TS U6154 ( .A0(intadd_8_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4559),
.Y(n4560) );
AOI21X1TS U6155 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n4562), .B0(n4561), .Y(
n4563) );
OAI2BB2XLTS U6156 ( .B0(n4669), .B1(n4566), .A0N(n4664), .A1N(
FPSENCOS_d_ff_Zn[31]), .Y(n1910) );
OAI2BB2XLTS U6157 ( .B0(n4667), .B1(n4566), .A0N(n4565), .A1N(
FPSENCOS_d_ff_Yn[31]), .Y(n1909) );
OAI2BB2XLTS U6158 ( .B0(n4568), .B1(n4577), .A0N(FPSENCOS_d_ff_Yn[0]), .A1N(
n4571), .Y(n1908) );
INVX2TS U6159 ( .A(n4567), .Y(n4595) );
OAI2BB2XLTS U6160 ( .B0(n4595), .B1(n4568), .A0N(n4609), .A1N(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1907) );
OAI2BB2XLTS U6161 ( .B0(n2395), .B1(n4577), .A0N(FPSENCOS_d_ff_Yn[1]), .A1N(
n4571), .Y(n1906) );
INVX2TS U6162 ( .A(n4569), .Y(n4591) );
OAI2BB2XLTS U6163 ( .B0(n4599), .B1(n2395), .A0N(n4591), .A1N(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1905) );
OAI2BB2XLTS U6164 ( .B0(n4570), .B1(n4577), .A0N(FPSENCOS_d_ff_Yn[2]), .A1N(
n4571), .Y(n1904) );
OAI2BB2XLTS U6165 ( .B0(n4599), .B1(n4570), .A0N(n4591), .A1N(
FPSENCOS_d_ff3_sh_y_out[2]), .Y(n1903) );
OAI2BB2XLTS U6166 ( .B0(n4572), .B1(n4577), .A0N(FPSENCOS_d_ff_Yn[3]), .A1N(
n4571), .Y(n1902) );
OAI2BB2XLTS U6167 ( .B0(n4595), .B1(n4572), .A0N(n4580), .A1N(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1901) );
BUFX3TS U6168 ( .A(n2344), .Y(n4584) );
OAI2BB2XLTS U6169 ( .B0(n4573), .B1(n4577), .A0N(FPSENCOS_d_ff_Yn[4]), .A1N(
n4584), .Y(n1900) );
OAI2BB2XLTS U6170 ( .B0(n4599), .B1(n4573), .A0N(n4609), .A1N(
FPSENCOS_d_ff3_sh_y_out[4]), .Y(n1899) );
OAI2BB2XLTS U6171 ( .B0(n4574), .B1(n4577), .A0N(FPSENCOS_d_ff_Yn[5]), .A1N(
n4584), .Y(n1898) );
OAI2BB2XLTS U6172 ( .B0(n4599), .B1(n4574), .A0N(n4580), .A1N(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1897) );
OAI2BB2XLTS U6173 ( .B0(n4575), .B1(n4577), .A0N(FPSENCOS_d_ff_Yn[6]), .A1N(
n4584), .Y(n1896) );
OAI2BB2XLTS U6174 ( .B0(n4599), .B1(n4575), .A0N(n4580), .A1N(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1895) );
OAI2BB2XLTS U6175 ( .B0(n4576), .B1(n4577), .A0N(FPSENCOS_d_ff_Yn[7]), .A1N(
n4584), .Y(n1894) );
OAI2BB2XLTS U6176 ( .B0(n4599), .B1(n4576), .A0N(n4580), .A1N(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1893) );
OAI2BB2XLTS U6177 ( .B0(n2385), .B1(n4577), .A0N(FPSENCOS_d_ff_Yn[8]), .A1N(
n4584), .Y(n1892) );
OAI2BB2XLTS U6178 ( .B0(n4595), .B1(n2385), .A0N(n4580), .A1N(
FPSENCOS_d_ff3_sh_y_out[8]), .Y(n1891) );
BUFX3TS U6179 ( .A(n4578), .Y(n4589) );
OAI2BB2XLTS U6180 ( .B0(n4579), .B1(n4589), .A0N(FPSENCOS_d_ff_Yn[9]), .A1N(
n4584), .Y(n1890) );
OAI2BB2XLTS U6181 ( .B0(n4595), .B1(n4579), .A0N(n4580), .A1N(
FPSENCOS_d_ff3_sh_y_out[9]), .Y(n1889) );
OAI2BB2XLTS U6182 ( .B0(n4581), .B1(n4589), .A0N(FPSENCOS_d_ff_Yn[10]),
.A1N(n4584), .Y(n1888) );
OAI2BB2XLTS U6183 ( .B0(n4599), .B1(n4581), .A0N(n4580), .A1N(
FPSENCOS_d_ff3_sh_y_out[10]), .Y(n1887) );
OAI2BB2XLTS U6184 ( .B0(n4582), .B1(n4589), .A0N(FPSENCOS_d_ff_Yn[11]),
.A1N(n4584), .Y(n1886) );
OAI2BB2XLTS U6185 ( .B0(n4599), .B1(n4582), .A0N(n4591), .A1N(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1885) );
OAI2BB2XLTS U6186 ( .B0(n4583), .B1(n4589), .A0N(FPSENCOS_d_ff_Yn[12]),
.A1N(n4584), .Y(n1884) );
OAI2BB2XLTS U6187 ( .B0(n4595), .B1(n4583), .A0N(n4591), .A1N(
FPSENCOS_d_ff3_sh_y_out[12]), .Y(n1883) );
OAI2BB2XLTS U6188 ( .B0(n4585), .B1(n4589), .A0N(FPSENCOS_d_ff_Yn[13]),
.A1N(n4584), .Y(n1882) );
OAI2BB2XLTS U6189 ( .B0(n4595), .B1(n4585), .A0N(n4591), .A1N(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1881) );
BUFX3TS U6190 ( .A(n2344), .Y(n4597) );
OAI2BB2XLTS U6191 ( .B0(n4586), .B1(n4589), .A0N(FPSENCOS_d_ff_Yn[14]),
.A1N(n4597), .Y(n1880) );
OAI2BB2XLTS U6192 ( .B0(n4611), .B1(n4586), .A0N(n4609), .A1N(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1879) );
OAI2BB2XLTS U6193 ( .B0(n2380), .B1(n4589), .A0N(FPSENCOS_d_ff_Yn[15]),
.A1N(n4597), .Y(n1878) );
OAI2BB2XLTS U6194 ( .B0(n4587), .B1(n4589), .A0N(FPSENCOS_d_ff_Yn[16]),
.A1N(n4597), .Y(n1876) );
OAI2BB2XLTS U6195 ( .B0(n4595), .B1(n4587), .A0N(n4591), .A1N(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1875) );
OAI2BB2XLTS U6196 ( .B0(n4588), .B1(n4589), .A0N(FPSENCOS_d_ff_Yn[17]),
.A1N(n4597), .Y(n1874) );
OAI2BB2XLTS U6197 ( .B0(n4611), .B1(n4588), .A0N(n4591), .A1N(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1873) );
OAI2BB2XLTS U6198 ( .B0(n4590), .B1(n4589), .A0N(FPSENCOS_d_ff_Yn[18]),
.A1N(n4597), .Y(n1872) );
OAI2BB2XLTS U6199 ( .B0(n4595), .B1(n4590), .A0N(n4591), .A1N(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1871) );
OAI2BB2XLTS U6200 ( .B0(n4592), .B1(n4598), .A0N(FPSENCOS_d_ff_Yn[19]),
.A1N(n4597), .Y(n1870) );
OAI2BB2XLTS U6201 ( .B0(n4595), .B1(n4592), .A0N(n4591), .A1N(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1869) );
OAI2BB2XLTS U6202 ( .B0(n4593), .B1(n4598), .A0N(FPSENCOS_d_ff_Yn[20]),
.A1N(n4597), .Y(n1868) );
OAI2BB2XLTS U6203 ( .B0(n4611), .B1(n4593), .A0N(n4609), .A1N(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1867) );
OAI2BB2XLTS U6204 ( .B0(n4594), .B1(n4608), .A0N(FPSENCOS_d_ff_Yn[21]),
.A1N(n4597), .Y(n1866) );
OAI2BB2XLTS U6205 ( .B0(n4595), .B1(n4594), .A0N(n4609), .A1N(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1865) );
OAI2BB2XLTS U6206 ( .B0(n4596), .B1(n4608), .A0N(FPSENCOS_d_ff_Yn[22]),
.A1N(n4597), .Y(n1864) );
OAI2BB2XLTS U6207 ( .B0(n4611), .B1(n4596), .A0N(n4609), .A1N(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1863) );
OAI2BB2XLTS U6208 ( .B0(n4996), .B1(n4598), .A0N(FPSENCOS_d_ff_Yn[23]),
.A1N(n4597), .Y(n1862) );
OAI2BB2XLTS U6209 ( .B0(n5126), .B1(n4598), .A0N(FPSENCOS_d_ff_Yn[24]),
.A1N(n4607), .Y(n1861) );
OAI2BB2XLTS U6210 ( .B0(n5127), .B1(n4598), .A0N(FPSENCOS_d_ff_Yn[25]),
.A1N(n4607), .Y(n1860) );
OAI2BB2XLTS U6211 ( .B0(n5128), .B1(n4598), .A0N(FPSENCOS_d_ff_Yn[26]),
.A1N(n4607), .Y(n1859) );
OAI2BB2XLTS U6212 ( .B0(n5092), .B1(n4598), .A0N(FPSENCOS_d_ff_Yn[27]),
.A1N(n4607), .Y(n1858) );
OAI2BB2XLTS U6213 ( .B0(n5089), .B1(n4598), .A0N(FPSENCOS_d_ff_Yn[28]),
.A1N(n4607), .Y(n1857) );
OAI2BB2XLTS U6214 ( .B0(n5088), .B1(n4608), .A0N(FPSENCOS_d_ff_Yn[29]),
.A1N(n4607), .Y(n1856) );
OAI2BB2XLTS U6215 ( .B0(n5125), .B1(n4608), .A0N(FPSENCOS_d_ff_Yn[30]),
.A1N(n4607), .Y(n1855) );
AOI21X1TS U6216 ( .A0(intadd_7_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n4600),
.Y(n4601) );
AOI22X1TS U6217 ( .A0(n4604), .A1(n5125), .B0(FPSENCOS_d_ff3_sh_y_out[30]),
.B1(n4603), .Y(n4606) );
MXI2X1TS U6218 ( .A(n4606), .B(n5125), .S0(n4605), .Y(n1847) );
OAI2BB2XLTS U6219 ( .B0(n4610), .B1(n4608), .A0N(FPSENCOS_d_ff_Yn[31]),
.A1N(n4607), .Y(n1846) );
OAI2BB2XLTS U6220 ( .B0(n4611), .B1(n4610), .A0N(n4609), .A1N(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1845) );
AOI22X1TS U6221 ( .A0(Data_2[3]), .A1(n4616), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n4619), .Y(n4613) );
AOI22X1TS U6222 ( .A0(n4641), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n2333),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n4612) );
NAND2X1TS U6223 ( .A(n3242), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n4630) );
AOI22X1TS U6224 ( .A0(Data_2[5]), .A1(n4616), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n4619), .Y(n4615) );
AOI22X1TS U6225 ( .A0(n4641), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n2332),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n4614) );
NAND2X1TS U6226 ( .A(n4649), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n4625) );
AOI22X1TS U6227 ( .A0(Data_2[7]), .A1(n4616), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n4619), .Y(n4618) );
AOI22X1TS U6228 ( .A0(n4682), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n2333),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n4617) );
NAND2X1TS U6229 ( .A(n4649), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n4620) );
AOI22X1TS U6230 ( .A0(Data_2[11]), .A1(n4633), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n4619), .Y(n4622) );
AOI22X1TS U6231 ( .A0(n4641), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n2332),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n4621) );
AOI22X1TS U6232 ( .A0(Data_2[13]), .A1(n4633), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n4645), .Y(n4624) );
AOI22X1TS U6233 ( .A0(n4682), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n2333),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n4623) );
NAND2X1TS U6234 ( .A(n4649), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n4636) );
AOI22X1TS U6235 ( .A0(Data_2[14]), .A1(n4633), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n4645), .Y(n4627) );
AOI22X1TS U6236 ( .A0(n4641), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n2332),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n4626) );
AOI22X1TS U6237 ( .A0(Data_2[15]), .A1(n4633), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n4645), .Y(n4629) );
AOI22X1TS U6238 ( .A0(n4641), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n4681),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n4628) );
NAND2X1TS U6239 ( .A(n4649), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n4642) );
AOI22X1TS U6240 ( .A0(Data_2[16]), .A1(n4633), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n4645), .Y(n4632) );
AOI22X1TS U6241 ( .A0(n4641), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n2333),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n4631) );
AOI22X1TS U6242 ( .A0(Data_2[17]), .A1(n4633), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n4645), .Y(n4635) );
AOI22X1TS U6243 ( .A0(n4682), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n4681),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n4634) );
AOI22X1TS U6244 ( .A0(Data_2[18]), .A1(n3298), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n4645), .Y(n4638) );
AOI22X1TS U6245 ( .A0(n4641), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n2332),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n4637) );
AOI22X1TS U6246 ( .A0(Data_2[19]), .A1(n3298), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n4645), .Y(n4640) );
AOI22X1TS U6247 ( .A0(n4682), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n2333),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n4639) );
NAND2X1TS U6248 ( .A(n4649), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n4646) );
AOI22X1TS U6249 ( .A0(Data_2[20]), .A1(n4680), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n4645), .Y(n4644) );
AOI22X1TS U6250 ( .A0(n4641), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n2333),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n4643) );
AOI22X1TS U6251 ( .A0(Data_2[22]), .A1(n4680), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n4645), .Y(n4648) );
AOI22X1TS U6252 ( .A0(n4682), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n2332),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n4647) );
AOI22X1TS U6253 ( .A0(Data_2[27]), .A1(n4680), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n4679), .Y(n4651) );
AOI22X1TS U6254 ( .A0(n4682), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n2333),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n4650) );
NAND2X1TS U6255 ( .A(n4649), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n4655) );
AOI22X1TS U6256 ( .A0(Data_2[28]), .A1(n4680), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n4679), .Y(n4653) );
AOI22X1TS U6257 ( .A0(n4682), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n2332),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n4652) );
AOI22X1TS U6258 ( .A0(Data_2[29]), .A1(n4654), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n4679), .Y(n4657) );
AOI22X1TS U6259 ( .A0(n4682), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n2332),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n4656) );
OAI22X1TS U6260 ( .A0(n4659), .A1(n4658), .B0(n3392), .B1(n2438), .Y(n1813)
);
OAI2BB2XLTS U6261 ( .B0(n4669), .B1(n4660), .A0N(n4664), .A1N(
FPSENCOS_d_ff_Zn[23]), .Y(n1787) );
OAI2BB2XLTS U6262 ( .B0(n4667), .B1(n4660), .A0N(n4666), .A1N(
FPSENCOS_d_ff_Yn[23]), .Y(n1786) );
OAI2BB2XLTS U6263 ( .B0(n4678), .B1(n4660), .A0N(n4676), .A1N(
FPSENCOS_d_ff_Xn[23]), .Y(n1785) );
OAI2BB2XLTS U6264 ( .B0(n4669), .B1(n4661), .A0N(n4664), .A1N(
FPSENCOS_d_ff_Zn[24]), .Y(n1784) );
OAI2BB2XLTS U6265 ( .B0(n4667), .B1(n4661), .A0N(n4666), .A1N(
FPSENCOS_d_ff_Yn[24]), .Y(n1783) );
OAI2BB2XLTS U6266 ( .B0(n4678), .B1(n4661), .A0N(n4670), .A1N(
FPSENCOS_d_ff_Xn[24]), .Y(n1782) );
OAI2BB2XLTS U6267 ( .B0(n4669), .B1(n4662), .A0N(n4664), .A1N(
FPSENCOS_d_ff_Zn[25]), .Y(n1781) );
OAI2BB2XLTS U6268 ( .B0(n4667), .B1(n4662), .A0N(n4666), .A1N(
FPSENCOS_d_ff_Yn[25]), .Y(n1780) );
OAI2BB2XLTS U6269 ( .B0(n4678), .B1(n4662), .A0N(n4670), .A1N(
FPSENCOS_d_ff_Xn[25]), .Y(n1779) );
OAI2BB2XLTS U6270 ( .B0(n4669), .B1(n4663), .A0N(n4664), .A1N(
FPSENCOS_d_ff_Zn[26]), .Y(n1778) );
OAI2BB2XLTS U6271 ( .B0(n4667), .B1(n4663), .A0N(n4666), .A1N(
FPSENCOS_d_ff_Yn[26]), .Y(n1777) );
OAI2BB2XLTS U6272 ( .B0(n4678), .B1(n4663), .A0N(n4670), .A1N(
FPSENCOS_d_ff_Xn[26]), .Y(n1776) );
OAI2BB2XLTS U6273 ( .B0(n4669), .B1(n4665), .A0N(n4664), .A1N(
FPSENCOS_d_ff_Zn[27]), .Y(n1775) );
OAI2BB2XLTS U6274 ( .B0(n4667), .B1(n4665), .A0N(n4666), .A1N(
FPSENCOS_d_ff_Yn[27]), .Y(n1774) );
OAI2BB2XLTS U6275 ( .B0(n4678), .B1(n4665), .A0N(n4670), .A1N(
FPSENCOS_d_ff_Xn[27]), .Y(n1773) );
OAI2BB2XLTS U6276 ( .B0(n4669), .B1(n4668), .A0N(n4672), .A1N(
FPSENCOS_d_ff_Zn[28]), .Y(n1772) );
OAI2BB2XLTS U6277 ( .B0(n4667), .B1(n4668), .A0N(n4666), .A1N(
FPSENCOS_d_ff_Yn[28]), .Y(n1771) );
OAI2BB2XLTS U6278 ( .B0(n4678), .B1(n4668), .A0N(n4670), .A1N(
FPSENCOS_d_ff_Xn[28]), .Y(n1770) );
OAI2BB2XLTS U6279 ( .B0(n4669), .B1(n4671), .A0N(n4672), .A1N(
FPSENCOS_d_ff_Zn[29]), .Y(n1769) );
OAI2BB2XLTS U6280 ( .B0(n4678), .B1(n4671), .A0N(n4670), .A1N(
FPSENCOS_d_ff_Xn[29]), .Y(n1767) );
OAI2BB2XLTS U6281 ( .B0(n4673), .B1(n4677), .A0N(n4672), .A1N(
FPSENCOS_d_ff_Zn[30]), .Y(n1766) );
OAI2BB2XLTS U6282 ( .B0(n4678), .B1(n4677), .A0N(n4676), .A1N(
FPSENCOS_d_ff_Xn[30]), .Y(n1730) );
AOI22X1TS U6283 ( .A0(Data_2[31]), .A1(n4680), .B0(FPADDSUB_intDY_EWSW[31]),
.B1(n4679), .Y(n4684) );
AOI22X1TS U6284 ( .A0(n4682), .A1(FPSENCOS_d_ff3_sh_y_out[31]), .B0(n2332),
.B1(FPSENCOS_d_ff3_sh_x_out[31]), .Y(n4683) );
NAND2X1TS U6285 ( .A(n4684), .B(n4683), .Y(n1729) );
AOI22X1TS U6286 ( .A0(n4686), .A1(FPSENCOS_d_ff_Xn[31]), .B0(
FPSENCOS_d_ff_Yn[31]), .B1(n4685), .Y(n4689) );
XOR2X1TS U6287 ( .A(n4689), .B(n4688), .Y(n4690) );
OAI2BB2XLTS U6288 ( .B0(n3495), .B1(n4690), .A0N(n3397), .A1N(
cordic_result[31]), .Y(n1696) );
AOI21X1TS U6289 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_middle[1]), .A1(n4691),
.B0(intadd_0_A_2_), .Y(intadd_0_B_1_) );
AOI22X1TS U6290 ( .A0(n2361), .A1(n5005), .B0(n4692), .B1(n5129), .Y(n4696)
);
AOI21X1TS U6291 ( .A0(begin_operation), .A1(n3182), .B0(n5278), .Y(n4694) );
AOI21X1TS U6292 ( .A0(n4696), .A1(n4695), .B0(n4694), .Y(n1693) );
INVX2TS U6293 ( .A(n4746), .Y(n4706) );
OA22X1TS U6294 ( .A0(FPMULT_Op_MX[22]), .A1(n4746), .B0(n4700), .B1(
Data_1[22]), .Y(n1681) );
INVX2TS U6295 ( .A(n4746), .Y(n4702) );
INVX2TS U6296 ( .A(n4746), .Y(n4700) );
INVX2TS U6297 ( .A(n4746), .Y(n4745) );
BUFX3TS U6298 ( .A(n4708), .Y(n4712) );
OAI2BB2XLTS U6299 ( .B0(n4709), .B1(n5024), .A0N(n4712), .A1N(Data_2[22]),
.Y(n1649) );
OAI2BB2XLTS U6300 ( .B0(n4709), .B1(n5026), .A0N(n4712), .A1N(Data_2[21]),
.Y(n1648) );
OAI2BB2XLTS U6301 ( .B0(n4709), .B1(n5022), .A0N(n4712), .A1N(Data_2[20]),
.Y(n1647) );
OAI2BB2XLTS U6302 ( .B0(n4708), .B1(n5027), .A0N(n4713), .A1N(Data_2[19]),
.Y(n1646) );
OAI2BB2XLTS U6303 ( .B0(n4708), .B1(n5025), .A0N(n4710), .A1N(Data_2[18]),
.Y(n1645) );
OAI2BB2XLTS U6304 ( .B0(n4708), .B1(n5029), .A0N(n4710), .A1N(Data_2[17]),
.Y(n1644) );
OAI2BB2XLTS U6305 ( .B0(n4708), .B1(n5023), .A0N(n4709), .A1N(Data_2[16]),
.Y(n1643) );
OAI2BB2XLTS U6306 ( .B0(n4711), .B1(n5030), .A0N(n4709), .A1N(Data_2[15]),
.Y(n1642) );
OAI2BB2XLTS U6307 ( .B0(n4711), .B1(n5031), .A0N(n4710), .A1N(Data_2[14]),
.Y(n1641) );
OAI2BB2XLTS U6308 ( .B0(n4711), .B1(n5021), .A0N(n4710), .A1N(Data_2[13]),
.Y(n1640) );
OAI2BB2XLTS U6309 ( .B0(n4711), .B1(n5028), .A0N(n4710), .A1N(Data_2[11]),
.Y(n1638) );
OAI2BB2XLTS U6310 ( .B0(n4711), .B1(n5043), .A0N(n4710), .A1N(Data_2[10]),
.Y(n1637) );
OAI2BB2XLTS U6311 ( .B0(n4711), .B1(n5041), .A0N(n4710), .A1N(Data_2[9]),
.Y(n1636) );
OAI2BB2XLTS U6312 ( .B0(n4711), .B1(n5047), .A0N(n4710), .A1N(Data_2[8]),
.Y(n1635) );
OAI2BB2XLTS U6313 ( .B0(n4711), .B1(n5044), .A0N(n4710), .A1N(Data_2[7]),
.Y(n1634) );
OAI2BB2XLTS U6314 ( .B0(n4711), .B1(n5048), .A0N(n4712), .A1N(Data_2[6]),
.Y(n1633) );
OAI2BB2XLTS U6315 ( .B0(n4713), .B1(n5042), .A0N(n4712), .A1N(Data_2[5]),
.Y(n1632) );
OAI2BB2XLTS U6316 ( .B0(n4713), .B1(n5045), .A0N(n4712), .A1N(Data_2[4]),
.Y(n1631) );
OAI2BB2XLTS U6317 ( .B0(n4713), .B1(n5046), .A0N(n4712), .A1N(Data_2[3]),
.Y(n1630) );
OAI2BB2XLTS U6318 ( .B0(n4713), .B1(n5050), .A0N(n4712), .A1N(Data_2[2]),
.Y(n1629) );
OAI2BB2XLTS U6319 ( .B0(n4713), .B1(n5065), .A0N(n4712), .A1N(Data_2[1]),
.Y(n1628) );
OAI2BB2XLTS U6320 ( .B0(n4713), .B1(n2276), .A0N(n4712), .A1N(Data_2[0]),
.Y(n1627) );
NOR4X1TS U6321 ( .A(FPMULT_Op_MY[29]), .B(FPMULT_Op_MY[28]), .C(
FPMULT_Op_MY[27]), .D(FPMULT_Op_MY[26]), .Y(n4723) );
NOR4X1TS U6322 ( .A(FPMULT_Op_MY[15]), .B(n2242), .C(FPMULT_Op_MY[21]), .D(
n2244), .Y(n4715) );
NOR4X1TS U6323 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[4]), .C(
FPMULT_Op_MY[6]), .D(FPMULT_Op_MY[8]), .Y(n4719) );
NOR4X1TS U6324 ( .A(FPMULT_Op_MY[25]), .B(FPMULT_Op_MY[24]), .C(
FPMULT_Op_MY[23]), .D(FPMULT_Op_MY[30]), .Y(n4718) );
NOR4X1TS U6325 ( .A(FPMULT_Op_MY[0]), .B(FPMULT_Op_MY[9]), .C(n2243), .D(
n2245), .Y(n4717) );
NOR4X1TS U6326 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[3]), .C(
FPMULT_Op_MY[5]), .D(FPMULT_Op_MY[7]), .Y(n4716) );
NAND4XLTS U6327 ( .A(n4719), .B(n4718), .C(n4717), .D(n4716), .Y(n4720) );
NOR4X1TS U6328 ( .A(FPMULT_Op_MY[13]), .B(n2240), .C(n4721), .D(n4720), .Y(
n4722) );
NOR4BBX1TS U6329 ( .AN(n4727), .BN(n4726), .C(FPMULT_Op_MX[23]), .D(n4725),
.Y(n4740) );
NOR4X1TS U6330 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_Op_MX[30]), .C(
FPMULT_Op_MX[29]), .D(FPMULT_Op_MX[25]), .Y(n4738) );
NOR4X1TS U6331 ( .A(FPMULT_Op_MX[20]), .B(n2198), .C(n4736), .D(n4735), .Y(
n4737) );
AOI32X1TS U6332 ( .A0(n4744), .A1(n4743), .A2(n4742), .B0(n5005), .B1(n4741),
.Y(n1626) );
INVX2TS U6333 ( .A(n2347), .Y(n4848) );
OA22X1TS U6334 ( .A0(n4847), .A1(mult_result[23]), .B0(
FPMULT_exp_oper_result[0]), .B1(n4848), .Y(n1585) );
OA22X1TS U6335 ( .A0(n4847), .A1(mult_result[24]), .B0(
FPMULT_exp_oper_result[1]), .B1(n4848), .Y(n1584) );
OA22X1TS U6336 ( .A0(n4747), .A1(mult_result[25]), .B0(
FPMULT_exp_oper_result[2]), .B1(n4848), .Y(n1583) );
OA22X1TS U6337 ( .A0(n4747), .A1(mult_result[26]), .B0(
FPMULT_exp_oper_result[3]), .B1(n4848), .Y(n1582) );
OA22X1TS U6338 ( .A0(n4747), .A1(mult_result[27]), .B0(
FPMULT_exp_oper_result[4]), .B1(n4848), .Y(n1581) );
OA22X1TS U6339 ( .A0(n4747), .A1(mult_result[28]), .B0(
FPMULT_exp_oper_result[5]), .B1(n4848), .Y(n1580) );
OA22X1TS U6340 ( .A0(n4747), .A1(mult_result[29]), .B0(
FPMULT_exp_oper_result[6]), .B1(n4848), .Y(n1579) );
OA22X1TS U6341 ( .A0(n4847), .A1(mult_result[30]), .B0(
FPMULT_exp_oper_result[7]), .B1(n4848), .Y(n1578) );
INVX2TS U6342 ( .A(n4847), .Y(n4846) );
OAI2BB1X1TS U6343 ( .A0N(mult_result[31]), .A1N(n4846), .B0(n4750), .Y(n1577) );
AOI21X1TS U6344 ( .A0(n4754), .A1(n4752), .B0(n4751), .Y(n4753) );
OAI2BB2XLTS U6345 ( .B0(n4830), .B1(n5131), .A0N(n4783), .A1N(n4753), .Y(
n1576) );
INVX2TS U6346 ( .A(n4844), .Y(n4840) );
OAI2BB1X1TS U6347 ( .A0N(FPMULT_P_Sgf[45]), .A1N(n4840), .B0(n4755), .Y(
n1575) );
INVX2TS U6348 ( .A(n4811), .Y(n4845) );
AOI21X1TS U6349 ( .A0(n4759), .A1(n4757), .B0(n4756), .Y(n4758) );
OAI2BB1X1TS U6350 ( .A0N(FPMULT_P_Sgf[43]), .A1N(n4840), .B0(n4760), .Y(
n1573) );
AOI21X1TS U6351 ( .A0(n4764), .A1(n4762), .B0(n4761), .Y(n4763) );
OAI21XLTS U6352 ( .A0(n4768), .A1(FPMULT_Sgf_operation_EVEN1_Q_left[17]),
.B0(n4764), .Y(n4766) );
AOI21X1TS U6353 ( .A0(n4767), .A1(n4766), .B0(n4765), .Y(n1571) );
AOI21X1TS U6354 ( .A0(n4771), .A1(n4769), .B0(n4768), .Y(n4770) );
OAI2BB1X1TS U6355 ( .A0N(FPMULT_P_Sgf[39]), .A1N(n4840), .B0(n4772), .Y(
n1569) );
AOI21X1TS U6356 ( .A0(n4775), .A1(n4774), .B0(n4773), .Y(n4776) );
XNOR2X1TS U6357 ( .A(n4784), .B(intadd_0_SUM_19_), .Y(n4785) );
XOR2XLTS U6358 ( .A(n4786), .B(n4785), .Y(n4787) );
CMPR32X2TS U6359 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .B(n4789), .C(
n4788), .CO(n2585), .S(n4790) );
NAND2BXLTS U6360 ( .AN(n4792), .B(n4791), .Y(n4793) );
XOR2XLTS U6361 ( .A(n4794), .B(n4793), .Y(n4795) );
INVX2TS U6362 ( .A(n4796), .Y(n4802) );
INVX2TS U6363 ( .A(n4811), .Y(n4842) );
NAND2X1TS U6364 ( .A(n4842), .B(FPMULT_P_Sgf[24]), .Y(n4801) );
AOI32X1TS U6365 ( .A0(n4800), .A1(n4798), .A2(n4797), .B0(
FPMULT_Sgf_operation_EVEN1_Q_left[0]), .B1(n4798), .Y(n4799) );
AOI32X1TS U6366 ( .A0(n4802), .A1(n4801), .A2(n4800), .B0(n4799), .B1(n4801),
.Y(n1554) );
INVX2TS U6367 ( .A(n4844), .Y(n4843) );
XNOR2X1TS U6368 ( .A(intadd_0_SUM_5_), .B(n4803), .Y(n4804) );
XOR2XLTS U6369 ( .A(n4805), .B(n4804), .Y(n4806) );
XNOR2X1TS U6370 ( .A(n4807), .B(intadd_0_SUM_4_), .Y(n4808) );
XOR2XLTS U6371 ( .A(n4809), .B(n4808), .Y(n4810) );
NAND2BXLTS U6372 ( .AN(n4813), .B(n4812), .Y(n4814) );
XOR2XLTS U6373 ( .A(n4815), .B(n4814), .Y(n4816) );
NAND2BXLTS U6374 ( .AN(n4818), .B(n4817), .Y(n4819) );
XOR2XLTS U6375 ( .A(n4820), .B(n4819), .Y(n4821) );
NAND2BXLTS U6376 ( .AN(n4823), .B(n4822), .Y(n4824) );
XOR2XLTS U6377 ( .A(n4825), .B(n4824), .Y(n4826) );
AOI21X1TS U6378 ( .A0(intadd_0_SUM_0_), .A1(n4828), .B0(n4827), .Y(n4829) );
OAI2BB2XLTS U6379 ( .B0(n4845), .B1(n4831), .A0N(n4843), .A1N(
FPMULT_P_Sgf[11]), .Y(n1541) );
OAI2BB2XLTS U6380 ( .B0(n4842), .B1(n4832), .A0N(n4843), .A1N(
FPMULT_P_Sgf[10]), .Y(n1540) );
OAI2BB2XLTS U6381 ( .B0(n4842), .B1(n4833), .A0N(n4840), .A1N(
FPMULT_P_Sgf[9]), .Y(n1539) );
OAI2BB2XLTS U6382 ( .B0(n4842), .B1(n4834), .A0N(n4843), .A1N(
FPMULT_P_Sgf[8]), .Y(n1538) );
OAI2BB2XLTS U6383 ( .B0(n4842), .B1(n4835), .A0N(n4840), .A1N(
FPMULT_P_Sgf[7]), .Y(n1537) );
OAI2BB2XLTS U6384 ( .B0(n4842), .B1(n4836), .A0N(n4840), .A1N(
FPMULT_P_Sgf[6]), .Y(n1536) );
OAI2BB2XLTS U6385 ( .B0(n4842), .B1(n4837), .A0N(n4840), .A1N(
FPMULT_P_Sgf[5]), .Y(n1535) );
OAI2BB2XLTS U6386 ( .B0(n4842), .B1(n4838), .A0N(n4840), .A1N(
FPMULT_P_Sgf[4]), .Y(n1534) );
OAI2BB2XLTS U6387 ( .B0(n4842), .B1(n4839), .A0N(n4840), .A1N(
FPMULT_P_Sgf[3]), .Y(n1533) );
OAI2BB2XLTS U6388 ( .B0(n4842), .B1(n4841), .A0N(n4840), .A1N(
FPMULT_P_Sgf[2]), .Y(n1532) );
OAI2BB2XLTS U6389 ( .B0(n5093), .B1(n4848), .A0N(mult_result[6]), .A1N(n4849), .Y(n1499) );
INVX2TS U6390 ( .A(n4847), .Y(n4850) );
OAI2BB2XLTS U6391 ( .B0(n5122), .B1(n4848), .A0N(mult_result[19]), .A1N(
n4849), .Y(n1486) );
XNOR2X1TS U6392 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(
FPADDSUB_DmP_EXP_EWSW[27]), .Y(n4853) );
XOR2X1TS U6393 ( .A(intadd_6_n1), .B(n4853), .Y(n4854) );
INVX2TS U6394 ( .A(n4984), .Y(n4894) );
BUFX3TS U6395 ( .A(n4976), .Y(n4977) );
BUFX3TS U6396 ( .A(n4984), .Y(n4891) );
OA21XLTS U6397 ( .A0(n5280), .A1(underflow_flag_addsubt), .B0(n4860), .Y(
n1413) );
OAI22X1TS U6398 ( .A0(n5280), .A1(n4864), .B0(n4863), .B1(n2360), .Y(n1409)
);
OAI22X1TS U6399 ( .A0(n5280), .A1(n4868), .B0(n4867), .B1(n2360), .Y(n1406)
);
OAI22X1TS U6400 ( .A0(n5280), .A1(n4870), .B0(n4869), .B1(n2360), .Y(n1403)
);
OAI22X1TS U6401 ( .A0(n4901), .A1(n4873), .B0(n4872), .B1(n4967), .Y(n1400)
);
OAI22X1TS U6402 ( .A0(n5280), .A1(n4875), .B0(n4874), .B1(n4967), .Y(n1397)
);
OAI22X1TS U6403 ( .A0(n4901), .A1(n4877), .B0(n4876), .B1(n2360), .Y(n1394)
);
OAI22X1TS U6404 ( .A0(n5280), .A1(n4879), .B0(n4878), .B1(n4972), .Y(n1391)
);
INVX2TS U6405 ( .A(n4880), .Y(n4971) );
OAI22X1TS U6406 ( .A0(n4901), .A1(n4883), .B0(n4882), .B1(n4967), .Y(n1388)
);
OAI22X1TS U6407 ( .A0(n4901), .A1(n4886), .B0(n4885), .B1(n4972), .Y(n1385)
);
OAI22X1TS U6408 ( .A0(n4901), .A1(n4888), .B0(n4887), .B1(n4967), .Y(n1382)
);
OAI22X1TS U6409 ( .A0(n4901), .A1(n4890), .B0(n4889), .B1(n4972), .Y(n1379)
);
OAI22X1TS U6410 ( .A0(n4901), .A1(n4893), .B0(n4892), .B1(n2360), .Y(n1376)
);
BUFX3TS U6411 ( .A(n4984), .Y(n4986) );
OAI22X1TS U6412 ( .A0(n4901), .A1(n4896), .B0(n4895), .B1(n4972), .Y(n1373)
);
INVX2TS U6413 ( .A(n4984), .Y(n4987) );
OAI22X1TS U6414 ( .A0(n4901), .A1(n4898), .B0(n4897), .B1(n4967), .Y(n1370)
);
OAI22X1TS U6415 ( .A0(n4901), .A1(n4900), .B0(n4899), .B1(n4972), .Y(n1367)
);
OAI22X1TS U6416 ( .A0(n4975), .A1(n4903), .B0(n4902), .B1(n2360), .Y(n1364)
);
CLKXOR2X2TS U6417 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(
n4951) );
NOR2BX1TS U6418 ( .AN(FPADDSUB_intDX_EWSW[31]), .B(n4904), .Y(n4950) );
AOI22X1TS U6419 ( .A0(n5060), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n4906), .B1(
FPADDSUB_intDY_EWSW[1]), .Y(n4905) );
AOI22X1TS U6420 ( .A0(n2427), .A1(FPADDSUB_intDY_EWSW[9]), .B0(n2421), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n4907) );
AOI22X1TS U6421 ( .A0(n5053), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n2404), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n4908) );
OAI221XLTS U6422 ( .A0(n5053), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n2404),
.B1(FPADDSUB_intDY_EWSW[8]), .C0(n4908), .Y(n4911) );
AOI22X1TS U6423 ( .A0(n2414), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n2411), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n4909) );
NOR4X1TS U6424 ( .A(n4913), .B(n4911), .C(n4912), .D(n4910), .Y(n4940) );
AOI22X1TS U6425 ( .A0(n2407), .A1(FPADDSUB_intDY_EWSW[20]), .B0(n2430), .B1(
FPADDSUB_intDY_EWSW[10]), .Y(n4914) );
AOI22X1TS U6426 ( .A0(n2413), .A1(FPADDSUB_intDY_EWSW[27]), .B0(n2406), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n4915) );
AOI22X1TS U6427 ( .A0(n2417), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2429), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n4916) );
AOI22X1TS U6428 ( .A0(n2412), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n2434), .B1(
FPADDSUB_intDY_EWSW[15]), .Y(n4917) );
NOR4X1TS U6429 ( .A(n4921), .B(n4920), .C(n4919), .D(n4918), .Y(n4939) );
AOI22X1TS U6430 ( .A0(n5061), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n2428), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n4922) );
AOI22X1TS U6431 ( .A0(n2405), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n2426), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n4923) );
OAI22X1TS U6432 ( .A0(n2424), .A1(FPADDSUB_intDY_EWSW[13]), .B0(n2431), .B1(
FPADDSUB_intDY_EWSW[22]), .Y(n4924) );
OAI22X1TS U6433 ( .A0(n2425), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n2416), .B1(
FPADDSUB_intDY_EWSW[17]), .Y(n4926) );
OAI22X1TS U6434 ( .A0(n2423), .A1(FPADDSUB_intDY_EWSW[4]), .B0(n5051), .B1(
FPADDSUB_intDY_EWSW[26]), .Y(n4927) );
OAI22X1TS U6435 ( .A0(n4997), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n5059), .B1(
FPADDSUB_intDY_EWSW[29]), .Y(n4928) );
OAI22X1TS U6436 ( .A0(n2420), .A1(FPADDSUB_intDY_EWSW[0]), .B0(n2415), .B1(
FPADDSUB_intDY_EWSW[16]), .Y(n4929) );
NOR4X1TS U6437 ( .A(n4937), .B(n4936), .C(n4935), .D(n4934), .Y(n4938) );
OAI22X1TS U6438 ( .A0(n4942), .A1(n4951), .B0(n4950), .B1(n4941), .Y(n4943)
);
OAI2BB1X1TS U6439 ( .A0N(FPADDSUB_SIGN_FLAG_EXP), .A1N(n4944), .B0(n4943),
.Y(n1363) );
AOI21X1TS U6440 ( .A0(n4951), .A1(n4950), .B0(n4949), .Y(n1356) );
OAI22X1TS U6441 ( .A0(n4975), .A1(n4954), .B0(n4953), .B1(n4972), .Y(n1330)
);
OAI22X1TS U6442 ( .A0(n4975), .A1(n4957), .B0(n4956), .B1(n4967), .Y(n1314)
);
OAI22X1TS U6443 ( .A0(n4975), .A1(n4960), .B0(n4959), .B1(n2360), .Y(n1307)
);
INVX2TS U6444 ( .A(n4984), .Y(n4981) );
OAI22X1TS U6445 ( .A0(n4975), .A1(n4963), .B0(n4962), .B1(n4967), .Y(n1300)
);
OAI22X1TS U6446 ( .A0(n4975), .A1(n4966), .B0(n4965), .B1(n4967), .Y(n1293)
);
OAI22X1TS U6447 ( .A0(n4975), .A1(n4969), .B0(n4968), .B1(n4967), .Y(n1286)
);
OAI22X1TS U6448 ( .A0(n4975), .A1(n4974), .B0(n4973), .B1(n4967), .Y(n1279)
);
INVX2TS U6449 ( .A(n4984), .Y(n4983) );
BUFX3TS U6450 ( .A(n4984), .Y(n4978) );
INVX2TS U6451 ( .A(n4976), .Y(n4980) );
CMPR32X2TS U6453 ( .A(n2300), .B(n2198), .C(intadd_5_n5), .CO(intadd_5_n4),
.S(intadd_5_SUM_6_) );
initial $sdf_annotate("FPU_Interface2_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk1.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_KOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk1.tcl_KOA_1STAGE_syn.sdf");
endmodule
|
// test bench for CHIPPER Router
`include "globalVariable.v"
module tb_Top;
reg [`PKTID_SIZE-1:0] inPktID [4:0];
reg [`FLITNUM_SIZE-1:0] inFlitNum [4:0];
reg [`COORDINATE_SIZE-1:0] inSrc [4:0];
reg [`COORDINATE_SIZE-1:0] inDst [4:0];
reg [`FLITTYPE_SIZE-1:0] inType[4:0];
reg [3:0] inPG, inWU;
reg clk, reset, injectReq;
wire injectGrant;
wire [3:0] outPG, outWU;
wire [`PKTID_SIZE-1:0] outPktID [4:0];
wire [`FLITNUM_SIZE-1:0] outFlitNum [4:0];
wire [`COORDINATE_SIZE-1:0] outSrc [4:0];
wire [`COORDINATE_SIZE-1:0] outDst [4:0];
wire [`FLITTYPE_SIZE-1:0] outType[4:0];
wire [`CHANNEL_SIZE-1:0] w_outFlit[4:0];
wire [`PG_COUNTER_SIZE-1:0] pgCountValue = tb_Top.Top.pgCounter.pgCountValue;
reg [`DATA_SIZE-1:0] data[4:0];
Top Top (
.inPortE ({inPktID[0],inFlitNum[0],inSrc[0],inDst[0],inType[0],data[0]}),
.inPortW ({inPktID[1],inFlitNum[1],inSrc[1],inDst[1],inType[1],data[1]}),
.inPortN ({inPktID[2],inFlitNum[2],inSrc[2],inDst[2],inType[2],data[2]}),
.inPortS ({inPktID[3],inFlitNum[3],inSrc[3],inDst[3],inType[3],data[3]}),
.inPortLocal ({inPktID[4],inFlitNum[4],inSrc[4],inDst[4],inType[4],data[4]}),
.injectReq (injectReq),
.clk (clk),
.reset (reset),
.inPG (inPG),
.inWU (inWU),
.outPG (outPG),
.outWU (outWU),
.outPortE (w_outFlit[0]),
.outPortW (w_outFlit[1]),
.outPortN (w_outFlit[2]),
.outPortS (w_outFlit[3]),
.outPortLocal (w_outFlit[4]),
.injectGrant (injectGrant)
);
genvar i;
generate
for (i=0;i<5;i=i+1) begin
assign outPktID[i] = w_outFlit[i][`PKT_ID];
assign outFlitNum[i] = w_outFlit[i][`FLIT_NUM];
assign outSrc[i] = w_outFlit[i][`SRC];
assign outDst[i] = w_outFlit[i][`DST];
assign outType[i] = w_outFlit[i][`TYPE];
end
endgenerate
always @ *
#5 clk <= ~clk;
always @ (posedge clk)
$monitor ("@%0dns South=%d North=%d West=%d East=%d", $time,
tb_Top.Top.portStatus[3*`PORT_STAT_SIZE+:`PORT_STAT_SIZE], tb_Top.Top.portStatus[2*`PORT_STAT_SIZE+:`PORT_STAT_SIZE], tb_Top.Top.portStatus[1*`PORT_STAT_SIZE+:`PORT_STAT_SIZE], tb_Top.Top.portStatus[0*`PORT_STAT_SIZE+:`PORT_STAT_SIZE],);
initial begin
$dumpfile ("Top.vcd"); // output the value of signals
$dumpvars (0,Top); // Coupled with $dumpfile command, specify which signals to output. use instance name
// Initialization
clk = 0;
reset = 0;
injectReq = 0;
inPG = 4'b0000;
inWU = 4'b0000;
inPktID[0] = 8'd0; inPktID[1] = 8'd0; inPktID[2] = 8'd0; inPktID[3] = 8'd0; inPktID[4] = 8'd0;
inFlitNum[0] = 2'd0; inFlitNum[1] = 2'd0; inFlitNum[2] = 2'd0; inFlitNum[3] = 2'd0; inFlitNum[4] = 2'd0;
inSrc[0] = 6'o0; inSrc[1] = 6'o0; inSrc[2] = 6'o0; inSrc[3] = 6'o0; inSrc[4] = 6'o0;
inDst[0] = 6'o0; inDst[1] = 6'o0; inDst[2] = 6'o0; inDst[3] = 6'o0; inDst[4] = 6'o0;
inType[0] = 2'd0; inType[1] = 2'd0; inType[2] = 2'd0; inType[3] = 2'd0; inType[4] = 2'd0;
data[0] = 128'd0; data[1] = 128'd0; data[2] = 128'd0; data[3] = 128'd0; data[4] = 128'd0;
// Simulation starts here.
# 10;
reset = 1;
// Test1
// Pkt 0 and Pkt 1 compete for the North port. Pkt0 should win. Pkt 1 should be deflected.
// Pkt 2 and pkt 3 compete for local port. The result is pseudorandom.
// Pkt 4 will inject to either the channel 2 or 3, depending on the ejection result. Then, it will be deflected.
inPktID[0] = 8'd0; inPktID[1] = 8'd1; inPktID[2] = 8'd2; inPktID[3] = 8'd3; inPktID[4] = 8'd4;
inFlitNum[0] = 2'd0; inFlitNum[1] = 2'd0; inFlitNum[2] = 2'd0; inFlitNum[3] = 2'd0; inFlitNum[4] = 2'd0;
inSrc[0] = 6'o00; inSrc[1] = 6'o00; inSrc[2] = 6'o00; inSrc[3] = 6'o00; inSrc[4] = 6'o00;
inDst[0] = 6'o12; inDst[1] = 6'o12; inDst[2] = 6'o11; inDst[3] = 6'o11; inDst[4] = 6'o12;
inType[0] = 2'd0; inType[1] = 2'd0; inType[2] = 2'd0; inType[3] = 2'd0; inType[4] = 2'd0;
data[0] = 128'd0; data[1] = 128'd1; data[2] = 128'd2; data[3] = 128'd3; data[4] = 128'd4;
injectReq = 1;
# 10;
// Test2
// Pkt 0 and pkt 1 compete for the North port again. Pkt1 should win since its inFlitNum is smaller than that of Pkt0;
// Pkt 2 and pkt 3 compete for the East port. The result is pseudorandom.
// The injection request of pkt4 is denied.
inPktID[0] = 8'd0; inPktID[1] = 8'd0; inPktID[2] = 8'd1; inPktID[3] = 8'd1; inPktID[4] = 8'd4;
inFlitNum[0] = 2'd1; inFlitNum[1] = 2'd0; inFlitNum[2] = 2'd1; inFlitNum[3] = 2'd0; inFlitNum[4] = 2'd1;
inSrc[0] = 6'o00; inSrc[1] = 6'o00; inSrc[2] = 6'o00; inSrc[3] = 6'o00; inSrc[4] = 6'o00;
inDst[0] = 6'o12; inDst[1] = 6'o12; inDst[2] = 6'o21; inDst[3] = 6'o21; inDst[4] = 6'o21;
inType[0] = 2'd0; inType[1] = 2'd0; inType[2] = 2'd0; inType[3] = 2'd0; inType[3] = 2'd0;
data[0] = 128'd5; data[1] = 128'd6; data[2] = 128'd7; data[3] = 128'd8; data[4] = 128'd9;
injectReq = 1;
# 10;
inPktID[0] = 8'd0; inPktID[1] = 8'd0; inPktID[2] = 8'd0; inPktID[3] = 8'd0; inPktID[4] = 8'd0;
inFlitNum[0] = 2'd0; inFlitNum[1] = 2'd0; inFlitNum[2] = 2'd0; inFlitNum[3] = 2'd0; inFlitNum[4] = 2'd0;
inSrc[0] = 6'o0; inSrc[1] = 6'o0; inSrc[2] = 6'o0; inSrc[3] = 6'o0; inSrc[4] = 6'o0;
inDst[0] = 6'o0; inDst[1] = 6'o0; inDst[2] = 6'o0; inDst[3] = 6'o0; inDst[4] = 6'o0;
inType[0] = 2'd0; inType[1] = 2'd0; inType[2] = 2'd0; inType[3] = 2'd0; inType[4] = 2'd0;
data[0] = 128'd0; data[1] = 128'd0; data[2] = 128'd0; data[3] = 128'd0; data[4] = 128'd0;
# 9970;
// Test2
// Pkt 0 and pkt 1 compete for the North port again. Pkt1 should win since its inFlitNum is smaller than that of Pkt0;
// Pkt 2 and pkt 3 compete for the East port. The result is pseudorandom.
// The injection request of pkt4 is denied.
inPktID[2] = 8'd1; inPktID[3] = 8'd2; inPktID[4] = 8'd4;
inFlitNum[2] = 2'd1; inFlitNum[3] = 2'd0; inFlitNum[4] = 2'd1;
inSrc[2] = 6'o00; inSrc[3] = 6'o00; inSrc[4] = 6'o00;
inDst[2] = 6'o21; inDst[3] = 6'o01; inDst[4] = 6'o21;
inType[2] = 2'd0; inType[3] = 2'd0; inType[4] = 2'd0;
data[2] = 128'd5; data[3] = 128'd6; data[4] = 128'd9;
injectReq = 1;
# 5;
inPG = 4'b0011; // emulate the PG signal coming form the neighboring router
end
initial begin
# 10100; $finish; // simulation ends here.
end
endmodule |
// bsg_adder_one_hot
//
// adder whose inputs and outputs are all one hot signals
//
// the adder is by default a modulo adder, so it will wrap around
// if there is a carry out.
//
// if you don't want modulo, then make the output signal wide enough; i.e. set output_width_p>=2*width_p-1
//
`include "bsg_defines.v"
module bsg_adder_one_hot #(parameter `BSG_INV_PARAM(width_p), parameter output_width_p=width_p)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [output_width_p-1:0] o
);
genvar i,j;
initial assert (output_width_p >= width_p)
else begin $error("%m: unsupported output_width_p < width_p");
$finish();
end
for (i=0; i < output_width_p; i++) // for each output wire
begin: rof
wire [width_p-1:0] aggregate;
// for each input a_i
// compute what bit is necessary to make it total to i
// including wrap around in the modulo case
for (j=0; j < width_p; j=j+1)
begin: rof2
if (i < j)
begin: rof3
if (output_width_p+i-j < width_p)
assign aggregate[j] = a_i[j] & b_i[output_width_p+i-j];
else
assign aggregate[j] = 1'b0;
end
else
if (i-j < width_p)
assign aggregate[j] = a_i[j] & b_i[i-j];
else
assign aggregate[j] = 1'b0;
end // block: rof2
assign o[i] = | aggregate;
end // block: rof
endmodule
`BSG_ABSTRACT_MODULE(bsg_adder_one_hot)
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 07/21/05 - CR 212974 -- matched unisim parameters as requested by other tools
// 07/19/06 - Add else to handle x case for o_out (CR 234718).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/13/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS (O, I, IB);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
localparam MODULE_NAME = "IBUFDS";
output O;
input I, IB;
wire i_in, ib_in;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
assign O = o_out;
assign i_in = I;
assign ib_in = IB;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
#1 $finish;
end
endcase
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on %s instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", MODULE_NAME, CAPACITANCE);
#1 $finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
#1 $finish;
end
endcase // case(DIFF_TERM)
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", MODULE_NAME, IBUF_DELAY_VALUE);
#1 $finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
#1 $finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", MODULE_NAME, IFD_DELAY_VALUE);
#1 $finish;
end
endcase
end
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RIT
// Engineer: Cody Cziesler, Nick Desaulniers
//
// Create Date: 11:44:01 04/07/2011
// Design Name: execute
// Module Name: execute
// Project Name: omicron
// Target Devices: Xilinx Spartan-3E
// Tool versions:
// Description: Execute stage of pipelined cpu
//
// Revision 0.01 - File Created
// Revision 1.00 - Complete, untested
// Revision 2.00 - Fixed b, removed v and c from alu, tested w/ ModelSim
// Revision 3.00 - Fixed spacing, header (CRC)
// Revision 4.00 - Modified cu_alu_opcode width
// Revision 5.00 - Removed cu_reg_dest and logic for ex_reg_waddr (CRC)
//
//////////////////////////////////////////////////////////////////////////////////
module execute(
input clk_n,
input rst_n,
input [6:0] id_next_addr,
input [15:0] id_register1_data,
input [15:0] id_register2_data,
input [6:0] id_sign_ext_addr,
input [2:0] id_dest_reg_addr,
input [10:0] cu_alu_opcode,
input cu_alu_sel_b,
output [6:0] ex_sign_ext_next_addr,
output ex_alu_z,
output [15:0] ex_alu_result,
output [15:0] ex_register2_data,
output [2:0] ex_reg_waddr
);
wire [15:0] b;
// Mux for second operand
// if( cu_alu_sel_b ){
// b <= id_sign_ext_addr;
// }else{
// b <= id_register2_data;
// }
assign b = cu_alu_sel_b ? id_sign_ext_addr : id_register2_data;
assign ex_reg_waddr = id_dest_reg_addr;
assign ex_sign_ext_next_addr = id_next_addr + id_sign_ext_addr;
assign ex_register2_data = id_register2_data;
alu i_alu(
.a(id_register1_data),
.b(b),
.opcode(cu_alu_opcode),
.rst_n(rst_n),
.clk_n(clk_n),
.out(ex_alu_result),
.z(ex_alu_z)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BAI_TB_V
`define SKY130_FD_SC_LS__O21BAI_TB_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o21bai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_ls__o21bai dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BAI_TB_V
|
`include "../rtl/ram_sp.v"
`default_nettype none
`timescale 1ms/1us
module tb_ram_sp;
parameter DWIDTH = 8;
parameter AWIDTH = 12;
parameter CONTENT = "./memory.txt";
reg clock;
reg wren;
reg [AWIDTH-1:0] address;
reg [DWIDTH-1:0] data;
wire [DWIDTH-1:0] q;
ram_sp
#(
.DWIDTH ( 8 ),
.AWIDTH ( 12 ),
.CONTENT ( "./ram_content.txt" )
) _ram_sp
(
.clock ( clock ),
.wren ( wren ),
.address ( address ),
.data ( data ),
.q ( q )
);
parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD/2) clock = ~clock;
integer i;
initial begin
$dumpfile("tb_ram_sp.vcd");
$dumpvars(0, tb_ram_sp);
#1 clock=1'bx;wren=1'bx;address={AWIDTH{1'bx}};data={DWIDTH{1'bx}};
#(CLK_PERIOD) clock=0;address=0;wren=0;data=0;
for (i=0;i<=100;i=i+1) begin
#(CLK_PERIOD) address=i;wren=1;data=(100-i);
end
#(CLK_PERIOD) wren=0;
for (i=0;i<=100;i=i+1) begin
#(CLK_PERIOD) address=i;
end
#(CLK_PERIOD*50);
$finish(2);
end
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__EINVP_PP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_PP_SYMBOL_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014
// Date : Wed Sep 10 03:37:55 2014
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// d:/spira_heaven/0-myworks/ld3320_axi/ld3320_axi_1.0/src/VOICE_ROM_INIT/VOICE_ROM_INIT_stub.v
// Design : VOICE_ROM_INIT
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.2" *)
module VOICE_ROM_INIT(clka, wea, addra, dina, clkb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[5:0],dina[15:0],clkb,addrb[5:0],doutb[15:0]" */;
input clka;
input [0:0]wea;
input [5:0]addra;
input [15:0]dina;
input clkb;
input [5:0]addrb;
output [15:0]doutb;
endmodule
|
<%
var _ = core();
var ir = _.logic(4);
var len = _.logic(3);
var len = {
'??00': '0001',
'1?0?': '0001',
'0001': '0010',
'0010': '0100',
'0011': '1000'
};
%>
/*
module tail_length (${ _.get.list() });
${ _.get.ports() }
${ _.get.wires() }
${ _.get.body() }
*/
module tail_length (ir, len);
input [3:0] ir;
output [3:0] len;
reg [3:0] len;
reg ir32;
/*
..00 ..01 ..10 ..11
00.. 1 0 0 0
01.. 1 ? ? 0
10.. 1 1 0 0
11.. 1 1 0 0
len[0] = (ir[3] & !ir[1]) | (!ir[1] & !ir[0]);
..00 ..01 ..10 ..11
00.. 0 1 0 0
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[1] = !ir[3] & !ir[2] & !ir[1] & ir[0];
..00 ..01 ..10 ..11
00.. 0 0 1 0
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[2] = !ir[3] & !ir[2] & ir[1] & !ir[0];
..00 ..01 ..10 ..11
00.. 0 0 0 1
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[3] = !ir[3] & !ir[2] & ir[1] & ir[0];
..00 ..01 ..10 ..11
00.. 1 2 4 8
01.. 1 ? ? 0
10.. 1 1 0 0
11.. 1 1 0 0
*/
always @ (ir)
begin
len = {
(ir == 4'b0011),
(ir == 4'b0010),
(ir == 4'b0001),
((ir | 4'b0101) == 4'b1101) | ((ir | 4'b1100) == 4'b1100)
};
end
// 107.89 / 121.08
// always @ (ir)
// begin
// ir32 = |ir[3:2];
// len = {
// (!ir32 & ir[1] & ir[0]),
// (!ir32 & ir[1] & !ir[0]),
// (!ir32 & !ir[1] & ir[0]),
// ((ir[3] & !ir[1]) | (!ir[1] & !ir[0]))
// };
// end
// always @ (ir)
// casez (ir)
// 4'b??00: len = 1;
// 4'b1?0?: len = 1;
// 4'b0001: len = 2;
// 4'b0010: len = 4;
// 4'b0011: len = 8;
// default len = 0;
// endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_4_V
`define SKY130_FD_SC_HDLL__AND3B_4_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_4 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_SYMBOL_V
`define SKY130_FD_SC_LP__BUSRECEIVER_SYMBOL_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busreceiver (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1P_PP_SYMBOL_V
`define SKY130_FD_SC_LP__INPUTISO1P_PP_SYMBOL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1P_PP_SYMBOL_V
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=5000 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=Display_PLL" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//CBXI_INSTANCE_NAME="ADC_Display_PLL_display0_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module Display_PLL_altpll
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll1_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll1
(
.activeclock(),
.areset(areset),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 5000,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "off",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]},
locked = (wire_pll1_locked & pll_lock_sync);
endmodule //Display_PLL_altpll
//VALID FILE
|
//
// (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
//
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ps/1ps
module srio_gen2_0_srio_rst
(
input cfg_clk, // CFG interface clock
input log_clk, // LOG interface clock
input phy_clk, // PHY interface clock
input gt_pcs_clk, // GT Fabric interface clock
input sys_rst, // Global reset signal
input port_initialized, // Port is intialized
input phy_rcvd_link_reset, // Received 4 consecutive reset symbols
input force_reinit, // Force reinitialization
input clk_lock, // Indicates the MMCM has achieved a stable clock
output reg controlled_force_reinit, // Force reinitialization
output cfg_rst, // CFG dedicated reset
output log_rst, // LOG dedicated reset
output buf_rst, // BUF dedicated reset
output phy_rst, // PHY dedicated reset
output gt_pcs_rst // GT dedicated reset
);
// {{{ Parameter declarations -----------
// Reset State Machine
localparam IDLE = 4'b0001;
localparam LINKRESET = 4'b0010;
localparam PHY_RESET1 = 4'b0100;
localparam PHY_RESET2 = 4'b1000;
// }}} End Parameter declarations -------
wire sys_rst_buffered;
// {{{ wire declarations ----------------
reg [0:3] reset_state = IDLE;
reg [0:3] reset_next_state = IDLE;
(* ASYNC_REG = "TRUE" *)
reg [3:0] cfg_rst_srl;
(* ASYNC_REG = "TRUE" *)
reg [3:0] log_rst_srl;
(* ASYNC_REG = "TRUE" *)
reg [3:0] phy_rst_srl;
(* ASYNC_REG = "TRUE" *)
reg [3:0] gt_pcs_rst_srl;
reg sys_rst_int;
wire reset_condition = sys_rst || phy_rcvd_link_reset || sys_rst_int;
// }}} End wire declarations ------------
assign cfg_rst = cfg_rst_srl[3];
always @(posedge cfg_clk or posedge reset_condition) begin
if (reset_condition) begin
cfg_rst_srl <= 4'b1111;
end else if (clk_lock) begin
cfg_rst_srl <= {cfg_rst_srl[2:0], 1'b0};
end
end
assign log_rst = log_rst_srl[3];
always @(posedge log_clk or posedge reset_condition) begin
if (reset_condition) begin
log_rst_srl <= 4'b1111;
end else if (clk_lock) begin
log_rst_srl <= {log_rst_srl[2:0], 1'b0};
end
end
// The Buffer actively manages the reset due to the
// nature of the domain crossing being done in the buffer.
assign buf_rst = reset_condition;
assign phy_rst = phy_rst_srl[3];
always @(posedge phy_clk or posedge reset_condition) begin
if (reset_condition) begin
phy_rst_srl <= 4'b1111;
end else if (clk_lock) begin
phy_rst_srl <= {phy_rst_srl[2:0], 1'b0};
end
end
assign gt_pcs_rst = gt_pcs_rst_srl[3];
always @(posedge gt_pcs_clk or posedge reset_condition) begin
if (reset_condition) begin
gt_pcs_rst_srl <= 4'b1111;
end else if (clk_lock) begin
gt_pcs_rst_srl <= {gt_pcs_rst_srl[2:0], 1'b0};
end
end
// This controller is used to properly send link reset requests that were
// made by the user.
always@(posedge log_clk) begin
reset_state <= reset_next_state;
end
always @* begin
casex (reset_state)
IDLE: begin
// Current State Outputs
sys_rst_int = 1'b0;
controlled_force_reinit = 1'b0;
// Next State Outputs
if (force_reinit)
reset_next_state = LINKRESET;
else
reset_next_state = IDLE;
end
LINKRESET: begin
// Current State Outputs
sys_rst_int = 1'b0;
controlled_force_reinit = 1'b1;
// Next State Outputs
if (~port_initialized)
reset_next_state = PHY_RESET1;
else
reset_next_state = LINKRESET;
end
PHY_RESET1: begin
// Current State Outputs
sys_rst_int = 1'b1;
controlled_force_reinit = 1'b0;
// Next State Outputs
reset_next_state = PHY_RESET2;
end
PHY_RESET2: begin
// Current State Outputs
sys_rst_int = 1'b1;
controlled_force_reinit = 1'b0;
// Next State Outputs
if (force_reinit)
reset_next_state = PHY_RESET2;
else
reset_next_state = IDLE;
end
default: begin
// Current State Outputs
sys_rst_int = 1'b0;
controlled_force_reinit = 1'b0;
// Next State Outputs
reset_next_state = IDLE;
end
endcase
end
endmodule
// {{{ DISCLAIMER OF LIABILITY
// -----------------------------------------------------------------
// (c) Copyright 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// }}}
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Mon Oct 24 10:52:44 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.1 2005/10/25 13:15:36 wig Exp $
// $Date: 2005/10/25 13:15:36 $
// $Log: ent_ab.v,v $
// Revision 1.1 2005/10/25 13:15:36 wig
// Testcase result update
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.38 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No `defines in this module
module ent_ab
//
// Generated module inst_ab
//
(
input wire port_ab_1, // Use internally test1
output wire port_ab_2, // Use internally test2, no port generated
input wire [4:0] sig_13, // Create internal signal name
input wire [6:0] sig_14 // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns/10ps
`default_nettype none
module display_model #(
/**********************************************
640x480 60Hz VGA Monitor for default parameter
**********************************************/
parameter P_DOT_CYCLE = 40, //25MHz
//Counter Width
parameter P_H_AREA = 640,
parameter P_V_AREA = 480,
//Hsync
parameter P_THP = 95, //Hsync pulse width.(Unit:NCLK)
parameter P_THB = 48, //To Hsync - data width.(Unit:NCLK)
parameter P_THF = 15, //To data - next Hsync width.(Unit:NCLK)
//Vsync
parameter P_TVP = 2, //Vsync pulse width.(Unit:HSYNC)
parameter P_TVB = 33, //To Vsync - active data area width.(Unit:HSYNC)
parameter P_TVF = 10 //To active data area - next Vsync width.(Unit:HSYNC)
)(
input wire iFILE_DUMP,
input wire inSYNC_H,
input wire inSYNC_V,
input wire [7:0] iDISP_R,
input wire [7:0] iDISP_G,
input wire [7:0] iDISP_B
);
integer i, j;
reg [7:0] b_disp_r[0:(P_H_AREA*P_V_AREA)-1];
reg [7:0] b_disp_g[0:(P_H_AREA*P_V_AREA)-1];
reg [7:0] b_disp_b[0:(P_H_AREA*P_V_AREA)-1];
//Hsync-THP Check
integer hsync_thp_time;
reg hsync_thp_check_end;
initial begin
hsync_thp_time = 0;
hsync_thp_check_end = 0;
//Wait
#(P_DOT_CYCLE/2);
while(inSYNC_H == 0 || inSYNC_H == 1'bx)begin
#(P_DOT_CYCLE);
end
while(inSYNC_H == 1)begin
#(P_DOT_CYCLE);
end
//THP
while(!inSYNC_H)begin
hsync_thp_time = hsync_thp_time + 1;
#(P_DOT_CYCLE);
end
if(hsync_thp_time != P_THP)begin
$display("[ERROR][display_model] : THP Error. Correct%d, Fact%d", P_THP, hsync_thp_time);
$stop;
end
$display("[OK][display_model] : HSYNC THP Timing OK");
hsync_thp_check_end = 1;
end
//Hsync-other timing Check
integer hsync_other_time;
reg hsync_other_check_end;
initial begin
hsync_other_time = 0;
hsync_other_check_end = 0;
//Wait
#(P_DOT_CYCLE/2);
while(inSYNC_H == 0 || inSYNC_H == 1'bx)begin
#(P_DOT_CYCLE);
end
//THB or P_H_AREA or THF
while(inSYNC_H)begin
hsync_other_time = hsync_other_time + 1;
#(P_DOT_CYCLE);
end
if(hsync_other_time != (P_THB+P_H_AREA+P_THF))begin
$display("[ERROR][display_model] : THB or P_H_AREA or THF Error. Correct%d, Fact%d", (P_THB+P_H_AREA+P_THF), hsync_other_time);
$stop;
end
$display("[OK][display_model] : HSYNC THP, P_H_AREA, THF OK");
hsync_other_check_end = 1;
end
//Vsync Check
integer vsync_time;
reg vsync_check_end;
initial begin
vsync_time = 0;
vsync_check_end = 0;
//Wait
#(P_DOT_CYCLE);
while(!inSYNC_V || inSYNC_V == 1'bx)begin
#(P_DOT_CYCLE);
end
while(inSYNC_V)begin
#(P_DOT_CYCLE);
end
//TVP
while(!inSYNC_V)begin
#(P_DOT_CYCLE);
vsync_time = vsync_time + 1;
end
if(vsync_time != P_TVP*(P_THP+P_THB+P_H_AREA+P_THF))begin
$display("[ERROR][display_model] : TVP Error. Correct%d, Fact%d", P_TVP*(P_THP+P_THB+P_H_AREA+P_THF), vsync_time);
$stop;
end
else begin
$display("[OK][display_model] : TVP OK");
end
vsync_time = 0;
//TVB, P_V_AREA, TVF
while(inSYNC_V)begin
#(P_DOT_CYCLE);
vsync_time = vsync_time + 1;
end
if(vsync_time != (P_TVB+P_V_AREA+P_TVF)*(P_THP+P_THB+P_H_AREA+P_THF))begin
$display("[ERROR][display_model] : TVB or P_V_AREA or TVF Error. Correct%d, Fact%d", (P_TVB+P_V_AREA+P_TVF)*(P_THP+P_THB+P_H_AREA+P_THF), vsync_time);
$stop;
end
else begin
$display("[OK][display_model] : TVP, P_V_AREA, TVF OK");
end
$display("[OK][display_model] : Hsync Timing OK");
vsync_check_end = 1;
end
integer fp;
initial begin
#(P_DOT_CYCLE);
//File Dump Start
while(!iFILE_DUMP)begin
#(P_DOT_CYCLE);
end
//H, V sync check wait
while(!hsync_thp_check_end ||!hsync_other_check_end || !vsync_check_end)begin
#(P_DOT_CYCLE);
end
//File Open
fp = $fopen("dump_disp.bmp", "wb");
if(!fp)begin
$display("File open error");
$stop;
end
//Memory Reset
for(i = 0; i < P_H_AREA*P_V_AREA; i = i + 1)begin : MEM_RESET
b_disp_r[i] = 8'h0;
b_disp_g[i] = 8'h0;
b_disp_b[i] = 8'h0;
end
i = 0;
//Waif Vsync
while(inSYNC_V || inSYNC_V == 1'bx)begin
#(P_DOT_CYCLE);
end
#(P_DOT_CYCLE*(P_THP+P_THB+P_H_AREA+P_THF)*P_TVB);
//Get Data
while(i < P_H_AREA*P_V_AREA)begin
j = 0;
while(j < P_H_AREA)begin
b_disp_r[i] = iDISP_R;
b_disp_g[i] = iDISP_G;
b_disp_b[i] = iDISP_B;
i = i + 1;
j = j + 1;
#(P_DOT_CYCLE);
end
//Hsync Wait
while(inSYNC_H)begin
#(P_DOT_CYCLE);
end
while(!inSYNC_H)begin
#(P_DOT_CYCLE);
end
#(P_DOT_CYCLE*P_THB);
end
//File dump
tsk_write_bmp();
$fclose(fp);
$stop;
end
//File Header
reg [15:0] bfType = "BM";
reg [31:0] bfSize = 14+40+(P_V_AREA*P_H_AREA*4); //File Header + Info Header + PixcelData32bit
reg [15:0] bfReserved1 = 0;
reg [15:0] bfReserved2 = 0;
reg [31:0] bfOffBits = 14+40; //File Header + Info Header
//Info Header
reg [31:0] biSize = 40;
reg [31:0] biWidth = P_H_AREA;
reg [31:0] biHeight = P_V_AREA;
reg [15:0] biPlanes = 1;
reg [15:0] biBitCount = 32;
reg [31:0] biCopmression = 0;
reg [31:0] biSizeImage = 3780;
reg [31:0] biXPixPerMeter = 3780;
reg [31:0] biYPixPerMeter = 3780;
reg [31:0] biClrUsed = 0;
reg [31:0] biCirImportant = 0;
//ReserveData
reg [7:0] bBitReserved = 0;
task tsk_write_bmp;
begin
//Write File Header
$fwrite(fp, "%s", bfType);
$fwrite(fp, "%c", bfSize[7:0]);
$fwrite(fp, "%c", bfSize[15:8]);
$fwrite(fp, "%c", bfSize[23:16]);
$fwrite(fp, "%c", bfSize[31:24]);
$fwrite(fp, "%c", bfReserved1[7:0]);
$fwrite(fp, "%c", bfReserved1[15:8]);
$fwrite(fp, "%c", bfReserved2[7:0]);
$fwrite(fp, "%c", bfReserved2[15:8]);
$fwrite(fp, "%c", bfOffBits[7:0]);
$fwrite(fp, "%c", bfOffBits[15:8]);
$fwrite(fp, "%c", bfOffBits[23:16]);
$fwrite(fp, "%c", bfOffBits[31:24]);
//Write Info Header
$fwrite(fp, "%c", biSize[7:0]);
$fwrite(fp, "%c", biSize[15:8]);
$fwrite(fp, "%c", biSize[23:16]);
$fwrite(fp, "%c", biSize[31:24]);
$fwrite(fp, "%c", biWidth[7:0]);
$fwrite(fp, "%c", biWidth[15:8]);
$fwrite(fp, "%c", biWidth[23:16]);
$fwrite(fp, "%c", biWidth[31:24]);
$fwrite(fp, "%c", biHeight[7:0]);
$fwrite(fp, "%c", biHeight[15:8]);
$fwrite(fp, "%c", biHeight[23:16]);
$fwrite(fp, "%c", biHeight[31:24]);
$fwrite(fp, "%c", biPlanes[7:0]);
$fwrite(fp, "%c", biPlanes[15:8]);
$fwrite(fp, "%c", biBitCount[7:0]);
$fwrite(fp, "%c", biBitCount[15:8]);
$fwrite(fp, "%c", biCopmression[7:0]);
$fwrite(fp, "%c", biCopmression[15:8]);
$fwrite(fp, "%c", biCopmression[23:16]);
$fwrite(fp, "%c", biCopmression[31:24]);
$fwrite(fp, "%c", biSizeImage[7:0]);
$fwrite(fp, "%c", biSizeImage[15:8]);
$fwrite(fp, "%c", biSizeImage[23:16]);
$fwrite(fp, "%c", biSizeImage[31:24]);
$fwrite(fp, "%c", biXPixPerMeter[7:0]);
$fwrite(fp, "%c", biXPixPerMeter[15:8]);
$fwrite(fp, "%c", biXPixPerMeter[23:16]);
$fwrite(fp, "%c", biXPixPerMeter[31:24]);
$fwrite(fp, "%c", biYPixPerMeter[7:0]);
$fwrite(fp, "%c", biYPixPerMeter[15:8]);
$fwrite(fp, "%c", biYPixPerMeter[23:16]);
$fwrite(fp, "%c", biYPixPerMeter[31:24]);
$fwrite(fp, "%c", biClrUsed[7:0]);
$fwrite(fp, "%c", biClrUsed[15:8]);
$fwrite(fp, "%c", biClrUsed[23:16]);
$fwrite(fp, "%c", biClrUsed[31:24]);
$fwrite(fp, "%c", biCirImportant[7:0]);
$fwrite(fp, "%c", biCirImportant[15:8]);
$fwrite(fp, "%c", biCirImportant[23:16]);
$fwrite(fp, "%c", biCirImportant[31:24]);
//Write Pixcel Data
for(i = (P_V_AREA*P_H_AREA)-1; i >= 0 ; i = i - 1)begin : F_DATA_OUT
$fwrite(fp, "%c%c%c%c", b_disp_b[i], b_disp_g[i], b_disp_r[i], bBitReserved);
end
end
endtask
endmodule
`default_nettype wire
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_deccdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// This module has the following functionality :-
// 1. Perform the ECC correction on the 155 bit data readd out from
// the L2 array and convert it into the 128 bit corrected data
// 2. Mux 64 bit out of the 128 bit corrected data for the following
// 2 operations :-
// a. Partial Store.
// b. L2 Data Scrub.
// 3. Mux 39 bit out of the 155 bit uncorrected data for the following
// 3 operations :-
// a. Diagnostic accesses to l2data
// b. TAP reads to DRAM addresses.
// c. BIST accesses to l2data.
// Change ( 4/7/2003)
// Changed the input dword_sel_c8 to dword_sel_c7
// Keep the pin in the same place. Setup of
// dword_sel_c7 should be between 50-70ps.
// Added a 1 bit flop for dword_sel_c7.
module sctag_deccdp(/*AUTOARG*/
// Outputs
retdp_data_c8, deccdp_arbdp_data_c8, retdp_diag_data_c7,
lda_syndrome_c9, check0_c7, check1_c7, check2_c7, check3_c7,
parity0_c7, parity1_c7, parity2_c7, parity3_c7, so,
// Inputs
sel_higher_word_c7, sel_higher_dword_c7, dword_sel_c7,
retdp_data_c7, retdp_ecc_c7, rclk, si, se
);
output [127:0] retdp_data_c8; // data to oqdp
output [63:0] deccdp_arbdp_data_c8; // data to arbdatadp
output [38:0] retdp_diag_data_c7 ; // diagnostic data
output [27:0] lda_syndrome_c9; // to csr block
// from and to decc_ctl
input sel_higher_word_c7;
input sel_higher_dword_c7;
input dword_sel_c7;
output [5:0] check0_c7 ;
output [5:0] check1_c7 ;
output [5:0] check2_c7 ;
output [5:0] check3_c7 ;
output parity0_c7;
output parity1_c7;
output parity2_c7;
output parity3_c7;
input [127:0] retdp_data_c7;
input [27:0] retdp_ecc_c7;
input rclk;
input si, se;
output so;
wire [127:0] corr_data_c7;
wire [38:0] data_word0_c7;
wire [38:0] data_word1_c7;
wire [38:0] data_word2_c7;
wire [38:0] data_word3_c7;
wire [38:0] left_diag_out_c7;
wire [38:0] rgt_diag_out_c7;
wire [127:0] retdp_data_c8; // data to oqdp
wire [27:0] error_synd_c7;
wire [27:0] error_synd_c8;
wire dword_sel_c8;
zzecc_sctag_ecc39 bit117_155
(.dout(corr_data_c7[127:96]),
.cflag(check3_c7[5:0]),
.pflag(parity3_c7),
.parity(retdp_ecc_c7[27:21]),
.din(retdp_data_c7[127:96])
) ;
// msb to the left
dff_s #(32) ff_data_rtn_c8_127_96 // arrange this flop in 4 rows.
(.q (retdp_data_c8[127:96]), // interleave the bits
.din (corr_data_c7[127:96]), // For example, 96,100,104 .. belong to the same row
.clk (rclk),
.se(se), .si (), .so ()
) ;
zzecc_sctag_ecc39 bit78_116
(.dout(corr_data_c7[95:64]),
.cflag(check2_c7[5:0]),
.pflag(parity2_c7),
.parity(retdp_ecc_c7[20:14]),
.din(retdp_data_c7[95:64])
) ;
// msb to the left
dff_s #(32) ff_data_rtn_c8_95_64 // arrange this flop in 4 rows.
(.q (retdp_data_c8[95:64]), // interleave the bits
.din (corr_data_c7[95:64]), // For example, 64,68,8 .. belong to the same row
.clk (rclk),
.se(se), .si (), .so ()
) ;
zzecc_sctag_ecc39 bit39_77
(.dout(corr_data_c7[63:32]),
.cflag(check1_c7[5:0]),
.pflag(parity1_c7),
.parity(retdp_ecc_c7[13:7]),
.din(retdp_data_c7[63:32])
) ;
// msb to the left
dff_s #(32) ff_data_rtn_c8_63_32 // arrange this flop in 4 rows.
(.q (retdp_data_c8[63:32]), // interleave the bits
.din (corr_data_c7[63:32]), // For example, 32,36,40 .. belong to the same row
.clk (rclk),
.se(se), .si (), .so ()
) ;
zzecc_sctag_ecc39 bit0_38
(.dout (corr_data_c7[31:0]),
.cflag (check0_c7[5:0]),
.pflag (parity0_c7),
.parity (retdp_ecc_c7[6:0]),
.din (retdp_data_c7[31:0])
) ;
// msb to the left
dff_s #(32) ff_data_rtn_c8_31_0 // arrange this flop in 4 rows.
(.q (retdp_data_c8[31:0]), // interleave the bits
.din (corr_data_c7[31:0]), // For example, 32,36,40 .. belong to the same row
.clk (rclk),
.se(se), .si (), .so ()
) ;
//////////////////////////
// SYNDROME to csr_ctl.
//////////////////////////
assign error_synd_c7 = {parity3_c7,check3_c7[5:0],
parity2_c7,check2_c7[5:0],
parity1_c7,check1_c7[5:0],
parity0_c7,check0_c7[5:0]} ;
dff_s #(28) ff_error_synd_c8
(.q (error_synd_c8[27:0]),
.din (error_synd_c7[27:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(28) ff_lda_syndrome_c9
(.q (lda_syndrome_c9[27:0]),
.din (error_synd_c8[27:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_dword_sel_c8
(.q (dword_sel_c8),
.din (dword_sel_c7),
.clk (rclk),
.se(se), .si (), .so ()
) ;
mux2ds #(64) ret_mux
(.dout (deccdp_arbdp_data_c8[63:0]),
.in0 (retdp_data_c8[127:64]), .sel0 (~dword_sel_c8),
.in1 (retdp_data_c8[63:0]), .sel1 (dword_sel_c8)
) ;
assign data_word1_c7 = {retdp_data_c7[95:64], retdp_ecc_c7[20:14]} ;
assign data_word0_c7 = {retdp_data_c7[127:96],retdp_ecc_c7[27:21]} ;
mux2ds #(39) mux_left_diag_out
(.dout (left_diag_out_c7[38:0]),
.in0 (data_word0_c7[38:0]), .sel0 (~sel_higher_word_c7),
.in1 (data_word1_c7[38:0]), .sel1 (sel_higher_word_c7)
) ;
assign data_word3_c7 = {retdp_data_c7[31:0], retdp_ecc_c7[6:0]} ;
assign data_word2_c7 = {retdp_data_c7[63:32], retdp_ecc_c7[13:7]} ;
mux2ds #(39) mux_rgt_diag_out
(.dout (rgt_diag_out_c7[38:0]),
.in0 (data_word2_c7[38:0]), .sel0 (~sel_higher_word_c7),
.in1 (data_word3_c7[38:0]), .sel1 (sel_higher_word_c7)
) ;
mux2ds #(39) mux_diag_out
(.dout (retdp_diag_data_c7[38:0]),
.in0 (left_diag_out_c7[38:0]), .sel0 (~sel_higher_dword_c7),
.in1 (rgt_diag_out_c7[38:0]), .sel1 (sel_higher_dword_c7)
) ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311AI_1_V
`define SKY130_FD_SC_LP__O311AI_1_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311ai_1 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311AI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_BLACKBOX_V
`define SKY130_FD_SC_HS__FA_BLACKBOX_V
/**
* fa: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_BLACKBOX_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_a.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No user `defines in this module
module ent_a
//
// Generated Module inst_a
//
(
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Generated Module Inputs:
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output sig_o_a2;
// Generated Wires:
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22O_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A22O_BEHAVIORAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22O_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A31O_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a31o (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_8_V
`define SKY130_FD_SC_LS__EBUFN_8_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_8_V
|
// megafunction wizard: %LPM_CLSHIFT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_CLSHIFT
// ============================================================
// File Name: shift16.v
// Megafunction Name(s):
// LPM_CLSHIFT
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module shift16 (
data,
direction,
distance,
result);
input [31:0] data;
input direction;
input [3:0] distance;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_clshift LPM_CLSHIFT_component (
.data (data),
.direction (direction),
.distance (distance),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.overflow (),
.underflow ()
// synopsys translate_on
);
defparam
LPM_CLSHIFT_component.lpm_shifttype = "LOGICAL",
LPM_CLSHIFT_component.lpm_type = "LPM_CLSHIFT",
LPM_CLSHIFT_component.lpm_width = 32,
LPM_CLSHIFT_component.lpm_widthdist = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
// Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "32"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: lpm_widthdist NUMERIC "4"
// Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: port_direction NUMERIC "2"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL "direction"
// Retrieval info: USED_PORT: distance 0 0 4 0 INPUT NODEFVAL "distance[3..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
// Retrieval info: CONNECT: @distance 0 0 4 0 distance 0 0 4 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16_bb.v FALSE
|
module user_design(clk, rst, exception, input_rs232_rx, input_gps_rx, input_gps_count, input_rs232_rx_stb, input_gps_rx_stb, input_gps_count_stb, input_rs232_rx_ack, input_gps_rx_ack, input_gps_count_ack, output_tx_ctl, output_rs232_tx, output_leds, output_gps_tx, output_tx_freq, output_tx_am, output_tx_ctl_stb, output_rs232_tx_stb, output_leds_stb, output_gps_tx_stb, output_tx_freq_stb, output_tx_am_stb, output_tx_ctl_ack, output_rs232_tx_ack, output_leds_ack, output_gps_tx_ack, output_tx_freq_ack, output_tx_am_ack);
input clk;
input rst;
output exception;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_gps_rx;
input input_gps_rx_stb;
output input_gps_rx_ack;
input [31:0] input_gps_count;
input input_gps_count_stb;
output input_gps_count_ack;
output [31:0] output_tx_ctl;
output output_tx_ctl_stb;
input output_tx_ctl_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_gps_tx;
output output_gps_tx_stb;
input output_gps_tx_ack;
output [31:0] output_tx_freq;
output output_tx_freq_stb;
input output_tx_freq_ack;
output [31:0] output_tx_am;
output output_tx_am_stb;
input output_tx_am_ack;
wire exception_140447914110056;
main_0 main_0_140447914110056(
.clk(clk),
.rst(rst),
.exception(exception_140447914110056),
.input_gps_count(input_gps_count),
.input_gps_count_stb(input_gps_count_stb),
.input_gps_count_ack(input_gps_count_ack),
.input_gps_rx(input_gps_rx),
.input_gps_rx_stb(input_gps_rx_stb),
.input_gps_rx_ack(input_gps_rx_ack),
.input_rs232_rx(input_rs232_rx),
.input_rs232_rx_stb(input_rs232_rx_stb),
.input_rs232_rx_ack(input_rs232_rx_ack),
.output_rs232_tx(output_rs232_tx),
.output_rs232_tx_stb(output_rs232_tx_stb),
.output_rs232_tx_ack(output_rs232_tx_ack),
.output_leds(output_leds),
.output_leds_stb(output_leds_stb),
.output_leds_ack(output_leds_ack),
.output_freq_out(output_tx_freq),
.output_freq_out_stb(output_tx_freq_stb),
.output_freq_out_ack(output_tx_freq_ack),
.output_gps_tx(output_gps_tx),
.output_gps_tx_stb(output_gps_tx_stb),
.output_gps_tx_ack(output_gps_tx_ack),
.output_ctl_out(output_tx_ctl),
.output_ctl_out_stb(output_tx_ctl_stb),
.output_ctl_out_ack(output_tx_ctl_ack),
.output_am_out(output_tx_am),
.output_am_out_stb(output_tx_am_stb),
.output_am_out_ack(output_tx_am_ack));
assign exception = exception_140447914110056;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFBUF_8_V
`define SKY130_FD_SC_MS__BUFBUF_8_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__bufbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__bufbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFBUF_8_V
|
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 1.5
// \ \ Application : 7 Series FPGAs Transceivers Wizard
// / / Filename : rocketio_wrapper_tile_gt_frame_gen.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Module ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
//
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ns / 1ps
`define DLY #1
//***********************************Entity Declaration*******************************
module ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
// parameter to set the number of words in the BRAM
parameter WORDS_IN_BRAM = 512
)
(
// User Interface
output reg [79:0] TX_DATA_OUT,
output reg [7:0] TXCTRL_OUT,
// System Interface
input wire USER_CLK,
input wire SYSTEM_RESET
);
//********************************* Wire Declarations*********************************
wire tied_to_ground_i;
wire [31:0] tied_to_ground_vec_i;
wire [63:0] tx_data_bram_i;
wire [7:0] tx_ctrl_i;
//***************************Internal Register Declarations***************************
reg [8:0] read_counter_i;
reg [79:0] rom [0:511];
reg [79:0] tx_data_ram_r;
reg system_reset_r;
//*********************************Main Body of Code**********************************
assign tied_to_ground_vec_i = 32'h00000000;
assign tied_to_ground_i = 1'b0;
assign tied_to_vcc_i = 1'b1;
//___________ synchronizing the async reset for ease of timing simulation ________
always@(posedge USER_CLK)
system_reset_r <= `DLY SYSTEM_RESET;
//____________________________ Counter to read from BRAM __________________________
always @(posedge USER_CLK)
if(system_reset_r || (read_counter_i == "111111111"))
begin
read_counter_i <= `DLY 9'd0;
end
else read_counter_i <= `DLY read_counter_i + 9'd1;
// Assign TX_DATA_OUT to BRAM output
always @(posedge USER_CLK)
if(system_reset_r) TX_DATA_OUT <= `DLY 80'h0000000000;
else TX_DATA_OUT <= `DLY {tx_data_bram_i,tx_data_ram_r[15:0]};
// Assign TXCTRL_OUT to BRAM output
always @(posedge USER_CLK)
if(system_reset_r) TXCTRL_OUT <= `DLY 8'h0;
else TXCTRL_OUT <= `DLY tx_ctrl_i;
//________________________________ BRAM Inference Logic _____________________________
assign tx_data_bram_i = tx_data_ram_r[79:16];
assign tx_ctrl_i = tx_data_ram_r[15:8];
// initial
// begin
// $readmemh("../../mgt/gt_rom_init_tx.dat",rom,0,511);
// end
always @(posedge USER_CLK)
tx_data_ram_r <= `DLY rom[read_counter_i];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_1_V
`define SKY130_FD_SC_LS__O22AI_1_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22ai_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cluster_header_sync.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// The sync pulse cluster header is instatiated as a hard macro.
// This model is for simulation only.
module cluster_header_sync (/*AUTOARG*/
// Outputs
dram_rx_sync_local, dram_tx_sync_local, jbus_rx_sync_local,
jbus_tx_sync_local, so,
// Inputs
dram_rx_sync_global, dram_tx_sync_global, jbus_rx_sync_global,
jbus_tx_sync_global, cmp_gclk, cmp_rclk, si, se
);
output dram_rx_sync_local;
output dram_tx_sync_local;
output jbus_rx_sync_local;
output jbus_tx_sync_local;
output so;
input dram_rx_sync_global;
input dram_tx_sync_global;
input jbus_rx_sync_global;
input jbus_tx_sync_global;
input cmp_gclk;
input cmp_rclk;
input si;
input se;
wire dram_rx_so;
wire dram_tx_so;
wire jbus_rx_so;
bw_clk_cclk_sync sync_wrapper (
.dram_rx_sync_local(dram_rx_sync_local),
.dram_tx_sync_local(dram_tx_sync_local),
.jbus_rx_sync_local(jbus_rx_sync_local),
.jbus_tx_sync_local(jbus_tx_sync_local),
.so(so),
.dram_rx_sync_global(dram_rx_sync_global),
.dram_tx_sync_global(dram_tx_sync_global),
.jbus_rx_sync_global(jbus_rx_sync_global),
.jbus_tx_sync_global(jbus_tx_sync_global),
.cmp_gclk(cmp_gclk),
.cmp_rclk(cmp_rclk),
.si(si),
.se(se)
);
endmodule // cluster_header_sync
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_4_V
`define SKY130_FD_SC_LS__A22OI_4_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a22oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a22oi_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_4_V
|
`timescale 1ns/1ps
module tb_cocotb #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXIS_WIDTH = 24,
parameter AXIS_STROBE_WIDTH = (AXIS_WIDTH / 8),
parameter BUFFER_SIZE = 3
)(
input clk,
input rst,
input i_fsync,
//Write Address Channel
input AXIML_AWVALID,
input [ADDR_WIDTH - 1: 0] AXIML_AWADDR,
output AXIML_AWREADY,
//Write Data Channel
input AXIML_WVALID,
output AXIML_WREADY,
input [STROBE_WIDTH - 1:0] AXIML_WSTRB,
input [DATA_WIDTH - 1: 0] AXIML_WDATA,
//Write Response Channel
output AXIML_BVALID,
input AXIML_BREADY,
output [1:0] AXIML_BRESP,
//Read Address Channel
input AXIML_ARVALID,
output AXIML_ARREADY,
input [ADDR_WIDTH - 1: 0] AXIML_ARADDR,
//Read Data Channel
output AXIML_RVALID,
input AXIML_RREADY,
output [1:0] AXIML_RRESP,
output [DATA_WIDTH - 1: 0] AXIML_RDATA,
input [AXIS_WIDTH - 1:0] AXIMS_TDATA,
input AXIMS_TREADY,
input AXIMS_TVALID,
input AXIMS_TLAST,
input [AXIS_STROBE_WIDTH - 1: 0] AXIMS_TKEEP,
input [AXIS_STROBE_WIDTH - 1: 0] AXIMS_TSTRB,
input [3:0] AXIMS_TID,
input [31:0] AXIMS_TDEST,
input [3:0] AXIMS_TUSER
);
//Local Parameters
//Registers
reg r_rst;
always @ (*) r_rst = rst;
reg [3:0] test_id = 0;
reg [31:0] r_tear_count;
reg [7:0] r_tear_status;
wire w_register_data_sel;
reg r_tearing_effect;
wire w_write_n;
wire w_read_n;
wire [7:0] w_data;
wire [7:0] w_out_data;
wire [7:0] w_tri_data;
wire w_cs_n;
wire w_reset_n;
reg [7:0] r_read_data;
reg [15:0] r_write_parameter;
wire [3:0] w_axis_user;
assign w_axis_user = {3'h0, i_fsync};
//submodules
axi_pmod_tft #(
// .ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH ),
.AXIS_WIDTH (AXIS_WIDTH ),
.INVERT_AXI_RESET (0 ),
.INVERT_AXIS_RESET (0 ),
.BUFFER_SIZE (BUFFER_SIZE )
) dut (
.clk (clk ),
.rst (r_rst ),
//AXI Lite Interface
.i_awvalid (AXIML_AWVALID ),
.i_awaddr (AXIML_AWADDR ),
.o_awready (AXIML_AWREADY ),
.i_wvalid (AXIML_WVALID ),
.o_wready (AXIML_WREADY ),
.i_wstrb (AXIML_WSTRB ),
.i_wdata (AXIML_WDATA ),
.o_bvalid (AXIML_BVALID ),
.i_bready (AXIML_BREADY ),
.o_bresp (AXIML_BRESP ),
.i_arvalid (AXIML_ARVALID ),
.o_arready (AXIML_ARREADY ),
.i_araddr (AXIML_ARADDR ),
.o_rvalid (AXIML_RVALID ),
.i_rready (AXIML_RREADY ),
.o_rresp (AXIML_RRESP ),
.o_rdata (AXIML_RDATA ),
//AXI Stream
.i_axis_clk (clk ),
.i_axis_rst (r_rst ),
.o_axis_ready (AXIMS_TREADY ),
.i_axis_data (AXIMS_TDATA ),
.i_axis_last (AXIMS_TLAST ),
.i_axis_valid (AXIMS_TVALID ),
//.i_fsync (i_fsync ),
.i_axis_user (w_axis_user ),
//Physical Signals
.i_tearing_effect (r_tearing_effect ),
.o_register_data_sel (w_register_data_sel ),
.o_write_n (w_write_n ),
.o_read_n (w_read_n ),
.o_cs_n (w_cs_n ),
.o_reset_n (w_reset_n ),
.o_pmod_out_tft_data3 (w_out_data[0] ),
.o_pmod_out_tft_data8 (w_out_data[1] ),
.o_pmod_out_tft_data2 (w_out_data[2] ),
.o_pmod_out_tft_data1 (w_out_data[3] ),
.o_pmod_out_tft_data7 (w_out_data[4] ),
.o_pmod_out_tft_data9 (w_out_data[5] ),
.o_pmod_out_tft_data4 (w_out_data[6] ),
.o_pmod_out_tft_data10 (w_out_data[7] ),
.o_pmod_tri_tft_data3 (w_tri_data[0] ),
.o_pmod_tri_tft_data8 (w_tri_data[1] ),
.o_pmod_tri_tft_data2 (w_tri_data[2] ),
.o_pmod_tri_tft_data1 (w_tri_data[3] ),
.o_pmod_tri_tft_data7 (w_tri_data[4] ),
.o_pmod_tri_tft_data9 (w_tri_data[5] ),
.o_pmod_tri_tft_data4 (w_tri_data[6] ),
.o_pmod_tri_tft_data10 (w_tri_data[7] ),
.i_pmod_in_tft_data3 (r_read_data[0] ),
.i_pmod_in_tft_data8 (r_read_data[1] ),
.i_pmod_in_tft_data2 (r_read_data[2] ),
.i_pmod_in_tft_data1 (r_read_data[3] ),
.i_pmod_in_tft_data7 (r_read_data[4] ),
.i_pmod_in_tft_data9 (r_read_data[5] ),
.i_pmod_in_tft_data4 (r_read_data[6] ),
.i_pmod_in_tft_data10 (r_read_data[7] )
);
//asynchronus logic
//synchronous logic
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
always @ (posedge clk) begin
if (rst) begin
r_tear_count <= 0;
r_tear_status <= 8'h00;
r_tearing_effect <= 0;
end
else begin
if (r_tear_count < 400) begin
r_tear_count <= r_tear_count + 1;
end
else begin
if (r_tear_status == 8'h00) begin
r_tear_status <= 8'h80;
r_tearing_effect <= 1;
end
else begin
r_tear_status <= 8'h00;
r_tearing_effect <= 0;
end
r_tear_count <= 0;
end
end
end
always @ (posedge clk) begin
if (rst) begin
r_read_data <= 0;
r_write_parameter <= 0;
end
else begin
if (!w_write_n && w_register_data_sel) begin
r_write_parameter <= {r_write_parameter[7:0], w_out_data};
end
if (!w_register_data_sel & !w_cs_n) begin
case (w_out_data)
0: begin
r_read_data <= 8'h01;
end
14: begin
r_read_data <= r_tear_status;
end
44: begin
r_read_data <= 8'hFF;
end
184: begin
r_read_data <= 8'hAA;
end
endcase
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_MUX_2TO1_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_MUX_2TO1_BLACKBOX_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_mux_2to1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_MUX_2TO1_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module pixelq_op_top (
s_axi_CONTROL_BUS_AWADDR,
s_axi_CONTROL_BUS_AWVALID,
s_axi_CONTROL_BUS_AWREADY,
s_axi_CONTROL_BUS_WDATA,
s_axi_CONTROL_BUS_WSTRB,
s_axi_CONTROL_BUS_WVALID,
s_axi_CONTROL_BUS_WREADY,
s_axi_CONTROL_BUS_BRESP,
s_axi_CONTROL_BUS_BVALID,
s_axi_CONTROL_BUS_BREADY,
s_axi_CONTROL_BUS_ARADDR,
s_axi_CONTROL_BUS_ARVALID,
s_axi_CONTROL_BUS_ARREADY,
s_axi_CONTROL_BUS_RDATA,
s_axi_CONTROL_BUS_RRESP,
s_axi_CONTROL_BUS_RVALID,
s_axi_CONTROL_BUS_RREADY,
interrupt,
INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY,
INPUT_STREAM_TDATA,
INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST,
INPUT_STREAM_TID,
INPUT_STREAM_TDEST,
OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST,
aresetn,
aclk
);
parameter C_S_AXI_CONTROL_BUS_ADDR_WIDTH = 5;
parameter C_S_AXI_CONTROL_BUS_DATA_WIDTH = 32;
parameter RESET_ACTIVE_LOW = 1;
input [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1:0] s_axi_CONTROL_BUS_AWADDR ;
input s_axi_CONTROL_BUS_AWVALID ;
output s_axi_CONTROL_BUS_AWREADY ;
input [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1:0] s_axi_CONTROL_BUS_WDATA ;
input [C_S_AXI_CONTROL_BUS_DATA_WIDTH/8 - 1:0] s_axi_CONTROL_BUS_WSTRB ;
input s_axi_CONTROL_BUS_WVALID ;
output s_axi_CONTROL_BUS_WREADY ;
output [2 - 1:0] s_axi_CONTROL_BUS_BRESP ;
output s_axi_CONTROL_BUS_BVALID ;
input s_axi_CONTROL_BUS_BREADY ;
input [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1:0] s_axi_CONTROL_BUS_ARADDR ;
input s_axi_CONTROL_BUS_ARVALID ;
output s_axi_CONTROL_BUS_ARREADY ;
output [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1:0] s_axi_CONTROL_BUS_RDATA ;
output [2 - 1:0] s_axi_CONTROL_BUS_RRESP ;
output s_axi_CONTROL_BUS_RVALID ;
input s_axi_CONTROL_BUS_RREADY ;
output interrupt ;
input INPUT_STREAM_TVALID ;
output INPUT_STREAM_TREADY ;
input [24 - 1:0] INPUT_STREAM_TDATA ;
input [3 - 1:0] INPUT_STREAM_TKEEP ;
input [3 - 1:0] INPUT_STREAM_TSTRB ;
input [1 - 1:0] INPUT_STREAM_TUSER ;
input [1 - 1:0] INPUT_STREAM_TLAST ;
input [1 - 1:0] INPUT_STREAM_TID ;
input [1 - 1:0] INPUT_STREAM_TDEST ;
output OUTPUT_STREAM_TVALID ;
input OUTPUT_STREAM_TREADY ;
output [24 - 1:0] OUTPUT_STREAM_TDATA ;
output [3 - 1:0] OUTPUT_STREAM_TKEEP ;
output [3 - 1:0] OUTPUT_STREAM_TSTRB ;
output [1 - 1:0] OUTPUT_STREAM_TUSER ;
output [1 - 1:0] OUTPUT_STREAM_TLAST ;
output [1 - 1:0] OUTPUT_STREAM_TID ;
output [1 - 1:0] OUTPUT_STREAM_TDEST ;
input aresetn ;
input aclk ;
wire [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1:0] s_axi_CONTROL_BUS_AWADDR;
wire s_axi_CONTROL_BUS_AWVALID;
wire s_axi_CONTROL_BUS_AWREADY;
wire [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1:0] s_axi_CONTROL_BUS_WDATA;
wire [C_S_AXI_CONTROL_BUS_DATA_WIDTH/8 - 1:0] s_axi_CONTROL_BUS_WSTRB;
wire s_axi_CONTROL_BUS_WVALID;
wire s_axi_CONTROL_BUS_WREADY;
wire [2 - 1:0] s_axi_CONTROL_BUS_BRESP;
wire s_axi_CONTROL_BUS_BVALID;
wire s_axi_CONTROL_BUS_BREADY;
wire [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1:0] s_axi_CONTROL_BUS_ARADDR;
wire s_axi_CONTROL_BUS_ARVALID;
wire s_axi_CONTROL_BUS_ARREADY;
wire [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1:0] s_axi_CONTROL_BUS_RDATA;
wire [2 - 1:0] s_axi_CONTROL_BUS_RRESP;
wire s_axi_CONTROL_BUS_RVALID;
wire s_axi_CONTROL_BUS_RREADY;
wire interrupt;
wire INPUT_STREAM_TVALID;
wire INPUT_STREAM_TREADY;
wire [24 - 1:0] INPUT_STREAM_TDATA;
wire [3 - 1:0] INPUT_STREAM_TKEEP;
wire [3 - 1:0] INPUT_STREAM_TSTRB;
wire [1 - 1:0] INPUT_STREAM_TUSER;
wire [1 - 1:0] INPUT_STREAM_TLAST;
wire [1 - 1:0] INPUT_STREAM_TID;
wire [1 - 1:0] INPUT_STREAM_TDEST;
wire OUTPUT_STREAM_TVALID;
wire OUTPUT_STREAM_TREADY;
wire [24 - 1:0] OUTPUT_STREAM_TDATA;
wire [3 - 1:0] OUTPUT_STREAM_TKEEP;
wire [3 - 1:0] OUTPUT_STREAM_TSTRB;
wire [1 - 1:0] OUTPUT_STREAM_TUSER;
wire [1 - 1:0] OUTPUT_STREAM_TLAST;
wire [1 - 1:0] OUTPUT_STREAM_TID;
wire [1 - 1:0] OUTPUT_STREAM_TDEST;
wire aresetn;
wire [32 - 1:0] sig_pixelq_op_rows;
wire [32 - 1:0] sig_pixelq_op_cols;
wire sig_pixelq_op_ap_start;
wire sig_pixelq_op_ap_ready;
wire sig_pixelq_op_ap_done;
wire sig_pixelq_op_ap_idle;
wire [24 - 1:0] sig_pixelq_op_src_axi_V_data_V_dout;
wire sig_pixelq_op_src_axi_V_data_V_empty_n;
wire sig_pixelq_op_src_axi_V_data_V_read;
wire [3 - 1:0] sig_pixelq_op_src_axi_V_keep_V_dout;
wire sig_pixelq_op_src_axi_V_keep_V_empty_n;
wire sig_pixelq_op_src_axi_V_keep_V_read;
wire [3 - 1:0] sig_pixelq_op_src_axi_V_strb_V_dout;
wire sig_pixelq_op_src_axi_V_strb_V_empty_n;
wire sig_pixelq_op_src_axi_V_strb_V_read;
wire [1 - 1:0] sig_pixelq_op_src_axi_V_user_V_dout;
wire sig_pixelq_op_src_axi_V_user_V_empty_n;
wire sig_pixelq_op_src_axi_V_user_V_read;
wire [1 - 1:0] sig_pixelq_op_src_axi_V_last_V_dout;
wire sig_pixelq_op_src_axi_V_last_V_empty_n;
wire sig_pixelq_op_src_axi_V_last_V_read;
wire [1 - 1:0] sig_pixelq_op_src_axi_V_id_V_dout;
wire sig_pixelq_op_src_axi_V_id_V_empty_n;
wire sig_pixelq_op_src_axi_V_id_V_read;
wire [1 - 1:0] sig_pixelq_op_src_axi_V_dest_V_dout;
wire sig_pixelq_op_src_axi_V_dest_V_empty_n;
wire sig_pixelq_op_src_axi_V_dest_V_read;
wire [24 - 1:0] sig_pixelq_op_dst_axi_V_data_V_din;
wire sig_pixelq_op_dst_axi_V_data_V_full_n;
wire sig_pixelq_op_dst_axi_V_data_V_write;
wire [3 - 1:0] sig_pixelq_op_dst_axi_V_keep_V_din;
wire sig_pixelq_op_dst_axi_V_keep_V_full_n;
wire sig_pixelq_op_dst_axi_V_keep_V_write;
wire [3 - 1:0] sig_pixelq_op_dst_axi_V_strb_V_din;
wire sig_pixelq_op_dst_axi_V_strb_V_full_n;
wire sig_pixelq_op_dst_axi_V_strb_V_write;
wire [1 - 1:0] sig_pixelq_op_dst_axi_V_user_V_din;
wire sig_pixelq_op_dst_axi_V_user_V_full_n;
wire sig_pixelq_op_dst_axi_V_user_V_write;
wire [1 - 1:0] sig_pixelq_op_dst_axi_V_last_V_din;
wire sig_pixelq_op_dst_axi_V_last_V_full_n;
wire sig_pixelq_op_dst_axi_V_last_V_write;
wire [1 - 1:0] sig_pixelq_op_dst_axi_V_id_V_din;
wire sig_pixelq_op_dst_axi_V_id_V_full_n;
wire sig_pixelq_op_dst_axi_V_id_V_write;
wire [1 - 1:0] sig_pixelq_op_dst_axi_V_dest_V_din;
wire sig_pixelq_op_dst_axi_V_dest_V_full_n;
wire sig_pixelq_op_dst_axi_V_dest_V_write;
wire sig_pixelq_op_ap_rst;
pixelq_op pixelq_op_U(
.rows(sig_pixelq_op_rows),
.cols(sig_pixelq_op_cols),
.ap_start(sig_pixelq_op_ap_start),
.ap_ready(sig_pixelq_op_ap_ready),
.ap_done(sig_pixelq_op_ap_done),
.ap_idle(sig_pixelq_op_ap_idle),
.src_axi_V_data_V_dout(sig_pixelq_op_src_axi_V_data_V_dout),
.src_axi_V_data_V_empty_n(sig_pixelq_op_src_axi_V_data_V_empty_n),
.src_axi_V_data_V_read(sig_pixelq_op_src_axi_V_data_V_read),
.src_axi_V_keep_V_dout(sig_pixelq_op_src_axi_V_keep_V_dout),
.src_axi_V_keep_V_empty_n(sig_pixelq_op_src_axi_V_keep_V_empty_n),
.src_axi_V_keep_V_read(sig_pixelq_op_src_axi_V_keep_V_read),
.src_axi_V_strb_V_dout(sig_pixelq_op_src_axi_V_strb_V_dout),
.src_axi_V_strb_V_empty_n(sig_pixelq_op_src_axi_V_strb_V_empty_n),
.src_axi_V_strb_V_read(sig_pixelq_op_src_axi_V_strb_V_read),
.src_axi_V_user_V_dout(sig_pixelq_op_src_axi_V_user_V_dout),
.src_axi_V_user_V_empty_n(sig_pixelq_op_src_axi_V_user_V_empty_n),
.src_axi_V_user_V_read(sig_pixelq_op_src_axi_V_user_V_read),
.src_axi_V_last_V_dout(sig_pixelq_op_src_axi_V_last_V_dout),
.src_axi_V_last_V_empty_n(sig_pixelq_op_src_axi_V_last_V_empty_n),
.src_axi_V_last_V_read(sig_pixelq_op_src_axi_V_last_V_read),
.src_axi_V_id_V_dout(sig_pixelq_op_src_axi_V_id_V_dout),
.src_axi_V_id_V_empty_n(sig_pixelq_op_src_axi_V_id_V_empty_n),
.src_axi_V_id_V_read(sig_pixelq_op_src_axi_V_id_V_read),
.src_axi_V_dest_V_dout(sig_pixelq_op_src_axi_V_dest_V_dout),
.src_axi_V_dest_V_empty_n(sig_pixelq_op_src_axi_V_dest_V_empty_n),
.src_axi_V_dest_V_read(sig_pixelq_op_src_axi_V_dest_V_read),
.dst_axi_V_data_V_din(sig_pixelq_op_dst_axi_V_data_V_din),
.dst_axi_V_data_V_full_n(sig_pixelq_op_dst_axi_V_data_V_full_n),
.dst_axi_V_data_V_write(sig_pixelq_op_dst_axi_V_data_V_write),
.dst_axi_V_keep_V_din(sig_pixelq_op_dst_axi_V_keep_V_din),
.dst_axi_V_keep_V_full_n(sig_pixelq_op_dst_axi_V_keep_V_full_n),
.dst_axi_V_keep_V_write(sig_pixelq_op_dst_axi_V_keep_V_write),
.dst_axi_V_strb_V_din(sig_pixelq_op_dst_axi_V_strb_V_din),
.dst_axi_V_strb_V_full_n(sig_pixelq_op_dst_axi_V_strb_V_full_n),
.dst_axi_V_strb_V_write(sig_pixelq_op_dst_axi_V_strb_V_write),
.dst_axi_V_user_V_din(sig_pixelq_op_dst_axi_V_user_V_din),
.dst_axi_V_user_V_full_n(sig_pixelq_op_dst_axi_V_user_V_full_n),
.dst_axi_V_user_V_write(sig_pixelq_op_dst_axi_V_user_V_write),
.dst_axi_V_last_V_din(sig_pixelq_op_dst_axi_V_last_V_din),
.dst_axi_V_last_V_full_n(sig_pixelq_op_dst_axi_V_last_V_full_n),
.dst_axi_V_last_V_write(sig_pixelq_op_dst_axi_V_last_V_write),
.dst_axi_V_id_V_din(sig_pixelq_op_dst_axi_V_id_V_din),
.dst_axi_V_id_V_full_n(sig_pixelq_op_dst_axi_V_id_V_full_n),
.dst_axi_V_id_V_write(sig_pixelq_op_dst_axi_V_id_V_write),
.dst_axi_V_dest_V_din(sig_pixelq_op_dst_axi_V_dest_V_din),
.dst_axi_V_dest_V_full_n(sig_pixelq_op_dst_axi_V_dest_V_full_n),
.dst_axi_V_dest_V_write(sig_pixelq_op_dst_axi_V_dest_V_write),
.ap_rst(sig_pixelq_op_ap_rst),
.ap_clk(aclk)
);
pixelq_op_CONTROL_BUS_if #(
.C_ADDR_WIDTH(C_S_AXI_CONTROL_BUS_ADDR_WIDTH),
.C_DATA_WIDTH(C_S_AXI_CONTROL_BUS_DATA_WIDTH))
pixelq_op_CONTROL_BUS_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.I_rows(sig_pixelq_op_rows),
.I_cols(sig_pixelq_op_cols),
.I_ap_start(sig_pixelq_op_ap_start),
.O_ap_ready(sig_pixelq_op_ap_ready),
.O_ap_done(sig_pixelq_op_ap_done),
.O_ap_idle(sig_pixelq_op_ap_idle),
.AWADDR(s_axi_CONTROL_BUS_AWADDR),
.AWVALID(s_axi_CONTROL_BUS_AWVALID),
.AWREADY(s_axi_CONTROL_BUS_AWREADY),
.WDATA(s_axi_CONTROL_BUS_WDATA),
.WSTRB(s_axi_CONTROL_BUS_WSTRB),
.WVALID(s_axi_CONTROL_BUS_WVALID),
.WREADY(s_axi_CONTROL_BUS_WREADY),
.BRESP(s_axi_CONTROL_BUS_BRESP),
.BVALID(s_axi_CONTROL_BUS_BVALID),
.BREADY(s_axi_CONTROL_BUS_BREADY),
.ARADDR(s_axi_CONTROL_BUS_ARADDR),
.ARVALID(s_axi_CONTROL_BUS_ARVALID),
.ARREADY(s_axi_CONTROL_BUS_ARREADY),
.RDATA(s_axi_CONTROL_BUS_RDATA),
.RRESP(s_axi_CONTROL_BUS_RRESP),
.RVALID(s_axi_CONTROL_BUS_RVALID),
.RREADY(s_axi_CONTROL_BUS_RREADY),
.interrupt(interrupt));
pixelq_op_INPUT_STREAM_if pixelq_op_INPUT_STREAM_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.src_axi_V_data_V_dout(sig_pixelq_op_src_axi_V_data_V_dout),
.src_axi_V_data_V_empty_n(sig_pixelq_op_src_axi_V_data_V_empty_n),
.src_axi_V_data_V_read(sig_pixelq_op_src_axi_V_data_V_read),
.src_axi_V_keep_V_dout(sig_pixelq_op_src_axi_V_keep_V_dout),
.src_axi_V_keep_V_empty_n(sig_pixelq_op_src_axi_V_keep_V_empty_n),
.src_axi_V_keep_V_read(sig_pixelq_op_src_axi_V_keep_V_read),
.src_axi_V_strb_V_dout(sig_pixelq_op_src_axi_V_strb_V_dout),
.src_axi_V_strb_V_empty_n(sig_pixelq_op_src_axi_V_strb_V_empty_n),
.src_axi_V_strb_V_read(sig_pixelq_op_src_axi_V_strb_V_read),
.src_axi_V_user_V_dout(sig_pixelq_op_src_axi_V_user_V_dout),
.src_axi_V_user_V_empty_n(sig_pixelq_op_src_axi_V_user_V_empty_n),
.src_axi_V_user_V_read(sig_pixelq_op_src_axi_V_user_V_read),
.src_axi_V_last_V_dout(sig_pixelq_op_src_axi_V_last_V_dout),
.src_axi_V_last_V_empty_n(sig_pixelq_op_src_axi_V_last_V_empty_n),
.src_axi_V_last_V_read(sig_pixelq_op_src_axi_V_last_V_read),
.src_axi_V_id_V_dout(sig_pixelq_op_src_axi_V_id_V_dout),
.src_axi_V_id_V_empty_n(sig_pixelq_op_src_axi_V_id_V_empty_n),
.src_axi_V_id_V_read(sig_pixelq_op_src_axi_V_id_V_read),
.src_axi_V_dest_V_dout(sig_pixelq_op_src_axi_V_dest_V_dout),
.src_axi_V_dest_V_empty_n(sig_pixelq_op_src_axi_V_dest_V_empty_n),
.src_axi_V_dest_V_read(sig_pixelq_op_src_axi_V_dest_V_read),
.TVALID(INPUT_STREAM_TVALID),
.TREADY(INPUT_STREAM_TREADY),
.TDATA(INPUT_STREAM_TDATA),
.TKEEP(INPUT_STREAM_TKEEP),
.TSTRB(INPUT_STREAM_TSTRB),
.TUSER(INPUT_STREAM_TUSER),
.TLAST(INPUT_STREAM_TLAST),
.TID(INPUT_STREAM_TID),
.TDEST(INPUT_STREAM_TDEST));
pixelq_op_OUTPUT_STREAM_if pixelq_op_OUTPUT_STREAM_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.dst_axi_V_data_V_din(sig_pixelq_op_dst_axi_V_data_V_din),
.dst_axi_V_data_V_full_n(sig_pixelq_op_dst_axi_V_data_V_full_n),
.dst_axi_V_data_V_write(sig_pixelq_op_dst_axi_V_data_V_write),
.dst_axi_V_keep_V_din(sig_pixelq_op_dst_axi_V_keep_V_din),
.dst_axi_V_keep_V_full_n(sig_pixelq_op_dst_axi_V_keep_V_full_n),
.dst_axi_V_keep_V_write(sig_pixelq_op_dst_axi_V_keep_V_write),
.dst_axi_V_strb_V_din(sig_pixelq_op_dst_axi_V_strb_V_din),
.dst_axi_V_strb_V_full_n(sig_pixelq_op_dst_axi_V_strb_V_full_n),
.dst_axi_V_strb_V_write(sig_pixelq_op_dst_axi_V_strb_V_write),
.dst_axi_V_user_V_din(sig_pixelq_op_dst_axi_V_user_V_din),
.dst_axi_V_user_V_full_n(sig_pixelq_op_dst_axi_V_user_V_full_n),
.dst_axi_V_user_V_write(sig_pixelq_op_dst_axi_V_user_V_write),
.dst_axi_V_last_V_din(sig_pixelq_op_dst_axi_V_last_V_din),
.dst_axi_V_last_V_full_n(sig_pixelq_op_dst_axi_V_last_V_full_n),
.dst_axi_V_last_V_write(sig_pixelq_op_dst_axi_V_last_V_write),
.dst_axi_V_id_V_din(sig_pixelq_op_dst_axi_V_id_V_din),
.dst_axi_V_id_V_full_n(sig_pixelq_op_dst_axi_V_id_V_full_n),
.dst_axi_V_id_V_write(sig_pixelq_op_dst_axi_V_id_V_write),
.dst_axi_V_dest_V_din(sig_pixelq_op_dst_axi_V_dest_V_din),
.dst_axi_V_dest_V_full_n(sig_pixelq_op_dst_axi_V_dest_V_full_n),
.dst_axi_V_dest_V_write(sig_pixelq_op_dst_axi_V_dest_V_write),
.TVALID(OUTPUT_STREAM_TVALID),
.TREADY(OUTPUT_STREAM_TREADY),
.TDATA(OUTPUT_STREAM_TDATA),
.TKEEP(OUTPUT_STREAM_TKEEP),
.TSTRB(OUTPUT_STREAM_TSTRB),
.TUSER(OUTPUT_STREAM_TUSER),
.TLAST(OUTPUT_STREAM_TLAST),
.TID(OUTPUT_STREAM_TID),
.TDEST(OUTPUT_STREAM_TDEST));
pixelq_op_ap_rst_if #(
.RESET_ACTIVE_LOW(RESET_ACTIVE_LOW))
ap_rst_if_U(
.dout(sig_pixelq_op_ap_rst),
.din(aresetn));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Oct 31 12:11:23 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [8:0]probe19;
input [7:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [0:0]probe24;
input [7:0]probe25;
input [3:0]probe26;
endmodule
|
// MBT 7/24/2014
//
// bsg_sync_sync
//
// This is just two synchronization flops.
//
// We use the rp placement flop from synopsys.
// Fixme: move this into asic-specific components.
//
`ifndef rp_group
`define rp_group(x)
`define rp_place(x)
`define rp_endgroup(x)
`define rp_fill(x)
`define rp_array_dir(up)
`endif
`define bsg_sync_sync_unit(width_p) \
\
module bsg_sync_sync_``width_p``_unit \
( \
input oclk_i \
, input [width_p-1:0] iclk_data_i \
, output [width_p-1:0] oclk_data_o // after sync flops \
); \
\
`rp_group (bss_bank) \
`rp_place (hier bss_1 0 0) \
`rp_endgroup (bss_bank) \
\
genvar i; \
\
logic [width_p-1:0] bsg_SYNC_2_r; \
\
assign oclk_data_o = bsg_SYNC_2_r; \
\
for (i = 0; i < width_p; i = i + 1) \
begin : bss_unit \
`rp_group(bss_1) \
`rp_fill(0 0 UX) \
`rp_array_dir(up) \
`rp_endgroup(bss_1) \
SC7P5T_SYNC2SDFFQX2_SSC14SL hard_sync_int \
(.D (iclk_data_i[i]) \
,.CLK (oclk_i) \
,.SI (1'b0) \
,.SE (1'b0) \
,.Q (bsg_SYNC_2_r[i]) \
); \
end \
\
endmodule
`BSG_ABSTRACT_MODULE(bsg_sync_sync)
`bsg_sync_sync_unit(1)
`bsg_sync_sync_unit(2)
`bsg_sync_sync_unit(3)
`bsg_sync_sync_unit(4)
`bsg_sync_sync_unit(5)
`bsg_sync_sync_unit(6)
`bsg_sync_sync_unit(7)
`bsg_sync_sync_unit(8)
// warning: if you make this != 8, you need to modify other
// parts of this code.
`define bss_max_block 8
`define bss_if_clause(num) if ((width_p % `bss_max_block) == num) begin: z\
bsg_sync_sync_``num``_unit bss \
(.oclk_i \
,.iclk_data_i(iclk_data_i[width_p-1-:num]) \
,.oclk_data_o(oclk_data_o[width_p-1-:num]) \
); end
module bsg_sync_sync #(parameter `BSG_INV_PARAM(width_p ))
(
input oclk_i
, input [width_p-1:0] iclk_data_i
, output [width_p-1:0] oclk_data_o // after sync flops
);
genvar i;
// synopsys translate_off
/*
initial
begin
$display("%m: instantiating bss of size %d",width_p);
end
*/
// synopsys translate_on
for (i = 0; i < (width_p/`bss_max_block); i = i + 1)
begin : maxb
bsg_sync_sync_8_unit bss8
(.oclk_i
,.iclk_data_i(iclk_data_i[i*`bss_max_block+:`bss_max_block])
,.oclk_data_o(oclk_data_o[i*`bss_max_block+:`bss_max_block])
);
end
`bss_if_clause(1) else
`bss_if_clause(2) else
`bss_if_clause(3) else
`bss_if_clause(4) else
`bss_if_clause(5) else
`bss_if_clause(6) else
`bss_if_clause(7)
endmodule
`BSG_ABSTRACT_MODULE(bsg_sync_sync)
|
//*******************************************************************************************************************************************************/
// Module Name: stack
// Module Type: Last in First Out (LIFO) Stack Register
// Author: Shreyas Vinod
// Purpose: Stack for Neptune I v3.0
// Description: A synchronous Last in Firt Out (LIFO) Stack Register specifically designed for Neptune I.
//*******************************************************************************************************************************************************/
module stack(clk, rst, pop, push, wr, mem_fault, rd);
// Parameter Definitions
parameter width = 'd16; // Stack Data Width
parameter depth = 'd256; // Stack Depth
parameter add_width = 'd8; // Stack Addressing Width
// Inputs
input wire clk /* System Clock */, rst /* System Reset, Resets stack location. */; // Management Interfaces
input wire pop /* Stack Pop Enable */, push /* Stack Push Enable */; // Control Interfaces
input wire [width-1:0] wr /* Write Port */;
// Outputs
output reg mem_fault /* Memory Fault */;
output reg [width-1:0] rd /* Read Port */;
// Internal
reg [add_width-1:0] stk_loc /* Stack Location Register */;
reg [width-1:0] rd_out /* Storage Register for Read */;
reg [width-1:0] mem_arr [0:depth-1] /* Two-Dimensional Memory Array (Width-Depth Matrix) */;
// Stack Location Controller
always@(posedge clk) begin
if(rst) begin
mem_fault <= 1'b0; // Resets the mem_fault flag if rst is true.
stk_loc [add_width-1] <= {width{1'b0}};
end else if(push && !pop) stk_loc <= stk_loc + 1'b1; // Pushes the stack forward.
else if(pop && !push) stk_loc <= stk_loc - 1'b1; // Pulls the stack backward.
else if ((push && pop) && (stk_loc == 8'b0) || (push && (stk_loc = 8'b11111111))) mem_fault <= 1'b1; // Memory Fault instates itself on push-pop collision.
end
// Memory Read Block
always@(posedge clk) begin
rd [width-1:0] <= mem_arr[stk_loc] [width-1:0]; // Reads the contents of memory at every positive clock edge.
end
// Memory Write Block
always@(posedge clk) begin
if(push) mem_arr[stk_loc] [width-1:0] <= wr [width-1:0]; // Writes the value at wr to memory if push is true.
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_PP_SYMBOL_V
`define SKY130_FD_SC_LS__TAPMET1_PP_SYMBOL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapmet1 (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_PP_SYMBOL_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* UDP ethernet frame transmitter (UDP frame in, IP frame out)
*/
module udp_ip_tx
(
input wire clk,
input wire rst,
/*
* UDP frame input
*/
input wire s_udp_hdr_valid,
output wire s_udp_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [15:0] s_udp_source_port,
input wire [15:0] s_udp_dest_port,
input wire [15:0] s_udp_length,
input wire [15:0] s_udp_checksum,
input wire [7:0] s_udp_payload_axis_tdata,
input wire s_udp_payload_axis_tvalid,
output wire s_udp_payload_axis_tready,
input wire s_udp_payload_axis_tlast,
input wire s_udp_payload_axis_tuser,
/*
* IP frame output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [7:0] m_ip_payload_axis_tdata,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_payload_early_termination
);
/*
UDP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
source port 2 octets
desination port 2 octets
length 2 octets
checksum 2 octets
payload length octets
This module receives a UDP frame with header fields in parallel along with the
payload in an AXI stream, combines the header with the payload, passes through
the IP headers, and transmits the complete IP payload on an AXI interface.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_PAYLOAD = 3'd2,
STATE_WRITE_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_udp_hdr;
reg store_last_word;
reg [2:0] hdr_ptr_reg = 3'd0, hdr_ptr_next;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [7:0] last_word_data_reg = 8'd0;
reg [15:0] udp_source_port_reg = 16'd0;
reg [15:0] udp_dest_port_reg = 16'd0;
reg [15:0] udp_length_reg = 16'd0;
reg [15:0] udp_checksum_reg = 16'd0;
reg s_udp_hdr_ready_reg = 1'b0, s_udp_hdr_ready_next;
reg s_udp_payload_axis_tready_reg = 1'b0, s_udp_payload_axis_tready_next;
reg m_ip_hdr_valid_reg = 1'b0, m_ip_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_length_reg = 16'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [7:0] m_ip_protocol_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg busy_reg = 1'b0;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
// internal datapath
reg [7:0] m_ip_payload_axis_tdata_int;
reg m_ip_payload_axis_tvalid_int;
reg m_ip_payload_axis_tready_int_reg = 1'b0;
reg m_ip_payload_axis_tlast_int;
reg m_ip_payload_axis_tuser_int;
wire m_ip_payload_axis_tready_int_early;
assign s_udp_hdr_ready = s_udp_hdr_ready_reg;
assign s_udp_payload_axis_tready = s_udp_payload_axis_tready_reg;
assign m_ip_hdr_valid = m_ip_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign busy = busy_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
always @* begin
state_next = STATE_IDLE;
s_udp_hdr_ready_next = 1'b0;
s_udp_payload_axis_tready_next = 1'b0;
store_udp_hdr = 1'b0;
store_last_word = 1'b0;
hdr_ptr_next = hdr_ptr_reg;
word_count_next = word_count_reg;
m_ip_hdr_valid_next = m_ip_hdr_valid_reg && !m_ip_hdr_ready;
error_payload_early_termination_next = 1'b0;
m_ip_payload_axis_tdata_int = 8'd0;
m_ip_payload_axis_tvalid_int = 1'b0;
m_ip_payload_axis_tlast_int = 1'b0;
m_ip_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
hdr_ptr_next = 3'd0;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
if (s_udp_hdr_ready && s_udp_hdr_valid) begin
store_udp_hdr = 1'b1;
s_udp_hdr_ready_next = 1'b0;
m_ip_hdr_valid_next = 1'b1;
if (m_ip_payload_axis_tready_int_reg) begin
m_ip_payload_axis_tvalid_int = 1'b1;
m_ip_payload_axis_tdata_int = s_udp_source_port[15: 8];
hdr_ptr_next = 3'd1;
end
state_next = STATE_WRITE_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_HEADER: begin
// write header state
word_count_next = udp_length_reg - 16'd8;
if (m_ip_payload_axis_tready_int_reg) begin
// word transfer out
hdr_ptr_next = hdr_ptr_reg + 3'd1;
m_ip_payload_axis_tvalid_int = 1'b1;
state_next = STATE_WRITE_HEADER;
case (hdr_ptr_reg)
3'h0: m_ip_payload_axis_tdata_int = udp_source_port_reg[15: 8];
3'h1: m_ip_payload_axis_tdata_int = udp_source_port_reg[ 7: 0];
3'h2: m_ip_payload_axis_tdata_int = udp_dest_port_reg[15: 8];
3'h3: m_ip_payload_axis_tdata_int = udp_dest_port_reg[ 7: 0];
3'h4: m_ip_payload_axis_tdata_int = udp_length_reg[15: 8];
3'h5: m_ip_payload_axis_tdata_int = udp_length_reg[ 7: 0];
3'h6: m_ip_payload_axis_tdata_int = udp_checksum_reg[15: 8];
3'h7: begin
m_ip_payload_axis_tdata_int = udp_checksum_reg[ 7: 0];
s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early;
state_next = STATE_WRITE_PAYLOAD;
end
endcase
end else begin
state_next = STATE_WRITE_HEADER;
end
end
STATE_WRITE_PAYLOAD: begin
// write payload
s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early;
m_ip_payload_axis_tdata_int = s_udp_payload_axis_tdata;
m_ip_payload_axis_tlast_int = s_udp_payload_axis_tlast;
m_ip_payload_axis_tuser_int = s_udp_payload_axis_tuser;
if (s_udp_payload_axis_tready && s_udp_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd1;
m_ip_payload_axis_tvalid_int = 1'b1;
if (s_udp_payload_axis_tlast) begin
if (word_count_reg != 16'd1) begin
// end of frame, but length does not match
m_ip_payload_axis_tuser_int = 1'b1;
error_payload_early_termination_next = 1'b1;
end
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
if (word_count_reg == 16'd1) begin
store_last_word = 1'b1;
m_ip_payload_axis_tvalid_int = 1'b0;
state_next = STATE_WRITE_PAYLOAD_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
STATE_WRITE_PAYLOAD_LAST: begin
// read and discard until end of frame
s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early;
m_ip_payload_axis_tdata_int = last_word_data_reg;
m_ip_payload_axis_tlast_int = s_udp_payload_axis_tlast;
m_ip_payload_axis_tuser_int = s_udp_payload_axis_tuser;
if (s_udp_payload_axis_tready && s_udp_payload_axis_tvalid) begin
if (s_udp_payload_axis_tlast) begin
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
m_ip_payload_axis_tvalid_int = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
s_udp_payload_axis_tready_next = 1'b1;
if (s_udp_payload_axis_tvalid) begin
if (s_udp_payload_axis_tlast) begin
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_udp_hdr_ready_reg <= 1'b0;
s_udp_payload_axis_tready_reg <= 1'b0;
m_ip_hdr_valid_reg <= 1'b0;
busy_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_udp_hdr_ready_reg <= s_udp_hdr_ready_next;
s_udp_payload_axis_tready_reg <= s_udp_payload_axis_tready_next;
m_ip_hdr_valid_reg <= m_ip_hdr_valid_next;
busy_reg <= state_next != STATE_IDLE;
error_payload_early_termination_reg <= error_payload_early_termination_next;
end
hdr_ptr_reg <= hdr_ptr_next;
word_count_reg <= word_count_next;
// datapath
if (store_udp_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
m_ip_version_reg <= s_ip_version;
m_ip_ihl_reg <= s_ip_ihl;
m_ip_dscp_reg <= s_ip_dscp;
m_ip_ecn_reg <= s_ip_ecn;
m_ip_length_reg <= s_udp_length + 20;
m_ip_identification_reg <= s_ip_identification;
m_ip_flags_reg <= s_ip_flags;
m_ip_fragment_offset_reg <= s_ip_fragment_offset;
m_ip_ttl_reg <= s_ip_ttl;
m_ip_protocol_reg <= s_ip_protocol;
m_ip_header_checksum_reg <= s_ip_header_checksum;
m_ip_source_ip_reg <= s_ip_source_ip;
m_ip_dest_ip_reg <= s_ip_dest_ip;
udp_source_port_reg <= s_udp_source_port;
udp_dest_port_reg <= s_udp_dest_port;
udp_length_reg <= s_udp_length;
udp_checksum_reg <= s_udp_checksum;
end
if (store_last_word) begin
last_word_data_reg <= m_ip_payload_axis_tdata_int;
end
end
// output datapath logic
reg [7:0] m_ip_payload_axis_tdata_reg = 8'd0;
reg m_ip_payload_axis_tvalid_reg = 1'b0, m_ip_payload_axis_tvalid_next;
reg m_ip_payload_axis_tlast_reg = 1'b0;
reg m_ip_payload_axis_tuser_reg = 1'b0;
reg [7:0] temp_m_ip_payload_axis_tdata_reg = 8'd0;
reg temp_m_ip_payload_axis_tvalid_reg = 1'b0, temp_m_ip_payload_axis_tvalid_next;
reg temp_m_ip_payload_axis_tlast_reg = 1'b0;
reg temp_m_ip_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_ip_payload_int_to_output;
reg store_ip_payload_int_to_temp;
reg store_ip_payload_axis_temp_to_output;
assign m_ip_payload_axis_tdata = m_ip_payload_axis_tdata_reg;
assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
store_ip_payload_int_to_output = 1'b0;
store_ip_payload_int_to_temp = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b0;
if (m_ip_payload_axis_tready_int_reg) begin
// input is ready
if (m_ip_payload_axis_tready || !m_ip_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_temp = 1'b1;
end
end else if (m_ip_payload_axis_tready) begin
// input is not ready, but output is ready
m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_ip_payload_axis_tvalid_reg <= 1'b0;
m_ip_payload_axis_tready_int_reg <= 1'b0;
temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
end
// datapath
if (store_ip_payload_int_to_output) begin
m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end else if (store_ip_payload_axis_temp_to_output) begin
m_ip_payload_axis_tdata_reg <= temp_m_ip_payload_axis_tdata_reg;
m_ip_payload_axis_tlast_reg <= temp_m_ip_payload_axis_tlast_reg;
m_ip_payload_axis_tuser_reg <= temp_m_ip_payload_axis_tuser_reg;
end
if (store_ip_payload_int_to_temp) begin
temp_m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end
end
endmodule
`resetall
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: seven_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module seven_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/seven_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/seven_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_301x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_301x128 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input [300:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [300:0] q;
output rdempty;
output wrempty;
output wrfull;
output [6:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "301"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "301"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "301"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 301 0 INPUT NODEFVAL data[300..0]
// Retrieval info: USED_PORT: q 0 0 301 0 OUTPUT NODEFVAL q[300..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
// Retrieval info: CONNECT: @data 0 0 301 0 data 0 0 301 0
// Retrieval info: CONNECT: q 0 0 301 0 @q 0 0 301 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_301x128_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/* VGA Adapter
* ----------------
*
* This is an implementation of a VGA Adapter. The adapter uses VGA mode signalling to initiate
* a 640x480 resolution mode on a computer monitor, with a refresh rate of approximately 60Hz.
* It is designed for easy use in an early digital logic design course to facilitate student
* projects on the Altera DE2 Educational board.
*
* This implementation of the VGA adapter can display images of varying colour depth at a resolution of
* 320x240 or 160x120 superpixels. The concept of superpixels is introduced to reduce the amount of on-chip
* memory used by the adapter. The following table shows the number of bits of on-chip memory used by
* the adapter in various resolutions and colour depths.
*
* -------------------------------------------------------------------------------------------------------------------------------
* Resolution | Mono | 8 colours | 64 colours | 512 colours | 4096 colours | 32768 colours | 262144 colours | 2097152 colours |
* -------------------------------------------------------------------------------------------------------------------------------
* 160x120 | 19200 | 57600 | 115200 | 172800 | 230400 | 288000 | 345600 | 403200 |
* 320x240 | 78600 | 230400 | ############## Does not fit ############################################################## |
* -------------------------------------------------------------------------------------------------------------------------------
*
* By default the adapter works at the resolution of 320x240 with 8 colours. To set the adapter in any of
* the other modes, the adapter must be instantiated with specific parameters. These parameters are:
* - RESOLUTION - a string that should be either "320x240" or "160x120".
* - MONOCHROME - a string that should be "TRUE" if you only want black and white colours, and "FALSE"
* otherwise.
* - BITS_PER_COLOUR_CHANNEL - an integer specifying how many bits are available to describe each colour
* (R,G,B). A default value of 1 indicates that 1 bit will be used for red
* channel, 1 for green channel and 1 for blue channel. This allows 8 colours
* to be used.
*
* In addition to the above parameters, a BACKGROUND_IMAGE parameter can be specified. The parameter
* refers to a memory initilization file (MIF) which contains the initial contents of video memory.
* By specifying the initial contents of the memory we can force the adapter to initially display an
* image of our choice. Please note that the image described by the BACKGROUND_IMAGE file will only
* be valid right after your program the DE2 board. If your circuit draws a single pixel on the screen,
* the video memory will be altered and screen contents will be changed. In order to restore the background
* image your circuti will have to redraw the background image pixel by pixel, or you will have to
* reprogram the DE2 board, thus allowing the video memory to be rewritten.
*
* To use the module connect the vga_adapter to your circuit. Your circuit should produce a value for
* inputs X, Y and plot. When plot is high, at the next positive edge of the input clock the vga_adapter
* will change the contents of the video memory for the pixel at location (X,Y). At the next redraw
* cycle the VGA controller will update the contants of the screen by reading the video memory and copying
* it over to the screen. Since the monitor screen has no memory, the VGA controller has to copy the
* contents of the video memory to the screen once every 60th of a second to keep the image stable. Thus,
* the video memory should not be used for other purposes as it may interfere with the operation of the
* VGA Adapter.
*
* As a final note, ensure that the following conditions are met when using this module:
* 1. You are implementing the the VGA Adapter on the Altera DE2 board. Using another board may change
* the amount of memory you can use, the clock generation mechanism, as well as pin assignments required
* to properly drive the VGA digital-to-analog converter.
* 2. Outputs VGA_* should exist in your top level design. They should be assigned pin locations on the
* Altera DE2 board as specified by the DE2_pin_assignments.csv file.
* 3. The input clock must have a frequency of 50 MHz with a 50% duty cycle. On the Altera DE2 board
* PIN_N2 is the source for the 50MHz clock.
*
* During compilation with Quartus II you may receive the following warnings:
* - Warning: Variable or input pin "clocken1" is defined but never used
* - Warning: Pin "VGA_SYNC" stuck at VCC
* - Warning: Found xx output pins without output pin load capacitance assignment
* These warnings can be ignored. The first warning is generated, because the software generated
* memory module contains an input called "clocken1" and it does not drive logic. The second warning
* indicates that the VGA_SYNC signal is always high. This is intentional. The final warning is
* generated for the purposes of power analysis. It will persist unless the output pins are assigned
* output capacitance. Leaving the capacitance values at 0 pf did not affect the operation of the module.
*
* If you see any other warnings relating to the vga_adapter, be sure to examine them carefully. They may
* cause your circuit to malfunction.
*
* NOTES/REVISIONS:
* July 10, 2007 - Modified the original version of the VGA Adapter written by Sam Vafaee in 2006. The module
* now supports 2 different resolutions as well as uses half the memory compared to prior
* implementation. Also, all settings for the module can be specified from the point
* of instantiation, rather than by modifying the source code. (Tomasz S. Czajkowski)
*/
module vga_adapter(
resetn,
clock,
colour,
x, y, plot,
/* Signals for the DAC to drive the monitor. */
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS,
VGA_BLANK,
VGA_SYNC,
VGA_CLK);
parameter BITS_PER_COLOUR_CHANNEL = 1;
/* The number of bits per colour channel used to represent the colour of each pixel. A value
* of 1 means that Red, Green and Blue colour channels will use 1 bit each to represent the intensity
* of the respective colour channel. For BITS_PER_COLOUR_CHANNEL=1, the adapter can display 8 colours.
* In general, the adapter is able to use 2^(3*BITS_PER_COLOUR_CHANNEL ) colours. The number of colours is
* limited by the screen resolution and the amount of on-chip memory available on the target device.
*/
parameter MONOCHROME = "FALSE";
/* Set this parameter to "TRUE" if you only wish to use black and white colours. Doing so will reduce
* the amount of memory you will use by a factor of 3. */
parameter RESOLUTION = "320x240";
/* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on
* the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution).
* It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary
* to reduce the resolution for the Video Memory to fit within the on-chip memory limits.
*/
parameter BACKGROUND_IMAGE = "background.mif";
/* The initial screen displayed when the circuit is first programmed onto the DE2 board can be
* defined useing an MIF file. The file contains the initial colour for each pixel on the screen
* and is placed in the Video Memory (VideoMemory module) upon programming. Note that resetting the
* VGA Adapter will not cause the Video Memory to revert to the specified image. */
parameter USING_DE1 = "FALSE";
/* If set to "TRUE" it adjust the offset of the drawing mechanism to account for the differences
* between the DE2 and DE1 VGA digital to analogue converters. Set to "TRUE" if and only if
* you are running your circuit on a DE1 board. */
/*****************************************************************************/
/* Declare inputs and outputs. */
/*****************************************************************************/
input resetn;
input clock;
/* The colour input can be either 1 bit or 3*BITS_PER_COLOUR_CHANNEL bits wide, depending on
* the setting of the MONOCHROME parameter.
*/
input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] colour;
/* Specify the number of bits required to represent an (X,Y) coordinate on the screen for
* a given resolution.
*/
input [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
input [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
/* When plot is high then at the next positive edge of the clock the pixel at (x,y) will change to
* a new colour, defined by the value of the colour input.
*/
input plot;
/* These outputs drive the VGA display. The VGA_CLK is also used to clock the FSM responsible for
* controlling the data transferred to the DAC driving the monitor. */
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
output VGA_HS;
output VGA_VS;
output VGA_BLANK;
output VGA_SYNC;
output VGA_CLK;
/*****************************************************************************/
/* Declare local signals here. */
/*****************************************************************************/
wire valid_160x120;
wire valid_320x240;
/* Set to 1 if the specified coordinates are in a valid range for a given resolution.*/
wire writeEn;
/* This is a local signal that allows the Video Memory contents to be changed.
* It depends on the screen resolution, the values of X and Y inputs, as well as
* the state of the plot signal.
*/
wire [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] to_ctrl_colour;
/* Pixel colour read by the VGA controller */
wire [((RESOLUTION == "320x240") ? (16) : (14)):0] user_to_video_memory_addr;
/* This bus specifies the address in memory the user must write
* data to in order for the pixel intended to appear at location (X,Y) to be displayed
* at the correct location on the screen.
*/
wire [((RESOLUTION == "320x240") ? (16) : (14)):0] controller_to_video_memory_addr;
/* This bus specifies the address in memory the vga controller must read data from
* in order to determine the colour of a pixel located at coordinate (X,Y) of the screen.
*/
wire clock_25;
/* 25MHz clock generated by dividing the input clock frequency by 2. */
wire vcc, gnd;
/*****************************************************************************/
/* Instances of modules for the VGA adapter. */
/*****************************************************************************/
assign vcc = 1'b1;
assign gnd = 1'b0;
vga_address_translator user_input_translator(
.x(x), .y(y), .mem_address(user_to_video_memory_addr) );
defparam user_input_translator.RESOLUTION = RESOLUTION;
/* Convert user coordinates into a memory address. */
assign valid_160x120 = (({1'b0, x} >= 0) & ({1'b0, x} < 160) & ({1'b0, y} >= 0) & ({1'b0, y} < 120)) & (RESOLUTION == "160x120");
assign valid_320x240 = (({1'b0, x} >= 0) & ({1'b0, x} < 320) & ({1'b0, y} >= 0) & ({1'b0, y} < 240)) & (RESOLUTION == "320x240");
assign writeEn = (plot) & (valid_160x120 | valid_320x240);
/* Allow the user to plot a pixel if and only if the (X,Y) coordinates supplied are in a valid range. */
/* Create video memory. */
altsyncram VideoMemory (
.wren_a (writeEn),
.wren_b (gnd),
.clock0 (clock), // write clock
.clock1 (clock_25), // read clock
.clocken0 (vcc), // write enable clock
.clocken1 (vcc), // read enable clock
.address_a (user_to_video_memory_addr),
.address_b (controller_to_video_memory_addr),
.data_a (colour), // data in
.q_b (to_ctrl_colour) // data out
);
defparam
VideoMemory.WIDTH_A = ((MONOCHROME == "FALSE") ? (BITS_PER_COLOUR_CHANNEL*3) : 1),
VideoMemory.WIDTH_B = ((MONOCHROME == "FALSE") ? (BITS_PER_COLOUR_CHANNEL*3) : 1),
VideoMemory.INTENDED_DEVICE_FAMILY = "Cyclone II",
VideoMemory.OPERATION_MODE = "DUAL_PORT",
VideoMemory.WIDTHAD_A = ((RESOLUTION == "320x240") ? (17) : (15)),
VideoMemory.NUMWORDS_A = ((RESOLUTION == "320x240") ? (76800) : (19200)),
VideoMemory.WIDTHAD_B = ((RESOLUTION == "320x240") ? (17) : (15)),
VideoMemory.NUMWORDS_B = ((RESOLUTION == "320x240") ? (76800) : (19200)),
VideoMemory.OUTDATA_REG_B = "CLOCK1",
VideoMemory.ADDRESS_REG_B = "CLOCK1",
VideoMemory.CLOCK_ENABLE_INPUT_A = "BYPASS",
VideoMemory.CLOCK_ENABLE_INPUT_B = "BYPASS",
VideoMemory.CLOCK_ENABLE_OUTPUT_B = "BYPASS",
VideoMemory.POWER_UP_UNINITIALIZED = "FALSE",
VideoMemory.INIT_FILE = BACKGROUND_IMAGE;
vga_pll mypll(clock, clock_25);
/* This module generates a clock with half the frequency of the input clock.
* For the VGA adapter to operate correctly the clock signal 'clock' must be
* a 50MHz clock. The derived clock, which will then operate at 25MHz, is
* required to set the monitor into the 640x480@60Hz display mode (also known as
* the VGA mode).
*/
vga_controller controller(
.vga_clock(clock_25),
.resetn(resetn),
.pixel_colour(to_ctrl_colour),
.memory_address(controller_to_video_memory_addr),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK),
.VGA_SYNC(VGA_SYNC),
.VGA_CLK(VGA_CLK)
);
defparam controller.BITS_PER_COLOUR_CHANNEL = BITS_PER_COLOUR_CHANNEL ;
defparam controller.MONOCHROME = MONOCHROME;
defparam controller.RESOLUTION = RESOLUTION;
defparam controller.USING_DE1 = USING_DE1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_1_V
`define SKY130_FD_SC_HS__AND3B_1_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3b_1 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3b_1 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_1_V
|
//======================================================================
//
// tb_aes_decipher_block.v
// -----------------------
// Testbench for the AES decipher block module.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module tb_aes_decipher_block();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter DUMP_WAIT = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
parameter AES_128_BIT_KEY = 0;
parameter AES_256_BIT_KEY = 1;
parameter AES_DECIPHER = 1'b0;
parameter AES_ENCIPHER = 1'b1;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_next;
reg tb_keylen;
wire tb_ready;
wire [3 : 0] tb_round;
wire [127 : 0] tb_round_key;
reg [127 : 0] tb_block;
wire [127 : 0] tb_new_block;
reg [127 : 0] key_mem [0 : 14];
//----------------------------------------------------------------
// Assignments.
//----------------------------------------------------------------
assign tb_round_key = key_mem[tb_round];
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
aes_decipher_block dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.next(tb_next),
.keylen(tb_keylen),
.round(tb_round),
.round_key(tb_round_key),
.block(tb_block),
.new_block(tb_new_block),
.ready(tb_ready)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
$display("Interfaces");
$display("ready = 0x%01x, next = 0x%01x, keylen = 0x%01x",
dut.ready, dut.next, dut.keylen);
$display("block = 0x%032x", dut.block);
$display("new_block = 0x%032x", dut.new_block);
$display("");
$display("Control states");
$display("round = 0x%01x", dut.round);
$display("dec_ctrl = 0x%01x, update_type = 0x%01x, sword_ctr = 0x%01x, round_ctr = 0x%01x",
dut.dec_ctrl_reg, dut.update_type, dut.sword_ctr_reg, dut.round_ctr_reg);
$display("");
$display("Internal data values");
$display("round_key = 0x%016x", dut.round_key);
$display("sboxw = 0x%08x, new_sboxw = 0x%08x", dut.tmp_sboxw, dut.new_sboxw);
$display("block_w0_reg = 0x%08x, block_w1_reg = 0x%08x, block_w2_reg = 0x%08x, block_w3_reg = 0x%08x",
dut.block_w0_reg, dut.block_w1_reg, dut.block_w2_reg, dut.block_w3_reg);
$display("");
$display("old_block = 0x%08x", dut.round_logic.old_block);
$display("inv_shiftrows_block = 0x%08x", dut.round_logic.inv_shiftrows_block);
$display("inv_mixcolumns_block = 0x%08x", dut.round_logic.inv_mixcolumns_block);
$display("addkey_block = 0x%08x", dut.round_logic.addkey_block);
$display("block_w0_new = 0x%08x, block_w1_new = 0x%08x, block_w2_new = 0x%08x, block_w3_new = 0x%08x",
dut.block_new[127 : 096], dut.block_new[095 : 064],
dut.block_new[063 : 032], dut.block_new[031 : 000]);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_next = 0;
tb_keylen = 0;
tb_block = {4{32'h00000000}};
end
endtask // init_sim
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// wait_ready()
//
// Wait for the ready flag in the dut to be set.
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
task wait_ready;
begin
while (!tb_ready)
begin
#(CLK_PERIOD);
if (DUMP_WAIT)
begin
dump_dut_state();
end
end
end
endtask // wait_ready
//----------------------------------------------------------------
// test_ecb_de()
//
// Perform ECB mode encryption test.
//----------------------------------------------------------------
task test_ecb_dec(
input key_length,
input [127 : 0] block,
input [127 : 0] expected);
begin
$display("*** TC %0d ECB mode test started.", tc_ctr);
// Init the cipher with the given key and length.
tb_keylen = key_length;
// Perform decipher operation on the block.
tb_block = block;
tb_next = 1;
#(2 * CLK_PERIOD);
tb_next = 0;
#(2 * CLK_PERIOD);
wait_ready();
if (tb_new_block == expected)
begin
$display("*** TC %0d successful.", tc_ctr);
$display("");
end
else
begin
$display("*** ERROR: TC %0d NOT successful.", tc_ctr);
$display("Expected: 0x%032x", expected);
$display("Got: 0x%032x", tb_new_block);
$display("");
error_ctr = error_ctr + 1;
end
tc_ctr = tc_ctr + 1;
end
endtask // ecb_mode_single_block_test
//----------------------------------------------------------------
// tb_aes_decipher_block
// The main test functionality.
//
// Test cases taken from NIST SP 800-38A:
// http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf
//----------------------------------------------------------------
initial
begin : tb_aes_decipher_block
reg [127 : 0] nist_plaintext0;
reg [127 : 0] nist_plaintext1;
reg [127 : 0] nist_plaintext2;
reg [127 : 0] nist_plaintext3;
reg [127 : 0] nist_ecb_128_dec_ciphertext0;
reg [127 : 0] nist_ecb_128_dec_ciphertext1;
reg [127 : 0] nist_ecb_128_dec_ciphertext2;
reg [127 : 0] nist_ecb_128_dec_ciphertext3;
reg [127 : 0] nist_ecb_256_dec_ciphertext0;
reg [127 : 0] nist_ecb_256_dec_ciphertext1;
reg [127 : 0] nist_ecb_256_dec_ciphertext2;
reg [127 : 0] nist_ecb_256_dec_ciphertext3;
nist_plaintext0 = 128'h6bc1bee22e409f96e93d7e117393172a;
nist_plaintext1 = 128'hae2d8a571e03ac9c9eb76fac45af8e51;
nist_plaintext2 = 128'h30c81c46a35ce411e5fbc1191a0a52ef;
nist_plaintext3 = 128'hf69f2445df4f9b17ad2b417be66c3710;
nist_ecb_128_dec_ciphertext0 = 128'h3ad77bb40d7a3660a89ecaf32466ef97;
nist_ecb_128_dec_ciphertext1 = 128'hf5d3d58503b9699de785895a96fdbaaf;
nist_ecb_128_dec_ciphertext2 = 128'h43b1cd7f598ece23881b00e3ed030688;
nist_ecb_128_dec_ciphertext3 = 128'h7b0c785e27e8ad3f8223207104725dd4;
nist_ecb_256_dec_ciphertext0 = 255'hf3eed1bdb5d2a03c064b5a7e3db181f8;
nist_ecb_256_dec_ciphertext1 = 255'h591ccb10d410ed26dc5ba74a31362870;
nist_ecb_256_dec_ciphertext2 = 255'hb6ed21b99ca6f4f9f153e7b1beafed1d;
nist_ecb_256_dec_ciphertext3 = 255'h23304b7a39f9f3ff067d8d8f9e24ecc7;
$display(" -= Testbench for aes decipher block started =-");
$display(" ============================================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
// NIST 128 bit ECB tests.
key_mem[00] = 128'h2b7e151628aed2a6abf7158809cf4f3c;
key_mem[01] = 128'ha0fafe1788542cb123a339392a6c7605;
key_mem[02] = 128'hf2c295f27a96b9435935807a7359f67f;
key_mem[03] = 128'h3d80477d4716fe3e1e237e446d7a883b;
key_mem[04] = 128'hef44a541a8525b7fb671253bdb0bad00;
key_mem[05] = 128'hd4d1c6f87c839d87caf2b8bc11f915bc;
key_mem[06] = 128'h6d88a37a110b3efddbf98641ca0093fd;
key_mem[07] = 128'h4e54f70e5f5fc9f384a64fb24ea6dc4f;
key_mem[08] = 128'head27321b58dbad2312bf5607f8d292f;
key_mem[09] = 128'hac7766f319fadc2128d12941575c006e;
key_mem[10] = 128'hd014f9a8c9ee2589e13f0cc8b6630ca6;
key_mem[11] = 128'h00000000000000000000000000000000;
key_mem[12] = 128'h00000000000000000000000000000000;
key_mem[13] = 128'h00000000000000000000000000000000;
key_mem[14] = 128'h00000000000000000000000000000000;
test_ecb_dec(AES_128_BIT_KEY, nist_ecb_128_dec_ciphertext0, nist_plaintext0);
test_ecb_dec(AES_128_BIT_KEY, nist_ecb_128_dec_ciphertext1, nist_plaintext1);
test_ecb_dec(AES_128_BIT_KEY, nist_ecb_128_dec_ciphertext2, nist_plaintext2);
test_ecb_dec(AES_128_BIT_KEY, nist_ecb_128_dec_ciphertext3, nist_plaintext3);
// NIST 256 bit ECB tests.
key_mem[00] = 128'h603deb1015ca71be2b73aef0857d7781;
key_mem[01] = 128'h1f352c073b6108d72d9810a30914dff4;
key_mem[02] = 128'h9ba354118e6925afa51a8b5f2067fcde;
key_mem[03] = 128'ha8b09c1a93d194cdbe49846eb75d5b9a;
key_mem[04] = 128'hd59aecb85bf3c917fee94248de8ebe96;
key_mem[05] = 128'hb5a9328a2678a647983122292f6c79b3;
key_mem[06] = 128'h812c81addadf48ba24360af2fab8b464;
key_mem[07] = 128'h98c5bfc9bebd198e268c3ba709e04214;
key_mem[08] = 128'h68007bacb2df331696e939e46c518d80;
key_mem[09] = 128'hc814e20476a9fb8a5025c02d59c58239;
key_mem[10] = 128'hde1369676ccc5a71fa2563959674ee15;
key_mem[11] = 128'h5886ca5d2e2f31d77e0af1fa27cf73c3;
key_mem[12] = 128'h749c47ab18501ddae2757e4f7401905a;
key_mem[13] = 128'hcafaaae3e4d59b349adf6acebd10190d;
key_mem[14] = 128'hfe4890d1e6188d0b046df344706c631e;
test_ecb_dec(AES_256_BIT_KEY, nist_ecb_256_dec_ciphertext0, nist_plaintext0);
test_ecb_dec(AES_256_BIT_KEY, nist_ecb_256_dec_ciphertext1, nist_plaintext1);
test_ecb_dec(AES_256_BIT_KEY, nist_ecb_256_dec_ciphertext2, nist_plaintext2);
test_ecb_dec(AES_256_BIT_KEY, nist_ecb_256_dec_ciphertext3, nist_plaintext3);
display_test_result();
$display("");
$display("*** AES decipher block module simulation done. ***");
$finish;
end // aes_core_test
endmodule // tb_aes_decipher_block
//======================================================================
// EOF tb_aes_decipher_block.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBN_SYMBOL_V
`define SKY130_FD_SC_MS__DLXBN_SYMBOL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBN_SYMBOL_V
|
`timescale 1ns / 1ps
/*
-- Module Name: DES NiC Input Control Unit
-- Description: Unida de control para el bloque de entrada de la
interfaz de red. Este bloque se encarga de la captura de
nuevos paquetes provenientes de la red.
Ejerce control sobre registros de almacenamiento
individuales para cada flit de un paquete y lleva
a cabo las tares de control de flujo (creditos) con
respecto al router de la NoC.
-- Dependencies: -- system.vh
-- Parameters: -- BUFFER_DEPTH: Numero de flits que es capaz de
almacenar la cola de
almacenamiento de la NiC.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 18 de Junio 2015: Creacion
*/
`include "system.vh"
module des_nic_input_control_unit
(
input wire clk,
input wire reset,
// -- inputs ------------------------------------------------- >>>>>
input wire header_field_din,
input wire busy_engine_din,
input wire zero_credits_din,
// -- outputs ------------------------------------------------ >>>>>
output wire transfer2pe_strobe_dout,
output wire write_strobe_dout,
output wire [`DATA_FLITS:0] register_enable_dout
);
// -- Parametros locales ----------------------------------------- >>>>>
localparam IDLE = 2'b00;
localparam CAPTURE = 2'b01;
localparam WAIT = 2'b10;
localparam LOAD = 1'b1;
localparam SHIFT = 1'b0;
/*
-- Descripcion: Secuenciador para habilitacion de escritura en banco
de registro para flits. Los datos de trabajo para el
elemento de procesamiento se almacenan en registros
individuales, este contador habilita la escritura en
cada uno de ellos.
Este registro esta codificado en formato 'one hot', y
cada uno de sus bits habilita la captura de un flit en
un registro diferente.
Los elementos de memoria estan descritos en el modulo
des_nic_input_block.v
*/
// -- Elementos de memoria ----------------------------------- >>>>>
reg [`DATA_FLITS:0] register_enable_reg;
wire [`DATA_FLITS:0] register_enable_next;
always @(posedge clk)
if (reset)
register_enable_reg <= {{`DATA_FLITS{1'b0}}, 1'b1};
else
register_enable_reg <= register_enable_next;
// -- Logica del estado siguiente ---------------------------- >>>>>
assign register_enable_next = (state_next == CAPTURE) ? register_enable_reg << 1 :
(state_next == IDLE) ? {{`DATA_FLITS{1'b0}}, 1'b1} :
register_enable_reg;
// -- Logica de salidas -------------------------------------- >>>>>
assign register_enable_dout = register_enable_reg;
assign write_strobe_dout = (state_next == CAPTURE) ? 1'b1 : 1'b0;
/*
-- Descripcion: Maquina de estado finito para el control de recepcion de
paquetes para el PE del nodo.
La FSM espera el ingreso de un nuevo paquete a traves
del canal de entrada. Durante los siguientes 'n' ciclos
de reloj se registra cada flit perteneciente al paquete,
dando la primera posicion del medio de almacenamiento
al flit de cabecera.
Al finalizar la captura de flits de un paquete se
evalua la disponibilidad del elemento de procesamiento
(banderas:: busy_engine_din y zero_credits_din), en
caso de la presencia de cualquiera de las dos banderas
la FSM salta al estado WAIT para esperar disponibilidad
del elemento de procesamiento.
La señal capture_strobe indica la captura de un paquete
completo. esta señal se convierte en la señal de inicio
para el PE.
El control de flujo utiliza el mecanismo de creditos.
*/
// -- FSM -------------------------------------------------------- >>>>>
// -- Elementos de memoria ----------------------------------- >>>>>
reg [1:0] state_reg;
reg [1:0] state_next;
always @(posedge clk)
if (reset)
state_reg <= IDLE;
else
state_reg <= state_next;
// -- Logica del estado siguiente ---------------------------- >>>>>
always @(*)
begin
state_next <= state_reg;
case (state_reg)
IDLE:
if (header_field_din)
state_next <= CAPTURE;
CAPTURE:
if ((register_enable_reg == {`DATA_FLITS+1{1'b0}}) & (~busy_engine_din) & (~zero_credits_din))
state_next <= IDLE;
else if ((register_enable_reg == {`DATA_FLITS+1{1'b0}}) & (busy_engine_din | zero_credits_din))
state_next <= WAIT;
WAIT:
if (~busy_engine_din & ~zero_credits_din)
state_next <= IDLE;
endcase // state_reg
end
// -- Logica de salidas -------------------------------------- >>>>>
assign transfer2pe_strobe_dout = ((state_reg == CAPTURE | state_reg == WAIT) & (state_next == IDLE)) ? 1'b1 : 1'b0;
// -- Codigo no sintetizable ------------------------------------- >>>>>
reg [7*8:0] state_reg_dbg;
always @(*)
case (state_reg)
IDLE: state_reg_dbg = " IDLE ";
WAIT: state_reg_dbg = " WAIT ";
CAPTURE: state_reg_dbg = "CAPTURE";
default : state_reg_dbg = " ERROR ";
endcase
endmodule
/* Plantilla de instancia ---------------------------------------- >>>>>
des_nic_input_control_unit des_nic_input_control_unit
(
.clk (clk),
.reset (reset),
// -- inputs ------------------------------------------------- >>>>>
.header_field_din (header_field),
.busy_engine_din (busy_engine),
.zero_credits_din (zero_credits),
// -- outputs ------------------------------------------------ >>>>>
.transfer2pe_strobe_dout (transfer2pe_strobe),
.write_strobe_dout (write_strobe),
.register_enable_dout (register_enable)
);
*/ |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_4_V
`define SKY130_FD_SC_LS__CLKBUF_4_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkbuf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkbuf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 05/11/2017 12:23:41 PM
// Design Name:
// Module Name: EXECUTION_STAGE
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module EXECUTION_STAGE #(
parameter ADDRESS_WIDTH = 32 ,
parameter DATA_WIDTH = 32 ,
parameter REG_ADD_WIDTH = 5 ,
parameter ALU_INS_WIDTH = 5 ,
parameter D_CACHE_LW_WIDTH = 3 ,
parameter D_CACHE_SW_WIDTH = 2 ,
parameter HIGH = 1'b1 ,
parameter LOW = 1'b0
) (
input CLK ,
input STALL_EXECUTION_STAGE ,
input CLEAR_EXECUTION_STAGE ,
input [ADDRESS_WIDTH - 1 : 0] PC_IN ,
input [REG_ADD_WIDTH - 1 : 0] RD_ADDRESS_IN ,
input [DATA_WIDTH - 1 : 0] RS1_DATA ,
input [DATA_WIDTH - 1 : 0] RS2_DATA ,
input [DATA_WIDTH - 1 : 0] IMM_DATA ,
input [ALU_INS_WIDTH - 1 : 0] ALU_INSTRUCTION ,
input ALU_INPUT_1_SELECT ,
input ALU_INPUT_2_SELECT ,
input [D_CACHE_LW_WIDTH - 1 : 0] DATA_CACHE_LOAD_IN ,
input [D_CACHE_SW_WIDTH - 1 : 0] DATA_CACHE_STORE_IN ,
input WRITE_BACK_MUX_SELECT_IN ,
input RD_WRITE_ENABLE_IN ,
output [REG_ADD_WIDTH - 1 : 0] RD_ADDRESS_OUT ,
output [DATA_WIDTH - 1 : 0] ALU_OUT ,
output BRANCH_TAKEN ,
output [D_CACHE_LW_WIDTH - 1 : 0] DATA_CACHE_LOAD_OUT ,
output [D_CACHE_SW_WIDTH - 1 : 0] DATA_CACHE_STORE_OUT ,
output [DATA_WIDTH - 1 : 0] DATA_CACHE_STORE_DATA ,
output WRITE_BACK_MUX_SELECT_OUT ,
output RD_WRITE_ENABLE_OUT
);
reg [REG_ADD_WIDTH - 1 : 0] rd_address_out_reg ;
reg [DATA_WIDTH - 1 : 0] alu_out_reg ;
reg [D_CACHE_LW_WIDTH - 1 : 0] data_cache_load_out_reg ;
reg [D_CACHE_SW_WIDTH - 1 : 0] data_cache_store_out_reg ;
reg [DATA_WIDTH - 1 : 0] data_cache_store_data_reg ;
reg write_back_mux_select_out_reg ;
reg rd_write_enable_out_reg ;
wire [DATA_WIDTH - 1 : 0] alu_in1 ;
wire [DATA_WIDTH - 1 : 0] alu_in2 ;
wire [DATA_WIDTH - 1 : 0] alu_out ;
MULTIPLEXER_2_TO_1 alu_in1_mux(
.IN1(RS1_DATA),
.IN2(PC_IN),
.SELECT(ALU_INPUT_1_SELECT),
.OUT(alu_in1)
);
MULTIPLEXER_2_TO_1 alu_in2_mux(
.IN1(RS2_DATA),
.IN2(IMM_DATA),
.SELECT(ALU_INPUT_2_SELECT),
.OUT(alu_in2)
);
ALU alu(
.ALU_IN1(alu_in1),
.ALU_IN2(alu_in2),
.PC_IN(PC_IN),
.ALU_INSTRUCTION(ALU_INSTRUCTION),
.ALU_OUT(alu_out),
.BRANCH_TAKEN(BRANCH_TAKEN)
);
always@(posedge CLK)
begin
if((CLEAR_EXECUTION_STAGE == LOW) & (STALL_EXECUTION_STAGE == LOW))
begin
rd_address_out_reg <= RD_ADDRESS_IN ;
alu_out_reg <= alu_out ;
data_cache_load_out_reg <= DATA_CACHE_LOAD_IN ;
data_cache_store_out_reg <= DATA_CACHE_STORE_IN ;
data_cache_store_data_reg <= RS2_DATA ;
write_back_mux_select_out_reg <= WRITE_BACK_MUX_SELECT_IN ;
rd_write_enable_out_reg <= RD_WRITE_ENABLE_IN ;
end
else
begin
rd_address_out_reg <= 5'b0 ;
alu_out_reg <= 32'b0 ;
data_cache_load_out_reg <= 3'b0 ;
data_cache_store_out_reg <= 2'b0 ;
data_cache_store_data_reg <= 32'b0 ;
write_back_mux_select_out_reg <= 1'b0 ;
rd_write_enable_out_reg <= 1'b0 ;
end
end
assign RD_ADDRESS_OUT = rd_address_out_reg ;
assign ALU_OUT = alu_out_reg ;
assign DATA_CACHE_LOAD_OUT = data_cache_load_out_reg ;
assign DATA_CACHE_STORE_OUT = data_cache_store_out_reg ;
assign DATA_CACHE_STORE_DATA = data_cache_store_data_reg ;
assign WRITE_BACK_MUX_SELECT_OUT = write_back_mux_select_out_reg ;
assign RD_WRITE_ENABLE_OUT = rd_write_enable_out_reg ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__FILL_DIODE_FUNCTIONAL_PP_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fill_diode (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NAND3_FUNCTIONAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_FUNCTIONAL_V |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Sin_Cos.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Sin_Cos
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Sin_Cos
(
x,
sin,
cos
);
input signed [17:0] x; // sfix18_En14
output signed [17:0] sin; // sfix18_En16
output signed [17:0] cos; // sfix18_En16
parameter signed [17:0] t1_re_0 = 65536; // sfix18
parameter signed [17:0] t1_re_1 = 65531; // sfix18
parameter signed [17:0] t1_re_2 = 65516; // sfix18
parameter signed [17:0] t1_re_3 = 65492; // sfix18
parameter signed [17:0] t1_re_4 = 65457; // sfix18
parameter signed [17:0] t1_re_5 = 65413; // sfix18
parameter signed [17:0] t1_re_6 = 65358; // sfix18
parameter signed [17:0] t1_re_7 = 65294; // sfix18
parameter signed [17:0] t1_re_8 = 65220; // sfix18
parameter signed [17:0] t1_re_9 = 65137; // sfix18
parameter signed [17:0] t1_re_10 = 65043; // sfix18
parameter signed [17:0] t1_re_11 = 64940; // sfix18
parameter signed [17:0] t1_re_12 = 64827; // sfix18
parameter signed [17:0] t1_re_13 = 64704; // sfix18
parameter signed [17:0] t1_re_14 = 64571; // sfix18
parameter signed [17:0] t1_re_15 = 64429; // sfix18
parameter signed [17:0] t1_re_16 = 64277; // sfix18
parameter signed [17:0] t1_re_17 = 64115; // sfix18
parameter signed [17:0] t1_re_18 = 63944; // sfix18
parameter signed [17:0] t1_re_19 = 63763; // sfix18
parameter signed [17:0] t1_re_20 = 63572; // sfix18
parameter signed [17:0] t1_re_21 = 63372; // sfix18
parameter signed [17:0] t1_re_22 = 63162; // sfix18
parameter signed [17:0] t1_re_23 = 62943; // sfix18
parameter signed [17:0] t1_re_24 = 62714; // sfix18
parameter signed [17:0] t1_re_25 = 62476; // sfix18
parameter signed [17:0] t1_re_26 = 62228; // sfix18
parameter signed [17:0] t1_re_27 = 61971; // sfix18
parameter signed [17:0] t1_re_28 = 61705; // sfix18
parameter signed [17:0] t1_re_29 = 61429; // sfix18
parameter signed [17:0] t1_re_30 = 61145; // sfix18
parameter signed [17:0] t1_re_31 = 60851; // sfix18
parameter signed [17:0] t1_re_32 = 60547; // sfix18
parameter signed [17:0] t1_re_33 = 60235; // sfix18
parameter signed [17:0] t1_re_34 = 59914; // sfix18
parameter signed [17:0] t1_re_35 = 59583; // sfix18
parameter signed [17:0] t1_re_36 = 59244; // sfix18
parameter signed [17:0] t1_re_37 = 58896; // sfix18
parameter signed [17:0] t1_re_38 = 58538; // sfix18
parameter signed [17:0] t1_re_39 = 58172; // sfix18
parameter signed [17:0] t1_re_40 = 57798; // sfix18
parameter signed [17:0] t1_re_41 = 57414; // sfix18
parameter signed [17:0] t1_re_42 = 57022; // sfix18
parameter signed [17:0] t1_re_43 = 56621; // sfix18
parameter signed [17:0] t1_re_44 = 56212; // sfix18
parameter signed [17:0] t1_re_45 = 55794; // sfix18
parameter signed [17:0] t1_re_46 = 55368; // sfix18
parameter signed [17:0] t1_re_47 = 54934; // sfix18
parameter signed [17:0] t1_re_48 = 54491; // sfix18
parameter signed [17:0] t1_re_49 = 54040; // sfix18
parameter signed [17:0] t1_re_50 = 53581; // sfix18
parameter signed [17:0] t1_re_51 = 53114; // sfix18
parameter signed [17:0] t1_re_52 = 52639; // sfix18
parameter signed [17:0] t1_re_53 = 52156; // sfix18
parameter signed [17:0] t1_re_54 = 51665; // sfix18
parameter signed [17:0] t1_re_55 = 51166; // sfix18
parameter signed [17:0] t1_re_56 = 50660; // sfix18
parameter signed [17:0] t1_re_57 = 50146; // sfix18
parameter signed [17:0] t1_re_58 = 49624; // sfix18
parameter signed [17:0] t1_re_59 = 49095; // sfix18
parameter signed [17:0] t1_re_60 = 48559; // sfix18
parameter signed [17:0] t1_re_61 = 48015; // sfix18
parameter signed [17:0] t1_re_62 = 47464; // sfix18
parameter signed [17:0] t1_re_63 = 46906; // sfix18
parameter signed [17:0] t1_re_64 = 46341; // sfix18
parameter signed [17:0] t1_re_65 = 45769; // sfix18
parameter signed [17:0] t1_re_66 = 45190; // sfix18
parameter signed [17:0] t1_re_67 = 44604; // sfix18
parameter signed [17:0] t1_re_68 = 44011; // sfix18
parameter signed [17:0] t1_re_69 = 43412; // sfix18
parameter signed [17:0] t1_re_70 = 42806; // sfix18
parameter signed [17:0] t1_re_71 = 42194; // sfix18
parameter signed [17:0] t1_re_72 = 41576; // sfix18
parameter signed [17:0] t1_re_73 = 40951; // sfix18
parameter signed [17:0] t1_re_74 = 40320; // sfix18
parameter signed [17:0] t1_re_75 = 39683; // sfix18
parameter signed [17:0] t1_re_76 = 39040; // sfix18
parameter signed [17:0] t1_re_77 = 38391; // sfix18
parameter signed [17:0] t1_re_78 = 37736; // sfix18
parameter signed [17:0] t1_re_79 = 37076; // sfix18
parameter signed [17:0] t1_re_80 = 36410; // sfix18
parameter signed [17:0] t1_re_81 = 35738; // sfix18
parameter signed [17:0] t1_re_82 = 35062; // sfix18
parameter signed [17:0] t1_re_83 = 34380; // sfix18
parameter signed [17:0] t1_re_84 = 33692; // sfix18
parameter signed [17:0] t1_re_85 = 33000; // sfix18
parameter signed [17:0] t1_re_86 = 32303; // sfix18
parameter signed [17:0] t1_re_87 = 31600; // sfix18
parameter signed [17:0] t1_re_88 = 30893; // sfix18
parameter signed [17:0] t1_re_89 = 30182; // sfix18
parameter signed [17:0] t1_re_90 = 29466; // sfix18
parameter signed [17:0] t1_re_91 = 28745; // sfix18
parameter signed [17:0] t1_re_92 = 28020; // sfix18
parameter signed [17:0] t1_re_93 = 27291; // sfix18
parameter signed [17:0] t1_re_94 = 26558; // sfix18
parameter signed [17:0] t1_re_95 = 25821; // sfix18
parameter signed [17:0] t1_re_96 = 25080; // sfix18
parameter signed [17:0] t1_re_97 = 24335; // sfix18
parameter signed [17:0] t1_re_98 = 23586; // sfix18
parameter signed [17:0] t1_re_99 = 22834; // sfix18
parameter signed [17:0] t1_re_100 = 22078; // sfix18
parameter signed [17:0] t1_re_101 = 21320; // sfix18
parameter signed [17:0] t1_re_102 = 20557; // sfix18
parameter signed [17:0] t1_re_103 = 19792; // sfix18
parameter signed [17:0] t1_re_104 = 19024; // sfix18
parameter signed [17:0] t1_re_105 = 18253; // sfix18
parameter signed [17:0] t1_re_106 = 17479; // sfix18
parameter signed [17:0] t1_re_107 = 16703; // sfix18
parameter signed [17:0] t1_re_108 = 15924; // sfix18
parameter signed [17:0] t1_re_109 = 15143; // sfix18
parameter signed [17:0] t1_re_110 = 14359; // sfix18
parameter signed [17:0] t1_re_111 = 13573; // sfix18
parameter signed [17:0] t1_re_112 = 12785; // sfix18
parameter signed [17:0] t1_re_113 = 11996; // sfix18
parameter signed [17:0] t1_re_114 = 11204; // sfix18
parameter signed [17:0] t1_re_115 = 10411; // sfix18
parameter signed [17:0] t1_re_116 = 9616; // sfix18
parameter signed [17:0] t1_re_117 = 8820; // sfix18
parameter signed [17:0] t1_re_118 = 8022; // sfix18
parameter signed [17:0] t1_re_119 = 7224; // sfix18
parameter signed [17:0] t1_re_120 = 6424; // sfix18
parameter signed [17:0] t1_re_121 = 5623; // sfix18
parameter signed [17:0] t1_re_122 = 4821; // sfix18
parameter signed [17:0] t1_re_123 = 4019; // sfix18
parameter signed [17:0] t1_re_124 = 3216; // sfix18
parameter signed [17:0] t1_re_125 = 2412; // sfix18
parameter signed [17:0] t1_re_126 = 1608; // sfix18
parameter signed [17:0] t1_re_127 = 804; // sfix18
parameter signed [17:0] t1_re_128 = 0; // sfix18
parameter signed [17:0] t1_re_129 = -804; // sfix18
parameter signed [17:0] t1_re_130 = -1608; // sfix18
parameter signed [17:0] t1_re_131 = -2412; // sfix18
parameter signed [17:0] t1_re_132 = -3216; // sfix18
parameter signed [17:0] t1_re_133 = -4019; // sfix18
parameter signed [17:0] t1_re_134 = -4821; // sfix18
parameter signed [17:0] t1_re_135 = -5623; // sfix18
parameter signed [17:0] t1_re_136 = -6424; // sfix18
parameter signed [17:0] t1_re_137 = -7224; // sfix18
parameter signed [17:0] t1_re_138 = -8022; // sfix18
parameter signed [17:0] t1_re_139 = -8820; // sfix18
parameter signed [17:0] t1_re_140 = -9616; // sfix18
parameter signed [17:0] t1_re_141 = -10411; // sfix18
parameter signed [17:0] t1_re_142 = -11204; // sfix18
parameter signed [17:0] t1_re_143 = -11996; // sfix18
parameter signed [17:0] t1_re_144 = -12785; // sfix18
parameter signed [17:0] t1_re_145 = -13573; // sfix18
parameter signed [17:0] t1_re_146 = -14359; // sfix18
parameter signed [17:0] t1_re_147 = -15143; // sfix18
parameter signed [17:0] t1_re_148 = -15924; // sfix18
parameter signed [17:0] t1_re_149 = -16703; // sfix18
parameter signed [17:0] t1_re_150 = -17479; // sfix18
parameter signed [17:0] t1_re_151 = -18253; // sfix18
parameter signed [17:0] t1_re_152 = -19024; // sfix18
parameter signed [17:0] t1_re_153 = -19792; // sfix18
parameter signed [17:0] t1_re_154 = -20557; // sfix18
parameter signed [17:0] t1_re_155 = -21320; // sfix18
parameter signed [17:0] t1_re_156 = -22078; // sfix18
parameter signed [17:0] t1_re_157 = -22834; // sfix18
parameter signed [17:0] t1_re_158 = -23586; // sfix18
parameter signed [17:0] t1_re_159 = -24335; // sfix18
parameter signed [17:0] t1_re_160 = -25080; // sfix18
parameter signed [17:0] t1_re_161 = -25821; // sfix18
parameter signed [17:0] t1_re_162 = -26558; // sfix18
parameter signed [17:0] t1_re_163 = -27291; // sfix18
parameter signed [17:0] t1_re_164 = -28020; // sfix18
parameter signed [17:0] t1_re_165 = -28745; // sfix18
parameter signed [17:0] t1_re_166 = -29466; // sfix18
parameter signed [17:0] t1_re_167 = -30182; // sfix18
parameter signed [17:0] t1_re_168 = -30893; // sfix18
parameter signed [17:0] t1_re_169 = -31600; // sfix18
parameter signed [17:0] t1_re_170 = -32303; // sfix18
parameter signed [17:0] t1_re_171 = -33000; // sfix18
parameter signed [17:0] t1_re_172 = -33692; // sfix18
parameter signed [17:0] t1_re_173 = -34380; // sfix18
parameter signed [17:0] t1_re_174 = -35062; // sfix18
parameter signed [17:0] t1_re_175 = -35738; // sfix18
parameter signed [17:0] t1_re_176 = -36410; // sfix18
parameter signed [17:0] t1_re_177 = -37076; // sfix18
parameter signed [17:0] t1_re_178 = -37736; // sfix18
parameter signed [17:0] t1_re_179 = -38391; // sfix18
parameter signed [17:0] t1_re_180 = -39040; // sfix18
parameter signed [17:0] t1_re_181 = -39683; // sfix18
parameter signed [17:0] t1_re_182 = -40320; // sfix18
parameter signed [17:0] t1_re_183 = -40951; // sfix18
parameter signed [17:0] t1_re_184 = -41576; // sfix18
parameter signed [17:0] t1_re_185 = -42194; // sfix18
parameter signed [17:0] t1_re_186 = -42806; // sfix18
parameter signed [17:0] t1_re_187 = -43412; // sfix18
parameter signed [17:0] t1_re_188 = -44011; // sfix18
parameter signed [17:0] t1_re_189 = -44604; // sfix18
parameter signed [17:0] t1_re_190 = -45190; // sfix18
parameter signed [17:0] t1_re_191 = -45769; // sfix18
parameter signed [17:0] t1_re_192 = -46341; // sfix18
parameter signed [17:0] t1_re_193 = -46906; // sfix18
parameter signed [17:0] t1_re_194 = -47464; // sfix18
parameter signed [17:0] t1_re_195 = -48015; // sfix18
parameter signed [17:0] t1_re_196 = -48559; // sfix18
parameter signed [17:0] t1_re_197 = -49095; // sfix18
parameter signed [17:0] t1_re_198 = -49624; // sfix18
parameter signed [17:0] t1_re_199 = -50146; // sfix18
parameter signed [17:0] t1_re_200 = -50660; // sfix18
parameter signed [17:0] t1_re_201 = -51166; // sfix18
parameter signed [17:0] t1_re_202 = -51665; // sfix18
parameter signed [17:0] t1_re_203 = -52156; // sfix18
parameter signed [17:0] t1_re_204 = -52639; // sfix18
parameter signed [17:0] t1_re_205 = -53114; // sfix18
parameter signed [17:0] t1_re_206 = -53581; // sfix18
parameter signed [17:0] t1_re_207 = -54040; // sfix18
parameter signed [17:0] t1_re_208 = -54491; // sfix18
parameter signed [17:0] t1_re_209 = -54934; // sfix18
parameter signed [17:0] t1_re_210 = -55368; // sfix18
parameter signed [17:0] t1_re_211 = -55794; // sfix18
parameter signed [17:0] t1_re_212 = -56212; // sfix18
parameter signed [17:0] t1_re_213 = -56621; // sfix18
parameter signed [17:0] t1_re_214 = -57022; // sfix18
parameter signed [17:0] t1_re_215 = -57414; // sfix18
parameter signed [17:0] t1_re_216 = -57798; // sfix18
parameter signed [17:0] t1_re_217 = -58172; // sfix18
parameter signed [17:0] t1_re_218 = -58538; // sfix18
parameter signed [17:0] t1_re_219 = -58896; // sfix18
parameter signed [17:0] t1_re_220 = -59244; // sfix18
parameter signed [17:0] t1_re_221 = -59583; // sfix18
parameter signed [17:0] t1_re_222 = -59914; // sfix18
parameter signed [17:0] t1_re_223 = -60235; // sfix18
parameter signed [17:0] t1_re_224 = -60547; // sfix18
parameter signed [17:0] t1_re_225 = -60851; // sfix18
parameter signed [17:0] t1_re_226 = -61145; // sfix18
parameter signed [17:0] t1_re_227 = -61429; // sfix18
parameter signed [17:0] t1_re_228 = -61705; // sfix18
parameter signed [17:0] t1_re_229 = -61971; // sfix18
parameter signed [17:0] t1_re_230 = -62228; // sfix18
parameter signed [17:0] t1_re_231 = -62476; // sfix18
parameter signed [17:0] t1_re_232 = -62714; // sfix18
parameter signed [17:0] t1_re_233 = -62943; // sfix18
parameter signed [17:0] t1_re_234 = -63162; // sfix18
parameter signed [17:0] t1_re_235 = -63372; // sfix18
parameter signed [17:0] t1_re_236 = -63572; // sfix18
parameter signed [17:0] t1_re_237 = -63763; // sfix18
parameter signed [17:0] t1_re_238 = -63944; // sfix18
parameter signed [17:0] t1_re_239 = -64115; // sfix18
parameter signed [17:0] t1_re_240 = -64277; // sfix18
parameter signed [17:0] t1_re_241 = -64429; // sfix18
parameter signed [17:0] t1_re_242 = -64571; // sfix18
parameter signed [17:0] t1_re_243 = -64704; // sfix18
parameter signed [17:0] t1_re_244 = -64827; // sfix18
parameter signed [17:0] t1_re_245 = -64940; // sfix18
parameter signed [17:0] t1_re_246 = -65043; // sfix18
parameter signed [17:0] t1_re_247 = -65137; // sfix18
parameter signed [17:0] t1_re_248 = -65220; // sfix18
parameter signed [17:0] t1_re_249 = -65294; // sfix18
parameter signed [17:0] t1_re_250 = -65358; // sfix18
parameter signed [17:0] t1_re_251 = -65413; // sfix18
parameter signed [17:0] t1_re_252 = -65457; // sfix18
parameter signed [17:0] t1_re_253 = -65492; // sfix18
parameter signed [17:0] t1_re_254 = -65516; // sfix18
parameter signed [17:0] t1_re_255 = -65531; // sfix18
parameter signed [17:0] t1_re_256 = -65536; // sfix18
parameter signed [17:0] t1_re_257 = -65531; // sfix18
parameter signed [17:0] t1_re_258 = -65516; // sfix18
parameter signed [17:0] t1_re_259 = -65492; // sfix18
parameter signed [17:0] t1_re_260 = -65457; // sfix18
parameter signed [17:0] t1_re_261 = -65413; // sfix18
parameter signed [17:0] t1_re_262 = -65358; // sfix18
parameter signed [17:0] t1_re_263 = -65294; // sfix18
parameter signed [17:0] t1_re_264 = -65220; // sfix18
parameter signed [17:0] t1_re_265 = -65137; // sfix18
parameter signed [17:0] t1_re_266 = -65043; // sfix18
parameter signed [17:0] t1_re_267 = -64940; // sfix18
parameter signed [17:0] t1_re_268 = -64827; // sfix18
parameter signed [17:0] t1_re_269 = -64704; // sfix18
parameter signed [17:0] t1_re_270 = -64571; // sfix18
parameter signed [17:0] t1_re_271 = -64429; // sfix18
parameter signed [17:0] t1_re_272 = -64277; // sfix18
parameter signed [17:0] t1_re_273 = -64115; // sfix18
parameter signed [17:0] t1_re_274 = -63944; // sfix18
parameter signed [17:0] t1_re_275 = -63763; // sfix18
parameter signed [17:0] t1_re_276 = -63572; // sfix18
parameter signed [17:0] t1_re_277 = -63372; // sfix18
parameter signed [17:0] t1_re_278 = -63162; // sfix18
parameter signed [17:0] t1_re_279 = -62943; // sfix18
parameter signed [17:0] t1_re_280 = -62714; // sfix18
parameter signed [17:0] t1_re_281 = -62476; // sfix18
parameter signed [17:0] t1_re_282 = -62228; // sfix18
parameter signed [17:0] t1_re_283 = -61971; // sfix18
parameter signed [17:0] t1_re_284 = -61705; // sfix18
parameter signed [17:0] t1_re_285 = -61429; // sfix18
parameter signed [17:0] t1_re_286 = -61145; // sfix18
parameter signed [17:0] t1_re_287 = -60851; // sfix18
parameter signed [17:0] t1_re_288 = -60547; // sfix18
parameter signed [17:0] t1_re_289 = -60235; // sfix18
parameter signed [17:0] t1_re_290 = -59914; // sfix18
parameter signed [17:0] t1_re_291 = -59583; // sfix18
parameter signed [17:0] t1_re_292 = -59244; // sfix18
parameter signed [17:0] t1_re_293 = -58896; // sfix18
parameter signed [17:0] t1_re_294 = -58538; // sfix18
parameter signed [17:0] t1_re_295 = -58172; // sfix18
parameter signed [17:0] t1_re_296 = -57798; // sfix18
parameter signed [17:0] t1_re_297 = -57414; // sfix18
parameter signed [17:0] t1_re_298 = -57022; // sfix18
parameter signed [17:0] t1_re_299 = -56621; // sfix18
parameter signed [17:0] t1_re_300 = -56212; // sfix18
parameter signed [17:0] t1_re_301 = -55794; // sfix18
parameter signed [17:0] t1_re_302 = -55368; // sfix18
parameter signed [17:0] t1_re_303 = -54934; // sfix18
parameter signed [17:0] t1_re_304 = -54491; // sfix18
parameter signed [17:0] t1_re_305 = -54040; // sfix18
parameter signed [17:0] t1_re_306 = -53581; // sfix18
parameter signed [17:0] t1_re_307 = -53114; // sfix18
parameter signed [17:0] t1_re_308 = -52639; // sfix18
parameter signed [17:0] t1_re_309 = -52156; // sfix18
parameter signed [17:0] t1_re_310 = -51665; // sfix18
parameter signed [17:0] t1_re_311 = -51166; // sfix18
parameter signed [17:0] t1_re_312 = -50660; // sfix18
parameter signed [17:0] t1_re_313 = -50146; // sfix18
parameter signed [17:0] t1_re_314 = -49624; // sfix18
parameter signed [17:0] t1_re_315 = -49095; // sfix18
parameter signed [17:0] t1_re_316 = -48559; // sfix18
parameter signed [17:0] t1_re_317 = -48015; // sfix18
parameter signed [17:0] t1_re_318 = -47464; // sfix18
parameter signed [17:0] t1_re_319 = -46906; // sfix18
parameter signed [17:0] t1_re_320 = -46341; // sfix18
parameter signed [17:0] t1_re_321 = -45769; // sfix18
parameter signed [17:0] t1_re_322 = -45190; // sfix18
parameter signed [17:0] t1_re_323 = -44604; // sfix18
parameter signed [17:0] t1_re_324 = -44011; // sfix18
parameter signed [17:0] t1_re_325 = -43412; // sfix18
parameter signed [17:0] t1_re_326 = -42806; // sfix18
parameter signed [17:0] t1_re_327 = -42194; // sfix18
parameter signed [17:0] t1_re_328 = -41576; // sfix18
parameter signed [17:0] t1_re_329 = -40951; // sfix18
parameter signed [17:0] t1_re_330 = -40320; // sfix18
parameter signed [17:0] t1_re_331 = -39683; // sfix18
parameter signed [17:0] t1_re_332 = -39040; // sfix18
parameter signed [17:0] t1_re_333 = -38391; // sfix18
parameter signed [17:0] t1_re_334 = -37736; // sfix18
parameter signed [17:0] t1_re_335 = -37076; // sfix18
parameter signed [17:0] t1_re_336 = -36410; // sfix18
parameter signed [17:0] t1_re_337 = -35738; // sfix18
parameter signed [17:0] t1_re_338 = -35062; // sfix18
parameter signed [17:0] t1_re_339 = -34380; // sfix18
parameter signed [17:0] t1_re_340 = -33692; // sfix18
parameter signed [17:0] t1_re_341 = -33000; // sfix18
parameter signed [17:0] t1_re_342 = -32303; // sfix18
parameter signed [17:0] t1_re_343 = -31600; // sfix18
parameter signed [17:0] t1_re_344 = -30893; // sfix18
parameter signed [17:0] t1_re_345 = -30182; // sfix18
parameter signed [17:0] t1_re_346 = -29466; // sfix18
parameter signed [17:0] t1_re_347 = -28745; // sfix18
parameter signed [17:0] t1_re_348 = -28020; // sfix18
parameter signed [17:0] t1_re_349 = -27291; // sfix18
parameter signed [17:0] t1_re_350 = -26558; // sfix18
parameter signed [17:0] t1_re_351 = -25821; // sfix18
parameter signed [17:0] t1_re_352 = -25080; // sfix18
parameter signed [17:0] t1_re_353 = -24335; // sfix18
parameter signed [17:0] t1_re_354 = -23586; // sfix18
parameter signed [17:0] t1_re_355 = -22834; // sfix18
parameter signed [17:0] t1_re_356 = -22078; // sfix18
parameter signed [17:0] t1_re_357 = -21320; // sfix18
parameter signed [17:0] t1_re_358 = -20557; // sfix18
parameter signed [17:0] t1_re_359 = -19792; // sfix18
parameter signed [17:0] t1_re_360 = -19024; // sfix18
parameter signed [17:0] t1_re_361 = -18253; // sfix18
parameter signed [17:0] t1_re_362 = -17479; // sfix18
parameter signed [17:0] t1_re_363 = -16703; // sfix18
parameter signed [17:0] t1_re_364 = -15924; // sfix18
parameter signed [17:0] t1_re_365 = -15143; // sfix18
parameter signed [17:0] t1_re_366 = -14359; // sfix18
parameter signed [17:0] t1_re_367 = -13573; // sfix18
parameter signed [17:0] t1_re_368 = -12785; // sfix18
parameter signed [17:0] t1_re_369 = -11996; // sfix18
parameter signed [17:0] t1_re_370 = -11204; // sfix18
parameter signed [17:0] t1_re_371 = -10411; // sfix18
parameter signed [17:0] t1_re_372 = -9616; // sfix18
parameter signed [17:0] t1_re_373 = -8820; // sfix18
parameter signed [17:0] t1_re_374 = -8022; // sfix18
parameter signed [17:0] t1_re_375 = -7224; // sfix18
parameter signed [17:0] t1_re_376 = -6424; // sfix18
parameter signed [17:0] t1_re_377 = -5623; // sfix18
parameter signed [17:0] t1_re_378 = -4821; // sfix18
parameter signed [17:0] t1_re_379 = -4019; // sfix18
parameter signed [17:0] t1_re_380 = -3216; // sfix18
parameter signed [17:0] t1_re_381 = -2412; // sfix18
parameter signed [17:0] t1_re_382 = -1608; // sfix18
parameter signed [17:0] t1_re_383 = -804; // sfix18
parameter signed [17:0] t1_re_384 = 0; // sfix18
parameter signed [17:0] t1_re_385 = 804; // sfix18
parameter signed [17:0] t1_re_386 = 1608; // sfix18
parameter signed [17:0] t1_re_387 = 2412; // sfix18
parameter signed [17:0] t1_re_388 = 3216; // sfix18
parameter signed [17:0] t1_re_389 = 4019; // sfix18
parameter signed [17:0] t1_re_390 = 4821; // sfix18
parameter signed [17:0] t1_re_391 = 5623; // sfix18
parameter signed [17:0] t1_re_392 = 6424; // sfix18
parameter signed [17:0] t1_re_393 = 7224; // sfix18
parameter signed [17:0] t1_re_394 = 8022; // sfix18
parameter signed [17:0] t1_re_395 = 8820; // sfix18
parameter signed [17:0] t1_re_396 = 9616; // sfix18
parameter signed [17:0] t1_re_397 = 10411; // sfix18
parameter signed [17:0] t1_re_398 = 11204; // sfix18
parameter signed [17:0] t1_re_399 = 11996; // sfix18
parameter signed [17:0] t1_re_400 = 12785; // sfix18
parameter signed [17:0] t1_re_401 = 13573; // sfix18
parameter signed [17:0] t1_re_402 = 14359; // sfix18
parameter signed [17:0] t1_re_403 = 15143; // sfix18
parameter signed [17:0] t1_re_404 = 15924; // sfix18
parameter signed [17:0] t1_re_405 = 16703; // sfix18
parameter signed [17:0] t1_re_406 = 17479; // sfix18
parameter signed [17:0] t1_re_407 = 18253; // sfix18
parameter signed [17:0] t1_re_408 = 19024; // sfix18
parameter signed [17:0] t1_re_409 = 19792; // sfix18
parameter signed [17:0] t1_re_410 = 20557; // sfix18
parameter signed [17:0] t1_re_411 = 21320; // sfix18
parameter signed [17:0] t1_re_412 = 22078; // sfix18
parameter signed [17:0] t1_re_413 = 22834; // sfix18
parameter signed [17:0] t1_re_414 = 23586; // sfix18
parameter signed [17:0] t1_re_415 = 24335; // sfix18
parameter signed [17:0] t1_re_416 = 25080; // sfix18
parameter signed [17:0] t1_re_417 = 25821; // sfix18
parameter signed [17:0] t1_re_418 = 26558; // sfix18
parameter signed [17:0] t1_re_419 = 27291; // sfix18
parameter signed [17:0] t1_re_420 = 28020; // sfix18
parameter signed [17:0] t1_re_421 = 28745; // sfix18
parameter signed [17:0] t1_re_422 = 29466; // sfix18
parameter signed [17:0] t1_re_423 = 30182; // sfix18
parameter signed [17:0] t1_re_424 = 30893; // sfix18
parameter signed [17:0] t1_re_425 = 31600; // sfix18
parameter signed [17:0] t1_re_426 = 32303; // sfix18
parameter signed [17:0] t1_re_427 = 33000; // sfix18
parameter signed [17:0] t1_re_428 = 33692; // sfix18
parameter signed [17:0] t1_re_429 = 34380; // sfix18
parameter signed [17:0] t1_re_430 = 35062; // sfix18
parameter signed [17:0] t1_re_431 = 35738; // sfix18
parameter signed [17:0] t1_re_432 = 36410; // sfix18
parameter signed [17:0] t1_re_433 = 37076; // sfix18
parameter signed [17:0] t1_re_434 = 37736; // sfix18
parameter signed [17:0] t1_re_435 = 38391; // sfix18
parameter signed [17:0] t1_re_436 = 39040; // sfix18
parameter signed [17:0] t1_re_437 = 39683; // sfix18
parameter signed [17:0] t1_re_438 = 40320; // sfix18
parameter signed [17:0] t1_re_439 = 40951; // sfix18
parameter signed [17:0] t1_re_440 = 41576; // sfix18
parameter signed [17:0] t1_re_441 = 42194; // sfix18
parameter signed [17:0] t1_re_442 = 42806; // sfix18
parameter signed [17:0] t1_re_443 = 43412; // sfix18
parameter signed [17:0] t1_re_444 = 44011; // sfix18
parameter signed [17:0] t1_re_445 = 44604; // sfix18
parameter signed [17:0] t1_re_446 = 45190; // sfix18
parameter signed [17:0] t1_re_447 = 45769; // sfix18
parameter signed [17:0] t1_re_448 = 46341; // sfix18
parameter signed [17:0] t1_re_449 = 46906; // sfix18
parameter signed [17:0] t1_re_450 = 47464; // sfix18
parameter signed [17:0] t1_re_451 = 48015; // sfix18
parameter signed [17:0] t1_re_452 = 48559; // sfix18
parameter signed [17:0] t1_re_453 = 49095; // sfix18
parameter signed [17:0] t1_re_454 = 49624; // sfix18
parameter signed [17:0] t1_re_455 = 50146; // sfix18
parameter signed [17:0] t1_re_456 = 50660; // sfix18
parameter signed [17:0] t1_re_457 = 51166; // sfix18
parameter signed [17:0] t1_re_458 = 51665; // sfix18
parameter signed [17:0] t1_re_459 = 52156; // sfix18
parameter signed [17:0] t1_re_460 = 52639; // sfix18
parameter signed [17:0] t1_re_461 = 53114; // sfix18
parameter signed [17:0] t1_re_462 = 53581; // sfix18
parameter signed [17:0] t1_re_463 = 54040; // sfix18
parameter signed [17:0] t1_re_464 = 54491; // sfix18
parameter signed [17:0] t1_re_465 = 54934; // sfix18
parameter signed [17:0] t1_re_466 = 55368; // sfix18
parameter signed [17:0] t1_re_467 = 55794; // sfix18
parameter signed [17:0] t1_re_468 = 56212; // sfix18
parameter signed [17:0] t1_re_469 = 56621; // sfix18
parameter signed [17:0] t1_re_470 = 57022; // sfix18
parameter signed [17:0] t1_re_471 = 57414; // sfix18
parameter signed [17:0] t1_re_472 = 57798; // sfix18
parameter signed [17:0] t1_re_473 = 58172; // sfix18
parameter signed [17:0] t1_re_474 = 58538; // sfix18
parameter signed [17:0] t1_re_475 = 58896; // sfix18
parameter signed [17:0] t1_re_476 = 59244; // sfix18
parameter signed [17:0] t1_re_477 = 59583; // sfix18
parameter signed [17:0] t1_re_478 = 59914; // sfix18
parameter signed [17:0] t1_re_479 = 60235; // sfix18
parameter signed [17:0] t1_re_480 = 60547; // sfix18
parameter signed [17:0] t1_re_481 = 60851; // sfix18
parameter signed [17:0] t1_re_482 = 61145; // sfix18
parameter signed [17:0] t1_re_483 = 61429; // sfix18
parameter signed [17:0] t1_re_484 = 61705; // sfix18
parameter signed [17:0] t1_re_485 = 61971; // sfix18
parameter signed [17:0] t1_re_486 = 62228; // sfix18
parameter signed [17:0] t1_re_487 = 62476; // sfix18
parameter signed [17:0] t1_re_488 = 62714; // sfix18
parameter signed [17:0] t1_re_489 = 62943; // sfix18
parameter signed [17:0] t1_re_490 = 63162; // sfix18
parameter signed [17:0] t1_re_491 = 63372; // sfix18
parameter signed [17:0] t1_re_492 = 63572; // sfix18
parameter signed [17:0] t1_re_493 = 63763; // sfix18
parameter signed [17:0] t1_re_494 = 63944; // sfix18
parameter signed [17:0] t1_re_495 = 64115; // sfix18
parameter signed [17:0] t1_re_496 = 64277; // sfix18
parameter signed [17:0] t1_re_497 = 64429; // sfix18
parameter signed [17:0] t1_re_498 = 64571; // sfix18
parameter signed [17:0] t1_re_499 = 64704; // sfix18
parameter signed [17:0] t1_re_500 = 64827; // sfix18
parameter signed [17:0] t1_re_501 = 64940; // sfix18
parameter signed [17:0] t1_re_502 = 65043; // sfix18
parameter signed [17:0] t1_re_503 = 65137; // sfix18
parameter signed [17:0] t1_re_504 = 65220; // sfix18
parameter signed [17:0] t1_re_505 = 65294; // sfix18
parameter signed [17:0] t1_re_506 = 65358; // sfix18
parameter signed [17:0] t1_re_507 = 65413; // sfix18
parameter signed [17:0] t1_re_508 = 65457; // sfix18
parameter signed [17:0] t1_re_509 = 65492; // sfix18
parameter signed [17:0] t1_re_510 = 65516; // sfix18
parameter signed [17:0] t1_re_511 = 65531; // sfix18
parameter signed [17:0] t1_im_0 = 0; // sfix18
parameter signed [17:0] t1_im_1 = 804; // sfix18
parameter signed [17:0] t1_im_2 = 1608; // sfix18
parameter signed [17:0] t1_im_3 = 2412; // sfix18
parameter signed [17:0] t1_im_4 = 3216; // sfix18
parameter signed [17:0] t1_im_5 = 4019; // sfix18
parameter signed [17:0] t1_im_6 = 4821; // sfix18
parameter signed [17:0] t1_im_7 = 5623; // sfix18
parameter signed [17:0] t1_im_8 = 6424; // sfix18
parameter signed [17:0] t1_im_9 = 7224; // sfix18
parameter signed [17:0] t1_im_10 = 8022; // sfix18
parameter signed [17:0] t1_im_11 = 8820; // sfix18
parameter signed [17:0] t1_im_12 = 9616; // sfix18
parameter signed [17:0] t1_im_13 = 10411; // sfix18
parameter signed [17:0] t1_im_14 = 11204; // sfix18
parameter signed [17:0] t1_im_15 = 11996; // sfix18
parameter signed [17:0] t1_im_16 = 12785; // sfix18
parameter signed [17:0] t1_im_17 = 13573; // sfix18
parameter signed [17:0] t1_im_18 = 14359; // sfix18
parameter signed [17:0] t1_im_19 = 15143; // sfix18
parameter signed [17:0] t1_im_20 = 15924; // sfix18
parameter signed [17:0] t1_im_21 = 16703; // sfix18
parameter signed [17:0] t1_im_22 = 17479; // sfix18
parameter signed [17:0] t1_im_23 = 18253; // sfix18
parameter signed [17:0] t1_im_24 = 19024; // sfix18
parameter signed [17:0] t1_im_25 = 19792; // sfix18
parameter signed [17:0] t1_im_26 = 20557; // sfix18
parameter signed [17:0] t1_im_27 = 21320; // sfix18
parameter signed [17:0] t1_im_28 = 22078; // sfix18
parameter signed [17:0] t1_im_29 = 22834; // sfix18
parameter signed [17:0] t1_im_30 = 23586; // sfix18
parameter signed [17:0] t1_im_31 = 24335; // sfix18
parameter signed [17:0] t1_im_32 = 25080; // sfix18
parameter signed [17:0] t1_im_33 = 25821; // sfix18
parameter signed [17:0] t1_im_34 = 26558; // sfix18
parameter signed [17:0] t1_im_35 = 27291; // sfix18
parameter signed [17:0] t1_im_36 = 28020; // sfix18
parameter signed [17:0] t1_im_37 = 28745; // sfix18
parameter signed [17:0] t1_im_38 = 29466; // sfix18
parameter signed [17:0] t1_im_39 = 30182; // sfix18
parameter signed [17:0] t1_im_40 = 30893; // sfix18
parameter signed [17:0] t1_im_41 = 31600; // sfix18
parameter signed [17:0] t1_im_42 = 32303; // sfix18
parameter signed [17:0] t1_im_43 = 33000; // sfix18
parameter signed [17:0] t1_im_44 = 33692; // sfix18
parameter signed [17:0] t1_im_45 = 34380; // sfix18
parameter signed [17:0] t1_im_46 = 35062; // sfix18
parameter signed [17:0] t1_im_47 = 35738; // sfix18
parameter signed [17:0] t1_im_48 = 36410; // sfix18
parameter signed [17:0] t1_im_49 = 37076; // sfix18
parameter signed [17:0] t1_im_50 = 37736; // sfix18
parameter signed [17:0] t1_im_51 = 38391; // sfix18
parameter signed [17:0] t1_im_52 = 39040; // sfix18
parameter signed [17:0] t1_im_53 = 39683; // sfix18
parameter signed [17:0] t1_im_54 = 40320; // sfix18
parameter signed [17:0] t1_im_55 = 40951; // sfix18
parameter signed [17:0] t1_im_56 = 41576; // sfix18
parameter signed [17:0] t1_im_57 = 42194; // sfix18
parameter signed [17:0] t1_im_58 = 42806; // sfix18
parameter signed [17:0] t1_im_59 = 43412; // sfix18
parameter signed [17:0] t1_im_60 = 44011; // sfix18
parameter signed [17:0] t1_im_61 = 44604; // sfix18
parameter signed [17:0] t1_im_62 = 45190; // sfix18
parameter signed [17:0] t1_im_63 = 45769; // sfix18
parameter signed [17:0] t1_im_64 = 46341; // sfix18
parameter signed [17:0] t1_im_65 = 46906; // sfix18
parameter signed [17:0] t1_im_66 = 47464; // sfix18
parameter signed [17:0] t1_im_67 = 48015; // sfix18
parameter signed [17:0] t1_im_68 = 48559; // sfix18
parameter signed [17:0] t1_im_69 = 49095; // sfix18
parameter signed [17:0] t1_im_70 = 49624; // sfix18
parameter signed [17:0] t1_im_71 = 50146; // sfix18
parameter signed [17:0] t1_im_72 = 50660; // sfix18
parameter signed [17:0] t1_im_73 = 51166; // sfix18
parameter signed [17:0] t1_im_74 = 51665; // sfix18
parameter signed [17:0] t1_im_75 = 52156; // sfix18
parameter signed [17:0] t1_im_76 = 52639; // sfix18
parameter signed [17:0] t1_im_77 = 53114; // sfix18
parameter signed [17:0] t1_im_78 = 53581; // sfix18
parameter signed [17:0] t1_im_79 = 54040; // sfix18
parameter signed [17:0] t1_im_80 = 54491; // sfix18
parameter signed [17:0] t1_im_81 = 54934; // sfix18
parameter signed [17:0] t1_im_82 = 55368; // sfix18
parameter signed [17:0] t1_im_83 = 55794; // sfix18
parameter signed [17:0] t1_im_84 = 56212; // sfix18
parameter signed [17:0] t1_im_85 = 56621; // sfix18
parameter signed [17:0] t1_im_86 = 57022; // sfix18
parameter signed [17:0] t1_im_87 = 57414; // sfix18
parameter signed [17:0] t1_im_88 = 57798; // sfix18
parameter signed [17:0] t1_im_89 = 58172; // sfix18
parameter signed [17:0] t1_im_90 = 58538; // sfix18
parameter signed [17:0] t1_im_91 = 58896; // sfix18
parameter signed [17:0] t1_im_92 = 59244; // sfix18
parameter signed [17:0] t1_im_93 = 59583; // sfix18
parameter signed [17:0] t1_im_94 = 59914; // sfix18
parameter signed [17:0] t1_im_95 = 60235; // sfix18
parameter signed [17:0] t1_im_96 = 60547; // sfix18
parameter signed [17:0] t1_im_97 = 60851; // sfix18
parameter signed [17:0] t1_im_98 = 61145; // sfix18
parameter signed [17:0] t1_im_99 = 61429; // sfix18
parameter signed [17:0] t1_im_100 = 61705; // sfix18
parameter signed [17:0] t1_im_101 = 61971; // sfix18
parameter signed [17:0] t1_im_102 = 62228; // sfix18
parameter signed [17:0] t1_im_103 = 62476; // sfix18
parameter signed [17:0] t1_im_104 = 62714; // sfix18
parameter signed [17:0] t1_im_105 = 62943; // sfix18
parameter signed [17:0] t1_im_106 = 63162; // sfix18
parameter signed [17:0] t1_im_107 = 63372; // sfix18
parameter signed [17:0] t1_im_108 = 63572; // sfix18
parameter signed [17:0] t1_im_109 = 63763; // sfix18
parameter signed [17:0] t1_im_110 = 63944; // sfix18
parameter signed [17:0] t1_im_111 = 64115; // sfix18
parameter signed [17:0] t1_im_112 = 64277; // sfix18
parameter signed [17:0] t1_im_113 = 64429; // sfix18
parameter signed [17:0] t1_im_114 = 64571; // sfix18
parameter signed [17:0] t1_im_115 = 64704; // sfix18
parameter signed [17:0] t1_im_116 = 64827; // sfix18
parameter signed [17:0] t1_im_117 = 64940; // sfix18
parameter signed [17:0] t1_im_118 = 65043; // sfix18
parameter signed [17:0] t1_im_119 = 65137; // sfix18
parameter signed [17:0] t1_im_120 = 65220; // sfix18
parameter signed [17:0] t1_im_121 = 65294; // sfix18
parameter signed [17:0] t1_im_122 = 65358; // sfix18
parameter signed [17:0] t1_im_123 = 65413; // sfix18
parameter signed [17:0] t1_im_124 = 65457; // sfix18
parameter signed [17:0] t1_im_125 = 65492; // sfix18
parameter signed [17:0] t1_im_126 = 65516; // sfix18
parameter signed [17:0] t1_im_127 = 65531; // sfix18
parameter signed [17:0] t1_im_128 = 65536; // sfix18
parameter signed [17:0] t1_im_129 = 65531; // sfix18
parameter signed [17:0] t1_im_130 = 65516; // sfix18
parameter signed [17:0] t1_im_131 = 65492; // sfix18
parameter signed [17:0] t1_im_132 = 65457; // sfix18
parameter signed [17:0] t1_im_133 = 65413; // sfix18
parameter signed [17:0] t1_im_134 = 65358; // sfix18
parameter signed [17:0] t1_im_135 = 65294; // sfix18
parameter signed [17:0] t1_im_136 = 65220; // sfix18
parameter signed [17:0] t1_im_137 = 65137; // sfix18
parameter signed [17:0] t1_im_138 = 65043; // sfix18
parameter signed [17:0] t1_im_139 = 64940; // sfix18
parameter signed [17:0] t1_im_140 = 64827; // sfix18
parameter signed [17:0] t1_im_141 = 64704; // sfix18
parameter signed [17:0] t1_im_142 = 64571; // sfix18
parameter signed [17:0] t1_im_143 = 64429; // sfix18
parameter signed [17:0] t1_im_144 = 64277; // sfix18
parameter signed [17:0] t1_im_145 = 64115; // sfix18
parameter signed [17:0] t1_im_146 = 63944; // sfix18
parameter signed [17:0] t1_im_147 = 63763; // sfix18
parameter signed [17:0] t1_im_148 = 63572; // sfix18
parameter signed [17:0] t1_im_149 = 63372; // sfix18
parameter signed [17:0] t1_im_150 = 63162; // sfix18
parameter signed [17:0] t1_im_151 = 62943; // sfix18
parameter signed [17:0] t1_im_152 = 62714; // sfix18
parameter signed [17:0] t1_im_153 = 62476; // sfix18
parameter signed [17:0] t1_im_154 = 62228; // sfix18
parameter signed [17:0] t1_im_155 = 61971; // sfix18
parameter signed [17:0] t1_im_156 = 61705; // sfix18
parameter signed [17:0] t1_im_157 = 61429; // sfix18
parameter signed [17:0] t1_im_158 = 61145; // sfix18
parameter signed [17:0] t1_im_159 = 60851; // sfix18
parameter signed [17:0] t1_im_160 = 60547; // sfix18
parameter signed [17:0] t1_im_161 = 60235; // sfix18
parameter signed [17:0] t1_im_162 = 59914; // sfix18
parameter signed [17:0] t1_im_163 = 59583; // sfix18
parameter signed [17:0] t1_im_164 = 59244; // sfix18
parameter signed [17:0] t1_im_165 = 58896; // sfix18
parameter signed [17:0] t1_im_166 = 58538; // sfix18
parameter signed [17:0] t1_im_167 = 58172; // sfix18
parameter signed [17:0] t1_im_168 = 57798; // sfix18
parameter signed [17:0] t1_im_169 = 57414; // sfix18
parameter signed [17:0] t1_im_170 = 57022; // sfix18
parameter signed [17:0] t1_im_171 = 56621; // sfix18
parameter signed [17:0] t1_im_172 = 56212; // sfix18
parameter signed [17:0] t1_im_173 = 55794; // sfix18
parameter signed [17:0] t1_im_174 = 55368; // sfix18
parameter signed [17:0] t1_im_175 = 54934; // sfix18
parameter signed [17:0] t1_im_176 = 54491; // sfix18
parameter signed [17:0] t1_im_177 = 54040; // sfix18
parameter signed [17:0] t1_im_178 = 53581; // sfix18
parameter signed [17:0] t1_im_179 = 53114; // sfix18
parameter signed [17:0] t1_im_180 = 52639; // sfix18
parameter signed [17:0] t1_im_181 = 52156; // sfix18
parameter signed [17:0] t1_im_182 = 51665; // sfix18
parameter signed [17:0] t1_im_183 = 51166; // sfix18
parameter signed [17:0] t1_im_184 = 50660; // sfix18
parameter signed [17:0] t1_im_185 = 50146; // sfix18
parameter signed [17:0] t1_im_186 = 49624; // sfix18
parameter signed [17:0] t1_im_187 = 49095; // sfix18
parameter signed [17:0] t1_im_188 = 48559; // sfix18
parameter signed [17:0] t1_im_189 = 48015; // sfix18
parameter signed [17:0] t1_im_190 = 47464; // sfix18
parameter signed [17:0] t1_im_191 = 46906; // sfix18
parameter signed [17:0] t1_im_192 = 46341; // sfix18
parameter signed [17:0] t1_im_193 = 45769; // sfix18
parameter signed [17:0] t1_im_194 = 45190; // sfix18
parameter signed [17:0] t1_im_195 = 44604; // sfix18
parameter signed [17:0] t1_im_196 = 44011; // sfix18
parameter signed [17:0] t1_im_197 = 43412; // sfix18
parameter signed [17:0] t1_im_198 = 42806; // sfix18
parameter signed [17:0] t1_im_199 = 42194; // sfix18
parameter signed [17:0] t1_im_200 = 41576; // sfix18
parameter signed [17:0] t1_im_201 = 40951; // sfix18
parameter signed [17:0] t1_im_202 = 40320; // sfix18
parameter signed [17:0] t1_im_203 = 39683; // sfix18
parameter signed [17:0] t1_im_204 = 39040; // sfix18
parameter signed [17:0] t1_im_205 = 38391; // sfix18
parameter signed [17:0] t1_im_206 = 37736; // sfix18
parameter signed [17:0] t1_im_207 = 37076; // sfix18
parameter signed [17:0] t1_im_208 = 36410; // sfix18
parameter signed [17:0] t1_im_209 = 35738; // sfix18
parameter signed [17:0] t1_im_210 = 35062; // sfix18
parameter signed [17:0] t1_im_211 = 34380; // sfix18
parameter signed [17:0] t1_im_212 = 33692; // sfix18
parameter signed [17:0] t1_im_213 = 33000; // sfix18
parameter signed [17:0] t1_im_214 = 32303; // sfix18
parameter signed [17:0] t1_im_215 = 31600; // sfix18
parameter signed [17:0] t1_im_216 = 30893; // sfix18
parameter signed [17:0] t1_im_217 = 30182; // sfix18
parameter signed [17:0] t1_im_218 = 29466; // sfix18
parameter signed [17:0] t1_im_219 = 28745; // sfix18
parameter signed [17:0] t1_im_220 = 28020; // sfix18
parameter signed [17:0] t1_im_221 = 27291; // sfix18
parameter signed [17:0] t1_im_222 = 26558; // sfix18
parameter signed [17:0] t1_im_223 = 25821; // sfix18
parameter signed [17:0] t1_im_224 = 25080; // sfix18
parameter signed [17:0] t1_im_225 = 24335; // sfix18
parameter signed [17:0] t1_im_226 = 23586; // sfix18
parameter signed [17:0] t1_im_227 = 22834; // sfix18
parameter signed [17:0] t1_im_228 = 22078; // sfix18
parameter signed [17:0] t1_im_229 = 21320; // sfix18
parameter signed [17:0] t1_im_230 = 20557; // sfix18
parameter signed [17:0] t1_im_231 = 19792; // sfix18
parameter signed [17:0] t1_im_232 = 19024; // sfix18
parameter signed [17:0] t1_im_233 = 18253; // sfix18
parameter signed [17:0] t1_im_234 = 17479; // sfix18
parameter signed [17:0] t1_im_235 = 16703; // sfix18
parameter signed [17:0] t1_im_236 = 15924; // sfix18
parameter signed [17:0] t1_im_237 = 15143; // sfix18
parameter signed [17:0] t1_im_238 = 14359; // sfix18
parameter signed [17:0] t1_im_239 = 13573; // sfix18
parameter signed [17:0] t1_im_240 = 12785; // sfix18
parameter signed [17:0] t1_im_241 = 11996; // sfix18
parameter signed [17:0] t1_im_242 = 11204; // sfix18
parameter signed [17:0] t1_im_243 = 10411; // sfix18
parameter signed [17:0] t1_im_244 = 9616; // sfix18
parameter signed [17:0] t1_im_245 = 8820; // sfix18
parameter signed [17:0] t1_im_246 = 8022; // sfix18
parameter signed [17:0] t1_im_247 = 7224; // sfix18
parameter signed [17:0] t1_im_248 = 6424; // sfix18
parameter signed [17:0] t1_im_249 = 5623; // sfix18
parameter signed [17:0] t1_im_250 = 4821; // sfix18
parameter signed [17:0] t1_im_251 = 4019; // sfix18
parameter signed [17:0] t1_im_252 = 3216; // sfix18
parameter signed [17:0] t1_im_253 = 2412; // sfix18
parameter signed [17:0] t1_im_254 = 1608; // sfix18
parameter signed [17:0] t1_im_255 = 804; // sfix18
parameter signed [17:0] t1_im_256 = 0; // sfix18
parameter signed [17:0] t1_im_257 = -804; // sfix18
parameter signed [17:0] t1_im_258 = -1608; // sfix18
parameter signed [17:0] t1_im_259 = -2412; // sfix18
parameter signed [17:0] t1_im_260 = -3216; // sfix18
parameter signed [17:0] t1_im_261 = -4019; // sfix18
parameter signed [17:0] t1_im_262 = -4821; // sfix18
parameter signed [17:0] t1_im_263 = -5623; // sfix18
parameter signed [17:0] t1_im_264 = -6424; // sfix18
parameter signed [17:0] t1_im_265 = -7224; // sfix18
parameter signed [17:0] t1_im_266 = -8022; // sfix18
parameter signed [17:0] t1_im_267 = -8820; // sfix18
parameter signed [17:0] t1_im_268 = -9616; // sfix18
parameter signed [17:0] t1_im_269 = -10411; // sfix18
parameter signed [17:0] t1_im_270 = -11204; // sfix18
parameter signed [17:0] t1_im_271 = -11996; // sfix18
parameter signed [17:0] t1_im_272 = -12785; // sfix18
parameter signed [17:0] t1_im_273 = -13573; // sfix18
parameter signed [17:0] t1_im_274 = -14359; // sfix18
parameter signed [17:0] t1_im_275 = -15143; // sfix18
parameter signed [17:0] t1_im_276 = -15924; // sfix18
parameter signed [17:0] t1_im_277 = -16703; // sfix18
parameter signed [17:0] t1_im_278 = -17479; // sfix18
parameter signed [17:0] t1_im_279 = -18253; // sfix18
parameter signed [17:0] t1_im_280 = -19024; // sfix18
parameter signed [17:0] t1_im_281 = -19792; // sfix18
parameter signed [17:0] t1_im_282 = -20557; // sfix18
parameter signed [17:0] t1_im_283 = -21320; // sfix18
parameter signed [17:0] t1_im_284 = -22078; // sfix18
parameter signed [17:0] t1_im_285 = -22834; // sfix18
parameter signed [17:0] t1_im_286 = -23586; // sfix18
parameter signed [17:0] t1_im_287 = -24335; // sfix18
parameter signed [17:0] t1_im_288 = -25080; // sfix18
parameter signed [17:0] t1_im_289 = -25821; // sfix18
parameter signed [17:0] t1_im_290 = -26558; // sfix18
parameter signed [17:0] t1_im_291 = -27291; // sfix18
parameter signed [17:0] t1_im_292 = -28020; // sfix18
parameter signed [17:0] t1_im_293 = -28745; // sfix18
parameter signed [17:0] t1_im_294 = -29466; // sfix18
parameter signed [17:0] t1_im_295 = -30182; // sfix18
parameter signed [17:0] t1_im_296 = -30893; // sfix18
parameter signed [17:0] t1_im_297 = -31600; // sfix18
parameter signed [17:0] t1_im_298 = -32303; // sfix18
parameter signed [17:0] t1_im_299 = -33000; // sfix18
parameter signed [17:0] t1_im_300 = -33692; // sfix18
parameter signed [17:0] t1_im_301 = -34380; // sfix18
parameter signed [17:0] t1_im_302 = -35062; // sfix18
parameter signed [17:0] t1_im_303 = -35738; // sfix18
parameter signed [17:0] t1_im_304 = -36410; // sfix18
parameter signed [17:0] t1_im_305 = -37076; // sfix18
parameter signed [17:0] t1_im_306 = -37736; // sfix18
parameter signed [17:0] t1_im_307 = -38391; // sfix18
parameter signed [17:0] t1_im_308 = -39040; // sfix18
parameter signed [17:0] t1_im_309 = -39683; // sfix18
parameter signed [17:0] t1_im_310 = -40320; // sfix18
parameter signed [17:0] t1_im_311 = -40951; // sfix18
parameter signed [17:0] t1_im_312 = -41576; // sfix18
parameter signed [17:0] t1_im_313 = -42194; // sfix18
parameter signed [17:0] t1_im_314 = -42806; // sfix18
parameter signed [17:0] t1_im_315 = -43412; // sfix18
parameter signed [17:0] t1_im_316 = -44011; // sfix18
parameter signed [17:0] t1_im_317 = -44604; // sfix18
parameter signed [17:0] t1_im_318 = -45190; // sfix18
parameter signed [17:0] t1_im_319 = -45769; // sfix18
parameter signed [17:0] t1_im_320 = -46341; // sfix18
parameter signed [17:0] t1_im_321 = -46906; // sfix18
parameter signed [17:0] t1_im_322 = -47464; // sfix18
parameter signed [17:0] t1_im_323 = -48015; // sfix18
parameter signed [17:0] t1_im_324 = -48559; // sfix18
parameter signed [17:0] t1_im_325 = -49095; // sfix18
parameter signed [17:0] t1_im_326 = -49624; // sfix18
parameter signed [17:0] t1_im_327 = -50146; // sfix18
parameter signed [17:0] t1_im_328 = -50660; // sfix18
parameter signed [17:0] t1_im_329 = -51166; // sfix18
parameter signed [17:0] t1_im_330 = -51665; // sfix18
parameter signed [17:0] t1_im_331 = -52156; // sfix18
parameter signed [17:0] t1_im_332 = -52639; // sfix18
parameter signed [17:0] t1_im_333 = -53114; // sfix18
parameter signed [17:0] t1_im_334 = -53581; // sfix18
parameter signed [17:0] t1_im_335 = -54040; // sfix18
parameter signed [17:0] t1_im_336 = -54491; // sfix18
parameter signed [17:0] t1_im_337 = -54934; // sfix18
parameter signed [17:0] t1_im_338 = -55368; // sfix18
parameter signed [17:0] t1_im_339 = -55794; // sfix18
parameter signed [17:0] t1_im_340 = -56212; // sfix18
parameter signed [17:0] t1_im_341 = -56621; // sfix18
parameter signed [17:0] t1_im_342 = -57022; // sfix18
parameter signed [17:0] t1_im_343 = -57414; // sfix18
parameter signed [17:0] t1_im_344 = -57798; // sfix18
parameter signed [17:0] t1_im_345 = -58172; // sfix18
parameter signed [17:0] t1_im_346 = -58538; // sfix18
parameter signed [17:0] t1_im_347 = -58896; // sfix18
parameter signed [17:0] t1_im_348 = -59244; // sfix18
parameter signed [17:0] t1_im_349 = -59583; // sfix18
parameter signed [17:0] t1_im_350 = -59914; // sfix18
parameter signed [17:0] t1_im_351 = -60235; // sfix18
parameter signed [17:0] t1_im_352 = -60547; // sfix18
parameter signed [17:0] t1_im_353 = -60851; // sfix18
parameter signed [17:0] t1_im_354 = -61145; // sfix18
parameter signed [17:0] t1_im_355 = -61429; // sfix18
parameter signed [17:0] t1_im_356 = -61705; // sfix18
parameter signed [17:0] t1_im_357 = -61971; // sfix18
parameter signed [17:0] t1_im_358 = -62228; // sfix18
parameter signed [17:0] t1_im_359 = -62476; // sfix18
parameter signed [17:0] t1_im_360 = -62714; // sfix18
parameter signed [17:0] t1_im_361 = -62943; // sfix18
parameter signed [17:0] t1_im_362 = -63162; // sfix18
parameter signed [17:0] t1_im_363 = -63372; // sfix18
parameter signed [17:0] t1_im_364 = -63572; // sfix18
parameter signed [17:0] t1_im_365 = -63763; // sfix18
parameter signed [17:0] t1_im_366 = -63944; // sfix18
parameter signed [17:0] t1_im_367 = -64115; // sfix18
parameter signed [17:0] t1_im_368 = -64277; // sfix18
parameter signed [17:0] t1_im_369 = -64429; // sfix18
parameter signed [17:0] t1_im_370 = -64571; // sfix18
parameter signed [17:0] t1_im_371 = -64704; // sfix18
parameter signed [17:0] t1_im_372 = -64827; // sfix18
parameter signed [17:0] t1_im_373 = -64940; // sfix18
parameter signed [17:0] t1_im_374 = -65043; // sfix18
parameter signed [17:0] t1_im_375 = -65137; // sfix18
parameter signed [17:0] t1_im_376 = -65220; // sfix18
parameter signed [17:0] t1_im_377 = -65294; // sfix18
parameter signed [17:0] t1_im_378 = -65358; // sfix18
parameter signed [17:0] t1_im_379 = -65413; // sfix18
parameter signed [17:0] t1_im_380 = -65457; // sfix18
parameter signed [17:0] t1_im_381 = -65492; // sfix18
parameter signed [17:0] t1_im_382 = -65516; // sfix18
parameter signed [17:0] t1_im_383 = -65531; // sfix18
parameter signed [17:0] t1_im_384 = -65536; // sfix18
parameter signed [17:0] t1_im_385 = -65531; // sfix18
parameter signed [17:0] t1_im_386 = -65516; // sfix18
parameter signed [17:0] t1_im_387 = -65492; // sfix18
parameter signed [17:0] t1_im_388 = -65457; // sfix18
parameter signed [17:0] t1_im_389 = -65413; // sfix18
parameter signed [17:0] t1_im_390 = -65358; // sfix18
parameter signed [17:0] t1_im_391 = -65294; // sfix18
parameter signed [17:0] t1_im_392 = -65220; // sfix18
parameter signed [17:0] t1_im_393 = -65137; // sfix18
parameter signed [17:0] t1_im_394 = -65043; // sfix18
parameter signed [17:0] t1_im_395 = -64940; // sfix18
parameter signed [17:0] t1_im_396 = -64827; // sfix18
parameter signed [17:0] t1_im_397 = -64704; // sfix18
parameter signed [17:0] t1_im_398 = -64571; // sfix18
parameter signed [17:0] t1_im_399 = -64429; // sfix18
parameter signed [17:0] t1_im_400 = -64277; // sfix18
parameter signed [17:0] t1_im_401 = -64115; // sfix18
parameter signed [17:0] t1_im_402 = -63944; // sfix18
parameter signed [17:0] t1_im_403 = -63763; // sfix18
parameter signed [17:0] t1_im_404 = -63572; // sfix18
parameter signed [17:0] t1_im_405 = -63372; // sfix18
parameter signed [17:0] t1_im_406 = -63162; // sfix18
parameter signed [17:0] t1_im_407 = -62943; // sfix18
parameter signed [17:0] t1_im_408 = -62714; // sfix18
parameter signed [17:0] t1_im_409 = -62476; // sfix18
parameter signed [17:0] t1_im_410 = -62228; // sfix18
parameter signed [17:0] t1_im_411 = -61971; // sfix18
parameter signed [17:0] t1_im_412 = -61705; // sfix18
parameter signed [17:0] t1_im_413 = -61429; // sfix18
parameter signed [17:0] t1_im_414 = -61145; // sfix18
parameter signed [17:0] t1_im_415 = -60851; // sfix18
parameter signed [17:0] t1_im_416 = -60547; // sfix18
parameter signed [17:0] t1_im_417 = -60235; // sfix18
parameter signed [17:0] t1_im_418 = -59914; // sfix18
parameter signed [17:0] t1_im_419 = -59583; // sfix18
parameter signed [17:0] t1_im_420 = -59244; // sfix18
parameter signed [17:0] t1_im_421 = -58896; // sfix18
parameter signed [17:0] t1_im_422 = -58538; // sfix18
parameter signed [17:0] t1_im_423 = -58172; // sfix18
parameter signed [17:0] t1_im_424 = -57798; // sfix18
parameter signed [17:0] t1_im_425 = -57414; // sfix18
parameter signed [17:0] t1_im_426 = -57022; // sfix18
parameter signed [17:0] t1_im_427 = -56621; // sfix18
parameter signed [17:0] t1_im_428 = -56212; // sfix18
parameter signed [17:0] t1_im_429 = -55794; // sfix18
parameter signed [17:0] t1_im_430 = -55368; // sfix18
parameter signed [17:0] t1_im_431 = -54934; // sfix18
parameter signed [17:0] t1_im_432 = -54491; // sfix18
parameter signed [17:0] t1_im_433 = -54040; // sfix18
parameter signed [17:0] t1_im_434 = -53581; // sfix18
parameter signed [17:0] t1_im_435 = -53114; // sfix18
parameter signed [17:0] t1_im_436 = -52639; // sfix18
parameter signed [17:0] t1_im_437 = -52156; // sfix18
parameter signed [17:0] t1_im_438 = -51665; // sfix18
parameter signed [17:0] t1_im_439 = -51166; // sfix18
parameter signed [17:0] t1_im_440 = -50660; // sfix18
parameter signed [17:0] t1_im_441 = -50146; // sfix18
parameter signed [17:0] t1_im_442 = -49624; // sfix18
parameter signed [17:0] t1_im_443 = -49095; // sfix18
parameter signed [17:0] t1_im_444 = -48559; // sfix18
parameter signed [17:0] t1_im_445 = -48015; // sfix18
parameter signed [17:0] t1_im_446 = -47464; // sfix18
parameter signed [17:0] t1_im_447 = -46906; // sfix18
parameter signed [17:0] t1_im_448 = -46341; // sfix18
parameter signed [17:0] t1_im_449 = -45769; // sfix18
parameter signed [17:0] t1_im_450 = -45190; // sfix18
parameter signed [17:0] t1_im_451 = -44604; // sfix18
parameter signed [17:0] t1_im_452 = -44011; // sfix18
parameter signed [17:0] t1_im_453 = -43412; // sfix18
parameter signed [17:0] t1_im_454 = -42806; // sfix18
parameter signed [17:0] t1_im_455 = -42194; // sfix18
parameter signed [17:0] t1_im_456 = -41576; // sfix18
parameter signed [17:0] t1_im_457 = -40951; // sfix18
parameter signed [17:0] t1_im_458 = -40320; // sfix18
parameter signed [17:0] t1_im_459 = -39683; // sfix18
parameter signed [17:0] t1_im_460 = -39040; // sfix18
parameter signed [17:0] t1_im_461 = -38391; // sfix18
parameter signed [17:0] t1_im_462 = -37736; // sfix18
parameter signed [17:0] t1_im_463 = -37076; // sfix18
parameter signed [17:0] t1_im_464 = -36410; // sfix18
parameter signed [17:0] t1_im_465 = -35738; // sfix18
parameter signed [17:0] t1_im_466 = -35062; // sfix18
parameter signed [17:0] t1_im_467 = -34380; // sfix18
parameter signed [17:0] t1_im_468 = -33692; // sfix18
parameter signed [17:0] t1_im_469 = -33000; // sfix18
parameter signed [17:0] t1_im_470 = -32303; // sfix18
parameter signed [17:0] t1_im_471 = -31600; // sfix18
parameter signed [17:0] t1_im_472 = -30893; // sfix18
parameter signed [17:0] t1_im_473 = -30182; // sfix18
parameter signed [17:0] t1_im_474 = -29466; // sfix18
parameter signed [17:0] t1_im_475 = -28745; // sfix18
parameter signed [17:0] t1_im_476 = -28020; // sfix18
parameter signed [17:0] t1_im_477 = -27291; // sfix18
parameter signed [17:0] t1_im_478 = -26558; // sfix18
parameter signed [17:0] t1_im_479 = -25821; // sfix18
parameter signed [17:0] t1_im_480 = -25080; // sfix18
parameter signed [17:0] t1_im_481 = -24335; // sfix18
parameter signed [17:0] t1_im_482 = -23586; // sfix18
parameter signed [17:0] t1_im_483 = -22834; // sfix18
parameter signed [17:0] t1_im_484 = -22078; // sfix18
parameter signed [17:0] t1_im_485 = -21320; // sfix18
parameter signed [17:0] t1_im_486 = -20557; // sfix18
parameter signed [17:0] t1_im_487 = -19792; // sfix18
parameter signed [17:0] t1_im_488 = -19024; // sfix18
parameter signed [17:0] t1_im_489 = -18253; // sfix18
parameter signed [17:0] t1_im_490 = -17479; // sfix18
parameter signed [17:0] t1_im_491 = -16703; // sfix18
parameter signed [17:0] t1_im_492 = -15924; // sfix18
parameter signed [17:0] t1_im_493 = -15143; // sfix18
parameter signed [17:0] t1_im_494 = -14359; // sfix18
parameter signed [17:0] t1_im_495 = -13573; // sfix18
parameter signed [17:0] t1_im_496 = -12785; // sfix18
parameter signed [17:0] t1_im_497 = -11996; // sfix18
parameter signed [17:0] t1_im_498 = -11204; // sfix18
parameter signed [17:0] t1_im_499 = -10411; // sfix18
parameter signed [17:0] t1_im_500 = -9616; // sfix18
parameter signed [17:0] t1_im_501 = -8820; // sfix18
parameter signed [17:0] t1_im_502 = -8022; // sfix18
parameter signed [17:0] t1_im_503 = -7224; // sfix18
parameter signed [17:0] t1_im_504 = -6424; // sfix18
parameter signed [17:0] t1_im_505 = -5623; // sfix18
parameter signed [17:0] t1_im_506 = -4821; // sfix18
parameter signed [17:0] t1_im_507 = -4019; // sfix18
parameter signed [17:0] t1_im_508 = -3216; // sfix18
parameter signed [17:0] t1_im_509 = -2412; // sfix18
parameter signed [17:0] t1_im_510 = -1608; // sfix18
parameter signed [17:0] t1_im_511 = -804; // sfix18
parameter signed [17:0] t1_re_0_2 = 65536; // sfix18
parameter signed [17:0] t1_re_1_2 = 65536; // sfix18
parameter signed [17:0] t1_re_2_2 = 65536; // sfix18
parameter signed [17:0] t1_re_3_2 = 65536; // sfix18
parameter signed [17:0] t1_re_4_2 = 65536; // sfix18
parameter signed [17:0] t1_re_5_2 = 65536; // sfix18
parameter signed [17:0] t1_re_6_2 = 65536; // sfix18
parameter signed [17:0] t1_re_7_2 = 65536; // sfix18
parameter signed [17:0] t1_re_8_2 = 65536; // sfix18
parameter signed [17:0] t1_re_9_2 = 65536; // sfix18
parameter signed [17:0] t1_re_10_2 = 65536; // sfix18
parameter signed [17:0] t1_re_11_2 = 65536; // sfix18
parameter signed [17:0] t1_re_12_2 = 65536; // sfix18
parameter signed [17:0] t1_re_13_2 = 65536; // sfix18
parameter signed [17:0] t1_re_14_2 = 65536; // sfix18
parameter signed [17:0] t1_re_15_2 = 65536; // sfix18
parameter signed [17:0] t1_re_16_2 = 65536; // sfix18
parameter signed [17:0] t1_re_17_2 = 65536; // sfix18
parameter signed [17:0] t1_re_18_2 = 65536; // sfix18
parameter signed [17:0] t1_re_19_2 = 65536; // sfix18
parameter signed [17:0] t1_re_20_2 = 65536; // sfix18
parameter signed [17:0] t1_re_21_2 = 65536; // sfix18
parameter signed [17:0] t1_re_22_2 = 65536; // sfix18
parameter signed [17:0] t1_re_23_2 = 65536; // sfix18
parameter signed [17:0] t1_re_24_2 = 65536; // sfix18
parameter signed [17:0] t1_re_25_2 = 65536; // sfix18
parameter signed [17:0] t1_re_26_2 = 65536; // sfix18
parameter signed [17:0] t1_re_27_2 = 65536; // sfix18
parameter signed [17:0] t1_re_28_2 = 65536; // sfix18
parameter signed [17:0] t1_re_29_2 = 65536; // sfix18
parameter signed [17:0] t1_re_30_2 = 65536; // sfix18
parameter signed [17:0] t1_re_31_2 = 65536; // sfix18
parameter signed [17:0] t1_re_32_2 = 65536; // sfix18
parameter signed [17:0] t1_re_33_2 = 65536; // sfix18
parameter signed [17:0] t1_re_34_2 = 65536; // sfix18
parameter signed [17:0] t1_re_35_2 = 65536; // sfix18
parameter signed [17:0] t1_re_36_2 = 65536; // sfix18
parameter signed [17:0] t1_re_37_2 = 65536; // sfix18
parameter signed [17:0] t1_re_38_2 = 65536; // sfix18
parameter signed [17:0] t1_re_39_2 = 65536; // sfix18
parameter signed [17:0] t1_re_40_2 = 65536; // sfix18
parameter signed [17:0] t1_re_41_2 = 65536; // sfix18
parameter signed [17:0] t1_re_42_2 = 65536; // sfix18
parameter signed [17:0] t1_re_43_2 = 65536; // sfix18
parameter signed [17:0] t1_re_44_2 = 65536; // sfix18
parameter signed [17:0] t1_re_45_2 = 65536; // sfix18
parameter signed [17:0] t1_re_46_2 = 65536; // sfix18
parameter signed [17:0] t1_re_47_2 = 65536; // sfix18
parameter signed [17:0] t1_re_48_2 = 65536; // sfix18
parameter signed [17:0] t1_re_49_2 = 65536; // sfix18
parameter signed [17:0] t1_re_50_2 = 65536; // sfix18
parameter signed [17:0] t1_re_51_2 = 65536; // sfix18
parameter signed [17:0] t1_re_52_2 = 65536; // sfix18
parameter signed [17:0] t1_re_53_2 = 65536; // sfix18
parameter signed [17:0] t1_re_54_2 = 65536; // sfix18
parameter signed [17:0] t1_re_55_2 = 65536; // sfix18
parameter signed [17:0] t1_re_56_2 = 65536; // sfix18
parameter signed [17:0] t1_re_57_2 = 65536; // sfix18
parameter signed [17:0] t1_re_58_2 = 65536; // sfix18
parameter signed [17:0] t1_re_59_2 = 65536; // sfix18
parameter signed [17:0] t1_re_60_2 = 65536; // sfix18
parameter signed [17:0] t1_re_61_2 = 65536; // sfix18
parameter signed [17:0] t1_re_62_2 = 65536; // sfix18
parameter signed [17:0] t1_re_63_2 = 65536; // sfix18
parameter signed [17:0] t1_re_64_2 = 65536; // sfix18
parameter signed [17:0] t1_re_65_2 = 65536; // sfix18
parameter signed [17:0] t1_re_66_2 = 65536; // sfix18
parameter signed [17:0] t1_re_67_2 = 65536; // sfix18
parameter signed [17:0] t1_re_68_2 = 65536; // sfix18
parameter signed [17:0] t1_re_69_2 = 65536; // sfix18
parameter signed [17:0] t1_re_70_2 = 65536; // sfix18
parameter signed [17:0] t1_re_71_2 = 65536; // sfix18
parameter signed [17:0] t1_re_72_2 = 65536; // sfix18
parameter signed [17:0] t1_re_73_2 = 65536; // sfix18
parameter signed [17:0] t1_re_74_2 = 65536; // sfix18
parameter signed [17:0] t1_re_75_2 = 65536; // sfix18
parameter signed [17:0] t1_re_76_2 = 65536; // sfix18
parameter signed [17:0] t1_re_77_2 = 65536; // sfix18
parameter signed [17:0] t1_re_78_2 = 65536; // sfix18
parameter signed [17:0] t1_re_79_2 = 65536; // sfix18
parameter signed [17:0] t1_re_80_2 = 65536; // sfix18
parameter signed [17:0] t1_re_81_2 = 65536; // sfix18
parameter signed [17:0] t1_re_82_2 = 65536; // sfix18
parameter signed [17:0] t1_re_83_2 = 65536; // sfix18
parameter signed [17:0] t1_re_84_2 = 65536; // sfix18
parameter signed [17:0] t1_re_85_2 = 65536; // sfix18
parameter signed [17:0] t1_re_86_2 = 65536; // sfix18
parameter signed [17:0] t1_re_87_2 = 65536; // sfix18
parameter signed [17:0] t1_re_88_2 = 65536; // sfix18
parameter signed [17:0] t1_re_89_2 = 65536; // sfix18
parameter signed [17:0] t1_re_90_2 = 65536; // sfix18
parameter signed [17:0] t1_re_91_2 = 65536; // sfix18
parameter signed [17:0] t1_re_92_2 = 65536; // sfix18
parameter signed [17:0] t1_re_93_2 = 65536; // sfix18
parameter signed [17:0] t1_re_94_2 = 65536; // sfix18
parameter signed [17:0] t1_re_95_2 = 65536; // sfix18
parameter signed [17:0] t1_re_96_2 = 65536; // sfix18
parameter signed [17:0] t1_re_97_2 = 65536; // sfix18
parameter signed [17:0] t1_re_98_2 = 65536; // sfix18
parameter signed [17:0] t1_re_99_2 = 65536; // sfix18
parameter signed [17:0] t1_re_100_2 = 65536; // sfix18
parameter signed [17:0] t1_re_101_2 = 65536; // sfix18
parameter signed [17:0] t1_re_102_2 = 65536; // sfix18
parameter signed [17:0] t1_re_103_2 = 65536; // sfix18
parameter signed [17:0] t1_re_104_2 = 65536; // sfix18
parameter signed [17:0] t1_re_105_2 = 65536; // sfix18
parameter signed [17:0] t1_re_106_2 = 65536; // sfix18
parameter signed [17:0] t1_re_107_2 = 65536; // sfix18
parameter signed [17:0] t1_re_108_2 = 65536; // sfix18
parameter signed [17:0] t1_re_109_2 = 65536; // sfix18
parameter signed [17:0] t1_re_110_2 = 65536; // sfix18
parameter signed [17:0] t1_re_111_2 = 65536; // sfix18
parameter signed [17:0] t1_re_112_2 = 65536; // sfix18
parameter signed [17:0] t1_re_113_2 = 65536; // sfix18
parameter signed [17:0] t1_re_114_2 = 65536; // sfix18
parameter signed [17:0] t1_re_115_2 = 65536; // sfix18
parameter signed [17:0] t1_re_116_2 = 65536; // sfix18
parameter signed [17:0] t1_re_117_2 = 65536; // sfix18
parameter signed [17:0] t1_re_118_2 = 65536; // sfix18
parameter signed [17:0] t1_re_119_2 = 65536; // sfix18
parameter signed [17:0] t1_re_120_2 = 65536; // sfix18
parameter signed [17:0] t1_re_121_2 = 65536; // sfix18
parameter signed [17:0] t1_re_122_2 = 65536; // sfix18
parameter signed [17:0] t1_re_123_2 = 65536; // sfix18
parameter signed [17:0] t1_re_124_2 = 65536; // sfix18
parameter signed [17:0] t1_re_125_2 = 65536; // sfix18
parameter signed [17:0] t1_re_126_2 = 65536; // sfix18
parameter signed [17:0] t1_re_127_2 = 65536; // sfix18
parameter signed [17:0] t1_re_128_2 = 65536; // sfix18
parameter signed [17:0] t1_re_129_2 = 65536; // sfix18
parameter signed [17:0] t1_re_130_2 = 65536; // sfix18
parameter signed [17:0] t1_re_131_2 = 65536; // sfix18
parameter signed [17:0] t1_re_132_2 = 65536; // sfix18
parameter signed [17:0] t1_re_133_2 = 65536; // sfix18
parameter signed [17:0] t1_re_134_2 = 65536; // sfix18
parameter signed [17:0] t1_re_135_2 = 65536; // sfix18
parameter signed [17:0] t1_re_136_2 = 65536; // sfix18
parameter signed [17:0] t1_re_137_2 = 65536; // sfix18
parameter signed [17:0] t1_re_138_2 = 65536; // sfix18
parameter signed [17:0] t1_re_139_2 = 65536; // sfix18
parameter signed [17:0] t1_re_140_2 = 65536; // sfix18
parameter signed [17:0] t1_re_141_2 = 65536; // sfix18
parameter signed [17:0] t1_re_142_2 = 65536; // sfix18
parameter signed [17:0] t1_re_143_2 = 65536; // sfix18
parameter signed [17:0] t1_re_144_2 = 65536; // sfix18
parameter signed [17:0] t1_re_145_2 = 65536; // sfix18
parameter signed [17:0] t1_re_146_2 = 65536; // sfix18
parameter signed [17:0] t1_re_147_2 = 65536; // sfix18
parameter signed [17:0] t1_re_148_2 = 65536; // sfix18
parameter signed [17:0] t1_re_149_2 = 65536; // sfix18
parameter signed [17:0] t1_re_150_2 = 65536; // sfix18
parameter signed [17:0] t1_re_151_2 = 65536; // sfix18
parameter signed [17:0] t1_re_152_2 = 65536; // sfix18
parameter signed [17:0] t1_re_153_2 = 65536; // sfix18
parameter signed [17:0] t1_re_154_2 = 65536; // sfix18
parameter signed [17:0] t1_re_155_2 = 65536; // sfix18
parameter signed [17:0] t1_re_156_2 = 65536; // sfix18
parameter signed [17:0] t1_re_157_2 = 65536; // sfix18
parameter signed [17:0] t1_re_158_2 = 65536; // sfix18
parameter signed [17:0] t1_re_159_2 = 65536; // sfix18
parameter signed [17:0] t1_re_160_2 = 65536; // sfix18
parameter signed [17:0] t1_re_161_2 = 65536; // sfix18
parameter signed [17:0] t1_re_162_2 = 65536; // sfix18
parameter signed [17:0] t1_re_163_2 = 65535; // sfix18
parameter signed [17:0] t1_re_164_2 = 65535; // sfix18
parameter signed [17:0] t1_re_165_2 = 65535; // sfix18
parameter signed [17:0] t1_re_166_2 = 65535; // sfix18
parameter signed [17:0] t1_re_167_2 = 65535; // sfix18
parameter signed [17:0] t1_re_168_2 = 65535; // sfix18
parameter signed [17:0] t1_re_169_2 = 65535; // sfix18
parameter signed [17:0] t1_re_170_2 = 65535; // sfix18
parameter signed [17:0] t1_re_171_2 = 65535; // sfix18
parameter signed [17:0] t1_re_172_2 = 65535; // sfix18
parameter signed [17:0] t1_re_173_2 = 65535; // sfix18
parameter signed [17:0] t1_re_174_2 = 65535; // sfix18
parameter signed [17:0] t1_re_175_2 = 65535; // sfix18
parameter signed [17:0] t1_re_176_2 = 65535; // sfix18
parameter signed [17:0] t1_re_177_2 = 65535; // sfix18
parameter signed [17:0] t1_re_178_2 = 65535; // sfix18
parameter signed [17:0] t1_re_179_2 = 65535; // sfix18
parameter signed [17:0] t1_re_180_2 = 65535; // sfix18
parameter signed [17:0] t1_re_181_2 = 65535; // sfix18
parameter signed [17:0] t1_re_182_2 = 65535; // sfix18
parameter signed [17:0] t1_re_183_2 = 65535; // sfix18
parameter signed [17:0] t1_re_184_2 = 65535; // sfix18
parameter signed [17:0] t1_re_185_2 = 65535; // sfix18
parameter signed [17:0] t1_re_186_2 = 65535; // sfix18
parameter signed [17:0] t1_re_187_2 = 65535; // sfix18
parameter signed [17:0] t1_re_188_2 = 65535; // sfix18
parameter signed [17:0] t1_re_189_2 = 65535; // sfix18
parameter signed [17:0] t1_re_190_2 = 65535; // sfix18
parameter signed [17:0] t1_re_191_2 = 65535; // sfix18
parameter signed [17:0] t1_re_192_2 = 65535; // sfix18
parameter signed [17:0] t1_re_193_2 = 65535; // sfix18
parameter signed [17:0] t1_re_194_2 = 65535; // sfix18
parameter signed [17:0] t1_re_195_2 = 65535; // sfix18
parameter signed [17:0] t1_re_196_2 = 65535; // sfix18
parameter signed [17:0] t1_re_197_2 = 65535; // sfix18
parameter signed [17:0] t1_re_198_2 = 65535; // sfix18
parameter signed [17:0] t1_re_199_2 = 65535; // sfix18
parameter signed [17:0] t1_re_200_2 = 65535; // sfix18
parameter signed [17:0] t1_re_201_2 = 65535; // sfix18
parameter signed [17:0] t1_re_202_2 = 65535; // sfix18
parameter signed [17:0] t1_re_203_2 = 65535; // sfix18
parameter signed [17:0] t1_re_204_2 = 65535; // sfix18
parameter signed [17:0] t1_re_205_2 = 65535; // sfix18
parameter signed [17:0] t1_re_206_2 = 65535; // sfix18
parameter signed [17:0] t1_re_207_2 = 65535; // sfix18
parameter signed [17:0] t1_re_208_2 = 65535; // sfix18
parameter signed [17:0] t1_re_209_2 = 65535; // sfix18
parameter signed [17:0] t1_re_210_2 = 65535; // sfix18
parameter signed [17:0] t1_re_211_2 = 65535; // sfix18
parameter signed [17:0] t1_re_212_2 = 65535; // sfix18
parameter signed [17:0] t1_re_213_2 = 65535; // sfix18
parameter signed [17:0] t1_re_214_2 = 65535; // sfix18
parameter signed [17:0] t1_re_215_2 = 65535; // sfix18
parameter signed [17:0] t1_re_216_2 = 65535; // sfix18
parameter signed [17:0] t1_re_217_2 = 65535; // sfix18
parameter signed [17:0] t1_re_218_2 = 65535; // sfix18
parameter signed [17:0] t1_re_219_2 = 65535; // sfix18
parameter signed [17:0] t1_re_220_2 = 65535; // sfix18
parameter signed [17:0] t1_re_221_2 = 65535; // sfix18
parameter signed [17:0] t1_re_222_2 = 65535; // sfix18
parameter signed [17:0] t1_re_223_2 = 65535; // sfix18
parameter signed [17:0] t1_re_224_2 = 65535; // sfix18
parameter signed [17:0] t1_re_225_2 = 65535; // sfix18
parameter signed [17:0] t1_re_226_2 = 65535; // sfix18
parameter signed [17:0] t1_re_227_2 = 65535; // sfix18
parameter signed [17:0] t1_re_228_2 = 65535; // sfix18
parameter signed [17:0] t1_re_229_2 = 65535; // sfix18
parameter signed [17:0] t1_re_230_2 = 65535; // sfix18
parameter signed [17:0] t1_re_231_2 = 65535; // sfix18
parameter signed [17:0] t1_re_232_2 = 65535; // sfix18
parameter signed [17:0] t1_re_233_2 = 65535; // sfix18
parameter signed [17:0] t1_re_234_2 = 65535; // sfix18
parameter signed [17:0] t1_re_235_2 = 65535; // sfix18
parameter signed [17:0] t1_re_236_2 = 65535; // sfix18
parameter signed [17:0] t1_re_237_2 = 65535; // sfix18
parameter signed [17:0] t1_re_238_2 = 65535; // sfix18
parameter signed [17:0] t1_re_239_2 = 65535; // sfix18
parameter signed [17:0] t1_re_240_2 = 65535; // sfix18
parameter signed [17:0] t1_re_241_2 = 65535; // sfix18
parameter signed [17:0] t1_re_242_2 = 65535; // sfix18
parameter signed [17:0] t1_re_243_2 = 65535; // sfix18
parameter signed [17:0] t1_re_244_2 = 65535; // sfix18
parameter signed [17:0] t1_re_245_2 = 65535; // sfix18
parameter signed [17:0] t1_re_246_2 = 65535; // sfix18
parameter signed [17:0] t1_re_247_2 = 65535; // sfix18
parameter signed [17:0] t1_re_248_2 = 65535; // sfix18
parameter signed [17:0] t1_re_249_2 = 65535; // sfix18
parameter signed [17:0] t1_re_250_2 = 65535; // sfix18
parameter signed [17:0] t1_re_251_2 = 65535; // sfix18
parameter signed [17:0] t1_re_252_2 = 65535; // sfix18
parameter signed [17:0] t1_re_253_2 = 65535; // sfix18
parameter signed [17:0] t1_re_254_2 = 65535; // sfix18
parameter signed [17:0] t1_re_255_2 = 65535; // sfix18
parameter signed [17:0] t1_re_256_2 = 65535; // sfix18
parameter signed [17:0] t1_re_257_2 = 65535; // sfix18
parameter signed [17:0] t1_re_258_2 = 65535; // sfix18
parameter signed [17:0] t1_re_259_2 = 65535; // sfix18
parameter signed [17:0] t1_re_260_2 = 65535; // sfix18
parameter signed [17:0] t1_re_261_2 = 65535; // sfix18
parameter signed [17:0] t1_re_262_2 = 65535; // sfix18
parameter signed [17:0] t1_re_263_2 = 65535; // sfix18
parameter signed [17:0] t1_re_264_2 = 65535; // sfix18
parameter signed [17:0] t1_re_265_2 = 65535; // sfix18
parameter signed [17:0] t1_re_266_2 = 65535; // sfix18
parameter signed [17:0] t1_re_267_2 = 65535; // sfix18
parameter signed [17:0] t1_re_268_2 = 65535; // sfix18
parameter signed [17:0] t1_re_269_2 = 65535; // sfix18
parameter signed [17:0] t1_re_270_2 = 65535; // sfix18
parameter signed [17:0] t1_re_271_2 = 65535; // sfix18
parameter signed [17:0] t1_re_272_2 = 65535; // sfix18
parameter signed [17:0] t1_re_273_2 = 65535; // sfix18
parameter signed [17:0] t1_re_274_2 = 65535; // sfix18
parameter signed [17:0] t1_re_275_2 = 65535; // sfix18
parameter signed [17:0] t1_re_276_2 = 65535; // sfix18
parameter signed [17:0] t1_re_277_2 = 65535; // sfix18
parameter signed [17:0] t1_re_278_2 = 65535; // sfix18
parameter signed [17:0] t1_re_279_2 = 65535; // sfix18
parameter signed [17:0] t1_re_280_2 = 65535; // sfix18
parameter signed [17:0] t1_re_281_2 = 65535; // sfix18
parameter signed [17:0] t1_re_282_2 = 65535; // sfix18
parameter signed [17:0] t1_re_283_2 = 65534; // sfix18
parameter signed [17:0] t1_re_284_2 = 65534; // sfix18
parameter signed [17:0] t1_re_285_2 = 65534; // sfix18
parameter signed [17:0] t1_re_286_2 = 65534; // sfix18
parameter signed [17:0] t1_re_287_2 = 65534; // sfix18
parameter signed [17:0] t1_re_288_2 = 65534; // sfix18
parameter signed [17:0] t1_re_289_2 = 65534; // sfix18
parameter signed [17:0] t1_re_290_2 = 65534; // sfix18
parameter signed [17:0] t1_re_291_2 = 65534; // sfix18
parameter signed [17:0] t1_re_292_2 = 65534; // sfix18
parameter signed [17:0] t1_re_293_2 = 65534; // sfix18
parameter signed [17:0] t1_re_294_2 = 65534; // sfix18
parameter signed [17:0] t1_re_295_2 = 65534; // sfix18
parameter signed [17:0] t1_re_296_2 = 65534; // sfix18
parameter signed [17:0] t1_re_297_2 = 65534; // sfix18
parameter signed [17:0] t1_re_298_2 = 65534; // sfix18
parameter signed [17:0] t1_re_299_2 = 65534; // sfix18
parameter signed [17:0] t1_re_300_2 = 65534; // sfix18
parameter signed [17:0] t1_re_301_2 = 65534; // sfix18
parameter signed [17:0] t1_re_302_2 = 65534; // sfix18
parameter signed [17:0] t1_re_303_2 = 65534; // sfix18
parameter signed [17:0] t1_re_304_2 = 65534; // sfix18
parameter signed [17:0] t1_re_305_2 = 65534; // sfix18
parameter signed [17:0] t1_re_306_2 = 65534; // sfix18
parameter signed [17:0] t1_re_307_2 = 65534; // sfix18
parameter signed [17:0] t1_re_308_2 = 65534; // sfix18
parameter signed [17:0] t1_re_309_2 = 65534; // sfix18
parameter signed [17:0] t1_re_310_2 = 65534; // sfix18
parameter signed [17:0] t1_re_311_2 = 65534; // sfix18
parameter signed [17:0] t1_re_312_2 = 65534; // sfix18
parameter signed [17:0] t1_re_313_2 = 65534; // sfix18
parameter signed [17:0] t1_re_314_2 = 65534; // sfix18
parameter signed [17:0] t1_re_315_2 = 65534; // sfix18
parameter signed [17:0] t1_re_316_2 = 65534; // sfix18
parameter signed [17:0] t1_re_317_2 = 65534; // sfix18
parameter signed [17:0] t1_re_318_2 = 65534; // sfix18
parameter signed [17:0] t1_re_319_2 = 65534; // sfix18
parameter signed [17:0] t1_re_320_2 = 65534; // sfix18
parameter signed [17:0] t1_re_321_2 = 65534; // sfix18
parameter signed [17:0] t1_re_322_2 = 65534; // sfix18
parameter signed [17:0] t1_re_323_2 = 65534; // sfix18
parameter signed [17:0] t1_re_324_2 = 65534; // sfix18
parameter signed [17:0] t1_re_325_2 = 65534; // sfix18
parameter signed [17:0] t1_re_326_2 = 65534; // sfix18
parameter signed [17:0] t1_re_327_2 = 65534; // sfix18
parameter signed [17:0] t1_re_328_2 = 65534; // sfix18
parameter signed [17:0] t1_re_329_2 = 65534; // sfix18
parameter signed [17:0] t1_re_330_2 = 65534; // sfix18
parameter signed [17:0] t1_re_331_2 = 65534; // sfix18
parameter signed [17:0] t1_re_332_2 = 65534; // sfix18
parameter signed [17:0] t1_re_333_2 = 65534; // sfix18
parameter signed [17:0] t1_re_334_2 = 65534; // sfix18
parameter signed [17:0] t1_re_335_2 = 65534; // sfix18
parameter signed [17:0] t1_re_336_2 = 65534; // sfix18
parameter signed [17:0] t1_re_337_2 = 65534; // sfix18
parameter signed [17:0] t1_re_338_2 = 65534; // sfix18
parameter signed [17:0] t1_re_339_2 = 65534; // sfix18
parameter signed [17:0] t1_re_340_2 = 65534; // sfix18
parameter signed [17:0] t1_re_341_2 = 65534; // sfix18
parameter signed [17:0] t1_re_342_2 = 65534; // sfix18
parameter signed [17:0] t1_re_343_2 = 65534; // sfix18
parameter signed [17:0] t1_re_344_2 = 65534; // sfix18
parameter signed [17:0] t1_re_345_2 = 65534; // sfix18
parameter signed [17:0] t1_re_346_2 = 65534; // sfix18
parameter signed [17:0] t1_re_347_2 = 65534; // sfix18
parameter signed [17:0] t1_re_348_2 = 65534; // sfix18
parameter signed [17:0] t1_re_349_2 = 65534; // sfix18
parameter signed [17:0] t1_re_350_2 = 65534; // sfix18
parameter signed [17:0] t1_re_351_2 = 65534; // sfix18
parameter signed [17:0] t1_re_352_2 = 65534; // sfix18
parameter signed [17:0] t1_re_353_2 = 65534; // sfix18
parameter signed [17:0] t1_re_354_2 = 65534; // sfix18
parameter signed [17:0] t1_re_355_2 = 65534; // sfix18
parameter signed [17:0] t1_re_356_2 = 65534; // sfix18
parameter signed [17:0] t1_re_357_2 = 65534; // sfix18
parameter signed [17:0] t1_re_358_2 = 65534; // sfix18
parameter signed [17:0] t1_re_359_2 = 65534; // sfix18
parameter signed [17:0] t1_re_360_2 = 65534; // sfix18
parameter signed [17:0] t1_re_361_2 = 65534; // sfix18
parameter signed [17:0] t1_re_362_2 = 65534; // sfix18
parameter signed [17:0] t1_re_363_2 = 65534; // sfix18
parameter signed [17:0] t1_re_364_2 = 65534; // sfix18
parameter signed [17:0] t1_re_365_2 = 65533; // sfix18
parameter signed [17:0] t1_re_366_2 = 65533; // sfix18
parameter signed [17:0] t1_re_367_2 = 65533; // sfix18
parameter signed [17:0] t1_re_368_2 = 65533; // sfix18
parameter signed [17:0] t1_re_369_2 = 65533; // sfix18
parameter signed [17:0] t1_re_370_2 = 65533; // sfix18
parameter signed [17:0] t1_re_371_2 = 65533; // sfix18
parameter signed [17:0] t1_re_372_2 = 65533; // sfix18
parameter signed [17:0] t1_re_373_2 = 65533; // sfix18
parameter signed [17:0] t1_re_374_2 = 65533; // sfix18
parameter signed [17:0] t1_re_375_2 = 65533; // sfix18
parameter signed [17:0] t1_re_376_2 = 65533; // sfix18
parameter signed [17:0] t1_re_377_2 = 65533; // sfix18
parameter signed [17:0] t1_re_378_2 = 65533; // sfix18
parameter signed [17:0] t1_re_379_2 = 65533; // sfix18
parameter signed [17:0] t1_re_380_2 = 65533; // sfix18
parameter signed [17:0] t1_re_381_2 = 65533; // sfix18
parameter signed [17:0] t1_re_382_2 = 65533; // sfix18
parameter signed [17:0] t1_re_383_2 = 65533; // sfix18
parameter signed [17:0] t1_re_384_2 = 65533; // sfix18
parameter signed [17:0] t1_re_385_2 = 65533; // sfix18
parameter signed [17:0] t1_re_386_2 = 65533; // sfix18
parameter signed [17:0] t1_re_387_2 = 65533; // sfix18
parameter signed [17:0] t1_re_388_2 = 65533; // sfix18
parameter signed [17:0] t1_re_389_2 = 65533; // sfix18
parameter signed [17:0] t1_re_390_2 = 65533; // sfix18
parameter signed [17:0] t1_re_391_2 = 65533; // sfix18
parameter signed [17:0] t1_re_392_2 = 65533; // sfix18
parameter signed [17:0] t1_re_393_2 = 65533; // sfix18
parameter signed [17:0] t1_re_394_2 = 65533; // sfix18
parameter signed [17:0] t1_re_395_2 = 65533; // sfix18
parameter signed [17:0] t1_re_396_2 = 65533; // sfix18
parameter signed [17:0] t1_re_397_2 = 65533; // sfix18
parameter signed [17:0] t1_re_398_2 = 65533; // sfix18
parameter signed [17:0] t1_re_399_2 = 65533; // sfix18
parameter signed [17:0] t1_re_400_2 = 65533; // sfix18
parameter signed [17:0] t1_re_401_2 = 65533; // sfix18
parameter signed [17:0] t1_re_402_2 = 65533; // sfix18
parameter signed [17:0] t1_re_403_2 = 65533; // sfix18
parameter signed [17:0] t1_re_404_2 = 65533; // sfix18
parameter signed [17:0] t1_re_405_2 = 65533; // sfix18
parameter signed [17:0] t1_re_406_2 = 65533; // sfix18
parameter signed [17:0] t1_re_407_2 = 65533; // sfix18
parameter signed [17:0] t1_re_408_2 = 65533; // sfix18
parameter signed [17:0] t1_re_409_2 = 65533; // sfix18
parameter signed [17:0] t1_re_410_2 = 65533; // sfix18
parameter signed [17:0] t1_re_411_2 = 65533; // sfix18
parameter signed [17:0] t1_re_412_2 = 65533; // sfix18
parameter signed [17:0] t1_re_413_2 = 65533; // sfix18
parameter signed [17:0] t1_re_414_2 = 65533; // sfix18
parameter signed [17:0] t1_re_415_2 = 65533; // sfix18
parameter signed [17:0] t1_re_416_2 = 65533; // sfix18
parameter signed [17:0] t1_re_417_2 = 65533; // sfix18
parameter signed [17:0] t1_re_418_2 = 65533; // sfix18
parameter signed [17:0] t1_re_419_2 = 65533; // sfix18
parameter signed [17:0] t1_re_420_2 = 65533; // sfix18
parameter signed [17:0] t1_re_421_2 = 65533; // sfix18
parameter signed [17:0] t1_re_422_2 = 65533; // sfix18
parameter signed [17:0] t1_re_423_2 = 65533; // sfix18
parameter signed [17:0] t1_re_424_2 = 65533; // sfix18
parameter signed [17:0] t1_re_425_2 = 65533; // sfix18
parameter signed [17:0] t1_re_426_2 = 65533; // sfix18
parameter signed [17:0] t1_re_427_2 = 65533; // sfix18
parameter signed [17:0] t1_re_428_2 = 65533; // sfix18
parameter signed [17:0] t1_re_429_2 = 65533; // sfix18
parameter signed [17:0] t1_re_430_2 = 65533; // sfix18
parameter signed [17:0] t1_re_431_2 = 65533; // sfix18
parameter signed [17:0] t1_re_432_2 = 65532; // sfix18
parameter signed [17:0] t1_re_433_2 = 65532; // sfix18
parameter signed [17:0] t1_re_434_2 = 65532; // sfix18
parameter signed [17:0] t1_re_435_2 = 65532; // sfix18
parameter signed [17:0] t1_re_436_2 = 65532; // sfix18
parameter signed [17:0] t1_re_437_2 = 65532; // sfix18
parameter signed [17:0] t1_re_438_2 = 65532; // sfix18
parameter signed [17:0] t1_re_439_2 = 65532; // sfix18
parameter signed [17:0] t1_re_440_2 = 65532; // sfix18
parameter signed [17:0] t1_re_441_2 = 65532; // sfix18
parameter signed [17:0] t1_re_442_2 = 65532; // sfix18
parameter signed [17:0] t1_re_443_2 = 65532; // sfix18
parameter signed [17:0] t1_re_444_2 = 65532; // sfix18
parameter signed [17:0] t1_re_445_2 = 65532; // sfix18
parameter signed [17:0] t1_re_446_2 = 65532; // sfix18
parameter signed [17:0] t1_re_447_2 = 65532; // sfix18
parameter signed [17:0] t1_re_448_2 = 65532; // sfix18
parameter signed [17:0] t1_re_449_2 = 65532; // sfix18
parameter signed [17:0] t1_re_450_2 = 65532; // sfix18
parameter signed [17:0] t1_re_451_2 = 65532; // sfix18
parameter signed [17:0] t1_re_452_2 = 65532; // sfix18
parameter signed [17:0] t1_re_453_2 = 65532; // sfix18
parameter signed [17:0] t1_re_454_2 = 65532; // sfix18
parameter signed [17:0] t1_re_455_2 = 65532; // sfix18
parameter signed [17:0] t1_re_456_2 = 65532; // sfix18
parameter signed [17:0] t1_re_457_2 = 65532; // sfix18
parameter signed [17:0] t1_re_458_2 = 65532; // sfix18
parameter signed [17:0] t1_re_459_2 = 65532; // sfix18
parameter signed [17:0] t1_re_460_2 = 65532; // sfix18
parameter signed [17:0] t1_re_461_2 = 65532; // sfix18
parameter signed [17:0] t1_re_462_2 = 65532; // sfix18
parameter signed [17:0] t1_re_463_2 = 65532; // sfix18
parameter signed [17:0] t1_re_464_2 = 65532; // sfix18
parameter signed [17:0] t1_re_465_2 = 65532; // sfix18
parameter signed [17:0] t1_re_466_2 = 65532; // sfix18
parameter signed [17:0] t1_re_467_2 = 65532; // sfix18
parameter signed [17:0] t1_re_468_2 = 65532; // sfix18
parameter signed [17:0] t1_re_469_2 = 65532; // sfix18
parameter signed [17:0] t1_re_470_2 = 65532; // sfix18
parameter signed [17:0] t1_re_471_2 = 65532; // sfix18
parameter signed [17:0] t1_re_472_2 = 65532; // sfix18
parameter signed [17:0] t1_re_473_2 = 65532; // sfix18
parameter signed [17:0] t1_re_474_2 = 65532; // sfix18
parameter signed [17:0] t1_re_475_2 = 65532; // sfix18
parameter signed [17:0] t1_re_476_2 = 65532; // sfix18
parameter signed [17:0] t1_re_477_2 = 65532; // sfix18
parameter signed [17:0] t1_re_478_2 = 65532; // sfix18
parameter signed [17:0] t1_re_479_2 = 65532; // sfix18
parameter signed [17:0] t1_re_480_2 = 65532; // sfix18
parameter signed [17:0] t1_re_481_2 = 65532; // sfix18
parameter signed [17:0] t1_re_482_2 = 65532; // sfix18
parameter signed [17:0] t1_re_483_2 = 65532; // sfix18
parameter signed [17:0] t1_re_484_2 = 65532; // sfix18
parameter signed [17:0] t1_re_485_2 = 65532; // sfix18
parameter signed [17:0] t1_re_486_2 = 65532; // sfix18
parameter signed [17:0] t1_re_487_2 = 65532; // sfix18
parameter signed [17:0] t1_re_488_2 = 65532; // sfix18
parameter signed [17:0] t1_re_489_2 = 65531; // sfix18
parameter signed [17:0] t1_re_490_2 = 65531; // sfix18
parameter signed [17:0] t1_re_491_2 = 65531; // sfix18
parameter signed [17:0] t1_re_492_2 = 65531; // sfix18
parameter signed [17:0] t1_re_493_2 = 65531; // sfix18
parameter signed [17:0] t1_re_494_2 = 65531; // sfix18
parameter signed [17:0] t1_re_495_2 = 65531; // sfix18
parameter signed [17:0] t1_re_496_2 = 65531; // sfix18
parameter signed [17:0] t1_re_497_2 = 65531; // sfix18
parameter signed [17:0] t1_re_498_2 = 65531; // sfix18
parameter signed [17:0] t1_re_499_2 = 65531; // sfix18
parameter signed [17:0] t1_re_500_2 = 65531; // sfix18
parameter signed [17:0] t1_re_501_2 = 65531; // sfix18
parameter signed [17:0] t1_re_502_2 = 65531; // sfix18
parameter signed [17:0] t1_re_503_2 = 65531; // sfix18
parameter signed [17:0] t1_re_504_2 = 65531; // sfix18
parameter signed [17:0] t1_re_505_2 = 65531; // sfix18
parameter signed [17:0] t1_re_506_2 = 65531; // sfix18
parameter signed [17:0] t1_re_507_2 = 65531; // sfix18
parameter signed [17:0] t1_re_508_2 = 65531; // sfix18
parameter signed [17:0] t1_re_509_2 = 65531; // sfix18
parameter signed [17:0] t1_re_510_2 = 65531; // sfix18
parameter signed [17:0] t1_re_511_2 = 65531; // sfix18
parameter signed [17:0] t1_im_0_2 = 0; // sfix18
parameter signed [17:0] t1_im_1_2 = 2; // sfix18
parameter signed [17:0] t1_im_2_2 = 3; // sfix18
parameter signed [17:0] t1_im_3_2 = 5; // sfix18
parameter signed [17:0] t1_im_4_2 = 6; // sfix18
parameter signed [17:0] t1_im_5_2 = 8; // sfix18
parameter signed [17:0] t1_im_6_2 = 9; // sfix18
parameter signed [17:0] t1_im_7_2 = 11; // sfix18
parameter signed [17:0] t1_im_8_2 = 13; // sfix18
parameter signed [17:0] t1_im_9_2 = 14; // sfix18
parameter signed [17:0] t1_im_10_2 = 16; // sfix18
parameter signed [17:0] t1_im_11_2 = 17; // sfix18
parameter signed [17:0] t1_im_12_2 = 19; // sfix18
parameter signed [17:0] t1_im_13_2 = 20; // sfix18
parameter signed [17:0] t1_im_14_2 = 22; // sfix18
parameter signed [17:0] t1_im_15_2 = 24; // sfix18
parameter signed [17:0] t1_im_16_2 = 25; // sfix18
parameter signed [17:0] t1_im_17_2 = 27; // sfix18
parameter signed [17:0] t1_im_18_2 = 28; // sfix18
parameter signed [17:0] t1_im_19_2 = 30; // sfix18
parameter signed [17:0] t1_im_20_2 = 31; // sfix18
parameter signed [17:0] t1_im_21_2 = 33; // sfix18
parameter signed [17:0] t1_im_22_2 = 35; // sfix18
parameter signed [17:0] t1_im_23_2 = 36; // sfix18
parameter signed [17:0] t1_im_24_2 = 38; // sfix18
parameter signed [17:0] t1_im_25_2 = 39; // sfix18
parameter signed [17:0] t1_im_26_2 = 41; // sfix18
parameter signed [17:0] t1_im_27_2 = 42; // sfix18
parameter signed [17:0] t1_im_28_2 = 44; // sfix18
parameter signed [17:0] t1_im_29_2 = 46; // sfix18
parameter signed [17:0] t1_im_30_2 = 47; // sfix18
parameter signed [17:0] t1_im_31_2 = 49; // sfix18
parameter signed [17:0] t1_im_32_2 = 50; // sfix18
parameter signed [17:0] t1_im_33_2 = 52; // sfix18
parameter signed [17:0] t1_im_34_2 = 53; // sfix18
parameter signed [17:0] t1_im_35_2 = 55; // sfix18
parameter signed [17:0] t1_im_36_2 = 57; // sfix18
parameter signed [17:0] t1_im_37_2 = 58; // sfix18
parameter signed [17:0] t1_im_38_2 = 60; // sfix18
parameter signed [17:0] t1_im_39_2 = 61; // sfix18
parameter signed [17:0] t1_im_40_2 = 63; // sfix18
parameter signed [17:0] t1_im_41_2 = 64; // sfix18
parameter signed [17:0] t1_im_42_2 = 66; // sfix18
parameter signed [17:0] t1_im_43_2 = 68; // sfix18
parameter signed [17:0] t1_im_44_2 = 69; // sfix18
parameter signed [17:0] t1_im_45_2 = 71; // sfix18
parameter signed [17:0] t1_im_46_2 = 72; // sfix18
parameter signed [17:0] t1_im_47_2 = 74; // sfix18
parameter signed [17:0] t1_im_48_2 = 75; // sfix18
parameter signed [17:0] t1_im_49_2 = 77; // sfix18
parameter signed [17:0] t1_im_50_2 = 79; // sfix18
parameter signed [17:0] t1_im_51_2 = 80; // sfix18
parameter signed [17:0] t1_im_52_2 = 82; // sfix18
parameter signed [17:0] t1_im_53_2 = 83; // sfix18
parameter signed [17:0] t1_im_54_2 = 85; // sfix18
parameter signed [17:0] t1_im_55_2 = 86; // sfix18
parameter signed [17:0] t1_im_56_2 = 88; // sfix18
parameter signed [17:0] t1_im_57_2 = 90; // sfix18
parameter signed [17:0] t1_im_58_2 = 91; // sfix18
parameter signed [17:0] t1_im_59_2 = 93; // sfix18
parameter signed [17:0] t1_im_60_2 = 94; // sfix18
parameter signed [17:0] t1_im_61_2 = 96; // sfix18
parameter signed [17:0] t1_im_62_2 = 97; // sfix18
parameter signed [17:0] t1_im_63_2 = 99; // sfix18
parameter signed [17:0] t1_im_64_2 = 101; // sfix18
parameter signed [17:0] t1_im_65_2 = 102; // sfix18
parameter signed [17:0] t1_im_66_2 = 104; // sfix18
parameter signed [17:0] t1_im_67_2 = 105; // sfix18
parameter signed [17:0] t1_im_68_2 = 107; // sfix18
parameter signed [17:0] t1_im_69_2 = 108; // sfix18
parameter signed [17:0] t1_im_70_2 = 110; // sfix18
parameter signed [17:0] t1_im_71_2 = 112; // sfix18
parameter signed [17:0] t1_im_72_2 = 113; // sfix18
parameter signed [17:0] t1_im_73_2 = 115; // sfix18
parameter signed [17:0] t1_im_74_2 = 116; // sfix18
parameter signed [17:0] t1_im_75_2 = 118; // sfix18
parameter signed [17:0] t1_im_76_2 = 119; // sfix18
parameter signed [17:0] t1_im_77_2 = 121; // sfix18
parameter signed [17:0] t1_im_78_2 = 123; // sfix18
parameter signed [17:0] t1_im_79_2 = 124; // sfix18
parameter signed [17:0] t1_im_80_2 = 126; // sfix18
parameter signed [17:0] t1_im_81_2 = 127; // sfix18
parameter signed [17:0] t1_im_82_2 = 129; // sfix18
parameter signed [17:0] t1_im_83_2 = 130; // sfix18
parameter signed [17:0] t1_im_84_2 = 132; // sfix18
parameter signed [17:0] t1_im_85_2 = 134; // sfix18
parameter signed [17:0] t1_im_86_2 = 135; // sfix18
parameter signed [17:0] t1_im_87_2 = 137; // sfix18
parameter signed [17:0] t1_im_88_2 = 138; // sfix18
parameter signed [17:0] t1_im_89_2 = 140; // sfix18
parameter signed [17:0] t1_im_90_2 = 141; // sfix18
parameter signed [17:0] t1_im_91_2 = 143; // sfix18
parameter signed [17:0] t1_im_92_2 = 145; // sfix18
parameter signed [17:0] t1_im_93_2 = 146; // sfix18
parameter signed [17:0] t1_im_94_2 = 148; // sfix18
parameter signed [17:0] t1_im_95_2 = 149; // sfix18
parameter signed [17:0] t1_im_96_2 = 151; // sfix18
parameter signed [17:0] t1_im_97_2 = 152; // sfix18
parameter signed [17:0] t1_im_98_2 = 154; // sfix18
parameter signed [17:0] t1_im_99_2 = 156; // sfix18
parameter signed [17:0] t1_im_100_2 = 157; // sfix18
parameter signed [17:0] t1_im_101_2 = 159; // sfix18
parameter signed [17:0] t1_im_102_2 = 160; // sfix18
parameter signed [17:0] t1_im_103_2 = 162; // sfix18
parameter signed [17:0] t1_im_104_2 = 163; // sfix18
parameter signed [17:0] t1_im_105_2 = 165; // sfix18
parameter signed [17:0] t1_im_106_2 = 167; // sfix18
parameter signed [17:0] t1_im_107_2 = 168; // sfix18
parameter signed [17:0] t1_im_108_2 = 170; // sfix18
parameter signed [17:0] t1_im_109_2 = 171; // sfix18
parameter signed [17:0] t1_im_110_2 = 173; // sfix18
parameter signed [17:0] t1_im_111_2 = 174; // sfix18
parameter signed [17:0] t1_im_112_2 = 176; // sfix18
parameter signed [17:0] t1_im_113_2 = 177; // sfix18
parameter signed [17:0] t1_im_114_2 = 179; // sfix18
parameter signed [17:0] t1_im_115_2 = 181; // sfix18
parameter signed [17:0] t1_im_116_2 = 182; // sfix18
parameter signed [17:0] t1_im_117_2 = 184; // sfix18
parameter signed [17:0] t1_im_118_2 = 185; // sfix18
parameter signed [17:0] t1_im_119_2 = 187; // sfix18
parameter signed [17:0] t1_im_120_2 = 188; // sfix18
parameter signed [17:0] t1_im_121_2 = 190; // sfix18
parameter signed [17:0] t1_im_122_2 = 192; // sfix18
parameter signed [17:0] t1_im_123_2 = 193; // sfix18
parameter signed [17:0] t1_im_124_2 = 195; // sfix18
parameter signed [17:0] t1_im_125_2 = 196; // sfix18
parameter signed [17:0] t1_im_126_2 = 198; // sfix18
parameter signed [17:0] t1_im_127_2 = 199; // sfix18
parameter signed [17:0] t1_im_128_2 = 201; // sfix18
parameter signed [17:0] t1_im_129_2 = 203; // sfix18
parameter signed [17:0] t1_im_130_2 = 204; // sfix18
parameter signed [17:0] t1_im_131_2 = 206; // sfix18
parameter signed [17:0] t1_im_132_2 = 207; // sfix18
parameter signed [17:0] t1_im_133_2 = 209; // sfix18
parameter signed [17:0] t1_im_134_2 = 210; // sfix18
parameter signed [17:0] t1_im_135_2 = 212; // sfix18
parameter signed [17:0] t1_im_136_2 = 214; // sfix18
parameter signed [17:0] t1_im_137_2 = 215; // sfix18
parameter signed [17:0] t1_im_138_2 = 217; // sfix18
parameter signed [17:0] t1_im_139_2 = 218; // sfix18
parameter signed [17:0] t1_im_140_2 = 220; // sfix18
parameter signed [17:0] t1_im_141_2 = 221; // sfix18
parameter signed [17:0] t1_im_142_2 = 223; // sfix18
parameter signed [17:0] t1_im_143_2 = 225; // sfix18
parameter signed [17:0] t1_im_144_2 = 226; // sfix18
parameter signed [17:0] t1_im_145_2 = 228; // sfix18
parameter signed [17:0] t1_im_146_2 = 229; // sfix18
parameter signed [17:0] t1_im_147_2 = 231; // sfix18
parameter signed [17:0] t1_im_148_2 = 232; // sfix18
parameter signed [17:0] t1_im_149_2 = 234; // sfix18
parameter signed [17:0] t1_im_150_2 = 236; // sfix18
parameter signed [17:0] t1_im_151_2 = 237; // sfix18
parameter signed [17:0] t1_im_152_2 = 239; // sfix18
parameter signed [17:0] t1_im_153_2 = 240; // sfix18
parameter signed [17:0] t1_im_154_2 = 242; // sfix18
parameter signed [17:0] t1_im_155_2 = 243; // sfix18
parameter signed [17:0] t1_im_156_2 = 245; // sfix18
parameter signed [17:0] t1_im_157_2 = 247; // sfix18
parameter signed [17:0] t1_im_158_2 = 248; // sfix18
parameter signed [17:0] t1_im_159_2 = 250; // sfix18
parameter signed [17:0] t1_im_160_2 = 251; // sfix18
parameter signed [17:0] t1_im_161_2 = 253; // sfix18
parameter signed [17:0] t1_im_162_2 = 254; // sfix18
parameter signed [17:0] t1_im_163_2 = 256; // sfix18
parameter signed [17:0] t1_im_164_2 = 258; // sfix18
parameter signed [17:0] t1_im_165_2 = 259; // sfix18
parameter signed [17:0] t1_im_166_2 = 261; // sfix18
parameter signed [17:0] t1_im_167_2 = 262; // sfix18
parameter signed [17:0] t1_im_168_2 = 264; // sfix18
parameter signed [17:0] t1_im_169_2 = 265; // sfix18
parameter signed [17:0] t1_im_170_2 = 267; // sfix18
parameter signed [17:0] t1_im_171_2 = 269; // sfix18
parameter signed [17:0] t1_im_172_2 = 270; // sfix18
parameter signed [17:0] t1_im_173_2 = 272; // sfix18
parameter signed [17:0] t1_im_174_2 = 273; // sfix18
parameter signed [17:0] t1_im_175_2 = 275; // sfix18
parameter signed [17:0] t1_im_176_2 = 276; // sfix18
parameter signed [17:0] t1_im_177_2 = 278; // sfix18
parameter signed [17:0] t1_im_178_2 = 280; // sfix18
parameter signed [17:0] t1_im_179_2 = 281; // sfix18
parameter signed [17:0] t1_im_180_2 = 283; // sfix18
parameter signed [17:0] t1_im_181_2 = 284; // sfix18
parameter signed [17:0] t1_im_182_2 = 286; // sfix18
parameter signed [17:0] t1_im_183_2 = 287; // sfix18
parameter signed [17:0] t1_im_184_2 = 289; // sfix18
parameter signed [17:0] t1_im_185_2 = 291; // sfix18
parameter signed [17:0] t1_im_186_2 = 292; // sfix18
parameter signed [17:0] t1_im_187_2 = 294; // sfix18
parameter signed [17:0] t1_im_188_2 = 295; // sfix18
parameter signed [17:0] t1_im_189_2 = 297; // sfix18
parameter signed [17:0] t1_im_190_2 = 298; // sfix18
parameter signed [17:0] t1_im_191_2 = 300; // sfix18
parameter signed [17:0] t1_im_192_2 = 302; // sfix18
parameter signed [17:0] t1_im_193_2 = 303; // sfix18
parameter signed [17:0] t1_im_194_2 = 305; // sfix18
parameter signed [17:0] t1_im_195_2 = 306; // sfix18
parameter signed [17:0] t1_im_196_2 = 308; // sfix18
parameter signed [17:0] t1_im_197_2 = 309; // sfix18
parameter signed [17:0] t1_im_198_2 = 311; // sfix18
parameter signed [17:0] t1_im_199_2 = 313; // sfix18
parameter signed [17:0] t1_im_200_2 = 314; // sfix18
parameter signed [17:0] t1_im_201_2 = 316; // sfix18
parameter signed [17:0] t1_im_202_2 = 317; // sfix18
parameter signed [17:0] t1_im_203_2 = 319; // sfix18
parameter signed [17:0] t1_im_204_2 = 320; // sfix18
parameter signed [17:0] t1_im_205_2 = 322; // sfix18
parameter signed [17:0] t1_im_206_2 = 324; // sfix18
parameter signed [17:0] t1_im_207_2 = 325; // sfix18
parameter signed [17:0] t1_im_208_2 = 327; // sfix18
parameter signed [17:0] t1_im_209_2 = 328; // sfix18
parameter signed [17:0] t1_im_210_2 = 330; // sfix18
parameter signed [17:0] t1_im_211_2 = 331; // sfix18
parameter signed [17:0] t1_im_212_2 = 333; // sfix18
parameter signed [17:0] t1_im_213_2 = 335; // sfix18
parameter signed [17:0] t1_im_214_2 = 336; // sfix18
parameter signed [17:0] t1_im_215_2 = 338; // sfix18
parameter signed [17:0] t1_im_216_2 = 339; // sfix18
parameter signed [17:0] t1_im_217_2 = 341; // sfix18
parameter signed [17:0] t1_im_218_2 = 342; // sfix18
parameter signed [17:0] t1_im_219_2 = 344; // sfix18
parameter signed [17:0] t1_im_220_2 = 346; // sfix18
parameter signed [17:0] t1_im_221_2 = 347; // sfix18
parameter signed [17:0] t1_im_222_2 = 349; // sfix18
parameter signed [17:0] t1_im_223_2 = 350; // sfix18
parameter signed [17:0] t1_im_224_2 = 352; // sfix18
parameter signed [17:0] t1_im_225_2 = 353; // sfix18
parameter signed [17:0] t1_im_226_2 = 355; // sfix18
parameter signed [17:0] t1_im_227_2 = 357; // sfix18
parameter signed [17:0] t1_im_228_2 = 358; // sfix18
parameter signed [17:0] t1_im_229_2 = 360; // sfix18
parameter signed [17:0] t1_im_230_2 = 361; // sfix18
parameter signed [17:0] t1_im_231_2 = 363; // sfix18
parameter signed [17:0] t1_im_232_2 = 364; // sfix18
parameter signed [17:0] t1_im_233_2 = 366; // sfix18
parameter signed [17:0] t1_im_234_2 = 368; // sfix18
parameter signed [17:0] t1_im_235_2 = 369; // sfix18
parameter signed [17:0] t1_im_236_2 = 371; // sfix18
parameter signed [17:0] t1_im_237_2 = 372; // sfix18
parameter signed [17:0] t1_im_238_2 = 374; // sfix18
parameter signed [17:0] t1_im_239_2 = 375; // sfix18
parameter signed [17:0] t1_im_240_2 = 377; // sfix18
parameter signed [17:0] t1_im_241_2 = 379; // sfix18
parameter signed [17:0] t1_im_242_2 = 380; // sfix18
parameter signed [17:0] t1_im_243_2 = 382; // sfix18
parameter signed [17:0] t1_im_244_2 = 383; // sfix18
parameter signed [17:0] t1_im_245_2 = 385; // sfix18
parameter signed [17:0] t1_im_246_2 = 386; // sfix18
parameter signed [17:0] t1_im_247_2 = 388; // sfix18
parameter signed [17:0] t1_im_248_2 = 390; // sfix18
parameter signed [17:0] t1_im_249_2 = 391; // sfix18
parameter signed [17:0] t1_im_250_2 = 393; // sfix18
parameter signed [17:0] t1_im_251_2 = 394; // sfix18
parameter signed [17:0] t1_im_252_2 = 396; // sfix18
parameter signed [17:0] t1_im_253_2 = 397; // sfix18
parameter signed [17:0] t1_im_254_2 = 399; // sfix18
parameter signed [17:0] t1_im_255_2 = 401; // sfix18
parameter signed [17:0] t1_im_256_2 = 402; // sfix18
parameter signed [17:0] t1_im_257_2 = 404; // sfix18
parameter signed [17:0] t1_im_258_2 = 405; // sfix18
parameter signed [17:0] t1_im_259_2 = 407; // sfix18
parameter signed [17:0] t1_im_260_2 = 408; // sfix18
parameter signed [17:0] t1_im_261_2 = 410; // sfix18
parameter signed [17:0] t1_im_262_2 = 412; // sfix18
parameter signed [17:0] t1_im_263_2 = 413; // sfix18
parameter signed [17:0] t1_im_264_2 = 415; // sfix18
parameter signed [17:0] t1_im_265_2 = 416; // sfix18
parameter signed [17:0] t1_im_266_2 = 418; // sfix18
parameter signed [17:0] t1_im_267_2 = 419; // sfix18
parameter signed [17:0] t1_im_268_2 = 421; // sfix18
parameter signed [17:0] t1_im_269_2 = 423; // sfix18
parameter signed [17:0] t1_im_270_2 = 424; // sfix18
parameter signed [17:0] t1_im_271_2 = 426; // sfix18
parameter signed [17:0] t1_im_272_2 = 427; // sfix18
parameter signed [17:0] t1_im_273_2 = 429; // sfix18
parameter signed [17:0] t1_im_274_2 = 430; // sfix18
parameter signed [17:0] t1_im_275_2 = 432; // sfix18
parameter signed [17:0] t1_im_276_2 = 434; // sfix18
parameter signed [17:0] t1_im_277_2 = 435; // sfix18
parameter signed [17:0] t1_im_278_2 = 437; // sfix18
parameter signed [17:0] t1_im_279_2 = 438; // sfix18
parameter signed [17:0] t1_im_280_2 = 440; // sfix18
parameter signed [17:0] t1_im_281_2 = 441; // sfix18
parameter signed [17:0] t1_im_282_2 = 443; // sfix18
parameter signed [17:0] t1_im_283_2 = 445; // sfix18
parameter signed [17:0] t1_im_284_2 = 446; // sfix18
parameter signed [17:0] t1_im_285_2 = 448; // sfix18
parameter signed [17:0] t1_im_286_2 = 449; // sfix18
parameter signed [17:0] t1_im_287_2 = 451; // sfix18
parameter signed [17:0] t1_im_288_2 = 452; // sfix18
parameter signed [17:0] t1_im_289_2 = 454; // sfix18
parameter signed [17:0] t1_im_290_2 = 456; // sfix18
parameter signed [17:0] t1_im_291_2 = 457; // sfix18
parameter signed [17:0] t1_im_292_2 = 459; // sfix18
parameter signed [17:0] t1_im_293_2 = 460; // sfix18
parameter signed [17:0] t1_im_294_2 = 462; // sfix18
parameter signed [17:0] t1_im_295_2 = 463; // sfix18
parameter signed [17:0] t1_im_296_2 = 465; // sfix18
parameter signed [17:0] t1_im_297_2 = 467; // sfix18
parameter signed [17:0] t1_im_298_2 = 468; // sfix18
parameter signed [17:0] t1_im_299_2 = 470; // sfix18
parameter signed [17:0] t1_im_300_2 = 471; // sfix18
parameter signed [17:0] t1_im_301_2 = 473; // sfix18
parameter signed [17:0] t1_im_302_2 = 474; // sfix18
parameter signed [17:0] t1_im_303_2 = 476; // sfix18
parameter signed [17:0] t1_im_304_2 = 478; // sfix18
parameter signed [17:0] t1_im_305_2 = 479; // sfix18
parameter signed [17:0] t1_im_306_2 = 481; // sfix18
parameter signed [17:0] t1_im_307_2 = 482; // sfix18
parameter signed [17:0] t1_im_308_2 = 484; // sfix18
parameter signed [17:0] t1_im_309_2 = 485; // sfix18
parameter signed [17:0] t1_im_310_2 = 487; // sfix18
parameter signed [17:0] t1_im_311_2 = 489; // sfix18
parameter signed [17:0] t1_im_312_2 = 490; // sfix18
parameter signed [17:0] t1_im_313_2 = 492; // sfix18
parameter signed [17:0] t1_im_314_2 = 493; // sfix18
parameter signed [17:0] t1_im_315_2 = 495; // sfix18
parameter signed [17:0] t1_im_316_2 = 496; // sfix18
parameter signed [17:0] t1_im_317_2 = 498; // sfix18
parameter signed [17:0] t1_im_318_2 = 500; // sfix18
parameter signed [17:0] t1_im_319_2 = 501; // sfix18
parameter signed [17:0] t1_im_320_2 = 503; // sfix18
parameter signed [17:0] t1_im_321_2 = 504; // sfix18
parameter signed [17:0] t1_im_322_2 = 506; // sfix18
parameter signed [17:0] t1_im_323_2 = 507; // sfix18
parameter signed [17:0] t1_im_324_2 = 509; // sfix18
parameter signed [17:0] t1_im_325_2 = 511; // sfix18
parameter signed [17:0] t1_im_326_2 = 512; // sfix18
parameter signed [17:0] t1_im_327_2 = 514; // sfix18
parameter signed [17:0] t1_im_328_2 = 515; // sfix18
parameter signed [17:0] t1_im_329_2 = 517; // sfix18
parameter signed [17:0] t1_im_330_2 = 518; // sfix18
parameter signed [17:0] t1_im_331_2 = 520; // sfix18
parameter signed [17:0] t1_im_332_2 = 521; // sfix18
parameter signed [17:0] t1_im_333_2 = 523; // sfix18
parameter signed [17:0] t1_im_334_2 = 525; // sfix18
parameter signed [17:0] t1_im_335_2 = 526; // sfix18
parameter signed [17:0] t1_im_336_2 = 528; // sfix18
parameter signed [17:0] t1_im_337_2 = 529; // sfix18
parameter signed [17:0] t1_im_338_2 = 531; // sfix18
parameter signed [17:0] t1_im_339_2 = 532; // sfix18
parameter signed [17:0] t1_im_340_2 = 534; // sfix18
parameter signed [17:0] t1_im_341_2 = 536; // sfix18
parameter signed [17:0] t1_im_342_2 = 537; // sfix18
parameter signed [17:0] t1_im_343_2 = 539; // sfix18
parameter signed [17:0] t1_im_344_2 = 540; // sfix18
parameter signed [17:0] t1_im_345_2 = 542; // sfix18
parameter signed [17:0] t1_im_346_2 = 543; // sfix18
parameter signed [17:0] t1_im_347_2 = 545; // sfix18
parameter signed [17:0] t1_im_348_2 = 547; // sfix18
parameter signed [17:0] t1_im_349_2 = 548; // sfix18
parameter signed [17:0] t1_im_350_2 = 550; // sfix18
parameter signed [17:0] t1_im_351_2 = 551; // sfix18
parameter signed [17:0] t1_im_352_2 = 553; // sfix18
parameter signed [17:0] t1_im_353_2 = 554; // sfix18
parameter signed [17:0] t1_im_354_2 = 556; // sfix18
parameter signed [17:0] t1_im_355_2 = 558; // sfix18
parameter signed [17:0] t1_im_356_2 = 559; // sfix18
parameter signed [17:0] t1_im_357_2 = 561; // sfix18
parameter signed [17:0] t1_im_358_2 = 562; // sfix18
parameter signed [17:0] t1_im_359_2 = 564; // sfix18
parameter signed [17:0] t1_im_360_2 = 565; // sfix18
parameter signed [17:0] t1_im_361_2 = 567; // sfix18
parameter signed [17:0] t1_im_362_2 = 569; // sfix18
parameter signed [17:0] t1_im_363_2 = 570; // sfix18
parameter signed [17:0] t1_im_364_2 = 572; // sfix18
parameter signed [17:0] t1_im_365_2 = 573; // sfix18
parameter signed [17:0] t1_im_366_2 = 575; // sfix18
parameter signed [17:0] t1_im_367_2 = 576; // sfix18
parameter signed [17:0] t1_im_368_2 = 578; // sfix18
parameter signed [17:0] t1_im_369_2 = 580; // sfix18
parameter signed [17:0] t1_im_370_2 = 581; // sfix18
parameter signed [17:0] t1_im_371_2 = 583; // sfix18
parameter signed [17:0] t1_im_372_2 = 584; // sfix18
parameter signed [17:0] t1_im_373_2 = 586; // sfix18
parameter signed [17:0] t1_im_374_2 = 587; // sfix18
parameter signed [17:0] t1_im_375_2 = 589; // sfix18
parameter signed [17:0] t1_im_376_2 = 591; // sfix18
parameter signed [17:0] t1_im_377_2 = 592; // sfix18
parameter signed [17:0] t1_im_378_2 = 594; // sfix18
parameter signed [17:0] t1_im_379_2 = 595; // sfix18
parameter signed [17:0] t1_im_380_2 = 597; // sfix18
parameter signed [17:0] t1_im_381_2 = 598; // sfix18
parameter signed [17:0] t1_im_382_2 = 600; // sfix18
parameter signed [17:0] t1_im_383_2 = 602; // sfix18
parameter signed [17:0] t1_im_384_2 = 603; // sfix18
parameter signed [17:0] t1_im_385_2 = 605; // sfix18
parameter signed [17:0] t1_im_386_2 = 606; // sfix18
parameter signed [17:0] t1_im_387_2 = 608; // sfix18
parameter signed [17:0] t1_im_388_2 = 609; // sfix18
parameter signed [17:0] t1_im_389_2 = 611; // sfix18
parameter signed [17:0] t1_im_390_2 = 613; // sfix18
parameter signed [17:0] t1_im_391_2 = 614; // sfix18
parameter signed [17:0] t1_im_392_2 = 616; // sfix18
parameter signed [17:0] t1_im_393_2 = 617; // sfix18
parameter signed [17:0] t1_im_394_2 = 619; // sfix18
parameter signed [17:0] t1_im_395_2 = 620; // sfix18
parameter signed [17:0] t1_im_396_2 = 622; // sfix18
parameter signed [17:0] t1_im_397_2 = 624; // sfix18
parameter signed [17:0] t1_im_398_2 = 625; // sfix18
parameter signed [17:0] t1_im_399_2 = 627; // sfix18
parameter signed [17:0] t1_im_400_2 = 628; // sfix18
parameter signed [17:0] t1_im_401_2 = 630; // sfix18
parameter signed [17:0] t1_im_402_2 = 631; // sfix18
parameter signed [17:0] t1_im_403_2 = 633; // sfix18
parameter signed [17:0] t1_im_404_2 = 635; // sfix18
parameter signed [17:0] t1_im_405_2 = 636; // sfix18
parameter signed [17:0] t1_im_406_2 = 638; // sfix18
parameter signed [17:0] t1_im_407_2 = 639; // sfix18
parameter signed [17:0] t1_im_408_2 = 641; // sfix18
parameter signed [17:0] t1_im_409_2 = 642; // sfix18
parameter signed [17:0] t1_im_410_2 = 644; // sfix18
parameter signed [17:0] t1_im_411_2 = 646; // sfix18
parameter signed [17:0] t1_im_412_2 = 647; // sfix18
parameter signed [17:0] t1_im_413_2 = 649; // sfix18
parameter signed [17:0] t1_im_414_2 = 650; // sfix18
parameter signed [17:0] t1_im_415_2 = 652; // sfix18
parameter signed [17:0] t1_im_416_2 = 653; // sfix18
parameter signed [17:0] t1_im_417_2 = 655; // sfix18
parameter signed [17:0] t1_im_418_2 = 657; // sfix18
parameter signed [17:0] t1_im_419_2 = 658; // sfix18
parameter signed [17:0] t1_im_420_2 = 660; // sfix18
parameter signed [17:0] t1_im_421_2 = 661; // sfix18
parameter signed [17:0] t1_im_422_2 = 663; // sfix18
parameter signed [17:0] t1_im_423_2 = 664; // sfix18
parameter signed [17:0] t1_im_424_2 = 666; // sfix18
parameter signed [17:0] t1_im_425_2 = 668; // sfix18
parameter signed [17:0] t1_im_426_2 = 669; // sfix18
parameter signed [17:0] t1_im_427_2 = 671; // sfix18
parameter signed [17:0] t1_im_428_2 = 672; // sfix18
parameter signed [17:0] t1_im_429_2 = 674; // sfix18
parameter signed [17:0] t1_im_430_2 = 675; // sfix18
parameter signed [17:0] t1_im_431_2 = 677; // sfix18
parameter signed [17:0] t1_im_432_2 = 679; // sfix18
parameter signed [17:0] t1_im_433_2 = 680; // sfix18
parameter signed [17:0] t1_im_434_2 = 682; // sfix18
parameter signed [17:0] t1_im_435_2 = 683; // sfix18
parameter signed [17:0] t1_im_436_2 = 685; // sfix18
parameter signed [17:0] t1_im_437_2 = 686; // sfix18
parameter signed [17:0] t1_im_438_2 = 688; // sfix18
parameter signed [17:0] t1_im_439_2 = 690; // sfix18
parameter signed [17:0] t1_im_440_2 = 691; // sfix18
parameter signed [17:0] t1_im_441_2 = 693; // sfix18
parameter signed [17:0] t1_im_442_2 = 694; // sfix18
parameter signed [17:0] t1_im_443_2 = 696; // sfix18
parameter signed [17:0] t1_im_444_2 = 697; // sfix18
parameter signed [17:0] t1_im_445_2 = 699; // sfix18
parameter signed [17:0] t1_im_446_2 = 701; // sfix18
parameter signed [17:0] t1_im_447_2 = 702; // sfix18
parameter signed [17:0] t1_im_448_2 = 704; // sfix18
parameter signed [17:0] t1_im_449_2 = 705; // sfix18
parameter signed [17:0] t1_im_450_2 = 707; // sfix18
parameter signed [17:0] t1_im_451_2 = 708; // sfix18
parameter signed [17:0] t1_im_452_2 = 710; // sfix18
parameter signed [17:0] t1_im_453_2 = 712; // sfix18
parameter signed [17:0] t1_im_454_2 = 713; // sfix18
parameter signed [17:0] t1_im_455_2 = 715; // sfix18
parameter signed [17:0] t1_im_456_2 = 716; // sfix18
parameter signed [17:0] t1_im_457_2 = 718; // sfix18
parameter signed [17:0] t1_im_458_2 = 719; // sfix18
parameter signed [17:0] t1_im_459_2 = 721; // sfix18
parameter signed [17:0] t1_im_460_2 = 723; // sfix18
parameter signed [17:0] t1_im_461_2 = 724; // sfix18
parameter signed [17:0] t1_im_462_2 = 726; // sfix18
parameter signed [17:0] t1_im_463_2 = 727; // sfix18
parameter signed [17:0] t1_im_464_2 = 729; // sfix18
parameter signed [17:0] t1_im_465_2 = 730; // sfix18
parameter signed [17:0] t1_im_466_2 = 732; // sfix18
parameter signed [17:0] t1_im_467_2 = 734; // sfix18
parameter signed [17:0] t1_im_468_2 = 735; // sfix18
parameter signed [17:0] t1_im_469_2 = 737; // sfix18
parameter signed [17:0] t1_im_470_2 = 738; // sfix18
parameter signed [17:0] t1_im_471_2 = 740; // sfix18
parameter signed [17:0] t1_im_472_2 = 741; // sfix18
parameter signed [17:0] t1_im_473_2 = 743; // sfix18
parameter signed [17:0] t1_im_474_2 = 745; // sfix18
parameter signed [17:0] t1_im_475_2 = 746; // sfix18
parameter signed [17:0] t1_im_476_2 = 748; // sfix18
parameter signed [17:0] t1_im_477_2 = 749; // sfix18
parameter signed [17:0] t1_im_478_2 = 751; // sfix18
parameter signed [17:0] t1_im_479_2 = 752; // sfix18
parameter signed [17:0] t1_im_480_2 = 754; // sfix18
parameter signed [17:0] t1_im_481_2 = 756; // sfix18
parameter signed [17:0] t1_im_482_2 = 757; // sfix18
parameter signed [17:0] t1_im_483_2 = 759; // sfix18
parameter signed [17:0] t1_im_484_2 = 760; // sfix18
parameter signed [17:0] t1_im_485_2 = 762; // sfix18
parameter signed [17:0] t1_im_486_2 = 763; // sfix18
parameter signed [17:0] t1_im_487_2 = 765; // sfix18
parameter signed [17:0] t1_im_488_2 = 767; // sfix18
parameter signed [17:0] t1_im_489_2 = 768; // sfix18
parameter signed [17:0] t1_im_490_2 = 770; // sfix18
parameter signed [17:0] t1_im_491_2 = 771; // sfix18
parameter signed [17:0] t1_im_492_2 = 773; // sfix18
parameter signed [17:0] t1_im_493_2 = 774; // sfix18
parameter signed [17:0] t1_im_494_2 = 776; // sfix18
parameter signed [17:0] t1_im_495_2 = 778; // sfix18
parameter signed [17:0] t1_im_496_2 = 779; // sfix18
parameter signed [17:0] t1_im_497_2 = 781; // sfix18
parameter signed [17:0] t1_im_498_2 = 782; // sfix18
parameter signed [17:0] t1_im_499_2 = 784; // sfix18
parameter signed [17:0] t1_im_500_2 = 785; // sfix18
parameter signed [17:0] t1_im_501_2 = 787; // sfix18
parameter signed [17:0] t1_im_502_2 = 789; // sfix18
parameter signed [17:0] t1_im_503_2 = 790; // sfix18
parameter signed [17:0] t1_im_504_2 = 792; // sfix18
parameter signed [17:0] t1_im_505_2 = 793; // sfix18
parameter signed [17:0] t1_im_506_2 = 795; // sfix18
parameter signed [17:0] t1_im_507_2 = 796; // sfix18
parameter signed [17:0] t1_im_508_2 = 798; // sfix18
parameter signed [17:0] t1_im_509_2 = 800; // sfix18
parameter signed [17:0] t1_im_510_2 = 801; // sfix18
parameter signed [17:0] t1_im_511_2 = 803; // sfix18
wire signed [17:0] Convert_Data_Type_out1; // sfix18_En14
wire signed [35:0] Normalize_Gain_mul_temp; // sfix36_En33
wire [17:0] Normalize_Gain_out1; // ufix18_En18
wire [17:0] elec_pos_scaled; // ufix18
wire [8:0] y; // ufix9
wire [15:0] Data_Type_Conversion1_out1; // uint16
wire signed [17:0] Direct_Lookup_Table_n_D_t1_re [0:511]; // sfix18_En16 [512]
wire signed [17:0] Direct_Lookup_Table_n_D_t1_im [0:511]; // sfix18_En16 [512]
wire signed [17:0] Direct_Lookup_Table_n_D_out1_re; // sfix18_En16
wire signed [17:0] Direct_Lookup_Table_n_D_out1_im; // sfix18_En16
wire [8:0] y_1; // ufix9
wire [15:0] Data_Type_Conversion2_out1; // uint16
wire signed [17:0] Direct_Lookup_Table_n_D_1_t1_re [0:511]; // sfix18_En16 [512]
wire signed [17:0] Direct_Lookup_Table_n_D_1_t1_im [0:511]; // sfix18_En16 [512]
wire signed [17:0] Direct_Lookup_Table_n_D_1_out1_re; // sfix18_En16
wire signed [17:0] Direct_Lookup_Table_n_D_1_out1_im; // sfix18_En16
wire signed [35:0] cos_coefficient; // sfix36_En32
wire signed [35:0] sin_coefficient; // sfix36_En32
wire signed [17:0] sin_coefficient_1; // sfix18_En16
wire signed [17:0] cos_coefficient_1; // sfix18_En16
// Rotation Coefficients Sin Cos
//
// Calculate sine and cosine of electrical angle using look up table.
// <S18>/Convert_Data_Type
controllerHdl_Convert_Data_Type_block1 u_Convert_Data_Type (.In1(x), // sfix18_En14
.Out1(Convert_Data_Type_out1) // sfix18_En14
);
// <S18>/Normalize Gain
assign Normalize_Gain_mul_temp = 83443 * Convert_Data_Type_out1;
assign Normalize_Gain_out1 = ((Normalize_Gain_mul_temp[35] == 1'b0) && (Normalize_Gain_mul_temp[34:33] != 2'b00) ? 18'b111111111111111111 :
(Normalize_Gain_mul_temp[35] == 1'b1 ? 18'b000000000000000000 :
Normalize_Gain_mul_temp[32:15]));
// <S18>/Remove Scaling
assign elec_pos_scaled = Normalize_Gain_out1;
// <S18>/Mark_Extract_Bits
controllerHdl_Mark_Extract_Bits_block u_Mark_Extract_Bits (.In1(elec_pos_scaled), // ufix18
.Out1(y) // ufix9
);
// <S18>/Data Type Conversion1
assign Data_Type_Conversion1_out1 = y;
// <S18>/Direct Lookup Table (n-D)
assign Direct_Lookup_Table_n_D_t1_re[0] = t1_re_0;
assign Direct_Lookup_Table_n_D_t1_re[1] = t1_re_1;
assign Direct_Lookup_Table_n_D_t1_re[2] = t1_re_2;
assign Direct_Lookup_Table_n_D_t1_re[3] = t1_re_3;
assign Direct_Lookup_Table_n_D_t1_re[4] = t1_re_4;
assign Direct_Lookup_Table_n_D_t1_re[5] = t1_re_5;
assign Direct_Lookup_Table_n_D_t1_re[6] = t1_re_6;
assign Direct_Lookup_Table_n_D_t1_re[7] = t1_re_7;
assign Direct_Lookup_Table_n_D_t1_re[8] = t1_re_8;
assign Direct_Lookup_Table_n_D_t1_re[9] = t1_re_9;
assign Direct_Lookup_Table_n_D_t1_re[10] = t1_re_10;
assign Direct_Lookup_Table_n_D_t1_re[11] = t1_re_11;
assign Direct_Lookup_Table_n_D_t1_re[12] = t1_re_12;
assign Direct_Lookup_Table_n_D_t1_re[13] = t1_re_13;
assign Direct_Lookup_Table_n_D_t1_re[14] = t1_re_14;
assign Direct_Lookup_Table_n_D_t1_re[15] = t1_re_15;
assign Direct_Lookup_Table_n_D_t1_re[16] = t1_re_16;
assign Direct_Lookup_Table_n_D_t1_re[17] = t1_re_17;
assign Direct_Lookup_Table_n_D_t1_re[18] = t1_re_18;
assign Direct_Lookup_Table_n_D_t1_re[19] = t1_re_19;
assign Direct_Lookup_Table_n_D_t1_re[20] = t1_re_20;
assign Direct_Lookup_Table_n_D_t1_re[21] = t1_re_21;
assign Direct_Lookup_Table_n_D_t1_re[22] = t1_re_22;
assign Direct_Lookup_Table_n_D_t1_re[23] = t1_re_23;
assign Direct_Lookup_Table_n_D_t1_re[24] = t1_re_24;
assign Direct_Lookup_Table_n_D_t1_re[25] = t1_re_25;
assign Direct_Lookup_Table_n_D_t1_re[26] = t1_re_26;
assign Direct_Lookup_Table_n_D_t1_re[27] = t1_re_27;
assign Direct_Lookup_Table_n_D_t1_re[28] = t1_re_28;
assign Direct_Lookup_Table_n_D_t1_re[29] = t1_re_29;
assign Direct_Lookup_Table_n_D_t1_re[30] = t1_re_30;
assign Direct_Lookup_Table_n_D_t1_re[31] = t1_re_31;
assign Direct_Lookup_Table_n_D_t1_re[32] = t1_re_32;
assign Direct_Lookup_Table_n_D_t1_re[33] = t1_re_33;
assign Direct_Lookup_Table_n_D_t1_re[34] = t1_re_34;
assign Direct_Lookup_Table_n_D_t1_re[35] = t1_re_35;
assign Direct_Lookup_Table_n_D_t1_re[36] = t1_re_36;
assign Direct_Lookup_Table_n_D_t1_re[37] = t1_re_37;
assign Direct_Lookup_Table_n_D_t1_re[38] = t1_re_38;
assign Direct_Lookup_Table_n_D_t1_re[39] = t1_re_39;
assign Direct_Lookup_Table_n_D_t1_re[40] = t1_re_40;
assign Direct_Lookup_Table_n_D_t1_re[41] = t1_re_41;
assign Direct_Lookup_Table_n_D_t1_re[42] = t1_re_42;
assign Direct_Lookup_Table_n_D_t1_re[43] = t1_re_43;
assign Direct_Lookup_Table_n_D_t1_re[44] = t1_re_44;
assign Direct_Lookup_Table_n_D_t1_re[45] = t1_re_45;
assign Direct_Lookup_Table_n_D_t1_re[46] = t1_re_46;
assign Direct_Lookup_Table_n_D_t1_re[47] = t1_re_47;
assign Direct_Lookup_Table_n_D_t1_re[48] = t1_re_48;
assign Direct_Lookup_Table_n_D_t1_re[49] = t1_re_49;
assign Direct_Lookup_Table_n_D_t1_re[50] = t1_re_50;
assign Direct_Lookup_Table_n_D_t1_re[51] = t1_re_51;
assign Direct_Lookup_Table_n_D_t1_re[52] = t1_re_52;
assign Direct_Lookup_Table_n_D_t1_re[53] = t1_re_53;
assign Direct_Lookup_Table_n_D_t1_re[54] = t1_re_54;
assign Direct_Lookup_Table_n_D_t1_re[55] = t1_re_55;
assign Direct_Lookup_Table_n_D_t1_re[56] = t1_re_56;
assign Direct_Lookup_Table_n_D_t1_re[57] = t1_re_57;
assign Direct_Lookup_Table_n_D_t1_re[58] = t1_re_58;
assign Direct_Lookup_Table_n_D_t1_re[59] = t1_re_59;
assign Direct_Lookup_Table_n_D_t1_re[60] = t1_re_60;
assign Direct_Lookup_Table_n_D_t1_re[61] = t1_re_61;
assign Direct_Lookup_Table_n_D_t1_re[62] = t1_re_62;
assign Direct_Lookup_Table_n_D_t1_re[63] = t1_re_63;
assign Direct_Lookup_Table_n_D_t1_re[64] = t1_re_64;
assign Direct_Lookup_Table_n_D_t1_re[65] = t1_re_65;
assign Direct_Lookup_Table_n_D_t1_re[66] = t1_re_66;
assign Direct_Lookup_Table_n_D_t1_re[67] = t1_re_67;
assign Direct_Lookup_Table_n_D_t1_re[68] = t1_re_68;
assign Direct_Lookup_Table_n_D_t1_re[69] = t1_re_69;
assign Direct_Lookup_Table_n_D_t1_re[70] = t1_re_70;
assign Direct_Lookup_Table_n_D_t1_re[71] = t1_re_71;
assign Direct_Lookup_Table_n_D_t1_re[72] = t1_re_72;
assign Direct_Lookup_Table_n_D_t1_re[73] = t1_re_73;
assign Direct_Lookup_Table_n_D_t1_re[74] = t1_re_74;
assign Direct_Lookup_Table_n_D_t1_re[75] = t1_re_75;
assign Direct_Lookup_Table_n_D_t1_re[76] = t1_re_76;
assign Direct_Lookup_Table_n_D_t1_re[77] = t1_re_77;
assign Direct_Lookup_Table_n_D_t1_re[78] = t1_re_78;
assign Direct_Lookup_Table_n_D_t1_re[79] = t1_re_79;
assign Direct_Lookup_Table_n_D_t1_re[80] = t1_re_80;
assign Direct_Lookup_Table_n_D_t1_re[81] = t1_re_81;
assign Direct_Lookup_Table_n_D_t1_re[82] = t1_re_82;
assign Direct_Lookup_Table_n_D_t1_re[83] = t1_re_83;
assign Direct_Lookup_Table_n_D_t1_re[84] = t1_re_84;
assign Direct_Lookup_Table_n_D_t1_re[85] = t1_re_85;
assign Direct_Lookup_Table_n_D_t1_re[86] = t1_re_86;
assign Direct_Lookup_Table_n_D_t1_re[87] = t1_re_87;
assign Direct_Lookup_Table_n_D_t1_re[88] = t1_re_88;
assign Direct_Lookup_Table_n_D_t1_re[89] = t1_re_89;
assign Direct_Lookup_Table_n_D_t1_re[90] = t1_re_90;
assign Direct_Lookup_Table_n_D_t1_re[91] = t1_re_91;
assign Direct_Lookup_Table_n_D_t1_re[92] = t1_re_92;
assign Direct_Lookup_Table_n_D_t1_re[93] = t1_re_93;
assign Direct_Lookup_Table_n_D_t1_re[94] = t1_re_94;
assign Direct_Lookup_Table_n_D_t1_re[95] = t1_re_95;
assign Direct_Lookup_Table_n_D_t1_re[96] = t1_re_96;
assign Direct_Lookup_Table_n_D_t1_re[97] = t1_re_97;
assign Direct_Lookup_Table_n_D_t1_re[98] = t1_re_98;
assign Direct_Lookup_Table_n_D_t1_re[99] = t1_re_99;
assign Direct_Lookup_Table_n_D_t1_re[100] = t1_re_100;
assign Direct_Lookup_Table_n_D_t1_re[101] = t1_re_101;
assign Direct_Lookup_Table_n_D_t1_re[102] = t1_re_102;
assign Direct_Lookup_Table_n_D_t1_re[103] = t1_re_103;
assign Direct_Lookup_Table_n_D_t1_re[104] = t1_re_104;
assign Direct_Lookup_Table_n_D_t1_re[105] = t1_re_105;
assign Direct_Lookup_Table_n_D_t1_re[106] = t1_re_106;
assign Direct_Lookup_Table_n_D_t1_re[107] = t1_re_107;
assign Direct_Lookup_Table_n_D_t1_re[108] = t1_re_108;
assign Direct_Lookup_Table_n_D_t1_re[109] = t1_re_109;
assign Direct_Lookup_Table_n_D_t1_re[110] = t1_re_110;
assign Direct_Lookup_Table_n_D_t1_re[111] = t1_re_111;
assign Direct_Lookup_Table_n_D_t1_re[112] = t1_re_112;
assign Direct_Lookup_Table_n_D_t1_re[113] = t1_re_113;
assign Direct_Lookup_Table_n_D_t1_re[114] = t1_re_114;
assign Direct_Lookup_Table_n_D_t1_re[115] = t1_re_115;
assign Direct_Lookup_Table_n_D_t1_re[116] = t1_re_116;
assign Direct_Lookup_Table_n_D_t1_re[117] = t1_re_117;
assign Direct_Lookup_Table_n_D_t1_re[118] = t1_re_118;
assign Direct_Lookup_Table_n_D_t1_re[119] = t1_re_119;
assign Direct_Lookup_Table_n_D_t1_re[120] = t1_re_120;
assign Direct_Lookup_Table_n_D_t1_re[121] = t1_re_121;
assign Direct_Lookup_Table_n_D_t1_re[122] = t1_re_122;
assign Direct_Lookup_Table_n_D_t1_re[123] = t1_re_123;
assign Direct_Lookup_Table_n_D_t1_re[124] = t1_re_124;
assign Direct_Lookup_Table_n_D_t1_re[125] = t1_re_125;
assign Direct_Lookup_Table_n_D_t1_re[126] = t1_re_126;
assign Direct_Lookup_Table_n_D_t1_re[127] = t1_re_127;
assign Direct_Lookup_Table_n_D_t1_re[128] = t1_re_128;
assign Direct_Lookup_Table_n_D_t1_re[129] = t1_re_129;
assign Direct_Lookup_Table_n_D_t1_re[130] = t1_re_130;
assign Direct_Lookup_Table_n_D_t1_re[131] = t1_re_131;
assign Direct_Lookup_Table_n_D_t1_re[132] = t1_re_132;
assign Direct_Lookup_Table_n_D_t1_re[133] = t1_re_133;
assign Direct_Lookup_Table_n_D_t1_re[134] = t1_re_134;
assign Direct_Lookup_Table_n_D_t1_re[135] = t1_re_135;
assign Direct_Lookup_Table_n_D_t1_re[136] = t1_re_136;
assign Direct_Lookup_Table_n_D_t1_re[137] = t1_re_137;
assign Direct_Lookup_Table_n_D_t1_re[138] = t1_re_138;
assign Direct_Lookup_Table_n_D_t1_re[139] = t1_re_139;
assign Direct_Lookup_Table_n_D_t1_re[140] = t1_re_140;
assign Direct_Lookup_Table_n_D_t1_re[141] = t1_re_141;
assign Direct_Lookup_Table_n_D_t1_re[142] = t1_re_142;
assign Direct_Lookup_Table_n_D_t1_re[143] = t1_re_143;
assign Direct_Lookup_Table_n_D_t1_re[144] = t1_re_144;
assign Direct_Lookup_Table_n_D_t1_re[145] = t1_re_145;
assign Direct_Lookup_Table_n_D_t1_re[146] = t1_re_146;
assign Direct_Lookup_Table_n_D_t1_re[147] = t1_re_147;
assign Direct_Lookup_Table_n_D_t1_re[148] = t1_re_148;
assign Direct_Lookup_Table_n_D_t1_re[149] = t1_re_149;
assign Direct_Lookup_Table_n_D_t1_re[150] = t1_re_150;
assign Direct_Lookup_Table_n_D_t1_re[151] = t1_re_151;
assign Direct_Lookup_Table_n_D_t1_re[152] = t1_re_152;
assign Direct_Lookup_Table_n_D_t1_re[153] = t1_re_153;
assign Direct_Lookup_Table_n_D_t1_re[154] = t1_re_154;
assign Direct_Lookup_Table_n_D_t1_re[155] = t1_re_155;
assign Direct_Lookup_Table_n_D_t1_re[156] = t1_re_156;
assign Direct_Lookup_Table_n_D_t1_re[157] = t1_re_157;
assign Direct_Lookup_Table_n_D_t1_re[158] = t1_re_158;
assign Direct_Lookup_Table_n_D_t1_re[159] = t1_re_159;
assign Direct_Lookup_Table_n_D_t1_re[160] = t1_re_160;
assign Direct_Lookup_Table_n_D_t1_re[161] = t1_re_161;
assign Direct_Lookup_Table_n_D_t1_re[162] = t1_re_162;
assign Direct_Lookup_Table_n_D_t1_re[163] = t1_re_163;
assign Direct_Lookup_Table_n_D_t1_re[164] = t1_re_164;
assign Direct_Lookup_Table_n_D_t1_re[165] = t1_re_165;
assign Direct_Lookup_Table_n_D_t1_re[166] = t1_re_166;
assign Direct_Lookup_Table_n_D_t1_re[167] = t1_re_167;
assign Direct_Lookup_Table_n_D_t1_re[168] = t1_re_168;
assign Direct_Lookup_Table_n_D_t1_re[169] = t1_re_169;
assign Direct_Lookup_Table_n_D_t1_re[170] = t1_re_170;
assign Direct_Lookup_Table_n_D_t1_re[171] = t1_re_171;
assign Direct_Lookup_Table_n_D_t1_re[172] = t1_re_172;
assign Direct_Lookup_Table_n_D_t1_re[173] = t1_re_173;
assign Direct_Lookup_Table_n_D_t1_re[174] = t1_re_174;
assign Direct_Lookup_Table_n_D_t1_re[175] = t1_re_175;
assign Direct_Lookup_Table_n_D_t1_re[176] = t1_re_176;
assign Direct_Lookup_Table_n_D_t1_re[177] = t1_re_177;
assign Direct_Lookup_Table_n_D_t1_re[178] = t1_re_178;
assign Direct_Lookup_Table_n_D_t1_re[179] = t1_re_179;
assign Direct_Lookup_Table_n_D_t1_re[180] = t1_re_180;
assign Direct_Lookup_Table_n_D_t1_re[181] = t1_re_181;
assign Direct_Lookup_Table_n_D_t1_re[182] = t1_re_182;
assign Direct_Lookup_Table_n_D_t1_re[183] = t1_re_183;
assign Direct_Lookup_Table_n_D_t1_re[184] = t1_re_184;
assign Direct_Lookup_Table_n_D_t1_re[185] = t1_re_185;
assign Direct_Lookup_Table_n_D_t1_re[186] = t1_re_186;
assign Direct_Lookup_Table_n_D_t1_re[187] = t1_re_187;
assign Direct_Lookup_Table_n_D_t1_re[188] = t1_re_188;
assign Direct_Lookup_Table_n_D_t1_re[189] = t1_re_189;
assign Direct_Lookup_Table_n_D_t1_re[190] = t1_re_190;
assign Direct_Lookup_Table_n_D_t1_re[191] = t1_re_191;
assign Direct_Lookup_Table_n_D_t1_re[192] = t1_re_192;
assign Direct_Lookup_Table_n_D_t1_re[193] = t1_re_193;
assign Direct_Lookup_Table_n_D_t1_re[194] = t1_re_194;
assign Direct_Lookup_Table_n_D_t1_re[195] = t1_re_195;
assign Direct_Lookup_Table_n_D_t1_re[196] = t1_re_196;
assign Direct_Lookup_Table_n_D_t1_re[197] = t1_re_197;
assign Direct_Lookup_Table_n_D_t1_re[198] = t1_re_198;
assign Direct_Lookup_Table_n_D_t1_re[199] = t1_re_199;
assign Direct_Lookup_Table_n_D_t1_re[200] = t1_re_200;
assign Direct_Lookup_Table_n_D_t1_re[201] = t1_re_201;
assign Direct_Lookup_Table_n_D_t1_re[202] = t1_re_202;
assign Direct_Lookup_Table_n_D_t1_re[203] = t1_re_203;
assign Direct_Lookup_Table_n_D_t1_re[204] = t1_re_204;
assign Direct_Lookup_Table_n_D_t1_re[205] = t1_re_205;
assign Direct_Lookup_Table_n_D_t1_re[206] = t1_re_206;
assign Direct_Lookup_Table_n_D_t1_re[207] = t1_re_207;
assign Direct_Lookup_Table_n_D_t1_re[208] = t1_re_208;
assign Direct_Lookup_Table_n_D_t1_re[209] = t1_re_209;
assign Direct_Lookup_Table_n_D_t1_re[210] = t1_re_210;
assign Direct_Lookup_Table_n_D_t1_re[211] = t1_re_211;
assign Direct_Lookup_Table_n_D_t1_re[212] = t1_re_212;
assign Direct_Lookup_Table_n_D_t1_re[213] = t1_re_213;
assign Direct_Lookup_Table_n_D_t1_re[214] = t1_re_214;
assign Direct_Lookup_Table_n_D_t1_re[215] = t1_re_215;
assign Direct_Lookup_Table_n_D_t1_re[216] = t1_re_216;
assign Direct_Lookup_Table_n_D_t1_re[217] = t1_re_217;
assign Direct_Lookup_Table_n_D_t1_re[218] = t1_re_218;
assign Direct_Lookup_Table_n_D_t1_re[219] = t1_re_219;
assign Direct_Lookup_Table_n_D_t1_re[220] = t1_re_220;
assign Direct_Lookup_Table_n_D_t1_re[221] = t1_re_221;
assign Direct_Lookup_Table_n_D_t1_re[222] = t1_re_222;
assign Direct_Lookup_Table_n_D_t1_re[223] = t1_re_223;
assign Direct_Lookup_Table_n_D_t1_re[224] = t1_re_224;
assign Direct_Lookup_Table_n_D_t1_re[225] = t1_re_225;
assign Direct_Lookup_Table_n_D_t1_re[226] = t1_re_226;
assign Direct_Lookup_Table_n_D_t1_re[227] = t1_re_227;
assign Direct_Lookup_Table_n_D_t1_re[228] = t1_re_228;
assign Direct_Lookup_Table_n_D_t1_re[229] = t1_re_229;
assign Direct_Lookup_Table_n_D_t1_re[230] = t1_re_230;
assign Direct_Lookup_Table_n_D_t1_re[231] = t1_re_231;
assign Direct_Lookup_Table_n_D_t1_re[232] = t1_re_232;
assign Direct_Lookup_Table_n_D_t1_re[233] = t1_re_233;
assign Direct_Lookup_Table_n_D_t1_re[234] = t1_re_234;
assign Direct_Lookup_Table_n_D_t1_re[235] = t1_re_235;
assign Direct_Lookup_Table_n_D_t1_re[236] = t1_re_236;
assign Direct_Lookup_Table_n_D_t1_re[237] = t1_re_237;
assign Direct_Lookup_Table_n_D_t1_re[238] = t1_re_238;
assign Direct_Lookup_Table_n_D_t1_re[239] = t1_re_239;
assign Direct_Lookup_Table_n_D_t1_re[240] = t1_re_240;
assign Direct_Lookup_Table_n_D_t1_re[241] = t1_re_241;
assign Direct_Lookup_Table_n_D_t1_re[242] = t1_re_242;
assign Direct_Lookup_Table_n_D_t1_re[243] = t1_re_243;
assign Direct_Lookup_Table_n_D_t1_re[244] = t1_re_244;
assign Direct_Lookup_Table_n_D_t1_re[245] = t1_re_245;
assign Direct_Lookup_Table_n_D_t1_re[246] = t1_re_246;
assign Direct_Lookup_Table_n_D_t1_re[247] = t1_re_247;
assign Direct_Lookup_Table_n_D_t1_re[248] = t1_re_248;
assign Direct_Lookup_Table_n_D_t1_re[249] = t1_re_249;
assign Direct_Lookup_Table_n_D_t1_re[250] = t1_re_250;
assign Direct_Lookup_Table_n_D_t1_re[251] = t1_re_251;
assign Direct_Lookup_Table_n_D_t1_re[252] = t1_re_252;
assign Direct_Lookup_Table_n_D_t1_re[253] = t1_re_253;
assign Direct_Lookup_Table_n_D_t1_re[254] = t1_re_254;
assign Direct_Lookup_Table_n_D_t1_re[255] = t1_re_255;
assign Direct_Lookup_Table_n_D_t1_re[256] = t1_re_256;
assign Direct_Lookup_Table_n_D_t1_re[257] = t1_re_257;
assign Direct_Lookup_Table_n_D_t1_re[258] = t1_re_258;
assign Direct_Lookup_Table_n_D_t1_re[259] = t1_re_259;
assign Direct_Lookup_Table_n_D_t1_re[260] = t1_re_260;
assign Direct_Lookup_Table_n_D_t1_re[261] = t1_re_261;
assign Direct_Lookup_Table_n_D_t1_re[262] = t1_re_262;
assign Direct_Lookup_Table_n_D_t1_re[263] = t1_re_263;
assign Direct_Lookup_Table_n_D_t1_re[264] = t1_re_264;
assign Direct_Lookup_Table_n_D_t1_re[265] = t1_re_265;
assign Direct_Lookup_Table_n_D_t1_re[266] = t1_re_266;
assign Direct_Lookup_Table_n_D_t1_re[267] = t1_re_267;
assign Direct_Lookup_Table_n_D_t1_re[268] = t1_re_268;
assign Direct_Lookup_Table_n_D_t1_re[269] = t1_re_269;
assign Direct_Lookup_Table_n_D_t1_re[270] = t1_re_270;
assign Direct_Lookup_Table_n_D_t1_re[271] = t1_re_271;
assign Direct_Lookup_Table_n_D_t1_re[272] = t1_re_272;
assign Direct_Lookup_Table_n_D_t1_re[273] = t1_re_273;
assign Direct_Lookup_Table_n_D_t1_re[274] = t1_re_274;
assign Direct_Lookup_Table_n_D_t1_re[275] = t1_re_275;
assign Direct_Lookup_Table_n_D_t1_re[276] = t1_re_276;
assign Direct_Lookup_Table_n_D_t1_re[277] = t1_re_277;
assign Direct_Lookup_Table_n_D_t1_re[278] = t1_re_278;
assign Direct_Lookup_Table_n_D_t1_re[279] = t1_re_279;
assign Direct_Lookup_Table_n_D_t1_re[280] = t1_re_280;
assign Direct_Lookup_Table_n_D_t1_re[281] = t1_re_281;
assign Direct_Lookup_Table_n_D_t1_re[282] = t1_re_282;
assign Direct_Lookup_Table_n_D_t1_re[283] = t1_re_283;
assign Direct_Lookup_Table_n_D_t1_re[284] = t1_re_284;
assign Direct_Lookup_Table_n_D_t1_re[285] = t1_re_285;
assign Direct_Lookup_Table_n_D_t1_re[286] = t1_re_286;
assign Direct_Lookup_Table_n_D_t1_re[287] = t1_re_287;
assign Direct_Lookup_Table_n_D_t1_re[288] = t1_re_288;
assign Direct_Lookup_Table_n_D_t1_re[289] = t1_re_289;
assign Direct_Lookup_Table_n_D_t1_re[290] = t1_re_290;
assign Direct_Lookup_Table_n_D_t1_re[291] = t1_re_291;
assign Direct_Lookup_Table_n_D_t1_re[292] = t1_re_292;
assign Direct_Lookup_Table_n_D_t1_re[293] = t1_re_293;
assign Direct_Lookup_Table_n_D_t1_re[294] = t1_re_294;
assign Direct_Lookup_Table_n_D_t1_re[295] = t1_re_295;
assign Direct_Lookup_Table_n_D_t1_re[296] = t1_re_296;
assign Direct_Lookup_Table_n_D_t1_re[297] = t1_re_297;
assign Direct_Lookup_Table_n_D_t1_re[298] = t1_re_298;
assign Direct_Lookup_Table_n_D_t1_re[299] = t1_re_299;
assign Direct_Lookup_Table_n_D_t1_re[300] = t1_re_300;
assign Direct_Lookup_Table_n_D_t1_re[301] = t1_re_301;
assign Direct_Lookup_Table_n_D_t1_re[302] = t1_re_302;
assign Direct_Lookup_Table_n_D_t1_re[303] = t1_re_303;
assign Direct_Lookup_Table_n_D_t1_re[304] = t1_re_304;
assign Direct_Lookup_Table_n_D_t1_re[305] = t1_re_305;
assign Direct_Lookup_Table_n_D_t1_re[306] = t1_re_306;
assign Direct_Lookup_Table_n_D_t1_re[307] = t1_re_307;
assign Direct_Lookup_Table_n_D_t1_re[308] = t1_re_308;
assign Direct_Lookup_Table_n_D_t1_re[309] = t1_re_309;
assign Direct_Lookup_Table_n_D_t1_re[310] = t1_re_310;
assign Direct_Lookup_Table_n_D_t1_re[311] = t1_re_311;
assign Direct_Lookup_Table_n_D_t1_re[312] = t1_re_312;
assign Direct_Lookup_Table_n_D_t1_re[313] = t1_re_313;
assign Direct_Lookup_Table_n_D_t1_re[314] = t1_re_314;
assign Direct_Lookup_Table_n_D_t1_re[315] = t1_re_315;
assign Direct_Lookup_Table_n_D_t1_re[316] = t1_re_316;
assign Direct_Lookup_Table_n_D_t1_re[317] = t1_re_317;
assign Direct_Lookup_Table_n_D_t1_re[318] = t1_re_318;
assign Direct_Lookup_Table_n_D_t1_re[319] = t1_re_319;
assign Direct_Lookup_Table_n_D_t1_re[320] = t1_re_320;
assign Direct_Lookup_Table_n_D_t1_re[321] = t1_re_321;
assign Direct_Lookup_Table_n_D_t1_re[322] = t1_re_322;
assign Direct_Lookup_Table_n_D_t1_re[323] = t1_re_323;
assign Direct_Lookup_Table_n_D_t1_re[324] = t1_re_324;
assign Direct_Lookup_Table_n_D_t1_re[325] = t1_re_325;
assign Direct_Lookup_Table_n_D_t1_re[326] = t1_re_326;
assign Direct_Lookup_Table_n_D_t1_re[327] = t1_re_327;
assign Direct_Lookup_Table_n_D_t1_re[328] = t1_re_328;
assign Direct_Lookup_Table_n_D_t1_re[329] = t1_re_329;
assign Direct_Lookup_Table_n_D_t1_re[330] = t1_re_330;
assign Direct_Lookup_Table_n_D_t1_re[331] = t1_re_331;
assign Direct_Lookup_Table_n_D_t1_re[332] = t1_re_332;
assign Direct_Lookup_Table_n_D_t1_re[333] = t1_re_333;
assign Direct_Lookup_Table_n_D_t1_re[334] = t1_re_334;
assign Direct_Lookup_Table_n_D_t1_re[335] = t1_re_335;
assign Direct_Lookup_Table_n_D_t1_re[336] = t1_re_336;
assign Direct_Lookup_Table_n_D_t1_re[337] = t1_re_337;
assign Direct_Lookup_Table_n_D_t1_re[338] = t1_re_338;
assign Direct_Lookup_Table_n_D_t1_re[339] = t1_re_339;
assign Direct_Lookup_Table_n_D_t1_re[340] = t1_re_340;
assign Direct_Lookup_Table_n_D_t1_re[341] = t1_re_341;
assign Direct_Lookup_Table_n_D_t1_re[342] = t1_re_342;
assign Direct_Lookup_Table_n_D_t1_re[343] = t1_re_343;
assign Direct_Lookup_Table_n_D_t1_re[344] = t1_re_344;
assign Direct_Lookup_Table_n_D_t1_re[345] = t1_re_345;
assign Direct_Lookup_Table_n_D_t1_re[346] = t1_re_346;
assign Direct_Lookup_Table_n_D_t1_re[347] = t1_re_347;
assign Direct_Lookup_Table_n_D_t1_re[348] = t1_re_348;
assign Direct_Lookup_Table_n_D_t1_re[349] = t1_re_349;
assign Direct_Lookup_Table_n_D_t1_re[350] = t1_re_350;
assign Direct_Lookup_Table_n_D_t1_re[351] = t1_re_351;
assign Direct_Lookup_Table_n_D_t1_re[352] = t1_re_352;
assign Direct_Lookup_Table_n_D_t1_re[353] = t1_re_353;
assign Direct_Lookup_Table_n_D_t1_re[354] = t1_re_354;
assign Direct_Lookup_Table_n_D_t1_re[355] = t1_re_355;
assign Direct_Lookup_Table_n_D_t1_re[356] = t1_re_356;
assign Direct_Lookup_Table_n_D_t1_re[357] = t1_re_357;
assign Direct_Lookup_Table_n_D_t1_re[358] = t1_re_358;
assign Direct_Lookup_Table_n_D_t1_re[359] = t1_re_359;
assign Direct_Lookup_Table_n_D_t1_re[360] = t1_re_360;
assign Direct_Lookup_Table_n_D_t1_re[361] = t1_re_361;
assign Direct_Lookup_Table_n_D_t1_re[362] = t1_re_362;
assign Direct_Lookup_Table_n_D_t1_re[363] = t1_re_363;
assign Direct_Lookup_Table_n_D_t1_re[364] = t1_re_364;
assign Direct_Lookup_Table_n_D_t1_re[365] = t1_re_365;
assign Direct_Lookup_Table_n_D_t1_re[366] = t1_re_366;
assign Direct_Lookup_Table_n_D_t1_re[367] = t1_re_367;
assign Direct_Lookup_Table_n_D_t1_re[368] = t1_re_368;
assign Direct_Lookup_Table_n_D_t1_re[369] = t1_re_369;
assign Direct_Lookup_Table_n_D_t1_re[370] = t1_re_370;
assign Direct_Lookup_Table_n_D_t1_re[371] = t1_re_371;
assign Direct_Lookup_Table_n_D_t1_re[372] = t1_re_372;
assign Direct_Lookup_Table_n_D_t1_re[373] = t1_re_373;
assign Direct_Lookup_Table_n_D_t1_re[374] = t1_re_374;
assign Direct_Lookup_Table_n_D_t1_re[375] = t1_re_375;
assign Direct_Lookup_Table_n_D_t1_re[376] = t1_re_376;
assign Direct_Lookup_Table_n_D_t1_re[377] = t1_re_377;
assign Direct_Lookup_Table_n_D_t1_re[378] = t1_re_378;
assign Direct_Lookup_Table_n_D_t1_re[379] = t1_re_379;
assign Direct_Lookup_Table_n_D_t1_re[380] = t1_re_380;
assign Direct_Lookup_Table_n_D_t1_re[381] = t1_re_381;
assign Direct_Lookup_Table_n_D_t1_re[382] = t1_re_382;
assign Direct_Lookup_Table_n_D_t1_re[383] = t1_re_383;
assign Direct_Lookup_Table_n_D_t1_re[384] = t1_re_384;
assign Direct_Lookup_Table_n_D_t1_re[385] = t1_re_385;
assign Direct_Lookup_Table_n_D_t1_re[386] = t1_re_386;
assign Direct_Lookup_Table_n_D_t1_re[387] = t1_re_387;
assign Direct_Lookup_Table_n_D_t1_re[388] = t1_re_388;
assign Direct_Lookup_Table_n_D_t1_re[389] = t1_re_389;
assign Direct_Lookup_Table_n_D_t1_re[390] = t1_re_390;
assign Direct_Lookup_Table_n_D_t1_re[391] = t1_re_391;
assign Direct_Lookup_Table_n_D_t1_re[392] = t1_re_392;
assign Direct_Lookup_Table_n_D_t1_re[393] = t1_re_393;
assign Direct_Lookup_Table_n_D_t1_re[394] = t1_re_394;
assign Direct_Lookup_Table_n_D_t1_re[395] = t1_re_395;
assign Direct_Lookup_Table_n_D_t1_re[396] = t1_re_396;
assign Direct_Lookup_Table_n_D_t1_re[397] = t1_re_397;
assign Direct_Lookup_Table_n_D_t1_re[398] = t1_re_398;
assign Direct_Lookup_Table_n_D_t1_re[399] = t1_re_399;
assign Direct_Lookup_Table_n_D_t1_re[400] = t1_re_400;
assign Direct_Lookup_Table_n_D_t1_re[401] = t1_re_401;
assign Direct_Lookup_Table_n_D_t1_re[402] = t1_re_402;
assign Direct_Lookup_Table_n_D_t1_re[403] = t1_re_403;
assign Direct_Lookup_Table_n_D_t1_re[404] = t1_re_404;
assign Direct_Lookup_Table_n_D_t1_re[405] = t1_re_405;
assign Direct_Lookup_Table_n_D_t1_re[406] = t1_re_406;
assign Direct_Lookup_Table_n_D_t1_re[407] = t1_re_407;
assign Direct_Lookup_Table_n_D_t1_re[408] = t1_re_408;
assign Direct_Lookup_Table_n_D_t1_re[409] = t1_re_409;
assign Direct_Lookup_Table_n_D_t1_re[410] = t1_re_410;
assign Direct_Lookup_Table_n_D_t1_re[411] = t1_re_411;
assign Direct_Lookup_Table_n_D_t1_re[412] = t1_re_412;
assign Direct_Lookup_Table_n_D_t1_re[413] = t1_re_413;
assign Direct_Lookup_Table_n_D_t1_re[414] = t1_re_414;
assign Direct_Lookup_Table_n_D_t1_re[415] = t1_re_415;
assign Direct_Lookup_Table_n_D_t1_re[416] = t1_re_416;
assign Direct_Lookup_Table_n_D_t1_re[417] = t1_re_417;
assign Direct_Lookup_Table_n_D_t1_re[418] = t1_re_418;
assign Direct_Lookup_Table_n_D_t1_re[419] = t1_re_419;
assign Direct_Lookup_Table_n_D_t1_re[420] = t1_re_420;
assign Direct_Lookup_Table_n_D_t1_re[421] = t1_re_421;
assign Direct_Lookup_Table_n_D_t1_re[422] = t1_re_422;
assign Direct_Lookup_Table_n_D_t1_re[423] = t1_re_423;
assign Direct_Lookup_Table_n_D_t1_re[424] = t1_re_424;
assign Direct_Lookup_Table_n_D_t1_re[425] = t1_re_425;
assign Direct_Lookup_Table_n_D_t1_re[426] = t1_re_426;
assign Direct_Lookup_Table_n_D_t1_re[427] = t1_re_427;
assign Direct_Lookup_Table_n_D_t1_re[428] = t1_re_428;
assign Direct_Lookup_Table_n_D_t1_re[429] = t1_re_429;
assign Direct_Lookup_Table_n_D_t1_re[430] = t1_re_430;
assign Direct_Lookup_Table_n_D_t1_re[431] = t1_re_431;
assign Direct_Lookup_Table_n_D_t1_re[432] = t1_re_432;
assign Direct_Lookup_Table_n_D_t1_re[433] = t1_re_433;
assign Direct_Lookup_Table_n_D_t1_re[434] = t1_re_434;
assign Direct_Lookup_Table_n_D_t1_re[435] = t1_re_435;
assign Direct_Lookup_Table_n_D_t1_re[436] = t1_re_436;
assign Direct_Lookup_Table_n_D_t1_re[437] = t1_re_437;
assign Direct_Lookup_Table_n_D_t1_re[438] = t1_re_438;
assign Direct_Lookup_Table_n_D_t1_re[439] = t1_re_439;
assign Direct_Lookup_Table_n_D_t1_re[440] = t1_re_440;
assign Direct_Lookup_Table_n_D_t1_re[441] = t1_re_441;
assign Direct_Lookup_Table_n_D_t1_re[442] = t1_re_442;
assign Direct_Lookup_Table_n_D_t1_re[443] = t1_re_443;
assign Direct_Lookup_Table_n_D_t1_re[444] = t1_re_444;
assign Direct_Lookup_Table_n_D_t1_re[445] = t1_re_445;
assign Direct_Lookup_Table_n_D_t1_re[446] = t1_re_446;
assign Direct_Lookup_Table_n_D_t1_re[447] = t1_re_447;
assign Direct_Lookup_Table_n_D_t1_re[448] = t1_re_448;
assign Direct_Lookup_Table_n_D_t1_re[449] = t1_re_449;
assign Direct_Lookup_Table_n_D_t1_re[450] = t1_re_450;
assign Direct_Lookup_Table_n_D_t1_re[451] = t1_re_451;
assign Direct_Lookup_Table_n_D_t1_re[452] = t1_re_452;
assign Direct_Lookup_Table_n_D_t1_re[453] = t1_re_453;
assign Direct_Lookup_Table_n_D_t1_re[454] = t1_re_454;
assign Direct_Lookup_Table_n_D_t1_re[455] = t1_re_455;
assign Direct_Lookup_Table_n_D_t1_re[456] = t1_re_456;
assign Direct_Lookup_Table_n_D_t1_re[457] = t1_re_457;
assign Direct_Lookup_Table_n_D_t1_re[458] = t1_re_458;
assign Direct_Lookup_Table_n_D_t1_re[459] = t1_re_459;
assign Direct_Lookup_Table_n_D_t1_re[460] = t1_re_460;
assign Direct_Lookup_Table_n_D_t1_re[461] = t1_re_461;
assign Direct_Lookup_Table_n_D_t1_re[462] = t1_re_462;
assign Direct_Lookup_Table_n_D_t1_re[463] = t1_re_463;
assign Direct_Lookup_Table_n_D_t1_re[464] = t1_re_464;
assign Direct_Lookup_Table_n_D_t1_re[465] = t1_re_465;
assign Direct_Lookup_Table_n_D_t1_re[466] = t1_re_466;
assign Direct_Lookup_Table_n_D_t1_re[467] = t1_re_467;
assign Direct_Lookup_Table_n_D_t1_re[468] = t1_re_468;
assign Direct_Lookup_Table_n_D_t1_re[469] = t1_re_469;
assign Direct_Lookup_Table_n_D_t1_re[470] = t1_re_470;
assign Direct_Lookup_Table_n_D_t1_re[471] = t1_re_471;
assign Direct_Lookup_Table_n_D_t1_re[472] = t1_re_472;
assign Direct_Lookup_Table_n_D_t1_re[473] = t1_re_473;
assign Direct_Lookup_Table_n_D_t1_re[474] = t1_re_474;
assign Direct_Lookup_Table_n_D_t1_re[475] = t1_re_475;
assign Direct_Lookup_Table_n_D_t1_re[476] = t1_re_476;
assign Direct_Lookup_Table_n_D_t1_re[477] = t1_re_477;
assign Direct_Lookup_Table_n_D_t1_re[478] = t1_re_478;
assign Direct_Lookup_Table_n_D_t1_re[479] = t1_re_479;
assign Direct_Lookup_Table_n_D_t1_re[480] = t1_re_480;
assign Direct_Lookup_Table_n_D_t1_re[481] = t1_re_481;
assign Direct_Lookup_Table_n_D_t1_re[482] = t1_re_482;
assign Direct_Lookup_Table_n_D_t1_re[483] = t1_re_483;
assign Direct_Lookup_Table_n_D_t1_re[484] = t1_re_484;
assign Direct_Lookup_Table_n_D_t1_re[485] = t1_re_485;
assign Direct_Lookup_Table_n_D_t1_re[486] = t1_re_486;
assign Direct_Lookup_Table_n_D_t1_re[487] = t1_re_487;
assign Direct_Lookup_Table_n_D_t1_re[488] = t1_re_488;
assign Direct_Lookup_Table_n_D_t1_re[489] = t1_re_489;
assign Direct_Lookup_Table_n_D_t1_re[490] = t1_re_490;
assign Direct_Lookup_Table_n_D_t1_re[491] = t1_re_491;
assign Direct_Lookup_Table_n_D_t1_re[492] = t1_re_492;
assign Direct_Lookup_Table_n_D_t1_re[493] = t1_re_493;
assign Direct_Lookup_Table_n_D_t1_re[494] = t1_re_494;
assign Direct_Lookup_Table_n_D_t1_re[495] = t1_re_495;
assign Direct_Lookup_Table_n_D_t1_re[496] = t1_re_496;
assign Direct_Lookup_Table_n_D_t1_re[497] = t1_re_497;
assign Direct_Lookup_Table_n_D_t1_re[498] = t1_re_498;
assign Direct_Lookup_Table_n_D_t1_re[499] = t1_re_499;
assign Direct_Lookup_Table_n_D_t1_re[500] = t1_re_500;
assign Direct_Lookup_Table_n_D_t1_re[501] = t1_re_501;
assign Direct_Lookup_Table_n_D_t1_re[502] = t1_re_502;
assign Direct_Lookup_Table_n_D_t1_re[503] = t1_re_503;
assign Direct_Lookup_Table_n_D_t1_re[504] = t1_re_504;
assign Direct_Lookup_Table_n_D_t1_re[505] = t1_re_505;
assign Direct_Lookup_Table_n_D_t1_re[506] = t1_re_506;
assign Direct_Lookup_Table_n_D_t1_re[507] = t1_re_507;
assign Direct_Lookup_Table_n_D_t1_re[508] = t1_re_508;
assign Direct_Lookup_Table_n_D_t1_re[509] = t1_re_509;
assign Direct_Lookup_Table_n_D_t1_re[510] = t1_re_510;
assign Direct_Lookup_Table_n_D_t1_re[511] = t1_re_511;
assign Direct_Lookup_Table_n_D_t1_im[0] = t1_im_0;
assign Direct_Lookup_Table_n_D_t1_im[1] = t1_im_1;
assign Direct_Lookup_Table_n_D_t1_im[2] = t1_im_2;
assign Direct_Lookup_Table_n_D_t1_im[3] = t1_im_3;
assign Direct_Lookup_Table_n_D_t1_im[4] = t1_im_4;
assign Direct_Lookup_Table_n_D_t1_im[5] = t1_im_5;
assign Direct_Lookup_Table_n_D_t1_im[6] = t1_im_6;
assign Direct_Lookup_Table_n_D_t1_im[7] = t1_im_7;
assign Direct_Lookup_Table_n_D_t1_im[8] = t1_im_8;
assign Direct_Lookup_Table_n_D_t1_im[9] = t1_im_9;
assign Direct_Lookup_Table_n_D_t1_im[10] = t1_im_10;
assign Direct_Lookup_Table_n_D_t1_im[11] = t1_im_11;
assign Direct_Lookup_Table_n_D_t1_im[12] = t1_im_12;
assign Direct_Lookup_Table_n_D_t1_im[13] = t1_im_13;
assign Direct_Lookup_Table_n_D_t1_im[14] = t1_im_14;
assign Direct_Lookup_Table_n_D_t1_im[15] = t1_im_15;
assign Direct_Lookup_Table_n_D_t1_im[16] = t1_im_16;
assign Direct_Lookup_Table_n_D_t1_im[17] = t1_im_17;
assign Direct_Lookup_Table_n_D_t1_im[18] = t1_im_18;
assign Direct_Lookup_Table_n_D_t1_im[19] = t1_im_19;
assign Direct_Lookup_Table_n_D_t1_im[20] = t1_im_20;
assign Direct_Lookup_Table_n_D_t1_im[21] = t1_im_21;
assign Direct_Lookup_Table_n_D_t1_im[22] = t1_im_22;
assign Direct_Lookup_Table_n_D_t1_im[23] = t1_im_23;
assign Direct_Lookup_Table_n_D_t1_im[24] = t1_im_24;
assign Direct_Lookup_Table_n_D_t1_im[25] = t1_im_25;
assign Direct_Lookup_Table_n_D_t1_im[26] = t1_im_26;
assign Direct_Lookup_Table_n_D_t1_im[27] = t1_im_27;
assign Direct_Lookup_Table_n_D_t1_im[28] = t1_im_28;
assign Direct_Lookup_Table_n_D_t1_im[29] = t1_im_29;
assign Direct_Lookup_Table_n_D_t1_im[30] = t1_im_30;
assign Direct_Lookup_Table_n_D_t1_im[31] = t1_im_31;
assign Direct_Lookup_Table_n_D_t1_im[32] = t1_im_32;
assign Direct_Lookup_Table_n_D_t1_im[33] = t1_im_33;
assign Direct_Lookup_Table_n_D_t1_im[34] = t1_im_34;
assign Direct_Lookup_Table_n_D_t1_im[35] = t1_im_35;
assign Direct_Lookup_Table_n_D_t1_im[36] = t1_im_36;
assign Direct_Lookup_Table_n_D_t1_im[37] = t1_im_37;
assign Direct_Lookup_Table_n_D_t1_im[38] = t1_im_38;
assign Direct_Lookup_Table_n_D_t1_im[39] = t1_im_39;
assign Direct_Lookup_Table_n_D_t1_im[40] = t1_im_40;
assign Direct_Lookup_Table_n_D_t1_im[41] = t1_im_41;
assign Direct_Lookup_Table_n_D_t1_im[42] = t1_im_42;
assign Direct_Lookup_Table_n_D_t1_im[43] = t1_im_43;
assign Direct_Lookup_Table_n_D_t1_im[44] = t1_im_44;
assign Direct_Lookup_Table_n_D_t1_im[45] = t1_im_45;
assign Direct_Lookup_Table_n_D_t1_im[46] = t1_im_46;
assign Direct_Lookup_Table_n_D_t1_im[47] = t1_im_47;
assign Direct_Lookup_Table_n_D_t1_im[48] = t1_im_48;
assign Direct_Lookup_Table_n_D_t1_im[49] = t1_im_49;
assign Direct_Lookup_Table_n_D_t1_im[50] = t1_im_50;
assign Direct_Lookup_Table_n_D_t1_im[51] = t1_im_51;
assign Direct_Lookup_Table_n_D_t1_im[52] = t1_im_52;
assign Direct_Lookup_Table_n_D_t1_im[53] = t1_im_53;
assign Direct_Lookup_Table_n_D_t1_im[54] = t1_im_54;
assign Direct_Lookup_Table_n_D_t1_im[55] = t1_im_55;
assign Direct_Lookup_Table_n_D_t1_im[56] = t1_im_56;
assign Direct_Lookup_Table_n_D_t1_im[57] = t1_im_57;
assign Direct_Lookup_Table_n_D_t1_im[58] = t1_im_58;
assign Direct_Lookup_Table_n_D_t1_im[59] = t1_im_59;
assign Direct_Lookup_Table_n_D_t1_im[60] = t1_im_60;
assign Direct_Lookup_Table_n_D_t1_im[61] = t1_im_61;
assign Direct_Lookup_Table_n_D_t1_im[62] = t1_im_62;
assign Direct_Lookup_Table_n_D_t1_im[63] = t1_im_63;
assign Direct_Lookup_Table_n_D_t1_im[64] = t1_im_64;
assign Direct_Lookup_Table_n_D_t1_im[65] = t1_im_65;
assign Direct_Lookup_Table_n_D_t1_im[66] = t1_im_66;
assign Direct_Lookup_Table_n_D_t1_im[67] = t1_im_67;
assign Direct_Lookup_Table_n_D_t1_im[68] = t1_im_68;
assign Direct_Lookup_Table_n_D_t1_im[69] = t1_im_69;
assign Direct_Lookup_Table_n_D_t1_im[70] = t1_im_70;
assign Direct_Lookup_Table_n_D_t1_im[71] = t1_im_71;
assign Direct_Lookup_Table_n_D_t1_im[72] = t1_im_72;
assign Direct_Lookup_Table_n_D_t1_im[73] = t1_im_73;
assign Direct_Lookup_Table_n_D_t1_im[74] = t1_im_74;
assign Direct_Lookup_Table_n_D_t1_im[75] = t1_im_75;
assign Direct_Lookup_Table_n_D_t1_im[76] = t1_im_76;
assign Direct_Lookup_Table_n_D_t1_im[77] = t1_im_77;
assign Direct_Lookup_Table_n_D_t1_im[78] = t1_im_78;
assign Direct_Lookup_Table_n_D_t1_im[79] = t1_im_79;
assign Direct_Lookup_Table_n_D_t1_im[80] = t1_im_80;
assign Direct_Lookup_Table_n_D_t1_im[81] = t1_im_81;
assign Direct_Lookup_Table_n_D_t1_im[82] = t1_im_82;
assign Direct_Lookup_Table_n_D_t1_im[83] = t1_im_83;
assign Direct_Lookup_Table_n_D_t1_im[84] = t1_im_84;
assign Direct_Lookup_Table_n_D_t1_im[85] = t1_im_85;
assign Direct_Lookup_Table_n_D_t1_im[86] = t1_im_86;
assign Direct_Lookup_Table_n_D_t1_im[87] = t1_im_87;
assign Direct_Lookup_Table_n_D_t1_im[88] = t1_im_88;
assign Direct_Lookup_Table_n_D_t1_im[89] = t1_im_89;
assign Direct_Lookup_Table_n_D_t1_im[90] = t1_im_90;
assign Direct_Lookup_Table_n_D_t1_im[91] = t1_im_91;
assign Direct_Lookup_Table_n_D_t1_im[92] = t1_im_92;
assign Direct_Lookup_Table_n_D_t1_im[93] = t1_im_93;
assign Direct_Lookup_Table_n_D_t1_im[94] = t1_im_94;
assign Direct_Lookup_Table_n_D_t1_im[95] = t1_im_95;
assign Direct_Lookup_Table_n_D_t1_im[96] = t1_im_96;
assign Direct_Lookup_Table_n_D_t1_im[97] = t1_im_97;
assign Direct_Lookup_Table_n_D_t1_im[98] = t1_im_98;
assign Direct_Lookup_Table_n_D_t1_im[99] = t1_im_99;
assign Direct_Lookup_Table_n_D_t1_im[100] = t1_im_100;
assign Direct_Lookup_Table_n_D_t1_im[101] = t1_im_101;
assign Direct_Lookup_Table_n_D_t1_im[102] = t1_im_102;
assign Direct_Lookup_Table_n_D_t1_im[103] = t1_im_103;
assign Direct_Lookup_Table_n_D_t1_im[104] = t1_im_104;
assign Direct_Lookup_Table_n_D_t1_im[105] = t1_im_105;
assign Direct_Lookup_Table_n_D_t1_im[106] = t1_im_106;
assign Direct_Lookup_Table_n_D_t1_im[107] = t1_im_107;
assign Direct_Lookup_Table_n_D_t1_im[108] = t1_im_108;
assign Direct_Lookup_Table_n_D_t1_im[109] = t1_im_109;
assign Direct_Lookup_Table_n_D_t1_im[110] = t1_im_110;
assign Direct_Lookup_Table_n_D_t1_im[111] = t1_im_111;
assign Direct_Lookup_Table_n_D_t1_im[112] = t1_im_112;
assign Direct_Lookup_Table_n_D_t1_im[113] = t1_im_113;
assign Direct_Lookup_Table_n_D_t1_im[114] = t1_im_114;
assign Direct_Lookup_Table_n_D_t1_im[115] = t1_im_115;
assign Direct_Lookup_Table_n_D_t1_im[116] = t1_im_116;
assign Direct_Lookup_Table_n_D_t1_im[117] = t1_im_117;
assign Direct_Lookup_Table_n_D_t1_im[118] = t1_im_118;
assign Direct_Lookup_Table_n_D_t1_im[119] = t1_im_119;
assign Direct_Lookup_Table_n_D_t1_im[120] = t1_im_120;
assign Direct_Lookup_Table_n_D_t1_im[121] = t1_im_121;
assign Direct_Lookup_Table_n_D_t1_im[122] = t1_im_122;
assign Direct_Lookup_Table_n_D_t1_im[123] = t1_im_123;
assign Direct_Lookup_Table_n_D_t1_im[124] = t1_im_124;
assign Direct_Lookup_Table_n_D_t1_im[125] = t1_im_125;
assign Direct_Lookup_Table_n_D_t1_im[126] = t1_im_126;
assign Direct_Lookup_Table_n_D_t1_im[127] = t1_im_127;
assign Direct_Lookup_Table_n_D_t1_im[128] = t1_im_128;
assign Direct_Lookup_Table_n_D_t1_im[129] = t1_im_129;
assign Direct_Lookup_Table_n_D_t1_im[130] = t1_im_130;
assign Direct_Lookup_Table_n_D_t1_im[131] = t1_im_131;
assign Direct_Lookup_Table_n_D_t1_im[132] = t1_im_132;
assign Direct_Lookup_Table_n_D_t1_im[133] = t1_im_133;
assign Direct_Lookup_Table_n_D_t1_im[134] = t1_im_134;
assign Direct_Lookup_Table_n_D_t1_im[135] = t1_im_135;
assign Direct_Lookup_Table_n_D_t1_im[136] = t1_im_136;
assign Direct_Lookup_Table_n_D_t1_im[137] = t1_im_137;
assign Direct_Lookup_Table_n_D_t1_im[138] = t1_im_138;
assign Direct_Lookup_Table_n_D_t1_im[139] = t1_im_139;
assign Direct_Lookup_Table_n_D_t1_im[140] = t1_im_140;
assign Direct_Lookup_Table_n_D_t1_im[141] = t1_im_141;
assign Direct_Lookup_Table_n_D_t1_im[142] = t1_im_142;
assign Direct_Lookup_Table_n_D_t1_im[143] = t1_im_143;
assign Direct_Lookup_Table_n_D_t1_im[144] = t1_im_144;
assign Direct_Lookup_Table_n_D_t1_im[145] = t1_im_145;
assign Direct_Lookup_Table_n_D_t1_im[146] = t1_im_146;
assign Direct_Lookup_Table_n_D_t1_im[147] = t1_im_147;
assign Direct_Lookup_Table_n_D_t1_im[148] = t1_im_148;
assign Direct_Lookup_Table_n_D_t1_im[149] = t1_im_149;
assign Direct_Lookup_Table_n_D_t1_im[150] = t1_im_150;
assign Direct_Lookup_Table_n_D_t1_im[151] = t1_im_151;
assign Direct_Lookup_Table_n_D_t1_im[152] = t1_im_152;
assign Direct_Lookup_Table_n_D_t1_im[153] = t1_im_153;
assign Direct_Lookup_Table_n_D_t1_im[154] = t1_im_154;
assign Direct_Lookup_Table_n_D_t1_im[155] = t1_im_155;
assign Direct_Lookup_Table_n_D_t1_im[156] = t1_im_156;
assign Direct_Lookup_Table_n_D_t1_im[157] = t1_im_157;
assign Direct_Lookup_Table_n_D_t1_im[158] = t1_im_158;
assign Direct_Lookup_Table_n_D_t1_im[159] = t1_im_159;
assign Direct_Lookup_Table_n_D_t1_im[160] = t1_im_160;
assign Direct_Lookup_Table_n_D_t1_im[161] = t1_im_161;
assign Direct_Lookup_Table_n_D_t1_im[162] = t1_im_162;
assign Direct_Lookup_Table_n_D_t1_im[163] = t1_im_163;
assign Direct_Lookup_Table_n_D_t1_im[164] = t1_im_164;
assign Direct_Lookup_Table_n_D_t1_im[165] = t1_im_165;
assign Direct_Lookup_Table_n_D_t1_im[166] = t1_im_166;
assign Direct_Lookup_Table_n_D_t1_im[167] = t1_im_167;
assign Direct_Lookup_Table_n_D_t1_im[168] = t1_im_168;
assign Direct_Lookup_Table_n_D_t1_im[169] = t1_im_169;
assign Direct_Lookup_Table_n_D_t1_im[170] = t1_im_170;
assign Direct_Lookup_Table_n_D_t1_im[171] = t1_im_171;
assign Direct_Lookup_Table_n_D_t1_im[172] = t1_im_172;
assign Direct_Lookup_Table_n_D_t1_im[173] = t1_im_173;
assign Direct_Lookup_Table_n_D_t1_im[174] = t1_im_174;
assign Direct_Lookup_Table_n_D_t1_im[175] = t1_im_175;
assign Direct_Lookup_Table_n_D_t1_im[176] = t1_im_176;
assign Direct_Lookup_Table_n_D_t1_im[177] = t1_im_177;
assign Direct_Lookup_Table_n_D_t1_im[178] = t1_im_178;
assign Direct_Lookup_Table_n_D_t1_im[179] = t1_im_179;
assign Direct_Lookup_Table_n_D_t1_im[180] = t1_im_180;
assign Direct_Lookup_Table_n_D_t1_im[181] = t1_im_181;
assign Direct_Lookup_Table_n_D_t1_im[182] = t1_im_182;
assign Direct_Lookup_Table_n_D_t1_im[183] = t1_im_183;
assign Direct_Lookup_Table_n_D_t1_im[184] = t1_im_184;
assign Direct_Lookup_Table_n_D_t1_im[185] = t1_im_185;
assign Direct_Lookup_Table_n_D_t1_im[186] = t1_im_186;
assign Direct_Lookup_Table_n_D_t1_im[187] = t1_im_187;
assign Direct_Lookup_Table_n_D_t1_im[188] = t1_im_188;
assign Direct_Lookup_Table_n_D_t1_im[189] = t1_im_189;
assign Direct_Lookup_Table_n_D_t1_im[190] = t1_im_190;
assign Direct_Lookup_Table_n_D_t1_im[191] = t1_im_191;
assign Direct_Lookup_Table_n_D_t1_im[192] = t1_im_192;
assign Direct_Lookup_Table_n_D_t1_im[193] = t1_im_193;
assign Direct_Lookup_Table_n_D_t1_im[194] = t1_im_194;
assign Direct_Lookup_Table_n_D_t1_im[195] = t1_im_195;
assign Direct_Lookup_Table_n_D_t1_im[196] = t1_im_196;
assign Direct_Lookup_Table_n_D_t1_im[197] = t1_im_197;
assign Direct_Lookup_Table_n_D_t1_im[198] = t1_im_198;
assign Direct_Lookup_Table_n_D_t1_im[199] = t1_im_199;
assign Direct_Lookup_Table_n_D_t1_im[200] = t1_im_200;
assign Direct_Lookup_Table_n_D_t1_im[201] = t1_im_201;
assign Direct_Lookup_Table_n_D_t1_im[202] = t1_im_202;
assign Direct_Lookup_Table_n_D_t1_im[203] = t1_im_203;
assign Direct_Lookup_Table_n_D_t1_im[204] = t1_im_204;
assign Direct_Lookup_Table_n_D_t1_im[205] = t1_im_205;
assign Direct_Lookup_Table_n_D_t1_im[206] = t1_im_206;
assign Direct_Lookup_Table_n_D_t1_im[207] = t1_im_207;
assign Direct_Lookup_Table_n_D_t1_im[208] = t1_im_208;
assign Direct_Lookup_Table_n_D_t1_im[209] = t1_im_209;
assign Direct_Lookup_Table_n_D_t1_im[210] = t1_im_210;
assign Direct_Lookup_Table_n_D_t1_im[211] = t1_im_211;
assign Direct_Lookup_Table_n_D_t1_im[212] = t1_im_212;
assign Direct_Lookup_Table_n_D_t1_im[213] = t1_im_213;
assign Direct_Lookup_Table_n_D_t1_im[214] = t1_im_214;
assign Direct_Lookup_Table_n_D_t1_im[215] = t1_im_215;
assign Direct_Lookup_Table_n_D_t1_im[216] = t1_im_216;
assign Direct_Lookup_Table_n_D_t1_im[217] = t1_im_217;
assign Direct_Lookup_Table_n_D_t1_im[218] = t1_im_218;
assign Direct_Lookup_Table_n_D_t1_im[219] = t1_im_219;
assign Direct_Lookup_Table_n_D_t1_im[220] = t1_im_220;
assign Direct_Lookup_Table_n_D_t1_im[221] = t1_im_221;
assign Direct_Lookup_Table_n_D_t1_im[222] = t1_im_222;
assign Direct_Lookup_Table_n_D_t1_im[223] = t1_im_223;
assign Direct_Lookup_Table_n_D_t1_im[224] = t1_im_224;
assign Direct_Lookup_Table_n_D_t1_im[225] = t1_im_225;
assign Direct_Lookup_Table_n_D_t1_im[226] = t1_im_226;
assign Direct_Lookup_Table_n_D_t1_im[227] = t1_im_227;
assign Direct_Lookup_Table_n_D_t1_im[228] = t1_im_228;
assign Direct_Lookup_Table_n_D_t1_im[229] = t1_im_229;
assign Direct_Lookup_Table_n_D_t1_im[230] = t1_im_230;
assign Direct_Lookup_Table_n_D_t1_im[231] = t1_im_231;
assign Direct_Lookup_Table_n_D_t1_im[232] = t1_im_232;
assign Direct_Lookup_Table_n_D_t1_im[233] = t1_im_233;
assign Direct_Lookup_Table_n_D_t1_im[234] = t1_im_234;
assign Direct_Lookup_Table_n_D_t1_im[235] = t1_im_235;
assign Direct_Lookup_Table_n_D_t1_im[236] = t1_im_236;
assign Direct_Lookup_Table_n_D_t1_im[237] = t1_im_237;
assign Direct_Lookup_Table_n_D_t1_im[238] = t1_im_238;
assign Direct_Lookup_Table_n_D_t1_im[239] = t1_im_239;
assign Direct_Lookup_Table_n_D_t1_im[240] = t1_im_240;
assign Direct_Lookup_Table_n_D_t1_im[241] = t1_im_241;
assign Direct_Lookup_Table_n_D_t1_im[242] = t1_im_242;
assign Direct_Lookup_Table_n_D_t1_im[243] = t1_im_243;
assign Direct_Lookup_Table_n_D_t1_im[244] = t1_im_244;
assign Direct_Lookup_Table_n_D_t1_im[245] = t1_im_245;
assign Direct_Lookup_Table_n_D_t1_im[246] = t1_im_246;
assign Direct_Lookup_Table_n_D_t1_im[247] = t1_im_247;
assign Direct_Lookup_Table_n_D_t1_im[248] = t1_im_248;
assign Direct_Lookup_Table_n_D_t1_im[249] = t1_im_249;
assign Direct_Lookup_Table_n_D_t1_im[250] = t1_im_250;
assign Direct_Lookup_Table_n_D_t1_im[251] = t1_im_251;
assign Direct_Lookup_Table_n_D_t1_im[252] = t1_im_252;
assign Direct_Lookup_Table_n_D_t1_im[253] = t1_im_253;
assign Direct_Lookup_Table_n_D_t1_im[254] = t1_im_254;
assign Direct_Lookup_Table_n_D_t1_im[255] = t1_im_255;
assign Direct_Lookup_Table_n_D_t1_im[256] = t1_im_256;
assign Direct_Lookup_Table_n_D_t1_im[257] = t1_im_257;
assign Direct_Lookup_Table_n_D_t1_im[258] = t1_im_258;
assign Direct_Lookup_Table_n_D_t1_im[259] = t1_im_259;
assign Direct_Lookup_Table_n_D_t1_im[260] = t1_im_260;
assign Direct_Lookup_Table_n_D_t1_im[261] = t1_im_261;
assign Direct_Lookup_Table_n_D_t1_im[262] = t1_im_262;
assign Direct_Lookup_Table_n_D_t1_im[263] = t1_im_263;
assign Direct_Lookup_Table_n_D_t1_im[264] = t1_im_264;
assign Direct_Lookup_Table_n_D_t1_im[265] = t1_im_265;
assign Direct_Lookup_Table_n_D_t1_im[266] = t1_im_266;
assign Direct_Lookup_Table_n_D_t1_im[267] = t1_im_267;
assign Direct_Lookup_Table_n_D_t1_im[268] = t1_im_268;
assign Direct_Lookup_Table_n_D_t1_im[269] = t1_im_269;
assign Direct_Lookup_Table_n_D_t1_im[270] = t1_im_270;
assign Direct_Lookup_Table_n_D_t1_im[271] = t1_im_271;
assign Direct_Lookup_Table_n_D_t1_im[272] = t1_im_272;
assign Direct_Lookup_Table_n_D_t1_im[273] = t1_im_273;
assign Direct_Lookup_Table_n_D_t1_im[274] = t1_im_274;
assign Direct_Lookup_Table_n_D_t1_im[275] = t1_im_275;
assign Direct_Lookup_Table_n_D_t1_im[276] = t1_im_276;
assign Direct_Lookup_Table_n_D_t1_im[277] = t1_im_277;
assign Direct_Lookup_Table_n_D_t1_im[278] = t1_im_278;
assign Direct_Lookup_Table_n_D_t1_im[279] = t1_im_279;
assign Direct_Lookup_Table_n_D_t1_im[280] = t1_im_280;
assign Direct_Lookup_Table_n_D_t1_im[281] = t1_im_281;
assign Direct_Lookup_Table_n_D_t1_im[282] = t1_im_282;
assign Direct_Lookup_Table_n_D_t1_im[283] = t1_im_283;
assign Direct_Lookup_Table_n_D_t1_im[284] = t1_im_284;
assign Direct_Lookup_Table_n_D_t1_im[285] = t1_im_285;
assign Direct_Lookup_Table_n_D_t1_im[286] = t1_im_286;
assign Direct_Lookup_Table_n_D_t1_im[287] = t1_im_287;
assign Direct_Lookup_Table_n_D_t1_im[288] = t1_im_288;
assign Direct_Lookup_Table_n_D_t1_im[289] = t1_im_289;
assign Direct_Lookup_Table_n_D_t1_im[290] = t1_im_290;
assign Direct_Lookup_Table_n_D_t1_im[291] = t1_im_291;
assign Direct_Lookup_Table_n_D_t1_im[292] = t1_im_292;
assign Direct_Lookup_Table_n_D_t1_im[293] = t1_im_293;
assign Direct_Lookup_Table_n_D_t1_im[294] = t1_im_294;
assign Direct_Lookup_Table_n_D_t1_im[295] = t1_im_295;
assign Direct_Lookup_Table_n_D_t1_im[296] = t1_im_296;
assign Direct_Lookup_Table_n_D_t1_im[297] = t1_im_297;
assign Direct_Lookup_Table_n_D_t1_im[298] = t1_im_298;
assign Direct_Lookup_Table_n_D_t1_im[299] = t1_im_299;
assign Direct_Lookup_Table_n_D_t1_im[300] = t1_im_300;
assign Direct_Lookup_Table_n_D_t1_im[301] = t1_im_301;
assign Direct_Lookup_Table_n_D_t1_im[302] = t1_im_302;
assign Direct_Lookup_Table_n_D_t1_im[303] = t1_im_303;
assign Direct_Lookup_Table_n_D_t1_im[304] = t1_im_304;
assign Direct_Lookup_Table_n_D_t1_im[305] = t1_im_305;
assign Direct_Lookup_Table_n_D_t1_im[306] = t1_im_306;
assign Direct_Lookup_Table_n_D_t1_im[307] = t1_im_307;
assign Direct_Lookup_Table_n_D_t1_im[308] = t1_im_308;
assign Direct_Lookup_Table_n_D_t1_im[309] = t1_im_309;
assign Direct_Lookup_Table_n_D_t1_im[310] = t1_im_310;
assign Direct_Lookup_Table_n_D_t1_im[311] = t1_im_311;
assign Direct_Lookup_Table_n_D_t1_im[312] = t1_im_312;
assign Direct_Lookup_Table_n_D_t1_im[313] = t1_im_313;
assign Direct_Lookup_Table_n_D_t1_im[314] = t1_im_314;
assign Direct_Lookup_Table_n_D_t1_im[315] = t1_im_315;
assign Direct_Lookup_Table_n_D_t1_im[316] = t1_im_316;
assign Direct_Lookup_Table_n_D_t1_im[317] = t1_im_317;
assign Direct_Lookup_Table_n_D_t1_im[318] = t1_im_318;
assign Direct_Lookup_Table_n_D_t1_im[319] = t1_im_319;
assign Direct_Lookup_Table_n_D_t1_im[320] = t1_im_320;
assign Direct_Lookup_Table_n_D_t1_im[321] = t1_im_321;
assign Direct_Lookup_Table_n_D_t1_im[322] = t1_im_322;
assign Direct_Lookup_Table_n_D_t1_im[323] = t1_im_323;
assign Direct_Lookup_Table_n_D_t1_im[324] = t1_im_324;
assign Direct_Lookup_Table_n_D_t1_im[325] = t1_im_325;
assign Direct_Lookup_Table_n_D_t1_im[326] = t1_im_326;
assign Direct_Lookup_Table_n_D_t1_im[327] = t1_im_327;
assign Direct_Lookup_Table_n_D_t1_im[328] = t1_im_328;
assign Direct_Lookup_Table_n_D_t1_im[329] = t1_im_329;
assign Direct_Lookup_Table_n_D_t1_im[330] = t1_im_330;
assign Direct_Lookup_Table_n_D_t1_im[331] = t1_im_331;
assign Direct_Lookup_Table_n_D_t1_im[332] = t1_im_332;
assign Direct_Lookup_Table_n_D_t1_im[333] = t1_im_333;
assign Direct_Lookup_Table_n_D_t1_im[334] = t1_im_334;
assign Direct_Lookup_Table_n_D_t1_im[335] = t1_im_335;
assign Direct_Lookup_Table_n_D_t1_im[336] = t1_im_336;
assign Direct_Lookup_Table_n_D_t1_im[337] = t1_im_337;
assign Direct_Lookup_Table_n_D_t1_im[338] = t1_im_338;
assign Direct_Lookup_Table_n_D_t1_im[339] = t1_im_339;
assign Direct_Lookup_Table_n_D_t1_im[340] = t1_im_340;
assign Direct_Lookup_Table_n_D_t1_im[341] = t1_im_341;
assign Direct_Lookup_Table_n_D_t1_im[342] = t1_im_342;
assign Direct_Lookup_Table_n_D_t1_im[343] = t1_im_343;
assign Direct_Lookup_Table_n_D_t1_im[344] = t1_im_344;
assign Direct_Lookup_Table_n_D_t1_im[345] = t1_im_345;
assign Direct_Lookup_Table_n_D_t1_im[346] = t1_im_346;
assign Direct_Lookup_Table_n_D_t1_im[347] = t1_im_347;
assign Direct_Lookup_Table_n_D_t1_im[348] = t1_im_348;
assign Direct_Lookup_Table_n_D_t1_im[349] = t1_im_349;
assign Direct_Lookup_Table_n_D_t1_im[350] = t1_im_350;
assign Direct_Lookup_Table_n_D_t1_im[351] = t1_im_351;
assign Direct_Lookup_Table_n_D_t1_im[352] = t1_im_352;
assign Direct_Lookup_Table_n_D_t1_im[353] = t1_im_353;
assign Direct_Lookup_Table_n_D_t1_im[354] = t1_im_354;
assign Direct_Lookup_Table_n_D_t1_im[355] = t1_im_355;
assign Direct_Lookup_Table_n_D_t1_im[356] = t1_im_356;
assign Direct_Lookup_Table_n_D_t1_im[357] = t1_im_357;
assign Direct_Lookup_Table_n_D_t1_im[358] = t1_im_358;
assign Direct_Lookup_Table_n_D_t1_im[359] = t1_im_359;
assign Direct_Lookup_Table_n_D_t1_im[360] = t1_im_360;
assign Direct_Lookup_Table_n_D_t1_im[361] = t1_im_361;
assign Direct_Lookup_Table_n_D_t1_im[362] = t1_im_362;
assign Direct_Lookup_Table_n_D_t1_im[363] = t1_im_363;
assign Direct_Lookup_Table_n_D_t1_im[364] = t1_im_364;
assign Direct_Lookup_Table_n_D_t1_im[365] = t1_im_365;
assign Direct_Lookup_Table_n_D_t1_im[366] = t1_im_366;
assign Direct_Lookup_Table_n_D_t1_im[367] = t1_im_367;
assign Direct_Lookup_Table_n_D_t1_im[368] = t1_im_368;
assign Direct_Lookup_Table_n_D_t1_im[369] = t1_im_369;
assign Direct_Lookup_Table_n_D_t1_im[370] = t1_im_370;
assign Direct_Lookup_Table_n_D_t1_im[371] = t1_im_371;
assign Direct_Lookup_Table_n_D_t1_im[372] = t1_im_372;
assign Direct_Lookup_Table_n_D_t1_im[373] = t1_im_373;
assign Direct_Lookup_Table_n_D_t1_im[374] = t1_im_374;
assign Direct_Lookup_Table_n_D_t1_im[375] = t1_im_375;
assign Direct_Lookup_Table_n_D_t1_im[376] = t1_im_376;
assign Direct_Lookup_Table_n_D_t1_im[377] = t1_im_377;
assign Direct_Lookup_Table_n_D_t1_im[378] = t1_im_378;
assign Direct_Lookup_Table_n_D_t1_im[379] = t1_im_379;
assign Direct_Lookup_Table_n_D_t1_im[380] = t1_im_380;
assign Direct_Lookup_Table_n_D_t1_im[381] = t1_im_381;
assign Direct_Lookup_Table_n_D_t1_im[382] = t1_im_382;
assign Direct_Lookup_Table_n_D_t1_im[383] = t1_im_383;
assign Direct_Lookup_Table_n_D_t1_im[384] = t1_im_384;
assign Direct_Lookup_Table_n_D_t1_im[385] = t1_im_385;
assign Direct_Lookup_Table_n_D_t1_im[386] = t1_im_386;
assign Direct_Lookup_Table_n_D_t1_im[387] = t1_im_387;
assign Direct_Lookup_Table_n_D_t1_im[388] = t1_im_388;
assign Direct_Lookup_Table_n_D_t1_im[389] = t1_im_389;
assign Direct_Lookup_Table_n_D_t1_im[390] = t1_im_390;
assign Direct_Lookup_Table_n_D_t1_im[391] = t1_im_391;
assign Direct_Lookup_Table_n_D_t1_im[392] = t1_im_392;
assign Direct_Lookup_Table_n_D_t1_im[393] = t1_im_393;
assign Direct_Lookup_Table_n_D_t1_im[394] = t1_im_394;
assign Direct_Lookup_Table_n_D_t1_im[395] = t1_im_395;
assign Direct_Lookup_Table_n_D_t1_im[396] = t1_im_396;
assign Direct_Lookup_Table_n_D_t1_im[397] = t1_im_397;
assign Direct_Lookup_Table_n_D_t1_im[398] = t1_im_398;
assign Direct_Lookup_Table_n_D_t1_im[399] = t1_im_399;
assign Direct_Lookup_Table_n_D_t1_im[400] = t1_im_400;
assign Direct_Lookup_Table_n_D_t1_im[401] = t1_im_401;
assign Direct_Lookup_Table_n_D_t1_im[402] = t1_im_402;
assign Direct_Lookup_Table_n_D_t1_im[403] = t1_im_403;
assign Direct_Lookup_Table_n_D_t1_im[404] = t1_im_404;
assign Direct_Lookup_Table_n_D_t1_im[405] = t1_im_405;
assign Direct_Lookup_Table_n_D_t1_im[406] = t1_im_406;
assign Direct_Lookup_Table_n_D_t1_im[407] = t1_im_407;
assign Direct_Lookup_Table_n_D_t1_im[408] = t1_im_408;
assign Direct_Lookup_Table_n_D_t1_im[409] = t1_im_409;
assign Direct_Lookup_Table_n_D_t1_im[410] = t1_im_410;
assign Direct_Lookup_Table_n_D_t1_im[411] = t1_im_411;
assign Direct_Lookup_Table_n_D_t1_im[412] = t1_im_412;
assign Direct_Lookup_Table_n_D_t1_im[413] = t1_im_413;
assign Direct_Lookup_Table_n_D_t1_im[414] = t1_im_414;
assign Direct_Lookup_Table_n_D_t1_im[415] = t1_im_415;
assign Direct_Lookup_Table_n_D_t1_im[416] = t1_im_416;
assign Direct_Lookup_Table_n_D_t1_im[417] = t1_im_417;
assign Direct_Lookup_Table_n_D_t1_im[418] = t1_im_418;
assign Direct_Lookup_Table_n_D_t1_im[419] = t1_im_419;
assign Direct_Lookup_Table_n_D_t1_im[420] = t1_im_420;
assign Direct_Lookup_Table_n_D_t1_im[421] = t1_im_421;
assign Direct_Lookup_Table_n_D_t1_im[422] = t1_im_422;
assign Direct_Lookup_Table_n_D_t1_im[423] = t1_im_423;
assign Direct_Lookup_Table_n_D_t1_im[424] = t1_im_424;
assign Direct_Lookup_Table_n_D_t1_im[425] = t1_im_425;
assign Direct_Lookup_Table_n_D_t1_im[426] = t1_im_426;
assign Direct_Lookup_Table_n_D_t1_im[427] = t1_im_427;
assign Direct_Lookup_Table_n_D_t1_im[428] = t1_im_428;
assign Direct_Lookup_Table_n_D_t1_im[429] = t1_im_429;
assign Direct_Lookup_Table_n_D_t1_im[430] = t1_im_430;
assign Direct_Lookup_Table_n_D_t1_im[431] = t1_im_431;
assign Direct_Lookup_Table_n_D_t1_im[432] = t1_im_432;
assign Direct_Lookup_Table_n_D_t1_im[433] = t1_im_433;
assign Direct_Lookup_Table_n_D_t1_im[434] = t1_im_434;
assign Direct_Lookup_Table_n_D_t1_im[435] = t1_im_435;
assign Direct_Lookup_Table_n_D_t1_im[436] = t1_im_436;
assign Direct_Lookup_Table_n_D_t1_im[437] = t1_im_437;
assign Direct_Lookup_Table_n_D_t1_im[438] = t1_im_438;
assign Direct_Lookup_Table_n_D_t1_im[439] = t1_im_439;
assign Direct_Lookup_Table_n_D_t1_im[440] = t1_im_440;
assign Direct_Lookup_Table_n_D_t1_im[441] = t1_im_441;
assign Direct_Lookup_Table_n_D_t1_im[442] = t1_im_442;
assign Direct_Lookup_Table_n_D_t1_im[443] = t1_im_443;
assign Direct_Lookup_Table_n_D_t1_im[444] = t1_im_444;
assign Direct_Lookup_Table_n_D_t1_im[445] = t1_im_445;
assign Direct_Lookup_Table_n_D_t1_im[446] = t1_im_446;
assign Direct_Lookup_Table_n_D_t1_im[447] = t1_im_447;
assign Direct_Lookup_Table_n_D_t1_im[448] = t1_im_448;
assign Direct_Lookup_Table_n_D_t1_im[449] = t1_im_449;
assign Direct_Lookup_Table_n_D_t1_im[450] = t1_im_450;
assign Direct_Lookup_Table_n_D_t1_im[451] = t1_im_451;
assign Direct_Lookup_Table_n_D_t1_im[452] = t1_im_452;
assign Direct_Lookup_Table_n_D_t1_im[453] = t1_im_453;
assign Direct_Lookup_Table_n_D_t1_im[454] = t1_im_454;
assign Direct_Lookup_Table_n_D_t1_im[455] = t1_im_455;
assign Direct_Lookup_Table_n_D_t1_im[456] = t1_im_456;
assign Direct_Lookup_Table_n_D_t1_im[457] = t1_im_457;
assign Direct_Lookup_Table_n_D_t1_im[458] = t1_im_458;
assign Direct_Lookup_Table_n_D_t1_im[459] = t1_im_459;
assign Direct_Lookup_Table_n_D_t1_im[460] = t1_im_460;
assign Direct_Lookup_Table_n_D_t1_im[461] = t1_im_461;
assign Direct_Lookup_Table_n_D_t1_im[462] = t1_im_462;
assign Direct_Lookup_Table_n_D_t1_im[463] = t1_im_463;
assign Direct_Lookup_Table_n_D_t1_im[464] = t1_im_464;
assign Direct_Lookup_Table_n_D_t1_im[465] = t1_im_465;
assign Direct_Lookup_Table_n_D_t1_im[466] = t1_im_466;
assign Direct_Lookup_Table_n_D_t1_im[467] = t1_im_467;
assign Direct_Lookup_Table_n_D_t1_im[468] = t1_im_468;
assign Direct_Lookup_Table_n_D_t1_im[469] = t1_im_469;
assign Direct_Lookup_Table_n_D_t1_im[470] = t1_im_470;
assign Direct_Lookup_Table_n_D_t1_im[471] = t1_im_471;
assign Direct_Lookup_Table_n_D_t1_im[472] = t1_im_472;
assign Direct_Lookup_Table_n_D_t1_im[473] = t1_im_473;
assign Direct_Lookup_Table_n_D_t1_im[474] = t1_im_474;
assign Direct_Lookup_Table_n_D_t1_im[475] = t1_im_475;
assign Direct_Lookup_Table_n_D_t1_im[476] = t1_im_476;
assign Direct_Lookup_Table_n_D_t1_im[477] = t1_im_477;
assign Direct_Lookup_Table_n_D_t1_im[478] = t1_im_478;
assign Direct_Lookup_Table_n_D_t1_im[479] = t1_im_479;
assign Direct_Lookup_Table_n_D_t1_im[480] = t1_im_480;
assign Direct_Lookup_Table_n_D_t1_im[481] = t1_im_481;
assign Direct_Lookup_Table_n_D_t1_im[482] = t1_im_482;
assign Direct_Lookup_Table_n_D_t1_im[483] = t1_im_483;
assign Direct_Lookup_Table_n_D_t1_im[484] = t1_im_484;
assign Direct_Lookup_Table_n_D_t1_im[485] = t1_im_485;
assign Direct_Lookup_Table_n_D_t1_im[486] = t1_im_486;
assign Direct_Lookup_Table_n_D_t1_im[487] = t1_im_487;
assign Direct_Lookup_Table_n_D_t1_im[488] = t1_im_488;
assign Direct_Lookup_Table_n_D_t1_im[489] = t1_im_489;
assign Direct_Lookup_Table_n_D_t1_im[490] = t1_im_490;
assign Direct_Lookup_Table_n_D_t1_im[491] = t1_im_491;
assign Direct_Lookup_Table_n_D_t1_im[492] = t1_im_492;
assign Direct_Lookup_Table_n_D_t1_im[493] = t1_im_493;
assign Direct_Lookup_Table_n_D_t1_im[494] = t1_im_494;
assign Direct_Lookup_Table_n_D_t1_im[495] = t1_im_495;
assign Direct_Lookup_Table_n_D_t1_im[496] = t1_im_496;
assign Direct_Lookup_Table_n_D_t1_im[497] = t1_im_497;
assign Direct_Lookup_Table_n_D_t1_im[498] = t1_im_498;
assign Direct_Lookup_Table_n_D_t1_im[499] = t1_im_499;
assign Direct_Lookup_Table_n_D_t1_im[500] = t1_im_500;
assign Direct_Lookup_Table_n_D_t1_im[501] = t1_im_501;
assign Direct_Lookup_Table_n_D_t1_im[502] = t1_im_502;
assign Direct_Lookup_Table_n_D_t1_im[503] = t1_im_503;
assign Direct_Lookup_Table_n_D_t1_im[504] = t1_im_504;
assign Direct_Lookup_Table_n_D_t1_im[505] = t1_im_505;
assign Direct_Lookup_Table_n_D_t1_im[506] = t1_im_506;
assign Direct_Lookup_Table_n_D_t1_im[507] = t1_im_507;
assign Direct_Lookup_Table_n_D_t1_im[508] = t1_im_508;
assign Direct_Lookup_Table_n_D_t1_im[509] = t1_im_509;
assign Direct_Lookup_Table_n_D_t1_im[510] = t1_im_510;
assign Direct_Lookup_Table_n_D_t1_im[511] = t1_im_511;
assign Direct_Lookup_Table_n_D_out1_re = Direct_Lookup_Table_n_D_t1_re[Data_Type_Conversion1_out1];
assign Direct_Lookup_Table_n_D_out1_im = Direct_Lookup_Table_n_D_t1_im[Data_Type_Conversion1_out1];
// <S18>/Mark_Extract_Bits1
controllerHdl_Mark_Extract_Bits1 u_Mark_Extract_Bits1 (.In1(elec_pos_scaled), // ufix18
.Out1(y_1) // ufix9
);
// <S18>/Data Type Conversion2
assign Data_Type_Conversion2_out1 = y_1;
// <S18>/Direct Lookup Table (n-D)1
assign Direct_Lookup_Table_n_D_1_t1_re[0] = t1_re_0_2;
assign Direct_Lookup_Table_n_D_1_t1_re[1] = t1_re_1_2;
assign Direct_Lookup_Table_n_D_1_t1_re[2] = t1_re_2_2;
assign Direct_Lookup_Table_n_D_1_t1_re[3] = t1_re_3_2;
assign Direct_Lookup_Table_n_D_1_t1_re[4] = t1_re_4_2;
assign Direct_Lookup_Table_n_D_1_t1_re[5] = t1_re_5_2;
assign Direct_Lookup_Table_n_D_1_t1_re[6] = t1_re_6_2;
assign Direct_Lookup_Table_n_D_1_t1_re[7] = t1_re_7_2;
assign Direct_Lookup_Table_n_D_1_t1_re[8] = t1_re_8_2;
assign Direct_Lookup_Table_n_D_1_t1_re[9] = t1_re_9_2;
assign Direct_Lookup_Table_n_D_1_t1_re[10] = t1_re_10_2;
assign Direct_Lookup_Table_n_D_1_t1_re[11] = t1_re_11_2;
assign Direct_Lookup_Table_n_D_1_t1_re[12] = t1_re_12_2;
assign Direct_Lookup_Table_n_D_1_t1_re[13] = t1_re_13_2;
assign Direct_Lookup_Table_n_D_1_t1_re[14] = t1_re_14_2;
assign Direct_Lookup_Table_n_D_1_t1_re[15] = t1_re_15_2;
assign Direct_Lookup_Table_n_D_1_t1_re[16] = t1_re_16_2;
assign Direct_Lookup_Table_n_D_1_t1_re[17] = t1_re_17_2;
assign Direct_Lookup_Table_n_D_1_t1_re[18] = t1_re_18_2;
assign Direct_Lookup_Table_n_D_1_t1_re[19] = t1_re_19_2;
assign Direct_Lookup_Table_n_D_1_t1_re[20] = t1_re_20_2;
assign Direct_Lookup_Table_n_D_1_t1_re[21] = t1_re_21_2;
assign Direct_Lookup_Table_n_D_1_t1_re[22] = t1_re_22_2;
assign Direct_Lookup_Table_n_D_1_t1_re[23] = t1_re_23_2;
assign Direct_Lookup_Table_n_D_1_t1_re[24] = t1_re_24_2;
assign Direct_Lookup_Table_n_D_1_t1_re[25] = t1_re_25_2;
assign Direct_Lookup_Table_n_D_1_t1_re[26] = t1_re_26_2;
assign Direct_Lookup_Table_n_D_1_t1_re[27] = t1_re_27_2;
assign Direct_Lookup_Table_n_D_1_t1_re[28] = t1_re_28_2;
assign Direct_Lookup_Table_n_D_1_t1_re[29] = t1_re_29_2;
assign Direct_Lookup_Table_n_D_1_t1_re[30] = t1_re_30_2;
assign Direct_Lookup_Table_n_D_1_t1_re[31] = t1_re_31_2;
assign Direct_Lookup_Table_n_D_1_t1_re[32] = t1_re_32_2;
assign Direct_Lookup_Table_n_D_1_t1_re[33] = t1_re_33_2;
assign Direct_Lookup_Table_n_D_1_t1_re[34] = t1_re_34_2;
assign Direct_Lookup_Table_n_D_1_t1_re[35] = t1_re_35_2;
assign Direct_Lookup_Table_n_D_1_t1_re[36] = t1_re_36_2;
assign Direct_Lookup_Table_n_D_1_t1_re[37] = t1_re_37_2;
assign Direct_Lookup_Table_n_D_1_t1_re[38] = t1_re_38_2;
assign Direct_Lookup_Table_n_D_1_t1_re[39] = t1_re_39_2;
assign Direct_Lookup_Table_n_D_1_t1_re[40] = t1_re_40_2;
assign Direct_Lookup_Table_n_D_1_t1_re[41] = t1_re_41_2;
assign Direct_Lookup_Table_n_D_1_t1_re[42] = t1_re_42_2;
assign Direct_Lookup_Table_n_D_1_t1_re[43] = t1_re_43_2;
assign Direct_Lookup_Table_n_D_1_t1_re[44] = t1_re_44_2;
assign Direct_Lookup_Table_n_D_1_t1_re[45] = t1_re_45_2;
assign Direct_Lookup_Table_n_D_1_t1_re[46] = t1_re_46_2;
assign Direct_Lookup_Table_n_D_1_t1_re[47] = t1_re_47_2;
assign Direct_Lookup_Table_n_D_1_t1_re[48] = t1_re_48_2;
assign Direct_Lookup_Table_n_D_1_t1_re[49] = t1_re_49_2;
assign Direct_Lookup_Table_n_D_1_t1_re[50] = t1_re_50_2;
assign Direct_Lookup_Table_n_D_1_t1_re[51] = t1_re_51_2;
assign Direct_Lookup_Table_n_D_1_t1_re[52] = t1_re_52_2;
assign Direct_Lookup_Table_n_D_1_t1_re[53] = t1_re_53_2;
assign Direct_Lookup_Table_n_D_1_t1_re[54] = t1_re_54_2;
assign Direct_Lookup_Table_n_D_1_t1_re[55] = t1_re_55_2;
assign Direct_Lookup_Table_n_D_1_t1_re[56] = t1_re_56_2;
assign Direct_Lookup_Table_n_D_1_t1_re[57] = t1_re_57_2;
assign Direct_Lookup_Table_n_D_1_t1_re[58] = t1_re_58_2;
assign Direct_Lookup_Table_n_D_1_t1_re[59] = t1_re_59_2;
assign Direct_Lookup_Table_n_D_1_t1_re[60] = t1_re_60_2;
assign Direct_Lookup_Table_n_D_1_t1_re[61] = t1_re_61_2;
assign Direct_Lookup_Table_n_D_1_t1_re[62] = t1_re_62_2;
assign Direct_Lookup_Table_n_D_1_t1_re[63] = t1_re_63_2;
assign Direct_Lookup_Table_n_D_1_t1_re[64] = t1_re_64_2;
assign Direct_Lookup_Table_n_D_1_t1_re[65] = t1_re_65_2;
assign Direct_Lookup_Table_n_D_1_t1_re[66] = t1_re_66_2;
assign Direct_Lookup_Table_n_D_1_t1_re[67] = t1_re_67_2;
assign Direct_Lookup_Table_n_D_1_t1_re[68] = t1_re_68_2;
assign Direct_Lookup_Table_n_D_1_t1_re[69] = t1_re_69_2;
assign Direct_Lookup_Table_n_D_1_t1_re[70] = t1_re_70_2;
assign Direct_Lookup_Table_n_D_1_t1_re[71] = t1_re_71_2;
assign Direct_Lookup_Table_n_D_1_t1_re[72] = t1_re_72_2;
assign Direct_Lookup_Table_n_D_1_t1_re[73] = t1_re_73_2;
assign Direct_Lookup_Table_n_D_1_t1_re[74] = t1_re_74_2;
assign Direct_Lookup_Table_n_D_1_t1_re[75] = t1_re_75_2;
assign Direct_Lookup_Table_n_D_1_t1_re[76] = t1_re_76_2;
assign Direct_Lookup_Table_n_D_1_t1_re[77] = t1_re_77_2;
assign Direct_Lookup_Table_n_D_1_t1_re[78] = t1_re_78_2;
assign Direct_Lookup_Table_n_D_1_t1_re[79] = t1_re_79_2;
assign Direct_Lookup_Table_n_D_1_t1_re[80] = t1_re_80_2;
assign Direct_Lookup_Table_n_D_1_t1_re[81] = t1_re_81_2;
assign Direct_Lookup_Table_n_D_1_t1_re[82] = t1_re_82_2;
assign Direct_Lookup_Table_n_D_1_t1_re[83] = t1_re_83_2;
assign Direct_Lookup_Table_n_D_1_t1_re[84] = t1_re_84_2;
assign Direct_Lookup_Table_n_D_1_t1_re[85] = t1_re_85_2;
assign Direct_Lookup_Table_n_D_1_t1_re[86] = t1_re_86_2;
assign Direct_Lookup_Table_n_D_1_t1_re[87] = t1_re_87_2;
assign Direct_Lookup_Table_n_D_1_t1_re[88] = t1_re_88_2;
assign Direct_Lookup_Table_n_D_1_t1_re[89] = t1_re_89_2;
assign Direct_Lookup_Table_n_D_1_t1_re[90] = t1_re_90_2;
assign Direct_Lookup_Table_n_D_1_t1_re[91] = t1_re_91_2;
assign Direct_Lookup_Table_n_D_1_t1_re[92] = t1_re_92_2;
assign Direct_Lookup_Table_n_D_1_t1_re[93] = t1_re_93_2;
assign Direct_Lookup_Table_n_D_1_t1_re[94] = t1_re_94_2;
assign Direct_Lookup_Table_n_D_1_t1_re[95] = t1_re_95_2;
assign Direct_Lookup_Table_n_D_1_t1_re[96] = t1_re_96_2;
assign Direct_Lookup_Table_n_D_1_t1_re[97] = t1_re_97_2;
assign Direct_Lookup_Table_n_D_1_t1_re[98] = t1_re_98_2;
assign Direct_Lookup_Table_n_D_1_t1_re[99] = t1_re_99_2;
assign Direct_Lookup_Table_n_D_1_t1_re[100] = t1_re_100_2;
assign Direct_Lookup_Table_n_D_1_t1_re[101] = t1_re_101_2;
assign Direct_Lookup_Table_n_D_1_t1_re[102] = t1_re_102_2;
assign Direct_Lookup_Table_n_D_1_t1_re[103] = t1_re_103_2;
assign Direct_Lookup_Table_n_D_1_t1_re[104] = t1_re_104_2;
assign Direct_Lookup_Table_n_D_1_t1_re[105] = t1_re_105_2;
assign Direct_Lookup_Table_n_D_1_t1_re[106] = t1_re_106_2;
assign Direct_Lookup_Table_n_D_1_t1_re[107] = t1_re_107_2;
assign Direct_Lookup_Table_n_D_1_t1_re[108] = t1_re_108_2;
assign Direct_Lookup_Table_n_D_1_t1_re[109] = t1_re_109_2;
assign Direct_Lookup_Table_n_D_1_t1_re[110] = t1_re_110_2;
assign Direct_Lookup_Table_n_D_1_t1_re[111] = t1_re_111_2;
assign Direct_Lookup_Table_n_D_1_t1_re[112] = t1_re_112_2;
assign Direct_Lookup_Table_n_D_1_t1_re[113] = t1_re_113_2;
assign Direct_Lookup_Table_n_D_1_t1_re[114] = t1_re_114_2;
assign Direct_Lookup_Table_n_D_1_t1_re[115] = t1_re_115_2;
assign Direct_Lookup_Table_n_D_1_t1_re[116] = t1_re_116_2;
assign Direct_Lookup_Table_n_D_1_t1_re[117] = t1_re_117_2;
assign Direct_Lookup_Table_n_D_1_t1_re[118] = t1_re_118_2;
assign Direct_Lookup_Table_n_D_1_t1_re[119] = t1_re_119_2;
assign Direct_Lookup_Table_n_D_1_t1_re[120] = t1_re_120_2;
assign Direct_Lookup_Table_n_D_1_t1_re[121] = t1_re_121_2;
assign Direct_Lookup_Table_n_D_1_t1_re[122] = t1_re_122_2;
assign Direct_Lookup_Table_n_D_1_t1_re[123] = t1_re_123_2;
assign Direct_Lookup_Table_n_D_1_t1_re[124] = t1_re_124_2;
assign Direct_Lookup_Table_n_D_1_t1_re[125] = t1_re_125_2;
assign Direct_Lookup_Table_n_D_1_t1_re[126] = t1_re_126_2;
assign Direct_Lookup_Table_n_D_1_t1_re[127] = t1_re_127_2;
assign Direct_Lookup_Table_n_D_1_t1_re[128] = t1_re_128_2;
assign Direct_Lookup_Table_n_D_1_t1_re[129] = t1_re_129_2;
assign Direct_Lookup_Table_n_D_1_t1_re[130] = t1_re_130_2;
assign Direct_Lookup_Table_n_D_1_t1_re[131] = t1_re_131_2;
assign Direct_Lookup_Table_n_D_1_t1_re[132] = t1_re_132_2;
assign Direct_Lookup_Table_n_D_1_t1_re[133] = t1_re_133_2;
assign Direct_Lookup_Table_n_D_1_t1_re[134] = t1_re_134_2;
assign Direct_Lookup_Table_n_D_1_t1_re[135] = t1_re_135_2;
assign Direct_Lookup_Table_n_D_1_t1_re[136] = t1_re_136_2;
assign Direct_Lookup_Table_n_D_1_t1_re[137] = t1_re_137_2;
assign Direct_Lookup_Table_n_D_1_t1_re[138] = t1_re_138_2;
assign Direct_Lookup_Table_n_D_1_t1_re[139] = t1_re_139_2;
assign Direct_Lookup_Table_n_D_1_t1_re[140] = t1_re_140_2;
assign Direct_Lookup_Table_n_D_1_t1_re[141] = t1_re_141_2;
assign Direct_Lookup_Table_n_D_1_t1_re[142] = t1_re_142_2;
assign Direct_Lookup_Table_n_D_1_t1_re[143] = t1_re_143_2;
assign Direct_Lookup_Table_n_D_1_t1_re[144] = t1_re_144_2;
assign Direct_Lookup_Table_n_D_1_t1_re[145] = t1_re_145_2;
assign Direct_Lookup_Table_n_D_1_t1_re[146] = t1_re_146_2;
assign Direct_Lookup_Table_n_D_1_t1_re[147] = t1_re_147_2;
assign Direct_Lookup_Table_n_D_1_t1_re[148] = t1_re_148_2;
assign Direct_Lookup_Table_n_D_1_t1_re[149] = t1_re_149_2;
assign Direct_Lookup_Table_n_D_1_t1_re[150] = t1_re_150_2;
assign Direct_Lookup_Table_n_D_1_t1_re[151] = t1_re_151_2;
assign Direct_Lookup_Table_n_D_1_t1_re[152] = t1_re_152_2;
assign Direct_Lookup_Table_n_D_1_t1_re[153] = t1_re_153_2;
assign Direct_Lookup_Table_n_D_1_t1_re[154] = t1_re_154_2;
assign Direct_Lookup_Table_n_D_1_t1_re[155] = t1_re_155_2;
assign Direct_Lookup_Table_n_D_1_t1_re[156] = t1_re_156_2;
assign Direct_Lookup_Table_n_D_1_t1_re[157] = t1_re_157_2;
assign Direct_Lookup_Table_n_D_1_t1_re[158] = t1_re_158_2;
assign Direct_Lookup_Table_n_D_1_t1_re[159] = t1_re_159_2;
assign Direct_Lookup_Table_n_D_1_t1_re[160] = t1_re_160_2;
assign Direct_Lookup_Table_n_D_1_t1_re[161] = t1_re_161_2;
assign Direct_Lookup_Table_n_D_1_t1_re[162] = t1_re_162_2;
assign Direct_Lookup_Table_n_D_1_t1_re[163] = t1_re_163_2;
assign Direct_Lookup_Table_n_D_1_t1_re[164] = t1_re_164_2;
assign Direct_Lookup_Table_n_D_1_t1_re[165] = t1_re_165_2;
assign Direct_Lookup_Table_n_D_1_t1_re[166] = t1_re_166_2;
assign Direct_Lookup_Table_n_D_1_t1_re[167] = t1_re_167_2;
assign Direct_Lookup_Table_n_D_1_t1_re[168] = t1_re_168_2;
assign Direct_Lookup_Table_n_D_1_t1_re[169] = t1_re_169_2;
assign Direct_Lookup_Table_n_D_1_t1_re[170] = t1_re_170_2;
assign Direct_Lookup_Table_n_D_1_t1_re[171] = t1_re_171_2;
assign Direct_Lookup_Table_n_D_1_t1_re[172] = t1_re_172_2;
assign Direct_Lookup_Table_n_D_1_t1_re[173] = t1_re_173_2;
assign Direct_Lookup_Table_n_D_1_t1_re[174] = t1_re_174_2;
assign Direct_Lookup_Table_n_D_1_t1_re[175] = t1_re_175_2;
assign Direct_Lookup_Table_n_D_1_t1_re[176] = t1_re_176_2;
assign Direct_Lookup_Table_n_D_1_t1_re[177] = t1_re_177_2;
assign Direct_Lookup_Table_n_D_1_t1_re[178] = t1_re_178_2;
assign Direct_Lookup_Table_n_D_1_t1_re[179] = t1_re_179_2;
assign Direct_Lookup_Table_n_D_1_t1_re[180] = t1_re_180_2;
assign Direct_Lookup_Table_n_D_1_t1_re[181] = t1_re_181_2;
assign Direct_Lookup_Table_n_D_1_t1_re[182] = t1_re_182_2;
assign Direct_Lookup_Table_n_D_1_t1_re[183] = t1_re_183_2;
assign Direct_Lookup_Table_n_D_1_t1_re[184] = t1_re_184_2;
assign Direct_Lookup_Table_n_D_1_t1_re[185] = t1_re_185_2;
assign Direct_Lookup_Table_n_D_1_t1_re[186] = t1_re_186_2;
assign Direct_Lookup_Table_n_D_1_t1_re[187] = t1_re_187_2;
assign Direct_Lookup_Table_n_D_1_t1_re[188] = t1_re_188_2;
assign Direct_Lookup_Table_n_D_1_t1_re[189] = t1_re_189_2;
assign Direct_Lookup_Table_n_D_1_t1_re[190] = t1_re_190_2;
assign Direct_Lookup_Table_n_D_1_t1_re[191] = t1_re_191_2;
assign Direct_Lookup_Table_n_D_1_t1_re[192] = t1_re_192_2;
assign Direct_Lookup_Table_n_D_1_t1_re[193] = t1_re_193_2;
assign Direct_Lookup_Table_n_D_1_t1_re[194] = t1_re_194_2;
assign Direct_Lookup_Table_n_D_1_t1_re[195] = t1_re_195_2;
assign Direct_Lookup_Table_n_D_1_t1_re[196] = t1_re_196_2;
assign Direct_Lookup_Table_n_D_1_t1_re[197] = t1_re_197_2;
assign Direct_Lookup_Table_n_D_1_t1_re[198] = t1_re_198_2;
assign Direct_Lookup_Table_n_D_1_t1_re[199] = t1_re_199_2;
assign Direct_Lookup_Table_n_D_1_t1_re[200] = t1_re_200_2;
assign Direct_Lookup_Table_n_D_1_t1_re[201] = t1_re_201_2;
assign Direct_Lookup_Table_n_D_1_t1_re[202] = t1_re_202_2;
assign Direct_Lookup_Table_n_D_1_t1_re[203] = t1_re_203_2;
assign Direct_Lookup_Table_n_D_1_t1_re[204] = t1_re_204_2;
assign Direct_Lookup_Table_n_D_1_t1_re[205] = t1_re_205_2;
assign Direct_Lookup_Table_n_D_1_t1_re[206] = t1_re_206_2;
assign Direct_Lookup_Table_n_D_1_t1_re[207] = t1_re_207_2;
assign Direct_Lookup_Table_n_D_1_t1_re[208] = t1_re_208_2;
assign Direct_Lookup_Table_n_D_1_t1_re[209] = t1_re_209_2;
assign Direct_Lookup_Table_n_D_1_t1_re[210] = t1_re_210_2;
assign Direct_Lookup_Table_n_D_1_t1_re[211] = t1_re_211_2;
assign Direct_Lookup_Table_n_D_1_t1_re[212] = t1_re_212_2;
assign Direct_Lookup_Table_n_D_1_t1_re[213] = t1_re_213_2;
assign Direct_Lookup_Table_n_D_1_t1_re[214] = t1_re_214_2;
assign Direct_Lookup_Table_n_D_1_t1_re[215] = t1_re_215_2;
assign Direct_Lookup_Table_n_D_1_t1_re[216] = t1_re_216_2;
assign Direct_Lookup_Table_n_D_1_t1_re[217] = t1_re_217_2;
assign Direct_Lookup_Table_n_D_1_t1_re[218] = t1_re_218_2;
assign Direct_Lookup_Table_n_D_1_t1_re[219] = t1_re_219_2;
assign Direct_Lookup_Table_n_D_1_t1_re[220] = t1_re_220_2;
assign Direct_Lookup_Table_n_D_1_t1_re[221] = t1_re_221_2;
assign Direct_Lookup_Table_n_D_1_t1_re[222] = t1_re_222_2;
assign Direct_Lookup_Table_n_D_1_t1_re[223] = t1_re_223_2;
assign Direct_Lookup_Table_n_D_1_t1_re[224] = t1_re_224_2;
assign Direct_Lookup_Table_n_D_1_t1_re[225] = t1_re_225_2;
assign Direct_Lookup_Table_n_D_1_t1_re[226] = t1_re_226_2;
assign Direct_Lookup_Table_n_D_1_t1_re[227] = t1_re_227_2;
assign Direct_Lookup_Table_n_D_1_t1_re[228] = t1_re_228_2;
assign Direct_Lookup_Table_n_D_1_t1_re[229] = t1_re_229_2;
assign Direct_Lookup_Table_n_D_1_t1_re[230] = t1_re_230_2;
assign Direct_Lookup_Table_n_D_1_t1_re[231] = t1_re_231_2;
assign Direct_Lookup_Table_n_D_1_t1_re[232] = t1_re_232_2;
assign Direct_Lookup_Table_n_D_1_t1_re[233] = t1_re_233_2;
assign Direct_Lookup_Table_n_D_1_t1_re[234] = t1_re_234_2;
assign Direct_Lookup_Table_n_D_1_t1_re[235] = t1_re_235_2;
assign Direct_Lookup_Table_n_D_1_t1_re[236] = t1_re_236_2;
assign Direct_Lookup_Table_n_D_1_t1_re[237] = t1_re_237_2;
assign Direct_Lookup_Table_n_D_1_t1_re[238] = t1_re_238_2;
assign Direct_Lookup_Table_n_D_1_t1_re[239] = t1_re_239_2;
assign Direct_Lookup_Table_n_D_1_t1_re[240] = t1_re_240_2;
assign Direct_Lookup_Table_n_D_1_t1_re[241] = t1_re_241_2;
assign Direct_Lookup_Table_n_D_1_t1_re[242] = t1_re_242_2;
assign Direct_Lookup_Table_n_D_1_t1_re[243] = t1_re_243_2;
assign Direct_Lookup_Table_n_D_1_t1_re[244] = t1_re_244_2;
assign Direct_Lookup_Table_n_D_1_t1_re[245] = t1_re_245_2;
assign Direct_Lookup_Table_n_D_1_t1_re[246] = t1_re_246_2;
assign Direct_Lookup_Table_n_D_1_t1_re[247] = t1_re_247_2;
assign Direct_Lookup_Table_n_D_1_t1_re[248] = t1_re_248_2;
assign Direct_Lookup_Table_n_D_1_t1_re[249] = t1_re_249_2;
assign Direct_Lookup_Table_n_D_1_t1_re[250] = t1_re_250_2;
assign Direct_Lookup_Table_n_D_1_t1_re[251] = t1_re_251_2;
assign Direct_Lookup_Table_n_D_1_t1_re[252] = t1_re_252_2;
assign Direct_Lookup_Table_n_D_1_t1_re[253] = t1_re_253_2;
assign Direct_Lookup_Table_n_D_1_t1_re[254] = t1_re_254_2;
assign Direct_Lookup_Table_n_D_1_t1_re[255] = t1_re_255_2;
assign Direct_Lookup_Table_n_D_1_t1_re[256] = t1_re_256_2;
assign Direct_Lookup_Table_n_D_1_t1_re[257] = t1_re_257_2;
assign Direct_Lookup_Table_n_D_1_t1_re[258] = t1_re_258_2;
assign Direct_Lookup_Table_n_D_1_t1_re[259] = t1_re_259_2;
assign Direct_Lookup_Table_n_D_1_t1_re[260] = t1_re_260_2;
assign Direct_Lookup_Table_n_D_1_t1_re[261] = t1_re_261_2;
assign Direct_Lookup_Table_n_D_1_t1_re[262] = t1_re_262_2;
assign Direct_Lookup_Table_n_D_1_t1_re[263] = t1_re_263_2;
assign Direct_Lookup_Table_n_D_1_t1_re[264] = t1_re_264_2;
assign Direct_Lookup_Table_n_D_1_t1_re[265] = t1_re_265_2;
assign Direct_Lookup_Table_n_D_1_t1_re[266] = t1_re_266_2;
assign Direct_Lookup_Table_n_D_1_t1_re[267] = t1_re_267_2;
assign Direct_Lookup_Table_n_D_1_t1_re[268] = t1_re_268_2;
assign Direct_Lookup_Table_n_D_1_t1_re[269] = t1_re_269_2;
assign Direct_Lookup_Table_n_D_1_t1_re[270] = t1_re_270_2;
assign Direct_Lookup_Table_n_D_1_t1_re[271] = t1_re_271_2;
assign Direct_Lookup_Table_n_D_1_t1_re[272] = t1_re_272_2;
assign Direct_Lookup_Table_n_D_1_t1_re[273] = t1_re_273_2;
assign Direct_Lookup_Table_n_D_1_t1_re[274] = t1_re_274_2;
assign Direct_Lookup_Table_n_D_1_t1_re[275] = t1_re_275_2;
assign Direct_Lookup_Table_n_D_1_t1_re[276] = t1_re_276_2;
assign Direct_Lookup_Table_n_D_1_t1_re[277] = t1_re_277_2;
assign Direct_Lookup_Table_n_D_1_t1_re[278] = t1_re_278_2;
assign Direct_Lookup_Table_n_D_1_t1_re[279] = t1_re_279_2;
assign Direct_Lookup_Table_n_D_1_t1_re[280] = t1_re_280_2;
assign Direct_Lookup_Table_n_D_1_t1_re[281] = t1_re_281_2;
assign Direct_Lookup_Table_n_D_1_t1_re[282] = t1_re_282_2;
assign Direct_Lookup_Table_n_D_1_t1_re[283] = t1_re_283_2;
assign Direct_Lookup_Table_n_D_1_t1_re[284] = t1_re_284_2;
assign Direct_Lookup_Table_n_D_1_t1_re[285] = t1_re_285_2;
assign Direct_Lookup_Table_n_D_1_t1_re[286] = t1_re_286_2;
assign Direct_Lookup_Table_n_D_1_t1_re[287] = t1_re_287_2;
assign Direct_Lookup_Table_n_D_1_t1_re[288] = t1_re_288_2;
assign Direct_Lookup_Table_n_D_1_t1_re[289] = t1_re_289_2;
assign Direct_Lookup_Table_n_D_1_t1_re[290] = t1_re_290_2;
assign Direct_Lookup_Table_n_D_1_t1_re[291] = t1_re_291_2;
assign Direct_Lookup_Table_n_D_1_t1_re[292] = t1_re_292_2;
assign Direct_Lookup_Table_n_D_1_t1_re[293] = t1_re_293_2;
assign Direct_Lookup_Table_n_D_1_t1_re[294] = t1_re_294_2;
assign Direct_Lookup_Table_n_D_1_t1_re[295] = t1_re_295_2;
assign Direct_Lookup_Table_n_D_1_t1_re[296] = t1_re_296_2;
assign Direct_Lookup_Table_n_D_1_t1_re[297] = t1_re_297_2;
assign Direct_Lookup_Table_n_D_1_t1_re[298] = t1_re_298_2;
assign Direct_Lookup_Table_n_D_1_t1_re[299] = t1_re_299_2;
assign Direct_Lookup_Table_n_D_1_t1_re[300] = t1_re_300_2;
assign Direct_Lookup_Table_n_D_1_t1_re[301] = t1_re_301_2;
assign Direct_Lookup_Table_n_D_1_t1_re[302] = t1_re_302_2;
assign Direct_Lookup_Table_n_D_1_t1_re[303] = t1_re_303_2;
assign Direct_Lookup_Table_n_D_1_t1_re[304] = t1_re_304_2;
assign Direct_Lookup_Table_n_D_1_t1_re[305] = t1_re_305_2;
assign Direct_Lookup_Table_n_D_1_t1_re[306] = t1_re_306_2;
assign Direct_Lookup_Table_n_D_1_t1_re[307] = t1_re_307_2;
assign Direct_Lookup_Table_n_D_1_t1_re[308] = t1_re_308_2;
assign Direct_Lookup_Table_n_D_1_t1_re[309] = t1_re_309_2;
assign Direct_Lookup_Table_n_D_1_t1_re[310] = t1_re_310_2;
assign Direct_Lookup_Table_n_D_1_t1_re[311] = t1_re_311_2;
assign Direct_Lookup_Table_n_D_1_t1_re[312] = t1_re_312_2;
assign Direct_Lookup_Table_n_D_1_t1_re[313] = t1_re_313_2;
assign Direct_Lookup_Table_n_D_1_t1_re[314] = t1_re_314_2;
assign Direct_Lookup_Table_n_D_1_t1_re[315] = t1_re_315_2;
assign Direct_Lookup_Table_n_D_1_t1_re[316] = t1_re_316_2;
assign Direct_Lookup_Table_n_D_1_t1_re[317] = t1_re_317_2;
assign Direct_Lookup_Table_n_D_1_t1_re[318] = t1_re_318_2;
assign Direct_Lookup_Table_n_D_1_t1_re[319] = t1_re_319_2;
assign Direct_Lookup_Table_n_D_1_t1_re[320] = t1_re_320_2;
assign Direct_Lookup_Table_n_D_1_t1_re[321] = t1_re_321_2;
assign Direct_Lookup_Table_n_D_1_t1_re[322] = t1_re_322_2;
assign Direct_Lookup_Table_n_D_1_t1_re[323] = t1_re_323_2;
assign Direct_Lookup_Table_n_D_1_t1_re[324] = t1_re_324_2;
assign Direct_Lookup_Table_n_D_1_t1_re[325] = t1_re_325_2;
assign Direct_Lookup_Table_n_D_1_t1_re[326] = t1_re_326_2;
assign Direct_Lookup_Table_n_D_1_t1_re[327] = t1_re_327_2;
assign Direct_Lookup_Table_n_D_1_t1_re[328] = t1_re_328_2;
assign Direct_Lookup_Table_n_D_1_t1_re[329] = t1_re_329_2;
assign Direct_Lookup_Table_n_D_1_t1_re[330] = t1_re_330_2;
assign Direct_Lookup_Table_n_D_1_t1_re[331] = t1_re_331_2;
assign Direct_Lookup_Table_n_D_1_t1_re[332] = t1_re_332_2;
assign Direct_Lookup_Table_n_D_1_t1_re[333] = t1_re_333_2;
assign Direct_Lookup_Table_n_D_1_t1_re[334] = t1_re_334_2;
assign Direct_Lookup_Table_n_D_1_t1_re[335] = t1_re_335_2;
assign Direct_Lookup_Table_n_D_1_t1_re[336] = t1_re_336_2;
assign Direct_Lookup_Table_n_D_1_t1_re[337] = t1_re_337_2;
assign Direct_Lookup_Table_n_D_1_t1_re[338] = t1_re_338_2;
assign Direct_Lookup_Table_n_D_1_t1_re[339] = t1_re_339_2;
assign Direct_Lookup_Table_n_D_1_t1_re[340] = t1_re_340_2;
assign Direct_Lookup_Table_n_D_1_t1_re[341] = t1_re_341_2;
assign Direct_Lookup_Table_n_D_1_t1_re[342] = t1_re_342_2;
assign Direct_Lookup_Table_n_D_1_t1_re[343] = t1_re_343_2;
assign Direct_Lookup_Table_n_D_1_t1_re[344] = t1_re_344_2;
assign Direct_Lookup_Table_n_D_1_t1_re[345] = t1_re_345_2;
assign Direct_Lookup_Table_n_D_1_t1_re[346] = t1_re_346_2;
assign Direct_Lookup_Table_n_D_1_t1_re[347] = t1_re_347_2;
assign Direct_Lookup_Table_n_D_1_t1_re[348] = t1_re_348_2;
assign Direct_Lookup_Table_n_D_1_t1_re[349] = t1_re_349_2;
assign Direct_Lookup_Table_n_D_1_t1_re[350] = t1_re_350_2;
assign Direct_Lookup_Table_n_D_1_t1_re[351] = t1_re_351_2;
assign Direct_Lookup_Table_n_D_1_t1_re[352] = t1_re_352_2;
assign Direct_Lookup_Table_n_D_1_t1_re[353] = t1_re_353_2;
assign Direct_Lookup_Table_n_D_1_t1_re[354] = t1_re_354_2;
assign Direct_Lookup_Table_n_D_1_t1_re[355] = t1_re_355_2;
assign Direct_Lookup_Table_n_D_1_t1_re[356] = t1_re_356_2;
assign Direct_Lookup_Table_n_D_1_t1_re[357] = t1_re_357_2;
assign Direct_Lookup_Table_n_D_1_t1_re[358] = t1_re_358_2;
assign Direct_Lookup_Table_n_D_1_t1_re[359] = t1_re_359_2;
assign Direct_Lookup_Table_n_D_1_t1_re[360] = t1_re_360_2;
assign Direct_Lookup_Table_n_D_1_t1_re[361] = t1_re_361_2;
assign Direct_Lookup_Table_n_D_1_t1_re[362] = t1_re_362_2;
assign Direct_Lookup_Table_n_D_1_t1_re[363] = t1_re_363_2;
assign Direct_Lookup_Table_n_D_1_t1_re[364] = t1_re_364_2;
assign Direct_Lookup_Table_n_D_1_t1_re[365] = t1_re_365_2;
assign Direct_Lookup_Table_n_D_1_t1_re[366] = t1_re_366_2;
assign Direct_Lookup_Table_n_D_1_t1_re[367] = t1_re_367_2;
assign Direct_Lookup_Table_n_D_1_t1_re[368] = t1_re_368_2;
assign Direct_Lookup_Table_n_D_1_t1_re[369] = t1_re_369_2;
assign Direct_Lookup_Table_n_D_1_t1_re[370] = t1_re_370_2;
assign Direct_Lookup_Table_n_D_1_t1_re[371] = t1_re_371_2;
assign Direct_Lookup_Table_n_D_1_t1_re[372] = t1_re_372_2;
assign Direct_Lookup_Table_n_D_1_t1_re[373] = t1_re_373_2;
assign Direct_Lookup_Table_n_D_1_t1_re[374] = t1_re_374_2;
assign Direct_Lookup_Table_n_D_1_t1_re[375] = t1_re_375_2;
assign Direct_Lookup_Table_n_D_1_t1_re[376] = t1_re_376_2;
assign Direct_Lookup_Table_n_D_1_t1_re[377] = t1_re_377_2;
assign Direct_Lookup_Table_n_D_1_t1_re[378] = t1_re_378_2;
assign Direct_Lookup_Table_n_D_1_t1_re[379] = t1_re_379_2;
assign Direct_Lookup_Table_n_D_1_t1_re[380] = t1_re_380_2;
assign Direct_Lookup_Table_n_D_1_t1_re[381] = t1_re_381_2;
assign Direct_Lookup_Table_n_D_1_t1_re[382] = t1_re_382_2;
assign Direct_Lookup_Table_n_D_1_t1_re[383] = t1_re_383_2;
assign Direct_Lookup_Table_n_D_1_t1_re[384] = t1_re_384_2;
assign Direct_Lookup_Table_n_D_1_t1_re[385] = t1_re_385_2;
assign Direct_Lookup_Table_n_D_1_t1_re[386] = t1_re_386_2;
assign Direct_Lookup_Table_n_D_1_t1_re[387] = t1_re_387_2;
assign Direct_Lookup_Table_n_D_1_t1_re[388] = t1_re_388_2;
assign Direct_Lookup_Table_n_D_1_t1_re[389] = t1_re_389_2;
assign Direct_Lookup_Table_n_D_1_t1_re[390] = t1_re_390_2;
assign Direct_Lookup_Table_n_D_1_t1_re[391] = t1_re_391_2;
assign Direct_Lookup_Table_n_D_1_t1_re[392] = t1_re_392_2;
assign Direct_Lookup_Table_n_D_1_t1_re[393] = t1_re_393_2;
assign Direct_Lookup_Table_n_D_1_t1_re[394] = t1_re_394_2;
assign Direct_Lookup_Table_n_D_1_t1_re[395] = t1_re_395_2;
assign Direct_Lookup_Table_n_D_1_t1_re[396] = t1_re_396_2;
assign Direct_Lookup_Table_n_D_1_t1_re[397] = t1_re_397_2;
assign Direct_Lookup_Table_n_D_1_t1_re[398] = t1_re_398_2;
assign Direct_Lookup_Table_n_D_1_t1_re[399] = t1_re_399_2;
assign Direct_Lookup_Table_n_D_1_t1_re[400] = t1_re_400_2;
assign Direct_Lookup_Table_n_D_1_t1_re[401] = t1_re_401_2;
assign Direct_Lookup_Table_n_D_1_t1_re[402] = t1_re_402_2;
assign Direct_Lookup_Table_n_D_1_t1_re[403] = t1_re_403_2;
assign Direct_Lookup_Table_n_D_1_t1_re[404] = t1_re_404_2;
assign Direct_Lookup_Table_n_D_1_t1_re[405] = t1_re_405_2;
assign Direct_Lookup_Table_n_D_1_t1_re[406] = t1_re_406_2;
assign Direct_Lookup_Table_n_D_1_t1_re[407] = t1_re_407_2;
assign Direct_Lookup_Table_n_D_1_t1_re[408] = t1_re_408_2;
assign Direct_Lookup_Table_n_D_1_t1_re[409] = t1_re_409_2;
assign Direct_Lookup_Table_n_D_1_t1_re[410] = t1_re_410_2;
assign Direct_Lookup_Table_n_D_1_t1_re[411] = t1_re_411_2;
assign Direct_Lookup_Table_n_D_1_t1_re[412] = t1_re_412_2;
assign Direct_Lookup_Table_n_D_1_t1_re[413] = t1_re_413_2;
assign Direct_Lookup_Table_n_D_1_t1_re[414] = t1_re_414_2;
assign Direct_Lookup_Table_n_D_1_t1_re[415] = t1_re_415_2;
assign Direct_Lookup_Table_n_D_1_t1_re[416] = t1_re_416_2;
assign Direct_Lookup_Table_n_D_1_t1_re[417] = t1_re_417_2;
assign Direct_Lookup_Table_n_D_1_t1_re[418] = t1_re_418_2;
assign Direct_Lookup_Table_n_D_1_t1_re[419] = t1_re_419_2;
assign Direct_Lookup_Table_n_D_1_t1_re[420] = t1_re_420_2;
assign Direct_Lookup_Table_n_D_1_t1_re[421] = t1_re_421_2;
assign Direct_Lookup_Table_n_D_1_t1_re[422] = t1_re_422_2;
assign Direct_Lookup_Table_n_D_1_t1_re[423] = t1_re_423_2;
assign Direct_Lookup_Table_n_D_1_t1_re[424] = t1_re_424_2;
assign Direct_Lookup_Table_n_D_1_t1_re[425] = t1_re_425_2;
assign Direct_Lookup_Table_n_D_1_t1_re[426] = t1_re_426_2;
assign Direct_Lookup_Table_n_D_1_t1_re[427] = t1_re_427_2;
assign Direct_Lookup_Table_n_D_1_t1_re[428] = t1_re_428_2;
assign Direct_Lookup_Table_n_D_1_t1_re[429] = t1_re_429_2;
assign Direct_Lookup_Table_n_D_1_t1_re[430] = t1_re_430_2;
assign Direct_Lookup_Table_n_D_1_t1_re[431] = t1_re_431_2;
assign Direct_Lookup_Table_n_D_1_t1_re[432] = t1_re_432_2;
assign Direct_Lookup_Table_n_D_1_t1_re[433] = t1_re_433_2;
assign Direct_Lookup_Table_n_D_1_t1_re[434] = t1_re_434_2;
assign Direct_Lookup_Table_n_D_1_t1_re[435] = t1_re_435_2;
assign Direct_Lookup_Table_n_D_1_t1_re[436] = t1_re_436_2;
assign Direct_Lookup_Table_n_D_1_t1_re[437] = t1_re_437_2;
assign Direct_Lookup_Table_n_D_1_t1_re[438] = t1_re_438_2;
assign Direct_Lookup_Table_n_D_1_t1_re[439] = t1_re_439_2;
assign Direct_Lookup_Table_n_D_1_t1_re[440] = t1_re_440_2;
assign Direct_Lookup_Table_n_D_1_t1_re[441] = t1_re_441_2;
assign Direct_Lookup_Table_n_D_1_t1_re[442] = t1_re_442_2;
assign Direct_Lookup_Table_n_D_1_t1_re[443] = t1_re_443_2;
assign Direct_Lookup_Table_n_D_1_t1_re[444] = t1_re_444_2;
assign Direct_Lookup_Table_n_D_1_t1_re[445] = t1_re_445_2;
assign Direct_Lookup_Table_n_D_1_t1_re[446] = t1_re_446_2;
assign Direct_Lookup_Table_n_D_1_t1_re[447] = t1_re_447_2;
assign Direct_Lookup_Table_n_D_1_t1_re[448] = t1_re_448_2;
assign Direct_Lookup_Table_n_D_1_t1_re[449] = t1_re_449_2;
assign Direct_Lookup_Table_n_D_1_t1_re[450] = t1_re_450_2;
assign Direct_Lookup_Table_n_D_1_t1_re[451] = t1_re_451_2;
assign Direct_Lookup_Table_n_D_1_t1_re[452] = t1_re_452_2;
assign Direct_Lookup_Table_n_D_1_t1_re[453] = t1_re_453_2;
assign Direct_Lookup_Table_n_D_1_t1_re[454] = t1_re_454_2;
assign Direct_Lookup_Table_n_D_1_t1_re[455] = t1_re_455_2;
assign Direct_Lookup_Table_n_D_1_t1_re[456] = t1_re_456_2;
assign Direct_Lookup_Table_n_D_1_t1_re[457] = t1_re_457_2;
assign Direct_Lookup_Table_n_D_1_t1_re[458] = t1_re_458_2;
assign Direct_Lookup_Table_n_D_1_t1_re[459] = t1_re_459_2;
assign Direct_Lookup_Table_n_D_1_t1_re[460] = t1_re_460_2;
assign Direct_Lookup_Table_n_D_1_t1_re[461] = t1_re_461_2;
assign Direct_Lookup_Table_n_D_1_t1_re[462] = t1_re_462_2;
assign Direct_Lookup_Table_n_D_1_t1_re[463] = t1_re_463_2;
assign Direct_Lookup_Table_n_D_1_t1_re[464] = t1_re_464_2;
assign Direct_Lookup_Table_n_D_1_t1_re[465] = t1_re_465_2;
assign Direct_Lookup_Table_n_D_1_t1_re[466] = t1_re_466_2;
assign Direct_Lookup_Table_n_D_1_t1_re[467] = t1_re_467_2;
assign Direct_Lookup_Table_n_D_1_t1_re[468] = t1_re_468_2;
assign Direct_Lookup_Table_n_D_1_t1_re[469] = t1_re_469_2;
assign Direct_Lookup_Table_n_D_1_t1_re[470] = t1_re_470_2;
assign Direct_Lookup_Table_n_D_1_t1_re[471] = t1_re_471_2;
assign Direct_Lookup_Table_n_D_1_t1_re[472] = t1_re_472_2;
assign Direct_Lookup_Table_n_D_1_t1_re[473] = t1_re_473_2;
assign Direct_Lookup_Table_n_D_1_t1_re[474] = t1_re_474_2;
assign Direct_Lookup_Table_n_D_1_t1_re[475] = t1_re_475_2;
assign Direct_Lookup_Table_n_D_1_t1_re[476] = t1_re_476_2;
assign Direct_Lookup_Table_n_D_1_t1_re[477] = t1_re_477_2;
assign Direct_Lookup_Table_n_D_1_t1_re[478] = t1_re_478_2;
assign Direct_Lookup_Table_n_D_1_t1_re[479] = t1_re_479_2;
assign Direct_Lookup_Table_n_D_1_t1_re[480] = t1_re_480_2;
assign Direct_Lookup_Table_n_D_1_t1_re[481] = t1_re_481_2;
assign Direct_Lookup_Table_n_D_1_t1_re[482] = t1_re_482_2;
assign Direct_Lookup_Table_n_D_1_t1_re[483] = t1_re_483_2;
assign Direct_Lookup_Table_n_D_1_t1_re[484] = t1_re_484_2;
assign Direct_Lookup_Table_n_D_1_t1_re[485] = t1_re_485_2;
assign Direct_Lookup_Table_n_D_1_t1_re[486] = t1_re_486_2;
assign Direct_Lookup_Table_n_D_1_t1_re[487] = t1_re_487_2;
assign Direct_Lookup_Table_n_D_1_t1_re[488] = t1_re_488_2;
assign Direct_Lookup_Table_n_D_1_t1_re[489] = t1_re_489_2;
assign Direct_Lookup_Table_n_D_1_t1_re[490] = t1_re_490_2;
assign Direct_Lookup_Table_n_D_1_t1_re[491] = t1_re_491_2;
assign Direct_Lookup_Table_n_D_1_t1_re[492] = t1_re_492_2;
assign Direct_Lookup_Table_n_D_1_t1_re[493] = t1_re_493_2;
assign Direct_Lookup_Table_n_D_1_t1_re[494] = t1_re_494_2;
assign Direct_Lookup_Table_n_D_1_t1_re[495] = t1_re_495_2;
assign Direct_Lookup_Table_n_D_1_t1_re[496] = t1_re_496_2;
assign Direct_Lookup_Table_n_D_1_t1_re[497] = t1_re_497_2;
assign Direct_Lookup_Table_n_D_1_t1_re[498] = t1_re_498_2;
assign Direct_Lookup_Table_n_D_1_t1_re[499] = t1_re_499_2;
assign Direct_Lookup_Table_n_D_1_t1_re[500] = t1_re_500_2;
assign Direct_Lookup_Table_n_D_1_t1_re[501] = t1_re_501_2;
assign Direct_Lookup_Table_n_D_1_t1_re[502] = t1_re_502_2;
assign Direct_Lookup_Table_n_D_1_t1_re[503] = t1_re_503_2;
assign Direct_Lookup_Table_n_D_1_t1_re[504] = t1_re_504_2;
assign Direct_Lookup_Table_n_D_1_t1_re[505] = t1_re_505_2;
assign Direct_Lookup_Table_n_D_1_t1_re[506] = t1_re_506_2;
assign Direct_Lookup_Table_n_D_1_t1_re[507] = t1_re_507_2;
assign Direct_Lookup_Table_n_D_1_t1_re[508] = t1_re_508_2;
assign Direct_Lookup_Table_n_D_1_t1_re[509] = t1_re_509_2;
assign Direct_Lookup_Table_n_D_1_t1_re[510] = t1_re_510_2;
assign Direct_Lookup_Table_n_D_1_t1_re[511] = t1_re_511_2;
assign Direct_Lookup_Table_n_D_1_t1_im[0] = t1_im_0_2;
assign Direct_Lookup_Table_n_D_1_t1_im[1] = t1_im_1_2;
assign Direct_Lookup_Table_n_D_1_t1_im[2] = t1_im_2_2;
assign Direct_Lookup_Table_n_D_1_t1_im[3] = t1_im_3_2;
assign Direct_Lookup_Table_n_D_1_t1_im[4] = t1_im_4_2;
assign Direct_Lookup_Table_n_D_1_t1_im[5] = t1_im_5_2;
assign Direct_Lookup_Table_n_D_1_t1_im[6] = t1_im_6_2;
assign Direct_Lookup_Table_n_D_1_t1_im[7] = t1_im_7_2;
assign Direct_Lookup_Table_n_D_1_t1_im[8] = t1_im_8_2;
assign Direct_Lookup_Table_n_D_1_t1_im[9] = t1_im_9_2;
assign Direct_Lookup_Table_n_D_1_t1_im[10] = t1_im_10_2;
assign Direct_Lookup_Table_n_D_1_t1_im[11] = t1_im_11_2;
assign Direct_Lookup_Table_n_D_1_t1_im[12] = t1_im_12_2;
assign Direct_Lookup_Table_n_D_1_t1_im[13] = t1_im_13_2;
assign Direct_Lookup_Table_n_D_1_t1_im[14] = t1_im_14_2;
assign Direct_Lookup_Table_n_D_1_t1_im[15] = t1_im_15_2;
assign Direct_Lookup_Table_n_D_1_t1_im[16] = t1_im_16_2;
assign Direct_Lookup_Table_n_D_1_t1_im[17] = t1_im_17_2;
assign Direct_Lookup_Table_n_D_1_t1_im[18] = t1_im_18_2;
assign Direct_Lookup_Table_n_D_1_t1_im[19] = t1_im_19_2;
assign Direct_Lookup_Table_n_D_1_t1_im[20] = t1_im_20_2;
assign Direct_Lookup_Table_n_D_1_t1_im[21] = t1_im_21_2;
assign Direct_Lookup_Table_n_D_1_t1_im[22] = t1_im_22_2;
assign Direct_Lookup_Table_n_D_1_t1_im[23] = t1_im_23_2;
assign Direct_Lookup_Table_n_D_1_t1_im[24] = t1_im_24_2;
assign Direct_Lookup_Table_n_D_1_t1_im[25] = t1_im_25_2;
assign Direct_Lookup_Table_n_D_1_t1_im[26] = t1_im_26_2;
assign Direct_Lookup_Table_n_D_1_t1_im[27] = t1_im_27_2;
assign Direct_Lookup_Table_n_D_1_t1_im[28] = t1_im_28_2;
assign Direct_Lookup_Table_n_D_1_t1_im[29] = t1_im_29_2;
assign Direct_Lookup_Table_n_D_1_t1_im[30] = t1_im_30_2;
assign Direct_Lookup_Table_n_D_1_t1_im[31] = t1_im_31_2;
assign Direct_Lookup_Table_n_D_1_t1_im[32] = t1_im_32_2;
assign Direct_Lookup_Table_n_D_1_t1_im[33] = t1_im_33_2;
assign Direct_Lookup_Table_n_D_1_t1_im[34] = t1_im_34_2;
assign Direct_Lookup_Table_n_D_1_t1_im[35] = t1_im_35_2;
assign Direct_Lookup_Table_n_D_1_t1_im[36] = t1_im_36_2;
assign Direct_Lookup_Table_n_D_1_t1_im[37] = t1_im_37_2;
assign Direct_Lookup_Table_n_D_1_t1_im[38] = t1_im_38_2;
assign Direct_Lookup_Table_n_D_1_t1_im[39] = t1_im_39_2;
assign Direct_Lookup_Table_n_D_1_t1_im[40] = t1_im_40_2;
assign Direct_Lookup_Table_n_D_1_t1_im[41] = t1_im_41_2;
assign Direct_Lookup_Table_n_D_1_t1_im[42] = t1_im_42_2;
assign Direct_Lookup_Table_n_D_1_t1_im[43] = t1_im_43_2;
assign Direct_Lookup_Table_n_D_1_t1_im[44] = t1_im_44_2;
assign Direct_Lookup_Table_n_D_1_t1_im[45] = t1_im_45_2;
assign Direct_Lookup_Table_n_D_1_t1_im[46] = t1_im_46_2;
assign Direct_Lookup_Table_n_D_1_t1_im[47] = t1_im_47_2;
assign Direct_Lookup_Table_n_D_1_t1_im[48] = t1_im_48_2;
assign Direct_Lookup_Table_n_D_1_t1_im[49] = t1_im_49_2;
assign Direct_Lookup_Table_n_D_1_t1_im[50] = t1_im_50_2;
assign Direct_Lookup_Table_n_D_1_t1_im[51] = t1_im_51_2;
assign Direct_Lookup_Table_n_D_1_t1_im[52] = t1_im_52_2;
assign Direct_Lookup_Table_n_D_1_t1_im[53] = t1_im_53_2;
assign Direct_Lookup_Table_n_D_1_t1_im[54] = t1_im_54_2;
assign Direct_Lookup_Table_n_D_1_t1_im[55] = t1_im_55_2;
assign Direct_Lookup_Table_n_D_1_t1_im[56] = t1_im_56_2;
assign Direct_Lookup_Table_n_D_1_t1_im[57] = t1_im_57_2;
assign Direct_Lookup_Table_n_D_1_t1_im[58] = t1_im_58_2;
assign Direct_Lookup_Table_n_D_1_t1_im[59] = t1_im_59_2;
assign Direct_Lookup_Table_n_D_1_t1_im[60] = t1_im_60_2;
assign Direct_Lookup_Table_n_D_1_t1_im[61] = t1_im_61_2;
assign Direct_Lookup_Table_n_D_1_t1_im[62] = t1_im_62_2;
assign Direct_Lookup_Table_n_D_1_t1_im[63] = t1_im_63_2;
assign Direct_Lookup_Table_n_D_1_t1_im[64] = t1_im_64_2;
assign Direct_Lookup_Table_n_D_1_t1_im[65] = t1_im_65_2;
assign Direct_Lookup_Table_n_D_1_t1_im[66] = t1_im_66_2;
assign Direct_Lookup_Table_n_D_1_t1_im[67] = t1_im_67_2;
assign Direct_Lookup_Table_n_D_1_t1_im[68] = t1_im_68_2;
assign Direct_Lookup_Table_n_D_1_t1_im[69] = t1_im_69_2;
assign Direct_Lookup_Table_n_D_1_t1_im[70] = t1_im_70_2;
assign Direct_Lookup_Table_n_D_1_t1_im[71] = t1_im_71_2;
assign Direct_Lookup_Table_n_D_1_t1_im[72] = t1_im_72_2;
assign Direct_Lookup_Table_n_D_1_t1_im[73] = t1_im_73_2;
assign Direct_Lookup_Table_n_D_1_t1_im[74] = t1_im_74_2;
assign Direct_Lookup_Table_n_D_1_t1_im[75] = t1_im_75_2;
assign Direct_Lookup_Table_n_D_1_t1_im[76] = t1_im_76_2;
assign Direct_Lookup_Table_n_D_1_t1_im[77] = t1_im_77_2;
assign Direct_Lookup_Table_n_D_1_t1_im[78] = t1_im_78_2;
assign Direct_Lookup_Table_n_D_1_t1_im[79] = t1_im_79_2;
assign Direct_Lookup_Table_n_D_1_t1_im[80] = t1_im_80_2;
assign Direct_Lookup_Table_n_D_1_t1_im[81] = t1_im_81_2;
assign Direct_Lookup_Table_n_D_1_t1_im[82] = t1_im_82_2;
assign Direct_Lookup_Table_n_D_1_t1_im[83] = t1_im_83_2;
assign Direct_Lookup_Table_n_D_1_t1_im[84] = t1_im_84_2;
assign Direct_Lookup_Table_n_D_1_t1_im[85] = t1_im_85_2;
assign Direct_Lookup_Table_n_D_1_t1_im[86] = t1_im_86_2;
assign Direct_Lookup_Table_n_D_1_t1_im[87] = t1_im_87_2;
assign Direct_Lookup_Table_n_D_1_t1_im[88] = t1_im_88_2;
assign Direct_Lookup_Table_n_D_1_t1_im[89] = t1_im_89_2;
assign Direct_Lookup_Table_n_D_1_t1_im[90] = t1_im_90_2;
assign Direct_Lookup_Table_n_D_1_t1_im[91] = t1_im_91_2;
assign Direct_Lookup_Table_n_D_1_t1_im[92] = t1_im_92_2;
assign Direct_Lookup_Table_n_D_1_t1_im[93] = t1_im_93_2;
assign Direct_Lookup_Table_n_D_1_t1_im[94] = t1_im_94_2;
assign Direct_Lookup_Table_n_D_1_t1_im[95] = t1_im_95_2;
assign Direct_Lookup_Table_n_D_1_t1_im[96] = t1_im_96_2;
assign Direct_Lookup_Table_n_D_1_t1_im[97] = t1_im_97_2;
assign Direct_Lookup_Table_n_D_1_t1_im[98] = t1_im_98_2;
assign Direct_Lookup_Table_n_D_1_t1_im[99] = t1_im_99_2;
assign Direct_Lookup_Table_n_D_1_t1_im[100] = t1_im_100_2;
assign Direct_Lookup_Table_n_D_1_t1_im[101] = t1_im_101_2;
assign Direct_Lookup_Table_n_D_1_t1_im[102] = t1_im_102_2;
assign Direct_Lookup_Table_n_D_1_t1_im[103] = t1_im_103_2;
assign Direct_Lookup_Table_n_D_1_t1_im[104] = t1_im_104_2;
assign Direct_Lookup_Table_n_D_1_t1_im[105] = t1_im_105_2;
assign Direct_Lookup_Table_n_D_1_t1_im[106] = t1_im_106_2;
assign Direct_Lookup_Table_n_D_1_t1_im[107] = t1_im_107_2;
assign Direct_Lookup_Table_n_D_1_t1_im[108] = t1_im_108_2;
assign Direct_Lookup_Table_n_D_1_t1_im[109] = t1_im_109_2;
assign Direct_Lookup_Table_n_D_1_t1_im[110] = t1_im_110_2;
assign Direct_Lookup_Table_n_D_1_t1_im[111] = t1_im_111_2;
assign Direct_Lookup_Table_n_D_1_t1_im[112] = t1_im_112_2;
assign Direct_Lookup_Table_n_D_1_t1_im[113] = t1_im_113_2;
assign Direct_Lookup_Table_n_D_1_t1_im[114] = t1_im_114_2;
assign Direct_Lookup_Table_n_D_1_t1_im[115] = t1_im_115_2;
assign Direct_Lookup_Table_n_D_1_t1_im[116] = t1_im_116_2;
assign Direct_Lookup_Table_n_D_1_t1_im[117] = t1_im_117_2;
assign Direct_Lookup_Table_n_D_1_t1_im[118] = t1_im_118_2;
assign Direct_Lookup_Table_n_D_1_t1_im[119] = t1_im_119_2;
assign Direct_Lookup_Table_n_D_1_t1_im[120] = t1_im_120_2;
assign Direct_Lookup_Table_n_D_1_t1_im[121] = t1_im_121_2;
assign Direct_Lookup_Table_n_D_1_t1_im[122] = t1_im_122_2;
assign Direct_Lookup_Table_n_D_1_t1_im[123] = t1_im_123_2;
assign Direct_Lookup_Table_n_D_1_t1_im[124] = t1_im_124_2;
assign Direct_Lookup_Table_n_D_1_t1_im[125] = t1_im_125_2;
assign Direct_Lookup_Table_n_D_1_t1_im[126] = t1_im_126_2;
assign Direct_Lookup_Table_n_D_1_t1_im[127] = t1_im_127_2;
assign Direct_Lookup_Table_n_D_1_t1_im[128] = t1_im_128_2;
assign Direct_Lookup_Table_n_D_1_t1_im[129] = t1_im_129_2;
assign Direct_Lookup_Table_n_D_1_t1_im[130] = t1_im_130_2;
assign Direct_Lookup_Table_n_D_1_t1_im[131] = t1_im_131_2;
assign Direct_Lookup_Table_n_D_1_t1_im[132] = t1_im_132_2;
assign Direct_Lookup_Table_n_D_1_t1_im[133] = t1_im_133_2;
assign Direct_Lookup_Table_n_D_1_t1_im[134] = t1_im_134_2;
assign Direct_Lookup_Table_n_D_1_t1_im[135] = t1_im_135_2;
assign Direct_Lookup_Table_n_D_1_t1_im[136] = t1_im_136_2;
assign Direct_Lookup_Table_n_D_1_t1_im[137] = t1_im_137_2;
assign Direct_Lookup_Table_n_D_1_t1_im[138] = t1_im_138_2;
assign Direct_Lookup_Table_n_D_1_t1_im[139] = t1_im_139_2;
assign Direct_Lookup_Table_n_D_1_t1_im[140] = t1_im_140_2;
assign Direct_Lookup_Table_n_D_1_t1_im[141] = t1_im_141_2;
assign Direct_Lookup_Table_n_D_1_t1_im[142] = t1_im_142_2;
assign Direct_Lookup_Table_n_D_1_t1_im[143] = t1_im_143_2;
assign Direct_Lookup_Table_n_D_1_t1_im[144] = t1_im_144_2;
assign Direct_Lookup_Table_n_D_1_t1_im[145] = t1_im_145_2;
assign Direct_Lookup_Table_n_D_1_t1_im[146] = t1_im_146_2;
assign Direct_Lookup_Table_n_D_1_t1_im[147] = t1_im_147_2;
assign Direct_Lookup_Table_n_D_1_t1_im[148] = t1_im_148_2;
assign Direct_Lookup_Table_n_D_1_t1_im[149] = t1_im_149_2;
assign Direct_Lookup_Table_n_D_1_t1_im[150] = t1_im_150_2;
assign Direct_Lookup_Table_n_D_1_t1_im[151] = t1_im_151_2;
assign Direct_Lookup_Table_n_D_1_t1_im[152] = t1_im_152_2;
assign Direct_Lookup_Table_n_D_1_t1_im[153] = t1_im_153_2;
assign Direct_Lookup_Table_n_D_1_t1_im[154] = t1_im_154_2;
assign Direct_Lookup_Table_n_D_1_t1_im[155] = t1_im_155_2;
assign Direct_Lookup_Table_n_D_1_t1_im[156] = t1_im_156_2;
assign Direct_Lookup_Table_n_D_1_t1_im[157] = t1_im_157_2;
assign Direct_Lookup_Table_n_D_1_t1_im[158] = t1_im_158_2;
assign Direct_Lookup_Table_n_D_1_t1_im[159] = t1_im_159_2;
assign Direct_Lookup_Table_n_D_1_t1_im[160] = t1_im_160_2;
assign Direct_Lookup_Table_n_D_1_t1_im[161] = t1_im_161_2;
assign Direct_Lookup_Table_n_D_1_t1_im[162] = t1_im_162_2;
assign Direct_Lookup_Table_n_D_1_t1_im[163] = t1_im_163_2;
assign Direct_Lookup_Table_n_D_1_t1_im[164] = t1_im_164_2;
assign Direct_Lookup_Table_n_D_1_t1_im[165] = t1_im_165_2;
assign Direct_Lookup_Table_n_D_1_t1_im[166] = t1_im_166_2;
assign Direct_Lookup_Table_n_D_1_t1_im[167] = t1_im_167_2;
assign Direct_Lookup_Table_n_D_1_t1_im[168] = t1_im_168_2;
assign Direct_Lookup_Table_n_D_1_t1_im[169] = t1_im_169_2;
assign Direct_Lookup_Table_n_D_1_t1_im[170] = t1_im_170_2;
assign Direct_Lookup_Table_n_D_1_t1_im[171] = t1_im_171_2;
assign Direct_Lookup_Table_n_D_1_t1_im[172] = t1_im_172_2;
assign Direct_Lookup_Table_n_D_1_t1_im[173] = t1_im_173_2;
assign Direct_Lookup_Table_n_D_1_t1_im[174] = t1_im_174_2;
assign Direct_Lookup_Table_n_D_1_t1_im[175] = t1_im_175_2;
assign Direct_Lookup_Table_n_D_1_t1_im[176] = t1_im_176_2;
assign Direct_Lookup_Table_n_D_1_t1_im[177] = t1_im_177_2;
assign Direct_Lookup_Table_n_D_1_t1_im[178] = t1_im_178_2;
assign Direct_Lookup_Table_n_D_1_t1_im[179] = t1_im_179_2;
assign Direct_Lookup_Table_n_D_1_t1_im[180] = t1_im_180_2;
assign Direct_Lookup_Table_n_D_1_t1_im[181] = t1_im_181_2;
assign Direct_Lookup_Table_n_D_1_t1_im[182] = t1_im_182_2;
assign Direct_Lookup_Table_n_D_1_t1_im[183] = t1_im_183_2;
assign Direct_Lookup_Table_n_D_1_t1_im[184] = t1_im_184_2;
assign Direct_Lookup_Table_n_D_1_t1_im[185] = t1_im_185_2;
assign Direct_Lookup_Table_n_D_1_t1_im[186] = t1_im_186_2;
assign Direct_Lookup_Table_n_D_1_t1_im[187] = t1_im_187_2;
assign Direct_Lookup_Table_n_D_1_t1_im[188] = t1_im_188_2;
assign Direct_Lookup_Table_n_D_1_t1_im[189] = t1_im_189_2;
assign Direct_Lookup_Table_n_D_1_t1_im[190] = t1_im_190_2;
assign Direct_Lookup_Table_n_D_1_t1_im[191] = t1_im_191_2;
assign Direct_Lookup_Table_n_D_1_t1_im[192] = t1_im_192_2;
assign Direct_Lookup_Table_n_D_1_t1_im[193] = t1_im_193_2;
assign Direct_Lookup_Table_n_D_1_t1_im[194] = t1_im_194_2;
assign Direct_Lookup_Table_n_D_1_t1_im[195] = t1_im_195_2;
assign Direct_Lookup_Table_n_D_1_t1_im[196] = t1_im_196_2;
assign Direct_Lookup_Table_n_D_1_t1_im[197] = t1_im_197_2;
assign Direct_Lookup_Table_n_D_1_t1_im[198] = t1_im_198_2;
assign Direct_Lookup_Table_n_D_1_t1_im[199] = t1_im_199_2;
assign Direct_Lookup_Table_n_D_1_t1_im[200] = t1_im_200_2;
assign Direct_Lookup_Table_n_D_1_t1_im[201] = t1_im_201_2;
assign Direct_Lookup_Table_n_D_1_t1_im[202] = t1_im_202_2;
assign Direct_Lookup_Table_n_D_1_t1_im[203] = t1_im_203_2;
assign Direct_Lookup_Table_n_D_1_t1_im[204] = t1_im_204_2;
assign Direct_Lookup_Table_n_D_1_t1_im[205] = t1_im_205_2;
assign Direct_Lookup_Table_n_D_1_t1_im[206] = t1_im_206_2;
assign Direct_Lookup_Table_n_D_1_t1_im[207] = t1_im_207_2;
assign Direct_Lookup_Table_n_D_1_t1_im[208] = t1_im_208_2;
assign Direct_Lookup_Table_n_D_1_t1_im[209] = t1_im_209_2;
assign Direct_Lookup_Table_n_D_1_t1_im[210] = t1_im_210_2;
assign Direct_Lookup_Table_n_D_1_t1_im[211] = t1_im_211_2;
assign Direct_Lookup_Table_n_D_1_t1_im[212] = t1_im_212_2;
assign Direct_Lookup_Table_n_D_1_t1_im[213] = t1_im_213_2;
assign Direct_Lookup_Table_n_D_1_t1_im[214] = t1_im_214_2;
assign Direct_Lookup_Table_n_D_1_t1_im[215] = t1_im_215_2;
assign Direct_Lookup_Table_n_D_1_t1_im[216] = t1_im_216_2;
assign Direct_Lookup_Table_n_D_1_t1_im[217] = t1_im_217_2;
assign Direct_Lookup_Table_n_D_1_t1_im[218] = t1_im_218_2;
assign Direct_Lookup_Table_n_D_1_t1_im[219] = t1_im_219_2;
assign Direct_Lookup_Table_n_D_1_t1_im[220] = t1_im_220_2;
assign Direct_Lookup_Table_n_D_1_t1_im[221] = t1_im_221_2;
assign Direct_Lookup_Table_n_D_1_t1_im[222] = t1_im_222_2;
assign Direct_Lookup_Table_n_D_1_t1_im[223] = t1_im_223_2;
assign Direct_Lookup_Table_n_D_1_t1_im[224] = t1_im_224_2;
assign Direct_Lookup_Table_n_D_1_t1_im[225] = t1_im_225_2;
assign Direct_Lookup_Table_n_D_1_t1_im[226] = t1_im_226_2;
assign Direct_Lookup_Table_n_D_1_t1_im[227] = t1_im_227_2;
assign Direct_Lookup_Table_n_D_1_t1_im[228] = t1_im_228_2;
assign Direct_Lookup_Table_n_D_1_t1_im[229] = t1_im_229_2;
assign Direct_Lookup_Table_n_D_1_t1_im[230] = t1_im_230_2;
assign Direct_Lookup_Table_n_D_1_t1_im[231] = t1_im_231_2;
assign Direct_Lookup_Table_n_D_1_t1_im[232] = t1_im_232_2;
assign Direct_Lookup_Table_n_D_1_t1_im[233] = t1_im_233_2;
assign Direct_Lookup_Table_n_D_1_t1_im[234] = t1_im_234_2;
assign Direct_Lookup_Table_n_D_1_t1_im[235] = t1_im_235_2;
assign Direct_Lookup_Table_n_D_1_t1_im[236] = t1_im_236_2;
assign Direct_Lookup_Table_n_D_1_t1_im[237] = t1_im_237_2;
assign Direct_Lookup_Table_n_D_1_t1_im[238] = t1_im_238_2;
assign Direct_Lookup_Table_n_D_1_t1_im[239] = t1_im_239_2;
assign Direct_Lookup_Table_n_D_1_t1_im[240] = t1_im_240_2;
assign Direct_Lookup_Table_n_D_1_t1_im[241] = t1_im_241_2;
assign Direct_Lookup_Table_n_D_1_t1_im[242] = t1_im_242_2;
assign Direct_Lookup_Table_n_D_1_t1_im[243] = t1_im_243_2;
assign Direct_Lookup_Table_n_D_1_t1_im[244] = t1_im_244_2;
assign Direct_Lookup_Table_n_D_1_t1_im[245] = t1_im_245_2;
assign Direct_Lookup_Table_n_D_1_t1_im[246] = t1_im_246_2;
assign Direct_Lookup_Table_n_D_1_t1_im[247] = t1_im_247_2;
assign Direct_Lookup_Table_n_D_1_t1_im[248] = t1_im_248_2;
assign Direct_Lookup_Table_n_D_1_t1_im[249] = t1_im_249_2;
assign Direct_Lookup_Table_n_D_1_t1_im[250] = t1_im_250_2;
assign Direct_Lookup_Table_n_D_1_t1_im[251] = t1_im_251_2;
assign Direct_Lookup_Table_n_D_1_t1_im[252] = t1_im_252_2;
assign Direct_Lookup_Table_n_D_1_t1_im[253] = t1_im_253_2;
assign Direct_Lookup_Table_n_D_1_t1_im[254] = t1_im_254_2;
assign Direct_Lookup_Table_n_D_1_t1_im[255] = t1_im_255_2;
assign Direct_Lookup_Table_n_D_1_t1_im[256] = t1_im_256_2;
assign Direct_Lookup_Table_n_D_1_t1_im[257] = t1_im_257_2;
assign Direct_Lookup_Table_n_D_1_t1_im[258] = t1_im_258_2;
assign Direct_Lookup_Table_n_D_1_t1_im[259] = t1_im_259_2;
assign Direct_Lookup_Table_n_D_1_t1_im[260] = t1_im_260_2;
assign Direct_Lookup_Table_n_D_1_t1_im[261] = t1_im_261_2;
assign Direct_Lookup_Table_n_D_1_t1_im[262] = t1_im_262_2;
assign Direct_Lookup_Table_n_D_1_t1_im[263] = t1_im_263_2;
assign Direct_Lookup_Table_n_D_1_t1_im[264] = t1_im_264_2;
assign Direct_Lookup_Table_n_D_1_t1_im[265] = t1_im_265_2;
assign Direct_Lookup_Table_n_D_1_t1_im[266] = t1_im_266_2;
assign Direct_Lookup_Table_n_D_1_t1_im[267] = t1_im_267_2;
assign Direct_Lookup_Table_n_D_1_t1_im[268] = t1_im_268_2;
assign Direct_Lookup_Table_n_D_1_t1_im[269] = t1_im_269_2;
assign Direct_Lookup_Table_n_D_1_t1_im[270] = t1_im_270_2;
assign Direct_Lookup_Table_n_D_1_t1_im[271] = t1_im_271_2;
assign Direct_Lookup_Table_n_D_1_t1_im[272] = t1_im_272_2;
assign Direct_Lookup_Table_n_D_1_t1_im[273] = t1_im_273_2;
assign Direct_Lookup_Table_n_D_1_t1_im[274] = t1_im_274_2;
assign Direct_Lookup_Table_n_D_1_t1_im[275] = t1_im_275_2;
assign Direct_Lookup_Table_n_D_1_t1_im[276] = t1_im_276_2;
assign Direct_Lookup_Table_n_D_1_t1_im[277] = t1_im_277_2;
assign Direct_Lookup_Table_n_D_1_t1_im[278] = t1_im_278_2;
assign Direct_Lookup_Table_n_D_1_t1_im[279] = t1_im_279_2;
assign Direct_Lookup_Table_n_D_1_t1_im[280] = t1_im_280_2;
assign Direct_Lookup_Table_n_D_1_t1_im[281] = t1_im_281_2;
assign Direct_Lookup_Table_n_D_1_t1_im[282] = t1_im_282_2;
assign Direct_Lookup_Table_n_D_1_t1_im[283] = t1_im_283_2;
assign Direct_Lookup_Table_n_D_1_t1_im[284] = t1_im_284_2;
assign Direct_Lookup_Table_n_D_1_t1_im[285] = t1_im_285_2;
assign Direct_Lookup_Table_n_D_1_t1_im[286] = t1_im_286_2;
assign Direct_Lookup_Table_n_D_1_t1_im[287] = t1_im_287_2;
assign Direct_Lookup_Table_n_D_1_t1_im[288] = t1_im_288_2;
assign Direct_Lookup_Table_n_D_1_t1_im[289] = t1_im_289_2;
assign Direct_Lookup_Table_n_D_1_t1_im[290] = t1_im_290_2;
assign Direct_Lookup_Table_n_D_1_t1_im[291] = t1_im_291_2;
assign Direct_Lookup_Table_n_D_1_t1_im[292] = t1_im_292_2;
assign Direct_Lookup_Table_n_D_1_t1_im[293] = t1_im_293_2;
assign Direct_Lookup_Table_n_D_1_t1_im[294] = t1_im_294_2;
assign Direct_Lookup_Table_n_D_1_t1_im[295] = t1_im_295_2;
assign Direct_Lookup_Table_n_D_1_t1_im[296] = t1_im_296_2;
assign Direct_Lookup_Table_n_D_1_t1_im[297] = t1_im_297_2;
assign Direct_Lookup_Table_n_D_1_t1_im[298] = t1_im_298_2;
assign Direct_Lookup_Table_n_D_1_t1_im[299] = t1_im_299_2;
assign Direct_Lookup_Table_n_D_1_t1_im[300] = t1_im_300_2;
assign Direct_Lookup_Table_n_D_1_t1_im[301] = t1_im_301_2;
assign Direct_Lookup_Table_n_D_1_t1_im[302] = t1_im_302_2;
assign Direct_Lookup_Table_n_D_1_t1_im[303] = t1_im_303_2;
assign Direct_Lookup_Table_n_D_1_t1_im[304] = t1_im_304_2;
assign Direct_Lookup_Table_n_D_1_t1_im[305] = t1_im_305_2;
assign Direct_Lookup_Table_n_D_1_t1_im[306] = t1_im_306_2;
assign Direct_Lookup_Table_n_D_1_t1_im[307] = t1_im_307_2;
assign Direct_Lookup_Table_n_D_1_t1_im[308] = t1_im_308_2;
assign Direct_Lookup_Table_n_D_1_t1_im[309] = t1_im_309_2;
assign Direct_Lookup_Table_n_D_1_t1_im[310] = t1_im_310_2;
assign Direct_Lookup_Table_n_D_1_t1_im[311] = t1_im_311_2;
assign Direct_Lookup_Table_n_D_1_t1_im[312] = t1_im_312_2;
assign Direct_Lookup_Table_n_D_1_t1_im[313] = t1_im_313_2;
assign Direct_Lookup_Table_n_D_1_t1_im[314] = t1_im_314_2;
assign Direct_Lookup_Table_n_D_1_t1_im[315] = t1_im_315_2;
assign Direct_Lookup_Table_n_D_1_t1_im[316] = t1_im_316_2;
assign Direct_Lookup_Table_n_D_1_t1_im[317] = t1_im_317_2;
assign Direct_Lookup_Table_n_D_1_t1_im[318] = t1_im_318_2;
assign Direct_Lookup_Table_n_D_1_t1_im[319] = t1_im_319_2;
assign Direct_Lookup_Table_n_D_1_t1_im[320] = t1_im_320_2;
assign Direct_Lookup_Table_n_D_1_t1_im[321] = t1_im_321_2;
assign Direct_Lookup_Table_n_D_1_t1_im[322] = t1_im_322_2;
assign Direct_Lookup_Table_n_D_1_t1_im[323] = t1_im_323_2;
assign Direct_Lookup_Table_n_D_1_t1_im[324] = t1_im_324_2;
assign Direct_Lookup_Table_n_D_1_t1_im[325] = t1_im_325_2;
assign Direct_Lookup_Table_n_D_1_t1_im[326] = t1_im_326_2;
assign Direct_Lookup_Table_n_D_1_t1_im[327] = t1_im_327_2;
assign Direct_Lookup_Table_n_D_1_t1_im[328] = t1_im_328_2;
assign Direct_Lookup_Table_n_D_1_t1_im[329] = t1_im_329_2;
assign Direct_Lookup_Table_n_D_1_t1_im[330] = t1_im_330_2;
assign Direct_Lookup_Table_n_D_1_t1_im[331] = t1_im_331_2;
assign Direct_Lookup_Table_n_D_1_t1_im[332] = t1_im_332_2;
assign Direct_Lookup_Table_n_D_1_t1_im[333] = t1_im_333_2;
assign Direct_Lookup_Table_n_D_1_t1_im[334] = t1_im_334_2;
assign Direct_Lookup_Table_n_D_1_t1_im[335] = t1_im_335_2;
assign Direct_Lookup_Table_n_D_1_t1_im[336] = t1_im_336_2;
assign Direct_Lookup_Table_n_D_1_t1_im[337] = t1_im_337_2;
assign Direct_Lookup_Table_n_D_1_t1_im[338] = t1_im_338_2;
assign Direct_Lookup_Table_n_D_1_t1_im[339] = t1_im_339_2;
assign Direct_Lookup_Table_n_D_1_t1_im[340] = t1_im_340_2;
assign Direct_Lookup_Table_n_D_1_t1_im[341] = t1_im_341_2;
assign Direct_Lookup_Table_n_D_1_t1_im[342] = t1_im_342_2;
assign Direct_Lookup_Table_n_D_1_t1_im[343] = t1_im_343_2;
assign Direct_Lookup_Table_n_D_1_t1_im[344] = t1_im_344_2;
assign Direct_Lookup_Table_n_D_1_t1_im[345] = t1_im_345_2;
assign Direct_Lookup_Table_n_D_1_t1_im[346] = t1_im_346_2;
assign Direct_Lookup_Table_n_D_1_t1_im[347] = t1_im_347_2;
assign Direct_Lookup_Table_n_D_1_t1_im[348] = t1_im_348_2;
assign Direct_Lookup_Table_n_D_1_t1_im[349] = t1_im_349_2;
assign Direct_Lookup_Table_n_D_1_t1_im[350] = t1_im_350_2;
assign Direct_Lookup_Table_n_D_1_t1_im[351] = t1_im_351_2;
assign Direct_Lookup_Table_n_D_1_t1_im[352] = t1_im_352_2;
assign Direct_Lookup_Table_n_D_1_t1_im[353] = t1_im_353_2;
assign Direct_Lookup_Table_n_D_1_t1_im[354] = t1_im_354_2;
assign Direct_Lookup_Table_n_D_1_t1_im[355] = t1_im_355_2;
assign Direct_Lookup_Table_n_D_1_t1_im[356] = t1_im_356_2;
assign Direct_Lookup_Table_n_D_1_t1_im[357] = t1_im_357_2;
assign Direct_Lookup_Table_n_D_1_t1_im[358] = t1_im_358_2;
assign Direct_Lookup_Table_n_D_1_t1_im[359] = t1_im_359_2;
assign Direct_Lookup_Table_n_D_1_t1_im[360] = t1_im_360_2;
assign Direct_Lookup_Table_n_D_1_t1_im[361] = t1_im_361_2;
assign Direct_Lookup_Table_n_D_1_t1_im[362] = t1_im_362_2;
assign Direct_Lookup_Table_n_D_1_t1_im[363] = t1_im_363_2;
assign Direct_Lookup_Table_n_D_1_t1_im[364] = t1_im_364_2;
assign Direct_Lookup_Table_n_D_1_t1_im[365] = t1_im_365_2;
assign Direct_Lookup_Table_n_D_1_t1_im[366] = t1_im_366_2;
assign Direct_Lookup_Table_n_D_1_t1_im[367] = t1_im_367_2;
assign Direct_Lookup_Table_n_D_1_t1_im[368] = t1_im_368_2;
assign Direct_Lookup_Table_n_D_1_t1_im[369] = t1_im_369_2;
assign Direct_Lookup_Table_n_D_1_t1_im[370] = t1_im_370_2;
assign Direct_Lookup_Table_n_D_1_t1_im[371] = t1_im_371_2;
assign Direct_Lookup_Table_n_D_1_t1_im[372] = t1_im_372_2;
assign Direct_Lookup_Table_n_D_1_t1_im[373] = t1_im_373_2;
assign Direct_Lookup_Table_n_D_1_t1_im[374] = t1_im_374_2;
assign Direct_Lookup_Table_n_D_1_t1_im[375] = t1_im_375_2;
assign Direct_Lookup_Table_n_D_1_t1_im[376] = t1_im_376_2;
assign Direct_Lookup_Table_n_D_1_t1_im[377] = t1_im_377_2;
assign Direct_Lookup_Table_n_D_1_t1_im[378] = t1_im_378_2;
assign Direct_Lookup_Table_n_D_1_t1_im[379] = t1_im_379_2;
assign Direct_Lookup_Table_n_D_1_t1_im[380] = t1_im_380_2;
assign Direct_Lookup_Table_n_D_1_t1_im[381] = t1_im_381_2;
assign Direct_Lookup_Table_n_D_1_t1_im[382] = t1_im_382_2;
assign Direct_Lookup_Table_n_D_1_t1_im[383] = t1_im_383_2;
assign Direct_Lookup_Table_n_D_1_t1_im[384] = t1_im_384_2;
assign Direct_Lookup_Table_n_D_1_t1_im[385] = t1_im_385_2;
assign Direct_Lookup_Table_n_D_1_t1_im[386] = t1_im_386_2;
assign Direct_Lookup_Table_n_D_1_t1_im[387] = t1_im_387_2;
assign Direct_Lookup_Table_n_D_1_t1_im[388] = t1_im_388_2;
assign Direct_Lookup_Table_n_D_1_t1_im[389] = t1_im_389_2;
assign Direct_Lookup_Table_n_D_1_t1_im[390] = t1_im_390_2;
assign Direct_Lookup_Table_n_D_1_t1_im[391] = t1_im_391_2;
assign Direct_Lookup_Table_n_D_1_t1_im[392] = t1_im_392_2;
assign Direct_Lookup_Table_n_D_1_t1_im[393] = t1_im_393_2;
assign Direct_Lookup_Table_n_D_1_t1_im[394] = t1_im_394_2;
assign Direct_Lookup_Table_n_D_1_t1_im[395] = t1_im_395_2;
assign Direct_Lookup_Table_n_D_1_t1_im[396] = t1_im_396_2;
assign Direct_Lookup_Table_n_D_1_t1_im[397] = t1_im_397_2;
assign Direct_Lookup_Table_n_D_1_t1_im[398] = t1_im_398_2;
assign Direct_Lookup_Table_n_D_1_t1_im[399] = t1_im_399_2;
assign Direct_Lookup_Table_n_D_1_t1_im[400] = t1_im_400_2;
assign Direct_Lookup_Table_n_D_1_t1_im[401] = t1_im_401_2;
assign Direct_Lookup_Table_n_D_1_t1_im[402] = t1_im_402_2;
assign Direct_Lookup_Table_n_D_1_t1_im[403] = t1_im_403_2;
assign Direct_Lookup_Table_n_D_1_t1_im[404] = t1_im_404_2;
assign Direct_Lookup_Table_n_D_1_t1_im[405] = t1_im_405_2;
assign Direct_Lookup_Table_n_D_1_t1_im[406] = t1_im_406_2;
assign Direct_Lookup_Table_n_D_1_t1_im[407] = t1_im_407_2;
assign Direct_Lookup_Table_n_D_1_t1_im[408] = t1_im_408_2;
assign Direct_Lookup_Table_n_D_1_t1_im[409] = t1_im_409_2;
assign Direct_Lookup_Table_n_D_1_t1_im[410] = t1_im_410_2;
assign Direct_Lookup_Table_n_D_1_t1_im[411] = t1_im_411_2;
assign Direct_Lookup_Table_n_D_1_t1_im[412] = t1_im_412_2;
assign Direct_Lookup_Table_n_D_1_t1_im[413] = t1_im_413_2;
assign Direct_Lookup_Table_n_D_1_t1_im[414] = t1_im_414_2;
assign Direct_Lookup_Table_n_D_1_t1_im[415] = t1_im_415_2;
assign Direct_Lookup_Table_n_D_1_t1_im[416] = t1_im_416_2;
assign Direct_Lookup_Table_n_D_1_t1_im[417] = t1_im_417_2;
assign Direct_Lookup_Table_n_D_1_t1_im[418] = t1_im_418_2;
assign Direct_Lookup_Table_n_D_1_t1_im[419] = t1_im_419_2;
assign Direct_Lookup_Table_n_D_1_t1_im[420] = t1_im_420_2;
assign Direct_Lookup_Table_n_D_1_t1_im[421] = t1_im_421_2;
assign Direct_Lookup_Table_n_D_1_t1_im[422] = t1_im_422_2;
assign Direct_Lookup_Table_n_D_1_t1_im[423] = t1_im_423_2;
assign Direct_Lookup_Table_n_D_1_t1_im[424] = t1_im_424_2;
assign Direct_Lookup_Table_n_D_1_t1_im[425] = t1_im_425_2;
assign Direct_Lookup_Table_n_D_1_t1_im[426] = t1_im_426_2;
assign Direct_Lookup_Table_n_D_1_t1_im[427] = t1_im_427_2;
assign Direct_Lookup_Table_n_D_1_t1_im[428] = t1_im_428_2;
assign Direct_Lookup_Table_n_D_1_t1_im[429] = t1_im_429_2;
assign Direct_Lookup_Table_n_D_1_t1_im[430] = t1_im_430_2;
assign Direct_Lookup_Table_n_D_1_t1_im[431] = t1_im_431_2;
assign Direct_Lookup_Table_n_D_1_t1_im[432] = t1_im_432_2;
assign Direct_Lookup_Table_n_D_1_t1_im[433] = t1_im_433_2;
assign Direct_Lookup_Table_n_D_1_t1_im[434] = t1_im_434_2;
assign Direct_Lookup_Table_n_D_1_t1_im[435] = t1_im_435_2;
assign Direct_Lookup_Table_n_D_1_t1_im[436] = t1_im_436_2;
assign Direct_Lookup_Table_n_D_1_t1_im[437] = t1_im_437_2;
assign Direct_Lookup_Table_n_D_1_t1_im[438] = t1_im_438_2;
assign Direct_Lookup_Table_n_D_1_t1_im[439] = t1_im_439_2;
assign Direct_Lookup_Table_n_D_1_t1_im[440] = t1_im_440_2;
assign Direct_Lookup_Table_n_D_1_t1_im[441] = t1_im_441_2;
assign Direct_Lookup_Table_n_D_1_t1_im[442] = t1_im_442_2;
assign Direct_Lookup_Table_n_D_1_t1_im[443] = t1_im_443_2;
assign Direct_Lookup_Table_n_D_1_t1_im[444] = t1_im_444_2;
assign Direct_Lookup_Table_n_D_1_t1_im[445] = t1_im_445_2;
assign Direct_Lookup_Table_n_D_1_t1_im[446] = t1_im_446_2;
assign Direct_Lookup_Table_n_D_1_t1_im[447] = t1_im_447_2;
assign Direct_Lookup_Table_n_D_1_t1_im[448] = t1_im_448_2;
assign Direct_Lookup_Table_n_D_1_t1_im[449] = t1_im_449_2;
assign Direct_Lookup_Table_n_D_1_t1_im[450] = t1_im_450_2;
assign Direct_Lookup_Table_n_D_1_t1_im[451] = t1_im_451_2;
assign Direct_Lookup_Table_n_D_1_t1_im[452] = t1_im_452_2;
assign Direct_Lookup_Table_n_D_1_t1_im[453] = t1_im_453_2;
assign Direct_Lookup_Table_n_D_1_t1_im[454] = t1_im_454_2;
assign Direct_Lookup_Table_n_D_1_t1_im[455] = t1_im_455_2;
assign Direct_Lookup_Table_n_D_1_t1_im[456] = t1_im_456_2;
assign Direct_Lookup_Table_n_D_1_t1_im[457] = t1_im_457_2;
assign Direct_Lookup_Table_n_D_1_t1_im[458] = t1_im_458_2;
assign Direct_Lookup_Table_n_D_1_t1_im[459] = t1_im_459_2;
assign Direct_Lookup_Table_n_D_1_t1_im[460] = t1_im_460_2;
assign Direct_Lookup_Table_n_D_1_t1_im[461] = t1_im_461_2;
assign Direct_Lookup_Table_n_D_1_t1_im[462] = t1_im_462_2;
assign Direct_Lookup_Table_n_D_1_t1_im[463] = t1_im_463_2;
assign Direct_Lookup_Table_n_D_1_t1_im[464] = t1_im_464_2;
assign Direct_Lookup_Table_n_D_1_t1_im[465] = t1_im_465_2;
assign Direct_Lookup_Table_n_D_1_t1_im[466] = t1_im_466_2;
assign Direct_Lookup_Table_n_D_1_t1_im[467] = t1_im_467_2;
assign Direct_Lookup_Table_n_D_1_t1_im[468] = t1_im_468_2;
assign Direct_Lookup_Table_n_D_1_t1_im[469] = t1_im_469_2;
assign Direct_Lookup_Table_n_D_1_t1_im[470] = t1_im_470_2;
assign Direct_Lookup_Table_n_D_1_t1_im[471] = t1_im_471_2;
assign Direct_Lookup_Table_n_D_1_t1_im[472] = t1_im_472_2;
assign Direct_Lookup_Table_n_D_1_t1_im[473] = t1_im_473_2;
assign Direct_Lookup_Table_n_D_1_t1_im[474] = t1_im_474_2;
assign Direct_Lookup_Table_n_D_1_t1_im[475] = t1_im_475_2;
assign Direct_Lookup_Table_n_D_1_t1_im[476] = t1_im_476_2;
assign Direct_Lookup_Table_n_D_1_t1_im[477] = t1_im_477_2;
assign Direct_Lookup_Table_n_D_1_t1_im[478] = t1_im_478_2;
assign Direct_Lookup_Table_n_D_1_t1_im[479] = t1_im_479_2;
assign Direct_Lookup_Table_n_D_1_t1_im[480] = t1_im_480_2;
assign Direct_Lookup_Table_n_D_1_t1_im[481] = t1_im_481_2;
assign Direct_Lookup_Table_n_D_1_t1_im[482] = t1_im_482_2;
assign Direct_Lookup_Table_n_D_1_t1_im[483] = t1_im_483_2;
assign Direct_Lookup_Table_n_D_1_t1_im[484] = t1_im_484_2;
assign Direct_Lookup_Table_n_D_1_t1_im[485] = t1_im_485_2;
assign Direct_Lookup_Table_n_D_1_t1_im[486] = t1_im_486_2;
assign Direct_Lookup_Table_n_D_1_t1_im[487] = t1_im_487_2;
assign Direct_Lookup_Table_n_D_1_t1_im[488] = t1_im_488_2;
assign Direct_Lookup_Table_n_D_1_t1_im[489] = t1_im_489_2;
assign Direct_Lookup_Table_n_D_1_t1_im[490] = t1_im_490_2;
assign Direct_Lookup_Table_n_D_1_t1_im[491] = t1_im_491_2;
assign Direct_Lookup_Table_n_D_1_t1_im[492] = t1_im_492_2;
assign Direct_Lookup_Table_n_D_1_t1_im[493] = t1_im_493_2;
assign Direct_Lookup_Table_n_D_1_t1_im[494] = t1_im_494_2;
assign Direct_Lookup_Table_n_D_1_t1_im[495] = t1_im_495_2;
assign Direct_Lookup_Table_n_D_1_t1_im[496] = t1_im_496_2;
assign Direct_Lookup_Table_n_D_1_t1_im[497] = t1_im_497_2;
assign Direct_Lookup_Table_n_D_1_t1_im[498] = t1_im_498_2;
assign Direct_Lookup_Table_n_D_1_t1_im[499] = t1_im_499_2;
assign Direct_Lookup_Table_n_D_1_t1_im[500] = t1_im_500_2;
assign Direct_Lookup_Table_n_D_1_t1_im[501] = t1_im_501_2;
assign Direct_Lookup_Table_n_D_1_t1_im[502] = t1_im_502_2;
assign Direct_Lookup_Table_n_D_1_t1_im[503] = t1_im_503_2;
assign Direct_Lookup_Table_n_D_1_t1_im[504] = t1_im_504_2;
assign Direct_Lookup_Table_n_D_1_t1_im[505] = t1_im_505_2;
assign Direct_Lookup_Table_n_D_1_t1_im[506] = t1_im_506_2;
assign Direct_Lookup_Table_n_D_1_t1_im[507] = t1_im_507_2;
assign Direct_Lookup_Table_n_D_1_t1_im[508] = t1_im_508_2;
assign Direct_Lookup_Table_n_D_1_t1_im[509] = t1_im_509_2;
assign Direct_Lookup_Table_n_D_1_t1_im[510] = t1_im_510_2;
assign Direct_Lookup_Table_n_D_1_t1_im[511] = t1_im_511_2;
assign Direct_Lookup_Table_n_D_1_out1_re = Direct_Lookup_Table_n_D_1_t1_re[Data_Type_Conversion2_out1];
assign Direct_Lookup_Table_n_D_1_out1_im = Direct_Lookup_Table_n_D_1_t1_im[Data_Type_Conversion2_out1];
// <S18>/Complex_Multiply
controllerHdl_Complex_Multiply u_Complex_Multiply (.In1_re(Direct_Lookup_Table_n_D_out1_re), // sfix18_En16
.In1_im(Direct_Lookup_Table_n_D_out1_im), // sfix18_En16
.In2_re(Direct_Lookup_Table_n_D_1_out1_re), // sfix18_En16
.In2_im(Direct_Lookup_Table_n_D_1_out1_im), // sfix18_En16
.Re(cos_coefficient), // sfix36_En32
.Im(sin_coefficient) // sfix36_En32
);
// <S18>/Data Type Conversion3
assign sin_coefficient_1 = sin_coefficient[33:16];
assign sin = sin_coefficient_1;
// <S18>/Data Type Conversion
assign cos_coefficient_1 = cos_coefficient[33:16];
assign cos = cos_coefficient_1;
endmodule // controllerHdl_Sin_Cos
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_SYMBOL_V
`define SKY130_FD_SC_MS__EINVN_SYMBOL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__einvn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_SYMBOL_V
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
Debug State Capture
Trigger captures the state of 3 x 32-bit words (96 bits total). A
clock counter is started. Everytime the 96-bit input bits change
an entry is made in the buffer with the previous state and how many
clocks that state was detected.
Addr
0x000 : Control/Status
0x004 : Live Input Data (32-bit Word 0)
0x008 : Live Input Data (32-bit Word 1)
0x00C : Live Input Data (32-bit Word 2)
0x010 : [Clock Count #0]
0x014 : [Word0 #0]
0x018 : [Word1 #0]
0x01C : [Word2 #0]
0x020 : [Clock Count #1]
0x024 : [Word0 #1]
0x028 : [Word1 #1]
0x02C : [Word2 #1]
(...)
16-bytes per state detected. First word is "clock count".
Next three words are state detected for the clock count.
(...)
0xFFF :
Control -
[0] Arm Trigger
[1] Force Trigger (Arm must also be set)
[2] Sample Done
[3] Sample Running
[7-4] RESERVED
[15-8] Mode (to debug target to select data/trigger settings)
[31-16] RESERVED
*/
module rcn_debug_state
(
input rcn_clk,
input rcn_rst,
input [68:0] rcn_in,
output [68:0] rcn_out,
output reg [7:0] lsa_mode,
input lsa_clk,
input lsa_trigger,
input [95:0] lsa_data
);
parameter ADDR_BASE = 1; // 4kB window
parameter INIT_ARMED = 1;
parameter INIT_FORCED = 0;
parameter INIT_MODE = 8'd0;
wire rcn_cs;
wire rcn_wr;
wire [23:0] rcn_addr;
wire [31:0] rcn_wdata;
reg [31:0] rcn_rdata;
rcn_slave #(.ADDR_BASE(ADDR_BASE), .ADDR_MASK(24'hFFF000)) rcn_slave
(
.rst(rcn_rst),
.clk(rcn_clk),
.rcn_in(rcn_in),
.rcn_out(rcn_out),
.cs(rcn_cs),
.wr(rcn_wr),
.mask(),
.addr(rcn_addr),
.wdata(rcn_wdata),
.rdata(rcn_rdata)
);
//
// Clock domain crossing
//
reg [1:0] sync_av;
reg [1:0] sync_lsa;
reg [1:0] sync_lsa_av;
reg ctrl_arm;
reg rcn_arm;
reg lsa_arm;
reg ctrl_force;
reg rcn_force;
reg lsa_force;
reg [7:0] ctrl_mode;
reg [7:0] rcn_mode;
// lsa_mode in port list
reg sample_done;
reg rcn_done;
reg lsa_done;
wire sample_running;
reg rcn_running;
reg lsa_running;
wire [95:0] sample_live = lsa_data;
reg [95:0] rcn_live;
reg [95:0] lsa_live;
always @ (posedge rcn_clk or posedge rcn_rst)
if (rcn_rst)
begin
sync_lsa_av <= 2'd0;
sync_av <= 2'd0;
end
else
begin
sync_lsa_av <= sync_lsa;
sync_av <= (sync_lsa_av == sync_av) ? sync_av + 2'd1 : sync_av;
end
always @ (posedge lsa_clk)
sync_lsa <= sync_av;
always @ (posedge rcn_clk)
if (sync_av == 2'b01)
{rcn_live, rcn_running, rcn_done, rcn_mode, rcn_force, rcn_arm} <=
{lsa_live, lsa_running, lsa_done, ctrl_mode, ctrl_force, ctrl_arm};
always @ (posedge lsa_clk)
if (sync_lsa == 2'b10)
{lsa_live, lsa_running, lsa_done, lsa_mode, lsa_force, lsa_arm} <=
{sample_live, sample_running, sample_done, rcn_mode, rcn_force, rcn_arm};
//
// Sample state machine
//
reg [8:0] sample_waddr;
assign sample_running = sample_waddr[8];
reg [127:0] sample_data[255:0];
reg [95:0] sample_state;
reg [95:0] sample_state_d1;
wire sample_next = (sample_state != sample_state_d1);
reg [31:0] sample_cnt;
always @ (posedge lsa_clk)
sample_done <= lsa_arm && (sample_waddr == 8'd0);
always @ (posedge lsa_clk)
if (!lsa_arm)
sample_waddr <= 9'h001;
else if (!sample_waddr[8] && |sample_waddr[7:0])
sample_waddr <= sample_waddr + 9'd1;
else if (sample_waddr == 9'h100)
sample_waddr <= (lsa_force || lsa_trigger) ? 9'h101 : 9'h100;
else if (sample_next && (sample_waddr != 9'h000))
sample_waddr <= sample_waddr + 9'd1;
always @ (posedge lsa_clk)
begin
sample_state <= lsa_data;
sample_state_d1 <= sample_state;
sample_cnt <= (!sample_running || sample_next) ? 32'd1 :
(sample_cnt != 32'hFFFFFFFF) ? sample_cnt + 32'd1
: sample_cnt;
end
always @ (posedge lsa_clk)
if (lsa_arm)
sample_data[sample_waddr[7:0]] <= (sample_waddr[8]) ? {sample_state_d1, sample_cnt} : 96'd0;
//
// Control register
//
reg init_cycle;
always @ (posedge rcn_clk or posedge rcn_rst)
if (rcn_rst)
begin
ctrl_arm <= 1'b0;
ctrl_force <= 1'b0;
ctrl_mode <= 8'd0;
init_cycle <= 1'b0;
end
else if (!init_cycle)
begin
ctrl_arm <= (INIT_ARMED != 0);
ctrl_force <= (INIT_FORCED != 0);
ctrl_mode <= INIT_MODE;
init_cycle <= 1'b1;
end
else if (rcn_cs && rcn_wr && (rcn_addr[11:2] == 10'd0))
begin
ctrl_arm <= rcn_wdata[0];
ctrl_force <= rcn_wdata[1];
ctrl_mode <= rcn_wdata[15:8];
end
always @ (posedge rcn_clk)
if (rcn_addr[11:2] == 10'd0)
rcn_rdata <= {16'd0, ctrl_mode, 4'd0, rcn_running, rcn_done, ctrl_force, ctrl_arm};
else if (rcn_addr[11:2] == 10'd1)
rcn_rdata <= rcn_live[31:0];
else if (rcn_addr[11:2] == 10'd2)
rcn_rdata <= rcn_live[63:32];
else if (rcn_addr[11:2] == 10'd3)
rcn_rdata <= rcn_live[95:64];
else if (rcn_addr[3:2] == 2'b00)
rcn_rdata <= sample_data[rcn_addr[11:4]][31:0];
else if (rcn_addr[3:2] == 2'b01)
rcn_rdata <= sample_data[rcn_addr[11:4]][63:32];
else if (rcn_addr[3:2] == 2'b10)
rcn_rdata <= sample_data[rcn_addr[11:4]][95:64];
else
rcn_rdata <= sample_data[rcn_addr[11:4]][127:96];
endmodule
|
//
// Copyright (c) 2015 Jan Adelsbach <[email protected]>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module pdp1_flg_offset(fl_n, fl_mask);
input [0:2] fl_n;
output reg [0:5] fl_mask;
always @(fl_n) begin
case(fl_n)
3'b000:
fl_mask <= 6'b000000;
3'b001:
fl_mask <= 6'b000001;
3'b010:
fl_mask <= 6'b000010;
3'b011:
fl_mask <= 6'b000100;
3'b100:
fl_mask <= 6'b001000;
3'b101:
fl_mask <= 6'b010000;
3'b110:
fl_mask <= 6'b100000;
3'b111:
fl_mask <= 6'b111111;
endcase // case (op_mask[9:11])
end // always @ (w_pf_immed or sk_pf)
endmodule // pdp1_flg_offset
module pdp1_skp_decoder(sk_mask, sk_i, sk_ac, sk_io, sk_ov,
sk_sw, sk_pf, sk_skp);
parameter pdp_model = "PDP-1"; // Or PDP-1D
input [0:11] sk_mask;
input sk_i;
input [0:17] sk_ac;
input [0:17] sk_io;
input sk_ov;
input [0:5] sk_sw;
input [0:5] sk_pf;
output sk_skp;
wire w_io_p;
wire w_ac_p;
wire w_pf_p;
wire w_sw_p;
wire w_or;
wire [0:2] w_pf_immed;
wire [0:2] w_sw_immed;
wire [6:0] w_pf_off;
wire [0:6] w_sw_off;
wire [0:5] w_pf_mask;
wire [0:5] w_sw_mask;
assign w_pf_immed = sk_mask[9:11];
assign w_sw_immed = sk_mask[6:8];
pdp1_flg_offset pf(w_pf_immed, w_pf_mask);
pdp1_flg_offset sw(w_sw_immed, w_sw_mask);
assign sk_skp = (sk_i) ? ~w_or : w_or;
assign w_or = w_io_p | w_ac_p | (sk_mask[2] & ~sk_ov) | w_pf_p | w_sw_p;
generate
if(pdp_model == "PDP-1D")
assign w_io_p = (sk_mask[0] & (|sk_io[1:17])) |
(sk_mask[1] & ~sk_io[0]);
else
assign w_io_p = (sk_mask[1] & ~sk_io[0]);
endgenerate
assign w_ac_p = (sk_mask[3] & sk_ac[0]) |
(sk_mask[4] & ~sk_ac[0]) |
(sk_mask[5] & ~(|sk_ac));
assign w_pf_p = ~(|w_pf_immed) ? 1'b0 :
(&w_pf_immed) ? ~(&sk_pf) : ~(|(sk_pf & w_pf_mask));
assign w_sw_p = ~(|w_sw_immed) ? 1'b0 :
(&w_sw_immed) ? ~(&sk_sw) : ~(|(sk_sw & w_sw_mask));
endmodule // pdp1_skp_decoder
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Triple-port synchronous 128x32 RAM
* Port 1, read-only
* Port 2, read-only
* Port 3, write-only
*/
module pfpu_tpram(
input sys_clk,
input [6:0] p1_a,
output reg [31:0] p1_d,
input [6:0] p2_a,
output reg [31:0] p2_d,
input p3_en,
input [6:0] p3_a,
input [31:0] p3_d
);
/*
* Duplicate the contents over two dual-port BRAMs
* Port A(WO) Port B(RO)
* Mem1 P3 P1
* Mem2 P3 P2
*/
reg [31:0] mem1[0:127];
always @(posedge sys_clk) begin
if(p3_en)
mem1[p3_a] <= p3_d;
p1_d <= mem1[p1_a];
end
reg [31:0] mem2[0:127];
always @(posedge sys_clk) begin
if(p3_en)
mem2[p3_a] <= p3_d;
p2_d <= mem2[p2_a];
end
endmodule
|
module Keyboard_driver(clk, reset, ready_pulse, Keyboard_Data, ACK, STB, DAT_O);
input clk;
input reset;
input ready_pulse;
input [7: 0] Keyboard_Data;
input STB;
output ACK;
output [31: 0] DAT_O;
reg [31: 0] data_hold = 0;
reg [7: 0] data_cooked;
reg [23: 0] data_cnt = 0;
reg f0 = 0;
assign DAT_O = {data_cooked, data_cnt};
assign ACK = STB;
always @(posedge ready_pulse) begin
if (Keyboard_Data == 8'hf0)
f0 <= 1;
else begin
if (!f0) begin
data_hold <= Keyboard_Data;
data_cnt <= data_cnt + 1;
end else
f0 <= 0;
end
end
always @* begin
case(data_hold)
8'h16: data_cooked = 49;// 1
8'h1E: data_cooked = 50;// 2
8'h26: data_cooked = 51;// 3
8'h25: data_cooked = 52;// 4
8'h2E: data_cooked = 53;// 5
8'h36: data_cooked = 54;// 6
8'h3D: data_cooked = 55;// 7
8'h3E: data_cooked = 56;// 8
8'h46: data_cooked = 57;// 9
8'h45: data_cooked = 48;// 0
8'h4E: data_cooked = 45;// -
8'h55: data_cooked = 43;// +
8'h15: data_cooked = 113;// q
8'h1D: data_cooked = 119;// w
8'h24: data_cooked = 101;// e
8'h2D: data_cooked = 114;// r
8'h2C: data_cooked = 116;// t
8'h35: data_cooked = 121;// y
8'h3C: data_cooked = 117;// u
8'h43: data_cooked = 105;// i
8'h44: data_cooked = 111;// o
8'h4D: data_cooked = 112;// p
8'h54: data_cooked = 91;// [
8'h5B: data_cooked = 93;// ]
8'h1C: data_cooked = 97;// a
8'h1B: data_cooked = 115;// s
8'h23: data_cooked = 100;// d
8'h2B: data_cooked = 102;// f
8'h34: data_cooked = 103;// g
8'h33: data_cooked = 104;// h
8'h3B: data_cooked = 106;// j
8'h42: data_cooked = 107;// k
8'h4B: data_cooked = 108;// l
8'h4C: data_cooked = 59;// ;
8'h52: data_cooked = 92;// \
8'h1A: data_cooked = 122;// z
8'h22: data_cooked = 120;// x
8'h21: data_cooked = 99;// c
8'h2A: data_cooked = 118;// v
8'h32: data_cooked = 98;// b
8'h31: data_cooked = 110;// n
8'h3A: data_cooked = 109;// m
8'h41: data_cooked = 44;// ,
8'h49: data_cooked = 46;// .
8'h4A: data_cooked = 47;// /
8'h29: data_cooked = 32;//
8'h66: data_cooked = 8; // Backspace
8'h5A: data_cooked = 10;// Enter to '\n'
default: data_cooked = 0;
endcase
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file Data_Mem.v when simulating
// the core, Data_Mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module Data_Mem(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("Data_Mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3e")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_gt_common_1 (
// reset and clocks
rst,
ref_clk,
qpll_clk,
qpll_ref_clk,
qpll_locked,
// drp interface
drp_clk,
drp_en,
drp_addr,
drp_wr,
drp_wdata,
drp_rdata,
drp_ready);
// parameters
parameter QPLL_REFCLK_DIV = 2;
parameter QPLL_CFG = 27'h06801C1;
parameter QPLL_FBDIV_RATIO = 1'b1;
parameter QPLL_FBDIV = 10'b0000110000;
// reset and clocks
input rst;
input ref_clk;
output qpll_clk;
output qpll_ref_clk;
output qpll_locked;
// drp interface
input drp_clk;
input drp_en;
input [11:0] drp_addr;
input drp_wr;
input [15:0] drp_wdata;
output [15:0] drp_rdata;
output drp_ready;
// instantiations
GTXE2_COMMON #(
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("3.0"),
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (QPLL_CFG),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV))
i_gtxe2_common (
.DRPCLK (drp_clk),
.DRPEN (drp_en),
.DRPADDR (drp_addr[7:0]),
.DRPWE (drp_wr),
.DRPDI (drp_wdata),
.DRPDO (drp_rdata),
.DRPRDY (drp_ready),
.GTGREFCLK (1'd0),
.GTNORTHREFCLK0 (1'd0),
.GTNORTHREFCLK1 (1'd0),
.GTREFCLK0 (ref_clk),
.GTREFCLK1 (1'd0),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.QPLLDMONITOR (),
.QPLLOUTCLK (qpll_clk),
.QPLLOUTREFCLK (qpll_ref_clk),
.REFCLKOUTMONITOR (),
.QPLLFBCLKLOST (),
.QPLLLOCK (qpll_locked),
.QPLLLOCKDETCLK (drp_clk),
.QPLLLOCKEN (1'd1),
.QPLLOUTRESET (1'd0),
.QPLLPD (1'd0),
.QPLLREFCLKLOST (),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (rst),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
.BGBYPASSB (1'd1),
.BGMONITORENB (1'd1),
.BGPDB (1'd1),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (1'd1));
endmodule
// ***************************************************************************
// ***************************************************************************
|
(** * Sub: Subtyping *)
Require Import SfLib.
Require Import Maps.
Require Import Types.
(* ################################################################# *)
(** * Concepts *)
(** We now turn to the study of _subtyping_, a key feature
needed to support the object-oriented programming style. *)
(* ================================================================= *)
(** ** A Motivating Example *)
(** Suppose we are writing a program involving two record types
defined as follows:
Person = {name:String, age:Nat}
Student = {name:String, age:Nat, gpa:Nat}
*)
(** In the simply typed lamdba-calculus with records, the term
(\r:Person. (r.age)+1) {name="Pat",age=21,gpa=1}
is not typable, since it applies a function that wants a one-field
record to an argument that actually provides two fields, while the
[T_App] rule demands that the domain type of the function being
applied must match the type of the argument precisely.
But this is silly: we're passing the function a _better_ argument
than it needs! The only thing the body of the function can
possibly do with its record argument [r] is project the field [age]
from it: nothing else is allowed by the type, and the presence or
absence of an extra [gpa] field makes no difference at all. So,
intuitively, it seems that this function should be applicable to
any record value that has at least an [age] field.
More generally, a record with more fields is "at least as good in
any context" as one with just a subset of these fields, in the
sense that any value belonging to the longer record type can be
used _safely_ in any context expecting the shorter record type. If
the context expects something with the shorter type but we actually
give it something with the longer type, nothing bad will
happen (formally, the program will not get stuck).
The principle at work here is called _subtyping_. We say that "[S]
is a subtype of [T]", written [S <: T], if a value of type [S] can
safely be used in any context where a value of type [T] is
expected. The idea of subtyping applies not only to records, but
to all of the type constructors in the language -- functions,
pairs, etc. *)
(* ================================================================= *)
(** ** Subtyping and Object-Oriented Languages *)
(** Subtyping plays a fundamental role in many programming
languages -- in particular, it is closely related to the notion of
_subclassing_ in object-oriented languages.
An _object_ in Java, C[#], etc. can be thought of as a record,
some of whose fields are functions ("methods") and some of whose
fields are data values ("fields" or "instance variables").
Invoking a method [m] of an object [o] on some arguments [a1..an]
roughly consists of projecting out the [m] field of [o] and
applying it to [a1..an].
The type of an object is called a _class_ -- or, in some
languages, an _interface_. It describes which methods and which
data fields the object offers. Classes and interfaces are related
by the _subclass_ and _subinterface_ relations. An object
belonging to a subclass (or subinterface) is required to provide
all the methods and fields of one belonging to a superclass (or
superinterface), plus possibly some more.
The fact that an object from a subclass can be used in place of
one from a superclass provides a degree of flexibility that is is
extremely handy for organizing complex libraries. For example, a
GUI toolkit like Java's Swing framework might define an abstract
interface [Component] that collects together the common fields and
methods of all objects having a graphical representation that can
be displayed on the screen and interact with the user, such as the
buttons, checkboxes, and scrollbars of a typical GUI. A method
that relies only on this common interface can now be applied to
any of these objects.
Of course, real object-oriented languages include many other
features besides these. For example, fields can be updated.
Fields and methods can be declared [private]. Classes can give
_initializers_ that are used when constructing objects. Code in
subclasses can cooperate with code in superclasses via
_inheritance_. Classes can have static methods and fields. Etc.,
etc.
To keep things simple here, we won't deal with any of these
issues -- in fact, we won't even talk any more about objects or
classes. (There is a lot of discussion in [Pierce 2002], if
you are interested.) Instead, we'll study the core concepts
behind the subclass / subinterface relation in the simplified
setting of the STLC. *)
(* ================================================================= *)
(** ** The Subsumption Rule *)
(** Our goal for this chapter is to add subtyping to the simply typed
lambda-calculus (with some of the basic extensions from [MoreStlc]).
This involves two steps:
- Defining a binary _subtype relation_ between types.
- Enriching the typing relation to take subtyping into account.
The second step is actually very simple. We add just a single rule
to the typing relation: the so-called _rule of subsumption_:
Gamma |- t : S S <: T
------------------------- (T_Sub)
Gamma |- t : T
This rule says, intuitively, that it is OK to "forget" some of
what we know about a term. *)
(** For example, we may know that [t] is a record with two
fields (e.g., [S = {x:A->A, y:B->B}]), but choose to forget about
one of the fields ([T = {y:B->B}]) so that we can pass [t] to a
function that requires just a single-field record. *)
(* ================================================================= *)
(** ** The Subtype Relation *)
(** The first step -- the definition of the relation [S <: T] -- is
where all the action is. Let's look at each of the clauses of its
definition. *)
(* ----------------------------------------------------------------- *)
(** *** Structural Rules *)
(** To start off, we impose two "structural rules" that are
independent of any particular type constructor: a rule of
_transitivity_, which says intuitively that, if [S] is
better (richer, safer) than [U] and [U] is better than [T],
then [S] is better than [T]...
S <: U U <: T
---------------- (S_Trans)
S <: T
... and a rule of _reflexivity_, since certainly any type [T] is
as good as itself:
------ (S_Refl)
T <: T
*)
(* ----------------------------------------------------------------- *)
(** *** Products *)
(** Now we consider the individual type constructors, one by one,
beginning with product types. We consider one pair to be a subtype
of another if each of its components is.
S1 <: T1 S2 <: T2
-------------------- (S_Prod)
S1 * S2 <: T1 * T2
*)
(* ----------------------------------------------------------------- *)
(** *** Arrows *)
(** The subtyping rule for arrows is a little less intuitive.
Suppose we have functions [f] and [g] with these types:
f : C -> Student
g : (C->Person) -> D
That is, [f] is a function that yields a record of type [Student],
and [g] is a (higher-order) function that expects its argument to be
a function yielding a record of type [Person]. Also suppose that
[Student] is a subtype of [Person]. Then the application [g f] is
safe even though their types do not match up precisely, because
the only thing [g] can do with [f] is to apply it to some
argument (of type [C]); the result will actually be a [Student],
while [g] will be expecting a [Person], but this is safe because
the only thing [g] can then do is to project out the two fields
that it knows about ([name] and [age]), and these will certainly
be among the fields that are present.
This example suggests that the subtyping rule for arrow types
should say that two arrow types are in the subtype relation if
their results are:
S2 <: T2
---------------- (S_Arrow_Co)
S1 -> S2 <: S1 -> T2
We can generalize this to allow the arguments of the two arrow
types to be in the subtype relation as well:
T1 <: S1 S2 <: T2
-------------------- (S_Arrow)
S1 -> S2 <: T1 -> T2
But notice that the argument types are subtypes "the other way round":
in order to conclude that [S1->S2] to be a subtype of [T1->T2], it
must be the case that [T1] is a subtype of [S1]. The arrow
constructor is said to be _contravariant_ in its first argument
and _covariant_ in its second.
Here is an example that illustrates this:
f : Person -> C
g : (Student -> C) -> D
The application [g f] is safe, because the only thing the body of
[g] can do with [f] is to apply it to some argument of type
[Student]. Since [f] requires records having (at least) the
fields of a [Person], this will always work. So [Person -> C] is a
subtype of [Student -> C] since [Student] is a subtype of
[Person].
The intuition is that, if we have a function [f] of type [S1->S2],
then we know that [f] accepts elements of type [S1]; clearly, [f]
will also accept elements of any subtype [T1] of [S1]. The type of
[f] also tells us that it returns elements of type [S2]; we can
also view these results belonging to any supertype [T2] of
[S2]. That is, any function [f] of type [S1->S2] can also be
viewed as having type [T1->T2]. *)
(* ----------------------------------------------------------------- *)
(** *** Records *)
(** What about subtyping for record types? *)
(** The basic intuition is that it is always safe to use a "bigger"
record in place of a "smaller" one. That is, given a record type,
adding extra fields will always result in a subtype. If some code
is expecting a record with fields [x] and [y], it is perfectly safe
for it to receive a record with fields [x], [y], and [z]; the [z]
field will simply be ignored. For example,
{name:String, age:Nat, gpa:Nat} <: {name:String, age:Nat}
{name:String, age:Nat} <: {name:String} {name:String} <: {}
This is known as "width subtyping" for records. *)
(** We can also create a subtype of a record type by replacing the type
of one of its fields with a subtype. If some code is expecting a
record with a field [x] of type [T], it will be happy with a record
having a field [x] of type [S] as long as [S] is a subtype of
[T]. For example,
{x:Student} <: {x:Person}
This is known as "depth subtyping". *)
(** Finally, although the fields of a record type are written in a
particular order, the order does not really matter. For example,
{name:String,age:Nat} <: {age:Nat,name:String}
This is known as "permutation subtyping". *)
(** We _could_ formalize these requirements in a single subtyping rule
for records as follows:
forall jk in j1..jn,
exists ip in i1..im, such that
jk=ip and Sp <: Tk
---------------------------------- (S_Rcd)
{i1:S1...im:Sm} <: {j1:T1...jn:Tn}
That is, the record on the left should have all the field labels of
the one on the right (and possibly more), while the types of the
common fields should be in the subtype relation.
However, this rule is rather heavy and hard to read, so it is often
decomposed into three simpler rules, which can be combined using
[S_Trans] to achieve all the same effects. *)
(** First, adding fields to the end of a record type gives a subtype:
n > m
--------------------------------- (S_RcdWidth)
{i1:T1...in:Tn} <: {i1:T1...im:Tm}
We can use [S_RcdWidth] to drop later fields of a multi-field
record while keeping earlier fields, showing for example that
[{age:Nat,name:String} <: {name:String}]. *)
(** Second, subtyping can be applied inside the components of a compound
record type:
S1 <: T1 ... Sn <: Tn
---------------------------------- (S_RcdDepth)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
For example, we can use [S_RcdDepth] and [S_RcdWidth] together to
show that [{y:Student, x:Nat} <: {y:Person}]. *)
(** Third, subtyping can reorder fields. For example, we
want [{name:String, gpa:Nat, age:Nat} <: Person]. (We
haven't quite achieved this yet: using just [S_RcdDepth] and
[S_RcdWidth] we can only drop fields from the _end_ of a record
type.) So we add:
{i1:S1...in:Sn} is a permutation of {i1:T1...in:Tn}
--------------------------------------------------- (S_RcdPerm)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
*)
(** It is worth noting that full-blown language designs may choose not
to adopt all of these subtyping rules. For example, in Java:
- A subclass may not change the argument or result types of a
method of its superclass (i.e., no depth subtyping or no arrow
subtyping, depending how you look at it).
- Each class member (field or method) can be assigned a single
index, adding new indices "on the right" as more members are
added in subclasses (i.e., no permutation for classes).
- A class may implement multiple interfaces -- so-called "multiple
inheritance" of interfaces (i.e., permutation is allowed for
interfaces). *)
(** **** Exercise: 2 stars, recommended (arrow_sub_wrong) *)
(** Suppose we had incorrectly defined subtyping as covariant on both
the right and the left of arrow types:
S1 <: T1 S2 <: T2
-------------------- (S_Arrow_wrong)
S1 -> S2 <: T1 -> T2
Give a concrete example of functions [f] and [g] with the following types...
f : Student -> Nat
g : (Person -> Nat) -> Nat
... such that the application [g f] will get stuck during
execution.
[] *)
(* ----------------------------------------------------------------- *)
(** *** Top *)
(** Finally, it is convenient to give the subtype relation a maximum
element -- a type that lies above every other type and is
inhabited by all (well-typed) values. We do this by adding to the
language one new type constant, called [Top], together with a
subtyping rule that places it above every other type in the
subtype relation:
-------- (S_Top)
S <: Top
The [Top] type is an analog of the [Object] type in Java and C[#]. *)
(* ----------------------------------------------------------------- *)
(** *** Summary *)
(** In summary, we form the STLC with subtyping by starting with the
pure STLC (over some set of base types) and then...
- adding a base type [Top],
- adding the rule of subsumption
Gamma |- t : S S <: T
------------------------- (T_Sub)
Gamma |- t : T
to the typing relation, and
- defining a subtype relation as follows:
S <: U U <: T
---------------- (S_Trans)
S <: T
------ (S_Refl)
T <: T
-------- (S_Top)
S <: Top
S1 <: T1 S2 <: T2
-------------------- (S_Prod)
S1 * S2 <: T1 * T2
T1 <: S1 S2 <: T2
-------------------- (S_Arrow)
S1 -> S2 <: T1 -> T2
n > m
--------------------------------- (S_RcdWidth)
{i1:T1...in:Tn} <: {i1:T1...im:Tm}
S1 <: T1 ... Sn <: Tn
---------------------------------- (S_RcdDepth)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
{i1:S1...in:Sn} is a permutation of {i1:T1...in:Tn}
--------------------------------------------------- (S_RcdPerm)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
*)
(* ================================================================= *)
(** ** Exercises *)
(** **** Exercise: 1 star, optional (subtype_instances_tf_1) *)
(** Suppose we have types [S], [T], [U], and [V] with [S <: T]
and [U <: V]. Which of the following subtyping assertions
are then true? Write _true_ or _false_ after each one.
([A], [B], and [C] here are base types.)
- [T->S <: T->S]
- [Top->U <: S->Top]
- [(C->C) -> (A*B) <: (C->C) -> (Top*B)]
- [T->T->U <: S->S->V]
- [(T->T)->U <: (S->S)->V]
- [((T->S)->T)->U <: ((S->T)->S)->V]
- [S*V <: T*U]
[] *)
(** **** Exercise: 2 stars (subtype_order) *)
(** The following types happen to form a linear order with respect to subtyping:
- [Top]
- [Top -> Student]
- [Student -> Person]
- [Student -> Top]
- [Person -> Student]
Write these types in order from the most specific to the most general.
Where does the type [Top->Top->Student] fit into this order?
[] *)
(** **** Exercise: 1 star (subtype_instances_tf_2) *)
(** Which of the following statements are true? Write _true_ or
_false_ after each one.
forall S T,
S <: T ->
S->S <: T->T
forall S,
S <: A->A ->
exists T,
S = T->T /\ T <: A
forall S T1 T2,
(S <: T1 -> T2) ->
exists S1 S2,
S = S1 -> S2 /\ T1 <: S1 /\ S2 <: T2
exists S,
S <: S->S
exists S,
S->S <: S
forall S T1 T2,
S <: T1*T2 ->
exists S1 S2,
S = S1*S2 /\ S1 <: T1 /\ S2 <: T2
[] *)
(** **** Exercise: 1 star (subtype_concepts_tf) *)
(** Which of the following statements are true, and which are false?
- There exists a type that is a supertype of every other type.
- There exists a type that is a subtype of every other type.
- There exists a pair type that is a supertype of every other
pair type.
- There exists a pair type that is a subtype of every other
pair type.
- There exists an arrow type that is a supertype of every other
arrow type.
- There exists an arrow type that is a subtype of every other
arrow type.
- There is an infinite descending chain of distinct types in the
subtype relation---that is, an infinite sequence of types
[S0], [S1], etc., such that all the [Si]'s are different and
each [S(i+1)] is a subtype of [Si].
- There is an infinite _ascending_ chain of distinct types in
the subtype relation---that is, an infinite sequence of types
[S0], [S1], etc., such that all the [Si]'s are different and
each [S(i+1)] is a supertype of [Si].
[] *)
(** **** Exercise: 2 stars (proper_subtypes) *)
(** Is the following statement true or false? Briefly explain your
answer.
forall T,
~(exists n, T = TBase n) ->
exists S,
S <: T /\ S <> T
[] *)
(** **** Exercise: 2 stars (small_large_1) *)
(**
- What is the _smallest_ type [T] ("smallest" in the subtype
relation) that makes the following assertion true? (Assume we
have [Unit] among the base types and [unit] as a constant of this
type.)
empty |- (\p:T*Top. p.fst) ((\z:A.z), unit) : A->A
- What is the _largest_ type [T] that makes the same assertion true?
[] *)
(** **** Exercise: 2 stars (small_large_2) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
empty |- (\p:(A->A * B->B). p) ((\z:A.z), (\z:B.z)) : T
- What is the _largest_ type [T] that makes the same assertion true?
[] *)
(** **** Exercise: 2 stars, optional (small_large_3) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
a:A |- (\p:(A*T). (p.snd) (p.fst)) (a , \z:A.z) : A
- What is the _largest_ type [T] that makes the same assertion true?
[] *)
(** **** Exercise: 2 stars (small_large_4) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
exists S,
empty |- (\p:(A*T). (p.snd) (p.fst)) : S
- What is the _largest_ type [T] that makes the same
assertion true?
[] *)
(** **** Exercise: 2 stars (smallest_1) *)
(** What is the _smallest_ type [T] that makes the following
assertion true?
exists S, exists t,
empty |- (\x:T. x x) t : S
]]
[] *)
(** **** Exercise: 2 stars (smallest_2) *)
(** What is the _smallest_ type [T] that makes the following
assertion true?
empty |- (\x:Top. x) ((\z:A.z) , (\z:B.z)) : T
]]
[] *)
(** **** Exercise: 3 stars, optional (count_supertypes) *)
(** How many supertypes does the record type [{x:A, y:C->C}] have? That is,
how many different types [T] are there such that [{x:A, y:C->C} <:
T]? (We consider two types to be different if they are written
differently, even if each is a subtype of the other. For example,
[{x:A,y:B}] and [{y:B,x:A}] are different.)
[] *)
(** **** Exercise: 2 stars (pair_permutation) *)
(** The subtyping rule for product types
S1 <: T1 S2 <: T2
-------------------- (S_Prod)
S1*S2 <: T1*T2
intuitively corresponds to the "depth" subtyping rule for records.
Extending the analogy, we might consider adding a "permutation" rule
--------------
T1*T2 <: T2*T1
for products. Is this a good idea? Briefly explain why or why not.
[] *)
(* ################################################################# *)
(** * Formal Definitions *)
(** Most of the definitions needed to formalize what we've discussed
above -- in particular, the syntax and operational semantics of
the language -- are identical to what we saw in the last chapter.
We just need to extend the typing relation with the subsumption
rule and add a new [Inductive] definition for the subtyping
relation. Let's first do the identical bits. *)
(* ================================================================= *)
(** ** Core Definitions *)
(* ----------------------------------------------------------------- *)
(** *** Syntax *)
(** In the rest of the chapter, we formalize just base types,
booleans, arrow types, [Unit], and [Top], omitting record types
and leaving product types as an exercise. For the sake of more
interesting examples, we'll add an arbitrary set of base types
like [String], [Float], etc. (Since they are just for examples,
we won't bother adding any operations over these base types, but
we could easily do so.) *)
Inductive ty : Type :=
| TTop : ty
| TBool : ty
| TBase : id -> ty
| TArrow : ty -> ty -> ty
| TUnit : ty
.
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| tunit : tm
.
(* ----------------------------------------------------------------- *)
(** *** Substitution *)
(** The definition of substitution remains exactly the same as for the
pure STLC. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y =>
if beq_id x y then s else t
| tabs y T t1 =>
tabs y T (if beq_id x y then t1 else (subst x s t1))
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif (subst x s t1) (subst x s t2) (subst x s t3)
| tunit =>
tunit
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ----------------------------------------------------------------- *)
(** *** Reduction *)
(** Likewise the definitions of the [value] property and the [step]
relation. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse
| v_unit :
value tunit
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Hint Constructors step.
(* ================================================================= *)
(** ** Subtyping *)
(** Now we come to the interesting part. We begin by defining
the subtyping relation and developing some of its important
technical properties. *)
(** The definition of subtyping is just what we sketched in the
motivating discussion. *)
Reserved Notation "T '<:' U" (at level 40).
Inductive subtype : ty -> ty -> Prop :=
| S_Refl : forall T,
T <: T
| S_Trans : forall S U T,
S <: U ->
U <: T ->
S <: T
| S_Top : forall S,
S <: TTop
| S_Arrow : forall S1 S2 T1 T2,
T1 <: S1 ->
S2 <: T2 ->
(TArrow S1 S2) <: (TArrow T1 T2)
where "T '<:' U" := (subtype T U).
(** Note that we don't need any special rules for base types: they are
automatically subtypes of themselves (by [S_Refl]) and [Top] (by
[S_Top]), and that's all we want. *)
Hint Constructors subtype.
Module Examples.
Notation x := (Id 0).
Notation y := (Id 1).
Notation z := (Id 2).
Notation A := (TBase (Id 6)).
Notation B := (TBase (Id 7)).
Notation C := (TBase (Id 8)).
Notation String := (TBase (Id 9)).
Notation Float := (TBase (Id 10)).
Notation Integer := (TBase (Id 11)).
Example subtyping_example_0 :
(TArrow C TBool) <: (TArrow C TTop).
(* C->Bool <: C->Top *)
Proof. auto. Qed.
(** **** Exercise: 2 stars, optional (subtyping_judgements) *)
(** (Wait to do this exercise after you have added product types to the
language -- see exercise [products] -- at least up to this point
in the file).
Recall that, in chapter [MoreStlc], the optional section "Encoding
Records" describes how records can be encoded as pairs.
Using this encoding, define pair types representing the following
record types:
Person := { name : String }
Student := { name : String ;
gpa : Float }
Employee := { name : String ;
ssn : Integer }
*)
Definition Person : ty :=
(* FILL IN HERE *) admit.
Definition Student : ty :=
(* FILL IN HERE *) admit.
Definition Employee : ty :=
(* FILL IN HERE *) admit.
(** Now use the definition of the subtype relation to prove the following: *)
Example sub_student_person :
Student <: Person.
Proof.
(* FILL IN HERE *) Admitted.
Example sub_employee_person :
Employee <: Person.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The following facts are mostly easy to prove in Coq. To get
full benefit from the exercises, make sure you also
understand how to prove them on paper! *)
(** **** Exercise: 1 star, optional (subtyping_example_1) *)
Example subtyping_example_1 :
(TArrow TTop Student) <: (TArrow (TArrow C C) Person).
(* Top->Student <: (C->C)->Person *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (subtyping_example_2) *)
Example subtyping_example_2 :
(TArrow TTop Person) <: (TArrow Person TTop).
(* Top->Person <: Person->Top *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples.
(* ================================================================= *)
(** ** Typing *)
(** The only change to the typing relation is the addition of the rule
of subsumption, [T_Sub]. *)
Definition context := partial_map ty.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
(* Same as before *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- (tvar x) \in T
| T_Abs : forall Gamma x T11 T12 t12,
(update Gamma x T11) |- t12 \in T12 ->
Gamma |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (TArrow T1 T2) ->
Gamma |- t2 \in T1 ->
Gamma |- (tapp t1 t2) \in T2
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- (tif t1 t2 t3) \in T
| T_Unit : forall Gamma,
Gamma |- tunit \in TUnit
(* New rule of subsumption *)
| T_Sub : forall Gamma t S T,
Gamma |- t \in S ->
S <: T ->
Gamma |- t \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
(** The following hints help [auto] and [eauto] construct typing
derivations. (See chapter [UseAuto] for more on hints.) *)
Hint Extern 2 (has_type _ (tapp _ _) _) =>
eapply T_App; auto.
Hint Extern 2 (_ = _) => compute; reflexivity.
Module Examples2.
Import Examples.
(** Do the following exercises after you have added product types to
the language. For each informal typing judgement, write it as a
formal statement in Coq and prove it. *)
(** **** Exercise: 1 star, optional (typing_example_0) *)
(* empty |- ((\z:A.z), (\z:B.z))
: (A->A * B->B) *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (typing_example_1) *)
(* empty |- (\x:(Top * B->B). x.snd) ((\z:A.z), (\z:B.z))
: B->B *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (typing_example_2) *)
(* empty |- (\z:(C->C)->(Top * B->B). (z (\x:C.x)).snd)
(\z:C->C. ((\z:A.z), (\z:B.z)))
: B->B *)
(* FILL IN HERE *)
(** [] *)
End Examples2.
(* ################################################################# *)
(** * Properties *)
(** The fundamental properties of the system that we want to
check are the same as always: progress and preservation. Unlike
the extension of the STLC with references (chapter [References]),
we don't need to change the _statements_ of these properties to
take subtyping into account. However, their proofs do become a
little bit more involved. *)
(* ================================================================= *)
(** ** Inversion Lemmas for Subtyping *)
(** Before we look at the properties of the typing relation, we need
to establish a couple of critical structural properties of the
subtype relation:
- [Bool] is the only subtype of [Bool], and
- every subtype of an arrow type is itself an arrow type. *)
(** These are called _inversion lemmas_ because they play a
similar role in proofs as the built-in [inversion] tactic: given a
hypothesis that there exists a derivation of some subtyping
statement [S <: T] and some constraints on the shape of [S] and/or
[T], each inversion lemma reasons about what this derivation must
look like to tell us something further about the shapes of [S] and
[T] and the existence of subtype relations between their parts. *)
(** **** Exercise: 2 stars, optional (sub_inversion_Bool) *)
Lemma sub_inversion_Bool : forall U,
U <: TBool ->
U = TBool.
Proof with auto.
intros U Hs.
remember TBool as V.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
U <: (TArrow V1 V2) ->
exists U1, exists U2,
U = (TArrow U1 U2) /\ (V1 <: U1) /\ (U2 <: V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (TArrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Canonical Forms *)
(** The proof of the progress theorem -- that a well-typed
non-value can always take a step -- doesn't need to change too
much: we just need one small refinement. When we're considering
the case where the term in question is an application [t1 t2]
where both [t1] and [t2] are values, we need to know that [t1] has
the _form_ of a lambda-abstraction, so that we can apply the
[ST_AppAbs] reduction rule. In the ordinary STLC, this is
obvious: we know that [t1] has a function type [T11->T12], and
there is only one rule that can be used to give a function type to
a value -- rule [T_Abs] -- and the form of the conclusion of this
rule forces [t1] to be an abstraction.
In the STLC with subtyping, this reasoning doesn't quite work
because there's another rule that can be used to show that a value
has a function type: subsumption. Fortunately, this possibility
doesn't change things much: if the last rule used to show [Gamma
|- t1 : T11->T12] is subsumption, then there is some
_sub_-derivation whose subject is also [t1], and we can reason by
induction until we finally bottom out at a use of [T_Abs].
This bit of reasoning is packaged up in the following lemma, which
tells us the possible "canonical forms" (i.e., values) of function
type. *)
(** **** Exercise: 3 stars, optional (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
Gamma |- s \in (TArrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tabs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Similarly, the canonical forms of type [Bool] are the constants
[true] and [false]. *)
Lemma canonical_forms_of_Bool : forall Gamma s,
Gamma |- s \in TBool ->
value s ->
(s = ttrue \/ s = tfalse).
Proof with eauto.
intros Gamma s Hty Hv.
remember TBool as T.
induction Hty; try solve by inversion...
- (* T_Sub *)
subst. apply sub_inversion_Bool in H. subst...
Qed.
(* ================================================================= *)
(** ** Progress *)
(** The proof of progress now proceeds just like the one for the
pure STLC, except that in several places we invoke canonical forms
lemmas... *)
(** _Theorem_ (Progress): For any term [t] and type [T], if [empty |-
t : T] then [t] is a value or [t ==> t'] for some term [t'].
_Proof_: Let [t] and [T] be given, with [empty |- t : T]. Proceed
by induction on the typing derivation.
The cases for [T_Abs], [T_Unit], [T_True] and [T_False] are
immediate because abstractions, [unit], [true], and [false] are
already values. The [T_Var] case is vacuous because variables
cannot be typed in the empty context. The remaining cases are
more interesting:
- If the last step in the typing derivation uses rule [T_App],
then there are terms [t1] [t2] and types [T1] and [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2], and [empty |-
t2 : T1]. Moreover, by the induction hypothesis, either [t1] is
a value or it steps, and either [t2] is a value or it steps.
There are three possibilities to consider:
- Suppose [t1 ==> t1'] for some term [t1']. Then [t1 t2 ==> t1' t2]
by [ST_App1].
- Suppose [t1] is a value and [t2 ==> t2'] for some term [t2'].
Then [t1 t2 ==> t1 t2'] by rule [ST_App2] because [t1] is a
value.
- Finally, suppose [t1] and [t2] are both values. By the lemma
about canonical forms for arrow types, we know that [t1] has the
form [\x:S1.s2] for some [x], [S1], and [s2]. But then
[(\x:S1.s2) t2 ==> [x:=t2]s2] by [ST_AppAbs], since [t2] is a
value.
- If the final step of the derivation uses rule [T_If], then there
are terms [t1], [t2], and [t3] such that [t = if t1 then t2 else
t3], with [empty |- t1 : Bool] and with [empty |- t2 : T] and
[empty |- t3 : T]. Moreover, by the induction hypothesis,
either [t1] is a value or it steps.
- If [t1] is a value, then by the canonical forms lemma for
booleans, either [t1 = true] or [t1 = false]. In either
case, [t] can step, using rule [ST_IfTrue] or [ST_IfFalse].
- If [t1] can step, then so can [t], by rule [ST_If].
- If the final step of the derivation is by [T_Sub], then there is
a type [S] such that [S <: T] and [empty |- t : S]. The desired
result is exactly the induction hypothesis for the typing
subderivation. *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
induction Ht;
intros HeqGamma; subst...
- (* T_Var *)
inversion H.
- (* T_App *)
right.
destruct IHHt1; subst...
+ (* t1 is a value *)
destruct IHHt2; subst...
* (* t2 is a value *)
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists ([x:=t2]t12)...
* (* t2 steps *)
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
+ (* t1 steps *)
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
- (* T_If *)
right.
destruct IHHt1.
+ (* t1 is a value *) eauto.
+ assert (t1 = ttrue \/ t1 = tfalse)
by (eapply canonical_forms_of_Bool; eauto).
inversion H0; subst...
+ inversion H. rename x into t1'. eauto.
Qed.
(* ================================================================= *)
(** ** Inversion Lemmas for Typing *)
(** The proof of the preservation theorem also becomes a little more
complex with the addition of subtyping. The reason is that, as
with the "inversion lemmas for subtyping" above, there are a
number of facts about the typing relation that are immediate from
the definition in the pure STLC (formally: that can be obtained
directly from the [inversion] tactic) but that require real proofs
in the presence of subtyping because there are multiple ways to
derive the same [has_type] statement.
The following inversion lemma tells us that, if we have a
derivation of some typing statement [Gamma |- \x:S1.t2 : T] whose
subject is an abstraction, then there must be some subderivation
giving a type to the body [t2]. *)
(** _Lemma_: If [Gamma |- \x:S1.t2 : T], then there is a type [S2]
such that [Gamma, x:S1 |- t2 : S2] and [S1 -> S2 <: T].
(Notice that the lemma does _not_ say, "then [T] itself is an arrow
type" -- this is tempting, but false!)
_Proof_: Let [Gamma], [x], [S1], [t2] and [T] be given as
described. Proceed by induction on the derivation of [Gamma |-
\x:S1.t2 : T]. Cases [T_Var], [T_App], are vacuous as those
rules cannot be used to give a type to a syntactic abstraction.
- If the last step of the derivation is a use of [T_Abs] then
there is a type [T12] such that [T = S1 -> T12] and [Gamma,
x:S1 |- t2 : T12]. Picking [T12] for [S2] gives us what we
need: [S1 -> T12 <: S1 -> T12] follows from [S_Refl].
- If the last step of the derivation is a use of [T_Sub] then
there is a type [S] such that [S <: T] and [Gamma |- \x:S1.t2 :
S]. The IH for the typing subderivation tell us that there is
some type [S2] with [S1 -> S2 <: S] and [Gamma, x:S1 |- t2 :
S2]. Picking type [S2] gives us what we need, since [S1 -> S2
<: T] then follows by [S_Trans]. *)
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
Gamma |- (tabs x S1 t2) \in T ->
(exists S2, (TArrow S1 S2) <: T
/\ (update Gamma x S1) |- t2 \in S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tabs x S1 t2) as t.
induction H;
inversion Heqt; subst; intros; try solve by inversion.
- (* T_Abs *)
exists T12...
- (* T_Sub *)
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
(** Similarly... *)
Lemma typing_inversion_var : forall Gamma x T,
Gamma |- (tvar x) \in T ->
exists S,
Gamma x = Some S /\ S <: T.
Proof with eauto.
intros Gamma x T Hty.
remember (tvar x) as t.
induction Hty; intros;
inversion Heqt; subst; try solve by inversion.
- (* T_Var *)
exists T...
- (* T_Sub *)
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
Gamma |- (tapp t1 t2) \in T2 ->
exists T1,
Gamma |- t1 \in (TArrow T1 T2) /\
Gamma |- t2 \in T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tapp t1 t2) as t.
induction Hty; intros;
inversion Heqt; subst; try solve by inversion.
- (* T_App *)
exists T1...
- (* T_Sub *)
destruct IHHty as [U1 [Hty1 Hty2]]...
Qed.
Lemma typing_inversion_true : forall Gamma T,
Gamma |- ttrue \in T ->
TBool <: T.
Proof with eauto.
intros Gamma T Htyp. remember ttrue as tu.
induction Htyp;
inversion Heqtu; subst; intros...
Qed.
Lemma typing_inversion_false : forall Gamma T,
Gamma |- tfalse \in T ->
TBool <: T.
Proof with eauto.
intros Gamma T Htyp. remember tfalse as tu.
induction Htyp;
inversion Heqtu; subst; intros...
Qed.
Lemma typing_inversion_if : forall Gamma t1 t2 t3 T,
Gamma |- (tif t1 t2 t3) \in T ->
Gamma |- t1 \in TBool
/\ Gamma |- t2 \in T
/\ Gamma |- t3 \in T.
Proof with eauto.
intros Gamma t1 t2 t3 T Hty.
remember (tif t1 t2 t3) as t.
induction Hty; intros;
inversion Heqt; subst; try solve by inversion.
- (* T_If *)
auto.
- (* T_Sub *)
destruct (IHHty H0) as [H1 [H2 H3]]...
Qed.
Lemma typing_inversion_unit : forall Gamma T,
Gamma |- tunit \in T ->
TUnit <: T.
Proof with eauto.
intros Gamma T Htyp. remember tunit as tu.
induction Htyp;
inversion Heqtu; subst; intros...
Qed.
(** The inversion lemmas for typing and for subtyping between arrow
types can be packaged up as a useful "combination lemma" telling
us exactly what we'll actually require below. *)
Lemma abs_arrow : forall x S1 s2 T1 T2,
empty |- (tabs x S1 s2) \in (TArrow T1 T2) ->
T1 <: S1
/\ (update empty x S1) |- s2 \in T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
inversion Hty as [S2 [Hsub Hty1]].
apply sub_inversion_arrow in Hsub.
inversion Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ================================================================= *)
(** ** Context Invariance *)
(** The context invariance lemma follows the same pattern as in the
pure STLC. *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3)
.
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
Gamma |- t \in S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in S.
Proof with eauto.
intros. generalize dependent Gamma'.
induction H;
intros Gamma' Heqv...
- (* T_Var *)
apply T_Var... rewrite <- Heqv...
- (* T_Abs *)
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold update, t_update. destruct (beq_idP x x0)...
- (* T_If *)
apply T_If...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
induction Htyp;
subst; inversion Hafi; subst...
- (* T_Abs *)
destruct (IHHtyp H4) as [T Hctx]. exists T.
unfold update, t_update in Hctx.
rewrite <- beq_id_false_iff in H2.
rewrite H2 in Hctx... Qed.
(* ================================================================= *)
(** ** Substitution *)
(** The _substitution lemma_ is proved along the same lines as
for the pure STLC. The only significant change is that there are
several places where, instead of the built-in [inversion] tactic,
we need to use the inversion lemmas that we proved above to
extract structural information from assumptions about the
well-typedness of subterms. *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
(update Gamma x U) |- t \in S ->
empty |- v \in U ->
Gamma |- ([x:=v]t) \in S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
induction t; intros; simpl.
- (* tvar *)
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt)
as [T [Hctx Hsub]].
unfold update, t_update in Hctx.
destruct (beq_idP x y) as [Hxy|Hxy]; eauto;
subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra)
as [T' HT']...
inversion HT'.
- (* tapp *)
destruct (typing_inversion_app _ _ _ _ Htypt)
as [T1 [Htypt1 Htypt2]].
eapply T_App...
- (* tabs *)
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
apply T_Sub with (TArrow T1 T2)... apply T_Abs...
destruct (beq_idP x y) as [Hxy|Hxy].
+ (* x=y *)
eapply context_invariance...
subst.
intros x Hafi. unfold update, t_update.
destruct (beq_id y x)...
+ (* x<>y *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold update, t_update.
destruct (beq_idP y z)...
subst.
rewrite <- beq_id_false_iff in Hxy. rewrite Hxy...
- (* ttrue *)
assert (TBool <: S)
by apply (typing_inversion_true _ _ Htypt)...
- (* tfalse *)
assert (TBool <: S)
by apply (typing_inversion_false _ _ Htypt)...
- (* tif *)
assert ((update Gamma x U) |- t1 \in TBool
/\ (update Gamma x U) |- t2 \in S
/\ (update Gamma x U) |- t3 \in S)
by apply (typing_inversion_if _ _ _ _ _ Htypt).
inversion H as [H1 [H2 H3]].
apply IHt1 in H1. apply IHt2 in H2. apply IHt3 in H3.
auto.
- (* tunit *)
assert (TUnit <: S)
by apply (typing_inversion_unit _ _ Htypt)...
Qed.
(* ================================================================= *)
(** ** Preservation *)
(** The proof of preservation now proceeds pretty much as in earlier
chapters, using the substitution lemma at the appropriate point
and again using inversion lemmas from above to extract structural
information from typing assumptions. *)
(** _Theorem_ (Preservation): If [t], [t'] are terms and [T] is a type
such that [empty |- t : T] and [t ==> t'], then [empty |- t' :
T].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We
proceed by induction on the structure of this typing derivation,
leaving [t'] general. The cases [T_Abs], [T_Unit], [T_True], and
[T_False] cases are vacuous because abstractions and constants
don't step. Case [T_Var] is vacuous as well, since the context is
empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] and [t2] and types [T1] and [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2], and
[empty |- t2 : T1].
By the definition of the step relation, there are three ways
[t1 t2] can step. Cases [ST_App1] and [ST_App2] follow
immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then [t1 =
\x:S.t12] for some type [S] and term [t12], and [t' =
[x:=t2]t12].
By lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by the substitution lemma
([substitution_preserves_typing]) that [empty |- [x:=t2]
t12 : T2] as desired.
- If the final step of the derivation uses rule [T_If], then
there are terms [t1], [t2], and [t3] such that [t = if t1 then
t2 else t3], with [empty |- t1 : Bool] and with [empty |- t2 :
T] and [empty |- t3 : T]. Moreover, by the induction
hypothesis, if [t1] steps to [t1'] then [empty |- t1' : Bool].
There are three cases to consider, depending on which rule was
used to show [t ==> t'].
- If [t ==> t'] by rule [ST_If], then [t' = if t1' then t2
else t3] with [t1 ==> t1']. By the induction hypothesis,
[empty |- t1' : Bool], and so [empty |- t' : T] by [T_If].
- If [t ==> t'] by rule [ST_IfTrue] or [ST_IfFalse], then
either [t' = t2] or [t' = t3], and [empty |- t' : T]
follows by assumption.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub]. [] *)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
induction HT;
intros t' HeqGamma HE; subst; inversion HE; subst...
- (* T_App *)
inversion HE; subst...
+ (* ST_AppAbs *)
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
Qed.
(* ================================================================= *)
(** ** Records, via Products and Top *)
(** This formalization of the STLC with subtyping omits record
types for brevity. If we want to deal with them more seriously,
we have two choices.
First, we can treat them as part of the core language, writing
down proper syntax, typing, and subtyping rules for them. Chapter
[RecordSub] shows how this extension works.
On the other hand, if we are treating them as a derived form that
is desugared in the parser, then we shouldn't need any new rules:
we should just check that the existing rules for subtyping product
and [Unit] types give rise to reasonable rules for record
subtyping via this encoding. To do this, we just need to make one
small change to the encoding described earlier: instead of using
[Unit] as the base case in the encoding of tuples and the "don't
care" placeholder in the encoding of records, we use [Top]. So:
{a:Nat, b:Nat} ----> {Nat,Nat} i.e., (Nat,(Nat,Top))
{c:Nat, a:Nat} ----> {Nat,Top,Nat} i.e., (Nat,(Top,(Nat,Top)))
The encoding of record values doesn't change at all. It is
easy (and instructive) to check that the subtyping rules above are
validated by the encoding. *)
(* ================================================================= *)
(** ** Exercises *)
(** **** Exercise: 2 stars (variations) *)
(** Each part of this problem suggests a different way of changing the
definition of the STLC with Unit and subtyping. (These changes
are not cumulative: each part starts from the original language.)
In each part, list which properties (Progress, Preservation, both,
or neither) become false. If a property becomes false, give a
counterexample.
- Suppose we add the following typing rule:
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
- Suppose we add the following reduction rule:
-------------------- (ST_Funny21)
unit ==> (\x:Top. x)
- Suppose we add the following subtyping rule:
---------------- (S_Funny3)
Unit <: Top->Top
- Suppose we add the following subtyping rule:
---------------- (S_Funny4)
Top->Top <: Unit
- Suppose we add the following reduction rule:
--------------------- (ST_Funny5)
(unit t) ==> (t unit)
- Suppose we add the same reduction rule _and_ a new typing rule:
--------------------- (ST_Funny5)
(unit t) ==> (t unit)
------------------------ (T_Funny6)
empty |- Unit : Top->Top
- Suppose we _change_ the arrow subtyping rule to:
S1 <: T1 S2 <: T2
----------------- (S_Arrow')
S1->S2 <: T1->T2
[] *)
(* ################################################################# *)
(** * Exercise: Adding Products *)
(** **** Exercise: 4 stars (products) *)
(** Adding pairs, projections, and product types to the system we have
defined is a relatively straightforward matter. Carry out this
extension:
- Add constructors for pairs, first and second projections, and
product types to the definitions of [ty] and [tm]. (Don't
forget to add corresponding cases to [T_cases] and [t_cases].)
- Extend the substitution function and value relation as in
chapter [MoreSTLC].
- Extend the operational semantics with the same reduction rules
as in chapter [MoreSTLC].
- Extend the subtyping relation with this rule:
S1 <: T1 S2 <: T2
--------------------- (Sub_Prod)
S1 * S2 <: T1 * T2
- Extend the typing relation with the same rules for pairs and
projections as in chapter [MoreSTLC].
- Extend the proofs of progress, preservation, and all their
supporting lemmas to deal with the new constructs. (You'll also
need to add some completely new lemmas.)
[] *)
(** $Date: 2016-05-26 17:51:14 -0400 (Thu, 26 May 2016) $ *)
|
`timescale 1 ns / 1 ps
module axis_interconnector #
(
parameter integer C_PIXEL_WIDTH = 8,
parameter integer C_S_STREAM_NUM = 8,
parameter integer C_M_STREAM_NUM = 8,
parameter integer C_ONE2MANY = 0
)
(
input wire clk,
input wire resetn,
/// S0_AXIS
input wire s0_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s0_axis_tdata,
input wire s0_axis_tuser,
input wire s0_axis_tlast,
output wire s0_axis_tready,
input wire [C_M_STREAM_NUM-1:0] s0_dst_bmp,
/// M0_AXIS
output wire m0_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m0_axis_tdata,
output wire m0_axis_tuser,
output wire m0_axis_tlast,
input wire m0_axis_tready,
/// S1_AXIS
input wire s1_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s1_axis_tdata,
input wire s1_axis_tuser,
input wire s1_axis_tlast,
output wire s1_axis_tready,
input wire [C_M_STREAM_NUM-1:0] s1_dst_bmp,
/// M1_AXIS
output wire m1_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m1_axis_tdata,
output wire m1_axis_tuser,
output wire m1_axis_tlast,
input wire m1_axis_tready,
/// S2_AXIS
input wire s2_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s2_axis_tdata,
input wire s2_axis_tuser,
input wire s2_axis_tlast,
output wire s2_axis_tready,
input wire [C_M_STREAM_NUM-1:0] s2_dst_bmp,
/// M2_AXIS
output wire m2_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m2_axis_tdata,
output wire m2_axis_tuser,
output wire m2_axis_tlast,
input wire m2_axis_tready,
/// S3_AXIS
input wire s3_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s3_axis_tdata,
input wire s3_axis_tuser,
input wire s3_axis_tlast,
output wire s3_axis_tready,
input wire [C_M_STREAM_NUM-1:0] s3_dst_bmp,
/// M3_AXIS
output wire m3_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m3_axis_tdata,
output wire m3_axis_tuser,
output wire m3_axis_tlast,
input wire m3_axis_tready,
/// S4_AXIS
input wire s4_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s4_axis_tdata,
input wire s4_axis_tuser,
input wire s4_axis_tlast,
output wire s4_axis_tready,
input wire [C_M_STREAM_NUM-1:0] s4_dst_bmp,
/// M4_AXIS
output wire m4_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m4_axis_tdata,
output wire m4_axis_tuser,
output wire m4_axis_tlast,
input wire m4_axis_tready,
/// S5_AXIS
input wire s5_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s5_axis_tdata,
input wire s5_axis_tuser,
input wire s5_axis_tlast,
output wire s5_axis_tready,
input wire [C_M_STREAM_NUM-1:0] s5_dst_bmp,
/// M5_AXIS
output wire m5_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m5_axis_tdata,
output wire m5_axis_tuser,
output wire m5_axis_tlast,
input wire m5_axis_tready,
/// S6_AXIS
input wire s6_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s6_axis_tdata,
input wire s6_axis_tuser,
input wire s6_axis_tlast,
output wire s6_axis_tready,
input wire [C_M_STREAM_NUM-1:0] s6_dst_bmp,
/// M6_AXIS
output wire m6_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m6_axis_tdata,
output wire m6_axis_tuser,
output wire m6_axis_tlast,
input wire m6_axis_tready,
/// S7_AXIS
input wire s7_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s7_axis_tdata,
input wire s7_axis_tuser,
input wire s7_axis_tlast,
output wire s7_axis_tready,
input wire [C_M_STREAM_NUM-1:0] s7_dst_bmp,
/// M7_AXIS
output wire m7_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m7_axis_tdata,
output wire m7_axis_tuser,
output wire m7_axis_tlast,
input wire m7_axis_tready
);
localparam integer C_MAX_STREAM_NUM = 8;
generate
genvar i;
genvar j;
endgenerate
wire s_tvalid [C_MAX_STREAM_NUM-1:0];
wire [C_PIXEL_WIDTH-1:0] s_tdata [C_MAX_STREAM_NUM-1:0];
wire s_tuser [C_MAX_STREAM_NUM-1:0];
wire s_tlast [C_MAX_STREAM_NUM-1:0];
wire s_tready [C_MAX_STREAM_NUM-1:0];
wire [C_M_STREAM_NUM-1:0] s_dst_bmp[C_MAX_STREAM_NUM-1:0];
wire m_tvalid [C_MAX_STREAM_NUM-1:0];
wire [C_PIXEL_WIDTH-1:0] m_tdata [C_MAX_STREAM_NUM-1:0];
wire m_tuser [C_MAX_STREAM_NUM-1:0];
wire m_tlast [C_MAX_STREAM_NUM-1:0];
wire m_tready [C_MAX_STREAM_NUM-1:0];
`define ASSIGN_STREAM(i) \
assign s_tvalid[i] = s``i``_axis_tvalid; \
assign s_tdata[i] = s``i``_axis_tdata; \
assign s_tuser[i] = s``i``_axis_tuser; \
assign s_tlast[i] = s``i``_axis_tlast; \
assign s``i``_axis_tready = s_tready[i]; \
assign s_dst_bmp[i] = s``i``_dst_bmp; \
assign m``i``_axis_tvalid = m_tvalid[i]; \
assign m``i``_axis_tdata = m_tdata[i] ; \
assign m``i``_axis_tuser = m_tuser[i] ; \
assign m``i``_axis_tlast = m_tlast[i] ; \
assign m_tready[i] = m``i``_axis_tready; \
`ASSIGN_STREAM(0)
`ASSIGN_STREAM(1)
`ASSIGN_STREAM(2)
`ASSIGN_STREAM(3)
`ASSIGN_STREAM(4)
`ASSIGN_STREAM(5)
`ASSIGN_STREAM(6)
`ASSIGN_STREAM(7)
/// convert
wire [C_S_STREAM_NUM-1:0] sc_tvalid ;
wire [C_S_STREAM_NUM-1:0] sc_tdata [C_PIXEL_WIDTH-1:0];
wire [C_S_STREAM_NUM-1:0] sc_tuser ;
wire [C_S_STREAM_NUM-1:0] sc_tlast ;
wire [C_S_STREAM_NUM-1:0] sc_tready ;
reg m_valid[C_M_STREAM_NUM-1:0];
reg [C_PIXEL_WIDTH-1:0] m_data [C_M_STREAM_NUM-1:0];
reg m_user [C_M_STREAM_NUM-1:0];
reg m_last [C_M_STREAM_NUM-1:0];
wire [C_M_STREAM_NUM-1:0] m_4s_ready;
wire [C_M_STREAM_NUM-1:0] s_2m_valid;
wire [C_M_STREAM_NUM-1:0] s_2m_next;
wire [C_S_STREAM_NUM-1:0] m_src_bmp[C_M_STREAM_NUM-1:0];
generate
for (i = 0; i < C_S_STREAM_NUM; i = i+1) begin: single_stream_convert
assign sc_tvalid[i] = s_tvalid[i];
assign sc_tuser [i] = s_tuser [i];
assign sc_tlast [i] = s_tlast [i];
assign s_tready[i] = sc_tready[i];
for (j = 0; j < C_PIXEL_WIDTH; j = j + 1) begin: single_stream_bit_convert
assign sc_tdata [j][i] = s_tdata [i][j];
end
if (C_ONE2MANY)
assign sc_tready[i] = ((m_4s_ready & s_dst_bmp[i]) == s_dst_bmp[i]);
else
assign sc_tready[i] = ((m_4s_ready & s_dst_bmp[i]) != 0);
end
for (i = C_S_STREAM_NUM; i < C_MAX_STREAM_NUM; i = i+1) begin: disabled_s_stream
assign s_tready[i] = 0;
end
endgenerate
generate
for (i = 0; i < C_M_STREAM_NUM; i = i+1) begin: single_out
for (j = 0; j < C_S_STREAM_NUM; j = j+1) begin: single_in_bmp
assign m_src_bmp[i][j] = s_dst_bmp[j][i];
end
assign m_4s_ready[i] = (~m_tvalid[i] | m_tready[i]);
assign m_tvalid[i] = m_valid[i];
assign m_tdata [i] = m_data[i];
assign m_tuser [i] = m_user[i];
assign m_tlast [i] = m_last[i];
assign s_2m_valid[i] = ((sc_tvalid & m_src_bmp[i]) != 0);
if (C_ONE2MANY) begin
assign s_2m_next[i] = (s_2m_valid[i] && ((sc_tready & m_src_bmp[i]) != 0));
always @ (posedge clk) begin
if (resetn == 1'b0)
m_valid[i] <= 0;
else if (s_2m_next[i])
m_valid[i] <= 1;
else if (m_tready[i])
m_valid[i] <= 0;
end
end
else begin
assign s_2m_next[i] = (s_2m_valid[i] && m_4s_ready[i]);
always @ (posedge clk) begin
if (resetn == 1'b0)
m_valid[i] <= 0;
else if (s_2m_valid[i])
m_valid[i] <= 1;
else if (m_tready[i])
m_valid[i] <= 0;
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m_user[i] <= 0;
m_last[i] <= 0;
end
else if (s_2m_next[i]) begin
m_user[i] <= ((sc_tuser & m_src_bmp[i]) != 0);
m_last[i] <= ((sc_tlast & m_src_bmp[i]) != 0);
end
end
for (j = 0; j < C_PIXEL_WIDTH; j=j+1) begin: single_bit_assign
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m_data[i][j] <= 0;
end
else if (s_2m_next[i]) begin
m_data[i][j] <= ((sc_tdata[j] & m_src_bmp[i]) != 0);
end
end
end
end
for (i = C_M_STREAM_NUM; i < C_MAX_STREAM_NUM; i = i+1) begin: disabled_m_stream
assign m_tvalid[i] = 0;
assign m_tdata [i] = 0;
assign m_tuser [i] = 0;
assign m_tlast [i] = 0;
end
endgenerate
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 15:47:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.v
// Design : system_clk_wiz_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module system_clk_wiz_0_0
(clk_out1,
resetn,
locked,
clk_in1);
output clk_out1;
input resetn;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
wire resetn;
system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.resetn(resetn));
endmodule
(* ORIG_REF_NAME = "system_clk_wiz_0_0_clk_wiz" *)
module system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
(clk_out1,
resetn,
locked,
clk_in1);
output clk_out1;
input resetn;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_system_clk_wiz_0_0;
wire clk_out1;
wire clk_out1_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfbout_system_clk_wiz_0_0;
wire locked;
wire reset_high;
wire resetn;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_system_clk_wiz_0_0),
.O(clkfbout_buf_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_system_clk_wiz_0_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(36.500000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(8.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(36.500000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_system_clk_wiz_0_0),
.CLKFBOUT(clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_system_clk_wiz_0_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_system_clk_wiz_0_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset_high));
LUT1 #(
.INIT(2'h1))
mmcm_adv_inst_i_1
(.I0(resetn),
.O(reset_high));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_hex0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 6: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 6: 0] data_out;
wire [ 6: 0] out_port;
wire [ 6: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {7 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 127;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[6 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND4BB_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_TB_V
`define SKY130_FD_SC_HDLL__BUF_TB_V
/**
* buf: Buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__buf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__buf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_TB_V
|
/* Generated by Yosys 0.8+498 (git sha1 b67a098, gcc 7.3.1 -fPIC -Os) */
module gcd(clk, \req_msg[0] , \req_msg[1] , \req_msg[2] , \req_msg[3] , \req_msg[4] , \req_msg[5] , \req_msg[6] , \req_msg[7] , \req_msg[8] , \req_msg[9] , \req_msg[10] , \req_msg[11] , \req_msg[12] , \req_msg[13] , \req_msg[14] , \req_msg[15] , \req_msg[16] , \req_msg[17] , \req_msg[18] , \req_msg[19] , \req_msg[20] , \req_msg[21] , \req_msg[22] , \req_msg[23] , \req_msg[24] , \req_msg[25] , \req_msg[26] , \req_msg[27] , \req_msg[28] , \req_msg[29] , \req_msg[30] , \req_msg[31] , req_rdy, req_val, reset, \resp_msg[0] , \resp_msg[1] , \resp_msg[2] , \resp_msg[3] , \resp_msg[4] , \resp_msg[5] , \resp_msg[6] , \resp_msg[7] , \resp_msg[8] , \resp_msg[9] , \resp_msg[10] , \resp_msg[11] , \resp_msg[12] , \resp_msg[13] , \resp_msg[14] , \resp_msg[15] , resp_rdy, resp_val);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
input clk;
wire \ctrl.state.out_reg[0].qi ;
wire \ctrl.state.out_reg[1].qi ;
wire \dpath.a_reg.out_reg[0].qi ;
wire \dpath.a_reg.out_reg[10].qi ;
wire \dpath.a_reg.out_reg[11].qi ;
wire \dpath.a_reg.out_reg[12].qi ;
wire \dpath.a_reg.out_reg[13].qi ;
wire \dpath.a_reg.out_reg[14].qi ;
wire \dpath.a_reg.out_reg[15].qi ;
wire \dpath.a_reg.out_reg[1].qi ;
wire \dpath.a_reg.out_reg[2].qi ;
wire \dpath.a_reg.out_reg[3].qi ;
wire \dpath.a_reg.out_reg[4].qi ;
wire \dpath.a_reg.out_reg[5].qi ;
wire \dpath.a_reg.out_reg[6].qi ;
wire \dpath.a_reg.out_reg[7].qi ;
wire \dpath.a_reg.out_reg[8].qi ;
wire \dpath.a_reg.out_reg[9].qi ;
wire \dpath.b_reg.out_reg[0].qi ;
wire \dpath.b_reg.out_reg[10].qi ;
wire \dpath.b_reg.out_reg[11].qi ;
wire \dpath.b_reg.out_reg[12].qi ;
wire \dpath.b_reg.out_reg[13].qi ;
wire \dpath.b_reg.out_reg[14].qi ;
wire \dpath.b_reg.out_reg[15].qi ;
wire \dpath.b_reg.out_reg[1].qi ;
wire \dpath.b_reg.out_reg[2].qi ;
wire \dpath.b_reg.out_reg[3].qi ;
wire \dpath.b_reg.out_reg[4].qi ;
wire \dpath.b_reg.out_reg[5].qi ;
wire \dpath.b_reg.out_reg[6].qi ;
wire \dpath.b_reg.out_reg[7].qi ;
wire \dpath.b_reg.out_reg[8].qi ;
wire \dpath.b_reg.out_reg[9].qi ;
input \req_msg[0] ;
input \req_msg[10] ;
input \req_msg[11] ;
input \req_msg[12] ;
input \req_msg[13] ;
input \req_msg[14] ;
input \req_msg[15] ;
input \req_msg[16] ;
input \req_msg[17] ;
input \req_msg[18] ;
input \req_msg[19] ;
input \req_msg[1] ;
input \req_msg[20] ;
input \req_msg[21] ;
input \req_msg[22] ;
input \req_msg[23] ;
input \req_msg[24] ;
input \req_msg[25] ;
input \req_msg[26] ;
input \req_msg[27] ;
input \req_msg[28] ;
input \req_msg[29] ;
input \req_msg[2] ;
input \req_msg[30] ;
input \req_msg[31] ;
input \req_msg[3] ;
input \req_msg[4] ;
input \req_msg[5] ;
input \req_msg[6] ;
input \req_msg[7] ;
input \req_msg[8] ;
input \req_msg[9] ;
output req_rdy;
input req_val;
input reset;
output \resp_msg[0] ;
output \resp_msg[10] ;
output \resp_msg[11] ;
output \resp_msg[12] ;
output \resp_msg[13] ;
output \resp_msg[14] ;
output \resp_msg[15] ;
output \resp_msg[1] ;
output \resp_msg[2] ;
output \resp_msg[3] ;
output \resp_msg[4] ;
output \resp_msg[5] ;
output \resp_msg[6] ;
output \resp_msg[7] ;
output \resp_msg[8] ;
output \resp_msg[9] ;
input resp_rdy;
output resp_val;
NOR2_X2 _276_ (
.A1(\ctrl.state.out_reg[1].qi ),
.A2(\ctrl.state.out_reg[0].qi ),
.ZN(_034_)
);
BUF_X4 _277_ (
.A(_034_),
.Z(req_rdy)
);
INV_X1 _278_ (
.A(\dpath.a_reg.out_reg[15].qi ),
.ZN(_035_)
);
NOR2_X1 _279_ (
.A1(_035_),
.A2(\dpath.b_reg.out_reg[15].qi ),
.ZN(_036_)
);
INV_X1 _280_ (
.A(_036_),
.ZN(_037_)
);
INV_X1 _281_ (
.A(\dpath.b_reg.out_reg[13].qi ),
.ZN(_038_)
);
NOR2_X1 _282_ (
.A1(_038_),
.A2(\dpath.a_reg.out_reg[13].qi ),
.ZN(_039_)
);
INV_X1 _283_ (
.A(\dpath.b_reg.out_reg[12].qi ),
.ZN(_040_)
);
NOR2_X1 _284_ (
.A1(_040_),
.A2(\dpath.a_reg.out_reg[12].qi ),
.ZN(_041_)
);
NOR2_X1 _285_ (
.A1(_039_),
.A2(_041_),
.ZN(_042_)
);
INV_X1 _286_ (
.A(\dpath.b_reg.out_reg[14].qi ),
.ZN(_043_)
);
NOR2_X1 _287_ (
.A1(_043_),
.A2(\dpath.a_reg.out_reg[14].qi ),
.ZN(_044_)
);
INV_X1 _288_ (
.A(_044_),
.ZN(_045_)
);
AND2_X1 _289_ (
.A1(_042_),
.A2(_045_),
.ZN(_046_)
);
INV_X1 _290_ (
.A(\dpath.b_reg.out_reg[9].qi ),
.ZN(_047_)
);
NOR2_X1 _291_ (
.A1(_047_),
.A2(\dpath.a_reg.out_reg[9].qi ),
.ZN(_048_)
);
INV_X1 _292_ (
.A(\dpath.a_reg.out_reg[8].qi ),
.ZN(_049_)
);
AOI21_X1 _293_ (
.A(_048_),
.B1(\dpath.b_reg.out_reg[8].qi ),
.B2(_049_),
.ZN(_050_)
);
INV_X1 _294_ (
.A(\dpath.b_reg.out_reg[11].qi ),
.ZN(_051_)
);
NOR2_X1 _295_ (
.A1(_051_),
.A2(\dpath.a_reg.out_reg[11].qi ),
.ZN(_052_)
);
INV_X1 _296_ (
.A(\dpath.b_reg.out_reg[10].qi ),
.ZN(_053_)
);
NOR2_X1 _297_ (
.A1(_053_),
.A2(\dpath.a_reg.out_reg[10].qi ),
.ZN(_054_)
);
NOR2_X1 _298_ (
.A1(_052_),
.A2(_054_),
.ZN(_055_)
);
AND2_X1 _299_ (
.A1(_050_),
.A2(_055_),
.ZN(_056_)
);
INV_X16 _300_ (
.A(\dpath.b_reg.out_reg[3].qi ),
.ZN(_057_)
);
NOR2_X4 _301_ (
.A1(_057_),
.A2(\dpath.a_reg.out_reg[3].qi ),
.ZN(_058_)
);
INV_X16 _302_ (
.A(\dpath.a_reg.out_reg[2].qi ),
.ZN(_059_)
);
NOR3_X2 _303_ (
.A1(_058_),
.A2(\dpath.b_reg.out_reg[2].qi ),
.A3(_059_),
.ZN(_060_)
);
AOI21_X1 _304_ (
.A(_060_),
.B1(_057_),
.B2(\dpath.a_reg.out_reg[3].qi ),
.ZN(_061_)
);
INV_X1 _305_ (
.A(_061_),
.ZN(_062_)
);
INV_X32 _306_ (
.A(\dpath.a_reg.out_reg[1].qi ),
.ZN(_063_)
);
AND2_X4 _307_ (
.A1(_063_),
.A2(\dpath.b_reg.out_reg[1].qi ),
.ZN(_064_)
);
INV_X4 _308_ (
.A(_064_),
.ZN(_065_)
);
INV_X32 _309_ (
.A(\dpath.a_reg.out_reg[0].qi ),
.ZN(_066_)
);
OAI211_X4 _310_ (
.A(\dpath.b_reg.out_reg[0].qi ),
.B(_066_),
.C1(_063_),
.C2(\dpath.b_reg.out_reg[1].qi ),
.ZN(_067_)
);
NAND2_X4 _311_ (
.A1(_065_),
.A2(_067_),
.ZN(_068_)
);
INV_X16 _312_ (
.A(\dpath.b_reg.out_reg[2].qi ),
.ZN(_069_)
);
NOR2_X1 _313_ (
.A1(_069_),
.A2(\dpath.a_reg.out_reg[2].qi ),
.ZN(_070_)
);
NOR3_X4 _314_ (
.A1(_068_),
.A2(_058_),
.A3(_070_),
.ZN(_071_)
);
NOR2_X2 _315_ (
.A1(_062_),
.A2(_071_),
.ZN(_072_)
);
INV_X1 _316_ (
.A(\dpath.b_reg.out_reg[4].qi ),
.ZN(_073_)
);
NOR2_X1 _317_ (
.A1(_073_),
.A2(\dpath.a_reg.out_reg[4].qi ),
.ZN(_074_)
);
INV_X32 _318_ (
.A(\dpath.b_reg.out_reg[5].qi ),
.ZN(_075_)
);
NOR2_X4 _319_ (
.A1(_075_),
.A2(\dpath.a_reg.out_reg[5].qi ),
.ZN(_076_)
);
INV_X4 _320_ (
.A(\dpath.a_reg.out_reg[6].qi ),
.ZN(_077_)
);
NAND2_X1 _321_ (
.A1(_077_),
.A2(\dpath.b_reg.out_reg[6].qi ),
.ZN(_078_)
);
INV_X1 _322_ (
.A(\dpath.b_reg.out_reg[7].qi ),
.ZN(_079_)
);
OAI21_X4 _323_ (
.A(_078_),
.B1(_079_),
.B2(\dpath.a_reg.out_reg[7].qi ),
.ZN(_080_)
);
NOR4_X4 _324_ (
.A1(_072_),
.A2(_074_),
.A3(_076_),
.A4(_080_),
.ZN(_081_)
);
NOR2_X1 _325_ (
.A1(_077_),
.A2(\dpath.b_reg.out_reg[6].qi ),
.ZN(_082_)
);
OAI21_X1 _326_ (
.A(_082_),
.B1(_079_),
.B2(\dpath.a_reg.out_reg[7].qi ),
.ZN(_083_)
);
INV_X1 _327_ (
.A(\dpath.a_reg.out_reg[7].qi ),
.ZN(_084_)
);
INV_X32 _328_ (
.A(\dpath.a_reg.out_reg[4].qi ),
.ZN(_085_)
);
NOR3_X2 _329_ (
.A1(_076_),
.A2(\dpath.b_reg.out_reg[4].qi ),
.A3(_085_),
.ZN(_086_)
);
AOI21_X4 _330_ (
.A(_086_),
.B1(_075_),
.B2(\dpath.a_reg.out_reg[5].qi ),
.ZN(_087_)
);
OAI221_X4 _331_ (
.A(_083_),
.B1(\dpath.b_reg.out_reg[7].qi ),
.B2(_084_),
.C1(_087_),
.C2(_080_),
.ZN(_088_)
);
OAI211_X1 _332_ (
.A(_046_),
.B(_056_),
.C1(_081_),
.C2(_088_),
.ZN(_089_)
);
AND2_X1 _333_ (
.A1(_035_),
.A2(\dpath.b_reg.out_reg[15].qi ),
.ZN(_090_)
);
INV_X1 _334_ (
.A(_090_),
.ZN(_091_)
);
NAND2_X1 _335_ (
.A1(_038_),
.A2(\dpath.a_reg.out_reg[13].qi ),
.ZN(_092_)
);
NAND2_X1 _336_ (
.A1(_040_),
.A2(\dpath.a_reg.out_reg[12].qi ),
.ZN(_093_)
);
NAND2_X1 _337_ (
.A1(_092_),
.A2(_093_),
.ZN(_094_)
);
INV_X1 _338_ (
.A(_039_),
.ZN(_095_)
);
NAND3_X1 _339_ (
.A1(_094_),
.A2(_045_),
.A3(_095_),
.ZN(_096_)
);
NAND2_X1 _340_ (
.A1(_043_),
.A2(\dpath.a_reg.out_reg[14].qi ),
.ZN(_097_)
);
NAND2_X1 _341_ (
.A1(_096_),
.A2(_097_),
.ZN(_098_)
);
INV_X1 _342_ (
.A(\dpath.b_reg.out_reg[8].qi ),
.ZN(_099_)
);
OAI211_X1 _343_ (
.A(_099_),
.B(\dpath.a_reg.out_reg[8].qi ),
.C1(_047_),
.C2(\dpath.a_reg.out_reg[9].qi ),
.ZN(_100_)
);
NAND2_X1 _344_ (
.A1(_047_),
.A2(\dpath.a_reg.out_reg[9].qi ),
.ZN(_101_)
);
AOI211_X1 _345_ (
.A(_052_),
.B(_054_),
.C1(_100_),
.C2(_101_),
.ZN(_102_)
);
NAND2_X1 _346_ (
.A1(_051_),
.A2(\dpath.a_reg.out_reg[11].qi ),
.ZN(_103_)
);
NAND2_X1 _347_ (
.A1(_053_),
.A2(\dpath.a_reg.out_reg[10].qi ),
.ZN(_104_)
);
OAI21_X1 _348_ (
.A(_103_),
.B1(_052_),
.B2(_104_),
.ZN(_105_)
);
OR2_X1 _349_ (
.A1(_102_),
.A2(_105_),
.ZN(_106_)
);
AOI21_X1 _350_ (
.A(_098_),
.B1(_106_),
.B2(_046_),
.ZN(_107_)
);
AND4_X1 _351_ (
.A1(_037_),
.A2(_089_),
.A3(_091_),
.A4(_107_),
.ZN(_108_)
);
AOI22_X1 _352_ (
.A1(_089_),
.A2(_107_),
.B1(_037_),
.B2(_091_),
.ZN(_109_)
);
OR2_X1 _353_ (
.A1(_108_),
.A2(_109_),
.ZN(\resp_msg[15] )
);
BUF_X4 _354_ (
.A(\ctrl.state.out_reg[1].qi ),
.Z(_110_)
);
INV_X2 _355_ (
.A(\ctrl.state.out_reg[0].qi ),
.ZN(_111_)
);
BUF_X4 _356_ (
.A(_111_),
.Z(_112_)
);
AND3_X1 _357_ (
.A1(_042_),
.A2(_091_),
.A3(_045_),
.ZN(_113_)
);
OAI211_X4 _358_ (
.A(_056_),
.B(_113_),
.C1(_081_),
.C2(_088_),
.ZN(_114_)
);
OAI21_X1 _359_ (
.A(_091_),
.B1(_098_),
.B2(_036_),
.ZN(_115_)
);
OAI21_X1 _360_ (
.A(_113_),
.B1(_102_),
.B2(_105_),
.ZN(_116_)
);
NAND3_X4 _361_ (
.A1(_114_),
.A2(_115_),
.A3(_116_),
.ZN(_117_)
);
NOR2_X1 _362_ (
.A1(_111_),
.A2(\ctrl.state.out_reg[1].qi ),
.ZN(_118_)
);
INV_X1 _363_ (
.A(_118_),
.ZN(_119_)
);
NOR2_X4 _364_ (
.A1(_117_),
.A2(_119_),
.ZN(_120_)
);
AOI221_X4 _365_ (
.A(_110_),
.B1(_112_),
.B2(\req_msg[31] ),
.C1(_120_),
.C2(\dpath.b_reg.out_reg[15].qi ),
.ZN(_121_)
);
AND2_X4 _366_ (
.A1(_117_),
.A2(_118_),
.ZN(_122_)
);
BUF_X4 _367_ (
.A(_122_),
.Z(_123_)
);
OAI21_X1 _368_ (
.A(_123_),
.B1(_109_),
.B2(_108_),
.ZN(_124_)
);
BUF_X4 _369_ (
.A(\ctrl.state.out_reg[1].qi ),
.Z(_125_)
);
AOI22_X1 _370_ (
.A1(_121_),
.A2(_124_),
.B1(_125_),
.B2(_035_),
.ZN(_008_)
);
NOR2_X2 _371_ (
.A1(_081_),
.A2(_088_),
.ZN(_126_)
);
NAND3_X1 _372_ (
.A1(_050_),
.A2(_042_),
.A3(_055_),
.ZN(_127_)
);
OR2_X1 _373_ (
.A1(_126_),
.A2(_127_),
.ZN(_128_)
);
AOI22_X1 _374_ (
.A1(_106_),
.A2(_042_),
.B1(_095_),
.B2(_094_),
.ZN(_129_)
);
NAND2_X1 _375_ (
.A1(_128_),
.A2(_129_),
.ZN(_130_)
);
XOR2_X1 _376_ (
.A(\dpath.b_reg.out_reg[14].qi ),
.B(\dpath.a_reg.out_reg[14].qi ),
.Z(_131_)
);
XNOR2_X1 _377_ (
.A(_130_),
.B(_131_),
.ZN(\resp_msg[14] )
);
INV_X1 _378_ (
.A(\ctrl.state.out_reg[1].qi ),
.ZN(_132_)
);
BUF_X4 _379_ (
.A(_132_),
.Z(_133_)
);
NOR2_X1 _380_ (
.A1(_133_),
.A2(\dpath.a_reg.out_reg[14].qi ),
.ZN(_134_)
);
NAND2_X1 _381_ (
.A1(\resp_msg[14] ),
.A2(_123_),
.ZN(_135_)
);
AOI221_X4 _382_ (
.A(\ctrl.state.out_reg[1].qi ),
.B1(_111_),
.B2(\req_msg[30] ),
.C1(_120_),
.C2(\dpath.b_reg.out_reg[14].qi ),
.ZN(_136_)
);
AOI21_X1 _383_ (
.A(_134_),
.B1(_135_),
.B2(_136_),
.ZN(_007_)
);
INV_X1 _384_ (
.A(_106_),
.ZN(_137_)
);
INV_X1 _385_ (
.A(_056_),
.ZN(_138_)
);
OAI211_X1 _386_ (
.A(_093_),
.B(_137_),
.C1(_126_),
.C2(_138_),
.ZN(_139_)
);
INV_X1 _387_ (
.A(_041_),
.ZN(_140_)
);
AND4_X1 _388_ (
.A1(_095_),
.A2(_139_),
.A3(_140_),
.A4(_092_),
.ZN(_141_)
);
AOI22_X1 _389_ (
.A1(_139_),
.A2(_140_),
.B1(_095_),
.B2(_092_),
.ZN(_142_)
);
NOR2_X1 _390_ (
.A1(_141_),
.A2(_142_),
.ZN(\resp_msg[13] )
);
NOR2_X1 _391_ (
.A1(_133_),
.A2(\dpath.a_reg.out_reg[13].qi ),
.ZN(_143_)
);
NAND2_X1 _392_ (
.A1(\resp_msg[13] ),
.A2(_123_),
.ZN(_144_)
);
AOI221_X4 _393_ (
.A(\ctrl.state.out_reg[1].qi ),
.B1(_111_),
.B2(\req_msg[29] ),
.C1(_120_),
.C2(\dpath.b_reg.out_reg[13].qi ),
.ZN(_145_)
);
AOI21_X1 _394_ (
.A(_143_),
.B1(_144_),
.B2(_145_),
.ZN(_006_)
);
OAI21_X1 _395_ (
.A(_137_),
.B1(_126_),
.B2(_138_),
.ZN(_146_)
);
XOR2_X1 _396_ (
.A(\dpath.b_reg.out_reg[12].qi ),
.B(\dpath.a_reg.out_reg[12].qi ),
.Z(_147_)
);
XNOR2_X1 _397_ (
.A(_146_),
.B(_147_),
.ZN(\resp_msg[12] )
);
NOR2_X1 _398_ (
.A1(_133_),
.A2(\dpath.a_reg.out_reg[12].qi ),
.ZN(_148_)
);
AOI221_X1 _399_ (
.A(_125_),
.B1(_112_),
.B2(\req_msg[28] ),
.C1(\resp_msg[12] ),
.C2(_122_),
.ZN(_149_)
);
BUF_X4 _400_ (
.A(_117_),
.Z(_150_)
);
OR3_X1 _401_ (
.A1(_150_),
.A2(_040_),
.A3(_119_),
.ZN(_151_)
);
AOI21_X1 _402_ (
.A(_148_),
.B1(_149_),
.B2(_151_),
.ZN(_005_)
);
INV_X1 _403_ (
.A(_054_),
.ZN(_152_)
);
OAI211_X1 _404_ (
.A(_050_),
.B(_152_),
.C1(_081_),
.C2(_088_),
.ZN(_153_)
);
AOI21_X1 _405_ (
.A(_054_),
.B1(_100_),
.B2(_101_),
.ZN(_154_)
);
AOI21_X1 _406_ (
.A(_154_),
.B1(\dpath.a_reg.out_reg[10].qi ),
.B2(_053_),
.ZN(_155_)
);
AND2_X1 _407_ (
.A1(_153_),
.A2(_155_),
.ZN(_156_)
);
XNOR2_X1 _408_ (
.A(\dpath.b_reg.out_reg[11].qi ),
.B(\dpath.a_reg.out_reg[11].qi ),
.ZN(_157_)
);
XNOR2_X1 _409_ (
.A(_156_),
.B(_157_),
.ZN(\resp_msg[11] )
);
NOR2_X1 _410_ (
.A1(_133_),
.A2(\dpath.a_reg.out_reg[11].qi ),
.ZN(_158_)
);
AOI221_X1 _411_ (
.A(_125_),
.B1(_112_),
.B2(\req_msg[27] ),
.C1(\resp_msg[11] ),
.C2(_122_),
.ZN(_159_)
);
OR3_X1 _412_ (
.A1(_150_),
.A2(_051_),
.A3(_119_),
.ZN(_160_)
);
AOI21_X1 _413_ (
.A(_158_),
.B1(_159_),
.B2(_160_),
.ZN(_004_)
);
OAI21_X1 _414_ (
.A(_050_),
.B1(_081_),
.B2(_088_),
.ZN(_161_)
);
AND2_X1 _415_ (
.A1(_100_),
.A2(_101_),
.ZN(_162_)
);
AND4_X1 _416_ (
.A1(_152_),
.A2(_161_),
.A3(_104_),
.A4(_162_),
.ZN(_163_)
);
AOI22_X1 _417_ (
.A1(_161_),
.A2(_162_),
.B1(_152_),
.B2(_104_),
.ZN(_164_)
);
OR2_X1 _418_ (
.A1(_163_),
.A2(_164_),
.ZN(\resp_msg[10] )
);
NOR2_X1 _419_ (
.A1(_133_),
.A2(\dpath.a_reg.out_reg[10].qi ),
.ZN(_165_)
);
AOI221_X4 _420_ (
.A(_110_),
.B1(_112_),
.B2(\req_msg[26] ),
.C1(_120_),
.C2(\dpath.b_reg.out_reg[10].qi ),
.ZN(_166_)
);
OAI21_X1 _421_ (
.A(_123_),
.B1(_164_),
.B2(_163_),
.ZN(_167_)
);
AOI21_X1 _422_ (
.A(_165_),
.B1(_166_),
.B2(_167_),
.ZN(_003_)
);
AOI21_X1 _423_ (
.A(_126_),
.B1(\dpath.b_reg.out_reg[8].qi ),
.B2(_049_),
.ZN(_168_)
);
NOR2_X1 _424_ (
.A1(_049_),
.A2(\dpath.b_reg.out_reg[8].qi ),
.ZN(_169_)
);
NOR2_X1 _425_ (
.A1(_168_),
.A2(_169_),
.ZN(_170_)
);
XNOR2_X1 _426_ (
.A(\dpath.b_reg.out_reg[9].qi ),
.B(\dpath.a_reg.out_reg[9].qi ),
.ZN(_171_)
);
XNOR2_X1 _427_ (
.A(_170_),
.B(_171_),
.ZN(\resp_msg[9] )
);
NOR2_X1 _428_ (
.A1(_133_),
.A2(\dpath.a_reg.out_reg[9].qi ),
.ZN(_172_)
);
AOI221_X2 _429_ (
.A(_110_),
.B1(_112_),
.B2(\req_msg[25] ),
.C1(\resp_msg[9] ),
.C2(_122_),
.ZN(_173_)
);
OR3_X1 _430_ (
.A1(_150_),
.A2(_047_),
.A3(_119_),
.ZN(_174_)
);
AOI21_X1 _431_ (
.A(_172_),
.B1(_173_),
.B2(_174_),
.ZN(_017_)
);
XNOR2_X1 _432_ (
.A(\dpath.b_reg.out_reg[8].qi ),
.B(\dpath.a_reg.out_reg[8].qi ),
.ZN(_175_)
);
XNOR2_X1 _433_ (
.A(_126_),
.B(_175_),
.ZN(\resp_msg[8] )
);
AOI221_X2 _434_ (
.A(_110_),
.B1(_112_),
.B2(\req_msg[24] ),
.C1(_123_),
.C2(\resp_msg[8] ),
.ZN(_176_)
);
OR3_X1 _435_ (
.A1(_150_),
.A2(_099_),
.A3(_119_),
.ZN(_177_)
);
AOI22_X1 _436_ (
.A1(_176_),
.A2(_177_),
.B1(_125_),
.B2(_049_),
.ZN(_016_)
);
NAND2_X1 _437_ (
.A1(_085_),
.A2(\dpath.b_reg.out_reg[4].qi ),
.ZN(_178_)
);
OAI221_X1 _438_ (
.A(_178_),
.B1(_075_),
.B2(\dpath.a_reg.out_reg[5].qi ),
.C1(_071_),
.C2(_062_),
.ZN(_179_)
);
NAND2_X1 _439_ (
.A1(_179_),
.A2(_087_),
.ZN(_180_)
);
XOR2_X1 _440_ (
.A(\dpath.a_reg.out_reg[6].qi ),
.B(\dpath.b_reg.out_reg[6].qi ),
.Z(_181_)
);
XNOR2_X1 _441_ (
.A(_180_),
.B(_181_),
.ZN(\resp_msg[6] )
);
AOI221_X2 _442_ (
.A(_110_),
.B1(_112_),
.B2(\req_msg[22] ),
.C1(_123_),
.C2(\resp_msg[6] ),
.ZN(_182_)
);
NAND2_X1 _443_ (
.A1(_120_),
.A2(\dpath.b_reg.out_reg[6].qi ),
.ZN(_183_)
);
AOI22_X1 _444_ (
.A1(_182_),
.A2(_183_),
.B1(_125_),
.B2(_077_),
.ZN(_014_)
);
OAI21_X1 _445_ (
.A(_072_),
.B1(\dpath.b_reg.out_reg[4].qi ),
.B2(_085_),
.ZN(_184_)
);
NAND2_X1 _446_ (
.A1(_184_),
.A2(_178_),
.ZN(_185_)
);
XNOR2_X1 _447_ (
.A(\dpath.b_reg.out_reg[5].qi ),
.B(\dpath.a_reg.out_reg[5].qi ),
.ZN(_186_)
);
XNOR2_X1 _448_ (
.A(_185_),
.B(_186_),
.ZN(\resp_msg[5] )
);
NOR2_X1 _449_ (
.A1(_133_),
.A2(\dpath.a_reg.out_reg[5].qi ),
.ZN(_187_)
);
AOI221_X1 _450_ (
.A(_110_),
.B1(_112_),
.B2(\req_msg[21] ),
.C1(_123_),
.C2(\resp_msg[5] ),
.ZN(_188_)
);
OR3_X1 _451_ (
.A1(_150_),
.A2(_075_),
.A3(_119_),
.ZN(_189_)
);
AOI21_X1 _452_ (
.A(_187_),
.B1(_188_),
.B2(_189_),
.ZN(_013_)
);
XNOR2_X1 _453_ (
.A(\dpath.b_reg.out_reg[4].qi ),
.B(\dpath.a_reg.out_reg[4].qi ),
.ZN(_190_)
);
XNOR2_X1 _454_ (
.A(_072_),
.B(_190_),
.ZN(\resp_msg[4] )
);
AOI221_X2 _455_ (
.A(_110_),
.B1(_111_),
.B2(\req_msg[20] ),
.C1(_123_),
.C2(\resp_msg[4] ),
.ZN(_191_)
);
OR3_X1 _456_ (
.A1(_150_),
.A2(_073_),
.A3(_119_),
.ZN(_192_)
);
AOI22_X1 _457_ (
.A1(_191_),
.A2(_192_),
.B1(_125_),
.B2(_085_),
.ZN(_012_)
);
AOI22_X1 _458_ (
.A1(_065_),
.A2(_067_),
.B1(_069_),
.B2(\dpath.a_reg.out_reg[2].qi ),
.ZN(_193_)
);
NOR2_X1 _459_ (
.A1(_193_),
.A2(_070_),
.ZN(_194_)
);
XOR2_X1 _460_ (
.A(\dpath.b_reg.out_reg[3].qi ),
.B(\dpath.a_reg.out_reg[3].qi ),
.Z(_195_)
);
XNOR2_X1 _461_ (
.A(_194_),
.B(_195_),
.ZN(\resp_msg[3] )
);
NOR2_X1 _462_ (
.A1(_133_),
.A2(\dpath.a_reg.out_reg[3].qi ),
.ZN(_196_)
);
AOI221_X1 _463_ (
.A(_110_),
.B1(_112_),
.B2(\req_msg[19] ),
.C1(_123_),
.C2(\resp_msg[3] ),
.ZN(_197_)
);
OR3_X1 _464_ (
.A1(_150_),
.A2(_057_),
.A3(_119_),
.ZN(_198_)
);
AOI21_X1 _465_ (
.A(_196_),
.B1(_197_),
.B2(_198_),
.ZN(_011_)
);
XNOR2_X1 _466_ (
.A(\dpath.b_reg.out_reg[2].qi ),
.B(\dpath.a_reg.out_reg[2].qi ),
.ZN(_199_)
);
XNOR2_X1 _467_ (
.A(_068_),
.B(_199_),
.ZN(\resp_msg[2] )
);
AOI221_X4 _468_ (
.A(_110_),
.B1(_111_),
.B2(\req_msg[18] ),
.C1(_122_),
.C2(\resp_msg[2] ),
.ZN(_200_)
);
OR3_X1 _469_ (
.A1(_150_),
.A2(_069_),
.A3(_119_),
.ZN(_201_)
);
AOI22_X1 _470_ (
.A1(_200_),
.A2(_201_),
.B1(_125_),
.B2(_059_),
.ZN(_010_)
);
XNOR2_X1 _471_ (
.A(\dpath.b_reg.out_reg[1].qi ),
.B(\dpath.a_reg.out_reg[1].qi ),
.ZN(_202_)
);
INV_X1 _472_ (
.A(\dpath.b_reg.out_reg[0].qi ),
.ZN(_203_)
);
NOR2_X1 _473_ (
.A1(_203_),
.A2(\dpath.a_reg.out_reg[0].qi ),
.ZN(_204_)
);
XNOR2_X1 _474_ (
.A(_202_),
.B(_204_),
.ZN(\resp_msg[1] )
);
AOI221_X4 _475_ (
.A(_110_),
.B1(_111_),
.B2(\req_msg[17] ),
.C1(_120_),
.C2(\dpath.b_reg.out_reg[1].qi ),
.ZN(_205_)
);
NAND3_X1 _476_ (
.A1(_150_),
.A2(_118_),
.A3(\resp_msg[1] ),
.ZN(_206_)
);
AOI22_X1 _477_ (
.A1(_205_),
.A2(_206_),
.B1(_125_),
.B2(_063_),
.ZN(_009_)
);
XOR2_X1 _478_ (
.A(\dpath.b_reg.out_reg[0].qi ),
.B(\dpath.a_reg.out_reg[0].qi ),
.Z(\resp_msg[0] )
);
AOI221_X4 _479_ (
.A(\ctrl.state.out_reg[1].qi ),
.B1(_111_),
.B2(\req_msg[16] ),
.C1(_120_),
.C2(\dpath.b_reg.out_reg[0].qi ),
.ZN(_207_)
);
NAND3_X1 _480_ (
.A1(_150_),
.A2(_118_),
.A3(\resp_msg[0] ),
.ZN(_208_)
);
AOI22_X1 _481_ (
.A1(_207_),
.A2(_208_),
.B1(_125_),
.B2(_066_),
.ZN(_002_)
);
NOR2_X1 _482_ (
.A1(_133_),
.A2(\ctrl.state.out_reg[0].qi ),
.ZN(resp_val)
);
NOR2_X1 _483_ (
.A1(\dpath.b_reg.out_reg[3].qi ),
.A2(\dpath.b_reg.out_reg[1].qi ),
.ZN(_209_)
);
AND3_X1 _484_ (
.A1(_209_),
.A2(_069_),
.A3(_203_),
.ZN(_210_)
);
NAND3_X1 _485_ (
.A1(_210_),
.A2(_073_),
.A3(_079_),
.ZN(_211_)
);
NOR3_X1 _486_ (
.A1(\dpath.b_reg.out_reg[9].qi ),
.A2(\dpath.b_reg.out_reg[10].qi ),
.A3(\dpath.b_reg.out_reg[11].qi ),
.ZN(_212_)
);
NAND2_X1 _487_ (
.A1(_212_),
.A2(_099_),
.ZN(_213_)
);
NOR4_X1 _488_ (
.A1(_211_),
.A2(\dpath.b_reg.out_reg[12].qi ),
.A3(\dpath.b_reg.out_reg[15].qi ),
.A4(_213_),
.ZN(_214_)
);
NAND3_X1 _489_ (
.A1(_214_),
.A2(_038_),
.A3(_043_),
.ZN(_215_)
);
NOR3_X1 _490_ (
.A1(_215_),
.A2(\dpath.b_reg.out_reg[5].qi ),
.A3(\dpath.b_reg.out_reg[6].qi ),
.ZN(_216_)
);
NAND3_X1 _491_ (
.A1(_117_),
.A2(_118_),
.A3(_216_),
.ZN(_217_)
);
AOI221_X4 _492_ (
.A(reset),
.B1(resp_rdy),
.B2(resp_val),
.C1(_217_),
.C2(_133_),
.ZN(_001_)
);
NAND3_X1 _493_ (
.A1(_132_),
.A2(_111_),
.A3(req_val),
.ZN(_218_)
);
AOI221_X1 _494_ (
.A(reset),
.B1(_112_),
.B2(_218_),
.C1(_123_),
.C2(_216_),
.ZN(_000_)
);
MUX2_X1 _495_ (
.A(\dpath.a_reg.out_reg[13].qi ),
.B(\req_msg[13] ),
.S(req_rdy),
.Z(_219_)
);
NOR2_X4 _496_ (
.A1(_120_),
.A2(_034_),
.ZN(_220_)
);
BUF_X8 _497_ (
.A(_220_),
.Z(_221_)
);
MUX2_X1 _498_ (
.A(_219_),
.B(\dpath.b_reg.out_reg[13].qi ),
.S(_221_),
.Z(_022_)
);
MUX2_X1 _499_ (
.A(\dpath.a_reg.out_reg[15].qi ),
.B(\req_msg[15] ),
.S(req_rdy),
.Z(_222_)
);
MUX2_X1 _500_ (
.A(_222_),
.B(\dpath.b_reg.out_reg[15].qi ),
.S(_221_),
.Z(_024_)
);
MUX2_X1 _501_ (
.A(\dpath.a_reg.out_reg[14].qi ),
.B(\req_msg[14] ),
.S(req_rdy),
.Z(_223_)
);
MUX2_X1 _502_ (
.A(_223_),
.B(\dpath.b_reg.out_reg[14].qi ),
.S(_221_),
.Z(_023_)
);
MUX2_X1 _503_ (
.A(\dpath.a_reg.out_reg[12].qi ),
.B(\req_msg[12] ),
.S(req_rdy),
.Z(_224_)
);
MUX2_X1 _504_ (
.A(_224_),
.B(\dpath.b_reg.out_reg[12].qi ),
.S(_221_),
.Z(_021_)
);
MUX2_X1 _505_ (
.A(\dpath.a_reg.out_reg[11].qi ),
.B(\req_msg[11] ),
.S(req_rdy),
.Z(_225_)
);
MUX2_X1 _506_ (
.A(_225_),
.B(\dpath.b_reg.out_reg[11].qi ),
.S(_221_),
.Z(_020_)
);
MUX2_X1 _507_ (
.A(\dpath.a_reg.out_reg[10].qi ),
.B(\req_msg[10] ),
.S(req_rdy),
.Z(_226_)
);
MUX2_X1 _508_ (
.A(_226_),
.B(\dpath.b_reg.out_reg[10].qi ),
.S(_221_),
.Z(_019_)
);
MUX2_X1 _509_ (
.A(\dpath.a_reg.out_reg[9].qi ),
.B(\req_msg[9] ),
.S(req_rdy),
.Z(_227_)
);
MUX2_X1 _510_ (
.A(_227_),
.B(\dpath.b_reg.out_reg[9].qi ),
.S(_221_),
.Z(_033_)
);
MUX2_X1 _511_ (
.A(\dpath.a_reg.out_reg[8].qi ),
.B(\req_msg[8] ),
.S(req_rdy),
.Z(_228_)
);
MUX2_X1 _512_ (
.A(_228_),
.B(\dpath.b_reg.out_reg[8].qi ),
.S(_221_),
.Z(_032_)
);
MUX2_X1 _513_ (
.A(\dpath.a_reg.out_reg[7].qi ),
.B(\req_msg[7] ),
.S(req_rdy),
.Z(_229_)
);
MUX2_X1 _514_ (
.A(_229_),
.B(\dpath.b_reg.out_reg[7].qi ),
.S(_221_),
.Z(_031_)
);
MUX2_X1 _515_ (
.A(\dpath.a_reg.out_reg[6].qi ),
.B(\req_msg[6] ),
.S(_034_),
.Z(_230_)
);
MUX2_X1 _516_ (
.A(_230_),
.B(\dpath.b_reg.out_reg[6].qi ),
.S(_221_),
.Z(_030_)
);
MUX2_X1 _517_ (
.A(\dpath.a_reg.out_reg[5].qi ),
.B(\req_msg[5] ),
.S(_034_),
.Z(_231_)
);
MUX2_X1 _518_ (
.A(_231_),
.B(\dpath.b_reg.out_reg[5].qi ),
.S(_220_),
.Z(_029_)
);
MUX2_X1 _519_ (
.A(\dpath.a_reg.out_reg[4].qi ),
.B(\req_msg[4] ),
.S(_034_),
.Z(_232_)
);
MUX2_X1 _520_ (
.A(_232_),
.B(\dpath.b_reg.out_reg[4].qi ),
.S(_220_),
.Z(_028_)
);
MUX2_X1 _521_ (
.A(\dpath.a_reg.out_reg[3].qi ),
.B(\req_msg[3] ),
.S(_034_),
.Z(_233_)
);
MUX2_X1 _522_ (
.A(_233_),
.B(\dpath.b_reg.out_reg[3].qi ),
.S(_220_),
.Z(_027_)
);
MUX2_X1 _523_ (
.A(\dpath.a_reg.out_reg[2].qi ),
.B(\req_msg[2] ),
.S(_034_),
.Z(_234_)
);
MUX2_X1 _524_ (
.A(_234_),
.B(\dpath.b_reg.out_reg[2].qi ),
.S(_220_),
.Z(_026_)
);
MUX2_X1 _525_ (
.A(\dpath.a_reg.out_reg[1].qi ),
.B(\req_msg[1] ),
.S(_034_),
.Z(_235_)
);
MUX2_X1 _526_ (
.A(_235_),
.B(\dpath.b_reg.out_reg[1].qi ),
.S(_220_),
.Z(_025_)
);
MUX2_X1 _527_ (
.A(\dpath.a_reg.out_reg[0].qi ),
.B(\req_msg[0] ),
.S(_034_),
.Z(_236_)
);
MUX2_X1 _528_ (
.A(_236_),
.B(\dpath.b_reg.out_reg[0].qi ),
.S(_220_),
.Z(_018_)
);
AOI22_X1 _529_ (
.A1(_179_),
.A2(_087_),
.B1(_077_),
.B2(\dpath.b_reg.out_reg[6].qi ),
.ZN(_237_)
);
NOR2_X1 _530_ (
.A1(_237_),
.A2(_082_),
.ZN(_238_)
);
XNOR2_X1 _531_ (
.A(\dpath.b_reg.out_reg[7].qi ),
.B(\dpath.a_reg.out_reg[7].qi ),
.ZN(_239_)
);
XNOR2_X1 _532_ (
.A(_238_),
.B(_239_),
.ZN(\resp_msg[7] )
);
AOI221_X2 _533_ (
.A(\ctrl.state.out_reg[1].qi ),
.B1(_111_),
.B2(\req_msg[23] ),
.C1(\resp_msg[7] ),
.C2(_122_),
.ZN(_240_)
);
OR3_X1 _534_ (
.A1(_117_),
.A2(_079_),
.A3(_119_),
.ZN(_241_)
);
AOI22_X1 _535_ (
.A1(_240_),
.A2(_241_),
.B1(_125_),
.B2(_084_),
.ZN(_015_)
);
DFF_X1 _536_ (
.CK(clk),
.D(_008_),
.Q(\dpath.a_reg.out_reg[15].qi ),
.QN(_242_)
);
DFF_X1 _537_ (
.CK(clk),
.D(_007_),
.Q(\dpath.a_reg.out_reg[14].qi ),
.QN(_243_)
);
DFF_X1 _538_ (
.CK(clk),
.D(_006_),
.Q(\dpath.a_reg.out_reg[13].qi ),
.QN(_244_)
);
DFF_X1 _539_ (
.CK(clk),
.D(_005_),
.Q(\dpath.a_reg.out_reg[12].qi ),
.QN(_245_)
);
DFF_X1 _540_ (
.CK(clk),
.D(_004_),
.Q(\dpath.a_reg.out_reg[11].qi ),
.QN(_246_)
);
DFF_X1 _541_ (
.CK(clk),
.D(_003_),
.Q(\dpath.a_reg.out_reg[10].qi ),
.QN(_247_)
);
DFF_X1 _542_ (
.CK(clk),
.D(_017_),
.Q(\dpath.a_reg.out_reg[9].qi ),
.QN(_248_)
);
DFF_X1 _543_ (
.CK(clk),
.D(_016_),
.Q(\dpath.a_reg.out_reg[8].qi ),
.QN(_249_)
);
DFF_X1 _544_ (
.CK(clk),
.D(_014_),
.Q(\dpath.a_reg.out_reg[6].qi ),
.QN(_250_)
);
DFF_X1 _545_ (
.CK(clk),
.D(_013_),
.Q(\dpath.a_reg.out_reg[5].qi ),
.QN(_251_)
);
DFF_X1 _546_ (
.CK(clk),
.D(_012_),
.Q(\dpath.a_reg.out_reg[4].qi ),
.QN(_252_)
);
DFF_X1 _547_ (
.CK(clk),
.D(_011_),
.Q(\dpath.a_reg.out_reg[3].qi ),
.QN(_253_)
);
DFF_X1 _548_ (
.CK(clk),
.D(_010_),
.Q(\dpath.a_reg.out_reg[2].qi ),
.QN(_254_)
);
DFF_X1 _549_ (
.CK(clk),
.D(_009_),
.Q(\dpath.a_reg.out_reg[1].qi ),
.QN(_255_)
);
DFF_X1 _550_ (
.CK(clk),
.D(_002_),
.Q(\dpath.a_reg.out_reg[0].qi ),
.QN(_256_)
);
DFF_X1 _551_ (
.CK(clk),
.D(_001_),
.Q(\ctrl.state.out_reg[1].qi ),
.QN(_257_)
);
DFF_X1 _552_ (
.CK(clk),
.D(_000_),
.Q(\ctrl.state.out_reg[0].qi ),
.QN(_258_)
);
DFF_X1 _553_ (
.CK(clk),
.D(_022_),
.Q(\dpath.b_reg.out_reg[13].qi ),
.QN(_259_)
);
DFF_X1 _554_ (
.CK(clk),
.D(_024_),
.Q(\dpath.b_reg.out_reg[15].qi ),
.QN(_260_)
);
DFF_X1 _555_ (
.CK(clk),
.D(_023_),
.Q(\dpath.b_reg.out_reg[14].qi ),
.QN(_261_)
);
DFF_X1 _556_ (
.CK(clk),
.D(_021_),
.Q(\dpath.b_reg.out_reg[12].qi ),
.QN(_262_)
);
DFF_X1 _557_ (
.CK(clk),
.D(_020_),
.Q(\dpath.b_reg.out_reg[11].qi ),
.QN(_263_)
);
DFF_X1 _558_ (
.CK(clk),
.D(_019_),
.Q(\dpath.b_reg.out_reg[10].qi ),
.QN(_264_)
);
DFF_X1 _559_ (
.CK(clk),
.D(_033_),
.Q(\dpath.b_reg.out_reg[9].qi ),
.QN(_265_)
);
DFF_X1 _560_ (
.CK(clk),
.D(_032_),
.Q(\dpath.b_reg.out_reg[8].qi ),
.QN(_266_)
);
DFF_X1 _561_ (
.CK(clk),
.D(_031_),
.Q(\dpath.b_reg.out_reg[7].qi ),
.QN(_267_)
);
DFF_X1 _562_ (
.CK(clk),
.D(_030_),
.Q(\dpath.b_reg.out_reg[6].qi ),
.QN(_268_)
);
DFF_X1 _563_ (
.CK(clk),
.D(_029_),
.Q(\dpath.b_reg.out_reg[5].qi ),
.QN(_269_)
);
DFF_X1 _564_ (
.CK(clk),
.D(_028_),
.Q(\dpath.b_reg.out_reg[4].qi ),
.QN(_270_)
);
DFF_X1 _565_ (
.CK(clk),
.D(_027_),
.Q(\dpath.b_reg.out_reg[3].qi ),
.QN(_271_)
);
DFF_X1 _566_ (
.CK(clk),
.D(_026_),
.Q(\dpath.b_reg.out_reg[2].qi ),
.QN(_272_)
);
DFF_X1 _567_ (
.CK(clk),
.D(_025_),
.Q(\dpath.b_reg.out_reg[1].qi ),
.QN(_273_)
);
DFF_X1 _568_ (
.CK(clk),
.D(_018_),
.Q(\dpath.b_reg.out_reg[0].qi ),
.QN(_274_)
);
DFF_X1 _569_ (
.CK(clk),
.D(_015_),
.Q(\dpath.a_reg.out_reg[7].qi ),
.QN(_275_)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRTN_TB_V
`define SKY130_FD_SC_LS__DFRTN_TB_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfrtn.v"
module top();
// Inputs are registered
reg D;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ls__dfrtn dut (.D(D), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRTN_TB_V
|
`include "../config.inc"
`include "../video2ram.v"
`include "../edge_detect.v"
`include "../Flag_CrossDomain.v"
`include "../ram2video.v"
module video2ram_tb;
reg clkIn = 0;
reg clkOut = 0;
reg [11:0] counterX;
reg [11:0] counterY;
wire [23:0] wrdata;
wire [23:0] rddata;
wire [14:0] wraddr;
wire wren;
wire wrclock;
wire starttriggerIn;
wire [14:0] rdaddr;
wire starttriggerOut;
wire HSYNC;
wire VSYNC;
wire DE;
wire CLOCK;
wire [23:0] video_out;
video2ram video2ram(
.clock(clkIn),
.R(8'd0),
.G(8'd0),
.B(8'd0),
.counterX(counterX),
.counterY(counterY),
.line_doubler(1'b0),
.wrdata(wrdata),
.wraddr(wraddr),
.wren(wren),
.wrclock(wrclock),
.starttrigger(starttriggerIn)
);
Flag_CrossDomain trigger(
.clkA(clkIn),
.FlagIn_clkA(starttriggerIn),
.clkB(clkOut),
.FlagOut_clkB(starttriggerOut)
);
ram2video ram2video(
.starttrigger(starttriggerOut),
.clock(clkOut),
.reset(1'b1),
.line_doubler(1'b0),
.add_line(1'b0),
.rddata(rddata),
.hsync(HSYNC),
.vsync(VSYNC),
.DrawArea(DE),
.videoClock(CLOCK),
.rdaddr(rdaddr),
.video_out(video_out)
);
`ifdef _1080p_
initial $display("1080p");
always #250 clkIn = ~clkIn;
always #91 clkOut = ~clkOut;
`endif
`ifdef _960p_
initial $display("960p");
always #2000 clkIn = ~clkIn;
always #1001 clkOut = ~clkOut;
`endif
`ifdef _VGA_
initial $display("VGA");
always #400 clkIn = ~clkIn;
always #429 clkOut = ~clkOut;
`endif
always @(posedge clkIn) begin
if (counterX < 858 - 1) begin
counterX <= counterX + 1;
end else begin
counterX <= 0;
if (counterY < 525 - 1) begin
//$display("y:%0d ay:%0d ay2:%0d - %0d %0d", counterY, video2ram.ram_addrY_reg, ram2video.ram_addrY_reg, (video2ram.ram_addrY_reg == ram2video.ram_addrY_reg), rdaddr);
counterY <= counterY + 1;
end else begin
counterY <= 0;
end
end
end
`define __IsVerticalCaptureTime(y) ( \
video2ram.line_doubler \
? (y < 240 || (y > 262 && y < video2ram.V_CAPTURE_END)) \
: (y >= video2ram.V_CAPTURE_START && y < video2ram.V_CAPTURE_END) \
)
`define __IsCaptureTime(x,y) ( \
`__IsVerticalCaptureTime(y) && x >= video2ram.H_CAPTURE_START && x < video2ram.H_CAPTURE_END \
)
initial
begin
counterX <= 0;
counterY <= 0;
$monitor("%0d - %0d: %0dx%0d %0d(%0d) %0dx%0d %0d", $time, starttriggerOut, counterX, counterY, wraddr, wren, ram2video.counterX_reg, ram2video.counterY_reg, rdaddr);
wait (starttriggerOut) begin
$display("TRIGGER");
end
wait ((counterY >= 480 && ram2video.counterY_reg >= `VERTICAL_LINES_VISIBLE - `VERTICAL_OFFSET) || (wren && `IsDrawAreaVGA(ram2video.counterX_reg, ram2video.counterY_reg) && wraddr == rdaddr)) begin
$display("stop: y:%0d ay:%0d ay2:%0d", counterY, wraddr, rdaddr);
$finish;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_TB_V
`define SKY130_FD_SC_LP__A221OI_TB_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a221oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_TB_V
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={650.000000} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525.000000} readRate={0.5} writeRate={0.5} /><IO interface={CAN} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={23.809525} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={64} clockFreq={150} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=525.000000, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.073, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.034, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.03, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.082, PCW_UIPARAM_DDR_BOARD_DELAY0=0.176, PCW_UIPARAM_DDR_BOARD_DELAY1=0.159, PCW_UIPARAM_DDR_BOARD_DELAY2=0.162, PCW_UIPARAM_DDR_BOARD_DELAY3=0.187, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=27.85, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=22.87, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=22.9, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=29.9, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=27, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=22.8, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=24, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=30.45, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=20.6, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=165, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50.000000, PCW_APU_PERIPHERAL_FREQMHZ=650.000000, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=24, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=150, PCW_FPGA2_PERIPHERAL_FREQMHZ=12.288000, PCW_FPGA3_PERIPHERAL_FREQMHZ=100.000000, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=26, PCW_IOPLL_CTRL_FBDIV=20, PCW_DDRPLL_CTRL_FBDIV=21, PCW_CPU_CPU_PLL_FREQMHZ=1300.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1050.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=150, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K128M16 JT-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=EMIO, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=1, PCW_CAN0_CAN0_IO=MIO 10 .. 11, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=DDR PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=ARM PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=1, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0 = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
module decoder (cx,d);
output [17:0] d;
input [20:0] cx;
reg [17:0] d;
reg [2:0] s;
reg [20:0] cx1;
parameter s0 = 3'b100;
parameter s1 = 3'b010;
parameter s2 = 3'b001;
parameter s3 = 3'b000;
parameter s4 = 3'b000;
parameter s5 = 3'b000;
parameter s6 = 3'b000;
parameter s7 = 3'b000;
parameter s8 = 3'b000;
parameter s9 = 3'b000;
parameter s10 = 3'b000;
parameter s11 = 3'b000;
parameter s12 = 3'b000;
parameter s13 = 3'b000;
parameter s14 = 3'b000;
parameter s15 = 3'b000;
parameter s16 = 3'b000;
parameter s17 = 3'b000;
parameter s18 = 3'b100;
parameter s19 = 3'b010;
parameter s20 = 3'b001;
always @(cx)
begin
cx1[0] = cx[0];
cx1[1] = cx[1];
cx1[2] = cx[2];
cx1[3] = cx[3];
cx1[4] = cx[4];
cx1[5] = cx[5];
cx1[6] = cx[6];
cx1[7] = cx[7];
cx1[8] = cx[8];
cx1[9] = cx[9];
cx1[10] = cx[10];
cx1[11] = cx[11];
cx1[12] = cx[12];
cx1[13] = cx[13];
cx1[14] = cx[14];
cx1[15] = cx[15];
cx1[16] = cx[16];
cx1[17] = cx[17];
cx1[18] = cx[18];
cx1[19] = cx[19];
cx1[20] = cx[20];
s[0]= cx[0]+ cx[18];
s[1]= cx[1]+ cx[19];
s[2]= cx[2]+ cx[20];
case(s)
s0:
begin
if(cx[0]==1'b0)
begin
cx1[0]=1'b1;
end
else
begin
cx1[0]=1'b0;
end
end
s1:
begin
if(cx[1]==1'b0)
begin
cx1[1]=1'b1;
end
else
begin
cx1[1]=1'b0;
end
end
s2:
begin
if(cx[2]==1'b0)
begin
cx1[2]=1'b1;
end
else
begin
cx1[2]=1'b0;
end
end
s3:
begin
if(cx[3]==1'b0)
begin
cx1[3]=1'b1;
end
else
begin
cx1[3]=1'b0;
end
end
s4:
begin
if(cx[4]==1'b0)
begin
cx1[4]=1'b1;
end
else
begin
cx1[4]=1'b0;
end
end
s5:
begin
if(cx[5]==1'b0)
begin
cx1[5]=1'b1;
end
else
begin
cx1[5]=1'b0;
end
end
s6:
begin
if(cx[6]==1'b0)
begin
cx1[6]=1'b1;
end
else
begin
cx1[6]=1'b0;
end
end
s7:
begin
if(cx[7]==1'b0)
begin
cx1[7]=1'b1;
end
else
begin
cx1[7]=1'b0;
end
end
s8:
begin
if(cx[8]==1'b0)
begin
cx1[8]=1'b1;
end
else
begin
cx1[8]=1'b0;
end
end
s9:
begin
if(cx[9]==1'b0)
begin
cx1[9]=1'b1;
end
else
begin
cx1[9]=1'b0;
end
end
s10:
begin
if(cx[10]==1'b0)
begin
cx1[10]=1'b1;
end
else
begin
cx1[10]=1'b0;
end
end
s11:
begin
if(cx[11]==1'b0)
begin
cx1[11]=1'b1;
end
else
begin
cx1[11]=1'b0;
end
end
s12:
begin
if(cx[12]==1'b0)
begin
cx1[12]=1'b1;
end
else
begin
cx1[12]=1'b0;
end
end
s13:
begin
if(cx[13]==1'b0)
begin
cx1[13]=1'b1;
end
else
begin
cx1[13]=1'b0;
end
end
s14:
begin
if(cx[14]==1'b0)
begin
cx1[14]=1'b1;
end
else
begin
cx1[14]=1'b0;
end
end
s15:
begin
if(cx[15]==1'b0)
begin
cx1[15]=1'b1;
end
else
begin
cx1[15]=1'b0;
end
end
s16:
begin
if(cx[16]==1'b0)
begin
cx1[16]=1'b1;
end
else
begin
cx1[16]=1'b0;
end
end
s17:
begin
if(cx[17]==1'b0)
begin
cx1[17]=1'b1;
end
else
begin
cx1[17]=1'b0;
end
end
s18:
begin
if(cx[18]==1'b0)
begin
cx1[18]=1'b1;
end
else
begin
cx1[18]=1'b0;
end
end
s19:
begin
if(cx[19]==1'b0)
begin
cx1[19]=1'b1;
end
else
begin
cx1[19]=1'b0;
end
end
s20:
begin
if(cx[20]==1'b0)
begin
cx1[20]=1'b1;
end
else
begin
cx1[20]=1'b0;
end
end
default:
begin
cx1[0]=cx[0];
cx1[1]=cx[1];
cx1[2]=cx[2];
cx1[3]=cx[3];
cx1[4]=cx[4];
cx1[5]=cx[5];
cx1[6]=cx[6];
cx1[7]=cx[7];
cx1[8]=cx[8];
cx1[9]=cx[9];
cx1[10]=cx[10];
cx1[11]=cx[11];
cx1[12]=cx[12];
cx1[13]=cx[13];
cx1[14]=cx[14];
cx1[15]=cx[15];
cx1[16]=cx[16];
cx1[17]=cx[17];
cx1[18]=cx[18];
cx1[19]=cx[19];
cx1[20]=cx[20];
end
endcase
d[0] = cx1[0];
d[1] = cx1[1];
d[2] = cx1[2];
d[3] = cx1[3];
d[4] = cx1[4];
d[5] = cx1[5];
d[6] = cx1[6];
d[7] = cx1[7];
d[8] = cx1[8];
d[9] = cx1[9];
d[10] = cx1[10];
d[11] = cx1[11];
d[12] = cx1[12];
d[13] = cx1[13];
d[14] = cx1[14];
d[15] = cx1[15];
d[16] = cx1[16];
d[17] = cx1[17];
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 6-Bit Look-Up Table
// /___/ /\ Filename : LUT6.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Replace primitive with function; Remove buf.
// 01/07/06 - 222733 - Add LOC Parameter
// 06/04/07 - Add wire declaration to internal signal.
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// 09/12/16 - ANSI ports, speed improvements
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`celldefine
module LUT6 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0000000000000000
)(
output O,
input I0,
input I1,
input I2,
input I3,
input I4,
input I5
);
// define constants
localparam MODULE_NAME = "LUT6";
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "LUT6_dr.v"
`else
reg [63:0] INIT_REG = INIT;
`endif
// begin behavioral model
reg O_out;
assign O = O_out;
function lut_mux8_f;
input [7:0] d;
input [2:0] s;
begin
if (((s[2]^s[1]^s[0]) === 1'b1) || ((s[2]^s[1]^s[0]) === 1'b0))
lut_mux8_f = d[s];
else if ( ~(|d) || &d)
lut_mux8_f = d[0];
else if ((((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) &&
(d[{1'b0,s[1:0]}] === d[{1'b1,s[1:0]}]))
lut_mux8_f = d[{1'b0,s[1:0]}];
else if ((((s[2]^s[0]) === 1'b1) || ((s[2]^s[0]) === 1'b0)) &&
(d[{s[2],1'b0,s[0]}] === d[{s[2],1'b1,s[0]}]))
lut_mux8_f = d[{s[2],1'b0,s[0]}];
else if ((((s[2]^s[1]) === 1'b1) || ((s[2]^s[1]) === 1'b0)) &&
(d[{s[2],s[1],1'b0}] === d[{s[2],s[1],1'b1}]))
lut_mux8_f = d[{s[2:1],1'b0}];
else if (((s[0] === 1'b1) || (s[0] === 1'b0)) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b0,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b1,s[0]}]))
lut_mux8_f = d[{1'b0,1'b0,s[0]}];
else if (((s[1] === 1'b1) || (s[1] === 1'b0)) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b0}]) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b1}]))
lut_mux8_f = d[{1'b0,s[1],1'b0}];
else if (((s[2] === 1'b1) || (s[2] === 1'b0)) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b0}]) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b1}]))
lut_mux8_f = d[{s[2],1'b0,1'b0}];
else
lut_mux8_f = 1'bx;
end
endfunction
always @(I0 or I1 or I2 or I3 or I4 or I5) begin
if ( (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b1)
O_out = INIT_REG[{I5, I4, I3, I2, I1, I0}];
else if ( ~(|INIT_REG) || &INIT_REG )
O_out = INIT_REG[0];
else
O_out = lut_mux8_f ({lut_mux8_f (INIT_REG[63:56], {I2, I1, I0}),
lut_mux8_f (INIT_REG[55:48], {I2, I1, I0}),
lut_mux8_f (INIT_REG[47:40], {I2, I1, I0}),
lut_mux8_f (INIT_REG[39:32], {I2, I1, I0}),
lut_mux8_f (INIT_REG[31:24], {I2, I1, I0}),
lut_mux8_f (INIT_REG[23:16], {I2, I1, I0}),
lut_mux8_f ( INIT_REG[15:8], {I2, I1, I0}),
lut_mux8_f ( INIT_REG[7:0], {I2, I1, I0})}, {I5, I4, I3});
end
// end behavioral model
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(I2 => O) = (0:0:0, 0:0:0);
(I3 => O) = (0:0:0, 0:0:0);
(I4 => O) = (0:0:0, 0:0:0);
(I5 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: David McCoy ([email protected])
* Description: Arbitrates access to the command bus data interface and the
* Data Bus interface
*
* Changes:
* 2015.09.07: Initial Commit
*/
module sdio_data_control #(
parameter DEFAULT_MIN_READ_COOLDOWN = 400
)(
input clk,
input rst,
output o_data_bus_busy,
output o_data_read_avail,
input i_write_flg,
input i_block_mode_flg,
input [12:0] i_data_cnt,
output reg [12:0] o_total_data_cnt,
input i_inc_addr_flg,
input [17:0] i_cmd_address,
output reg [17:0] o_address,
input i_activate,
output reg o_finished,
input i_cmd_bus_sel, /* If this is high we can only read/write one byte */
input i_mem_sel,
input [3:0] i_func_sel,
//Command Bus Interface
input [7:0] i_cmd_wr_data,
output [7:0] o_cmd_rd_data,
//Phy Data Bus Inteface
input i_data_phy_wr_stb,
input [7:0] i_data_phy_wr_data,
output o_data_phy_rd_stb,
output [7:0] o_data_phy_rd_data,
input i_data_phy_hst_rdy, /* DATA PHY -> Func: Ready for receive data */
output o_data_phy_com_rdy,
output o_data_phy_activate,
input i_data_phy_finished,
//CIA Interface
output reg o_cia_wr_stb,
output reg [7:0] o_cia_wr_data,
input i_cia_rd_stb,
input [7:0] i_cia_rd_data,
output reg o_cia_hst_rdy,
input i_cia_com_rdy,
output reg o_cia_activate,
input [15:0] i_cia_block_size,
//Function 1 Interface
output reg o_func1_wr_stb,
output reg [7:0] o_func1_wr_data,
input i_func1_rd_stb,
input [7:0] i_func1_rd_data,
output reg o_func1_hst_rdy,
input i_func1_com_rdy,
output reg o_func1_activate,
input [15:0] i_func1_block_size,
//Function 2 Interface
output reg o_func2_wr_stb,
output reg [7:0] o_func2_wr_data,
input i_func2_rd_stb,
input [7:0] i_func2_rd_data,
output reg o_func2_hst_rdy,
input i_func2_com_rdy,
output reg o_func2_activate,
input [15:0] i_func2_block_size,
//Function 3 Interface
output reg o_func3_wr_stb,
output reg [7:0] o_func3_wr_data,
input i_func3_rd_stb,
input [7:0] i_func3_rd_data,
output reg o_func3_hst_rdy,
input i_func3_com_rdy,
output reg o_func3_activate,
input [15:0] i_func3_block_size,
//Function 4 Interface
output reg o_func4_wr_stb,
output reg [7:0] o_func4_wr_data,
input i_func4_rd_stb,
input [7:0] i_func4_rd_data,
output reg o_func4_hst_rdy,
input i_func4_com_rdy,
output reg o_func4_activate,
input [15:0] i_func4_block_size,
//Function 5 Interface
output reg o_func5_wr_stb,
output reg [7:0] o_func5_wr_data,
input i_func5_rd_stb,
input [7:0] i_func5_rd_data,
output reg o_func5_hst_rdy,
input i_func5_com_rdy,
output reg o_func5_activate,
input [15:0] i_func5_block_size,
//Function 6 Interface
output reg o_func6_wr_stb,
output reg [7:0] o_func6_wr_data,
input i_func6_rd_stb,
input [7:0] i_func6_rd_data,
output reg o_func6_hst_rdy,
input i_func6_com_rdy,
output reg o_func6_activate,
input [15:0] i_func6_block_size,
//Function 7 Interface
output reg o_func7_wr_stb,
output reg [7:0] o_func7_wr_data,
input i_func7_rd_stb,
input [7:0] i_func7_rd_data,
output reg o_func7_hst_rdy,
input i_func7_com_rdy,
output reg o_func7_activate,
input [15:0] i_func7_block_size,
//Memory Interface
output reg o_mem_wr_stb,
output reg [7:0] o_mem_wr_data,
input i_mem_rd_stb,
input [7:0] i_mem_rd_data,
output reg o_mem_hst_rdy,
input i_mem_com_rdy,
output reg o_mem_activate,
input [15:0] i_mem_block_size
);
//local parameters
localparam IDLE = 4'h0;
localparam CONFIG = 4'h1;
localparam ACTIVATE = 4'h2;
localparam WRITE = 4'h3;
localparam READ = 4'h4;
localparam WAIT_FOR_PHY = 4'h5;
localparam READ_COOLDOWN = 4'h6;
localparam FINISHED = 4'h7;
//registes/wires
reg rd_stb;
reg [7:0] rd_data;
wire wr_stb;
wire [7:0] wr_data;
reg com_rdy;
wire [3:0] func_select;
reg [15:0] block_size;
reg [9:0] total_block_count; //Total number of blocks to transfer
reg [9:0] block_count;
reg [9:0] data_count; //Current byte we are working on
reg continuous; //This is a continuous transfer, don't stop till i_activate is deasserted
reg data_cntrl_rdy;
reg data_activate;
reg [31:0] read_cooldown;
reg lcl_wr_stb;
wire lcl_rd_stb;
reg lcl_hst_rdy;
reg lcl_activate;
//wire lcl_finished;
wire d_activate;
reg [3:0] state;
reg [3:0] ld_state;
//submodules
//asynchronous logic
assign lcl_rd_stb = i_cmd_bus_sel ? rd_stb : 1'b0;
assign o_cmd_rd_data = i_cmd_bus_sel ? rd_data : 8'h00;
assign o_data_phy_rd_stb = !i_cmd_bus_sel ? rd_stb : 1'b0;
assign o_data_phy_rd_data = !i_cmd_bus_sel ? rd_data : 8'h00;
assign o_data_phy_com_rdy = !i_cmd_bus_sel ? com_rdy : 1'b0;
assign o_data_phy_activate = !i_cmd_bus_sel ? data_activate : 1'b0;
assign wr_stb = i_cmd_bus_sel ? lcl_wr_stb : i_data_phy_wr_stb;
assign wr_data = i_cmd_bus_sel ? i_cmd_wr_data : i_data_phy_wr_data;
//assign data_cntrl_rdy = i_cmd_bus_sel ? lcl_hst_rdy : i_data_phy_hst_rdy;
//assign lcl_finished = i_cmd_bus_sel ? finished : 1'b0;
//assign i_activate = i_cmd_bus_sel ? lcl_activate : i_data_phy_activate;
assign d_activate = i_cmd_bus_sel ? i_activate : data_activate;
assign func_select = i_mem_sel ? 4'h8 : {1'b0, i_func_sel};
assign o_data_bus_busy = (state == ACTIVATE);
//TODO: Not implemented yet
assign o_data_read_avail = 1'b0;
//Multiplexer: Cmd Layer, Data Phy Layer -> Func Layer
always @ (*) begin
if (rst) begin
o_cia_wr_stb = 0;
o_cia_wr_data = 0;
o_cia_hst_rdy = 0;
o_func1_wr_stb = 0;
o_func1_wr_data = 0;
o_func1_hst_rdy = 0;
o_func2_wr_stb = 0;
o_func2_wr_data = 0;
o_func2_hst_rdy = 0;
o_func3_wr_stb = 0;
o_func3_wr_data = 0;
o_func3_hst_rdy = 0;
o_func4_wr_stb = 0;
o_func4_wr_data = 0;
o_func4_hst_rdy = 0;
o_func5_wr_stb = 0;
o_func5_wr_data = 0;
o_func5_hst_rdy = 0;
o_func6_wr_stb = 0;
o_func6_wr_data = 0;
o_func6_hst_rdy = 0;
o_func7_wr_stb = 0;
o_func7_wr_data = 0;
o_func7_hst_rdy = 0;
o_mem_wr_stb = 0;
o_mem_wr_data = 0;
o_mem_hst_rdy = 0;
end
else begin
//If nothing overrides these values, just set them to zero
o_cia_wr_stb = 0;
o_cia_wr_data = 0;
o_cia_hst_rdy = 0;
o_cia_activate = 0;
o_func1_wr_stb = 0;
o_func1_wr_data = 0;
o_func1_hst_rdy = 0;
o_func1_activate = 0;
o_func2_wr_stb = 0;
o_func2_wr_data = 0;
o_func2_hst_rdy = 0;
o_func2_activate = 0;
o_func3_wr_stb = 0;
o_func3_wr_data = 0;
o_func3_hst_rdy = 0;
o_func3_activate = 0;
o_func4_wr_stb = 0;
o_func4_wr_data = 0;
o_func4_hst_rdy = 0;
o_func4_activate = 0;
o_func5_wr_stb = 0;
o_func5_wr_data = 0;
o_func5_hst_rdy = 0;
o_func5_activate = 0;
o_func6_wr_stb = 0;
o_func6_wr_data = 0;
o_func6_hst_rdy = 0;
o_func6_activate = 0;
o_func7_wr_stb = 0;
o_func7_wr_data = 0;
o_func7_hst_rdy = 0;
o_func7_activate = 0;
o_mem_wr_stb = 0;
o_mem_wr_data = 0;
o_mem_hst_rdy = 0;
o_mem_activate = 0;
case (func_select)
0: begin
o_cia_wr_stb = wr_stb;
o_cia_wr_data = wr_data;
o_cia_hst_rdy = data_cntrl_rdy;
o_cia_activate = d_activate;
end
1: begin
o_func1_wr_stb = wr_stb;
o_func1_wr_data = wr_data;
o_func1_hst_rdy = data_cntrl_rdy;
o_func1_activate = d_activate;
end
2: begin
o_func2_wr_stb = wr_stb;
o_func2_wr_data = wr_data;
o_func2_hst_rdy = data_cntrl_rdy;
o_func2_activate = d_activate;
end
3: begin
o_func3_wr_stb = wr_stb;
o_func3_wr_data = wr_data;
o_func3_hst_rdy = data_cntrl_rdy;
o_func3_activate = d_activate;
end
4: begin
o_func4_wr_stb = wr_stb;
o_func4_wr_data = wr_data;
o_func4_hst_rdy = data_cntrl_rdy;
o_func4_activate = d_activate;
end
5: begin
o_func5_wr_stb = wr_stb;
o_func5_wr_data = wr_data;
o_func5_hst_rdy = data_cntrl_rdy;
o_func5_activate = d_activate;
end
6: begin
o_func6_wr_stb = wr_stb;
o_func6_wr_data = wr_data;
o_func6_hst_rdy = data_cntrl_rdy;
o_func6_activate = d_activate;
end
7: begin
o_func7_wr_stb = wr_stb;
o_func7_wr_data = wr_data;
o_func7_hst_rdy = data_cntrl_rdy;
o_func7_activate = d_activate;
end
8: begin
o_mem_wr_stb = wr_stb;
o_mem_wr_data = wr_data;
o_mem_hst_rdy = data_cntrl_rdy;
o_mem_activate = d_activate;
end
default: begin
end
endcase
end
end
//Multiplexer: Func -> Cmd Layer, Data Phy Layer
always @ (*) begin
if (rst) begin
rd_stb = 0;
rd_data = 0;
com_rdy = 0;
block_size = 0;
end
else begin
case (func_select)
0: begin
rd_stb = i_cia_rd_stb;
rd_data = i_cia_rd_data;
com_rdy = i_cia_com_rdy & data_cntrl_rdy;
block_size = i_cia_block_size;
//finished = i_cia_finished;
end
1: begin
rd_stb = i_func1_rd_stb;
rd_data = i_func1_rd_data;
com_rdy = i_func1_com_rdy & data_cntrl_rdy;
block_size = i_func1_block_size;
//finished = i_func1_finished;
end
2: begin
rd_stb = i_func2_rd_stb;
rd_data = i_func2_rd_data;
com_rdy = i_func2_com_rdy & data_cntrl_rdy;
block_size = i_func2_block_size;
//finished = i_func2_finished;
end
3: begin
rd_stb = i_func3_rd_stb;
rd_data = i_func3_rd_data;
com_rdy = i_func3_com_rdy & data_cntrl_rdy;
block_size = i_func3_block_size;
//finished = i_func3_finished;
end
4: begin
rd_stb = i_func4_rd_stb;
rd_data = i_func4_rd_data;
com_rdy = i_func4_com_rdy & data_cntrl_rdy;
block_size = i_func4_block_size;
//finished = i_func4_finished;
end
5: begin
rd_stb = i_func5_rd_stb;
rd_data = i_func5_rd_data;
com_rdy = i_func5_com_rdy & data_cntrl_rdy;
block_size = i_func5_block_size;
//finished = i_func5_finished;
end
6: begin
rd_stb = i_func6_rd_stb;
rd_data = i_func6_rd_data;
com_rdy = i_func6_com_rdy & data_cntrl_rdy;
block_size = i_func6_block_size;
//finished = i_func6_finished;
end
7: begin
rd_stb = i_func7_rd_stb;
rd_data = i_func7_rd_data;
com_rdy = i_func7_com_rdy & data_cntrl_rdy;
block_size = i_func7_block_size;
//finished = i_func7_finished;
end
8: begin
rd_stb = i_mem_rd_stb;
rd_data = i_mem_rd_data;
com_rdy = i_mem_com_rdy & data_cntrl_rdy;
block_size = i_mem_block_size;
//finished = i_mem_finished;
end
default: begin
rd_stb = 1'b0;
rd_data = 8'h0;
com_rdy = 1'b0;
end
endcase
end
end
//synchronous logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
o_finished <= 0;
total_block_count <= 0;
o_total_data_cnt <= 0;
block_count <= 0;
data_count <= 0;
continuous <= 0;
data_cntrl_rdy <= 0;
o_address <= 0;
data_activate <= 0;
read_cooldown <= DEFAULT_MIN_READ_COOLDOWN;
end
else begin
case (state)
IDLE: begin
o_finished <= 0;
continuous <= 0;
total_block_count <= 0;
o_total_data_cnt <= 0;
data_count <= 0;
block_count <= 0;
data_cntrl_rdy <= 0;
o_address <= i_cmd_address;
data_activate <= 0;
if (i_block_mode_flg) begin
if (i_data_cnt == 0) begin
continuous <= 1;
total_block_count <= 0;
end
else begin
total_block_count <= i_data_cnt;
end
end
else begin
total_block_count <= 0;
end
if (i_activate) begin
state <= CONFIG;
end
end
CONFIG: begin
//We are ready to go, activate is high
//Is this block mode?
//Check to see if we need to adjust data_count (from 0 -> 512)
data_count <= 0;
if (i_block_mode_flg) begin
o_total_data_cnt <= block_size;
if (!continuous) begin
block_count <= block_count + 1;
end
end
else begin
if (i_data_cnt == 0) begin
o_total_data_cnt <= 512;
end
else begin
o_total_data_cnt <= i_data_cnt;
end
end
state <= ACTIVATE;
end
ACTIVATE: begin
data_activate <= 1;
if (i_cmd_bus_sel || i_data_phy_hst_rdy) begin
data_cntrl_rdy <= 1;
if (data_count < o_total_data_cnt) begin
if (wr_stb || rd_stb) begin
data_count <= data_count + 1;
if (i_inc_addr_flg) begin
o_address <= o_address + 1;
end
end
end
else begin
data_cntrl_rdy <= 0;
if (i_block_mode_flg) begin
if (i_write_flg) begin
state <= WAIT_FOR_PHY;
end
else begin
data_count <= 0;
state <= READ_COOLDOWN;
end
end
else begin
state <= FINISHED;
end
end
end
end
WAIT_FOR_PHY: begin
if (i_data_phy_finished) begin
if (continuous || (block_count < total_block_count)) begin
state <= CONFIG;
end
else begin
state <= FINISHED;
end
data_activate <= 0;
end
end
READ_COOLDOWN: begin
if (data_count < read_cooldown) begin
data_count <= data_count + 1;
end
else begin
data_activate <= 0;
if (continuous || (block_count < total_block_count)) begin
state <= CONFIG;
end
else begin
state <= FINISHED;
end
end
end
FINISHED: begin
data_activate <= 0;
o_finished <= 1;
end
default: begin
state <= FINISHED;
end
endcase
if (!i_activate) begin
//When !i_activate go back to IDLE, this can effectively cancel transactions or is used when finished is detected
state <= IDLE;
end
end
end
//Local Data Reader/Writer
always @ (posedge clk) begin
lcl_wr_stb <= 0;
if (rst) begin
ld_state <= IDLE;
lcl_hst_rdy <= 0;
end
else begin
case (ld_state)
IDLE: begin
lcl_hst_rdy <= 0;
if (i_cmd_bus_sel) begin
if (i_activate) begin
if (i_write_flg) begin
lcl_hst_rdy <= 1;
ld_state <= WRITE;
end
else begin
ld_state <= READ;
end
end
end
end
WRITE: begin
if (com_rdy) begin
lcl_wr_stb <= 1;
ld_state <= FINISHED;
end
end
READ: begin
lcl_hst_rdy <= 1;
if (lcl_rd_stb) begin
ld_state <= FINISHED;
end
end
FINISHED: begin
lcl_hst_rdy <= 0;
if (!i_activate) begin
ld_state <= IDLE;
end
end
default: begin
ld_state <= FINISHED;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD1_1_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD1_1_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv3sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv3sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd1_1 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkdlyinv3sd1 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd1_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkdlyinv3sd1 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD1_1_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ad
//
// Generated
// by: wig
// on: Thu Apr 26 09:40:09 2007
// cmd: /home/wig/work/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ad.v,v 1.2 2007/04/26 15:45:52 wig Exp $
// $Date: 2007/04/26 15:45:52 $
// $Log: ent_ad.v,v $
// Revision 1.2 2007/04/26 15:45:52 wig
// Updated testcase files
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.108 2007/04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ad
//
// No user `defines in this module
module ent_ad
//
// Generated Module inst_ad
//
(
port_ad_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ad_2;
// Generated Wires:
wire port_ad_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ad
//
//
//!End of Module/s
// --------------------------------------------------------------
|
Require Import Verdi.Verdi.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.exteq.
Require Import Verdi.Ssrexport.
Set Implicit Arguments.
Class LabeledMultiParams (P : BaseParams) :=
{
lb_name : Type ;
lb_msg : Type ;
lb_msg_eq_dec : forall x y : lb_msg, {x = y} + {x <> y} ;
lb_name_eq_dec : forall x y : lb_name, {x = y} + {x <> y} ;
lb_nodes : list lb_name ;
lb_all_names_nodes : forall n, In n lb_nodes ;
lb_no_dup_nodes : NoDup lb_nodes ;
label : Type ;
label_silent : label ;
lb_init_handlers : lb_name -> data ;
lb_net_handlers : lb_name -> lb_name -> lb_msg -> data -> label * (list output) * data * list (lb_name * lb_msg) ;
lb_input_handlers : lb_name -> input -> data -> label * (list output) * data * list (lb_name * lb_msg)
}.
Section UnlabeledParams.
Context {base_params : BaseParams}.
Context {labeled_multi_params : LabeledMultiParams base_params}.
Definition unlabeled_net_handlers me src m st :=
let '(lb, out, st', ps) := lb_net_handlers me src m st in (out, st', ps).
Definition unlabeled_input_handlers me inp st :=
let '(lb, out, st', ps) := lb_input_handlers me inp st in (out, st', ps).
Global Instance unlabeled_multi_params : MultiParams base_params :=
{
name := lb_name ;
msg := lb_msg ;
msg_eq_dec := lb_msg_eq_dec ;
name_eq_dec := lb_name_eq_dec ;
nodes := lb_nodes ;
all_names_nodes := lb_all_names_nodes ;
no_dup_nodes := lb_no_dup_nodes ;
init_handlers := lb_init_handlers;
net_handlers := unlabeled_net_handlers ;
input_handlers := unlabeled_input_handlers
}.
End UnlabeledParams.
Section LabeledStepExecution.
Variable A : Type.
Variable L : Type.
Variable trace : Type.
Definition lb_step_relation := A -> L -> A -> list trace -> Prop.
Definition lb_step_ex (step : lb_step_relation) (l : L) (a : A) : Prop :=
exists a' tr, step a l a' tr.
Record event := { evt_a : A ; evt_l : L ; evt_trace : list trace }.
Definition enabled (step : lb_step_relation) (l : L) (e : event) : Prop :=
lb_step_ex step l (evt_a e).
Definition occurred (l : L) (e : event) : Prop := l = evt_l e.
Definition inf_enabled (step : lb_step_relation) (l : L) (s : infseq event) : Prop :=
inf_often (now (enabled step l)) s.
Definition cont_enabled (step : lb_step_relation) (l : L) (s : infseq event) : Prop :=
continuously (now (enabled step l)) s.
Definition inf_occurred (l : L) (s : infseq event) : Prop :=
inf_often (now (occurred l)) s.
Definition strong_fairness (step : lb_step_relation) (silent : L) (s : infseq event) : Prop :=
forall l : L, l <> silent -> inf_enabled step l s -> inf_occurred l s.
Definition weak_fairness (step : lb_step_relation) (silent : L) (s : infseq event) : Prop :=
forall l : L, l <> silent -> cont_enabled step l s -> inf_occurred l s.
Lemma strong_fairness_invar :
forall step e silent s, strong_fairness step silent (Cons e s) -> strong_fairness step silent s.
Proof using.
unfold strong_fairness. unfold inf_enabled, inf_occurred, inf_often.
intros step e silent s fair l neq alev.
assert (alevt_es: always (eventually (now (enabled step l))) (Cons e s)).
constructor.
constructor 2. destruct alev; assumption.
simpl. assumption.
clear alev. generalize (fair l neq alevt_es); clear fair alevt_es.
intro fair; case (always_Cons fair); trivial.
Qed.
Lemma strong_fairness_extensional :
forall step silent, extensional (strong_fairness step silent).
Proof using.
move => step silent.
rewrite /extensional /strong_fairness /inf_enabled /inf_occurred /=.
move => s1 s2 H_eq H_s1 l' H_neq' H_en.
have H_s1l := H_s1 l'.
move: H_s1l.
set s1i := inf_often (now (occurred _)) s1.
move => H_s1l.
suff H_suff: s1i.
move: H_suff.
apply extensional_inf_often => //.
exact: extensional_now.
apply: H_s1l => {s1i}; first by [].
move: H_en.
apply: extensional_inf_often; last exact: exteq_sym.
exact: extensional_now.
Qed.
Lemma weak_fairness_invar :
forall step e silent s, weak_fairness step silent (Cons e s) -> weak_fairness step silent s.
Proof using.
unfold weak_fairness. unfold cont_enabled, inf_occurred, continuously, inf_often.
intros step e silent s fair a neq eval.
assert (eval_es: eventually (always (now (enabled step a))) (Cons e s)).
apply E_next. assumption.
apply fair in eval_es.
apply always_invar in eval_es.
assumption.
assumption.
Qed.
Lemma weak_fairness_extensional :
forall step silent, extensional (weak_fairness step silent).
Proof using.
move => step silent.
rewrite /extensional /weak_fairness /cont_enabled /inf_occurred /=.
move => s1 s2 H_eq H_s1 l' H_neq' H_en.
have H_s1l := H_s1 l'.
move: H_s1l.
set s1i := inf_often (now (occurred _)) s1.
move => H_s1l.
suff H_suff: s1i.
move: H_suff.
apply extensional_inf_often => //.
exact: extensional_now.
apply: H_s1l => {s1i}; first by [].
move: H_en.
apply: extensional_continuously; last exact: exteq_sym.
exact: extensional_now.
Qed.
Lemma strong_fairness_weak :
forall step silent s, strong_fairness step silent s -> weak_fairness step silent s.
Proof using.
move => step silent.
case => e s.
rewrite /strong_fairness /weak_fairness /inf_enabled /cont_enabled.
move => H_str l neq H_cont.
apply: H_str; first by [].
exact: continuously_inf_often.
Qed.
CoInductive lb_step_execution (step : lb_step_relation) : infseq event -> Prop :=
Cons_lb_step_exec : forall (e e' : event) (tr : list trace) (s : infseq event),
step (evt_a e) (evt_l e) (evt_a e') tr ->
evt_trace e' = evt_trace e ++ tr ->
lb_step_execution step (Cons e' s) ->
lb_step_execution step (Cons e (Cons e' s)).
Lemma lb_step_execution_invar :
forall step x s, lb_step_execution step (Cons x s) -> lb_step_execution step s.
Proof using.
intros step x s e. change (lb_step_execution step (tl (Cons x s))).
destruct e; simpl. assumption.
Qed.
Lemma lb_step_execution_extensional :
forall step, extensional (lb_step_execution step).
Proof using.
move => step.
rewrite /extensional /=.
cofix c.
case => e1; case => e1' s1.
case => e2; case => e2' s2 H_eq.
find_apply_lem_hyp exteq_inversion.
break_and.
find_copy_apply_lem_hyp exteq_inversion.
break_and.
repeat find_rewrite.
move => H_exec.
inversion H_exec; subst.
apply (Cons_lb_step_exec _ tr) => //.
by apply: c; eauto.
Qed.
Definition event_step_star (step : step_relation A trace) (init : A) (e : event) :=
refl_trans_1n_trace step init (evt_a e) (evt_trace e).
Definition step_star_lb_step_reachable (lb_step : lb_step_relation) (step : step_relation A trace) (init : A) :=
forall a l a' tr tr',
refl_trans_1n_trace step init a tr' ->
lb_step a l a' tr ->
refl_trans_1n_trace step init a' (tr' ++ tr).
Lemma step_star_lb_step_execution :
forall lb_step step init,
step_star_lb_step_reachable lb_step step init ->
forall s, event_step_star step init (hd s) ->
lb_step_execution lb_step s ->
always (now (event_step_star step init)) s.
Proof using.
move => lb_step step init H_r.
case => e s H_star.
move: e s H_star.
cofix cf.
move => e.
case => e' s H_star H_exec'.
constructor; first by [].
apply cf.
inversion H_exec'; subst_max.
simpl in *.
rewrite /event_step_star /=.
rewrite /event_step_star /= in H_star.
rewrite /step_star_lb_step_reachable in H_r.
have H_d := H_r _ _ _ _ _ H_star H2.
rewrite H3.
exact: H_r _ _ _ _ _ H_star H2.
move: H_exec'.
apply: lb_step_execution_invar.
Qed.
End LabeledStepExecution.
Section LabeledStepAsync.
Context `{labeled_multi_params : LabeledMultiParams}.
Inductive lb_step_async : lb_step_relation network label (name * (input + list output)) :=
| LabeledStepAsync_deliver : forall net net' p xs ys out d l lb,
nwPackets net = xs ++ p :: ys ->
lb_net_handlers (pDst p) (pSrc p) (pBody p) (nwState net (pDst p)) = (lb, out, d, l) ->
net' = mkNetwork (send_packets (pDst p) l ++ xs ++ ys)
(update name_eq_dec (nwState net) (pDst p) d) ->
lb_step_async net lb net' [(pDst p, inr out)]
| LabeledStepAsync_input : forall h net net' out inp d l lb,
lb_input_handlers h inp (nwState net h) = (lb, out, d, l) ->
net' = mkNetwork (send_packets h l ++ nwPackets net)
(update name_eq_dec (nwState net) h d) ->
lb_step_async net lb net' [(h, inl inp); (h, inr out)]
| LabeledStepAsync_stutter : forall net, lb_step_async net label_silent net [].
Lemma step_async_star_lb_step_reachable :
step_star_lb_step_reachable lb_step_async step_async step_async_init.
Proof using.
rewrite /step_star_lb_step_reachable.
move => net l.
move => net' tr tr' H_star H_st.
invcs H_st.
- set net' := {| nwPackets := _ ; nwState := _ |}.
apply (@refl_trans_1n_trace_trans _ _ _ _ net) => //.
have ->: [(pDst p, inr out)] = [(pDst p, inr out)] ++ [] by [].
apply: (@RT1nTStep _ _ _ _ net'); last exact: RT1nTBase.
apply: (@StepAsync_deliver _ _ _ _ _ xs ys _ d l0) => //.
rewrite /net_handlers /= /unlabeled_net_handlers /=.
repeat break_let.
by tuple_inversion.
- set net' := {| nwPackets := _ ; nwState := _ |}.
apply (@refl_trans_1n_trace_trans _ _ _ _ net) => //.
have ->: [(h, inl inp); (h, inr out)] = [(h, inl inp); (h, inr out)] ++ [] by [].
apply: (@RT1nTStep _ _ _ _ net'); last exact: RT1nTBase.
apply: StepAsync_input => //.
rewrite /input_handlers /= /unlabeled_input_handlers /=.
repeat break_let.
by tuple_inversion.
- by have ->: tr' ++ [] = tr' by auto with datatypes.
Qed.
Lemma step_async_star_lb_step_execution :
forall s, event_step_star step_async step_async_init (hd s) ->
lb_step_execution lb_step_async s ->
always (now (event_step_star step_async step_async_init)) s.
Proof using.
apply: step_star_lb_step_execution.
exact: step_async_star_lb_step_reachable.
Qed.
End LabeledStepAsync.
Section LabeledStepFailure.
Context `{labeled_multi_params : LabeledMultiParams}.
Inductive lb_step_failure : lb_step_relation (list name * network) label (name * (input + list output)) :=
| LabeledStepFailure_deliver : forall net net' failed p xs ys out d l lb,
nwPackets net = xs ++ p :: ys ->
~ In (pDst p) failed ->
lb_net_handlers (pDst p) (pSrc p) (pBody p) (nwState net (pDst p)) = (lb, out, d, l) ->
net' = mkNetwork (send_packets (pDst p) l ++ xs ++ ys)
(update name_eq_dec (nwState net) (pDst p) d) ->
lb_step_failure (failed, net) lb (failed, net') [(pDst p, inr out)]
| LabeledStepFailure_input : forall h net net' failed out inp d l lb,
~ In h failed ->
lb_input_handlers h inp (nwState net h) = (lb, out, d, l) ->
net' = mkNetwork (send_packets h l ++ nwPackets net)
(update name_eq_dec (nwState net) h d) ->
lb_step_failure (failed, net) lb (failed, net') [(h, inl inp); (h, inr out)]
| LabeledStepFailure_stutter : forall net failed, lb_step_failure (failed, net) label_silent (failed, net) [].
Context {failure_params : FailureParams unlabeled_multi_params}.
Lemma step_failure_star_lb_step_reachable :
step_star_lb_step_reachable lb_step_failure step_failure step_failure_init.
Proof using.
rewrite /step_star_lb_step_reachable.
case => failed net l.
case => failed' net' tr tr' H_star H_st.
invcs H_st.
- set net' := {| nwPackets := _ ; nwState := _ |}.
apply (@refl_trans_1n_trace_trans _ _ _ _ (failed', net)) => //.
have ->: [(pDst p, inr out)] = [(pDst p, inr out)] ++ [] by [].
apply: (@RT1nTStep _ _ _ _ (failed', net')); last exact: RT1nTBase.
apply: (@StepFailure_deliver _ _ _ _ _ _ _ xs ys _ d l0) => //.
rewrite /net_handlers /= /unlabeled_net_handlers /=.
repeat break_let.
by tuple_inversion.
- set net' := {| nwPackets := _ ; nwState := _ |}.
apply (@refl_trans_1n_trace_trans _ _ _ _ (failed', net)) => //.
have ->: [(h, inl inp); (h, inr out)] = [(h, inl inp); (h, inr out)] ++ [] by [].
apply: (@RT1nTStep _ _ _ _ (failed', net')); last exact: RT1nTBase.
apply: StepFailure_input => //.
rewrite /input_handlers /= /unlabeled_input_handlers /=.
repeat break_let.
by tuple_inversion.
- by have ->: tr' ++ [] = tr' by auto with datatypes.
Qed.
Lemma step_failure_star_lb_step_execution :
forall s, event_step_star step_failure step_failure_init (hd s) ->
lb_step_execution lb_step_failure s ->
always (now (event_step_star step_failure step_failure_init)) s.
Proof using.
apply: step_star_lb_step_execution.
exact: step_failure_star_lb_step_reachable.
Qed.
End LabeledStepFailure.
Section LabeledStepOrderFailure.
Context `{labeled_multi_params : LabeledMultiParams}.
Inductive lb_step_ordered_failure : lb_step_relation (list name * ordered_network) label (name * (input + output)) :=
| LabeledStepOrderedFailure_deliver : forall net net' failed tr m ms out d l from to lb,
onwPackets net from to = m :: ms ->
~ In to failed ->
lb_net_handlers to from m (onwState net to) = (lb, out, d, l) ->
net' = mkONetwork (collate name_eq_dec to (update2 name_eq_dec (onwPackets net) from to ms) l)
(update name_eq_dec (onwState net) to d) ->
tr = map2fst to (map inr out) ->
lb_step_ordered_failure (failed, net) lb (failed, net') tr
| LabeledStepOrderedFailure_input : forall h net net' failed tr out inp d l lb,
~ In h failed ->
lb_input_handlers h inp (onwState net h) = (lb, out, d, l) ->
net' = mkONetwork (collate name_eq_dec h (onwPackets net) l)
(update name_eq_dec (onwState net) h d) ->
tr = (h, inl inp) :: map2fst h (map inr out) ->
lb_step_ordered_failure (failed, net) lb (failed, net') tr
| LabeledStepOrderedFailure_stutter : forall net failed, lb_step_ordered_failure (failed, net) label_silent (failed, net) [].
Context {overlay_params : NameOverlayParams unlabeled_multi_params}.
Context {fail_msg_params : FailMsgParams unlabeled_multi_params}.
Lemma step_ordered_failure_star_lb_step_reachable :
step_star_lb_step_reachable lb_step_ordered_failure step_ordered_failure step_ordered_failure_init.
Proof using.
rewrite /step_star_lb_step_reachable.
case => failed net l.
case => failed' net' tr tr' H_star H_st.
invcs H_st.
- set net' := {| onwPackets := _ ; onwState := _ |}.
apply (@refl_trans_1n_trace_trans _ _ _ _ (failed', net)) => //.
rewrite (app_nil_end (map2fst _ _)).
apply: (@RT1nTStep _ _ _ _ (failed', net')); last exact: RT1nTBase.
apply: (StepOrderedFailure_deliver _ _ _ H3) => //.
rewrite /net_handlers /= /unlabeled_net_handlers /=.
repeat break_let.
by tuple_inversion.
- set net' := {| onwPackets := _ ; onwState := _ |}.
apply (@refl_trans_1n_trace_trans _ _ _ _ (failed', net)) => //.
rewrite (app_nil_end (_ :: _)).
apply: (@RT1nTStep _ _ _ _ (failed', net')); last exact: RT1nTBase.
apply: StepOrderedFailure_input => //; first by [].
rewrite /input_handlers /= /unlabeled_input_handlers /=.
repeat break_let.
by tuple_inversion.
- by have ->: tr' ++ [] = tr' by auto with datatypes.
Qed.
Lemma step_ordered_failure_star_lb_step_execution :
forall s, event_step_star step_ordered_failure step_ordered_failure_init (hd s) ->
lb_step_execution lb_step_ordered_failure s ->
always (now (event_step_star step_ordered_failure step_ordered_failure_init)) s.
Proof using.
apply: step_star_lb_step_execution.
exact: step_ordered_failure_star_lb_step_reachable.
Qed.
End LabeledStepOrderFailure.
Section LabeledStepOrderDynamic.
Context `{labeled_multi_params : LabeledMultiParams}.
Inductive lb_step_ordered_dynamic : lb_step_relation ordered_dynamic_network label (name * (input + output)) :=
| LabeledStepOrderedDynamic_deliver : forall net net' tr m ms out d d' l from to lb,
In to (odnwNodes net) ->
odnwState net to = Some d ->
odnwPackets net from to = m :: ms ->
lb_net_handlers to from m d = (lb, out, d', l) ->
net' = {| odnwNodes := odnwNodes net;
odnwPackets := collate name_eq_dec to (update2 name_eq_dec (odnwPackets net) from to ms) l;
odnwState := update name_eq_dec (odnwState net) to (Some d') |} ->
tr = map2fst to (map inr out) ->
lb_step_ordered_dynamic net lb net' tr
| LabeledStepOrderedDynamic_input : forall h net net' tr out inp d d' l lb,
In h (odnwNodes net) ->
odnwState net h = Some d ->
lb_input_handlers h inp d = (lb, out, d', l) ->
net' = {| odnwNodes := odnwNodes net;
odnwPackets := collate name_eq_dec h (odnwPackets net) l;
odnwState := update name_eq_dec (odnwState net) h (Some d') |} ->
tr = (h, inl inp) :: map2fst h (map inr out) ->
lb_step_ordered_dynamic net lb net' tr
| LabeledStepOrderedDynamic_stutter : forall net,
lb_step_ordered_dynamic net label_silent net [].
Context {overlay_params : NameOverlayParams unlabeled_multi_params}.
Context {new_msg_params : NewMsgParams unlabeled_multi_params}.
Lemma step_ordered_dynamic_star_lb_step_reachable :
step_star_lb_step_reachable lb_step_ordered_dynamic step_ordered_dynamic step_ordered_dynamic_init.
Proof using.
rewrite /step_star_lb_step_reachable.
move => net l.
move => net' tr tr' H_star H_st.
invcs H_st.
- set net' := {| odnwNodes := _ ; odnwPackets := _ ; odnwState := _ |}.
apply (@refl_trans_1n_trace_trans _ _ _ _ net) => //.
rewrite (app_nil_end (map2fst _ _)).
apply: (@RT1nTStep _ _ _ _ net'); last exact: RT1nTBase.
apply: (StepOrderedDynamic_deliver _ _ _ H0 H1) => //.
rewrite /net_handlers /= /unlabeled_net_handlers /=.
repeat break_let.
by tuple_inversion.
- set net' := {| odnwNodes := _ ; odnwPackets := _ ; odnwState := _ |}.
apply (@refl_trans_1n_trace_trans _ _ _ _ net) => //.
rewrite (app_nil_end (_ :: _)).
apply: (@RT1nTStep _ _ _ _ net'); last exact: RT1nTBase.
apply: (StepOrderedDynamic_input _ _ H0) => //.
rewrite /input_handlers /= /unlabeled_input_handlers /=.
repeat break_let.
by tuple_inversion.
- by have ->: tr' ++ [] = tr' by auto with datatypes.
Qed.
Lemma step_ordered_dynamic_star_lb_step_execution :
forall s, event_step_star step_ordered_dynamic step_ordered_dynamic_init (hd s) ->
lb_step_execution lb_step_ordered_dynamic s ->
always (now (event_step_star step_ordered_dynamic step_ordered_dynamic_init)) s.
Proof using.
apply: step_star_lb_step_execution.
exact: step_ordered_dynamic_star_lb_step_reachable.
Qed.
End LabeledStepOrderDynamic.
Section LabeledStepOrderDynamicFailure.
Context `{labeled_multi_params : LabeledMultiParams}.
Inductive lb_step_ordered_dynamic_failure : lb_step_relation (list name * ordered_dynamic_network) label (name * (input + output)) :=
| LabeledStepOrderedDynamicFailure_deliver : forall net net' failed tr m ms out d d' l from to lb,
~ In to failed ->
In to (odnwNodes net) ->
odnwState net to = Some d ->
odnwPackets net from to = m :: ms ->
lb_net_handlers to from m d = (lb, out, d', l) ->
net' = {| odnwNodes := odnwNodes net;
odnwPackets := collate name_eq_dec to (update2 name_eq_dec (odnwPackets net) from to ms) l;
odnwState := update name_eq_dec (odnwState net) to (Some d') |} ->
tr = map2fst to (map inr out) ->
lb_step_ordered_dynamic_failure (failed, net) lb (failed, net') tr
| LabeledStepOrderedDynamicFailure_input : forall h net net' failed tr out inp d d' l lb,
~ In h failed ->
In h (odnwNodes net) ->
odnwState net h = Some d ->
lb_input_handlers h inp d = (lb, out, d', l) ->
net' = {| odnwNodes := odnwNodes net;
odnwPackets := collate name_eq_dec h (odnwPackets net) l;
odnwState := update name_eq_dec (odnwState net) h (Some d') |} ->
tr = (h, inl inp) :: map2fst h (map inr out) ->
lb_step_ordered_dynamic_failure (failed, net) lb (failed, net') tr
| LabeledStepOrderedDynamicFailure_stutter : forall net failed,
lb_step_ordered_dynamic_failure (failed, net) label_silent (failed, net) [].
Context {overlay_params : NameOverlayParams unlabeled_multi_params}.
Context {fail_msg_params : FailMsgParams unlabeled_multi_params}.
Context {new_msg_params : NewMsgParams unlabeled_multi_params}.
Lemma step_ordered_dynamic_failure_star_lb_step_reachable :
step_star_lb_step_reachable lb_step_ordered_dynamic_failure step_ordered_dynamic_failure step_ordered_dynamic_failure_init.
Proof using.
rewrite /step_star_lb_step_reachable.
case => failed net l.
case => failed' net' tr tr' H_star H_st.
invcs H_st.
- set net' := {| odnwNodes := _ ; odnwPackets := _ ; odnwState := _ |}.
apply (@refl_trans_1n_trace_trans _ _ _ _ (failed', net)) => //.
rewrite (app_nil_end (map2fst _ _)).
apply: (@RT1nTStep _ _ _ _ (failed', net')); last exact: RT1nTBase.
apply: (StepOrderedDynamicFailure_deliver _ _ _ _ _ H5 H6) => //.
rewrite /net_handlers /= /unlabeled_net_handlers /=.
repeat break_let.
by tuple_inversion.
- set net' := {| odnwNodes := _ ; odnwPackets := _ ; odnwState := _ |}.
apply (@refl_trans_1n_trace_trans _ _ _ _ (failed', net)) => //.
rewrite (app_nil_end (_ :: _)).
apply: (@RT1nTStep _ _ _ _ (failed', net')); last exact: RT1nTBase.
apply: (StepOrderedDynamicFailure_input _ _ _ _ H5) => //.
rewrite /input_handlers /= /unlabeled_input_handlers /=.
repeat break_let.
by tuple_inversion.
- by have ->: tr' ++ [] = tr' by auto with datatypes.
Qed.
Lemma step_ordered_dynamic_failure_star_lb_step_execution :
forall s, event_step_star step_ordered_dynamic_failure step_ordered_dynamic_failure_init (hd s) ->
lb_step_execution lb_step_ordered_dynamic_failure s ->
always (now (event_step_star step_ordered_dynamic_failure step_ordered_dynamic_failure_init)) s.
Proof using.
apply: step_star_lb_step_execution.
exact: step_ordered_dynamic_failure_star_lb_step_reachable.
Qed.
End LabeledStepOrderDynamicFailure.
Hint Extern 4 (@LabeledMultiParams _) => apply unlabeled_multi_params : typeclass_instances.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_SYMBOL_V
`define SKY130_FD_SC_HS__A222O_SYMBOL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a222o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
input C2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_SYMBOL_V
|
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