text
stringlengths 938
1.05M
|
|---|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: sys_pll_rb.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module sys_pll_rb (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sys_pll_rb.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_rb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_rb.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_rb.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_rb.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_rb.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_rb_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_rb_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: March, 7th 2017
*/
`timescale 1ns / 1ps
module jt51_sincf #(parameter win=1, wout=5)
(
input clk,
input [win-1:0] din,
output reg [wout-1:0] dout
);
reg [win-1:0] mem[23:0];
genvar i;
generate
for (i=23; i>0; i=i-1) begin: meminput
always @(posedge clk)
mem[i] <= mem[i-1];
end
endgenerate
always @(posedge clk) begin
mem[0] <= din;
dout <= mem[0] + mem[1] + mem[2] + mem[3] +
mem[4] + mem[5] + mem[6] + mem[7] +
mem[8] + mem[9] + mem[10] + mem[11] +
mem[12] + mem[13] + mem[14] + mem[15] +
mem[16] + mem[17] + mem[18] + mem[19] +
mem[20] + mem[21] + mem[22] + mem[23];
end
endmodule |
// iverilog -y .. -o tb-RdyPipe.vvp tb-RdyPipe.v
// vvp tb-RdyPipe.vvp
`timescale 1ns/1ns
module tb;
localparam W = 8;
localparam CYC = 10;
reg clk, rst;
reg idata_vld;
wire idata_rdy;
reg [W-1:0] idata;
wire odata_vld;
reg odata_rdy;
wire [W-1:0] odata;
RdyPipe#(W) dut(clk, rst, idata_vld, idata_rdy, idata, odata_vld, odata_rdy, odata);
initial begin
#0;
rst = 1'b1;
#(10*CYC+CYC/3);
rst = 1'b0;
end
initial begin
#0;
clk = 1'b0;
#(CYC);
forever begin
clk = 1'b1;
#(CYC/2);
clk = 1'b0;
#(CYC-CYC/2);
end
end
task wait_reset_release;
begin
@(posedge clk);
while (rst) @(posedge clk);
end
endtask
event idata_update_event;
reg idata_update_ctrl;
initial begin :ivld
reg [31:0] rngseed, rnum;
integer n;
#0;
idata_vld = 1'b0;
wait_reset_release;
rngseed = 32'h01234567;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
idata_vld <= 1'b0;
idata_update_ctrl = 1'b0;
-> idata_update_event;
repeat (n) @(posedge clk);
end
idata_vld <= 1'b1;
idata_update_ctrl = 1'b1;
-> idata_update_event;
@(posedge clk);
while (~idata_rdy) @(posedge clk);
end
end
initial begin :idat
reg [31:0] rngseed, rnum;
#0;
idata = {W{1'b0}};
rngseed = 32'h23456789;
forever begin
@(idata_update_event);
if (idata_update_ctrl) begin
rnum = $random(rngseed);
idata <= rnum[W-1:0];
end else begin
idata <= {W{1'bx}};
end
end
end
initial begin :ordy
reg [31:0] rngseed, rnum;
integer n;
#0;
odata_rdy = 1'b0;
wait_reset_release;
rngseed = 32'h12345678;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
odata_rdy <= 1'b0;
repeat (n) @(posedge clk);
end
odata_rdy <= 1'b1;
@(posedge clk);
end
end
initial begin
$dumpfile("tb-RdyPipe.vcd");
$dumpvars(0, dut);
#(1000*CYC);
$display("Simulated 1000 cycles.");
$finish;
end
initial begin :verify_idata
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h23456789;
forever begin
if (idata_vld & idata_rdy) begin
rnum = $random(rngseed);
if (idata !== rnum[W-1:0]) begin
$display("%0t: Error: idata %h != %h", $time, idata, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, idata);
end
@(posedge clk);
end
end
initial begin :verify_odata
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h23456789;
forever begin
if (odata_vld & odata_rdy) begin
rnum = $random(rngseed);
if (odata !== rnum[W-1:0]) begin
$display("%0t: Error: odata %h != %h", $time, odata, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, odata);
end
@(posedge clk);
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__INV_FUNCTIONAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_FUNCTIONAL_PP_V |
`include "senior_defines.vh"
module dsp_core(
input wire clk_i,
input wire reset_i,
// for io operations
output wire [15:0] io_data_o,
input wire [15:0] io_data_i,
output wire io_wr_strobe_o,
output wire io_rd_strobe_o,
output wire [7:0] io_addr_o,
// for PM
output wire [15:0] pm_addr_o,
input wire [31:0] pm_data_i,
// for DM0
output wire [15:0] dm0_addr_o,
output wire [15:0] dm0_data_o,
output wire dm0_wr_en_o,
input wire [15:0] dm0_data_i,
// for DM1
output wire [15:0] dm1_addr_o,
output wire [15:0] dm1_data_o,
output wire dm1_wr_en_o,
input wire [15:0] dm1_data_i
);
//internal declarations
wire [15:0] pm_addr;
wire [15:0] rf_opb_bus_dm;
wire interrupt;
wire pc_opa_sel;
wire pfc_loopn_sel;
wire [2:0] pc_mode_sel;
wire nopmux_sel;
wire condition_check;
wire condition_check_p5;
wire [15:0] loopb;
wire [15:0] loope;
wire [15:0] rf_opa_bus;
reg [15:0] io_rf_bus;
reg [15:0] dm1_data;
wire [15:0] io_in_data;
wire [15:0] ise;
wire [15:0] id_lc_loopn_value;
wire [15:0] id_lc_loope_value;
wire [31:0] pm_inst_bus;
wire [15:0] rf_opa_bus_unr;
wire [15:0] fwdmux_opa_bus_unr;
wire [15:0] fwdmux_opb_bus_unr;
wire [15:0] rfpp_rf_rfin;
wire [15:0] mac_data_bus;
wire [15:0] mac_data_bus_unr;
wire [15:0] alu_data_bus;
wire [15:0] alu_data_bus_unr;
wire [15:0] selected_op_a;
wire [15:0] selected_op_b;
wire loop_flag;
wire [15:0] rf_opb_bus_unr;
wire [15:0] rf_opb_bus;
wire [15:0] rf_opa_bus_alu;
wire wb_mux_o_rf_cond;
wire [`ALU_NUM_FLAGS-1:0] alu_o_flags;
reg [`ALU_NUM_FLAGS-1:0] alu_o_flags_ff;
wire [`MAC_NUM_FLAGS-1:0] alu_o_masked_mac_flags;
wire [`MAC_NUM_FLAGS-1:0] mac_o_flags;
//SPR signals
parameter spr_dat_w = `SPR_DATA_BUS_WIDTH;
parameter spr_adr_w = `SPR_ADR_BUS_WIDTH;
reg [spr_dat_w-1:0] spr_result;
wire [spr_dat_w-1:0] loop_counter_o_spr_dat;
wire [spr_dat_w-1:0] agu_o_spr_dat;
wire [spr_dat_w-1:0] alu_o_spr_dat;
wire [spr_dat_w-1:0] mac_o_spr_dat;
wire [`SENIOR_NATIVE_WIDTH-1:0] id_o_imm_val_p3;
wire [`SENIOR_NATIVE_WIDTH-1:0] id_o_imm_val_p4;
wire [`SENIOR_NATIVE_WIDTH-1:0] id_o_imm_val_p5;
wire [spr_dat_w-1:0] spr_dat;
wire [spr_adr_w-1:0] spr_adr;
wire spr_wren;
//Control signals
wire [`PFC_CTRL_WIDTH-1:0] id_o_pc_fsm_ctrl;
wire [`IO_CTRL_WIDTH-1:0] id_o_io_ctrl;
wire [`OPSEL_CTRL_WIDTH-1:0] id_o_opsel_ctrl;
wire [`LC_CTRL_WIDTH-1:0] id_o_loop_counter_ctrl;
wire [`AGU_CTRL_WIDTH-1:0] id_o_agu_ctrl;
wire [`WB_MUX_CTRL_WIDTH-1:0] id_o_wb_mux_ctrl;
wire [`RF_CTRL_WIDTH-1:0] id_o_rf_ctrl;
wire [`ALU_CTRL_WIDTH-1:0] id_o_alu_ctrl;
wire [`MAC_CTRL_WIDTH-1:0] id_o_mac_ctrl;
wire [`COND_LOGIC_CTRL_WIDTH-1:0] id_o_cond_logic_ctrl_p5;
wire [`COND_LOGIC_CTRL_WIDTH-1:0] id_o_cond_logic_ctrl_p4;
wire [`SPR_CTRL_WIDTH-1:0] id_o_spr_ctrl;
wire [`DM_DATA_SELECT_CTRL_WIDTH-1:0] id_o_dm_data_select_ctrl;
wire [`FWDMUX_CTRL_WIDTH-1:0] fwd_o_fwdmux_ctrl;
wire [`FWD_CTRL_WIDTH-1:0] id_o_fwd_ctrl;
always @(posedge clk_i) begin
spr_result <=
loop_counter_o_spr_dat |
agu_o_spr_dat |
alu_o_spr_dat |
mac_o_spr_dat;
end
assign interrupt = 0;
assign spr_adr = id_o_spr_ctrl`SPR_ADR;
assign spr_wren = id_o_spr_ctrl`SPR_WREN;
assign spr_dat = (id_o_spr_ctrl`SPR_SOURCE == `SPR_SOURCE_RF)
? rf_opa_bus
: id_o_imm_val_p4;
reg [15:0] pm_addr_ff;
reg condition_check_ff;
assign pm_addr_o = pm_addr;
always@(posedge clk_i) begin
pm_addr_ff <= pm_addr;
condition_check_ff <= wb_mux_o_rf_cond;
io_rf_bus <= io_in_data;
end
// instances
pc_fsm pc_fsm(
// Outputs
.pfc_pc_add_opa_sel_o (pc_opa_sel),
.pfc_lc_loopn_sel_o (pfc_loopn_sel),
.pfc_pc_sel_o (pc_mode_sel),
.pfc_inst_nop_o (nopmux_sel),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.jump_decision_i (condition_check),
.lc_pfc_loope_i (loope),
.lc_pfc_loop_flag_i (loop_flag),
.ctrl_i (id_o_pc_fsm_ctrl),
.interrupt (interrupt),
.pc_addr_bus_i (pm_addr_ff));
io io
(
// Outputs
.io_intdata_o (io_in_data),
.io_wr_strobe_o (io_wr_strobe_o),
.io_rd_strobe_o (io_rd_strobe_o),
.io_data_o (io_data_o),
.io_addr_o (io_addr_o),
// Inputs
.io_intdata_i (rf_opa_bus),
.ctrl_i (id_o_io_ctrl),
.io_data_i (io_data_i));
program_counter program_counter
(
// Outputs
.pc_addr_bus_o (pm_addr),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.ise_i (ise),
.lc_pc_loopb_i (loopb),
.ta_i (rf_opa_bus),
.pfc_pcadd_opa_sel_i (pc_opa_sel),
.pfc_pc_sel_i (pc_mode_sel),
.stack_address_i (dm1_data_i));
loop_controller loop_counter
(
// Outputs
.lc_pfc_loop_flag_o (loop_flag),
.lc_pfc_loopb_o (loopb),
.lc_pfc_loope_o (loope),
.spr_dat_o (loop_counter_o_spr_dat),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.pfc_lc_loopn_sel_i (pfc_loopn_sel),
.ctrl_i (id_o_loop_counter_ctrl),
.rf_opa_bus_i (rf_opa_bus),
.pc_lc_addr_i (pm_addr_ff),
.spr_dat_i (spr_dat),
.spr_adr_i (spr_adr),
.spr_wren_i (spr_wren));
nop_mux nop_mux(
.pfc_inst_nop_i (nopmux_sel),
.pm_inst_bus_i (pm_data_i),
.pm_inst_bus_o (pm_inst_bus)
);
instruction_decoder instruction_decoder
(
// Outputs
.agu_ctrl_o (id_o_agu_ctrl),
.alu_ctrl_o (id_o_alu_ctrl),
.mac_ctrl_o (id_o_mac_ctrl),
.cond_logic_ctrl_p5_o (id_o_cond_logic_ctrl_p5),
.cond_logic_ctrl_p4_o (id_o_cond_logic_ctrl_p4),
.loop_counter_ctrl_o (id_o_loop_counter_ctrl),
.wb_mux_ctrl_o (id_o_wb_mux_ctrl),
.pc_fsm_ctrl_o (id_o_pc_fsm_ctrl),
.rf_ctrl_o (id_o_rf_ctrl),
.io_ctrl_o (id_o_io_ctrl),
.opsel_ctrl_o (id_o_opsel_ctrl),
.imm_val_p3_o (id_o_imm_val_p3),
.imm_val_p4_o (id_o_imm_val_p4),
.imm_val_p5_o (id_o_imm_val_p5),
.spr_ctrl_o (id_o_spr_ctrl),
.dm_data_select_ctrl_o (id_o_dm_data_select_ctrl),
.fwd_ctrl_o (id_o_fwd_ctrl),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.pm_inst_bus_i (pm_inst_bus));
combined_agu agu
(
// Outputs
.dm0_address_o (dm0_addr_o),
.dm0_wren_o (dm0_wr_en_o),
.dm1_address_o (dm1_addr_o),
.dm1_wren_o (dm1_wr_en_o),
.spr_dat_o (agu_o_spr_dat),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.ctrl_i (id_o_agu_ctrl),
.id_data_bus_i (id_o_imm_val_p3),
.rf_opa_bus_i (fwdmux_opa_bus_unr),
.spr_dat_i (spr_dat),
.spr_adr_i (spr_adr),
.spr_wren_i (spr_wren));
// data_memory muxes
assign dm0_data_o = id_o_dm_data_select_ctrl`DM0_SELECT ? fwdmux_opa_bus_unr : fwdmux_opb_bus_unr;
assign dm1_data_o = dm1_data;
always@* begin
dm1_data = fwdmux_opb_bus_unr;
case(id_o_dm_data_select_ctrl`DM1_SELECT)
2'b00: dm1_data = fwdmux_opb_bus_unr;
2'b01: dm1_data = pm_addr;
2'b10: dm1_data = pm_addr+1;
2'b11: dm1_data = spr_result; //To be able to push sr registers to stack, not used at this time
endcase
end
write_back_mux wb_mux
(
// Outputs
.dat_o (rfpp_rf_rfin),
.rf_cond_o (wb_mux_o_rf_cond),
// Inputs
.io_rf_bus_i (io_rf_bus),
.id_data_bus_i (id_o_imm_val_p5),
.mac_data_bus_i (mac_data_bus),
.alu_data_bus_i (alu_data_bus),
.rf_opa_in_bus_i (rf_opa_bus),
.dm0_data_bus_i (dm0_data_i),
.dm1_data_bus_i (dm1_data_i),
.spr_result_i (spr_result),
.cond_check_p4_i (condition_check),
.cond_check_p5_i (condition_check_p5),
.ctrl_i (id_o_wb_mux_ctrl));
operand_select opsel
(
// Outputs
.op_a_o (selected_op_a),
.op_b_o (selected_op_b),
// Inputs
.imm_val_i (id_o_imm_val_p3),
.rf_a_i (fwdmux_opa_bus_unr),
.rf_b_i (fwdmux_opb_bus_unr),
.ctrl_i (id_o_opsel_ctrl));
fwd_ctrl fwd
(
//Outputs
.fwdmux_ctrl_o (fwd_o_fwdmux_ctrl),
//Inputs
.ctrl_i (id_o_fwd_ctrl),
.condition_p4_i (condition_check),
.condition_p5_i (condition_check_p5),
.condition_wb_i (condition_check_ff),
.rf_ctrl_i (id_o_rf_ctrl));
fwdmux fwdmux
(
//Outputs
.opa_o (fwdmux_opa_bus_unr),
.opb_o (fwdmux_opb_bus_unr),
//Inputs
.ctrl_i (fwd_o_fwdmux_ctrl),
.rf_a_i (rf_opa_bus_unr),
.rf_b_i (rf_opb_bus_unr),
.dm1_data_i (dm1_data_i),
.alu_p4_result_i (alu_data_bus_unr),
.wb_result_i (rfpp_rf_rfin),
.mac_p5_result_i (mac_data_bus_unr));
register_file register_file
(
// Outputs
.dat_a_o (rf_opa_bus_unr),
.dat_b_o (rf_opb_bus_unr),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.pass_through_dat_i (id_o_imm_val_p3),
.ctrl_i (id_o_rf_ctrl),
.dat_i (rfpp_rf_rfin),
.dm_dat_i (dm1_data_i),
.register_enable_i (condition_check_ff));
dff operandA_register(
// Outputs
.clocked_dat_o (rf_opa_bus),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.dat_i (fwdmux_opa_bus_unr));
dff operandB_register(
// Outputs
.clocked_dat_o (rf_opb_bus),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.dat_i (selected_op_b));
dff operandA_alu_register(
// Outputs
.clocked_dat_o(rf_opa_bus_alu),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.dat_i (selected_op_a));
dff operandB_DM_register(
// Outputs
.clocked_dat_o(rf_opb_bus_dm),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.dat_i (selected_op_b));
alu ALU(
// Outputs
.flags_o (alu_o_flags),
.masked_mac_flags_o (alu_o_masked_mac_flags),
.result_o (alu_data_bus),
.result_unr_o (alu_data_bus_unr),
.spr_dat_o (alu_o_spr_dat),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.ctrl_i (id_o_alu_ctrl),
.opa_i (rf_opa_bus_alu),
.opb_i (rf_opb_bus),
.condition_check_i (condition_check),
.mac_flags_i (mac_o_flags),
.spr_dat_i (spr_dat),
.spr_adr_i (spr_adr),
.spr_wren_i (spr_wren));
mac MAC(
// Outputs
.dat_o (mac_data_bus),
.dat_o_unr (mac_data_bus_unr),
.flags_o (mac_o_flags),
.spr_dat_o (mac_o_spr_dat),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.dm0_data_bus_i (dm0_data_i),
.rf_opa_bus_i (fwdmux_opa_bus_unr),
.dm1_data_bus_i (dm1_data_i),
.rf_opb_bus_i (fwdmux_opb_bus_unr),
.ctrl_i (id_o_mac_ctrl),
.alu_flags_i (alu_o_flags),
.condition_check_i (condition_check_p5),
.spr_dat_i (spr_dat),
.spr_adr_i (spr_adr),
.spr_wren_i (spr_wren));
condition_logic condition_logic_p4
(
// Outputs
.condition_check_o (condition_check),
// Inputs
.ctrl_i (id_o_cond_logic_ctrl_p4),
.alu_flags_i (alu_o_flags),
.mac_flags_i (mac_o_flags));
always@(posedge clk_i) begin
alu_o_flags_ff <= alu_o_flags;
end
condition_logic condition_logic_p5
(
// Outputs
.condition_check_o (condition_check_p5),
// Inputs
.ctrl_i (id_o_cond_logic_ctrl_p5),
.alu_flags_i (alu_o_flags_ff),
.mac_flags_i (mac_o_flags));
endmodule
|
`timescale 1ns / 1ps
module jt12_test;
reg rst;
`include "../common/dump.vh"
reg clk; // 4MHz clock
initial begin
clk = 0;
forever #125 clk=~clk;
end
reg [1:0] clkcnt;
reg clk_en;
reg rst0;
initial begin
rst0=0;
#10 rst0=1;
#10 rst0=0;
end
always @(negedge clk or posedge rst0)
if( rst0 ) begin
clkcnt <= 2'd0;
clk_en <= 1'b0;
end
else begin
if ( clkcnt== 2'b1 ) begin
clkcnt <= 2'd0;
clk_en <= 1'b1;
end
else begin
clkcnt <= clkcnt+1'b1;
clk_en <= 1'b0;
end
end
integer limit_time_cnt;
initial begin
rst = 0;
limit_time_cnt=0;
#500 rst = 1;
#600 rst = 0;
// reset again, when all the pipeline is clear
#(2500*1000) rst=1;
#1000 rst=0;
end
`ifdef LIMITTIME
initial begin
for( limit_time_cnt=`LIMITTIME; limit_time_cnt>0; limit_time_cnt=limit_time_cnt-1 )
#(1000*1000);
$finish;
end
`endif
wire cs_n, wr_n, prog_done;
wire [ 7:0] din, dout;
wire signed [11:0] right, left;
wire [ 1:0] addr;
jt12_testdata #(.rand_wait(`RANDWAIT)) u_testdata(
.rst ( rst ),
.clk ( clk ),
.cs_n ( cs_n ),
.wr_n ( wr_n ),
.dout ( din ),
.din ( dout ),
.addr ( addr ),
.prog_done(prog_done)
);
always @(posedge clk)
if( prog_done ) begin
#(2000*1000);
`ifdef DUMPSOUND
$display("DUMP END");
`endif
$finish;
end
wire sample, mux_sample;
wire signed [11:0] snd_left, snd_right;
wire irq_n = 1'b1;
jt12 uut(
.rst ( rst ),
.clk ( clk ),
.cen ( 1'b1 ),
.din ( din ),
.addr ( addr ),
.cs_n ( cs_n ),
.wr_n ( wr_n ),
.limiter_en( 1'b1 ),
.dout ( dout ),
.irq_n ( irq_n ),
// 1 bit output per channel at 1.3MHz
.snd_left ( snd_left ),
.snd_right ( snd_right ),
// unused outputs
.snd_sample(),
.mux_right(),
.mux_left(),
.mux_sample()
);
`ifdef DUMPSOUND
initial $display("DUMP START");
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_TB_V
`define SKY130_FD_SC_HDLL__INV_TB_V
/**
* inv: Inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__inv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BAI_BLACKBOX_V
`define SKY130_FD_SC_LS__O21BAI_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BAI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S18KAPWR_1_V
`define SKY130_FD_SC_LP__DLYBUF4S18KAPWR_1_V
/**
* dlybuf4s18kapwr: Delay Buffer 4-stage 0.18um length inner stage
* gates on keep-alive power rail.
*
* Verilog wrapper for dlybuf4s18kapwr with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlybuf4s18kapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlybuf4s18kapwr_1 (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlybuf4s18kapwr base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlybuf4s18kapwr_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlybuf4s18kapwr base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S18KAPWR_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A221O_BEHAVIORAL_PP_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a221o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221O_BEHAVIORAL_PP_V |
// tb200.v - A WCI::OCP test bench with BFM, DUT, and Monitor/Observer
// Copyright (c) 2010 Atomic Rules LLC - ALL RIGHTS RESERVED
//
// This testbench instances three components, and provides them with a common clock and reset
// These three components are connected together with the WCI0_ signal group
// 1. A BFM "Initiator" which initiates WCI cycles
// 2. A DUT "Taget" which completes WCI cycles
// 3. A Monitor/Observer which watches ober the WCI cycles
`timescale 1ns/1ps
module tb200 ();
reg CLK; // System Clock
reg RST_N; // System Reset (active-low)
always begin // Clock generation...
#5; CLK = 1'b0;
#5; CLK = 1'b1;
end
initial begin: initblock
integer i;
localparam resetCycles = 16;
#0 RST_N = 1'b0; $display("[%0d] %m: System Reset Asserted, RST_N=0", $time);
for (i=0;i<resetCycles;i=i+1) @(posedge CLK);
#0 RST_N = 1'b1; $display("[%0d] %m: System Reset Released, RST_N=1", $time);
end
// WCI0_ WCI::OCP Wires to interconnect the BFM, DUT and Monitor...
wire WCI0_Clk = CLK; // Connect system clock to be the clock of the WCI0 M/S/O link
wire WCI0_MReset_n;
wire [2:0] WCI0_MCmd;
wire WCI0_MAddrSpace;
wire [3:0] WCI0_MByteEn;
wire [19:0] WCI0_MAddr;
wire [31:0] WCI0_MData;
wire [1:0] WCI0_SResp;
wire [31:0] WCI0_SData;
wire WCI0_SThreadBusy;
wire [1:0] WCI0_SFlag;
wire [1:0] WCI0_MFlag;
mkWciOcpInitiator bfm ( // Instance the BFM Initiator...
.CLK (CLK),
.RST_N (RST_N),
// .wciM0_Clk (WCI0_Clk),
.RST_N_wciM0 (WCI0_MReset_n), // WCI0_MReset_n is the reset source for this WCI0 link
.wciM0_MCmd (WCI0_MCmd),
.wciM0_MAddrSpace (WCI0_MAddrSpace),
.wciM0_MByteEn (WCI0_MByteEn),
.wciM0_MAddr (WCI0_MAddr),
.wciM0_MData (WCI0_MData),
.wciM0_SResp (WCI0_SResp),
.wciM0_SData (WCI0_SData),
.wciM0_SThreadBusy (WCI0_SThreadBusy),
.wciM0_SFlag (WCI0_SFlag),
.wciM0_MFlag (WCI0_MFlag)
);
mkWciOcpTarget wut ( // Instance the "Worker Under Test" (WUT) target
.wciS0_Clk (WCI0_Clk),
.wciS0_MReset_n (WCI0_MReset_n),
.wciS0_MCmd (WCI0_MCmd),
.wciS0_MAddrSpace (WCI0_MAddrSpace),
.wciS0_MByteEn (WCI0_MByteEn),
.wciS0_MAddr (WCI0_MAddr),
.wciS0_MData (WCI0_MData),
.wciS0_SResp (WCI0_SResp),
.wciS0_SData (WCI0_SData),
.wciS0_SThreadBusy (WCI0_SThreadBusy),
.wciS0_SFlag (WCI0_SFlag),
.wciS0_MFlag (WCI0_MFlag)
);
mkWciOcpMonitor mon ( // Instance the Monitor/Observer...
.CLK (CLK),
.RST_N (RST_N),
.CLK_wci_clk (WCI0_Clk),
.RST_N_wci_rstn (WCI0_MReset_n),
.wciO0_MCmd (WCI0_MCmd),
.wciO0_MAddrSpace (WCI0_MAddrSpace),
.wciO0_MByteEn (WCI0_MByteEn),
.wciO0_MAddr (WCI0_MAddr),
.wciO0_MData (WCI0_MData),
.wciO0_SResp (WCI0_SResp),
.wciO0_SData (WCI0_SData),
.wciO0_SThreadBusy (WCI0_SThreadBusy),
.wciO0_SFlag (WCI0_SFlag),
.wciO0_MFlag (WCI0_MFlag)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVP_8_V
`define SKY130_FD_SC_MS__EINVP_8_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvp_8 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvp_8 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVP_8_V
|
`default_nettype none
`timescale 1ns/1ns
`define simulation
module tb_ptr();
wire clk, reset;
clock clock(clk, reset);
reg write = 0;
reg [31:0] writedata = 0;
reg iobus_iob_poweron = 1;
reg iobus_iob_reset = 0;
reg iobus_datao_clear = 0;
reg iobus_datao_set = 0;
reg iobus_cono_clear = 0;
reg iobus_cono_set = 0;
reg iobus_iob_fm_datai = 0;
reg iobus_iob_fm_status = 0;
reg [3:9] iobus_ios = 0;
reg [0:35] iobus_iob_in = 0;
wire [1:7] iobus_pi_req;
wire [0:35] iobus_iob_out;
reg key_start = 0;
reg key_stop = 0;
reg key_tape_feed = 0;
wire data_rq;
ptr ptr(.clk(clk), .reset(~reset),
.iobus_iob_poweron(iobus_iob_poweron),
.iobus_iob_reset(iobus_iob_reset),
.iobus_datao_clear(iobus_datao_clear),
.iobus_datao_set(iobus_datao_set),
.iobus_cono_clear(iobus_cono_clear),
.iobus_cono_set(iobus_cono_set),
.iobus_iob_fm_datai(iobus_iob_fm_datai),
.iobus_iob_fm_status(iobus_iob_fm_status),
.iobus_ios(iobus_ios),
.iobus_iob_in(iobus_iob_in),
.iobus_pi_req(iobus_pi_req),
.iobus_iob_out(iobus_iob_out),
.key_start(key_start),
.key_stop(key_stop),
.key_tape_feed(key_tape_feed),
.s_write(write),
.s_writedata(writedata),
.fe_data_rq(data_rq));
initial begin
$dumpfile("dump.vcd");
$dumpvars();
#100;
iobus_iob_reset <= 1;
#100;
iobus_iob_reset <= 0;
#100;
iobus_ios <= 7'b001_000_1;
key_start <= 1;
#20;
key_start <= 0;
#200;
// key_tape_feed <= 1;
ptr.ptr_pia <= 1;
ptr.ptr_flag <= 0;
ptr.ptr_busy <= 1;
ptr.ptr <= 1;
end
initial begin: foo
integer i;
@(posedge data_rq);
for(i = 0; i < 20; i = i+1) begin
@(posedge clk);
end
write <= 1;
writedata <= 'o277;
@(posedge clk);
write <= 0;
/*
@(posedge data_rq);
for(i = 0; i < 20; i = i+1) begin
@(posedge clk);
end
write <= 1;
writedata <= 'o266;
@(posedge clk);
write <= 0;
@(posedge data_rq);
for(i = 0; i < 20; i = i+1) begin
@(posedge clk);
end
write <= 1;
writedata <= 'o255;
@(posedge clk);
write <= 0;
@(posedge data_rq);
for(i = 0; i < 20; i = i+1) begin
@(posedge clk);
end
write <= 1;
writedata <= 'o244;
@(posedge clk);
write <= 0;
@(posedge data_rq);
for(i = 0; i < 20; i = i+1) begin
@(posedge clk);
end
write <= 1;
writedata <= 'o233;
@(posedge clk);
write <= 0;
@(posedge data_rq);
for(i = 0; i < 20; i = i+1) begin
@(posedge clk);
end
write <= 1;
writedata <= 'o222;
@(posedge clk);
write <= 0;
@(posedge (|iobus_pi_req));
iobus_iob_fm_datai <= 1;
#400;
iobus_iob_fm_datai <= 0;
key_stop <= 1;
#20;
key_stop <= 0;
*/
end
initial begin
#40000;
$finish;
end
endmodule
|
`timescale 1ns / 1ps
`include "../src/axis_blender.v"
module test_axis_blender_2lvl(
);
parameter integer C_CHN_WIDTH = 8;
parameter integer C_S0_CHN_NUM = 1;
parameter integer C_S1_CHN_NUM = 3;
parameter integer C_ALPHA_WIDTH = 8;
parameter integer C_S1_ENABLE = 1;
parameter integer C_IN_NEED_WIDTH = 1;
parameter integer C_OUT_NEED_WIDTH = 0; /// must be (C_IN_NEED_WIDTH - 1), min val is 0
parameter integer C_M_WIDTH = 24; /// must be max(C_S0_CHN_NUM, C_S1_CHN_NUM) * C_CHN_WIDTH
parameter integer C_TEST = 0;
reg clk;
reg resetn;
localparam integer C_MAX_STREAM_NUM = 2;
localparam integer C_IMG_BITS = 12;
reg [C_MAX_STREAM_NUM-1:0] s_random ;
reg [C_IMG_BITS-1:0] s_width;
reg [C_IMG_BITS-1:0] s_height;
reg s_valid [C_MAX_STREAM_NUM-1:0];
wire [C_M_WIDTH + C_ALPHA_WIDTH-1:0] s_data [C_MAX_STREAM_NUM-1:0];
wire [C_IN_NEED_WIDTH:0] s_user [C_MAX_STREAM_NUM-1:0];
wire s_last [C_MAX_STREAM_NUM-1:0];
wire s_ready [C_MAX_STREAM_NUM-1:0];
reg s_enable [C_MAX_STREAM_NUM-1:0];
reg m_random ;
reg m_enprint;
wire sint_valid;
wire [C_CHN_WIDTH*C_S0_CHN_NUM-1:0] sint_data ;
wire sint_user ;
wire sint_last ;
wire sint_ready;
wire m_valid ;
wire [C_M_WIDTH-1:0] m_data ;
wire [C_OUT_NEED_WIDTH:0]m_user ;
wire m_last ;
reg m_ready ;
axis_blender # (
.C_CHN_WIDTH (8 ),
.C_S0_CHN_NUM (1 ),
.C_S1_CHN_NUM (1 ),
.C_ALPHA_WIDTH (0 ),
.C_S1_ENABLE (0 ),
.C_IN_NEED_WIDTH (1 ),
.C_OUT_NEED_WIDTH (0 ),
.C_M_WIDTH (8 ),
.C_TEST (0 )
) blender1 (
.clk(clk),
.resetn(resetn),
.s0_axis_tvalid(s_valid [0]),
.s0_axis_tdata (s_data [0][7:0]),
.s0_axis_tuser (s_user [0][1:0]),
.s0_axis_tlast (s_last [0]),
.s0_axis_tready(s_ready [0]),
//.s1_enable (0),
//.s1_axis_tvalid(0),
//.s1_axis_tdata (0),
//.s1_axis_tuser (0),
//.s1_axis_tlast (0),
//.s1_axis_tready(0),
.m_axis_tvalid(sint_valid ),
.m_axis_tdata (sint_data ),
.m_axis_tuser (sint_user ),
.m_axis_tlast (sint_last ),
.m_axis_tready(sint_ready )
);
axis_blender # (
.C_CHN_WIDTH (8 ),
.C_S0_CHN_NUM (1 ),
.C_S1_CHN_NUM (3 ),
.C_ALPHA_WIDTH (8 ),
.C_S1_ENABLE (1 ),
.C_IN_NEED_WIDTH (0 ),
.C_OUT_NEED_WIDTH (0),
.C_M_WIDTH (24 ),
.C_TEST (0 )
) blender2 (
.clk(clk),
.resetn(resetn),
.s0_axis_tvalid(sint_valid ),
.s0_axis_tdata (sint_data ),
.s0_axis_tuser (sint_user ),
.s0_axis_tlast (sint_last ),
.s0_axis_tready(sint_ready ),
.s1_enable (s_enable [0]),
.s1_axis_tvalid(s_valid [1]),
.s1_axis_tdata (s_data [1]),
.s1_axis_tuser (s_user [1][0]),
.s1_axis_tlast (s_last [1]),
.s1_axis_tready(s_ready [1]),
.m_axis_tvalid(m_valid ),
.m_axis_tdata (m_data ),
.m_axis_tuser (m_user ),
.m_axis_tlast (m_last ),
.m_axis_tready(m_ready )
);
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
initial begin
s_enable[0] <= 1;
s_enable[1] <= 1;
s_random <= 2'b11;
m_random <= 1'b1;
m_enprint <= 1'b1;
s_width <= 3;
s_height <= 5;
end
generate
genvar i;
genvar j;
for (i = 0; i < 2; i = i + 1) begin: single_input
reg [C_IMG_BITS-1:0] s_ridx;
reg [C_IMG_BITS-1:0] s_cidx;
reg en_input;
always @ (posedge clk) begin
if (resetn == 1'b0) en_input <= 1'b0;
else en_input <= (s_random[i] ? {$random}%2 : 1);
end
always @ (posedge clk) begin
if (resetn == 1'b0)
s_valid[i] <= 1'b0;
else if (~s_valid[i]) begin
if (en_input)
s_valid[i] <= 1'b1;
end
else begin
if (s_ready[i])
s_valid[i] <= en_input;
end
end
assign s_data[i] = (s_ridx * 16 + s_cidx) + (255 << 16);
assign s_user[i] = (s_ridx == 0 && s_cidx == 0);
assign s_last[i] = (s_cidx == s_width - 1);
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s_ridx <= 0;
s_cidx <= 0;
end
else if (s_valid[i] && s_ready[i]) begin
if (s_cidx != s_width - 1) begin
s_cidx <= s_cidx + 1;
s_ridx <= s_ridx;
end
else if (s_ridx != s_height - 1) begin
s_cidx <= 0;
s_ridx <= s_ridx + 1;
end
else begin
s_cidx <= 0;
s_ridx <= 0;
end
end
end
end
endgenerate
generate
reg [C_IMG_BITS-1:0] m_ridx;
reg [C_IMG_BITS-1:0] m_cidx;
reg en_output;
always @ (posedge clk) begin
if (resetn == 1'b0) en_output <= 1'b0;
else en_output <= (m_random ? {$random}%2 : 1);
end
always @(posedge clk) begin
if (resetn == 1'b0)
m_ready <= 1'b0;
else if (~m_ready)
m_ready <= en_output;
else begin
if (m_valid)
m_ready <= en_output;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
m_ridx = 0;
m_cidx = 0;
end
else if (m_ready && m_valid) begin
if (m_user[0]) begin
m_ridx = 0;
m_cidx = 0;
end
else if (m_last) begin
m_cidx = 0;
m_ridx = m_ridx + 1;
end
else begin
m_cidx = m_cidx + 1;
m_ridx = m_ridx;
end
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
end
else if (m_ready && m_valid && m_enprint) begin
if (m_user[0])
$write("out new frame: \n");
$write("%h ", m_data);
if (m_last)
$write("\n");
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:01:54 12/16/2014
// Design Name:
// Module Name: MUX1_8
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MUX1_8( address,
wr_en,din,
wr_en0,wr_en1,wr_en2,wr_en3,wr_en4,wr_en5,wr_en6,wr_en7,
din0 ,din1 ,din2 ,din3 ,din4 ,din5 ,din6 ,din7
);
input [2:0] address;
input wr_en;
input [127:0] din;
output reg wr_en0;
output reg wr_en1;
output reg wr_en2;
output reg wr_en3;
output reg wr_en4;
output reg wr_en5;
output reg wr_en6;
output reg wr_en7;
output reg [127:0] din0;
output reg [127:0] din1;
output reg [127:0] din2;
output reg [127:0] din3;
output reg [127:0] din4;
output reg [127:0] din5;
output reg [127:0] din6;
output reg [127:0] din7;
always@(*)
begin
case(address)
3'd0:begin
wr_en0=wr_en;
wr_en1=1'b0;
wr_en2=1'b0;
wr_en3=1'b0;
wr_en4=1'b0;
wr_en5=1'b0;
wr_en6=1'b0;
wr_en7=1'b0;
din0=din;
din1=128'b0;
din2=128'b0;
din3=128'b0;
din4=128'b0;
din5=128'b0;
din6=128'b0;
din7=128'b0;
end
3'd1:begin
wr_en0=1'b0;
wr_en1=wr_en;
wr_en2=1'b0;
wr_en3=1'b0;
wr_en4=1'b0;
wr_en5=1'b0;
wr_en6=1'b0;
wr_en7=1'b0;
din0=128'b0;
din1=din;
din2=128'b0;
din3=128'b0;
din4=128'b0;
din5=128'b0;
din6=128'b0;
din7=128'b0;
end
3'd2:begin
wr_en0=1'b0;
wr_en1=1'b0;
wr_en2=wr_en;
wr_en3=1'b0;
wr_en4=1'b0;
wr_en5=1'b0;
wr_en6=1'b0;
wr_en7=1'b0;
din0=128'b0;
din1=128'b0;
din2=din;
din3=128'b0;
din4=128'b0;
din5=128'b0;
din6=128'b0;
din7=128'b0;
end
3'd3:begin
wr_en0=1'b0;
wr_en1=1'b0;
wr_en2=1'b0;
wr_en3=wr_en;
wr_en4=1'b0;
wr_en5=1'b0;
wr_en6=1'b0;
wr_en7=1'b0;
din0=128'b0;
din1=128'b0;
din2=128'b0;
din3=din;
din4=128'b0;
din5=128'b0;
din6=128'b0;
din7=128'b0;
end
3'd4:begin
wr_en0=1'b0;
wr_en1=1'b0;
wr_en2=1'b0;
wr_en3=1'b0;
wr_en4=wr_en;
wr_en5=1'b0;
wr_en6=1'b0;
wr_en7=1'b0;
din0=128'b0;
din1=128'b0;
din2=128'b0;
din3=128'b0;
din4=din;
din5=128'b0;
din6=128'b0;
din7=128'b0;
end
3'd5:begin
wr_en0=1'b0;
wr_en1=1'b0;
wr_en2=1'b0;
wr_en3=1'b0;
wr_en4=1'b0;
wr_en5=wr_en;
wr_en6=1'b0;
wr_en7=1'b0;
din0=128'b0;
din1=128'b0;
din2=128'b0;
din3=128'b0;
din4=128'b0;
din5=din;
din6=128'b0;
din7=128'b0;
end
3'd6:begin
wr_en0=1'b0;
wr_en1=1'b0;
wr_en2=1'b0;
wr_en3=1'b0;
wr_en4=1'b0;
wr_en5=1'b0;
wr_en6=wr_en;
wr_en7=1'b0;
din0=128'b0;
din1=128'b0;
din2=128'b0;
din3=128'b0;
din4=128'b0;
din5=128'b0;
din6=din;
din7=128'b0;
end
3'd7:begin
wr_en0=1'b0;
wr_en1=1'b0;
wr_en2=1'b0;
wr_en3=1'b0;
wr_en4=1'b0;
wr_en5=1'b0;
wr_en6=1'b0;
wr_en7=wr_en;
din0=128'b0;
din1=128'b0;
din2=128'b0;
din3=128'b0;
din4=128'b0;
din5=128'b0;
din6=128'b0;
din7=din;
end
default:begin
wr_en0=1'b0;
wr_en1=1'b0;
wr_en2=1'b0;
wr_en3=1'b0;
wr_en4=1'b0;
wr_en5=1'b0;
wr_en6=1'b0;
wr_en7=1'b0;
din0=128'b0;
din1=128'b0;
din2=128'b0;
din3=128'b0;
din4=128'b0;
din5=128'b0;
din6=128'b0;
din7=128'b0;
end
endcase
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_ResetCatchAndSync_2(
input clock,
input reset,
input test_mode,
output io_sync_reset
);
wire reset_n_catch_reg_clock;
wire reset_n_catch_reg_reset;
wire [19:0] reset_n_catch_reg_io_d;
wire [19:0] reset_n_catch_reg_io_q;
wire reset_n_catch_reg_io_en;
wire [18:0] T_6;
wire [19:0] T_7;
wire T_8;
wire T_9;
sirv_AsyncResetRegVec_129 reset_n_catch_reg (
.clock(reset_n_catch_reg_clock),
.reset(reset_n_catch_reg_reset),
.io_d(reset_n_catch_reg_io_d),
.io_q(reset_n_catch_reg_io_q),
.io_en(reset_n_catch_reg_io_en)
);
assign io_sync_reset = test_mode ? reset : T_9;
assign reset_n_catch_reg_clock = clock;
assign reset_n_catch_reg_reset = reset;
assign reset_n_catch_reg_io_d = T_7;
assign reset_n_catch_reg_io_en = 1'h1;
assign T_6 = reset_n_catch_reg_io_q[19:1];
assign T_7 = {1'h1,T_6};
assign T_8 = reset_n_catch_reg_io_q[0];
assign T_9 = ~ T_8;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_MUX_2TO1_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_MUX_2TO1_SYMBOL_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_mux_2to1 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_MUX_2TO1_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTP_1_V
`define SKY130_FD_SC_LP__SRSDFRTP_1_V
/**
* srsdfrtp: Scan flop with sleep mode, inverted reset, non-inverted
* clock, single output.
*
* Verilog wrapper for srsdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srsdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srsdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__srsdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.SLEEP_B(SLEEP_B),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srsdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
SLEEP_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__srsdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTP_1_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_datram.v when simulating
// the core, cx4_datram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_datram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [11 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("77"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(3072),
.C_READ_DEPTH_B(3072),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(3072),
.C_WRITE_DEPTH_B(3072),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFSBP_BEHAVIORAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSBP_BEHAVIORAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_rq_rhq_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Request Header Queue Buffer
// Top level Module: jbi_min_rq_rhq_buf
// Where Instantiated: jbi_min_rq_rhq
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_min_rq_rhq_buf(/*AUTOARG*/
// Outputs
rhq_rdata,
// Inputs
clk, cpu_clk, hold, csr_16x65array_margin, testmux_sel, rhq_csn_wr,
rhq_csn_rd, rhq_waddr, rhq_raddr, wdq_rhq_wdata
);
input clk;
input cpu_clk;
input hold;
input [4:0] csr_16x65array_margin;
input testmux_sel;
input rhq_csn_wr;
input rhq_csn_rd;
input [`JBI_RHQ_ADDR_WIDTH-1:0] rhq_waddr;
input [`JBI_RHQ_ADDR_WIDTH-1:0] rhq_raddr;
input [`JBI_RHQ_WIDTH-1:0] wdq_rhq_wdata;
output [`JBI_RHQ_WIDTH-1:0] rhq_rdata;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_RHQ_WIDTH-1:0] rhq_rdata;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire dangle;
bw_rf_16x65 u_rhq_buf
(.rd_clk(cpu_clk), // read clock
.wr_clk(clk), // read clock
.csn_rd(rhq_csn_rd), // read enable -- active low
.csn_wr(rhq_csn_wr), // write enable -- active low
.hold(hold), // Bypass signal -- unflopped -- bypass input data when 0
.scan_en(1'b0), // Scan enable unflopped
.margin(csr_16x65array_margin), // Delay for the circuits--- set to 10101
.rd_a(rhq_raddr), // read address
.wr_a(rhq_waddr), // Write address
.di({1'b0, wdq_rhq_wdata}), // Data input
.testmux_sel(testmux_sel), // bypass signal -- unflopped -- testmux_sel = 1 bypasses di to do
.si(), // scan in -- NOT CONNECTED
.so(), // scan out -- TIED TO ZERO
.listen_out({dangle, rhq_rdata}), // Listening flop--
.do() // Data out
);
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/mem/rtl/")
// verilog-auto-sense-defines-constant:t
// End:
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pix_pll0.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pix_pll0 (
areset,
inclk0,
c0,
c1,
c2,
c3,
c4,
c5,
c6,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output c6;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] sub_wire0;
wire sub_wire8;
wire [0:0] sub_wire11 = 1'h0;
wire [3:3] sub_wire7 = sub_wire0[3:3];
wire [6:6] sub_wire6 = sub_wire0[6:6];
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [5:5] sub_wire2 = sub_wire0[5:5];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c5 = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire c4 = sub_wire5;
wire c6 = sub_wire6;
wire c3 = sub_wire7;
wire locked = sub_wire8;
wire sub_wire9 = inclk0;
wire [1:0] sub_wire10 = {sub_wire11, sub_wire9};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire10),
.clk (sub_wire0),
.locked (sub_wire8),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 68,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 69,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 8,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 9,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 164,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 207,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 104,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 207,
altpll_component.clk3_phase_shift = "0",
altpll_component.clk4_divide_by = 68,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 207,
altpll_component.clk4_phase_shift = "0",
altpll_component.clk5_divide_by = 35,
altpll_component.clk5_duty_cycle = 50,
altpll_component.clk5_multiply_by = 151,
altpll_component.clk5_phase_shift = "0",
altpll_component.clk6_divide_by = 40,
altpll_component.clk6_duty_cycle = 50,
altpll_component.clk6_multiply_by = 259,
altpll_component.clk6_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 40000,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pix_pll0",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_USED",
altpll_component.port_clk6 = "PORT_USED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 7;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "4"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "68"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "8"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "164"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "104"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "68"
// Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "35"
// Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "40"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.367647"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "28.125000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "31.554878"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "49.759617"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "76.102943"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "107.857140"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE6 STRING "161.875000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "69"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "9"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "207"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "207"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "207"
// Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "151"
// Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "259"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "31.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "75.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "108.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "162.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pix_pll0.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK5 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK6 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLK5 STRING "1"
// Retrieval info: PRIVATE: USE_CLK6 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "68"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "69"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "164"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "207"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "104"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "207"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "68"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "207"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "35"
// Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "151"
// Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK6_DIVIDE_BY NUMERIC "40"
// Retrieval info: CONSTANT: CLK6_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK6_MULTIPLY_BY NUMERIC "259"
// Retrieval info: CONSTANT: CLK6_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5"
// Retrieval info: USED_PORT: c6 0 0 0 0 OUTPUT_CLK_EXT VCC "c6"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5
// Retrieval info: CONNECT: c6 0 0 0 0 @clk 0 0 1 6
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll0.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll0.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll0.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll0.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll0.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll0_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll0_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//sata_link_layer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
module sata_link_layer (
input rst, //reset
input clk,
//Command Interface
output link_layer_ready,
input sync_escape,
output post_align_write,
input hold,
//Phy Layer
input phy_ready,
output write_ready,
input platform_ready,
//XXX: I probably need some feedback to indicate that there is room to write
output [31:0] tx_dout,
output tx_isk,
input [31:0] rx_din,
input [3:0] rx_isk,
input write_start,
output write_strobe,
input [31:0] write_data,
input [31:0] write_size,
input write_hold,
output write_finished,
input write_abort,
output read_start,
output read_strobe,
output [31:0] read_data,
input read_ready,
output read_finished,
output read_crc_ok,
output remote_abort,
output xmit_error,
output wsize_z_error,
input prim_scrambler_en,
input data_scrambler_en,
input is_device,
output [3:0] lax_i_state,
output [3:0] lax_r_state,
output [3:0] lax_w_state,
output [3:0] lax_w_fstate,
//Detection
output detect_sync,
output detect_r_rdy,
output detect_r_ip,
output detect_r_ok,
output detect_r_err,
output detect_x_rdy,
output detect_sof,
output detect_eof,
output detect_wtrm,
output detect_cont,
output detect_hold,
output detect_holda,
output detect_align,
output detect_preq_s,
output detect_preq_p,
output detect_xrdy_xrdy,
output send_crc,
output dbg_send_holda,
output [23:0] in_data_addra,
output [12:0] d_count,
output [12:0] write_count,
output [3:0] buffer_pos
);
//Parameters
parameter NOT_READY = 4'h0;
parameter IDLE = 4'h1;
parameter PM_DENY = 4'h2;
//Registers/Wires
reg [3:0] state;
//Primatives
reg send_sync;
reg send_pmack;
reg send_pmnack;
wire sli_idle;
wire [31:0] sli_tx_dout;
wire sli_tx_isk;
reg write_en;
wire write_idle;
wire [31:0] slw_tx_dout;
wire slw_tx_isk;
reg read_en;
wire read_idle;
wire [31:0] slr_tx_dout;
wire slr_tx_isk;
wire [31:0] ll_tx_dout;
wire ll_tx_isk;
wire last_prim;
//Submodules
//XXX: I can probably use only one CRC checker for the entire stack but to make it easier I'm gonna use two for
//the read and write path
//XXX: maybe add a scrambler for PRIM scrambling
cont_controller ccon (
.rst (rst ),
.clk (clk ),
.phy_ready (phy_ready ),
.xmit_cont_en (prim_scrambler_en ),
.last_prim (last_prim ),
.rx_din (rx_din ),
.rx_isk (rx_isk ),
.ll_tx_din (ll_tx_dout ),
.ll_tx_isk (ll_tx_isk ),
.cont_tx_dout (tx_dout ),
.cont_tx_isk (tx_isk ),
.detect_sync (detect_sync ),
.detect_r_rdy (detect_r_rdy ),
.detect_r_ip (detect_r_ip ),
.detect_r_err (detect_r_err ),
.detect_r_ok (detect_r_ok ),
.detect_x_rdy (detect_x_rdy ),
.detect_sof (detect_sof ),
.detect_eof (detect_eof ),
.detect_wtrm (detect_wtrm ),
.detect_cont (detect_cont ),
.detect_hold (detect_hold ),
.detect_holda (detect_holda ),
.detect_preq_s (detect_preq_s ),
.detect_preq_p (detect_preq_p ),
.detect_align (detect_align ),
.detect_xrdy_xrdy (detect_xrdy_xrdy )
);
sata_link_layer_write slw (
.rst (rst ),
.clk (clk ),
.en (write_en ),
.idle (write_idle ),
.phy_ready (phy_ready ),
.write_ready (write_ready ),
.send_sync_escape (sync_escape ),
.detect_x_rdy (detect_x_rdy ),
.detect_r_rdy (detect_r_rdy ),
.detect_r_ip (detect_r_ip ),
.detect_r_err (detect_r_err ),
.detect_r_ok (detect_r_ok ),
.detect_cont (detect_cont ),
.detect_hold (detect_hold ),
.detect_holda (detect_holda ),
.detect_sync (detect_sync ),
.detect_align (detect_align ),
.send_holda (dbg_send_holda ),
.write_start (write_start ),
.write_strobe (write_strobe ),
.write_data (write_data ),
.write_size (write_size ),
.write_hold (write_hold ),
.write_finished (write_finished ),
.write_abort (write_abort ),
.last_prim (last_prim ),
.send_crc (send_crc ),
.post_align_write (post_align_write ),
.tx_dout (slw_tx_dout ),
.tx_isk (slw_tx_isk ),
.rx_din (rx_din ),
.rx_isk (rx_isk ),
.xmit_error (xmit_error ),
.wsize_z_error (wsize_z_error ),
.data_scrambler_en (data_scrambler_en ),
.is_device (is_device ),
.state (lax_w_state ),
.fstate (lax_w_fstate ),
.in_data_addra (in_data_addra ),
.write_count (write_count ),
.d_count (d_count ),
.buffer_pos (buffer_pos )
);
sata_link_layer_read slr (
.rst (rst ),
.clk (clk ),
.en (read_en ),
.idle (read_idle ),
.sync_escape (sync_escape ),
.phy_ready (phy_ready ),
.dbg_hold (hold ),
.detect_align (detect_align ),
.detect_sync (detect_sync ),
.detect_x_rdy (detect_x_rdy ),
.detect_sof (detect_sof ),
.detect_eof (detect_eof ),
.detect_wtrm (detect_wtrm ),
.detect_cont (detect_cont ),
.detect_holda (detect_holda ),
.detect_hold (detect_hold ),
.detect_xrdy_xrdy (detect_xrdy_xrdy ),
.tx_dout (slr_tx_dout ),
.tx_isk (slr_tx_isk ),
.rx_din (rx_din ),
.rx_isk (rx_isk ),
.read_ready (read_ready ),
.read_strobe (read_strobe ),
.read_data (read_data ),
.read_start (read_start ),
.read_finished (read_finished ),
.remote_abort (remote_abort ),
.crc_ok (read_crc_ok ),
.data_scrambler_en (data_scrambler_en ),
.is_device (is_device ),
.lax_r_state (lax_r_state )
);
//Asynchronous logic
assign ll_tx_dout = (!read_idle) ? slr_tx_dout : (!write_idle) ? slw_tx_dout : sli_tx_dout;
assign ll_tx_isk = (!read_idle) ? slr_tx_isk : (!write_idle) ? slw_tx_isk : sli_tx_isk;
assign sli_tx_dout = (send_pmnack) ? `PRIM_PMNACK :
(send_pmack) ? `PRIM_PMACK :
`PRIM_SYNC;
assign sli_tx_isk = 1;
assign link_layer_ready = (state == IDLE) && read_idle && write_idle;
assign lax_i_state = state;
//Main State Machine
always @ (posedge clk) begin
if (rst) begin
state <= NOT_READY;
send_pmnack <= 0;
send_pmack <= 0;
write_en <= 0;
read_en <= 0;
end
else begin
//Strobes
send_pmnack <= 0;
send_pmack <= 0;
write_en <= 0;
read_en <= 0;
if (!platform_ready) begin
state <= NOT_READY;
end
if (phy_ready) begin
case (state)
NOT_READY: begin
if (platform_ready) begin
state <= IDLE;
end
end
IDLE: begin
write_en <= 1;
read_en <= 1;
if (detect_preq_s || detect_preq_p) begin
send_pmnack <= 1;
state <= PM_DENY;
end
end
PM_DENY: begin
if (detect_preq_s || detect_preq_p) begin
send_pmnack <= 1;
end
else begin
state <= IDLE;
end
end
default: begin
state <= NOT_READY;
end
endcase
end
end
end
endmodule
|
(*
Copyright 2014 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Website: http://nuprl.org/html/verification/
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export Coq.Lists.List.
Export List.ListNotations.
Require Export Coq.Program.Tactics.
(*Require Import SfLib.*)
Require Import String. Open Scope string_scope.
Require Import Omega.
Require Export eq_rel.
(** Taken from SfLib *)
Ltac move_to_top x :=
match reverse goal with
| H : _ |- _ => try move x after H
end.
Tactic Notation "assert_eq" ident(x) constr(v) :=
let H := fresh in
assert (x = v) as H by reflexivity;
clear H.
Tactic Notation "Case_aux" ident(x) constr(name) :=
first [
set (x := name); move_to_top x
| assert_eq x name; move_to_top x
| fail 1 "because we are working on a different case" ].
Tactic Notation "Case" constr(name) := Case_aux Case name.
Tactic Notation "SCase" constr(name) := Case_aux SCase name.
Tactic Notation "SSCase" constr(name) := Case_aux SSCase name.
Tactic Notation "SSSCase" constr(name) := Case_aux SSSCase name.
Tactic Notation "SSSSCase" constr(name) := Case_aux SSSSCase name.
Tactic Notation "SSSSSCase" constr(name) := Case_aux SSSSSCase name.
Tactic Notation "SSSSSSCase" constr(name) := Case_aux SSSSSSCase name.
Tactic Notation "SSSSSSSCase" constr(name) := Case_aux SSSSSSSCase name.
Ltac repd :=
repeat match goal with
| [ H : _ /\ _ |- _ ] => destruct H
| [ H : prod _ _ |- _ ] => destruct H
end.
Ltac exrepd :=
repeat match goal with
| [ H : _ /\ _ |- _ ] => destruct H
| [ H : prod _ _ |- _ ] => destruct H
| [ H : exists v : _,_ |- _ ] =>
let name := fresh v in
destruct H as [name]
| [ H : { v : _ | _ } |- _ ] =>
let name := fresh v in
destruct H as [name]
| [ H : { v : _ & _ } |- _ ] =>
let name := fresh v in
destruct H as [name]
| [ H : { v : _ | _ & _ } |- _ ] =>
let name := fresh v in
destruct H as [name]
end.
Ltac repnd :=
repeat match goal with
| [ H : _ /\ _ |- _ ] =>
let name := fresh H in destruct H as [name H]
| [ H : prod _ _ |- _ ] =>
let name := fresh H in destruct H as [name H]
end.
Ltac repdors :=
repeat match goal with
| [ H : _ \/ _ |- _ ] =>
let name := fresh H in destruct H as [name | H]
| [ H : sum _ _ |- _ ] =>
let name := fresh H in destruct H as [name | H]
end.
(*
Notation "'texists' x , p" := (sigT (fun x => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'texists' x : t , p" := (sigT (fun x:t => p))
(at level 200, x ident, right associativity,
format "'[' 'texists' '/ ' x : t , '/ ' p ']'")
: type_scope.
Notation "'texists('x : t ')' , p" := (sigT (fun x:t => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'texists ('x : t ')' , p" := (sigT (fun x:t => p))
(at level 200, x ident, right associativity) : type_scope.
*)
Tactic Notation "exintro" constr(c) :=
apply existT with (x:=c).
Tactic Notation "eexintro" :=
econstructor.
(*
Lemma tr1 : texists n, n=1.
Proof. exintro 1. reflexivity.
Restart. eexintro. eauto.
Qed.
*)
Ltac iffalse :=
match goal with
| [ H : False |- _ ] => destruct H
end.
Ltac ifvoid :=
match goal with
| [ H : void |- _ ] => destruct H
end.
Ltac provefalse := assert False; try iffalse.
Ltac provevoid := assert void; try ifvoid.
Tactic Notation "complete" tactic(tac) := tac; fail.
Tactic Notation "cauto" tactic(tac) := tac; auto; fail.
(** tries to prove a 'or' concl *)
Ltac cpltLR :=
complete auto
|| complete (left; auto; cpltLR)
|| complete (right; auto; cpltLR).
Ltac sp_step :=
match goal with
(* true conclusion *)
| [ H : ?P |- ?P ] => exact H
| [ |- True ] => constructor
| [ |- ?x <-> ?x ] => complete (split; auto)
| [ |- ?x <o> ?x ] => complete (split; auto)
| [ |- ?x <o> ?y ] => complete (split; auto)
| [ |- (?x <o> ?y) <o> ((?x -> ?y) ## (?y -> ?x))] => complete (apply tiff_is_prod_implies1)
| [ |- ((?x -> ?y) ## (?y -> ?x)) <o> (?x <o> ?y)] => complete (apply tiff_is_prod_implies2)
| [ H : ?x = ?y |- ?y = ?x ] => symmetry; assumption
| [ H1 : ?x = ?y, H2 : ?x = ?z |- ?y = ?z] => rewrite <- H1; assumption
(* false hypotheses *)
| [ H : False |- _ ] => destruct H
| [ H : not True |- _ ] => destruct H; auto
| [ H : notT True |- _ ] => destruct H; auto
| [ H : void |- _ ] => destruct H
| [ H : true = false |- _ ] => inversion H
| [ H : false = true |- _ ] => inversion H
| [ H : Some _ = None |- _ ] => inversion H
| [ H : None = Some _ |- _ ] => inversion H
| [ H : [] = _ :: _ |- _ ] => inversion H (* 0/1+ *)
| [ H : _ :: _ = [] |- _ ] => inversion H (* 1+/0 *)
| [ H : [_] = _ :: _ :: _ |- _ ] => inversion H (* 1/2+ *)
| [ H : _ :: _ :: _ = [_] |- _ ] => inversion H (* 2+/1 *)
| [ H : [_] = _ :: _ :: _ :: _ |- _ ] => inversion H (* 1/3+ *)
| [ H : _ :: _ :: _ :: _ = [_] |- _ ] => inversion H (* 3+/1 *)
| [ H : [_;_] = _ :: _ :: _ :: _ |- _ ] => inversion H (* 2/3+ *)
| [ H : _ :: _ :: _ :: _ = [_;_] |- _ ] => inversion H (* 3+/2 *)
| [ H : 0 = S _ |- _ ] => inversion H
| [ H : S _ = 0 |- _ ] => inversion H
| [ H : ?n < 0 |- _ ] => inversion H || omega
| [ H : ?x <> ?x |- _ ] => provefalse; apply H; symmetry
| [ H : not (?x = ?x) |- _ ] => provefalse; apply H; symmetry
| [ H : notT (?x = ?x) |- _ ] => provefalse; apply H; symmetry
| [ H1 : not (?x = ?y), H2 : ?y = ?x |- _ ] => provefalse; apply H1; symmetry; assumption
| [ H1 : notT (?x = ?y), H2 : ?y = ?x |- _ ] => provefalse; apply H1; symmetry; assumption
(* some simple reasoning on the conclusion *)
| [ |- _ -> _ ] => intro
| [ |- ~ _ ] => intro
| [ |- not _ ] => intro
| [ |- notT _ ] => intro
| [ |- _ /\ _ ] => constructor (* not always a good thing to do *)
| [ |- prod _ _ ] => constructor (* not always a good thing to do *)
(* some simple reasoning on the hypotheses *)
| [ H1 : context[not _], H2 : _ |- _ ] => apply H1 in H2; iffalse
| [ H1 : context[notT _], H2 : _ |- _ ] => apply H1 in H2; iffalse
| [ H : _ /\ _ |- _ ] => destruct H
| [ H : exists (v : _),_ |- _ ] => let name := fresh v in destruct H as [name]
| [ H1 : ?P -> ?Q, H2 : ?P |- _ ] => specialize (H1 H2)
| [ H1 : ~ ?P, H2 : ?P |- _ ] => specialize (H1 H2)
| [ H1 : (?P [[+]] ?R) -> ?Q, H2 : ?P |- _ ] => specialize (H1 (inl H2))
| [ H1 : (?R [[+]] ?P) -> ?Q, H2 : ?P |- _ ] => specialize (H1 (inr H2))
| [ H : ((?P = ?P) [[+]] _) -> ?Q |- _ ] => specialize (H (inl eq_refl))
| [ H : (_ [[+]] (?P = ?P)) -> ?Q |- _ ] => specialize (H (inr eq_refl))
| [ H : { v : _ | _ } |- _ ] => let name := fresh v in destruct H as [name]
| [ H : { v : _ & _ } |- _ ] => let name := fresh v in destruct H as [name]
| [ H : { v : _ | _ & _ } |- _ ] => let name := fresh v in destruct H as [name]
| [ H : prod _ _ |- _ ] => let name := fresh H in destruct H as [name H]
| [ H : _ \/ _ |- _ ] => destruct H (* not always a good thing to do *)
| [ H : sum _ _ |- _ ] => destruct H (* not always a good thing to do *)
| [ H : sumbool _ _ |- _ ] => destruct H (* not always a good thing to do *)
end.
Ltac sp :=
repeat sp_step;
try assumption;
try reflexivity;
try cpltLR.
Ltac tcsp := try (complete sp).
Ltac allsimpl :=
repeat match goal with
| [ H : _ |- _ ] => progress (simpl in H)
| [ |- _ ] => progress simpl
end.
Ltac simphyps :=
repeat match goal with
| [ H : _ |- _ ] => progress (simpl in H)
end.
Ltac applyall tac :=
repeat match goal with
| [ H : _ |- _] => apply tac in H
end.
Ltac allunfold op :=
repeat match goal with
| [ H : _ |- _ ] => progress (unfold op in H)
| [ |- _ ] => progress (unfold op)
end.
Ltac allfold op :=
repeat match goal with
| [ H : _ |- _ ] => progress (fold op in H)
| [ |- _ ] => progress (fold op)
end.
Ltac allunfolds ops :=
match ops with
| [] => auto
| ?op :: ?ops => (allunfold op; allunfolds ops)
end.
Ltac allrewrite op :=
repeat match goal with
| [ H : _ |- _ ] => progress (rewrite op in H || rewrite op)
end.
Ltac alltrewrite op :=
repeat match goal with
| [ H : _ |- _ ] => progress (trw_h op H || trw op)
end.
Ltac alltrewrite_rev op :=
repeat match goal with
| [ H : _ |- _ ] => progress (trw_rev_h op H || trw_rev op)
end.
Ltac dands :=
repeat match goal with
| [ |- _ /\ _ ] => split
| [ |- prod _ _ ] => split
end.
Ltac thin H := clear H.
Ltac thin_trivials :=
repeat match goal with
| [ H : ?T = ?T |- _ ] => clear H
| [ H : ?T <-> ?T |- _ ] => clear H
| [ H : ?T <o> ?T |- _ ] => clear H
| [ H : ?T -> ?T |- _ ] => clear H
| [ H1 : ?T, H2 : ?T |- _ ] => clear H2
| [ H : True |- _ ] => clear H
| [ H : ~ False |- _ ] => clear H
| [ H : notT False |- _ ] => clear H
end.
Ltac GC := thin_trivials.
Ltac parallel x h :=
match goal with
| [ H : exists _ : ?P, _ |- exists _ : ?P, _] =>
(destruct H as [x h]; exists x)
| [ H : {_ : ?P & _} |- {_ : ?P & _} ] =>
(destruct H as [x h]; exists x)
end.
Ltac pnot H :=
match goal with
| [ H : ~ ?P |- ~ ?Q ] =>
(intro q; apply H)
end.
(*
Ltac lexists l :=
match l with
| nil => try (auto ;fail)
| ?t :: ?ts => (exists t ; lexists ts)
end.
*)
Lemma iff_symm : forall a b, (a <-> b) <-> (b <-> a).
Proof.
repeat (sp; split; sp); destruct H; auto.
Qed.
Lemma prod_sym : forall a b, a ## b -> b ## a.
Proof.
sp.
Qed.
Lemma sum_sym : forall a b, a [[+]] b -> b [[+]] a.
Proof.
sp.
Qed.
Ltac symm :=
match goal with
| [ |- ?a <-> ?b ] => rewrite iff_symm
| [ |- ?a <o> ?b ] => apply t_iff_sym
| [ |- ?a ## ?b ] => apply prod_sym
| [ |- ?a [[+]] ?b ] => apply sum_sym
end.
Tactic Notation "inv_sub_clear" ident (h) :=
inversion h; subst; clear h.
Require Export LibTactics.
Ltac clear_eq x y :=
match goal with
| [ H : x = y |- _ ] => clear H
end.
Tactic Notation "duplicate" ident(H) "as" simple_intropattern(newname) :=
let name := fresh newname
in remember H as name;
clear_eq name H.
Tactic Notation "duplicate" ident(H) :=
let name := fresh H
in remember H as name;
clear_eq name H.
Tactic Notation "applydup" constr(l) "in" ident(H) :=
let newH := fresh H in
remember H as newH; clear_eq newH H; apply l in newH.
Tactic Notation "applydup" constr(l) "in" ident(H) "as" simple_intropattern(newname):=
remember H as newname; clear_eq newname H; apply l in newname.
Tactic Notation "dup" ident(H) "as" simple_intropattern(newname) :=
let T := type of H in
assert T as newname by trivial.
Ltac apply_in_hyp name :=
match goal with
| [ H1 : context[ _ -> _], H2 : _ |- _ ] =>
remember H2 as name;
clear_eq name H2;
apply H1 in name
end.
Ltac apply_hyp :=
match goal with
| [ H : context[ _ -> _] |- _ ] =>
apply H
end.
Ltac use_iff_l :=
match goal with
| [ H : _ <o> _ |- _ ] => apply (tiff_fst H)
end.
Ltac use_iff_r :=
match goal with
| [ H : _ <o> _ |- _ ] => apply (tiff_snd H)
end.
Ltac use_iff_l_in_hyp :=
match goal with
| [ H1 : _ <o> _ , H2 : _ |- _ ] => apply (tiff_fst H1) in H2
end.
Ltac use_iff_r_in_hyp :=
match goal with
| [ H1 : _ <o> _ , H2 : _ |- _ ] => apply (tiff_snd H1) in H2
end.
(*
Ltac duplicateas H newname :=
let name := fresh newname
in remember H as name;
clears_last.
Ltac duplicate H := duplicateas H H.
*)
Ltac exrepnd :=
repeat match goal with
| [ H : _ /\ _ |- _ ] => let name := fresh H in destruct H as [name H]
| [ H : prod _ _ |- _ ] => let name := fresh H in destruct H as [name H]
| [ H : exists (v : _),_ |- _ ] =>
let vname := fresh v in
let hname := fresh H in
destruct H as [vname hname]
| [ H : { v : _ | _ } |- _ ] =>
let vname := fresh v in
let hname := fresh H in
destruct H as [vname hname]
| [ H : { v : _ & _ } |- _ ] =>
let vname := fresh v in
let hname := fresh H in
destruct H as [vname hname]
end.
Tactic Notation "instlemma" constr(l) "as" simple_intropattern(I) :=
remember l as I; clears_last.
Ltac dimp H :=
match type of H with
| ?T1 -> ?T2 =>
let name := fresh "hyp" in
assert T1 as name; auto; try (apply H in name)
end.
Ltac d_imp H :=
match type of H with
| ?T1 -> ?T2 =>
let name := fresh "hyp" in
assert T1 as name;
auto;
try (assert T2 by (complete auto); clear name)
end. (* ; try (apply H in name)*)
Ltac dest_imp H hyp :=
match type of H with
| ?T1 -> ?T2 =>
assert T1 as hyp;
[ clear H; try (complete sp)
| try (let concl := fresh "hyp" in
assert T2 as concl by (complete auto);
clear hyp;
clear H;
rename concl into H)
; try (complete sp)
]
end.
Ltac destimp H hyp :=
match type of H with
| ?T1 -> ?T2 =>
assert T1 as hyp;
[ clear H; try (complete sp)
| try (let concl := fresh "hyp" in
assert T2 as concl by (complete auto);
clear hyp;
clear H;
rename concl into H)
; try (complete auto)
]
end.
Ltac autodimp H hyp :=
match type of H with
| ?T1 -> ?T2 =>
assert T1 as hyp;
[ clear H; try (complete auto)
| try (let concl := fresh "hyp" in
pose proof (H hyp) as concl;
clear hyp;
clear H;
rename concl into H)
; try (complete auto)
]
end.
(*
Ltac autodimp H hyp :=
match type of H with
| ?T1 -> ?T2 =>
assert T1 as hyp;
[ clear H; try (complete auto)
| try (let concl := fresh "hyp" in
assert T2 as concl by (complete auto);
clear hyp;
clear H;
rename concl into H)
; try (complete auto)
]
end.
*)
Tactic Notation "sp_iff" ident(c) :=
split;
[ Case_aux c "->"
| Case_aux c "<-"
].
Tactic Notation "split_iff" ident(c) :=
split;
[ Case_aux c "->"
| Case_aux c "<-"
].
Tactic Notation "split_ciff" ident(c) :=
split; split;
[ Case_aux c "->"
| Case_aux c "<-"
].
Tactic Notation "op_cases" ident(H) ident(c) :=
destruct H;
[ Case_aux c "some"
| Case_aux c "none"
].
Ltac allapply op :=
repeat match goal with
| [ H : _ |- _ ] => progress (apply op in H )
end.
Ltac allapplysym op :=
repeat match goal with
| [ H : _ |- _ ] => progress
(apply op in H || symmetry in H;
apply op in H)
end.
Tactic Notation "apply_clear" ident(L) "in" ident(H) :=
apply L in H; clear L.
Tactic Notation "apply_clear" ident(L) :=
apply L; clear L.
Tactic Notation "applydup_clear" ident(L) "in" ident(H) :=
let newH := fresh H in remember H as newH; clears_last;
apply L in newH; clear L.
Tactic Notation "repnud" ident(H) :=
unfolds_in_base H; repnd.
Tactic Notation "exrepnud" ident(H) :=
unfolds_in_base H; exrepnd.
Tactic Notation "invertsn" ident(H):=
inverts H as H.
Tactic Notation "spauto":=
repeat (auto;split;auto).
Ltac rewrite_term t i :=
match goal with
[ H : t = _ |- _ ] => rewrite H in i
| [ H : _ = t |- _ ] => rewrite <- H in i
end.
Ltac rterm t :=
match goal with
[ H : t = _ |- _ ] => rewrite H
| [ H : _ = t |- _ ] => rewrite <- H
end.
Tactic Notation "dorn" ident(H):= destruct H as [H | H].
Tactic Notation "destructr" constr(ob) "as" simple_intropattern(names) :=
let eqname:= fresh "Hdeq" in
remember ob as eqname; destruct eqname as names.
Tactic Notation "ddestructr" constr(ob) "as" simple_intropattern(names) :=
let eqname:= fresh "Hdeq" in
remember ob as eqname; destruct eqname as names.
Tactic Notation "destructrn" constr(ob) "as" simple_intropattern(names) simple_intropattern(eq):=
remember ob as eq; destruct eq as names.
Ltac intron name :=
let newn:= fresh name in
introv newn.
(**intro with names like name1 name2 name3 ....*)
Ltac introns name :=
repeat(
let newn:= fresh name in
introv newn).
Ltac invertsna hyp names :=
inverts hyp as; introns names.
Ltac revert_all :=
repeat(
let H:= get_last_hyp tt in
revert H).
Ltac fail_if_not_number n :=
match n with
| S ?m => fail_if_not_number m
| 0 => idtac
end.
Tactic Notation "applysym" constr(L) "in" ident(H):=
( (apply L in H) || (symmetry in H;apply L in H)).
Ltac try_sym H T:=
( (T) || (symmetry in H;T)).
Ltac rewrite_once op :=
match goal with
| [ H : _ |- _ ] => (rewrite op in H || rewrite op)
end.
Ltac dpair_eq :=
match goal with
| [ H : (_,_)=(_,_) |- _ ] =>
let Hl := fresh H "l" in
let Hr := fresh H "r" in
inverts H as Hl Hr
end.
Tactic Notation "spc" := sp; try (congruence).
Ltac rename_last Hn :=
let H := get_last_hyp tt in
rename H into Hn.
Ltac cases_ifn Hn :=
cases_if; clears_last; rename_last Hn.
Lemma hide_hyp :
forall (P : Type),
P <o> (P ## True).
Proof. split; sp.
Qed.
Ltac cases_ifd Hn :=
match goal with
[ |- context[if ?d then ?tt else ?ff] ]
=> let Hnt := fresh Hn "t" in
let Hnf := fresh Hn "f" in
destruct d as [Hnt | Hnf] end.
Ltac apply_eq f H Hn :=
match goal with
[ H: (?l = ?r) |- _] => assert (f l = f r) as Hn by (f_equal;sp)
end.
Ltac clear_all :=
repeat match goal with
| [ H : _ |- _ ] => clear H
end.
Ltac clear_ors :=
repeat match goal with
| [ H : _ [[+]] _ |- _ ] => clear H
end.
Ltac gen_some x :=
match goal with
| [ H : forall v : _, _ |- _ ] => generalize (H x); intro
end.
Ltac no_duplicate h :=
let T := type of h in
match goal with
| [ H1 : T, H2 : T |- _ ] => fail 1
| _ => idtac
end.
Ltac discover_step :=
match goal with
| [ H : context[?a <o> ?b] |- _ ] =>
first [ assert a as name by (complete sp);
rw H in name;
no_duplicate name
| assert b as name by (complete sp);
rw <- H in name;
no_duplicate name
]
| [ H : context[?a -> _] |- _ ] =>
let name := fresh "h" in
assert a as name by (complete sp);
apply H in name;
no_duplicate name
| [ H : context[_ -> _], H2 : ?c |- _ ] =>
let name := fresh "h" in
assert c as name by auto;
apply H in name;
no_duplicate name
| [ H : context[_ <o> _], H2 : ?c |- _ ] =>
let name := fresh "h" in
assert c as name by auto;
rw H in name;
no_duplicate name
| [ H : context[_ <o> _], H2 : ?c |- _ ] =>
let name := fresh "h" in
assert c as name by auto;
rw <- H in name;
no_duplicate name
end.
Ltac discover := repeat discover_step.
Ltac allapplydup op :=
repeat match goal with
| [ H : ?T |- _ ] =>
let h := fresh "h" in
assert T as h by auto;
apply op in h;
no_duplicate h
end.
Ltac invs :=
match goal with
| [ H : _ :: _ = _ :: _ |- _ ] => inversion H; subst; GC
end.
Tactic Notation "apph" tactic(tac) :=
match goal with
| [ H : context[ _ -> _] |- _ ] => apply H; tac
end.
Ltac make_and H1 H2 :=
let Ha := fresh H1 H2 in
pose proof (H1, H2) as Ha; clear H1; clear H2.
(** From Adam's LibTactics.v ... ,move to tactics.v*)
Definition ltac_something (P:Type) (e:P) := e.
Notation "'Something'" :=
(@ltac_something _ _).
Lemma ltac_something_eq : forall (e:Type),
e = (@ltac_something _ e).
Proof. auto. Qed.
Lemma ltac_something_hide : forall (e:Type),
e -> (@ltac_something _ e).
Proof. auto. Qed.
Lemma ltac_something_show : forall (e:Type),
(@ltac_something _ e) -> e.
Proof. auto. Qed.
Ltac show_hyp H :=
apply ltac_something_show in H.
Ltac hide_hyp H :=
apply ltac_something_hide in H.
Ltac show_hyps :=
repeat match goal with
H: @ltac_something _ _ |- _ => show_hyp H end.
Ltac dlt Hyp :=
match type of Hyp with
| 0 < _ => fail 1
| S _ < S _ => apply lt_S_n in Hyp
| ?n < S _ => destruct n
end.
Ltac GClte :=
match goal with
[ H : ?n < ?m |- _ ] => fail_if_not_number n; fail_if_not_number m; clear H
|[ H : ?n <= ?m |- _ ] => fail_if_not_number n; fail_if_not_number m; clear H
end.
Ltac clear_dependents x :=
repeat match goal with
[ H : context[x] |- _ ] => clear H
end.
Ltac revert_dependents x :=
repeat match goal with
[ H : context[x] |- _ ] => revert H
end;
revert x.
Ltac dtiffs2 := repeat match goal with
[ H: forall _ : ?X, _ <o> _ |- _] =>
let Hl:= fresh H "tl" in
let Hr:= fresh H "tr" in
pose proof (fun x:X => tiff_fst (H x)) as Hl;
pose proof (fun x:X => tiff_snd (H x)) as Hr; hide_hyp H
| [ H: forall (_ : ?X) (_ : ?Y), _ <o> _ |- _] =>
let Hl:= fresh H "tl" in
let Hr:= fresh H "tr" in
pose proof (fun x:X => (fun y:Y => tiff_fst (H x y))) as Hl;
pose proof (fun x:X => (fun y:Y => tiff_snd (H x y))) as Hr; hide_hyp H
end; show_hyps.
Ltac prove_iff h :=
let T := type of h in
match goal with
| [ |- ?c ] =>
let e := fresh "e" in
assert (T <o> c) as e; try (complete (rw <- e; auto))
end.
Ltac rep_eexists :=
repeat match goal with
[ |- sigT _ ] => eexists
end.
Ltac move_term_to_top t :=
match reverse goal with
| H1 : t, H2 : _ |- _ =>
let h := fresh "h" in
rename H1 into h;
assert t as H1 by trivial;
clear h
end.
Ltac dsum_step :=
match goal with
| [ |- context[if ?x then _ else _] ] =>
match type of x with
| {_} + {_} => destruct x
end
| [ |- context[if ?x then _ else _] ] =>
match type of x with
| sum _ _ => destruct x
end
| [ |- context[if ?x then _ else _] ] =>
match type of x with
| decidable _ => destruct x
end
| [ |- context[d2b ?x] ] =>
match type of x with
| decidable _ => destruct x
end
| [H : context[if ?x then _ else _] |- _ ] =>
match type of x with
| {_} + {_} => destruct x
end
| [H : context[if ?x then _ else _] |- _ ] =>
match type of x with
| sum _ _ => destruct x
end
| [H : context[if ?x then _ else _] |- _ ] =>
match type of x with
| decidable _ => destruct x
end
| [H : context[d2b ?x] |- _ ] =>
match type of x with
| decidable _ => destruct x
end
end.
Ltac dsum := repeat dsum_step.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_SYMBOL_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_SYMBOL_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sleep_sergate_plv (
//# {{power|Power}}
input SLEEP ,
output VIRTPWR
);
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam NO = 7; // number of access events
// packed structures
struct packed {
logic e0;
logic [1:0] e1;
logic [3:0] e2;
logic [7:0] e3;
} struct_bg; // big endian structure
/* verilator lint_off LITENDIAN */
struct packed {
logic e0;
logic [0:1] e1;
logic [0:3] e2;
logic [0:7] e3;
} struct_lt; // little endian structure
/* verilator lint_on LITENDIAN */
localparam WS = 15; // $bits(struct_bg)
integer cnt = 0;
// event counter
always @ (posedge clk)
begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'bx)
if (cnt[30:2]==0) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==1) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==2) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==3) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==4) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==5) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==6) struct_bg <= {WS{1'bx}};
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_bg <= '{0 ,1 , 2, 3};
else if (cnt[30:2]==2) struct_bg <= '{e0:1, e1:2, e2:3, e3:4};
else if (cnt[30:2]==3) struct_bg <= '{e3:6, e2:4, e1:2, e0:0};
else if (cnt[30:2]==4) struct_bg <= '{default:13};
else if (cnt[30:2]==5) struct_bg <= '{e2:8'haa, default:1};
else if (cnt[30:2]==6) struct_bg <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]==0) begin if (struct_bg !== 15'bx_xx_xxxx_xxxxxxxx) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_bg !== 15'b0_01_0010_00000011) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_bg !== 15'b1_10_0011_00000100) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_bg !== 15'b0_10_0100_00000110) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_bg !== 15'b1_01_1101_00001101) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_bg !== 15'b1_01_1010_00000001) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==6) begin if (struct_bg !== 15'b1_10_1011_00011100) begin $display("%b", struct_bg); $stop(); end end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'bx)
if (cnt[30:2]==0) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==1) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==2) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==3) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==4) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==5) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==6) struct_lt <= {WS{1'bx}};
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_lt <= '{0 ,1 , 2, 3};
else if (cnt[30:2]==2) struct_lt <= '{e0:1, e1:2, e2:3, e3:4};
else if (cnt[30:2]==3) struct_lt <= '{e3:6, e2:4, e1:2, e0:0};
else if (cnt[30:2]==4) struct_lt <= '{default:13};
else if (cnt[30:2]==5) struct_lt <= '{e2:8'haa, default:1};
else if (cnt[30:2]==6) struct_lt <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]==0) begin if (struct_lt !== 15'bx_xx_xxxx_xxxxxxxx) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_lt !== 15'b0_01_0010_00000011) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_lt !== 15'b1_10_0011_00000100) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_lt !== 15'b0_10_0100_00000110) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_lt !== 15'b1_01_1101_00001101) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_lt !== 15'b1_01_1010_00000001) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==6) begin if (struct_lt !== 15'b1_10_1011_00011100) begin $display("%b", struct_lt); $stop(); end end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_dft_jtag_tap.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "ctu.h"
module ctu_dft_jtag_tap(/*AUTOARG*/
// Outputs
instructions, next_instructions, capture_dr_state, shift_dr_state,
pause_dr_state, update_dr_state, shift_exit2_dr_state,
update_ir_state, clock_dr, tdo, tdo_en,
// Inputs
tck, tck_l, trst_n, tms, tdi, so, bypass_sel, dft_pin_pscan
);
input tck;
input tck_l;
input trst_n;
input tms;
input tdi;
input so;
input bypass_sel;
input dft_pin_pscan;
output [`TAP_INSTR_WIDTH-1:0] instructions;
output [`TAP_INSTR_WIDTH-1:0] next_instructions;
output capture_dr_state;
output shift_dr_state;
output pause_dr_state;
output update_dr_state;
output shift_exit2_dr_state;
output update_ir_state;
output clock_dr;
output tdo;
output tdo_en;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [`TAP_INSTR_WIDTH-1:0] instructions;
reg [`TAP_INSTR_WIDTH-1:0] next_instructions;
wire capture_dr_state;
wire shift_dr_state;
wire pause_dr_state;
wire update_dr_state;
wire shift_exit2_dr_state;
wire update_ir_state;
wire clock_dr;
wire tdo;
wire tdo_en;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
parameter TAP_RESET = 16'h0001,
TAP_TEST = 16'h0002,
TAP_SEL_DR = 16'h0004,
TAP_CAP_DR = 16'h0008,
TAP_SHIFT_DR = 16'h0010,
TAP_EXIT1_DR = 16'h0020,
TAP_PAUSE_DR = 16'h0040,
TAP_EXIT2_DR = 16'h0080,
TAP_UPDATE_DR = 16'h0100,
TAP_SEL_IR = 16'h0200,
TAP_CAP_IR = 16'h0400,
TAP_SHIFT_IR = 16'h0800,
TAP_EXIT1_IR = 16'h1000,
TAP_PAUSE_IR = 16'h2000,
TAP_EXIT2_IR = 16'h4000,
TAP_UPDATE_IR = 16'h8000,
TAP_STATE_WIDTH = 16;
parameter TAP_RESET_BIT = 0,
// TAP_TEST_BIT = 1,
// TAP_SEL_DR_BIT = 2,
TAP_CAP_DR_BIT = 3,
TAP_SHIFT_DR_BIT = 4,
// TAP_EXIT1_DR_BIT = 5,
TAP_PAUSE_DR_BIT = 6,
TAP_EXIT2_DR_BIT = 7,
TAP_UPDATE_DR_BIT = 8,
// TAP_SEL_IR_BIT = 9,
TAP_CAP_IR_BIT = 10,
TAP_SHIFT_IR_BIT = 11,
// TAP_EXIT1_IR_BIT = 12,
// TAP_PAUSE_IR_BIT = 13,
// TAP_EXIT2_IR_BIT = 14,
TAP_UPDATE_IR_BIT = 15;
wire [15:0] tap_state;
reg [15:0] next_tap_state;
wire tap_state_reset_negedge;
wire capture_shift_dr;
wire next_tap_state_reset_negedge;
wire next_capture_shift_dr;
reg next_tdo;
wire next_tdo_en;
wire [`TAP_INSTR_WIDTH-1:0] new_instructions;
reg [`TAP_INSTR_WIDTH-1:0] next_new_instructions;
wire reset_muxed;
wire instructions_rst_l;
wire tdi_ff;
wire tdi_ff_en;
wire tdi_ff_rst_l;
//*******************************************************************************
// Tap State Machine
//*******************************************************************************
always @ ( /*AUTOSENSE*/tap_state or tms) begin
case (tap_state)
TAP_RESET: begin
if (tms)
next_tap_state = TAP_RESET;
else
next_tap_state = TAP_TEST;
end
TAP_TEST: begin
if (tms)
next_tap_state = TAP_SEL_DR;
else
next_tap_state = TAP_TEST;
end
TAP_SEL_DR: begin
if (tms)
next_tap_state = TAP_SEL_IR;
else
next_tap_state = TAP_CAP_DR;
end
TAP_CAP_DR: begin
if (tms)
next_tap_state = TAP_EXIT1_DR;
else
next_tap_state = TAP_SHIFT_DR;
end
TAP_SHIFT_DR: begin
if (tms)
next_tap_state = TAP_EXIT1_DR;
else
next_tap_state = TAP_SHIFT_DR;
end
TAP_EXIT1_DR: begin
if (tms)
next_tap_state = TAP_UPDATE_DR;
else
next_tap_state = TAP_PAUSE_DR;
end
TAP_PAUSE_DR: begin
if (tms)
next_tap_state = TAP_EXIT2_DR;
else
next_tap_state = TAP_PAUSE_DR;
end
TAP_EXIT2_DR: begin
if (tms)
next_tap_state = TAP_UPDATE_DR;
else
next_tap_state = TAP_SHIFT_DR;
end
TAP_UPDATE_DR: begin
if (tms)
next_tap_state = TAP_SEL_DR;
else
next_tap_state = TAP_TEST;
end
TAP_SEL_IR: begin
if (tms)
next_tap_state = TAP_RESET;
else
next_tap_state = TAP_CAP_IR;
end
TAP_CAP_IR: begin
if (tms)
next_tap_state = TAP_EXIT1_IR;
else
next_tap_state = TAP_SHIFT_IR;
end
TAP_SHIFT_IR: begin
if (tms)
next_tap_state = TAP_EXIT1_IR;
else
next_tap_state = TAP_SHIFT_IR;
end
TAP_EXIT1_IR: begin
if (tms)
next_tap_state = TAP_UPDATE_IR;
else
next_tap_state = TAP_PAUSE_IR;
end
TAP_PAUSE_IR: begin
if (tms)
next_tap_state = TAP_EXIT2_IR;
else
next_tap_state = TAP_PAUSE_IR;
end
TAP_EXIT2_IR: begin
if (tms)
next_tap_state = TAP_UPDATE_IR;
else
next_tap_state = TAP_SHIFT_IR;
end
TAP_UPDATE_IR: begin
if (tms)
next_tap_state = TAP_SEL_DR;
else
next_tap_state = TAP_TEST;
end
// CoverMeter line_off
default: next_tap_state = {TAP_STATE_WIDTH{1'bx}};
// CoverMeter line_on
endcase
end
// Tap state
assign capture_dr_state = tap_state[TAP_CAP_DR_BIT];
assign shift_dr_state = tap_state[TAP_SHIFT_DR_BIT];
assign pause_dr_state = tap_state[TAP_PAUSE_DR_BIT];
assign update_dr_state = tap_state[TAP_UPDATE_DR_BIT];
assign update_ir_state = tap_state[TAP_UPDATE_IR_BIT];
assign shift_exit2_dr_state = tap_state[TAP_SHIFT_DR_BIT] | tap_state[TAP_EXIT2_DR_BIT];
//*******************************************************************************
// Instruction Register
//*******************************************************************************
always @ ( /*AUTOSENSE*/new_instructions or tap_state or tdi) begin
if (tap_state[TAP_CAP_IR_BIT]) //load
next_new_instructions = { {`TAP_INSTR_WIDTH-1{1'b0}}, 1'b1 };
else begin
if (tap_state[TAP_SHIFT_IR_BIT]) //shift
next_new_instructions = { tdi, new_instructions[`TAP_INSTR_WIDTH-1:1] };
else
next_new_instructions = new_instructions;
end
end
always @ ( /*AUTOSENSE*/instructions or new_instructions or tap_state) begin
if (tap_state[TAP_UPDATE_IR_BIT])
next_instructions = new_instructions;
else
next_instructions = instructions;
end
// - instruction register must have default instruction (idcode) when tap is in reset state
// - if in pin-based pscan, do not reset instruction register on tap state because
// tap sm is on scan chain
assign next_tap_state_reset_negedge = tap_state[TAP_RESET_BIT];
assign reset_muxed = dft_pin_pscan ? 1'b0 : tap_state_reset_negedge;
assign instructions_rst_l = ~reset_muxed & trst_n;
//*******************************************************************************
// TDO
//*******************************************************************************
assign tdi_ff_en = tap_state[TAP_SHIFT_DR_BIT];
assign tdi_ff_rst_l = ~(bypass_sel & tap_state[TAP_CAP_DR_BIT]);
// Negedge
assign next_tdo_en = tap_state[TAP_SHIFT_IR_BIT] | tap_state[TAP_SHIFT_DR_BIT];
always @ ( /*AUTOSENSE*/bypass_sel or new_instructions or so
or tap_state or tdi_ff) begin
if (tap_state[TAP_SHIFT_IR_BIT])
next_tdo = new_instructions[0];
else if (bypass_sel)
next_tdo = tdi_ff;
else
next_tdo = so;
end
//*******************************************************************************
// *_dr
//*******************************************************************************
// clock_dr == 0 when idle
assign next_capture_shift_dr = tap_state[TAP_SHIFT_DR_BIT] | tap_state[TAP_CAP_DR_BIT];
//assign clock_dr = tck & capture_shift_dr;
ctu_and2 u_and2_clock_dr
(
.z(clock_dr),
.a(tck),
.b(capture_shift_dr)
);
//*******************************************************************************
// DFF Instantiations
//*******************************************************************************
//--------------------
// NEGEDGE
//--------------------
dff_ns #(1) u_dffsl_tap_state_reset_negedge
( .din (next_tap_state_reset_negedge),
.clk (tck_l),
.q (tap_state_reset_negedge)
);
//*******************************************************************************
// Async Reset and Set DFFRL/DFFSL Instantiations
//*******************************************************************************
//--------------------
// POSEDGE
//--------------------
dffsl_async_ns #(1) u_dffsl_tap_state0
( .din (next_tap_state[0]),
.clk (tck),
.set_l (trst_n),
.q (tap_state[0])
);
dffrl_async_ns #(TAP_STATE_WIDTH-1) u_dffrl_async_tap_state
( .din (next_tap_state[TAP_STATE_WIDTH-1:1]),
.clk (tck),
.rst_l (trst_n),
.q (tap_state[TAP_STATE_WIDTH-1:1])
);
// DEFAULT TO IDCODE
dffsl_async_ns #(1) u_dffsl_new_instructions0
( .din (next_new_instructions[0]),
.clk (tck),
.set_l (trst_n),
.q (new_instructions[0])
);
dffrl_async_ns #(`TAP_INSTR_WIDTH-1) u_dffrl_async_new_instructions
( .din (next_new_instructions[`TAP_INSTR_WIDTH-1:1]),
.clk (tck),
.rst_l (trst_n),
.q (new_instructions[`TAP_INSTR_WIDTH-1:1])
);
//--------------------
// NEGEDGE
//--------------------
// DEFAULT TO IDCODE
dffsl_async_ns #(1) u_dffsl_instructions0
( .din (next_instructions[0]),
.clk (tck_l),
.set_l (instructions_rst_l),
.q (instructions[0])
);
dffrl_async_ns #(`TAP_INSTR_WIDTH-1) u_dffrl_async_instructions
( .din (next_instructions[`TAP_INSTR_WIDTH-1:1]),
.clk (tck_l),
.rst_l (instructions_rst_l),
.q (instructions[`TAP_INSTR_WIDTH-1:1])
);
dffrl_async_ns #(1) u_dffrl_async_capture_shift_dr
( .din (next_capture_shift_dr),
.clk (tck_l),
.rst_l (trst_n),
.q (capture_shift_dr)
);
dffrl_async_ns #(1) u_dffrl_async_tdo
( .din (next_tdo),
.clk (tck_l),
.rst_l (trst_n),
.q (tdo)
);
dffrl_async_ns #(1) u_dffrl_async_tdo_en
( .din (next_tdo_en),
.clk (tck_l),
.rst_l (trst_n),
.q (tdo_en)
);
//*******************************************************************************
// DFFRLE Instantiations
//*******************************************************************************
//--------------------
// POSEDGE
//--------------------
dffrle_ns #(1) u_dffrle_tdi_ff
( .din (tdi),
.clk (tck),
.en (tdi_ff_en),
.rst_l (tdi_ff_rst_l),
.q (tdi_ff)
);
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-files:("../../../common/rtl/swrvr_macro.v")
// verilog-auto-sense-defines-constant:t
// End:
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:04:55 07/15/2014
// Design Name: cic_decim
// Module Name: U:/GitHubA2300_ltxdev/hdl/test/cic_decim_stimulus.v
// Project Name: Asr2300FpgaCore_2chrx
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cic_decim
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cic_decim_stimulus;
parameter DSPCLK_PERIOD = 1000.0/128.0; //128 MHz
// Inputs
reg sclr;
wire nd;
reg reset;
reg dspclk;
reg rate_we;
reg [11:0] din;
reg [12:0] rate;
// Outputs
wire rfd;
wire rdy;
wire [15:0] dout;
//create 32 MHz strobed
reg [1:0] strobe_nd;
always @(posedge dspclk)
begin
if(reset) strobe_nd <= 4'h0;
else strobe_nd <= strobe_nd + 4'h1;
end
assign nd = strobe_nd == 0;
// Instantiate the Unit Under Test (UUT)
cic_decim uut (
.sclr(sclr | reset),
.rfd(rfd),
.rdy(rdy),
.nd(nd),
.clk(dspclk),
.rate_we(rate_we),
.dout(dout),
.din(din),
.rate(rate)
);
initial begin
// Initialize Inputs
sclr = 0;
dspclk = 1;
rate_we = 0;
din = 12'h010;
rate = 12'h4;
// Wait 100 ns for global reset to finish
#100 reset = 1;
#(DSPCLK_PERIOD*4)reset = 0;
#(DSPCLK_PERIOD) rate_we = 1;
#(DSPCLK_PERIOD) rate_we = 0;
#(DSPCLK_PERIOD*120) sclr = 1;
#(DSPCLK_PERIOD) sclr = 0;
#(DSPCLK_PERIOD*64) rate_we = 1;
#(DSPCLK_PERIOD) rate_we = 0;
// Add stimulus here
#(DSPCLK_PERIOD*75) rate_we = 1;
#(DSPCLK_PERIOD) rate_we = 0;
end
//////////////////////////////////////////////////////////////////////
// Clocks
//////////////////////////////////////////////////////////////////////
always @(dspclk)
#(DSPCLK_PERIOD / 2.0) dspclk<= !dspclk;
endmodule
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Nov 14 15:54:43 EST 2016
//
// Method conflict info:
// Method: output_arbs_0_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_0_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_1_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_1_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_2_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_2_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_3_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_3_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_4_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_4_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
//
// Ports:
// Name I/O size props
// output_arbs_0_select O 5
// output_arbs_1_select O 5
// output_arbs_2_select O 5
// output_arbs_3_select O 5
// output_arbs_4_select O 5
// CLK I 1 unused
// RST_N I 1 unused
// output_arbs_0_select_requests I 5
// output_arbs_1_select_requests I 5
// output_arbs_2_select_requests I 5
// output_arbs_3_select_requests I 5
// output_arbs_4_select_requests I 5
// EN_output_arbs_0_next I 1 unused
// EN_output_arbs_1_next I 1 unused
// EN_output_arbs_2_next I 1 unused
// EN_output_arbs_3_next I 1 unused
// EN_output_arbs_4_next I 1 unused
//
// Combinational paths from inputs to outputs:
// output_arbs_0_select_requests -> output_arbs_0_select
// output_arbs_1_select_requests -> output_arbs_1_select
// output_arbs_2_select_requests -> output_arbs_2_select
// output_arbs_3_select_requests -> output_arbs_3_select
// output_arbs_4_select_requests -> output_arbs_4_select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkRouterOutputArbitersStatic(CLK,
RST_N,
output_arbs_0_select_requests,
output_arbs_0_select,
EN_output_arbs_0_next,
output_arbs_1_select_requests,
output_arbs_1_select,
EN_output_arbs_1_next,
output_arbs_2_select_requests,
output_arbs_2_select,
EN_output_arbs_2_next,
output_arbs_3_select_requests,
output_arbs_3_select,
EN_output_arbs_3_next,
output_arbs_4_select_requests,
output_arbs_4_select,
EN_output_arbs_4_next);
input CLK;
input RST_N;
// value method output_arbs_0_select
input [4 : 0] output_arbs_0_select_requests;
output [4 : 0] output_arbs_0_select;
// action method output_arbs_0_next
input EN_output_arbs_0_next;
// value method output_arbs_1_select
input [4 : 0] output_arbs_1_select_requests;
output [4 : 0] output_arbs_1_select;
// action method output_arbs_1_next
input EN_output_arbs_1_next;
// value method output_arbs_2_select
input [4 : 0] output_arbs_2_select_requests;
output [4 : 0] output_arbs_2_select;
// action method output_arbs_2_next
input EN_output_arbs_2_next;
// value method output_arbs_3_select
input [4 : 0] output_arbs_3_select_requests;
output [4 : 0] output_arbs_3_select;
// action method output_arbs_3_next
input EN_output_arbs_3_next;
// value method output_arbs_4_select
input [4 : 0] output_arbs_4_select_requests;
output [4 : 0] output_arbs_4_select;
// action method output_arbs_4_next
input EN_output_arbs_4_next;
// signals for module outputs
wire [4 : 0] output_arbs_0_select,
output_arbs_1_select,
output_arbs_2_select,
output_arbs_3_select,
output_arbs_4_select;
// value method output_arbs_0_select
assign output_arbs_0_select =
{ output_arbs_0_select_requests[4],
!output_arbs_0_select_requests[4] &&
output_arbs_0_select_requests[3],
!output_arbs_0_select_requests[4] &&
!output_arbs_0_select_requests[3] &&
output_arbs_0_select_requests[2],
!output_arbs_0_select_requests[4] &&
!output_arbs_0_select_requests[3] &&
!output_arbs_0_select_requests[2] &&
output_arbs_0_select_requests[1],
!output_arbs_0_select_requests[4] &&
!output_arbs_0_select_requests[3] &&
!output_arbs_0_select_requests[2] &&
!output_arbs_0_select_requests[1] &&
output_arbs_0_select_requests[0] } ;
// value method output_arbs_1_select
assign output_arbs_1_select =
{ !output_arbs_1_select_requests[0] &&
output_arbs_1_select_requests[4],
!output_arbs_1_select_requests[0] &&
!output_arbs_1_select_requests[4] &&
output_arbs_1_select_requests[3],
!output_arbs_1_select_requests[0] &&
!output_arbs_1_select_requests[4] &&
!output_arbs_1_select_requests[3] &&
output_arbs_1_select_requests[2],
!output_arbs_1_select_requests[0] &&
!output_arbs_1_select_requests[4] &&
!output_arbs_1_select_requests[3] &&
!output_arbs_1_select_requests[2] &&
output_arbs_1_select_requests[1],
output_arbs_1_select_requests[0] } ;
// value method output_arbs_2_select
assign output_arbs_2_select =
{ !output_arbs_2_select_requests[1] &&
!output_arbs_2_select_requests[0] &&
output_arbs_2_select_requests[4],
!output_arbs_2_select_requests[1] &&
!output_arbs_2_select_requests[0] &&
!output_arbs_2_select_requests[4] &&
output_arbs_2_select_requests[3],
!output_arbs_2_select_requests[1] &&
!output_arbs_2_select_requests[0] &&
!output_arbs_2_select_requests[4] &&
!output_arbs_2_select_requests[3] &&
output_arbs_2_select_requests[2],
output_arbs_2_select_requests[1],
!output_arbs_2_select_requests[1] &&
output_arbs_2_select_requests[0] } ;
// value method output_arbs_3_select
assign output_arbs_3_select =
{ !output_arbs_3_select_requests[2] &&
!output_arbs_3_select_requests[1] &&
!output_arbs_3_select_requests[0] &&
output_arbs_3_select_requests[4],
!output_arbs_3_select_requests[2] &&
!output_arbs_3_select_requests[1] &&
!output_arbs_3_select_requests[0] &&
!output_arbs_3_select_requests[4] &&
output_arbs_3_select_requests[3],
output_arbs_3_select_requests[2],
!output_arbs_3_select_requests[2] &&
output_arbs_3_select_requests[1],
!output_arbs_3_select_requests[2] &&
!output_arbs_3_select_requests[1] &&
output_arbs_3_select_requests[0] } ;
// value method output_arbs_4_select
assign output_arbs_4_select =
{ !output_arbs_4_select_requests[3] &&
!output_arbs_4_select_requests[2] &&
!output_arbs_4_select_requests[1] &&
!output_arbs_4_select_requests[0] &&
output_arbs_4_select_requests[4],
output_arbs_4_select_requests[3],
!output_arbs_4_select_requests[3] &&
output_arbs_4_select_requests[2],
!output_arbs_4_select_requests[3] &&
!output_arbs_4_select_requests[2] &&
output_arbs_4_select_requests[1],
!output_arbs_4_select_requests[3] &&
!output_arbs_4_select_requests[2] &&
!output_arbs_4_select_requests[1] &&
output_arbs_4_select_requests[0] } ;
endmodule // mkRouterOutputArbitersStatic
|
//ÊýÂë¹Ü¼Æ·ÖÄ£¿é
module Seg_Display
(
input clk,
input rst,
input add_cube,
inout [1:0]game_status,
output reg[15:0]point,
output reg[7:0]seg_out,
output reg[3:0]sel
);
localparam RESTART = 2'b00;
reg[31:0]clk_cnt;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
seg_out <= 0;
clk_cnt <= 0;
sel <= 0;
end
else if (game_status == RESTART) begin
seg_out <= 0;
clk_cnt <= 0;
sel <= 0;
end
else
begin
if(clk_cnt <= 20_0000)
begin
clk_cnt <= clk_cnt+1;
if(clk_cnt == 5_0000)
begin
sel <= 4'b1110;
case(point[3:0])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 10_0000)
begin
sel <= 4'b1101;
case(point[7:4])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 15_0000)
begin
sel <= 4'b1011;
case(point[11:8])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 20_0000)
begin
sel <= 4'b0111;
case(point[15:12])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
end
else
clk_cnt <= 0;
end
end
reg addcube_state;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
point <= 0;
addcube_state <= 0;
end
else if (game_status == RESTART) begin
point <= 0;
addcube_state <= 0;
end
else begin
case(addcube_state)
0: begin
if(add_cube) begin
if(point[3:0] < 9)
point[3:0] <= point[3:0] + 1;
else begin
point[3:0] <= 0;
if(point[7:4] < 9)
point[7:4] <= point[7:4] + 1;
else begin
point[7:4] <= 0;
if(point[11:8] < 9)
point[11:8] <= point[11:8] + 1;
else begin
point[11:8] <= 0;
point[15:12] <= point[15:12] + 1;
end
end
end
addcube_state <= 1;
end
end
1: begin
if(!add_cube)
addcube_state <= 0;
end
endcase
end
end
endmodule |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_9x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_9x256 (
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input clock;
input [8:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [8:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [7:0] sub_wire1;
wire sub_wire2;
wire [8:0] sub_wire3;
wire sub_wire4;
wire almost_full = sub_wire0;
wire [7:0] usedw = sub_wire1[7:0];
wire empty = sub_wire2;
wire [8:0] q = sub_wire3[8:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 240,
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 9,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "240"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "9"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "9"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "240"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL data[8..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL q[8..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 9 0 data 0 0 9 0
// Retrieval info: CONNECT: q 0 0 9 0 @q 0 0 9 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_9x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_9x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_9x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_9x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_9x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_9x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_9x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_9x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:55:30 03/10/2014
// Design Name:
// Module Name: Frequency
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Frequency_Block(
input wire clk,
input wire rst,
input wire rand,
output reg pass
);
parameter n = 100, M = 200, U = 6790;
reg [7:0] count_bits0, count_bits1, count_ones;
reg [6:0] count_blocks;
reg [19:0] chi_sqr; //log2((M^2)/4*n)
always @(posedge clk)
if (rst) begin
count_bits0 <= 8'HFF;
count_bits1 <= 0;
count_blocks <= 0;
count_ones <= 0;
chi_sqr <= 0;
pass <= 0;
end
else begin
count_bits0 <= count_bits0 + 1;
if (count_bits0 == (M-1)) begin
count_bits0 <= 0;
count_blocks <= count_blocks + 1;
if (count_blocks == (n-1)) begin
count_blocks <= 0;
end
end
count_bits1 <= count_bits0;
//count_bits2 <= count_bits1;
if (rand) count_ones <= count_ones + 1;
if (count_bits1 == (M-1)) begin
count_ones <= rand;
chi_sqr <= chi_sqr + (count_ones - M/2)*(count_ones - M/2);
end
if (count_blocks == 0)
if (count_bits1 == 0)
begin
chi_sqr <= 0;
if (chi_sqr <= U) pass <= 1;
else pass <= 0;
end
end
endmodule
|
// Based on US Patent # 4,486,739 (expired)
// Byte Oriented DC Balanced 8B/10B Partitioned Block Transmission Code
// Author: Franaszek et al.
//
// https://patentimages.storage.googleapis.com/67/2d/ad/0258c2f0d807bf/US4486739.pdf
//
`include "bsg_defines.v"
module bsg_8b10b_encode_comb
( input [7:0] data_i
, input k_i
, input rd_i
, output logic [9:0] data_o
, output logic rd_o
, output logic kerr_o
);
wire A = data_i[0];
wire B = data_i[1];
wire C = data_i[2];
wire D = data_i[3];
wire E = data_i[4];
wire F = data_i[5];
wire G = data_i[6];
wire H = data_i[7];
// From FIG. 3
wire AxorB = A ^ B;
wire CxorD = C ^ D;
wire AandB = A & B;
wire CandD = C & D;
wire NAandNB = ~A & ~B;
wire NCandND = ~C & ~D;
wire L22 = (AandB & NCandND) | (CandD & NAandNB) | (AxorB & CxorD);
wire L40 = AandB & CandD;
wire L04 = NAandNB & NCandND;
wire L13 = (AxorB & NCandND) | (CxorD & NAandNB);
wire L31 = (AxorB & CandD) | (CxorD & AandB);
// From FIG. 4
wire FxorG = F ^ G;
wire FandG = F & G;
wire NFandNG = ~F & ~G;
wire NFandNGandNH = NFandNG & ~H;
wire FxorGandK = FxorG & k_i;
wire FxorGandNH = FxorG & ~H;
wire FandGandH = FandG & H;
wire S = (rd_i & L31 & D & ~E) | (~rd_i & L13 & ~D & E);
// Form FIG. 5
wire T0 = L13 & D & E; // Intermediate net
wire PDM1S6 = T0 | (~L22 & ~L31 & ~E);
wire ND0S6 = PDM1S6;
wire PD0S6 = (E & ~L22 & ~L13) | k_i;
wire NDM1S6 = (L31 & ~D & ~E) | PD0S6;
wire NDM1S4 = FandG;
wire ND0S4 = NFandNG;
wire PDM1S4 = NFandNG | FxorGandK;
wire PD0S4 = FandGandH;
// From FIG. 6
wire COMPLS6 = (NDM1S6 & rd_i) | (~rd_i & PDM1S6);
wire NDL6 = (PD0S6 & ~COMPLS6) | (COMPLS6 & ND0S6) | (~ND0S6 & ~PD0S6 & rd_i);
wire COMPLS4 = (NDM1S4 & NDL6) | (~NDL6 & PDM1S4 );
assign rd_o = (NDL6 & ~PD0S4 & ~ND0S4) | (ND0S4 & COMPLS4) | (~COMPLS4 & PD0S4);
// From FIG. 7
wire N0 = A;
wire N1 = (~L40 & B) | L04;
wire N2 = (L04 | C) | T0;
wire N3 = D & ~L40;
wire N4 = (~T0 & E) | (~E & L13);
wire N5 = (~E & L22) | (L22 & k_i) | (L04 & E) | (E & L40) | (E & L13 & ~D);
assign data_o[0] = N0 ^ COMPLS6;
assign data_o[1] = N1 ^ COMPLS6;
assign data_o[2] = N2 ^ COMPLS6;
assign data_o[3] = N3 ^ COMPLS6;
assign data_o[4] = N4 ^ COMPLS6;
assign data_o[5] = N5 ^ COMPLS6;
// From FIG. 8
wire T1 = (S & FandGandH) | (FandGandH & k_i); // Intermediate net
wire N6 = ~(~F | T1);
wire N7 = G | NFandNGandNH;
wire N8 = H;
wire N9 = T1 | FxorGandNH;
assign data_o[6] = N6 ^ COMPLS4;
assign data_o[7] = N7 ^ COMPLS4;
assign data_o[8] = N8 ^ COMPLS4;
assign data_o[9] = N9 ^ COMPLS4;
// Not in patent
assign kerr_o = k_i & ~(NAandNB & CandD & E) & ~(FandGandH & E & L31) ;
endmodule
|
/*
* Copyright (C) 2020-2021 The SymbiFlow Authors.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`include "muxcy.v"
`include "xorcy.v"
module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
wire CIN = CI | CYINIT;
MUXCY muxcy0 (.O(CO[0]), .CI(CIN), .DI(DI[0]), .S(S[0]));
MUXCY muxcy1 (.O(CO[1]), .CI(CO[0]), .DI(DI[1]), .S(S[1]));
MUXCY muxcy2 (.O(CO[2]), .CI(CO[1]), .DI(DI[2]), .S(S[2]));
MUXCY muxcy3 (.O(CO[3]), .CI(CO[2]), .DI(DI[3]), .S(S[3]));
XORCY xorcy0 (.O(O[0]), .CI(CIN), .LI(S[0]));
XORCY xorcy1 (.O(O[1]), .CI(CO[0]), .LI(S[1]));
XORCY xorcy2 (.O(O[2]), .CI(CO[1]), .LI(S[2]));
XORCY xorcy3 (.O(O[3]), .CI(CO[2]), .LI(S[3]));
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pad_ddr1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module pad_ddr1(ddr1_bypass_data ,spare_ddr1_pindata ,spare_ddr1_pin ,
ddr_testmode_l ,ddr1_dll_bypass_l ,bscan_mode_ctl_in ,
spare_ddr1_pad ,spare_ddr1_paddata ,ps_select ,ddr_se ,ddr_so ,
ddr_si ,bscan_hiz_l_in ,test_mode ,serial_in ,afo ,bypass_enable ,
serial_out ,afi ,bscan_update_dr_out ,bscan_shift_dr_out ,
bscan_clock_dr_out ,bscan_hiz_l_out ,bypass_enable_out ,
ps_select_out ,bscan_mode_ctl_out ,pad_ddr1_bso ,dram_arst_l ,
dram_gdbginit_l ,ddr0_ddr1_cbu ,dram1_io_ptr_clk_inv ,dram1_io_bank
,dram1_dq ,dram_gclk ,clk_ddr1_cken ,dram1_cb ,dram1_ck_p ,
ddr0_ddr1_cbd ,dram_grst_l ,dram1_ba ,dram1_cas_l ,dram1_ras_l ,
dram1_cke ,vdd18 ,ctu_ddr1_dll_delayctr ,bscan_clock_dr_in ,
ctu_ddr1_iodll_rst_l ,dram1_io_pad_enable ,pad_ddr1_bsi ,
ddr1_ctu_dll_lock ,dram_adbginit_l ,dram1_dqs ,dram1_addr ,
dram1_we_l ,dram1_ck_n ,dram1_io_cs_l ,bscan_shift_dr_in ,
dram1_io_write_en_l ,bscan_update_dr_in ,dram1_io_drive_enable ,
ddr1_ctu_dll_overflow ,dram1_io_cas_l ,dram1_io_ras_l ,
dram1_io_clk_enable ,io_dram1_data_valid ,dram1_io_addr ,
io_dram1_data_in ,dram1_io_channel_disabled ,io_dram1_ecc_in ,
dram1_io_drive_data ,dram1_io_data_out ,dram1_io_cke ,
dram1_io_pad_clk_inv ,dram1_cs_l, ddr1_lpf_code );
output [4:0] ddr1_lpf_code ;
output [143:0] serial_out ;
output [143:0] afi ;
output [3:0] dram1_ck_p ;
output [2:0] dram1_ba ;
output [14:0] dram1_addr ;
output [3:0] dram1_ck_n ;
output [255:0] io_dram1_data_in ;
output [31:0] io_dram1_ecc_in ;
output [3:0] dram1_cs_l ;
input [4:0] ddr1_bypass_data ;
input [2:0] spare_ddr1_pindata ;
input [6:0] spare_ddr1_paddata ;
input [143:0] serial_in ;
input [143:0] afo ;
input [8:1] ddr0_ddr1_cbu ;
input [4:0] dram1_io_ptr_clk_inv ;
input [2:0] dram1_io_bank ;
input [1:0] dram_gclk ;
input [8:1] ddr0_ddr1_cbd ;
input [2:0] ctu_ddr1_dll_delayctr ;
input [3:0] dram1_io_cs_l ;
input [14:0] dram1_io_addr ;
input [287:0] dram1_io_data_out ;
inout [2:0] spare_ddr1_pin ;
inout [6:0] spare_ddr1_pad ;
inout [127:0] dram1_dq ;
inout [15:0] dram1_cb ;
inout [35:0] dram1_dqs ;
output ddr_so ;
output bscan_update_dr_out ;
output bscan_shift_dr_out ;
output bscan_clock_dr_out ;
output bscan_hiz_l_out ;
output bypass_enable_out ;
output ps_select_out ;
output bscan_mode_ctl_out ;
output pad_ddr1_bso ;
output dram1_cas_l ;
output dram1_ras_l ;
output dram1_cke ;
output ddr1_ctu_dll_lock ;
output dram1_we_l ;
output ddr1_ctu_dll_overflow ;
output io_dram1_data_valid ;
input ddr_testmode_l ;
input ddr1_dll_bypass_l ;
input bscan_mode_ctl_in ;
input ps_select ;
input ddr_se ;
input ddr_si ;
input bscan_hiz_l_in ;
input test_mode ;
input bypass_enable ;
input dram_arst_l ;
input dram_gdbginit_l ;
input clk_ddr1_cken ;
input dram_grst_l ;
input vdd18 ;
input bscan_clock_dr_in ;
input ctu_ddr1_iodll_rst_l ;
input dram1_io_pad_enable ;
input pad_ddr1_bsi ;
input dram_adbginit_l ;
input bscan_shift_dr_in ;
input dram1_io_write_en_l ;
input bscan_update_dr_in ;
input dram1_io_drive_enable ;
input dram1_io_cas_l ;
input dram1_io_ras_l ;
input dram1_io_clk_enable ;
input dram1_io_channel_disabled ;
input dram1_io_drive_data ;
input dram1_io_cke ;
input dram1_io_pad_clk_inv ;
supply1 vdd ;
wire strobe ;
wire rst_l ;
wire scan0 ;
wire scan1 ;
wire net147 ;
wire rclk ;
wire arst2_l ;
ddr_ch_b ddr1_ddr_ch_b (
.arst_l_out (arst2_l ),
.afo ({afo } ),
.serial_in ({serial_in } ),
.afi ({afi } ),
.serial_out ({serial_out } ),
.dram_io_data_out ({dram1_io_data_out } ),
.spare_ddr_pin ({spare_ddr1_pin[2] ,spare_ddr1_pad[6:0] ,
spare_ddr1_pin[1:0] } ),
.spare_ddr_data ({spare_ddr1_pindata[2] ,spare_ddr1_paddata[6:0] ,
spare_ddr1_pindata[1:0] } ),
.dram_io_ptr_clk_inv ({dram1_io_ptr_clk_inv } ),
.io_dram_data_in ({io_dram1_data_in } ),
.io_dram_ecc_in ({io_dram1_ecc_in } ),
.dram_io_addr ({dram1_io_addr } ),
.dram_io_bank ({dram1_io_bank } ),
.dram_io_cs_l ({dram1_io_cs_l } ),
.dram_dq ({dram1_dq } ),
.dram_addr ({dram1_addr } ),
.dram_cb ({dram1_cb } ),
.dram_dqs ({dram1_dqs } ),
.dram_ba ({dram1_ba } ),
.dram_ck_n ({dram1_ck_n } ),
.dram_ck_p ({dram1_ck_p } ),
.dram_cs_l ({dram1_cs_l } ),
.lpf_code ({ddr1_lpf_code } ),
.cbu ({ddr0_ddr1_cbu } ),
.cbd ({ddr0_ddr1_cbd } ),
.pad_clk_si (ddr_si ),
.testmode_l (ddr_testmode_l ),
.test_mode (test_mode ),
.bypass_enable_out (bypass_enable_out ),
.ps_select_out (ps_select_out ),
.rclk (rclk ),
.se (ddr_se ),
.pad_clk_so (scan0 ),
.update_dr_in (bscan_update_dr_in ),
.bso (pad_ddr1_bso ),
.bsi (pad_ddr1_bsi ),
.bypass_enable_in (bypass_enable ),
.mode_ctrl_out (bscan_mode_ctl_out ),
.update_dr_out (bscan_update_dr_out ),
.shift_dr_out (bscan_shift_dr_out ),
.clock_dr_out (bscan_clock_dr_out ),
.hiz_n_out (bscan_hiz_l_out ),
.ps_select_in (ps_select ),
.mode_ctrl_in (bscan_mode_ctl_in ),
.shift_dr_in (bscan_shift_dr_in ),
.clock_dr_in (bscan_clock_dr_in ),
.hiz_n_in (bscan_hiz_l_in ),
.strobe (strobe ),
.dram_io_clk_enable (dram1_io_clk_enable ),
.dram_io_cke (dram1_io_cke ),
.dram_io_ras_l (dram1_io_ras_l ),
.dram_io_write_en_l (dram1_io_write_en_l ),
.dram_io_cas_l (dram1_io_cas_l ),
.dram_cke (dram1_cke ),
.io_dram_data_valid (io_dram1_data_valid ),
.dram_ras_l (dram1_ras_l ),
.dram_we_l (dram1_we_l ),
.dram_cas_l (dram1_cas_l ),
.burst_length_four (vdd ),
.dram_io_pad_clk_inv (dram1_io_pad_clk_inv ),
.dram_io_pad_enable (dram1_io_pad_enable ),
.dram_io_drive_enable (dram1_io_drive_enable ),
.rst_l (rst_l ),
.dram_arst_l (dram_arst_l ),
.dram_io_channel_disabled (dram1_io_channel_disabled ),
.dram_io_drive_data (dram1_io_drive_data ),
.vdd_h (vdd18 ) );
// ECO 7016: added ddr1_iodll_code_adjust 10/11/04
wire [4:0] ddr1_lpf_code_pre;
wire scan1_pre;
bw_iodll_code_adjust ddr1_iodll_code_adjust (
.bypass_data (ddr1_bypass_data[4:0]),
.ddr_clk_in (rclk),
.delay_ctrl (ctu_ddr1_dll_delayctr[2:0]),
.io_dll_bypass_l (ddr1_dll_bypass_l),
.iodll_reset_l (ctu_ddr1_iodll_rst_l),
.s_controller_out (ddr1_lpf_code_pre[4:0]),
.s_percent_ctrl_out (ddr1_lpf_code[4:0]),
.se (ddr_se),
.si (scan1_pre),
.so (scan1));
bw_iodll ddr1_master_dll (
.ddr_testmode_l (ddr_testmode_l ),
.bypass_data ({ddr1_bypass_data } ),
.lpf_out ({ddr1_lpf_code_pre } ),
.delay_ctrl ({ctu_ddr1_dll_delayctr } ),
.so (scan1_pre ),
.io_dll_bypass_l (ddr1_dll_bypass_l ),
.io_dll_reset_l (ctu_ddr1_iodll_rst_l ),
.se (ddr_se ),
.si (scan0 ),
.ddr_clk_in (rclk ),
.iodll_lock (ddr1_ctu_dll_lock ),
.overflow (ddr1_ctu_dll_overflow ),
.strobe (strobe ) );
// End ECO 7016
bw_clk_cl_ddr_ddr pad_ddr1_header (
.gclk ({dram_gclk } ),
.ddr_rclk (rclk ),
.so (ddr_so_pre_latch ),
.si (scan1 ),
.gdbginit_l (dram_gdbginit_l ),
.grst_l (dram_grst_l ),
.cluster_grst_l (rst_l ),
.dbginit_l (net147 ),
.rclk (rclk ),
.se (ddr_se ),
.adbginit_l (dram_adbginit_l ),
.arst_l (dram_arst_l ),
.arst2_l (arst2_l ),
.cluster_cken (clk_ddr1_cken ) );
bw_u1_scanl_2x lockup_latch(
.so(ddr_so),
.sd(ddr_so_pre_latch),
.ck(rclk));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_NSR_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_NSR_BLACKBOX_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$NSR (
Q ,
SET ,
RESET,
CLK_N,
D
);
output Q ;
input SET ;
input RESET;
input CLK_N;
input D ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_NSR_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_SYMBOL_V
`define SKY130_FD_SC_HD__O2BB2AI_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_SYMBOL_V
|
`define bsg_mem_1r1w_sync_macro(words,bits) \
if (els_p == words && width_p == bits) \
begin: macro \
hard_mem_1r1w_d``words``_w``bits``_wrapper \
mem \
(.clk_i ( clk_i ) \
,.reset_i ( reset_i ) \
,.w_v_i ( w_v_i ) \
,.w_addr_i( w_addr_i ) \
,.w_data_i( w_data_i ) \
,.r_v_i ( r_v_i ) \
,.r_addr_i( r_addr_i ) \
,.r_data_o( r_data_o ) \
); \
end
module bsg_mem_1r1w_sync #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p = 0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 0
// NOTE: unused
, parameter substitute_1r1w_p = 0
)
( input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_1r1w_sync_macro(64,50) else
`bsg_mem_1r1w_sync_macro(1024,4) else
// no hardened version found
begin : notmacro
initial if (substitute_1r1w_p != 0) $warning("substitute_1r1w_p will have no effect");
bsg_mem_1r1w_sync_synth #(.width_p(width_p), .els_p(els_p), .read_write_same_addr_p(read_write_same_addr_p), .harden_p(harden_p))
synth
(.*);
end // block: notmacro
//synopsys translate_off
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DFRBP_BEHAVIORAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_r_no_pg/sky130_fd_sc_hs__u_df_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dfrbp (
RESET_B,
CLK ,
D ,
Q ,
Q_N ,
VPWR ,
VGND
);
// Module ports
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_df_p_r_no_pg u_df_p_r_no_pg0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRBP_BEHAVIORAL_V |
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
// IP Revision: 1
`timescale 1ns/1ps
module zqynq_lab_1_design_processing_system7_0_1 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
input [1 : 0] IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_vip_v1_0_1 #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100.0),
.C_FCLK_CLK1_FREQ(10.0),
.C_FCLK_CLK2_FREQ(10.0),
.C_FCLK_CLK3_FREQ(10.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(IRQ_F2P),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
Require Import Eqdep List.
Require Omega.
Set Implicit Arguments.
(** A version of [injection] that does some standard simplifications afterward: clear the hypothesis in question, bring the new facts above the double line, and attempt substitution for known variables. *)
Ltac inject H := injection H; clear H; intros; try subst.
(** Try calling tactic function [f] on all hypotheses, keeping the first application that doesn't fail. *)
Ltac appHyps f :=
match goal with
| [ H : _ |- _ ] => f H
end.
(** Succeed iff [x] is in the list [ls], represented with left-associated nested tuples. *)
Ltac inList x ls :=
match ls with
| x => idtac
| (_, x) => idtac
| (?LS, _) => inList x LS
end.
(** Try calling tactic function [f] on every element of tupled list [ls], keeping the first call not to fail. *)
Ltac app f ls :=
match ls with
| (?LS, ?X) => f X || app f LS || fail 1
| _ => f ls
end.
(** Run [f] on every element of [ls], not just the first that doesn't fail. *)
Ltac all f ls :=
match ls with
| (?LS, ?X) => f X; all f LS
| (_, _) => fail 1
| _ => f ls
end.
(** Workhorse tactic to simplify hypotheses for a variety of proofs.
* Argument [invOne] is a tuple-list of predicates for which we always do inversion automatically. *)
Ltac simplHyp invOne :=
(** Helper function to do inversion on certain hypotheses, where [H] is the hypothesis and [F] its head symbol *)
let invert H F :=
(** We only proceed for those predicates in [invOne]. *)
inList F invOne;
(** This case covers an inversion that succeeds immediately, meaning no constructors of [F] applied. *)
(inversion H; fail)
(** Otherwise, we only proceed if inversion eliminates all but one constructor case. *)
|| (inversion H; [idtac]; clear H; try subst) in
match goal with
(** Eliminate all existential hypotheses. *)
| [ H : ex _ |- _ ] => destruct H
(** Find opportunities to take advantage of injectivity of data constructors, for several different arities. *)
| [ H : ?F ?X = ?F ?Y |- ?G ] =>
(** This first branch of the [||] fails the whole attempt iff the arguments of the constructor applications are already easy to prove equal. *)
(assert (X = Y); [ assumption | fail 1 ])
(** If we pass that filter, then we use injection on [H] and do some simplification as in [inject].
* The odd-looking check of the goal form is to avoid cases where [injection] gives a more complex result because of dependent typing, which we aren't equipped to handle here. *)
|| (injection H;
match goal with
| [ |- X = Y -> G ] =>
try clear H; intros; try subst
end)
| [ H : ?F ?X ?U = ?F ?Y ?V |- ?G ] =>
(assert (X = Y); [ assumption
| assert (U = V); [ assumption | fail 1 ] ])
|| (injection H;
match goal with
| [ |- U = V -> X = Y -> G ] =>
try clear H; intros; try subst
end)
(** Consider some different arities of a predicate [F] in a hypothesis that we might want to invert. *)
| [ H : ?F _ |- _ ] => invert H F
| [ H : ?F _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ _ |- _ ] => invert H F
(** Use an (axiom-dependent!) inversion principle for dependent pairs, from the standard library. *)
| [ H : existT _ ?T _ = existT _ ?T _ |- _ ] => generalize (inj_pair2 _ _ _ _ _ H); clear H
(** If we're not ready to use that principle yet, try the standard inversion, which often enables the previous rule. *)
| [ H : existT _ _ _ = existT _ _ _ |- _ ] => inversion H; clear H
(** Similar logic to the cases for constructor injectivity above, but specialized to [Some], since the above cases won't deal with polymorphic constructors. *)
| [ H : Some _ = Some _ |- _ ] => injection H; clear H
end.
(** Find some hypothesis to rewrite with, ensuring that [auto] proves all of the extra subgoals added by [rewrite]. *)
Ltac rewriteHyp :=
match goal with
| [ H : _ |- _ ] => rewrite H by solve [ auto ]
end.
(** Combine [autorewrite] with automatic hypothesis rewrites. *)
Ltac rewriterP := repeat (rewriteHyp; autorewrite with core in *).
Ltac rewriter := autorewrite with core in *; rewriterP.
(** This one is just so darned useful, let's add it as a hint here. *)
Hint Rewrite app_ass.
(** Devious marker predicate to use for encoding state within proof goals *)
Definition done (T : Type) (x : T) := True.
(** Try a new instantiation of a universally quantified fact, proved by [e].
* [trace] is an accumulator recording which instantiations we choose. *)
Ltac inster e trace :=
(** Does [e] have any quantifiers left? *)
match type of e with
| forall x : _, _ =>
(** Yes, so let's pick the first context variable of the right type. *)
match goal with
| [ H : _ |- _ ] =>
inster (e H) (trace, H)
| _ => fail 2
end
| _ =>
(** No more quantifiers, so now we check if the trace we computed was already used. *)
match trace with
| (_, _) =>
(** We only reach this case if the trace is nonempty, ensuring that [inster] fails if no progress can be made. *)
match goal with
| [ H : done (trace, _) |- _ ] =>
(** Uh oh, found a record of this trace in the context! Abort to backtrack to try another trace. *)
fail 1
| _ =>
(** What is the type of the proof [e] now? *)
let T := type of e in
match type of T with
| Prop =>
(** [e] should be thought of as a proof, so let's add it to the context, and also add a new marker hypothesis recording our choice of trace. *)
generalize e; intro;
assert (done (trace, tt)) by constructor
| _ =>
(** [e] is something beside a proof. Better make sure no element of our current trace was generated by a previous call to [inster], or we might get stuck in an infinite loop! (We store previous [inster] terms in second positions of tuples used as arguments to [done] in hypotheses. Proofs instantiated by [inster] merely use [tt] in such positions.) *)
all ltac:(fun X =>
match goal with
| [ H : done (_, X) |- _ ] => fail 1
| _ => idtac
end) trace;
(** Pick a new name for our new instantiation. *)
let i := fresh "i" in (pose (i := e);
assert (done (trace, i)) by constructor)
end
end
end
end.
(** After a round of application with the above, we will have a lot of junk [done] markers to clean up; hence this tactic. *)
Ltac un_done :=
repeat match goal with
| [ H : done _ |- _ ] => clear H
end.
Require Import JMeq.
(** A more parameterized version of the famous [crush]. Extra arguments are:
* - A tuple-list of lemmas we try [inster]-ing
* - A tuple-list of predicates we try inversion for *)
Ltac crush' lemmas invOne :=
(** A useful combination of standard automation *)
let sintuition := simpl in *; intuition; try subst;
repeat (simplHyp invOne; intuition; try subst); try congruence in
(** A fancier version of [rewriter] from above, which uses [crush'] to discharge side conditions *)
let rewriter := autorewrite with core in *;
repeat (match goal with
| [ H : ?P |- _ ] =>
match P with
| context[JMeq] => fail 1 (** JMeq is too fancy to deal with here. *)
| _ => rewrite H by crush' lemmas invOne
end
end; autorewrite with core in *) in
(** Now the main sequence of heuristics: *)
(sintuition; rewriter;
match lemmas with
| false => idtac (** No lemmas? Nothing to do here *)
| _ =>
(** Try a loop of instantiating lemmas... *)
repeat ((app ltac:(fun L => inster L L) lemmas
(** ...or instantiating hypotheses... *)
|| appHyps ltac:(fun L => inster L L));
(** ...and then simplifying hypotheses. *)
repeat (simplHyp invOne; intuition)); un_done
end;
sintuition; rewriter; sintuition;
(** End with a last attempt to prove an arithmetic fact with [omega], or prove any sort of fact in a context that is contradictory by reasoning that [omega] can do. *)
try omega; try (elimtype False; omega)).
(** [crush] instantiates [crush'] with the simplest possible parameters. *)
Ltac crush := crush' false fail.
(** * Wrap Program's [dependent destruction] in a slightly more pleasant form *)
Require Import Program.Equality.
(** Run [dependent destruction] on [E] and look for opportunities to simplify the result.
The weird introduction of [x] helps get around limitations of [dependent destruction], in terms of which sorts of arguments it will accept (e.g., variables bound to hypotheses within Ltac [match]es). *)
Ltac dep_destruct E :=
let x := fresh "x" in
remember E as x; simpl in x; dependent destruction x;
try match goal with
| [ H : _ = E |- _ ] => rewrite <- H in *; clear H
end.
(** Nuke all hypotheses that we can get away with, without invalidating the goal statement. *)
Ltac clear_all :=
repeat match goal with
| [ H : _ |- _ ] => clear H
end.
(** Instantiate a quantifier in a hypothesis [H] with value [v], or, if [v] doesn't have the right type, with a new unification variable.
* Also prove the lefthand sides of any implications that this exposes, simplifying [H] to leave out those implications. *)
Ltac guess v H :=
repeat match type of H with
| forall x : ?T, _ =>
match type of T with
| Prop =>
(let H' := fresh "H'" in
assert (H' : T); [
solve [ eauto 6 ]
| specialize (H H'); clear H' ])
|| fail 1
| _ =>
specialize (H v)
|| let x := fresh "x" in
evar (x : T);
let x' := eval unfold x in x in
clear x; specialize (H x')
end
end.
(** Version of [guess] that leaves the original [H] intact *)
Ltac guessKeep v H :=
let H' := fresh "H'" in
generalize H; intro H'; guess v H'.
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cclk_sync.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cclk_sync (/*AUTOARG*/
// Outputs
dram_rx_sync_local, dram_tx_sync_local, jbus_rx_sync_local,
jbus_tx_sync_local, so,
// Inputs
dram_rx_sync_global, dram_tx_sync_global, jbus_rx_sync_global,
jbus_tx_sync_global, cmp_gclk, cmp_rclk, si, se
);
output dram_rx_sync_local;
output dram_tx_sync_local;
output jbus_rx_sync_local;
output jbus_tx_sync_local;
output so;
input dram_rx_sync_global;
input dram_tx_sync_global;
input jbus_rx_sync_global;
input jbus_tx_sync_global;
input cmp_gclk;
input cmp_rclk;
input si;
input se;
wire dram_rx_so;
wire dram_tx_so;
wire jbus_rx_so;
sync_pulse_synchronizer dram_rx_synchronizer (
.sync_out(dram_rx_sync_local),
.so(dram_rx_so),
.async_in(dram_rx_sync_global),
.gclk(cmp_gclk),
.rclk(cmp_rclk),
.si(si),
.se(se)
);
sync_pulse_synchronizer dram_tx_synchronizer (
.sync_out(dram_tx_sync_local),
.so(dram_tx_so),
.async_in(dram_tx_sync_global),
.gclk(cmp_gclk),
.rclk(cmp_rclk),
.si(dram_rx_so),
.se(se)
);
sync_pulse_synchronizer jbus_rx_synchronizer (
.sync_out(jbus_rx_sync_local),
.so(jbus_rx_so),
.async_in(jbus_rx_sync_global),
.gclk(cmp_gclk),
.rclk(cmp_rclk),
.si(dram_tx_so),
.se(se)
);
sync_pulse_synchronizer jbus_tx_synchronizer (
.sync_out(jbus_tx_sync_local),
.so(so),
.async_in(jbus_tx_sync_global),
.gclk(cmp_gclk),
.rclk(cmp_rclk),
.si(jbus_rx_so),
.se(se)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BAI_SYMBOL_V
`define SKY130_FD_SC_LS__O21BAI_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BAI_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVPWRVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__TAPVPWRVGND_BEHAVIORAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvpwrvgnd (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVPWRVGND_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRBP_LP_V
`define SKY130_FD_SC_LP__DFRBP_LP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrbp_lp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrbp_lp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRBP_LP_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Run-Length encoder ////
//// ////
//// 1) Retreive zig-zag-ed samples (starting with DC coeff.) ////
//// 2) Translate DC-coeff. into 11bit-size and amplitude ////
//// 3) Translate AC-coeff. into zero-runs, size and amplitude ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_rle.v,v 1.4 2002/10/31 12:53:39 rherveille Exp $
//
// $Date: 2002/10/31 12:53:39 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_rle.v,v $
// Revision 1.4 2002/10/31 12:53:39 rherveille
// *** empty log message ***
//
// Revision 1.3 2002/10/23 18:58:54 rherveille
// Fixed a bug in the zero-run (run-length-coder)
//
// Revision 1.2 2002/10/23 09:07:04 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_rle(clk, rst, ena, dstrb, din, size, rlen, amp, douten, bstart);
//
// parameters
//
//
// inputs & outputs
//
input clk; // system clock
input rst; // asynchronous reset
input ena; // clock enable
input dstrb;
input [11:0] din; // data input
output [ 3:0] size; // size
output [ 3:0] rlen; // run-length
output [11:0] amp; // amplitude
output douten; // data output enable
output bstart; // block start
//
// variables
//
wire [ 3:0] rle_rlen, rz1_rlen, rz2_rlen, rz3_rlen, rz4_rlen;
wire [ 3:0] rle_size, rz1_size, rz2_size, rz3_size, rz4_size;
wire [11:0] rle_amp, rz1_amp, rz2_amp, rz3_amp, rz4_amp;
wire rle_den, rz1_den, rz2_den, rz3_den, rz4_den;
wire rle_dc, rz1_dc, rz2_dc, rz3_dc, rz4_dc;
//
// module body
//
reg ddstrb;
always @(posedge clk)
ddstrb <= #1 dstrb;
// generate run-length encoded signals
jpeg_rle1 rle(
.clk(clk),
.rst(rst),
.ena(ena),
.go(ddstrb),
.din(din),
.rlen(rle_rlen),
.size(rle_size),
.amp(rle_amp),
.den(rle_den),
.dcterm(rle_dc)
);
// Find (15,0) (0,0) sequences and replace by (0,0)
// There can be max. 4 (15,0) sequences in a row
// step1
jpeg_rzs rz1(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rle_rlen),
.sizei(rle_size),
.ampi(rle_amp),
.deni(rle_den),
.dci(rle_dc),
.rleno(rz1_rlen),
.sizeo(rz1_size),
.ampo(rz1_amp),
.deno(rz1_den),
.dco(rz1_dc)
);
// step2
jpeg_rzs rz2(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz1_rlen),
.sizei(rz1_size),
.ampi(rz1_amp),
.deni(rz1_den),
.dci(rz1_dc),
.rleno(rz2_rlen),
.sizeo(rz2_size),
.ampo(rz2_amp),
.deno(rz2_den),
.dco(rz2_dc)
);
// step3
jpeg_rzs rz3(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz2_rlen),
.sizei(rz2_size),
.ampi(rz2_amp),
.deni(rz2_den),
.dci(rz2_dc),
.rleno(rz3_rlen),
.sizeo(rz3_size),
.ampo(rz3_amp),
.deno(rz3_den),
.dco(rz3_dc)
);
// step4
jpeg_rzs rz4(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz3_rlen),
.sizei(rz3_size),
.ampi(rz3_amp),
.deni(rz3_den),
.dci(rz3_dc),
.rleno(rz4_rlen),
.sizeo(rz4_size),
.ampo(rz4_amp),
.deno(rz4_den),
.dco(rz4_dc)
);
// assign outputs
assign rlen = rz4_rlen;
assign size = rz4_size;
assign amp = rz4_amp;
assign douten = rz4_den;
assign bstart = rz4_dc;
endmodule
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module alu_slice(a, b, c, less, sel, cout, out);
input a, b, c, less;
input [2:0] sel;
output cout, out;
wire sum, cout, ANDresult,less, ORresult, b_inv;
reg out;
assign b_inv = sel[2] ^ b;
assign ANDresult = a & b;
assign ORresult = a | b;
fulladder f1(a, b_inv, c, sum, cout);
always @(a or b or c or less or sel)
begin
case(sel[1:0])
2'b00: out = ANDresult;
2'b01: out = ORresult;
2'b10: out = sum;
2'b11: out = less;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_1_V
`define SKY130_FD_SC_HVL__SDFXBP_1_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxbp_1 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND4BB_PP_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4BB_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__FILL_PP_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fill (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O221AI_BEHAVIORAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NAND3B_PP_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_4_V
`define SKY130_FD_SC_LP__A22O_4_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_1_V
`define SKY130_FD_SC_HVL__AND2_1_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__and2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__and2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_1_V
|
`timescale 1ns/1ps
module dpram_xlx #(
parameter ADDRWIDTH = 4,
parameter DATAWIDTH = 8,
parameter [ADDRWIDTH:0] DEPTH = 16
) (
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [0 : 0] wea;
input [ADDRWIDTH-1 : 0] addra;
input [DATAWIDTH-1 : 0] dina;
output[DATAWIDTH-1 : 0] douta;
input clkb;
input enb;
input [0 : 0] web;
input [ADDRWIDTH-1 : 0] addrb;
input [DATAWIDTH-1 : 0] dinb;
output[DATAWIDTH-1 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V4_3 #(
.C_ADDRA_WIDTH(ADDRWIDTH),
.C_ADDRB_WIDTH(ADDRWIDTH),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(DEPTH),
.C_READ_DEPTH_B(DEPTH),
.C_READ_WIDTH_A(DATAWIDTH),
.C_READ_WIDTH_B(DATAWIDTH),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(DEPTH),
.C_WRITE_DEPTH_B(DEPTH),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(DATAWIDTH),
.C_WRITE_WIDTH_B(DATAWIDTH),
.C_XDEVICEFAMILY("spartan6"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of dpram_xlx is "black_box"
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NOR2B_FUNCTIONAL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor2b (
Y ,
A ,
B_N
);
// Module ports
output Y ;
input A ;
input B_N;
// Local signals
wire not0_out ;
wire and0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y, not0_out, B_N );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_FUNCTIONAL_V |
//
// sd_card.v
//
// This file implelents a sd card for the MIST board since on the board
// the SD card is connected to the ARM IO controller and the FPGA has no
// direct connection to the SD card. This file provides a SD card like
// interface to the IO controller easing porting of cores that expect
// a direct interface to the SD card.
//
// Copyright (c) 2014 Till Harbaum <[email protected]>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the Lesser GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// http://elm-chan.org/docs/mmc/mmc_e.html
module sd_card (
input clk_sys,
// link to user_io for io controller
output [31:0] sd_lba,
output reg sd_rd,
output reg sd_wr,
input sd_ack,
input sd_ack_conf,
output sd_conf,
output sd_sdhc,
input img_mounted,
input [31:0] img_size,
output reg sd_busy = 0,
// data coming in from io controller
input [7:0] sd_buff_dout,
input sd_buff_wr,
// data going out to io controller
output [7:0] sd_buff_din,
input [8:0] sd_buff_addr,
// configuration input
input allow_sdhc,
input sd_cs,
input sd_sck,
input sd_sdi,
output reg sd_sdo
);
wire [31:0] OCR = { 1'b1, sd_sdhc, 6'h0, 9'h1f, 15'h0 }; // bit31 = finished powerup
// bit30 = 1 -> high capaciry card (sdhc)
// 15-23 supported voltage range
wire [7:0] READ_DATA_TOKEN = 8'hfe;
// number of bytes to wait after a command before sending the reply
localparam NCR=4;
localparam RD_STATE_IDLE = 2'd0;
localparam RD_STATE_WAIT_IO = 2'd1;
localparam RD_STATE_SEND_TOKEN = 2'd2;
localparam RD_STATE_SEND_DATA = 2'd3;
reg [1:0] read_state = RD_STATE_IDLE;
localparam WR_STATE_IDLE = 3'd0;
localparam WR_STATE_EXP_DTOKEN = 3'd1;
localparam WR_STATE_RECV_DATA = 3'd2;
localparam WR_STATE_RECV_CRC0 = 3'd3;
localparam WR_STATE_RECV_CRC1 = 3'd4;
localparam WR_STATE_SEND_DRESP = 3'd5;
localparam WR_STATE_BUSY = 3'd6;
reg [2:0] write_state = WR_STATE_IDLE;
reg card_is_reset = 1'b0; // flag that card has received a reset command
reg [6:0] sbuf;
reg cmd55;
reg [7:0] cmd = 8'h00;
reg [2:0] bit_cnt = 3'd0; // counts bits 0-7 0-7 ...
reg [3:0] byte_cnt= 4'd15; // counts bytes
reg [39:0] args;
assign sd_lba = sd_sdhc?args[39:8]:{9'd0, args[39:17]};
reg [7:0] reply;
reg [7:0] reply0, reply1, reply2, reply3;
reg [3:0] reply_len;
// ------------------------- SECTOR BUFFER -----------------------
// the buffer itself. Can hold one sector
reg [8:0] buffer_ptr;
wire [7:0] buffer_dout;
reg [7:0] buffer_din;
reg buffer_write_strobe;
sd_card_dpram #(8, 9) buffer_dpram
(
.clock_a (clk_sys),
.address_a (sd_buff_addr),
.data_a (sd_buff_dout),
.wren_a (sd_buff_wr & sd_ack),
.q_a (sd_buff_din),
.clock_b (clk_sys),
.address_b (buffer_ptr),
.data_b (buffer_din),
.wren_b (buffer_write_strobe),
.q_b (buffer_dout)
);
wire [7:0] WRITE_DATA_RESPONSE = 8'h05;
// ------------------------- CSD/CID BUFFER ----------------------
reg [7:0] conf;
assign sd_conf = sd_configuring;
reg sd_configuring = 1;
reg [4:0] conf_buff_ptr;
reg [7:0] conf_byte;
reg[255:0] csdcid;
// conf[0]==1 -> io controller is using an sdhc card
wire sd_has_sdhc = conf[0];
assign sd_sdhc = allow_sdhc && sd_has_sdhc;
always @(posedge clk_sys) begin
reg old_mounted;
if (sd_buff_wr & sd_ack_conf) begin
if (sd_buff_addr == 32) begin
conf <= sd_buff_dout;
sd_configuring <= 0;
end
else csdcid[(31-sd_buff_addr) << 3 +:8] <= sd_buff_dout;
end
conf_byte <= csdcid[(31-conf_buff_ptr) << 3 +:8];
old_mounted <= img_mounted;
if (~old_mounted & img_mounted) begin
// update card size in case of a virtual SD image
if (sd_sdhc)
// CSD V1.0 size = (c_size + 1) * 512K
csdcid[69:48] <= {9'd0, img_size[31:19] };
else begin
// CSD V2.0 no. of blocks = c_size ** (c_size_mult + 2)
csdcid[49:47] <= 3'd7; //c_size_mult
csdcid[73:62] <= img_size[29:18]; //c_size
end
end
end
always@(posedge clk_sys) begin
reg old_sd_sck;
reg [5:0] ack;
ack <= {ack[4:0], sd_ack};
if(ack[5:4] == 'b01) { sd_rd, sd_wr } <= 2'b00;
if(ack[5:4] == 'b10) sd_busy <= 0;
buffer_write_strobe <= 0;
if (buffer_write_strobe) buffer_ptr <= buffer_ptr + 1'd1;
old_sd_sck <= sd_sck;
// advance transmitter state machine on falling sck edge, so data is valid on the
// rising edge
// ----------------- spi transmitter --------------------
if(sd_cs == 0 && old_sd_sck && ~sd_sck) begin
sd_sdo <= 1'b1; // default: send 1's (busy/wait)
if(byte_cnt == 5+NCR) begin
sd_sdo <= reply[~bit_cnt];
if(bit_cnt == 7) begin
// these three commands all have a reply_len of 0 and will thus
// not send more than a single reply byte
// CMD9: SEND_CSD
// CMD10: SEND_CID
if((cmd == 8'h49)||(cmd == 8'h4a))
read_state <= RD_STATE_SEND_TOKEN; // jump directly to data transmission
// CMD17: READ_SINGLE_BLOCK
if(cmd == 8'h51) begin
read_state <= RD_STATE_WAIT_IO; // start waiting for data from io controller
sd_rd <= 1; // trigger request to io controller
sd_busy <= 1;
end
end
end
else if((reply_len > 0) && (byte_cnt == 5+NCR+1))
sd_sdo <= reply0[~bit_cnt];
else if((reply_len > 1) && (byte_cnt == 5+NCR+2))
sd_sdo <= reply1[~bit_cnt];
else if((reply_len > 2) && (byte_cnt == 5+NCR+3))
sd_sdo <= reply2[~bit_cnt];
else if((reply_len > 3) && (byte_cnt == 5+NCR+4))
sd_sdo <= reply3[~bit_cnt];
else
sd_sdo <= 1'b1;
// ---------- read state machine processing -------------
case(read_state)
RD_STATE_IDLE: ;
// don't do anything
// waiting for io controller to return data
RD_STATE_WAIT_IO: begin
buffer_ptr <= 0;
if(~sd_busy && (bit_cnt == 7))
read_state <= RD_STATE_SEND_TOKEN;
end
// send data token
RD_STATE_SEND_TOKEN: begin
sd_sdo <= READ_DATA_TOKEN[~bit_cnt];
if(bit_cnt == 7) begin
read_state <= RD_STATE_SEND_DATA; // next: send data
conf_buff_ptr <= (cmd == 8'h4a) ? 5'h0 : 5'h10;
end
end
// send data
RD_STATE_SEND_DATA: begin
if(cmd == 8'h51) // CMD17: READ_SINGLE_BLOCK
sd_sdo <= buffer_dout[~bit_cnt];
else if(cmd == 8'h49) begin // CMD9: SEND_CSD
sd_sdo <= conf_byte[~bit_cnt];
end
else if(cmd == 8'h4a) // CMD10: SEND_CID
sd_sdo <= conf_byte[~bit_cnt];
else
sd_sdo <= 1'b1;
if(bit_cnt == 7) begin
// sent 512 sector data bytes?
if((cmd == 8'h51) && &buffer_ptr) // (buffer_ptr ==511))
read_state <= RD_STATE_IDLE; // next: send crc. It's ignored so return to idle state
// sent 16 cid/csd data bytes?
else if(((cmd == 8'h49)||(cmd == 8'h4a)) && conf_buff_ptr[3:0] == 4'h0f) // && (buffer_rptr == 16))
read_state <= RD_STATE_IDLE; // return to idle state
else begin
buffer_ptr <= buffer_ptr + 1'd1;
conf_buff_ptr<= conf_buff_ptr+ 1'd1;
end
end
end
endcase
// ------------------ write support ----------------------
// send write data response
if(write_state == WR_STATE_SEND_DRESP)
sd_sdo <= WRITE_DATA_RESPONSE[~bit_cnt];
// busy after write until the io controller sends ack
if(write_state == WR_STATE_BUSY)
sd_sdo <= 1'b0;
end
// spi receiver
// cs is active low
if(sd_cs == 1) begin
bit_cnt <= 3'd0;
end else if (~old_sd_sck & sd_sck) begin
bit_cnt <= bit_cnt + 3'd1;
// assemble byte
if(bit_cnt != 7)
sbuf[6:0] <= { sbuf[5:0], sd_sdi };
else begin
// finished reading one byte
// byte counter runs against 15 byte boundary
if(byte_cnt != 15)
byte_cnt <= byte_cnt + 4'd1;
// byte_cnt > 6 -> complete command received
// first byte of valid command is 01xxxxxx
// don't accept new commands once a write or read command has been accepted
if((byte_cnt > 5) && (write_state == WR_STATE_IDLE) &&
(read_state == RD_STATE_IDLE) && sbuf[6:5] == 2'b01) begin
byte_cnt <= 4'd0;
cmd <= { sbuf, sd_sdi};
// set cmd55 flag if previous command was 55
cmd55 <= (cmd == 8'h77);
end
// parse additional command bytes
if(byte_cnt == 0) args[39:32] <= { sbuf, sd_sdi};
if(byte_cnt == 1) args[31:24] <= { sbuf, sd_sdi};
if(byte_cnt == 2) args[23:16] <= { sbuf, sd_sdi};
if(byte_cnt == 3) args[15:8] <= { sbuf, sd_sdi};
if(byte_cnt == 4) args[7:0] <= { sbuf, sd_sdi};
// last byte received, evaluate
if(byte_cnt == 5) begin
// default:
reply <= 8'h04; // illegal command
reply_len <= 4'd0; // no extra reply bytes
// CMD0: GO_IDLE_STATE
if(cmd == 8'h40) begin
card_is_reset <= 1'b1;
reply <= 8'h01; // ok, busy
end
// every other command is only accepted after a reset
else if(card_is_reset) begin
case(cmd)
// CMD1: SEND_OP_COND
8'h41: reply <= 8'h00; // ok, not busy
// CMD8: SEND_IF_COND (V2 only)
8'h48: begin
reply <= 8'h01; // ok, busy
reply0 <= 8'h00;
reply1 <= 8'h00;
reply2 <= { 4'b0, args[19:16] };
reply3 <= args[15:8];
reply_len <= 4'd4;
end
// CMD9: SEND_CSD
8'h49: reply <= 8'h00; // ok
// CMD10: SEND_CID
8'h4a: reply <= 8'h00; // ok
// CMD16: SET_BLOCKLEN
8'h50:
// we only support a block size of 512
if(args[39:8] == 32'd512)
reply <= 8'h00; // ok
else
reply <= 8'h40; // parmeter error
// CMD17: READ_SINGLE_BLOCK
8'h51: reply <= 8'h00; // ok
// CMD24: WRITE_BLOCK
8'h58: begin
reply <= 8'h00; // ok
write_state <= WR_STATE_EXP_DTOKEN; // expect data token
end
// ACMD41: APP_SEND_OP_COND
8'h69: if(cmd55) begin
reply <= 8'h00; // ok, not busy
end
// CMD55: APP_COND
8'h77: reply <= 8'h01; // ok, busy
// CMD58: READ_OCR
8'h7a: begin
reply <= 8'h00; // ok
reply0 <= OCR[31:24]; // bit 30 = 1 -> high capacity card
reply1 <= OCR[23:16];
reply2 <= OCR[15:8];
reply3 <= OCR[7:0];
reply_len <= 4'd4;
end
endcase
end
end
// ---------- handle write -----------
case(write_state)
// don't do anything in idle state
WR_STATE_IDLE: ;
// waiting for data token
WR_STATE_EXP_DTOKEN:
if({ sbuf, sd_sdi} == 8'hfe ) begin
write_state <= WR_STATE_RECV_DATA;
buffer_ptr <= 9'd0;
end
// transfer 512 bytes
WR_STATE_RECV_DATA: begin
// push one byte into local buffer
buffer_write_strobe <= 1'b1;
buffer_din <= { sbuf, sd_sdi };
// all bytes written?
if(&buffer_ptr)
write_state <= WR_STATE_RECV_CRC0;
end
// transfer 1st crc byte
WR_STATE_RECV_CRC0:
write_state <= WR_STATE_RECV_CRC1;
// transfer 2nd crc byte
WR_STATE_RECV_CRC1:
write_state <= WR_STATE_SEND_DRESP;
// send data response
WR_STATE_SEND_DRESP: begin
write_state <= WR_STATE_BUSY;
sd_wr <= 1; // trigger write request to io ontroller
sd_busy <= 1;
end
// wait for io controller to accept data
WR_STATE_BUSY:
if(~sd_busy)
write_state <= WR_STATE_IDLE;
default: ;
endcase
end
end
end
endmodule
module sd_card_dpram #(parameter DATAWIDTH=8, ADDRWIDTH=9)
(
input clock_a,
input [ADDRWIDTH-1:0] address_a,
input [DATAWIDTH-1:0] data_a,
input wren_a,
output reg [DATAWIDTH-1:0] q_a,
input clock_b,
input [ADDRWIDTH-1:0] address_b,
input [DATAWIDTH-1:0] data_b,
input wren_b,
output reg [DATAWIDTH-1:0] q_b
);
reg [DATAWIDTH-1:0] ram[0:(1<<ADDRWIDTH)-1];
always @(posedge clock_a) begin
q_a <= ram[address_a];
if(wren_a) begin
q_a <= data_a;
ram[address_a] <= data_a;
end
end
always @(posedge clock_b) begin
q_b <= ram[address_b];
if(wren_b) begin
q_b <= data_b;
ram[address_b] <= data_b;
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_DFF_PS_BLACKBOX_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$PS (
Q ,
D ,
CLK,
SET
);
output Q ;
input D ;
input CLK;
input SET;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_PS_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _no_description_
// /___/ /\ Filename : FRAME_ECCE4.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module FRAME_ECCE4
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output CRCERROR,
output ECCERRORNOTSINGLE,
output ECCERRORSINGLE,
output ENDOFFRAME,
output ENDOFSCAN,
output [26:0] FAR,
input [1:0] FARSEL,
input ICAPBOTCLK,
input ICAPTOPCLK
);
endmodule
`endcelldefine
|
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ([email protected])
//
// Copyright (c) 2004,2007 Guy Hutchison ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80_mcode
(/*AUTOARG*/
// Outputs
MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg,
Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC,
Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ,
LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF,
ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR,
I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write,
// Inputs
IR, ISet, MCycle, F, NMICycle, IntCycle
);
parameter Mode = 3;
parameter Flag_C = 0;
parameter Flag_N = 1;
parameter Flag_P = 2;
parameter Flag_X = 3;
parameter Flag_H = 4;
parameter Flag_Y = 5;
parameter Flag_Z = 6;
parameter Flag_S = 7;
parameter Flag_GB_C = 4;
parameter Flag_GB_H = 5;
parameter Flag_GB_N = 6;
parameter Flag_GB_Z = 7;
input [7:0] IR;
input [1:0] ISet ;
input [6:0] MCycle ;
input [7:0] F ;
input NMICycle ;
input IntCycle ;
output [2:0] MCycles ;
output [2:0] TStates ;
output [1:0] Prefix ; // None,BC,ED,DD/FD
output Inc_PC ;
output Inc_WZ ;
output [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc
output Read_To_Reg ;
output Read_To_Acc ;
output [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
output [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
output [3:0] ALU_Op ;
output Save_ALU ;
output PreserveC ;
output Arith16 ;
output [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
output IORQ ;
output Jump ;
output JumpE ;
output JumpXY ;
output Call ;
output RstP ;
output LDZ ;
output LDW ;
output LDSPHL ;
output [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None
output ExchangeDH ;
output ExchangeRp ;
output ExchangeAF ;
output ExchangeRS ;
output I_DJNZ ;
output I_CPL ;
output I_CCF ;
output I_SCF ;
output I_RETN ;
output I_BT ;
output I_BC ;
output I_BTR ;
output I_RLD ;
output I_RRD ;
output I_INRC ;
output SetDI ;
output SetEI ;
output [1:0] IMode ;
output Halt ;
output NoRead ;
output Write ;
// regs
reg [2:0] MCycles ;
reg [2:0] TStates ;
reg [1:0] Prefix ; // None,BC,ED,DD/FD
reg Inc_PC ;
reg Inc_WZ ;
reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc
reg Read_To_Reg ;
reg Read_To_Acc ;
reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
reg [3:0] ALU_Op ;
reg Save_ALU ;
reg PreserveC ;
reg Arith16 ;
reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
reg IORQ ;
reg Jump ;
reg JumpE ;
reg JumpXY ;
reg Call ;
reg RstP ;
reg LDZ ;
reg LDW ;
reg LDSPHL ;
reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None
reg ExchangeDH ;
reg ExchangeRp ;
reg ExchangeAF ;
reg ExchangeRS ;
reg I_DJNZ ;
reg I_CPL ;
reg I_CCF ;
reg I_SCF ;
reg I_RETN ;
reg I_BT ;
reg I_BC ;
reg I_BTR ;
reg I_RLD ;
reg I_RRD ;
reg I_INRC ;
reg SetDI ;
reg SetEI ;
reg [1:0] IMode ;
reg Halt ;
reg NoRead ;
reg Write ;
parameter aNone = 3'b111;
parameter aBC = 3'b000;
parameter aDE = 3'b001;
parameter aXY = 3'b010;
parameter aIOA = 3'b100;
parameter aSP = 3'b101;
parameter aZI = 3'b110;
// constant aNone : std_logic_vector[2:0] = 3'b000;
// constant aXY : std_logic_vector[2:0] = 3'b001;
// constant aIOA : std_logic_vector[2:0] = 3'b010;
// constant aSP : std_logic_vector[2:0] = 3'b011;
// constant aBC : std_logic_vector[2:0] = 3'b100;
// constant aDE : std_logic_vector[2:0] = 3'b101;
// constant aZI : std_logic_vector[2:0] = 3'b110;
function is_cc_true;
input [7:0] F;
input [2:0] cc;
begin
if (Mode == 3 )
begin
case (cc)
3'b000 : is_cc_true = F[Flag_GB_Z] == 1'b0; // NZ
3'b001 : is_cc_true = F[Flag_GB_Z] == 1'b1; // Z
3'b010 : is_cc_true = F[Flag_GB_C] == 1'b0; // NC
3'b011 : is_cc_true = F[Flag_GB_C] == 1'b1; // C
3'b100 : is_cc_true = 0;
3'b101 : is_cc_true = 0;
3'b110 : is_cc_true = 0;
3'b111 : is_cc_true = 0;
endcase
end
else
begin
case (cc)
3'b000 : is_cc_true = F[6] == 1'b0; // NZ
3'b001 : is_cc_true = F[6] == 1'b1; // Z
3'b010 : is_cc_true = F[0] == 1'b0; // NC
3'b011 : is_cc_true = F[0] == 1'b1; // C
3'b100 : is_cc_true = F[2] == 1'b0; // PO
3'b101 : is_cc_true = F[2] == 1'b1; // PE
3'b110 : is_cc_true = F[7] == 1'b0; // P
3'b111 : is_cc_true = F[7] == 1'b1; // M
endcase
end
end
endfunction // is_cc_true
reg [2:0] DDD;
reg [2:0] SSS;
reg [1:0] DPAIR;
always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle
or NMICycle)
begin
DDD = IR[5:3];
SSS = IR[2:0];
DPAIR = IR[5:4];
MCycles = 3'b001;
if (MCycle[0] )
begin
TStates = 3'b100;
end
else
begin
TStates = 3'b011;
end
Prefix = 2'b00;
Inc_PC = 1'b0;
Inc_WZ = 1'b0;
IncDec_16 = 4'b0000;
Read_To_Acc = 1'b0;
Read_To_Reg = 1'b0;
Set_BusB_To = 4'b0000;
Set_BusA_To = 4'b0000;
ALU_Op = { 1'b0, IR[5:3] };
Save_ALU = 1'b0;
PreserveC = 1'b0;
Arith16 = 1'b0;
IORQ = 1'b0;
Set_Addr_To = aNone;
Jump = 1'b0;
JumpE = 1'b0;
JumpXY = 1'b0;
Call = 1'b0;
RstP = 1'b0;
LDZ = 1'b0;
LDW = 1'b0;
LDSPHL = 1'b0;
Special_LD = 3'b000;
ExchangeDH = 1'b0;
ExchangeRp = 1'b0;
ExchangeAF = 1'b0;
ExchangeRS = 1'b0;
I_DJNZ = 1'b0;
I_CPL = 1'b0;
I_CCF = 1'b0;
I_SCF = 1'b0;
I_RETN = 1'b0;
I_BT = 1'b0;
I_BC = 1'b0;
I_BTR = 1'b0;
I_RLD = 1'b0;
I_RRD = 1'b0;
I_INRC = 1'b0;
SetDI = 1'b0;
SetEI = 1'b0;
IMode = 2'b10; //2'b11
Halt = 1'b0;
NoRead = 1'b0;
Write = 1'b0;
case (ISet)
2'b00 :
begin
//----------------------------------------------------------------------------
//
// Unprefixed instructions
//
//----------------------------------------------------------------------------
casex (IR)
// 8 BIT LOAD GROUP
8'b01xxxxxx :
begin
if (IR[5:0] == 6'b110110)
Halt = 1'b1;
else if (IR[2:0] == 3'b110)
begin
// LD r,(HL)
MCycles = 3'b010;
if (MCycle[0])
Set_Addr_To = aXY;
if (MCycle[1])
begin
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
end
end // if (IR[2:0] == 3'b110)
else if (IR[5:3] == 3'b110)
begin
// LD (HL),r
MCycles = 3'b010;
if (MCycle[0])
begin
Set_Addr_To = aXY;
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
end
if (MCycle[1])
Write = 1'b1;
end // if (IR[5:3] == 3'b110)
else
begin
Set_BusB_To[2:0] = SSS;
ExchangeRp = 1'b1;
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
end // else: !if(IR[5:3] == 3'b110)
end // case: 8'b01xxxxxx
8'b00xxx110 :
begin
if (IR[5:3] == 3'b110)
begin
// LD (HL),n
MCycles = 3'b011;
if (MCycle[1])
begin
Inc_PC = 1'b1;
Set_Addr_To = aXY;
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
end
if (MCycle[2])
Write = 1'b1;
end // if (IR[5:3] == 3'b110)
else
begin
// LD r,n
MCycles = 3'b010;
if (MCycle[1])
begin
Inc_PC = 1'b1;
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
end
end
end
8'b00001010 :
begin
// LD A,(BC)
MCycles = 3'b010;
if (MCycle[0])
Set_Addr_To = aBC;
if (MCycle[1])
Read_To_Acc = 1'b1;
end // case: 8'b00001010
8'b00011010 :
begin
// LD A,(DE)
MCycles = 3'b010;
if (MCycle[0])
Set_Addr_To = aDE;
if (MCycle[1])
Read_To_Acc = 1'b1;
end // case: 8'b00011010
8'b00111010 :
begin
if (Mode == 3 )
begin
// LDD A,(HL)
MCycles = 3'b010;
if (MCycle[0])
Set_Addr_To = aXY;
if (MCycle[1])
begin
Read_To_Acc = 1'b1;
IncDec_16 = 4'b1110;
end
end
else
begin
// LD A,(nn)
MCycles = 3'b100;
if (MCycle[1])
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
if (MCycle[2])
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
end
if (MCycle[3])
begin
Read_To_Acc = 1'b1;
end
end // else: !if(Mode == 3 )
end // case: 8'b00111010
8'b00000010 :
begin
// LD (BC),A
MCycles = 3'b010;
if (MCycle[0])
begin
Set_Addr_To = aBC;
Set_BusB_To = 4'b0111;
end
if (MCycle[1])
begin
Write = 1'b1;
end
end // case: 8'b00000010
8'b00010010 :
begin
// LD (DE),A
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aDE;
Set_BusB_To = 4'b0111;
end
MCycle[1] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b00010010
8'b00110010 :
begin
if (Mode == 3 )
begin
// LDD (HL),A
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
Set_BusB_To = 4'b0111;
end
MCycle[1] :
begin
Write = 1'b1;
IncDec_16 = 4'b1110;
end
default :;
endcase // case(MCycle)
end
else
begin
// LD (nn),A
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
Set_BusB_To = 4'b0111;
end
MCycle[3] :
begin
Write = 1'b1;
end
default :;
endcase
end // else: !if(Mode == 3 )
end // case: 8'b00110010
// 16 BIT LOAD GROUP
8'b00000001,8'b00010001,8'b00100001,8'b00110001 :
begin
// LD dd,nn
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Read_To_Reg = 1'b1;
if (DPAIR == 2'b11 )
begin
Set_BusA_To[3:0] = 4'b1000;
end
else
begin
Set_BusA_To[2:1] = DPAIR;
Set_BusA_To[0] = 1'b1;
end
end // case: 2
MCycle[2] :
begin
Inc_PC = 1'b1;
Read_To_Reg = 1'b1;
if (DPAIR == 2'b11 )
begin
Set_BusA_To[3:0] = 4'b1001;
end
else
begin
Set_BusA_To[2:1] = DPAIR;
Set_BusA_To[0] = 1'b0;
end
end // case: 3
default :;
endcase // case(MCycle)
end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001
8'b00101010 :
begin
if (Mode == 3 )
begin
// LDI A,(HL)
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
MCycle[1] :
begin
Read_To_Acc = 1'b1;
IncDec_16 = 4'b0110;
end
default :;
endcase
end
else
begin
// LD HL,(nn)
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
end
MCycle[3] :
begin
Set_BusA_To[2:0] = 3'b101; // L
Read_To_Reg = 1'b1;
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
end
MCycle[4] :
begin
Set_BusA_To[2:0] = 3'b100; // H
Read_To_Reg = 1'b1;
end
default :;
endcase
end // else: !if(Mode == 3 )
end // case: 8'b00101010
8'b00100010 :
begin
if (Mode == 3 )
begin
// LDI (HL),A
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
Set_BusB_To = 4'b0111;
end
MCycle[1] :
begin
Write = 1'b1;
IncDec_16 = 4'b0110;
end
default :;
endcase
end
else
begin
// LD (nn),HL
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
Set_BusB_To = 4'b0101; // L
end
MCycle[3] :
begin
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
Write = 1'b1;
Set_BusB_To = 4'b0100; // H
end
MCycle[4] :
Write = 1'b1;
default :;
endcase
end // else: !if(Mode == 3 )
end // case: 8'b00100010
8'b11111001 :
begin
// LD SP,HL
TStates = 3'b110;
LDSPHL = 1'b1;
end
8'b11xx0101 :
begin
// PUSH qq
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
if (DPAIR == 2'b11 )
begin
Set_BusB_To = 4'b0111;
end
else
begin
Set_BusB_To[2:1] = DPAIR;
Set_BusB_To[0] = 1'b0;
Set_BusB_To[3] = 1'b0;
end
end // case: 1
MCycle[1] :
begin
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
if (DPAIR == 2'b11 )
begin
Set_BusB_To = 4'b1011;
end
else
begin
Set_BusB_To[2:1] = DPAIR;
Set_BusB_To[0] = 1'b1;
Set_BusB_To[3] = 1'b0;
end
Write = 1'b1;
end // case: 2
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
8'b11xx0001 :
begin
// POP qq
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
Read_To_Reg = 1'b1;
if (DPAIR == 2'b11 )
begin
Set_BusA_To[3:0] = 4'b1011;
end
else
begin
Set_BusA_To[2:1] = DPAIR;
Set_BusA_To[0] = 1'b1;
end
end // case: 2
MCycle[2] :
begin
IncDec_16 = 4'b0111;
Read_To_Reg = 1'b1;
if (DPAIR == 2'b11 )
begin
Set_BusA_To[3:0] = 4'b0111;
end
else
begin
Set_BusA_To[2:1] = DPAIR;
Set_BusA_To[0] = 1'b0;
end
end // case: 3
default :;
endcase // case(MCycle)
end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001
// EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
8'b11101011 :
begin
if (Mode != 3 )
begin
// EX DE,HL
ExchangeDH = 1'b1;
end
end
8'b00001000 :
begin
if (Mode == 3 )
begin
// LD (nn),SP
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
Set_BusB_To = 4'b1000;
end
MCycle[3] :
begin
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
Write = 1'b1;
Set_BusB_To = 4'b1001;
end
MCycle[4] :
Write = 1'b1;
default :;
endcase
end
else if (Mode < 2 )
begin
// EX AF,AF'
ExchangeAF = 1'b1;
end
end // case: 8'b00001000
8'b11011001 :
begin
if (Mode == 3 )
begin
// RETI
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
LDZ = 1'b1;
end
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
I_RETN = 1'b1; // GameBoy -- Remove to reenable FF1
SetEI = 1'b1;
end
default :;
endcase
end
else if (Mode < 2 )
begin
// EXX
ExchangeRS = 1'b1;
end
end // case: 8'b11011001
8'b11100011 :
begin
if (Mode != 3 )
begin
// EX (SP),HL
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
MCycle[1] :
begin
Read_To_Reg = 1'b1;
Set_BusA_To = 4'b0101;
Set_BusB_To = 4'b0101;
Set_Addr_To = aSP;
end
MCycle[2] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
TStates = 3'b100;
Write = 1'b1;
end
MCycle[3] :
begin
Read_To_Reg = 1'b1;
Set_BusA_To = 4'b0100;
Set_BusB_To = 4'b0100;
Set_Addr_To = aSP;
end
MCycle[4] :
begin
IncDec_16 = 4'b1111;
TStates = 3'b101;
Write = 1'b1;
end
default :;
endcase
end // if (Mode != 3 )
end // case: 8'b11100011
// 8 BIT ARITHMETIC AND LOGICAL GROUP
8'b10xxxxxx :
begin
if (IR[2:0] == 3'b110)
begin
// ADD A,(HL)
// ADC A,(HL)
// SUB A,(HL)
// SBC A,(HL)
// AND A,(HL)
// OR A,(HL)
// XOR A,(HL)
// CP A,(HL)
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
MCycle[1] :
begin
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusB_To[2:0] = SSS;
Set_BusA_To[2:0] = 3'b111;
end
default :;
endcase // case(MCycle)
end // if (IR[2:0] == 3'b110)
else
begin
// ADD A,r
// ADC A,r
// SUB A,r
// SBC A,r
// AND A,r
// OR A,r
// XOR A,r
// CP A,r
Set_BusB_To[2:0] = SSS;
Set_BusA_To[2:0] = 3'b111;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
end // else: !if(IR[2:0] == 3'b110)
end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
8'b11xxx110 :
begin
// ADD A,n
// ADC A,n
// SUB A,n
// SBC A,n
// AND A,n
// OR A,n
// XOR A,n
// CP A,n
MCycles = 3'b010;
if (MCycle[1] )
begin
Inc_PC = 1'b1;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusB_To[2:0] = SSS;
Set_BusA_To[2:0] = 3'b111;
end
end
8'b00xxx100 :
begin
if (IR[5:3] == 3'b110)
begin
// INC (HL)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
MCycle[1] :
begin
TStates = 3'b100;
Set_Addr_To = aXY;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
PreserveC = 1'b1;
ALU_Op = 4'b0000;
Set_BusB_To = 4'b1010;
Set_BusA_To[2:0] = DDD;
end // case: 2
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b00110100
else
begin
// INC r
Set_BusB_To = 4'b1010;
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
PreserveC = 1'b1;
ALU_Op = 4'b0000;
end
end
8'b00xxx101 :
begin
if (IR[5:3] == 3'b110)
begin
// DEC (HL)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
MCycle[1] :
begin
TStates = 3'b100;
Set_Addr_To = aXY;
ALU_Op = 4'b0010;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
PreserveC = 1'b1;
Set_BusB_To = 4'b1010;
Set_BusA_To[2:0] = DDD;
end // case: 2
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end
else
begin
// DEC r
Set_BusB_To = 4'b1010;
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
PreserveC = 1'b1;
ALU_Op = 4'b0010;
end
end
// GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
8'b00100111 :
begin
// DAA
Set_BusA_To[2:0] = 3'b111;
Read_To_Reg = 1'b1;
ALU_Op = 4'b1100;
Save_ALU = 1'b1;
end
8'b00101111 :
// CPL
I_CPL = 1'b1;
8'b00111111 :
// CCF
I_CCF = 1'b1;
8'b00110111 :
// SCF
I_SCF = 1'b1;
8'b00000000 :
begin
if (NMICycle == 1'b1 )
begin
// NMI
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1101;
end
MCycle[1] :
begin
TStates = 3'b100;
Write = 1'b1;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1100;
end
MCycle[2] :
begin
TStates = 3'b100;
Write = 1'b1;
end
default :;
endcase // case(MCycle)
end
else if (IntCycle == 1'b1 )
begin
// INT (IM 2)
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[0] :
begin
LDZ = 1'b1;
TStates = 3'b101;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1101;
end
MCycle[1] :
begin
TStates = 3'b100;
Write = 1'b1;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1100;
end
MCycle[2] :
begin
TStates = 3'b100;
Write = 1'b1;
end
MCycle[3] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[4] :
Jump = 1'b1;
default :;
endcase
end
end // case: 8'b00000000
8'b11110011 :
// DI
SetDI = 1'b1;
8'b11111011 :
// EI
SetEI = 1'b1;
// 16 BIT ARITHMETIC GROUP
8'b00xx1001 :
begin
// ADD HL,ss
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusA_To[2:0] = 3'b101;
case (IR[5:4])
0,1,2 :
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b1;
end
default :
Set_BusB_To = 4'b1000;
endcase // case(IR[5:4])
TStates = 3'b100;
Arith16 = 1'b1;
end // case: 2
MCycle[2] :
begin
NoRead = 1'b1;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0001;
Set_BusA_To[2:0] = 3'b100;
case (IR[5:4])
0,1,2 :
begin
Set_BusB_To[2:1] = IR[5:4];
end
default :
Set_BusB_To = 4'b1001;
endcase
Arith16 = 1'b1;
end // case: 3
default :;
endcase // case(MCycle)
end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001
8'b00xx0011 :
begin
// INC ss
TStates = 3'b110;
IncDec_16[3:2] = 2'b01;
IncDec_16[1:0] = DPAIR;
end
8'b00xx1011 :
begin
// DEC ss
TStates = 3'b110;
IncDec_16[3:2] = 2'b11;
IncDec_16[1:0] = DPAIR;
end
// ROTATE AND SHIFT GROUP
8'b00000111,
// RLCA
8'b00010111,
// RLA
8'b00001111,
// RRCA
8'b00011111 :
// RRA
begin
Set_BusA_To[2:0] = 3'b111;
ALU_Op = 4'b1000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
end // case: 8'b00000111,...
// JUMP GROUP
8'b11000011 :
begin
// JP nn
MCycles = 3'b011;
if (MCycle[1])
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
if (MCycle[2])
begin
Inc_PC = 1'b1;
Jump = 1'b1;
end
end // case: 8'b11000011
8'b11xxx010 :
begin
if (IR[5] == 1'b1 && Mode == 3 )
begin
case (IR[4:3])
2'b00 :
begin
// LD ($FF00+C),A
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
begin
IORQ = 1'b1; // GameBoy -- Added (was in wrong mcycle)
Set_Addr_To = aBC;
Set_BusB_To = 4'b0111;
end
MCycle[1] :
begin
Write = 1'b1;
//IORQ = 1'b1; // GameBoy -- Removed (wrong mcycle)
end
default :;
endcase // case(MCycle)
end // case: 2'b00
2'b01 :
begin
// LD (nn),A
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
Set_BusB_To = 4'b0111;
end
MCycle[3] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: default :...
2'b10 :
begin
// LD A,($FF00+C)
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aBC;
MCycle[1] :
begin
Read_To_Acc = 1'b1;
IORQ = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 2'b10
2'b11 :
begin
// LD A,(nn)
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
end
MCycle[3] :
Read_To_Acc = 1'b1;
default :;
endcase // case(MCycle)
end
endcase
end
else
begin
// JP cc,nn
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Inc_PC = 1'b1;
if (is_cc_true(F, IR[5:3]) )
begin
Jump = 1'b1;
end
end
default :;
endcase
end // else: !if(DPAIR == 2'b11 )
end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010
8'b00011000 :
begin
if (Mode != 2 )
begin
// JR e
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
Inc_PC = 1'b1;
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
TStates = 3'b101;
end
default :;
endcase
end // if (Mode != 2 )
end // case: 8'b00011000
// Conditional relative jumps (JR [C/NC/Z/NZ], e)
8'b001xx000 :
begin
if (Mode != 2 )
begin
MCycles = 3'd3;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
case (IR[4:3])
0 : MCycles = (F[Flag_Z]) ? 3'd2 : 3'd3;
1 : MCycles = (!F[Flag_Z]) ? 3'd2 : 3'd3;
2 : MCycles = (F[Flag_C]) ? 3'd2 : 3'd3;
3 : MCycles = (!F[Flag_C]) ? 3'd2 : 3'd3;
endcase
end
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
TStates = 3'd5;
end
default :;
endcase
end // if (Mode != 2 )
end // case: 8'b00111000
8'b11101001 :
// JP (HL)
JumpXY = 1'b1;
8'b00010000 :
begin
if (Mode == 3 )
begin
I_DJNZ = 1'b1;
end
else if (Mode < 2 )
begin
// DJNZ,e
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
I_DJNZ = 1'b1;
Set_BusB_To = 4'b1010;
Set_BusA_To[2:0] = 3'b000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0010;
end
MCycle[1] :
begin
I_DJNZ = 1'b1;
Inc_PC = 1'b1;
end
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
TStates = 3'b101;
end
default :;
endcase
end // if (Mode < 2 )
end // case: 8'b00010000
// CALL AND RETURN GROUP
8'b11001101 :
begin
// CALL nn
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
IncDec_16 = 4'b1111;
Inc_PC = 1'b1;
TStates = 3'b100;
Set_Addr_To = aSP;
LDW = 1'b1;
Set_BusB_To = 4'b1101;
end
MCycle[3] :
begin
Write = 1'b1;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1100;
end
MCycle[4] :
begin
Write = 1'b1;
Call = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b11001101
8'b11xxx100 :
begin
if (IR[5] == 1'b0 || Mode != 3 )
begin
// CALL cc,nn
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Inc_PC = 1'b1;
LDW = 1'b1;
if (is_cc_true(F, IR[5:3]) )
begin
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
TStates = 3'b100;
Set_BusB_To = 4'b1101;
end
else
begin
MCycles = 3'b011;
end // else: !if(is_cc_true(F, IR[5:3]) )
end // case: 3
MCycle[3] :
begin
Write = 1'b1;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1100;
end
MCycle[4] :
begin
Write = 1'b1;
Call = 1'b1;
end
default :;
endcase
end // if (IR[5] == 1'b0 || Mode != 3 )
end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100
8'b11001001 :
begin
// RET
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
Set_Addr_To = aSP;
end
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
LDZ = 1'b1;
end
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
end
default :;
endcase // case(MCycle)
end // case: 8'b11001001
8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 :
begin
if (IR[5] == 1'b1 && Mode == 3 )
begin
case (IR[4:3])
2'b00 :
begin
// LD ($FF00+nn),A
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
Set_BusB_To = 4'b0111;
end
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 2'b00
2'b01 :
begin
// ADD SP,n
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
ALU_Op = 4'b0000;
Inc_PC = 1'b1;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusA_To = 4'b1000;
Set_BusB_To = 4'b0110;
end
MCycle[2] :
begin
NoRead = 1'b1;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0001;
Set_BusA_To = 4'b1001;
Set_BusB_To = 4'b1110; // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
end
default :;
endcase // case(MCycle)
end // case: 2'b01
2'b10 :
begin
// LD A,($FF00+nn)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
end
MCycle[2] :
Read_To_Acc = 1'b1;
default :;
endcase // case(MCycle)
end // case: 2'b10
2'b11 :
begin
// LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
end
MCycle[3] :
begin
Set_BusA_To[2:0] = 3'b101; // L
Read_To_Reg = 1'b1;
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
end
MCycle[4] :
begin
Set_BusA_To[2:0] = 3'b100; // H
Read_To_Reg = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 2'b11
endcase // case(IR[4:3])
end
else
begin
// RET cc
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
if (is_cc_true(F, IR[5:3]) )
begin
Set_Addr_To = aSP;
end
else
begin
MCycles = 3'b001;
end
TStates = 3'b101;
end // case: 1
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
LDZ = 1'b1;
end
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
end
default :;
endcase
end // else: !if(IR[5] == 1'b1 && Mode == 3 )
end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000
8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 :
begin
// RST p
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1101;
end
MCycle[1] :
begin
Write = 1'b1;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1100;
end
MCycle[2] :
begin
Write = 1'b1;
RstP = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111
// INPUT AND OUTPUT GROUP
8'b11011011 :
begin
if (Mode != 3 )
begin
// IN A,(n)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
end
MCycle[2] :
begin
Read_To_Acc = 1'b1;
IORQ = 1'b1;
end
default :;
endcase
end // if (Mode != 3 )
end // case: 8'b11011011
8'b11010011 :
begin
if (Mode != 3 )
begin
// OUT (n),A
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
Set_BusB_To = 4'b0111;
end
MCycle[2] :
begin
Write = 1'b1;
IORQ = 1'b1;
end
default :;
endcase
end // if (Mode != 3 )
end // case: 8'b11010011
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// MULTIBYTE INSTRUCTIONS
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
8'b11001011 :
begin
if (Mode != 2 )
begin
Prefix = 2'b01;
end
end
8'b11101101 :
begin
if (Mode < 2 )
begin
Prefix = 2'b10;
end
end
8'b11011101,8'b11111101 :
begin
if (Mode < 2 )
begin
Prefix = 2'b11;
end
end
endcase // case(IR)
end // case: 2'b00
2'b01 :
begin
//----------------------------------------------------------------------------
//
// CB prefixed instructions
//
//----------------------------------------------------------------------------
Set_BusA_To[2:0] = IR[2:0];
Set_BusB_To[2:0] = IR[2:0];
casex (IR)
8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111,
8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111,
8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111,
8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111,
8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 :
begin
// RLC r
// RL r
// RRC r
// RR r
// SLA r
// SRA r
// SRL r
// SLL r (Undocumented) / SWAP r
if (MCycle[0] ) begin
ALU_Op = 4'b1000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
end
end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
8'b00xxx110 :
begin
// RLC (HL)
// RL (HL)
// RRC (HL)
// RR (HL)
// SRA (HL)
// SRL (HL)
// SLA (HL)
// SLL (HL) (Undocumented) / SWAP (HL)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
MCycle[1] :
begin
ALU_Op = 4'b1000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_Addr_To = aXY;
TStates = 3'b100;
end
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110
8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111,
8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
begin
// BIT b,r
if (MCycle[0] )
begin
Set_BusB_To[2:0] = IR[2:0];
ALU_Op = 4'b1001;
end
end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 :
begin
// BIT b,(HL)
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
MCycle[1] :
begin
ALU_Op = 4'b1001;
TStates = 3'b100;
end
default :;
endcase // case(MCycle)
end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110
8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,
8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111,
8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111,
8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111,
8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111,
8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111,
8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111,
8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 :
begin
// SET b,r
if (MCycle[0] )
begin
ALU_Op = 4'b1010;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
end
end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,...
8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 :
begin
// SET b,(HL)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
MCycle[1] :
begin
ALU_Op = 4'b1010;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_Addr_To = aXY;
TStates = 3'b100;
end
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
begin
// RES b,r
if (MCycle[0] )
begin
ALU_Op = 4'b1011;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
end
end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 :
begin
// RES b,(HL)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
MCycle[1] :
begin
ALU_Op = 4'b1011;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_Addr_To = aXY;
TStates = 3'b100;
end
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
endcase // case(IR)
end // case: 2'b01
default :
begin : default_ed_block
//----------------------------------------------------------------------------
//
// ED prefixed instructions
//
//----------------------------------------------------------------------------
casex (IR)
/*
* Undocumented NOP instructions commented out to reduce size of mcode
*
8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111
,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111
,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111
,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111
,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111
,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111
,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111
,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111
,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111
,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111
,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111
,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111
, 8'b10100100,8'b10100101,8'b10100110,8'b10100111
, 8'b10101100,8'b10101101,8'b10101110,8'b10101111
, 8'b10110100,8'b10110101,8'b10110110,8'b10110111
, 8'b10111100,8'b10111101,8'b10111110,8'b10111111
,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111
,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111
,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111
,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111
,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111
,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111
,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111
,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 :
; // NOP, undocumented
8'b01111110,8'b01111111 :
// NOP, undocumented
;
*/
// 8 BIT LOAD GROUP
8'b01010111 :
begin
// LD A,I
Special_LD = 3'b100;
TStates = 3'b101;
end
8'b01011111 :
begin
// LD A,R
Special_LD = 3'b101;
TStates = 3'b101;
end
8'b01000111 :
begin
// LD I,A
Special_LD = 3'b110;
TStates = 3'b101;
end
8'b01001111 :
begin
// LD R,A
Special_LD = 3'b111;
TStates = 3'b101;
end
// 16 BIT LOAD GROUP
8'b01001011,8'b01011011,8'b01101011,8'b01111011 :
begin
// LD dd,(nn)
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
end
MCycle[3] :
begin
Read_To_Reg = 1'b1;
if (IR[5:4] == 2'b11 )
begin
Set_BusA_To = 4'b1000;
end
else
begin
Set_BusA_To[2:1] = IR[5:4];
Set_BusA_To[0] = 1'b1;
end
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
end // case: 4
MCycle[4] :
begin
Read_To_Reg = 1'b1;
if (IR[5:4] == 2'b11 )
begin
Set_BusA_To = 4'b1001;
end
else
begin
Set_BusA_To[2:1] = IR[5:4];
Set_BusA_To[0] = 1'b0;
end
end // case: 5
default :;
endcase // case(MCycle)
end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011
8'b01000011,8'b01010011,8'b01100011,8'b01110011 :
begin
// LD (nn),dd
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
if (IR[5:4] == 2'b11 )
begin
Set_BusB_To = 4'b1000;
end
else
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b1;
Set_BusB_To[3] = 1'b0;
end
end // case: 3
MCycle[3] :
begin
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
Write = 1'b1;
if (IR[5:4] == 2'b11 )
begin
Set_BusB_To = 4'b1001;
end
else
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b0;
Set_BusB_To[3] = 1'b0;
end
end // case: 4
MCycle[4] :
begin
Write = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011
8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 :
begin
// LDI, LDD, LDIR, LDDR
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
IncDec_16 = 4'b1100; // BC
end
MCycle[1] :
begin
Set_BusB_To = 4'b0110;
Set_BusA_To[2:0] = 3'b111;
ALU_Op = 4'b0000;
Set_Addr_To = aDE;
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0110; // IX
end
else
begin
IncDec_16 = 4'b1110;
end
end // case: 2
MCycle[2] :
begin
I_BT = 1'b1;
TStates = 3'b101;
Write = 1'b1;
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0101; // DE
end
else
begin
IncDec_16 = 4'b1101;
end
end // case: 3
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
end
default :;
endcase // case(MCycle)
end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000
8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 :
begin
// CPI, CPD, CPIR, CPDR
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
IncDec_16 = 4'b1100; // BC
end
MCycle[1] :
begin
Set_BusB_To = 4'b0110;
Set_BusA_To[2:0] = 3'b111;
ALU_Op = 4'b0111;
Save_ALU = 1'b1;
PreserveC = 1'b1;
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0110;
end
else
begin
IncDec_16 = 4'b1110;
end
end // case: 2
MCycle[2] :
begin
NoRead = 1'b1;
I_BC = 1'b1;
TStates = 3'b101;
end
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
end
default :;
endcase // case(MCycle)
end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001
8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100 :
begin
// NEG
ALU_Op = 4'b0010;
Set_BusB_To = 4'b0111;
Set_BusA_To = 4'b1010;
Read_To_Acc = 1'b1;
Save_ALU = 1'b1;
end
8'b01000110,8'b01001110,8'b01100110,8'b01101110 :
begin
// IM 0
IMode = 2'b00;
end
8'b01010110,8'b01110110 :
// IM 1
IMode = 2'b01;
8'b01011110,8'b01110111 :
// IM 2
IMode = 2'b10;
// 16 bit arithmetic
8'b01001010,8'b01011010,8'b01101010,8'b01111010 :
begin
// ADC HL,ss
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0001;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusA_To[2:0] = 3'b101;
case (IR[5:4])
0,1,2 :
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b1;
end
default :
Set_BusB_To = 4'b1000;
endcase
TStates = 3'b100;
end // case: 2
MCycle[2] :
begin
NoRead = 1'b1;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0001;
Set_BusA_To[2:0] = 3'b100;
case (IR[5:4])
0,1,2 :
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b0;
end
default :
Set_BusB_To = 4'b1001;
endcase // case(IR[5:4])
end // case: 3
default :;
endcase // case(MCycle)
end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010
8'b01000010,8'b01010010,8'b01100010,8'b01110010 :
begin
// SBC HL,ss
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0011;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusA_To[2:0] = 3'b101;
case (IR[5:4])
0,1,2 :
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b1;
end
default :
Set_BusB_To = 4'b1000;
endcase
TStates = 3'b100;
end // case: 2
MCycle[2] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0011;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusA_To[2:0] = 3'b100;
case (IR[5:4])
0,1,2 :
Set_BusB_To[2:1] = IR[5:4];
default :
Set_BusB_To = 4'b1001;
endcase
end // case: 3
default :;
endcase // case(MCycle)
end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010
8'b01101111 :
begin
// RLD
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
Set_Addr_To = aXY;
end
MCycle[2] :
begin
Read_To_Reg = 1'b1;
Set_BusB_To[2:0] = 3'b110;
Set_BusA_To[2:0] = 3'b111;
ALU_Op = 4'b1101;
TStates = 3'b100;
Set_Addr_To = aXY;
Save_ALU = 1'b1;
end
MCycle[3] :
begin
I_RLD = 1'b1;
Write = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01101111
8'b01100111 :
begin
// RRD
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[1] :
Set_Addr_To = aXY;
MCycle[2] :
begin
Read_To_Reg = 1'b1;
Set_BusB_To[2:0] = 3'b110;
Set_BusA_To[2:0] = 3'b111;
ALU_Op = 4'b1110;
TStates = 3'b100;
Set_Addr_To = aXY;
Save_ALU = 1'b1;
end
MCycle[3] :
begin
I_RRD = 1'b1;
Write = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01100111
8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 :
begin
// RETI, RETN
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
LDZ = 1'b1;
end
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
I_RETN = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101
8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 :
begin
// IN r,(C)
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aBC;
MCycle[1] :
begin
IORQ = 1'b1;
if (IR[5:3] != 3'b110 )
begin
Read_To_Reg = 1'b1;
Set_BusA_To[2:0] = IR[5:3];
end
I_INRC = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000
8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 :
begin
// OUT (C),r
// OUT (C),0
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aBC;
Set_BusB_To[2:0] = IR[5:3];
if (IR[5:3] == 3'b110 )
begin
Set_BusB_To[3] = 1'b1;
end
end
MCycle[1] :
begin
Write = 1'b1;
IORQ = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001
8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 :
begin
// INI, IND, INIR, INDR
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aBC;
Set_BusB_To = 4'b1010;
Set_BusA_To = 4'b0000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0010;
end
MCycle[1] :
begin
IORQ = 1'b1;
Set_BusB_To = 4'b0110;
Set_Addr_To = aXY;
end
MCycle[2] :
begin
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0110;
end
else
begin
IncDec_16 = 4'b1110;
end
TStates = 3'b100;
Write = 1'b1;
I_BTR = 1'b1;
end // case: 3
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
end
default :;
endcase // case(MCycle)
end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010
8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 :
begin
// OUTI, OUTD, OTIR, OTDR
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
Set_Addr_To = aXY;
Set_BusB_To = 4'b1010;
Set_BusA_To = 4'b0000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0010;
end
MCycle[1] :
begin
Set_BusB_To = 4'b0110;
Set_Addr_To = aBC;
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0110;
end
else
begin
IncDec_16 = 4'b1110;
end
end
MCycle[2] :
begin
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0010;
end
else
begin
IncDec_16 = 4'b1010;
end
IORQ = 1'b1;
Write = 1'b1;
I_BTR = 1'b1;
end // case: 3
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
end
default :;
endcase // case(MCycle)
end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
endcase // case(IR)
end // block: default_ed_block
endcase // case(ISet)
if (Mode == 1 )
begin
if (MCycle[0] )
begin
//TStates = 3'b100;
end
else
begin
TStates = 3'b011;
end
end
if (Mode == 3 )
begin
if (MCycle[0] )
begin
//TStates = 3'b100;
end
else
begin
TStates = 3'b100;
end
end
if (Mode < 2 )
begin
if (MCycle[5] )
begin
Inc_PC = 1'b1;
if (Mode == 1 )
begin
Set_Addr_To = aXY;
TStates = 3'b100;
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
end
if (IR == 8'b00110110 || IR == 8'b11001011 )
begin
Set_Addr_To = aNone;
end
end
if (MCycle[6] )
begin
if (Mode == 0 )
begin
TStates = 3'b101;
end
if (ISet != 2'b01 )
begin
Set_Addr_To = aXY;
end
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
if (IR == 8'b00110110 || ISet == 2'b01 )
begin
// LD (HL),n
Inc_PC = 1'b1;
end
else
begin
NoRead = 1'b1;
end
end
end // if (Mode < 2 )
end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
endmodule // T80_MCode
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: top_nto1_ddr_se_tx.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: June 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: Example single ended output transmitter for DDR clock and data using 2 x BUFIO2
// Serdes factor and number of data lines are set by constants in the code
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
//
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module top_nto1_ddr_se_tx (
input reset, // reset (active high)
input refclkin_p, refclkin_n, // frequency generator clock input
output [7:0] dataout, // single ended data outputs
output clkout) ; // single ended clock output
// Parameters for serdes factor and number of IO pins
parameter integer S = 8 ; // Set the serdes factor
parameter integer D = 8 ; // Set the number of inputs and outputs
parameter integer DS = (D*S)-1 ; // Used for bus widths = serdes factor * number of inputs - 1
wire rst ;
reg [DS:0] txd ; // Registered Data to serdeses
// Parameters for clock generation
parameter [S-1:0] TX_CLK_GEN = 8'hAA ; // Transmit a constant to make a clock
assign rst = reset ; // active high reset pin
// Reference Clock Input genertaes IO clocks via 2 x BUFIO2
clock_generator_ddr_s8_diff #(
.S (S))
inst_clkgen(
.clkin_p (refclkin_p),
.clkin_n (refclkin_n),
.ioclkap (txioclkp),
.ioclkan (txioclkn),
.serdesstrobea (tx_serdesstrobe),
.ioclkbp (),
.ioclkbn (),
.serdesstrobeb (),
.gclk (tx_bufg_x1)) ;
always @ (posedge tx_bufg_x1 or posedge rst) // Generate some data to transmit
begin
if (rst == 1'b1) begin
txd <= 64'h3000000000000001 ;
end
else begin
txd <= {txd[63:60], txd[58:0], txd[59]} ;
end
end
// Transmitter Logic - Instantiate serialiser to generate forwarded clock
serdes_n_to_1_ddr_s8_se #(
.S (S),
.D (1))
inst_clkout (
.dataout (clkout),
.txioclkp (txioclkp),
.txioclkn (txioclkn),
.txserdesstrobe (tx_serdesstrobe),
.gclk (tx_bufg_x1),
.reset (rst),
.datain (TX_CLK_GEN)); // Transmit a constant to make the clock
// Instantiate Outputs and output serialisers for output data lines
serdes_n_to_1_ddr_s8_se #(
.S (S),
.D (D))
inst_dataout (
.dataout (dataout),
.txioclkp (txioclkp),
.txioclkn (txioclkn),
.txserdesstrobe (tx_serdesstrobe),
.gclk (tx_bufg_x1),
.reset (rst),
.datain (txd));
endmodule
|
module ARM_CU_ALU_TestBench;
parameter sim_time = 750*2; // Num of Cycles * 2
wire [17:0] signals;
wire IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode;
wire [3:0] CU;
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;
//ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output[3:0] CU, input MFC, Reset,Clk);
ControlUnit cu(IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);
reg [31:0] A,B;
reg [3:0] FLAGS;
reg S,ALU_OUT;
wire [31:0] Out;
wire [3:0] FLAGS_OUT;
//ARM_ALU(input wire [31:0] A,B,input wire[4:0] OP,input wire [3:0] FLAGS,output wire [31:0] Out,output wire [3:0] FLAGS_OUT, input wire S,ALU_OUT,);
ARM_ALU alu(A,B, opcode, FLAGS, Out,FLAGS_OUT,S,ALUSTORE);
reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);
initial fork
MFC = 0; Reset=1 ; Clk=0 ; FLAGS =0;
#1 MFC = 1;#1 Reset=0 ;#1 A=1; #1 B=0; #1 FLAGS=FLAGS_OUT;#1 S=1;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("ARM_CU_ALU_TestBench.vcd");
$dumpvars(0,ARM_CU_ALU_TestBench);
$display(" Test Results" );
$monitor("A=%4h,B=%4h,opcode=%3d,Out=%3h,FLAGS_OUT=%3d,FLAGS=%3d,S=%3d,ALUSTORE=%3d",A,B,opcode,Out,FLAGS_OUT,FLAGS,S,ALUSTORE);
end
endmodule
//iverilog ARM_ALU.v controlunit.v Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile.v ARM_CU_ALU_TestBench.v |
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 256 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Store buffer
// FUNCTION: FIFO - buffer with direct input order and 8-th inverse output order
// FILES: [email protected] - 1-st,2-nd,3-d data buffer, contains:
// RAM2x256C.v - dual ported synchronous RAM, contains:
// RAM256.v -single ported synchronous RAM
// PROPERTIES: 1) Has the volume of 2x256 complex data
// 2) Contains 2- port RAM and address counter
// 3)Has 256-clock cycle period starting with the START impulse
// and continuing forever
// 4) Signal RDY precedes the 1-st correct datum outputted from the buffer
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1 ns / 1 ps
`include "FFT256_CONFIG.inc"
module BUFRAM256C ( CLK ,RST ,ED ,START ,DR ,DI ,RDY ,DOR ,DOI );
`FFT256paramnb
output RDY ;
reg RDY ;
output [nb-1:0] DOR ;
wire [nb-1:0] DOR ;
output [nb-1:0] DOI ;
wire [nb-1:0] DOI ;
input CLK ;
wire CLK ;
input RST ;
wire RST ;
input ED ;
wire ED ;
input START ;
wire START ;
input [nb-1:0] DR ;
wire [nb-1:0] DR ;
input [nb-1:0] DI ;
wire [nb-1:0] DI ;
wire odd, we;
wire [7:0] addrw,addrr;
reg [8:0] addr;
reg [9:0] ct2; //counter for the RDY signal
always @(posedge CLK) // CTADDR
begin
if (RST) begin
addr<=8'b0000_0000;
ct2<= 9'b10000_0001;
RDY<=1'b0; end
else if (START) begin
addr<=8'b0000_0000;
ct2<= 8'b0000_0000;
RDY<=1'b0;end
else if (ED) begin
RDY<=1'b0;
addr<=addr+1;
if (ct2!=257)
ct2<=ct2+1;
if (ct2==256)
RDY<=1'b1;
end
end
assign addrw= addr[7:0];
assign odd=addr[8]; // signal which switches the 2 parts of the buffer
assign addrr={addr[3 : 0], addr[7 : 4]}; // 16-th inverse output address
assign we = ED;
RAM2x256C #(nb) URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd),
.ADDRW(addrw), .ADDRR(addrr),
.DR(DR),.DI(DI),
.DOR(DOR), .DOI(DOI));
endmodule
|
module OpcodeBuffer
#(parameter ADDRESS_WIDTH = 32, parameter WORD_WIDTH = 32)
(
input wire clk,
input wire reset,
input wire [ADDRESS_WIDTH-1:0] ip,
input wire startLoading,
input wire [7:0] ramData,
input wire ramBusy,
output reg busy,
output reg [WORD_WIDTH-1:0] opcode,
output reg [ADDRESS_WIDTH-1:0] address,
output reg request
);
reg [7:0] operation[0:3];
reg [3:0] counter = 0;
reg [3:0] status = 0;
integer i;
initial begin
for(i = 0; i < 4; i = i + 1)
$dumpvars(0,operation[i]);
end
always @(posedge clk)
begin
request = 0;
if(startLoading & ~busy)
begin
request = 1;
busy = 1;
address = ip;
counter = 0;
end
else if(busy)
begin
if(~ramBusy)
begin
operation[counter] = ramData;
request = 1;
counter = counter + 1;
address = address + 1;
end
end
if(busy && counter >= 4)
begin
counter = 0;
busy = 0;
opcode[31:24] <= operation[0];
opcode[23:16] <= operation[1];
opcode[15:8] <= operation[2];
opcode[7:0] <= operation[3];
end
if(reset)
begin
counter = 0;
status <= 0;
opcode <= 0;
address = 0;
busy = 0;
end
end
endmodule
|
`timescale 1ps/1ps
module sim_fsusb_encoder
(inout dp,
inout dm);
localparam HALFBIT = 41667;
localparam BIT = 83333;
reg oe = 1'b0;
reg vp = 1'b1;
reg vm = 1'b0;
assign dp = oe ? vp : 1'bz;
assign dm = oe ? vm : 1'bz;
integer i;
wire [7:0] sync = 8'b1101_0101;
reg decoded, prev_state, save_bit;
integer byte_count, bit_count, num_rx_ones;
reg [7:0] rx_byte;
reg [7:0] rx_pkt[63:0];
`include "usb_pids.v"
`include "usb_defs.v"
integer tx_num_ones = 0;
/*
task tx_sync;
integer bit_cnt;
begin
vp = 1'b1;
vm = 1'b0;
oe = 1'b1;
#BIT;
for (bit_cnt = 0; bit_cnt < 8; bit_cnt = bit_cnt + 1) begin
vp = sync[bit_cnt];
vm = ~sync[bit_cnt];
#BIT;
end
tx_nrzi = 1'b1;
tx_prev_bit = 1'b1;
tx_num_ones = 1'b1;
end
endtask
*/
task tx_byte;
input [7:0] byte;
integer bit_cnt;
reg bit;
begin
for (bit_cnt = 0; bit_cnt < 8; bit_cnt = bit_cnt + 1) begin
bit = byte[bit_cnt]; // save some typing
if (bit) begin
tx_num_ones = tx_num_ones + 1'b1;
if (tx_num_ones >= 7) begin
// bit stuffing... throw a bit-flip in there
//nrzi = ~nrzi;
vp = ~vp;
vm = ~vm;
#BIT;
tx_num_ones = 0;
end
#BIT; // to send a "1" we just leave the lines the same
end else begin
// to send a "0" we toggle the lines
vp = ~vp;
vm = ~vm;
#BIT;
tx_num_ones = 0;
end
end
end
endtask
task tx_32bits_be;
input [31:0] bits;
begin
tx_byte(bits[31:24]);
tx_byte(bits[23:16]);
tx_byte(bits[15:8]);
tx_byte(bits[7:0]);
end
endtask
task tx_eop;
begin
vp = 1'b0;
vm = 1'b0;
#BIT;
#BIT;
vp = 1'b1;
#BIT;
oe = 1'b0;
end
endtask
task tx_warmup;
begin
oe = 1'b1;
vp = 1'b1;
vm = 1'b0;
#BIT;
end
endtask
task rx_data0;
integer len;
begin
len = byte_count - 3;
$display("%t rx data0 len %d ", $time, len);
#(2*BIT);
tx_warmup();
tx_byte(USB_SYNC);
tx_byte(PID_ACK);
tx_eop();
end
endtask
integer rx_in_cnt = 0;
task rx_in;
begin
$display("%t rx IN", $time);
#(2*BIT);
tx_warmup();
tx_byte(USB_SYNC);
if (rx_in_cnt == 0) begin
$display("%t sending NAK", $time);
tx_byte(PID_NAK);
end else if (rx_in_cnt == 5) begin
$display("not transmitting anything in response to this IN request...");
end else begin
if (rx_pkt[1] == 8'h91) begin
$display("%t received IN pkt on EP1", $time);
tx_byte(PID_DATA1); // TODO: toggle data0 / data1
tx_encoder_pkt();
/*
for (i = 0; i < 64; i = i + 1) begin
//$display("%t tx 0x%02h", $time, 64-i);
tx_byte(64-i);
end
*/
end else if (rx_pkt[1] == 8'h00 | rx_pkt[1] == 8'h01 | rx_pkt[1] == USB_DEV_ADDR) begin
$display("%t responding to IN pkt on EP0", $time);
tx_byte(PID_DATA1);
// for now, always just a zero-length packet
tx_byte(0);
tx_byte(0);
end else begin
$display("%t unhandled IN request!", $time);
for (i = 0; i < 64; i = i + 1) begin
$display("rx %d = 0x%02h", $time, rx_pkt[i]);
//$display("%t tx 0x%02h", $time, 64-i);
//tx_byte(64-i);
end
end
end
tx_eop();
rx_in_cnt = rx_in_cnt + 1;
end
endtask
reg [31:0] motor_temp;
initial begin
motor_temp = 32'h0000_d142;
end
task tx_encoder_pkt;
begin
tx_32bits_be(32'h0000_0000);
tx_32bits_be(32'h4efa_0707);
tx_32bits_be(32'he160_4346);
tx_32bits_be(32'h100c_2239);
tx_32bits_be(32'h8156_4346);
tx_32bits_be(32'hb6ea_2d39);
tx_32bits_be(32'h0); // enc angle slow
tx_32bits_be(32'h0); // enc vel slow
tx_32bits_be(32'h0); // enc raw
tx_32bits_be(32'h0); // halls
tx_32bits_be(motor_temp);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
motor_temp = motor_temp + 32'h2; // add 1 degrees each time
end
endtask
initial begin
oe = 1'b0;
vp = 1'b0;
vm = 1'b0;
//$printtimescale;
// wait for USB reset
wait(~dp && ~dm);
$display("%t usb reset start", $time);
wait(dp && ~dm);
$display("%t usb reset end", $time); // todo: time reset pulse length
wait(~dp && ~dm);
$display("%t usb reset2 start", $time);
wait(dp && ~dm);
$display("%t usb reset2 end", $time); // todo: time reset pulse length
forever begin
num_rx_ones = 0;
bit_count = 0;
byte_count = 0;
rx_byte = 8'h0;
prev_state = 1;
decoded = 0;
save_bit = 1; // this is set to 0 when we get a stuffed bit
wait(~dp);
//$display("%t fsusb pkt start", $time);
#41667; // shift to the middle of a bit period
for (i = 0; i < 8; i = i + 1) begin
//$display("%t sync bit", $time);
if (dp != ~dm) begin
$display("illegal usb state at %t", $time);
#1000 $finish();
end
if (sync[i] != dm) begin
$display("sync fail at %t", $time);
#1000 $finish();
end
#83333; // skip over a full bit
end
//$display("%t sync OK", $time);
// decode the NRZI data
while (~(dp == 0 & dm == 0)) begin
if (dp != ~dm) begin
$display("%t illegal usb state", $time);
#1000 $finish();
end
if (prev_state != dm) begin
decoded = 0;
prev_state = dm;
if (num_rx_ones == 6) begin
$display("%t stuffed bit detected", $time);
save_bit = 0; // it's a stuffed bit; ignore it
end
else
save_bit = 1;
num_rx_ones = 0;
//$display("%t rx flip @ %d", $time, bit_count);
end else begin
decoded = 1;
num_rx_ones = num_rx_ones + 1;
save_bit = 1; // ones are never stuffed
if (num_rx_ones > 6) begin
$display("%t received more than 6 ones in a row.", $time);
#100000 $finish();
end
//$display("%t rx same @ %d", $time, bit_count);
end
if (save_bit) begin
rx_byte = { decoded, rx_byte[7:1] };
bit_count = bit_count + 1;
end
if (bit_count == 8) begin
rx_pkt[byte_count] = rx_byte;
if (byte_count == 0) begin
case (rx_byte)
PID_SOF: $display("%t SOF", $time);
PID_SETUP: $display("%t SETUP", $time);
PID_DATA0: $display("%t DATA0", $time);
PID_IN : $display("%t IN", $time);
PID_ACK : $display("%t ACK", $time);
default: begin
$display("%t ERROR: rx unknown PID (0x%02h)", $time, rx_byte);
$finish();
end
endcase
end
else
$display("%t rx 0x%02h", $time, rx_byte);
byte_count = byte_count + 1;
bit_count = 0;
end
#83333; // skip over a full bit
end
if (num_rx_ones == 6) begin
$display("%t expected to see bit-stuffing right before SE0", $time);
#100000 $finish();
end
if (bit_count != 0) begin
$display("%t SE0 seen at non-byte boundary", $time);
#5000 $finish();
end
//$display("%t found SE0", $time);
#83333;
if (dp != 0 | dm != 0) begin
$display("%t SE0 state wasn't two bits long", $time);
#1000 $finish();
end
#83333;
if (dp != 1 | dm != 0) begin
$display("%t didn't finish EOP with J state", $time);
#1000 $finish();
end
#83.333;
$display("%t packet RX complete", $time);
case (rx_pkt[0])
PID_SOF: ;
PID_SETUP: ;
PID_DATA0: rx_data0();
PID_IN: rx_in();
PID_ACK: ;
default: begin
$display("%t unknown rx PID (0x%02h)", $time, rx_pkt[0]);
$finish();
end
endcase
//if (rx_pkt[0] == PID_DATA0)
// rx_data0();
end
end
endmodule
|
// ghrd_10as066n2_dipsw_pio.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_dipsw_pio (
input wire clk, // clk.clk
input wire [3:0] in_port, // external_connection.export
output wire irq, // irq.irq
input wire reset_n, // reset.reset_n
input wire [1:0] address, // s1.address
input wire write_n, // .write_n
input wire [31:0] writedata, // .writedata
input wire chipselect, // .chipselect
output wire [31:0] readdata // .readdata
);
ghrd_10as066n2_dipsw_pio_altera_avalon_pio_171_67u3hiq dipsw_pio (
.clk (clk), // input, width = 1, clk.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.address (address), // input, width = 2, s1.address
.write_n (write_n), // input, width = 1, .write_n
.writedata (writedata), // input, width = 32, .writedata
.chipselect (chipselect), // input, width = 1, .chipselect
.readdata (readdata), // output, width = 32, .readdata
.in_port (in_port), // input, width = 4, external_connection.export
.irq (irq) // output, width = 1, irq.irq
);
endmodule
|
//-----------------------------------------------------------------------------
// system_nfa_accept_samples_generic_hw_top_0_wrapper.v
//-----------------------------------------------------------------------------
`timescale 1 ps / 100 fs
`uselib lib=unisims_ver lib=proc_common_v3_00_a lib=plbv46_slave_single_v1_01_a lib=nfa_accept_samples_generic_hw_top_v1_01_a
module system_nfa_accept_samples_generic_hw_top_0_wrapper
(
aclk,
aresetn,
indices_MPLB_Clk,
indices_MPLB_Rst,
indices_M_request,
indices_M_priority,
indices_M_busLock,
indices_M_RNW,
indices_M_BE,
indices_M_MSize,
indices_M_size,
indices_M_type,
indices_M_TAttribute,
indices_M_lockErr,
indices_M_abort,
indices_M_UABus,
indices_M_ABus,
indices_M_wrDBus,
indices_M_wrBurst,
indices_M_rdBurst,
indices_PLB_MAddrAck,
indices_PLB_MSSize,
indices_PLB_MRearbitrate,
indices_PLB_MTimeout,
indices_PLB_MBusy,
indices_PLB_MRdErr,
indices_PLB_MWrErr,
indices_PLB_MIRQ,
indices_PLB_MRdDBus,
indices_PLB_MRdWdAddr,
indices_PLB_MRdDAck,
indices_PLB_MRdBTerm,
indices_PLB_MWrDAck,
indices_PLB_MWrBTerm,
nfa_finals_buckets_MPLB_Clk,
nfa_finals_buckets_MPLB_Rst,
nfa_finals_buckets_M_request,
nfa_finals_buckets_M_priority,
nfa_finals_buckets_M_busLock,
nfa_finals_buckets_M_RNW,
nfa_finals_buckets_M_BE,
nfa_finals_buckets_M_MSize,
nfa_finals_buckets_M_size,
nfa_finals_buckets_M_type,
nfa_finals_buckets_M_TAttribute,
nfa_finals_buckets_M_lockErr,
nfa_finals_buckets_M_abort,
nfa_finals_buckets_M_UABus,
nfa_finals_buckets_M_ABus,
nfa_finals_buckets_M_wrDBus,
nfa_finals_buckets_M_wrBurst,
nfa_finals_buckets_M_rdBurst,
nfa_finals_buckets_PLB_MAddrAck,
nfa_finals_buckets_PLB_MSSize,
nfa_finals_buckets_PLB_MRearbitrate,
nfa_finals_buckets_PLB_MTimeout,
nfa_finals_buckets_PLB_MBusy,
nfa_finals_buckets_PLB_MRdErr,
nfa_finals_buckets_PLB_MWrErr,
nfa_finals_buckets_PLB_MIRQ,
nfa_finals_buckets_PLB_MRdDBus,
nfa_finals_buckets_PLB_MRdWdAddr,
nfa_finals_buckets_PLB_MRdDAck,
nfa_finals_buckets_PLB_MRdBTerm,
nfa_finals_buckets_PLB_MWrDAck,
nfa_finals_buckets_PLB_MWrBTerm,
nfa_forward_buckets_MPLB_Clk,
nfa_forward_buckets_MPLB_Rst,
nfa_forward_buckets_M_request,
nfa_forward_buckets_M_priority,
nfa_forward_buckets_M_busLock,
nfa_forward_buckets_M_RNW,
nfa_forward_buckets_M_BE,
nfa_forward_buckets_M_MSize,
nfa_forward_buckets_M_size,
nfa_forward_buckets_M_type,
nfa_forward_buckets_M_TAttribute,
nfa_forward_buckets_M_lockErr,
nfa_forward_buckets_M_abort,
nfa_forward_buckets_M_UABus,
nfa_forward_buckets_M_ABus,
nfa_forward_buckets_M_wrDBus,
nfa_forward_buckets_M_wrBurst,
nfa_forward_buckets_M_rdBurst,
nfa_forward_buckets_PLB_MAddrAck,
nfa_forward_buckets_PLB_MSSize,
nfa_forward_buckets_PLB_MRearbitrate,
nfa_forward_buckets_PLB_MTimeout,
nfa_forward_buckets_PLB_MBusy,
nfa_forward_buckets_PLB_MRdErr,
nfa_forward_buckets_PLB_MWrErr,
nfa_forward_buckets_PLB_MIRQ,
nfa_forward_buckets_PLB_MRdDBus,
nfa_forward_buckets_PLB_MRdWdAddr,
nfa_forward_buckets_PLB_MRdDAck,
nfa_forward_buckets_PLB_MRdBTerm,
nfa_forward_buckets_PLB_MWrDAck,
nfa_forward_buckets_PLB_MWrBTerm,
nfa_initials_buckets_MPLB_Clk,
nfa_initials_buckets_MPLB_Rst,
nfa_initials_buckets_M_request,
nfa_initials_buckets_M_priority,
nfa_initials_buckets_M_busLock,
nfa_initials_buckets_M_RNW,
nfa_initials_buckets_M_BE,
nfa_initials_buckets_M_MSize,
nfa_initials_buckets_M_size,
nfa_initials_buckets_M_type,
nfa_initials_buckets_M_TAttribute,
nfa_initials_buckets_M_lockErr,
nfa_initials_buckets_M_abort,
nfa_initials_buckets_M_UABus,
nfa_initials_buckets_M_ABus,
nfa_initials_buckets_M_wrDBus,
nfa_initials_buckets_M_wrBurst,
nfa_initials_buckets_M_rdBurst,
nfa_initials_buckets_PLB_MAddrAck,
nfa_initials_buckets_PLB_MSSize,
nfa_initials_buckets_PLB_MRearbitrate,
nfa_initials_buckets_PLB_MTimeout,
nfa_initials_buckets_PLB_MBusy,
nfa_initials_buckets_PLB_MRdErr,
nfa_initials_buckets_PLB_MWrErr,
nfa_initials_buckets_PLB_MIRQ,
nfa_initials_buckets_PLB_MRdDBus,
nfa_initials_buckets_PLB_MRdWdAddr,
nfa_initials_buckets_PLB_MRdDAck,
nfa_initials_buckets_PLB_MRdBTerm,
nfa_initials_buckets_PLB_MWrDAck,
nfa_initials_buckets_PLB_MWrBTerm,
sample_buffer_MPLB_Clk,
sample_buffer_MPLB_Rst,
sample_buffer_M_request,
sample_buffer_M_priority,
sample_buffer_M_busLock,
sample_buffer_M_RNW,
sample_buffer_M_BE,
sample_buffer_M_MSize,
sample_buffer_M_size,
sample_buffer_M_type,
sample_buffer_M_TAttribute,
sample_buffer_M_lockErr,
sample_buffer_M_abort,
sample_buffer_M_UABus,
sample_buffer_M_ABus,
sample_buffer_M_wrDBus,
sample_buffer_M_wrBurst,
sample_buffer_M_rdBurst,
sample_buffer_PLB_MAddrAck,
sample_buffer_PLB_MSSize,
sample_buffer_PLB_MRearbitrate,
sample_buffer_PLB_MTimeout,
sample_buffer_PLB_MBusy,
sample_buffer_PLB_MRdErr,
sample_buffer_PLB_MWrErr,
sample_buffer_PLB_MIRQ,
sample_buffer_PLB_MRdDBus,
sample_buffer_PLB_MRdWdAddr,
sample_buffer_PLB_MRdDAck,
sample_buffer_PLB_MRdBTerm,
sample_buffer_PLB_MWrDAck,
sample_buffer_PLB_MWrBTerm,
splb_slv0_SPLB_Clk,
splb_slv0_SPLB_Rst,
splb_slv0_PLB_ABus,
splb_slv0_PLB_UABus,
splb_slv0_PLB_PAValid,
splb_slv0_PLB_SAValid,
splb_slv0_PLB_rdPrim,
splb_slv0_PLB_wrPrim,
splb_slv0_PLB_masterID,
splb_slv0_PLB_abort,
splb_slv0_PLB_busLock,
splb_slv0_PLB_RNW,
splb_slv0_PLB_BE,
splb_slv0_PLB_MSize,
splb_slv0_PLB_size,
splb_slv0_PLB_type,
splb_slv0_PLB_lockErr,
splb_slv0_PLB_wrDBus,
splb_slv0_PLB_wrBurst,
splb_slv0_PLB_rdBurst,
splb_slv0_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri,
splb_slv0_PLB_reqPri,
splb_slv0_PLB_TAttribute,
splb_slv0_Sl_addrAck,
splb_slv0_Sl_SSize,
splb_slv0_Sl_wait,
splb_slv0_Sl_rearbitrate,
splb_slv0_Sl_wrDAck,
splb_slv0_Sl_wrComp,
splb_slv0_Sl_wrBTerm,
splb_slv0_Sl_rdDBus,
splb_slv0_Sl_rdWdAddr,
splb_slv0_Sl_rdDAck,
splb_slv0_Sl_rdComp,
splb_slv0_Sl_rdBTerm,
splb_slv0_Sl_MBusy,
splb_slv0_Sl_MWrErr,
splb_slv0_Sl_MRdErr,
splb_slv0_Sl_MIRQ
);
input aclk;
input aresetn;
input indices_MPLB_Clk;
input indices_MPLB_Rst;
output indices_M_request;
output [0:1] indices_M_priority;
output indices_M_busLock;
output indices_M_RNW;
output [0:7] indices_M_BE;
output [0:1] indices_M_MSize;
output [0:3] indices_M_size;
output [0:2] indices_M_type;
output [0:15] indices_M_TAttribute;
output indices_M_lockErr;
output indices_M_abort;
output [0:31] indices_M_UABus;
output [0:31] indices_M_ABus;
output [0:63] indices_M_wrDBus;
output indices_M_wrBurst;
output indices_M_rdBurst;
input indices_PLB_MAddrAck;
input [0:1] indices_PLB_MSSize;
input indices_PLB_MRearbitrate;
input indices_PLB_MTimeout;
input indices_PLB_MBusy;
input indices_PLB_MRdErr;
input indices_PLB_MWrErr;
input indices_PLB_MIRQ;
input [0:63] indices_PLB_MRdDBus;
input [0:3] indices_PLB_MRdWdAddr;
input indices_PLB_MRdDAck;
input indices_PLB_MRdBTerm;
input indices_PLB_MWrDAck;
input indices_PLB_MWrBTerm;
input nfa_finals_buckets_MPLB_Clk;
input nfa_finals_buckets_MPLB_Rst;
output nfa_finals_buckets_M_request;
output [0:1] nfa_finals_buckets_M_priority;
output nfa_finals_buckets_M_busLock;
output nfa_finals_buckets_M_RNW;
output [0:7] nfa_finals_buckets_M_BE;
output [0:1] nfa_finals_buckets_M_MSize;
output [0:3] nfa_finals_buckets_M_size;
output [0:2] nfa_finals_buckets_M_type;
output [0:15] nfa_finals_buckets_M_TAttribute;
output nfa_finals_buckets_M_lockErr;
output nfa_finals_buckets_M_abort;
output [0:31] nfa_finals_buckets_M_UABus;
output [0:31] nfa_finals_buckets_M_ABus;
output [0:63] nfa_finals_buckets_M_wrDBus;
output nfa_finals_buckets_M_wrBurst;
output nfa_finals_buckets_M_rdBurst;
input nfa_finals_buckets_PLB_MAddrAck;
input [0:1] nfa_finals_buckets_PLB_MSSize;
input nfa_finals_buckets_PLB_MRearbitrate;
input nfa_finals_buckets_PLB_MTimeout;
input nfa_finals_buckets_PLB_MBusy;
input nfa_finals_buckets_PLB_MRdErr;
input nfa_finals_buckets_PLB_MWrErr;
input nfa_finals_buckets_PLB_MIRQ;
input [0:63] nfa_finals_buckets_PLB_MRdDBus;
input [0:3] nfa_finals_buckets_PLB_MRdWdAddr;
input nfa_finals_buckets_PLB_MRdDAck;
input nfa_finals_buckets_PLB_MRdBTerm;
input nfa_finals_buckets_PLB_MWrDAck;
input nfa_finals_buckets_PLB_MWrBTerm;
input nfa_forward_buckets_MPLB_Clk;
input nfa_forward_buckets_MPLB_Rst;
output nfa_forward_buckets_M_request;
output [0:1] nfa_forward_buckets_M_priority;
output nfa_forward_buckets_M_busLock;
output nfa_forward_buckets_M_RNW;
output [0:7] nfa_forward_buckets_M_BE;
output [0:1] nfa_forward_buckets_M_MSize;
output [0:3] nfa_forward_buckets_M_size;
output [0:2] nfa_forward_buckets_M_type;
output [0:15] nfa_forward_buckets_M_TAttribute;
output nfa_forward_buckets_M_lockErr;
output nfa_forward_buckets_M_abort;
output [0:31] nfa_forward_buckets_M_UABus;
output [0:31] nfa_forward_buckets_M_ABus;
output [0:63] nfa_forward_buckets_M_wrDBus;
output nfa_forward_buckets_M_wrBurst;
output nfa_forward_buckets_M_rdBurst;
input nfa_forward_buckets_PLB_MAddrAck;
input [0:1] nfa_forward_buckets_PLB_MSSize;
input nfa_forward_buckets_PLB_MRearbitrate;
input nfa_forward_buckets_PLB_MTimeout;
input nfa_forward_buckets_PLB_MBusy;
input nfa_forward_buckets_PLB_MRdErr;
input nfa_forward_buckets_PLB_MWrErr;
input nfa_forward_buckets_PLB_MIRQ;
input [0:63] nfa_forward_buckets_PLB_MRdDBus;
input [0:3] nfa_forward_buckets_PLB_MRdWdAddr;
input nfa_forward_buckets_PLB_MRdDAck;
input nfa_forward_buckets_PLB_MRdBTerm;
input nfa_forward_buckets_PLB_MWrDAck;
input nfa_forward_buckets_PLB_MWrBTerm;
input nfa_initials_buckets_MPLB_Clk;
input nfa_initials_buckets_MPLB_Rst;
output nfa_initials_buckets_M_request;
output [0:1] nfa_initials_buckets_M_priority;
output nfa_initials_buckets_M_busLock;
output nfa_initials_buckets_M_RNW;
output [0:7] nfa_initials_buckets_M_BE;
output [0:1] nfa_initials_buckets_M_MSize;
output [0:3] nfa_initials_buckets_M_size;
output [0:2] nfa_initials_buckets_M_type;
output [0:15] nfa_initials_buckets_M_TAttribute;
output nfa_initials_buckets_M_lockErr;
output nfa_initials_buckets_M_abort;
output [0:31] nfa_initials_buckets_M_UABus;
output [0:31] nfa_initials_buckets_M_ABus;
output [0:63] nfa_initials_buckets_M_wrDBus;
output nfa_initials_buckets_M_wrBurst;
output nfa_initials_buckets_M_rdBurst;
input nfa_initials_buckets_PLB_MAddrAck;
input [0:1] nfa_initials_buckets_PLB_MSSize;
input nfa_initials_buckets_PLB_MRearbitrate;
input nfa_initials_buckets_PLB_MTimeout;
input nfa_initials_buckets_PLB_MBusy;
input nfa_initials_buckets_PLB_MRdErr;
input nfa_initials_buckets_PLB_MWrErr;
input nfa_initials_buckets_PLB_MIRQ;
input [0:63] nfa_initials_buckets_PLB_MRdDBus;
input [0:3] nfa_initials_buckets_PLB_MRdWdAddr;
input nfa_initials_buckets_PLB_MRdDAck;
input nfa_initials_buckets_PLB_MRdBTerm;
input nfa_initials_buckets_PLB_MWrDAck;
input nfa_initials_buckets_PLB_MWrBTerm;
input sample_buffer_MPLB_Clk;
input sample_buffer_MPLB_Rst;
output sample_buffer_M_request;
output [0:1] sample_buffer_M_priority;
output sample_buffer_M_busLock;
output sample_buffer_M_RNW;
output [0:7] sample_buffer_M_BE;
output [0:1] sample_buffer_M_MSize;
output [0:3] sample_buffer_M_size;
output [0:2] sample_buffer_M_type;
output [0:15] sample_buffer_M_TAttribute;
output sample_buffer_M_lockErr;
output sample_buffer_M_abort;
output [0:31] sample_buffer_M_UABus;
output [0:31] sample_buffer_M_ABus;
output [0:63] sample_buffer_M_wrDBus;
output sample_buffer_M_wrBurst;
output sample_buffer_M_rdBurst;
input sample_buffer_PLB_MAddrAck;
input [0:1] sample_buffer_PLB_MSSize;
input sample_buffer_PLB_MRearbitrate;
input sample_buffer_PLB_MTimeout;
input sample_buffer_PLB_MBusy;
input sample_buffer_PLB_MRdErr;
input sample_buffer_PLB_MWrErr;
input sample_buffer_PLB_MIRQ;
input [0:63] sample_buffer_PLB_MRdDBus;
input [0:3] sample_buffer_PLB_MRdWdAddr;
input sample_buffer_PLB_MRdDAck;
input sample_buffer_PLB_MRdBTerm;
input sample_buffer_PLB_MWrDAck;
input sample_buffer_PLB_MWrBTerm;
input splb_slv0_SPLB_Clk;
input splb_slv0_SPLB_Rst;
input [0:31] splb_slv0_PLB_ABus;
input [0:31] splb_slv0_PLB_UABus;
input splb_slv0_PLB_PAValid;
input splb_slv0_PLB_SAValid;
input splb_slv0_PLB_rdPrim;
input splb_slv0_PLB_wrPrim;
input [0:2] splb_slv0_PLB_masterID;
input splb_slv0_PLB_abort;
input splb_slv0_PLB_busLock;
input splb_slv0_PLB_RNW;
input [0:7] splb_slv0_PLB_BE;
input [0:1] splb_slv0_PLB_MSize;
input [0:3] splb_slv0_PLB_size;
input [0:2] splb_slv0_PLB_type;
input splb_slv0_PLB_lockErr;
input [0:63] splb_slv0_PLB_wrDBus;
input splb_slv0_PLB_wrBurst;
input splb_slv0_PLB_rdBurst;
input splb_slv0_PLB_wrPendReq;
input splb_slv0_PLB_rdPendReq;
input [0:1] splb_slv0_PLB_wrPendPri;
input [0:1] splb_slv0_PLB_rdPendPri;
input [0:1] splb_slv0_PLB_reqPri;
input [0:15] splb_slv0_PLB_TAttribute;
output splb_slv0_Sl_addrAck;
output [0:1] splb_slv0_Sl_SSize;
output splb_slv0_Sl_wait;
output splb_slv0_Sl_rearbitrate;
output splb_slv0_Sl_wrDAck;
output splb_slv0_Sl_wrComp;
output splb_slv0_Sl_wrBTerm;
output [0:63] splb_slv0_Sl_rdDBus;
output [0:3] splb_slv0_Sl_rdWdAddr;
output splb_slv0_Sl_rdDAck;
output splb_slv0_Sl_rdComp;
output splb_slv0_Sl_rdBTerm;
output [0:5] splb_slv0_Sl_MBusy;
output [0:5] splb_slv0_Sl_MWrErr;
output [0:5] splb_slv0_Sl_MRdErr;
output [0:5] splb_slv0_Sl_MIRQ;
nfa_accept_samples_generic_hw_top
#(
.RESET_ACTIVE_LOW ( 1 ),
.C_indices_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_indices_AWIDTH ( 32 ),
.C_indices_DWIDTH ( 64 ),
.C_indices_NATIVE_DWIDTH ( 64 ),
.C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_finals_buckets_AWIDTH ( 32 ),
.C_nfa_finals_buckets_DWIDTH ( 64 ),
.C_nfa_finals_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_forward_buckets_AWIDTH ( 32 ),
.C_nfa_forward_buckets_DWIDTH ( 64 ),
.C_nfa_forward_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_initials_buckets_AWIDTH ( 32 ),
.C_nfa_initials_buckets_DWIDTH ( 64 ),
.C_nfa_initials_buckets_NATIVE_DWIDTH ( 64 ),
.C_sample_buffer_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_sample_buffer_AWIDTH ( 32 ),
.C_sample_buffer_DWIDTH ( 64 ),
.C_sample_buffer_NATIVE_DWIDTH ( 64 ),
.C_SPLB_SLV0_BASEADDR ( 32'hD0000000 ),
.C_SPLB_SLV0_HIGHADDR ( 32'hD00000FF ),
.C_SPLB_SLV0_AWIDTH ( 32 ),
.C_SPLB_SLV0_DWIDTH ( 64 ),
.C_SPLB_SLV0_NUM_MASTERS ( 6 ),
.C_SPLB_SLV0_MID_WIDTH ( 3 ),
.C_SPLB_SLV0_NATIVE_DWIDTH ( 32 ),
.C_SPLB_SLV0_P2P ( 0 ),
.C_SPLB_SLV0_SUPPORT_BURSTS ( 0 ),
.C_SPLB_SLV0_SMALLEST_MASTER ( 32 ),
.C_SPLB_SLV0_INCLUDE_DPHASE_TIMER ( 0 )
)
nfa_accept_samples_generic_hw_top_0 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.indices_MPLB_Clk ( indices_MPLB_Clk ),
.indices_MPLB_Rst ( indices_MPLB_Rst ),
.indices_M_request ( indices_M_request ),
.indices_M_priority ( indices_M_priority ),
.indices_M_busLock ( indices_M_busLock ),
.indices_M_RNW ( indices_M_RNW ),
.indices_M_BE ( indices_M_BE ),
.indices_M_MSize ( indices_M_MSize ),
.indices_M_size ( indices_M_size ),
.indices_M_type ( indices_M_type ),
.indices_M_TAttribute ( indices_M_TAttribute ),
.indices_M_lockErr ( indices_M_lockErr ),
.indices_M_abort ( indices_M_abort ),
.indices_M_UABus ( indices_M_UABus ),
.indices_M_ABus ( indices_M_ABus ),
.indices_M_wrDBus ( indices_M_wrDBus ),
.indices_M_wrBurst ( indices_M_wrBurst ),
.indices_M_rdBurst ( indices_M_rdBurst ),
.indices_PLB_MAddrAck ( indices_PLB_MAddrAck ),
.indices_PLB_MSSize ( indices_PLB_MSSize ),
.indices_PLB_MRearbitrate ( indices_PLB_MRearbitrate ),
.indices_PLB_MTimeout ( indices_PLB_MTimeout ),
.indices_PLB_MBusy ( indices_PLB_MBusy ),
.indices_PLB_MRdErr ( indices_PLB_MRdErr ),
.indices_PLB_MWrErr ( indices_PLB_MWrErr ),
.indices_PLB_MIRQ ( indices_PLB_MIRQ ),
.indices_PLB_MRdDBus ( indices_PLB_MRdDBus ),
.indices_PLB_MRdWdAddr ( indices_PLB_MRdWdAddr ),
.indices_PLB_MRdDAck ( indices_PLB_MRdDAck ),
.indices_PLB_MRdBTerm ( indices_PLB_MRdBTerm ),
.indices_PLB_MWrDAck ( indices_PLB_MWrDAck ),
.indices_PLB_MWrBTerm ( indices_PLB_MWrBTerm ),
.nfa_finals_buckets_MPLB_Clk ( nfa_finals_buckets_MPLB_Clk ),
.nfa_finals_buckets_MPLB_Rst ( nfa_finals_buckets_MPLB_Rst ),
.nfa_finals_buckets_M_request ( nfa_finals_buckets_M_request ),
.nfa_finals_buckets_M_priority ( nfa_finals_buckets_M_priority ),
.nfa_finals_buckets_M_busLock ( nfa_finals_buckets_M_busLock ),
.nfa_finals_buckets_M_RNW ( nfa_finals_buckets_M_RNW ),
.nfa_finals_buckets_M_BE ( nfa_finals_buckets_M_BE ),
.nfa_finals_buckets_M_MSize ( nfa_finals_buckets_M_MSize ),
.nfa_finals_buckets_M_size ( nfa_finals_buckets_M_size ),
.nfa_finals_buckets_M_type ( nfa_finals_buckets_M_type ),
.nfa_finals_buckets_M_TAttribute ( nfa_finals_buckets_M_TAttribute ),
.nfa_finals_buckets_M_lockErr ( nfa_finals_buckets_M_lockErr ),
.nfa_finals_buckets_M_abort ( nfa_finals_buckets_M_abort ),
.nfa_finals_buckets_M_UABus ( nfa_finals_buckets_M_UABus ),
.nfa_finals_buckets_M_ABus ( nfa_finals_buckets_M_ABus ),
.nfa_finals_buckets_M_wrDBus ( nfa_finals_buckets_M_wrDBus ),
.nfa_finals_buckets_M_wrBurst ( nfa_finals_buckets_M_wrBurst ),
.nfa_finals_buckets_M_rdBurst ( nfa_finals_buckets_M_rdBurst ),
.nfa_finals_buckets_PLB_MAddrAck ( nfa_finals_buckets_PLB_MAddrAck ),
.nfa_finals_buckets_PLB_MSSize ( nfa_finals_buckets_PLB_MSSize ),
.nfa_finals_buckets_PLB_MRearbitrate ( nfa_finals_buckets_PLB_MRearbitrate ),
.nfa_finals_buckets_PLB_MTimeout ( nfa_finals_buckets_PLB_MTimeout ),
.nfa_finals_buckets_PLB_MBusy ( nfa_finals_buckets_PLB_MBusy ),
.nfa_finals_buckets_PLB_MRdErr ( nfa_finals_buckets_PLB_MRdErr ),
.nfa_finals_buckets_PLB_MWrErr ( nfa_finals_buckets_PLB_MWrErr ),
.nfa_finals_buckets_PLB_MIRQ ( nfa_finals_buckets_PLB_MIRQ ),
.nfa_finals_buckets_PLB_MRdDBus ( nfa_finals_buckets_PLB_MRdDBus ),
.nfa_finals_buckets_PLB_MRdWdAddr ( nfa_finals_buckets_PLB_MRdWdAddr ),
.nfa_finals_buckets_PLB_MRdDAck ( nfa_finals_buckets_PLB_MRdDAck ),
.nfa_finals_buckets_PLB_MRdBTerm ( nfa_finals_buckets_PLB_MRdBTerm ),
.nfa_finals_buckets_PLB_MWrDAck ( nfa_finals_buckets_PLB_MWrDAck ),
.nfa_finals_buckets_PLB_MWrBTerm ( nfa_finals_buckets_PLB_MWrBTerm ),
.nfa_forward_buckets_MPLB_Clk ( nfa_forward_buckets_MPLB_Clk ),
.nfa_forward_buckets_MPLB_Rst ( nfa_forward_buckets_MPLB_Rst ),
.nfa_forward_buckets_M_request ( nfa_forward_buckets_M_request ),
.nfa_forward_buckets_M_priority ( nfa_forward_buckets_M_priority ),
.nfa_forward_buckets_M_busLock ( nfa_forward_buckets_M_busLock ),
.nfa_forward_buckets_M_RNW ( nfa_forward_buckets_M_RNW ),
.nfa_forward_buckets_M_BE ( nfa_forward_buckets_M_BE ),
.nfa_forward_buckets_M_MSize ( nfa_forward_buckets_M_MSize ),
.nfa_forward_buckets_M_size ( nfa_forward_buckets_M_size ),
.nfa_forward_buckets_M_type ( nfa_forward_buckets_M_type ),
.nfa_forward_buckets_M_TAttribute ( nfa_forward_buckets_M_TAttribute ),
.nfa_forward_buckets_M_lockErr ( nfa_forward_buckets_M_lockErr ),
.nfa_forward_buckets_M_abort ( nfa_forward_buckets_M_abort ),
.nfa_forward_buckets_M_UABus ( nfa_forward_buckets_M_UABus ),
.nfa_forward_buckets_M_ABus ( nfa_forward_buckets_M_ABus ),
.nfa_forward_buckets_M_wrDBus ( nfa_forward_buckets_M_wrDBus ),
.nfa_forward_buckets_M_wrBurst ( nfa_forward_buckets_M_wrBurst ),
.nfa_forward_buckets_M_rdBurst ( nfa_forward_buckets_M_rdBurst ),
.nfa_forward_buckets_PLB_MAddrAck ( nfa_forward_buckets_PLB_MAddrAck ),
.nfa_forward_buckets_PLB_MSSize ( nfa_forward_buckets_PLB_MSSize ),
.nfa_forward_buckets_PLB_MRearbitrate ( nfa_forward_buckets_PLB_MRearbitrate ),
.nfa_forward_buckets_PLB_MTimeout ( nfa_forward_buckets_PLB_MTimeout ),
.nfa_forward_buckets_PLB_MBusy ( nfa_forward_buckets_PLB_MBusy ),
.nfa_forward_buckets_PLB_MRdErr ( nfa_forward_buckets_PLB_MRdErr ),
.nfa_forward_buckets_PLB_MWrErr ( nfa_forward_buckets_PLB_MWrErr ),
.nfa_forward_buckets_PLB_MIRQ ( nfa_forward_buckets_PLB_MIRQ ),
.nfa_forward_buckets_PLB_MRdDBus ( nfa_forward_buckets_PLB_MRdDBus ),
.nfa_forward_buckets_PLB_MRdWdAddr ( nfa_forward_buckets_PLB_MRdWdAddr ),
.nfa_forward_buckets_PLB_MRdDAck ( nfa_forward_buckets_PLB_MRdDAck ),
.nfa_forward_buckets_PLB_MRdBTerm ( nfa_forward_buckets_PLB_MRdBTerm ),
.nfa_forward_buckets_PLB_MWrDAck ( nfa_forward_buckets_PLB_MWrDAck ),
.nfa_forward_buckets_PLB_MWrBTerm ( nfa_forward_buckets_PLB_MWrBTerm ),
.nfa_initials_buckets_MPLB_Clk ( nfa_initials_buckets_MPLB_Clk ),
.nfa_initials_buckets_MPLB_Rst ( nfa_initials_buckets_MPLB_Rst ),
.nfa_initials_buckets_M_request ( nfa_initials_buckets_M_request ),
.nfa_initials_buckets_M_priority ( nfa_initials_buckets_M_priority ),
.nfa_initials_buckets_M_busLock ( nfa_initials_buckets_M_busLock ),
.nfa_initials_buckets_M_RNW ( nfa_initials_buckets_M_RNW ),
.nfa_initials_buckets_M_BE ( nfa_initials_buckets_M_BE ),
.nfa_initials_buckets_M_MSize ( nfa_initials_buckets_M_MSize ),
.nfa_initials_buckets_M_size ( nfa_initials_buckets_M_size ),
.nfa_initials_buckets_M_type ( nfa_initials_buckets_M_type ),
.nfa_initials_buckets_M_TAttribute ( nfa_initials_buckets_M_TAttribute ),
.nfa_initials_buckets_M_lockErr ( nfa_initials_buckets_M_lockErr ),
.nfa_initials_buckets_M_abort ( nfa_initials_buckets_M_abort ),
.nfa_initials_buckets_M_UABus ( nfa_initials_buckets_M_UABus ),
.nfa_initials_buckets_M_ABus ( nfa_initials_buckets_M_ABus ),
.nfa_initials_buckets_M_wrDBus ( nfa_initials_buckets_M_wrDBus ),
.nfa_initials_buckets_M_wrBurst ( nfa_initials_buckets_M_wrBurst ),
.nfa_initials_buckets_M_rdBurst ( nfa_initials_buckets_M_rdBurst ),
.nfa_initials_buckets_PLB_MAddrAck ( nfa_initials_buckets_PLB_MAddrAck ),
.nfa_initials_buckets_PLB_MSSize ( nfa_initials_buckets_PLB_MSSize ),
.nfa_initials_buckets_PLB_MRearbitrate ( nfa_initials_buckets_PLB_MRearbitrate ),
.nfa_initials_buckets_PLB_MTimeout ( nfa_initials_buckets_PLB_MTimeout ),
.nfa_initials_buckets_PLB_MBusy ( nfa_initials_buckets_PLB_MBusy ),
.nfa_initials_buckets_PLB_MRdErr ( nfa_initials_buckets_PLB_MRdErr ),
.nfa_initials_buckets_PLB_MWrErr ( nfa_initials_buckets_PLB_MWrErr ),
.nfa_initials_buckets_PLB_MIRQ ( nfa_initials_buckets_PLB_MIRQ ),
.nfa_initials_buckets_PLB_MRdDBus ( nfa_initials_buckets_PLB_MRdDBus ),
.nfa_initials_buckets_PLB_MRdWdAddr ( nfa_initials_buckets_PLB_MRdWdAddr ),
.nfa_initials_buckets_PLB_MRdDAck ( nfa_initials_buckets_PLB_MRdDAck ),
.nfa_initials_buckets_PLB_MRdBTerm ( nfa_initials_buckets_PLB_MRdBTerm ),
.nfa_initials_buckets_PLB_MWrDAck ( nfa_initials_buckets_PLB_MWrDAck ),
.nfa_initials_buckets_PLB_MWrBTerm ( nfa_initials_buckets_PLB_MWrBTerm ),
.sample_buffer_MPLB_Clk ( sample_buffer_MPLB_Clk ),
.sample_buffer_MPLB_Rst ( sample_buffer_MPLB_Rst ),
.sample_buffer_M_request ( sample_buffer_M_request ),
.sample_buffer_M_priority ( sample_buffer_M_priority ),
.sample_buffer_M_busLock ( sample_buffer_M_busLock ),
.sample_buffer_M_RNW ( sample_buffer_M_RNW ),
.sample_buffer_M_BE ( sample_buffer_M_BE ),
.sample_buffer_M_MSize ( sample_buffer_M_MSize ),
.sample_buffer_M_size ( sample_buffer_M_size ),
.sample_buffer_M_type ( sample_buffer_M_type ),
.sample_buffer_M_TAttribute ( sample_buffer_M_TAttribute ),
.sample_buffer_M_lockErr ( sample_buffer_M_lockErr ),
.sample_buffer_M_abort ( sample_buffer_M_abort ),
.sample_buffer_M_UABus ( sample_buffer_M_UABus ),
.sample_buffer_M_ABus ( sample_buffer_M_ABus ),
.sample_buffer_M_wrDBus ( sample_buffer_M_wrDBus ),
.sample_buffer_M_wrBurst ( sample_buffer_M_wrBurst ),
.sample_buffer_M_rdBurst ( sample_buffer_M_rdBurst ),
.sample_buffer_PLB_MAddrAck ( sample_buffer_PLB_MAddrAck ),
.sample_buffer_PLB_MSSize ( sample_buffer_PLB_MSSize ),
.sample_buffer_PLB_MRearbitrate ( sample_buffer_PLB_MRearbitrate ),
.sample_buffer_PLB_MTimeout ( sample_buffer_PLB_MTimeout ),
.sample_buffer_PLB_MBusy ( sample_buffer_PLB_MBusy ),
.sample_buffer_PLB_MRdErr ( sample_buffer_PLB_MRdErr ),
.sample_buffer_PLB_MWrErr ( sample_buffer_PLB_MWrErr ),
.sample_buffer_PLB_MIRQ ( sample_buffer_PLB_MIRQ ),
.sample_buffer_PLB_MRdDBus ( sample_buffer_PLB_MRdDBus ),
.sample_buffer_PLB_MRdWdAddr ( sample_buffer_PLB_MRdWdAddr ),
.sample_buffer_PLB_MRdDAck ( sample_buffer_PLB_MRdDAck ),
.sample_buffer_PLB_MRdBTerm ( sample_buffer_PLB_MRdBTerm ),
.sample_buffer_PLB_MWrDAck ( sample_buffer_PLB_MWrDAck ),
.sample_buffer_PLB_MWrBTerm ( sample_buffer_PLB_MWrBTerm ),
.splb_slv0_SPLB_Clk ( splb_slv0_SPLB_Clk ),
.splb_slv0_SPLB_Rst ( splb_slv0_SPLB_Rst ),
.splb_slv0_PLB_ABus ( splb_slv0_PLB_ABus ),
.splb_slv0_PLB_UABus ( splb_slv0_PLB_UABus ),
.splb_slv0_PLB_PAValid ( splb_slv0_PLB_PAValid ),
.splb_slv0_PLB_SAValid ( splb_slv0_PLB_SAValid ),
.splb_slv0_PLB_rdPrim ( splb_slv0_PLB_rdPrim ),
.splb_slv0_PLB_wrPrim ( splb_slv0_PLB_wrPrim ),
.splb_slv0_PLB_masterID ( splb_slv0_PLB_masterID ),
.splb_slv0_PLB_abort ( splb_slv0_PLB_abort ),
.splb_slv0_PLB_busLock ( splb_slv0_PLB_busLock ),
.splb_slv0_PLB_RNW ( splb_slv0_PLB_RNW ),
.splb_slv0_PLB_BE ( splb_slv0_PLB_BE ),
.splb_slv0_PLB_MSize ( splb_slv0_PLB_MSize ),
.splb_slv0_PLB_size ( splb_slv0_PLB_size ),
.splb_slv0_PLB_type ( splb_slv0_PLB_type ),
.splb_slv0_PLB_lockErr ( splb_slv0_PLB_lockErr ),
.splb_slv0_PLB_wrDBus ( splb_slv0_PLB_wrDBus ),
.splb_slv0_PLB_wrBurst ( splb_slv0_PLB_wrBurst ),
.splb_slv0_PLB_rdBurst ( splb_slv0_PLB_rdBurst ),
.splb_slv0_PLB_wrPendReq ( splb_slv0_PLB_wrPendReq ),
.splb_slv0_PLB_rdPendReq ( splb_slv0_PLB_rdPendReq ),
.splb_slv0_PLB_wrPendPri ( splb_slv0_PLB_wrPendPri ),
.splb_slv0_PLB_rdPendPri ( splb_slv0_PLB_rdPendPri ),
.splb_slv0_PLB_reqPri ( splb_slv0_PLB_reqPri ),
.splb_slv0_PLB_TAttribute ( splb_slv0_PLB_TAttribute ),
.splb_slv0_Sl_addrAck ( splb_slv0_Sl_addrAck ),
.splb_slv0_Sl_SSize ( splb_slv0_Sl_SSize ),
.splb_slv0_Sl_wait ( splb_slv0_Sl_wait ),
.splb_slv0_Sl_rearbitrate ( splb_slv0_Sl_rearbitrate ),
.splb_slv0_Sl_wrDAck ( splb_slv0_Sl_wrDAck ),
.splb_slv0_Sl_wrComp ( splb_slv0_Sl_wrComp ),
.splb_slv0_Sl_wrBTerm ( splb_slv0_Sl_wrBTerm ),
.splb_slv0_Sl_rdDBus ( splb_slv0_Sl_rdDBus ),
.splb_slv0_Sl_rdWdAddr ( splb_slv0_Sl_rdWdAddr ),
.splb_slv0_Sl_rdDAck ( splb_slv0_Sl_rdDAck ),
.splb_slv0_Sl_rdComp ( splb_slv0_Sl_rdComp ),
.splb_slv0_Sl_rdBTerm ( splb_slv0_Sl_rdBTerm ),
.splb_slv0_Sl_MBusy ( splb_slv0_Sl_MBusy ),
.splb_slv0_Sl_MWrErr ( splb_slv0_Sl_MWrErr ),
.splb_slv0_Sl_MRdErr ( splb_slv0_Sl_MRdErr ),
.splb_slv0_Sl_MIRQ ( splb_slv0_Sl_MIRQ )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_P_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_P_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_pwrgood_pp$P (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VPWR
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_P_SYMBOL_V
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: fb_block.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module fb_block (
address,
clock,
data,
wren,
q);
input [7:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR4_BLACKBOX_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_BLACKBOX_V
|
`ifndef xlConvPkgIncluded
`include "conv_pkg.v"
`endif
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/channelizer/fft1/Subsystem
module channelizer_256_subsystem_x0 (
input [32-1:0] in1,
output [16-1:0] imag,
output [16-1:0] real_x0
);
wire [16-1:0] reinterpret1_output_port_net;
wire [16-1:0] reinterpret_output_port_net;
wire [32-1:0] dual_port_ram_doutb_net;
wire [16-1:0] slice_y_net;
wire [16-1:0] slice1_y_net;
assign imag = reinterpret1_output_port_net;
assign real_x0 = reinterpret_output_port_net;
assign dual_port_ram_doutb_net = in1;
sysgen_reinterpret_4e0592666f reinterpret (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.input_port(slice_y_net),
.output_port(reinterpret_output_port_net)
);
sysgen_reinterpret_4e0592666f reinterpret1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.input_port(slice1_y_net),
.output_port(reinterpret1_output_port_net)
);
channelizer_256_xlslice #(
.new_lsb(0),
.new_msb(15),
.x_width(32),
.y_width(16)
)
slice (
.x(dual_port_ram_doutb_net),
.y(slice_y_net)
);
channelizer_256_xlslice #(
.new_lsb(16),
.new_msb(31),
.x_width(32),
.y_width(16)
)
slice1 (
.x(dual_port_ram_doutb_net),
.y(slice1_y_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/channelizer/fft1/Subsystem1
module channelizer_256_subsystem1_x0 (
input [25-1:0] imag,
input [25-1:0] real_x0,
input clk_1,
input ce_1,
output [32-1:0] out1
);
wire [32-1:0] concat_y_net;
wire [25-1:0] ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_im_0_net;
wire [25-1:0] ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_re_0_net;
wire clk_net;
wire ce_net;
wire [16-1:0] convert2_dout_net;
wire [16-1:0] reinterpret2_output_port_net;
wire [16-1:0] reinterpret1_output_port_net;
wire [16-1:0] convert_dout_net;
assign out1 = concat_y_net;
assign ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_im_0_net = imag;
assign ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_re_0_net = real_x0;
assign clk_net = clk_1;
assign ce_net = ce_1;
sysgen_concat_c4b57f4497 concat (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.in0(reinterpret2_output_port_net),
.in1(reinterpret1_output_port_net),
.y(concat_y_net)
);
channelizer_256_xlconvert #(
.bool_conversion(0),
.din_arith(2),
.din_bin_pt(15),
.din_width(25),
.dout_arith(2),
.dout_bin_pt(13),
.dout_width(16),
.latency(0),
.overflow(`xlSaturate),
.quantization(`xlTruncate)
)
convert (
.clr(1'b0),
.en(1'b1),
.din(ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_im_0_net),
.clk(clk_net),
.ce(ce_net),
.dout(convert_dout_net)
);
channelizer_256_xlconvert #(
.bool_conversion(0),
.din_arith(2),
.din_bin_pt(15),
.din_width(25),
.dout_arith(2),
.dout_bin_pt(13),
.dout_width(16),
.latency(0),
.overflow(`xlSaturate),
.quantization(`xlTruncate)
)
convert2 (
.clr(1'b0),
.en(1'b1),
.din(ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_re_0_net),
.clk(clk_net),
.ce(ce_net),
.dout(convert2_dout_net)
);
sysgen_reinterpret_3149fc1051 reinterpret1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.input_port(convert2_dout_net),
.output_port(reinterpret1_output_port_net)
);
sysgen_reinterpret_3149fc1051 reinterpret2 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.input_port(convert_dout_net),
.output_port(reinterpret2_output_port_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/channelizer/fft1
module channelizer_256_fft1 (
input [1-1:0] ready_out,
input [1-1:0] valid_in,
input [32-1:0] data_in,
input [1-1:0] last_in,
input [1-1:0] reset_in,
input clk_1,
input ce_1,
output ready_in,
output valid_out,
output [32-1:0] data_out
);
wire ifft_fast_fourier_transform_8_1_s_axis_data_tready_net;
wire ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net;
wire [32-1:0] concat_y_net;
wire [1-1:0] ready_out_net;
wire [1-1:0] logical_y_net_x0;
wire [32-1:0] dual_port_ram_doutb_net;
wire [1-1:0] delay1_q_net;
wire [1-1:0] logical_y_net;
wire clk_net;
wire ce_net;
wire [16-1:0] reinterpret1_output_port_net;
wire [16-1:0] reinterpret_output_port_net;
wire [25-1:0] ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_im_0_net;
wire [25-1:0] ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_re_0_net;
wire [1-1:0] ifft_op_net;
wire ifft_fast_fourier_transform_8_1_s_axis_config_tready_net;
wire ifft_fast_fourier_transform_8_1_m_axis_data_tlast_net;
wire ifft_fast_fourier_transform_8_1_event_frame_started_net;
wire ifft_fast_fourier_transform_8_1_event_tlast_unexpected_net;
wire ifft_fast_fourier_transform_8_1_event_tlast_missing_net;
wire ifft_fast_fourier_transform_8_1_event_data_in_channel_halt_net;
wire ifft_fast_fourier_transform_8_1_event_status_channel_halt_net;
wire ifft_fast_fourier_transform_8_1_event_data_out_channel_halt_net;
wire inverter_op_net;
assign ready_in = ifft_fast_fourier_transform_8_1_s_axis_data_tready_net;
assign valid_out = ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net;
assign data_out = concat_y_net;
assign ready_out_net = ready_out;
assign logical_y_net_x0 = valid_in;
assign dual_port_ram_doutb_net = data_in;
assign delay1_q_net = last_in;
assign logical_y_net = reset_in;
assign clk_net = clk_1;
assign ce_net = ce_1;
channelizer_256_subsystem_x0 subsystem_x4 (
.in1(dual_port_ram_doutb_net),
.imag(reinterpret1_output_port_net),
.real_x0(reinterpret_output_port_net)
);
channelizer_256_subsystem1_x0 subsystem1 (
.imag(ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_im_0_net),
.real_x0(ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_re_0_net),
.clk_1(clk_net),
.ce_1(ce_net),
.out1(concat_y_net)
);
sysgen_constant_b7c50d0aca ifft (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(ifft_op_net)
);
xlfast_fourier_transform_fff9011127114b5dfa3d6ad9e3e76129 ifft_fast_fourier_transform_8_1 (
.s_axis_config_tdata_fwd_inv(ifft_op_net),
.s_axis_config_tvalid(ifft_fast_fourier_transform_8_1_s_axis_config_tready_net),
.s_axis_data_tdata_xn_im_0(reinterpret1_output_port_net),
.s_axis_data_tdata_xn_re_0(reinterpret_output_port_net),
.s_axis_data_tvalid(logical_y_net_x0),
.s_axis_data_tlast(delay1_q_net),
.m_axis_data_tready(ready_out_net),
.rst(inverter_op_net),
.clk(clk_net),
.ce(ce_net),
.s_axis_config_tready(ifft_fast_fourier_transform_8_1_s_axis_config_tready_net),
.s_axis_data_tready(ifft_fast_fourier_transform_8_1_s_axis_data_tready_net),
.m_axis_data_tdata_xn_im_0(ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_im_0_net),
.m_axis_data_tdata_xn_re_0(ifft_fast_fourier_transform_8_1_m_axis_data_tdata_xn_re_0_net),
.m_axis_data_tvalid(ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net),
.m_axis_data_tlast(ifft_fast_fourier_transform_8_1_m_axis_data_tlast_net),
.event_frame_started(ifft_fast_fourier_transform_8_1_event_frame_started_net),
.event_tlast_unexpected(ifft_fast_fourier_transform_8_1_event_tlast_unexpected_net),
.event_tlast_missing(ifft_fast_fourier_transform_8_1_event_tlast_missing_net),
.event_data_in_channel_halt(ifft_fast_fourier_transform_8_1_event_data_in_channel_halt_net),
.event_status_channel_halt(ifft_fast_fourier_transform_8_1_event_status_channel_halt_net),
.event_data_out_channel_halt(ifft_fast_fourier_transform_8_1_event_data_out_channel_halt_net)
);
sysgen_inverter_692c4e9d5f inverter (
.clr(1'b0),
.ip(logical_y_net),
.clk(clk_net),
.ce(ce_net),
.op(inverter_op_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/channelizer/frame_reverse
module channelizer_256_frame_reverse (
input ready_out,
input valid_in,
input [32-1:0] data_in,
input last_in,
input [1-1:0] reset_in,
input clk_1,
input ce_1,
output [1-1:0] valid_out,
output [32-1:0] data_out,
output [1-1:0] last_out
);
wire ce_net;
wire [1-1:0] constant1_op_net;
wire [1-1:0] logical_y_net_x0;
wire [32-1:0] dual_port_ram_doutb_net;
wire [1-1:0] delay1_q_net;
wire ifft_fast_fourier_transform_8_1_s_axis_data_tready_net;
wire fir_compiler_7_2_1_m_axis_data_tvalid_net;
wire [32-1:0] concat_y_net;
wire fir_compiler_7_2_1_m_axis_data_tlast_net;
wire [1-1:0] logical_y_net;
wire clk_net;
wire [32-1:0] constant_op_net;
wire [1-1:0] constant2_op_net;
wire [9-1:0] counter_op_net;
wire [1-1:0] logical1_y_net;
wire [9-1:0] counter2_op_net;
wire [1-1:0] delay_q_net;
wire [32-1:0] dual_port_ram_douta_net;
assign valid_out = logical_y_net_x0;
assign data_out = dual_port_ram_doutb_net;
assign last_out = delay1_q_net;
assign ifft_fast_fourier_transform_8_1_s_axis_data_tready_net = ready_out;
assign fir_compiler_7_2_1_m_axis_data_tvalid_net = valid_in;
assign concat_y_net = data_in;
assign fir_compiler_7_2_1_m_axis_data_tlast_net = last_in;
assign logical_y_net = reset_in;
assign clk_net = clk_1;
assign ce_net = ce_1;
sysgen_constant_0430b901da constant (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant_op_net)
);
sysgen_constant_f007950b6c constant1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant1_op_net)
);
sysgen_constant_b7c50d0aca constant2 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant2_op_net)
);
channelizer_256_xlcounter_free #(
.core_name0("channelizer_256_c_counter_binary_v12_0_0"),
.op_arith(`xlUnsigned),
.op_width(9)
)
counter (
.clr(1'b0),
.rst(logical_y_net),
.en(logical1_y_net),
.clk(clk_net),
.ce(ce_net),
.op(counter_op_net)
);
channelizer_256_xlcounter_free #(
.core_name0("channelizer_256_c_counter_binary_v12_0_1"),
.op_arith(`xlUnsigned),
.op_width(9)
)
counter2 (
.clr(1'b0),
.rst(logical_y_net),
.en(logical1_y_net),
.clk(clk_net),
.ce(ce_net),
.op(counter2_op_net)
);
sysgen_delay_be4b47a029 delay (
.clr(1'b0),
.d(constant2_op_net),
.rst(logical_y_net),
.en(logical1_y_net),
.clk(clk_net),
.ce(ce_net),
.q(delay_q_net)
);
sysgen_delay_9d893c921a delay1 (
.clr(1'b0),
.d(fir_compiler_7_2_1_m_axis_data_tlast_net),
.rst(logical_y_net),
.en(logical1_y_net),
.clk(clk_net),
.ce(ce_net),
.q(delay1_q_net)
);
channelizer_256_xldpram #(
.c_address_width_a(9),
.c_address_width_b(9),
.c_width_a(32),
.c_width_b(32),
.core_name0("channelizer_256_blk_mem_gen_v8_2_0"),
.latency(1)
)
dual_port_ram (
.addra(counter_op_net),
.dina(concat_y_net),
.wea(logical1_y_net),
.addrb(counter2_op_net),
.dinb(constant_op_net),
.web(constant1_op_net),
.rsta(logical_y_net),
.rstb(logical_y_net),
.ena(logical1_y_net),
.enb(logical1_y_net),
.a_clk(clk_net),
.a_ce(ce_net),
.b_clk(clk_net),
.b_ce(ce_net),
.douta(dual_port_ram_douta_net),
.doutb(dual_port_ram_doutb_net)
);
sysgen_logical_2d2e86ecb2 logical (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(delay_q_net),
.d1(fir_compiler_7_2_1_m_axis_data_tvalid_net),
.y(logical_y_net_x0)
);
sysgen_logical_2d2e86ecb2 logical1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(ifft_fast_fourier_transform_8_1_s_axis_data_tready_net),
.d1(fir_compiler_7_2_1_m_axis_data_tvalid_net),
.y(logical1_y_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/channelizer/poly_phase_filter/Subsystem
module channelizer_256_subsystem (
input [32-1:0] in1,
input clk_1,
input ce_1,
output [18-1:0] imag,
output [18-1:0] real_x0
);
wire [18-1:0] convert_dout_net;
wire [18-1:0] convert1_dout_net;
wire [32-1:0] data_in_net;
wire clk_net;
wire ce_net;
wire [16-1:0] reinterpret3_output_port_net;
wire [16-1:0] reinterpret_output_port_net;
wire [16-1:0] lower_y_net;
wire [16-1:0] upper_y_net;
assign imag = convert_dout_net;
assign real_x0 = convert1_dout_net;
assign data_in_net = in1;
assign clk_net = clk_1;
assign ce_net = ce_1;
channelizer_256_xlconvert #(
.bool_conversion(0),
.din_arith(2),
.din_bin_pt(0),
.din_width(16),
.dout_arith(2),
.dout_bin_pt(0),
.dout_width(18),
.latency(0),
.overflow(`xlWrap),
.quantization(`xlTruncate)
)
convert (
.clr(1'b0),
.en(1'b1),
.din(reinterpret3_output_port_net),
.clk(clk_net),
.ce(ce_net),
.dout(convert_dout_net)
);
channelizer_256_xlconvert #(
.bool_conversion(0),
.din_arith(2),
.din_bin_pt(0),
.din_width(16),
.dout_arith(2),
.dout_bin_pt(0),
.dout_width(18),
.latency(0),
.overflow(`xlWrap),
.quantization(`xlTruncate)
)
convert1 (
.clr(1'b0),
.en(1'b1),
.din(reinterpret_output_port_net),
.clk(clk_net),
.ce(ce_net),
.dout(convert1_dout_net)
);
sysgen_reinterpret_4e0592666f reinterpret (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.input_port(lower_y_net),
.output_port(reinterpret_output_port_net)
);
sysgen_reinterpret_4e0592666f reinterpret3 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.input_port(upper_y_net),
.output_port(reinterpret3_output_port_net)
);
channelizer_256_xlslice #(
.new_lsb(0),
.new_msb(15),
.x_width(32),
.y_width(16)
)
lower (
.x(data_in_net),
.y(lower_y_net)
);
channelizer_256_xlslice #(
.new_lsb(16),
.new_msb(31),
.x_width(32),
.y_width(16)
)
upper (
.x(data_in_net),
.y(upper_y_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/channelizer/poly_phase_filter/Subsystem1
module channelizer_256_subsystem1 (
input [34-1:0] imag,
input [34-1:0] real_x0,
output [32-1:0] out1
);
wire [32-1:0] concat_y_net;
wire [34-1:0] fir_compiler_7_2_1_m_axis_data_tdata_path1_net;
wire [34-1:0] fir_compiler_7_2_1_m_axis_data_tdata_path0_net;
wire [16-1:0] slice1_y_net;
wire [16-1:0] slice_y_net;
wire [34-1:0] reinterpret1_output_port_net;
wire [34-1:0] reinterpret2_output_port_net;
assign out1 = concat_y_net;
assign fir_compiler_7_2_1_m_axis_data_tdata_path1_net = imag;
assign fir_compiler_7_2_1_m_axis_data_tdata_path0_net = real_x0;
sysgen_concat_c4b57f4497 concat (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.in0(slice1_y_net),
.in1(slice_y_net),
.y(concat_y_net)
);
sysgen_reinterpret_6f16badb5b reinterpret1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.input_port(fir_compiler_7_2_1_m_axis_data_tdata_path0_net),
.output_port(reinterpret1_output_port_net)
);
sysgen_reinterpret_6f16badb5b reinterpret2 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.input_port(fir_compiler_7_2_1_m_axis_data_tdata_path1_net),
.output_port(reinterpret2_output_port_net)
);
channelizer_256_xlslice #(
.new_lsb(15),
.new_msb(30),
.x_width(34),
.y_width(16)
)
slice (
.x(reinterpret1_output_port_net),
.y(slice_y_net)
);
channelizer_256_xlslice #(
.new_lsb(15),
.new_msb(30),
.x_width(34),
.y_width(16)
)
slice1 (
.x(reinterpret2_output_port_net),
.y(slice1_y_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/channelizer/poly_phase_filter/Subsystem2
module channelizer_256_subsystem2 (
input ready_in,
input [1-1:0] reset_in,
input clk_1,
input ce_1,
output [1-1:0] valid_out,
output [1-1:0] last_out,
output [8-1:0] data_out
);
wire [1-1:0] relational_op_net;
wire [8-1:0] counter_op_net;
wire fir_compiler_7_2_1_s_axis_config_tready_net;
wire [1-1:0] logical_y_net;
wire clk_net;
wire ce_net;
wire [1-1:0] inverter_op_net;
wire [8-1:0] constant_op_net;
wire [1-1:0] constant1_op_net;
wire [1-1:0] delay_q_net;
assign valid_out = inverter_op_net;
assign last_out = relational_op_net;
assign data_out = counter_op_net;
assign fir_compiler_7_2_1_s_axis_config_tready_net = ready_in;
assign logical_y_net = reset_in;
assign clk_net = clk_1;
assign ce_net = ce_1;
sysgen_constant_39c35f37c7 constant (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant_op_net)
);
sysgen_constant_b7c50d0aca constant1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant1_op_net)
);
channelizer_256_xlcounter_free #(
.core_name0("channelizer_256_c_counter_binary_v12_0_2"),
.op_arith(`xlUnsigned),
.op_width(8)
)
counter (
.clr(1'b0),
.rst(logical_y_net),
.en(fir_compiler_7_2_1_s_axis_config_tready_net),
.clk(clk_net),
.ce(ce_net),
.op(counter_op_net)
);
sysgen_delay_9d893c921a delay (
.clr(1'b0),
.d(constant1_op_net),
.rst(logical_y_net),
.en(relational_op_net),
.clk(clk_net),
.ce(ce_net),
.q(delay_q_net)
);
sysgen_inverter_692c4e9d5f inverter (
.clr(1'b0),
.ip(delay_q_net),
.clk(clk_net),
.ce(ce_net),
.op(inverter_op_net)
);
sysgen_relational_004edd55c3 relational (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.a(constant_op_net),
.b(counter_op_net),
.op(relational_op_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/channelizer/poly_phase_filter/Subsystem3
module channelizer_256_subsystem3 (
input ready,
input [1-1:0] reset_in,
input [1-1:0] valid,
input clk_1,
input ce_1,
output [1-1:0] last_out
);
wire [1-1:0] relational_op_net;
wire fir_compiler_7_2_1_s_axis_data_tready_net;
wire [1-1:0] logical_y_net_x0;
wire [1-1:0] valid_in_net;
wire clk_net;
wire ce_net;
wire [8-1:0] constant_op_net;
wire [8-1:0] counter_op_net;
wire [1-1:0] logical_y_net;
assign last_out = relational_op_net;
assign fir_compiler_7_2_1_s_axis_data_tready_net = ready;
assign logical_y_net_x0 = reset_in;
assign valid_in_net = valid;
assign clk_net = clk_1;
assign ce_net = ce_1;
sysgen_constant_39c35f37c7 constant (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant_op_net)
);
channelizer_256_xlcounter_free #(
.core_name0("channelizer_256_c_counter_binary_v12_0_2"),
.op_arith(`xlUnsigned),
.op_width(8)
)
counter (
.clr(1'b0),
.rst(logical_y_net_x0),
.en(logical_y_net),
.clk(clk_net),
.ce(ce_net),
.op(counter_op_net)
);
sysgen_logical_2d2e86ecb2 logical (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(fir_compiler_7_2_1_s_axis_data_tready_net),
.d1(valid_in_net),
.y(logical_y_net)
);
sysgen_relational_004edd55c3 relational (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.a(constant_op_net),
.b(counter_op_net),
.op(relational_op_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/channelizer/poly_phase_filter
module channelizer_256_poly_phase_filter (
input ready_out,
input [1-1:0] valid_in,
input [32-1:0] data_in,
input [1-1:0] last_in,
input [1-1:0] reset_in,
input clk_1,
input ce_1,
output ready_in,
output valid_out,
output [32-1:0] data_out,
output last_out
);
wire fir_compiler_7_2_1_s_axis_data_tready_net;
wire fir_compiler_7_2_1_m_axis_data_tvalid_net;
wire [32-1:0] concat_y_net;
wire fir_compiler_7_2_1_m_axis_data_tlast_net;
wire ifft_fast_fourier_transform_8_1_s_axis_data_tready_net;
wire [1-1:0] valid_in_net;
wire [32-1:0] data_in_net;
wire [1-1:0] last_in_net;
wire [1-1:0] logical_y_net;
wire clk_net;
wire ce_net;
wire [18-1:0] convert_dout_net;
wire [18-1:0] convert1_dout_net;
wire [34-1:0] fir_compiler_7_2_1_m_axis_data_tdata_path1_net;
wire [34-1:0] fir_compiler_7_2_1_m_axis_data_tdata_path0_net;
wire [1-1:0] inverter_op_net_x0;
wire [1-1:0] relational_op_net;
wire [8-1:0] counter_op_net;
wire fir_compiler_7_2_1_s_axis_config_tready_net;
wire [1-1:0] relational_op_net_x0;
wire fir_compiler_7_2_1_event_s_data_tlast_missing_net;
wire fir_compiler_7_2_1_event_s_data_tlast_unexpected_net;
wire fir_compiler_7_2_1_event_s_config_tlast_missing_net;
wire fir_compiler_7_2_1_event_s_config_tlast_unexpected_net;
wire inverter_op_net;
assign ready_in = fir_compiler_7_2_1_s_axis_data_tready_net;
assign valid_out = fir_compiler_7_2_1_m_axis_data_tvalid_net;
assign data_out = concat_y_net;
assign last_out = fir_compiler_7_2_1_m_axis_data_tlast_net;
assign ifft_fast_fourier_transform_8_1_s_axis_data_tready_net = ready_out;
assign valid_in_net = valid_in;
assign data_in_net = data_in;
assign last_in_net = last_in;
assign logical_y_net = reset_in;
assign clk_net = clk_1;
assign ce_net = ce_1;
channelizer_256_subsystem subsystem_x4 (
.in1(data_in_net),
.clk_1(clk_net),
.ce_1(ce_net),
.imag(convert_dout_net),
.real_x0(convert1_dout_net)
);
channelizer_256_subsystem1 subsystem1 (
.imag(fir_compiler_7_2_1_m_axis_data_tdata_path1_net),
.real_x0(fir_compiler_7_2_1_m_axis_data_tdata_path0_net),
.out1(concat_y_net)
);
channelizer_256_subsystem2 subsystem2 (
.ready_in(fir_compiler_7_2_1_s_axis_config_tready_net),
.reset_in(logical_y_net),
.clk_1(clk_net),
.ce_1(ce_net),
.valid_out(inverter_op_net_x0),
.last_out(relational_op_net),
.data_out(counter_op_net)
);
channelizer_256_subsystem3 subsystem3 (
.ready(fir_compiler_7_2_1_s_axis_data_tready_net),
.reset_in(logical_y_net),
.valid(valid_in_net),
.clk_1(clk_net),
.ce_1(ce_net),
.last_out(relational_op_net_x0)
);
xlfir_compiler_573796d8d5d147c7c9fe715a25c3e2c7 fir_compiler_7_2_1 (
.s_axis_data_tvalid(valid_in_net),
.s_axis_data_tlast(relational_op_net_x0),
.s_axis_data_tdata_path1(convert_dout_net),
.s_axis_data_tdata_path0(convert1_dout_net),
.s_axis_config_tvalid(inverter_op_net_x0),
.s_axis_config_tlast(relational_op_net),
.s_axis_config_tdata_fsel(counter_op_net),
.m_axis_data_tready(ifft_fast_fourier_transform_8_1_s_axis_data_tready_net),
.rst(inverter_op_net),
.src_clk(clk_net),
.src_ce(ce_net),
.clk(clk_net),
.ce(ce_net),
.s_axis_data_tready(fir_compiler_7_2_1_s_axis_data_tready_net),
.s_axis_config_tready(fir_compiler_7_2_1_s_axis_config_tready_net),
.m_axis_data_tvalid(fir_compiler_7_2_1_m_axis_data_tvalid_net),
.m_axis_data_tlast(fir_compiler_7_2_1_m_axis_data_tlast_net),
.m_axis_data_tdata_path1(fir_compiler_7_2_1_m_axis_data_tdata_path1_net),
.m_axis_data_tdata_path0(fir_compiler_7_2_1_m_axis_data_tdata_path0_net),
.event_s_data_tlast_missing(fir_compiler_7_2_1_event_s_data_tlast_missing_net),
.event_s_data_tlast_unexpected(fir_compiler_7_2_1_event_s_data_tlast_unexpected_net),
.event_s_config_tlast_missing(fir_compiler_7_2_1_event_s_config_tlast_missing_net),
.event_s_config_tlast_unexpected(fir_compiler_7_2_1_event_s_config_tlast_unexpected_net)
);
sysgen_inverter_692c4e9d5f inverter (
.clr(1'b0),
.ip(logical_y_net),
.clk(clk_net),
.ce(ce_net),
.op(inverter_op_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/channelizer/reset_register
module channelizer_256_reset_register (
input [1-1:0] set_stb,
input [8-1:0] set_addr,
input clk_1,
input ce_1,
output [1-1:0] reset_out
);
wire [1-1:0] delay_q_net;
wire [1-1:0] set_stb_in_net;
wire [8-1:0] set_addr_in_net;
wire clk_net;
wire ce_net;
wire [1-1:0] constant_op_net;
wire [2-1:0] counter_op_net;
wire [1-1:0] relational1_op_net;
wire [1-1:0] logical_y_net;
wire [1-1:0] relational_op_net;
wire [8-1:0] address_op_net;
wire [2-1:0] address1_op_net;
assign reset_out = delay_q_net;
assign set_stb_in_net = set_stb;
assign set_addr_in_net = set_addr;
assign clk_net = clk_1;
assign ce_net = ce_1;
sysgen_constant_b7c50d0aca constant (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant_op_net)
);
channelizer_256_xlcounter_free #(
.core_name0("channelizer_256_c_counter_binary_v12_0_3"),
.op_arith(`xlUnsigned),
.op_width(2)
)
counter (
.clr(1'b0),
.rst(relational1_op_net),
.en(delay_q_net),
.clk(clk_net),
.ce(ce_net),
.op(counter_op_net)
);
sysgen_delay_9d893c921a delay (
.clr(1'b0),
.d(constant_op_net),
.rst(relational1_op_net),
.en(logical_y_net),
.clk(clk_net),
.ce(ce_net),
.q(delay_q_net)
);
sysgen_logical_2d2e86ecb2 logical (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(set_stb_in_net),
.d1(relational_op_net),
.y(logical_y_net)
);
sysgen_relational_004edd55c3 relational (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.a(set_addr_in_net),
.b(address_op_net),
.op(relational_op_net)
);
sysgen_relational_dfd2a4be8a relational1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.a(counter_op_net),
.b(address1_op_net),
.op(relational1_op_net)
);
sysgen_constant_9a49104451 address (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(address_op_net)
);
sysgen_constant_88effd842b address1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(address1_op_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/channelizer
module channelizer_256_channelizer (
input [1-1:0] ready_out,
input [1-1:0] valid_in,
input [32-1:0] data_in,
input [1-1:0] last_in,
input [1-1:0] reset_in,
input [1-1:0] set_stb_in,
input [8-1:0] set_addr_in,
input clk_1,
input ce_1,
output ready_in,
output valid_out,
output [32-1:0] data_out,
output last_out,
output [1-1:0] reset_out
);
wire fir_compiler_7_2_1_s_axis_data_tready_net;
wire ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net;
wire [32-1:0] concat_y_net_x0;
wire axi_fifo_m_axis_tlast_net;
wire [1-1:0] logical_y_net;
wire [1-1:0] ready_out_net;
wire [1-1:0] valid_in_net;
wire [32-1:0] data_in_net;
wire [1-1:0] last_in_net;
wire [1-1:0] reset_in_net;
wire [1-1:0] set_stb_in_net;
wire [8-1:0] set_addr_in_net;
wire clk_net;
wire ce_net;
wire ifft_fast_fourier_transform_8_1_s_axis_data_tready_net;
wire [1-1:0] logical_y_net_x0;
wire [32-1:0] dual_port_ram_doutb_net;
wire [1-1:0] delay1_q_net;
wire fir_compiler_7_2_1_m_axis_data_tvalid_net;
wire [32-1:0] concat_y_net;
wire fir_compiler_7_2_1_m_axis_data_tlast_net;
wire [1-1:0] delay_q_net;
wire axi_fifo_m_axis_tvalid_net;
wire [8-1:0] axi_fifo_m_axis_tdata_net;
wire axi_fifo_s_axis_tready_net;
wire inverter_op_net;
wire logical2_y_net;
wire logical1_y_net;
wire [8-1:0] constant_op_net;
assign ready_in = fir_compiler_7_2_1_s_axis_data_tready_net;
assign valid_out = ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net;
assign data_out = concat_y_net_x0;
assign last_out = axi_fifo_m_axis_tlast_net;
assign reset_out = logical_y_net;
assign ready_out_net = ready_out;
assign valid_in_net = valid_in;
assign data_in_net = data_in;
assign last_in_net = last_in;
assign reset_in_net = reset_in;
assign set_stb_in_net = set_stb_in;
assign set_addr_in_net = set_addr_in;
assign clk_net = clk_1;
assign ce_net = ce_1;
channelizer_256_fft1 fft1 (
.ready_out(ready_out_net),
.valid_in(logical_y_net_x0),
.data_in(dual_port_ram_doutb_net),
.last_in(delay1_q_net),
.reset_in(logical_y_net),
.clk_1(clk_net),
.ce_1(ce_net),
.ready_in(ifft_fast_fourier_transform_8_1_s_axis_data_tready_net),
.valid_out(ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net),
.data_out(concat_y_net_x0)
);
channelizer_256_frame_reverse frame_reverse (
.ready_out(ifft_fast_fourier_transform_8_1_s_axis_data_tready_net),
.valid_in(fir_compiler_7_2_1_m_axis_data_tvalid_net),
.data_in(concat_y_net),
.last_in(fir_compiler_7_2_1_m_axis_data_tlast_net),
.reset_in(logical_y_net),
.clk_1(clk_net),
.ce_1(ce_net),
.valid_out(logical_y_net_x0),
.data_out(dual_port_ram_doutb_net),
.last_out(delay1_q_net)
);
channelizer_256_poly_phase_filter poly_phase_filter (
.ready_out(ifft_fast_fourier_transform_8_1_s_axis_data_tready_net),
.valid_in(valid_in_net),
.data_in(data_in_net),
.last_in(last_in_net),
.reset_in(logical_y_net),
.clk_1(clk_net),
.ce_1(ce_net),
.ready_in(fir_compiler_7_2_1_s_axis_data_tready_net),
.valid_out(fir_compiler_7_2_1_m_axis_data_tvalid_net),
.data_out(concat_y_net),
.last_out(fir_compiler_7_2_1_m_axis_data_tlast_net)
);
channelizer_256_reset_register reset_register (
.set_stb(set_stb_in_net),
.set_addr(set_addr_in_net),
.clk_1(clk_net),
.ce_1(ce_net),
.reset_out(delay_q_net)
);
channelizer_256_xlaxififogen #(
.core_name0("channelizer_256_fifo_generator_v12_0_0"),
.depth_bits(13),
.has_aresetn(1),
.tdata_width(8),
.tdest_width(4),
.tid_width(8),
.tuser_width(4)
)
axi_fifo (
.aresetn(inverter_op_net),
.m_axis_tready(logical2_y_net),
.s_axis_tvalid(logical1_y_net),
.s_axis_tdata(constant_op_net),
.s_axis_tlast(last_in_net),
.s_aclk(clk_net),
.ce(ce_net),
.m_axis_tvalid(axi_fifo_m_axis_tvalid_net),
.m_axis_tdata(axi_fifo_m_axis_tdata_net),
.m_axis_tlast(axi_fifo_m_axis_tlast_net),
.s_axis_tready(axi_fifo_s_axis_tready_net)
);
sysgen_constant_b12bb16a5f constant (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant_op_net)
);
sysgen_inverter_692c4e9d5f inverter (
.clr(1'b0),
.ip(logical_y_net),
.clk(clk_net),
.ce(ce_net),
.op(inverter_op_net)
);
sysgen_logical_0bf9ba7bf4 logical (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(delay_q_net),
.d1(reset_in_net),
.y(logical_y_net)
);
sysgen_logical_2d2e86ecb2 logical1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(fir_compiler_7_2_1_s_axis_data_tready_net),
.d1(valid_in_net),
.y(logical1_y_net)
);
sysgen_logical_2d2e86ecb2 logical2 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(ready_out_net),
.d1(ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net),
.y(logical2_y_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/implementation_interface_in
module channelizer_256_implementation_interface_in (
input ready_out,
input [32-1:0] data_in,
input [1-1:0] last_in,
input [1-1:0] reset_in,
input [8-1:0] set_addr_in,
input [1-1:0] set_stb_in,
input [1-1:0] valid_in
);
wire fir_compiler_7_2_1_s_axis_data_tready_net;
wire [32-1:0] data_in_net;
wire [1-1:0] last_in_net;
wire [1-1:0] reset_in_net;
wire [8-1:0] set_addr_in_net;
wire [1-1:0] set_stb_in_net;
wire [1-1:0] valid_in_net;
assign fir_compiler_7_2_1_s_axis_data_tready_net = ready_out;
assign data_in_net = data_in;
assign last_in_net = last_in;
assign reset_in_net = reset_in;
assign set_addr_in_net = set_addr_in;
assign set_stb_in_net = set_stb_in;
assign valid_in_net = valid_in;
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256/implementation_interface_out
module channelizer_256_implementation_interface_out (
input valid_in,
input [32-1:0] data_in,
input last_in,
input [1-1:0] reset_in,
input [1-1:0] set_strb_in,
input [8-1:0] set_addr_in,
input [1-1:0] ready_out
);
wire ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net;
wire [32-1:0] concat_y_net;
wire axi_fifo_m_axis_tlast_net;
wire [1-1:0] logical_y_net;
wire [1-1:0] set_stb_in_net;
wire [8-1:0] set_addr_in_net;
wire [1-1:0] ready_out_net;
assign ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net = valid_in;
assign concat_y_net = data_in;
assign axi_fifo_m_axis_tlast_net = last_in;
assign logical_y_net = reset_in;
assign set_stb_in_net = set_strb_in;
assign set_addr_in_net = set_addr_in;
assign ready_out_net = ready_out;
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block channelizer_256_struct
module channelizer_256_struct (
input [32-1:0] data_in,
input [1-1:0] last_in,
input [1-1:0] reset_in,
input [8-1:0] set_addr_in,
input [32-1:0] set_data_in,
input [1-1:0] set_stb_in,
input [1-1:0] valid_in,
input [1-1:0] ready_out,
input clk_1,
input ce_1,
output [1-1:0] ready_in,
output [32-1:0] data_out,
output [1-1:0] last_out,
output [1-1:0] valid_out
);
wire [1-1:0] axi_fifo_m_axis_tlast_net;
wire [1-1:0] ready_out_net;
wire [1-1:0] ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net;
wire clk_net;
wire ce_net;
wire [1-1:0] logical_y_net;
wire [32-1:0] data_in_net;
wire [1-1:0] last_in_net;
wire [1-1:0] fir_compiler_7_2_1_s_axis_data_tready_net;
wire [1-1:0] reset_in_net;
wire [8-1:0] set_addr_in_net;
wire [32-1:0] set_data_in_net;
wire [1-1:0] set_stb_in_net;
wire [1-1:0] valid_in_net;
wire [32-1:0] concat_y_net;
assign data_in_net = data_in;
assign last_in_net = last_in;
assign ready_in = fir_compiler_7_2_1_s_axis_data_tready_net;
assign reset_in_net = reset_in;
assign set_addr_in_net = set_addr_in;
assign set_data_in_net = set_data_in;
assign set_stb_in_net = set_stb_in;
assign valid_in_net = valid_in;
assign data_out = concat_y_net;
assign last_out = axi_fifo_m_axis_tlast_net;
assign ready_out_net = ready_out;
assign valid_out = ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net;
assign clk_net = clk_1;
assign ce_net = ce_1;
channelizer_256_channelizer channelizer (
.ready_out(ready_out_net),
.valid_in(valid_in_net),
.data_in(data_in_net),
.last_in(last_in_net),
.reset_in(reset_in_net),
.set_stb_in(set_stb_in_net),
.set_addr_in(set_addr_in_net),
.clk_1(clk_net),
.ce_1(ce_net),
.ready_in(fir_compiler_7_2_1_s_axis_data_tready_net),
.valid_out(ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net),
.data_out(concat_y_net),
.last_out(axi_fifo_m_axis_tlast_net),
.reset_out(logical_y_net)
);
channelizer_256_implementation_interface_in implementation_interface_in (
.ready_out(fir_compiler_7_2_1_s_axis_data_tready_net),
.data_in(data_in_net),
.last_in(last_in_net),
.reset_in(reset_in_net),
.set_addr_in(set_addr_in_net),
.set_stb_in(set_stb_in_net),
.valid_in(valid_in_net)
);
channelizer_256_implementation_interface_out implementation_interface_out (
.valid_in(ifft_fast_fourier_transform_8_1_m_axis_data_tvalid_net),
.data_in(concat_y_net),
.last_in(axi_fifo_m_axis_tlast_net),
.reset_in(logical_y_net),
.set_strb_in(set_stb_in_net),
.set_addr_in(set_addr_in_net),
.ready_out(ready_out_net)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block
module channelizer_256_default_clock_driver (
input channelizer_256_sysclk,
input channelizer_256_sysce,
input channelizer_256_sysclr,
output channelizer_256_clk1,
output channelizer_256_ce1
);
xlclockdriver #(
.period(1),
.log_2_period(1)
)
clockdriver (
.sysclk(channelizer_256_sysclk),
.sysce(channelizer_256_sysce),
.sysclr(channelizer_256_sysclr),
.clk(channelizer_256_clk1),
.ce(channelizer_256_ce1)
);
endmodule
`timescale 1 ns / 10 ps
// Generated from Simulink block
(* core_generation_info = "channelizer_256,sysgen_core_2015_2,{,compilation=Synthesized Checkpoint,block_icon_display=Default,family=kintex7,part=xc7k410t,speed=-2,package=ffg900,synthesis_language=verilog,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=1,ce_clr=0,clock_period=5,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=50000,axi_fifo=1,concat=2,constant=11,convert=4,counter=5,delay=4,dpram=1,fir_compiler_v7_2=1,inv=4,logical=12,reinterpret=18,relational=4,slice=16,xfft_v9_0=1,}" *)
module channelizer_256 (
input [32-1:0] data_in,
input [1-1:0] last_in,
input [1-1:0] reset_in,
input [8-1:0] set_addr_in,
input [32-1:0] set_data_in,
input [1-1:0] set_stb_in,
input [1-1:0] valid_in,
input [1-1:0] ready_out,
input clk,
output [1-1:0] ready_in,
output [32-1:0] data_out,
output [1-1:0] last_out,
output [1-1:0] valid_out
);
wire clk_1_net;
wire ce_1_net;
channelizer_256_default_clock_driver channelizer_256_default_clock_driver (
.channelizer_256_sysclk(clk),
.channelizer_256_sysce(1'b1),
.channelizer_256_sysclr(1'b0),
.channelizer_256_clk1(clk_1_net),
.channelizer_256_ce1(ce_1_net)
);
channelizer_256_struct channelizer_256_struct (
.data_in(data_in),
.last_in(last_in),
.reset_in(reset_in),
.set_addr_in(set_addr_in),
.set_data_in(set_data_in),
.set_stb_in(set_stb_in),
.valid_in(valid_in),
.ready_out(ready_out),
.clk_1(clk_1_net),
.ce_1(ce_1_net),
.ready_in(ready_in),
.data_out(data_out),
.last_out(last_out),
.valid_out(valid_out)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O32A_FUNCTIONAL_PP_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32A_FUNCTIONAL_PP_V |
/*
Project: RECON 2017
Author: Jeff Lieu <[email protected]>
Description: recon_0_top level
*/
/* Note that the PORT_0_WIDTH doesn't propagate to the NIOS system */
module recon_1_top #(parameter PORT_0_WIDTH = 32) (
input sys_clk,
input sys_rstn,
inout [ PORT_0_WIDTH-1:0] port_0_io,
output uart_0_txd,
input uart_0_rxd,
output wire epcs_0_dclk, // epcs_0.dclk
output wire epcs_0_sce, // .sce
output wire epcs_0_sdo, // .sdo
input wire epcs_0_data0
);
wire [PORT_0_WIDTH-1:0] port_0_out;
wire [PORT_0_WIDTH-1:0] port_0_in;
wire [PORT_0_WIDTH-1:0] port_0_oe;
wire [PORT_0_WIDTH-1:0] port_0_opdrn;
buttonDebouncer
#( /* Debounce time - Count in nanosecond */
.pDEBOUNCE_PERIOD (100_000_000),
/* Clock Input period - Count in nanosecond */
.pCLKIN_PERIOD (20 ),
/* Size of button array */
.pARRAY_SIZE (1 ),
/*
Polarity configures the edge detection which edge would cause a tick
Buttons are default to active low, which means a "Button Down" event is generated when the signal level fall from High to Low
Active high (pPOLARITY = 1) means a Button Down when the signal level changes from Low to High
*/
.pPOLARITY (0)) resetDebounce
(
.clk (sys_clk),
.buttons (sys_rstn),
.buttonState (sys_rstn_db), /* In Verilog, you can have an implied net declaration */
.buttonUpTick (),
.buttonDwTick ()
);
/* NIOS System - Configured and Generated by QSYS */
recon_1 (
.altpll_0_locked_export ( ), // altpll_0_locked.export
.clk_clk (sys_clk), // clk.clk
.recon_io_0_io_port_io_out (port_0_out), // recon_io_0_io_port.io_out
.recon_io_0_io_port_io_opdrn (port_0_opdrn), // .io_opdrn
.recon_io_0_io_port_io_in (port_0_in), // .io_in
.recon_io_0_io_port_io_oe (port_0_oe), // .io_oe
.recon_timer_0_clock_tick_second (), // recon_timer_0_clock_tick.second
.recon_timer_0_clock_tick_millisecond (), // .millisecond
.recon_timer_0_clock_tick_microsec (), // .microsec
.reset_reset_n (sys_rstn_db), // reset.reset_n
.uart_0_rxd (uart_0_rxd),
.uart_0_txd (uart_0_txd),
.epcs_0_dclk (epcs_0_dclk), // epcs_0.dclk
.epcs_0_sce (epcs_0_sce), // .sce
.epcs_0_sdo (epcs_0_sdo), // .sdo
.epcs_0_data0 (epcs_0_data0)
);
/* You can Insert your own Debouncer for the Button Here if required */
genvar IO;
generate
for (IO = 0; IO<PORT_0_WIDTH;IO=IO+1)
begin : assign_io
assign port_0_io[IO] = (port_0_oe[IO]==1'b0||(port_0_out[IO]==1'b1&&port_0_opdrn[IO]==1'b1))?1'bz:port_0_out[IO];
assign port_0_in[IO] = port_0_io[IO];
end
endgenerate
endmodule
|
// ======================================================================
// AnalogLedSensor_DN7C3CA006.v generated from TopDesign.cysch
// 02/22/2017 at 19:36
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_FAMILY_FM0P 4
`define CYDEV_CHIP_FAMILY_FM3 5
`define CYDEV_CHIP_FAMILY_FM4 6
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_MEMBER_4G 2
`define CYDEV_CHIP_REVISION_4G_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4G_ES 17
`define CYDEV_CHIP_REVISION_4G_ES2 33
`define CYDEV_CHIP_MEMBER_4U 3
`define CYDEV_CHIP_REVISION_4U_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4E 4
`define CYDEV_CHIP_REVISION_4E_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4O 5
`define CYDEV_CHIP_REVISION_4O_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4N 6
`define CYDEV_CHIP_REVISION_4N_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4Q 7
`define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4D 8
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4J 9
`define CYDEV_CHIP_REVISION_4J_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4K 10
`define CYDEV_CHIP_REVISION_4K_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4H 11
`define CYDEV_CHIP_REVISION_4H_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4A 12
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4F 13
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4P 14
`define CYDEV_CHIP_REVISION_4P_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4M 15
`define CYDEV_CHIP_REVISION_4M_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4L 16
`define CYDEV_CHIP_REVISION_4L_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4I 17
`define CYDEV_CHIP_REVISION_4I_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4C 18
`define CYDEV_CHIP_REVISION_4C_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_5B 19
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_MEMBER_5A 20
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21
`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22
`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23
`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_FM3 24
`define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_FM4 25
`define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 13
`define CYDEV_CHIP_REVISION_USED 0
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// BLE_v2_0(GapConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<CyGapConfiguration xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema">\r\n <DevAddress>00A050000000</DevAddress>\r\n <SiliconGeneratedAddress>true</SiliconGeneratedAddress>\r\n <MtuSize>23</MtuSize>\r\n <TxPowerLevel>0</TxPowerLevel>\r\n <TxPowerLevelConnection>0</TxPowerLevelConnection>\r\n <TxPowerLevelAdvScan>0</TxPowerLevelAdvScan>\r\n <SecurityConfig>\r\n <SecurityMode>SECURITY_MODE_1</SecurityMode>\r\n <SecurityLevel>NO_SECURITY</SecurityLevel>\r\n <IOCapability>DISPLAY</IOCapability>\r\n <PairingMethod>JUST_WORKS</PairingMethod>\r\n <Bonding>BOND</Bonding>\r\n <EncryptionKeySize>16</EncryptionKeySize>\r\n </SecurityConfig>\r\n <AdvertisementConfig>\r\n <AdvScanMode>FAST_CONNECTION</AdvScanMode>\r\n <AdvFastScanInterval>\r\n <Minimum>1000</Minimum>\r\n <Maximum>1000</Maximum>\r\n </AdvFastScanInterval>\r\n <AdvReducedScanInterval>\r\n <Minimum>1000</Minimum>\r\n <Maximum>10240</Maximum>\r\n </AdvReducedScanInterval>\r\n <AdvDiscoveryMode>NON_DISCOVERABLE</AdvDiscoveryMode>\r\n <AdvType>NON_CONNECTABLE</AdvType>\r\n <AdvFilterPolicy>SCAN_REQUEST_ANY_CONNECT_REQUEST_ANY</AdvFilterPolicy>\r\n <AdvChannelMap>ALL</AdvChannelMap>\r\n <AdvFastTimeout>0</AdvFastTimeout>\r\n <AdvReducedTimeout>150</AdvReducedTimeout>\r\n <EnableReducedAdvertising>false</EnableReducedAdvertising>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </AdvertisementConfig>\r\n <ScanConfig>\r\n <ScanFastWindow>30</ScanFastWindow>\r\n <ScanFastInterval>30</ScanFastInterval>\r\n <ScanTimeout>30</ScanTimeout>\r\n <ScanReducedWindow>1125</ScanReducedWindow>\r\n <ScanReducedInterval>1280</ScanReducedInterval>\r\n <ScanReducedTimeout>150</ScanReducedTimeout>\r\n <EnableReducedScan>true</EnableReducedScan>\r\n <ScanDiscoveryMode>GENERAL</ScanDiscoveryMode>\r\n <ScanningState>ACTIVE</ScanningState>\r\n <ScanFilterPolicy>ACCEPT_ALL_ADV_PACKETS</ScanFilterPolicy>\r\n <DuplicateFiltering>false</DuplicateFiltering>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </ScanConfig>\r\n <AdvertisementPacket>\r\n <PacketType>ADVERTISEMENT</PacketType>\r\n <Items>\r\n <CyADStructure>\r\n <ADType>1</ADType>\r\n <ADData>04</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>9</ADType>\r\n <ADData>41:69:72:20:42:65:61:63:6F:6E</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>255</ADType>\r\n <ADData>31:01:00:00:00:00:00:00</ADData>\r\n </CyADStructure>\r\n </Items>\r\n </AdvertisementPacket>\r\n <ScanResponsePacket>\r\n <PacketType>SCAN_RESPONSE</PacketType>\r\n <Items />\r\n </ScanResponsePacket>\r\n</CyGapConfiguration>, HalBaudRate=115200, ImportFilePath=, L2capMpsSize=23, L2capMtuSize=23, L2capNumChannels=1, L2capNumPsm=1, Mode=0, ProfileConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<Profile xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema" ID="1" DisplayName="Custom" Name="Custom" Type="org.bluetooth.profile.custom">\r\n <CyProfileRole ID="2" DisplayName="Server" Name="Server">\r\n <CyService ID="3" DisplayName="Generic Access" Name="Generic Access" Type="org.bluetooth.service.generic_access" UUID="1800">\r\n <CyCharacteristic ID="4" DisplayName="Device Name" Name="Device Name" Type="org.bluetooth.characteristic.gap.device_name" UUID="2A00">\r\n <Field Name="Name">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>10</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>Air Beacon</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="5" DisplayName="Appearance" Name="Appearance" Type="org.bluetooth.characteristic.gap.appearance" UUID="2A01">\r\n <Field Name="Category">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>ENUM</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="7" DisplayName="Generic Attribute" Name="Generic Attribute" Type="org.bluetooth.service.generic_attribute" UUID="1801">\r\n <CyCharacteristic ID="8" DisplayName="Service Changed" Name="Service Changed" Type="org.bluetooth.characteristic.gatt.service_changed" UUID="2A05">\r\n <CyDescriptor ID="9" DisplayName="Client Characteristic Configuration" Name="Client Characteristic Configuration" Type="org.bluetooth.descriptor.gatt.client_characteristic_configuration" UUID="2902">\r\n <Field Name="Properties">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>3</Maximum>\r\n </Range>\r\n <ValueType>BITFIELD</ValueType>\r\n <Bit>\r\n <Index>0</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Notifications disabled" />\r\n <Enumeration key="1" value="Notifications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <Bit>\r\n <Index>1</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Indications disabled" />\r\n <Enumeration key="1" value="Indications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyDescriptor>\r\n <Field Name="Start of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="End of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="INDICATE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="10" DisplayName="Custom Service" Name="Custom Service" Type="org.bluetooth.service.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyCharacteristic ID="11" DisplayName="Custom Characteristic" Name="Custom Characteristic" Type="org.bluetooth.characteristic.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyDescriptor ID="12" DisplayName="Custom Descriptor" Name="Custom Descriptor" Type="org.bluetooth.descriptor.custom" UUID="0000000000001000800000805F9B34FB">\r\n <Field Name="New field">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="false" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyDescriptor>\r\n <Field Name="New field">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="BROADCAST" Present="false" Mandatory="false" />\r\n <Property Type="READ" Present="false" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITE_WITHOUT_RESPONSE" Present="false" Mandatory="false" />\r\n <Property Type="NOTIFY" Present="false" Mandatory="false" />\r\n <Property Type="INDICATE" Present="false" Mandatory="false" />\r\n <Property Type="AUTHENTICATED_SIGNED_WRITES" Present="false" Mandatory="false" />\r\n <Property Type="RELIABLE_WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITABLE_AUXILIARIES" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>NONE</AccessPermission>\r\n </Permission>\r\n </CyCharacteristic>\r\n <Declaration>PrimarySingleInstance</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <ProfileRoleIndex>0</ProfileRoleIndex>\r\n <RoleType>SERVER</RoleType>\r\n </CyProfileRole>\r\n <GapRole>BROADCASTER</GapRole>\r\n</Profile>, SharingMode=0, StackMode=3, UseDeepSleep=true, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMPONENT_NAME=BLE_v2_0, CY_CONST_CONFIG=true, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=BLE_v2_0.pdf, CY_FITTER_NAME=BLE, CY_INSTANCE_SHORT_NAME=BLE, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=0, CY_PDL_DRIVER_NAME=, CY_PDL_DRIVER_REQ_VERSION=, CY_PDL_DRIVER_SUBGROUP=, CY_PDL_DRIVER_VARIANT=, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 4.0, INSTANCE_NAME=BLE, )
module BLE_v2_0_0 (
clk);
output clk;
wire Net_60;
wire Net_53;
wire Net_37;
wire Net_63;
wire Net_15;
wire Net_14;
wire Net_55;
cy_m0s8_ble_v1_0 cy_m0s8_ble (
.interrupt(Net_15),
.rf_ext_pa_en(Net_63));
cy_isr_v1_0
#(.int_type(2'b10))
bless_isr
(.int_signal(Net_15));
cy_clock_v1_0
#(.id("34930e12-af9a-4d94-86a4-9071ff746fb7/5ae6fa4d-f41a-4a35-8821-7ce70389cb0c"),
.source_clock_id("9A908CA6-5BB3-4db0-B098-959E5D90882B"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(0))
LFCLK
(.clock_out(Net_53));
assign clk = Net_55 | Net_53;
assign Net_55 = 1'h0;
endmodule
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: cy_analog_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`endif
// Component: Bus_Connect_v2_10
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_10"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_10\Bus_Connect_v2_10.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_10"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_10\Bus_Connect_v2_10.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// ADC_SAR_SEQ_P4_v2_10(AdcAClock=2, AdcAdjust=1, AdcAlternateResolution=0, AdcAvgMode=1, AdcAvgSamplesNum=3, AdcBClock=2, AdcCClock=2, AdcChannelsEnConf=1, AdcChannelsModeConf=0, AdcClock=1, AdcClockFrequency=1600000, AdcCompareMode=0, AdcDataFormatJustification=0, AdcDClock=2, AdcDedicatedExtVref=true, AdcDifferentialResultFormat=1, AdcHighLimit=2047, AdcInjChannelEnabled=false, AdcInputBufGain=0, AdcLowLimit=0, AdcMaxResolution=12, AdcSampleMode=0, AdcSarMuxChannelConfig=0, AdcSequencedChannels=1, AdcSingleEndedNegativeInput=0, AdcSingleResultFormat=1, AdcSymbolHasSingleEndedInputChannel=false, AdcTotalChannels=1, AdcVrefSelect=1, AdcVrefVoltage_mV=1024, rm_int=false, SeqChannelsConfigTable=<?xml version="1.0" encoding="utf-16"?><CyChannelsConfigTable xmlns:Version="2_10"><m_channelsConfigTable><CyChannelsConfigTableRow><m_enabled>false</m_enabled><m_resolution>Twelve</m_resolution><m_mode>Diff</m_mode><m_averaged>false</m_averaged><m_acqTime>AClocks</m_acqTime><m_limitsDetectIntrEnabled>false</m_limitsDetectIntrEnabled><m_saturationIntrEnabled>false</m_saturationIntrEnabled></CyChannelsConfigTableRow><CyChannelsConfigTableRow><m_enabled>true</m_enabled><m_resolution>Twelve</m_resolution><m_mode>Single</m_mode><m_averaged>false</m_averaged><m_acqTime>AClocks</m_acqTime><m_limitsDetectIntrEnabled>false</m_limitsDetectIntrEnabled><m_saturationIntrEnabled>false</m_saturationIntrEnabled></CyChannelsConfigTableRow></m_channelsConfigTable></CyChannelsConfigTable>, TermMode_aclk=0, TermMode_eoc=0, TermMode_sdone=0, TermMode_soc=0, TermMode_vinMinus0=0, TermMode_vinMinus1=0, TermMode_vinMinus10=0, TermMode_vinMinus11=0, TermMode_vinMinus12=0, TermMode_vinMinus13=0, TermMode_vinMinus14=0, TermMode_vinMinus15=0, TermMode_vinMinus2=0, TermMode_vinMinus3=0, TermMode_vinMinus4=0, TermMode_vinMinus5=0, TermMode_vinMinus6=0, TermMode_vinMinus7=0, TermMode_vinMinus8=0, TermMode_vinMinus9=0, TermMode_vinMinusINJ=0, TermMode_vinNeg=0, TermMode_vinPlus0=0, TermMode_vinPlus1=0, TermMode_vinPlus10=0, TermMode_vinPlus11=0, TermMode_vinPlus12=0, TermMode_vinPlus13=0, TermMode_vinPlus14=0, TermMode_vinPlus15=0, TermMode_vinPlus2=0, TermMode_vinPlus3=0, TermMode_vinPlus4=0, TermMode_vinPlus5=0, TermMode_vinPlus6=0, TermMode_vinPlus7=0, TermMode_vinPlus8=0, TermMode_vinPlus9=0, TermMode_vinPlusINJ=0, TermMode_Vref=0, TermVisibility_aclk=false, TermVisibility_eoc=true, TermVisibility_sdone=true, TermVisibility_soc=false, TermVisibility_vinMinus0=false, TermVisibility_vinMinus1=false, TermVisibility_vinMinus10=false, TermVisibility_vinMinus11=false, TermVisibility_vinMinus12=false, TermVisibility_vinMinus13=false, TermVisibility_vinMinus14=false, TermVisibility_vinMinus15=false, TermVisibility_vinMinus2=false, TermVisibility_vinMinus3=false, TermVisibility_vinMinus4=false, TermVisibility_vinMinus5=false, TermVisibility_vinMinus6=false, TermVisibility_vinMinus7=false, TermVisibility_vinMinus8=false, TermVisibility_vinMinus9=false, TermVisibility_vinMinusINJ=false, TermVisibility_vinNeg=false, TermVisibility_vinPlus0=true, TermVisibility_vinPlus1=false, TermVisibility_vinPlus10=false, TermVisibility_vinPlus11=false, TermVisibility_vinPlus12=false, TermVisibility_vinPlus13=false, TermVisibility_vinPlus14=false, TermVisibility_vinPlus15=false, TermVisibility_vinPlus2=false, TermVisibility_vinPlus3=false, TermVisibility_vinPlus4=false, TermVisibility_vinPlus5=false, TermVisibility_vinPlus6=false, TermVisibility_vinPlus7=false, TermVisibility_vinPlus8=false, TermVisibility_vinPlus9=false, TermVisibility_vinPlusINJ=false, TermVisibility_Vref=false, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMPONENT_NAME=ADC_SAR_SEQ_P4_v2_10, CY_CONST_CONFIG=true, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=ADC, CY_INSTANCE_SHORT_NAME=ADC, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=10, CY_PDL_DRIVER_NAME=, CY_PDL_DRIVER_REQ_VERSION=, CY_PDL_DRIVER_SUBGROUP=, CY_PDL_DRIVER_VARIANT=, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 4.0, INSTANCE_NAME=ADC, )
module ADC_SAR_SEQ_P4_v2_10_1 (
Vref,
sdone,
eoc,
aclk,
vinPlus0,
soc);
inout Vref;
electrical Vref;
output sdone;
output eoc;
input aclk;
inout vinPlus0;
electrical vinPlus0;
input soc;
wire Net_3209;
electrical Net_3164;
wire Net_3128;
wire [11:0] Net_3111;
wire Net_3110;
wire [3:0] Net_3109;
wire Net_3108;
electrical Net_3166;
electrical Net_3167;
electrical Net_3168;
electrical Net_3169;
electrical Net_3170;
electrical Net_3171;
electrical Net_3172;
electrical Net_3173;
electrical Net_3174;
electrical Net_3175;
electrical Net_3176;
electrical Net_3177;
electrical Net_3178;
electrical Net_3179;
electrical Net_3180;
electrical muxout_plus;
electrical Net_3181;
electrical muxout_minus;
electrical Net_3227;
electrical Net_3113;
electrical Net_3225;
electrical [16:0] mux_bus_minus;
electrical [16:0] mux_bus_plus;
electrical Net_3226;
wire Net_3103;
wire Net_3104;
wire Net_3105;
wire Net_3106;
wire Net_3107;
electrical Net_3165;
electrical Net_3182;
electrical Net_3183;
electrical Net_3184;
electrical Net_3185;
electrical Net_3186;
electrical Net_3187;
electrical Net_3188;
electrical Net_3189;
electrical Net_3190;
electrical Net_3191;
electrical Net_3192;
electrical Net_3193;
electrical Net_3194;
electrical Net_3195;
electrical Net_3196;
electrical Net_3197;
electrical Net_3198;
electrical Net_3132;
electrical Net_3133;
electrical Net_3134;
electrical Net_3135;
electrical Net_3136;
electrical Net_3137;
electrical Net_3138;
electrical Net_3139;
electrical Net_3140;
electrical Net_3141;
electrical Net_3142;
electrical Net_3143;
electrical Net_3144;
electrical Net_3145;
electrical Net_3146;
electrical Net_3147;
electrical Net_3148;
electrical Net_3149;
electrical Net_3150;
electrical Net_3151;
electrical Net_3152;
electrical Net_3153;
electrical Net_3154;
electrical Net_3159;
electrical Net_3157;
electrical Net_3158;
electrical Net_3160;
electrical Net_3161;
electrical Net_3162;
electrical Net_3163;
electrical Net_3156;
electrical Net_3155;
wire Net_3120;
electrical Net_3119;
electrical Net_3118;
wire Net_3124;
electrical Net_3122;
electrical Net_3117;
electrical Net_3121;
electrical Net_3123;
wire Net_3112;
wire Net_3126;
wire Net_3125;
electrical Net_2793;
electrical Net_2794;
electrical Net_1851;
electrical Net_2580;
electrical [0:0] Net_2375;
electrical [0:0] Net_1450;
electrical Net_3046;
electrical Net_3016;
wire Net_3235;
electrical Net_2099;
wire Net_17;
wire Net_1845;
electrical Net_2020;
electrical Net_124;
electrical Net_2102;
wire [1:0] Net_3207;
electrical Net_8;
electrical Net_43;
ZeroTerminal ZeroTerminal_8 (
.z(Net_3125));
assign Net_3126 = Net_3125 | Net_1845;
cy_isr_v1_0
#(.int_type(2'b10))
IRQ
(.int_signal(Net_3112));
cy_analog_noconnect_v1_0 cy_analog_noconnect_44 (
.noconnect(Net_3123));
cy_analog_noconnect_v1_0 cy_analog_noconnect_40 (
.noconnect(Net_3121));
cy_analog_noconnect_v1_0 cy_analog_noconnect_39 (
.noconnect(Net_3117));
// cy_analog_virtualmux_43 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_43_connect(Net_124, muxout_minus);
defparam cy_analog_virtualmux_43_connect.sig_width = 1;
// cy_analog_virtualmux_42 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_42_connect(Net_2020, muxout_plus);
defparam cy_analog_virtualmux_42_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_38 (
.noconnect(Net_3118));
cy_analog_noconnect_v1_0 cy_analog_noconnect_41 (
.noconnect(Net_3119));
cy_analog_noconnect_v1_0 cy_analog_noconnect_43 (
.noconnect(Net_3122));
// adc_plus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_plus_in_sel_connect(muxout_plus, mux_bus_plus[0]);
defparam adc_plus_in_sel_connect.sig_width = 1;
Bus_Connect_v2_10 Connect_1 (
.in_bus(mux_bus_plus[16:0]),
.out_bus(Net_1450[0:0]));
defparam Connect_1.in_width = 17;
defparam Connect_1.out_width = 1;
// adc_minus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_minus_in_sel_connect(muxout_minus, mux_bus_minus[0]);
defparam adc_minus_in_sel_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_3 (
.noconnect(Net_1851));
// cy_analog_virtualmux_37 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_37_connect(Net_3016, mux_bus_plus[1]);
defparam cy_analog_virtualmux_37_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_21 (
.noconnect(Net_3147));
cy_analog_noconnect_v1_0 cy_analog_noconnect_20 (
.noconnect(Net_3146));
cy_analog_noconnect_v1_0 cy_analog_noconnect_19 (
.noconnect(Net_3145));
cy_analog_noconnect_v1_0 cy_analog_noconnect_18 (
.noconnect(Net_3144));
cy_analog_noconnect_v1_0 cy_analog_noconnect_17 (
.noconnect(Net_3143));
cy_analog_noconnect_v1_0 cy_analog_noconnect_16 (
.noconnect(Net_3142));
cy_analog_noconnect_v1_0 cy_analog_noconnect_15 (
.noconnect(Net_3141));
cy_analog_noconnect_v1_0 cy_analog_noconnect_14 (
.noconnect(Net_3140));
cy_analog_noconnect_v1_0 cy_analog_noconnect_13 (
.noconnect(Net_3139));
cy_analog_noconnect_v1_0 cy_analog_noconnect_12 (
.noconnect(Net_3138));
cy_analog_noconnect_v1_0 cy_analog_noconnect_11 (
.noconnect(Net_3137));
cy_analog_noconnect_v1_0 cy_analog_noconnect_10 (
.noconnect(Net_3136));
cy_analog_noconnect_v1_0 cy_analog_noconnect_9 (
.noconnect(Net_3135));
cy_analog_noconnect_v1_0 cy_analog_noconnect_8 (
.noconnect(Net_3134));
cy_analog_noconnect_v1_0 cy_analog_noconnect_7 (
.noconnect(Net_3133));
cy_analog_noconnect_v1_0 cy_analog_noconnect_6 (
.noconnect(Net_3132));
// cy_analog_virtualmux_36 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_36_connect(Net_3046, mux_bus_minus[1]);
defparam cy_analog_virtualmux_36_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_37 (
.noconnect(Net_3165));
ZeroTerminal ZeroTerminal_5 (
.z(Net_3107));
ZeroTerminal ZeroTerminal_4 (
.z(Net_3106));
ZeroTerminal ZeroTerminal_3 (
.z(Net_3105));
ZeroTerminal ZeroTerminal_2 (
.z(Net_3104));
ZeroTerminal ZeroTerminal_1 (
.z(Net_3103));
cy_analog_noconnect_v1_0 cy_analog_noconnect_1 (
.noconnect(Net_3113));
// ext_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vref_sel_connect(Net_43, Net_3227);
defparam ext_vref_sel_connect.sig_width = 1;
Bus_Connect_v2_10 Connect_2 (
.in_bus(mux_bus_minus[16:0]),
.out_bus(Net_2375[0:0]));
defparam Connect_2.in_width = 17;
defparam Connect_2.out_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_35 (
.noconnect(Net_3181));
cy_analog_noconnect_v1_0 cy_analog_noconnect_34 (
.noconnect(Net_3180));
cy_analog_noconnect_v1_0 cy_analog_noconnect_33 (
.noconnect(Net_3179));
cy_analog_noconnect_v1_0 cy_analog_noconnect_32 (
.noconnect(Net_3178));
cy_analog_noconnect_v1_0 cy_analog_noconnect_31 (
.noconnect(Net_3177));
cy_analog_noconnect_v1_0 cy_analog_noconnect_30 (
.noconnect(Net_3176));
cy_analog_noconnect_v1_0 cy_analog_noconnect_29 (
.noconnect(Net_3175));
cy_analog_noconnect_v1_0 cy_analog_noconnect_28 (
.noconnect(Net_3174));
cy_analog_noconnect_v1_0 cy_analog_noconnect_27 (
.noconnect(Net_3173));
cy_analog_noconnect_v1_0 cy_analog_noconnect_26 (
.noconnect(Net_3172));
cy_analog_noconnect_v1_0 cy_analog_noconnect_25 (
.noconnect(Net_3171));
cy_analog_noconnect_v1_0 cy_analog_noconnect_24 (
.noconnect(Net_3170));
cy_analog_noconnect_v1_0 cy_analog_noconnect_23 (
.noconnect(Net_3169));
cy_analog_noconnect_v1_0 cy_analog_noconnect_22 (
.noconnect(Net_3168));
cy_analog_noconnect_v1_0 cy_analog_noconnect_4 (
.noconnect(Net_3167));
cy_analog_noconnect_v1_0 cy_analog_noconnect_2 (
.noconnect(Net_3166));
// int_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 int_vref_sel_connect(Net_8, Net_3113);
defparam int_vref_sel_connect.sig_width = 1;
// clk_src_sel (cy_virtualmux_v1_0)
assign Net_17 = Net_1845;
cy_psoc4_sar_v1_0 cy_psoc4_sar (
.vplus(Net_2020),
.vminus(Net_124),
.vref(Net_8),
.ext_vref(Net_43),
.clock(Net_17),
.sw_negvref(Net_3103),
.cfg_st_sel(Net_3207[1:0]),
.cfg_average(Net_3104),
.cfg_resolution(Net_3105),
.cfg_differential(Net_3106),
.trigger(Net_3235),
.data_hilo_sel(Net_3107),
.sample_done(sdone),
.chan_id_valid(Net_3108),
.chan_id(Net_3109[3:0]),
.data_valid(Net_3110),
.eos_intr(eoc),
.data(Net_3111[11:0]),
.irq(Net_3112));
// ext_vneg_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vneg_sel_connect(Net_2580, Net_1851);
defparam ext_vneg_sel_connect.sig_width = 1;
// VMux_soc (cy_virtualmux_v1_0)
assign Net_3235 = soc;
ZeroTerminal ZeroTerminal_6 (
.z(Net_3207[0]));
ZeroTerminal ZeroTerminal_7 (
.z(Net_3207[1]));
// cy_analog_virtualmux_vplus0 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus0_connect(mux_bus_plus[0], vinPlus0);
defparam cy_analog_virtualmux_vplus0_connect.sig_width = 1;
// cy_analog_virtualmux_vplus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus1_connect(mux_bus_plus[1], Net_3132);
defparam cy_analog_virtualmux_vplus1_connect.sig_width = 1;
// cy_analog_virtualmux_vplus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus2_connect(mux_bus_plus[2], Net_3133);
defparam cy_analog_virtualmux_vplus2_connect.sig_width = 1;
// cy_analog_virtualmux_vplus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus3_connect(mux_bus_plus[3], Net_3134);
defparam cy_analog_virtualmux_vplus3_connect.sig_width = 1;
// cy_analog_virtualmux_vplus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus4_connect(mux_bus_plus[4], Net_3135);
defparam cy_analog_virtualmux_vplus4_connect.sig_width = 1;
// cy_analog_virtualmux_vplus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus5_connect(mux_bus_plus[5], Net_3136);
defparam cy_analog_virtualmux_vplus5_connect.sig_width = 1;
// cy_analog_virtualmux_vplus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus6_connect(mux_bus_plus[6], Net_3137);
defparam cy_analog_virtualmux_vplus6_connect.sig_width = 1;
// cy_analog_virtualmux_vplus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus7_connect(mux_bus_plus[7], Net_3138);
defparam cy_analog_virtualmux_vplus7_connect.sig_width = 1;
// cy_analog_virtualmux_vplus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus8_connect(mux_bus_plus[8], Net_3139);
defparam cy_analog_virtualmux_vplus8_connect.sig_width = 1;
// cy_analog_virtualmux_vplus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus9_connect(mux_bus_plus[9], Net_3140);
defparam cy_analog_virtualmux_vplus9_connect.sig_width = 1;
// cy_analog_virtualmux_vplus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus10_connect(mux_bus_plus[10], Net_3141);
defparam cy_analog_virtualmux_vplus10_connect.sig_width = 1;
// cy_analog_virtualmux_vplus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus11_connect(mux_bus_plus[11], Net_3142);
defparam cy_analog_virtualmux_vplus11_connect.sig_width = 1;
// cy_analog_virtualmux_vplus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus12_connect(mux_bus_plus[12], Net_3143);
defparam cy_analog_virtualmux_vplus12_connect.sig_width = 1;
// cy_analog_virtualmux_vplus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus13_connect(mux_bus_plus[13], Net_3144);
defparam cy_analog_virtualmux_vplus13_connect.sig_width = 1;
// cy_analog_virtualmux_vplus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus14_connect(mux_bus_plus[14], Net_3145);
defparam cy_analog_virtualmux_vplus14_connect.sig_width = 1;
// cy_analog_virtualmux_vplus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus15_connect(mux_bus_plus[15], Net_3146);
defparam cy_analog_virtualmux_vplus15_connect.sig_width = 1;
// cy_analog_virtualmux_vplus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus_inj_connect(Net_3016, Net_3147);
defparam cy_analog_virtualmux_vplus_inj_connect.sig_width = 1;
// cy_analog_virtualmux_vminus0 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus0_connect(mux_bus_minus[0], Net_3166);
defparam cy_analog_virtualmux_vminus0_connect.sig_width = 1;
// cy_analog_virtualmux_vminus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus1_connect(mux_bus_minus[1], Net_3167);
defparam cy_analog_virtualmux_vminus1_connect.sig_width = 1;
// cy_analog_virtualmux_vminus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus2_connect(mux_bus_minus[2], Net_3168);
defparam cy_analog_virtualmux_vminus2_connect.sig_width = 1;
// cy_analog_virtualmux_vminus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus3_connect(mux_bus_minus[3], Net_3169);
defparam cy_analog_virtualmux_vminus3_connect.sig_width = 1;
// cy_analog_virtualmux_vminus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus4_connect(mux_bus_minus[4], Net_3170);
defparam cy_analog_virtualmux_vminus4_connect.sig_width = 1;
// cy_analog_virtualmux_vminus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus5_connect(mux_bus_minus[5], Net_3171);
defparam cy_analog_virtualmux_vminus5_connect.sig_width = 1;
// cy_analog_virtualmux_vminus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus6_connect(mux_bus_minus[6], Net_3172);
defparam cy_analog_virtualmux_vminus6_connect.sig_width = 1;
// cy_analog_virtualmux_vminus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus7_connect(mux_bus_minus[7], Net_3173);
defparam cy_analog_virtualmux_vminus7_connect.sig_width = 1;
// cy_analog_virtualmux_vminus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus8_connect(mux_bus_minus[8], Net_3174);
defparam cy_analog_virtualmux_vminus8_connect.sig_width = 1;
// cy_analog_virtualmux_vminus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus9_connect(mux_bus_minus[9], Net_3175);
defparam cy_analog_virtualmux_vminus9_connect.sig_width = 1;
// cy_analog_virtualmux_vminus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus10_connect(mux_bus_minus[10], Net_3176);
defparam cy_analog_virtualmux_vminus10_connect.sig_width = 1;
// cy_analog_virtualmux_vminus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus11_connect(mux_bus_minus[11], Net_3177);
defparam cy_analog_virtualmux_vminus11_connect.sig_width = 1;
// cy_analog_virtualmux_vminus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus12_connect(mux_bus_minus[12], Net_3178);
defparam cy_analog_virtualmux_vminus12_connect.sig_width = 1;
// cy_analog_virtualmux_vminus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus13_connect(mux_bus_minus[13], Net_3179);
defparam cy_analog_virtualmux_vminus13_connect.sig_width = 1;
// cy_analog_virtualmux_vminus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus14_connect(mux_bus_minus[14], Net_3180);
defparam cy_analog_virtualmux_vminus14_connect.sig_width = 1;
// cy_analog_virtualmux_vminus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus15_connect(mux_bus_minus[15], Net_3181);
defparam cy_analog_virtualmux_vminus15_connect.sig_width = 1;
// cy_analog_virtualmux_vminus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus_inj_connect(Net_3046, Net_3165);
defparam cy_analog_virtualmux_vminus_inj_connect.sig_width = 1;
cy_clock_v1_0
#(.id("fc8927d7-c4e2-4edd-a602-d03ad2da52e9/5c71752a-e182-47ca-942c-9cb20adbdf2f"),
.source_clock_id(""),
.divisor(0),
.period("625000000"),
.is_direct(0),
.is_digital(0))
intClock
(.clock_out(Net_1845));
cy_analog_noconnect_v1_0 cy_analog_noconnect_5 (
.noconnect(Net_3227));
endmodule
// top
module top ;
wire Net_2666;
wire Net_2665;
wire Net_2664;
wire Net_2663;
electrical Net_2662;
wire Net_2551;
electrical Net_2493;
electrical Net_3222;
electrical Net_3338;
electrical Net_3701;
electrical Net_3702;
cy_annotation_universal_v1_0 GND_1 (
.connect({
Net_2493
})
);
defparam GND_1.comp_name = "Gnd_v1_0";
defparam GND_1.port_names = "T1";
defparam GND_1.width = 1;
BLE_v2_0_0 BLE (
.clk(Net_2551));
wire [0:0] tmpOE__Adc_IN_net;
wire [0:0] tmpFB_0__Adc_IN_net;
wire [0:0] tmpIO_0__Adc_IN_net;
wire [0:0] tmpINTERRUPT_0__Adc_IN_net;
electrical [0:0] tmpSIOVREF__Adc_IN_net;
cy_psoc3_pins_v1_10
#(.id("77715107-f8d5-47e5-a629-0fb83101ac6b"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Adc_IN
(.oe(tmpOE__Adc_IN_net),
.y({1'b0}),
.fb({tmpFB_0__Adc_IN_net[0:0]}),
.analog({Net_3222}),
.io({tmpIO_0__Adc_IN_net[0:0]}),
.siovref(tmpSIOVREF__Adc_IN_net),
.interrupt({tmpINTERRUPT_0__Adc_IN_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Adc_IN_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Sensor_Power_net;
wire [0:0] tmpFB_0__Sensor_Power_net;
wire [0:0] tmpIO_0__Sensor_Power_net;
wire [0:0] tmpINTERRUPT_0__Sensor_Power_net;
electrical [0:0] tmpSIOVREF__Sensor_Power_net;
cy_psoc3_pins_v1_10
#(.id("df0a1340-6685-423f-80b5-67d3a4260d3d"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b1),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Sensor_Power
(.oe(tmpOE__Sensor_Power_net),
.y({1'b0}),
.fb({tmpFB_0__Sensor_Power_net[0:0]}),
.io({tmpIO_0__Sensor_Power_net[0:0]}),
.siovref(tmpSIOVREF__Sensor_Power_net),
.interrupt({tmpINTERRUPT_0__Sensor_Power_net[0:0]}),
.annotation({Net_3338}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Sensor_Power_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ADC_SAR_SEQ_P4_v2_10_1 ADC (
.Vref(Net_2662),
.sdone(Net_2663),
.eoc(Net_2664),
.aclk(1'b0),
.vinPlus0(Net_3222),
.soc(1'b0));
cy_annotation_universal_v1_0 L_1 (
.connect({
Net_2493,
Net_3701
})
);
defparam L_1.comp_name = "Inductor_v1_0";
defparam L_1.port_names = "T1, T2";
defparam L_1.width = 2;
cy_annotation_universal_v1_0 C_1 (
.connect({
Net_3701,
Net_3702
})
);
defparam C_1.comp_name = "Capacitor_v1_0";
defparam C_1.port_names = "T1, T2";
defparam C_1.width = 2;
wire [0:0] tmpOE__STATUS_net;
wire [0:0] tmpFB_0__STATUS_net;
wire [0:0] tmpIO_0__STATUS_net;
wire [0:0] tmpINTERRUPT_0__STATUS_net;
electrical [0:0] tmpSIOVREF__STATUS_net;
cy_psoc3_pins_v1_10
#(.id("e851a3b9-efb8-48be-bbb8-b303b216c393"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
STATUS
(.oe(tmpOE__STATUS_net),
.y({1'b0}),
.fb({tmpFB_0__STATUS_net[0:0]}),
.io({tmpIO_0__STATUS_net[0:0]}),
.siovref(tmpSIOVREF__STATUS_net),
.interrupt({tmpINTERRUPT_0__STATUS_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__STATUS_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : bs_dump.v
// Author : fanyibo
// Created : 2014-07-11
// Description : dump bit stream
//
// $Id$
//-------------------------------------------------------------------
`ifdef DUMP_BS
integer f_bs;
integer bs_num;
initial begin
bs_num = 0;
f_bs = $fopen("./dump/bs.dat","wb");
end
always @(frame_num)
$fdisplay(f_bs, "\nFrame Number =%3d", frame_num);
always @(posedge clk) begin
if (dut.u_top.winc_o) begin
bs_num = bs_num + 1;
$fwrite(f_bs, "%h ", dut.u_top.wdata_o);
if (!(bs_num%16)) $fdisplay(f_bs, ";");
// if (u_top.frame_done) begin
// $fwrite(f_bs, "\n");
// bs_num = 0;
// end
end
end
`endif |
`timescale 1 ns / 1 ps
`include "Volume_Pregain_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module Volume_Pregain_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
/*
*******************************************************************************
* File Name : ada_core.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 19th, 2014
* Author : Angel Terrones <[email protected]>
*
* Disclaimer : Copyright 2014 Angel Terrones
* Release under the MIT License.
*
* Description : The top-level ADA processor.
*******************************************************************************
*/
`include "ada_defines.v"
module ada_core(
input clk,
input rst,
// external interrupts
input [31:0] io_interrupt, //
// I/O port
input [31:0] io_data_i, // data from device
input io_ready, // device is ready
output [31:0] io_address, // device address
output [31:0] io_data_o, // data to device
output io_we, // write to device
output io_enable, // enable operation
// External Instruction Memory/Instruction Cache
input [31:0] eimem_cache_data_i, // Data from memory
input eimem_cache_ready, // memory is ready
output [31:0] eimem_cache_address, // data address
output eimem_cache_wr, // write = 1, read = 0,
output eimem_cache_enable, // enable operation
// External Data Memory/Data Cache
input [31:0] edmem_cache_data_i, // Data from memory
input edmem_cache_ready, // memory is ready
output [31:0] edmem_cache_address, // data address
output [31:0] edmem_cache_data_o, // data to memory
output edmem_cache_wr, // write = 1, read = 0,
output edmem_cache_enable, // enable operation
// Instruction & Data cache
output icache_flush,
output dcache_flush
);
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire [31:0] if_pc_add4;
wire [31:0] ia_pc;
wire [31:0] if_pc;
wire [31:0] id_instruction;
wire [31:0] id_pc_current;
wire [31:0] id_pc_add4;
wire [4:0] id_exu_operation;
wire [31:0] id_exu_port_a;
wire [31:0] id_exu_port_b;
wire [31:0] id_mem_store_data;
wire id_mem_write;
wire id_mem_read;
wire id_mem_byte;
wire id_mem_halfword;
wire id_mem_sign_ext;
wire id_mem_exu_mem_select;
wire [4:0] id_gpr_wa;
wire id_gpr_we;
wire [4:0] ex_exu_operation;
wire [31:0] ex_exu_port_a;
wire [31:0] ex_exu_port_b;
wire [31:0] ex_mem_store_data;
wire ex_mem_write;
wire ex_mem_read;
wire ex_mem_byte;
wire ex_mem_halfword;
wire ex_mem_sign_ext;
wire ex_mem_exu_mem_select;
wire [4:0] ex_gpr_wa;
wire ex_gpr_we;
wire ex_kernel_mode;
wire [31:0] ex_pc_current;
wire ex_mem_can_exception;
wire [31:0] ex_exu_result;
wire [31:0] mem_exu_result;
wire mem_mem_exu_mem_select;
wire [4:0] mem_gpr_wa;
wire [31:0] mem_gpr_wd;
wire mem_gpr_we;
wire [4:0] wb_gpr_wa;
wire [31:0] wb_gpr_wd;
wire wb_gpr_we;
wire [4:0] id_gpr_port_a;
wire [4:0] id_gpr_port_b;
wire [1:0] forward_port_a_select;
wire [1:0] forward_port_b_select;
wire if_stall;
wire id_stall;
wire ex_stall;
wire mem_stall;
wire wb_stall;
wire [4:0] sr_ra;
wire [4:0] sr_wa;
wire [31:0] sr_wd;
wire sr_we;
wire id_is_flushed;
wire exc_op_reset;
wire exc_op_shutdown;
wire exc_op_syscall;
wire exc_op_break;
wire exc_op_invalid;
wire exc_op_rfe;
wire exc_op_rfb;
wire exc_bad_branch_addr;
wire exc_div_zero;
wire [31:0] mem_pc_current;
wire id_id_can_exception;
wire id_ex_can_exception;
wire id_mem_can_exception;
wire ex_ex_can_exception;
wire [31:0] sr_data_input;
wire id_kernel_mode;
wire if_flush;
wire id_flush;
wire ex_flush;
wire mem_flush;
wire if_exception_stall;
wire id_exception_stall;
wire ex_exception_stall;
wire mem_exception_stall;
wire exception_pc_selector;
wire [31:0] exception_pc;
//------------------------------------------------
// watch from here
wire [31:0] if_instruction;
wire [31:0] dmem_data_o;
wire if_mem_request_stall;
wire mem_request_stall;
wire exc_bad_if_address;
wire exc_bad_mem_address;
wire haz_take_branch;
wire [31:0] pc_branch_address;
wire haz_ex_stall;
wire [31:0] mem_mem_store_data;
wire mem_mem_write;
wire mem_mem_read;
wire mem_mem_byte;
wire mem_mem_halfword;
wire mem_mem_sign_ext;
wire mem_kernel_mode;
wire mem_mem_can_exception;
wire [31:0] iimem_address;
wire [31:0] iimem_data_i;
wire iimem_we;
wire [31:0] dimem_data_i;
wire [31:0] dimem_address;
wire [31:0] dimem_data_o;
wire dimem_we;
//--------------------------------------------------------------------------
// Instantiate
//--------------------------------------------------------------------------
ada_mux_4_1 pc_source(
.select({exception_pc_selector, haz_take_branch}),
.in0(if_pc_add4),
.in1(pc_branch_address),
.in2(exception_pc),
.in3(exception_pc),
.out(ia_pc)
);
//------------------------------------------------------------------------------------------------------------------
ada_iaif_stage iaif_register(
.clk(clk),
.rst(rst),
.pc_in(ia_pc),
.if_stall(if_stall),
.pc_out(if_pc)
);
//------------------------------------------------------------------------------------------------------------------
ada_add pc_add4(
.A(if_pc),
.B(32'h0000_0004),
.C(if_pc_add4)
);
//------------------------------------------------------------------------------------------------------------------
ada_ifid_stage ifid_register(
.clk(clk),
.rst(rst),
.if_instruction(if_instruction),
.if_pc_current(if_pc),
.if_pc_add4(if_pc_add4),
.if_stall(if_stall),
.if_flush(if_flush),
.id_stall(id_stall),
.if_is_ds(haz_take_branch),
.id_instruction(id_instruction), //
.id_pc_current(id_pc_current),
.id_pc_add4(id_pc_add4),
.id_is_flushed(id_is_flushed)
);
//------------------------------------------------------------------------------------------------------------------
ada_id_stage id_stage(
.clk(clk),
.instruction(id_instruction),
.pc_current(id_pc_current),
.pc_next(id_pc_add4),
.forward_port_a_select(forward_port_a_select),
.forward_port_b_select(forward_port_b_select),
.exu_fwd_data(ex_exu_result),
.mem_fwd_data(mem_gpr_wd),
.wb_fwd_data(wb_gpr_wd),
.wb_gpr_wa(wb_gpr_wa),
.wb_gpr_wd(wb_gpr_wd),
.wb_gpr_we(wb_gpr_we),
.sr_data_input(sr_data_input),
.sr_sm(id_kernel_mode),
.haz_take_branch(haz_take_branch), //
.exc_op_reset(exc_op_reset),
.exc_op_shutdown(exc_op_shutdown),
.exc_op_syscall(exc_op_syscall),
.exc_op_break(exc_op_break),
.exc_op_invalid(exc_op_invalid),
.exc_op_rfe(exc_op_rfe),
.exc_op_rfb(exc_op_rfb),
.exc_bad_branch_addr(exc_bad_branch_addr),
.pc_branch_address(pc_branch_address),
.id_gpr_port_a(id_gpr_port_a),
.id_gpr_port_b(id_gpr_port_b),
.exu_operation(id_exu_operation),
.exu_port_a(id_exu_port_a),
.exu_port_b(id_exu_port_b),
.mem_store_data(id_mem_store_data),
.exu_gpr_wa(id_gpr_wa),
.exu_gpr_we(id_gpr_we),
.sr_ra(sr_ra),
.sr_wa(sr_wa),
.sr_wd(sr_wd),
.sr_we(sr_we),
.mem_write(id_mem_write),
.mem_read(id_mem_read),
.mem_byte(id_mem_byte),
.mem_halfword(id_mem_halfword),
.mem_sign_ext(id_mem_sign_ext),
.mem_exu_mem_select(id_mem_exu_mem_select),
.id_can_exception(id_id_can_exception),
.ex_can_exception(id_ex_can_exception),
.mem_can_exception(id_mem_can_exception)
);
//------------------------------------------------------------------------------------------------------------------
ada_idex_stage idex_register(
.clk(clk),
.rst(rst),
.id_exu_operation(id_exu_operation),
.id_exu_port_a(id_exu_port_a),
.id_exu_port_b(id_exu_port_b),
.id_mem_store_data(id_mem_store_data),
.id_mem_write(id_mem_write),
.id_mem_read(id_mem_read),
.id_mem_byte(id_mem_byte),
.id_mem_halfword(id_mem_halfword),
.id_mem_sign_ext(id_mem_sign_ext),
.id_mem_exu_mem_select(id_mem_exu_mem_select),
.id_gpr_wa(id_gpr_wa),
.id_gpr_we(id_gpr_we),
.id_kernel_mode(id_kernel_mode),
.id_pc_current(id_pc_current),
.id_ex_can_exc(id_ex_can_exception),
.id_mem_can_exc(id_mem_can_exception),
.id_flush(id_flush),
.id_stall(id_stall),
.ex_stall(ex_stall),
.ex_exu_operation(ex_exu_operation), //
.ex_exu_port_a(ex_exu_port_a),
.ex_exu_port_b(ex_exu_port_b),
.ex_mem_store_data(ex_mem_store_data),
.ex_mem_write(ex_mem_write),
.ex_mem_read(ex_mem_read),
.ex_mem_byte(ex_mem_byte),
.ex_mem_halfword(ex_mem_halfword),
.ex_mem_sign_ext(ex_mem_sign_ext),
.ex_mem_exu_mem_select(ex_mem_exu_mem_select),
.ex_gpr_wa(ex_gpr_wa),
.ex_gpr_we(ex_gpr_we),
.ex_kernel_mode(ex_kernel_mode),
.ex_pc_current(ex_pc_current),
.ex_ex_can_exc(ex_ex_can_exception),
.ex_mem_can_exc(ex_mem_can_exception)
);
//------------------------------------------------------------------------------------------------------------------
ada_exu ex_unit(
.clk(clk),
.rst(rst),
.port_a(ex_exu_port_a),
.port_b(ex_exu_port_b),
.operation(ex_exu_operation),
.ex_stall(ex_stall),
.ex_flush(ex_flush),
.result(ex_exu_result), //
.exc_div_zero(exc_div_zero),
.haz_ex_stall(haz_ex_stall)
);
//------------------------------------------------------------------------------------------------------------------
ada_exmem_stage exmem_register(
.clk(clk),
.rst(rst),
.ex_exu_result(ex_exu_result),
.ex_mem_store_data(ex_mem_store_data),
.ex_mem_write(ex_mem_write),
.ex_mem_read(ex_mem_read),
.ex_mem_byte(ex_mem_byte),
.ex_mem_halfword(ex_mem_halfword),
.ex_mem_sign_ext(ex_mem_sign_ext),
.ex_mem_exu_mem_select(ex_mem_exu_mem_select),
.ex_gpr_wa(ex_gpr_wa),
.ex_gpr_we(ex_gpr_we),
.ex_kernel_mode(ex_kernel_mode),
.ex_pc_current(ex_pc_current),
.ex_mem_can_exc(ex_mem_can_exception),
.ex_flush(ex_flush),
.ex_stall(ex_stall),
.mem_stall(mem_stall),
.mem_exu_result(mem_exu_result), //
.mem_mem_store_data(mem_mem_store_data),
.mem_mem_write(mem_mem_write),
.mem_mem_read(mem_mem_read),
.mem_mem_byte(mem_mem_byte),
.mem_mem_halfword(mem_mem_halfword),
.mem_mem_sign_ext(mem_mem_sign_ext),
.mem_mem_exu_mem_select(mem_mem_exu_mem_select),
.mem_gpr_wa(mem_gpr_wa),
.mem_gpr_we(mem_gpr_we),
.mem_kernel_mode(mem_kernel_mode),
.mem_pc_current(mem_pc_current),
.mem_mem_can_exc(mem_mem_can_exception)
);
//------------------------------------------------------------------------------------------------------------------
ada_mux_2_1 mux_2_1(
.select(mem_mem_exu_mem_select),
.in0(mem_exu_result),
.in1(dmem_data_o),
.out(mem_gpr_wd) //
);
//------------------------------------------------------------------------------------------------------------------
ada_memwb_stage memwb_register(
.clk(clk),
.rst(rst),
.mem_gpr_wd(mem_gpr_wd),
.mem_gpr_wa(mem_gpr_wa),
.mem_gpr_we(mem_gpr_we),
.mem_flush(mem_flush),
.mem_stall(mem_stall),
.wb_stall(wb_stall),
.wb_gpr_wd(wb_gpr_wd), //
.wb_gpr_wa(wb_gpr_wa),
.wb_gpr_we(wb_gpr_we)
);
//------------------------------------------------------------------------------------------------------------------
ada_hazard hazard_unit(
.id_gpr_port_a(id_gpr_port_a),
.id_gpr_port_b(id_gpr_port_b),
.ex_gpr_wa(ex_gpr_wa),
.mem_gpr_wa(mem_gpr_wa),
.wb_gpr_wa(wb_gpr_wa),
.ex_gpr_we(ex_gpr_we),
.mem_gpr_we(mem_gpr_we),
.wb_gpr_we(wb_gpr_we),
.if_mem_request_stall(if_mem_request_stall),
.ex_data_read(ex_mem_read),
.mem_request_stall(mem_request_stall),
.if_exception_stall(if_exception_stall),
.id_exception_stall(id_exception_stall),
.ex_exception_stall(ex_exception_stall),
.mem_exception_stall(mem_exception_stall),
.ex_exu_stall(haz_ex_stall),
.forward_port_a_select(forward_port_a_select), //
.forward_port_b_select(forward_port_b_select),
.if_stall(if_stall),
.id_stall(id_stall),
.ex_stall(ex_stall),
.mem_stall(mem_stall),
.wb_stall(wb_stall)
);
//------------------------------------------------------------------------------------------------------------------
ada_exception exception_unit(
.clk(clk),
.rst(rst),
.reg_ra(sr_ra),
.reg_wa(sr_wa),
.reg_data_i(sr_wd),
.reg_we(sr_we),
.id_stall(id_stall),
.id_is_flushed(id_is_flushed),
.exc_if_invalid_address(exc_bad_if_address),
.exc_op_reset(exc_op_reset),
.exc_op_shutdown(exc_op_shutdown),
.exc_op_syscall(exc_op_syscall),
.exc_op_break(exc_op_break),
.exc_op_invalid(exc_op_invalid),
.exc_branch_invalid_address(exc_bad_branch_addr),
.exc_div_zero(exc_div_zero),
.exc_mem_invalid_address(exc_bad_mem_address),
.op_rfe(exc_op_rfe),
.op_rfb(exc_op_rfb),
.io_interrupt(io_interrupt),
.if_bad_address(if_pc),
.id_exc_pc(id_pc_current),
.ex_exc_pc(ex_pc_current),
.mem_exc_pc(mem_pc_current),
.mem_bad_address(mem_exu_result),
.id_can_exc(id_id_can_exception | id_ex_can_exception | id_mem_can_exception),
.ex_can_exc(ex_ex_can_exception | ex_mem_can_exception),
.mem_can_exc(mem_mem_can_exception),
.reg_data_o(sr_data_input), ////////////////////////////
.kernel_mode(id_kernel_mode),
.if_exc_flush(if_flush),
.id_exc_flush(id_flush),
.ex_exc_flush(ex_flush),
.mem_exc_flush(mem_flush),
.if_exception_stall(if_exception_stall),
.id_exception_stall(id_exception_stall),
.ex_exception_stall(ex_exception_stall),
.mem_exception_stall(mem_exception_stall),
.exception_pc_selector(exception_pc_selector),
.exception_pc(exception_pc),
.icache_flush(dcache_flush),
.dcache_flush(icache_flush)
);
//------------------------------------------------------------------------------------------------------------------
ada_bram internal_memory(
// instruction
.a_clk(clk),
.a_wr(iimem_we),
.a_addr(iimem_address[7:0]),
.a_din(32'hFFFF_FFFF),
.a_dout(iimem_data_i),
// data
.b_clk(clk),
.b_wr(dimem_we),
.b_addr(dimem_address[7:0]),
.b_din(dimem_data_o),
.b_dout(dimem_data_i)
);
//------------------------------------------------------------------------------------------------------------------
ada_mem_decoder mem_decoder(
.clk(clk),
.rst(rst),
// IF interface
.imem_address(if_pc), // Instruction address
.imem_data(if_instruction), // Instruction data
// MEM interface
.dmem_address(mem_exu_result), // Data address
.dmem_data_i(mem_mem_store_data), // Data to memory
.data_word(~(mem_mem_halfword | mem_mem_byte)), // word access
.data_halfword(mem_mem_halfword), // halfword access
.data_byte(mem_mem_byte), // byte access
.dmem_read(mem_mem_read), // read data memory
.dmem_write(mem_mem_write), // write data memory
.data_sign_extend(mem_mem_sign_ext), // read data (byte/half) with sign extended
.dmem_data_o(dmem_data_o), // data from memory
// I/O
.io_data_i(io_data_i), // data from device
.io_ready(io_ready), // device is ready
.io_address(io_address), // device address
.io_data_o(io_data_o), // data to device
.io_we(io_we), // write to device
.io_enable(io_enable), // enable operation
// Internal IM
.iimem_data_i(iimem_data_i), // data from memory
.iimem_address(iimem_address), // instruction address
.iimem_we(iimem_we), // write enable
// Internal DM
.dimem_data_i(dimem_data_i), // data from memory
.dimem_address(dimem_address), // instruction address
.dimem_data_o(dimem_data_o), // data to memory
.dimem_we(dimem_we), // write enable
// External Instruction Memory/Instruction Cache
.eimem_cache_data_i(eimem_cache_data_i), // Data from memory
.eimem_cache_ready(eimem_cache_ready), // memory is ready
.eimem_cache_address(eimem_cache_address), // data address
.eimem_cache_wr(eimem_cache_wr), // write = 1, read = 0,
.eimem_cache_enable(eimem_cache_enable), // enable operation
// External Data Memory/Data Cache
.edmem_cache_data_i(edmem_cache_data_i), // Data from memory
.edmem_cache_ready(edmem_cache_ready), // memory is ready
.edmem_cache_address(edmem_cache_address), // data address
.edmem_cache_data_o(edmem_cache_data_o), // data to memory
.edmem_cache_wr(edmem_cache_wr), // write = 1, read = 0,
.edmem_cache_enable(edmem_cache_enable), // enable operation
// pipeline
.if_kernel_mode(id_kernel_mode), // privilege access in IF stage
.mem_kernel_mode(mem_kernel_mode), // privilege access in MEM stage
.if_stall(if_stall), // Stop transactions if IF is stalled
.if_flush(if_flush), // abort IF
.exc_bad_if_address(exc_bad_if_address), // panic
.exc_bad_mem_address(exc_bad_mem_address), // panic
.if_stall_md(if_mem_request_stall), // long operation
.mem_stall_md(mem_request_stall) // long operation
);
//------------------------------------------------------------------------------------------------------------------
endmodule
|
// soc_system_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2015.01.07.15:08:30
`timescale 1 ps / 1 ps
module soc_system_hps_0 #(
parameter F2S_Width = 3,
parameter S2F_Width = 2
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire f2h_cold_rst_req_n, // f2h_cold_reset_req.reset_n
input wire f2h_dbg_rst_req_n, // f2h_debug_reset_req.reset_n
input wire f2h_warm_rst_req_n, // f2h_warm_reset_req.reset_n
input wire [27:0] f2h_stm_hwevents, // f2h_stm_hw_events.stm_hwevents
input wire f2h_axi_clk, // f2h_axi_clock.clk
input wire [7:0] f2h_AWID, // f2h_axi_slave.awid
input wire [31:0] f2h_AWADDR, // .awaddr
input wire [3:0] f2h_AWLEN, // .awlen
input wire [2:0] f2h_AWSIZE, // .awsize
input wire [1:0] f2h_AWBURST, // .awburst
input wire [1:0] f2h_AWLOCK, // .awlock
input wire [3:0] f2h_AWCACHE, // .awcache
input wire [2:0] f2h_AWPROT, // .awprot
input wire f2h_AWVALID, // .awvalid
output wire f2h_AWREADY, // .awready
input wire [4:0] f2h_AWUSER, // .awuser
input wire [7:0] f2h_WID, // .wid
input wire [127:0] f2h_WDATA, // .wdata
input wire [15:0] f2h_WSTRB, // .wstrb
input wire f2h_WLAST, // .wlast
input wire f2h_WVALID, // .wvalid
output wire f2h_WREADY, // .wready
output wire [7:0] f2h_BID, // .bid
output wire [1:0] f2h_BRESP, // .bresp
output wire f2h_BVALID, // .bvalid
input wire f2h_BREADY, // .bready
input wire [7:0] f2h_ARID, // .arid
input wire [31:0] f2h_ARADDR, // .araddr
input wire [3:0] f2h_ARLEN, // .arlen
input wire [2:0] f2h_ARSIZE, // .arsize
input wire [1:0] f2h_ARBURST, // .arburst
input wire [1:0] f2h_ARLOCK, // .arlock
input wire [3:0] f2h_ARCACHE, // .arcache
input wire [2:0] f2h_ARPROT, // .arprot
input wire f2h_ARVALID, // .arvalid
output wire f2h_ARREADY, // .arready
input wire [4:0] f2h_ARUSER, // .aruser
output wire [7:0] f2h_RID, // .rid
output wire [127:0] f2h_RDATA, // .rdata
output wire [1:0] f2h_RRESP, // .rresp
output wire f2h_RLAST, // .rlast
output wire f2h_RVALID, // .rvalid
input wire f2h_RREADY, // .rready
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [63:0] h2f_WDATA, // .wdata
output wire [7:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [63:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
input wire [31:0] f2h_irq_p0, // f2h_irq0.irq
input wire [31:0] f2h_irq_p1, // f2h_irq1.irq
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 3)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
soc_system_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.f2h_cold_rst_req_n (f2h_cold_rst_req_n), // f2h_cold_reset_req.reset_n
.f2h_dbg_rst_req_n (f2h_dbg_rst_req_n), // f2h_debug_reset_req.reset_n
.f2h_warm_rst_req_n (f2h_warm_rst_req_n), // f2h_warm_reset_req.reset_n
.f2h_stm_hwevents (f2h_stm_hwevents), // f2h_stm_hw_events.stm_hwevents
.f2h_axi_clk (f2h_axi_clk), // f2h_axi_clock.clk
.f2h_AWID (f2h_AWID), // f2h_axi_slave.awid
.f2h_AWADDR (f2h_AWADDR), // .awaddr
.f2h_AWLEN (f2h_AWLEN), // .awlen
.f2h_AWSIZE (f2h_AWSIZE), // .awsize
.f2h_AWBURST (f2h_AWBURST), // .awburst
.f2h_AWLOCK (f2h_AWLOCK), // .awlock
.f2h_AWCACHE (f2h_AWCACHE), // .awcache
.f2h_AWPROT (f2h_AWPROT), // .awprot
.f2h_AWVALID (f2h_AWVALID), // .awvalid
.f2h_AWREADY (f2h_AWREADY), // .awready
.f2h_AWUSER (f2h_AWUSER), // .awuser
.f2h_WID (f2h_WID), // .wid
.f2h_WDATA (f2h_WDATA), // .wdata
.f2h_WSTRB (f2h_WSTRB), // .wstrb
.f2h_WLAST (f2h_WLAST), // .wlast
.f2h_WVALID (f2h_WVALID), // .wvalid
.f2h_WREADY (f2h_WREADY), // .wready
.f2h_BID (f2h_BID), // .bid
.f2h_BRESP (f2h_BRESP), // .bresp
.f2h_BVALID (f2h_BVALID), // .bvalid
.f2h_BREADY (f2h_BREADY), // .bready
.f2h_ARID (f2h_ARID), // .arid
.f2h_ARADDR (f2h_ARADDR), // .araddr
.f2h_ARLEN (f2h_ARLEN), // .arlen
.f2h_ARSIZE (f2h_ARSIZE), // .arsize
.f2h_ARBURST (f2h_ARBURST), // .arburst
.f2h_ARLOCK (f2h_ARLOCK), // .arlock
.f2h_ARCACHE (f2h_ARCACHE), // .arcache
.f2h_ARPROT (f2h_ARPROT), // .arprot
.f2h_ARVALID (f2h_ARVALID), // .arvalid
.f2h_ARREADY (f2h_ARREADY), // .arready
.f2h_ARUSER (f2h_ARUSER), // .aruser
.f2h_RID (f2h_RID), // .rid
.f2h_RDATA (f2h_RDATA), // .rdata
.f2h_RRESP (f2h_RRESP), // .rresp
.f2h_RLAST (f2h_RLAST), // .rlast
.f2h_RVALID (f2h_RVALID), // .rvalid
.f2h_RREADY (f2h_RREADY), // .rready
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY), // .rready
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY), // .rready
.f2h_irq_p0 (f2h_irq_p0), // f2h_irq0.irq
.f2h_irq_p1 (f2h_irq_p1) // f2h_irq1.irq
);
soc_system_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SRDLRTP_PP_BLACKBOX_V
/**
* srdlrtp: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlrtp (
Q ,
RESET_B,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLRTP_PP_BLACKBOX_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file counter_fifo.v when simulating
// the core, counter_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module counter_fifo(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input rst;
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(510),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_0_V
`define SKY130_FD_SC_LP__BUFLP_0_V
/**
* buflp: Buffer, Low Power.
*
* Verilog wrapper for buflp with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buflp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buflp_0 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buflp_0 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_0_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_data_fifo:2.1
// IP Revision: 6
(* X_CORE_INFO = "axi_data_fifo_v2_1_6_axi_data_fifo,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_m00_data_fifo_0,axi_data_fifo_v2_1_6_axi_data_fifo,{}" *)
(* CORE_GENERATION_INFO = "zc702_m00_data_fifo_0,axi_data_fifo_v2_1_6_axi_data_fifo,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_data_fifo,x_ipVersion=2.1,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_WRITE_FIFO_DEPTH=512,C_AXI_WRITE_FIFO_TYPE=bram,C_AXI_WRITE_FIFO_DELAY=1,C_AXI_READ_FIFO_DEPTH=512,C_AXI_READ_FIFO_TYPE=bram,C_AXI_READ_FIFO_DELAY=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_m00_data_fifo_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_data_fifo_v2_1_6_axi_data_fifo #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_WRITE_FIFO_DEPTH(512),
.C_AXI_WRITE_FIFO_TYPE("bram"),
.C_AXI_WRITE_FIFO_DELAY(1),
.C_AXI_READ_FIFO_DEPTH(512),
.C_AXI_READ_FIFO_TYPE("bram"),
.C_AXI_READ_FIFO_DELAY(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Engineer: Christian P. Feist
//
// Create Date: 16:33:45 05/05/2016
// Design Name: trivium_top
// Module Name: /home/chris/Documents/FPGA/Work/Trivium/hdl/tb/trivium_top_tb.v
// Project Name: Trivium
// Target Device: Spartan-6, Zynq
// Tool versions: ISE 14.7, Vivado v2016.2
// Description: The module trivium_top is tested using reference I/O files. Each
// test incorporates the pre-loading with a new key and IV, as well
// as providing input words and checking the correctness of the
// encrypted output words.
//
// Verilog Test Fixture created by ISE for module: trivium_top
//
// Dependencies: /
//
// Revision:
// Revision 0.01 - File Created
// Revision 0.02 - Modifications to accomodate new core interface
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module trivium_top_tb;
////////////////////////////////////////////////////////////////////////////////
// Helper function definitions
////////////////////////////////////////////////////////////////////////////////
/* Get the number of tests contained in a specified file */
function [31:0] get_num_tests;
input [8*20:1] i_file_name;
reg [8*20:1] cur_line;
integer cur_num;
integer fd;
integer scan_ret;
begin
cur_num = 0;
fd = $fopen(i_file_name, "r");
if (!fd) begin
$display("ERROR: Could not open '%s'", i_file_name);
get_num_tests = 0;
end
else begin
/* Iterate over lines */
scan_ret = $fscanf(fd, "%s", cur_line);
while (scan_ret) begin
if (cur_line == "-")
cur_num = cur_num + 1;
scan_ret = $fscanf(fd, "%s", cur_line);
end
$fclose(fd);
get_num_tests = cur_num;
end
end
endfunction
/* Returns the key or IV of a particular test */
function [79:0] get_key_iv;
input [8*20:1] i_file_name;
input [8*3:1] key_or_iv;
input [31:0] test_num;
reg [8*20:1] cur_line;
reg [79:0] ret_val;
integer cur_num;
integer fd;
integer scan_ret;
integer fpos;
begin
cur_num = 0;
fd = $fopen(i_file_name, "r");
if (!fd) begin
$display("ERROR: Could not open '%s'", i_file_name);
$finish;
end
else begin
/* Iterate until specified test is found */
fpos = $ftell(fd);
scan_ret = $fscanf(fd, "%s", cur_line);
while (cur_num < test_num && scan_ret) begin
if (cur_line == "-")
cur_num = cur_num + 1;
fpos = $ftell(fd);
scan_ret = $fscanf(fd, "%s", cur_line);
end
if (cur_line == ".") begin
$display("ERROR: Incorrect test number specified: %d", test_num);
$fclose(fd);
$finish;
end
/* Get key or IV and return, get back previous line to interpret as hex */
$fseek(fd, fpos, 0);
if (key_or_iv == "key")
scan_ret = $fscanf(fd, "%h", ret_val);
else if (key_or_iv == "iv") begin
scan_ret = $fscanf(fd, "%h", ret_val);
scan_ret = $fscanf(fd, "%h", ret_val);
end
else begin
$display("ERROR: Could not read requested value!");
$fclose(fd);
$finish;
end
$fclose(fd);
get_key_iv = ret_val;
end
end
endfunction
/* Return the number of 32-bit words in specified test */
function [31:0] get_num_words;
input [8*20:1] i_file_name;
input integer line_num;
input integer test_num;
reg [8*20:1] cur_line;
integer cur_num;
integer fd;
integer fpos;
integer scan_ret;
begin
cur_num = 0;
fd = $fopen(i_file_name, "r");
if (!fd) begin
$display("ERROR: Could not open '%s'", i_file_name);
$finish;
end
else begin
/* Iterate until specified test is found */
fpos = $ftell(fd);
scan_ret = $fscanf(fd, "%s", cur_line);
while (cur_num < test_num && scan_ret) begin
if (cur_line == "-")
cur_num = cur_num + 1;
fpos = $ftell(fd);
scan_ret = $fscanf(fd, "%s", cur_line);
end
if (cur_line == ".") begin
$display("ERROR: Incorrect test number specified: %d", test_num);
$fclose(fd);
$finish;
end
/* Skip the key and IV in case we are reading from input reference */
$fseek(fd, fpos, 0);
if (i_file_name == "trivium_ref_in.txt") begin
scan_ret = $fscanf(fd, "%s", cur_line);
scan_ret = $fscanf(fd, "%s", cur_line);
end
/* Counter number of words in current test */
cur_num = 0;
cur_line = "";
scan_ret = $fscanf(fd, "%s", cur_line);
while (cur_line != "-") begin
cur_num = cur_num + 1;
scan_ret = $fscanf(fd, "%s", cur_line);
end
$fclose(fd);
get_num_words = cur_num;
end
end
endfunction
/* Return 32-bit word from specified file */
function [31:0] get_word;
input [8*20:1] i_file_name;
input integer line_num;
input integer test_num;
reg [8*20:1] cur_line;
reg [79:0] cur_word;
integer cur_num;
integer fd;
integer fpos;
integer scan_ret;
begin
cur_num = 0;
fd = $fopen(i_file_name, "r");
if (!fd) begin
$display("ERROR: Could not open '%s'", i_file_name);
$finish;
end
else begin
/* Iterate until specified test is found */
fpos = $ftell(fd);
scan_ret = $fscanf(fd, "%s", cur_line);
while (cur_num < test_num && scan_ret) begin
if (cur_line == "-")
cur_num = cur_num + 1;
fpos = $ftell(fd);
scan_ret = $fscanf(fd, "%s", cur_line);
end
if (cur_line == ".") begin
$display("ERROR: Incorrect test number specified: %d", test_num);
$fclose(fd);
$finish;
end
/* Skip the key and IV in case we are reading from input reference */
$fseek(fd, fpos, 0);
if (i_file_name == "trivium_ref_in.txt") begin
scan_ret = $fscanf(fd, "%h", cur_word);
scan_ret = $fscanf(fd, "%h", cur_word);
end
/* Skip to specified word */
cur_num = 0;
scan_ret = $fscanf(fd, "%h", cur_word);
while (cur_num < line_num && scan_ret) begin
cur_num = cur_num + 1;
scan_ret = $fscanf(fd, "%h", cur_word);
end
$fclose(fd);
get_word = cur_word[31:0];
end
end
endfunction
////////////////////////////////////////////////////////////////////////////////
// Signal definitions
////////////////////////////////////////////////////////////////////////////////
/* Module inputs */
reg clk_i;
reg n_rst_i;
reg [31:0] dat_i;
reg [31:0] ld_dat_i;
reg [2:0] ld_reg_a_i;
reg [2:0] ld_reg_b_i;
reg init_i;
reg proc_i;
/* Module outputs */
wire [31:0] dat_o;
wire busy_o;
/* Other signals */
reg start_tests_s; /* Flag indicating the start of the tests */
reg [95:0] key_r; /* Key used for encryption */
reg [95:0] iv_r; /* IV used for encryption */
integer instr_v; /* Current stimulus instruction index */
integer dat_cntr_v; /* Data counter variable */
integer cur_test_v; /* Index of current test */
////////////////////////////////////////////////////////////////////////////////
// UUT Instantiation
////////////////////////////////////////////////////////////////////////////////
trivium_top uut(
.clk_i(clk_i),
.n_rst_i(n_rst_i),
.dat_i(dat_i),
.ld_dat_i(ld_dat_i),
.ld_reg_a_i(ld_reg_a_i),
.ld_reg_b_i(ld_reg_b_i),
.init_i(init_i),
.proc_i(proc_i),
.dat_o(dat_o),
.busy_o(busy_o)
);
////////////////////////////////////////////////////////////////////////////////
// UUT Initialization
////////////////////////////////////////////////////////////////////////////////
initial begin
/* Initialize Inputs */
clk_i = 0;
n_rst_i = 0;
dat_i = 0;
ld_dat_i = 0;
ld_reg_a_i = 0;
ld_reg_b_i = 0;
init_i = 0;
proc_i = 0;
/* Initialize other signals/variables */
start_tests_s = 0;
instr_v = 0;
dat_cntr_v = 0;
cur_test_v = 0;
/* Wait 100 ns for global reset to finish */
#100;
n_rst_i = 1'b1;
start_tests_s = 1'b1;
end
////////////////////////////////////////////////////////////////////////////////
// Clock generation
////////////////////////////////////////////////////////////////////////////////
always begin
#10 clk_i = ~clk_i;
end
////////////////////////////////////////////////////////////////////////////////
// Stimulus process
////////////////////////////////////////////////////////////////////////////////
always @(posedge clk_i or negedge n_rst_i) begin
if (!n_rst_i) begin
/* Reset registers driven here */
dat_i <= 0;
ld_dat_i <= 0;
ld_reg_a_i <= 0;
ld_reg_b_i <= 0;
init_i <= 0;
proc_i <= 0;
instr_v <= 0;
dat_cntr_v <= 0;
key_r <= 0;
iv_r <= 0;
end
else if (start_tests_s) begin
case (instr_v)
0: begin /* Instruction 0: Check if core is ready */
if (busy_o) begin
$display("ERROR: Test (Core ready) failed!");
$finish;
end
/* Get the current key and IV */
key_r[79:0] <= get_key_iv("trivium_ref_in.txt", "key", cur_test_v);
iv_r[79:0] <= get_key_iv("trivium_ref_in.txt", "iv", cur_test_v);
instr_v <= instr_v + 1;
end
1: begin /* Instruction 1: Write key to core */
/* Default value */
ld_reg_a_i <= 0;
if (dat_cntr_v < 3) begin
ld_reg_a_i[dat_cntr_v] <= 1'b1;
ld_dat_i <= key_r[(dat_cntr_v*32)+:32];
dat_cntr_v <= dat_cntr_v + 1;
end
else begin
dat_cntr_v = 0;
instr_v <= instr_v + 1;
end
end
2: begin /* Instruction 2: Write IV to core */
/* Default value */
ld_reg_b_i <= 0;
if (dat_cntr_v < 3) begin
ld_reg_b_i[dat_cntr_v] <= 1'b1;
ld_dat_i <= iv_r[(dat_cntr_v*32)+:32];
dat_cntr_v <= dat_cntr_v + 1;
end
else begin
dat_cntr_v <= 0;
instr_v <= instr_v + 1;
end
end
3: begin /* Instruction 3: Initialize the cipher */
init_i <= 1'b1;
if (busy_o)
instr_v <= instr_v + 1;
end
4: begin /* Instruction 4: Present a 32-bit value to encrypt */
init_i <= 0;
if (!busy_o) begin
proc_i <= 1'b1;
dat_i <= get_word("trivium_ref_in.txt", dat_cntr_v, cur_test_v);
instr_v <= instr_v + 1;
end
end
5: begin /* Instruction 5: Wait until device busy */
if (busy_o) begin
proc_i <= 0;
instr_v <= instr_v + 1;
end
end
6: begin /* Instruction 6: Get ciphertext from device */
if (!busy_o) begin
// Compare received ciphertext to reference
if (dat_o != get_word("trivium_ref_out.txt", dat_cntr_v, cur_test_v)) begin
$display("ERROR: Incorrect output in test %d, word %d!", cur_test_v, dat_cntr_v);
$display("%04x != %04x, input = %04x", dat_o, get_word("trivium_ref_out.txt", dat_cntr_v, cur_test_v), get_word("trivium_ref_in.txt", dat_cntr_v, cur_test_v));
$finish;
end
// Check if there is more data to encrypt in current test
if (dat_cntr_v < get_num_words("trivium_ref_in.txt", dat_cntr_v, cur_test_v) - 1) begin
dat_cntr_v <= dat_cntr_v + 1;
instr_v <= 4;
end
else begin
dat_cntr_v <= 0;
instr_v <= instr_v + 1;
end
end
end
7: begin /* Instruction 7: Check if all tests completed and decide what to do */
if (cur_test_v < get_num_tests("trivium_ref_in.txt") - 1) begin
cur_test_v <= cur_test_v + 1;
instr_v <= 0;
end
else begin
cur_test_v <= 0;
instr_v <= instr_v + 1;
end
end
default: begin
$display("Tests successfully completed!");
$finish;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_gpiov2 (IN_H, PAD_A_NOESD_H,PAD_A_ESD_0_H,PAD_A_ESD_1_H,
PAD, DM, HLD_H_N, IN, INP_DIS, IB_MODE_SEL, ENABLE_H, ENABLE_VDDA_H, ENABLE_INP_H, OE_N,
TIE_HI_ESD, TIE_LO_ESD, SLOW, VTRIP_SEL, HLD_OVR, ANALOG_EN, ANALOG_SEL, ENABLE_VDDIO, ENABLE_VSWITCH_H,
ANALOG_POL, OUT, AMUXBUS_A, AMUXBUS_B
,VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD, VSSIO,
VSSD, VSSIO_Q
);
input OUT;
input OE_N;
input HLD_H_N;
input ENABLE_H;
input ENABLE_INP_H;
input ENABLE_VDDA_H;
input ENABLE_VSWITCH_H;
input ENABLE_VDDIO;
input INP_DIS;
input IB_MODE_SEL;
input VTRIP_SEL;
input SLOW;
input HLD_OVR;
input ANALOG_EN;
input ANALOG_SEL;
input ANALOG_POL;
input [2:0] DM;
inout VDDIO;
inout VDDIO_Q;
inout VDDA;
inout VCCD;
inout VSWITCH;
inout VCCHIB;
inout VSSA;
inout VSSD;
inout VSSIO_Q;
inout VSSIO;
inout PAD;
inout PAD_A_NOESD_H,PAD_A_ESD_0_H,PAD_A_ESD_1_H;
inout AMUXBUS_A;
inout AMUXBUS_B;
output IN;
output IN_H;
output TIE_HI_ESD, TIE_LO_ESD;
reg [2:0] dm_final;
reg slow_final, vtrip_sel_final, inp_dis_final, out_final, oe_n_final, hld_ovr_final, analog_en_final, ib_mode_sel_final, analog_en_vdda, analog_en_vswitch,analog_en_vddio_q;
wire [2:0] dm_buf;
wire slow_buf, vtrip_sel_buf, inp_dis_buf, out_buf, oe_n_buf, hld_ovr_buf,ib_mode_sel_buf;
wire [2:0] dm_del;
wire slow_del, vtrip_sel_del, inp_dis_del, out_del, oe_n_del, hld_ovr_del,ib_mode_sel_del;
wire hld_h_n_del;
wire hld_h_n_buf;
reg notifier_dm, notifier_slow, notifier_oe_n, notifier_out, notifier_vtrip_sel, notifier_hld_ovr, notifier_inp_dis, notifier_ib_mode_sel;
reg notifier_enable_h, notifier;
assign hld_h_n_buf = hld_h_n_del;
assign hld_ovr_buf = hld_ovr_del;
assign dm_buf = dm_del;
assign inp_dis_buf = inp_dis_del;
assign vtrip_sel_buf = vtrip_sel_del;
assign slow_buf = slow_del;
assign oe_n_buf = oe_n_del;
assign out_buf = out_del;
assign ib_mode_sel_buf = ib_mode_sel_del;
specify
(INP_DIS => IN) = (0:0:0 , 0:0:0);
(INP_DIS => IN_H) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL==1'b0 & VTRIP_SEL==1'b1 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL==1'b0 & VTRIP_SEL==1'b1 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OUT => PAD ) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( IB_MODE_SEL==1'b1 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL==1'b1 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OUT=> PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL==1'b0 & VTRIP_SEL==1'b0 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL==1'b0 & VTRIP_SEL==1'b0 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
$width (negedge HLD_H_N, (15.500:0:15.500));
$width (posedge HLD_H_N, (15.500:0:15.500));
$width (negedge HLD_OVR, (15.500:0:15.500));
$width (posedge HLD_OVR, (15.500:0:15.500));
specparam tsetup = 5;
specparam tsetup1 = 0;
specparam thold = 5;
$setuphold (posedge ENABLE_H, negedge HLD_H_N, tsetup, thold, notifier_enable_h);
$setuphold (posedge ENABLE_VDDIO, posedge ENABLE_H, tsetup1, thold, notifier_enable_h);
$setuphold (negedge ENABLE_H, negedge ENABLE_VDDIO, tsetup1, thold, notifier_enable_h);
$setuphold (negedge HLD_H_N, posedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (negedge HLD_H_N, negedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (negedge HLD_H_N, posedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (negedge HLD_H_N, negedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (negedge HLD_H_N, posedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (negedge HLD_H_N, negedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (negedge HLD_H_N, posedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (negedge HLD_H_N, negedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (negedge HLD_H_N, posedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (negedge HLD_H_N, negedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (negedge HLD_H_N, posedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (negedge HLD_H_N, negedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (negedge HLD_H_N, posedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (negedge HLD_H_N, negedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (negedge HLD_H_N, posedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (negedge HLD_H_N, negedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (negedge HLD_H_N, posedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (negedge HLD_H_N, negedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (negedge HLD_H_N, posedge IB_MODE_SEL,tsetup, thold, notifier_ib_mode_sel,ENABLE_H==1'b1,ENABLE_H==1'b1, hld_h_n_del,ib_mode_sel_del);
$setuphold (negedge HLD_H_N, negedge IB_MODE_SEL,tsetup, thold, notifier_ib_mode_sel,ENABLE_H==1'b1,ENABLE_H==1'b1, hld_h_n_del,ib_mode_sel_del);
$setuphold (posedge HLD_H_N, posedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (posedge HLD_H_N, negedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (posedge HLD_H_N, posedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (posedge HLD_H_N, negedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (posedge HLD_H_N, posedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (posedge HLD_H_N, negedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (posedge HLD_H_N, posedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (posedge HLD_H_N, negedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (posedge HLD_H_N, posedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (posedge HLD_H_N, negedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (posedge HLD_H_N, posedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (posedge HLD_H_N, negedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (posedge HLD_H_N, posedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (posedge HLD_H_N, negedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (posedge HLD_H_N, posedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (posedge HLD_H_N, negedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (posedge HLD_H_N, posedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (posedge HLD_H_N, negedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (posedge HLD_H_N, posedge IB_MODE_SEL,tsetup, thold, notifier_ib_mode_sel,ENABLE_H==1'b1,ENABLE_H==1'b1,hld_h_n_del,ib_mode_sel_del);
$setuphold (posedge HLD_H_N, negedge IB_MODE_SEL,tsetup, thold, notifier_ib_mode_sel,ENABLE_H==1'b1,ENABLE_H==1'b1,hld_h_n_del,ib_mode_sel_del);
$setuphold (posedge HLD_OVR, negedge HLD_H_N, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_ovr_del, hld_h_n_del);
$setuphold (posedge DM[2], negedge HLD_H_N, tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, dm_del[2], hld_h_n_del);
$setuphold (posedge DM[1], negedge HLD_H_N, tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, dm_del[1], hld_h_n_del);
$setuphold (posedge DM[0], negedge HLD_H_N, tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, dm_del[0], hld_h_n_del);
$setuphold (posedge INP_DIS, negedge HLD_H_N, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, inp_dis_del, hld_h_n_del);
$setuphold (posedge VTRIP_SEL, negedge HLD_H_N, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, vtrip_sel_del, hld_h_n_del);
$setuphold (posedge SLOW, negedge HLD_H_N, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, slow_del, hld_h_n_del);
$setuphold (posedge OE_N, negedge HLD_H_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, oe_n_del, hld_h_n_del);
$setuphold (posedge OUT, negedge HLD_H_N, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, out_del, hld_h_n_del);
$setuphold (posedge IB_MODE_SEL,negedge HLD_H_N, tsetup, thold, notifier_ib_mode_sel,ENABLE_H==1'b1,ENABLE_H==1'b1, ib_mode_sel_del, hld_h_n_del);
endspecify
wire pwr_good_amux = ((hld_h_n_buf===0 || ENABLE_H===0) ? 1:(VCCD===1)) && (VSSD===0) && (VSSA===0) && (VSSIO_Q===0);
wire pwr_good_hold_ovr_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0) && (VCCHIB===1);
wire pwr_good_active_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0) && (VCCD===1);
wire pwr_good_hold_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0);
wire pwr_good_active_mode_vdda = (VDDA===1) && (VSSD===0) && (VCCD===1);
wire pwr_good_hold_mode_vdda = (VDDA===1) && (VSSD===0);
wire pwr_good_inpbuff_hv = (VDDIO_Q===1) && (VSSD===0) && (inp_dis_final===0 && dm_final!==3'b000 && ib_mode_sel_final===1 ? VCCHIB===1 : 1);
wire pwr_good_inpbuff_lv = (VDDIO_Q===1) && (VSSD===0) && (VCCHIB===1);
wire pwr_good_output_driver = (VDDIO===1) && (VDDIO_Q===1)&& (VSSIO===0) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_analog_en_vdda = (VDDA===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_analog_en_vddio_q = (VDDIO_Q ===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_analog_en_vswitch = (VSWITCH ===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_amux_vccd = ((hld_h_n_buf===0 || ENABLE_H===0) ? 1:(VCCD===1));
parameter MAX_WARNING_COUNT = 100;
wire pad_tristate = oe_n_final === 1 || dm_final === 3'b000 || dm_final === 3'b001;
wire x_on_pad = !pwr_good_output_driver
|| (dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'bx)
|| (^dm_final[2:0] === 1'bx && oe_n_final===1'b0)
|| (slow_final===1'bx && dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'b0);
`ifdef SKY130_FD_IO_TOP_GPIOV2_SLOW_BEHV
parameter SLOW_1_DELAY= 70;
parameter SLOW_0_DELAY= 40;
`else
parameter SLOW_1_DELAY= 0;
parameter SLOW_0_DELAY= 0;
`endif
integer slow_1_delay,slow_0_delay,slow_delay;
initial slow_1_delay = SLOW_1_DELAY;
initial slow_0_delay = SLOW_0_DELAY;
always @(*)
begin
if (SLOW===1)
slow_delay = slow_1_delay;
else
slow_delay = slow_0_delay;
end
bufif1 (pull1, strong0) #slow_delay dm2 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b010));
bufif1 (strong1, pull0) #slow_delay dm3 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b011));
bufif1 (highz1, strong0) #slow_delay dm4 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b100));
bufif1 (strong1, highz0) #slow_delay dm5 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b101));
bufif1 (strong1, strong0) #slow_delay dm6 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b110));
bufif1 (pull1, pull0) #slow_delay dm7 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b111));
tran pad_esd_1 (PAD,PAD_A_NOESD_H);
tran pad_esd_2 (PAD,PAD_A_ESD_0_H);
tran pad_esd_3 (PAD,PAD_A_ESD_1_H);
wire x_on_in_hv = (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===1'b1)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===1'b0);
wire x_on_in_lv = (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (ENABLE_H===0 && ^ENABLE_VDDIO===1'bx)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===1'b0);
wire disable_inp_buff = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_INP_H===0;
assign IN_H = (x_on_in_hv===1 || pwr_good_inpbuff_hv===0) ? 1'bx : (disable_inp_buff===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
wire disable_inp_buff_lv = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_VDDIO===0;
assign IN = (x_on_in_lv===1 || pwr_good_inpbuff_lv===0 ) ? 1'bx : (disable_inp_buff_lv===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
assign TIE_HI_ESD = VDDIO===1'b1 ? 1'b1 : 1'bx;
assign TIE_LO_ESD = VSSIO===1'b0 ? 1'b0 : 1'bx;
wire functional_mode_amux = (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_analog_en_vswitch ===1 );
wire x_on_analog_en_vdda = (pwr_good_analog_en_vdda !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VDDA_H ===1'bx) ));
wire zero_on_analog_en_vdda = ( (pwr_good_analog_en_vdda ===1 && ENABLE_VDDA_H ===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vddio_q = ( pwr_good_analog_en_vddio_q !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) ));
wire zero_on_analog_en_vddio_q = ( (pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vswitch = (pwr_good_analog_en_vswitch !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VSWITCH_H ===1'bx) ));
wire zero_on_analog_en_vswitch = ( (pwr_good_analog_en_vswitch ===1 && ENABLE_VSWITCH_H ===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
always @(*)
begin : LATCH_dm
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
dm_final <= 3'bxxx;
end
else if (ENABLE_H===0)
begin
dm_final <= 3'b000;
end
else if (hld_h_n_buf===1)
begin
dm_final <= (^dm_buf[2:0] === 1'bx || !pwr_good_active_mode) ? 3'bxxx : dm_buf;
end
end
always @(notifier_enable_h or notifier_dm)
begin
disable LATCH_dm; dm_final <= 3'bxxx;
end
always @(*)
begin : LATCH_inp_dis
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
inp_dis_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
inp_dis_final <= 1'b1;
end
else if (hld_h_n_buf===1)
begin
inp_dis_final <= (^inp_dis_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : inp_dis_buf;
end
end
always @(notifier_enable_h or notifier_inp_dis)
begin
disable LATCH_inp_dis; inp_dis_final <= 1'bx;
end
always @(*)
begin : LATCH_vtrip_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
vtrip_sel_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
vtrip_sel_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
vtrip_sel_final <= (^vtrip_sel_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : vtrip_sel_buf;
end
end
always @(notifier_enable_h or notifier_vtrip_sel)
begin
disable LATCH_vtrip_sel; vtrip_sel_final <= 1'bx;
end
always @(*)
begin : LATCH_ib_mode_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
ib_mode_sel_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
ib_mode_sel_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
ib_mode_sel_final <= (^ib_mode_sel_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : ib_mode_sel_buf;
end
end
always @(notifier_enable_h or notifier_ib_mode_sel)
begin
disable LATCH_ib_mode_sel; ib_mode_sel_final <= 1'bx;
end
always @(*)
begin : LATCH_slow
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
slow_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
slow_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
slow_final <= (^slow_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : slow_buf;
end
end
always @(notifier_enable_h or notifier_slow)
begin
disable LATCH_slow; slow_final <= 1'bx;
end
always @(*)
begin : LATCH_hld_ovr
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
hld_ovr_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
hld_ovr_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
hld_ovr_final <= (^hld_ovr_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : hld_ovr_buf;
end
end
always @(notifier_enable_h or notifier_hld_ovr)
begin
disable LATCH_hld_ovr; hld_ovr_final <= 1'bx;
end
always @(*)
begin : LATCH_oe_n
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx || (hld_h_n_buf===0 && hld_ovr_final===1'bx) || (hld_h_n_buf===1 && hld_ovr_final===1'bx))))
begin
oe_n_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
oe_n_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
oe_n_final <= (^oe_n_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : oe_n_buf;
end
end
always @(notifier_enable_h or notifier_oe_n)
begin
disable LATCH_oe_n; oe_n_final <= 1'bx;
end
always @(*)
begin : LATCH_out
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx ||(hld_h_n_buf===0 && hld_ovr_final===1'bx || (hld_h_n_buf===1 && hld_ovr_final===1'bx)))))
begin
out_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
out_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
out_final <= (^out_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : out_buf;
end
end
always @(notifier_enable_h or notifier_out)
begin
disable LATCH_out; out_final <= 1'bx;
end
always @(*)
begin
if (x_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'bx;
end
else if ( zero_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'b0;
end
else if (x_on_analog_en_vdda !==1 && zero_on_analog_en_vdda !==1)
begin
analog_en_vdda <= ANALOG_EN;
end
if (x_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'bx;
end
else if ( zero_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'b0;
end
else if ( x_on_analog_en_vddio_q !==1 && zero_on_analog_en_vddio_q !==1)
begin
analog_en_vddio_q <= ANALOG_EN;
end
if (x_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'bx;
end
else if ( zero_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'b0;
end
else if (x_on_analog_en_vswitch !==1 && zero_on_analog_en_vswitch !==1)
begin
analog_en_vswitch <= ANALOG_EN;
end
if ( (analog_en_vswitch ===1'bx && analog_en_vdda ===1'bx) || (analog_en_vswitch ===1'bx && analog_en_vddio_q ===1'bx) || (analog_en_vddio_q ===1'bx && analog_en_vdda ===1'bx ) )
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vdda ===1'bx && (analog_en_vddio_q ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vddio_q ===1'bx && (analog_en_vdda ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vswitch===1'bx && (analog_en_vdda ===1 || analog_en_vddio_q ===1 ))
begin
analog_en_final <= 1'bx;
end
else if ((analog_en_vdda ===0 && analog_en_vddio_q ===0 )|| (analog_en_vdda ===0 && analog_en_vswitch===0 ) || (analog_en_vddio_q ===0 && analog_en_vswitch===0 ))
begin
analog_en_final <=0;
end
else if (analog_en_vdda ===1 && analog_en_vddio_q ===1 && analog_en_vswitch ===1)
begin
analog_en_final <=1;
end
end
wire [2:0] amux_select = {ANALOG_SEL, ANALOG_POL, out_buf};
wire invalid_controls_amux = (analog_en_final===1'bx && inp_dis_final===1)
|| !pwr_good_amux
|| (analog_en_final===1 && ^amux_select[2:0] === 1'bx && inp_dis_final===1);
wire enable_pad_amuxbus_a = invalid_controls_amux ? 1'bx : (amux_select===3'b001 || amux_select===3'b010) && (analog_en_final===1);
wire enable_pad_amuxbus_b = invalid_controls_amux ? 1'bx : (amux_select===3'b101 || amux_select===3'b110) && (analog_en_final===1);
wire enable_pad_vssio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b100 || amux_select===3'b000) && (analog_en_final===1);
wire enable_pad_vddio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b011 || amux_select===3'b111) && (analog_en_final===1);
tranif1 pad_amuxbus_a (PAD, AMUXBUS_A, enable_pad_amuxbus_a);
tranif1 pad_amuxbus_b (PAD, AMUXBUS_B, enable_pad_amuxbus_b);
bufif1 pad_vddio_q (PAD, VDDIO_Q, enable_pad_vddio_q);
bufif1 pad_vssio_q (PAD, VSSIO_Q, enable_pad_vssio_q);
reg dis_err_msgs;
integer msg_count_pad,msg_count_pad1,msg_count_pad2,msg_count_pad3,msg_count_pad4,msg_count_pad5,msg_count_pad6,msg_count_pad7,msg_count_pad8,msg_count_pad9,msg_count_pad10,msg_count_pad11,msg_count_pad12;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0;
msg_count_pad1 = 0;
msg_count_pad2 = 0;
msg_count_pad3 = 0;
msg_count_pad4 = 0;
msg_count_pad5 = 0;
msg_count_pad6 = 0;
msg_count_pad7 = 0;
msg_count_pad8 = 0;
msg_count_pad9 = 0;
msg_count_pad10 = 0;
msg_count_pad11 = 0;
msg_count_pad12 = 0;
`ifdef SKY130_FD_IO_TOP_GPIOV2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
wire #100 error_enable_vddio = (ENABLE_VDDIO===0 && ENABLE_H===1);
event event_error_enable_vddio;
always @(error_enable_vddio)
begin
if (!dis_err_msgs)
begin
if (error_enable_vddio===1)
begin
msg_count_pad = msg_count_pad + 1;
->event_error_enable_vddio;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : Enable_h (= %b) and ENABLE_VDDIO (= %b) are complement of each \other. This is an illegal combination as ENABLE_VDDIO and ENABLE_H are the same input signals IN different power \domains %m", ENABLE_H, ENABLE_VDDIO, $stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda = ( VDDA===1 && VDDIO_Q !==1 && ENABLE_VDDA_H===1 );
event event_error_vdda;
always @(error_vdda)
begin
if (!dis_err_msgs)
begin
if (error_vdda===1)
begin
msg_count_pad1 = msg_count_pad1 + 1;
->event_error_vdda;
if (msg_count_pad1 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VDDA_H (= %b) cannot be 1 when VDDA (= %b) and VDDIO_Q (= %b) %m",ENABLE_VDDA_H, VDDA,VDDIO_Q,$stime);
end
else
if (msg_count_pad1 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda2 = ( VDDA===1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && VCCD===1 && ANALOG_EN ===1 );
event event_error_vdda2;
always @(error_vdda2)
begin
if (!dis_err_msgs)
begin
if (error_vdda2===1)
begin
msg_count_pad2 = msg_count_pad2 + 1;
->event_error_vdda2;
if (msg_count_pad2 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ANALOG_EN (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b),hld_h_n_buf (= %b) and VCCD (= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad2 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda3 = ( VDDA===1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && VCCD !==1 );
event event_error_vdda3;
always @(error_vdda3)
begin
if (!dis_err_msgs)
begin
if (error_vdda3===1)
begin
msg_count_pad3 = msg_count_pad3 + 1;
->event_error_vdda3;
if (msg_count_pad3 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : VCCD (= %b) cannot be any value other than 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",VCCD,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad3 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch1 = (VDDA !==1 && VDDIO_Q !==1 && VSWITCH ===1 && (ENABLE_VSWITCH_H===1)) ;
event event_error_vswitch1;
always @(error_vswitch1)
begin
if (!dis_err_msgs)
begin
if (error_vswitch1===1)
begin
msg_count_pad4 = msg_count_pad4 + 1;
->event_error_vswitch1;
if (msg_count_pad4 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VSWITCH_H (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad4 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch2 = (VDDA !==1 && VDDIO_Q !==1 && VSWITCH ===1 && VCCD===1 && ANALOG_EN===1);
event event_error_vswitch2;
always @(error_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vswitch2===1)
begin
msg_count_pad5 = msg_count_pad5 + 1;
->event_error_vswitch2;
if (msg_count_pad5 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ANALOG_EN (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b) & VCCD(= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,VCCD,$stime);
end
else
if (msg_count_pad5 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch3 = (VDDA ===1 && VDDIO_Q !==1 && VSWITCH ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch3;
always @(error_vswitch3)
begin
if (!dis_err_msgs)
begin
if (error_vswitch3===1)
begin
msg_count_pad6 = msg_count_pad6 + 1;
->event_error_vswitch3;
if (msg_count_pad6 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad6 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch4 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch4;
always @(error_vswitch4)
begin
if (!dis_err_msgs)
begin
if (error_vswitch4===1)
begin
msg_count_pad7 = msg_count_pad7 + 1;
->event_error_vswitch4;
if (msg_count_pad7 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad7 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch5 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1);
event event_error_vswitch5;
always @(error_vswitch5)
begin
if (!dis_err_msgs)
begin
if (error_vswitch5===1)
begin
msg_count_pad8 = msg_count_pad8 + 1;
->event_error_vswitch5;
if (msg_count_pad8 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ANALOG_EN(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b),hld_h_n_buf (= %b) and VCCD (= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad8 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q1 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD!==1);
event event_error_vddio_q1;
always @(error_vddio_q1)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q1===1)
begin
msg_count_pad9 = msg_count_pad9 + 1;
->event_error_vddio_q1;
if (msg_count_pad9 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : VCCD(= %b) cannot be any value other than 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",VCCD,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad9 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q2 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1);
event event_error_vddio_q2;
always @(error_vddio_q2)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q2===1)
begin
msg_count_pad10 = msg_count_pad10 + 1;
->event_error_vddio_q2;
if (msg_count_pad10 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ANALOG_EN(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b) , hld_h_n_buf (= %b) && VCCD (= %b) %m",ANALOG_EN, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad10 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_supply_good = ( VDDA ===1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1 && ENABLE_VSWITCH_H !==1 && ENABLE_VSWITCH_H !==0 );
event event_error_supply_good;
always @(error_supply_good)
begin
if (!dis_err_msgs)
begin
if (error_supply_good===1)
begin
msg_count_pad11 = msg_count_pad11 + 1;
->event_error_supply_good;
if (msg_count_pad11 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VSWITCH_H(= %b) should be either 1 or 0 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,VCCD (= %b) and ANALOG_EN(= %b) %m",ENABLE_VSWITCH_H, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,ANALOG_EN,$stime);
end
else
if (msg_count_pad11 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda_vddioq_vswitch2 = ( VDDA ===1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1 && ENABLE_VDDA_H !==1 && ENABLE_VDDA_H !==0 );
event event_error_vdda_vddioq_vswitch2;
always @(error_vdda_vddioq_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vdda_vddioq_vswitch2===1)
begin
msg_count_pad12 = msg_count_pad12 + 1;
->event_error_vdda_vddioq_vswitch2;
if (msg_count_pad12 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VDDA_H(= %b) should be either 1 or 0 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,VCCD (= %b) and ANALOG_EN(= %b) %m",ENABLE_VDDA_H, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,ANALOG_EN,$stime);
end
else
if (msg_count_pad12 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
|
/*
-- ============================================================================
-- FILE NAME : bus_if.v
-- DESCRIPTION : ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "cpu.h"
`include "bus.h"
/********** ¥â¥¸¥å©`¥ë **********/
module bus_if (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥åÐźÅ
output reg busy, // ¥Ó¥¸©`ÐźÅ
/********** CPU¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordAddrBus] addr, // ¥¢¥É¥ì¥¹
input wire as_, // ¥¢¥É¥ì¥¹Óп
input wire rw, // Õi¤ß£¯ø¤
input wire [`WordDataBus] wr_data, // ø¤Þz¤ß¥Ç©`¥¿
output reg [`WordDataBus] rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
/********** SPM¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] spm_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire [`WordAddrBus] spm_addr, // ¥¢¥É¥ì¥¹
output reg spm_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire spm_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] spm_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] bus_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire bus_rdy_, // ¥ì¥Ç¥£
input wire bus_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
output reg bus_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
output reg [`WordAddrBus] bus_addr, // ¥¢¥É¥ì¥¹
output reg bus_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output reg bus_rw, // Õi¤ß£¯ø¤
output reg [`WordDataBus] bus_wr_data // ø¤Þz¤ß¥Ç©`¥¿
);
/********** ÄÚ²¿ÐźŠ**********/
reg [`BusIfStateBus] state; // ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹¤Î×´B
reg [`WordDataBus] rd_buf; // Õi¤ß³ö¤·¥Ð¥Ã¥Õ¥¡
wire [`BusSlaveIndexBus] s_index; // ¥Ð¥¹¥¹¥ì©`¥Ö¥¤¥ó¥Ç¥Ã¥¯¥¹
/********** ¥Ð¥¹¥¹¥ì©`¥Ö¤Î¥¤¥ó¥Ç¥Ã¥¯¥¹ **********/
assign s_index = addr[`BusSlaveIndexLoc];
/********** ³öÁ¦¤Î¥¢¥µ¥¤¥ó **********/
assign spm_addr = addr;
assign spm_rw = rw;
assign spm_wr_data = wr_data;
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹¤ÎÖÆÓù **********/
always @(*) begin
/* ¥Ç¥Õ¥©¥ë¥È */
rd_data = `WORD_DATA_W'h0;
spm_as_ = `DISABLE_;
busy = `DISABLE;
/* ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹¤Î×´B */
case (state)
`BUS_IF_STATE_IDLE : begin // ¥¢¥¤¥É¥ë
/* ¥á¥â¥ê¥¢¥¯¥»¥¹ */
if ((flush == `DISABLE) && (as_ == `ENABLE_)) begin
/* ¥¢¥¯¥»¥¹ÏȤÎßxk */
if (s_index == `BUS_SLAVE_1) begin // SPM¤Ø¥¢¥¯¥»¥¹
if (stall == `DISABLE) begin // ¥¹¥È©`¥ë°kÉú¤Î¥Á¥§¥Ã¥¯
spm_as_ = `ENABLE_;
if (rw == `READ) begin // Õi¤ß³ö¤·¥¢¥¯¥»¥¹
rd_data = spm_rd_data;
end
end
end else begin // ¥Ð¥¹¤Ø¥¢¥¯¥»¥¹
busy = `ENABLE;
end
end
end
`BUS_IF_STATE_REQ : begin // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
busy = `ENABLE;
end
`BUS_IF_STATE_ACCESS : begin // ¥Ð¥¹¥¢¥¯¥»¥¹
/* ¥ì¥Ç¥£´ý¤Á */
if (bus_rdy_ == `ENABLE_) begin // ¥ì¥Ç¥£µ½×Å
if (rw == `READ) begin // Õi¤ß³ö¤·¥¢¥¯¥»¥¹
rd_data = bus_rd_data;
end
end else begin // ¥ì¥Ç¥£Î´µ½×Å
busy = `ENABLE;
end
end
`BUS_IF_STATE_STALL : begin // ¥¹¥È©`¥ë
if (rw == `READ) begin // Õi¤ß³ö¤·¥¢¥¯¥»¥¹
rd_data = rd_buf;
end
end
endcase
end
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹¤Î×´BÖÆÓù **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ·ÇͬÆڥꥻ¥Ã¥È */
state <= #1 `BUS_IF_STATE_IDLE;
bus_req_ <= #1 `DISABLE_;
bus_addr <= #1 `WORD_ADDR_W'h0;
bus_as_ <= #1 `DISABLE_;
bus_rw <= #1 `READ;
bus_wr_data <= #1 `WORD_DATA_W'h0;
rd_buf <= #1 `WORD_DATA_W'h0;
end else begin
/* ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹¤Î×´B */
case (state)
`BUS_IF_STATE_IDLE : begin // ¥¢¥¤¥É¥ë
/* ¥á¥â¥ê¥¢¥¯¥»¥¹ */
if ((flush == `DISABLE) && (as_ == `ENABLE_)) begin
/* ¥¢¥¯¥»¥¹ÏȤÎßxk */
if (s_index != `BUS_SLAVE_1) begin // ¥Ð¥¹¤Ø¥¢¥¯¥»¥¹
state <= #1 `BUS_IF_STATE_REQ;
bus_req_ <= #1 `ENABLE_;
bus_addr <= #1 addr;
bus_rw <= #1 rw;
bus_wr_data <= #1 wr_data;
end
end
end
`BUS_IF_STATE_REQ : begin // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
/* ¥Ð¥¹¥°¥é¥ó¥È´ý¤Á */
if (bus_grnt_ == `ENABLE_) begin // ¥Ð¥¹Ø«@µÃ
state <= #1 `BUS_IF_STATE_ACCESS;
bus_as_ <= #1 `ENABLE_;
end
end
`BUS_IF_STATE_ACCESS : begin // ¥Ð¥¹¥¢¥¯¥»¥¹
/* ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö¤Î¥Í¥²©`¥È */
bus_as_ <= #1 `DISABLE_;
/* ¥ì¥Ç¥£´ý¤Á */
if (bus_rdy_ == `ENABLE_) begin // ¥ì¥Ç¥£µ½×Å
bus_req_ <= #1 `DISABLE_;
bus_addr <= #1 `WORD_ADDR_W'h0;
bus_rw <= #1 `READ;
bus_wr_data <= #1 `WORD_DATA_W'h0;
/* Õi¤ß³ö¤·¥Ç©`¥¿¤Î±£´æ */
if (bus_rw == `READ) begin // Õi¤ß³ö¤·¥¢¥¯¥»¥¹
rd_buf <= #1 bus_rd_data;
end
/* ¥¹¥È©`¥ë°kÉú¤Î¥Á¥§¥Ã¥¯ */
if (stall == `ENABLE) begin // ¥¹¥È©`¥ë°kÉú
state <= #1 `BUS_IF_STATE_STALL;
end else begin // ¥¹¥È©`¥ëδ°kÉú
state <= #1 `BUS_IF_STATE_IDLE;
end
end
end
`BUS_IF_STATE_STALL : begin // ¥¹¥È©`¥ë
/* ¥¹¥È©`¥ë°kÉú¤Î¥Á¥§¥Ã¥¯ */
if (stall == `DISABLE) begin // ¥¹¥È©`¥ë½â³ý
state <= #1 `BUS_IF_STATE_IDLE;
end
end
endcase
end
end
endmodule
|
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
//
// Company: University of Bonn
// Engineer: John Bieling
//
// Sample implementation of jTDC using Spartan6 on
// ELB VFB6 board with Discriminator inputs
//
//////////////////////////////////////////////////////////////////////////////////
module jDisc (
inout wire [31:0] D_INT,
input wire [15:0] A_INT,
input wire WRITE_INT,
input wire READ_INT,
output wire DTACK_INT,
input wire CLK,
inout wire SCL_General,
inout wire SDA_General,
output wire [7:0] USER_LED,
input wire [7:0] Pushbutton,
input wire [1:0] Differential_IN,
inout wire [73:0] FPGA_SPARE,
input wire [3:0] NIM_IN,
output wire [3:0] NIM_OUT,
inout wire [73:0] MEZ_A,
inout wire [73:0] MEZ_B,
inout wire [73:0] MEZ_C,
input wire [5:0] ID_A,
input wire [5:0] ID_B,
input wire [5:0] ID_C);
//-----------------------------------------------------------------------------
//-- Basic Setup --------------------------------------------------------------
//-----------------------------------------------------------------------------
parameter fw = 8'h22;
parameter resolution = 2; //readout every second carry step
parameter bits = 96; //empirical value for resolution=2 on VFB6
parameter encodedbits = 9; //includes hit bit
parameter fifocounts = 15; //max event size: (fifocounts+1)*1024-150;
parameter disc_channels = 48; //number of disk_input channels max=48
parameter input_channels = disc_channels+2;
parameter tdc_channels = 51+disc_channels; //because we have the "extra" channel 50, which is not used
genvar i;
//-----------------------------------------------------------------------------
//-- IO cards Setup for VFB6 board --------------------------------------------
//-----------------------------------------------------------------------------
wire [15:0] DISC16_A_INPUT;
wire [15:0] DISC16_B_INPUT;
wire [15:0] DISC16_C_INPUT;
mez_disc16 #(.mybaseaddress(16'hA000),.use_clk_buf(16'b0)) disc16_meza ( .databus(databus), .addressbus(addressbus) , .writesignal(writesignal) , .readsignal(readsignal) , .Discriminator_Channel(DISC16_A_INPUT), .MEZ({ID_A,MEZ_A}), .CLK(CLKBUS));
mez_disc16 #(.mybaseaddress(16'hA040),.use_clk_buf(16'b0)) disc16_mezb ( .databus(databus), .addressbus(addressbus) , .writesignal(writesignal) , .readsignal(readsignal) , .Discriminator_Channel(DISC16_B_INPUT), .MEZ({ID_B,MEZ_B}), .CLK(CLKBUS));
mez_disc16 #(.mybaseaddress(16'hA080),.use_clk_buf(16'b0)) disc16_mezc ( .databus(databus), .addressbus(addressbus) , .writesignal(writesignal) , .readsignal(readsignal) , .Discriminator_Channel(DISC16_C_INPUT), .MEZ({ID_C,MEZ_C}), .CLK(CLKBUS));
//-----------------------------------------------------------------------------
//-- CLK Setup for Spartan6 ---------------------------------------------------
//-----------------------------------------------------------------------------
wire CLKBUS;
wire CLK200;
wire CLK400;
pll_vfb6_400 PLL_TDC (
.CLKIN(CLK),
.CLK1(CLKBUS),
.CLK2(CLK200),
.CLK4(CLK400));
//---------------------------------------------------------------------------------
//-- VME-BUS Setup for VFB6 board (res. addr: h0000, h0004, h0008, h0010, h0014) --
//---------------------------------------------------------------------------------
wire [31:0] statusregister;
wire [31:0] databus;
wire [15:0] addressbus;
wire readsignal;
wire writesignal;
assign statusregister [7:0] = 8'b00000001; //-- Firmware version
assign statusregister [13:8] = 6'b000001; //-- Firmware type
//-- For REV B boards
//Discriminator MEZ does not provide an ID
//assign statusregister [19:14] = ID_A; //-- Board type Mezzanine_A
//assign statusregister [25:20] = ID_B; //-- Board type Mezzanine_B
//assign statusregister [31:26] = ID_C; //-- Board type Mezzanine_C
bus_interface_vfb6 BUS_INT (
.board_databus(D_INT),
.board_address(A_INT),
.board_read(READ_INT),
.board_write(WRITE_INT),
.board_dtack(DTACK_INT),
.CLK(CLKBUS),
.statusregister(statusregister),
.internal_databus(databus),
.internal_address(addressbus),
.internal_read(readsignal),
.internal_write(writesignal));
//-----------------------------------------------------------------------------
//-- I2C Setup for VFB6 board (res. addr: h0030, h0034, h0038, h003C, h0040) --
//-- not needed for actual jTDC, just an additional feature of the VFB6 --
//-----------------------------------------------------------------------------
i2c_interface I2C_INT (
.databus(databus),
.addressbus(addressbus),
.CLK(CLKBUS),
.writesignal(writesignal),
.readsignal(readsignal),
.SCL_General(SCL_General),
.SDA_General(SDA_General));
//-----------------------------------------------------------------------------
//-- VME Control Register A ---------------------------------------------------
//-----------------------------------------------------------------------------
(* KEEP = "true" *) wire [31:0] config_register_A;
rw_register #(.myaddress(16'h0020)) VME_CONFIG_REGISTER_A (
.databus(databus),
.addressbus(addressbus),
.readsignal(readsignal),
.writesignal(writesignal),
.CLK(CLKBUS),
.registerbits(config_register_A));
wire [4:0] geoid = config_register_A[4:0];
wire dutycycle = config_register_A[5];
wire edgechoice = config_register_A[6];
wire tdc_trigger_select = config_register_A[7];
wire [23:0] clock_limit = config_register_A[31:8];
//-----------------------------------------------------------------------------
//-- VME Control Register B ---------------------------------------------------
//-----------------------------------------------------------------------------
(* KEEP = "TRUE" *) wire [31:0] config_register_B;
rw_register #(.myaddress(16'h0028)) VME_CONFIG_REGISTER_B (
.databus(databus),
.addressbus(addressbus),
.writesignal(writesignal),
.readsignal(readsignal),
.CLK(CLKBUS),
.registerbits(config_register_B));
wire [8:0] busyshift = config_register_B[8:0];
wire stop_counting_on_busy = config_register_B[9];
wire [4:0] busyextend = config_register_B[15:11];
wire [3:0] hightime = config_register_B[19:16];
wire [3:0] deadtime = config_register_B[23:20];
wire [2:0] trigger_group_0 = config_register_B[26:24];
wire [2:0] trigger_group_1 = config_register_B[29:27];
wire disable_external_latch = config_register_B[30];
wire fake_mode = config_register_B[31];
//-----------------------------------------------------------------------------
//-- VME Trigger Register -----------------------------------------------------
//-----------------------------------------------------------------------------
wire [7:0] iFW = fw;
wire [7:0] iCH = tdc_channels;
wire [7:0] iBIT = encodedbits-1; //the hit-bit is not pushed into the fifo
wire [7:0] iM = 8'h40;
wire [31:0] trigger_register_wire;
toggle_register #(.myaddress(16'h0024)) VME_TRIGGER_REGISTER (
.databus(databus),
.addressbus(addressbus),
.writesignal(writesignal),
.readsignal(readsignal),
.CLK(CLKBUS),
.info({iCH,iBIT,iM,iFW}),
.registerbits(trigger_register_wire));
//cross clock domain
reg [31:0] trigger_register;
always@(posedge CLK200)
begin
trigger_register <= trigger_register_wire;
end
//-- toggle bit 0: tdc_reset, make tdc_reset multiple cycles long
wire tdc_reset_start = trigger_register[0];
reg [3:0] tdc_reset_counter = 4'b0000;
reg tdc_reset;
reg tdc_reset_buffer;
always@(posedge CLKBUS)
begin
tdc_reset <= tdc_reset_buffer;
if (tdc_reset_counter == 4'b0000)
begin
tdc_reset_buffer <= 1'b0;
if (tdc_reset_start == 1'b1) tdc_reset_counter <= 4'b1111;
end else begin
tdc_reset_buffer <= 1'b1;
tdc_reset_counter <= tdc_reset_counter - 1;
end
end
//-- toggle bit 1: vme_counter_reset
wire vme_counter_reset;
datapipe #(.data_width(1),.pipe_steps(2)) counter_reset_pipe (
.data(trigger_register[1]),
.piped_data(vme_counter_reset),
.CLK(CLK200));
//-- toggle bit 2: vme_counter_latch
wire vme_counter_latch;
datapipe #(.data_width(1),.pipe_steps(1)) counter_latch_pipe (
.data(trigger_register[2]),
.piped_data(vme_counter_latch),
.CLK(CLK200));
//-- toggle bit 3: output_reset
wire output_reset = trigger_register[3];
//-- toggle bit 6: generate fake data input for busyshift measurement
wire fake_data;
signal_clipper fake_data_clip ( .sig(trigger_register[6]), .CLK(CLK200), .clipped_sig(fake_data));
//-----------------------------------------------------------------------------
//-- Enable Register ----------------------------------------------------------
//-----------------------------------------------------------------------------
//to keep the config equal to jTDC, the lowest 16bit of each
//config register correspond to the 16 disc inputs of each MEZ
//the remaining 16bit of each register are ignored
(* KEEP = "TRUE" *) wire [95:0] enable_register;
rw_register #(.myaddress(16'h2000)) VME_ENABLE_REGISTER_A (
.databus(databus),
.addressbus(addressbus),
.writesignal(writesignal),
.readsignal(readsignal),
.CLK(CLKBUS),
.registerbits({enable_register[63:48],enable_register[15:0]}));
rw_register #(.myaddress(16'h2004)) VME_ENABLE_REGISTER_B (
.databus(databus),
.addressbus(addressbus),
.writesignal(writesignal),
.readsignal(readsignal),
.CLK(CLKBUS),
.registerbits({enable_register[79:64],enable_register[31:16]}));
rw_register #(.myaddress(16'h2008)) VME_ENABLE_REGISTER_C (
.databus(databus),
.addressbus(addressbus),
.writesignal(writesignal),
.readsignal(readsignal),
.CLK(CLKBUS),
.registerbits({enable_register[95:80],enable_register[47:32]}));
//-----------------------------------------------------------------------------
//-- Busy & Latch -------------------------------------------------------------
//-----------------------------------------------------------------------------
wire raw_busy;
wire latch;
reg busy;
reg counter_latch;
reg counter_reset;
//the leading edge of the "busy & latch" signal is the actual latch, which is used only to latch the input scaler
//while the "busy & latch" signal is asserted, the input scaler will not count (if stop_counting_on_busy is set)
leading_edge_extractor LATCH_EXTRACTOR (.sig(NIM_IN[0]), .CLK(CLK200), .unclipped_extend(busyextend), .clipped_sig(latch), .unclipped_sig(raw_busy) );
always@(posedge CLK200)
begin
busy <= stop_counting_on_busy & raw_busy;
counter_latch <= vme_counter_latch | (latch & ~disable_external_latch);
counter_reset <= vme_counter_reset;
end
//-----------------------------------------------------------------------------
//-- Map Inputs To 100 TDC Channels -------------------------------------------
//-----------------------------------------------------------------------------
wire [47:0] DISC_INPUTS = {DISC16_C_INPUT,DISC16_B_INPUT,DISC16_A_INPUT};
wire [input_channels-1:0] input_enable;
wire [input_channels-1:0] input_channel;
assign input_channel[0] = NIM_IN[0];
assign input_enable[0] = 1'b1;
assign input_enable[disc_channels:1] = enable_register[disc_channels-1:0];
assign input_channel[disc_channels:1] = (edgechoice == 1'b0) ? DISC_INPUTS[disc_channels-1:0] : ~DISC_INPUTS[disc_channels-1:0];
assign input_channel[input_channels-1] = NIM_IN[2];
assign input_enable[input_channels-1] = 1'b1;
//-----------------------------------------------------------------------------
//-- Sampling -----------------------------------------------------------------
//-----------------------------------------------------------------------------
wire [99:0] tdc_hits;
wire [input_channels-1:0] scaler_hits;
wire [tdc_channels*encodedbits-1:0] tdc_data_codes;
generate
for (i=0; i < input_channels; i=i+1) begin : INPUTSTAGE_LE
wire [bits-1:0] sample;
carry_sampler_spartan6 #(.bits(bits),.resolution(resolution)) SAMPLER (
.d(~input_channel[i]),
.q(sample),
.CLK(CLK400));
wire scaler;
encode_96bit_pattern #(.encodedbits(encodedbits)) ENCODE ( //For leading edge
.edgechoice(1'b1),
.d(sample),
.enable(input_enable[i]),
.CLK400(CLK400),
.CLK200(CLK200),
.code(tdc_data_codes[(i+1)*encodedbits-1:i*encodedbits]),
.tdc_hit(tdc_hits[i]),
.scaler_hit(scaler));
//fake scaler hit for busyshift determination
reg scaler_buffer;
if (i==1) begin
always@(posedge CLK200)
begin
if (fake_mode == 1'b1) begin
scaler_buffer <= fake_data;
end else begin
scaler_buffer <= scaler;
end
end
end else begin
always@(posedge CLK200)
begin
scaler_buffer <= scaler;
end
end
assign scaler_hits[i] = scaler_buffer;
end
for (i=51; i < disc_channels+51; i=i+1) begin : INPUTSTAGE_TE
encode_96bit_pattern #(.encodedbits(encodedbits)) ENCODE ( //For trailing edge
.edgechoice(1'b0),
.d(INPUTSTAGE_LE[i-50].sample),
.enable(input_enable[i-50]),
.CLK400(CLK400),
.CLK200(CLK200),
.code(tdc_data_codes[(i+1)*encodedbits-1:(i)*encodedbits]),
.tdc_hit(tdc_hits[i]),
.scaler_hit()); // we do not need scaler for TE, scaler_hits[i]
end
endgenerate
//unused channels
assign tdc_hits[99:tdc_channels] = 'b0;
//-----------------------------------------------------------------------------
//-- Generate Trigger Outputs -------------------------------------------------
//-----------------------------------------------------------------------------
wire [47:0] trigger_hits;
wire [23:0] trigger_first_or;
//only use data channels for trigger output
assign trigger_hits[47:0] = tdc_hits[48:1];
generate
for (i=0; i < 24; i=i+1) begin : TRIGGER_ORHITS
assign trigger_first_or[i] = |trigger_hits[i*2+1:i*2];
end
endgenerate
reg [23:0] trigger_out_0;
reg [5:0] trigger_out_1;
reg trigger_out_A;
reg trigger_out_B;
reg trigger_out_C;
reg [2:0] trigger_choice_0;
reg [2:0] trigger_choice_1;
reg [1:0] trigger_out;
always@(posedge CLK200)
begin
// generate trigger output signal
trigger_out_0 <= trigger_first_or;
trigger_out_1[0] <= |trigger_out_0[ 3: 0]; //A
trigger_out_1[1] <= |trigger_out_0[ 7: 4]; //A
trigger_out_1[2] <= |trigger_out_0[11: 8]; //B
trigger_out_1[3] <= |trigger_out_0[15:12]; //B
trigger_out_1[4] <= |trigger_out_0[19:16]; //C
trigger_out_1[5] <= |trigger_out_0[23:20]; //C
trigger_out_A <= |trigger_out_1[1:0]; //should cover input 1-16
trigger_out_B <= |trigger_out_1[3:2]; // 17-32
trigger_out_C <= |trigger_out_1[5:4]; // 33-48
if (trigger_group_0[0] == 1'b1) trigger_choice_0[0] <= trigger_out_A; else trigger_choice_0[0] <= 1'b0;
if (trigger_group_0[1] == 1'b1) trigger_choice_0[1] <= trigger_out_B; else trigger_choice_0[1] <= 1'b0;
if (trigger_group_0[2] == 1'b1) trigger_choice_0[2] <= trigger_out_C; else trigger_choice_0[2] <= 1'b0;
if (trigger_group_1[0] == 1'b1) trigger_choice_1[0] <= trigger_out_A; else trigger_choice_1[0] <= 1'b0;
if (trigger_group_1[1] == 1'b1) trigger_choice_1[1] <= trigger_out_B; else trigger_choice_1[1] <= 1'b0;
if (trigger_group_1[2] == 1'b1) trigger_choice_1[2] <= trigger_out_C; else trigger_choice_1[2] <= 1'b0;
trigger_out[0] <= |trigger_choice_0;
trigger_out[1] <= |trigger_choice_1;
end
//-----------------------------------------------------------------------------
//-- jTDC ---------------------------------------------------------------------
//-----------------------------------------------------------------------------
wire data_fifo_readrequest;
wire event_fifo_readrequest;
wire [31:0] data_fifo_value;
wire [31:0] event_fifo_value;
jTDC_core #(.tdc_channels(tdc_channels), .encodedbits(encodedbits), .fifocounts(fifocounts)) jTDC (
.tdc_hits(tdc_hits),
.tdc_data_codes(tdc_data_codes),
.tdc_trigger_select(tdc_trigger_select),
.tdc_reset(tdc_reset),
.clock_limit(clock_limit),
.geoid(geoid),
.iBIT(iBIT),
.CLK200(CLK200),
.CLKBUS(CLKBUS),
.event_fifo_readrequest(event_fifo_readrequest),
.data_fifo_readrequest(data_fifo_readrequest),
.event_fifo_value(event_fifo_value),
.data_fifo_value(data_fifo_value) );
readonly_register_with_readtrigger #(.myaddress(16'h8888)) EVENT_FIFO_READOUT (
.databus(databus),
.addressbus(addressbus),
.readsignal(readsignal),
.readtrigger(event_fifo_readrequest),
.CLK(CLKBUS),
.registerbits(event_fifo_value));
readonly_register_with_readtrigger #(.myaddress(16'h4444)) DATA_FIFO_READOUT (
.databus(databus),
.addressbus(addressbus),
.readsignal(readsignal),
.readtrigger(data_fifo_readrequest),
.CLK(CLKBUS),
.registerbits(data_fifo_value));
//-----------------------------------------------------------------------------
//-- SCALER -------------------------------------------------------------------
//-----------------------------------------------------------------------------
generate
if (input_channels > 0)
begin
//to reduce routing of the global addressbus, we implement an additional
//128 addr mux for the input scaler, they will use only one external addr
//each read request to the clock_counter_reg resets the scaler_addr and
//each read request to the input_counter_reg increments the scaler_addr
//furthermore, the input_counter_reg can be addressed by 128 consecutive
//addresses (addressbus is masked), so the external readout can be performed
//as usual, the input scalers just need to be read out in order
wire scaler_readout_addr_reset;
wire scaler_readout_addr_next;
reg [6:0] scaler_readout_addr;
wire [31:0] scaler_readout_pipe_addr;
wor [31:0] muxed_counts;
//busyshift
wire [63:0] shifted_hits;
BRAMSHIFT_512 #(.shift_bitsize(9),.width(2),.input_pipe_steps(1),.output_pipe_steps(1)) BRAM_BUSYSHIFT (
.d({'b0,scaler_hits}),
.q(shifted_hits),
.CLK(CLK200), .shift(busyshift));
//input counter
for (i=0; i < 64; i=i+1) begin : INPUT_HITS_COUNTER
if (i<input_channels) begin
//take sample[0] (re-inverted) for dutycycle measurement
(* KEEP = "true" *) wire dutyline = ~INPUTSTAGE_LE[i].sample[0];
reg busycount;
reg busycount_0;
reg busycount_1;
reg input_buffer;
always@(posedge CLK200) begin
input_buffer <= dutyline;
busycount_0 <= shifted_hits[i] && ~busy;
busycount_1 <= busycount_0;
if (dutycycle == 1'b0) busycount <= busycount_1;
else busycount <= input_buffer;
end
wire [31:0] input_counts;
dsp_multioption_counter #(.clip_count(0)) INPUT_COUNTER (
.countClock(CLK200),
.count(busycount),
.reset(counter_reset),
.countout(input_counts));
wire [31:0] input_latched_counts;
datalatch #(.latch_pipe_steps(1)) INPUT_COUNTER_DATALATCH (
.CLK(CLK200),
.latch(counter_latch),
.data(input_counts),
.latched_data(input_latched_counts));
//use the scaler_readout_addr to mux the correct counter to the readout register
//since the source data is latched, the ucf constraint CROSSCLOCK is giving this mux 50ns to settle
assign muxed_counts = (scaler_readout_addr == i) ? input_latched_counts : 32'b0;
end
end
reg delayed_inv_busy;
always@(posedge CLK200) begin
delayed_inv_busy <= !busy;
end
//referenz clock counter (to be able to calculate rates)
wire [31:0] pureclkcounts;
slimfast_multioption_counter #(.clip_count(0)) PURE_CLOCK_COUNTER (
.countClock(CLK200),
.count(delayed_inv_busy),
.reset(counter_reset),
.countout(pureclkcounts));
wire [31:0] clklatch;
datalatch #(.latch_pipe_steps(1)) CLOCK_COUNTER_DATALATCH (
.CLK(CLK200),
.latch(counter_latch),
.data(pureclkcounts),
.latched_data(clklatch));
//read of this register resets the scaler_readout_addr
readonly_register_with_readtrigger #(.myaddress(16'h0044)) CLOCK_COUNTER_READOUT (
.databus(databus),
.addressbus(addressbus),
.readsignal(readsignal),
.readtrigger(scaler_readout_addr_reset),
.CLK(CLKBUS),
.registerbits(clklatch));
//increment scaler_readout_addr on the negedge of next (=read)
//to keep the muxed value stable during read
dsp_multioption_counter #(.clip_count(1),.clip_reset(1)) SCALER_READOUT_ADDR_INC (
.countClock(CLKBUS),
.count(~scaler_readout_addr_next),
.reset(scaler_readout_addr_reset),
.countout(scaler_readout_pipe_addr));
reg [31:0] muxed_counts_pipe;
always@(posedge CLKBUS) begin
muxed_counts_pipe <= muxed_counts;
scaler_readout_addr <= scaler_readout_pipe_addr[6:0];
end
//each read of this register increments the scaler_readout_addr
readonly_register_with_readtrigger #(.myaddress(16'h4000)) INPUT_COUNTER_READOUT (
.databus(databus),
.addressbus({addressbus[15:9],9'b0}), //from these 9 bits only 7 are usable
.readsignal(readsignal),
.readtrigger(scaler_readout_addr_next),
.CLK(CLKBUS),
.registerbits(muxed_counts_pipe));
end
endgenerate
//-----------------------------------------------------------------------------
//-- NIM Outputs --------------------------------------------------------------
//-----------------------------------------------------------------------------
wire [1:0] trigger_output;
output_shaper TRIGGER_SHAPER_0 (
.d(trigger_out[0]),
.hightime(hightime),
.deadtime(deadtime),
.CLK(CLK200),
.pulse(trigger_output[0]),
.reset(output_reset));
output_shaper TRIGGER_SHAPER_1 (
.d(trigger_out[1]),
.hightime(hightime),
.deadtime(deadtime),
.CLK(CLK200),
.pulse(trigger_output[1]),
.reset(output_reset));
assign NIM_OUT[0] = 0;
assign NIM_OUT[1] = trigger_output[0]; //trigger out A
assign NIM_OUT[2] = 0;
assign NIM_OUT[3] = trigger_output[1]; //trigger out B
assign FPGA_SPARE = 0;
assign USER_LED = 0;
endmodule
|
//-----------------------------------------------------------------------------
//
// piwi, Feb 2019
//-----------------------------------------------------------------------------
module hi_get_trace(
ck_1356megb,
adc_d, trace_enable, major_mode,
ssp_frame, ssp_din, ssp_clk
);
input ck_1356megb;
input [7:0] adc_d;
input trace_enable;
input [2:0] major_mode;
output ssp_frame, ssp_din, ssp_clk;
// clock divider
reg [6:0] clock_cnt;
always @(negedge ck_1356megb)
begin
clock_cnt <= clock_cnt + 1;
end
// sample at 13,56MHz / 8. The highest signal frequency (subcarrier) is 848,5kHz, i.e. in this case we oversample by a factor of 2
reg [2:0] sample_clock;
always @(negedge ck_1356megb)
begin
if (sample_clock == 3'd7)
sample_clock <= 3'd0;
else
sample_clock <= sample_clock + 1;
end
reg [11:0] addr;
reg [11:0] start_addr;
reg [2:0] previous_major_mode;
reg write_enable1;
reg write_enable2;
always @(negedge ck_1356megb)
begin
previous_major_mode <= major_mode;
if (major_mode == `FPGA_MAJOR_MODE_HF_GET_TRACE)
begin
write_enable1 <= 1'b0;
write_enable2 <= 1'b0;
if (previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched into GET_TRACE mode
addr <= start_addr;
if (clock_cnt == 7'd0)
begin
if (addr == 12'd3071)
addr <= 12'd0;
else
addr <= addr + 1;
end
end
else if (major_mode != `FPGA_MAJOR_MODE_OFF)
begin
if (trace_enable)
begin
if (addr[11] == 1'b0)
begin
write_enable1 <= 1'b1;
write_enable2 <= 1'b0;
end
else
begin
write_enable1 <= 1'b0;
write_enable2 <= 1'b1;
end
if (sample_clock == 3'b000)
begin
if (addr == 12'd3071)
begin
addr <= 12'd0;
write_enable1 <= 1'b1;
write_enable2 <= 1'b0;
end
else
begin
addr <= addr + 1;
end
end
end
else
begin
write_enable1 <= 1'b0;
write_enable2 <= 1'b0;
start_addr <= addr;
end
end
else // major_mode == `FPGA_MAJOR_MODE_OFF
begin
write_enable1 <= 1'b0;
write_enable2 <= 1'b0;
if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off
begin
start_addr <= addr;
end
end
end
// (2+1)k RAM
reg [7:0] D_out1, D_out2;
reg [7:0] ram1 [2047:0]; // 2048 u8
reg [7:0] ram2 [1023:0]; // 1024 u8
always @(negedge ck_1356megb)
begin
if (write_enable1)
begin
ram1[addr[10:0]] <= adc_d;
D_out1 <= adc_d;
end
else
D_out1 <= ram1[addr[10:0]];
if (write_enable2)
begin
ram2[addr[9:0]] <= adc_d;
D_out2 <= adc_d;
end
else
D_out2 <= ram2[addr[9:0]];
end
// SSC communication to ARM
reg ssp_clk;
reg ssp_frame;
reg [7:0] shift_out;
always @(negedge ck_1356megb)
begin
if (clock_cnt[3:0] == 4'd0) // update shift register every 16 clock cycles
begin
if (clock_cnt[6:4] == 3'd0) // either load new value
begin
if (addr[11] == 1'b0)
shift_out <= D_out1;
else
shift_out <= D_out2;
end
else
begin
// or shift left
shift_out[7:1] <= shift_out[6:0];
end
end
ssp_clk <= ~clock_cnt[3]; // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz
if (clock_cnt[6:4] == 3'b000) // set ssp_frame for 0...31
ssp_frame <= 1'b1;
else
ssp_frame <= 1'b0;
end
assign ssp_din = shift_out[7];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:16:57 02/26/2016
// Design Name:
// Module Name: Register
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Register(
input clock_in,
input regWrite,
input [4:0] readReg1, //address to be read1
input [4:0] readReg2,
input [4:0] writeReg, //address to be write
input [31:0] writeData,
output reg [31:0] readData1,
output reg [31:0] readData2
);
reg [31:0] regFile[31:0];
always @(readReg1 or readReg2 or posedge clock_in)
begin
readData1 = regFile[readReg1];
readData2 = regFile[readReg2];
end
always @(negedge clock_in)
begin
if(regWrite)
regFile[writeReg] = writeData;
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// All of the general modules for ICB relevant functions
//
// ====================================================================
// ===========================================================================
//
// Description:
// The module to handle the ICB bus arbitration
//
// ===========================================================================
module sirv_gnrl_icb_arbt # (
parameter AW = 32,
parameter DW = 64,
parameter USR_W = 1,
parameter ARBT_SCHEME = 0,//0: priority based; 1: rrobin
// The number of outstanding transactions supported
parameter FIFO_OUTS_NUM = 1,
parameter FIFO_CUT_READY = 0,
// ARBT_NUM=4 ICB ports, so 2 bits for port id
parameter ARBT_NUM = 4,
parameter ALLOW_0CYCL_RSP = 1,
parameter ARBT_PTR_W = 2
) (
output o_icb_cmd_valid,
input o_icb_cmd_ready,
output [1-1:0] o_icb_cmd_read,
output [AW-1:0] o_icb_cmd_addr,
output [DW-1:0] o_icb_cmd_wdata,
output [DW/8-1:0] o_icb_cmd_wmask,
output [2-1:0] o_icb_cmd_burst,
output [2-1:0] o_icb_cmd_beat,
output o_icb_cmd_lock,
output o_icb_cmd_excl,
output [1:0] o_icb_cmd_size,
output [USR_W-1:0] o_icb_cmd_usr,
input o_icb_rsp_valid,
output o_icb_rsp_ready,
input o_icb_rsp_err,
input o_icb_rsp_excl_ok,
input [DW-1:0] o_icb_rsp_rdata,
input [USR_W-1:0] o_icb_rsp_usr,
output [ARBT_NUM*1-1:0] i_bus_icb_cmd_ready,
input [ARBT_NUM*1-1:0] i_bus_icb_cmd_valid,
input [ARBT_NUM*1-1:0] i_bus_icb_cmd_read,
input [ARBT_NUM*AW-1:0] i_bus_icb_cmd_addr,
input [ARBT_NUM*DW-1:0] i_bus_icb_cmd_wdata,
input [ARBT_NUM*DW/8-1:0] i_bus_icb_cmd_wmask,
input [ARBT_NUM*2-1:0] i_bus_icb_cmd_burst,
input [ARBT_NUM*2-1:0] i_bus_icb_cmd_beat ,
input [ARBT_NUM*1-1:0] i_bus_icb_cmd_lock ,
input [ARBT_NUM*1-1:0] i_bus_icb_cmd_excl ,
input [ARBT_NUM*2-1:0] i_bus_icb_cmd_size ,
input [ARBT_NUM*USR_W-1:0] i_bus_icb_cmd_usr ,
output [ARBT_NUM*1-1:0] i_bus_icb_rsp_valid,
input [ARBT_NUM*1-1:0] i_bus_icb_rsp_ready,
output [ARBT_NUM*1-1:0] i_bus_icb_rsp_err,
output [ARBT_NUM*1-1:0] i_bus_icb_rsp_excl_ok,
output [ARBT_NUM*DW-1:0] i_bus_icb_rsp_rdata,
output [ARBT_NUM*USR_W-1:0] i_bus_icb_rsp_usr,
input clk,
input rst_n
);
integer j;
wire [ARBT_NUM-1:0] i_bus_icb_cmd_grt_vec;
wire [ARBT_NUM-1:0] i_bus_icb_cmd_sel;
wire o_icb_cmd_valid_real;
wire o_icb_cmd_ready_real;
wire [1-1:0] i_icb_cmd_read [ARBT_NUM-1:0];
wire [AW-1:0] i_icb_cmd_addr [ARBT_NUM-1:0];
wire [DW-1:0] i_icb_cmd_wdata[ARBT_NUM-1:0];
wire [DW/8-1:0] i_icb_cmd_wmask[ARBT_NUM-1:0];
wire [2-1:0] i_icb_cmd_burst[ARBT_NUM-1:0];
wire [2-1:0] i_icb_cmd_beat [ARBT_NUM-1:0];
wire [1-1:0] i_icb_cmd_lock [ARBT_NUM-1:0];
wire [1-1:0] i_icb_cmd_excl [ARBT_NUM-1:0];
wire [2-1:0] i_icb_cmd_size [ARBT_NUM-1:0];
wire [USR_W-1:0]i_icb_cmd_usr [ARBT_NUM-1:0];
reg [1-1:0] sel_o_icb_cmd_read;
reg [AW-1:0] sel_o_icb_cmd_addr;
reg [DW-1:0] sel_o_icb_cmd_wdata;
reg [DW/8-1:0] sel_o_icb_cmd_wmask;
reg [2-1:0] sel_o_icb_cmd_burst;
reg [2-1:0] sel_o_icb_cmd_beat ;
reg [1-1:0] sel_o_icb_cmd_lock ;
reg [1-1:0] sel_o_icb_cmd_excl ;
reg [2-1:0] sel_o_icb_cmd_size ;
reg [USR_W-1:0]sel_o_icb_cmd_usr ;
wire o_icb_rsp_ready_pre;
wire o_icb_rsp_valid_pre;
wire rspid_fifo_bypass;
wire rspid_fifo_wen;
wire rspid_fifo_ren;
wire [ARBT_PTR_W-1:0] i_icb_rsp_port_id;
wire rspid_fifo_i_valid;
wire rspid_fifo_o_valid;
wire rspid_fifo_i_ready;
wire rspid_fifo_o_ready;
wire [ARBT_PTR_W-1:0] rspid_fifo_rdat;
wire [ARBT_PTR_W-1:0] rspid_fifo_wdat;
wire rspid_fifo_full;
wire rspid_fifo_empty;
reg [ARBT_PTR_W-1:0] i_arbt_indic_id;
wire i_icb_cmd_ready_pre;
wire i_icb_cmd_valid_pre;
wire arbt_ena;
wire [ARBT_PTR_W-1:0] o_icb_rsp_port_id;
genvar i;
generate //{
if(ARBT_NUM == 1) begin:arbt_num_eq_1_gen// {
assign i_bus_icb_cmd_ready = o_icb_cmd_ready ;
assign o_icb_cmd_valid = i_bus_icb_cmd_valid;
assign o_icb_cmd_read = i_bus_icb_cmd_read ;
assign o_icb_cmd_addr = i_bus_icb_cmd_addr ;
assign o_icb_cmd_wdata = i_bus_icb_cmd_wdata;
assign o_icb_cmd_wmask = i_bus_icb_cmd_wmask;
assign o_icb_cmd_burst = i_bus_icb_cmd_burst;
assign o_icb_cmd_beat = i_bus_icb_cmd_beat ;
assign o_icb_cmd_lock = i_bus_icb_cmd_lock ;
assign o_icb_cmd_excl = i_bus_icb_cmd_excl ;
assign o_icb_cmd_size = i_bus_icb_cmd_size ;
assign o_icb_cmd_usr = i_bus_icb_cmd_usr ;
assign o_icb_rsp_ready = i_bus_icb_rsp_ready;
assign i_bus_icb_rsp_valid = o_icb_rsp_valid ;
assign i_bus_icb_rsp_err = o_icb_rsp_err ;
assign i_bus_icb_rsp_excl_ok = o_icb_rsp_excl_ok ;
assign i_bus_icb_rsp_rdata = o_icb_rsp_rdata ;
assign i_bus_icb_rsp_usr = o_icb_rsp_usr ;
end//}
else begin:arbt_num_gt_1_gen//{
assign o_icb_cmd_valid = o_icb_cmd_valid_real & (~rspid_fifo_full);
assign o_icb_cmd_ready_real = o_icb_cmd_ready & (~rspid_fifo_full);
// Distract the icb from the bus declared ports
for(i = 0; i < ARBT_NUM; i = i+1)//{
begin:icb_distract_gen
assign i_icb_cmd_read [i] = i_bus_icb_cmd_read [(i+1)*1 -1 : i*1 ];
assign i_icb_cmd_addr [i] = i_bus_icb_cmd_addr [(i+1)*AW -1 : i*AW ];
assign i_icb_cmd_wdata[i] = i_bus_icb_cmd_wdata[(i+1)*DW -1 : i*DW ];
assign i_icb_cmd_wmask[i] = i_bus_icb_cmd_wmask[(i+1)*(DW/8)-1 : i*(DW/8)];
assign i_icb_cmd_burst[i] = i_bus_icb_cmd_burst[(i+1)*2 -1 : i*2 ];
assign i_icb_cmd_beat [i] = i_bus_icb_cmd_beat [(i+1)*2 -1 : i*2 ];
assign i_icb_cmd_lock [i] = i_bus_icb_cmd_lock [(i+1)*1 -1 : i*1 ];
assign i_icb_cmd_excl [i] = i_bus_icb_cmd_excl [(i+1)*1 -1 : i*1 ];
assign i_icb_cmd_size [i] = i_bus_icb_cmd_size [(i+1)*2 -1 : i*2 ];
assign i_icb_cmd_usr [i] = i_bus_icb_cmd_usr [(i+1)*USR_W -1 : i*USR_W ];
assign i_bus_icb_cmd_ready[i] = i_bus_icb_cmd_grt_vec[i] & o_icb_cmd_ready_real;
assign i_bus_icb_rsp_valid[i] = o_icb_rsp_valid_pre & (o_icb_rsp_port_id == i);
end//}
if(ARBT_SCHEME == 0) begin:priorty_arbt//{
wire arbt_ena = 1'b0;//No use
for(i = 0; i < ARBT_NUM; i = i+1)//{
begin:priroty_grt_vec_gen
if(i==0) begin: i_is_0
assign i_bus_icb_cmd_grt_vec[i] = 1'b1;
end
else begin:i_is_not_0
assign i_bus_icb_cmd_grt_vec[i] = ~(|i_bus_icb_cmd_valid[i-1:0]);
end
assign i_bus_icb_cmd_sel[i] = i_bus_icb_cmd_grt_vec[i] & i_bus_icb_cmd_valid[i];
end//}
end//}
if(ARBT_SCHEME == 1) begin:rrobin_arbt//{
assign arbt_ena = o_icb_cmd_valid & o_icb_cmd_ready;
sirv_gnrl_rrobin # (
.ARBT_NUM(ARBT_NUM)
)u_sirv_gnrl_rrobin(
.grt_vec (i_bus_icb_cmd_grt_vec),
.req_vec (i_bus_icb_cmd_valid),
.arbt_ena (arbt_ena),
.clk (clk),
.rst_n (rst_n)
);
assign i_bus_icb_cmd_sel = i_bus_icb_cmd_grt_vec;
end//}
always @ (*) begin : sel_o_apb_cmd_ready_PROC
sel_o_icb_cmd_read = {1 {1'b0}};
sel_o_icb_cmd_addr = {AW {1'b0}};
sel_o_icb_cmd_wdata = {DW {1'b0}};
sel_o_icb_cmd_wmask = {DW/8{1'b0}};
sel_o_icb_cmd_burst = {2 {1'b0}};
sel_o_icb_cmd_beat = {2 {1'b0}};
sel_o_icb_cmd_lock = {1 {1'b0}};
sel_o_icb_cmd_excl = {1 {1'b0}};
sel_o_icb_cmd_size = {2 {1'b0}};
sel_o_icb_cmd_usr = {USR_W{1'b0}};
for(j = 0; j < ARBT_NUM; j = j+1) begin//{
sel_o_icb_cmd_read = sel_o_icb_cmd_read | ({1 {i_bus_icb_cmd_sel[j]}} & i_icb_cmd_read [j]);
sel_o_icb_cmd_addr = sel_o_icb_cmd_addr | ({AW {i_bus_icb_cmd_sel[j]}} & i_icb_cmd_addr [j]);
sel_o_icb_cmd_wdata = sel_o_icb_cmd_wdata | ({DW {i_bus_icb_cmd_sel[j]}} & i_icb_cmd_wdata[j]);
sel_o_icb_cmd_wmask = sel_o_icb_cmd_wmask | ({DW/8 {i_bus_icb_cmd_sel[j]}} & i_icb_cmd_wmask[j]);
sel_o_icb_cmd_burst = sel_o_icb_cmd_burst | ({2 {i_bus_icb_cmd_sel[j]}} & i_icb_cmd_burst[j]);
sel_o_icb_cmd_beat = sel_o_icb_cmd_beat | ({2 {i_bus_icb_cmd_sel[j]}} & i_icb_cmd_beat [j]);
sel_o_icb_cmd_lock = sel_o_icb_cmd_lock | ({1 {i_bus_icb_cmd_sel[j]}} & i_icb_cmd_lock [j]);
sel_o_icb_cmd_excl = sel_o_icb_cmd_excl | ({1 {i_bus_icb_cmd_sel[j]}} & i_icb_cmd_excl [j]);
sel_o_icb_cmd_size = sel_o_icb_cmd_size | ({2 {i_bus_icb_cmd_sel[j]}} & i_icb_cmd_size [j]);
sel_o_icb_cmd_usr = sel_o_icb_cmd_usr | ({USR_W{i_bus_icb_cmd_sel[j]}} & i_icb_cmd_usr [j]);
end//}
end
assign o_icb_cmd_valid_real = |i_bus_icb_cmd_valid;
always @ (*) begin : i_arbt_indic_id_PROC
i_arbt_indic_id = {ARBT_PTR_W{1'b0}};
for(j = 0; j < ARBT_NUM; j = j+1) begin//{
i_arbt_indic_id = i_arbt_indic_id | {ARBT_PTR_W{i_bus_icb_cmd_sel[j]}} & $unsigned(j);
end//}
end
assign rspid_fifo_wen = o_icb_cmd_valid & o_icb_cmd_ready;
assign rspid_fifo_ren = o_icb_rsp_valid & o_icb_rsp_ready;
if(ALLOW_0CYCL_RSP == 1) begin: allow_0rsp
assign rspid_fifo_bypass = rspid_fifo_empty & rspid_fifo_wen & rspid_fifo_ren;
assign o_icb_rsp_port_id = rspid_fifo_empty ? rspid_fifo_wdat : rspid_fifo_rdat;
// We dont need this empty qualifications because we allow the 0 cyle response
assign o_icb_rsp_valid_pre = o_icb_rsp_valid;
assign o_icb_rsp_ready = o_icb_rsp_ready_pre;
end
else begin: no_allow_0rsp
assign rspid_fifo_bypass = 1'b0;
assign o_icb_rsp_port_id = rspid_fifo_empty ? {ARBT_PTR_W{1'b0}} : rspid_fifo_rdat;
assign o_icb_rsp_valid_pre = (~rspid_fifo_empty) & o_icb_rsp_valid;
assign o_icb_rsp_ready = (~rspid_fifo_empty) & o_icb_rsp_ready_pre;
end
assign rspid_fifo_i_valid = rspid_fifo_wen & (~rspid_fifo_bypass);
assign rspid_fifo_full = (~rspid_fifo_i_ready);
assign rspid_fifo_o_ready = rspid_fifo_ren & (~rspid_fifo_bypass);
assign rspid_fifo_empty = (~rspid_fifo_o_valid);
assign rspid_fifo_wdat = i_arbt_indic_id;
if(FIFO_OUTS_NUM == 1) begin:dp_1//{
sirv_gnrl_pipe_stage # (
.CUT_READY (FIFO_CUT_READY),
.DP (1),
.DW (ARBT_PTR_W)
) u_sirv_gnrl_rspid_fifo (
.i_vld(rspid_fifo_i_valid),
.i_rdy(rspid_fifo_i_ready),
.i_dat(rspid_fifo_wdat ),
.o_vld(rspid_fifo_o_valid),
.o_rdy(rspid_fifo_o_ready),
.o_dat(rspid_fifo_rdat ),
.clk (clk),
.rst_n(rst_n)
);
end//}
else begin: dp_gt1//{
sirv_gnrl_fifo # (
.CUT_READY (FIFO_CUT_READY),
.MSKO (0),
.DP (FIFO_OUTS_NUM),
.DW (ARBT_PTR_W)
) u_sirv_gnrl_rspid_fifo (
.i_vld(rspid_fifo_i_valid),
.i_rdy(rspid_fifo_i_ready),
.i_dat(rspid_fifo_wdat ),
.o_vld(rspid_fifo_o_valid),
.o_rdy(rspid_fifo_o_ready),
.o_dat(rspid_fifo_rdat ),
.clk (clk),
.rst_n(rst_n)
);
end//}
assign o_icb_cmd_read = sel_o_icb_cmd_read ;
assign o_icb_cmd_addr = sel_o_icb_cmd_addr ;
assign o_icb_cmd_wdata = sel_o_icb_cmd_wdata;
assign o_icb_cmd_wmask = sel_o_icb_cmd_wmask;
assign o_icb_cmd_burst = sel_o_icb_cmd_burst;
assign o_icb_cmd_beat = sel_o_icb_cmd_beat ;
assign o_icb_cmd_lock = sel_o_icb_cmd_lock ;
assign o_icb_cmd_excl = sel_o_icb_cmd_excl ;
assign o_icb_cmd_size = sel_o_icb_cmd_size ;
assign o_icb_cmd_usr = sel_o_icb_cmd_usr ;
assign o_icb_rsp_ready_pre = i_bus_icb_rsp_ready[o_icb_rsp_port_id];
assign i_bus_icb_rsp_err = {ARBT_NUM{o_icb_rsp_err }};
assign i_bus_icb_rsp_excl_ok = {ARBT_NUM{o_icb_rsp_excl_ok}};
assign i_bus_icb_rsp_rdata = {ARBT_NUM{o_icb_rsp_rdata}};
assign i_bus_icb_rsp_usr = {ARBT_NUM{o_icb_rsp_usr}};
end//}
endgenerate //}
endmodule
// ===========================================================================
//
// Description:
// The module to handle the ICB bus buffer stages
//
// ===========================================================================
module sirv_gnrl_icb_buffer # (
parameter OUTS_CNT_W = 1,
parameter AW = 32,
parameter DW = 32,
parameter CMD_CUT_READY = 0,
parameter RSP_CUT_READY = 0,
parameter CMD_DP = 0,
parameter RSP_DP = 0,
parameter USR_W = 1
) (
output icb_buffer_active,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [1-1:0] i_icb_cmd_read,
input [AW-1:0] i_icb_cmd_addr,
input [DW-1:0] i_icb_cmd_wdata,
input [DW/8-1:0] i_icb_cmd_wmask,
input i_icb_cmd_lock,
input i_icb_cmd_excl,
input [1:0] i_icb_cmd_size,
input [1:0] i_icb_cmd_burst,
input [1:0] i_icb_cmd_beat,
input [USR_W-1:0] i_icb_cmd_usr,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output i_icb_rsp_err,
output i_icb_rsp_excl_ok,
output [DW-1:0] i_icb_rsp_rdata,
output [USR_W-1:0] i_icb_rsp_usr,
output o_icb_cmd_valid,
input o_icb_cmd_ready,
output [1-1:0] o_icb_cmd_read,
output [AW-1:0] o_icb_cmd_addr,
output [DW-1:0] o_icb_cmd_wdata,
output [DW/8-1:0] o_icb_cmd_wmask,
output o_icb_cmd_lock,
output o_icb_cmd_excl,
output [1:0] o_icb_cmd_size,
output [1:0] o_icb_cmd_burst,
output [1:0] o_icb_cmd_beat,
output [USR_W-1:0] o_icb_cmd_usr,
input o_icb_rsp_valid,
output o_icb_rsp_ready,
input o_icb_rsp_err,
input o_icb_rsp_excl_ok,
input [DW-1:0] o_icb_rsp_rdata,
input [USR_W-1:0] o_icb_rsp_usr,
input clk,
input rst_n
);
localparam CMD_PACK_W = (1+AW+DW+(DW/8)+1+1+2+2+2+USR_W);
wire [CMD_PACK_W-1:0] cmd_fifo_i_dat = {
i_icb_cmd_read,
i_icb_cmd_addr,
i_icb_cmd_wdata,
i_icb_cmd_wmask,
i_icb_cmd_lock,
i_icb_cmd_excl,
i_icb_cmd_size,
i_icb_cmd_burst,
i_icb_cmd_beat,
i_icb_cmd_usr};
wire [CMD_PACK_W-1:0] cmd_fifo_o_dat;
assign {
o_icb_cmd_read,
o_icb_cmd_addr,
o_icb_cmd_wdata,
o_icb_cmd_wmask,
o_icb_cmd_lock,
o_icb_cmd_excl,
o_icb_cmd_size,
o_icb_cmd_burst,
o_icb_cmd_beat,
o_icb_cmd_usr} = cmd_fifo_o_dat;
sirv_gnrl_fifo # (
.CUT_READY (CMD_CUT_READY),
.MSKO (0),
.DP (CMD_DP),
.DW (CMD_PACK_W)
) u_sirv_gnrl_cmd_fifo (
.i_vld(i_icb_cmd_valid),
.i_rdy(i_icb_cmd_ready),
.i_dat(cmd_fifo_i_dat ),
.o_vld(o_icb_cmd_valid),
.o_rdy(o_icb_cmd_ready),
.o_dat(cmd_fifo_o_dat ),
.clk (clk),
.rst_n(rst_n)
);
localparam RSP_PACK_W = (2+DW+USR_W);
wire [RSP_PACK_W-1:0] rsp_fifo_i_dat = {
o_icb_rsp_err,
o_icb_rsp_excl_ok,
o_icb_rsp_rdata,
o_icb_rsp_usr};
wire [RSP_PACK_W-1:0] rsp_fifo_o_dat;
assign {
i_icb_rsp_err,
i_icb_rsp_excl_ok,
i_icb_rsp_rdata,
i_icb_rsp_usr} = rsp_fifo_o_dat;
sirv_gnrl_fifo # (
.CUT_READY (RSP_CUT_READY),
.MSKO (0),
.DP (RSP_DP),
.DW (RSP_PACK_W)
) u_sirv_gnrl_rsp_fifo (
.i_vld(o_icb_rsp_valid),
.i_rdy(o_icb_rsp_ready),
.i_dat(rsp_fifo_i_dat ),
.o_vld(i_icb_rsp_valid),
.o_rdy(i_icb_rsp_ready),
.o_dat(rsp_fifo_o_dat ),
.clk (clk),
.rst_n(rst_n)
);
wire outs_cnt_inc = i_icb_cmd_valid & i_icb_cmd_ready;
wire outs_cnt_dec = i_icb_rsp_valid & i_icb_rsp_ready;
// If meanwhile no or have set and clear, then no changes
wire outs_cnt_ena = outs_cnt_inc ^ outs_cnt_dec;
// If only inc or only dec
wire outs_cnt_r;
wire outs_cnt_nxt = outs_cnt_inc ? (outs_cnt_r + 1'b1) : (outs_cnt_r - 1'b1);
sirv_gnrl_dfflr #(OUTS_CNT_W) outs_cnt_dfflr (outs_cnt_ena, outs_cnt_nxt, outs_cnt_r, clk, rst_n);
assign icb_buffer_active = i_icb_cmd_valid | (~(outs_cnt_r == {OUTS_CNT_W{1'b0}}));
endmodule
// ===========================================================================
//
// Description:
// The module to handle the ICB bus width conversion from 32bits to 64bits
//
// ===========================================================================
module sirv_gnrl_icb_n2w # (
parameter AW = 32,
parameter USR_W = 1,
parameter FIFO_OUTS_NUM = 8,
parameter FIFO_CUT_READY = 0,
parameter X_W = 32,
parameter Y_W = 64
) (
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [1-1:0] i_icb_cmd_read,
input [AW-1:0] i_icb_cmd_addr,
input [X_W-1:0] i_icb_cmd_wdata,
input [X_W/8-1:0] i_icb_cmd_wmask,
input i_icb_cmd_lock,
input i_icb_cmd_excl,
input [1:0] i_icb_cmd_size,
input [1:0] i_icb_cmd_burst,
input [1:0] i_icb_cmd_beat,
input [USR_W-1:0] i_icb_cmd_usr,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output i_icb_rsp_err,
output i_icb_rsp_excl_ok,
output [X_W-1:0] i_icb_rsp_rdata,
output [USR_W-1:0] i_icb_rsp_usr,
output o_icb_cmd_valid,
input o_icb_cmd_ready,
output [1-1:0] o_icb_cmd_read,
output [AW-1:0] o_icb_cmd_addr,
output [Y_W-1:0] o_icb_cmd_wdata,
output [Y_W/8-1:0] o_icb_cmd_wmask,
output o_icb_cmd_lock,
output o_icb_cmd_excl,
output [1:0] o_icb_cmd_size,
output [1:0] o_icb_cmd_burst,
output [1:0] o_icb_cmd_beat,
output [USR_W-1:0] o_icb_cmd_usr,
input o_icb_rsp_valid,
output o_icb_rsp_ready,
input o_icb_rsp_err,
input o_icb_rsp_excl_ok,
input [Y_W-1:0] o_icb_rsp_rdata,
input [USR_W-1:0] o_icb_rsp_usr,
input clk,
input rst_n
);
wire cmd_y_lo_hi;
wire rsp_y_lo_hi;
wire n2w_fifo_wen = i_icb_cmd_valid & i_icb_cmd_ready;
wire n2w_fifo_ren = i_icb_rsp_valid & i_icb_rsp_ready;
wire n2w_fifo_i_ready;
wire n2w_fifo_i_valid = n2w_fifo_wen;
wire n2w_fifo_full = (~n2w_fifo_i_ready);
wire n2w_fifo_o_valid ;
wire n2w_fifo_o_ready = n2w_fifo_ren;
wire n2w_fifo_empty = (~n2w_fifo_o_valid);
generate
if(FIFO_OUTS_NUM == 1) begin:fifo_dp_1//{
sirv_gnrl_pipe_stage # (
.CUT_READY (FIFO_CUT_READY),
.DP (1),
.DW (1)
) u_sirv_gnrl_n2w_fifo (
.i_vld(n2w_fifo_i_valid),
.i_rdy(n2w_fifo_i_ready),
.i_dat(cmd_y_lo_hi ),
.o_vld(n2w_fifo_o_valid),
.o_rdy(n2w_fifo_o_ready),
.o_dat(rsp_y_lo_hi ),
.clk (clk),
.rst_n(rst_n)
);
end//}
else begin: fifo_dp_gt_1//{
sirv_gnrl_fifo # (
.CUT_READY (FIFO_CUT_READY),
.MSKO (0),
.DP (FIFO_OUTS_NUM),
.DW (1)
) u_sirv_gnrl_n2w_fifo (
.i_vld(n2w_fifo_i_valid),
.i_rdy(n2w_fifo_i_ready),
.i_dat(cmd_y_lo_hi ),
.o_vld(n2w_fifo_o_valid),
.o_rdy(n2w_fifo_o_ready),
.o_dat(rsp_y_lo_hi ),
.clk (clk),
.rst_n(rst_n)
);
end//}
endgenerate
generate
if(X_W == 32) begin: x_w_32//{
if(Y_W == 64) begin: y_w_64//{
assign cmd_y_lo_hi = i_icb_cmd_addr[2];
end//}
end//}
endgenerate
assign o_icb_cmd_valid = (~n2w_fifo_full) & i_icb_cmd_valid;
assign i_icb_cmd_ready = (~n2w_fifo_full) & o_icb_cmd_ready;
assign o_icb_cmd_read = i_icb_cmd_read ;
assign o_icb_cmd_addr = i_icb_cmd_addr ;
assign o_icb_cmd_lock = i_icb_cmd_lock ;
assign o_icb_cmd_excl = i_icb_cmd_excl ;
assign o_icb_cmd_size = i_icb_cmd_size ;
assign o_icb_cmd_burst = i_icb_cmd_burst;
assign o_icb_cmd_beat = i_icb_cmd_beat ;
assign o_icb_cmd_usr = i_icb_cmd_usr ;
assign o_icb_cmd_wdata = {i_icb_cmd_wdata,i_icb_cmd_wdata};
assign o_icb_cmd_wmask = cmd_y_lo_hi ? {i_icb_cmd_wmask, {X_W/8{1'b0}}} : { {X_W/8{1'b0}},i_icb_cmd_wmask};
assign i_icb_rsp_valid = o_icb_rsp_valid ;
assign i_icb_rsp_err = o_icb_rsp_err ;
assign i_icb_rsp_excl_ok = o_icb_rsp_excl_ok ;
assign i_icb_rsp_rdata = rsp_y_lo_hi ? o_icb_rsp_rdata[Y_W-1:X_W] : o_icb_rsp_rdata[X_W-1:0] ;
assign i_icb_rsp_usr = o_icb_rsp_usr ;
assign o_icb_rsp_ready = i_icb_rsp_ready;
endmodule
// ===========================================================================
//
// Description:
// The module to handle the ICB bus de-mux
//
// ===========================================================================
module sirv_gnrl_icb_splt # (
parameter AW = 32,
parameter DW = 64,
// The number of outstanding supported
parameter FIFO_OUTS_NUM = 8,
parameter FIFO_CUT_READY = 0,
// SPLT_NUM=4 ports, so 2 bits for port id
parameter SPLT_NUM = 4,
parameter SPLT_PTR_1HOT = 1,// Currently we always use 1HOT (i.e., this is configured as 1)
// do not try to configure it as 0, becuase we never use it and verify it
parameter SPLT_PTR_W = 4,
parameter ALLOW_DIFF = 1,
parameter ALLOW_0CYCL_RSP = 1,
parameter VLD_MSK_PAYLOAD = 0,
parameter USR_W = 1
) (
input [SPLT_NUM-1:0] i_icb_splt_indic,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [1-1:0] i_icb_cmd_read,
input [AW-1:0] i_icb_cmd_addr,
input [DW-1:0] i_icb_cmd_wdata,
input [DW/8-1:0] i_icb_cmd_wmask,
input [1:0] i_icb_cmd_burst,
input [1:0] i_icb_cmd_beat,
input i_icb_cmd_lock,
input i_icb_cmd_excl,
input [1:0] i_icb_cmd_size,
input [USR_W-1:0]i_icb_cmd_usr,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output i_icb_rsp_err,
output i_icb_rsp_excl_ok,
output [DW-1:0] i_icb_rsp_rdata,
output [USR_W-1:0] i_icb_rsp_usr,
input [SPLT_NUM*1-1:0] o_bus_icb_cmd_ready,
output [SPLT_NUM*1-1:0] o_bus_icb_cmd_valid,
output [SPLT_NUM*1-1:0] o_bus_icb_cmd_read,
output [SPLT_NUM*AW-1:0] o_bus_icb_cmd_addr,
output [SPLT_NUM*DW-1:0] o_bus_icb_cmd_wdata,
output [SPLT_NUM*DW/8-1:0] o_bus_icb_cmd_wmask,
output [SPLT_NUM*2-1:0] o_bus_icb_cmd_burst,
output [SPLT_NUM*2-1:0] o_bus_icb_cmd_beat,
output [SPLT_NUM*1-1:0] o_bus_icb_cmd_lock,
output [SPLT_NUM*1-1:0] o_bus_icb_cmd_excl,
output [SPLT_NUM*2-1:0] o_bus_icb_cmd_size,
output [SPLT_NUM*USR_W-1:0]o_bus_icb_cmd_usr,
input [SPLT_NUM*1-1:0] o_bus_icb_rsp_valid,
output [SPLT_NUM*1-1:0] o_bus_icb_rsp_ready,
input [SPLT_NUM*1-1:0] o_bus_icb_rsp_err,
input [SPLT_NUM*1-1:0] o_bus_icb_rsp_excl_ok,
input [SPLT_NUM*DW-1:0] o_bus_icb_rsp_rdata,
input [SPLT_NUM*USR_W-1:0] o_bus_icb_rsp_usr,
input clk,
input rst_n
);
integer j;
wire [SPLT_NUM-1:0] o_icb_cmd_valid;
wire [SPLT_NUM-1:0] o_icb_cmd_ready;
wire [1-1:0] o_icb_cmd_read [SPLT_NUM-1:0];
wire [AW-1:0] o_icb_cmd_addr [SPLT_NUM-1:0];
wire [DW-1:0] o_icb_cmd_wdata[SPLT_NUM-1:0];
wire [DW/8-1:0] o_icb_cmd_wmask[SPLT_NUM-1:0];
wire [1:0] o_icb_cmd_burst[SPLT_NUM-1:0];
wire [1:0] o_icb_cmd_beat [SPLT_NUM-1:0];
wire o_icb_cmd_lock [SPLT_NUM-1:0];
wire o_icb_cmd_excl [SPLT_NUM-1:0];
wire [1:0] o_icb_cmd_size [SPLT_NUM-1:0];
wire [USR_W-1:0]o_icb_cmd_usr [SPLT_NUM-1:0];
wire [SPLT_NUM-1:0] o_icb_rsp_valid;
wire [SPLT_NUM-1:0] o_icb_rsp_ready;
wire [SPLT_NUM-1:0] o_icb_rsp_err ;
wire [SPLT_NUM-1:0] o_icb_rsp_excl_ok ;
wire [DW-1:0] o_icb_rsp_rdata [SPLT_NUM-1:0];
wire [USR_W-1:0] o_icb_rsp_usr [SPLT_NUM-1:0];
reg sel_o_apb_cmd_ready;
wire rspid_fifo_bypass;
wire rspid_fifo_wen;
wire rspid_fifo_ren;
wire [SPLT_PTR_W-1:0] o_icb_rsp_port_id;
wire rspid_fifo_i_valid;
wire rspid_fifo_o_valid;
wire rspid_fifo_i_ready;
wire rspid_fifo_o_ready;
wire [SPLT_PTR_W-1:0] rspid_fifo_rdat;
wire [SPLT_PTR_W-1:0] rspid_fifo_wdat;
wire rspid_fifo_full;
wire rspid_fifo_empty;
reg [SPLT_PTR_W-1:0] i_splt_indic_id;
wire i_icb_cmd_ready_pre;
wire i_icb_cmd_valid_pre;
wire i_icb_rsp_ready_pre;
wire i_icb_rsp_valid_pre;
genvar i;
generate //{
if(SPLT_NUM == 1) begin:splt_num_eq_1_gen// {
assign i_icb_cmd_ready = o_bus_icb_cmd_ready;
assign o_bus_icb_cmd_valid = i_icb_cmd_valid;
assign o_bus_icb_cmd_read = i_icb_cmd_read ;
assign o_bus_icb_cmd_addr = i_icb_cmd_addr ;
assign o_bus_icb_cmd_wdata = i_icb_cmd_wdata;
assign o_bus_icb_cmd_wmask = i_icb_cmd_wmask;
assign o_bus_icb_cmd_burst = i_icb_cmd_burst;
assign o_bus_icb_cmd_beat = i_icb_cmd_beat ;
assign o_bus_icb_cmd_lock = i_icb_cmd_lock ;
assign o_bus_icb_cmd_excl = i_icb_cmd_excl ;
assign o_bus_icb_cmd_size = i_icb_cmd_size ;
assign o_bus_icb_cmd_usr = i_icb_cmd_usr ;
assign o_bus_icb_rsp_ready = i_icb_rsp_ready;
assign i_icb_rsp_valid = o_bus_icb_rsp_valid;
assign i_icb_rsp_err = o_bus_icb_rsp_err ;
assign i_icb_rsp_excl_ok = o_bus_icb_rsp_excl_ok ;
assign i_icb_rsp_rdata = o_bus_icb_rsp_rdata;
assign i_icb_rsp_usr = o_bus_icb_rsp_usr;
end//}
else begin:splt_num_gt_1_gen//{
for(i = 0; i < SPLT_NUM; i = i+1)//{
begin:icb_distract_gen
assign o_icb_cmd_ready[i] = o_bus_icb_cmd_ready[(i+1)*1 -1 : (i)*1 ];
assign o_bus_icb_cmd_valid[(i+1)*1 -1 : i*1 ] = o_icb_cmd_valid[i];
assign o_bus_icb_cmd_read [(i+1)*1 -1 : i*1 ] = o_icb_cmd_read [i];
assign o_bus_icb_cmd_addr [(i+1)*AW -1 : i*AW ] = o_icb_cmd_addr [i];
assign o_bus_icb_cmd_wdata[(i+1)*DW -1 : i*DW ] = o_icb_cmd_wdata[i];
assign o_bus_icb_cmd_wmask[(i+1)*(DW/8)-1 : i*(DW/8)] = o_icb_cmd_wmask[i];
assign o_bus_icb_cmd_burst[(i+1)*2 -1 : i*2 ] = o_icb_cmd_burst[i];
assign o_bus_icb_cmd_beat [(i+1)*2 -1 : i*2 ] = o_icb_cmd_beat [i];
assign o_bus_icb_cmd_lock [(i+1)*1 -1 : i*1 ] = o_icb_cmd_lock [i];
assign o_bus_icb_cmd_excl [(i+1)*1 -1 : i*1 ] = o_icb_cmd_excl [i];
assign o_bus_icb_cmd_size [(i+1)*2 -1 : i*2 ] = o_icb_cmd_size [i];
assign o_bus_icb_cmd_usr [(i+1)*USR_W -1 : i*USR_W ] = o_icb_cmd_usr [i];
assign o_bus_icb_rsp_ready[(i+1)*1-1 :i*1 ] = o_icb_rsp_ready[i];
assign o_icb_rsp_valid[i] = o_bus_icb_rsp_valid[(i+1)*1-1 :i*1 ];
assign o_icb_rsp_err [i] = o_bus_icb_rsp_err [(i+1)*1-1 :i*1 ];
assign o_icb_rsp_excl_ok [i] = o_bus_icb_rsp_excl_ok [(i+1)*1-1 :i*1 ];
assign o_icb_rsp_rdata[i] = o_bus_icb_rsp_rdata[(i+1)*DW-1:i*DW];
assign o_icb_rsp_usr [i] = o_bus_icb_rsp_usr [(i+1)*USR_W-1:i*USR_W];
end//}
///////////////////////
// Input ICB will be accepted when
// (*) The targeted icb have "ready" asserted
// (*) The FIFO is not full
always @ (*) begin : sel_o_apb_cmd_ready_PROC
sel_o_apb_cmd_ready = 1'b0;
for(j = 0; j < SPLT_NUM; j = j+1) begin//{
sel_o_apb_cmd_ready = sel_o_apb_cmd_ready | (i_icb_splt_indic[j] & o_icb_cmd_ready[j]);
end//}
end
assign i_icb_cmd_ready_pre = sel_o_apb_cmd_ready;
if(ALLOW_DIFF == 1) begin:allow_diff// {
assign i_icb_cmd_valid_pre = i_icb_cmd_valid & (~rspid_fifo_full);
assign i_icb_cmd_ready = i_icb_cmd_ready_pre & (~rspid_fifo_full);
end
else begin:not_allow_diff
// The next transaction can only be issued if there is no any outstanding
// transactions to different targets
wire cmd_diff_branch = (~rspid_fifo_empty) & (~(rspid_fifo_wdat == rspid_fifo_rdat));
assign i_icb_cmd_valid_pre = i_icb_cmd_valid & (~cmd_diff_branch) & (~rspid_fifo_full);
assign i_icb_cmd_ready = i_icb_cmd_ready_pre & (~cmd_diff_branch) & (~rspid_fifo_full);
end
if(SPLT_PTR_1HOT == 1) begin:ptr_1hot// {
always @ (*) begin : i_splt_indic_id_PROC
i_splt_indic_id = i_icb_splt_indic;
end
end
else begin:ptr_not_1hot//}{
always @ (*) begin : i_splt_indic_id_PROC
i_splt_indic_id = {SPLT_PTR_W{1'b0}};
for(j = 0; j < SPLT_NUM; j = j+1) begin//{
i_splt_indic_id = i_splt_indic_id | ({SPLT_PTR_W{i_icb_splt_indic[j]}} & $unsigned(j));
end//}
end
end//}
assign rspid_fifo_wen = i_icb_cmd_valid & i_icb_cmd_ready;
assign rspid_fifo_ren = i_icb_rsp_valid & i_icb_rsp_ready;
if(ALLOW_0CYCL_RSP == 1) begin: allow_0rsp
assign rspid_fifo_bypass = rspid_fifo_empty & rspid_fifo_wen & rspid_fifo_ren;
assign o_icb_rsp_port_id = rspid_fifo_empty ? rspid_fifo_wdat : rspid_fifo_rdat;
// We dont need this empty qualifications because we allow the 0 cyle response
assign i_icb_rsp_valid = i_icb_rsp_valid_pre;
assign i_icb_rsp_ready_pre = i_icb_rsp_ready;
end
else begin: no_allow_0rsp
assign rspid_fifo_bypass = 1'b0;
assign o_icb_rsp_port_id = rspid_fifo_empty ? {SPLT_PTR_W{1'b0}} : rspid_fifo_rdat;
assign i_icb_rsp_valid = (~rspid_fifo_empty) & i_icb_rsp_valid_pre;
assign i_icb_rsp_ready_pre = (~rspid_fifo_empty) & i_icb_rsp_ready;
end
assign rspid_fifo_i_valid = rspid_fifo_wen & (~rspid_fifo_bypass);
assign rspid_fifo_full = (~rspid_fifo_i_ready);
assign rspid_fifo_o_ready = rspid_fifo_ren & (~rspid_fifo_bypass);
assign rspid_fifo_empty = (~rspid_fifo_o_valid);
assign rspid_fifo_wdat = i_splt_indic_id;
if(FIFO_OUTS_NUM == 1) begin:fifo_dp_1//{
sirv_gnrl_pipe_stage # (
.CUT_READY (FIFO_CUT_READY),
.DP (1),
.DW (SPLT_PTR_W)
) u_sirv_gnrl_rspid_fifo (
.i_vld(rspid_fifo_i_valid),
.i_rdy(rspid_fifo_i_ready),
.i_dat(rspid_fifo_wdat ),
.o_vld(rspid_fifo_o_valid),
.o_rdy(rspid_fifo_o_ready),
.o_dat(rspid_fifo_rdat ),
.clk (clk),
.rst_n(rst_n)
);
end//}
else begin: fifo_dp_gt_1//{
sirv_gnrl_fifo # (
.CUT_READY (FIFO_CUT_READY),
.MSKO (0),
.DP (FIFO_OUTS_NUM),
.DW (SPLT_PTR_W)
) u_sirv_gnrl_rspid_fifo (
.i_vld(rspid_fifo_i_valid),
.i_rdy(rspid_fifo_i_ready),
.i_dat(rspid_fifo_wdat ),
.o_vld(rspid_fifo_o_valid),
.o_rdy(rspid_fifo_o_ready),
.o_dat(rspid_fifo_rdat ),
.clk (clk),
.rst_n(rst_n)
);
end//}
///////////////////////
//
for(i = 0; i < SPLT_NUM; i = i+1)//{
begin:o_icb_cmd_valid_gen
assign o_icb_cmd_valid[i] = i_icb_splt_indic[i] & i_icb_cmd_valid_pre;
if(VLD_MSK_PAYLOAD == 0) begin: no_vld_msk_payload
assign o_icb_cmd_read [i] = i_icb_cmd_read ;
assign o_icb_cmd_addr [i] = i_icb_cmd_addr ;
assign o_icb_cmd_wdata[i] = i_icb_cmd_wdata;
assign o_icb_cmd_wmask[i] = i_icb_cmd_wmask;
assign o_icb_cmd_burst[i] = i_icb_cmd_burst;
assign o_icb_cmd_beat [i] = i_icb_cmd_beat ;
assign o_icb_cmd_lock [i] = i_icb_cmd_lock ;
assign o_icb_cmd_excl [i] = i_icb_cmd_excl ;
assign o_icb_cmd_size [i] = i_icb_cmd_size ;
assign o_icb_cmd_usr [i] = i_icb_cmd_usr ;
end
else begin: vld_msk_payload
assign o_icb_cmd_read [i] = {1 {o_icb_cmd_valid[i]}} & i_icb_cmd_read ;
assign o_icb_cmd_addr [i] = {AW {o_icb_cmd_valid[i]}} & i_icb_cmd_addr ;
assign o_icb_cmd_wdata[i] = {DW {o_icb_cmd_valid[i]}} & i_icb_cmd_wdata;
assign o_icb_cmd_wmask[i] = {DW/8 {o_icb_cmd_valid[i]}} & i_icb_cmd_wmask;
assign o_icb_cmd_burst[i] = {2 {o_icb_cmd_valid[i]}} & i_icb_cmd_burst;
assign o_icb_cmd_beat [i] = {2 {o_icb_cmd_valid[i]}} & i_icb_cmd_beat ;
assign o_icb_cmd_lock [i] = {1 {o_icb_cmd_valid[i]}} & i_icb_cmd_lock ;
assign o_icb_cmd_excl [i] = {1 {o_icb_cmd_valid[i]}} & i_icb_cmd_excl ;
assign o_icb_cmd_size [i] = {2 {o_icb_cmd_valid[i]}} & i_icb_cmd_size ;
assign o_icb_cmd_usr [i] = {USR_W{o_icb_cmd_valid[i]}} & i_icb_cmd_usr ;
end
end//}
//
///////////////////////
//
//
if(SPLT_PTR_1HOT == 1) begin:ptr_1hot_rsp// {
for(i = 0; i < SPLT_NUM; i = i+1)//{
begin:o_icb_rsp_ready_gen
assign o_icb_rsp_ready[i] = (o_icb_rsp_port_id[i] & i_icb_rsp_ready_pre);
end//}
//
assign i_icb_rsp_valid_pre = |(o_icb_rsp_valid & o_icb_rsp_port_id);
reg sel_i_icb_rsp_err;
reg sel_i_icb_rsp_excl_ok;
reg [DW-1:0] sel_i_icb_rsp_rdata;
reg [USR_W-1:0] sel_i_icb_rsp_usr;
always @ (*) begin : sel_icb_rsp_PROC
sel_i_icb_rsp_err = 1'b0;
sel_i_icb_rsp_excl_ok = 1'b0;
sel_i_icb_rsp_rdata = {DW {1'b0}};
sel_i_icb_rsp_usr = {USR_W{1'b0}};
for(j = 0; j < SPLT_NUM; j = j+1) begin//{
sel_i_icb_rsp_err = sel_i_icb_rsp_err | ( o_icb_rsp_port_id[j] & o_icb_rsp_err[j]);
sel_i_icb_rsp_excl_ok = sel_i_icb_rsp_excl_ok | ( o_icb_rsp_port_id[j] & o_icb_rsp_excl_ok[j]);
sel_i_icb_rsp_rdata = sel_i_icb_rsp_rdata | ({DW {o_icb_rsp_port_id[j]}} & o_icb_rsp_rdata[j]);
sel_i_icb_rsp_usr = sel_i_icb_rsp_usr | ({USR_W{o_icb_rsp_port_id[j]}} & o_icb_rsp_usr[j]);
end//}
end
assign i_icb_rsp_err = sel_i_icb_rsp_err ;
assign i_icb_rsp_excl_ok = sel_i_icb_rsp_excl_ok ;
assign i_icb_rsp_rdata = sel_i_icb_rsp_rdata;
assign i_icb_rsp_usr = sel_i_icb_rsp_usr ;
end
else begin:ptr_not_1hot_rsp//}{
for(i = 0; i < SPLT_NUM; i = i+1)//{
begin:o_icb_rsp_ready_gen
assign o_icb_rsp_ready[i] = (o_icb_rsp_port_id == i) & i_icb_rsp_ready_pre;
end//}
//
assign i_icb_rsp_valid_pre = o_icb_rsp_valid[o_icb_rsp_port_id];
assign i_icb_rsp_err = o_icb_rsp_err [o_icb_rsp_port_id];
assign i_icb_rsp_excl_ok = o_icb_rsp_excl_ok[o_icb_rsp_port_id];
assign i_icb_rsp_rdata = o_icb_rsp_rdata [o_icb_rsp_port_id];
assign i_icb_rsp_usr = o_icb_rsp_usr [o_icb_rsp_port_id];
end//}
end//}
endgenerate //}
endmodule
// ===========================================================================
//
// Description:
// The module to handle the simple-ICB bus to AXI bus conversion
//
// ===========================================================================
module sirv_gnrl_icb2axi # (
parameter AXI_FIFO_DP = 0, // This is to optionally add the pipeline stage for AXI bus
// if the depth is 0, then means pass through, not add pipeline
// if the depth is 2, then means added one ping-pong buffer stage
parameter AXI_FIFO_CUT_READY = 1, // This is to cut the back-pressure signal if you set as 1
parameter AW = 32,
parameter FIFO_OUTS_NUM = 8,
parameter FIFO_CUT_READY = 0,
parameter DW = 64 // 64 or 32 bits
) (
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [1-1:0] i_icb_cmd_read,
input [AW-1:0] i_icb_cmd_addr,
input [DW-1:0] i_icb_cmd_wdata,
input [DW/8-1:0] i_icb_cmd_wmask,
input [1:0] i_icb_cmd_size,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output i_icb_rsp_err,
output [DW-1:0] i_icb_rsp_rdata,
output o_axi_arvalid,
input o_axi_arready,
output [AW-1:0] o_axi_araddr,
output [3:0] o_axi_arcache,
output [2:0] o_axi_arprot,
output [1:0] o_axi_arlock,
output [1:0] o_axi_arburst,
output [3:0] o_axi_arlen,
output [2:0] o_axi_arsize,
output o_axi_awvalid,
input o_axi_awready,
output [AW-1:0] o_axi_awaddr,
output [3:0] o_axi_awcache,
output [2:0] o_axi_awprot,
output [1:0] o_axi_awlock,
output [1:0] o_axi_awburst,
output [3:0] o_axi_awlen,
output [2:0] o_axi_awsize,
input o_axi_rvalid,
output o_axi_rready,
input [DW-1:0] o_axi_rdata,
input [1:0] o_axi_rresp,
input o_axi_rlast,
output o_axi_wvalid,
input o_axi_wready,
output [DW-1:0] o_axi_wdata,
output [(DW/8)-1:0] o_axi_wstrb,
output o_axi_wlast,
input o_axi_bvalid,
output o_axi_bready,
input [1:0] o_axi_bresp,
input clk,
input rst_n
);
wire i_axi_arvalid;
wire i_axi_arready;
wire [AW-1:0] i_axi_araddr;
wire [3:0] i_axi_arcache;
wire [2:0] i_axi_arprot;
wire [1:0] i_axi_arlock;
wire [1:0] i_axi_arburst;
wire [3:0] i_axi_arlen;
wire [2:0] i_axi_arsize;
wire i_axi_awvalid;
wire i_axi_awready;
wire [AW-1:0] i_axi_awaddr;
wire [3:0] i_axi_awcache;
wire [2:0] i_axi_awprot;
wire [1:0] i_axi_awlock;
wire [1:0] i_axi_awburst;
wire [3:0] i_axi_awlen;
wire [2:0] i_axi_awsize;
wire i_axi_rvalid;
wire i_axi_rready;
wire [DW-1:0] i_axi_rdata;
wire [1:0] i_axi_rresp;
wire i_axi_rlast;
wire i_axi_wvalid;
wire i_axi_wready;
wire [DW-1:0] i_axi_wdata;
wire [(DW/8)-1:0] i_axi_wstrb;
wire i_axi_wlast;
wire i_axi_bvalid;
wire i_axi_bready;
wire [1:0] i_axi_bresp;
//////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////
// Convert the ICB to AXI Read/Write address and Wdata channel
//
// Generate the AXI address channel valid which is direct got
// from ICB command channel
assign i_axi_arvalid = i_icb_cmd_valid & i_icb_cmd_read;
// If it is the read transaction, need to pass to AR channel only
// If it is the write transaction, need to pass to AW and W channel both
// But in all case, need to check FIFO is not ful
wire rw_fifo_full;
assign i_icb_cmd_ready = (~rw_fifo_full) &
(i_icb_cmd_read ? i_axi_arready : (i_axi_awready & i_axi_wready));
assign i_axi_awvalid = i_icb_cmd_valid & (~i_icb_cmd_read) & i_axi_wready & (~rw_fifo_full);
assign i_axi_wvalid = i_icb_cmd_valid & (~i_icb_cmd_read) & i_axi_awready & (~rw_fifo_full);
//
// Generate the AXI address channel address which is direct got
// from ICB command channel
assign i_axi_araddr = i_icb_cmd_addr;
assign i_axi_awaddr = i_icb_cmd_addr;
//
// For these attribute signals we just make it tied to zero
assign i_axi_arcache = 4'b0;
assign i_axi_awcache = 4'b0;
assign i_axi_arprot = 3'b0;
assign i_axi_awprot = 3'b0;
assign i_axi_arlock = 2'b0;
assign i_axi_awlock = 2'b0;
//
// The ICB does not support burst now, so just make it fixed
assign i_axi_arburst = 2'b0;
assign i_axi_awburst = 2'b0;
assign i_axi_arlen = 4'b0;
assign i_axi_awlen = 4'b0;
generate
if(DW==32) begin:dw_32
assign i_axi_arsize = 3'b10;
assign i_axi_awsize = 3'b10;
end
if(DW==64) begin:dw_64
assign i_axi_arsize = 3'b11;
assign i_axi_awsize = 3'b11;
end
endgenerate
// Generate the Write data channel
assign i_axi_wdata = i_icb_cmd_wdata;
assign i_axi_wstrb = i_icb_cmd_wmask;
assign i_axi_wlast = 1'b1;
wire rw_fifo_wen = i_icb_cmd_valid & i_icb_cmd_ready;
wire rw_fifo_ren = i_icb_rsp_valid & i_icb_rsp_ready;
wire rw_fifo_i_ready;
wire rw_fifo_i_valid = rw_fifo_wen;
wire rw_fifo_o_valid ;
wire rw_fifo_o_ready = rw_fifo_ren;
assign rw_fifo_full = (~rw_fifo_i_ready);
wire rw_fifo_empty = (~rw_fifo_o_valid);
wire i_icb_rsp_read;
sirv_gnrl_fifo # (
.CUT_READY (FIFO_CUT_READY),
.MSKO (1),
.DP (FIFO_OUTS_NUM),
.DW (1)
) u_sirv_gnrl_rw_fifo (
.i_vld(rw_fifo_i_valid),
.i_rdy(rw_fifo_i_ready),
.i_dat(i_icb_cmd_read ),
.o_vld(rw_fifo_o_valid),
.o_rdy(rw_fifo_o_ready),
.o_dat(i_icb_rsp_read ),
.clk (clk),
.rst_n(rst_n)
);
//////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////
// Generate the response channel
assign i_icb_rsp_valid = i_icb_rsp_read ? i_axi_rvalid : i_axi_bvalid;
assign i_axi_rready = i_icb_rsp_read & i_icb_rsp_ready;
assign i_axi_bready = (~i_icb_rsp_read) & i_icb_rsp_ready;
assign i_icb_rsp_err = i_icb_rsp_read ? i_axi_rresp[1] //SLVERR or DECERR
: i_axi_bresp[1];
assign i_icb_rsp_rdata = i_icb_rsp_read ? i_axi_rdata : {DW{1'b0}};
sirv_gnrl_axi_buffer #(
.CHNL_FIFO_DP (AXI_FIFO_DP ),
.CHNL_FIFO_CUT_READY (AXI_FIFO_CUT_READY),
.AW (AW),
.DW (DW)
) u_sirv_gnrl_axi_buffer (
.i_axi_arvalid (i_axi_arvalid),
.i_axi_arready (i_axi_arready),
.i_axi_araddr (i_axi_araddr ),
.i_axi_arcache (i_axi_arcache),
.i_axi_arprot (i_axi_arprot ),
.i_axi_arlock (i_axi_arlock ),
.i_axi_arburst (i_axi_arburst),
.i_axi_arlen (i_axi_arlen ),
.i_axi_arsize (i_axi_arsize ),
.i_axi_awvalid (i_axi_awvalid),
.i_axi_awready (i_axi_awready),
.i_axi_awaddr (i_axi_awaddr ),
.i_axi_awcache (i_axi_awcache),
.i_axi_awprot (i_axi_awprot ),
.i_axi_awlock (i_axi_awlock ),
.i_axi_awburst (i_axi_awburst),
.i_axi_awlen (i_axi_awlen ),
.i_axi_awsize (i_axi_awsize ),
.i_axi_rvalid (i_axi_rvalid ),
.i_axi_rready (i_axi_rready ),
.i_axi_rdata (i_axi_rdata ),
.i_axi_rresp (i_axi_rresp ),
.i_axi_rlast (i_axi_rlast ),
.i_axi_wvalid (i_axi_wvalid ),
.i_axi_wready (i_axi_wready ),
.i_axi_wdata (i_axi_wdata ),
.i_axi_wstrb (i_axi_wstrb ),
.i_axi_wlast (i_axi_wlast ),
.i_axi_bvalid (i_axi_bvalid ),
.i_axi_bready (i_axi_bready ),
.i_axi_bresp (i_axi_bresp ),
.o_axi_arvalid (o_axi_arvalid),
.o_axi_arready (o_axi_arready),
.o_axi_araddr (o_axi_araddr ),
.o_axi_arcache (o_axi_arcache),
.o_axi_arprot (o_axi_arprot ),
.o_axi_arlock (o_axi_arlock ),
.o_axi_arburst (o_axi_arburst),
.o_axi_arlen (o_axi_arlen ),
.o_axi_arsize (o_axi_arsize ),
.o_axi_awvalid (o_axi_awvalid),
.o_axi_awready (o_axi_awready),
.o_axi_awaddr (o_axi_awaddr ),
.o_axi_awcache (o_axi_awcache),
.o_axi_awprot (o_axi_awprot ),
.o_axi_awlock (o_axi_awlock ),
.o_axi_awburst (o_axi_awburst),
.o_axi_awlen (o_axi_awlen ),
.o_axi_awsize (o_axi_awsize ),
.o_axi_rvalid (o_axi_rvalid ),
.o_axi_rready (o_axi_rready ),
.o_axi_rdata (o_axi_rdata ),
.o_axi_rresp (o_axi_rresp ),
.o_axi_rlast (o_axi_rlast ),
.o_axi_wvalid (o_axi_wvalid ),
.o_axi_wready (o_axi_wready ),
.o_axi_wdata (o_axi_wdata ),
.o_axi_wstrb (o_axi_wstrb ),
.o_axi_wlast (o_axi_wlast ),
.o_axi_bvalid (o_axi_bvalid ),
.o_axi_bready (o_axi_bready ),
.o_axi_bresp (o_axi_bresp ),
.clk (clk),
.rst_n(rst_n)
);
endmodule
// ===========================================================================
//
// Description:
// The module to handle the simple-ICB bus to Wishbone bus conversion
// Note: in order to support the open source I2C IP, which is 8 bits
// wide bus and byte-addresable, so here this module is just ICB to
// wishbone 8-bits bus conversion
//
// ===========================================================================
module sirv_gnrl_icb32towishb8 # (
parameter AW = 32
) (
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [1-1:0] i_icb_cmd_read,
input [AW-1:0] i_icb_cmd_addr,
input [32-1:0] i_icb_cmd_wdata,
input [32/8-1:0] i_icb_cmd_wmask,
input [1:0] i_icb_cmd_size,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output i_icb_rsp_err,
output [32-1:0] i_icb_rsp_rdata,
// The 8bits wishbone slave (e.g., I2C) must be accessed by load/store byte instructions
output [AW-1:0] wb_adr, // lower address bits
output [8-1:0] wb_dat_w, // databus input
input [8-1:0] wb_dat_r, // databus output
output wb_we, // write enable input
output wb_stb, // stobe/core select signal
output wb_cyc, // valid bus cycle input
input wb_ack, // bus cycle acknowledge output
input clk,
input rst_n
);
assign wb_adr = i_icb_cmd_addr;
assign wb_we = ~i_icb_cmd_read;
// The 32bits bus to 8bits bus remapping
assign wb_dat_w =
i_icb_cmd_wmask[3] ? i_icb_cmd_wdata[31:24] :
i_icb_cmd_wmask[2] ? i_icb_cmd_wdata[23:16] :
i_icb_cmd_wmask[1] ? i_icb_cmd_wdata[15:8] :
i_icb_cmd_wmask[0] ? i_icb_cmd_wdata[7:0] :
8'b0;
wire [32-1:0] wb_dat_r_remap =
{24'b0,wb_dat_r} << {i_icb_cmd_addr[1:0],3'b0};
// Since the Wishbone reponse channel does not have handhake scheme, but the
// ICB have, so the response may not be accepted by the upstream master
// So in order to make sure the functionality is correct, we must put
// a reponse bypass-buffer here, to always be able to accept response from wishbone
//
sirv_gnrl_fifo # (
.CUT_READY (1),
.MSKO (0),
.DP(1),
.DW(32)
) u_rsp_fifo(
.i_vld(wb_ack),
.i_rdy(),
.i_dat(wb_dat_r_remap),
.o_vld(i_icb_rsp_valid),
.o_rdy(i_icb_rsp_ready),
.o_dat(i_icb_rsp_rdata),
.clk (clk ),
.rst_n(rst_n)
);
// We only initiate the reqeust when the response buffer is empty, to make
// sure when the response back from wishbone we can alway be able to
// accept it
assign wb_stb = (~i_icb_rsp_valid) & i_icb_cmd_valid;
assign wb_cyc = (~i_icb_rsp_valid) & i_icb_cmd_valid;
assign i_icb_cmd_ready = (~i_icb_rsp_valid) & wb_ack;
assign i_icb_rsp_err = 1'b0;// Wishbone have no error response
endmodule
// ===========================================================================
//
// Description:
// The module to handle the simple-ICB bus to APB bus conversion
//
// ===========================================================================
module sirv_gnrl_icb2apb # (
parameter AW = 32,
parameter FIFO_OUTS_NUM = 8,
parameter FIFO_CUT_READY = 0,
parameter DW = 64 // 64 or 32 bits
) (
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [1-1:0] i_icb_cmd_read,
input [AW-1:0] i_icb_cmd_addr,
input [DW-1:0] i_icb_cmd_wdata,
input [DW/8-1:0] i_icb_cmd_wmask,
input [1:0] i_icb_cmd_size,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output i_icb_rsp_err,
output [DW-1:0] i_icb_rsp_rdata,
output [AW-1:0] apb_paddr,
output apb_pwrite,
output apb_pselx,
output apb_penable,
output [DW-1:0] apb_pwdata,
input [DW-1:0] apb_prdata,
input clk,
input rst_n
);
// Since the APB reponse channel does not have handhake scheme, but the
// ICB have, so the response may not be accepted by the upstream master
// So in order to make sure the functionality is correct, we must put
// a reponse bypass-buffer here, to always be able to accept response from apb
//
wire apb_enable_r;
sirv_gnrl_fifo # (
.CUT_READY (1),
.MSKO (0),
.DP(1),
.DW(DW)
) u_rsp_fifo(
.i_vld(apb_enable_r),
.i_rdy(),
.i_dat(apb_prdata),
.o_vld(i_icb_rsp_valid),
.o_rdy(i_icb_rsp_ready),
.o_dat(i_icb_rsp_rdata),
.clk (clk ),
.rst_n(rst_n)
);
assign i_icb_rsp_err = 1'b0;// Wishbone have no error response
// apb enable will be set if it is now not set and the new icb valid is coming
// And we only initiate the reqeust when the response buffer is empty, to make
// sure when the response back from APB we can alway be able to
wire apb_enable_set = (~apb_enable_r) & i_icb_cmd_valid & (~i_icb_rsp_valid);
// apb enable will be clear if it is now already set
wire apb_enable_clr = apb_enable_r;
wire apb_enable_ena = apb_enable_set | apb_enable_clr;
wire apb_enable_nxt = apb_enable_set & (~apb_enable_clr);
sirv_gnrl_dfflr #(1) apb_enable_dfflr (apb_enable_ena, apb_enable_nxt, apb_enable_r, clk, rst_n);
assign i_icb_cmd_ready = apb_enable_r & (~i_icb_rsp_valid);
assign apb_paddr = i_icb_cmd_addr;
assign apb_pwrite = (~i_icb_cmd_read);
assign apb_pselx = i_icb_cmd_valid;
assign apb_penable= apb_enable_r;
assign apb_pwdata = i_icb_cmd_wdata;
endmodule
// ===========================================================================
//
// Description:
// Verilog module for the AXI bus pipeline stage
//
// ===========================================================================
module sirv_gnrl_axi_buffer
#(
parameter CHNL_FIFO_DP = 2,
parameter CHNL_FIFO_CUT_READY = 2,
parameter AW = 32,
parameter DW = 32
)
(
input i_axi_arvalid,
output i_axi_arready,
input [AW-1:0] i_axi_araddr,
input [3:0] i_axi_arcache,
input [2:0] i_axi_arprot,
input [1:0] i_axi_arlock,
input [1:0] i_axi_arburst,
input [3:0] i_axi_arlen,
input [2:0] i_axi_arsize,
input i_axi_awvalid,
output i_axi_awready,
input [AW-1:0] i_axi_awaddr,
input [3:0] i_axi_awcache,
input [2:0] i_axi_awprot,
input [1:0] i_axi_awlock,
input [1:0] i_axi_awburst,
input [3:0] i_axi_awlen,
input [2:0] i_axi_awsize,
output i_axi_rvalid,
input i_axi_rready,
output [DW-1:0] i_axi_rdata,
output [1:0] i_axi_rresp,
output i_axi_rlast,
input i_axi_wvalid,
output i_axi_wready,
input [DW-1:0] i_axi_wdata,
input [(DW/8)-1:0] i_axi_wstrb,
input i_axi_wlast,
output i_axi_bvalid,
input i_axi_bready,
output [1:0] i_axi_bresp,
output o_axi_arvalid,
input o_axi_arready,
output [AW-1:0] o_axi_araddr,
output [3:0] o_axi_arcache,
output [2:0] o_axi_arprot,
output [1:0] o_axi_arlock,
output [1:0] o_axi_arburst,
output [3:0] o_axi_arlen,
output [2:0] o_axi_arsize,
output o_axi_awvalid,
input o_axi_awready,
output [AW-1:0] o_axi_awaddr,
output [3:0] o_axi_awcache,
output [2:0] o_axi_awprot,
output [1:0] o_axi_awlock,
output [1:0] o_axi_awburst,
output [3:0] o_axi_awlen,
output [2:0] o_axi_awsize,
input o_axi_rvalid,
output o_axi_rready,
input [DW-1:0] o_axi_rdata,
input [1:0] o_axi_rresp,
input o_axi_rlast,
output o_axi_wvalid,
input o_axi_wready,
output [DW-1:0] o_axi_wdata,
output [(DW/8)-1:0] o_axi_wstrb,
output o_axi_wlast,
input o_axi_bvalid,
output o_axi_bready,
input [1:0] o_axi_bresp,
input clk,
input rst_n
);
localparam AR_CHNL_W = 4+3+2+4+3+2+AW;
localparam AW_CHNL_W = AR_CHNL_W;
wire [AR_CHNL_W -1:0] i_axi_ar_chnl =
{
i_axi_araddr,
i_axi_arcache,
i_axi_arprot ,
i_axi_arlock ,
i_axi_arburst,
i_axi_arlen ,
i_axi_arsize
};
wire [AR_CHNL_W -1:0] o_axi_ar_chnl;
assign {
o_axi_araddr,
o_axi_arcache,
o_axi_arprot ,
o_axi_arlock ,
o_axi_arburst,
o_axi_arlen ,
o_axi_arsize
} = o_axi_ar_chnl;
sirv_gnrl_fifo #(
.CUT_READY (CHNL_FIFO_CUT_READY),
.MSKO (0),
.DP (CHNL_FIFO_DP),
.DW (AR_CHNL_W)
) o_axi_ar_fifo (
.i_rdy (i_axi_arready),
.i_vld (i_axi_arvalid),
.i_dat (i_axi_ar_chnl),
.o_rdy (o_axi_arready),
.o_vld (o_axi_arvalid),
.o_dat (o_axi_ar_chnl),
.clk (clk ),
.rst_n (rst_n)
);
wire [AW_CHNL_W-1:0] i_axi_aw_chnl =
{
i_axi_awaddr,
i_axi_awcache,
i_axi_awprot ,
i_axi_awlock ,
i_axi_awburst,
i_axi_awlen ,
i_axi_awsize
};
wire [AW_CHNL_W-1:0] o_axi_aw_chnl;
assign {
o_axi_awaddr,
o_axi_awcache,
o_axi_awprot ,
o_axi_awlock ,
o_axi_awburst,
o_axi_awlen ,
o_axi_awsize
} = o_axi_aw_chnl;
sirv_gnrl_fifo #(
.CUT_READY (CHNL_FIFO_CUT_READY),
.MSKO (0),
.DP (CHNL_FIFO_DP),
.DW (AW_CHNL_W)
) o_axi_aw_fifo (
.i_rdy (i_axi_awready),
.i_vld (i_axi_awvalid),
.i_dat (i_axi_aw_chnl ),
.o_rdy (o_axi_awready ),
.o_vld (o_axi_awvalid ),
.o_dat (o_axi_aw_chnl),
.clk (clk ),
.rst_n (rst_n)
);
localparam W_CHNL_W = DW+(DW/8)+1;
wire [W_CHNL_W-1:0] i_axi_w_chnl = {
i_axi_wdata,
i_axi_wstrb,
i_axi_wlast
};
wire [W_CHNL_W-1:0] o_axi_w_chnl;
assign {
o_axi_wdata,
o_axi_wstrb,
o_axi_wlast} = o_axi_w_chnl;
sirv_gnrl_fifo #(
.CUT_READY (CHNL_FIFO_CUT_READY),
.MSKO (0),
.DP (CHNL_FIFO_DP),
.DW (W_CHNL_W)
) o_axi_wdata_fifo(
.i_rdy (i_axi_wready),
.i_vld (i_axi_wvalid),
.i_dat (i_axi_w_chnl ),
.o_rdy (o_axi_wready),
.o_vld (o_axi_wvalid),
.o_dat (o_axi_w_chnl),
.clk (clk ),
.rst_n (rst_n)
);
//
localparam R_CHNL_W = DW+2+1;
wire [R_CHNL_W-1:0] o_axi_r_chnl = {
o_axi_rdata,
o_axi_rresp,
o_axi_rlast
};
wire [R_CHNL_W-1:0] i_axi_r_chnl;
assign {
i_axi_rdata,
i_axi_rresp,
i_axi_rlast} = i_axi_r_chnl;
sirv_gnrl_fifo # (
.CUT_READY (CHNL_FIFO_CUT_READY),
.MSKO (0),
.DP (CHNL_FIFO_DP),
.DW (R_CHNL_W)
) o_axi_rdata_fifo(
.i_rdy (o_axi_rready),
.i_vld (o_axi_rvalid),
.i_dat (o_axi_r_chnl ),
.o_rdy (i_axi_rready),
.o_vld (i_axi_rvalid),
.o_dat (i_axi_r_chnl),
.clk (clk ),
.rst_n (rst_n)
);
//
localparam B_CHNL_W = 2;
wire [B_CHNL_W -1:0] o_axi_b_chnl = {
o_axi_bresp
};
wire [B_CHNL_W -1:0] i_axi_b_chnl;
assign {
i_axi_bresp
} = i_axi_b_chnl;
sirv_gnrl_fifo #(
.CUT_READY (CHNL_FIFO_CUT_READY),
.MSKO (0),
.DP (CHNL_FIFO_DP),
.DW (B_CHNL_W)
) o_axi_bresp_fifo (
.i_rdy (o_axi_bready ),
.i_vld (o_axi_bvalid ),
.i_dat (o_axi_b_chnl),
.o_rdy (i_axi_bready),
.o_vld (i_axi_bvalid),
.o_dat (i_axi_b_chnl),
.clk (clk ),
.rst_n (rst_n)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211A_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O211A_FUNCTIONAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211A_FUNCTIONAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_gt_rx_valid_filter_7x.v
// Version : 1.11
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ns
module pcie_7x_v1_11_0_gt_rx_valid_filter_7x #(
parameter CLK_COR_MIN_LAT = 28,
parameter TCQ = 1
)
(
output [1:0] USER_RXCHARISK,
output [15:0] USER_RXDATA,
output USER_RXVALID,
output USER_RXELECIDLE,
output [ 2:0] USER_RX_STATUS,
output USER_RX_PHY_STATUS,
input [1:0] GT_RXCHARISK,
input [15:0] GT_RXDATA,
input GT_RXVALID,
input GT_RXELECIDLE,
input [ 2:0] GT_RX_STATUS,
input GT_RX_PHY_STATUS,
input PLM_IN_L0,
input PLM_IN_RS,
input USER_CLK,
input RESET
);
localparam EIOS_DET_IDL = 5'b00001;
localparam EIOS_DET_NO_STR0 = 5'b00010;
localparam EIOS_DET_STR0 = 5'b00100;
localparam EIOS_DET_STR1 = 5'b01000;
localparam EIOS_DET_DONE = 5'b10000;
localparam EIOS_COM = 8'hBC;
localparam EIOS_IDL = 8'h7C;
localparam FTSOS_COM = 8'hBC;
localparam FTSOS_FTS = 8'h3C;
reg [4:0] reg_state_eios_det;
wire [4:0] state_eios_det;
reg reg_eios_detected;
wire eios_detected;
reg reg_symbol_after_eios;
wire symbol_after_eios;
localparam USER_RXVLD_IDL = 4'b0001;
localparam USER_RXVLD_EI = 4'b0010;
localparam USER_RXVLD_EI_DB0 = 4'b0100;
localparam USER_RXVLD_EI_DB1 = 4'b1000;
reg [1:0] gt_rxcharisk_q;
reg [15:0] gt_rxdata_q;
reg gt_rxvalid_q;
reg gt_rxelecidle_q;
reg [ 2:0] gt_rx_status_q;
reg gt_rx_phy_status_q;
reg gt_rx_is_skp0_q;
reg gt_rx_is_skp1_q;
// EIOS detector
always @(posedge USER_CLK) begin
if (RESET) begin
reg_eios_detected <= #TCQ 1'b0;
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ 2'b00;
gt_rxdata_q <= #TCQ 16'h0;
gt_rxvalid_q <= #TCQ 1'b0;
gt_rxelecidle_q <= #TCQ 1'b0;
gt_rx_status_q <= #TCQ 3'b000;
gt_rx_phy_status_q <= #TCQ 1'b0;
gt_rx_is_skp0_q <= #TCQ 1'b0;
gt_rx_is_skp1_q <= #TCQ 1'b0;
end else begin
reg_eios_detected <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ GT_RXCHARISK;
gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;
gt_rxdata_q <= #TCQ GT_RXDATA;
gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;
//De-assert rx_valid signal when EIOS is detected on RXDATA
if(((reg_state_eios_det == 5'b10000)) && (PLM_IN_L0)
) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (GT_RXELECIDLE && !gt_rxvalid_q) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else begin
gt_rxvalid_q <= GT_RXVALID;
end
if (gt_rxvalid_q) begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
else if (!gt_rxvalid_q && PLM_IN_L0) begin
gt_rx_status_q <= #TCQ 3'b0;
end
else begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS)
gt_rx_is_skp0_q <= #TCQ 1'b1;
else
gt_rx_is_skp0_q <= #TCQ 1'b0;
if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS)
gt_rx_is_skp1_q <= #TCQ 1'b1;
else
gt_rx_is_skp1_q <= #TCQ 1'b0;
case ( state_eios_det )
EIOS_DET_IDL : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&
(gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;
reg_eios_detected <= #TCQ 1'b1;
// gt_rxvalid_q <= #TCQ 1'b0;
end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))
reg_state_eios_det <= #TCQ EIOS_DET_STR0;
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_NO_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin
reg_state_eios_det <= #TCQ EIOS_DET_STR1;
reg_eios_detected <= #TCQ 1'b1;
gt_rxvalid_q <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b1;
end else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR1 : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_DONE : begin
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
endcase
end
end
assign state_eios_det = reg_state_eios_det;
assign eios_detected = reg_eios_detected;
assign symbol_after_eios = reg_symbol_after_eios;
/*SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),
.D(gt_rxelecidle_q),
.CLK(USER_CLK),
.CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
*/
wire rst_l = ~RESET;
assign USER_RXVALID = gt_rxvalid_q;
assign USER_RXCHARISK[0] = gt_rxvalid_q ? gt_rxcharisk_q[0] : 1'b0;
assign USER_RXCHARISK[1] = (gt_rxvalid_q && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;
assign USER_RXDATA[7:0] = gt_rxdata_q[7:0];
assign USER_RXDATA[15:8] = gt_rxdata_q[15:8];
assign USER_RX_STATUS = gt_rx_status_q;
assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;
assign USER_RXELECIDLE = gt_rxelecidle_q;
endmodule
|
module echo #(parameter freq = 50_000_000) (
input wire clk,
input wire rst_n,
// to CoreUART
input wire rxrdy,
input wire txrdy,
input wire[7:0] data_out,
output wire oen,
output wire wen,
output wire[7:0] data_in,
// to SG90
output wire servo_pwm,
// to HC-SR04
input wire echo,
output wire trig
);
wire[7:0] servo_angle;
wire[7:0] servo_sangle;
wire[7:0] servo_eangle;
wire servo_cycle_done;
wire[7:0] sonar_distance;
wire sonar_measure;
wire sonar_ready;
servo_driver #(.freq(freq)) servo(
.clk(clk),
.rst_n(rst_n),
.servo_pwm(servo_pwm),
.angle(servo_angle),
.cycle_done(servo_cycle_done)
);
servo_fsm #(.PWM_CYCLES_PER_ITER(1)) servo_ctrl(
.clk(clk),
.rst_n(rst_n),
.servo_cycle_done(servo_cycle_done),
.servo_angle(servo_angle),
.move_en(sonar_ready),
.start_angle(servo_sangle),
.end_angle(servo_eangle)
);
sonar_driver #(.freq(freq)) sonar(
.clk(clk),
.rst_n(rst_n),
.echo(echo),
.trig(trig),
.measure(sonar_measure),
.ready(sonar_ready),
.distance(sonar_distance)
);
control_unit cu(
.clk(clk),
.rst_n(rst_n),
.cmd(data_out),
.cmd_oen(oen),
.data(data_in),
.data_wen(wen),
.rx_rdy(rxrdy),
.tx_rdy(txrdy),
.servo_cycle_done(servo_cycle_done),
.servo_angle(servo_angle),
.start_angle(servo_sangle),
.end_angle(servo_eangle),
.sonar_distance(sonar_distance),
.sonar_measure(sonar_measure),
.sonar_ready(sonar_ready)
);
endmodule
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK keyboard
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: rk_kbd.v
//
module rk_kbd(
input clk,
input reset,
input ps2_clk,
input ps2_dat,
input[7:0] addr,
output reg[7:0] odata,
output reg cpurst,
output reg videomode,
output[2:0] shift);
reg[7:0] keystate[10:0];
assign shift = keystate[8][2:0];
always @(addr,keystate) begin
odata =
(keystate[0] & {8{addr[0]}})|
(keystate[1] & {8{addr[1]}})|
(keystate[2] & {8{addr[2]}})|
(keystate[3] & {8{addr[3]}})|
(keystate[4] & {8{addr[4]}})|
(keystate[5] & {8{addr[5]}})|
(keystate[6] & {8{addr[6]}})|
(keystate[7] & {8{addr[7]}});
end
reg[2:0] c;
reg[3:0] r;
reg extkey;
reg unpress;
reg[3:0] prev_clk;
reg[11:0] shift_reg;
wire[11:0] kdata = {ps2_dat,shift_reg[11:1]};
wire[7:0] kcode = kdata[9:2];
always @(*) begin
case (kcode)
8'h6C: {c,r} = 7'h00; // 7 home
8'h7D: {c,r} = 7'h10; // 9 pgup
8'h76: {c,r} = 7'h20; // esc
8'h05: {c,r} = 7'h30; // F1
8'h06: {c,r} = 7'h40; // F2
8'h04: {c,r} = 7'h50; // F3
8'h0C: {c,r} = 7'h60; // F4
8'h03: {c,r} = 7'h70; // F5
8'h0D: {c,r} = 7'h01; // tab
8'h71: {c,r} = 7'h11; // . del
8'h5A: {c,r} = 7'h21; // enter
8'h66: {c,r} = 7'h31; // bksp
8'h6B: {c,r} = 7'h41; // 4 left
8'h75: {c,r} = 7'h51; // 8 up
8'h74: {c,r} = 7'h61; // 6 right
8'h72: {c,r} = 7'h71; // 2 down
8'h45: {c,r} = 7'h02; // 0
8'h16: {c,r} = 7'h12; // 1
8'h1E: {c,r} = 7'h22; // 2
8'h26: {c,r} = 7'h32; // 3
8'h25: {c,r} = 7'h42; // 4
8'h2E: {c,r} = 7'h52; // 5
8'h36: {c,r} = 7'h62; // 6
8'h3D: {c,r} = 7'h72; // 7
8'h3E: {c,r} = 7'h03; // 8
8'h46: {c,r} = 7'h13; // 9
8'h55: {c,r} = 7'h23; // =
8'h0E: {c,r} = 7'h33; // `
8'h41: {c,r} = 7'h43; // ,
8'h4E: {c,r} = 7'h53; // -
8'h49: {c,r} = 7'h63; // .
8'h4A: {c,r} = extkey ? 7'h73 : 7'h73; // gray/ + /
8'h4C: {c,r} = 7'h04; // ;
8'h1C: {c,r} = 7'h14; // A
8'h32: {c,r} = 7'h24; // B
8'h21: {c,r} = 7'h34; // C
8'h23: {c,r} = 7'h44; // D
8'h24: {c,r} = 7'h54; // E
8'h2B: {c,r} = 7'h64; // F
8'h34: {c,r} = 7'h74; // G
8'h33: {c,r} = 7'h05; // H
8'h43: {c,r} = 7'h15; // I
8'h3B: {c,r} = 7'h25; // J
8'h42: {c,r} = 7'h35; // K
8'h4B: {c,r} = 7'h45; // L
8'h3A: {c,r} = 7'h55; // M
8'h31: {c,r} = 7'h65; // N
8'h44: {c,r} = 7'h75; // O
8'h4D: {c,r} = 7'h06; // P
8'h15: {c,r} = 7'h16; // Q
8'h2D: {c,r} = 7'h26; // R
8'h1B: {c,r} = 7'h36; // S
8'h2C: {c,r} = 7'h46; // T
8'h3C: {c,r} = 7'h56; // U
8'h2A: {c,r} = 7'h66; // V
8'h1D: {c,r} = 7'h76; // W
8'h22: {c,r} = 7'h07; // X
8'h35: {c,r} = 7'h17; // Y
8'h1A: {c,r} = 7'h27; // Z
8'h54: {c,r} = 7'h37; // [
8'h52: {c,r} = 7'h47; // '
8'h5B: {c,r} = 7'h57; // ]
8'h5D: {c,r} = 7'h67; // \!
8'h29: {c,r} = 7'h77; // space
8'h12: {c,r} = 7'h08; // lshift
8'h59: {c,r} = 7'h08; // rshift
8'h14: {c,r} = extkey ? 7'h18 : 7'h18; // rctrl + lctrl
8'h11: {c,r} = 7'h28; // lalt
/* 8'h0B: {c,r} = 7'h50; // F6
8'h83: {c,r} = 7'h70; // F7
8'h0A: {c,r} = 7'h12; // F8
8'h01: {c,r} = 7'h33; // F9
8'h07: {c,r} = 7'h56; // F12 - stop
8'h7C: {c,r} = 7'h46; // gray*
8'h7B: {c,r} = 7'h66; // gray-
8'h78: {c,r} = 7'h67; // F11 - rus
8'h73: {c,r} = 7'h28; // 5 center
8'h7A: {c,r} = 7'h48; // 3 pgdn
8'h69: {c,r} = 7'h68; // 1 end
8'h70: {c,r} = 7'h78; // 0 ins
*/ default: {c,r} = 7'h7F;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
prev_clk <= 0;
shift_reg <= 12'hFFF;
extkey <= 0;
unpress <= 0;
keystate[0] <= 0;
keystate[1] <= 0;
keystate[2] <= 0;
keystate[3] <= 0;
keystate[4] <= 0;
keystate[5] <= 0;
keystate[6] <= 0;
keystate[7] <= 0;
keystate[8] <= 0;
keystate[9] <= 0;
keystate[10] <= 0;
cpurst <= 0;
end else begin
prev_clk <= {ps2_clk,prev_clk[3:1]};
if (prev_clk==4'b1) begin
if (kdata[11]==1'b1 && ^kdata[10:2]==1'b1 && kdata[1:0]==2'b1) begin
shift_reg <= 12'hFFF;
if (kcode==8'hE0) extkey <= 1'b1; else
if (kcode==8'hF0) unpress <= 1'b1; else
begin
extkey <= 0;
unpress <= 0;
if(r!=4'hF) keystate[r][c] <= ~unpress;
if(kcode == 8'h07 && unpress == 1'b0) cpurst <= 1'b1; else cpurst <= 1'b0;
if(kcode == 8'h78 && unpress == 1'b0) videomode <= !videomode;
end
end else
shift_reg <= kdata;
end
end
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module bg (
address,
clock,
q);
input [9:0] address;
input clock;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../Desktop/bg.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "24"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../Desktop/bg.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_a 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32A_2_V
`define SKY130_FD_SC_HD__O32A_2_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32a_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32A_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:20:24 02/22/2015
// Design Name:
// Module Name: Add
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AddProcess(
input [31:0] z_postAllign,
input [3:0] Opcode_Allign,
input idle_Allign,
input [35:0] cout_Allign,
input [35:0] zout_Allign,
input [31:0] sout_Allign,
input [7:0] InsTagAllign,
input clock,
output reg idle_AddState,
output reg [31:0] sout_AddState,
output reg [27:0] sum_AddState,
output reg [3:0] Opcode_AddState,
output reg [31:0] z_postAddState,
output reg [7:0] InsTagAdder
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_Allign[35];
assign z_exponent = zout_Allign[34:27] - 127;
assign z_mantissa = {zout_Allign[26:0]};
assign c_sign = cout_Allign[35];
assign c_exponent = cout_Allign[34:27] - 127;
assign c_mantissa = {cout_Allign[26:0]};
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // Pre processed input is given 4'd11
// This requires pre processing. x = (a+1)/2 and y = (a-1)/2
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10,
PreProcess = 4'd11;
always @ (posedge clock)
begin
InsTagAdder <= InsTagAllign;
z_postAddState <= z_postAllign;
Opcode_AddState <= Opcode_Allign;
//if(Opcode_Allign == PreProcess) begin
idle_AddState <= idle_Allign;
if (idle_Allign != put_idle) begin
sout_AddState[30:23] <= c_exponent;
sout_AddState[22:0] <= 0;
if (c_sign == z_sign) begin
sum_AddState <= c_mantissa + z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
if (c_mantissa >= z_mantissa) begin
sum_AddState <= c_mantissa - z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
sum_AddState <= z_mantissa - c_mantissa;
sout_AddState[31] <= z_sign;
end
end
end
else begin
sout_AddState <= sout_Allign;
sum_AddState <= 0;
end
//end
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
wire [width-1:0] dec_test_expr = test_expr - {{width-1{1'b0}},1'b1};
wire zoh_test_expr = ((test_expr & dec_test_expr) == {width{1'b0}});
wire valid_test_expr = ((test_expr ^ test_expr) == {width{1'b0}});
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression contains more than 1 asserted bits");
end
end
end
assign fire_2state_1 = !zoh_test_expr;
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] one_hots_checked;
reg [width-1:0] prev_one_hots_checked;
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
prev_test_expr <= test_expr; // deliberately not reset
if (`OVL_RESET_SIGNAL == 1'b0) begin
one_hots_checked <= {width{1'b0}};
prev_one_hots_checked <= {width{1'b0}};
end
else begin
if (valid_test_expr && zoh_test_expr) begin
one_hots_checked <= one_hots_checked | test_expr;
end
prev_one_hots_checked <= one_hots_checked;
end
end
wire fire_cover_1, fire_cover_2, fire_cover_3;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("all_one_hots_checked covered"); // corner
end
if (fire_cover_3) begin
ovl_cover_t("test_expr_all_zeros covered"); // corner
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (one_hots_checked == {width{1'b1}}) && (one_hots_checked != prev_one_hots_checked));
assign fire_cover_3 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == {width{1'b0}}) && (prev_test_expr != {width{1'b0}}));
`endif // OVL_COVER_ON
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Jun 01 11:35:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_overlay_0_0/system_vga_overlay_0_0_sim_netlist.v
// Design : system_vga_overlay_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_overlay_0_0,vga_overlay,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_overlay,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_overlay_0_0
(clk,
rgb_0,
rgb_1,
rgb);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [23:0]rgb_0;
input [23:0]rgb_1;
output [23:0]rgb;
wire clk;
wire [23:0]rgb;
wire [23:0]rgb_0;
wire [23:0]rgb_1;
system_vga_overlay_0_0_vga_overlay U0
(.clk(clk),
.rgb(rgb),
.rgb_0({rgb_0[23:17],rgb_0[15:9],rgb_0[7:1]}),
.rgb_1({rgb_1[23:17],rgb_1[15:9],rgb_1[7:1]}));
endmodule
(* ORIG_REF_NAME = "vga_overlay" *)
module system_vga_overlay_0_0_vga_overlay
(rgb,
rgb_1,
clk,
rgb_0);
output [23:0]rgb;
input [20:0]rgb_1;
input clk;
input [20:0]rgb_0;
wire [6:0]b_0;
wire [6:0]b_1;
wire clk;
wire [6:0]g_0;
wire [6:0]g_1;
wire [6:0]r_0;
wire [6:0]r_1;
wire [23:0]rgb;
wire [7:0]rgb0;
wire [7:0]rgb00_out;
wire [7:0]rgb01_out;
wire \rgb[11]_i_2_n_0 ;
wire \rgb[11]_i_3_n_0 ;
wire \rgb[11]_i_4_n_0 ;
wire \rgb[11]_i_5_n_0 ;
wire \rgb[15]_i_2_n_0 ;
wire \rgb[15]_i_3_n_0 ;
wire \rgb[15]_i_4_n_0 ;
wire \rgb[19]_i_2_n_0 ;
wire \rgb[19]_i_3_n_0 ;
wire \rgb[19]_i_4_n_0 ;
wire \rgb[19]_i_5_n_0 ;
wire \rgb[23]_i_2_n_0 ;
wire \rgb[23]_i_3_n_0 ;
wire \rgb[23]_i_4_n_0 ;
wire \rgb[3]_i_2_n_0 ;
wire \rgb[3]_i_3_n_0 ;
wire \rgb[3]_i_4_n_0 ;
wire \rgb[3]_i_5_n_0 ;
wire \rgb[7]_i_2_n_0 ;
wire \rgb[7]_i_3_n_0 ;
wire \rgb[7]_i_4_n_0 ;
wire [20:0]rgb_0;
wire [20:0]rgb_1;
wire \rgb_reg[11]_i_1_n_0 ;
wire \rgb_reg[11]_i_1_n_1 ;
wire \rgb_reg[11]_i_1_n_2 ;
wire \rgb_reg[11]_i_1_n_3 ;
wire \rgb_reg[15]_i_1_n_2 ;
wire \rgb_reg[15]_i_1_n_3 ;
wire \rgb_reg[19]_i_1_n_0 ;
wire \rgb_reg[19]_i_1_n_1 ;
wire \rgb_reg[19]_i_1_n_2 ;
wire \rgb_reg[19]_i_1_n_3 ;
wire \rgb_reg[23]_i_1_n_2 ;
wire \rgb_reg[23]_i_1_n_3 ;
wire \rgb_reg[3]_i_1_n_0 ;
wire \rgb_reg[3]_i_1_n_1 ;
wire \rgb_reg[3]_i_1_n_2 ;
wire \rgb_reg[3]_i_1_n_3 ;
wire \rgb_reg[7]_i_1_n_2 ;
wire \rgb_reg[7]_i_1_n_3 ;
wire [2:2]\NLW_rgb_reg[15]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_reg[15]_i_1_O_UNCONNECTED ;
wire [2:2]\NLW_rgb_reg[23]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_reg[23]_i_1_O_UNCONNECTED ;
wire [2:2]\NLW_rgb_reg[7]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_reg[7]_i_1_O_UNCONNECTED ;
FDRE \b_0_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_0[0]),
.Q(b_0[0]),
.R(1'b0));
FDRE \b_0_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_0[1]),
.Q(b_0[1]),
.R(1'b0));
FDRE \b_0_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_0[2]),
.Q(b_0[2]),
.R(1'b0));
FDRE \b_0_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_0[3]),
.Q(b_0[3]),
.R(1'b0));
FDRE \b_0_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_0[4]),
.Q(b_0[4]),
.R(1'b0));
FDRE \b_0_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_0[5]),
.Q(b_0[5]),
.R(1'b0));
FDRE \b_0_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_0[6]),
.Q(b_0[6]),
.R(1'b0));
FDRE \b_1_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_1[0]),
.Q(b_1[0]),
.R(1'b0));
FDRE \b_1_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_1[1]),
.Q(b_1[1]),
.R(1'b0));
FDRE \b_1_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_1[2]),
.Q(b_1[2]),
.R(1'b0));
FDRE \b_1_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_1[3]),
.Q(b_1[3]),
.R(1'b0));
FDRE \b_1_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_1[4]),
.Q(b_1[4]),
.R(1'b0));
FDRE \b_1_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_1[5]),
.Q(b_1[5]),
.R(1'b0));
FDRE \b_1_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_1[6]),
.Q(b_1[6]),
.R(1'b0));
FDRE \g_0_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_0[7]),
.Q(g_0[0]),
.R(1'b0));
FDRE \g_0_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_0[8]),
.Q(g_0[1]),
.R(1'b0));
FDRE \g_0_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_0[9]),
.Q(g_0[2]),
.R(1'b0));
FDRE \g_0_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_0[10]),
.Q(g_0[3]),
.R(1'b0));
FDRE \g_0_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_0[11]),
.Q(g_0[4]),
.R(1'b0));
FDRE \g_0_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_0[12]),
.Q(g_0[5]),
.R(1'b0));
FDRE \g_0_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_0[13]),
.Q(g_0[6]),
.R(1'b0));
FDRE \g_1_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_1[7]),
.Q(g_1[0]),
.R(1'b0));
FDRE \g_1_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_1[8]),
.Q(g_1[1]),
.R(1'b0));
FDRE \g_1_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_1[9]),
.Q(g_1[2]),
.R(1'b0));
FDRE \g_1_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_1[10]),
.Q(g_1[3]),
.R(1'b0));
FDRE \g_1_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_1[11]),
.Q(g_1[4]),
.R(1'b0));
FDRE \g_1_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_1[12]),
.Q(g_1[5]),
.R(1'b0));
FDRE \g_1_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_1[13]),
.Q(g_1[6]),
.R(1'b0));
FDRE \r_0_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_0[14]),
.Q(r_0[0]),
.R(1'b0));
FDRE \r_0_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_0[15]),
.Q(r_0[1]),
.R(1'b0));
FDRE \r_0_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_0[16]),
.Q(r_0[2]),
.R(1'b0));
FDRE \r_0_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_0[17]),
.Q(r_0[3]),
.R(1'b0));
FDRE \r_0_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_0[18]),
.Q(r_0[4]),
.R(1'b0));
FDRE \r_0_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_0[19]),
.Q(r_0[5]),
.R(1'b0));
FDRE \r_0_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_0[20]),
.Q(r_0[6]),
.R(1'b0));
FDRE \r_1_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_1[14]),
.Q(r_1[0]),
.R(1'b0));
FDRE \r_1_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_1[15]),
.Q(r_1[1]),
.R(1'b0));
FDRE \r_1_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_1[16]),
.Q(r_1[2]),
.R(1'b0));
FDRE \r_1_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_1[17]),
.Q(r_1[3]),
.R(1'b0));
FDRE \r_1_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_1[18]),
.Q(r_1[4]),
.R(1'b0));
FDRE \r_1_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_1[19]),
.Q(r_1[5]),
.R(1'b0));
FDRE \r_1_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_1[20]),
.Q(r_1[6]),
.R(1'b0));
LUT2 #(
.INIT(4'h6))
\rgb[11]_i_2
(.I0(g_0[3]),
.I1(g_1[3]),
.O(\rgb[11]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[11]_i_3
(.I0(g_0[2]),
.I1(g_1[2]),
.O(\rgb[11]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[11]_i_4
(.I0(g_0[1]),
.I1(g_1[1]),
.O(\rgb[11]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[11]_i_5
(.I0(g_0[0]),
.I1(g_1[0]),
.O(\rgb[11]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[15]_i_2
(.I0(g_0[6]),
.I1(g_1[6]),
.O(\rgb[15]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[15]_i_3
(.I0(g_0[5]),
.I1(g_1[5]),
.O(\rgb[15]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[15]_i_4
(.I0(g_0[4]),
.I1(g_1[4]),
.O(\rgb[15]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[19]_i_2
(.I0(r_0[3]),
.I1(r_1[3]),
.O(\rgb[19]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[19]_i_3
(.I0(r_0[2]),
.I1(r_1[2]),
.O(\rgb[19]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[19]_i_4
(.I0(r_0[1]),
.I1(r_1[1]),
.O(\rgb[19]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[19]_i_5
(.I0(r_0[0]),
.I1(r_1[0]),
.O(\rgb[19]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[23]_i_2
(.I0(r_0[6]),
.I1(r_1[6]),
.O(\rgb[23]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[23]_i_3
(.I0(r_0[5]),
.I1(r_1[5]),
.O(\rgb[23]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[23]_i_4
(.I0(r_0[4]),
.I1(r_1[4]),
.O(\rgb[23]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[3]_i_2
(.I0(b_0[3]),
.I1(b_1[3]),
.O(\rgb[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[3]_i_3
(.I0(b_0[2]),
.I1(b_1[2]),
.O(\rgb[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[3]_i_4
(.I0(b_0[1]),
.I1(b_1[1]),
.O(\rgb[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[3]_i_5
(.I0(b_0[0]),
.I1(b_1[0]),
.O(\rgb[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[7]_i_2
(.I0(b_0[6]),
.I1(b_1[6]),
.O(\rgb[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[7]_i_3
(.I0(b_0[5]),
.I1(b_1[5]),
.O(\rgb[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[7]_i_4
(.I0(b_0[4]),
.I1(b_1[4]),
.O(\rgb[7]_i_4_n_0 ));
FDRE \rgb_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb0[0]),
.Q(rgb[0]),
.R(1'b0));
FDRE \rgb_reg[10]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[2]),
.Q(rgb[10]),
.R(1'b0));
FDRE \rgb_reg[11]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[3]),
.Q(rgb[11]),
.R(1'b0));
CARRY4 \rgb_reg[11]_i_1
(.CI(1'b0),
.CO({\rgb_reg[11]_i_1_n_0 ,\rgb_reg[11]_i_1_n_1 ,\rgb_reg[11]_i_1_n_2 ,\rgb_reg[11]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(g_0[3:0]),
.O(rgb00_out[3:0]),
.S({\rgb[11]_i_2_n_0 ,\rgb[11]_i_3_n_0 ,\rgb[11]_i_4_n_0 ,\rgb[11]_i_5_n_0 }));
FDRE \rgb_reg[12]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[4]),
.Q(rgb[12]),
.R(1'b0));
FDRE \rgb_reg[13]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[5]),
.Q(rgb[13]),
.R(1'b0));
FDRE \rgb_reg[14]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[6]),
.Q(rgb[14]),
.R(1'b0));
FDRE \rgb_reg[15]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[7]),
.Q(rgb[15]),
.R(1'b0));
CARRY4 \rgb_reg[15]_i_1
(.CI(\rgb_reg[11]_i_1_n_0 ),
.CO({rgb00_out[7],\NLW_rgb_reg[15]_i_1_CO_UNCONNECTED [2],\rgb_reg[15]_i_1_n_2 ,\rgb_reg[15]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,g_0[6:4]}),
.O({\NLW_rgb_reg[15]_i_1_O_UNCONNECTED [3],rgb00_out[6:4]}),
.S({1'b1,\rgb[15]_i_2_n_0 ,\rgb[15]_i_3_n_0 ,\rgb[15]_i_4_n_0 }));
FDRE \rgb_reg[16]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[0]),
.Q(rgb[16]),
.R(1'b0));
FDRE \rgb_reg[17]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[1]),
.Q(rgb[17]),
.R(1'b0));
FDRE \rgb_reg[18]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[2]),
.Q(rgb[18]),
.R(1'b0));
FDRE \rgb_reg[19]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[3]),
.Q(rgb[19]),
.R(1'b0));
CARRY4 \rgb_reg[19]_i_1
(.CI(1'b0),
.CO({\rgb_reg[19]_i_1_n_0 ,\rgb_reg[19]_i_1_n_1 ,\rgb_reg[19]_i_1_n_2 ,\rgb_reg[19]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(r_0[3:0]),
.O(rgb01_out[3:0]),
.S({\rgb[19]_i_2_n_0 ,\rgb[19]_i_3_n_0 ,\rgb[19]_i_4_n_0 ,\rgb[19]_i_5_n_0 }));
FDRE \rgb_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb0[1]),
.Q(rgb[1]),
.R(1'b0));
FDRE \rgb_reg[20]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[4]),
.Q(rgb[20]),
.R(1'b0));
FDRE \rgb_reg[21]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[5]),
.Q(rgb[21]),
.R(1'b0));
FDRE \rgb_reg[22]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[6]),
.Q(rgb[22]),
.R(1'b0));
FDRE \rgb_reg[23]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[7]),
.Q(rgb[23]),
.R(1'b0));
CARRY4 \rgb_reg[23]_i_1
(.CI(\rgb_reg[19]_i_1_n_0 ),
.CO({rgb01_out[7],\NLW_rgb_reg[23]_i_1_CO_UNCONNECTED [2],\rgb_reg[23]_i_1_n_2 ,\rgb_reg[23]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,r_0[6:4]}),
.O({\NLW_rgb_reg[23]_i_1_O_UNCONNECTED [3],rgb01_out[6:4]}),
.S({1'b1,\rgb[23]_i_2_n_0 ,\rgb[23]_i_3_n_0 ,\rgb[23]_i_4_n_0 }));
FDRE \rgb_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb0[2]),
.Q(rgb[2]),
.R(1'b0));
FDRE \rgb_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb0[3]),
.Q(rgb[3]),
.R(1'b0));
CARRY4 \rgb_reg[3]_i_1
(.CI(1'b0),
.CO({\rgb_reg[3]_i_1_n_0 ,\rgb_reg[3]_i_1_n_1 ,\rgb_reg[3]_i_1_n_2 ,\rgb_reg[3]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(b_0[3:0]),
.O(rgb0[3:0]),
.S({\rgb[3]_i_2_n_0 ,\rgb[3]_i_3_n_0 ,\rgb[3]_i_4_n_0 ,\rgb[3]_i_5_n_0 }));
FDRE \rgb_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb0[4]),
.Q(rgb[4]),
.R(1'b0));
FDRE \rgb_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb0[5]),
.Q(rgb[5]),
.R(1'b0));
FDRE \rgb_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb0[6]),
.Q(rgb[6]),
.R(1'b0));
FDRE \rgb_reg[7]
(.C(clk),
.CE(1'b1),
.D(rgb0[7]),
.Q(rgb[7]),
.R(1'b0));
CARRY4 \rgb_reg[7]_i_1
(.CI(\rgb_reg[3]_i_1_n_0 ),
.CO({rgb0[7],\NLW_rgb_reg[7]_i_1_CO_UNCONNECTED [2],\rgb_reg[7]_i_1_n_2 ,\rgb_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,b_0[6:4]}),
.O({\NLW_rgb_reg[7]_i_1_O_UNCONNECTED [3],rgb0[6:4]}),
.S({1'b1,\rgb[7]_i_2_n_0 ,\rgb[7]_i_3_n_0 ,\rgb[7]_i_4_n_0 }));
FDRE \rgb_reg[8]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[0]),
.Q(rgb[8]),
.R(1'b0));
FDRE \rgb_reg[9]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[1]),
.Q(rgb[9]),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : mig_7series_0.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:36:27 $
// \ \ / \ Date Created : Fri Jan 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : QDRII+ SDRAM
// Purpose :
// Wrapper module for the user design top level file. This module can be
// instantiated in the system and interconnect as shown in example design
// (example_top module).
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_0 (
// Single-ended system clock
input sys_clk_i,
input [0:0] qdriip_cq_p, //Memory Interface
input [0:0] qdriip_cq_n,
input [35:0] qdriip_q,
output wire [0:0] qdriip_k_p,
output wire [0:0] qdriip_k_n,
output wire [35:0] qdriip_d,
output wire [18:0] qdriip_sa,
output wire qdriip_w_n,
output wire qdriip_r_n,
output wire [3:0] qdriip_bw_n,
output wire qdriip_dll_off_n,
// User Interface signals of Channel-0
input app_wr_cmd0,
input [18:0] app_wr_addr0,
input [143:0] app_wr_data0,
input [15:0] app_wr_bw_n0,
input app_rd_cmd0,
input [18:0] app_rd_addr0,
output wire app_rd_valid0,
output wire [143:0] app_rd_data0,
// User Interface signals of Channel-1. It is useful only for BL2 designs.
// All inputs of Channel-1 can be grounded for BL4 designs.
input app_wr_cmd1,
input [18:0] app_wr_addr1,
input [71:0] app_wr_data1,
input [7:0] app_wr_bw_n1,
input app_rd_cmd1,
input [18:0] app_rd_addr1,
output wire app_rd_valid1,
output wire [71:0] app_rd_data1,
output wire clk,
output wire rst_clk,
output init_calib_complete,
input sys_rst
);
// Start of IP top instance
mig_7series_0_mig u_mig_7series_0_mig (
// Memory interface ports
.qdriip_cq_p (qdriip_cq_p),
.qdriip_cq_n (qdriip_cq_n),
.qdriip_q (qdriip_q),
.qdriip_k_p (qdriip_k_p),
.qdriip_k_n (qdriip_k_n),
.qdriip_d (qdriip_d),
.qdriip_sa (qdriip_sa),
.qdriip_w_n (qdriip_w_n),
.qdriip_r_n (qdriip_r_n),
.qdriip_bw_n (qdriip_bw_n),
.qdriip_dll_off_n (qdriip_dll_off_n),
.init_calib_complete (init_calib_complete),
// Application interface ports
.app_wr_cmd0 (app_wr_cmd0),
.app_wr_cmd1 (app_wr_cmd1),
.app_wr_addr0 (app_wr_addr0),
.app_wr_addr1 (app_wr_addr1),
.app_rd_cmd0 (app_rd_cmd0),
.app_rd_cmd1 (app_rd_cmd1),
.app_rd_addr0 (app_rd_addr0),
.app_rd_addr1 (app_rd_addr1),
.app_wr_data0 (app_wr_data0),
.app_wr_data1 (app_wr_data1),
.app_wr_bw_n0 (app_wr_bw_n0),
.app_wr_bw_n1 (app_wr_bw_n1),
.app_rd_valid0 (app_rd_valid0),
.app_rd_valid1 (app_rd_valid1),
.app_rd_data0 (app_rd_data0),
.app_rd_data1 (app_rd_data1),
.clk (clk),
.rst_clk (rst_clk),
// System Clock Ports
.sys_clk_i (sys_clk_i),
.sys_rst (sys_rst)
);
// End of IP top instance
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// Company: Loctronix Corporation
// Engineer: Michael B. Mathews
//
// Create Date: 21:44:12 02/24/2014
// Design Name:
// Module Name: 4ChTxRx.v
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Container implementent 4 channel transmit and receive paths.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "../wca/hal/WcaHalRegisterDefs.vh" //grab register addresses.
`include "4ChTxRxRegisterDefs.vh"
`define IDENTIFIER 16'h0002 //4 CH Transceiver Identifier.
`define VERSION 16'h0104 //[ver].[rev]
`define PORTCAPS 16'h0303 //2 RX / 2 TX ports defined.
`define PORT_COUNT 4
`define PORT0_ADDR 2'h0 //TX Port 0 is EP 8h
`define PORT1_ADDR 2'h1 //Rx Port 1 is EP 88h
`define PORT2_ADDR 2'h2 //TX Port 2 is EP 9h
`define PORT3_ADDR 2'h3 //RX Port 3 is EP 89h
`define PORT_ADDR_MODE_SEQUENTIAL 0
`define PORT_ADDR_MODE_FIXED 1
//Following macros define the port mode and fixed address
//Changing these changes what is active.
`define PORT_MODE `PORT_ADDR_MODE_SEQUENTIAL
`define PORT_FIXED_ADDR `PORT0_ADDR
`define TX0_MODE 4'hB // TODO: Halfband filter (IPCore) needs to be replaced. Left out for now.
`define TX1_MODE 4'hB // TODO: Halfband filter (IPCore) needs to be replaced. Left out for now.
//DEFINE DDC / DUC Register addresses using WCA Component structure.
//This is defined in the 4CHTxRxRegisterDefs.vh.
`define DUC0_CTRL (`WCACOMP_DSP_DUC0 + `DSP_DDUC_CTRL)
`define DUC0_FREQ (`WCACOMP_DSP_DUC0 + `DSP_DDUC_PHASERATE)
`define DUC0_INTERP (`WCACOMP_DSP_DUC0 + `DSP_DDUC_SAMPRATE)
`define DDC0_CTRL (`WCACOMP_DSP_DDC0 + `DSP_DDUC_CTRL)
`define DDC0_FREQ (`WCACOMP_DSP_DDC0 + `DSP_DDUC_PHASERATE)
`define DDC0_DECIM (`WCACOMP_DSP_DDC0 + `DSP_DDUC_SAMPRATE)
`define DUC1_CTRL (`WCACOMP_DSP_DUC1 + `DSP_DDUC_CTRL)
`define DUC1_FREQ (`WCACOMP_DSP_DUC1 + `DSP_DDUC_PHASERATE)
`define DUC1_INTERP (`WCACOMP_DSP_DUC1 + `DSP_DDUC_SAMPRATE)
`define DDC1_CTRL (`WCACOMP_DSP_DDC1 + `DSP_DDUC_CTRL)
`define DDC1_FREQ (`WCACOMP_DSP_DDC1 + `DSP_DDUC_PHASERATE)
`define DDC1_DECIM (`WCACOMP_DSP_DDC1 + `DSP_DDUC_SAMPRATE)
module WcaContainer
(
input wire reset, //Active Hi
input wire clockData, //Runs control logics and Data I/O
input wire clockDsp, //Fundamental clock of Baseband DSP data. All sample clocks derive from this.
//RF0
input wire [23:0] rx0_iq,
output wire [23:0] tx0_iq,
input wire rx0_strobe, //Strobe of rx0 baseband data.
input wire tx0_strobe, //Strobe of tx0 baseband data.
//RF1
input wire [23:0] rx1_iq,
output wire [23:0] tx1_iq,
input wire rx1_strobe, //Strobe of rx1 baseband data.
input wire tx1_strobe, //Strobe of tx1 baseband data.
//LED
output wire [3:0] ledSelect, // {led_3, led_2, led_1, led_0}
output wire [5:0] rfSelect, // {rf_Wb2_RxSelect, rf_Wb1_RxSelect,
// rf_Ism_TxSelect, rf_Ism_ExtSelect,
// rf_Gps_ExtSelect, rf_Gps_DcBiasSelect}
//USB Port Interface
inout [31:0] pifData, // 32 bit port interface data bus.
output wire [(NBITS_ADDR+1):0] pifCtrl, // {addr[NBITS_ADDR:0], iocmd[1:0] }
input wire [6:0] pifStatus, // Interface status {fifo_full[0], fifo_empty[0], ioState[3:0], clk}
// 8 bit expansion port.
inout [7:0] ep_io,
output wire [7:0] evtsig, // Event Indicators.
//CPU Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter NBITS_ADDR = 2;
//*******************************
// Standard Registers
//*******************************
//Register returns the waveform id.
WcaReadWordReg #(`WCAHAL_IDWAVEFORM) waveformid ( .clock( clockData), .reset( reset),
.enableIn( 1'b1), .in(`IDENTIFIER),
.rbusCtrl(rbusCtrl),.rbusData(rbusData));
//Register returns the version identifier.
WcaReadWordReg #(`WCAHAL_VERSION) version ( .clock( clockData), .reset( reset),
.enableIn( 1'b1), .in(`VERSION),
.rbusCtrl(rbusCtrl),.rbusData(rbusData));
//*******************************
// I/O Control Registers
//*******************************
//RF Selection Switches
WcaWriteByteReg #(`WCAHAL_RFCONFIG) wr_rf_select
(.reset(reset),
.out( rfSelect ),
.rbusCtrl(rbusCtrl), .rbusData(rbusData) );
//*******************************************
// Expansion Port
//*******************************************
//Ground the expansion port interface.
//wire dspClkout;
//assign dpsClkout = clockDsp;
//assign ep_io = 8'hFF;
//*******************************************
// USB PORT Interface Control
//*******************************************
wire [4:0] portCtrl;
wire [1:0] portCmd;
wire clearSynch; //Wire clears all fifos when synch enabled.
wire enableSynch; // Wire enables all fifos with the synch bit set in the configuration register.
//Assign the LEDs to indicate which ports are enabled [ rx1, rx0, tx1, tx0]
assign ledSelect = { rx1_full, tx1_empty, rx0_full, tx0_empty};
//assign ledSelect = { tx0_duc_bbstrobe, tx0_duc_cfg[0], tx0_full, tx0_empty};
//Register returns the version identifier.
WcaReadWordReg #(`WCAHAL_PORTCAPS) rr_port_caps
(.clock( clockData), .reset( reset),
.enableIn( 1'b1), .in(`PORTCAPS),
.rbusCtrl(rbusCtrl),.rbusData(rbusData));
//Controller manages reading and writing port data with the USB Interface. Several
//Addressing modes are supported depending on needs.
WcaPortController #(`PORT_COUNT, NBITS_ADDR, `PORT_MODE, `PORT_FIXED_ADDR) port_controller(
.reset(reset),
.enable(1'b1),
.portCtrl( portCtrl), // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
.portCmd( portCmd), // Port Command ID
//Port Interface
.pifCtrl(pifCtrl), // {addr[NBITS_ADDR:0], iocmd[1:0] }
.pifStatus(pifStatus) // Interface status {fifo_full[0], fifo_empty[0], ioState[3:0], clk}
);
//*******************************************
// Event mapping
//*******************************************
wire evt_fifoerr;
//Assign events Upper four events are not assigned.
assign evtsig = { 3'h0, evt_fifoerr, rx1_full, tx1_empty, rx0_full, tx0_empty};
//Generate an event if the fifos.full.
assign evt_fifoerr = rx1_full | tx1_empty | rx0_full | tx0_empty;
//******************************************
// Channel TX0 Implementation.
//*******************************************
wire tx0_full, tx0_empty, tx0_afull, tx0_aempty;
wire [31:0] iq_port0;
wire [23:0] bbtx0_iq;
wire [7:0] tx0_duc_cfg;
wire [12:0] tx0_duc_rateinterp;
wire tx0_duc_rateinterp_we;
wire tx0_duc_cicstrobe;
wire tx0_duc_bbstrobe;
wire [31:0] tx0_duc_phasecordic;
wire [3:0] tx0_log2_rate;
// tx0_cicStrobe strobes the data sent from the CIC filter to the CORDIC
WcaDducController #(`DUC0_FREQ, `DUC0_INTERP, `DUC0_CTRL, `TX0_MODE ) tx0_DucController(
.clock(clockDsp), //input clock
.reset(reset), //input
.enable(tx0_duc_cfg[0]), //input
.strobe_if(tx0_strobe),
//Bind controller signals.
.cfg( tx0_duc_cfg), // output signal, read inside DDUC Controller
.rate_interp(tx0_duc_rateinterp), // output interp rate for CIC in DUC
.rate_interp_we(tx0_duc_rateinterp_we),
.log2_rate(tx0_log2_rate),
.strobe_cic(tx0_duc_cicstrobe), //output CIC baseband strobe rate
.strobe_bb( tx0_duc_bbstrobe),
.phase_cordic( tx0_duc_phasecordic),
//CPU Interface.
.rbusCtrl(rbusCtrl), // input address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
.rbusData(rbusData) // inout Tri-state I/O data, 8 bits
);
WcaReadPort #(.ADDR_PORT(`PORT0_ADDR)) tx0_port_read(
.reset(reset | tx0_duc_cfg[1]),
.port_enable( tx0_duc_cfg[0]),
.rd_clk(clockDsp), // Clock read input..
.rd_en(tx0_duc_bbstrobe), // Enables reading.
.rd_out(iq_port0), // Read Data output.
.empty(tx0_empty), // Active high indicates buffer is empty.
.full (tx0_full), // Active high indicates buffer is empty.
.prog_empty(tx0_aempty),
.prog_full(tx0_afull),
.pifData(pifData), // 32 bit port interface data bus.
.portCtrl(portCtrl), // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
.portCmd(portCmd) // Port Command ID
);
//Offset and interpolate Baseband frequency.
WcaUpConverter #(`TX0_MODE) tx0_duc
(
.clock( clockDsp), // input Clock
.reset( reset), // input reset
.enable(tx0_duc_cfg[0]), // input enable
.cfg( tx0_duc_cfg),
.rate_interp(tx0_duc_rateinterp),
.rate_interp_we(tx0_duc_rateinterp_we),
.strobe_cic(tx0_duc_cicstrobe),
.strobe_bb(tx0_duc_bbstrobe),
.phase_cordic( tx0_duc_phasecordic),
.log2_rate(tx0_log2_rate),
.strobe_if(tx0_strobe), // I.F. data output strobe (input).
//.iq_bb_in({16'h0100, 16'h0100}), // Baseband input data [31:0]
.iq_bb_in(iq_port0), // Baseband input data [31:0]
.iq_if_out(tx0_iq), // I.F. ouput [23:0] iq_out
.rbusCtrl(rbusCtrl),
.rbusData(rbusData)
);
//******************************************
// Channel RX0 Implementation.
//*******************************************
wire rx0_full, rx0_empty, rx0_afull, rx0_aempty;
wire [31:0] rx0_out;
wire [12:0] rx0_rate;
wire rx0_strobewrite;
// DDC0_CTRL (WcaWriteByteRegister)
wire [7:0] ddc0_ctrl;
wire clearRx0 = (clearSynch & ddc0_ctrl[6]) | ddc0_ctrl[1];
wire enableRx0 = (enableSynch & ddc0_ctrl[6]) | ddc0_ctrl[0];
WcaWriteByteReg #(`DDC0_CTRL) wr_ddc0_ctrl
(.reset(reset),
.out( ddc0_ctrl),
.rbusCtrl(rbusCtrl), .rbusData(rbusData) );
//Implement DDC with Dynamic configuration enabled.
WcaDownConverter #(`DDC0_FREQ, `DDC0_DECIM) rx0_ddc
(
.clock( clockDsp), // input Clock
.reset( reset ), // input reset
.aclr( clearRx0), // input clears state not configuration
.enable( enableRx0), // input enable
.dstrobe_in(rx0_strobe), // input dstrobe_in
.cfgflags( ddc0_ctrl[5:2]), // input cfgflags (dynamic mode enabled).
.iq_in(rx0_iq), // input [23:0] diq_in
.iq_out(rx0_out), // ouput [31:0] diq_out
.dstrobe_out(rx0_strobewrite), // ouput dstrobe_out
.rbusCtrl(rbusCtrl),
.rbusData(rbusData)
);
//Assign Port Address #1 as the DDC RX0 Output.
WcaPortWrite #(.ADDR_PORT(`PORT1_ADDR)) rx0_port_write
(
.reset(reset | clearRx0),
.port_enable( enableRx0),
.wr_clk(clockDsp), // Clock input to fifo.
.wr_en( rx0_strobewrite ), // Allows input if specified.
.wr_in( rx0_out), // Clock data input.
.empty( rx0_empty), // Active high indicates buffer is empty.
.full( rx0_full), // Active high indicates buffer is empty.
.prog_empty(rx0_aempty),
.prog_full(rx0_afull),
.pifData(pifData), // 32 bit port interface data bus.
.portCtrl(portCtrl), // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
.portCmd(portCmd) // Port Command ID
);
//******************************************
// Channel TX1 Implementation.
//*******************************************
wire tx1_full, tx1_empty, tx1_afull, tx1_aempty;
wire [31:0] iq_port1;
wire [23:0] bbtx1_iq;
wire [7:0] tx1_duc_cfg;
wire [12:0] tx1_duc_rateinterp;
wire tx1_duc_rateinterp_we;
wire tx1_duc_cicstrobe;
wire tx1_duc_bbstrobe;
wire [31:0] tx1_duc_phasecordic;
wire [3:0] tx1_log2_rate;
WcaDducController #(`DUC1_FREQ, `DUC1_INTERP, `DUC1_CTRL, `TX1_MODE ) tx1_DucController(
.clock(clockDsp), //input clock
.reset(reset), //input
.enable(tx1_duc_cfg[0]), //input
.strobe_if(tx1_strobe),
//Bind controller signals.
.cfg( tx1_duc_cfg), // output signal, read inside DDUC Controller
.rate_interp(tx1_duc_rateinterp), // output interp rate for CIC in DUC
.rate_interp_we(tx1_duc_rateinterp_we),
.log2_rate(tx1_log2_rate),
.strobe_cic(tx1_duc_cicstrobe), //output CIC baseband strobe rate
.strobe_bb( tx1_duc_bbstrobe),
.phase_cordic( tx1_duc_phasecordic),
//CPU Interface.
.rbusCtrl(rbusCtrl), // input address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
.rbusData(rbusData) // inout Tri-state I/O data, 8 bits
);
WcaReadPort #(.ADDR_PORT(`PORT2_ADDR)) tx1_port_read(
.reset(reset | tx1_duc_cfg[1]),
.port_enable( tx1_duc_cfg[0]),
.rd_clk(clockDsp), // Clock read input..
.rd_en(tx1_duc_bbstrobe), // Enables reading.
.rd_out(iq_port1), // Read Data output.
.empty(tx1_empty), // Active high indicates buffer is empty.
.full (tx1_full), // Active high indicates buffer is empty.
.prog_empty(tx1_aempty),
.prog_full(tx1_afull),
.pifData(pifData), // 32 bit port interface data bus.
.portCtrl(portCtrl), // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
.portCmd(portCmd) // Port Command ID
);
//Offset and interpolate Baseband frequency.
WcaUpConverter #(`TX1_MODE) tx1_duc
(
.clock( clockDsp), // input Clock
.reset( reset), // input reset
.enable(tx1_duc_cfg[0]), // input enable
.cfg( tx1_duc_cfg),
.rate_interp(tx1_duc_rateinterp),
.rate_interp_we(tx1_duc_rateinterp_we),
.strobe_cic(tx1_duc_cicstrobe),
.strobe_bb(tx1_duc_bbstrobe),
.phase_cordic( tx1_duc_phasecordic),
.log2_rate(tx1_log2_rate),
.strobe_if(tx1_strobe), // I.F. data output strobe (input).
.iq_bb_in(iq_port1), // Baseband input data [31:0]
.iq_if_out(tx1_iq), // I.F. ouput [23:0] iq_out
.rbusCtrl(rbusCtrl),
.rbusData(rbusData)
);
//******************************************
// Channel RX1 Implementation.
//*******************************************
wire rx1_full, rx1_empty, rx1_aempty, rx1_afull;
wire [31:0] rx1_out;
wire [12:0] rx1_rate;
wire rx1_strobewrite;
// DDC1_CTRL (WcaWriteByteRegister)
wire [7:0] ddc1_ctrl;
wire clearRx1 = (clearSynch & ddc1_ctrl[6]) | ddc1_ctrl[1];
wire enableRx1 = (enableSynch & ddc1_ctrl[6]) | ddc1_ctrl[0];
WcaWriteByteReg #(`DDC1_CTRL) wr_ddc1_ctrl
(.reset(reset),
.out( ddc1_ctrl),
.rbusCtrl(rbusCtrl), .rbusData(rbusData) );
//Implement DDC
WcaDownConverter #(`DDC1_FREQ, `DDC1_DECIM) rx1_ddc
(
.clock( clockDsp), // input Clock
.reset( reset ), // input reset
.aclr( clearRx1), // input clears state not configuration
.enable( enableRx1), // input enable
.dstrobe_in(rx1_strobe), // input dstrobe_in
.cfgflags( ddc1_ctrl[5:2]), // input cfgflags (dynamic mode enabled).
.iq_in(rx1_iq), // input [23:0] diq_in
.iq_out(rx1_out), // ouput [31:0] diq_out
.dstrobe_out(rx1_strobewrite), // ouput dstrobe_out
.rbusCtrl(rbusCtrl),
.rbusData(rbusData)
);
//Assign Port Address #3 as the DDC RX1 Output.
WcaPortWrite #(.ADDR_PORT(`PORT3_ADDR)) rx1_port_write
(
.reset(reset | clearRx1),
.port_enable( enableRx1),
.wr_clk(clockDsp), // Clock input to fifo.
.wr_en( rx1_strobewrite ), // write.
.wr_in( rx1_out), // Clock data input.
.empty( rx1_empty), // Active high indicates buffer is empty.
.full( rx1_full), // Active high indicates buffer is empty.
.prog_empty(rx1_aempty),
.prog_full(rx1_afull),
.pifData(pifData), // 32 bit port interface data bus.
.portCtrl(portCtrl), // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
.portCmd(portCmd) // Port Command ID
);
//Create multi-channel synchronization mode.
//WcaSynchEdgeDetect seClearSynch ( .clk(clock_dsp), .in((rx1_strobe& ddc0_ctrl[6] & ddc0_ctrl[1]) | (ddc1_ctrl[6] & ddc1_ctrl[1])), .rising( clearSynch) );
//WcaSynchEdgeDetect seEnableSynch ( .clk(clock_dsp), .in((ddc0_ctrl[6] & ddc0_ctrl[0]) | (ddc1_ctrl[6] & ddc1_ctrl[0])), .out( enableSynch) );
assign clearSynch = (ddc0_ctrl[6] & ddc0_ctrl[1]) | (ddc1_ctrl[6] & ddc1_ctrl[1]);
assign enableSynch = (ddc0_ctrl[6] & ddc0_ctrl[0]) | (ddc1_ctrl[6] & ddc1_ctrl[0]);
assign ep_io = { 2'h0, clearSynch, enableSynch, clearRx1, clearRx0, rx1_strobewrite, rx0_strobewrite};
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.