text
stringlengths 938
1.05M
|
|---|
module fifo_TB;
reg clk;
reg rst;
reg rd;
reg wr;
reg data_in;
fifo uttf(.rd(rd),.wr(wr),.din(data_in),.reset(rst),.clock(clk));
/* Clocking device */
always
begin
clk =1'b1;
#2;
clk=1'b0;
#2;
end
initial
begin
rst =1'b1;
#10000;
rst =1'b0;
end
initial begin
#4;
data_in=1'b1; #1 wr=1; #2 wr=0;
data_in="o"; #1 wr=1; #2 wr=0;
data_in="l"; #1 wr=1; #2 wr=0;
data_in="a"; #1 wr=1; #2 wr=0;
data_in=" "; #1 wr=1; #2 wr=0;
data_in="m"; #1 wr=1; #2 wr=0;
data_in="u"; #1 wr=1; #2 wr=0;
data_in="n"; #1 wr=1; #2 wr=0;
data_in="d"; #1 wr=1; #2 wr=0;
data_in="o"; #1 wr=1; #2 wr=0;
data_in="."; #1 wr=1; #2 wr=0;
data_in="1"; #1 wr=1; #2 wr=0;
data_in="2"; #1 wr=1; #2 wr=0;
data_in="3"; #1 wr=1; #2 wr=0;
data_in="4"; #1 wr=1; #2 wr=0;
data_in="5"; #1 wr=1; #2 wr=0;
data_in="6"; #1 wr=1; #2 wr=0;
data_in="7"; #1 wr=1; #2 wr=0;
data_in="8"; #1 wr=1; #2 wr=0;
data_in="9"; #1 wr=1; #2 wr=0;
data_in="0"; #1 wr=1; #2 wr=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
data_in="a"; #1 wr=1; rd=0;#2 wr=0;rd=1;
data_in="b"; #1 wr=1; #2 wr=0;
data_in="c"; #1 wr=1; #2 wr=0;
data_in="d"; #1 wr=1; #2 wr=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
#1 rd=1; #2 rd=0;
end
initial begin: TEST_CASE
$dumpfile("fifo_TB.vcd");
$dumpvars(-1, uttf);
#(1000000) $finish;
end
endmodule //
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output reg mcu_rrq = 0,
output mcu_write,
output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output reg dac_play_out = 0,
output reg dac_reset_out = 0,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
output reg [8:0] dac_ptr_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// feature enable
output reg [7:0] featurebits_out,
// gsu
output reg gsu_reset_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// DSP core features
output reg [15:0] dsp_feat_out = 16'h0000
);
initial begin
gsu_reset_out = 1'b1;
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf = 0;
reg MSU_RESET_OUT_BUF;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
reg [7:0] dsp_feat_tmp;
wire mcu_nextaddr;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
MSU_RESET_OUT_BUF <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
dac_play_out <= 1'b0;
8'he2: // resume DAC
dac_play_out <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
dac_ptr_out[8] <= param_data[0];
32'h3: begin
dac_ptr_out[7:0] <= param_data;
dac_reset_out <= 1'b1; // reset by default value, see above
end
endcase
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
endcase
8'heb: // control GSU reset
gsu_reset_out <= param_data[0];
8'hec:
begin // set DAC properties
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
8'hed:
featurebits_out <= param_data;
8'hee:
region_out <= param_data[0];
8'hef:
case (spi_byte_cnt)
32'h2: dsp_feat_tmp <= param_data[7:0];
32'h3: begin
dsp_feat_out <= {dsp_feat_tmp, param_data[7:0]};
end
endcase
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:4] == 4'hA)
MCU_DATA_IN_BUF <= snescmd_data_in;
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
always @(posedge clk) begin
mcu_rrq <= 1'b0;
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq <= 1'b1;
end
end
always @(posedge clk) begin
mcu_wrq <= 1'b0;
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq <= 1'b1;
end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:25:53 06/10/2015
// Design Name:
// Module Name: ControlUnit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ControlUnit(
input clk,
input[5:0] opcode,
input[5:0] func,
input[4:0] RS,
input MemOK,
input[31:0] C0State,
output MemRead,
output PCWrite,
output PCWriteCond,
output IorD,
output MemWrite,
output[2:0] WriteData,
output IRWrite,
output[1:0] ALUSrcA,
output RegWrite,
output[1:0] RegDst,
output SaveHalf,
output LoadHalf,
output[1:0] ALUop,
output[2:0] ALUSrcB,
output[2:0] PCSource,
output[5:0] CUState,
output[5:0] ALUFunc,
output C0Write,
output[1:0] C0Dst,
output[2:0] C0Src,
output CauseSource,
output SyscallInte,
output IsBne
);
reg [5:0] state;
assign CUState = state;
assign InteEn = C0State[0];
assign INTE = C0State[1];
initial begin
state <= 0;
end
assign R =(opcode==6'h00);
assign SLL_SRL_SRA =(opcode==6'h00 && func[5:2]==4'h0);
assign JR =(opcode==6'h00 && func==6'h8);
assign JALR =(opcode==6'h00 && func==6'h9);
assign SYSCALL = (opcode==6'h00 && func==6'hC);
assign J =(opcode==6'h02);
assign JAL =(opcode==6'h03);
assign BEQ =(opcode==6'h04);
assign BNE =(opcode==6'h05);
assign ADDI =(opcode==6'h08);
assign ADDIU =(opcode==6'h09);
assign SLTI =(opcode==6'h0A);
assign SLTIU =(opcode==6'h0B);
assign ANDI =(opcode==6'h0C);
assign ORI =(opcode==6'h0D);
assign XORI =(opcode==6'h0E);
assign LUI =(opcode==6'h0F);
assign MFC0 =(opcode==6'h10 && RS==5'h0);
assign MTC0 =(opcode==6'h10 && RS==5'h4);
assign ERET =(opcode==6'h10 && RS==5'h10 && func==6'h18);
assign MUL =(opcode==6'h1c);
assign LH =(opcode==6'h21);
assign LW =(opcode==6'h23);
assign SH =(opcode==6'h29);
assign SW =(opcode==6'h2B);
always @(posedge clk) begin
case(state)
0: begin
if(INTE && InteEn) begin
state <= 25;
end
else begin
state <= 23;
end
end
1: begin
if(LW | SW | LH | SH) begin
state <= 2;
end
else if (R)begin
if(JR) begin
state <= 14;
end
else if(JALR) begin
state <= 15;
end
else if(SLL_SRL_SRA) begin
state <= 19;
end
else if(SYSCALL) begin
state <= 29;
end
else begin
state <= 6;
end
end
else if (BEQ) begin
state <= 8;
end
else if (J) begin
state <= 9;
end
else if(JAL) begin
state <= 13;
end
else if(MFC0) begin
state <= 16;
end
else if(MTC0) begin
state <= 17;
end
else if(LUI) begin
state <= 18;
end
else if(ADDI | SLTI) begin
state <= 20;
end
else if(ANDI | ORI |XORI | ADDIU | SLTIU) begin
state <= 21;
end
else if(MUL) begin
state <= 22;
end
else if(ERET) begin
state <= 32;
end
else if(BNE) begin
state <= 34;
end
end
2: begin
if (LW)begin
state <= 3;
end
else if (SW)begin
state <= 5;
end
else if (SH)begin
state <= 11;
end
else if (LH)begin
state <= 10;
end
end
3: begin
state <= 4;
end
4: begin
if(MemOK) begin
state <= 0;
end
end
5: begin
state <= 33;
end
6: begin
state <= 7;
end
7: begin
state <= 0;
end
8: begin
state <= 0;
end
9: begin
state <= 0;
end
10: begin
state <= 4;
end
11: begin
state <= 33;
end
12: begin
state <= 0;
end
13: begin
state <=0;
end
14: begin
state <= 0;
end
15: begin
state <= 0;
end
16: begin
state <= 0;
end
17: begin
state <= 0;
end
18: begin
state <= 0;
end
19: begin
state <= 7;
end
20: begin
state <= 24;
end
21: begin
state <= 24;
end
22: begin
state <= 7;
end
23: begin
if(MemOK) begin
state <= 1;
end
end
24: begin
state <= 0;
end
25: begin
state <= 26;
end
26: begin
state <= 27;
end
27: begin
state <= 0;
end
28: begin
state <= 31;
end
29: begin
state <= 30;
end
30: begin
state <= 0;
end
31: begin
state <= 0;
end
32: begin
state <= 28;
end
33: begin
if(MemOK) begin
state <= 0;
end
end
34: begin
state <= 0;
end
default: begin
state <= 0;
end
endcase
end
assign state0 = (state == 0);
assign state1 = (state == 1);
assign state2 = (state == 2);
assign state3 = (state == 3);
assign state4 = (state == 4);
assign state5 = (state == 5);
assign state6 = (state == 6);
assign state7 = (state == 7);
assign state8 = (state == 8);
assign state9 = (state == 9);
assign state10 = (state == 10);
assign state11 = (state == 11);
assign state13 = (state == 13);
assign state14 = (state == 14);
assign state15 = (state == 15);
assign state16 = (state == 16);
assign state17 = (state == 17);
assign state18 = (state == 18);
assign state19 = (state == 19);
assign state20 = (state == 20);
assign state21 = (state == 21);
assign state22 = (state == 22);
assign state23 = (state == 23);
assign state24 = (state == 24);
assign state25 = (state == 25);
assign state26 = (state == 26);
assign state27 = (state == 27);
assign state28 = (state == 28);
assign state29 = (state == 29);
assign state30 = (state == 30);
assign state31 = (state == 31);
assign state32 = (state == 32);
assign state33 = (state == 33);
assign state34 = (state == 34);
assign PCWrite = state9 | state13 | state14 | state15 | (state23 & MemOK)|state27 | state28;
assign PCWriteCond = state8 | state34;
assign IorD = state3 | state5 | state10 | state11;
assign MemRead = state0 | state3 | state10;
assign MemWrite = state5 | state11;
assign WriteData[2] = state18;
assign WriteData[1] = state13 | state15 | state16;
assign WriteData[0] = state4 | state16;
assign IRWrite = state23 & MemOK;
assign ALUop[1] = state6 | state19 | state20 | state21 | state22;
assign ALUop[0] = state8 | state34;
assign ALUSrcA[1] = state19;
assign ALUSrcA[0] = state2 | state6 | state8 | state20 | state21 | state22 | state34;
assign ALUSrcB[2] = state21;
assign ALUSrcB[1] = state1 | state2 | state20;
assign ALUSrcB[0] = state1 | state23;
assign RegWrite = (state4 & MemOK) | state7 | state13 | state15 | state16 | state18 | state24;
assign RegDst[1] = state13;
assign RegDst[0] = state7 | state15;
assign SaveHalf = state11;
assign LoadHalf = state10;
assign PCSource[2] = state27 | state28;
assign PCSource[1] = state9 | state13 | state14 | state15;
assign PCSource[0] = state8 | state14 | state15 | state27 | state34;
assign IsBne = state34;
assign ALUFunc =
{6{R}} & func |
{6{ADDI}} & 6'h20 |
{6{ADDIU}} & 6'h21 |
{6{SLTI}} & 6'h2A |
{6{SLTIU}} & 6'h2B |
{6{ANDI}} & 6'h24 |
{6{ORI}} & 6'h25 |
{6{XORI}} & 6'h26 |
{6{MUL}} & 6'h3f;
assign C0Write = state17 | state25 | state26 | state29 | state31;
assign C0Dst[1]= state0 | state25 | state29 | state28 | state31;
assign C0Dst[0]= state26 | state29 | state32;
assign C0Src[2]= state31;
assign C0Src[1]= state25 | state29;
assign C0Src[0]= state26 | state29;
assign CauseSource = state30;
assign SyscallInte = state30;
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Simple/useful components
*
*/
module LAG_reg (data_in, data_out, clk, rst_n);
input flit_t data_in;
output flit_t data_out;
input clk, rst_n;
always@(posedge clk) begin
if (!rst_n) begin
data_out <= '0;
end else begin
data_out <= data_in;
end
end
endmodule
module LAG_pipelined_channel (data_in, data_out, clk, rst_n);
parameter stages = 0;
parameter nPC = 1; // Number of physical channels per trunk
input flit_t data_in[nPC-1:0];
output flit_t data_out[nPC-1:0];
input clk, rst_n;
genvar st, pc;
flit_t ch_reg[stages-1:0][nPC-1:0];
generate
if (stages==0) begin
// no registers in channel
assign data_out = data_in;
end else begin
for (st=0; st<stages; st++) begin:eachstage
if (st==0) begin
for (pc = 0; pc < nPC; pc++) begin:eachPC1
LAG_reg rg (.data_in(data_in[pc]), .data_out(ch_reg[0][pc]), .clk, .rst_n);
end
end else begin
for (pc = 0; pc < nPC; pc++) begin:eachPC2
LAG_reg rg (.data_in(ch_reg[st-1][pc]), .data_out(ch_reg[st][pc]), .clk, .rst_n);
end
end
end
assign data_out = ch_reg[stages-1];
end
endgenerate
endmodule
//
// Multiplexer with one-hot encoded select input
//
// - output is '0 if no select input is asserted
//
module LAG_mux_oh_select (data_in, select, data_out);
//parameter type dtype_t = byte;
parameter n = 4;
input flit_t data_in [n-1:0];
input [n-1:0] select;
output flit_t data_out;
int i;
always_comb
begin
data_out='0;
for (i=0; i<n; i++) begin
if (select[i]) data_out = data_in[i];
end
end
endmodule // LAG_mux_oh_select
//
// Crossbar built from multiplexers, one-hot encoded select input
//
module LAG_crossbar_oh_select (data_in, select, data_out);
//parameter type dtype_t = byte;
parameter n = 4;
input flit_t data_in [n-1:0];
// select[output][select-input];
input [n-1:0][n-1:0] select; // n one-hot encoded select signals per output
output flit_t data_out [n-1:0];
genvar i;
generate
for (i=0; i<n; i++) begin:outmuxes
LAG_mux_oh_select #(.n(n)) xbarmux (data_in, select[i], data_out[i]);
end
endgenerate
endmodule // LAG_crossbar_oh_select
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOBUFSRC_SYMBOL_V
`define SKY130_FD_SC_LP__ISOBUFSRC_SYMBOL_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__isobufsrc (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOBUFSRC_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:30:38 03/19/2013
// Design Name:
// Module Name: vga640x480
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga640x480(
input wire dclk, //pixel clock: 25MHz
input wire clr, //asynchronous reset
output wire hsync, //horizontal sync out
output wire vsync, //vertical sync out
output reg [2:0] red, //red vga output
output reg [2:0] green, //green vga output
output reg [1:0] blue, //blue vga output
output [9:0]x,
output [9:0]y
);
// video structure constants
parameter hpixels = 800;// horizontal pixels per line
parameter vlines = 521; // vertical lines per frame
parameter hpulse = 96; // hsync pulse length
parameter vpulse = 2; // vsync pulse length
parameter hbp = 144; // end of horizontal back porch
parameter hfp = 784; // beginning of horizontal front porch
parameter vbp = 31; // end of vertical back porch
parameter vfp = 511; // beginning of vertical front porch
// active horizontal video is therefore: 784 - 144 = 640
// active vertical video is therefore: 511 - 31 = 480
// registers for storing the horizontal & vertical counters
reg [9:0] hc;
reg [9:0] vc;
assign x = hc - hbp;
assign y = vc - vbp;
// Horizontal & vertical counters --
// this is how we keep track of where we are on the screen.
// ------------------------
// Sequential "always block", which is a block that is
// only triggered on signal transitions or "edges".
// posedge = rising edge & negedge = falling edge
// Assignment statements can only be used on type "reg" and need to be of the "non-blocking" type: <=
always @(posedge dclk or posedge clr)
begin
// reset condition
if (clr == 1)
begin
hc <= 0;
vc <= 0;
end
else
begin
// keep counting until the end of the line
if (hc < hpixels - 1)
hc <= hc + 1;
else
// When we hit the end of the line, reset the horizontal
// counter and increment the vertical counter.
// If vertical counter is at the end of the frame, then
// reset that one too.
begin
hc <= 0;
if (vc < vlines - 1)
vc <= vc + 1;
else
vc <= 0;
end
end
end
// generate sync pulses (active low)
// ----------------
// "assign" statements are a quick way to
// give values to variables of type: wire
assign hsync = (hc < hpulse) ? 0:1;
assign vsync = (vc < vpulse) ? 0:1;
// display 100% saturation colorbars
// ------------------------
// Combinational "always block", which is a block that is
// triggered when anything in the "sensitivity list" changes.
// The asterisk implies that everything that is capable of triggering the block
// is automatically included in the sensitivty list. In this case, it would be
// equivalent to the following: always @(hc, vc)
// Assignment statements can only be used on type "reg" and should be of the "blocking" type: =
always @(*)
begin
// first check if we're within vertical active video range
if (vc >= vbp && vc < vfp)
begin
// now display different colors every 80 pixels
// while we're within the active horizontal range
// -----------------
// display white bar
if (hc >= hbp && hc < (hbp+80))
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
// display yellow bar
else if (hc >= (hbp+80) && hc < (hbp+160))
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
// display cyan bar
else if (hc >= (hbp+160) && hc < (hbp+240))
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
// display green bar
else if (hc >= (hbp+240) && hc < (hbp+320))
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
// display magenta bar
else if (hc >= (hbp+320) && hc < (hbp+400))
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
// display red bar
else if (hc >= (hbp+400) && hc < (hbp+480))
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
// display blue bar
else if (hc >= (hbp+480) && hc < (hbp+560))
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
// display black bar
else if (hc >= (hbp+560) && hc < (hbp+640))
begin
red = 3'b000;
green = 3'b000;
blue = 2'b00;
end
// we're outside active horizontal range so display black
else
begin
red = 0;
green = 0;
blue = 0;
end
end
// we're outside active vertical range so display black
else
begin
red = 0;
green = 0;
blue = 0;
end
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: buffer_dp.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module buffer_dp (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [7:0] data;
input [8:0] rdaddress;
input rdclock;
input [8:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "512"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "buffer_dp"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "buffer_dp"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL rdaddress[8..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL wraddress[8..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
module Pruebas_Controlador_Gato;
// Inputs
reg clk;
reg reset_all;
reg reset_game;
reg boton_arriba_reg;
reg boton_abajo_reg;
reg boton_izq_reg;
reg boton_der_reg;
reg boton_elige_reg;
// Outputs
wire [3:0] cuadro;
wire [3:0] circulo;
wire [3:0] equis;
wire [1:0] vertical;
wire [1:0] horizontal;
wire [1:0] cruzada;
wire [2:0] state;
wire turno_p1_wire;
wire turno_p2_wire;
wire win_game;
wire loss_game;
wire tie_game;
// Instantiate the Unit Under Test (UUT)
Controlador_Gato uut (
.clk(clk),
.reset_all(reset_all),
.reset_game(reset_game),
.cuadro(cuadro),
.circulo(circulo),
.equis(equis),
.vertical(vertical),
.horizontal(horizontal),
.cruzada(cruzada),
.state(state),
.boton_arriba_reg(boton_arriba_reg),
.boton_abajo_reg(boton_abajo_reg),
.boton_izq_reg(boton_izq_reg),
.boton_der_reg(boton_der_reg),
.boton_elige_reg(boton_elige_reg),
.turno_p1_wire(turno_p1_wire),
.turno_p2_wire(turno_p2_wire),
.win_game(win_game),
.loss_game(loss_game),
.tie_game(tie_game)
);
always
#5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset_all = 0;
reset_game = 0;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 1;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 1;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 1;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 1;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 1;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 1;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 1;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 1;
#10;
boton_arriba_reg = 1;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 1;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 1;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 1;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 1;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 1;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 1;
#10;
boton_arriba_reg = 0;
boton_abajo_reg = 0;
boton_izq_reg = 0;
boton_der_reg = 0;
boton_elige_reg = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_BLACKBOX_V
`define SKY130_FD_SC_LS__TAPVGND2_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_BLACKBOX_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Mon Oct 24 15:17:36 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.2 2005/10/24 15:50:24 wig Exp $
// $Date: 2005/10/24 15:50:24 $
// $Log: ent_a.v,v $
// Revision 1.2 2005/10/24 15:50:24 wig
// added 'reg detection to ::out column
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.64 2005/10/20 17:28:26 lutscher Exp
//
// Generator: mix_0.pl Revision: 1.38 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_a
//
// No `defines in this module
module ent_a
//
// Generated module inst_a
//
(
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_17_10_5_go,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_15, // will not create a reg in inst_a
sig_16, // reg 16 in inst_a
sig_17, // reg in inst_a, ab and aa
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Generated Module Inputs:
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [5:0] p_mix_sig_17_10_5_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output [7:0] sig_15;
output [9:0] sig_16;
output [4:0] sig_17;
output sig_o_a2;
// Generated Wires:
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [5:0] p_mix_sig_17_10_5_go;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire [7:0] sig_15;
reg [9:0] sig_16;
reg [4:0] sig_17;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign p_mix_sig_17_10_5_go[5:0] = sig_17[10:5]; // __I_O_SLICE_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14), // Multiline comment 3...
.sig_17(sig_17[10:6]) // reg in inst_a, ab and aa
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14), // Multiline comment 3...
.sig_17(sig_17[5]) // reg in inst_a, ab and aa
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 32-Deep by 8-bit Wide Multi Port RAM
// /___/ /\ Filename : RAM32M.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/21/06 - Initial version.
// 12/01/06 - Fix cut/past error for port C and D (CR 430051)
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAM32M #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT_A = 64'h0000000000000000,
parameter [63:0] INIT_B = 64'h0000000000000000,
parameter [63:0] INIT_C = 64'h0000000000000000,
parameter [63:0] INIT_D = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output [1:0] DOA,
output [1:0] DOB,
output [1:0] DOC,
output [1:0] DOD,
input [4:0] ADDRA,
input [4:0] ADDRB,
input [4:0] ADDRC,
input [4:0] ADDRD,
input [1:0] DIA,
input [1:0] DIB,
input [1:0] DIC,
input [1:0] DID,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM32M";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire IS_WCLK_INVERTED_BIN;
wire [4:0] ADDRD_in;
wire [1:0] DIA_in;
wire [1:0] DIB_in;
wire [1:0] DIC_in;
wire [1:0] DID_in;
wire WCLK_in;
wire WE_in;
`ifdef XIL_TIMING
wire [4:0] ADDRD_dly;
wire [1:0] DIA_dly;
wire [1:0] DIB_dly;
wire [1:0] DIC_dly;
wire [1:0] DID_dly;
wire WCLK_dly;
wire WE_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign ADDRD_in = ADDRD_dly;
assign DIA_in = DIA_dly;
assign DIB_in = DIB_dly;
assign DIC_in = DIC_dly;
assign DID_in = DID_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign ADDRD_in = ADDRD;
assign DIA_in = DIA;
assign DIB_in = DIB;
assign DIC_in = DIC;
assign DID_in = DID;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED;
reg [63:0] mem_a, mem_b, mem_c, mem_d;
reg [5:0] addr_in2, addr_in1;
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
end
always @(ADDRD_in) begin
addr_in2 = 2 * ADDRD_in;
addr_in1 = 2 * ADDRD_in + 1;
end
always @(posedge WCLK_in)
if (WE_in) begin
mem_a[addr_in2] <= #100 DIA_in[0];
mem_a[addr_in1] <= #100 DIA_in[1];
mem_b[addr_in2] <= #100 DIB_in[0];
mem_b[addr_in1] <= #100 DIB_in[1];
mem_c[addr_in2] <= #100 DIC_in[0];
mem_c[addr_in1] <= #100 DIC_in[1];
mem_d[addr_in2] <= #100 DID_in[0];
mem_d[addr_in1] <= #100 DID_in[1];
end
assign DOA[0] = mem_a[2*ADDRA];
assign DOA[1] = mem_a[2*ADDRA + 1];
assign DOB[0] = mem_b[2*ADDRB];
assign DOB[1] = mem_b[2*ADDRB + 1];
assign DOC[0] = mem_c[2*ADDRC];
assign DOC[1] = mem_c[2*ADDRC + 1];
assign DOD[0] = mem_d[2*ADDRD_in];
assign DOD[1] = mem_d[2*ADDRD_in + 1];
`ifdef XIL_TIMING
always @(notifier) begin
mem_a[addr_in2] <= 1'bx;
mem_a[addr_in1] <= 1'bx;
mem_b[addr_in2] <= 1'bx;
mem_b[addr_in1] <= 1'bx;
mem_c[addr_in2] <= 1'bx;
mem_c[addr_in1] <= 1'bx;
mem_d[addr_in2] <= 1'bx;
mem_d[addr_in1] <= 1'bx;
end
assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN;
assign sh_clk_en_n = IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN;
specify
(WCLK => DOA[0]) = (0:0:0, 0:0:0);
(WCLK => DOA[1]) = (0:0:0, 0:0:0);
(WCLK => DOB[0]) = (0:0:0, 0:0:0);
(WCLK => DOB[1]) = (0:0:0, 0:0:0);
(WCLK => DOC[0]) = (0:0:0, 0:0:0);
(WCLK => DOC[1]) = (0:0:0, 0:0:0);
(WCLK => DOD[0]) = (0:0:0, 0:0:0);
(WCLK => DOD[1]) = (0:0:0, 0:0:0);
(ADDRA *> DOA[0]) = (0:0:0, 0:0:0);
(ADDRA *> DOA[1]) = (0:0:0, 0:0:0);
(ADDRB *> DOB[0]) = (0:0:0, 0:0:0);
(ADDRB *> DOB[1]) = (0:0:0, 0:0:0);
(ADDRC *> DOC[0]) = (0:0:0, 0:0:0);
(ADDRC *> DOC[1]) = (0:0:0, 0:0:0);
(ADDRD *> DOD[0]) = (0:0:0, 0:0:0);
(ADDRD *> DOD[1]) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:52:51 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57,
n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132,
n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148;
OAI21X2TS U46 ( .A0(n113), .A1(n112), .B0(n46), .Y(res[16]) );
NAND2XLTS U47 ( .A(n68), .B(n117), .Y(n119) );
NAND2XLTS U48 ( .A(n39), .B(n114), .Y(n116) );
NAND2X4TS U49 ( .A(n113), .B(n71), .Y(n46) );
CLKBUFX2TS U50 ( .A(n137), .Y(n33) );
OR2X2TS U51 ( .A(n78), .B(in1[14]), .Y(n39) );
OAI21X1TS U52 ( .A0(n76), .A1(in2[14]), .B0(add_sub), .Y(n74) );
INVX4TS U53 ( .A(n34), .Y(n48) );
NAND2X1TS U54 ( .A(n76), .B(add_sub), .Y(n77) );
CLKXOR2X2TS U55 ( .A(n80), .B(in2[13]), .Y(n81) );
NOR2XLTS U56 ( .A(n79), .B(n101), .Y(n80) );
NAND2XLTS U57 ( .A(n82), .B(add_sub), .Y(n83) );
NAND2BX2TS U58 ( .AN(in2[13]), .B(n79), .Y(n76) );
NOR2X2TS U59 ( .A(n82), .B(in2[12]), .Y(n79) );
NAND2X1TS U60 ( .A(n86), .B(add_sub), .Y(n87) );
NAND2X2TS U61 ( .A(in1[8]), .B(n70), .Y(n31) );
NAND2BX2TS U62 ( .AN(in2[9]), .B(n102), .Y(n86) );
NOR2X4TS U63 ( .A(n99), .B(in2[8]), .Y(n102) );
NAND2X1TS U64 ( .A(n99), .B(add_sub), .Y(n100) );
NAND2X4TS U65 ( .A(n127), .B(in1[6]), .Y(n97) );
NOR2X6TS U66 ( .A(n95), .B(in2[6]), .Y(n88) );
OR2X6TS U67 ( .A(n137), .B(in1[5]), .Y(n69) );
NAND2X4TS U68 ( .A(n95), .B(add_sub), .Y(n96) );
INVX3TS U69 ( .A(n67), .Y(n54) );
INVX6TS U70 ( .A(n133), .Y(n94) );
INVX8TS U71 ( .A(in2[3]), .Y(n62) );
INVX6TS U72 ( .A(in2[2]), .Y(n63) );
INVX6TS U73 ( .A(in2[1]), .Y(n64) );
INVX6TS U74 ( .A(in2[0]), .Y(n65) );
NOR2XLTS U75 ( .A(n102), .B(n101), .Y(n103) );
NAND2X1TS U76 ( .A(add_sub), .B(in2[0]), .Y(n130) );
OR2X4TS U77 ( .A(n92), .B(n101), .Y(n93) );
NOR2XLTS U78 ( .A(n84), .B(n101), .Y(n85) );
ADDHXLTS U79 ( .A(in2[0]), .B(in1[0]), .CO(n140), .S(res[0]) );
NAND2X4TS U80 ( .A(n50), .B(n48), .Y(n47) );
XNOR2X2TS U81 ( .A(n83), .B(in2[12]), .Y(n109) );
NAND2BX4TS U82 ( .AN(in2[11]), .B(n84), .Y(n82) );
XNOR2X2TS U83 ( .A(n87), .B(in2[10]), .Y(n111) );
NOR2X4TS U84 ( .A(n86), .B(in2[10]), .Y(n84) );
NOR2X4TS U85 ( .A(in2[4]), .B(in2[3]), .Y(n72) );
XOR2X1TS U86 ( .A(n116), .B(n115), .Y(res[14]) );
AND2X2TS U87 ( .A(n71), .B(n112), .Y(n38) );
OR2X4TS U88 ( .A(n75), .B(in1[15]), .Y(n71) );
NAND2X2TS U89 ( .A(n75), .B(in1[15]), .Y(n112) );
OR2X4TS U90 ( .A(n81), .B(in1[13]), .Y(n68) );
XOR2X1TS U91 ( .A(n129), .B(n128), .Y(res[6]) );
XOR2X1TS U92 ( .A(n139), .B(n138), .Y(res[5]) );
OAI21X1TS U93 ( .A0(n33), .A1(in1[5]), .B0(n126), .Y(n129) );
NAND2BX1TS U94 ( .AN(n132), .B(n131), .Y(n134) );
OAI211X1TS U95 ( .A0(in1[2]), .A1(n143), .B0(in1[1]), .C0(n141), .Y(n132) );
OAI21X1TS U96 ( .A0(in2[0]), .A1(in2[1]), .B0(add_sub), .Y(n124) );
NAND2X8TS U97 ( .A(n47), .B(n49), .Y(n113) );
NAND2X8TS U98 ( .A(n44), .B(n121), .Y(n70) );
XOR3X1TS U99 ( .A(n70), .B(in1[8]), .C(n120), .Y(res[8]) );
NAND2X2TS U100 ( .A(n120), .B(n70), .Y(n30) );
NAND2X2TS U101 ( .A(in1[8]), .B(n120), .Y(n32) );
NAND3X6TS U102 ( .A(n31), .B(n30), .C(n32), .Y(n105) );
XNOR2X4TS U103 ( .A(n100), .B(in2[8]), .Y(n120) );
NOR2X4TS U104 ( .A(n101), .B(in2[4]), .Y(n60) );
AND2X8TS U105 ( .A(n145), .B(in1[3]), .Y(n66) );
NAND2X8TS U106 ( .A(n90), .B(n73), .Y(n95) );
AND2X6TS U107 ( .A(n92), .B(n72), .Y(n90) );
NOR2X2TS U108 ( .A(n88), .B(n101), .Y(n89) );
XNOR2X2TS U109 ( .A(n74), .B(in2[15]), .Y(n75) );
NOR2X4TS U110 ( .A(n51), .B(n114), .Y(n50) );
NAND2BX4TS U111 ( .AN(in2[7]), .B(n88), .Y(n99) );
NAND2X2TS U112 ( .A(n101), .B(in2[4]), .Y(n59) );
NAND2X6TS U113 ( .A(n58), .B(in2[4]), .Y(n57) );
NAND2X4TS U114 ( .A(n61), .B(n60), .Y(n56) );
AO22XLTS U115 ( .A0(n148), .A1(in1[4]), .B0(n145), .B1(in1[3]), .Y(n125) );
INVX4TS U116 ( .A(n61), .Y(n58) );
XNOR2X2TS U117 ( .A(n77), .B(in2[14]), .Y(n78) );
INVX12TS U118 ( .A(add_sub), .Y(n101) );
NAND2X2TS U119 ( .A(n78), .B(in1[14]), .Y(n114) );
XOR2XLTS U120 ( .A(n148), .B(n147), .Y(res[4]) );
XNOR2X1TS U121 ( .A(n127), .B(in1[6]), .Y(n128) );
NAND2X1TS U122 ( .A(n35), .B(n121), .Y(n123) );
INVX2TS U123 ( .A(in1[9]), .Y(n43) );
XNOR2X1TS U124 ( .A(n33), .B(n136), .Y(n138) );
OR2X1TS U125 ( .A(n145), .B(in1[3]), .Y(n131) );
NOR2X2TS U126 ( .A(n34), .B(n51), .Y(n115) );
NOR2X4TS U127 ( .A(n101), .B(n90), .Y(n91) );
XNOR2X1TS U128 ( .A(n105), .B(n42), .Y(res[9]) );
AND2X8TS U129 ( .A(n118), .B(n68), .Y(n34) );
OR2X4TS U130 ( .A(in1[7]), .B(n98), .Y(n35) );
NAND2X2TS U131 ( .A(n81), .B(in1[13]), .Y(n117) );
OR2X4TS U132 ( .A(n127), .B(in1[6]), .Y(n36) );
NAND2X2TS U133 ( .A(n137), .B(in1[5]), .Y(n37) );
NAND2X2TS U134 ( .A(n98), .B(in1[7]), .Y(n121) );
XOR2X1TS U135 ( .A(n104), .B(n43), .Y(n42) );
CLKXOR2X2TS U136 ( .A(n103), .B(in2[9]), .Y(n104) );
AOI31X1TS U137 ( .A0(n143), .A1(in1[2]), .A2(n131), .B0(n125), .Y(n135) );
XNOR2X2TS U138 ( .A(n124), .B(in2[2]), .Y(n143) );
NAND2X8TS U139 ( .A(n40), .B(n37), .Y(n52) );
NAND2X8TS U140 ( .A(n69), .B(n53), .Y(n40) );
XOR2X2TS U141 ( .A(n113), .B(n38), .Y(res[15]) );
OAI2BB1X4TS U142 ( .A0N(in1[9]), .A1N(n105), .B0(n41), .Y(n110) );
OAI21X4TS U143 ( .A0(n105), .A1(in1[9]), .B0(n104), .Y(n41) );
NAND2X8TS U144 ( .A(n122), .B(n35), .Y(n44) );
XOR2X4TS U145 ( .A(n89), .B(in2[7]), .Y(n98) );
NAND2X8TS U146 ( .A(n45), .B(n97), .Y(n122) );
NAND2X8TS U147 ( .A(n52), .B(n36), .Y(n45) );
NOR3X8TS U148 ( .A(in2[1]), .B(in2[0]), .C(in2[2]), .Y(n92) );
NOR2X8TS U149 ( .A(n118), .B(n117), .Y(n51) );
OAI21X4TS U150 ( .A0(n34), .A1(n51), .B0(n39), .Y(n49) );
NAND2X8TS U151 ( .A(n55), .B(n54), .Y(n53) );
NAND2X8TS U152 ( .A(n66), .B(n94), .Y(n55) );
NAND3X8TS U153 ( .A(n57), .B(n56), .C(n59), .Y(n148) );
NOR2X8TS U154 ( .A(n148), .B(in1[4]), .Y(n133) );
NAND4X8TS U155 ( .A(n65), .B(n64), .C(n63), .D(n62), .Y(n61) );
XNOR2X1TS U156 ( .A(n119), .B(n118), .Y(res[13]) );
XNOR2X1TS U157 ( .A(n123), .B(n122), .Y(res[7]) );
XNOR2X4TS U158 ( .A(n93), .B(in2[3]), .Y(n145) );
XNOR2X4TS U159 ( .A(n96), .B(in2[6]), .Y(n127) );
AND2X4TS U160 ( .A(n148), .B(in1[4]), .Y(n67) );
INVX2TS U161 ( .A(in2[5]), .Y(n73) );
CLKXOR2X2TS U162 ( .A(n85), .B(in2[11]), .Y(n107) );
XOR2X4TS U163 ( .A(n91), .B(in2[5]), .Y(n137) );
ADDFHX4TS U164 ( .A(n107), .B(in1[11]), .CI(n106), .CO(n108), .S(res[11]) );
ADDFHX4TS U165 ( .A(n109), .B(in1[12]), .CI(n108), .CO(n118), .S(res[12]) );
ADDFHX4TS U166 ( .A(n111), .B(in1[10]), .CI(n110), .CO(n106), .S(res[10]) );
OAI2BB2XLTS U167 ( .B0(n135), .B1(n133), .A0N(n137), .A1N(in1[5]), .Y(n126)
);
XNOR2X1TS U168 ( .A(n130), .B(in2[1]), .Y(n141) );
AOI21X1TS U169 ( .A0(n135), .A1(n134), .B0(n133), .Y(n139) );
INVX2TS U170 ( .A(in1[5]), .Y(n136) );
CMPR32X2TS U171 ( .A(in1[1]), .B(n141), .C(n140), .CO(n142), .S(res[1]) );
CMPR32X2TS U172 ( .A(in1[2]), .B(n143), .C(n142), .CO(n144), .S(res[2]) );
CMPR32X2TS U173 ( .A(in1[3]), .B(n145), .C(n144), .CO(n146), .S(res[3]) );
XOR2X1TS U174 ( .A(in1[4]), .B(n146), .Y(n147) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_GeArN8R1P4_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_PP_SYMBOL_V
`define SKY130_FD_SC_LS__FILL_PP_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fill (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V
/**
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer,
* vpb/vnb taps, double-row-height
* cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V |
/*
Distributed under the MIT license.
Copyright (c) 2016 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`timescale 1ps / 1ps
`define MAJOR_VERSION 1
`define MINOR_VERSION 0
`define REVISION 0
`define MAJOR_RANGE 31:28
`define MINOR_RANGE 27:20
`define REVISION_RANGE 19:16
module axi_nes #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 32,
parameter AXIS_WIDTH = 24,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter INVERT_AXI_RESET = 1,
parameter INVERT_AXIS_RESET = 1,
parameter CLOCK_RATE = 100000000,
parameter FPS = 60,
parameter FRAME_WIDTH = 480,
parameter FRAME_HEIGHT = 272,
parameter X_OFFSET = 112,
parameter Y_OFFSET = 6,
parameter BG_COLOR = 0
)(
input clk,
input rst,
//AXI Lite Interface
//Write Address Channel
input i_awvalid,
input [ADDR_WIDTH - 1: 0] i_awaddr,
output o_awready,
//Write Data Channel
input i_wvalid,
output o_wready,
input [STROBE_WIDTH - 1:0] i_wstrb,
input [DATA_WIDTH - 1: 0] i_wdata,
//Write Response Channel
output o_bvalid,
input i_bready,
output [1:0] o_bresp,
//Read Address Channel
input i_arvalid,
output o_arready,
input [ADDR_WIDTH - 1: 0] i_araddr,
//Read Data Channel
output o_rvalid,
input i_rready,
output [1:0] o_rresp,
output [DATA_WIDTH - 1: 0] o_rdata,
//AXI Stream Output
input i_axis_clk,
input i_axis_rst,
output [3:0] o_axis_user,
output [AXIS_WIDTH - 1:0] o_axis_data,
input i_axis_ready,
output o_axis_last,
output o_axis_valid
);
//local parameters
//Address Map
localparam REG_CONTROL = 0;
localparam REG_STATUS = 1;
localparam REG_USER_INPUT = 2;
localparam REG_HCI_OPCODE_COUNT = 3;
localparam REG_HCI_OPCODE_ADDR = 4;
localparam REG_HCI_OPCODE = 5;
localparam REG_HCI_OPCODE_DATA = 6;
localparam REG_HCI_READ_STB = 7;
localparam REG_IMAGE_WIDTH = 8;
localparam REG_IMAGE_HEIGHT = 9;
localparam REG_IMAGE_SIZE = 10;
localparam REG_VERSION = 11;
//Control
localparam CONTROL_HCI_RESET = 0;
localparam CONTROL_CONSOLE_RESET = 1;
//Status
localparam STATUS_CLOCK_LOCKED = 0;
localparam STATUS_HCI_READY = 1;
localparam STATUS_HCI_NEW_STATUS = 2;
localparam STATUS_HCI_S_BOT = 16;
localparam STATUS_HCI_S_TOP = STATUS_HCI_S_BOT + 15;
//Register/Wire
//AXI Signals
reg [31:0] control;
wire [31:0] status;
//Simple User Interface
wire [ADDR_WIDTH - 1: 0] w_reg_address;
wire [((ADDR_WIDTH - 1) - 2): 0] w_reg_32bit_address;
reg r_reg_invalid_addr;
wire w_reg_in_rdy;
reg r_reg_in_ack_stb;
wire [DATA_WIDTH - 1: 0] w_reg_in_data;
wire w_reg_out_req;
reg r_reg_out_rdy_stb;
reg [DATA_WIDTH - 1: 0] r_reg_out_data;
wire w_axi_rst;
//NES Signals
reg r_console_reset;
wire [3:0] w_mute_control;
reg [7:0] r_jp1_state;
reg [7:0] r_jp2_state;
wire w_video_act;
wire w_sof_stb;
wire w_sol_stb;
wire [2:0] w_red;
wire [2:0] w_green;
wire [1:0] w_blue;
//HCI Interface
reg r_hci_reset;
reg [7:0] r_hci_opcode;
reg r_hci_opcode_strobe;
wire [15:0] w_hci_opcode_status;
reg [15:0] r_hci_opcode_status;
wire w_hci_opcode_ack;
reg r_hci_opcode_new_status;
reg [15:0] r_hci_address;
reg [31:0] r_hci_count;
reg r_hci_din_strobe;
wire w_hci_sm_ready;
reg [7:0] r_hci_din;
wire w_hci_dout_strobe;
reg r_hci_host_ready;
wire [7:0] w_hci_dout;
reg [7:0] r_hci_dout;
wire [23:0] w_rfifo_size;
wire [24:0] w_rfifo_data;
wire w_rfifo_act;
wire w_rfifo_stb;
wire w_rfifo_rdy;
wire [7:0] w_video_red;
wire [7:0] w_video_green;
wire [7:0] w_video_blue;
wire w_audio;
wire w_axis_rst;
//Submodules
/*
image_to_block_fifo i2bf (
.clk (clk ),
.axis_clk (i_axis_clk ),
.rst (w_axi_rst ),
.i_enable (w_enable_dma ),
.i_video_hsync (w_video_act ),
.i_sof_stb (w_sof_stb ),
.i_red (w_red ),
.i_green (w_green ),
.i_blue (w_blue ),
.o_rfifo_ready (w_rfifo_rdy ),
.i_rfifo_activate (w_rfifo_activate ),
.i_rfifo_strobe (w_rfifo_strobe ),
.o_rfifo_data (w_rfifo_data ),
.o_rfifo_size (w_rfifo_size )
);
*/
video_to_block_fifo #(
.BUFFER_SIZE (AXIS_WIDTH )
)v2bf(
//universal input
.clk (clk ),
.rst (w_axi_rst ),
//.i_enable (w_enable_dma ),
.i_enable (1'b1 ),
//Video In
.i_video_hsync (w_video_act ),
.i_video_sof_stb (w_sof_stb ),
.i_red (w_video_red ),
.i_green (w_video_green ),
.i_blue (w_video_blue ),
//Read Path
.i_rfifo_clk (i_axis_clk ),
.i_rfifo_rst (w_axis_rst ),
.o_rfifo_ready (w_rfifo_rdy ),
.i_rfifo_activate (w_rfifo_act ),
.i_rfifo_strobe (w_rfifo_stb ),
.o_rfifo_data (w_rfifo_data ),
.o_rfifo_size (w_rfifo_size )
);
//Take in an PPFIFO incomming video data and output an AXI Stream
adapter_ppfifo_2_axi_stream #(
.DATA_WIDTH (AXIS_WIDTH )
) as2p (
.rst (w_axis_rst ),
//Incomming PPFIFO
.i_ppfifo_rdy (w_rfifo_rdy ),
.o_ppfifo_act (w_rfifo_act ),
.i_ppfifo_size (w_rfifo_size ),
.o_ppfifo_stb (w_rfifo_stb ),
.i_ppfifo_data (w_rfifo_data ),
//AXI Stream Output
.i_axi_clk (i_axis_clk ),
.i_axi_ready (i_axis_ready ),
.o_axi_data (o_axis_data ),
.o_axi_last (o_axis_last ),
.o_axi_valid (o_axis_valid ),
.o_axi_user (o_axis_user )
);
nes_top #(
.CLOCK_RATE (CLOCK_RATE ),
.FPS (FPS ),
//Should be at the center of the screen
.FRAME_WIDTH (FRAME_WIDTH ),
.FRAME_HEIGHT (FRAME_HEIGHT ),
.X_OFFSET (X_OFFSET ),
.Y_OFFSET (Y_OFFSET ),
.BG_COLOR (BG_COLOR )
)nes (
.clk (clk ),
.rst (w_axi_rst ),
.i_console_reset (r_console_reset ),
.i_mute_control (w_mute_control ),
.i_jp1_state (r_jp1_state ),
.i_jp2_state (r_jp2_state ),
.o_audio (w_audio ),
//Video
.o_video_hsync (w_video_act ),
.o_sof_stb (w_sof_stb ),
.o_red (w_red ),
.o_green (w_green ),
.o_blue (w_blue ),
//HCI Interface
.i_hci_reset (r_hci_reset ),
.i_hci_opcode (r_hci_opcode ),
.i_hci_opcode_strobe (r_hci_opcode_strobe ),
.o_hci_opcode_status (w_hci_opcode_status ),
.o_hci_opcode_ack (w_hci_opcode_ack ),
.i_hci_address (r_hci_address ),
.i_hci_count (r_hci_count ),
.i_hci_data_strobe (r_hci_din_strobe ),
.o_hci_sm_ready (w_hci_sm_ready ),
.i_hci_data (r_hci_din ),
.o_hci_data_strobe (w_hci_dout_strobe ),
.i_hci_host_ready (r_hci_host_ready ),
.o_hci_data (w_hci_dout )
);
//Convert AXI Slave signals to a simple register/address strobe
axi_lite_slave #(
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH )
) axi_lite_reg_interface (
.clk (clk ),
.rst (w_axis_rst ),
.i_awvalid (i_awvalid ),
.i_awaddr (i_awaddr ),
.o_awready (o_awready ),
.i_wvalid (i_wvalid ),
.o_wready (o_wready ),
.i_wstrb (i_wstrb ),
.i_wdata (i_wdata ),
.o_bvalid (o_bvalid ),
.i_bready (i_bready ),
.o_bresp (o_bresp ),
.i_arvalid (i_arvalid ),
.o_arready (o_arready ),
.i_araddr (i_araddr ),
.o_rvalid (o_rvalid ),
.i_rready (i_rready ),
.o_rresp (o_rresp ),
.o_rdata (o_rdata ),
.o_reg_address (w_reg_address ),
.i_reg_invalid_addr (r_reg_invalid_addr ),
.o_reg_in_rdy (w_reg_in_rdy ),
.i_reg_in_ack_stb (r_reg_in_ack_stb ),
.o_reg_in_data (w_reg_in_data ),
.o_reg_out_req (w_reg_out_req ),
.i_reg_out_rdy_stb (r_reg_out_rdy_stb ),
.i_reg_out_data (r_reg_out_data )
);
//assign status[STATUS_CLOCK_LOCKED] = clk_locked;
assign status[STATUS_CLOCK_LOCKED] = 1'b0;
assign status[STATUS_HCI_READY] = w_hci_sm_ready;
//assign status[STATUS_HCI_NEW_STATUS] = r_hci_opcode_new_status;
assign status[STATUS_HCI_NEW_STATUS] = 1'b0;
assign status[STATUS_HCI_S_TOP:STATUS_HCI_S_BOT] = r_hci_opcode_status;
assign status[15:3] = 0;
assign w_mute_control = 4'h0;
assign w_video_red = {w_red, 5'h0};
assign w_video_blue = {w_blue, 5'h0};
assign w_video_green = {w_green, 6'h0};
//Asynchronous Logic
assign w_axi_rst = (INVERT_AXI_RESET) ? ~rst : rst;
assign w_axis_rst = (INVERT_AXIS_RESET) ? ~i_axis_rst : i_axis_rst;
assign w_reg_32bit_address = w_reg_address[(ADDR_WIDTH - 1): 2];
//blocks
always @ (posedge clk) begin
//De-assert Strobes
r_reg_in_ack_stb <= 0;
r_reg_out_rdy_stb <= 0;
r_reg_invalid_addr <= 0;
r_hci_opcode_strobe <= 0;
r_hci_din_strobe <= 0;
r_hci_host_ready <= 0;
if (w_axi_rst) begin
control <= 0;
r_reg_out_data <= 0;
r_console_reset <= 1;
r_hci_reset <= 1;
//HCI
r_hci_address <= 0;
r_hci_count <= 0;
r_hci_dout <= 0;
r_hci_opcode_status <= 0;
r_hci_opcode <= 0;
r_hci_din_strobe <= 0;
r_hci_din <= 0;
r_jp1_state <= 0;
r_jp2_state <= 0;
end
else begin
if (w_hci_opcode_ack) begin
r_hci_opcode_status <= w_hci_opcode_status;
end
if (w_hci_dout_strobe) begin
r_hci_dout <= w_hci_dout;
end
if (w_reg_in_rdy && !r_reg_in_ack_stb) begin
//From master
case (w_reg_32bit_address)
REG_CONTROL: begin
r_hci_reset <= w_reg_in_data[CONTROL_HCI_RESET];
r_console_reset <= w_reg_in_data[CONTROL_CONSOLE_RESET];
end
REG_USER_INPUT: begin
r_jp1_state <= w_reg_in_data[7:0];
r_jp2_state <= w_reg_in_data[15:8];
end
REG_HCI_OPCODE_COUNT: begin
r_hci_count <= w_reg_in_data;
end
REG_HCI_OPCODE_ADDR: begin
r_hci_address <= w_reg_in_data;
end
REG_HCI_OPCODE: begin
r_hci_opcode <= w_reg_in_data;
r_hci_opcode_strobe <= 1;
end
REG_HCI_OPCODE_DATA: begin
r_hci_din <= w_reg_in_data[7:0];
r_hci_din_strobe <= 1;
end
REG_HCI_READ_STB: begin
r_hci_host_ready <= w_reg_in_data[0];
end
default: begin
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_in_ack_stb <= 1;
end
else if (w_reg_out_req && !r_reg_out_rdy_stb) begin
//To master
case (w_reg_32bit_address)
REG_CONTROL: begin
r_reg_out_data <= 32'h0;
r_reg_out_data[CONTROL_HCI_RESET] <= r_hci_reset;
r_reg_out_data[CONTROL_CONSOLE_RESET] <= r_console_reset;
end
REG_STATUS: begin
r_reg_out_data <= status;
end
REG_HCI_OPCODE_COUNT: begin
r_reg_out_data <= r_hci_count;
end
REG_HCI_OPCODE_ADDR: begin
r_reg_out_data <= r_hci_address;
end
REG_HCI_OPCODE: begin
r_reg_out_data <= r_hci_opcode;
end
REG_HCI_OPCODE_DATA: begin
r_reg_out_data <= {24'h000000, r_hci_dout};
end
REG_VERSION: begin
r_reg_out_data <= 32'h00;
r_reg_out_data[`MAJOR_RANGE] <= `MAJOR_VERSION;
r_reg_out_data[`MINOR_RANGE] <= `MINOR_VERSION;
r_reg_out_data[`REVISION_RANGE] <= `REVISION;
end
default: begin
r_reg_out_data <= 32'h00;
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_out_rdy_stb <= 1;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/11 11:43:11
// Design Name:
// Module Name: lab5_3_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab5_3_1(
input ain,reset,clk,
output reg [2:0] yout,
output reg [2:0] state,nextstate
);
parameter S0 = 0,S1 = 1,S2 = 3,S3 = 5,S4 = 7,S5 = 2;
reg [5:0] ROM [7:0];
initial $readmemb ("/home/huchao/Daily-Learning/Verilog/lab5/lab5_1/lab5_3_1/data.txt", ROM, 0, 7);
always @(posedge clk or posedge reset)
begin
if(reset)
begin
{state,yout} = ROM[0];
end
else
begin
state <= nextstate;
end
end
always @(state or ain)
begin
case(state)
S0:
begin
if(ain)
{nextstate,yout} = ROM[state];
else
nextstate = S0;
end
S1:
begin
if(ain)
{nextstate,yout} = ROM[state];
else
nextstate = S1;
end
S2:
begin
if(ain)
{nextstate,yout} = ROM[state];
else
nextstate = S2;
end
S3:
begin
if(ain)
{nextstate,yout} = ROM[state];
else
nextstate = S3;
end
S4:
begin
if(ain)
{nextstate,yout} = ROM[state];
else
nextstate = S4;
end
S5:
begin
if(ain)
{nextstate,yout} = ROM[state];
else
nextstate = S5;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:59:33 10/30/2011
// Design Name: UXA 1A
// Module Name: M_uxa_ps2_busctl
// Project Name: Kestrel-2
// Target Devices: Nexys2
// Tool versions:
// Description:
// The PS/2 interface adapter isn't worth anything if you
// cannot use a microprocessor to talk to it. Towards this
// goal, we implement a Wishbone-compatible bus interface.
// This module's purpose deals with Wishbone's control bus
// signals and bus timing/acknowledgement state machines.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module M_uxa_ps2_busctl(
input sys_clk_i,
input sys_reset_i,
input wb_we_i,
input wb_stb_i,
input wb_dat_8_i,
input wb_dat_9_i,
output wb_ack_o,
output rp_inc_o,
output c_oe_o,
output d_oe_o
);
// When reading from the I/O port, we may simply respond to
// the processor's WB_STB_I signal right away. Reading from
// the I/O port takes no action. It's assumed that other logic
// maps the q_o outputs of the FIFO module directly to the
// wb_dat_o outputs.
//
// Update -- we need to insert wait states for the Kestrel's
// specific implementation of the J1A processor, because it's
// unable to handle at-clock-rate memory accesses.
//
// Original code: assign wb_ack_o = wb_stb_i;
reg wb_ack;
assign wb_ack_o = wb_ack;
// When writing, however, we need to be more careful. First,
// we need to capture the values of the C and D signals, and
// perhaps drive the corresponding PS/2 signals low.
reg c_oe;
reg d_oe;
assign c_oe_o = c_oe;
assign d_oe_o = d_oe;
// We also want to pop the FIFO upon writing to the port.
// rp_inc_n is the next clock's value for rp_inc.
reg rp_inc;
wire rp_inc_n = (~sys_reset_i & wb_stb_i & wb_we_i);
assign rp_inc_o = rp_inc;
always @(posedge sys_clk_i) begin
if (sys_reset_i) begin
c_oe <= 0;
d_oe <= 0;
rp_inc <= 0;
wb_ack <= 0;
end else begin
wb_ack <= ~wb_ack & wb_stb_i;
rp_inc <= rp_inc_n;
if(wb_stb_i & wb_we_i) begin
c_oe <= ~wb_dat_9_i;
d_oe <= ~wb_dat_8_i;
end
end
end
endmodule
|
// hps_design_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_mm_interconnect_0 (
input wire [11:0] smp_hps_h2f_lw_axi_master_awid, // smp_hps_h2f_lw_axi_master.awid
input wire [20:0] smp_hps_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] smp_hps_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] smp_hps_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] smp_hps_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] smp_hps_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] smp_hps_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] smp_hps_h2f_lw_axi_master_awprot, // .awprot
input wire smp_hps_h2f_lw_axi_master_awvalid, // .awvalid
output wire smp_hps_h2f_lw_axi_master_awready, // .awready
input wire [11:0] smp_hps_h2f_lw_axi_master_wid, // .wid
input wire [31:0] smp_hps_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] smp_hps_h2f_lw_axi_master_wstrb, // .wstrb
input wire smp_hps_h2f_lw_axi_master_wlast, // .wlast
input wire smp_hps_h2f_lw_axi_master_wvalid, // .wvalid
output wire smp_hps_h2f_lw_axi_master_wready, // .wready
output wire [11:0] smp_hps_h2f_lw_axi_master_bid, // .bid
output wire [1:0] smp_hps_h2f_lw_axi_master_bresp, // .bresp
output wire smp_hps_h2f_lw_axi_master_bvalid, // .bvalid
input wire smp_hps_h2f_lw_axi_master_bready, // .bready
input wire [11:0] smp_hps_h2f_lw_axi_master_arid, // .arid
input wire [20:0] smp_hps_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] smp_hps_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] smp_hps_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] smp_hps_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] smp_hps_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] smp_hps_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] smp_hps_h2f_lw_axi_master_arprot, // .arprot
input wire smp_hps_h2f_lw_axi_master_arvalid, // .arvalid
output wire smp_hps_h2f_lw_axi_master_arready, // .arready
output wire [11:0] smp_hps_h2f_lw_axi_master_rid, // .rid
output wire [31:0] smp_hps_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] smp_hps_h2f_lw_axi_master_rresp, // .rresp
output wire smp_hps_h2f_lw_axi_master_rlast, // .rlast
output wire smp_hps_h2f_lw_axi_master_rvalid, // .rvalid
input wire smp_hps_h2f_lw_axi_master_rready, // .rready
input wire pll_0_outclk0_clk, // pll_0_outclk0.clk
input wire pio_0_reset_reset_bridge_in_reset_reset, // pio_0_reset_reset_bridge_in_reset.reset
input wire smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
output wire [1:0] pio_0_s1_address, // pio_0_s1.address
output wire pio_0_s1_write, // .write
input wire [31:0] pio_0_s1_readdata, // .readdata
output wire [31:0] pio_0_s1_writedata, // .writedata
output wire pio_0_s1_chipselect // .chipselect
);
wire rsp_mux_src_valid; // rsp_mux:src_valid -> smp_hps_h2f_lw_axi_master_agent:write_rp_valid
wire [111:0] rsp_mux_src_data; // rsp_mux:src_data -> smp_hps_h2f_lw_axi_master_agent:write_rp_data
wire rsp_mux_src_ready; // smp_hps_h2f_lw_axi_master_agent:write_rp_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> smp_hps_h2f_lw_axi_master_agent:write_rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> smp_hps_h2f_lw_axi_master_agent:write_rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> smp_hps_h2f_lw_axi_master_agent:write_rp_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> smp_hps_h2f_lw_axi_master_agent:read_rp_valid
wire [111:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> smp_hps_h2f_lw_axi_master_agent:read_rp_data
wire rsp_mux_001_src_ready; // smp_hps_h2f_lw_axi_master_agent:read_rp_ready -> rsp_mux_001:src_ready
wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> smp_hps_h2f_lw_axi_master_agent:read_rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> smp_hps_h2f_lw_axi_master_agent:read_rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> smp_hps_h2f_lw_axi_master_agent:read_rp_endofpacket
wire [31:0] pio_0_s1_agent_m0_readdata; // pio_0_s1_translator:uav_readdata -> pio_0_s1_agent:m0_readdata
wire pio_0_s1_agent_m0_waitrequest; // pio_0_s1_translator:uav_waitrequest -> pio_0_s1_agent:m0_waitrequest
wire pio_0_s1_agent_m0_debugaccess; // pio_0_s1_agent:m0_debugaccess -> pio_0_s1_translator:uav_debugaccess
wire [20:0] pio_0_s1_agent_m0_address; // pio_0_s1_agent:m0_address -> pio_0_s1_translator:uav_address
wire [3:0] pio_0_s1_agent_m0_byteenable; // pio_0_s1_agent:m0_byteenable -> pio_0_s1_translator:uav_byteenable
wire pio_0_s1_agent_m0_read; // pio_0_s1_agent:m0_read -> pio_0_s1_translator:uav_read
wire pio_0_s1_agent_m0_readdatavalid; // pio_0_s1_translator:uav_readdatavalid -> pio_0_s1_agent:m0_readdatavalid
wire pio_0_s1_agent_m0_lock; // pio_0_s1_agent:m0_lock -> pio_0_s1_translator:uav_lock
wire [31:0] pio_0_s1_agent_m0_writedata; // pio_0_s1_agent:m0_writedata -> pio_0_s1_translator:uav_writedata
wire pio_0_s1_agent_m0_write; // pio_0_s1_agent:m0_write -> pio_0_s1_translator:uav_write
wire [2:0] pio_0_s1_agent_m0_burstcount; // pio_0_s1_agent:m0_burstcount -> pio_0_s1_translator:uav_burstcount
wire pio_0_s1_agent_rf_source_valid; // pio_0_s1_agent:rf_source_valid -> pio_0_s1_agent_rsp_fifo:in_valid
wire [112:0] pio_0_s1_agent_rf_source_data; // pio_0_s1_agent:rf_source_data -> pio_0_s1_agent_rsp_fifo:in_data
wire pio_0_s1_agent_rf_source_ready; // pio_0_s1_agent_rsp_fifo:in_ready -> pio_0_s1_agent:rf_source_ready
wire pio_0_s1_agent_rf_source_startofpacket; // pio_0_s1_agent:rf_source_startofpacket -> pio_0_s1_agent_rsp_fifo:in_startofpacket
wire pio_0_s1_agent_rf_source_endofpacket; // pio_0_s1_agent:rf_source_endofpacket -> pio_0_s1_agent_rsp_fifo:in_endofpacket
wire pio_0_s1_agent_rsp_fifo_out_valid; // pio_0_s1_agent_rsp_fifo:out_valid -> pio_0_s1_agent:rf_sink_valid
wire [112:0] pio_0_s1_agent_rsp_fifo_out_data; // pio_0_s1_agent_rsp_fifo:out_data -> pio_0_s1_agent:rf_sink_data
wire pio_0_s1_agent_rsp_fifo_out_ready; // pio_0_s1_agent:rf_sink_ready -> pio_0_s1_agent_rsp_fifo:out_ready
wire pio_0_s1_agent_rsp_fifo_out_startofpacket; // pio_0_s1_agent_rsp_fifo:out_startofpacket -> pio_0_s1_agent:rf_sink_startofpacket
wire pio_0_s1_agent_rsp_fifo_out_endofpacket; // pio_0_s1_agent_rsp_fifo:out_endofpacket -> pio_0_s1_agent:rf_sink_endofpacket
wire pio_0_s1_agent_rdata_fifo_src_valid; // pio_0_s1_agent:rdata_fifo_src_valid -> pio_0_s1_agent_rdata_fifo:in_valid
wire [33:0] pio_0_s1_agent_rdata_fifo_src_data; // pio_0_s1_agent:rdata_fifo_src_data -> pio_0_s1_agent_rdata_fifo:in_data
wire pio_0_s1_agent_rdata_fifo_src_ready; // pio_0_s1_agent_rdata_fifo:in_ready -> pio_0_s1_agent:rdata_fifo_src_ready
wire smp_hps_h2f_lw_axi_master_agent_write_cp_valid; // smp_hps_h2f_lw_axi_master_agent:write_cp_valid -> router:sink_valid
wire [111:0] smp_hps_h2f_lw_axi_master_agent_write_cp_data; // smp_hps_h2f_lw_axi_master_agent:write_cp_data -> router:sink_data
wire smp_hps_h2f_lw_axi_master_agent_write_cp_ready; // router:sink_ready -> smp_hps_h2f_lw_axi_master_agent:write_cp_ready
wire smp_hps_h2f_lw_axi_master_agent_write_cp_startofpacket; // smp_hps_h2f_lw_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
wire smp_hps_h2f_lw_axi_master_agent_write_cp_endofpacket; // smp_hps_h2f_lw_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [111:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire smp_hps_h2f_lw_axi_master_agent_read_cp_valid; // smp_hps_h2f_lw_axi_master_agent:read_cp_valid -> router_001:sink_valid
wire [111:0] smp_hps_h2f_lw_axi_master_agent_read_cp_data; // smp_hps_h2f_lw_axi_master_agent:read_cp_data -> router_001:sink_data
wire smp_hps_h2f_lw_axi_master_agent_read_cp_ready; // router_001:sink_ready -> smp_hps_h2f_lw_axi_master_agent:read_cp_ready
wire smp_hps_h2f_lw_axi_master_agent_read_cp_startofpacket; // smp_hps_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
wire smp_hps_h2f_lw_axi_master_agent_read_cp_endofpacket; // smp_hps_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [111:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire pio_0_s1_agent_rp_valid; // pio_0_s1_agent:rp_valid -> router_002:sink_valid
wire [111:0] pio_0_s1_agent_rp_data; // pio_0_s1_agent:rp_data -> router_002:sink_data
wire pio_0_s1_agent_rp_ready; // router_002:sink_ready -> pio_0_s1_agent:rp_ready
wire pio_0_s1_agent_rp_startofpacket; // pio_0_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire pio_0_s1_agent_rp_endofpacket; // pio_0_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [111:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> pio_0_s1_burst_adapter:sink0_valid
wire [111:0] cmd_mux_src_data; // cmd_mux:src_data -> pio_0_s1_burst_adapter:sink0_data
wire cmd_mux_src_ready; // pio_0_s1_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> pio_0_s1_burst_adapter:sink0_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> pio_0_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> pio_0_s1_burst_adapter:sink0_endofpacket
wire pio_0_s1_burst_adapter_source0_valid; // pio_0_s1_burst_adapter:source0_valid -> pio_0_s1_agent:cp_valid
wire [111:0] pio_0_s1_burst_adapter_source0_data; // pio_0_s1_burst_adapter:source0_data -> pio_0_s1_agent:cp_data
wire pio_0_s1_burst_adapter_source0_ready; // pio_0_s1_agent:cp_ready -> pio_0_s1_burst_adapter:source0_ready
wire [1:0] pio_0_s1_burst_adapter_source0_channel; // pio_0_s1_burst_adapter:source0_channel -> pio_0_s1_agent:cp_channel
wire pio_0_s1_burst_adapter_source0_startofpacket; // pio_0_s1_burst_adapter:source0_startofpacket -> pio_0_s1_agent:cp_startofpacket
wire pio_0_s1_burst_adapter_source0_endofpacket; // pio_0_s1_burst_adapter:source0_endofpacket -> pio_0_s1_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [111:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [111:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [111:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [111:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire pio_0_s1_agent_rdata_fifo_out_valid; // pio_0_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
wire [33:0] pio_0_s1_agent_rdata_fifo_out_data; // pio_0_s1_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
wire pio_0_s1_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> pio_0_s1_agent_rdata_fifo:out_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> pio_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> pio_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // pio_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> pio_0_s1_agent:rdata_fifo_sink_error
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pio_0_s1_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (pio_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pio_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pio_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (pio_0_s1_agent_m0_read), // .read
.uav_write (pio_0_s1_agent_m0_write), // .write
.uav_waitrequest (pio_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pio_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pio_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (pio_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (pio_0_s1_agent_m0_writedata), // .writedata
.uav_lock (pio_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (pio_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (pio_0_s1_address), // avalon_anti_slave_0.address
.av_write (pio_0_s1_write), // .write
.av_readdata (pio_0_s1_readdata), // .readdata
.av_writedata (pio_0_s1_writedata), // .writedata
.av_chipselect (pio_0_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (84),
.PKT_CACHE_H (106),
.PKT_CACHE_L (103),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_PROTECTION_H (102),
.PKT_PROTECTION_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_RESPONSE_STATUS_L (107),
.PKT_RESPONSE_STATUS_H (108),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (62),
.PKT_TRANS_LOCK (61),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_THREAD_ID_H (99),
.PKT_THREAD_ID_L (88),
.PKT_QOS_L (85),
.PKT_QOS_H (85),
.PKT_ORI_BURST_SIZE_L (109),
.PKT_ORI_BURST_SIZE_H (111),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.ID (0)
) smp_hps_h2f_lw_axi_master_agent (
.aclk (pll_0_outclk0_clk), // clk.clk
.aresetn (~smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (smp_hps_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (smp_hps_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (smp_hps_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (smp_hps_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (smp_hps_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (rsp_mux_src_valid), // write_rp.valid
.write_rp_data (rsp_mux_src_data), // .data
.write_rp_channel (rsp_mux_src_channel), // .channel
.write_rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.write_rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.write_rp_ready (rsp_mux_src_ready), // .ready
.read_cp_valid (smp_hps_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (smp_hps_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (smp_hps_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (smp_hps_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (smp_hps_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (rsp_mux_001_src_valid), // read_rp.valid
.read_rp_data (rsp_mux_001_src_data), // .data
.read_rp_channel (rsp_mux_001_src_channel), // .channel
.read_rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.read_rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.read_rp_ready (rsp_mux_001_src_ready), // .ready
.awid (smp_hps_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (smp_hps_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (smp_hps_h2f_lw_axi_master_awlen), // .awlen
.awsize (smp_hps_h2f_lw_axi_master_awsize), // .awsize
.awburst (smp_hps_h2f_lw_axi_master_awburst), // .awburst
.awlock (smp_hps_h2f_lw_axi_master_awlock), // .awlock
.awcache (smp_hps_h2f_lw_axi_master_awcache), // .awcache
.awprot (smp_hps_h2f_lw_axi_master_awprot), // .awprot
.awvalid (smp_hps_h2f_lw_axi_master_awvalid), // .awvalid
.awready (smp_hps_h2f_lw_axi_master_awready), // .awready
.wid (smp_hps_h2f_lw_axi_master_wid), // .wid
.wdata (smp_hps_h2f_lw_axi_master_wdata), // .wdata
.wstrb (smp_hps_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (smp_hps_h2f_lw_axi_master_wlast), // .wlast
.wvalid (smp_hps_h2f_lw_axi_master_wvalid), // .wvalid
.wready (smp_hps_h2f_lw_axi_master_wready), // .wready
.bid (smp_hps_h2f_lw_axi_master_bid), // .bid
.bresp (smp_hps_h2f_lw_axi_master_bresp), // .bresp
.bvalid (smp_hps_h2f_lw_axi_master_bvalid), // .bvalid
.bready (smp_hps_h2f_lw_axi_master_bready), // .bready
.arid (smp_hps_h2f_lw_axi_master_arid), // .arid
.araddr (smp_hps_h2f_lw_axi_master_araddr), // .araddr
.arlen (smp_hps_h2f_lw_axi_master_arlen), // .arlen
.arsize (smp_hps_h2f_lw_axi_master_arsize), // .arsize
.arburst (smp_hps_h2f_lw_axi_master_arburst), // .arburst
.arlock (smp_hps_h2f_lw_axi_master_arlock), // .arlock
.arcache (smp_hps_h2f_lw_axi_master_arcache), // .arcache
.arprot (smp_hps_h2f_lw_axi_master_arprot), // .arprot
.arvalid (smp_hps_h2f_lw_axi_master_arvalid), // .arvalid
.arready (smp_hps_h2f_lw_axi_master_arready), // .arready
.rid (smp_hps_h2f_lw_axi_master_rid), // .rid
.rdata (smp_hps_h2f_lw_axi_master_rdata), // .rdata
.rresp (smp_hps_h2f_lw_axi_master_rresp), // .rresp
.rlast (smp_hps_h2f_lw_axi_master_rlast), // .rlast
.rvalid (smp_hps_h2f_lw_axi_master_rvalid), // .rvalid
.rready (smp_hps_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (1'b0), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (111),
.PKT_ORI_BURST_SIZE_L (109),
.PKT_RESPONSE_STATUS_H (108),
.PKT_RESPONSE_STATUS_L (107),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_LOCK (61),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (102),
.PKT_PROTECTION_L (100),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (112),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) pio_0_s1_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (pio_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pio_0_s1_agent_m0_address), // m0.address
.m0_burstcount (pio_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (pio_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pio_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (pio_0_s1_agent_m0_lock), // .lock
.m0_readdata (pio_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (pio_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pio_0_s1_agent_m0_read), // .read
.m0_waitrequest (pio_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pio_0_s1_agent_m0_writedata), // .writedata
.m0_write (pio_0_s1_agent_m0_write), // .write
.rp_endofpacket (pio_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pio_0_s1_agent_rp_ready), // .ready
.rp_valid (pio_0_s1_agent_rp_valid), // .valid
.rp_data (pio_0_s1_agent_rp_data), // .data
.rp_startofpacket (pio_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (pio_0_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (pio_0_s1_burst_adapter_source0_valid), // .valid
.cp_data (pio_0_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (pio_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (pio_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (pio_0_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (pio_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pio_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pio_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pio_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pio_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pio_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pio_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pio_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pio_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pio_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (pio_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pio_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pio_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (113),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pio_0_s1_agent_rsp_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (pio_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pio_0_s1_agent_rf_source_data), // in.data
.in_valid (pio_0_s1_agent_rf_source_valid), // .valid
.in_ready (pio_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (pio_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pio_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (pio_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (pio_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (pio_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pio_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pio_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pio_0_s1_agent_rdata_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (pio_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pio_0_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (pio_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (pio_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (pio_0_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (pio_0_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (pio_0_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
hps_design_mm_interconnect_0_router router (
.sink_ready (smp_hps_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (smp_hps_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (smp_hps_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (smp_hps_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (smp_hps_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_router router_001 (
.sink_ready (smp_hps_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (smp_hps_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (smp_hps_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (smp_hps_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (smp_hps_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_router_002 router_002 (
.sink_ready (pio_0_s1_agent_rp_ready), // sink.ready
.sink_valid (pio_0_s1_agent_rp_valid), // .valid
.sink_data (pio_0_s1_agent_rp_data), // .data
.sink_startofpacket (pio_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pio_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (pio_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) pio_0_s1_burst_adapter (
.clk (pll_0_outclk0_clk), // cr0.clk
.reset (pio_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (pio_0_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (pio_0_s1_burst_adapter_source0_data), // .data
.source0_channel (pio_0_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (pio_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (pio_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (pio_0_s1_burst_adapter_source0_ready) // .ready
);
hps_design_mm_interconnect_0_cmd_demux cmd_demux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_cmd_demux cmd_demux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_cmd_mux cmd_mux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (pio_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_rsp_demux rsp_demux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (pio_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_rsp_mux rsp_mux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_rsp_mux rsp_mux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
hps_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (pll_0_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (pio_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (pio_0_s1_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (pio_0_s1_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (pio_0_s1_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule
|
module testbench_BoothPPG_32R4_NORM();
reg[31:0] mulcand;
reg[2:0] r4input;
reg sign;
wire[33:0] pp;
reg[33:0] expectPP;
task check(input [31:0]cand);
reg[3:0] i;
reg errorFlag;
begin
errorFlag = 0;
mulcand = cand;
sign = 1;
for(i = 4'b0;i <= 4'b0111; i = i+1) begin
r4input = i;
case(i[2:0])
3'b000: expectPP[32:0] = 33'b0;
3'b001: expectPP[32:0] = {cand[31], cand[31:0]};
3'b010: expectPP[32:0] = {cand[31], cand[31:0]};
3'b011: expectPP[32:0] = {cand[31:0], 1'b0};
3'b100: expectPP[32:0] = ~{cand[31:0], 1'b0};
3'b101: expectPP[32:0] = ~{cand[31], cand[31:0]};
3'b110: expectPP[32:0] = ~{cand[31], cand[31:0]};
3'b111: expectPP[32:0] = ~33'b0;
endcase
expectPP[33] = expectPP[32];
#10;
if(pp !== expectPP) begin
$display("fail: cand = %x, r4input = %3b, sign = %x, expect pp = %x, but actual pp = %x", cand , r4input, sign, expectPP, pp);
errorFlag = 1;
end
end
sign = 0;
for(i = 4'b0;i <= 4'b0111; i = i+1) begin
r4input = i;
case(i[2:0])
3'b000: expectPP[32:0] = 33'b0;
3'b001: expectPP[32:0] = {1'b0, cand[31:0]};
3'b010: expectPP[32:0] = {1'b0, cand[31:0]};
3'b011: expectPP[32:0] = {cand[31:0], 1'b0};
3'b100: expectPP[32:0] = ~{cand[31:0], 1'b0};
3'b101: expectPP[32:0] = ~{1'b0, cand[31:0]};
3'b110: expectPP[32:0] = ~{1'b0, cand[31:0]};
3'b111: expectPP[32:0] = ~33'b0;
endcase
expectPP[33] = r4input[2];
#10;
if(pp !== expectPP) begin
$display("fail: cand = %x, r4input = %3b, sign = %x, expect pp = %x, but actual pp = %x", cand , r4input, sign, expectPP, pp);
errorFlag = 1;
end
end
if(errorFlag === 0) begin
$display("mulcand = %x passed", cand);
end
else begin
$display("mulcand = %x failed", cand);
end
end
endtask
integer loopchk;
initial begin
for(loopchk = 0; loopchk < 100; loopchk = loopchk+1) begin
check($random());
end
check(32'h00000001);
check(32'h00000001);
check(32'h10000001);
check(32'hffffffff);
check(32'hdeadbeef);
end
BoothPPG_32R4_NORM ppg(.mulcand(mulcand), .r4input(r4input), .sign(sign), .pp(pp));
endmodule
|
(** * Rel: Properties of Relations *)
(** This short (and optional) chapter develops some basic definitions
and a few theorems about binary relations in Coq. The key
definitions are repeated where they are actually used (in the
[Smallstep] chapter), so readers who are already comfortable with
these ideas can safely skim or skip this chapter. However,
relations are also a good source of exercises for developing
facility with Coq's basic reasoning facilities, so it may be
useful to look at this material just after the [IndProp]
chapter. *)
Require Export IndProp.
Require Import Coq.omega.Omega.
(** A binary _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X -> X -> Prop.
(** Confusingly, the Coq standard library hijacks the generic term
"relation" for this specific instance of the idea. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, whereas the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-than-or-equal-to
relation, which we usually write [n1 <= n2]. *)
Print le.
(* ====> Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m *)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(** (Why did we write it this way instead of starting with [Inductive
le : relation nat...]? Because we wanted to put the first [nat]
to the left of the [:], which makes Coq generate a somewhat nicer
induction principle for reasoning about [<=].) *)
(* ################################################################# *)
(** * Basic Properties *)
(** As anyone knows who has taken an undergraduate discrete math
course, there is a lot to be said about relations in general,
including ways of classifying relations (as reflexive, transitive,
etc.), theorems that can be proved generically about certain sorts
of relations, constructions that build one relation from another,
etc. For example... *)
(* ----------------------------------------------------------------- *)
(** *** Partial Functions *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., [R x y1]
and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined earlier is a partial
function. *)
Print next_nat.
(* ====> Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n) *)
Check next_nat : relation nat.
Theorem next_nat_partial_function : partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity.
Qed.
(** However, the [<=] relation on numbers is not a partial
function. (Assume, for a contradiction, that [<=] is a partial
function. But then, since [0 <= 0] and [0 <= 1], it follows that
[0 = 1]. This is nonsense, so our assumption was
contradictory.) *)
Theorem le_not_a_partial_function : ~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense. {
apply Hc with (x := 0).
- apply le_n.
- apply le_S. apply le_n. }
inversion Nonsense.
Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in earlier is not a partial
function. *)
Theorem total_relation_is_not_a_partial_function :
~ (partial_function total_relation).
Proof.
unfold not, partial_function. intros Htr.
pose proof Htr 1 2 3.
assert (t1 : total_relation 1 2). apply tr_1. auto.
assert (t2 : total_relation 1 3). apply tr_1. auto.
pose proof H t1 t2. inversion H0.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] that we defined earlier is a
partial function. *)
Theorem rempty_relation_is_partial_function :
partial_function empty_relation.
Proof.
unfold partial_function. intros x y1 y2 H1 H2. inversion H2.
Qed.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Reflexive Relations *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive : reflexive le.
Proof.
unfold reflexive. intros n. apply le_n.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Transitive Relations *)
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans : transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
- (* le_n *) apply Hnm.
- (* le_S *) apply le_S. apply IHHmo.
Qed.
Theorem lt_trans: transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo.
Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using [le_trans]. Do this.*)
Lemma n_le_m__n_le_Sm : forall n m, n <= m -> n <= S m.
Proof.
intros n m Hnm. induction Hnm. auto. auto.
Qed.
Theorem lt_trans' : transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
- apply n_le_m__n_le_Sm. apply Hnm.
- apply n_le_m__n_le_Sm. apply IHHm'o.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' : transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
- inversion Hmo.
- apply le_S. inversion Hmo. rewrite <- H0.
apply Hnm. apply IHo'. apply H0.
Qed.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
- apply le_S. apply le_n.
- apply H.
Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
intros n m. intros H. inversion H. trivial.
apply le_Sn_le. apply H1.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~ (S n <= n)]
A formal proof of this is an optional exercise below, but try
writing an informal proof without doing the formal proof first.
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n, ~ (S n <= n).
Proof.
intros n. unfold not. intros H. induction n.
- inversion H.
- apply IHn. apply le_S_n. apply H.
Qed.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, let's look at a few other common ones... *)
(* ----------------------------------------------------------------- *)
(** *** Symmetric and Antisymmetric Relations *)
(** A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional *)
Theorem le_not_symmetric : ~ (symmetric le).
Proof.
unfold not, symmetric. intros.
assert (t : 0 <= 1) by omega.
pose proof H 0 1 t. inversion H0.
Qed.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional *)
Theorem le_antisymmetric : antisymmetric le.
Proof.
unfold antisymmetric. intros a b Hab Hba. omega.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Lemma le_step1 : forall n m, n < m -> S n <= m.
Proof.
intros n m Hnm. inversion Hnm. omega. omega.
Qed.
Lemma le_step2 : forall n m, S n <= S m -> n <= m.
Proof.
intros n m Hnm. omega.
Qed.
Theorem le_step : forall n m p, n < m -> m <= S p -> n <= p.
Proof.
intros n m p Hnm Hmp. apply le_step1 in Hnm. apply le_step2.
omega.
Qed.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Equivalence Relations *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(* ----------------------------------------------------------------- *)
(** *** Partial Orders and Preorders *)
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
- (* refl *) apply le_reflexive.
- split.
+ (* antisym *) apply le_antisymmetric.
+ (* transitive. *) apply le_trans. Qed.
(* ################################################################# *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y ->
clos_refl_trans R y z ->
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
- (* -> *)
intro H. induction H.
+ (* le_n *) apply rt_refl.
+ (* le_S *)
apply rt_trans with m. apply IHle. apply rt_step.
apply nn.
- (* <- *)
intro H. induction H.
+ (* rt_step *) inversion H. apply le_S. apply le_n.
+ (* rt_refl *) apply le_n.
+ (* rt_trans *)
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is natural:
it says, explicitly, that the reflexive and transitive closure of
[R] is the least relation that includes [R] and that is closed
under rules of reflexivity and transitivity. But it turns out
that this definition is not very convenient for doing proofs,
since the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions. Here is a more useful definition: *)
Inductive clos_refl_trans_1n {A : Type}
(R : relation A) (x : A)
: A -> Prop :=
| rt1n_refl : clos_refl_trans_1n R x x
| rt1n_trans (y z : A) :
R x y -> clos_refl_trans_1n R y z ->
clos_refl_trans_1n R x z.
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [clos_refl_trans_1n] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Lemma rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> clos_refl_trans_1n R x y.
Proof.
intros X R x y H.
apply rt1n_trans with y. apply H. apply rt1n_refl.
Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Lemma rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
clos_refl_trans_1n R x y ->
clos_refl_trans_1n R y z ->
clos_refl_trans_1n R x z.
Proof.
intros. induction H.
- apply H0.
- apply rt1n_trans with y. apply H.
apply IHclos_refl_trans_1n. apply H0.
Qed.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> clos_refl_trans_1n R x y.
Proof.
intros X R x y. split. intros H.
- induction H. apply rt1n_trans with y.
assumption. constructor. constructor.
apply rsc_trans with y. assumption. assumption.
- intros H. induction H. apply rt_refl. apply rt_trans with y.
apply rt_step. assumption. assumption.
Qed.
(** [] *)
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
module robo (
clk,
led0, led1, led2, led3, led4, led5, led6, led7,
servo0, servo1, servo2, servo3
);
input clk /* synthesis chip_pin = "R8" */;
output reg led0 /* synthesis chip_pin = "A15" */;
output reg led1 /* synthesis chip_pin = "A13" */;
output reg led2 /* synthesis chip_pin = "B13" */;
output reg led3 /* synthesis chip_pin = "A11" */;
output reg led4 /* synthesis chip_pin = "D1" */;
output reg led5 /* synthesis chip_pin = "F3" */;
output reg led6 /* synthesis chip_pin = "B1" */;
output reg led7 /* synthesis chip_pin = "L3" */;
output reg servo0 /* synthesis chip_pin = "B5" */; // JP1.10 GPIO_07
output reg servo1 /* synthesis chip_pin = "B4" */; // JP1.08 GPIO_05
output reg servo2 /* synthesis chip_pin = "A3" */; // JP1.06 GPIO_03
output reg servo3 /* synthesis chip_pin = "C3" */; // JP1.04 GPIO_01
/*
0.6..2.4 ms. = -90..+90 deg. 20ms -- repeat
1 ms / 40 ns = 25000 / 1024 = 24.4 [run[10]]
*/
/*
0 -- 25 MHz 40 ns
1 -- 12.5
2 -- 6.25
3 -- 3.125
4 -- 1.5
5 -- 781 KHz
6 -- 391
7 -- 195
8 -- 98khz
9 -- 49khz
10 -- 24khz
11
12
13
14
15
16
17
*/
// prescaller
reg [31:0] run;
always @(posedge clk)
run <= run + 32'b1;
// memory
reg [63:0] mem [0:255];
reg [63:0] data;
reg [7:0] ptr;
initial begin
$readmemh("ram.txt", mem);
end
always @*
data = mem[ptr];
// memory fetch timer
reg [31:0] tf;
reg tf_reset;
reg tf_en;
always @*
tf_reset = (tf === 32'd600);
always @*
tf_en = &run[10:0]; // T = 40.96 us
always @(posedge clk)
if (tf_en) begin
if (tf_reset) begin
tf <= 32'b0;
end else begin
tf <= tf + 32'b1;
end
end
always @(posedge clk)
if (tf_en & tf_reset)
ptr <= ptr + 1;
// pulse timer 0
reg [15:0] t0;
reg t0_valid;
always @*
t0_valid = |t0;
always @(posedge clk)
if (tf_en) begin
if (tf_reset) begin
t0 <= data[15:0];
end else begin
if (t0_valid) begin
t0 <= t0 - 16'b1;
end
end
end
// pulse timer 0
reg [15:0] t1;
reg t1_valid;
always @*
t1_valid = |t1;
always @(posedge clk)
if (tf_en) begin
if (tf_reset) begin
t1 <= data[31:16];
end else begin
if (t1_valid) begin
t1 <= t1 - 16'b1;
end
end
end
// pulse timer 0
reg [15:0] t2;
reg t2_valid;
always @*
t2_valid = |t2;
always @(posedge clk)
if (tf_en) begin
if (tf_reset) begin
t2 <= data[47:32];
end else begin
if (t2_valid) begin
t2 <= t2 - 16'b1;
end
end
end
// pulse timer 0
reg [15:0] t3;
reg t3_valid;
always @*
t3_valid = |t3;
always @(posedge clk)
if (tf_en) begin
if (tf_reset) begin
t3 <= data[63:48];
end else begin
if (t3_valid) begin
t3 <= t3 - 16'b1;
end
end
end
always @* begin
servo0 = t0_valid;
servo1 = t1_valid;
servo2 = t2_valid;
servo3 = t3_valid;
led0 = run[24];
led1 = run[25];
led2 = run[26];
led3 = run[27];
led4 = run[28];
led5 = run[29];
led6 = run[30];
led7 = run[31];
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.0
// \ \ Description : Xilinx Functional and Timing Simulation Library Component
// / / Onput Fixed or Variable Delay Element with Fine Adjustment.
// /___/ /\ Filename : ODELAYE2_FINEDELAY.v
// \ \ / \ Timestamp : Tue Feb 15 15:52:17 PST 2011
// \___\/\___\
//
// Revision:
// 02/15/11 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ODELAYE2_FINEDELAY (
CNTVALUEOUT,
DATAOUT,
C,
CE,
CINVCTRL,
CLKIN,
CNTVALUEIN,
INC,
LD,
LDPIPEEN,
ODATAIN,
OFDLY,
REGRST
);
parameter CINVCTRL_SEL = "FALSE";
parameter DELAY_SRC = "ODATAIN";
parameter FINEDELAY = "BYPASS";
parameter HIGH_PERFORMANCE_MODE = "FALSE";
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_ODATAIN_INVERTED = 1'b0;
parameter ODELAY_TYPE = "FIXED";
parameter integer ODELAY_VALUE = 0;
parameter PIPE_SEL = "FALSE";
parameter real REFCLK_FREQUENCY = 200.0;
parameter SIGNAL_PATTERN = "DATA";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter integer SIM_DELAY_D = 0;
localparam DELAY_D = (ODELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
`endif // ifdef XIL_TIMING
`ifndef XIL_TIMING
integer DELAY_D=0;
`endif // ifndef XIL_TIMING
output [4:0] CNTVALUEOUT;
output DATAOUT;
input C;
input CE;
input CINVCTRL;
input CLKIN;
input [4:0] CNTVALUEIN;
input INC;
input LD;
input LDPIPEEN;
input ODATAIN;
input [2:0] OFDLY;
input REGRST;
tri0 GSR = glbl.GSR;
real CALC_TAPDELAY_RD ; // regular tap delay
real CALC_TAPDELAY_FD ; // fine tap delay
real INIT_DELAY_RD;
real INIT_DELAY_FD;
//------------------- constants ------------------------------------
localparam MAX_DELAY_COUNT = 31;
localparam MIN_DELAY_COUNT = 0;
localparam MAX_REFCLK_FREQUENCYL = 210.0;
localparam MIN_REFCLK_FREQUENCYL = 190.0;
localparam MAX_REFCLK_FREQUENCYH = 410.0;
localparam MIN_REFCLK_FREQUENCYH = 290.0;
//------------------- variable declaration -------------------------
integer odelay_count;
integer CNTVALUEIN_INTEGER;
reg [4:0] cntvalueout_pre;
reg notifier;
reg data_mux = 0;
reg tap_out_rd = 0;
reg tap_out_fd = 0;
reg tap_out_final = 0;
reg DATAOUT_reg = 0;
wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3,
delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7,
delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11,
delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15,
delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19,
delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23,
delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27,
delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31;
wire fine_delay_0, fine_delay_1, fine_delay_2, fine_delay_3, fine_delay_4, fine_delay_5;
reg c_in;
wire c_in_pre,delay_c;
wire ce_in,delay_ce;
wire cinvctrl_in,delay_cinvctrl;
wire clkin_in,delay_clkin;
wire [4:0] cntvaluein_in,delay_cntvaluein;
wire odatain_in,delay_odatain;
wire ofdly_in,delay_ofdly;
wire gsr_in;
wire inc_in,delay_inc;
wire ld_in,delay_ld;
wire ldpipeen_in,delay_ldpipeen;
wire regrst_in,delay_regrst;
reg [4:0] qcntvalueout_reg = 5'b0;
reg [4:0] qcntvalueout_mux = 5'b0;
//----------------------------------------------------------------------
//------------------------------- Output ------------------------------
//----------------------------------------------------------------------
generate
case (FINEDELAY)
"BYPASS" : always @(tap_out_rd) tap_out_final = tap_out_rd;
"ADD_DLY" : always @(tap_out_fd) tap_out_final = tap_out_fd;
endcase
endgenerate
// CR 587496
// assign #INIT_DELAY DATAOUT = tap_out_final;
always @(tap_out_final)
DATAOUT_reg <= #INIT_DELAY_RD tap_out_final;
assign DATAOUT = DATAOUT_reg;
assign CNTVALUEOUT = cntvalueout_pre;
`ifndef XIL_TIMING
//----------------------------------------------------------------------
//------------------------------- Input -------------------------------
//----------------------------------------------------------------------
assign delay_c = C;
assign delay_ce = CE;
assign delay_cntvaluein = CNTVALUEIN;
assign delay_inc = INC;
assign delay_ld = LD;
assign delay_ldpipeen = LDPIPEEN;
assign delay_regrst = REGRST;
`endif // ifndef XIL_TIMING
assign delay_cinvctrl = CINVCTRL;
assign delay_clkin = CLKIN;
assign delay_odatain = ODATAIN;
assign delay_ofdly = OFDLY;
assign gsr_in = GSR;
assign c_in_pre = IS_C_INVERTED ^ delay_c;
assign ce_in = delay_ce;
assign cntvaluein_in = delay_cntvaluein;
assign inc_in = delay_inc;
assign ld_in = delay_ld;
assign ldpipeen_in = delay_ldpipeen;
assign regrst_in = delay_regrst;
assign cinvctrl_in = delay_cinvctrl;
assign clkin_in = delay_clkin;
assign odatain_in = IS_ODATAIN_INVERTED ^ delay_odatain;
assign ofdly_in = delay_ofdly;
//*** GLOBAL hidden GSR pin
always @(gsr_in) begin
if (gsr_in == 1'b1) begin
// For simprims, the fixed Delay values are taken from the sdf.
if (ODELAY_TYPE == "FIXED")
assign odelay_count = 0;
else
assign odelay_count = ODELAY_VALUE;
end
else if (gsr_in == 1'b0) begin
deassign odelay_count;
end
end
//------------------------------------------------------------
//--------------------- Initialization --------------------
//------------------------------------------------------------
initial begin
//-------- CINVCTRL_SEL check
case (CINVCTRL_SEL)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CINVCTRL_SEL on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CINVCTRL_SEL);
#1 $finish;
end
endcase
//-------- DELAY_SRC check
if (DELAY_SRC != "ODATAIN" && DELAY_SRC != "CLKIN") begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are ODATAIN or CLKIN", DELAY_SRC);
#1 $finish;
end
//-------- FINEDELAY check
if (FINEDELAY != "BYPASS" && FINEDELAY != "ADD_DLY") begin
$display("Attribute Syntax Error : The attribute FINEDELAY on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are BYPASS or ADD_DLY", FINEDELAY);
#1 $finish;
end
//-------- HIGH_PERFORMANCE_MODE check
case (HIGH_PERFORMANCE_MODE)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute HIGH_PERFORMANCE_MODE on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", HIGH_PERFORMANCE_MODE);
#1 $finish;
end
endcase
//-------- ODELAY_TYPE check
if (ODELAY_TYPE != "FIXED" && ODELAY_TYPE != "VARIABLE" && ODELAY_TYPE != "VAR_LOAD" && ODELAY_TYPE != "VAR_LOAD_PIPE") begin
$display("Attribute Syntax Error : The attribute ODELAY_TYPE on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE, VAR_LOAD or VAR_LOAD_PIPE", ODELAY_TYPE);
#1 $finish;
end
//-------- ODELAY_VALUE check
if (ODELAY_VALUE < MIN_DELAY_COUNT || ODELAY_VALUE > MAX_DELAY_COUNT) begin
$display("Attribute Syntax Error : The attribute ODELAY_VALUE on ODELAYE2_FINEDELAY instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 31", ODELAY_VALUE);
#1 $finish;
end
//-------- PIPE_SEL check
case (PIPE_SEL)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute PIPE_SEL on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PIPE_SEL);
#1 $finish;
end
endcase
//-------- REFCLK_FREQUENCY check
if ((REFCLK_FREQUENCY >= 190.0 && REFCLK_FREQUENCY <= 210.0) ||
(REFCLK_FREQUENCY >= 290.0 && REFCLK_FREQUENCY <= 310.0) ||
(REFCLK_FREQUENCY >=390.0 && REFCLK_FREQUENCY <= 410.0))
/* */;
else begin
$display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on ODELAYE2_FINEDELAY instance %m is set to %f. Legal values for this attribute are either between 190.0 and 210.0, or between 290.0 and 310.0 or between 390.0 and 410.0", REFCLK_FREQUENCY);
#1 $finish;
end
//-------- SIGNAL_PATTERN check
case (SIGNAL_PATTERN)
"CLOCK", "DATA" : ;
default : begin
$display("Attribute Syntax Error : The attribute SIGNAL_PATTERN on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are DATA or CLOCK.", SIGNAL_PATTERN);
#1 $finish;
end
endcase
//-------- CALC_TAPDELAY_RD check
INIT_DELAY_RD = 600; //regular delay
INIT_DELAY_FD = 40; //fine delay
end // initial begin
// CALC_TAPDELAY_RD value
initial begin
if ((REFCLK_FREQUENCY <= 410.0) && (REFCLK_FREQUENCY >= 390.0))
begin
CALC_TAPDELAY_RD = 39;
end
else if ((REFCLK_FREQUENCY <= 310.0) && (REFCLK_FREQUENCY >= 290.0))
begin
CALC_TAPDELAY_RD = 52;
end
else
begin
CALC_TAPDELAY_RD = 78;
end
CALC_TAPDELAY_FD = 10; //fine delay
end
//----------------------------------------------------------------------
//------------------------ Dynamic clock inversion ---------------------
//----------------------------------------------------------------------
generate
case (CINVCTRL_SEL)
"TRUE" : always @(c_in_pre or cinvctrl_in) c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre);
"FALSE" : always @(c_in_pre) c_in = c_in_pre;
endcase
endgenerate
//----------------------------------------------------------------------
//------------------------ CNTVALUEOUT ---------------------
//----------------------------------------------------------------------
always @(odelay_count) begin
// Fixed CNTVALUEOUT for when in FIXED mode because of simprim.
if(ODELAY_TYPE != "FIXED")
assign cntvalueout_pre = odelay_count;
else
assign cntvalueout_pre = ODELAY_VALUE;
end
//----------------------------------------------------------------------
//-------------------------- CNTVALUEIN LOAD --------------------------
//----------------------------------------------------------------------
always @(posedge c_in) begin
if (regrst_in == 1'b1)
qcntvalueout_reg = 5'b0;
else if (regrst_in == 1'b0 && ldpipeen_in == 1'b1) begin
qcntvalueout_reg = CNTVALUEIN_INTEGER;
end
end // always @(posedge c_in)
generate
case (PIPE_SEL)
"TRUE" : always @(qcntvalueout_reg) qcntvalueout_mux <= qcntvalueout_reg;
"FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER;
endcase
endgenerate
//----------------------------------------------------------------------
//-------------------------- ODELAY_COUNT ----------------------------
//----------------------------------------------------------------------
always @(posedge c_in) begin
if (ODELAY_TYPE == "VARIABLE" | ODELAY_TYPE == "VAR_LOAD" | ODELAY_TYPE == "VAR_LOAD_PIPE") begin
if (ld_in == 1'b1) begin
case (ODELAY_TYPE)
"VARIABLE" : odelay_count = ODELAY_VALUE;
"VAR_LOAD", "VAR_LOAD_PIPE" : odelay_count = qcntvalueout_mux;
endcase
end
else if (ld_in == 1'b0 && ce_in == 1'b1) begin
if (inc_in == 1'b1) begin
case (ODELAY_TYPE)
"VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin
if (odelay_count < MAX_DELAY_COUNT)
odelay_count = odelay_count + 1;
else if (odelay_count == MAX_DELAY_COUNT)
odelay_count = MIN_DELAY_COUNT;
end
endcase
end
else if (inc_in == 1'b0) begin
case (ODELAY_TYPE)
"VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin
if (odelay_count > MIN_DELAY_COUNT)
odelay_count = odelay_count - 1;
else if (odelay_count == MIN_DELAY_COUNT)
odelay_count = MAX_DELAY_COUNT;
end
endcase
end
end
end //
end // always @ (posedge c_in)
always @(cntvaluein_in or gsr_in) begin
case (cntvaluein_in)
5'b00000 : assign CNTVALUEIN_INTEGER = 0;
5'b00001 : assign CNTVALUEIN_INTEGER = 1;
5'b00010 : assign CNTVALUEIN_INTEGER = 2;
5'b00011 : assign CNTVALUEIN_INTEGER = 3;
5'b00100 : assign CNTVALUEIN_INTEGER = 4;
5'b00101 : assign CNTVALUEIN_INTEGER = 5;
5'b00110 : assign CNTVALUEIN_INTEGER = 6;
5'b00111 : assign CNTVALUEIN_INTEGER = 7;
5'b01000 : assign CNTVALUEIN_INTEGER = 8;
5'b01001 : assign CNTVALUEIN_INTEGER = 9;
5'b01010 : assign CNTVALUEIN_INTEGER = 10;
5'b01011 : assign CNTVALUEIN_INTEGER = 11;
5'b01100 : assign CNTVALUEIN_INTEGER = 12;
5'b01101 : assign CNTVALUEIN_INTEGER = 13;
5'b01110 : assign CNTVALUEIN_INTEGER = 14;
5'b01111 : assign CNTVALUEIN_INTEGER = 15;
5'b10000 : assign CNTVALUEIN_INTEGER = 16;
5'b10001 : assign CNTVALUEIN_INTEGER = 17;
5'b10010 : assign CNTVALUEIN_INTEGER = 18;
5'b10011 : assign CNTVALUEIN_INTEGER = 19;
5'b10100 : assign CNTVALUEIN_INTEGER = 20;
5'b10101 : assign CNTVALUEIN_INTEGER = 21;
5'b10110 : assign CNTVALUEIN_INTEGER = 22;
5'b10111 : assign CNTVALUEIN_INTEGER = 23;
5'b11000 : assign CNTVALUEIN_INTEGER = 24;
5'b11001 : assign CNTVALUEIN_INTEGER = 25;
5'b11010 : assign CNTVALUEIN_INTEGER = 26;
5'b11011 : assign CNTVALUEIN_INTEGER = 27;
5'b11100 : assign CNTVALUEIN_INTEGER = 28;
5'b11101 : assign CNTVALUEIN_INTEGER = 29;
5'b11110 : assign CNTVALUEIN_INTEGER = 30;
5'b11111 : assign CNTVALUEIN_INTEGER = 31;
endcase
end
//*********************************************************
//*** SELECT IDATA signal
//*********************************************************
always @(clkin_in or odatain_in) begin
case (DELAY_SRC)
"ODATAIN" : begin
data_mux <= odatain_in;
end
"CLKIN" : begin
data_mux <= clkin_in;
end
default : begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are CLKIN or ODATAIN", DELAY_SRC);
$finish;
end
endcase // case(DELAY_SRC)
end // always @(datain_in or idatain_in)
//*********************************************************
//*** DELAY IDATA signal
//*********************************************************
assign #(DELAY_D) delay_chain_0 = data_mux;
assign #CALC_TAPDELAY_RD delay_chain_1 = delay_chain_0;
assign #CALC_TAPDELAY_RD delay_chain_2 = delay_chain_1;
assign #CALC_TAPDELAY_RD delay_chain_3 = delay_chain_2;
assign #CALC_TAPDELAY_RD delay_chain_4 = delay_chain_3;
assign #CALC_TAPDELAY_RD delay_chain_5 = delay_chain_4;
assign #CALC_TAPDELAY_RD delay_chain_6 = delay_chain_5;
assign #CALC_TAPDELAY_RD delay_chain_7 = delay_chain_6;
assign #CALC_TAPDELAY_RD delay_chain_8 = delay_chain_7;
assign #CALC_TAPDELAY_RD delay_chain_9 = delay_chain_8;
assign #CALC_TAPDELAY_RD delay_chain_10 = delay_chain_9;
assign #CALC_TAPDELAY_RD delay_chain_11 = delay_chain_10;
assign #CALC_TAPDELAY_RD delay_chain_12 = delay_chain_11;
assign #CALC_TAPDELAY_RD delay_chain_13 = delay_chain_12;
assign #CALC_TAPDELAY_RD delay_chain_14 = delay_chain_13;
assign #CALC_TAPDELAY_RD delay_chain_15 = delay_chain_14;
assign #CALC_TAPDELAY_RD delay_chain_16 = delay_chain_15;
assign #CALC_TAPDELAY_RD delay_chain_17 = delay_chain_16;
assign #CALC_TAPDELAY_RD delay_chain_18 = delay_chain_17;
assign #CALC_TAPDELAY_RD delay_chain_19 = delay_chain_18;
assign #CALC_TAPDELAY_RD delay_chain_20 = delay_chain_19;
assign #CALC_TAPDELAY_RD delay_chain_21 = delay_chain_20;
assign #CALC_TAPDELAY_RD delay_chain_22 = delay_chain_21;
assign #CALC_TAPDELAY_RD delay_chain_23 = delay_chain_22;
assign #CALC_TAPDELAY_RD delay_chain_24 = delay_chain_23;
assign #CALC_TAPDELAY_RD delay_chain_25 = delay_chain_24;
assign #CALC_TAPDELAY_RD delay_chain_26 = delay_chain_25;
assign #CALC_TAPDELAY_RD delay_chain_27 = delay_chain_26;
assign #CALC_TAPDELAY_RD delay_chain_28 = delay_chain_27;
assign #CALC_TAPDELAY_RD delay_chain_29 = delay_chain_28;
assign #CALC_TAPDELAY_RD delay_chain_30 = delay_chain_29;
assign #CALC_TAPDELAY_RD delay_chain_31 = delay_chain_30;
//*********************************************************
//*** assign delay
//*********************************************************
always @(odelay_count) begin
case (odelay_count)
0: assign tap_out_rd = delay_chain_0;
1: assign tap_out_rd = delay_chain_1;
2: assign tap_out_rd = delay_chain_2;
3: assign tap_out_rd = delay_chain_3;
4: assign tap_out_rd = delay_chain_4;
5: assign tap_out_rd = delay_chain_5;
6: assign tap_out_rd = delay_chain_6;
7: assign tap_out_rd = delay_chain_7;
8: assign tap_out_rd = delay_chain_8;
9: assign tap_out_rd = delay_chain_9;
10: assign tap_out_rd = delay_chain_10;
11: assign tap_out_rd = delay_chain_11;
12: assign tap_out_rd = delay_chain_12;
13: assign tap_out_rd = delay_chain_13;
14: assign tap_out_rd = delay_chain_14;
15: assign tap_out_rd = delay_chain_15;
16: assign tap_out_rd = delay_chain_16;
17: assign tap_out_rd = delay_chain_17;
18: assign tap_out_rd = delay_chain_18;
19: assign tap_out_rd = delay_chain_19;
20: assign tap_out_rd = delay_chain_20;
21: assign tap_out_rd = delay_chain_21;
22: assign tap_out_rd = delay_chain_22;
23: assign tap_out_rd = delay_chain_23;
24: assign tap_out_rd = delay_chain_24;
25: assign tap_out_rd = delay_chain_25;
26: assign tap_out_rd = delay_chain_26;
27: assign tap_out_rd = delay_chain_27;
28: assign tap_out_rd = delay_chain_28;
29: assign tap_out_rd = delay_chain_29;
30: assign tap_out_rd = delay_chain_30;
31: assign tap_out_rd = delay_chain_31;
default:
assign tap_out_rd = delay_chain_0;
endcase
end // always @ (odelay_count)
//*********************************************************
//*** FINE DELAY signal
//*********************************************************
assign #(INIT_DELAY_FD) fine_delay_0 = tap_out_rd;
assign #CALC_TAPDELAY_FD fine_delay_1 = fine_delay_0;
assign #CALC_TAPDELAY_FD fine_delay_2 = fine_delay_1;
assign #CALC_TAPDELAY_FD fine_delay_3 = fine_delay_2;
assign #CALC_TAPDELAY_FD fine_delay_4 = fine_delay_3;
assign #CALC_TAPDELAY_FD fine_delay_5 = fine_delay_4;
always @(ofdly_in) begin
case (ofdly_in)
3'b000: assign tap_out_fd = fine_delay_0;
3'b001: assign tap_out_fd = fine_delay_1;
3'b010: assign tap_out_fd = fine_delay_2;
3'b011: assign tap_out_fd = fine_delay_3;
3'b100: assign tap_out_fd = fine_delay_4;
default:
assign tap_out_fd = 1'bx;
endcase
end // always @ (ofdly_in)
`ifdef XIL_TIMING
wire c_en_n;
wire c_en_p;
assign c_en_n = IS_C_INVERTED;
assign c_en_p = ~IS_C_INVERTED;
wire c_d_en;
wire o_d_en;
assign c_d_en = (odelay_count == 0) && (ofdly_in == 0) && (DELAY_SRC == "CLKIN");
assign o_d_en = (odelay_count == 0) && (ofdly_in == 0) && (DELAY_SRC == "ODATAIN");
//*** Timing Checks Start here
always @(notifier) begin
tap_out_rd <= 1'bx;
end
`endif // ifdef XIL_TIMING
`ifdef XIL_TIMING
specify
( C *> CNTVALUEOUT) = (0:0:0, 0:0:0);
( C => DATAOUT) = (0:0:0, 0:0:0);
( CINVCTRL *> CNTVALUEOUT) = (0:0:0, 0:0:0);
( CINVCTRL => DATAOUT) = (0:0:0, 0:0:0);
if (c_d_en) ( CLKIN => DATAOUT) = (0:0:0, 0:0:0);
if (o_d_en) ( ODATAIN => DATAOUT) = (0:0:0, 0:0:0);
$period (negedge C, 0:0:0, notifier);
$period (posedge C, 0:0:0, notifier);
$setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ce);
$setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ce);
$setuphold (posedge C, posedge INC, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_inc);
$setuphold (posedge C, negedge INC, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_inc);
$setuphold (posedge C, posedge LD, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ld);
$setuphold (posedge C, negedge LD, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ld);
$setuphold (posedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_cntvaluein);
$setuphold (posedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_cntvaluein);
$setuphold (posedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ldpipeen);
$setuphold (posedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ldpipeen);
$setuphold (posedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_regrst);
$setuphold (posedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_regrst);
$setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ce);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ce);
$setuphold (negedge C, posedge INC, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_inc);
$setuphold (negedge C, negedge INC, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_inc);
$setuphold (negedge C, posedge LD, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ld);
$setuphold (negedge C, negedge LD, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ld);
$setuphold (negedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_cntvaluein);
$setuphold (negedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_cntvaluein);
$setuphold (negedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ldpipeen);
$setuphold (negedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ldpipeen);
$setuphold (negedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_regrst);
$setuphold (negedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_regrst);
specparam PATHPULSE$ = 0;
endspecify
`endif // ifdef XIL_TIMING
endmodule // ODELAYE2_FINEDELAY
`endcelldefine
|
//wb_artemis_usb2_platform.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000000
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:artemis_usb2
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x022
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x03
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.artemis.cospandesign.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/05/23
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:4
*/
`include "artemis_usb2_platform_defines.v"
module wb_artemis_usb2_platform #(
parameter RX_PREAMP = 2'h3,
parameter TX_DIFF = 4'h6
)(
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
output reg o_wbs_int,
output o_platform_ready,
//--SATA Interface--
output o_sata_75mhz_clk,
output o_sata_error,
// GTP: Control/Data Interface
output [3:0] o_sata_rx_char_is_k,
output [31:0] o_sata_rx_data,
input i_sata_tx_char_is_k,
input [31:0] i_sata_tx_data,
// GTP: OOB Signals
input i_sata_tx_elec_idle,
input i_sata_tx_comm_init,
input i_sata_tx_comm_wake,
output o_sata_tx_oob_complete,
output o_sata_rx_elec_idle,
output o_sata_rx_comm_wake_detect,
output o_sata_rx_comm_init_detect,
output o_sata_rx_byte_is_aligned,
//OPTIONAL
output [2:0] o_sata_clk_correct_count,
output [3:0] o_sata_rx_char_is_comma,
//--PCIE Interface--
output o_pcie_62p5mhz_clk,
output o_pcie_error,
// GTP: Control/Data Interface
output [3:0] o_pcie_rx_char_is_k,
input [3:0] i_pcie_tx_char_is_k,
output [31:0] o_pcie_rx_data,
input [31:0] i_pcie_tx_data,
output o_pcie_phy_rx_valid,
output o_pcie_rx_byte_is_aligned,
// GTP: OOB Signals
input i_pcie_tx_detect_rx,
input i_pcie_tx_elec_idle,
input [3:0] i_pcie_disparity_mode,
output o_pcie_phy_status,
output o_pcie_rx_elec_idle,
//OPTIONAL
output [2:0] o_pcie_clk_correct_count,
//Physical Signals
input i_gtp0_clk_p,
input i_gtp0_clk_n,
input i_gtp1_clk_p,
input i_gtp1_clk_n,
input i_sata_phy_rx_p,
input i_sata_phy_rx_n,
input i_pcie_phy_rx_p,
input i_pcie_phy_rx_n,
output o_sata_phy_tx_p,
output o_sata_phy_tx_n,
output o_pcie_phy_tx_p,
output o_pcie_phy_tx_n
);
//Local Parameters
localparam GTP_CONTROL = 32'h00000000;
localparam GTP_STATUS = 32'h00000001;
localparam SATA_CLK_COUNT = 32'h00000002;
localparam SATA_FST_CLK_COUNT = 32'h00000003;
//Local Registers/Wires
reg [31:0] gtp_control = 32'h00;
wire [31:0] gtp_status;
wire pcie_rx_polarity;
wire usr_cntrl_reset;
wire sata_reset;
wire pcie_reset;
wire [1:0] rx_pre_amp;
wire [3:0] tx_diff_swing;
wire sata_pll_detect_k;
wire pcie_pll_detect_k;
wire sata_reset_done;
wire pcie_reset_done;
wire sata_dcm_locked;
wire pcie_dcm_locked;
reg sata_tx_comm_start;
reg sata_tx_comm_type;
wire [2:0] sata_rx_status;
wire [2:0] pcie_rx_status;
wire sata_loss_of_sync;
wire pcie_loss_of_sync;
wire [3:0] sata_disparity_error;
wire [3:0] pcie_disparity_error;
wire [3:0] sata_rx_not_in_table;
wire [3:0] pcie_rx_not_in_table;
wire sata_75mhz_clk;
wire [31:0] second_value;
wire [31:0] fst_second_value;
reg reg_sata_tx_comm_wake;
reg reg_sata_tx_comm_init;
wire sata_300mhz_clk;
//Submodules
artemis_pcie_sata aps(
.i_sata_reset (sata_reset ),
.i_pcie_reset (pcie_reset ),
.o_sata_pll_detect_k (sata_pll_detect_k ),
.o_pcie_pll_detect_k (pcie_pll_detect_k ),
.o_sata_reset_done (sata_reset_done ),
.o_pcie_reset_done (pcie_reset_done ),
.o_sata_75mhz_clk (sata_75mhz_clk ),
.o_sata_300mhz_clk (sata_300mhz_clk ),
.o_pcie_62p5mhz_clk (o_pcie_62p5mhz_clk ),
.o_sata_dcm_locked (sata_dcm_locked ),
.o_pcie_dcm_locked (pcie_dcm_locked ),
.o_sata_loss_of_sync (sata_loss_of_sync ),
.o_pcie_loss_of_sync (pcie_loss_of_sync ),
.o_sata_rx_char_is_comma (o_sata_rx_char_is_comma ),
.o_sata_rx_char_is_k (o_sata_rx_char_is_k ),
.o_pcie_rx_char_is_k (o_pcie_rx_char_is_k ),
.o_sata_disparity_error (sata_disparity_error ),
.o_pcie_disparity_error (pcie_disparity_error ),
.o_sata_rx_not_in_table (sata_rx_not_in_table ),
.o_pcie_rx_not_in_table (pcie_rx_not_in_table ),
.o_sata_clk_correct_count (o_sata_clk_correct_count ),
.o_pcie_clk_correct_count (o_pcie_clk_correct_count ),
.o_sata_rx_data (o_sata_rx_data ),
.o_pcie_rx_data (o_pcie_rx_data ),
.o_sata_rx_elec_idle (o_sata_rx_elec_idle ),
.o_pcie_rx_elec_idle (o_pcie_rx_elec_idle ),
.i_sata_rx_pre_amp (rx_pre_amp ),
.o_sata_rx_byte_is_aligned(o_sata_rx_byte_is_aligned),
.o_pcie_rx_byte_is_aligned(o_pcie_rx_byte_is_aligned),
.o_sata_rx_status (sata_rx_status ),
.o_pcie_rx_status (pcie_rx_status ),
.i_sata_phy_rx_p (i_sata_phy_rx_p ),
.i_sata_phy_rx_n (i_sata_phy_rx_n ),
.i_pcie_phy_rx_p (i_pcie_phy_rx_p ),
.i_pcie_phy_rx_n (i_pcie_phy_rx_n ),
.o_pcie_phy_status (o_pcie_phy_status ),
.o_pcie_phy_rx_valid (o_pcie_phy_rx_valid ),
.i_pcie_rx_polarity (pcie_rx_polarity ),
.i_pcie_disparity_mode (i_pcie_disparity_mode ),
.i_sata_tx_char_is_k (i_sata_tx_char_is_k ),
.i_pcie_tx_char_is_k (i_pcie_tx_char_is_k ),
.i_sata_tx_data (i_sata_tx_data ),
.i_pcie_tx_data (i_pcie_tx_data ),
.i_tx_diff_swing (tx_diff_swing ),
.o_sata_phy_tx_p (o_sata_phy_tx_p ),
.o_sata_phy_tx_n (o_sata_phy_tx_n ),
.o_pcie_phy_tx_p (o_pcie_phy_tx_p ),
.o_pcie_phy_tx_n (o_pcie_phy_tx_n ),
.i_pcie_tx_detect_rx (i_pcie_tx_detect_rx ),
.i_sata_tx_elec_idle (i_sata_tx_elec_idle ),
.i_pcie_tx_elec_idle (i_pcie_tx_elec_idle ),
.i_sata_tx_comm_start (sata_tx_comm_start ),
.i_sata_tx_comm_type (sata_tx_comm_type ),
.i_gtp0_clk_p (i_gtp0_clk_p ),
.i_gtp0_clk_n (i_gtp0_clk_n ),
.i_gtp1_clk_p (i_gtp1_clk_p ),
.i_gtp1_clk_n (i_gtp1_clk_n )
);
clock_counter #(
.REFCLK_SECOND_COUNTER (32'h05F5E100 )
) cc (
.clock_ref (clk ),
.rst (rst ),
.clock_input (sata_75mhz_clk ),
.value (second_value )
);
clock_counter #(
.REFCLK_SECOND_COUNTER (32'h05F5E100 )
) ccfst (
.clock_ref (clk ),
.rst (rst ),
.clock_input (sata_300mhz_clk ),
.value (fst_second_value )
);
//Asynchronous Logic
assign rx_pre_amp = gtp_control[`GTP_RX_PRE_AMP_HIGH :`GTP_RX_PRE_AMP_LOW ];
assign tx_diff_swing = gtp_control[`GTP_TX_DIFF_SWING_HIGH :`GTP_TX_DIFF_SWING_LOW ];
//assign pcie_rx_polarity = gtp_control[`PCIE_RX_POLARITY];
assign pcie_rx_polarity = 1'b0;
assign o_sata_75mhz_clk = sata_75mhz_clk;
assign sata_reset = rst || gtp_control[`SATA_RESET];
assign pcie_reset = rst || gtp_control[`PCIE_RESET];
assign o_sata_tx_oob_complete = sata_rx_status[0];
assign o_sata_rx_comm_wake_detect = sata_rx_status[1];
assign o_sata_rx_comm_init_detect = sata_rx_status[2];
//assign o_sata_error = (sata_disparity_error > 0) || (sata_rx_not_in_table > 0) || sata_loss_of_sync;
assign o_sata_error = (sata_disparity_error > 0) || (sata_rx_not_in_table > 0) || !o_sata_rx_byte_is_aligned;
//assign o_pcie_error = (pcie_disparity_error > 0) || (pcie_rx_not_in_table > 0) || pcie_loss_of_sync;
assign o_pcie_error = (pcie_disparity_error > 0) || (pcie_rx_not_in_table > 0) || !o_pcie_rx_byte_is_aligned;
assign o_platform_ready = (!sata_reset && sata_pll_detect_k && sata_dcm_locked && sata_reset_done);
//Translate SATA friendly signals to GTP Friendly signals
always @ (posedge sata_75mhz_clk) begin
if (sata_reset) begin
sata_tx_comm_start <= 0;
sata_tx_comm_type <= 0;
reg_sata_tx_comm_wake <= 0;
reg_sata_tx_comm_init <= 0;
end
else begin
if (!sata_reset_done) begin
sata_tx_comm_start <= 0;
sata_tx_comm_type <= 0;
reg_sata_tx_comm_wake <= 0;
reg_sata_tx_comm_init <= 0;
end
else begin
sata_tx_comm_start <= 0;
//Change the incomming wake/init strobes into latched values
if (i_sata_tx_comm_wake) begin
reg_sata_tx_comm_wake <= 1;
sata_tx_comm_type <= 1;
end
if (i_sata_tx_comm_init) begin
reg_sata_tx_comm_init <= 1;
sata_tx_comm_type <= 0;
end
//Translate the command
else if (reg_sata_tx_comm_init) begin
sata_tx_comm_start <= 1;
reg_sata_tx_comm_init <= 0;
end
else if (reg_sata_tx_comm_wake) begin
sata_tx_comm_start <= 1;
reg_sata_tx_comm_wake <= 0;
end
end
end
end
assign gtp_status[`SATA_PLL_DETECT_K ] = sata_pll_detect_k;
assign gtp_status[`PCIE_PLL_DETECT_K ] = pcie_pll_detect_k;
assign gtp_status[`SATA_RESET_DONE ] = sata_reset_done;
assign gtp_status[`PCIE_RESET_DONE ] = pcie_reset_done;
assign gtp_status[`SATA_DCM_PLL_LOCKED ] = sata_dcm_locked;
assign gtp_status[`PCIE_DCM_PLL_LOCKED ] = pcie_dcm_locked;
assign gtp_status[`SATA_RX_IDLE ] = o_sata_rx_elec_idle;
assign gtp_status[`PCIE_RX_IDLE ] = o_pcie_rx_elec_idle;
assign gtp_status[`SATA_TX_IDLE ] = i_sata_tx_elec_idle;
assign gtp_status[`PCIE_TX_IDLE ] = i_pcie_tx_elec_idle;
assign gtp_status[`SATA_LOSS_OF_SYNC ] = sata_loss_of_sync;
assign gtp_status[`PCIE_LOSS_OF_SYNC ] = pcie_loss_of_sync;
assign gtp_status[`SATA_BYTE_IS_ALIGNED] = o_sata_rx_byte_is_aligned;
assign gtp_status[`PCIE_BYTE_IS_ALIGNED] = o_pcie_rx_byte_is_aligned;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
gtp_control <= 0;
o_wbs_int <= 0;
// gtp_control[`SATA_RESET] <= 1;
// gtp_control[`PCIE_RESET] <= 1;
gtp_control[`GTP_RX_PRE_AMP_HIGH :`GTP_RX_PRE_AMP_LOW ] <= RX_PREAMP;
gtp_control[`GTP_TX_DIFF_SWING_HIGH :`GTP_TX_DIFF_SWING_LOW ] <= TX_DIFF;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
GTP_CONTROL: begin
gtp_control <= i_wbs_dat;
end
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
GTP_CONTROL: begin
o_wbs_dat <= gtp_control;
end
GTP_STATUS: begin
o_wbs_dat <= gtp_status;
end
SATA_CLK_COUNT: begin
o_wbs_dat <= second_value;
end
SATA_FST_CLK_COUNT: begin
o_wbs_dat <= fst_second_value;
end
default: begin
end
endcase
end
o_wbs_ack <= 1;
end
end
end
end
endmodule
|
//altera_mult_add ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="UNREGISTERED" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_addnsub3="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SELECTED_DEVICE_FAMILY="CYCLONEIVE" SIGNED_PIPELINE_ACLR_A="ACLR0" SIGNED_PIPELINE_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="UNREGISTERED" SIGNED_REGISTER_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_RESULT=16 aclr0 clock0 dataa datab result
//VERSION_BEGIN 13.0 cbx_altera_mult_add 2013:06:12:18:03:43:SJ cbx_altera_mult_add_rtl 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = altera_mult_add_rtl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_mult_add_s1u2
(
aclr0,
clock0,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr0;
input clock0;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [15:0] dataa;
tri0 [15:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] wire_altera_mult_add_rtl1_result;
altera_mult_add_rtl altera_mult_add_rtl1
(
.aclr0(aclr0),
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add_rtl1_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({22{1'b0}}),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({16{1'b0}}),
.scaninb({16{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sload_accum(1'b0),
.sourcea({1{1'b0}}),
.sourceb({1{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add_rtl1.accum_direction = "ADD",
altera_mult_add_rtl1.accum_sload_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_pipeline_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.accum_sload_register = "UNREGISTERED",
altera_mult_add_rtl1.accumulator = "NO",
altera_mult_add_rtl1.adder1_rounding = "NO",
altera_mult_add_rtl1.adder3_rounding = "NO",
altera_mult_add_rtl1.addnsub1_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub1_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_register3 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.chainout_aclr = "NONE",
altera_mult_add_rtl1.chainout_adder = "NO",
altera_mult_add_rtl1.chainout_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_rounding = "NO",
altera_mult_add_rtl1.chainout_saturate_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturation = "NO",
altera_mult_add_rtl1.coef0_0 = 0,
altera_mult_add_rtl1.coef0_1 = 0,
altera_mult_add_rtl1.coef0_2 = 0,
altera_mult_add_rtl1.coef0_3 = 0,
altera_mult_add_rtl1.coef0_4 = 0,
altera_mult_add_rtl1.coef0_5 = 0,
altera_mult_add_rtl1.coef0_6 = 0,
altera_mult_add_rtl1.coef0_7 = 0,
altera_mult_add_rtl1.coef1_0 = 0,
altera_mult_add_rtl1.coef1_1 = 0,
altera_mult_add_rtl1.coef1_2 = 0,
altera_mult_add_rtl1.coef1_3 = 0,
altera_mult_add_rtl1.coef1_4 = 0,
altera_mult_add_rtl1.coef1_5 = 0,
altera_mult_add_rtl1.coef1_6 = 0,
altera_mult_add_rtl1.coef1_7 = 0,
altera_mult_add_rtl1.coef2_0 = 0,
altera_mult_add_rtl1.coef2_1 = 0,
altera_mult_add_rtl1.coef2_2 = 0,
altera_mult_add_rtl1.coef2_3 = 0,
altera_mult_add_rtl1.coef2_4 = 0,
altera_mult_add_rtl1.coef2_5 = 0,
altera_mult_add_rtl1.coef2_6 = 0,
altera_mult_add_rtl1.coef2_7 = 0,
altera_mult_add_rtl1.coef3_0 = 0,
altera_mult_add_rtl1.coef3_1 = 0,
altera_mult_add_rtl1.coef3_2 = 0,
altera_mult_add_rtl1.coef3_3 = 0,
altera_mult_add_rtl1.coef3_4 = 0,
altera_mult_add_rtl1.coef3_5 = 0,
altera_mult_add_rtl1.coef3_6 = 0,
altera_mult_add_rtl1.coef3_7 = 0,
altera_mult_add_rtl1.coefsel0_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_register = "UNREGISTERED",
altera_mult_add_rtl1.dedicated_multiplier_circuitry = "YES",
altera_mult_add_rtl1.double_accum = "NO",
altera_mult_add_rtl1.dsp_block_balancing = "Auto",
altera_mult_add_rtl1.extra_latency = 0,
altera_mult_add_rtl1.input_aclr_a0 = "NONE",
altera_mult_add_rtl1.input_aclr_a1 = "NONE",
altera_mult_add_rtl1.input_aclr_a2 = "NONE",
altera_mult_add_rtl1.input_aclr_a3 = "NONE",
altera_mult_add_rtl1.input_aclr_b0 = "NONE",
altera_mult_add_rtl1.input_aclr_b1 = "NONE",
altera_mult_add_rtl1.input_aclr_b2 = "NONE",
altera_mult_add_rtl1.input_aclr_b3 = "NONE",
altera_mult_add_rtl1.input_aclr_c0 = "NONE",
altera_mult_add_rtl1.input_aclr_c1 = "NONE",
altera_mult_add_rtl1.input_aclr_c2 = "NONE",
altera_mult_add_rtl1.input_aclr_c3 = "NONE",
altera_mult_add_rtl1.input_register_a0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c3 = "UNREGISTERED",
altera_mult_add_rtl1.input_source_a0 = "DATAA",
altera_mult_add_rtl1.input_source_a1 = "DATAA",
altera_mult_add_rtl1.input_source_a2 = "DATAA",
altera_mult_add_rtl1.input_source_a3 = "DATAA",
altera_mult_add_rtl1.input_source_b0 = "DATAB",
altera_mult_add_rtl1.input_source_b1 = "DATAB",
altera_mult_add_rtl1.input_source_b2 = "DATAB",
altera_mult_add_rtl1.input_source_b3 = "DATAB",
altera_mult_add_rtl1.loadconst_control_aclr = "NONE",
altera_mult_add_rtl1.loadconst_control_register = "UNREGISTERED",
altera_mult_add_rtl1.loadconst_value = 64,
altera_mult_add_rtl1.mult01_round_aclr = "NONE",
altera_mult_add_rtl1.mult01_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult01_saturation_aclr = "ACLR0",
altera_mult_add_rtl1.mult01_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_round_aclr = "NONE",
altera_mult_add_rtl1.mult23_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_saturation_aclr = "NONE",
altera_mult_add_rtl1.mult23_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.multiplier01_rounding = "NO",
altera_mult_add_rtl1.multiplier01_saturation = "NO",
altera_mult_add_rtl1.multiplier1_direction = "ADD",
altera_mult_add_rtl1.multiplier23_rounding = "NO",
altera_mult_add_rtl1.multiplier23_saturation = "NO",
altera_mult_add_rtl1.multiplier3_direction = "ADD",
altera_mult_add_rtl1.multiplier_aclr0 = "ACLR0",
altera_mult_add_rtl1.multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.multiplier_aclr2 = "NONE",
altera_mult_add_rtl1.multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.multiplier_register0 = "CLOCK0",
altera_mult_add_rtl1.multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register2 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.number_of_multipliers = 1,
altera_mult_add_rtl1.output_aclr = "NONE",
altera_mult_add_rtl1.output_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_type = "NEAREST_INTEGER",
altera_mult_add_rtl1.output_rounding = "NO",
altera_mult_add_rtl1.output_saturate_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_type = "ASYMMETRIC",
altera_mult_add_rtl1.output_saturation = "NO",
altera_mult_add_rtl1.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_rtl1.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_rtl1.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_signa = "PORT_UNUSED",
altera_mult_add_rtl1.port_signb = "PORT_UNUSED",
altera_mult_add_rtl1.preadder_direction_0 = "ADD",
altera_mult_add_rtl1.preadder_direction_1 = "ADD",
altera_mult_add_rtl1.preadder_direction_2 = "ADD",
altera_mult_add_rtl1.preadder_direction_3 = "ADD",
altera_mult_add_rtl1.preadder_mode = "SIMPLE",
altera_mult_add_rtl1.representation_a = "UNSIGNED",
altera_mult_add_rtl1.representation_b = "UNSIGNED",
altera_mult_add_rtl1.rotate_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.rotate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_register = "UNREGISTERED",
altera_mult_add_rtl1.scanouta_aclr = "NONE",
altera_mult_add_rtl1.scanouta_register = "UNREGISTERED",
altera_mult_add_rtl1.selected_device_family = "Cyclone IV E",
altera_mult_add_rtl1.shift_mode = "NO",
altera_mult_add_rtl1.shift_right_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_pipeline_aclr = "NONE",
altera_mult_add_rtl1.shift_right_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_register = "UNREGISTERED",
altera_mult_add_rtl1.signed_aclr_a = "NONE",
altera_mult_add_rtl1.signed_aclr_b = "NONE",
altera_mult_add_rtl1.signed_pipeline_aclr_a = "ACLR0",
altera_mult_add_rtl1.signed_pipeline_aclr_b = "ACLR0",
altera_mult_add_rtl1.signed_pipeline_register_a = "CLOCK0",
altera_mult_add_rtl1.signed_pipeline_register_b = "CLOCK0",
altera_mult_add_rtl1.signed_register_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_b = "UNREGISTERED",
altera_mult_add_rtl1.systolic_aclr1 = "NONE",
altera_mult_add_rtl1.systolic_aclr3 = "NONE",
altera_mult_add_rtl1.systolic_delay1 = "UNREGISTERED",
altera_mult_add_rtl1.systolic_delay3 = "UNREGISTERED",
altera_mult_add_rtl1.use_sload_accum_port = "NO",
altera_mult_add_rtl1.width_a = 16,
altera_mult_add_rtl1.width_b = 16,
altera_mult_add_rtl1.width_c = 22,
altera_mult_add_rtl1.width_chainin = 1,
altera_mult_add_rtl1.width_coef = 18,
altera_mult_add_rtl1.width_msb = 17,
altera_mult_add_rtl1.width_result = 16,
altera_mult_add_rtl1.width_saturate_sign = 1,
altera_mult_add_rtl1.zero_chainout_output_aclr = "NONE",
altera_mult_add_rtl1.zero_chainout_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_pipeline_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_register = "UNREGISTERED",
altera_mult_add_rtl1.lpm_type = "altera_mult_add_rtl";
assign
result = wire_altera_mult_add_rtl1_result;
endmodule //altera_mult_add_s1u2
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_S_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_S_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_pwrgood_pp$PG$S (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input SLEEP ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_S_SYMBOL_V
|
/* A alu module*/
module ALU(inputA, inputB, ALUop, result, zero);
input [31:0] inputA, inputB;
input [2:0] ALUop;
output [31:0] result;
reg [31:0] result;
output zero;
reg zero;
/*whenever input or ALUop changes*/
always @(inputA or inputB or ALUop)
begin
/*it supports AND, OR, ADD, SLT with a zero output*/
casez(ALUop)
3'b110: result = inputA - inputB;
3'b010: result = inputA + inputB;
3'bz00: result = inputA & inputB;
3'b?01: result = inputA | inputB;
3'b?11:
if ( inputA - inputB >= 0 )
result = 1;
else
result = 0;
endcase
if (inputA == inputB)
zero = 1;
else
zero = 0;
end
endmodule
module ALUTestbench;
reg [31:0] inputA, inputB;
reg [2:0] ALUop;
wire [31:0] result;
wire zero;
ALU UUT(inputA, inputB, ALUop, result, zero);
initial begin
#20 inputA = 5;
inputB = 6;
ALUop = 3'b000;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b001;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b010;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b110;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b011;
#40 inputA = 9;
inputB = 3;
ALUop = 3'b011;
#40 inputA = 6;
inputB = 6;
ALUop = 3'b001;
#40 inputA = -8;
inputB = 6;
ALUop = 3'b001;
end
initial
#340 $stop;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//////////////////////////////////////////////////////////////////////////////
// This module is a ST wrapper for the soft IP NextGen controller and the MMR
//////////////////////////////////////////////////////////////////////////////
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_controller_st_top(
clk,
half_clk,
reset_n,
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
afi_rst_n,
afi_cs_n,
afi_cke,
afi_odt,
afi_addr,
afi_ba,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
afi_rrank,
afi_wrank,
afi_rlat,
afi_cal_success,
afi_cal_fail,
afi_cal_req,
afi_init_req,
afi_mem_clk_disable,
afi_cal_byte_lane_sel_n,
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
local_init_done,
local_refresh_ack,
local_powerdn_ack,
local_self_rfsh_ack,
local_deep_powerdn_ack,
local_refresh_req,
local_refresh_chip,
local_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_deep_powerdn_req,
local_deep_powerdn_chip,
local_zqcal_req,
local_zqcal_chip,
local_multicast,
local_priority,
ecc_interrupt,
csr_read_req,
csr_write_req,
csr_burst_count,
csr_beginbursttransfer,
csr_addr,
csr_wdata,
csr_rdata,
csr_be,
csr_rdata_valid,
csr_waitrequest,
tbp_empty,
cmd_gen_busy,
sideband_in_refresh
);
//////////////////////////////////////////////////////////////////////////////
parameter LOCAL_SIZE_WIDTH = "";
parameter LOCAL_ADDR_WIDTH = "";
parameter LOCAL_DATA_WIDTH = "";
parameter LOCAL_BE_WIDTH = "";
parameter LOCAL_ID_WIDTH = "";
parameter LOCAL_CS_WIDTH = "";
parameter MEM_IF_ADDR_WIDTH = "";
parameter MEM_IF_CLK_PAIR_COUNT = "";
parameter LOCAL_IF_TYPE = "";
parameter DWIDTH_RATIO = "";
parameter CTL_ODT_ENABLED = "";
parameter CTL_OUTPUT_REGD = "";
parameter CTL_TBP_NUM = "";
parameter WRBUFFER_ADDR_WIDTH = "";
parameter RDBUFFER_ADDR_WIDTH = "";
parameter MAX_PENDING_RD_CMD = 16;
parameter MAX_PENDING_WR_CMD = 8;
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_IF_CHIP = "";
parameter MEM_IF_BANKADDR_WIDTH = "";
parameter MEM_IF_ROW_WIDTH = "";
parameter MEM_IF_COL_WIDTH = "";
parameter MEM_IF_ODT_WIDTH = "";
parameter MEM_IF_DQS_WIDTH = "";
parameter MEM_IF_DWIDTH = "";
parameter MEM_IF_DM_WIDTH = "";
parameter MAX_MEM_IF_CS_WIDTH = "";
parameter MAX_MEM_IF_CHIP = "";
parameter MAX_MEM_IF_BANKADDR_WIDTH = "";
parameter MAX_MEM_IF_ROWADDR_WIDTH = "";
parameter MAX_MEM_IF_COLADDR_WIDTH = "";
parameter MAX_MEM_IF_ODT_WIDTH = "";
parameter MAX_MEM_IF_DQS_WIDTH = "";
parameter MAX_MEM_IF_DQ_WIDTH = "";
parameter MAX_MEM_IF_MASK_WIDTH = "";
parameter MAX_LOCAL_DATA_WIDTH = "";
parameter CFG_TYPE = "";
parameter CFG_INTERFACE_WIDTH = "";
parameter CFG_BURST_LENGTH = "";
parameter CFG_DEVICE_WIDTH = "";
parameter CFG_REORDER_DATA = "";
parameter CFG_DATA_REORDERING_TYPE = "";
parameter CFG_STARVE_LIMIT = "";
parameter CFG_ADDR_ORDER = "";
parameter MEM_CAS_WR_LAT = "";
parameter MEM_ADD_LAT = "";
parameter MEM_TCL = "";
parameter MEM_TRRD = "";
parameter MEM_TFAW = "";
parameter MEM_TRFC = "";
parameter MEM_TREFI = "";
parameter MEM_TRCD = "";
parameter MEM_TRP = "";
parameter MEM_TWR = "";
parameter MEM_TWTR = "";
parameter MEM_TRTP = "";
parameter MEM_TRAS = "";
parameter MEM_TRC = "";
parameter CFG_TCCD = "";
parameter MEM_AUTO_PD_CYCLES = "";
parameter CFG_SELF_RFSH_EXIT_CYCLES = "";
parameter CFG_PDN_EXIT_CYCLES = "";
parameter CFG_POWER_SAVING_EXIT_CYCLES = "";
parameter CFG_MEM_CLK_ENTRY_CYCLES = "";
parameter MEM_TMRD_CK = "";
parameter CTL_ECC_ENABLED = "";
parameter CTL_ECC_RMW_ENABLED = "";
parameter CTL_ECC_MULTIPLES_16_24_40_72 = "";
parameter CFG_GEN_SBE = "";
parameter CFG_GEN_DBE = "";
parameter CFG_ENABLE_INTR = "";
parameter CFG_MASK_SBE_INTR = "";
parameter CFG_MASK_DBE_INTR = "";
parameter CFG_MASK_CORRDROP_INTR = 0;
parameter CFG_CLR_INTR = "";
parameter CTL_USR_REFRESH = "";
parameter CTL_REGDIMM_ENABLED = "";
parameter CTL_ENABLE_BURST_INTERRUPT = "";
parameter CTL_ENABLE_BURST_TERMINATE = "";
parameter CFG_WRITE_ODT_CHIP = "";
parameter CFG_READ_ODT_CHIP = "";
parameter CFG_PORT_WIDTH_WRITE_ODT_CHIP = "";
parameter CFG_PORT_WIDTH_READ_ODT_CHIP = "";
parameter MEM_IF_CKE_WIDTH = "";//check
parameter CTL_CSR_ENABLED = "";
parameter CFG_ENABLE_NO_DM = "";
parameter CSR_ADDR_WIDTH = "";
parameter CSR_DATA_WIDTH = "";
parameter CSR_BE_WIDTH = "";
parameter CFG_ENABLE_DQS_TRACKING = 0;
parameter CFG_WLAT_BUS_WIDTH = 6;
parameter CFG_RLAT_BUS_WIDTH = 6;
parameter CFG_RRANK_BUS_WIDTH = 0;
parameter CFG_WRANK_BUS_WIDTH = 0;
parameter CFG_USE_SHADOW_REGS = 0;
parameter MEM_IF_RD_TO_WR_TURNAROUND_OCT = "";
parameter MEM_IF_WR_TO_RD_TURNAROUND_OCT = "";
parameter CTL_RD_TO_PCH_EXTRA_CLK = 0;
parameter CTL_RD_TO_RD_EXTRA_CLK = 0;
parameter CTL_WR_TO_WR_EXTRA_CLK = 0;
parameter CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK = 0;
parameter CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK = 0;
parameter CTL_ENABLE_WDATA_PATH_LATENCY = 0;
parameter CFG_ECC_DECODER_REG = 0;
parameter CFG_ERRCMD_FIFO_REG = 0;
parameter ENABLE_BURST_MERGE = 0;
//////////////////////////////////////////////////////////////////////////////
localparam CFG_LOCAL_SIZE_WIDTH = LOCAL_SIZE_WIDTH;
localparam CFG_LOCAL_ADDR_WIDTH = LOCAL_ADDR_WIDTH;
localparam CFG_LOCAL_DATA_WIDTH = LOCAL_DATA_WIDTH;
localparam CFG_LOCAL_BE_WIDTH = LOCAL_BE_WIDTH;
localparam CFG_LOCAL_ID_WIDTH = LOCAL_ID_WIDTH;
localparam CFG_LOCAL_IF_TYPE = LOCAL_IF_TYPE;
localparam CFG_MEM_IF_ADDR_WIDTH = MEM_IF_ADDR_WIDTH;
localparam CFG_MEM_IF_CLK_PAIR_COUNT = MEM_IF_CLK_PAIR_COUNT;
localparam CFG_DWIDTH_RATIO = DWIDTH_RATIO;
localparam CFG_ODT_ENABLED = CTL_ODT_ENABLED;
localparam CFG_CTL_TBP_NUM = CTL_TBP_NUM;
localparam CFG_WRBUFFER_ADDR_WIDTH = WRBUFFER_ADDR_WIDTH;
localparam CFG_RDBUFFER_ADDR_WIDTH = RDBUFFER_ADDR_WIDTH;
localparam CFG_MAX_PENDING_RD_CMD = MAX_PENDING_RD_CMD;
localparam CFG_MAX_PENDING_WR_CMD = MAX_PENDING_WR_CMD;
localparam CFG_MEM_IF_CS_WIDTH = MEM_IF_CS_WIDTH;
localparam CFG_MEM_IF_CHIP = MEM_IF_CHIP;
localparam CFG_MEM_IF_BA_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_MEM_IF_ROW_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_MEM_IF_COL_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_MEM_IF_CKE_WIDTH = MEM_IF_CKE_WIDTH;
localparam CFG_MEM_IF_ODT_WIDTH = MEM_IF_ODT_WIDTH;
localparam CFG_MEM_IF_DQS_WIDTH = MEM_IF_DQS_WIDTH;
localparam CFG_MEM_IF_DQ_WIDTH = MEM_IF_DWIDTH;
localparam CFG_MEM_IF_DM_WIDTH = MEM_IF_DM_WIDTH;
localparam CFG_COL_ADDR_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_ROW_ADDR_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_BANK_ADDR_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_CS_ADDR_WIDTH = LOCAL_CS_WIDTH;
localparam CFG_CAS_WR_LAT = MEM_CAS_WR_LAT;
localparam CFG_ADD_LAT = MEM_ADD_LAT;
localparam CFG_TCL = MEM_TCL;
localparam CFG_TRRD = MEM_TRRD;
localparam CFG_TFAW = MEM_TFAW;
localparam CFG_TRFC = MEM_TRFC;
localparam CFG_TREFI = MEM_TREFI;
localparam CFG_TRCD = MEM_TRCD;
localparam CFG_TRP = MEM_TRP;
localparam CFG_TWR = MEM_TWR;
localparam CFG_TWTR = MEM_TWTR;
localparam CFG_TRTP = MEM_TRTP;
localparam CFG_TRAS = MEM_TRAS;
localparam CFG_TRC = MEM_TRC;
localparam CFG_AUTO_PD_CYCLES = MEM_AUTO_PD_CYCLES;
localparam CFG_TMRD = MEM_TMRD_CK;
localparam CFG_ENABLE_ECC = CTL_ECC_ENABLED;
localparam CFG_ENABLE_AUTO_CORR = CTL_ECC_RMW_ENABLED;
localparam CFG_ECC_MULTIPLES_16_24_40_72 = CTL_ECC_MULTIPLES_16_24_40_72;
localparam CFG_ENABLE_ECC_CODE_OVERWRITES = 1'b1;
localparam CFG_CAL_REQ = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_RDWR = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD = 0 + CTL_RD_TO_RD_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 0 + CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_BC = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_PCH = 0 + CTL_RD_TO_PCH_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR = 0 + CTL_WR_TO_WR_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 0 + CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_BC = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 0;
localparam CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_PERIOD = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_PERIOD = 0;
localparam CFG_OUTPUT_REGD = CTL_OUTPUT_REGD;
localparam CFG_MASK_CORR_DROPPED_INTR = 0;
localparam CFG_USER_RFSH = CTL_USR_REFRESH;
localparam CFG_REGDIMM_ENABLE = CTL_REGDIMM_ENABLED;
localparam CFG_ENABLE_BURST_INTERRUPT = CTL_ENABLE_BURST_INTERRUPT;
localparam CFG_ENABLE_BURST_TERMINATE = CTL_ENABLE_BURST_TERMINATE;
localparam CFG_ENABLE_WDATA_PATH_LATENCY = CTL_ENABLE_WDATA_PATH_LATENCY;
localparam CFG_ENABLE_BURST_MERGE = ENABLE_BURST_MERGE;
localparam CFG_PORT_WIDTH_TYPE = 3;
localparam CFG_PORT_WIDTH_INTERFACE_WIDTH = 8;
localparam CFG_PORT_WIDTH_BURST_LENGTH = 5;
localparam CFG_PORT_WIDTH_DEVICE_WIDTH = 4;
localparam CFG_PORT_WIDTH_REORDER_DATA = 1;
localparam CFG_PORT_WIDTH_STARVE_LIMIT = 6;
localparam CFG_PORT_WIDTH_OUTPUT_REGD = 2;
localparam CFG_PORT_WIDTH_ADDR_ORDER = 2;
localparam CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CAS_WR_LAT = 4;
localparam CFG_PORT_WIDTH_ADD_LAT = 4;
localparam CFG_PORT_WIDTH_TCL = 4;
localparam CFG_PORT_WIDTH_TRRD = 4;
localparam CFG_PORT_WIDTH_TFAW = 6;
localparam CFG_PORT_WIDTH_TRFC = 9; //case:234203
localparam CFG_PORT_WIDTH_TREFI = 14; //case:234203
localparam CFG_PORT_WIDTH_TRCD = 4;
localparam CFG_PORT_WIDTH_TRP = 4;
localparam CFG_PORT_WIDTH_TWR = 5; //case:234203
localparam CFG_PORT_WIDTH_TWTR = 4;
localparam CFG_PORT_WIDTH_TRTP = 4;
localparam CFG_PORT_WIDTH_TRAS = 6; //case:234203
localparam CFG_PORT_WIDTH_TRC = 6;
localparam CFG_PORT_WIDTH_TCCD = 4;
localparam CFG_PORT_WIDTH_TMRD = 3;
localparam CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10;
localparam CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4;
localparam CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4;
localparam CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES = ((CTL_REGDIMM_ENABLED == 1) ? 13 : 6);
localparam CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 1;
localparam CFG_PORT_WIDTH_ENABLE_ECC = 1;
localparam CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1;
localparam CFG_PORT_WIDTH_GEN_SBE = 1;
localparam CFG_PORT_WIDTH_GEN_DBE = 1;
localparam CFG_PORT_WIDTH_ENABLE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_SBE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_DBE_INTR = 1;
localparam CFG_PORT_WIDTH_CLR_INTR = 1;
localparam CFG_PORT_WIDTH_USER_RFSH = 1;
localparam CFG_PORT_WIDTH_SELF_RFSH = 1;
localparam CFG_PORT_WIDTH_REGDIMM_ENABLE = 1;
localparam CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1;
localparam CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1;
localparam CFG_RDATA_RETURN_MODE = (CFG_REORDER_DATA == 1) ? "INORDER" : "PASSTHROUGH";
localparam CFG_LPDDR2_ENABLED = (CFG_TYPE == `MMR_TYPE_LPDDR2) ? 1 : 0;
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = (CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH);
localparam STS_PORT_WIDTH_SBE_ERROR = 1;
localparam STS_PORT_WIDTH_DBE_ERROR = 1;
localparam STS_PORT_WIDTH_CORR_DROP_ERROR = 1;
localparam STS_PORT_WIDTH_SBE_COUNT = 8;
localparam STS_PORT_WIDTH_DBE_COUNT = 8;
localparam STS_PORT_WIDTH_CORR_DROP_COUNT = 8;
// We are supposed to use these parameters when the CSR is enabled
// but the MAX_ parameters are not defined
//localparam AFI_CS_WIDTH = (MAX_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CKE_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ODT_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ADDR_WIDTH = (MAX_CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_BA_WIDTH = (MAX_CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * MAX_CFG_MEM_IF_CHIP);
localparam AFI_CS_WIDTH = (CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CKE_WIDTH = (CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ODT_WIDTH = (CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ADDR_WIDTH = (CFG_AFI_IF_FR_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_BA_WIDTH = (CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP);
localparam AFI_CMD_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_DQS_BURST_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_VALID_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_DM_WIDTH = (CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_WLAT_WIDTH = CFG_WLAT_BUS_WIDTH;
localparam AFI_RDATA_EN_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_RDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_RDATA_VALID_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_RRANK_WIDTH = CFG_RRANK_BUS_WIDTH;
localparam AFI_WRANK_WIDTH = CFG_WRANK_BUS_WIDTH;
localparam AFI_RLAT_WIDTH = CFG_RLAT_BUS_WIDTH;
localparam AFI_OTF_BITNUM = 12;
localparam AFI_AUTO_PRECHARGE_BITNUM = 10;
localparam AFI_MEM_CLK_DISABLE_WIDTH = CFG_MEM_IF_CLK_PAIR_COUNT;
//////////////////////////////////////////////////////////////////////////////
// BEGIN PORT SECTION
// Clk and reset signals
input clk;
input half_clk;
input reset_n;
// Command channel
output itf_cmd_ready;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
input [CFG_LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// Write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
input [CFG_LOCAL_BE_WIDTH - 1 : 0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
// Read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
// AFI signals
output [AFI_CMD_WIDTH - 1 : 0] afi_rst_n;
output [AFI_CS_WIDTH - 1 : 0] afi_cs_n;
output [AFI_CKE_WIDTH - 1 : 0] afi_cke;
output [AFI_ODT_WIDTH - 1 : 0] afi_odt;
output [AFI_ADDR_WIDTH - 1 : 0] afi_addr;
output [AFI_BA_WIDTH - 1 : 0] afi_ba;
output [AFI_CMD_WIDTH - 1 : 0] afi_ras_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_cas_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_we_n;
output [AFI_DQS_BURST_WIDTH - 1 : 0] afi_dqs_burst;
output [AFI_WDATA_VALID_WIDTH - 1 : 0] afi_wdata_valid;
output [AFI_WDATA_WIDTH - 1 : 0] afi_wdata;
output [AFI_DM_WIDTH - 1 : 0] afi_dm;
input [AFI_WLAT_WIDTH - 1 : 0] afi_wlat;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en_full;
output [AFI_RRANK_WIDTH - 1 : 0] afi_rrank;
output [AFI_WRANK_WIDTH - 1 : 0] afi_wrank;
input [AFI_RDATA_WIDTH - 1 : 0] afi_rdata;
input [AFI_RDATA_VALID_WIDTH - 1 : 0] afi_rdata_valid;
input [AFI_RLAT_WIDTH - 1 : 0] afi_rlat;
input afi_cal_success;
input afi_cal_fail;
output afi_cal_req;
output afi_init_req;
output [AFI_MEM_CLK_DISABLE_WIDTH - 1 : 0] afi_mem_clk_disable;
output [AFI_CAL_BYTE_LANE_SEL_N_WIDTH - 1 : 0] afi_cal_byte_lane_sel_n;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// Sideband signals
output local_init_done;
output local_refresh_ack;
output local_powerdn_ack;
output local_self_rfsh_ack;
output local_deep_powerdn_ack;
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_powerdn_req;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_deep_powerdn_chip;
input local_zqcal_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_zqcal_chip;
input local_multicast;
input local_priority;
// Csr & ecc signals
output ecc_interrupt;
input csr_read_req;
input csr_write_req;
input [1 - 1 : 0] csr_burst_count;
input csr_beginbursttransfer;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
input [CSR_BE_WIDTH - 1 : 0] csr_be;
output csr_rdata_valid;
output csr_waitrequest;
// Refresh controller signals
output tbp_empty;
output cmd_gen_busy;
output sideband_in_refresh;
// END PORT SECTION
//////////////////////////////////////////////////////////////////////////////
wire [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_gen_sbe;
wire cfg_gen_dbe;
wire cfg_reorder_data;
wire cfg_user_rfsh;
wire cfg_regdimm_enable;
wire cfg_enable_burst_interrupt;
wire cfg_enable_burst_terminate;
wire cfg_enable_dqs_tracking;
wire [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd;
wire cfg_enable_no_dm;
wire cfg_enable_ecc_code_overwrites;
wire [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
wire [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
wire [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
wire [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
wire [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
wire [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
wire [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
wire [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
wire [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
wire [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
wire [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
wire [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
wire [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
wire [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
wire [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
wire [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
wire [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
wire [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
wire [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES - 1 : 0] cfg_mem_clk_entry_cycles;
wire [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
wire cfg_enable_intr;
wire cfg_mask_sbe_intr;
wire cfg_mask_dbe_intr;
wire cfg_clr_intr;
wire cfg_cal_req;
wire [4 - 1 : 0] cfg_clock_off;
wire cfg_self_rfsh;
wire cfg_ganged_arf;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
wire [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] cfg_starve_limit;
wire [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip;
wire [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip;
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
wire [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] cfg_device_width;
wire [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
wire cfg_mask_corr_dropped_intr;
wire [2 - 1 : 0] cfg_mem_bl;
wire cfg_user_ecc_en;
//ECC related outputs from controller to csr
wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
wire [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
wire [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
//
// Reconfiguration Support
//
// cfg_* signals may be reconfigured to different values using the Configuration Status Registers
// - some cfg_* signals are not reconfigurable, and are always assigned to parameters
// - When CSR is not enabled
// - cfg_* signals are assigned to parameters
// - when CSR is enabled
// - cfg_* signals are assigned to csr_* signals
// - csr_* signal generation based on Configuration Registers
// - default value for csr_* signals are based on parameters
// cfg_* signals that are not reconfigurable
assign cfg_type = CFG_TYPE;
assign cfg_interface_width = CFG_INTERFACE_WIDTH;
assign cfg_device_width = CFG_DEVICE_WIDTH;
assign cfg_enable_ecc_code_overwrites = CFG_ENABLE_ECC_CODE_OVERWRITES;
assign cfg_enable_no_dm = CFG_ENABLE_NO_DM;
assign cfg_output_regd = CFG_OUTPUT_REGD;
assign cfg_pdn_exit_cycles = CFG_PDN_EXIT_CYCLES;
assign cfg_power_saving_exit_cycles = CFG_POWER_SAVING_EXIT_CYCLES;
assign cfg_mem_clk_entry_cycles = CFG_MEM_CLK_ENTRY_CYCLES;
assign cfg_self_rfsh_exit_cycles = CFG_SELF_RFSH_EXIT_CYCLES;
assign cfg_tccd = CFG_TCCD;
assign cfg_tmrd = CFG_TMRD;
assign cfg_user_rfsh = CFG_USER_RFSH;
assign cfg_write_odt_chip = CFG_WRITE_ODT_CHIP;
assign cfg_read_odt_chip = CFG_READ_ODT_CHIP;
assign cfg_enable_dqs_tracking = CFG_ENABLE_DQS_TRACKING;
assign cfg_enable_burst_interrupt = CFG_ENABLE_BURST_INTERRUPT;
assign cfg_enable_burst_terminate = CFG_ENABLE_BURST_TERMINATE;
assign cfg_extra_ctl_clk_act_to_rdwr = CFG_EXTRA_CTL_CLK_ACT_TO_RDWR;
assign cfg_extra_ctl_clk_act_to_pch = CFG_EXTRA_CTL_CLK_ACT_TO_PCH;
assign cfg_extra_ctl_clk_act_to_act = CFG_EXTRA_CTL_CLK_ACT_TO_ACT;
assign cfg_extra_ctl_clk_rd_to_rd = CFG_EXTRA_CTL_CLK_RD_TO_RD;
assign cfg_extra_ctl_clk_rd_to_rd_diff_chip = CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP;
assign cfg_extra_ctl_clk_rd_to_wr = CFG_EXTRA_CTL_CLK_RD_TO_WR;
assign cfg_extra_ctl_clk_rd_to_wr_bc = CFG_EXTRA_CTL_CLK_RD_TO_WR_BC;
assign cfg_extra_ctl_clk_rd_to_wr_diff_chip = CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP;
assign cfg_extra_ctl_clk_rd_to_pch = CFG_EXTRA_CTL_CLK_RD_TO_PCH;
assign cfg_extra_ctl_clk_rd_ap_to_valid = CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID;
assign cfg_extra_ctl_clk_wr_to_wr = CFG_EXTRA_CTL_CLK_WR_TO_WR;
assign cfg_extra_ctl_clk_wr_to_wr_diff_chip = CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP;
assign cfg_extra_ctl_clk_wr_to_rd = CFG_EXTRA_CTL_CLK_WR_TO_RD;
assign cfg_extra_ctl_clk_wr_to_rd_bc = CFG_EXTRA_CTL_CLK_WR_TO_RD_BC;
assign cfg_extra_ctl_clk_wr_to_rd_diff_chip = CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP;
assign cfg_extra_ctl_clk_wr_to_pch = CFG_EXTRA_CTL_CLK_WR_TO_PCH;
assign cfg_extra_ctl_clk_wr_ap_to_valid = CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID;
assign cfg_extra_ctl_clk_pch_to_valid = CFG_EXTRA_CTL_CLK_PCH_TO_VALID;
assign cfg_extra_ctl_clk_pch_all_to_valid = CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID;
assign cfg_extra_ctl_clk_act_to_act_diff_bank = CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK;
assign cfg_extra_ctl_clk_four_act_to_act = CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT;
assign cfg_extra_ctl_clk_arf_to_valid = CFG_EXTRA_CTL_CLK_ARF_TO_VALID;
assign cfg_extra_ctl_clk_pdn_to_valid = CFG_EXTRA_CTL_CLK_PDN_TO_VALID;
assign cfg_extra_ctl_clk_srf_to_valid = CFG_EXTRA_CTL_CLK_SRF_TO_VALID;
assign cfg_extra_ctl_clk_srf_to_zq_cal = CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL;
assign cfg_extra_ctl_clk_arf_period = CFG_EXTRA_CTL_CLK_ARF_PERIOD;
assign cfg_extra_ctl_clk_pdn_period = CFG_EXTRA_CTL_CLK_PDN_PERIOD;
// cfg_* signals that are reconfigurable
generate
if (CTL_CSR_ENABLED == 1 || CTL_ECC_ENABLED == 1) begin
wire [CFG_PORT_WIDTH_TYPE - 1 : 0] csr_cfg_type;
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] csr_cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] csr_cfg_addr_order;
wire csr_cfg_enable_ecc;
wire csr_cfg_enable_auto_corr;
wire csr_cfg_gen_sbe;
wire csr_cfg_gen_dbe;
wire csr_cfg_reorder_data;
wire csr_cfg_regdimm_enable;
wire [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] csr_cfg_cas_wr_lat;
wire [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] csr_cfg_add_lat;
wire [CFG_PORT_WIDTH_TCL - 1 : 0] csr_cfg_tcl;
wire [CFG_PORT_WIDTH_TRRD - 1 : 0] csr_cfg_trrd;
wire [CFG_PORT_WIDTH_TFAW - 1 : 0] csr_cfg_tfaw;
wire [CFG_PORT_WIDTH_TRFC - 1 : 0] csr_cfg_trfc;
wire [CFG_PORT_WIDTH_TREFI - 1 : 0] csr_cfg_trefi;
wire [CFG_PORT_WIDTH_TRCD - 1 : 0] csr_cfg_trcd;
wire [CFG_PORT_WIDTH_TRP - 1 : 0] csr_cfg_trp;
wire [CFG_PORT_WIDTH_TWR - 1 : 0] csr_cfg_twr;
wire [CFG_PORT_WIDTH_TWTR - 1 : 0] csr_cfg_twtr;
wire [CFG_PORT_WIDTH_TRTP - 1 : 0] csr_cfg_trtp;
wire [CFG_PORT_WIDTH_TRAS - 1 : 0] csr_cfg_tras;
wire [CFG_PORT_WIDTH_TRC - 1 : 0] csr_cfg_trc;
wire [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] csr_cfg_auto_pd_cycles;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] csr_cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] csr_cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] csr_cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] csr_cfg_cs_addr_width;
wire csr_cfg_enable_intr;
wire csr_cfg_mask_sbe_intr;
wire csr_cfg_mask_dbe_intr;
wire csr_cfg_clr_intr;
wire csr_cfg_cal_req;
wire [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] csr_cfg_clock_off;
wire csr_cfg_self_rfsh;
wire csr_cfg_ganged_arf;
wire [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] csr_cfg_starve_limit;
wire [8 - 1 : 0] int_csr_cfg_starve_limit;
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] csr_cfg_interface_width;
wire [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] csr_cfg_device_width;
wire csr_cfg_mask_corr_dropped_intr;
wire [2 - 1 : 0] csr_cfg_mem_bl;
wire csr_cfg_user_ecc_en;
assign cfg_burst_length = csr_cfg_burst_length;
assign cfg_reorder_data = csr_cfg_reorder_data;
assign csr_cfg_starve_limit = int_csr_cfg_starve_limit;
assign cfg_starve_limit = csr_cfg_starve_limit;
assign cfg_addr_order = csr_cfg_addr_order;
assign cfg_col_addr_width = csr_cfg_col_addr_width;
assign cfg_row_addr_width = csr_cfg_row_addr_width;
assign cfg_bank_addr_width = csr_cfg_bank_addr_width;
assign cfg_cs_addr_width = csr_cfg_cs_addr_width;
assign cfg_cas_wr_lat = csr_cfg_cas_wr_lat;
assign cfg_add_lat = csr_cfg_add_lat;
assign cfg_tcl = csr_cfg_tcl;
assign cfg_trrd = csr_cfg_trrd;
assign cfg_tfaw = csr_cfg_tfaw;
assign cfg_trfc = csr_cfg_trfc;
assign cfg_trefi = csr_cfg_trefi;
assign cfg_trcd = csr_cfg_trcd;
assign cfg_trp = csr_cfg_trp;
assign cfg_twr = csr_cfg_twr;
assign cfg_twtr = csr_cfg_twtr;
assign cfg_trtp = csr_cfg_trtp;
assign cfg_tras = csr_cfg_tras;
assign cfg_trc = csr_cfg_trc;
assign cfg_enable_ecc = csr_cfg_enable_ecc;
assign cfg_enable_auto_corr = csr_cfg_enable_auto_corr;
assign cfg_gen_sbe = csr_cfg_gen_sbe;
assign cfg_gen_dbe = csr_cfg_gen_dbe;
assign cfg_enable_intr = csr_cfg_enable_intr;
assign cfg_mask_sbe_intr = csr_cfg_mask_sbe_intr;
assign cfg_mask_dbe_intr = csr_cfg_mask_dbe_intr;
assign cfg_mask_corr_dropped_intr = csr_cfg_mask_corr_dropped_intr;
assign cfg_clr_intr = csr_cfg_clr_intr;
assign cfg_regdimm_enable = csr_cfg_regdimm_enable;
assign cfg_cal_req = csr_cfg_cal_req;
assign cfg_auto_pd_cycles = csr_cfg_auto_pd_cycles;
alt_mem_ddrx_csr # (
.CFG_AVALON_ADDR_WIDTH ( CSR_ADDR_WIDTH ),
.CFG_AVALON_DATA_WIDTH ( CSR_DATA_WIDTH ),
.CFG_BURST_LENGTH ( CFG_BURST_LENGTH ),
.CFG_REORDER_DATA ( CFG_REORDER_DATA ),
.CFG_STARVE_LIMIT ( CFG_STARVE_LIMIT ),
.CFG_ADDR_ORDER ( CFG_ADDR_ORDER ),
.CFG_COL_ADDR_WIDTH ( CFG_COL_ADDR_WIDTH ),
.CFG_ROW_ADDR_WIDTH ( CFG_ROW_ADDR_WIDTH ),
.CFG_BANK_ADDR_WIDTH ( CFG_BANK_ADDR_WIDTH ),
.CFG_CS_ADDR_WIDTH ( CFG_CS_ADDR_WIDTH ),
.CFG_CAS_WR_LAT ( CFG_CAS_WR_LAT ),
.CFG_ADD_LAT ( CFG_ADD_LAT ),
.CFG_TCL ( CFG_TCL ),
.CFG_TRRD ( CFG_TRRD ),
.CFG_TFAW ( CFG_TFAW ),
.CFG_TRFC ( CFG_TRFC ),
.CFG_TREFI ( CFG_TREFI ),
.CFG_TRCD ( CFG_TRCD ),
.CFG_TRP ( CFG_TRP ),
.CFG_TWR ( CFG_TWR ),
.CFG_TWTR ( CFG_TWTR ),
.CFG_TRTP ( CFG_TRTP ),
.CFG_TRAS ( CFG_TRAS ),
.CFG_TRC ( CFG_TRC ),
.CFG_AUTO_PD_CYCLES ( CFG_AUTO_PD_CYCLES ),
.CFG_ENABLE_ECC ( CFG_ENABLE_ECC ),
.CTL_ECC_CSR_ENABLED ( CFG_ENABLE_ECC ),
.CTL_CSR_ENABLED ( CTL_CSR_ENABLED ),
.CFG_ENABLE_AUTO_CORR ( CFG_ENABLE_AUTO_CORR ),
.CFG_REGDIMM_ENABLE ( CFG_REGDIMM_ENABLE ),
.MEM_IF_DQS_WIDTH ( CFG_MEM_IF_DQS_WIDTH )
) register_control_inst (
.avalon_mm_read ( csr_read_req ),
.avalon_mm_write ( csr_write_req ),
.avalon_mm_addr ( csr_addr ),
.avalon_mm_wdata ( csr_wdata ),
.avalon_mm_rdata ( csr_rdata ),
.avalon_mm_be ( csr_be ),
.avalon_mm_waitrequest ( csr_waitrequest ),
.avalon_mm_rdata_valid ( csr_rdata_valid ),
.cfg_burst_length ( csr_cfg_burst_length ),
.cfg_addr_order ( csr_cfg_addr_order ),
.cfg_enable_ecc ( csr_cfg_enable_ecc ),
.cfg_enable_auto_corr ( csr_cfg_enable_auto_corr ),
.cfg_gen_sbe ( csr_cfg_gen_sbe ),
.cfg_gen_dbe ( csr_cfg_gen_dbe ),
.cfg_reorder_data ( csr_cfg_reorder_data ),
.cfg_regdimm_enable ( csr_cfg_regdimm_enable ),
.cfg_cas_wr_lat ( csr_cfg_cas_wr_lat ),
.cfg_add_lat ( csr_cfg_add_lat ),
.cfg_tcl ( csr_cfg_tcl ),
.cfg_trrd ( csr_cfg_trrd ),
.cfg_tfaw ( csr_cfg_tfaw ),
.cfg_trfc ( csr_cfg_trfc ),
.cfg_trefi ( csr_cfg_trefi ),
.cfg_trcd ( csr_cfg_trcd ),
.cfg_trp ( csr_cfg_trp ),
.cfg_twr ( csr_cfg_twr ),
.cfg_twtr ( csr_cfg_twtr ),
.cfg_trtp ( csr_cfg_trtp ),
.cfg_tras ( csr_cfg_tras ),
.cfg_trc ( csr_cfg_trc ),
.cfg_auto_pd_cycles ( csr_cfg_auto_pd_cycles ),
.cfg_col_addr_width ( csr_cfg_col_addr_width ),
.cfg_row_addr_width ( csr_cfg_row_addr_width ),
.cfg_bank_addr_width ( csr_cfg_bank_addr_width ),
.cfg_cs_addr_width ( csr_cfg_cs_addr_width ),
.cfg_enable_intr ( csr_cfg_enable_intr ),
.cfg_mask_sbe_intr ( csr_cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr ( csr_cfg_mask_dbe_intr ),
.cfg_clr_intr ( csr_cfg_clr_intr ),
.cfg_clock_off ( csr_cfg_clock_off ),
.cfg_starve_limit ( int_csr_cfg_starve_limit ),
.cfg_mask_corr_dropped_intr ( csr_cfg_mask_corr_dropped_intr ),
.cfg_cal_req ( csr_cfg_cal_req ),
.local_power_down_ack ( local_powerdn_ack ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.sts_cal_success ( afi_cal_success ),
.sts_cal_fail ( afi_cal_fail ),
.sts_sbe_error ( sts_sbe_error ),
.sts_dbe_error ( sts_dbe_error ),
.sts_sbe_count ( sts_sbe_count ),
.sts_dbe_count ( sts_dbe_count ),
.sts_err_addr ( {{(32-CFG_LOCAL_ADDR_WIDTH){1'b0}} ,sts_err_addr} ),
.sts_corr_dropped ( sts_corr_dropped ),
.sts_corr_dropped_count ( sts_corr_dropped_count ),
.sts_corr_dropped_addr ( {{(32-CFG_LOCAL_ADDR_WIDTH){1'b0}} ,sts_corr_dropped_addr}),
.ctl_clk ( clk ),
.ctl_rst_n ( reset_n )
);
end
else begin
assign csr_rdata = 0;
assign csr_rdata_valid = 0;
assign csr_waitrequest = 0;
assign cfg_burst_length = CFG_BURST_LENGTH;
assign cfg_reorder_data = CFG_REORDER_DATA;
assign cfg_starve_limit = CFG_STARVE_LIMIT;
assign cfg_addr_order = CFG_ADDR_ORDER;
assign cfg_col_addr_width = CFG_COL_ADDR_WIDTH;
assign cfg_row_addr_width = CFG_ROW_ADDR_WIDTH;
assign cfg_bank_addr_width = CFG_BANK_ADDR_WIDTH;
assign cfg_cs_addr_width = CFG_CS_ADDR_WIDTH;
assign cfg_cas_wr_lat = CFG_CAS_WR_LAT;
assign cfg_add_lat = CFG_ADD_LAT;
assign cfg_tcl = CFG_TCL;
assign cfg_trrd = CFG_TRRD;
assign cfg_tfaw = CFG_TFAW;
assign cfg_trfc = CFG_TRFC;
assign cfg_trefi = CFG_TREFI;
assign cfg_trcd = CFG_TRCD;
assign cfg_trp = CFG_TRP;
assign cfg_twr = CFG_TWR;
assign cfg_twtr = CFG_TWTR;
assign cfg_trtp = CFG_TRTP;
assign cfg_tras = CFG_TRAS;
assign cfg_trc = CFG_TRC;
assign cfg_auto_pd_cycles = CFG_AUTO_PD_CYCLES;
assign cfg_enable_ecc = CFG_ENABLE_ECC;
assign cfg_enable_auto_corr = CFG_ENABLE_AUTO_CORR;
assign cfg_gen_sbe = CFG_GEN_SBE;
assign cfg_gen_dbe = CFG_GEN_DBE;
assign cfg_enable_intr = CFG_ENABLE_INTR;
assign cfg_mask_sbe_intr = CFG_MASK_SBE_INTR;
assign cfg_mask_dbe_intr = CFG_MASK_DBE_INTR;
assign cfg_mask_corr_dropped_intr = CFG_MASK_CORR_DROPPED_INTR;
assign cfg_clr_intr = CFG_CLR_INTR;
assign cfg_regdimm_enable = CFG_REGDIMM_ENABLE;
assign cfg_cal_req = CFG_CAL_REQ;
end
endgenerate
// Next Gen Controller
alt_mem_ddrx_controller # (
.CFG_LOCAL_SIZE_WIDTH ( CFG_LOCAL_SIZE_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH ( CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_DATA_WIDTH ( CFG_LOCAL_DATA_WIDTH ),
.CFG_LOCAL_ID_WIDTH ( CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_IF_TYPE ( CFG_LOCAL_IF_TYPE ),
.CFG_MEM_IF_ADDR_WIDTH ( CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_CLK_PAIR_COUNT ( CFG_MEM_IF_CLK_PAIR_COUNT ),
.CFG_DWIDTH_RATIO ( CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED ( CFG_ODT_ENABLED ),
.CFG_LPDDR2_ENABLED ( CFG_LPDDR2_ENABLED ),
.CFG_CTL_TBP_NUM ( CFG_CTL_TBP_NUM ),
.CFG_DATA_REORDERING_TYPE ( CFG_DATA_REORDERING_TYPE ),
.CFG_WRBUFFER_ADDR_WIDTH ( CFG_WRBUFFER_ADDR_WIDTH ),
.CFG_RDBUFFER_ADDR_WIDTH ( CFG_RDBUFFER_ADDR_WIDTH ),
.CFG_MAX_PENDING_RD_CMD ( CFG_MAX_PENDING_RD_CMD ),
.CFG_MAX_PENDING_WR_CMD ( CFG_MAX_PENDING_WR_CMD ),
.CFG_ECC_MULTIPLES_16_24_40_72 ( CFG_ECC_MULTIPLES_16_24_40_72 ),
.CFG_MEM_IF_CS_WIDTH ( CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_CHIP ( CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_BA_WIDTH ( CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH ( CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH ( CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_CKE_WIDTH ( CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ODT_WIDTH ( CFG_MEM_IF_ODT_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH ( CFG_MEM_IF_DQS_WIDTH ),
.CFG_MEM_IF_DQ_WIDTH ( CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DM_WIDTH ( CFG_MEM_IF_DM_WIDTH ),
.CFG_PORT_WIDTH_TYPE ( CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_INTERFACE_WIDTH ( CFG_PORT_WIDTH_INTERFACE_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH ( CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_DEVICE_WIDTH ( CFG_PORT_WIDTH_DEVICE_WIDTH ),
.CFG_PORT_WIDTH_REORDER_DATA ( CFG_PORT_WIDTH_REORDER_DATA ),
.CFG_PORT_WIDTH_STARVE_LIMIT ( CFG_PORT_WIDTH_STARVE_LIMIT ),
.CFG_PORT_WIDTH_OUTPUT_REGD ( CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_PORT_WIDTH_ADDR_ORDER ( CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH ( CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH ( CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH ( CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH ( CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT ( CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_ADD_LAT ( CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TCL ( CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_TRRD ( CFG_PORT_WIDTH_TRRD ),
.CFG_PORT_WIDTH_TFAW ( CFG_PORT_WIDTH_TFAW ),
.CFG_PORT_WIDTH_TRFC ( CFG_PORT_WIDTH_TRFC ),
.CFG_PORT_WIDTH_TREFI ( CFG_PORT_WIDTH_TREFI ),
.CFG_PORT_WIDTH_TRCD ( CFG_PORT_WIDTH_TRCD ),
.CFG_PORT_WIDTH_TRP ( CFG_PORT_WIDTH_TRP ),
.CFG_PORT_WIDTH_TWR ( CFG_PORT_WIDTH_TWR ),
.CFG_PORT_WIDTH_TWTR ( CFG_PORT_WIDTH_TWTR ),
.CFG_PORT_WIDTH_TRTP ( CFG_PORT_WIDTH_TRTP ),
.CFG_PORT_WIDTH_TRAS ( CFG_PORT_WIDTH_TRAS ),
.CFG_PORT_WIDTH_TRC ( CFG_PORT_WIDTH_TRC ),
.CFG_PORT_WIDTH_TCCD ( CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_TMRD ( CFG_PORT_WIDTH_TMRD ),
.CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ( CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ),
.CFG_PORT_WIDTH_PDN_EXIT_CYCLES ( CFG_PORT_WIDTH_PDN_EXIT_CYCLES ),
.CFG_PORT_WIDTH_AUTO_PD_CYCLES ( CFG_PORT_WIDTH_AUTO_PD_CYCLES ),
.CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ( CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ),
.CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES ( CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ),
.CFG_PORT_WIDTH_ENABLE_ECC ( CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR ( CFG_PORT_WIDTH_ENABLE_AUTO_CORR ),
.CFG_PORT_WIDTH_GEN_SBE ( CFG_PORT_WIDTH_GEN_SBE ),
.CFG_PORT_WIDTH_GEN_DBE ( CFG_PORT_WIDTH_GEN_DBE ),
.CFG_PORT_WIDTH_ENABLE_INTR ( CFG_PORT_WIDTH_ENABLE_INTR ),
.CFG_PORT_WIDTH_MASK_SBE_INTR ( CFG_PORT_WIDTH_MASK_SBE_INTR ),
.CFG_PORT_WIDTH_MASK_DBE_INTR ( CFG_PORT_WIDTH_MASK_DBE_INTR ),
.CFG_PORT_WIDTH_CLR_INTR ( CFG_PORT_WIDTH_CLR_INTR ),
.CFG_PORT_WIDTH_USER_RFSH ( CFG_PORT_WIDTH_USER_RFSH ),
.CFG_PORT_WIDTH_SELF_RFSH ( CFG_PORT_WIDTH_SELF_RFSH ),
.CFG_PORT_WIDTH_REGDIMM_ENABLE ( CFG_PORT_WIDTH_REGDIMM_ENABLE ),
.CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ( CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ),
.CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ( CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ),
.CFG_ENABLE_WDATA_PATH_LATENCY ( CFG_ENABLE_WDATA_PATH_LATENCY ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP ( CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP ( CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_WLAT_BUS_WIDTH ( CFG_WLAT_BUS_WIDTH ),
.CFG_RRANK_BUS_WIDTH ( CFG_RRANK_BUS_WIDTH ),
.CFG_WRANK_BUS_WIDTH ( CFG_WRANK_BUS_WIDTH ),
.CFG_USE_SHADOW_REGS ( CFG_USE_SHADOW_REGS ),
.CFG_RDATA_RETURN_MODE ( CFG_RDATA_RETURN_MODE ),
.CFG_ECC_DECODER_REG ( CFG_ECC_DECODER_REG ),
.CFG_ERRCMD_FIFO_REG ( CFG_ERRCMD_FIFO_REG ),
.CFG_ENABLE_BURST_MERGE ( CFG_ENABLE_BURST_MERGE )
) controller_inst (
.ctl_clk ( clk ),
.ctl_reset_n ( reset_n ),
.itf_cmd_ready ( itf_cmd_ready ),
.itf_cmd_valid ( itf_cmd_valid ),
.itf_cmd ( itf_cmd ),
.itf_cmd_address ( itf_cmd_address ),
.itf_cmd_burstlen ( itf_cmd_burstlen ),
.itf_cmd_id ( itf_cmd_id ),
.itf_cmd_priority ( itf_cmd_priority ),
.itf_cmd_autopercharge ( itf_cmd_autopercharge ),
.itf_cmd_multicast ( itf_cmd_multicast ),
.itf_wr_data_ready ( itf_wr_data_ready ),
.itf_wr_data_valid ( itf_wr_data_valid ),
.itf_wr_data ( itf_wr_data ),
.itf_wr_data_byte_en ( itf_wr_data_byte_en ),
.itf_wr_data_begin ( itf_wr_data_begin ),
.itf_wr_data_last ( itf_wr_data_last ),
.itf_wr_data_id ( itf_wr_data_id ),
.itf_rd_data_ready ( itf_rd_data_ready ),
.itf_rd_data_valid ( itf_rd_data_valid ),
.itf_rd_data ( itf_rd_data ),
.itf_rd_data_error ( itf_rd_data_error ),
.itf_rd_data_begin ( itf_rd_data_begin ),
.itf_rd_data_last ( itf_rd_data_last ),
.itf_rd_data_id ( itf_rd_data_id ),
.local_refresh_req ( local_refresh_req ),
.local_refresh_chip ( local_refresh_chip ),
.local_deep_powerdn_req ( local_deep_powerdn_req ),
.local_deep_powerdn_chip ( local_deep_powerdn_chip ),
.local_self_rfsh_req ( local_self_rfsh_req ),
.local_self_rfsh_chip ( local_self_rfsh_chip ),
.local_zqcal_req ( local_zqcal_req ),
.local_zqcal_chip ( local_zqcal_chip ),
.local_refresh_ack ( local_refresh_ack ),
.local_deep_powerdn_ack ( local_deep_powerdn_ack ),
.local_power_down_ack ( local_powerdn_ack ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.local_init_done ( local_init_done ),
.afi_cke ( afi_cke ),
.afi_cs_n ( afi_cs_n ),
.afi_ras_n ( afi_ras_n ),
.afi_cas_n ( afi_cas_n ),
.afi_we_n ( afi_we_n ),
.afi_ba ( afi_ba ),
.afi_addr ( afi_addr ),
.afi_odt ( afi_odt ),
.afi_rst_n ( afi_rst_n ),
.afi_dqs_burst ( afi_dqs_burst ),
.afi_wdata_valid ( afi_wdata_valid ),
.afi_wdata ( afi_wdata ),
.afi_dm ( afi_dm ),
.afi_wlat ( afi_wlat ),
.afi_rdata_en ( afi_rdata_en ),
.afi_rdata_en_full ( afi_rdata_en_full ),
.afi_rrank ( afi_rrank ),
.afi_wrank ( afi_wrank ),
.afi_rdata ( afi_rdata ),
.afi_rdata_valid ( afi_rdata_valid ),
.ctl_cal_success ( afi_cal_success ),
.ctl_cal_fail ( afi_cal_fail ),
.ctl_cal_req ( afi_cal_req ),
.ctl_init_req ( afi_init_req ),
.ctl_mem_clk_disable ( afi_mem_clk_disable ),
.ctl_cal_byte_lane_sel_n ( afi_cal_byte_lane_sel_n ),
.cfg_type ( cfg_type ),
.cfg_interface_width ( cfg_interface_width ),
.cfg_burst_length ( cfg_burst_length ),
.cfg_device_width ( cfg_device_width ),
.cfg_reorder_data ( cfg_reorder_data ),
.cfg_starve_limit ( cfg_starve_limit ),
.cfg_output_regd ( cfg_output_regd ),
.cfg_addr_order ( cfg_addr_order ),
.cfg_col_addr_width ( cfg_col_addr_width ),
.cfg_row_addr_width ( cfg_row_addr_width ),
.cfg_bank_addr_width ( cfg_bank_addr_width ),
.cfg_cs_addr_width ( cfg_cs_addr_width ),
.cfg_cas_wr_lat ( cfg_cas_wr_lat ),
.cfg_add_lat ( cfg_add_lat ),
.cfg_tcl ( cfg_tcl ),
.cfg_trrd ( cfg_trrd ),
.cfg_tfaw ( cfg_tfaw ),
.cfg_trfc ( cfg_trfc ),
.cfg_trefi ( cfg_trefi ),
.cfg_trcd ( cfg_trcd ),
.cfg_trp ( cfg_trp ),
.cfg_twr ( cfg_twr ),
.cfg_twtr ( cfg_twtr ),
.cfg_trtp ( cfg_trtp ),
.cfg_tras ( cfg_tras ),
.cfg_trc ( cfg_trc ),
.cfg_tccd ( cfg_tccd ),
.cfg_auto_pd_cycles ( cfg_auto_pd_cycles ),
.cfg_self_rfsh_exit_cycles ( cfg_self_rfsh_exit_cycles ),
.cfg_pdn_exit_cycles ( cfg_pdn_exit_cycles ),
.cfg_power_saving_exit_cycles ( cfg_power_saving_exit_cycles ),
.cfg_mem_clk_entry_cycles ( cfg_mem_clk_entry_cycles ),
.cfg_tmrd ( cfg_tmrd ),
.cfg_enable_ecc ( cfg_enable_ecc ),
.cfg_enable_auto_corr ( cfg_enable_auto_corr ),
.cfg_enable_no_dm ( cfg_enable_no_dm ),
.cfg_enable_ecc_code_overwrites ( cfg_enable_ecc_code_overwrites ),
.cfg_cal_req ( cfg_cal_req ),
.cfg_gen_sbe ( cfg_gen_sbe ),
.cfg_gen_dbe ( cfg_gen_dbe ),
.cfg_enable_intr ( cfg_enable_intr ),
.cfg_mask_sbe_intr ( cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr ( cfg_mask_dbe_intr ),
.cfg_mask_corr_dropped_intr ( cfg_mask_corr_dropped_intr ),
.cfg_clr_intr ( cfg_clr_intr ),
.cfg_user_rfsh ( cfg_user_rfsh ),
.cfg_regdimm_enable ( cfg_regdimm_enable ),
.cfg_enable_burst_interrupt ( cfg_enable_burst_interrupt ),
.cfg_enable_burst_terminate ( cfg_enable_burst_terminate ),
.cfg_write_odt_chip ( cfg_write_odt_chip ),
.cfg_read_odt_chip ( cfg_read_odt_chip ),
.cfg_extra_ctl_clk_act_to_rdwr ( cfg_extra_ctl_clk_act_to_rdwr ),
.cfg_extra_ctl_clk_act_to_pch ( cfg_extra_ctl_clk_act_to_pch ),
.cfg_extra_ctl_clk_act_to_act ( cfg_extra_ctl_clk_act_to_act ),
.cfg_extra_ctl_clk_rd_to_rd ( cfg_extra_ctl_clk_rd_to_rd ),
.cfg_extra_ctl_clk_rd_to_rd_diff_chip ( cfg_extra_ctl_clk_rd_to_rd_diff_chip ),
.cfg_extra_ctl_clk_rd_to_wr ( cfg_extra_ctl_clk_rd_to_wr ),
.cfg_extra_ctl_clk_rd_to_wr_bc ( cfg_extra_ctl_clk_rd_to_wr_bc ),
.cfg_extra_ctl_clk_rd_to_wr_diff_chip ( cfg_extra_ctl_clk_rd_to_wr_diff_chip ),
.cfg_extra_ctl_clk_rd_to_pch ( cfg_extra_ctl_clk_rd_to_pch ),
.cfg_extra_ctl_clk_rd_ap_to_valid ( cfg_extra_ctl_clk_rd_ap_to_valid ),
.cfg_extra_ctl_clk_wr_to_wr ( cfg_extra_ctl_clk_wr_to_wr ),
.cfg_extra_ctl_clk_wr_to_wr_diff_chip ( cfg_extra_ctl_clk_wr_to_wr_diff_chip ),
.cfg_extra_ctl_clk_wr_to_rd ( cfg_extra_ctl_clk_wr_to_rd ),
.cfg_extra_ctl_clk_wr_to_rd_bc ( cfg_extra_ctl_clk_wr_to_rd_bc ),
.cfg_extra_ctl_clk_wr_to_rd_diff_chip ( cfg_extra_ctl_clk_wr_to_rd_diff_chip ),
.cfg_extra_ctl_clk_wr_to_pch ( cfg_extra_ctl_clk_wr_to_pch ),
.cfg_extra_ctl_clk_wr_ap_to_valid ( cfg_extra_ctl_clk_wr_ap_to_valid ),
.cfg_extra_ctl_clk_pch_to_valid ( cfg_extra_ctl_clk_pch_to_valid ),
.cfg_extra_ctl_clk_pch_all_to_valid ( cfg_extra_ctl_clk_pch_all_to_valid ),
.cfg_extra_ctl_clk_act_to_act_diff_bank ( cfg_extra_ctl_clk_act_to_act_diff_bank ),
.cfg_extra_ctl_clk_four_act_to_act ( cfg_extra_ctl_clk_four_act_to_act ),
.cfg_extra_ctl_clk_arf_to_valid ( cfg_extra_ctl_clk_arf_to_valid ),
.cfg_extra_ctl_clk_pdn_to_valid ( cfg_extra_ctl_clk_pdn_to_valid ),
.cfg_extra_ctl_clk_srf_to_valid ( cfg_extra_ctl_clk_srf_to_valid ),
.cfg_extra_ctl_clk_srf_to_zq_cal ( cfg_extra_ctl_clk_srf_to_zq_cal ),
.cfg_extra_ctl_clk_arf_period ( cfg_extra_ctl_clk_arf_period ),
.cfg_extra_ctl_clk_pdn_period ( cfg_extra_ctl_clk_pdn_period ),
.cfg_enable_dqs_tracking ( cfg_enable_dqs_tracking ),
.ecc_interrupt ( ecc_interrupt ),
.sts_sbe_error ( sts_sbe_error ),
.sts_dbe_error ( sts_dbe_error ),
.sts_sbe_count ( sts_sbe_count ),
.sts_dbe_count ( sts_dbe_count ),
.sts_err_addr ( sts_err_addr ),
.sts_corr_dropped ( sts_corr_dropped ),
.sts_corr_dropped_count ( sts_corr_dropped_count ),
.sts_corr_dropped_addr ( sts_corr_dropped_addr ),
.afi_ctl_refresh_done ( afi_ctl_refresh_done ),
.afi_seq_busy ( afi_seq_busy ),
.afi_ctl_long_idle ( afi_ctl_long_idle ),
.itf_rd_data_id_early ( ),
.itf_rd_data_id_early_valid ( ),
.sts_cal_fail ( ),
.sts_cal_success ( ),
.tbp_empty ( tbp_empty ),
.cmd_gen_busy ( cmd_gen_busy ),
.sideband_in_refresh ( sideband_in_refresh )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311O_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A311O_PP_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a311o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311O_PP_SYMBOL_V
|
`ifndef _REGISTER
`define _REGISTER
module register16(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [15:0] out;
input [15:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 16'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register4(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [3:0] out;
input [3:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 4'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register3(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [2:0] out;
input [2:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 3'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register2(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [1:0] out;
input [1:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 2'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register1(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg out;
input in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 1'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DECAP_TB_V
`define SKY130_FD_SC_HDLL__DECAP_TB_V
/**
* decap: Decoupling capacitance filler.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__decap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hdll__decap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DECAP_TB_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
// Guarded parameter for num_cks < 1 (which is bad usage - see warning in top-level file)
parameter NUM_CKS_1 = (num_cks > 0) ? (num_cks - 1) : 0;
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
reg [NUM_CKS_1:0] monitor;
wire [NUM_CKS_1:0] monitor_1 = (monitor << 1);
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
monitor <= {num_cks{1'b0}};
end
else begin
monitor <= (monitor_1 | start_event);
end
end
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1, fire_2state_2, fire_2state_3;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal overlapping condition of start event is detected");
end
if (fire_2state_2) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expresson is asserted without a corresponding start_event");
end
if (fire_2state_3) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not asserted after elapse of num_cks cycles from start event");
end
end
end
assign fire_2state_1 = ((check_overlapping == 0) && (monitor_1 != {num_cks{1'b0}}) && start_event); // new start_event can occur in cycle test_expr is checked
assign fire_2state_2 = ((check_missing_start != 0) && ~monitor[NUM_CKS_1] && test_expr);
assign fire_2state_3 = (monitor[NUM_CKS_1] && ~test_expr);
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1, fire_xcheck_2;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
if (fire_xcheck_2) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
wire valid_start_event = ((start_event ^ start_event) == 1'b0);
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_start_event) begin
if (valid_start_event) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
always @ (valid_test_expr or monitor) begin
if (valid_test_expr || ~((check_missing_start==1) || monitor[NUM_CKS_1])) begin
fire_xcheck_2 = 1'b0;
end
else begin
fire_xcheck_2 = 1'b1; // test_expr X when check_missing_start or monitor[num_cks-1]
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
wire fire_cover_1, fire_cover_2;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("start_event covered"); // basic
end
if (fire_cover_2) begin
ovl_cover_t("overlapping_start_events covered"); // corner
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (start_event == 1'b1));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && ((check_overlapping==1) && (monitor_1 != {num_cks{1'b0}}) && start_event));
`endif // OVL_COVER_ON
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1,
c2,
locked);
input inclk0;
output c0;
output c1;
output c2;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 6,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 3125,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 16,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 2,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.256000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "0.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.25600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3125"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_PS_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_DFF_PS_SYMBOL_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$PS (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_PS_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_2_V
`define SKY130_FD_SC_LS__AND4BB_2_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4bb_2 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4bb_2 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Rose-Hulman Institute of Technology
// Engineer: Adam Michael
//
// Term Project - Phase 1
//////////////////////////////////////////////////////////////////////////////////
// -----------------------------------------------
// top-level module
// -----------------------------------------------
module PongNexys3(
input InputClock,
input rota,
input rotb,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output hsync,
output vsync
);
//reg clk50_int;
//always @(posedge InputClock) begin
// clk50_int <= ~clk50_int;
//end
//Clock50MHz ClockUnit(InputClock, clk50_int);
//wire clk50;
//BUFG bufg_inst(clk50, clk50_int);
wire clk50;
Clock50MHz ClockUnit(InputClock, clk50);
reg clk25_int;
always @(posedge clk50) begin
clk25_int <= ~clk25_int;
end
wire clk25;
BUFG bufg_inst(clk25, clk25_int);
wire [9:0] xpos;
wire [9:0] ypos;
video_timer video_timer_inst(clk25, hsync, vsync, xpos, ypos);
game game_inst(clk25, xpos, ypos, rota, rotb, red, green, blue);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_PP_V |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_SRAM_inputs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 14: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 14: 0] data_out;
wire [ 14: 0] out_port;
wire [ 14: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {15 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[14 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
`timescale 1ns/1ps
module tb_cocotb (
//Virtual Host Interface Signals
input clk,
input sata_clk,
input rst,
output master_ready,
input in_ready,
input [31:0] in_command,
input [31:0] in_address,
input [31:0] in_data,
input [27:0] in_data_count,
input out_ready,
output out_en,
output [31:0] out_status,
output [31:0] out_address,
output [31:0] out_data,
output [27:0] out_data_count,
input [31:0] test_id,
input ih_reset
);
//Parameters
//Registers/Wires
reg r_rst;
reg r_in_ready;
reg [31:0] r_in_command;
reg [31:0] r_in_address;
reg [31:0] r_in_data;
reg [27:0] r_in_data_count;
reg r_out_ready;
reg r_ih_reset;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
always @ (*) r_in_ready = in_ready;
always @ (*) r_in_command = in_command;
always @ (*) r_in_address = in_address;
always @ (*) r_in_data = in_data;
always @ (*) r_in_data_count = in_data_count;
always @ (*) r_out_ready = out_ready;
always @ (*) r_ih_reset = ih_reset;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (r_rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count),
.i_out_ready (r_out_ready ),
.o_en (out_en ),
.o_status (out_status ),
.o_address (out_address ),
.o_data (out_data ),
.o_data_count (out_data_count ),
.o_master_ready (master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_sdio_device s1 (
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_sel (4'b1111 ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (r_rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:17:40 02/18/2016
// Design Name:
// Module Name: tp_final
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tp_final
(
input wire clk,
input wire reset,
//Debugger unit
input wire rx,
output wire tx,
output wire [7:0] led
//Para test
//output wire ena_pip_test,
//output wire [31:0] pc_incrementado_PC_out_test,
//output wire [31:0] instruction_IF_test,
//output wire [31:0] write_data_WB_out_test
//output wire stallF_HZ_out_test
//output wire [2:0] state_reg_test
);
//Para test
//assign ena_pip_test = ena_pip;
//assign pc_incrementado_PC_out_test = pc_incrementado_PC_out;
//assign instruction_IF_test = instruction_IF;
//assign write_data_WB_out_test = write_data_WB_out;
//assign stallF_HZ_out_test = stallF_HZ_out;
//Debugger
wire ena_pip;
///////////////////////
//Cables del pipeline//
///////////////////////
//PC
wire [31:0] pc_incrementado_PC_out;
//Modulo IF
wire [31:0] pc_PC_out;
wire [31:0] instruction_IF;
//Modulo ID
////Input
wire [31:0] pc_incrementado_ID_in;
wire [31:0] instruction_ID_in;
wire [31:0] write_data_ID_in;
wire [4:0] write_addr_ID_in;
wire [31:0] alu_result_EX_in;
//wire reg_write_ID_in;
////Output
wire [31:0] reg_data1_ID_out;
wire [31:0] reg_data2_ID_out;
wire [31:0] sign_extend_ID_out;
wire [4:0] inst_25_21_ID_out;
wire [4:0] inst_20_16_ID_out;
wire [4:0] inst_15_11_ID_out;
wire [31:0] pc_jump_ID_out;
wire [31:0] pc_branch_ID_out;
//wire [7:0] ex_aluOp_ID_out;
//wire ex_aluSrc_ID_out;
//wire ex_regDst_ID_out;
//wire m_mem_write_ID_out;
//wire m_branch_ID_out;
//wire m_branchNot_ID_out;
//wire m_jump_ID_out;
//wire [5:0] m_opcode_ID_out;
//wire wb_regWrite_ID_out;
//wire wb_memToReg_ID_out;
//Modulo EX
wire [31:0] pc_incrementado_EX_in;
wire [31:0] reg_data1_EX_in;
wire [31:0] reg_data2_EX_in;
wire [31:0] sign_extend_EX_in;
wire [4:0] rt_EX_in;
wire [4:0] rd_EX_in;
//wire aluSrc_EX_in;
//wire regDst_EX_in;
//wire [7:0] aluOp_EX_in;
//wire [31:0] add_result_EX_out;
//wire [31:0] alu_result_EX_out;
wire [31:0] reg_data2_EX_out;
wire [4:0] rt_or_rd_EX_out;
wire zero;
//Modulo MEM
wire [31:0] addres_MEM_in;
wire [31:0] write_data_MEM_in;
//wire mem_write_MEM_in;
//wire [5:0] opcode_MEM_in;
wire [31:0] read_data_MEM_out;
//Modulo WB
wire [31:0] mem_data_WB_in;
wire [31:0] alu_result_WB_in;
//wire memToReg_WB_in;
wire [31:0] write_data_WB_out;
//HZ
////Control
//output wire flushE_HZ_out;
//output wire stallD_HZ_out;
//wire stallF_HZ_out;
//output wire [1:0] ForwardAE_HZ_out;
//output wire [1:0] ForwardBE_HZ_out;
//Registros
wire [31:0] reg_0_out;
wire [31:0] reg_1_out;
wire [31:0] reg_2_out;
wire [31:0] reg_3_out;
wire [31:0] reg_4_out;
wire [31:0] reg_5_out;
wire [31:0] reg_6_out;
wire [31:0] reg_7_out;
wire [31:0] reg_8_out;
wire [31:0] reg_9_out;
wire [31:0] reg_10_out;
wire [31:0] reg_11_out;
wire [31:0] reg_12_out;
wire [31:0] reg_13_out;
wire [31:0] reg_14_out;
wire [31:0] reg_15_out;
wire [31:0] reg_16_out;
wire [31:0] reg_17_out;
wire [31:0] reg_18_out;
wire [31:0] reg_19_out;
wire [31:0] reg_20_out;
wire [31:0] reg_21_out;
wire [31:0] reg_22_out;
wire [31:0] reg_23_out;
wire [31:0] reg_24_out;
wire [31:0] reg_25_out;
wire [31:0] reg_26_out;
wire [31:0] reg_27_out;
wire [31:0] reg_28_out;
wire [31:0] reg_29_out;
wire [31:0] reg_30_out;
wire [31:0] reg_31_out;
wire clk50;
clk_divider clk50MHz
(
.CLK_IN1(clk),
.CLK_OUT1(clk50),
.RESET(reset),
.LOCKED()
);
debugger_unit db (
.clk(clk50),
.reset(reset),
.ena_pip(ena_pip),
.led(led),
.rx(rx),
.tx(tx),
//PC
.pc_incrementado_PC_out(pc_incrementado_PC_out),
//Modulo IF
////Input
.pc_PC_out(pc_PC_out),
////Output
.instruction_IF_out(instruction_IF),
//Modulo ID
////Input
.pc_incrementado_ID_in(pc_incrementado_ID_in),
.instruction_ID_in(instruction_ID_in),
.write_data_ID_in(write_data_ID_in),
.write_addr_ID_in(write_addr_ID_in),
.alu_result_EX_in(alu_result_EX_in),
//.reg_write_ID_in(reg_write_ID_in),
////Output
.reg_data1_ID_out(reg_data1_ID_out),
.reg_data2_ID_out(reg_data2_ID_out),
.sign_extend_ID_out(sign_extend_ID_out),
.inst_25_21_ID_out(inst_25_21_ID_out),
.inst_20_16_ID_out(inst_20_16_ID_out),
.inst_15_11_ID_out(inst_15_11_ID_out),
.pc_jump_ID_out(pc_jump_ID_out),
.pc_branch_ID_out(pc_branch_ID_out),
//.ex_aluOp_ID_out(ex_aluOp_ID_out),
//.ex_aluSrc_ID_out(ex_aluSrc_ID_out),
//.ex_regDst_ID_out(ex_regDst_ID_out),
//.m_mem_write_ID_out(m_mem_write_ID_out),
//.m_branch_ID_out(m_branch_ID_out),
//.m_branchNot_ID_out(m_branchNot_ID_out),
//.jump_ID_out(m_jump_ID_out),
//.m_opcode_ID_out(m_opcode_ID_out),
//.wb_regWrite_ID_out(wb_regWrite_ID_out),
//.wb_memToReg_ID_out(wb_memToReg_ID_out),
//Modulo EX
.pc_incrementado_EX_in(pc_incrementado_EX_in),
.reg_data1_EX_in(reg_data1_EX_in),
.reg_data2_EX_in(reg_data2_EX_in),
.sign_extend_EX_in(sign_extend_EX_in),
.rt_EX_in(rt_EX_in),
.rd_EX_in(rd_EX_in),
//.aluSrc_EX_in(aluSrc_EX_in),
//.regDst_EX_in(regDst_EX_in),
//.aluOp_EX_in(aluOp_EX_in),
//.add_result_EX_out(add_result_EX_out),
//.alu_result_EX_out(alu_result_EX_in),
.reg_data2_EX_out(reg_data2_EX_out),
.rt_or_rd_EX_out(rt_or_rd_EX_out),
.zero(1'b0),
//Modulo MEM
.addres_MEM_in(addres_MEM_in),
.write_data_MEM_in(write_data_MEM_in),
//.mem_write_MEM_in(mem_write_MEM_in),
//.opcode_MEM_in(opcode_MEM_in),
.read_data_MEM_out(read_data_MEM_out),
//WB
.mem_data_WB_in(mem_data_WB_in),
.alu_result_WB_in(alu_result_WB_in),
//.memToReg_WB_in(memToReg_WB_in),
.write_data_WB_out(write_data_ID_in),
//HZ
//.stallF_HZ_out(stallF_HZ_out),
//Registros
.reg_0_out(reg_0_out),
.reg_1_out(reg_1_out),
.reg_2_out(reg_2_out),
.reg_3_out(reg_3_out),
.reg_4_out(reg_4_out),
.reg_5_out(reg_5_out),
.reg_6_out(reg_6_out),
.reg_7_out(reg_7_out),
.reg_8_out(reg_8_out),
.reg_9_out(reg_9_out),
.reg_10_out(reg_10_out),
.reg_11_out(reg_11_out),
.reg_12_out(reg_12_out),
.reg_13_out(reg_13_out),
.reg_14_out(reg_14_out),
.reg_15_out(reg_15_out),
.reg_16_out(reg_16_out),
.reg_17_out(reg_17_out),
.reg_18_out(reg_18_out),
.reg_19_out(reg_19_out),
.reg_20_out(reg_20_out),
.reg_21_out(reg_21_out),
.reg_22_out(reg_22_out),
.reg_23_out(reg_23_out),
.reg_24_out(reg_24_out),
.reg_25_out(reg_25_out),
.reg_26_out(reg_26_out),
.reg_27_out(reg_27_out),
.reg_28_out(reg_28_out),
.reg_29_out(reg_29_out),
.reg_30_out(reg_30_out),
.reg_31_out(reg_31_out)
);
pipeline pip
(
.clk(clk50),
.reset(reset),
.ena(ena_pip),
.test_pc_incrementado_PC(pc_incrementado_PC_out),
//Modulo IF
.test_pc_PC(pc_PC_out),
.test_instruction_IF(instruction_IF),
//Modulo ID
////Input
.test_pc_incrementado_IF_ID(pc_incrementado_ID_in),
.test_instruction_IF_ID(instruction_ID_in),
.test_mux_wb_data_WB(write_data_ID_in),
.test_reg_dest_addr_MEM_WB(write_addr_ID_in),
.test_alu_result_EX(alu_result_EX_in),
//.reg_write_ID_in(reg_write_ID_in),
////Output
.test_data1_ID(reg_data1_ID_out),
.test_data2_ID(reg_data2_ID_out),
.test_sign_extend_ID(sign_extend_ID_out),
.test_instruction_25_21_ID(inst_25_21_ID_out),
.test_instruction_20_16_ID(inst_20_16_ID_out),
.test_instruction_15_11_ID(inst_15_11_ID_out),
.test_pc_jump_ID(pc_jump_ID_out),
.test_pc_Branch_ID(pc_branch_ID_out),
//Modulo EX
////Input
.test_pc_incrementado_ID_EX_out(pc_incrementado_EX_in),
.test_data1_ID_EX_out(reg_data1_EX_in),
.test_data2_ID_EX_out(reg_data2_EX_in),
.test_sign_extended_ID_EX_out(sign_extend_EX_in),
.test_inst_20_16_ID_EX_out(rt_EX_in),
.test_inst_15_11_ID_EX_out(rd_EX_in),
////Output
//.test_alu_result_EX(alu_result_EX_out),
.test_reg_data2_EX(reg_data2_EX_out),
.test_reg_dest_addr_EX(rt_or_rd_EX_out),
//Modulo MEM
////Input
.test_alu_result_EXMEM(addres_MEM_in),
.test_reg_data2_EXMEM(write_data_MEM_in),
////Output
.test_data_MEM(read_data_MEM_out),
//WB
.test_mem_data_MEM_WB(mem_data_WB_in),
.test_alu_result_MEM_WB(alu_result_WB_in),
//.test_mux_wb_data_WB(write_data_WB_out),
//HZ
//.test_stallF_HZ(stallF_HZ_out),
//Registros
.reg_0(reg_0_out),
.reg_1(reg_1_out),
.reg_2(reg_2_out),
.reg_3(reg_3_out),
.reg_4(reg_4_out),
.reg_5(reg_5_out),
.reg_6(reg_6_out),
.reg_7(reg_7_out),
.reg_8(reg_8_out),
.reg_9(reg_9_out),
.reg_10(reg_10_out),
.reg_11(reg_11_out),
.reg_12(reg_12_out),
.reg_13(reg_13_out),
.reg_14(reg_14_out),
.reg_15(reg_15_out),
.reg_16(reg_16_out),
.reg_17(reg_17_out),
.reg_18(reg_18_out),
.reg_19(reg_19_out),
.reg_20(reg_20_out),
.reg_21(reg_21_out),
.reg_22(reg_22_out),
.reg_23(reg_23_out),
.reg_24(reg_24_out),
.reg_25(reg_25_out),
.reg_26(reg_26_out),
.reg_27(reg_27_out),
.reg_28(reg_28_out),
.reg_29(reg_29_out),
.reg_30(reg_30_out),
.reg_31(reg_31_out)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:31:20 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/ball_pixel_1/ball_pixel_sim_netlist.v
// Design : ball_pixel
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "ball_pixel,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module ball_pixel
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [11:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [11:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "12" *)
(* C_ADDRB_WIDTH = "12" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.822999 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "ball_pixel.mem" *)
(* C_INIT_FILE_NAME = "ball_pixel.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "3600" *)
(* C_READ_DEPTH_B = "3600" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "3600" *)
(* C_WRITE_DEPTH_B = "3600" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
ball_pixel_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[11:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[11:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module ball_pixel_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
ball_pixel_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[3:0]),
.douta(douta[3:0]),
.wea(wea));
ball_pixel_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[11:4]),
.douta(douta[11:4]),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module ball_pixel_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [3:0]douta;
input clka;
input [11:0]addra;
input [3:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [3:0]dina;
wire [3:0]douta;
wire [0:0]wea;
ball_pixel_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module ball_pixel_blk_mem_gen_prim_width__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module ball_pixel_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [3:0]douta;
input clka;
input [11:0]addra;
input [3:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [3:0]dina;
wire [3:0]douta;
wire [0:0]wea;
wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000001950000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000042000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000045300000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000129B92000000000000000000000),
.INIT_06(256'h00000000000000000000000000000000000000007AAABB940000000000000000),
.INIT_07(256'h00000000000000000000000000000000000000000025ACB9ABB4000000000000),
.INIT_08(256'h00000000000000000000000000000000000000000000006BBA9A99A400000000),
.INIT_09(256'h40000000000000000000000000000000000000000000000007BBA9ABAAC50000),
.INIT_0A(256'hABAA91000000000000000000000000000000000000000000000359BBAA9ABBB8),
.INIT_0B(256'h9BBA9ABB810000000000000000000000000000000000000000000005BA9ABB99),
.INIT_0C(256'hBBA9ABA9AABB800000000000000000000000000000000000000000000004ABA9),
.INIT_0D(256'h029BB99ABA99BB9A920000000000000000000000000000000000000000000038),
.INIT_0E(256'h000049BB99ABA9ABB99BB9300000000000000000000000000000000000000000),
.INIT_0F(256'h000000147ABBA9ABAA9ABA9ABC50000000000000000000000000000000000000),
.INIT_10(256'h000000000019AA9ABA9ABB99ABA9AC5000000000000000000000000000000000),
.INIT_11(256'h0000000000000018BBA9ABA99BBA9ABA9A400000000000000000000000000000),
.INIT_12(256'h0000000000000000B209BA9AABA9ABA9AABAAB84000000000000000000000000),
.INIT_13(256'h00000000000000000000941AB99BB99ABA99BB99AAA810000000000000000000),
.INIT_14(256'h000000000000000000000000149A9ABB99ABA9ABB99BA2110000000000000000),
.INIT_15(256'h000000000000000000000000000005CAABBA9ABA9ABBA9AB9000000000000000),
.INIT_16(256'h0000000000000000000000000000000006CAABA9ABB99ABA9ABB810000000000),
.INIT_17(256'h00068888600000000000000000000000000005AA9ABA99BBA9ABA99A91000000),
.INIT_18(256'h0000003FFEEFF30000000000000000000000000005BAAABA9ABA9AABA9B84000),
.INIT_19(256'hABB4000007EF8119FE6000000000000000000000000006CAAB99ABA99BB99AC5),
.INIT_1A(256'hABA9AA52000009F866669F8000000000000000000000000005AAAA9ABA9ABB99),
.INIT_1B(256'hABB99ABAA810000009E07FF60E8000000000000000000000000005BAAA9ABAA9),
.INIT_1C(256'h9ABA99BBA9A9AB93000009E07FF60E8000000000000000000000000006CAABA9),
.INIT_1D(256'h05BAAABA9ABA999ABBB4000009F867768F8000000000000000000000000005AA),
.INIT_1E(256'h000006CAAB99ABA9A9ABBAA4000007EF8119FE60000000000000000000000000),
.INIT_1F(256'h0000000005AAAA9ABA9ABA9ABBA40000013FFEEFF30000000000000000000000),
.INIT_20(256'h00000000000005BAAA9ABAA9ABA9ABB840000007899870000000000000000000),
.INIT_21(256'h000000000000000006CAABA9ABB99ABA9ABB9100000000000000000000000000),
.INIT_22(256'h0000000000000000000005B99ABA9ABB99ABA9AA800000000000000000000000),
.INIT_23(256'h000000000000000000000000036AA9ABA9ABBA9ABA9AA5100000000000000000),
.INIT_24(256'h0000000000000000000000000000000AB99BBA9ABA99BBAABB51100000000000),
.INIT_25(256'h240000000000000000000000000000000018AABB99ABA9ABB999ABA893000000),
.INIT_26(256'hAA916A200000000000000000000000000000001AB9ABA9ABAA9ABA999ABBA730),
.INIT_27(256'hABB99BB8AB9400000000000000000000000000000019BA9ABA9ABB99ABA999BB),
.INIT_28(256'hAABA9AA9ABBAABB4000000000000000000000000000000017CA9ABA99BBA9ABA),
.INIT_29(256'hBA99BB99A99ABA9A99A4000000000000000000000000000000005B9AABA9ABA9),
.INIT_2A(256'h99ABA9ABB99ABAABA9ABAAC5000000000000000000000000000000005AABB99A),
.INIT_2B(256'h36ABA9ABAA9ABA9AA9ABAA9ABBB8400000000000000000000000000000005BBA),
.INIT_2C(256'h0000007BBA9ABB99ABA99A9ABB99ABAA91000000000000000000000000000000),
.INIT_2D(256'h000000000006BBA9ABB99ABA9BA99BBA9ABB8100000000000000000000000000),
.INIT_2E(256'h00000000000000026ABA9ABBA9ABBBA9ABA9AABB800000000000000000000000),
.INIT_2F(256'h0000000000000000000007BBA9ABA99BB99ABA99BB9A92000000000000000000),
.INIT_30(256'h000000000000000000000000006BABBA9ABB99ABA9ABB99BB930000000000000),
.INIT_31(256'h0000000000000000000000000000002558BBA9ABA9ABAA9ABA9ABC5000000000),
.INIT_32(256'h000000000000000000000000000000000000049BBA9ABA9ABB99ABA9AC500000),
.INIT_33(256'h9B840000000000000000000000000000000000000029CCA9ABA99BBA9ABA9A40),
.INIT_34(256'hBBA9ABB91000000000000000000000000000000000000004669BBBA9ABA9AABA),
.INIT_35(256'hAAACBAABCAB90000000000000000000000000000000000000000007AA99ABA9A),
.INIT_36(256'h04665456545565554200000000000000000000000000000000000000001129CC),
.INIT_37(256'h0000000000000000000079000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:4],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module ball_pixel_blk_mem_gen_prim_wrapper_init__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h00000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_01(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F001199550000000000),
.INIT_02(256'h60707070707070707070707000000000000000004F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_03(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000442200),
.INIT_04(256'h00000010F0F0F0F0F0F0F0F0F0F0F0E030101010101010104F4F4F4F4F4F4F4F),
.INIT_05(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00),
.INIT_06(256'h0000004070701010F0F0F0F0F0F0F0F0F0F0F0F0E0D0D0D0D0D0D060004F4F4F),
.INIT_07(256'h6000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00),
.INIT_08(256'h00000044553300205080503070C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0C0),
.INIT_09(256'hF0F0F0F0E030104F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_0A(256'h4F4F4F0000112299BB992200006090600070F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0B(256'hF0F0F0F0F0F0F0F0F0E0600000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_0C(256'h4F4F4F4F4F4F000077AAAAAABBBB9934006080600070F0F0F0F0F0F0F0F0F0F0),
.INIT_0D(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0C0707040004F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_0E(256'h4F4F4F4F4F4F4F4F4F002255AACCBB99AABBBB44006080600080F0F0F0F0F0F0),
.INIT_0F(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F08010004F4F4F4F4F4F4F4F),
.INIT_10(256'h4F4F4F4F4F4F4F4F4F4F4F4F000066BBBBAA99AA9999AA44006080600070E0F0),
.INIT_11(256'h703030E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E0C000004F4F4F),
.INIT_12(256'h40004F4F4F4F4F4F4F4F4F4F4F4F4F000077BBBBAA99AABBAAAACC4500708070),
.INIT_13(256'h44306080802000D0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F080),
.INIT_14(256'hF0F0F0F08010004F4F4F4F4F4F4F4F4F4F4F00335599BBBBAAAA99AABBBBBB78),
.INIT_15(256'hAABBAAAA99013080802010E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_16(256'hF0F0F0F0F0F0F0F0E0C000004F4F4F4F4F4F4F4F4F000055BBAA99AABBBB9999),
.INIT_17(256'h99BBBBAA99AABBBB88013080802010E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_18(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F08040004F4F4F4F4F4F4F00000044AABBAA99),
.INIT_19(256'hBBBBAA99AABBAA99AAAABBBB8800308080503070C0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_1A(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F080004F4F4F4F4F4F4F00003388),
.INIT_1B(256'h002299BBBB9999AABBAA9999BBBB99AA891230707080600070F0F0F0F0F0F0F0),
.INIT_1C(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F070004F4F4F4F4F4F4F),
.INIT_1D(256'h4F4F4F004499BBBB9999AABBAA99AABBBB9999BBBB9933107080600070F0F0F0),
.INIT_1E(256'h70F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F070004F4F4F),
.INIT_1F(256'h10004F4F4F00114477AABBBBAA99AABBAAAA99AABBAA99AABBCC450060806000),
.INIT_20(256'h6080600070E0E0E0E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F080),
.INIT_21(256'hF0F0F0E0C010004F4F001199AAAA99AABBAA99AABBBB9999AABBAA99AACC5500),
.INIT_22(256'h99AA3400708070704010101030F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_23(256'hF0F0F0F0F0F0F0F0E010004F4F001188BBBBAA99AABBAA9999BBBBAA99AABBAA),
.INIT_24(256'hAAAABBAAAABB884430508080300020303060C0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_25(256'hF0F0F0F0F0F0F0F0F0F0F0F0D010004FBB220099BBAA99AAAABBAA99AABBAA99),
.INIT_26(256'hBBAA9999BBBB9999AAAAAA780130808030107090700060E0F0F0F0F0F0F0F0F0),
.INIT_27(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0D010004F994411AABB9999BBBB9999AA),
.INIT_28(256'h9999AABBAA99AABBBB9999BBAA221101003080807070708070702020E0F0F0F0),
.INIT_29(256'hB09090F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0D000004F114499AA99AABBBB),
.INIT_2A(256'hAABBBBAA99AABBAA99AABBBBAA99AABBA9303030305080808080807080804030),
.INIT_2B(256'h70708080802000D0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E030004F0055CCAA),
.INIT_2C(256'h0066CCAAAABBAA99AABBBB9999AABBAA99AABBBB988180808080707060707070),
.INIT_2D(256'h0000607070708080802010E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E06000),
.INIT_2E(256'hF0F080000055AAAA99AABBAA9999BBBBAA99AABBAA9999AAA981708080806000),
.INIT_2F(256'h707070767888C8C8B6707080802010E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_30(256'hF0F0F0F0F0F070000055BBAAAAAABBAA99AABBAA99AAAABBAA99BB7854708070),
.INIT_31(256'h00608070707093FFFFEEEEFFFF937070803020C0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_32(256'hF0F0F0F0F0F0F0F0F0F070000066CCAAAABB9999AABBAA9999BBBB9999AACC45),
.INIT_33(256'hAABBBB440060807070B7FEFF88111199FFFE76107080601080F0F0F0F0F0F0F0),
.INIT_34(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F070000055AAAAAAAA99AABBAA99AABBBB9999),
.INIT_35(256'hAABBAA99AAAA55324070807070D9FF886666666689FF78006090700070F0F0F0),
.INIT_36(256'h70F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F070000055BBAAAAAA99AABBAAAA99),
.INIT_37(256'hAABBBB9999AABBAAAA8811307070807060C9EE0077FFFF6600EE880060806000),
.INIT_38(256'h7080600070F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F070000066CCAAAABBAA99),
.INIT_39(256'h99AABBAA9999BBBBAA99AA99AABB9943107080600099EE0077FFFF6600EEC860),
.INIT_3A(256'h88FFC8707080600070F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F070000055AAAA),
.INIT_3B(256'h0055BBAAAAAABBAA99AABBAA999999AABBBBBB44006080600089FF8866777766),
.INIT_3C(256'h88011199FFFEB6707080600070F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F07000),
.INIT_3D(256'hF0F070000066CCAAAABB9999AABBAA99AA99AABBBBAAAA44007080600077FEFF),
.INIT_3E(256'h607193FFFFEEEEFFFF9370707080600070F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_3F(256'hF0F0F0F0F0F080000055AAAAAAAA99AABBAA99AABBAA99AABBBBAA3400708070),
.INIT_40(256'h44306080807080B7C8C999887770707080504060B0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_41(256'hF0F0F0F0F0F0F0F0F0E070000055BBAAAAAA99AABBAAAA99AABBAA99AABBBB78),
.INIT_42(256'h99AABBBB89013080807070707060000000608080802010E0F0F0F0F0F0F0F0F0),
.INIT_43(256'hF0F0F0F0F0F0F0F0F0F0F0F0E03010000066CCAAAABBAA99AABBBB9999AABBAA),
.INIT_44(256'h9999AABBAA99AAAA88003080807070707070606060708080802010E0F0F0F0F0),
.INIT_45(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0D000004F0055BB9999AABBAA99AABBBB),
.INIT_46(256'hAA99AABBBBAA99AABBAA99AAAA553130708080708080808080805040300000D0),
.INIT_47(256'h101030E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0D010004F003366AAAA99AABB),
.INIT_48(256'hBB9999BBBBAA99AABBAA9999BBBBAAAABBBB4501717070707060707080803000),
.INIT_49(256'h80802010C0D0E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0D010004F4F0000AA),
.INIT_4A(256'h4F001188AAAABBBB9999AABBAA99AABBBB999999AABBAA88A943007040000040),
.INIT_4B(256'h4234003090802010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E010004F),
.INIT_4C(256'hC010004F4F0011AABB99AABBAA99AABBAAAA99AABBAA999999AABBBBAA673330),
.INIT_4D(256'hAAAA9911569A123070803020C0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_4E(256'hF0F0F08010004F4F4F001199BBAA99AABBAA99AABBBB9999AABBAA999999BBBB),
.INIT_4F(256'hAABBBB9999BBBB88AABB9944107080601080F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_50(256'hF0F0F0F0F0F0F070004F4F4F4F4F001177CCAA99AABBAA9999BBBBAA99AABBAA),
.INIT_51(256'hAAAABBAA99AAAA99AABBBBAAAABBBB44006090700070F0F0F0F0F0F0F0F0F0F0),
.INIT_52(256'hF0F0F0F0F0F0F0F0F0F0E070004F4F4F4F4F4F0055BB99AAAABBAA99AABBAA99),
.INIT_53(256'hBBAA9999BBBB9999AA9999AABBAA99AA9999AA44006080600070F0F0F0F0F0F0),
.INIT_54(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0E030104F4F4F4F4F4F000055AAAABBBB9999AA),
.INIT_55(256'h9999AABBAA99AABBBB9999AABBAAAABBAA99AABBAAAACC45007090600080F0F0),
.INIT_56(256'h405090F0F0F0F0F0F0F0F0F0F0F0F0F0F0E000004F4F4F4F4F4F000055BBBBAA),
.INIT_57(256'h3366AABBAA99AABBAAAA99AABBAA99AAAA99AABBAAAA99AABBBBBB7844306070),
.INIT_58(256'h99013080802000D0F0F0F0F0F0F0F0F0F0F0F0F0F0C010004F4F4F4F4F4F4F00),
.INIT_59(256'h4F4F4F4F000077BBBBAA99AABBBB9999AABBAA9999AA99AABBBB9999AABBAAAA),
.INIT_5A(256'h99AABBBB88013080802010E0F0F0F0F0F0F0F0F0F0F0F0F09010004F4F4F4F4F),
.INIT_5B(256'h4F4F4F4F4F4F4F4F4F000066BBBBAA99AABBBB9999AABBAA99BBAA9999BBBBAA),
.INIT_5C(256'hAABBAA99AAAABBBB88003080802010E0F0F0F0F0F0F0F0F0F0F0F09040004F4F),
.INIT_5D(256'h004F4F4F4F4F4F4F4F4F4F4F4F4F002266AABBAA99AABBBBAA99AABBBBBBAA99),
.INIT_5E(256'hBB9999AABBAA9999BBBB99AA89123070803020C0F0F0F0F0F0F0F0F0F0F0C000),
.INIT_5F(256'hF09010004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000077BBBBAA99AABBAA9999BB),
.INIT_60(256'h99AABBBB9999AABBAA99AABBBB9999BBBB9933107080601080F0F0F0F0F0F0F0),
.INIT_61(256'hF0F0F0F09040004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000066BBAABBBBAA),
.INIT_62(256'h5588BBBBAA99AABBAA99AABBAAAA99AABBAA99AABBCC45006090700070F0F0F0),
.INIT_63(256'h70F0F0F0F0F0F0C000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F002255),
.INIT_64(256'h4F4F0000004499BBBBAA99AABBAA99AABBBB9999AABBAA99AACC550060806000),
.INIT_65(256'h7090600070F0F0F0F0F09010004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_66(256'h4F4F4F4F4F4F4F0000002299CCCCAA99AABBAA9999BBBBAA99AABBAA99AA3400),
.INIT_67(256'h99BB78443060804060808080808040004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_68(256'h4F4F4F4F4F4F4F4F4F4F4F4F00000044666699BBBBBBAA99AABBAA99AAAABBAA),
.INIT_69(256'hBBBBAA99AABBCB8901207070300000000000004F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_6A(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00000077AAAA9999AABBAA99AA),
.INIT_6B(256'hAAAAAACCBBAAAABBCCAABB99000010100000000000004F4F4F4F4F4F4F4F4F4F),
.INIT_6C(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000011112299CCCC),
.INIT_6D(256'h004466665544556655445555665555554422000000004F4F4F4F4F4F4F4F4F4F),
.INIT_6E(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000),
.INIT_6F(256'h4F4F4F4F4F00000000000000000000000000000077994F4F4F4F4F4F4F4F4F4F),
.INIT_70(256'h000000000000000000000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module ball_pixel_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
ball_pixel_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "12" *) (* C_ADDRB_WIDTH = "12" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.822999 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "ball_pixel.mem" *)
(* C_INIT_FILE_NAME = "ball_pixel.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "3600" *) (* C_READ_DEPTH_B = "3600" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "3600" *) (* C_WRITE_DEPTH_B = "3600" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module ball_pixel_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [11:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [11:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [11:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [11:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
ball_pixel_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module ball_pixel_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
ball_pixel_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_BLACKBOX_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_BLACKBOX_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s18 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_1_V
`define SKY130_FD_SC_MS__DFXTP_1_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfxtp_1 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfxtp_1 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_1_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// readWriteSPIWireData.v ////
//// ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Wait for TX data bytes. When data is ready generate
//// SPI TX data, SPI CLK, and read SPI RX data
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "spiMaster_defines.v"
module readWriteSPIWireData (clk, clkDelay, rst, rxDataOut, rxDataRdySet, spiClkOut, spiDataIn, spiDataOut, txDataEmpty, txDataFull, txDataFullClr, txDataIn);
input clk;
input [7:0]clkDelay;
input rst;
input spiDataIn;
input txDataFull;
input [7:0]txDataIn;
output [7:0]rxDataOut;
output rxDataRdySet;
output spiClkOut;
output spiDataOut;
output txDataEmpty;
output txDataFullClr;
wire clk;
wire [7:0]clkDelay;
wire rst;
reg [7:0]rxDataOut, next_rxDataOut;
reg rxDataRdySet, next_rxDataRdySet;
reg spiClkOut, next_spiClkOut;
wire spiDataIn;
reg spiDataOut, next_spiDataOut;
reg txDataEmpty, next_txDataEmpty;
wire txDataFull;
reg txDataFullClr, next_txDataFullClr;
wire [7:0]txDataIn;
// diagram signals declarations
reg [3:0]bitCnt, next_bitCnt;
reg [7:0]clkDelayCnt, next_clkDelayCnt;
reg [7:0]rxDataShiftReg, next_rxDataShiftReg;
reg [7:0]txDataShiftReg, next_txDataShiftReg;
// BINARY ENCODED state machine: rwSPISt
// State codes definitions:
`define WT_TX_DATA 2'b00
`define CLK_HI 2'b01
`define CLK_LO 2'b10
`define ST_RW_WIRE 2'b11
reg [1:0]CurrState_rwSPISt, NextState_rwSPISt;
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
// Machine: rwSPISt
// NextState logic (combinatorial)
always @ (txDataFull or txDataIn or clkDelayCnt or clkDelay or txDataShiftReg or rxDataShiftReg or spiDataIn or bitCnt or rxDataRdySet or txDataEmpty or txDataFullClr or spiClkOut or spiDataOut or rxDataOut or CurrState_rwSPISt)
begin
NextState_rwSPISt <= CurrState_rwSPISt;
// Set default values for outputs and signals
next_rxDataRdySet <= rxDataRdySet;
next_txDataEmpty <= txDataEmpty;
next_txDataShiftReg <= txDataShiftReg;
next_rxDataShiftReg <= rxDataShiftReg;
next_bitCnt <= bitCnt;
next_clkDelayCnt <= clkDelayCnt;
next_txDataFullClr <= txDataFullClr;
next_spiClkOut <= spiClkOut;
next_spiDataOut <= spiDataOut;
next_rxDataOut <= rxDataOut;
case (CurrState_rwSPISt) // synopsys parallel_case full_case
`WT_TX_DATA:
begin
next_rxDataRdySet <= 1'b0;
next_txDataEmpty <= 1'b1;
if (txDataFull == 1'b1)
begin
NextState_rwSPISt <= `CLK_HI;
next_txDataShiftReg <= txDataIn;
next_rxDataShiftReg <= 8'h00;
next_bitCnt <= 4'h0;
next_clkDelayCnt <= 8'h00;
next_txDataFullClr <= 1'b1;
next_txDataEmpty <= 1'b0;
end
end
`CLK_HI:
begin
next_clkDelayCnt <= clkDelayCnt + 1'b1;
next_txDataFullClr <= 1'b0;
next_rxDataRdySet <= 1'b0;
if (clkDelayCnt == clkDelay)
begin
NextState_rwSPISt <= `CLK_LO;
next_spiClkOut <= 1'b0;
next_spiDataOut <= txDataShiftReg[7];
next_txDataShiftReg <= {txDataShiftReg[6:0], 1'b0};
next_rxDataShiftReg <= {rxDataShiftReg[6:0], spiDataIn};
next_clkDelayCnt <= 8'h00;
end
end
`CLK_LO:
begin
next_clkDelayCnt <= clkDelayCnt + 1'b1;
if ((bitCnt == 4'h8) && (txDataFull == 1'b1))
begin
NextState_rwSPISt <= `CLK_HI;
next_rxDataRdySet <= 1'b1;
next_rxDataOut <= rxDataShiftReg;
next_txDataShiftReg <= txDataIn;
next_bitCnt <= 3'b000;
next_clkDelayCnt <= 8'h00;
next_txDataFullClr <= 1'b1;
end
else if (bitCnt == 4'h8)
begin
NextState_rwSPISt <= `WT_TX_DATA;
next_rxDataRdySet <= 1'b1;
next_rxDataOut <= rxDataShiftReg;
end
else if (clkDelayCnt == clkDelay)
begin
NextState_rwSPISt <= `CLK_HI;
next_spiClkOut <= 1'b1;
next_bitCnt <= bitCnt + 1'b1;
next_clkDelayCnt <= 8'h00;
end
end
`ST_RW_WIRE:
begin
next_bitCnt <= 4'h0;
next_clkDelayCnt <= 8'h00;
next_txDataFullClr <= 1'b0;
next_rxDataRdySet <= 1'b0;
next_txDataShiftReg <= 8'h00;
next_rxDataShiftReg <= 8'h00;
next_rxDataOut <= 8'h00;
next_spiDataOut <= 1'b0;
next_spiClkOut <= 1'b0;
next_txDataEmpty <= 1'b0;
NextState_rwSPISt <= `WT_TX_DATA;
end
endcase
end
// Current State Logic (sequential)
always @ (posedge clk)
begin
if (rst == 1'b1)
CurrState_rwSPISt <= `ST_RW_WIRE;
else
CurrState_rwSPISt <= NextState_rwSPISt;
end
// Registered outputs logic
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
rxDataRdySet <= 1'b0;
txDataEmpty <= 1'b0;
txDataFullClr <= 1'b0;
spiClkOut <= 1'b0;
spiDataOut <= 1'b0;
rxDataOut <= 8'h00;
txDataShiftReg <= 8'h00;
rxDataShiftReg <= 8'h00;
bitCnt <= 4'h0;
clkDelayCnt <= 8'h00;
end
else
begin
rxDataRdySet <= next_rxDataRdySet;
txDataEmpty <= next_txDataEmpty;
txDataFullClr <= next_txDataFullClr;
spiClkOut <= next_spiClkOut;
spiDataOut <= next_spiDataOut;
rxDataOut <= next_rxDataOut;
txDataShiftReg <= next_txDataShiftReg;
rxDataShiftReg <= next_rxDataShiftReg;
bitCnt <= next_bitCnt;
clkDelayCnt <= next_clkDelayCnt;
end
end
endmodule |
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
(* whitebox *)
module CBLOCK (
I,
O,
CIN,
COUT
);
input wire [3:0] I;
(* carry="C" *)
input wire CIN;
(* DELAY_MATRIX_I="30e-12 30e-12 30e-12 30e-12" *)
(* DELAY_CONST_CIN="30e-12" *)
output wire O;
(* carry="C" *)
(* DELAY_MATRIX_I="30e-12 30e-12 30e-12 30e-12" *)
(* DELAY_CONST_CIN="30e-12" *)
output wire COUT;
wire [4:0] internal_sum;
assign internal_sum = I + CIN;
assign O = internal_sum[4];
assign COUT = internal_sum[3];
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file WR_FLASH_POST_FIFO.v when simulating
// the core, WR_FLASH_POST_FIFO. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module WR_FLASH_POST_FIFO(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
valid
);
input rst;
input wr_clk;
input rd_clk;
input [63 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
output valid;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(64),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(8),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(1),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(13),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(12),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(7),
.C_RD_DEPTH(128),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(7),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.VALID(valid),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/*
* Copyright 2015, Stephen A. Rodgers. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
/*
* SERIAL DATA FORMAT
*
* When an event occurs, a 21 byte ASCII serial data packet will be emitted.
* The format of this packet is as follows:
*
*
* :ssdddddddddddddddd\r\n
*
* The output is ASCII.
*
* ss - Status bits in ASCII hex
* dddddddddddddddd - Data bits in ASCII hex (count + data bit)
* most significant bits first
*
*
* Status:
* -------
*
* BIT
* 7 Error (OVERRUN) Flag
* 6-4 Reserved
* 3-0 Channel ID
*
* 1. The overrun error flag will be sent if the FIFO was overrun on a
* specific channel. The count and data bytes will be undefined.
*
* 2. The reserved bits are set to 0
*
* 3. The channel ID indicates the channel which posted the event.
*
*
* Count and data bytes
*
*
*
* Bits 63:1 Number of 10MHz clocks since reset
* Bit 0 New state of the data bit
*
* Upon reset, an initial event will be posted on all channels.
*/
`default_nettype none
`define ATTN_CHECK 3'b000
`define SEND_HEADER 3'b001
`define SEND_STATUS_HIGH 3'b010
`define SEND_STATUS_LOW 3'b011
`define SEND_WORD_HIGH 3'b100
`define SEND_WORD_LOW 3'b101
`define SEND_TRAILER 3'b110
`define SEND_TRAILER2 3'b111
// System state machine
// Combinatorial part
module sys_sm_comb(sys_sm_cur, channel_cur, channel_scan, byteaddr, channel_data, hexchar, attention_ch0,
attention_ch1, attention_ch2, attention_ch3, overrun_cur, overrun_ch0, overrun_ch1, overrun_ch2, overrun_ch3,
utxdone, clearoverrun_ch0, clearoverrun_ch1, clearoverrun_ch2, clearoverrun_ch3, txstart, nextbyte,
overrun_next, unload_ch0, unload_ch1, unload_ch2, unload_ch3, next_scan_channel, hexnybble,sys_sm_next, channel_next, txdata);
input [2:0] sys_sm_cur;
input [1:0] channel_cur;
input [1:0] channel_scan;
input [2:0] byteaddr;
input [7:0] channel_data;
input [7:0] hexchar;
input attention_ch0;
input attention_ch1;
input attention_ch2;
input attention_ch3;
input overrun_cur;
input overrun_ch0;
input overrun_ch1;
input overrun_ch2;
input overrun_ch3;
input utxdone;
output reg clearoverrun_ch0;
output reg clearoverrun_ch1;
output reg clearoverrun_ch2;
output reg clearoverrun_ch3;
output reg txstart;
output reg nextbyte;
output reg overrun_next;
output reg unload_ch0;
output reg unload_ch1;
output reg unload_ch2;
output reg unload_ch3;
output reg next_scan_channel;
output reg [3:0] hexnybble;
output reg [2:0] sys_sm_next;
output reg [1:0] channel_next;
output reg [7:0] txdata;
always @ (*) begin
// Defaults
clearoverrun_ch0 <= 0;
clearoverrun_ch1 <= 0;
clearoverrun_ch2 <= 0;
clearoverrun_ch3 <= 0;
unload_ch0 <= 0;
unload_ch1 <= 0;
unload_ch2 <= 0;
unload_ch3 <= 0;
channel_next <= channel_cur;
overrun_next <= overrun_cur;
txstart <= 0;
nextbyte <= 0;
next_scan_channel <= 0;
txdata <= 8'h3A;
hexnybble <= 0;
case(sys_sm_cur)
`ATTN_CHECK:
// Check channel attention bits
if((channel_scan == 0) && (attention_ch0)) begin
// Save overrun state for later
overrun_next <= overrun_ch0;
// Clear channel overrun
clearoverrun_ch0 <= 1;
// Next state
sys_sm_next <= `SEND_HEADER;
// Set the channel we are going to work with
channel_next <= 0; // Channel 0
// Send the header byte
txstart <= 1;
// Next scan channel
next_scan_channel <= 1;
end else if((channel_scan == 1) && (attention_ch1)) begin
// Save overrun state for later
overrun_next <= overrun_ch1;
// Clear channel overrun
clearoverrun_ch1 <= 1;
// Next state
sys_sm_next <= `SEND_HEADER;
// Set the channel we are going to work with
channel_next <= 1; // Channel 1
// Send the header byte
txstart <= 1;
// Next scan channel
next_scan_channel <= 1;
end else if((channel_scan == 2) && (attention_ch2)) begin
// Save overrun state for later
overrun_next <= overrun_ch2;
// Clear channel overrun
clearoverrun_ch2 <= 1;
// Next state
sys_sm_next <= `SEND_HEADER;
// Set the channel we are going to work with
channel_next <= 2; // Channel 2
// Send the header byte
txstart <= 1;
// Next scan channel
next_scan_channel <= 1;
end else if((channel_scan == 3) &&(attention_ch3)) begin
// Save overrun state for later
overrun_next <= overrun_ch3;
// Clear channel overrun
clearoverrun_ch3 <= 1;
// Next state
sys_sm_next <= `SEND_HEADER;
// Set the channel we are going to work with
channel_next <= 3; // Channel 3
// Send the header byte
txstart <= 1;
// Next scan channel
next_scan_channel <= 1;
end else begin
// Nothing to send
// Next scan channel
next_scan_channel <= 1;
sys_sm_next <= `ATTN_CHECK;
end
`SEND_HEADER:
if(~utxdone)
// Still busy
sys_sm_next <= `SEND_HEADER;
else begin
// Send the status byte
//txdata <= {overrun_cur, 3'b000, channel_cur};
// Convert high bits of status
hexnybble <= {overrun_cur, 3'b000};
txdata <= hexchar;
txstart <= 1;
sys_sm_next <= `SEND_STATUS_HIGH;
end
`SEND_STATUS_HIGH:
if(~utxdone)
// Still busy
sys_sm_next <= `SEND_STATUS_HIGH;
else begin
// Send the low nybble of the status byte
hexnybble <= channel_cur;
txdata <= hexchar;
txstart <= 1;
sys_sm_next <= `SEND_STATUS_LOW;
end
`SEND_STATUS_LOW:
if(~utxdone)
// Still busy
sys_sm_next <= `SEND_STATUS_LOW;
else begin
// Send the highest nybble in the long long word
hexnybble <= channel_data[7:4];
txdata <= hexchar;
txstart <= 1;
sys_sm_next <= `SEND_WORD_HIGH;
end
`SEND_WORD_HIGH:
if(~utxdone)
// Still busy
sys_sm_next <= `SEND_WORD_HIGH;
else begin
// Low nybble
hexnybble <= channel_data[3:0];
txdata <= hexchar;
nextbyte <= 1;
txstart <= 1;
sys_sm_next <= `SEND_WORD_LOW;
end
`SEND_WORD_LOW:
if(~utxdone)
// Still busy
sys_sm_next <= `SEND_WORD_LOW;
else begin
if(byteaddr == 0) begin
txdata <= 8'h0D; // CR
txstart <= 1;
if(channel_cur == 4'b0000)
unload_ch0 <= 1;
else if (channel_cur == 4'b0001)
unload_ch1 <= 1;
else if (channel_cur == 4'b0010)
unload_ch2 <= 1;
else if (channel_cur == 4'b0011)
unload_ch3 <= 1;
sys_sm_next <= `SEND_TRAILER;
end else begin
// Next high nybble
hexnybble <= channel_data[7:4];
txdata <= hexchar;
txstart <= 1;
sys_sm_next <= `SEND_WORD_HIGH;
end
end
`SEND_TRAILER:
if(~utxdone)
// Still busy
sys_sm_next <= `SEND_TRAILER;
else begin
txdata <= 8'h0A;
txstart <= 1;
sys_sm_next <= `SEND_TRAILER2;
end
`SEND_TRAILER2:
if(~utxdone)
// Still busy
sys_sm_next <= `SEND_TRAILER2;
else
sys_sm_next <= `ATTN_CHECK;
default:
begin
sys_sm_next <= 3'bxxx;
channel_next <= 2'bxx;
txdata <= 8'bxxxxxxxx;
clearoverrun_ch0 <= 1'bx;
clearoverrun_ch1 <= 1'bx;
clearoverrun_ch2 <= 1'bx;
clearoverrun_ch3 <= 1'bx;
unload_ch0 <= 1'bx;
unload_ch1 <= 1'bx;
unload_ch2 <= 1'bx;
unload_ch3 <= 1'bx;
txstart <= 1'bx;
nextbyte <= 1'bx;
overrun_next <= 1'bx;
end
endcase
end
endmodule
// Sequential part
module sys_sm_seq(clk, rstn, overrun_next, sys_sm_next, channel_next, overrun_cur, sys_sm_cur, channel_cur);
input clk;
input rstn;
input overrun_next;
input [2:0] sys_sm_next;
input [1:0] channel_next;
output reg overrun_cur;
output reg [2:0] sys_sm_cur;
output reg [1:0] channel_cur;
always @(posedge clk or negedge rstn) begin
if(rstn == 0) begin
channel_cur <= 0;
overrun_cur <= 0;
sys_sm_cur <= `ATTN_CHECK;
end else begin
overrun_cur <= overrun_next;
channel_cur <= channel_next;
sys_sm_cur <= sys_sm_next;
end
end
endmodule
// Channel multiplexer
module channel_mux(ch0, ch1, ch2, ch3, channel, dataout);
input [7:0] ch0;
input [7:0] ch1;
input [7:0] ch2;
input [7:0] ch3;
input [1:0] channel;
output reg [7:0] dataout;
always @(*) begin
case(channel)
0:
dataout <= ch0;
1:
dataout <= ch1;
2:
dataout <= ch2;
3:
dataout <= ch3;
default:
dataout <= 0;
endcase
end
endmodule
// Convert hex nybble to ascii digit
module nybbletohexdigit(nybble, digit);
input [3:0] nybble;
output reg [7:0] digit;
always @(*) begin
case(nybble)
0:
digit <= 8'h30;
1:
digit <= 8'h31;
2:
digit <= 8'h32;
3:
digit <= 8'h33;
4:
digit <= 8'h34;
5:
digit <= 8'h35;
6:
digit <= 8'h36;
7:
digit <= 8'h37;
8:
digit <= 8'h38;
9:
digit <= 8'h39;
10:
digit <= 8'h41;
11:
digit <= 8'h42;
12:
digit <= 8'h43;
13:
digit <= 8'h44;
14:
digit <= 8'h45;
15:
digit <= 8'h46;
default:
digit <= 8'bxxxxxxxx;
endcase
end
endmodule
/*
* This is the module just below the root which is the top level generic verilog code
* no device specific code is in this module, that is all done in the root module.
*/
module system(clk, rstn, datain_ch0, datain_ch1, datain_ch2, datain_ch3, serialout, testout0, testout1, testout2, testout3);
input clk; // Counter and fifo clock
input rstn; // Global reset, low true
input datain_ch0; // Channel 0 Data bit input
input datain_ch1; // Channel 1 Data bit input
input datain_ch2; // Channel 2 Data bit input
input datain_ch3; // Channel 3 Data bit input
output serialout; // Async serial data out
output testout0;
output testout1;
output testout2;
output testout3;
wire unload_ch0;
wire clearoverrun_ch0;
wire attention_ch0;
wire overrun_ch0;
wire unload_ch1;
wire clearoverrun_ch1;
wire attention_ch1;
wire overrun_ch1;
wire unload_ch2;
wire clearoverrun_ch2;
wire attention_ch2;
wire overrun_ch2;
wire unload_ch3;
wire clearoverrun_ch3;
wire attention_ch3;
wire overrun_ch3;
wire txdone;
wire nextbyte;
wire txstart;
wire overrun_cur;
wire overrun_next;
wire next_scan_channel;
wire [2:0] sys_sm_cur;
wire [2:0] sys_sm_next;
wire [2:0] byteaddr;
wire [1:0] channel_cur;
wire [1:0] channel_scan;
wire [1:0] channel_next;
wire [7:0] txdata;
wire [7:0] dataout_ch0;
wire [7:0] dataout_ch1;
wire [7:0] dataout_ch2;
wire [7:0] dataout_ch3;
wire [7:0] dataout;
wire [7:0] hexchar;
wire [3:0] hexnybble;
wire [62:0] count;
// Instantiate free running counter
counter ctr63(
.clk(clk),
.rstn(rstn),
.up(1'b1),
.down(1'b0),
.count(count)
);
defparam ctr63.WIDTH = 63;
// Scan counter
counter ctr2(
.clk(clk),
.rstn(rstn),
.up(next_scan_channel),
.down(1'b0),
.count(channel_scan)
);
defparam ctr2.WIDTH = 2;
// Instantiate channel 0
channel ch0(
.clk(clk),
.rstn(rstn),
.datain(datain_ch0),
.unload(unload_ch0),
.counterin(count),
.byteaddr(~byteaddr), // Complemented so high nybbles get sent first
.clearoverrun(clearoverrun_ch0),
.overrun(overrun_ch0),
.attention(attention_ch0),
.dataout(dataout_ch0),
.testouta(testout0),
.testoutb(testout2)
);
// Instantiate channel 1
channel ch1(
.clk(clk),
.rstn(rstn),
.datain(datain_ch1),
.unload(unload_ch1),
.counterin(count),
.byteaddr(~byteaddr), // Complemented so high nybbles get sent first
.clearoverrun(clearoverrun_ch1),
.overrun(overrun_ch1),
.attention(attention_ch1),
.dataout(dataout_ch1),
.testouta(testout1),
.testoutb(testout3)
);
// Instantiate channel 2
channel ch2(
.clk(clk),
.rstn(rstn),
.datain(datain_ch2),
.unload(unload_ch2),
.counterin(count),
.byteaddr(~byteaddr), // Complemented so high nybbles get sent first
.clearoverrun(clearoverrun_ch2),
.overrun(overrun_ch2),
.attention(attention_ch2),
.dataout(dataout_ch2)
);
// Instantiate channel 3
channel ch3(
.clk(clk),
.rstn(rstn),
.datain(datain_ch3),
.unload(unload_ch3),
.counterin(count),
.byteaddr(~byteaddr), // Complemented so high nybbles get sent first
.clearoverrun(clearoverrun_ch3),
.overrun(overrun_ch3),
.attention(attention_ch3),
.dataout(dataout_ch3)
);
// Instantiate channel multiplexer
channel_mux cmux0(
.ch0(dataout_ch0),
.ch1(dataout_ch1),
.ch2(dataout_ch2),
.ch3(dataout_ch3),
.channel(channel_cur),
.dataout(dataout)
);
// Instantiate byte counter
counter bc0(
.clk(clk),
.rstn(rstn),
.up(nextbyte),
.down(1'b0),
.count(byteaddr)
);
defparam bc0.WIDTH = 3;
// Instantiate nybble to ascii hex converter
nybbletohexdigit ntohd0(
.nybble(hexnybble),
.digit(hexchar)
);
// Instantiate combinatorial part of state machine
sys_sm_comb ssc0(
.sys_sm_cur(sys_sm_cur),
.channel_cur(channel_cur),
.channel_scan(channel_scan),
.byteaddr(byteaddr),
.channel_data(dataout),
.attention_ch0(attention_ch0),
.attention_ch1(attention_ch1),
.attention_ch2(attention_ch2),
.attention_ch3(attention_ch3),
.overrun_cur(overrun_cur),
.overrun_ch0(overrun_ch0),
.overrun_ch1(overrun_ch1),
.overrun_ch2(overrun_ch2),
.overrun_ch3(overrun_ch3),
.utxdone(txdone),
.hexchar(hexchar),
.clearoverrun_ch0(clearoverrun_ch0),
.clearoverrun_ch1(clearoverrun_ch1),
.clearoverrun_ch2(clearoverrun_ch2),
.clearoverrun_ch3(clearoverrun_ch3),
.txstart(txstart),
.nextbyte(nextbyte),
.overrun_next(overrun_next),
.unload_ch0(unload_ch0),
.unload_ch1(unload_ch1),
.unload_ch2(unload_ch2),
.unload_ch3(unload_ch3),
.next_scan_channel(next_scan_channel),
.sys_sm_next(sys_sm_next),
.channel_next(channel_next),
.txdata(txdata),
.hexnybble(hexnybble)
);
// Instantiate sequential part of state machine
sys_sm_seq sss0(
.clk(clk),
.rstn(rstn),
.overrun_next(overrun_next),
.sys_sm_next(sys_sm_next),
.channel_next(channel_next),
.overrun_cur(overrun_cur),
.sys_sm_cur(sys_sm_cur),
.channel_cur(channel_cur)
);
// Instantiate a UART Transmitter
utx utx0(
.clk(clk),
.rstn(rstn),
.load(txstart),
.inbyte(txdata),
.serialout(serialout),
.done(txdone)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A211O_BEHAVIORAL_PP_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211O_BEHAVIORAL_PP_V |
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_show_PLIC_state O 1 const
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// RDY_set_addr_map O 1 const
// axi4_slave_awready O 1 reg
// axi4_slave_wready O 1 reg
// axi4_slave_bvalid O 1 reg
// axi4_slave_bid O 4 reg
// axi4_slave_bresp O 2 reg
// axi4_slave_arready O 1 reg
// axi4_slave_rvalid O 1 reg
// axi4_slave_rid O 4 reg
// axi4_slave_rdata O 64 reg
// axi4_slave_rresp O 2 reg
// axi4_slave_rlast O 1 reg
// v_targets_0_m_eip O 1
// v_targets_1_m_eip O 1
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// set_addr_map_addr_base I 64 reg
// set_addr_map_addr_lim I 64 reg
// axi4_slave_awvalid I 1
// axi4_slave_awid I 4 reg
// axi4_slave_awaddr I 64 reg
// axi4_slave_awlen I 8 reg
// axi4_slave_awsize I 3 reg
// axi4_slave_awburst I 2 reg
// axi4_slave_awlock I 1 reg
// axi4_slave_awcache I 4 reg
// axi4_slave_awprot I 3 reg
// axi4_slave_awqos I 4 reg
// axi4_slave_awregion I 4 reg
// axi4_slave_wvalid I 1
// axi4_slave_wdata I 64 reg
// axi4_slave_wstrb I 8 reg
// axi4_slave_wlast I 1 reg
// axi4_slave_bready I 1
// axi4_slave_arvalid I 1
// axi4_slave_arid I 4 reg
// axi4_slave_araddr I 64 reg
// axi4_slave_arlen I 8 reg
// axi4_slave_arsize I 3 reg
// axi4_slave_arburst I 2 reg
// axi4_slave_arlock I 1 reg
// axi4_slave_arcache I 4 reg
// axi4_slave_arprot I 3 reg
// axi4_slave_arqos I 4 reg
// axi4_slave_arregion I 4 reg
// axi4_slave_rready I 1
// v_sources_0_m_interrupt_req_set_not_clear I 1
// v_sources_1_m_interrupt_req_set_not_clear I 1
// v_sources_2_m_interrupt_req_set_not_clear I 1
// v_sources_3_m_interrupt_req_set_not_clear I 1
// v_sources_4_m_interrupt_req_set_not_clear I 1
// v_sources_5_m_interrupt_req_set_not_clear I 1
// v_sources_6_m_interrupt_req_set_not_clear I 1
// v_sources_7_m_interrupt_req_set_not_clear I 1
// v_sources_8_m_interrupt_req_set_not_clear I 1
// v_sources_9_m_interrupt_req_set_not_clear I 1
// v_sources_10_m_interrupt_req_set_not_clear I 1
// v_sources_11_m_interrupt_req_set_not_clear I 1
// v_sources_12_m_interrupt_req_set_not_clear I 1
// v_sources_13_m_interrupt_req_set_not_clear I 1
// v_sources_14_m_interrupt_req_set_not_clear I 1
// v_sources_15_m_interrupt_req_set_not_clear I 1
// EN_set_verbosity I 1
// EN_show_PLIC_state I 1 unused
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_set_addr_map I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkPLIC_16_2_7(CLK,
RST_N,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
EN_show_PLIC_state,
RDY_show_PLIC_state,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
set_addr_map_addr_base,
set_addr_map_addr_lim,
EN_set_addr_map,
RDY_set_addr_map,
axi4_slave_awvalid,
axi4_slave_awid,
axi4_slave_awaddr,
axi4_slave_awlen,
axi4_slave_awsize,
axi4_slave_awburst,
axi4_slave_awlock,
axi4_slave_awcache,
axi4_slave_awprot,
axi4_slave_awqos,
axi4_slave_awregion,
axi4_slave_awready,
axi4_slave_wvalid,
axi4_slave_wdata,
axi4_slave_wstrb,
axi4_slave_wlast,
axi4_slave_wready,
axi4_slave_bvalid,
axi4_slave_bid,
axi4_slave_bresp,
axi4_slave_bready,
axi4_slave_arvalid,
axi4_slave_arid,
axi4_slave_araddr,
axi4_slave_arlen,
axi4_slave_arsize,
axi4_slave_arburst,
axi4_slave_arlock,
axi4_slave_arcache,
axi4_slave_arprot,
axi4_slave_arqos,
axi4_slave_arregion,
axi4_slave_arready,
axi4_slave_rvalid,
axi4_slave_rid,
axi4_slave_rdata,
axi4_slave_rresp,
axi4_slave_rlast,
axi4_slave_rready,
v_sources_0_m_interrupt_req_set_not_clear,
v_sources_1_m_interrupt_req_set_not_clear,
v_sources_2_m_interrupt_req_set_not_clear,
v_sources_3_m_interrupt_req_set_not_clear,
v_sources_4_m_interrupt_req_set_not_clear,
v_sources_5_m_interrupt_req_set_not_clear,
v_sources_6_m_interrupt_req_set_not_clear,
v_sources_7_m_interrupt_req_set_not_clear,
v_sources_8_m_interrupt_req_set_not_clear,
v_sources_9_m_interrupt_req_set_not_clear,
v_sources_10_m_interrupt_req_set_not_clear,
v_sources_11_m_interrupt_req_set_not_clear,
v_sources_12_m_interrupt_req_set_not_clear,
v_sources_13_m_interrupt_req_set_not_clear,
v_sources_14_m_interrupt_req_set_not_clear,
v_sources_15_m_interrupt_req_set_not_clear,
v_targets_0_m_eip,
v_targets_1_m_eip);
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method show_PLIC_state
input EN_show_PLIC_state;
output RDY_show_PLIC_state;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method set_addr_map
input [63 : 0] set_addr_map_addr_base;
input [63 : 0] set_addr_map_addr_lim;
input EN_set_addr_map;
output RDY_set_addr_map;
// action method axi4_slave_m_awvalid
input axi4_slave_awvalid;
input [3 : 0] axi4_slave_awid;
input [63 : 0] axi4_slave_awaddr;
input [7 : 0] axi4_slave_awlen;
input [2 : 0] axi4_slave_awsize;
input [1 : 0] axi4_slave_awburst;
input axi4_slave_awlock;
input [3 : 0] axi4_slave_awcache;
input [2 : 0] axi4_slave_awprot;
input [3 : 0] axi4_slave_awqos;
input [3 : 0] axi4_slave_awregion;
// value method axi4_slave_m_awready
output axi4_slave_awready;
// action method axi4_slave_m_wvalid
input axi4_slave_wvalid;
input [63 : 0] axi4_slave_wdata;
input [7 : 0] axi4_slave_wstrb;
input axi4_slave_wlast;
// value method axi4_slave_m_wready
output axi4_slave_wready;
// value method axi4_slave_m_bvalid
output axi4_slave_bvalid;
// value method axi4_slave_m_bid
output [3 : 0] axi4_slave_bid;
// value method axi4_slave_m_bresp
output [1 : 0] axi4_slave_bresp;
// value method axi4_slave_m_buser
// action method axi4_slave_m_bready
input axi4_slave_bready;
// action method axi4_slave_m_arvalid
input axi4_slave_arvalid;
input [3 : 0] axi4_slave_arid;
input [63 : 0] axi4_slave_araddr;
input [7 : 0] axi4_slave_arlen;
input [2 : 0] axi4_slave_arsize;
input [1 : 0] axi4_slave_arburst;
input axi4_slave_arlock;
input [3 : 0] axi4_slave_arcache;
input [2 : 0] axi4_slave_arprot;
input [3 : 0] axi4_slave_arqos;
input [3 : 0] axi4_slave_arregion;
// value method axi4_slave_m_arready
output axi4_slave_arready;
// value method axi4_slave_m_rvalid
output axi4_slave_rvalid;
// value method axi4_slave_m_rid
output [3 : 0] axi4_slave_rid;
// value method axi4_slave_m_rdata
output [63 : 0] axi4_slave_rdata;
// value method axi4_slave_m_rresp
output [1 : 0] axi4_slave_rresp;
// value method axi4_slave_m_rlast
output axi4_slave_rlast;
// value method axi4_slave_m_ruser
// action method axi4_slave_m_rready
input axi4_slave_rready;
// action method v_sources_0_m_interrupt_req
input v_sources_0_m_interrupt_req_set_not_clear;
// action method v_sources_1_m_interrupt_req
input v_sources_1_m_interrupt_req_set_not_clear;
// action method v_sources_2_m_interrupt_req
input v_sources_2_m_interrupt_req_set_not_clear;
// action method v_sources_3_m_interrupt_req
input v_sources_3_m_interrupt_req_set_not_clear;
// action method v_sources_4_m_interrupt_req
input v_sources_4_m_interrupt_req_set_not_clear;
// action method v_sources_5_m_interrupt_req
input v_sources_5_m_interrupt_req_set_not_clear;
// action method v_sources_6_m_interrupt_req
input v_sources_6_m_interrupt_req_set_not_clear;
// action method v_sources_7_m_interrupt_req
input v_sources_7_m_interrupt_req_set_not_clear;
// action method v_sources_8_m_interrupt_req
input v_sources_8_m_interrupt_req_set_not_clear;
// action method v_sources_9_m_interrupt_req
input v_sources_9_m_interrupt_req_set_not_clear;
// action method v_sources_10_m_interrupt_req
input v_sources_10_m_interrupt_req_set_not_clear;
// action method v_sources_11_m_interrupt_req
input v_sources_11_m_interrupt_req_set_not_clear;
// action method v_sources_12_m_interrupt_req
input v_sources_12_m_interrupt_req_set_not_clear;
// action method v_sources_13_m_interrupt_req
input v_sources_13_m_interrupt_req_set_not_clear;
// action method v_sources_14_m_interrupt_req
input v_sources_14_m_interrupt_req_set_not_clear;
// action method v_sources_15_m_interrupt_req
input v_sources_15_m_interrupt_req_set_not_clear;
// value method v_targets_0_m_eip
output v_targets_0_m_eip;
// value method v_targets_1_m_eip
output v_targets_1_m_eip;
// signals for module outputs
wire [63 : 0] axi4_slave_rdata;
wire [3 : 0] axi4_slave_bid, axi4_slave_rid;
wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp;
wire RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_addr_map,
RDY_set_verbosity,
RDY_show_PLIC_state,
axi4_slave_arready,
axi4_slave_awready,
axi4_slave_bvalid,
axi4_slave_rlast,
axi4_slave_rvalid,
axi4_slave_wready,
v_targets_0_m_eip,
v_targets_1_m_eip;
// register m_cfg_verbosity
reg [3 : 0] m_cfg_verbosity;
wire [3 : 0] m_cfg_verbosity$D_IN;
wire m_cfg_verbosity$EN;
// register m_rg_addr_base
reg [63 : 0] m_rg_addr_base;
wire [63 : 0] m_rg_addr_base$D_IN;
wire m_rg_addr_base$EN;
// register m_rg_addr_lim
reg [63 : 0] m_rg_addr_lim;
wire [63 : 0] m_rg_addr_lim$D_IN;
wire m_rg_addr_lim$EN;
// register m_vrg_source_busy_0
reg m_vrg_source_busy_0;
reg m_vrg_source_busy_0$D_IN;
wire m_vrg_source_busy_0$EN;
// register m_vrg_source_busy_1
reg m_vrg_source_busy_1;
reg m_vrg_source_busy_1$D_IN;
wire m_vrg_source_busy_1$EN;
// register m_vrg_source_busy_10
reg m_vrg_source_busy_10;
reg m_vrg_source_busy_10$D_IN;
wire m_vrg_source_busy_10$EN;
// register m_vrg_source_busy_11
reg m_vrg_source_busy_11;
reg m_vrg_source_busy_11$D_IN;
wire m_vrg_source_busy_11$EN;
// register m_vrg_source_busy_12
reg m_vrg_source_busy_12;
reg m_vrg_source_busy_12$D_IN;
wire m_vrg_source_busy_12$EN;
// register m_vrg_source_busy_13
reg m_vrg_source_busy_13;
reg m_vrg_source_busy_13$D_IN;
wire m_vrg_source_busy_13$EN;
// register m_vrg_source_busy_14
reg m_vrg_source_busy_14;
reg m_vrg_source_busy_14$D_IN;
wire m_vrg_source_busy_14$EN;
// register m_vrg_source_busy_15
reg m_vrg_source_busy_15;
reg m_vrg_source_busy_15$D_IN;
wire m_vrg_source_busy_15$EN;
// register m_vrg_source_busy_16
reg m_vrg_source_busy_16;
reg m_vrg_source_busy_16$D_IN;
wire m_vrg_source_busy_16$EN;
// register m_vrg_source_busy_2
reg m_vrg_source_busy_2;
reg m_vrg_source_busy_2$D_IN;
wire m_vrg_source_busy_2$EN;
// register m_vrg_source_busy_3
reg m_vrg_source_busy_3;
reg m_vrg_source_busy_3$D_IN;
wire m_vrg_source_busy_3$EN;
// register m_vrg_source_busy_4
reg m_vrg_source_busy_4;
reg m_vrg_source_busy_4$D_IN;
wire m_vrg_source_busy_4$EN;
// register m_vrg_source_busy_5
reg m_vrg_source_busy_5;
reg m_vrg_source_busy_5$D_IN;
wire m_vrg_source_busy_5$EN;
// register m_vrg_source_busy_6
reg m_vrg_source_busy_6;
reg m_vrg_source_busy_6$D_IN;
wire m_vrg_source_busy_6$EN;
// register m_vrg_source_busy_7
reg m_vrg_source_busy_7;
reg m_vrg_source_busy_7$D_IN;
wire m_vrg_source_busy_7$EN;
// register m_vrg_source_busy_8
reg m_vrg_source_busy_8;
reg m_vrg_source_busy_8$D_IN;
wire m_vrg_source_busy_8$EN;
// register m_vrg_source_busy_9
reg m_vrg_source_busy_9;
reg m_vrg_source_busy_9$D_IN;
wire m_vrg_source_busy_9$EN;
// register m_vrg_source_ip_0
reg m_vrg_source_ip_0;
wire m_vrg_source_ip_0$D_IN, m_vrg_source_ip_0$EN;
// register m_vrg_source_ip_1
reg m_vrg_source_ip_1;
wire m_vrg_source_ip_1$D_IN, m_vrg_source_ip_1$EN;
// register m_vrg_source_ip_10
reg m_vrg_source_ip_10;
wire m_vrg_source_ip_10$D_IN, m_vrg_source_ip_10$EN;
// register m_vrg_source_ip_11
reg m_vrg_source_ip_11;
wire m_vrg_source_ip_11$D_IN, m_vrg_source_ip_11$EN;
// register m_vrg_source_ip_12
reg m_vrg_source_ip_12;
wire m_vrg_source_ip_12$D_IN, m_vrg_source_ip_12$EN;
// register m_vrg_source_ip_13
reg m_vrg_source_ip_13;
wire m_vrg_source_ip_13$D_IN, m_vrg_source_ip_13$EN;
// register m_vrg_source_ip_14
reg m_vrg_source_ip_14;
wire m_vrg_source_ip_14$D_IN, m_vrg_source_ip_14$EN;
// register m_vrg_source_ip_15
reg m_vrg_source_ip_15;
wire m_vrg_source_ip_15$D_IN, m_vrg_source_ip_15$EN;
// register m_vrg_source_ip_16
reg m_vrg_source_ip_16;
wire m_vrg_source_ip_16$D_IN, m_vrg_source_ip_16$EN;
// register m_vrg_source_ip_2
reg m_vrg_source_ip_2;
wire m_vrg_source_ip_2$D_IN, m_vrg_source_ip_2$EN;
// register m_vrg_source_ip_3
reg m_vrg_source_ip_3;
wire m_vrg_source_ip_3$D_IN, m_vrg_source_ip_3$EN;
// register m_vrg_source_ip_4
reg m_vrg_source_ip_4;
wire m_vrg_source_ip_4$D_IN, m_vrg_source_ip_4$EN;
// register m_vrg_source_ip_5
reg m_vrg_source_ip_5;
wire m_vrg_source_ip_5$D_IN, m_vrg_source_ip_5$EN;
// register m_vrg_source_ip_6
reg m_vrg_source_ip_6;
wire m_vrg_source_ip_6$D_IN, m_vrg_source_ip_6$EN;
// register m_vrg_source_ip_7
reg m_vrg_source_ip_7;
wire m_vrg_source_ip_7$D_IN, m_vrg_source_ip_7$EN;
// register m_vrg_source_ip_8
reg m_vrg_source_ip_8;
wire m_vrg_source_ip_8$D_IN, m_vrg_source_ip_8$EN;
// register m_vrg_source_ip_9
reg m_vrg_source_ip_9;
wire m_vrg_source_ip_9$D_IN, m_vrg_source_ip_9$EN;
// register m_vrg_source_prio_0
reg [2 : 0] m_vrg_source_prio_0;
wire [2 : 0] m_vrg_source_prio_0$D_IN;
wire m_vrg_source_prio_0$EN;
// register m_vrg_source_prio_1
reg [2 : 0] m_vrg_source_prio_1;
wire [2 : 0] m_vrg_source_prio_1$D_IN;
wire m_vrg_source_prio_1$EN;
// register m_vrg_source_prio_10
reg [2 : 0] m_vrg_source_prio_10;
wire [2 : 0] m_vrg_source_prio_10$D_IN;
wire m_vrg_source_prio_10$EN;
// register m_vrg_source_prio_11
reg [2 : 0] m_vrg_source_prio_11;
wire [2 : 0] m_vrg_source_prio_11$D_IN;
wire m_vrg_source_prio_11$EN;
// register m_vrg_source_prio_12
reg [2 : 0] m_vrg_source_prio_12;
wire [2 : 0] m_vrg_source_prio_12$D_IN;
wire m_vrg_source_prio_12$EN;
// register m_vrg_source_prio_13
reg [2 : 0] m_vrg_source_prio_13;
wire [2 : 0] m_vrg_source_prio_13$D_IN;
wire m_vrg_source_prio_13$EN;
// register m_vrg_source_prio_14
reg [2 : 0] m_vrg_source_prio_14;
wire [2 : 0] m_vrg_source_prio_14$D_IN;
wire m_vrg_source_prio_14$EN;
// register m_vrg_source_prio_15
reg [2 : 0] m_vrg_source_prio_15;
wire [2 : 0] m_vrg_source_prio_15$D_IN;
wire m_vrg_source_prio_15$EN;
// register m_vrg_source_prio_16
reg [2 : 0] m_vrg_source_prio_16;
wire [2 : 0] m_vrg_source_prio_16$D_IN;
wire m_vrg_source_prio_16$EN;
// register m_vrg_source_prio_2
reg [2 : 0] m_vrg_source_prio_2;
wire [2 : 0] m_vrg_source_prio_2$D_IN;
wire m_vrg_source_prio_2$EN;
// register m_vrg_source_prio_3
reg [2 : 0] m_vrg_source_prio_3;
wire [2 : 0] m_vrg_source_prio_3$D_IN;
wire m_vrg_source_prio_3$EN;
// register m_vrg_source_prio_4
reg [2 : 0] m_vrg_source_prio_4;
wire [2 : 0] m_vrg_source_prio_4$D_IN;
wire m_vrg_source_prio_4$EN;
// register m_vrg_source_prio_5
reg [2 : 0] m_vrg_source_prio_5;
wire [2 : 0] m_vrg_source_prio_5$D_IN;
wire m_vrg_source_prio_5$EN;
// register m_vrg_source_prio_6
reg [2 : 0] m_vrg_source_prio_6;
wire [2 : 0] m_vrg_source_prio_6$D_IN;
wire m_vrg_source_prio_6$EN;
// register m_vrg_source_prio_7
reg [2 : 0] m_vrg_source_prio_7;
wire [2 : 0] m_vrg_source_prio_7$D_IN;
wire m_vrg_source_prio_7$EN;
// register m_vrg_source_prio_8
reg [2 : 0] m_vrg_source_prio_8;
wire [2 : 0] m_vrg_source_prio_8$D_IN;
wire m_vrg_source_prio_8$EN;
// register m_vrg_source_prio_9
reg [2 : 0] m_vrg_source_prio_9;
wire [2 : 0] m_vrg_source_prio_9$D_IN;
wire m_vrg_source_prio_9$EN;
// register m_vrg_target_threshold_0
reg [2 : 0] m_vrg_target_threshold_0;
wire [2 : 0] m_vrg_target_threshold_0$D_IN;
wire m_vrg_target_threshold_0$EN;
// register m_vrg_target_threshold_1
reg [2 : 0] m_vrg_target_threshold_1;
wire [2 : 0] m_vrg_target_threshold_1$D_IN;
wire m_vrg_target_threshold_1$EN;
// register m_vvrg_ie_0_0
reg m_vvrg_ie_0_0;
wire m_vvrg_ie_0_0$D_IN, m_vvrg_ie_0_0$EN;
// register m_vvrg_ie_0_1
reg m_vvrg_ie_0_1;
wire m_vvrg_ie_0_1$D_IN, m_vvrg_ie_0_1$EN;
// register m_vvrg_ie_0_10
reg m_vvrg_ie_0_10;
wire m_vvrg_ie_0_10$D_IN, m_vvrg_ie_0_10$EN;
// register m_vvrg_ie_0_11
reg m_vvrg_ie_0_11;
wire m_vvrg_ie_0_11$D_IN, m_vvrg_ie_0_11$EN;
// register m_vvrg_ie_0_12
reg m_vvrg_ie_0_12;
wire m_vvrg_ie_0_12$D_IN, m_vvrg_ie_0_12$EN;
// register m_vvrg_ie_0_13
reg m_vvrg_ie_0_13;
wire m_vvrg_ie_0_13$D_IN, m_vvrg_ie_0_13$EN;
// register m_vvrg_ie_0_14
reg m_vvrg_ie_0_14;
wire m_vvrg_ie_0_14$D_IN, m_vvrg_ie_0_14$EN;
// register m_vvrg_ie_0_15
reg m_vvrg_ie_0_15;
wire m_vvrg_ie_0_15$D_IN, m_vvrg_ie_0_15$EN;
// register m_vvrg_ie_0_16
reg m_vvrg_ie_0_16;
wire m_vvrg_ie_0_16$D_IN, m_vvrg_ie_0_16$EN;
// register m_vvrg_ie_0_2
reg m_vvrg_ie_0_2;
wire m_vvrg_ie_0_2$D_IN, m_vvrg_ie_0_2$EN;
// register m_vvrg_ie_0_3
reg m_vvrg_ie_0_3;
wire m_vvrg_ie_0_3$D_IN, m_vvrg_ie_0_3$EN;
// register m_vvrg_ie_0_4
reg m_vvrg_ie_0_4;
wire m_vvrg_ie_0_4$D_IN, m_vvrg_ie_0_4$EN;
// register m_vvrg_ie_0_5
reg m_vvrg_ie_0_5;
wire m_vvrg_ie_0_5$D_IN, m_vvrg_ie_0_5$EN;
// register m_vvrg_ie_0_6
reg m_vvrg_ie_0_6;
wire m_vvrg_ie_0_6$D_IN, m_vvrg_ie_0_6$EN;
// register m_vvrg_ie_0_7
reg m_vvrg_ie_0_7;
wire m_vvrg_ie_0_7$D_IN, m_vvrg_ie_0_7$EN;
// register m_vvrg_ie_0_8
reg m_vvrg_ie_0_8;
wire m_vvrg_ie_0_8$D_IN, m_vvrg_ie_0_8$EN;
// register m_vvrg_ie_0_9
reg m_vvrg_ie_0_9;
wire m_vvrg_ie_0_9$D_IN, m_vvrg_ie_0_9$EN;
// register m_vvrg_ie_1_0
reg m_vvrg_ie_1_0;
wire m_vvrg_ie_1_0$D_IN, m_vvrg_ie_1_0$EN;
// register m_vvrg_ie_1_1
reg m_vvrg_ie_1_1;
wire m_vvrg_ie_1_1$D_IN, m_vvrg_ie_1_1$EN;
// register m_vvrg_ie_1_10
reg m_vvrg_ie_1_10;
wire m_vvrg_ie_1_10$D_IN, m_vvrg_ie_1_10$EN;
// register m_vvrg_ie_1_11
reg m_vvrg_ie_1_11;
wire m_vvrg_ie_1_11$D_IN, m_vvrg_ie_1_11$EN;
// register m_vvrg_ie_1_12
reg m_vvrg_ie_1_12;
wire m_vvrg_ie_1_12$D_IN, m_vvrg_ie_1_12$EN;
// register m_vvrg_ie_1_13
reg m_vvrg_ie_1_13;
wire m_vvrg_ie_1_13$D_IN, m_vvrg_ie_1_13$EN;
// register m_vvrg_ie_1_14
reg m_vvrg_ie_1_14;
wire m_vvrg_ie_1_14$D_IN, m_vvrg_ie_1_14$EN;
// register m_vvrg_ie_1_15
reg m_vvrg_ie_1_15;
wire m_vvrg_ie_1_15$D_IN, m_vvrg_ie_1_15$EN;
// register m_vvrg_ie_1_16
reg m_vvrg_ie_1_16;
wire m_vvrg_ie_1_16$D_IN, m_vvrg_ie_1_16$EN;
// register m_vvrg_ie_1_2
reg m_vvrg_ie_1_2;
wire m_vvrg_ie_1_2$D_IN, m_vvrg_ie_1_2$EN;
// register m_vvrg_ie_1_3
reg m_vvrg_ie_1_3;
wire m_vvrg_ie_1_3$D_IN, m_vvrg_ie_1_3$EN;
// register m_vvrg_ie_1_4
reg m_vvrg_ie_1_4;
wire m_vvrg_ie_1_4$D_IN, m_vvrg_ie_1_4$EN;
// register m_vvrg_ie_1_5
reg m_vvrg_ie_1_5;
wire m_vvrg_ie_1_5$D_IN, m_vvrg_ie_1_5$EN;
// register m_vvrg_ie_1_6
reg m_vvrg_ie_1_6;
wire m_vvrg_ie_1_6$D_IN, m_vvrg_ie_1_6$EN;
// register m_vvrg_ie_1_7
reg m_vvrg_ie_1_7;
wire m_vvrg_ie_1_7$D_IN, m_vvrg_ie_1_7$EN;
// register m_vvrg_ie_1_8
reg m_vvrg_ie_1_8;
wire m_vvrg_ie_1_8$D_IN, m_vvrg_ie_1_8$EN;
// register m_vvrg_ie_1_9
reg m_vvrg_ie_1_9;
wire m_vvrg_ie_1_9$D_IN, m_vvrg_ie_1_9$EN;
// ports of submodule m_f_reset_reqs
wire m_f_reset_reqs$CLR,
m_f_reset_reqs$DEQ,
m_f_reset_reqs$EMPTY_N,
m_f_reset_reqs$ENQ,
m_f_reset_reqs$FULL_N;
// ports of submodule m_f_reset_rsps
wire m_f_reset_rsps$CLR,
m_f_reset_rsps$DEQ,
m_f_reset_rsps$EMPTY_N,
m_f_reset_rsps$ENQ,
m_f_reset_rsps$FULL_N;
// ports of submodule m_slave_xactor_f_rd_addr
wire [96 : 0] m_slave_xactor_f_rd_addr$D_IN, m_slave_xactor_f_rd_addr$D_OUT;
wire m_slave_xactor_f_rd_addr$CLR,
m_slave_xactor_f_rd_addr$DEQ,
m_slave_xactor_f_rd_addr$EMPTY_N,
m_slave_xactor_f_rd_addr$ENQ,
m_slave_xactor_f_rd_addr$FULL_N;
// ports of submodule m_slave_xactor_f_rd_data
wire [70 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT;
wire m_slave_xactor_f_rd_data$CLR,
m_slave_xactor_f_rd_data$DEQ,
m_slave_xactor_f_rd_data$EMPTY_N,
m_slave_xactor_f_rd_data$ENQ,
m_slave_xactor_f_rd_data$FULL_N;
// ports of submodule m_slave_xactor_f_wr_addr
wire [96 : 0] m_slave_xactor_f_wr_addr$D_IN, m_slave_xactor_f_wr_addr$D_OUT;
wire m_slave_xactor_f_wr_addr$CLR,
m_slave_xactor_f_wr_addr$DEQ,
m_slave_xactor_f_wr_addr$EMPTY_N,
m_slave_xactor_f_wr_addr$ENQ,
m_slave_xactor_f_wr_addr$FULL_N;
// ports of submodule m_slave_xactor_f_wr_data
wire [72 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT;
wire m_slave_xactor_f_wr_data$CLR,
m_slave_xactor_f_wr_data$DEQ,
m_slave_xactor_f_wr_data$EMPTY_N,
m_slave_xactor_f_wr_data$ENQ,
m_slave_xactor_f_wr_data$FULL_N;
// ports of submodule m_slave_xactor_f_wr_resp
wire [5 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT;
wire m_slave_xactor_f_wr_resp$CLR,
m_slave_xactor_f_wr_resp$DEQ,
m_slave_xactor_f_wr_resp$EMPTY_N,
m_slave_xactor_f_wr_resp$ENQ,
m_slave_xactor_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_m_rl_process_rd_req,
CAN_FIRE_RL_m_rl_process_wr_req,
CAN_FIRE_RL_m_rl_reset,
CAN_FIRE_axi4_slave_m_arvalid,
CAN_FIRE_axi4_slave_m_awvalid,
CAN_FIRE_axi4_slave_m_bready,
CAN_FIRE_axi4_slave_m_rready,
CAN_FIRE_axi4_slave_m_wvalid,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_addr_map,
CAN_FIRE_set_verbosity,
CAN_FIRE_show_PLIC_state,
CAN_FIRE_v_sources_0_m_interrupt_req,
CAN_FIRE_v_sources_10_m_interrupt_req,
CAN_FIRE_v_sources_11_m_interrupt_req,
CAN_FIRE_v_sources_12_m_interrupt_req,
CAN_FIRE_v_sources_13_m_interrupt_req,
CAN_FIRE_v_sources_14_m_interrupt_req,
CAN_FIRE_v_sources_15_m_interrupt_req,
CAN_FIRE_v_sources_1_m_interrupt_req,
CAN_FIRE_v_sources_2_m_interrupt_req,
CAN_FIRE_v_sources_3_m_interrupt_req,
CAN_FIRE_v_sources_4_m_interrupt_req,
CAN_FIRE_v_sources_5_m_interrupt_req,
CAN_FIRE_v_sources_6_m_interrupt_req,
CAN_FIRE_v_sources_7_m_interrupt_req,
CAN_FIRE_v_sources_8_m_interrupt_req,
CAN_FIRE_v_sources_9_m_interrupt_req,
WILL_FIRE_RL_m_rl_process_rd_req,
WILL_FIRE_RL_m_rl_process_wr_req,
WILL_FIRE_RL_m_rl_reset,
WILL_FIRE_axi4_slave_m_arvalid,
WILL_FIRE_axi4_slave_m_awvalid,
WILL_FIRE_axi4_slave_m_bready,
WILL_FIRE_axi4_slave_m_rready,
WILL_FIRE_axi4_slave_m_wvalid,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_addr_map,
WILL_FIRE_set_verbosity,
WILL_FIRE_show_PLIC_state,
WILL_FIRE_v_sources_0_m_interrupt_req,
WILL_FIRE_v_sources_10_m_interrupt_req,
WILL_FIRE_v_sources_11_m_interrupt_req,
WILL_FIRE_v_sources_12_m_interrupt_req,
WILL_FIRE_v_sources_13_m_interrupt_req,
WILL_FIRE_v_sources_14_m_interrupt_req,
WILL_FIRE_v_sources_15_m_interrupt_req,
WILL_FIRE_v_sources_1_m_interrupt_req,
WILL_FIRE_v_sources_2_m_interrupt_req,
WILL_FIRE_v_sources_3_m_interrupt_req,
WILL_FIRE_v_sources_4_m_interrupt_req,
WILL_FIRE_v_sources_5_m_interrupt_req,
WILL_FIRE_v_sources_6_m_interrupt_req,
WILL_FIRE_v_sources_7_m_interrupt_req,
WILL_FIRE_v_sources_8_m_interrupt_req,
WILL_FIRE_v_sources_9_m_interrupt_req;
// inputs to muxes for submodule ports
wire MUX_m_vrg_source_busy_0$write_1__SEL_1,
MUX_m_vrg_source_busy_0$write_1__SEL_2,
MUX_m_vrg_source_busy_1$write_1__SEL_1,
MUX_m_vrg_source_busy_1$write_1__SEL_2,
MUX_m_vrg_source_busy_10$write_1__SEL_1,
MUX_m_vrg_source_busy_10$write_1__SEL_2,
MUX_m_vrg_source_busy_11$write_1__SEL_1,
MUX_m_vrg_source_busy_11$write_1__SEL_2,
MUX_m_vrg_source_busy_12$write_1__SEL_1,
MUX_m_vrg_source_busy_12$write_1__SEL_2,
MUX_m_vrg_source_busy_13$write_1__SEL_1,
MUX_m_vrg_source_busy_13$write_1__SEL_2,
MUX_m_vrg_source_busy_14$write_1__SEL_1,
MUX_m_vrg_source_busy_14$write_1__SEL_2,
MUX_m_vrg_source_busy_15$write_1__SEL_1,
MUX_m_vrg_source_busy_15$write_1__SEL_2,
MUX_m_vrg_source_busy_16$write_1__SEL_1,
MUX_m_vrg_source_busy_16$write_1__SEL_2,
MUX_m_vrg_source_busy_2$write_1__SEL_1,
MUX_m_vrg_source_busy_2$write_1__SEL_2,
MUX_m_vrg_source_busy_3$write_1__SEL_1,
MUX_m_vrg_source_busy_3$write_1__SEL_2,
MUX_m_vrg_source_busy_4$write_1__SEL_1,
MUX_m_vrg_source_busy_4$write_1__SEL_2,
MUX_m_vrg_source_busy_5$write_1__SEL_1,
MUX_m_vrg_source_busy_5$write_1__SEL_2,
MUX_m_vrg_source_busy_6$write_1__SEL_1,
MUX_m_vrg_source_busy_6$write_1__SEL_2,
MUX_m_vrg_source_busy_7$write_1__SEL_1,
MUX_m_vrg_source_busy_7$write_1__SEL_2,
MUX_m_vrg_source_busy_8$write_1__SEL_1,
MUX_m_vrg_source_busy_8$write_1__SEL_2,
MUX_m_vrg_source_busy_9$write_1__SEL_1,
MUX_m_vrg_source_busy_9$write_1__SEL_2,
MUX_m_vrg_source_prio_0$write_1__SEL_1,
MUX_m_vrg_source_prio_1$write_1__SEL_1,
MUX_m_vrg_source_prio_10$write_1__SEL_1,
MUX_m_vrg_source_prio_11$write_1__SEL_1,
MUX_m_vrg_source_prio_12$write_1__SEL_1,
MUX_m_vrg_source_prio_13$write_1__SEL_1,
MUX_m_vrg_source_prio_14$write_1__SEL_1,
MUX_m_vrg_source_prio_15$write_1__SEL_1,
MUX_m_vrg_source_prio_16$write_1__SEL_1,
MUX_m_vrg_source_prio_2$write_1__SEL_1,
MUX_m_vrg_source_prio_3$write_1__SEL_1,
MUX_m_vrg_source_prio_4$write_1__SEL_1,
MUX_m_vrg_source_prio_5$write_1__SEL_1,
MUX_m_vrg_source_prio_6$write_1__SEL_1,
MUX_m_vrg_source_prio_7$write_1__SEL_1,
MUX_m_vrg_source_prio_8$write_1__SEL_1,
MUX_m_vrg_source_prio_9$write_1__SEL_1,
MUX_m_vrg_target_threshold_0$write_1__SEL_1,
MUX_m_vrg_target_threshold_1$write_1__SEL_1,
MUX_m_vvrg_ie_0_0$write_1__SEL_1,
MUX_m_vvrg_ie_0_0$write_1__VAL_1,
MUX_m_vvrg_ie_0_1$write_1__SEL_1,
MUX_m_vvrg_ie_0_1$write_1__VAL_1,
MUX_m_vvrg_ie_0_10$write_1__SEL_1,
MUX_m_vvrg_ie_0_10$write_1__VAL_1,
MUX_m_vvrg_ie_0_11$write_1__SEL_1,
MUX_m_vvrg_ie_0_11$write_1__VAL_1,
MUX_m_vvrg_ie_0_12$write_1__SEL_1,
MUX_m_vvrg_ie_0_12$write_1__VAL_1,
MUX_m_vvrg_ie_0_13$write_1__SEL_1,
MUX_m_vvrg_ie_0_13$write_1__VAL_1,
MUX_m_vvrg_ie_0_14$write_1__SEL_1,
MUX_m_vvrg_ie_0_14$write_1__VAL_1,
MUX_m_vvrg_ie_0_15$write_1__SEL_1,
MUX_m_vvrg_ie_0_15$write_1__VAL_1,
MUX_m_vvrg_ie_0_16$write_1__SEL_1,
MUX_m_vvrg_ie_0_16$write_1__VAL_1,
MUX_m_vvrg_ie_0_2$write_1__SEL_1,
MUX_m_vvrg_ie_0_2$write_1__VAL_1,
MUX_m_vvrg_ie_0_3$write_1__SEL_1,
MUX_m_vvrg_ie_0_3$write_1__VAL_1,
MUX_m_vvrg_ie_0_4$write_1__SEL_1,
MUX_m_vvrg_ie_0_4$write_1__VAL_1,
MUX_m_vvrg_ie_0_5$write_1__SEL_1,
MUX_m_vvrg_ie_0_5$write_1__VAL_1,
MUX_m_vvrg_ie_0_6$write_1__SEL_1,
MUX_m_vvrg_ie_0_6$write_1__VAL_1,
MUX_m_vvrg_ie_0_7$write_1__SEL_1,
MUX_m_vvrg_ie_0_7$write_1__VAL_1,
MUX_m_vvrg_ie_0_8$write_1__SEL_1,
MUX_m_vvrg_ie_0_8$write_1__VAL_1,
MUX_m_vvrg_ie_0_9$write_1__SEL_1,
MUX_m_vvrg_ie_0_9$write_1__VAL_1,
MUX_m_vvrg_ie_1_0$write_1__SEL_1,
MUX_m_vvrg_ie_1_0$write_1__VAL_1,
MUX_m_vvrg_ie_1_1$write_1__SEL_1,
MUX_m_vvrg_ie_1_1$write_1__VAL_1,
MUX_m_vvrg_ie_1_10$write_1__SEL_1,
MUX_m_vvrg_ie_1_10$write_1__VAL_1,
MUX_m_vvrg_ie_1_11$write_1__SEL_1,
MUX_m_vvrg_ie_1_11$write_1__VAL_1,
MUX_m_vvrg_ie_1_12$write_1__SEL_1,
MUX_m_vvrg_ie_1_12$write_1__VAL_1,
MUX_m_vvrg_ie_1_13$write_1__SEL_1,
MUX_m_vvrg_ie_1_13$write_1__VAL_1,
MUX_m_vvrg_ie_1_14$write_1__SEL_1,
MUX_m_vvrg_ie_1_14$write_1__VAL_1,
MUX_m_vvrg_ie_1_15$write_1__SEL_1,
MUX_m_vvrg_ie_1_15$write_1__VAL_1,
MUX_m_vvrg_ie_1_16$write_1__SEL_1,
MUX_m_vvrg_ie_1_16$write_1__VAL_1,
MUX_m_vvrg_ie_1_2$write_1__SEL_1,
MUX_m_vvrg_ie_1_2$write_1__VAL_1,
MUX_m_vvrg_ie_1_3$write_1__SEL_1,
MUX_m_vvrg_ie_1_3$write_1__VAL_1,
MUX_m_vvrg_ie_1_4$write_1__SEL_1,
MUX_m_vvrg_ie_1_4$write_1__VAL_1,
MUX_m_vvrg_ie_1_5$write_1__SEL_1,
MUX_m_vvrg_ie_1_5$write_1__VAL_1,
MUX_m_vvrg_ie_1_6$write_1__SEL_1,
MUX_m_vvrg_ie_1_6$write_1__VAL_1,
MUX_m_vvrg_ie_1_7$write_1__SEL_1,
MUX_m_vvrg_ie_1_7$write_1__VAL_1,
MUX_m_vvrg_ie_1_8$write_1__SEL_1,
MUX_m_vvrg_ie_1_8$write_1__VAL_1,
MUX_m_vvrg_ie_1_9$write_1__SEL_1,
MUX_m_vvrg_ie_1_9$write_1__VAL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h86248;
reg [31 : 0] v__h86443;
reg [31 : 0] v__h86638;
reg [31 : 0] v__h86833;
reg [31 : 0] v__h87028;
reg [31 : 0] v__h87223;
reg [31 : 0] v__h87418;
reg [31 : 0] v__h87613;
reg [31 : 0] v__h87808;
reg [31 : 0] v__h88003;
reg [31 : 0] v__h88198;
reg [31 : 0] v__h88393;
reg [31 : 0] v__h88588;
reg [31 : 0] v__h88783;
reg [31 : 0] v__h88978;
reg [31 : 0] v__h89173;
reg [31 : 0] v__h5962;
reg [31 : 0] v__h13331;
reg [31 : 0] v__h13514;
reg [31 : 0] v__h13730;
reg [31 : 0] v__h13976;
reg [31 : 0] v__h18445;
reg [31 : 0] v__h24057;
reg [31 : 0] v__h26355;
reg [31 : 0] v__h26568;
reg [31 : 0] v__h26773;
reg [31 : 0] v__h27053;
reg [31 : 0] v__h27284;
reg [31 : 0] v__h28359;
reg [31 : 0] v__h28531;
reg [31 : 0] v__h76647;
reg [31 : 0] v__h76947;
reg [31 : 0] v__h77579;
reg [31 : 0] v__h77673;
reg [31 : 0] v__h77844;
reg [31 : 0] v__h78064;
reg [31 : 0] v__h85245;
reg [31 : 0] v__h85351;
reg [31 : 0] v__h85478;
reg [31 : 0] v__h5956;
reg [31 : 0] v__h13325;
reg [31 : 0] v__h13508;
reg [31 : 0] v__h13724;
reg [31 : 0] v__h13970;
reg [31 : 0] v__h18439;
reg [31 : 0] v__h24051;
reg [31 : 0] v__h26349;
reg [31 : 0] v__h26562;
reg [31 : 0] v__h26767;
reg [31 : 0] v__h27047;
reg [31 : 0] v__h27278;
reg [31 : 0] v__h28353;
reg [31 : 0] v__h28525;
reg [31 : 0] v__h76641;
reg [31 : 0] v__h76941;
reg [31 : 0] v__h77573;
reg [31 : 0] v__h77667;
reg [31 : 0] v__h77838;
reg [31 : 0] v__h78058;
reg [31 : 0] v__h85239;
reg [31 : 0] v__h85345;
reg [31 : 0] v__h85472;
reg [31 : 0] v__h86242;
reg [31 : 0] v__h86437;
reg [31 : 0] v__h86632;
reg [31 : 0] v__h86827;
reg [31 : 0] v__h87022;
reg [31 : 0] v__h87217;
reg [31 : 0] v__h87412;
reg [31 : 0] v__h87607;
reg [31 : 0] v__h87802;
reg [31 : 0] v__h87997;
reg [31 : 0] v__h88192;
reg [31 : 0] v__h88387;
reg [31 : 0] v__h88582;
reg [31 : 0] v__h88777;
reg [31 : 0] v__h88972;
reg [31 : 0] v__h89167;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] y_avValue_fst__h26466;
reg [2 : 0] x__h13769, x__h24096;
reg [1 : 0] v__h76713, y_avValue_snd__h26467;
reg CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48,
SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520;
wire [63 : 0] addr_offset__h13465,
addr_offset__h27245,
rdata___1__h26714,
rdata__h26520,
v__h13689,
v__h13934,
v__h18403,
v__h24016,
v__h24251,
v__h25556,
x__h26677,
y_avValue_fst__h26433,
y_avValue_fst__h26445,
y_avValue_fst__h26461,
y_avValue_fst__h26477,
y_avValue_fst__h26482,
y_avValue_fst__h26493,
y_avValue_fst__h26498,
y_avValue_fst__h26512;
wire [31 : 0] v_ie__h18406,
v_ip__h13937,
wdata32__h27246,
x__h23928,
x__h76716;
wire [9 : 0] source_id__h15937,
source_id__h16044,
source_id__h16117,
source_id__h16190,
source_id__h16263,
source_id__h16336,
source_id__h16409,
source_id__h16482,
source_id__h16555,
source_id__h16628,
source_id__h16701,
source_id__h16774,
source_id__h16847,
source_id__h16920,
source_id__h16993,
source_id__h17066,
source_id__h17139,
source_id__h17212,
source_id__h17285,
source_id__h17358,
source_id__h17431,
source_id__h17504,
source_id__h17577,
source_id__h17650,
source_id__h17723,
source_id__h17796,
source_id__h17869,
source_id__h17942,
source_id__h18015,
source_id__h18088,
source_id__h18161,
source_id__h20405,
source_id__h20581,
source_id__h20689,
source_id__h20797,
source_id__h20905,
source_id__h21013,
source_id__h21121,
source_id__h21229,
source_id__h21337,
source_id__h21445,
source_id__h21553,
source_id__h21661,
source_id__h21769,
source_id__h21877,
source_id__h21985,
source_id__h22093,
source_id__h22201,
source_id__h22309,
source_id__h22417,
source_id__h22525,
source_id__h22633,
source_id__h22741,
source_id__h22849,
source_id__h22957,
source_id__h23065,
source_id__h23173,
source_id__h23281,
source_id__h23389,
source_id__h23497,
source_id__h23605,
source_id__h23713,
source_id__h30233,
source_id__h31729,
source_id__h33225,
source_id__h34721,
source_id__h36217,
source_id__h37713,
source_id__h39209,
source_id__h40705,
source_id__h42201,
source_id__h43697,
source_id__h45193,
source_id__h46689,
source_id__h48185,
source_id__h49681,
source_id__h51177,
source_id__h52673,
source_id__h54169,
source_id__h55665,
source_id__h57161,
source_id__h58657,
source_id__h60153,
source_id__h61649,
source_id__h63145,
source_id__h64641,
source_id__h66137,
source_id__h67633,
source_id__h69129,
source_id__h70625,
source_id__h72121,
source_id__h73617,
source_id__h75113,
source_id_base__h13893,
source_id_base__h28620;
wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3078,
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3172,
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3080,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3174,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669,
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3082,
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3176,
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3070,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3164,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3072,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3166,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3074,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3168,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3076,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3170,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665,
b__h81741,
b__h83895,
max_id__h24210;
wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3037,
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3131,
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615,
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3042,
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3136,
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622,
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3047,
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3141,
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3052,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3146,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636,
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3057,
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3151,
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643,
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3062,
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3156,
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d2992,
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3086,
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552,
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d2997,
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3091,
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3002,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3096,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566,
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3007,
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3101,
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3012,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3106,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580,
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3017,
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3111,
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3022,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3116,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594,
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3027,
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3121,
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3032,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3126,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608,
a__h81740,
a__h83894;
wire [1 : 0] rresp__h26521,
v__h27250,
v__h27435,
v__h27448,
v__h28425,
v__h28444,
v__h28597,
v__h28616,
v__h76750,
y_avValue_snd__h26446,
y_avValue_snd__h26462,
y_avValue_snd__h26478,
y_avValue_snd__h26483,
y_avValue_snd__h26494,
y_avValue_snd__h26499,
y_avValue_snd__h26513;
wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d748,
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750,
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2874,
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2950,
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952,
NOT_m_cfg_verbosity_read_ULE_1_5___d16,
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248,
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538,
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695,
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d733,
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2844,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2857,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2868,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2923,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2935,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d826,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d880,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d892,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956,
NOT_m_vrg_source_busy_10_983_284_AND_NOT_m_cfg_ETC___d3288,
NOT_m_vrg_source_busy_11_984_292_AND_NOT_m_cfg_ETC___d3296,
NOT_m_vrg_source_busy_12_985_300_AND_NOT_m_cfg_ETC___d3304,
NOT_m_vrg_source_busy_13_986_308_AND_NOT_m_cfg_ETC___d3312,
NOT_m_vrg_source_busy_14_987_316_AND_NOT_m_cfg_ETC___d3320,
NOT_m_vrg_source_busy_15_988_324_AND_NOT_m_cfg_ETC___d3328,
NOT_m_vrg_source_busy_16_989_332_AND_NOT_m_cfg_ETC___d3336,
NOT_m_vrg_source_busy_1_974_213_AND_NOT_m_cfg__ETC___d3217,
NOT_m_vrg_source_busy_2_975_220_AND_NOT_m_cfg__ETC___d3224,
NOT_m_vrg_source_busy_3_976_228_AND_NOT_m_cfg__ETC___d3232,
NOT_m_vrg_source_busy_4_977_236_AND_NOT_m_cfg__ETC___d3240,
NOT_m_vrg_source_busy_5_978_244_AND_NOT_m_cfg__ETC___d3248,
NOT_m_vrg_source_busy_6_979_252_AND_NOT_m_cfg__ETC___d3256,
NOT_m_vrg_source_busy_7_980_260_AND_NOT_m_cfg__ETC___d3264,
NOT_m_vrg_source_busy_8_981_268_AND_NOT_m_cfg__ETC___d3272,
NOT_m_vrg_source_busy_9_982_276_AND_NOT_m_cfg__ETC___d3280,
_dfoo1,
_dfoo10,
_dfoo100,
_dfoo1000,
_dfoo1001,
_dfoo1002,
_dfoo1003,
_dfoo1004,
_dfoo1005,
_dfoo1006,
_dfoo1007,
_dfoo1008,
_dfoo1009,
_dfoo1010,
_dfoo1011,
_dfoo1012,
_dfoo1013,
_dfoo1014,
_dfoo1015,
_dfoo1016,
_dfoo1017,
_dfoo1018,
_dfoo1019,
_dfoo102,
_dfoo1020,
_dfoo1022,
_dfoo1024,
_dfoo1026,
_dfoo1028,
_dfoo1030,
_dfoo1032,
_dfoo1034,
_dfoo1036,
_dfoo1038,
_dfoo104,
_dfoo1040,
_dfoo1042,
_dfoo1044,
_dfoo1046,
_dfoo1048,
_dfoo1050,
_dfoo1052,
_dfoo1054,
_dfoo1056,
_dfoo1058,
_dfoo106,
_dfoo1060,
_dfoo1062,
_dfoo1064,
_dfoo1066,
_dfoo1068,
_dfoo1070,
_dfoo1072,
_dfoo1074,
_dfoo1076,
_dfoo1078,
_dfoo108,
_dfoo1080,
_dfoo1082,
_dfoo1084,
_dfoo1086,
_dfoo1088,
_dfoo1089,
_dfoo1090,
_dfoo1091,
_dfoo1092,
_dfoo1093,
_dfoo1094,
_dfoo1095,
_dfoo1096,
_dfoo1097,
_dfoo1098,
_dfoo1099,
_dfoo11,
_dfoo110,
_dfoo1100,
_dfoo1101,
_dfoo1102,
_dfoo1103,
_dfoo1104,
_dfoo1105,
_dfoo1106,
_dfoo1107,
_dfoo1108,
_dfoo1109,
_dfoo1110,
_dfoo1111,
_dfoo1112,
_dfoo1113,
_dfoo1114,
_dfoo1115,
_dfoo1116,
_dfoo1117,
_dfoo1118,
_dfoo1119,
_dfoo112,
_dfoo1120,
_dfoo1121,
_dfoo1122,
_dfoo1123,
_dfoo1124,
_dfoo1125,
_dfoo1126,
_dfoo1127,
_dfoo1128,
_dfoo1129,
_dfoo1130,
_dfoo1131,
_dfoo1132,
_dfoo1133,
_dfoo1134,
_dfoo1135,
_dfoo1136,
_dfoo1137,
_dfoo1138,
_dfoo1139,
_dfoo114,
_dfoo1140,
_dfoo1141,
_dfoo1142,
_dfoo1143,
_dfoo1144,
_dfoo1145,
_dfoo1146,
_dfoo1147,
_dfoo1148,
_dfoo1149,
_dfoo1150,
_dfoo1151,
_dfoo1152,
_dfoo1153,
_dfoo1154,
_dfoo1155,
_dfoo1156,
_dfoo1158,
_dfoo116,
_dfoo1160,
_dfoo1162,
_dfoo1164,
_dfoo1166,
_dfoo1168,
_dfoo1170,
_dfoo1172,
_dfoo1174,
_dfoo1176,
_dfoo1178,
_dfoo118,
_dfoo1180,
_dfoo1182,
_dfoo1184,
_dfoo1186,
_dfoo1188,
_dfoo1190,
_dfoo1192,
_dfoo1194,
_dfoo1196,
_dfoo1198,
_dfoo12,
_dfoo120,
_dfoo1200,
_dfoo1202,
_dfoo1204,
_dfoo1206,
_dfoo1208,
_dfoo1210,
_dfoo1212,
_dfoo1214,
_dfoo1216,
_dfoo1218,
_dfoo122,
_dfoo1220,
_dfoo1222,
_dfoo1224,
_dfoo1225,
_dfoo1226,
_dfoo1227,
_dfoo1228,
_dfoo1229,
_dfoo1230,
_dfoo1231,
_dfoo1232,
_dfoo1233,
_dfoo1234,
_dfoo1235,
_dfoo1236,
_dfoo1237,
_dfoo1238,
_dfoo1239,
_dfoo124,
_dfoo1240,
_dfoo1241,
_dfoo1242,
_dfoo1243,
_dfoo1244,
_dfoo1245,
_dfoo1246,
_dfoo1247,
_dfoo1248,
_dfoo1249,
_dfoo1250,
_dfoo1251,
_dfoo1252,
_dfoo1253,
_dfoo1254,
_dfoo1255,
_dfoo1256,
_dfoo1257,
_dfoo1258,
_dfoo1259,
_dfoo126,
_dfoo1260,
_dfoo1261,
_dfoo1262,
_dfoo1263,
_dfoo1264,
_dfoo1265,
_dfoo1266,
_dfoo1267,
_dfoo1268,
_dfoo1269,
_dfoo1270,
_dfoo1271,
_dfoo1272,
_dfoo1273,
_dfoo1274,
_dfoo1275,
_dfoo1276,
_dfoo1277,
_dfoo1278,
_dfoo1279,
_dfoo128,
_dfoo1280,
_dfoo1281,
_dfoo1282,
_dfoo1283,
_dfoo1284,
_dfoo1285,
_dfoo1286,
_dfoo1287,
_dfoo1288,
_dfoo1289,
_dfoo1290,
_dfoo1291,
_dfoo1292,
_dfoo1294,
_dfoo1296,
_dfoo1298,
_dfoo13,
_dfoo130,
_dfoo1300,
_dfoo1302,
_dfoo1304,
_dfoo1306,
_dfoo1308,
_dfoo1310,
_dfoo1312,
_dfoo1314,
_dfoo1316,
_dfoo1318,
_dfoo132,
_dfoo1320,
_dfoo1322,
_dfoo1324,
_dfoo1326,
_dfoo1328,
_dfoo1330,
_dfoo1332,
_dfoo1334,
_dfoo1336,
_dfoo1338,
_dfoo134,
_dfoo1340,
_dfoo1342,
_dfoo1344,
_dfoo1346,
_dfoo1348,
_dfoo1350,
_dfoo1352,
_dfoo1354,
_dfoo1356,
_dfoo1358,
_dfoo136,
_dfoo1360,
_dfoo1361,
_dfoo1362,
_dfoo1363,
_dfoo1364,
_dfoo1365,
_dfoo1366,
_dfoo1367,
_dfoo1368,
_dfoo1369,
_dfoo137,
_dfoo1370,
_dfoo1371,
_dfoo1372,
_dfoo1373,
_dfoo1374,
_dfoo1375,
_dfoo1376,
_dfoo1377,
_dfoo1378,
_dfoo1379,
_dfoo138,
_dfoo1380,
_dfoo1381,
_dfoo1382,
_dfoo1383,
_dfoo1384,
_dfoo1385,
_dfoo1386,
_dfoo1387,
_dfoo1388,
_dfoo1389,
_dfoo139,
_dfoo1390,
_dfoo1391,
_dfoo1392,
_dfoo1393,
_dfoo1394,
_dfoo1395,
_dfoo1396,
_dfoo1397,
_dfoo1398,
_dfoo1399,
_dfoo14,
_dfoo140,
_dfoo1400,
_dfoo1401,
_dfoo1402,
_dfoo1403,
_dfoo1404,
_dfoo1405,
_dfoo1406,
_dfoo1407,
_dfoo1408,
_dfoo1409,
_dfoo141,
_dfoo1410,
_dfoo1411,
_dfoo1412,
_dfoo1413,
_dfoo1414,
_dfoo1415,
_dfoo1416,
_dfoo1417,
_dfoo1418,
_dfoo1419,
_dfoo142,
_dfoo1420,
_dfoo1421,
_dfoo1422,
_dfoo1423,
_dfoo1424,
_dfoo1425,
_dfoo1426,
_dfoo1427,
_dfoo1428,
_dfoo143,
_dfoo1430,
_dfoo1432,
_dfoo1434,
_dfoo1436,
_dfoo1438,
_dfoo144,
_dfoo1440,
_dfoo1442,
_dfoo1444,
_dfoo1446,
_dfoo1448,
_dfoo145,
_dfoo1450,
_dfoo1452,
_dfoo1454,
_dfoo1456,
_dfoo1458,
_dfoo146,
_dfoo1460,
_dfoo1462,
_dfoo1464,
_dfoo1466,
_dfoo1468,
_dfoo147,
_dfoo1470,
_dfoo1472,
_dfoo1474,
_dfoo1476,
_dfoo1478,
_dfoo148,
_dfoo1480,
_dfoo1482,
_dfoo1484,
_dfoo1486,
_dfoo1488,
_dfoo149,
_dfoo1490,
_dfoo1492,
_dfoo1494,
_dfoo1496,
_dfoo1497,
_dfoo1498,
_dfoo1499,
_dfoo15,
_dfoo150,
_dfoo1500,
_dfoo1501,
_dfoo1502,
_dfoo1503,
_dfoo1504,
_dfoo1505,
_dfoo1506,
_dfoo1507,
_dfoo1508,
_dfoo1509,
_dfoo151,
_dfoo1510,
_dfoo1511,
_dfoo1512,
_dfoo1513,
_dfoo1514,
_dfoo1515,
_dfoo1516,
_dfoo1517,
_dfoo1518,
_dfoo1519,
_dfoo152,
_dfoo1520,
_dfoo1521,
_dfoo1522,
_dfoo1523,
_dfoo1524,
_dfoo1525,
_dfoo1526,
_dfoo1527,
_dfoo1528,
_dfoo1529,
_dfoo153,
_dfoo1530,
_dfoo1531,
_dfoo1532,
_dfoo1533,
_dfoo1534,
_dfoo1535,
_dfoo1536,
_dfoo1537,
_dfoo1538,
_dfoo1539,
_dfoo154,
_dfoo1540,
_dfoo1541,
_dfoo1542,
_dfoo1543,
_dfoo1544,
_dfoo1545,
_dfoo1546,
_dfoo1547,
_dfoo1548,
_dfoo1549,
_dfoo155,
_dfoo1550,
_dfoo1551,
_dfoo1552,
_dfoo1553,
_dfoo1554,
_dfoo1555,
_dfoo1556,
_dfoo1557,
_dfoo1558,
_dfoo1559,
_dfoo156,
_dfoo1560,
_dfoo1561,
_dfoo1562,
_dfoo1563,
_dfoo1564,
_dfoo1566,
_dfoo1568,
_dfoo157,
_dfoo1570,
_dfoo1572,
_dfoo1574,
_dfoo1576,
_dfoo1578,
_dfoo158,
_dfoo1580,
_dfoo1582,
_dfoo1584,
_dfoo1586,
_dfoo1588,
_dfoo159,
_dfoo1590,
_dfoo1592,
_dfoo1594,
_dfoo1596,
_dfoo1598,
_dfoo16,
_dfoo160,
_dfoo1600,
_dfoo1602,
_dfoo1604,
_dfoo1606,
_dfoo1608,
_dfoo161,
_dfoo1610,
_dfoo1612,
_dfoo1614,
_dfoo1616,
_dfoo1618,
_dfoo162,
_dfoo1620,
_dfoo1622,
_dfoo1624,
_dfoo1626,
_dfoo1628,
_dfoo163,
_dfoo1630,
_dfoo1632,
_dfoo1633,
_dfoo1634,
_dfoo1635,
_dfoo1636,
_dfoo1637,
_dfoo1638,
_dfoo1639,
_dfoo164,
_dfoo1640,
_dfoo1641,
_dfoo1642,
_dfoo1643,
_dfoo1644,
_dfoo1645,
_dfoo1646,
_dfoo1647,
_dfoo1648,
_dfoo1649,
_dfoo165,
_dfoo1650,
_dfoo1651,
_dfoo1652,
_dfoo1653,
_dfoo1654,
_dfoo1655,
_dfoo1656,
_dfoo1657,
_dfoo1658,
_dfoo1659,
_dfoo166,
_dfoo1660,
_dfoo1661,
_dfoo1662,
_dfoo1663,
_dfoo1664,
_dfoo1665,
_dfoo1666,
_dfoo1667,
_dfoo1668,
_dfoo1669,
_dfoo167,
_dfoo1670,
_dfoo1671,
_dfoo1672,
_dfoo1673,
_dfoo1674,
_dfoo1675,
_dfoo1676,
_dfoo1677,
_dfoo1678,
_dfoo1679,
_dfoo168,
_dfoo1680,
_dfoo1681,
_dfoo1682,
_dfoo1683,
_dfoo1684,
_dfoo1685,
_dfoo1686,
_dfoo1687,
_dfoo1688,
_dfoo1689,
_dfoo169,
_dfoo1690,
_dfoo1691,
_dfoo1692,
_dfoo1693,
_dfoo1694,
_dfoo1695,
_dfoo1696,
_dfoo1697,
_dfoo1698,
_dfoo1699,
_dfoo17,
_dfoo170,
_dfoo1700,
_dfoo1702,
_dfoo1704,
_dfoo1706,
_dfoo1708,
_dfoo171,
_dfoo1710,
_dfoo1712,
_dfoo1714,
_dfoo1716,
_dfoo1718,
_dfoo172,
_dfoo1720,
_dfoo1722,
_dfoo1724,
_dfoo1726,
_dfoo1728,
_dfoo173,
_dfoo1730,
_dfoo1732,
_dfoo1734,
_dfoo1736,
_dfoo1738,
_dfoo174,
_dfoo1740,
_dfoo1742,
_dfoo1744,
_dfoo1746,
_dfoo1748,
_dfoo175,
_dfoo1750,
_dfoo1752,
_dfoo1754,
_dfoo1756,
_dfoo1758,
_dfoo176,
_dfoo1760,
_dfoo1762,
_dfoo1764,
_dfoo1766,
_dfoo1768,
_dfoo1769,
_dfoo177,
_dfoo1770,
_dfoo1771,
_dfoo1772,
_dfoo1773,
_dfoo1774,
_dfoo1775,
_dfoo1776,
_dfoo1777,
_dfoo1778,
_dfoo1779,
_dfoo178,
_dfoo1780,
_dfoo1781,
_dfoo1782,
_dfoo1783,
_dfoo1784,
_dfoo1785,
_dfoo1786,
_dfoo1787,
_dfoo1788,
_dfoo1789,
_dfoo179,
_dfoo1790,
_dfoo1791,
_dfoo1792,
_dfoo1793,
_dfoo1794,
_dfoo1795,
_dfoo1796,
_dfoo1797,
_dfoo1798,
_dfoo1799,
_dfoo18,
_dfoo180,
_dfoo1800,
_dfoo1801,
_dfoo1802,
_dfoo1803,
_dfoo1804,
_dfoo1805,
_dfoo1806,
_dfoo1807,
_dfoo1808,
_dfoo1809,
_dfoo181,
_dfoo1810,
_dfoo1811,
_dfoo1812,
_dfoo1813,
_dfoo1814,
_dfoo1815,
_dfoo1816,
_dfoo1817,
_dfoo1818,
_dfoo1819,
_dfoo182,
_dfoo1820,
_dfoo1821,
_dfoo1822,
_dfoo1823,
_dfoo1824,
_dfoo1825,
_dfoo1826,
_dfoo1827,
_dfoo1828,
_dfoo1829,
_dfoo183,
_dfoo1830,
_dfoo1831,
_dfoo1832,
_dfoo1833,
_dfoo1834,
_dfoo1835,
_dfoo1836,
_dfoo1838,
_dfoo184,
_dfoo1840,
_dfoo1842,
_dfoo1844,
_dfoo1846,
_dfoo1848,
_dfoo185,
_dfoo1850,
_dfoo1852,
_dfoo1854,
_dfoo1856,
_dfoo1858,
_dfoo186,
_dfoo1860,
_dfoo1862,
_dfoo1864,
_dfoo1866,
_dfoo1868,
_dfoo187,
_dfoo1870,
_dfoo1872,
_dfoo1874,
_dfoo1876,
_dfoo1878,
_dfoo188,
_dfoo1880,
_dfoo1882,
_dfoo1884,
_dfoo1886,
_dfoo1888,
_dfoo189,
_dfoo1890,
_dfoo1892,
_dfoo1894,
_dfoo1896,
_dfoo1898,
_dfoo19,
_dfoo190,
_dfoo1900,
_dfoo1902,
_dfoo1904,
_dfoo1905,
_dfoo1906,
_dfoo1907,
_dfoo1908,
_dfoo1909,
_dfoo191,
_dfoo1910,
_dfoo1911,
_dfoo1912,
_dfoo1913,
_dfoo1914,
_dfoo1915,
_dfoo1916,
_dfoo1917,
_dfoo1918,
_dfoo1919,
_dfoo192,
_dfoo1920,
_dfoo1921,
_dfoo1922,
_dfoo1923,
_dfoo1924,
_dfoo1925,
_dfoo1926,
_dfoo1927,
_dfoo1928,
_dfoo1929,
_dfoo193,
_dfoo1930,
_dfoo1931,
_dfoo1932,
_dfoo1933,
_dfoo1934,
_dfoo1935,
_dfoo1936,
_dfoo1937,
_dfoo1938,
_dfoo1939,
_dfoo194,
_dfoo1940,
_dfoo1941,
_dfoo1942,
_dfoo1943,
_dfoo1944,
_dfoo1945,
_dfoo1946,
_dfoo1947,
_dfoo1948,
_dfoo1949,
_dfoo195,
_dfoo1950,
_dfoo1951,
_dfoo1952,
_dfoo1953,
_dfoo1954,
_dfoo1955,
_dfoo1956,
_dfoo1957,
_dfoo1958,
_dfoo1959,
_dfoo196,
_dfoo1960,
_dfoo1961,
_dfoo1962,
_dfoo1963,
_dfoo1964,
_dfoo1965,
_dfoo1966,
_dfoo1967,
_dfoo1968,
_dfoo1969,
_dfoo197,
_dfoo1970,
_dfoo1971,
_dfoo1972,
_dfoo1974,
_dfoo1976,
_dfoo1978,
_dfoo198,
_dfoo1980,
_dfoo1982,
_dfoo1984,
_dfoo1986,
_dfoo1988,
_dfoo199,
_dfoo1990,
_dfoo1992,
_dfoo1994,
_dfoo1996,
_dfoo1998,
_dfoo2,
_dfoo20,
_dfoo200,
_dfoo2000,
_dfoo2002,
_dfoo2004,
_dfoo2006,
_dfoo2008,
_dfoo201,
_dfoo2010,
_dfoo2012,
_dfoo2014,
_dfoo2016,
_dfoo2018,
_dfoo202,
_dfoo2020,
_dfoo2022,
_dfoo2024,
_dfoo2026,
_dfoo2028,
_dfoo203,
_dfoo2030,
_dfoo2032,
_dfoo2034,
_dfoo2036,
_dfoo2038,
_dfoo204,
_dfoo2040,
_dfoo2041,
_dfoo2043,
_dfoo2045,
_dfoo2047,
_dfoo2049,
_dfoo2051,
_dfoo2053,
_dfoo2055,
_dfoo2057,
_dfoo2059,
_dfoo206,
_dfoo2061,
_dfoo2063,
_dfoo2065,
_dfoo2067,
_dfoo2069,
_dfoo2071,
_dfoo2073,
_dfoo2075,
_dfoo2077,
_dfoo2079,
_dfoo208,
_dfoo2081,
_dfoo2083,
_dfoo2085,
_dfoo2087,
_dfoo2089,
_dfoo2091,
_dfoo2093,
_dfoo2095,
_dfoo2097,
_dfoo2099,
_dfoo21,
_dfoo210,
_dfoo2101,
_dfoo2103,
_dfoo2105,
_dfoo2107,
_dfoo212,
_dfoo214,
_dfoo216,
_dfoo218,
_dfoo22,
_dfoo220,
_dfoo222,
_dfoo224,
_dfoo226,
_dfoo228,
_dfoo23,
_dfoo230,
_dfoo232,
_dfoo234,
_dfoo236,
_dfoo238,
_dfoo24,
_dfoo240,
_dfoo242,
_dfoo244,
_dfoo246,
_dfoo248,
_dfoo25,
_dfoo250,
_dfoo252,
_dfoo254,
_dfoo256,
_dfoo258,
_dfoo26,
_dfoo260,
_dfoo262,
_dfoo264,
_dfoo266,
_dfoo268,
_dfoo27,
_dfoo270,
_dfoo272,
_dfoo273,
_dfoo274,
_dfoo275,
_dfoo276,
_dfoo277,
_dfoo278,
_dfoo279,
_dfoo28,
_dfoo280,
_dfoo281,
_dfoo282,
_dfoo283,
_dfoo284,
_dfoo285,
_dfoo286,
_dfoo287,
_dfoo288,
_dfoo289,
_dfoo29,
_dfoo290,
_dfoo291,
_dfoo292,
_dfoo293,
_dfoo294,
_dfoo295,
_dfoo296,
_dfoo297,
_dfoo298,
_dfoo299,
_dfoo3,
_dfoo30,
_dfoo300,
_dfoo301,
_dfoo302,
_dfoo303,
_dfoo304,
_dfoo305,
_dfoo306,
_dfoo307,
_dfoo308,
_dfoo309,
_dfoo31,
_dfoo310,
_dfoo311,
_dfoo312,
_dfoo313,
_dfoo314,
_dfoo315,
_dfoo316,
_dfoo317,
_dfoo318,
_dfoo319,
_dfoo32,
_dfoo320,
_dfoo321,
_dfoo322,
_dfoo323,
_dfoo324,
_dfoo325,
_dfoo326,
_dfoo327,
_dfoo328,
_dfoo329,
_dfoo33,
_dfoo330,
_dfoo331,
_dfoo332,
_dfoo333,
_dfoo334,
_dfoo335,
_dfoo336,
_dfoo337,
_dfoo338,
_dfoo339,
_dfoo34,
_dfoo340,
_dfoo342,
_dfoo344,
_dfoo346,
_dfoo348,
_dfoo35,
_dfoo350,
_dfoo352,
_dfoo354,
_dfoo356,
_dfoo358,
_dfoo36,
_dfoo360,
_dfoo362,
_dfoo364,
_dfoo366,
_dfoo368,
_dfoo37,
_dfoo370,
_dfoo372,
_dfoo374,
_dfoo376,
_dfoo378,
_dfoo38,
_dfoo380,
_dfoo382,
_dfoo384,
_dfoo386,
_dfoo388,
_dfoo39,
_dfoo390,
_dfoo392,
_dfoo394,
_dfoo396,
_dfoo398,
_dfoo4,
_dfoo40,
_dfoo400,
_dfoo402,
_dfoo404,
_dfoo406,
_dfoo408,
_dfoo409,
_dfoo41,
_dfoo410,
_dfoo411,
_dfoo412,
_dfoo413,
_dfoo414,
_dfoo415,
_dfoo416,
_dfoo417,
_dfoo418,
_dfoo419,
_dfoo42,
_dfoo420,
_dfoo421,
_dfoo422,
_dfoo423,
_dfoo424,
_dfoo425,
_dfoo426,
_dfoo427,
_dfoo428,
_dfoo429,
_dfoo43,
_dfoo430,
_dfoo431,
_dfoo432,
_dfoo433,
_dfoo434,
_dfoo435,
_dfoo436,
_dfoo437,
_dfoo438,
_dfoo439,
_dfoo44,
_dfoo440,
_dfoo441,
_dfoo442,
_dfoo443,
_dfoo444,
_dfoo445,
_dfoo446,
_dfoo447,
_dfoo448,
_dfoo449,
_dfoo45,
_dfoo450,
_dfoo451,
_dfoo452,
_dfoo453,
_dfoo454,
_dfoo455,
_dfoo456,
_dfoo457,
_dfoo458,
_dfoo459,
_dfoo46,
_dfoo460,
_dfoo461,
_dfoo462,
_dfoo463,
_dfoo464,
_dfoo465,
_dfoo466,
_dfoo467,
_dfoo468,
_dfoo469,
_dfoo47,
_dfoo470,
_dfoo471,
_dfoo472,
_dfoo473,
_dfoo474,
_dfoo475,
_dfoo476,
_dfoo478,
_dfoo48,
_dfoo480,
_dfoo482,
_dfoo484,
_dfoo486,
_dfoo488,
_dfoo49,
_dfoo490,
_dfoo492,
_dfoo494,
_dfoo496,
_dfoo498,
_dfoo5,
_dfoo50,
_dfoo500,
_dfoo502,
_dfoo504,
_dfoo506,
_dfoo508,
_dfoo51,
_dfoo510,
_dfoo512,
_dfoo514,
_dfoo516,
_dfoo518,
_dfoo52,
_dfoo520,
_dfoo522,
_dfoo524,
_dfoo526,
_dfoo528,
_dfoo53,
_dfoo530,
_dfoo532,
_dfoo534,
_dfoo536,
_dfoo538,
_dfoo54,
_dfoo540,
_dfoo542,
_dfoo544,
_dfoo545,
_dfoo546,
_dfoo547,
_dfoo548,
_dfoo549,
_dfoo55,
_dfoo550,
_dfoo551,
_dfoo552,
_dfoo553,
_dfoo554,
_dfoo555,
_dfoo556,
_dfoo557,
_dfoo558,
_dfoo559,
_dfoo56,
_dfoo560,
_dfoo561,
_dfoo562,
_dfoo563,
_dfoo564,
_dfoo565,
_dfoo566,
_dfoo567,
_dfoo568,
_dfoo569,
_dfoo57,
_dfoo570,
_dfoo571,
_dfoo572,
_dfoo573,
_dfoo574,
_dfoo575,
_dfoo576,
_dfoo577,
_dfoo578,
_dfoo579,
_dfoo58,
_dfoo580,
_dfoo581,
_dfoo582,
_dfoo583,
_dfoo584,
_dfoo585,
_dfoo586,
_dfoo587,
_dfoo588,
_dfoo589,
_dfoo59,
_dfoo590,
_dfoo591,
_dfoo592,
_dfoo593,
_dfoo594,
_dfoo595,
_dfoo596,
_dfoo597,
_dfoo598,
_dfoo599,
_dfoo6,
_dfoo60,
_dfoo600,
_dfoo601,
_dfoo602,
_dfoo603,
_dfoo604,
_dfoo605,
_dfoo606,
_dfoo607,
_dfoo608,
_dfoo609,
_dfoo61,
_dfoo610,
_dfoo611,
_dfoo612,
_dfoo614,
_dfoo616,
_dfoo618,
_dfoo62,
_dfoo620,
_dfoo622,
_dfoo624,
_dfoo626,
_dfoo628,
_dfoo63,
_dfoo630,
_dfoo632,
_dfoo634,
_dfoo636,
_dfoo638,
_dfoo64,
_dfoo640,
_dfoo642,
_dfoo644,
_dfoo646,
_dfoo648,
_dfoo65,
_dfoo650,
_dfoo652,
_dfoo654,
_dfoo656,
_dfoo658,
_dfoo66,
_dfoo660,
_dfoo662,
_dfoo664,
_dfoo666,
_dfoo668,
_dfoo67,
_dfoo670,
_dfoo672,
_dfoo674,
_dfoo676,
_dfoo678,
_dfoo68,
_dfoo680,
_dfoo681,
_dfoo682,
_dfoo683,
_dfoo684,
_dfoo685,
_dfoo686,
_dfoo687,
_dfoo688,
_dfoo689,
_dfoo690,
_dfoo691,
_dfoo692,
_dfoo693,
_dfoo694,
_dfoo695,
_dfoo696,
_dfoo697,
_dfoo698,
_dfoo699,
_dfoo7,
_dfoo70,
_dfoo700,
_dfoo701,
_dfoo702,
_dfoo703,
_dfoo704,
_dfoo705,
_dfoo706,
_dfoo707,
_dfoo708,
_dfoo709,
_dfoo710,
_dfoo711,
_dfoo712,
_dfoo713,
_dfoo714,
_dfoo715,
_dfoo716,
_dfoo717,
_dfoo718,
_dfoo719,
_dfoo72,
_dfoo720,
_dfoo721,
_dfoo722,
_dfoo723,
_dfoo724,
_dfoo725,
_dfoo726,
_dfoo727,
_dfoo728,
_dfoo729,
_dfoo730,
_dfoo731,
_dfoo732,
_dfoo733,
_dfoo734,
_dfoo735,
_dfoo736,
_dfoo737,
_dfoo738,
_dfoo739,
_dfoo74,
_dfoo740,
_dfoo741,
_dfoo742,
_dfoo743,
_dfoo744,
_dfoo745,
_dfoo746,
_dfoo747,
_dfoo748,
_dfoo750,
_dfoo752,
_dfoo754,
_dfoo756,
_dfoo758,
_dfoo76,
_dfoo760,
_dfoo762,
_dfoo764,
_dfoo766,
_dfoo768,
_dfoo770,
_dfoo772,
_dfoo774,
_dfoo776,
_dfoo778,
_dfoo78,
_dfoo780,
_dfoo782,
_dfoo784,
_dfoo786,
_dfoo788,
_dfoo790,
_dfoo792,
_dfoo794,
_dfoo796,
_dfoo798,
_dfoo8,
_dfoo80,
_dfoo800,
_dfoo802,
_dfoo804,
_dfoo806,
_dfoo808,
_dfoo810,
_dfoo812,
_dfoo814,
_dfoo816,
_dfoo817,
_dfoo818,
_dfoo819,
_dfoo82,
_dfoo820,
_dfoo821,
_dfoo822,
_dfoo823,
_dfoo824,
_dfoo825,
_dfoo826,
_dfoo827,
_dfoo828,
_dfoo829,
_dfoo830,
_dfoo831,
_dfoo832,
_dfoo833,
_dfoo834,
_dfoo835,
_dfoo836,
_dfoo837,
_dfoo838,
_dfoo839,
_dfoo84,
_dfoo840,
_dfoo841,
_dfoo842,
_dfoo843,
_dfoo844,
_dfoo845,
_dfoo846,
_dfoo847,
_dfoo848,
_dfoo849,
_dfoo850,
_dfoo851,
_dfoo852,
_dfoo853,
_dfoo854,
_dfoo855,
_dfoo856,
_dfoo857,
_dfoo858,
_dfoo859,
_dfoo86,
_dfoo860,
_dfoo861,
_dfoo862,
_dfoo863,
_dfoo864,
_dfoo865,
_dfoo866,
_dfoo867,
_dfoo868,
_dfoo869,
_dfoo870,
_dfoo871,
_dfoo872,
_dfoo873,
_dfoo874,
_dfoo875,
_dfoo876,
_dfoo877,
_dfoo878,
_dfoo879,
_dfoo88,
_dfoo880,
_dfoo881,
_dfoo882,
_dfoo883,
_dfoo884,
_dfoo886,
_dfoo888,
_dfoo890,
_dfoo892,
_dfoo894,
_dfoo896,
_dfoo898,
_dfoo9,
_dfoo90,
_dfoo900,
_dfoo902,
_dfoo904,
_dfoo906,
_dfoo908,
_dfoo910,
_dfoo912,
_dfoo914,
_dfoo916,
_dfoo918,
_dfoo92,
_dfoo920,
_dfoo922,
_dfoo924,
_dfoo926,
_dfoo928,
_dfoo930,
_dfoo932,
_dfoo934,
_dfoo936,
_dfoo938,
_dfoo94,
_dfoo940,
_dfoo942,
_dfoo944,
_dfoo946,
_dfoo948,
_dfoo950,
_dfoo952,
_dfoo953,
_dfoo954,
_dfoo955,
_dfoo956,
_dfoo957,
_dfoo958,
_dfoo959,
_dfoo96,
_dfoo960,
_dfoo961,
_dfoo962,
_dfoo963,
_dfoo964,
_dfoo965,
_dfoo966,
_dfoo967,
_dfoo968,
_dfoo969,
_dfoo970,
_dfoo971,
_dfoo972,
_dfoo973,
_dfoo974,
_dfoo975,
_dfoo976,
_dfoo977,
_dfoo978,
_dfoo979,
_dfoo98,
_dfoo980,
_dfoo981,
_dfoo982,
_dfoo983,
_dfoo984,
_dfoo985,
_dfoo986,
_dfoo987,
_dfoo988,
_dfoo989,
_dfoo990,
_dfoo991,
_dfoo992,
_dfoo993,
_dfoo994,
_dfoo995,
_dfoo996,
_dfoo997,
_dfoo998,
_dfoo999,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2860,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2862,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d837,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d839,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d841,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d843,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d845,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d847,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d849,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d851,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d853,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d855,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d857,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d859,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d861,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d863,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d865,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d867,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d869,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931,
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3036,
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3130,
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614,
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3041,
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3135,
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621,
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3046,
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3140,
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628,
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3051,
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3145,
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635,
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d686,
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3056,
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3150,
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642,
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3061,
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3155,
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649,
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3066,
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3160,
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656,
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d689,
m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551,
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d2996,
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3090,
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558,
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3001,
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3095,
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565,
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3006,
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3100,
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572,
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3011,
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3105,
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579,
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3016,
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3110,
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586,
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3021,
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3115,
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593,
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d680,
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3026,
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3120,
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600,
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3031,
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3125,
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607,
m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method show_PLIC_state
assign RDY_show_PLIC_state = 1'd1 ;
assign CAN_FIRE_show_PLIC_state = 1'd1 ;
assign WILL_FIRE_show_PLIC_state = EN_show_PLIC_state ;
// action method server_reset_request_put
assign RDY_server_reset_request_put = m_f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_reset_request_put = m_f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = m_f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = m_f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method set_addr_map
assign RDY_set_addr_map = 1'd1 ;
assign CAN_FIRE_set_addr_map = 1'd1 ;
assign WILL_FIRE_set_addr_map = EN_set_addr_map ;
// action method axi4_slave_m_awvalid
assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ;
// value method axi4_slave_m_awready
assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ;
// action method axi4_slave_m_wvalid
assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ;
// value method axi4_slave_m_wready
assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ;
// value method axi4_slave_m_bvalid
assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ;
// value method axi4_slave_m_bid
assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[5:2] ;
// value method axi4_slave_m_bresp
assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ;
// action method axi4_slave_m_bready
assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ;
// action method axi4_slave_m_arvalid
assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ;
// value method axi4_slave_m_arready
assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ;
// value method axi4_slave_m_rvalid
assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ;
// value method axi4_slave_m_rid
assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[70:67] ;
// value method axi4_slave_m_rdata
assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ;
// value method axi4_slave_m_rresp
assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ;
// value method axi4_slave_m_rlast
assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ;
// action method axi4_slave_m_rready
assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ;
// action method v_sources_0_m_interrupt_req
assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_0_m_interrupt_req = 1'd1 ;
// action method v_sources_1_m_interrupt_req
assign CAN_FIRE_v_sources_1_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_1_m_interrupt_req = 1'd1 ;
// action method v_sources_2_m_interrupt_req
assign CAN_FIRE_v_sources_2_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_2_m_interrupt_req = 1'd1 ;
// action method v_sources_3_m_interrupt_req
assign CAN_FIRE_v_sources_3_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_3_m_interrupt_req = 1'd1 ;
// action method v_sources_4_m_interrupt_req
assign CAN_FIRE_v_sources_4_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_4_m_interrupt_req = 1'd1 ;
// action method v_sources_5_m_interrupt_req
assign CAN_FIRE_v_sources_5_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_5_m_interrupt_req = 1'd1 ;
// action method v_sources_6_m_interrupt_req
assign CAN_FIRE_v_sources_6_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_6_m_interrupt_req = 1'd1 ;
// action method v_sources_7_m_interrupt_req
assign CAN_FIRE_v_sources_7_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_7_m_interrupt_req = 1'd1 ;
// action method v_sources_8_m_interrupt_req
assign CAN_FIRE_v_sources_8_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_8_m_interrupt_req = 1'd1 ;
// action method v_sources_9_m_interrupt_req
assign CAN_FIRE_v_sources_9_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_9_m_interrupt_req = 1'd1 ;
// action method v_sources_10_m_interrupt_req
assign CAN_FIRE_v_sources_10_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_10_m_interrupt_req = 1'd1 ;
// action method v_sources_11_m_interrupt_req
assign CAN_FIRE_v_sources_11_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_11_m_interrupt_req = 1'd1 ;
// action method v_sources_12_m_interrupt_req
assign CAN_FIRE_v_sources_12_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_12_m_interrupt_req = 1'd1 ;
// action method v_sources_13_m_interrupt_req
assign CAN_FIRE_v_sources_13_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_13_m_interrupt_req = 1'd1 ;
// action method v_sources_14_m_interrupt_req
assign CAN_FIRE_v_sources_14_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_14_m_interrupt_req = 1'd1 ;
// action method v_sources_15_m_interrupt_req
assign CAN_FIRE_v_sources_15_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ;
// value method v_targets_0_m_eip
assign v_targets_0_m_eip = a__h81740 > m_vrg_target_threshold_0 ;
// value method v_targets_1_m_eip
assign v_targets_1_m_eip = a__h83894 > m_vrg_target_threshold_1 ;
// submodule m_f_reset_reqs
FIFO20 #(.guarded(1'd1)) m_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(m_f_reset_reqs$ENQ),
.DEQ(m_f_reset_reqs$DEQ),
.CLR(m_f_reset_reqs$CLR),
.FULL_N(m_f_reset_reqs$FULL_N),
.EMPTY_N(m_f_reset_reqs$EMPTY_N));
// submodule m_f_reset_rsps
FIFO20 #(.guarded(1'd1)) m_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(m_f_reset_rsps$ENQ),
.DEQ(m_f_reset_rsps$DEQ),
.CLR(m_f_reset_rsps$CLR),
.FULL_N(m_f_reset_rsps$FULL_N),
.EMPTY_N(m_f_reset_rsps$EMPTY_N));
// submodule m_slave_xactor_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_slave_xactor_f_rd_addr$D_IN),
.ENQ(m_slave_xactor_f_rd_addr$ENQ),
.DEQ(m_slave_xactor_f_rd_addr$DEQ),
.CLR(m_slave_xactor_f_rd_addr$CLR),
.D_OUT(m_slave_xactor_f_rd_addr$D_OUT),
.FULL_N(m_slave_xactor_f_rd_addr$FULL_N),
.EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N));
// submodule m_slave_xactor_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) m_slave_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_slave_xactor_f_rd_data$D_IN),
.ENQ(m_slave_xactor_f_rd_data$ENQ),
.DEQ(m_slave_xactor_f_rd_data$DEQ),
.CLR(m_slave_xactor_f_rd_data$CLR),
.D_OUT(m_slave_xactor_f_rd_data$D_OUT),
.FULL_N(m_slave_xactor_f_rd_data$FULL_N),
.EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N));
// submodule m_slave_xactor_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_slave_xactor_f_wr_addr$D_IN),
.ENQ(m_slave_xactor_f_wr_addr$ENQ),
.DEQ(m_slave_xactor_f_wr_addr$DEQ),
.CLR(m_slave_xactor_f_wr_addr$CLR),
.D_OUT(m_slave_xactor_f_wr_addr$D_OUT),
.FULL_N(m_slave_xactor_f_wr_addr$FULL_N),
.EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N));
// submodule m_slave_xactor_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) m_slave_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_slave_xactor_f_wr_data$D_IN),
.ENQ(m_slave_xactor_f_wr_data$ENQ),
.DEQ(m_slave_xactor_f_wr_data$DEQ),
.CLR(m_slave_xactor_f_wr_data$CLR),
.D_OUT(m_slave_xactor_f_wr_data$D_OUT),
.FULL_N(m_slave_xactor_f_wr_data$FULL_N),
.EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N));
// submodule m_slave_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(1'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(m_slave_xactor_f_wr_resp$D_IN),
.ENQ(m_slave_xactor_f_wr_resp$ENQ),
.DEQ(m_slave_xactor_f_wr_resp$DEQ),
.CLR(m_slave_xactor_f_wr_resp$CLR),
.D_OUT(m_slave_xactor_f_wr_resp$D_OUT),
.FULL_N(m_slave_xactor_f_wr_resp$FULL_N),
.EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N));
// rule RL_m_rl_reset
assign CAN_FIRE_RL_m_rl_reset =
m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ;
// rule RL_m_rl_process_rd_req
assign CAN_FIRE_RL_m_rl_process_rd_req =
m_slave_xactor_f_rd_addr$EMPTY_N &&
m_slave_xactor_f_rd_data$FULL_N &&
!m_f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ;
// rule RL_m_rl_process_wr_req
assign CAN_FIRE_RL_m_rl_process_wr_req =
m_slave_xactor_f_wr_addr$EMPTY_N &&
m_slave_xactor_f_wr_data$EMPTY_N &&
m_slave_xactor_f_wr_resp$FULL_N &&
!m_f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_m_rl_process_wr_req = CAN_FIRE_RL_m_rl_process_wr_req ;
// inputs to muxes for submodule ports
assign MUX_m_vrg_source_busy_0$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd0 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_0$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd0 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_1$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd1 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_1$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd1 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_10$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd10 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_10$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd10 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_11$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd11 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_11$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd11 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_12$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd12 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_12$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd12 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_13$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd13 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_13$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd13 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_14$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd14 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_14$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd14 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_15$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd15 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_15$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd15 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_16$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd16 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_16$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd16 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_2$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd2 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_2$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd2 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_3$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd3 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_3$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd3 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_4$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd4 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_4$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd4 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_5$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd5 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_5$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd5 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_6$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd6 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_6$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd6 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_7$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd7 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_7$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd7 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_8$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd8 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_8$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd8 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_9$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd9 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_9$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd9 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_prio_0$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
addr_offset__h27245[11:2] == 10'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d826 ;
assign MUX_m_vrg_source_prio_1$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d837 ;
assign MUX_m_vrg_source_prio_10$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d855 ;
assign MUX_m_vrg_source_prio_11$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d857 ;
assign MUX_m_vrg_source_prio_12$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d859 ;
assign MUX_m_vrg_source_prio_13$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d861 ;
assign MUX_m_vrg_source_prio_14$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d863 ;
assign MUX_m_vrg_source_prio_15$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d865 ;
assign MUX_m_vrg_source_prio_16$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d867 ;
assign MUX_m_vrg_source_prio_2$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d839 ;
assign MUX_m_vrg_source_prio_3$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d841 ;
assign MUX_m_vrg_source_prio_4$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d843 ;
assign MUX_m_vrg_source_prio_5$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d845 ;
assign MUX_m_vrg_source_prio_6$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d847 ;
assign MUX_m_vrg_source_prio_7$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d849 ;
assign MUX_m_vrg_source_prio_8$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d851 ;
assign MUX_m_vrg_source_prio_9$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d853 ;
assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2860 ;
assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2862 ;
assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ;
assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ;
assign MUX_m_vvrg_ie_0_10$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ;
assign MUX_m_vvrg_ie_0_11$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ;
assign MUX_m_vvrg_ie_0_12$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ;
assign MUX_m_vvrg_ie_0_13$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ;
assign MUX_m_vvrg_ie_0_14$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ;
assign MUX_m_vvrg_ie_0_15$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ;
assign MUX_m_vvrg_ie_0_16$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ;
assign MUX_m_vvrg_ie_0_2$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ;
assign MUX_m_vvrg_ie_0_3$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ;
assign MUX_m_vvrg_ie_0_4$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ;
assign MUX_m_vvrg_ie_0_5$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ;
assign MUX_m_vvrg_ie_0_6$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ;
assign MUX_m_vvrg_ie_0_7$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ;
assign MUX_m_vvrg_ie_0_8$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ;
assign MUX_m_vvrg_ie_0_9$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ;
assign MUX_m_vvrg_ie_1_0$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ;
assign MUX_m_vvrg_ie_1_1$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ;
assign MUX_m_vvrg_ie_1_10$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ;
assign MUX_m_vvrg_ie_1_11$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ;
assign MUX_m_vvrg_ie_1_12$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ;
assign MUX_m_vvrg_ie_1_13$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ;
assign MUX_m_vvrg_ie_1_14$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ;
assign MUX_m_vvrg_ie_1_15$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ;
assign MUX_m_vvrg_ie_1_16$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ;
assign MUX_m_vvrg_ie_1_2$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ;
assign MUX_m_vvrg_ie_1_3$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ;
assign MUX_m_vvrg_ie_1_4$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ;
assign MUX_m_vvrg_ie_1_5$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ;
assign MUX_m_vvrg_ie_1_6$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ;
assign MUX_m_vvrg_ie_1_7$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ;
assign MUX_m_vvrg_ie_1_8$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ;
assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ;
assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 =
(source_id_base__h28620 == 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2040 ;
assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 =
(source_id_base__h28620 == 10'd1 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2038 ;
assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 =
(source_id_base__h28620 == 10'd10 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2020 ;
assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 =
(source_id_base__h28620 == 10'd11 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2018 ;
assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 =
(source_id_base__h28620 == 10'd12 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2016 ;
assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 =
(source_id_base__h28620 == 10'd13 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2014 ;
assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 =
(source_id_base__h28620 == 10'd14 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2012 ;
assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 =
(source_id_base__h28620 == 10'd15 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2010 ;
assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 =
(source_id_base__h28620 == 10'd16 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2008 ;
assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 =
(source_id_base__h28620 == 10'd2 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2036 ;
assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 =
(source_id_base__h28620 == 10'd3 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2034 ;
assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 =
(source_id_base__h28620 == 10'd4 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2032 ;
assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 =
(source_id_base__h28620 == 10'd5 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2030 ;
assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 =
(source_id_base__h28620 == 10'd6 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2028 ;
assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 =
(source_id_base__h28620 == 10'd7 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2026 ;
assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 =
(source_id_base__h28620 == 10'd8 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2024 ;
assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 =
(source_id_base__h28620 == 10'd9 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2022 ;
assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 =
(source_id_base__h28620 == 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo2006 ;
assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 =
(source_id_base__h28620 == 10'd1 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo2004 ;
assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 =
(source_id_base__h28620 == 10'd10 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1986 ;
assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 =
(source_id_base__h28620 == 10'd11 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1984 ;
assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 =
(source_id_base__h28620 == 10'd12 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1982 ;
assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 =
(source_id_base__h28620 == 10'd13 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1980 ;
assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 =
(source_id_base__h28620 == 10'd14 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1978 ;
assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 =
(source_id_base__h28620 == 10'd15 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1976 ;
assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 =
(source_id_base__h28620 == 10'd16 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1974 ;
assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 =
(source_id_base__h28620 == 10'd2 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo2002 ;
assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 =
(source_id_base__h28620 == 10'd3 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo2000 ;
assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 =
(source_id_base__h28620 == 10'd4 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1998 ;
assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 =
(source_id_base__h28620 == 10'd5 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1996 ;
assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 =
(source_id_base__h28620 == 10'd6 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1994 ;
assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 =
(source_id_base__h28620 == 10'd7 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1992 ;
assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 =
(source_id_base__h28620 == 10'd8 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1990 ;
assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 =
(source_id_base__h28620 == 10'd9 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1988 ;
// register m_cfg_verbosity
assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign m_cfg_verbosity$EN = EN_set_verbosity ;
// register m_rg_addr_base
assign m_rg_addr_base$D_IN = set_addr_map_addr_base ;
assign m_rg_addr_base$EN = EN_set_addr_map ;
// register m_rg_addr_lim
assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ;
assign m_rg_addr_lim$EN = EN_set_addr_map ;
// register m_vrg_source_busy_0
always@(MUX_m_vrg_source_busy_0$write_1__SEL_1 or
MUX_m_vrg_source_busy_0$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_0$write_1__SEL_1: m_vrg_source_busy_0$D_IN = 1'd0;
MUX_m_vrg_source_busy_0$write_1__SEL_2: m_vrg_source_busy_0$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_0$D_IN = 1'd0;
default: m_vrg_source_busy_0$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_0$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd0 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd0 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_1
always@(MUX_m_vrg_source_busy_1$write_1__SEL_1 or
MUX_m_vrg_source_busy_1$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_1$write_1__SEL_1: m_vrg_source_busy_1$D_IN = 1'd0;
MUX_m_vrg_source_busy_1$write_1__SEL_2: m_vrg_source_busy_1$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_1$D_IN = 1'd0;
default: m_vrg_source_busy_1$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_1$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd1 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd1 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_10
always@(MUX_m_vrg_source_busy_10$write_1__SEL_1 or
MUX_m_vrg_source_busy_10$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_10$write_1__SEL_1: m_vrg_source_busy_10$D_IN = 1'd0;
MUX_m_vrg_source_busy_10$write_1__SEL_2: m_vrg_source_busy_10$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_10$D_IN = 1'd0;
default: m_vrg_source_busy_10$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_10$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd10 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd10 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_11
always@(MUX_m_vrg_source_busy_11$write_1__SEL_1 or
MUX_m_vrg_source_busy_11$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_11$write_1__SEL_1: m_vrg_source_busy_11$D_IN = 1'd0;
MUX_m_vrg_source_busy_11$write_1__SEL_2: m_vrg_source_busy_11$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_11$D_IN = 1'd0;
default: m_vrg_source_busy_11$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_11$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd11 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd11 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_12
always@(MUX_m_vrg_source_busy_12$write_1__SEL_1 or
MUX_m_vrg_source_busy_12$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_12$write_1__SEL_1: m_vrg_source_busy_12$D_IN = 1'd0;
MUX_m_vrg_source_busy_12$write_1__SEL_2: m_vrg_source_busy_12$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_12$D_IN = 1'd0;
default: m_vrg_source_busy_12$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_12$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd12 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd12 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_13
always@(MUX_m_vrg_source_busy_13$write_1__SEL_1 or
MUX_m_vrg_source_busy_13$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_13$write_1__SEL_1: m_vrg_source_busy_13$D_IN = 1'd0;
MUX_m_vrg_source_busy_13$write_1__SEL_2: m_vrg_source_busy_13$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_13$D_IN = 1'd0;
default: m_vrg_source_busy_13$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_13$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd13 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd13 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_14
always@(MUX_m_vrg_source_busy_14$write_1__SEL_1 or
MUX_m_vrg_source_busy_14$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_14$write_1__SEL_1: m_vrg_source_busy_14$D_IN = 1'd0;
MUX_m_vrg_source_busy_14$write_1__SEL_2: m_vrg_source_busy_14$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_14$D_IN = 1'd0;
default: m_vrg_source_busy_14$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_14$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd14 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd14 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_15
always@(MUX_m_vrg_source_busy_15$write_1__SEL_1 or
MUX_m_vrg_source_busy_15$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_15$write_1__SEL_1: m_vrg_source_busy_15$D_IN = 1'd0;
MUX_m_vrg_source_busy_15$write_1__SEL_2: m_vrg_source_busy_15$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_15$D_IN = 1'd0;
default: m_vrg_source_busy_15$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_15$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd15 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd15 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_16
always@(MUX_m_vrg_source_busy_16$write_1__SEL_1 or
MUX_m_vrg_source_busy_16$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_16$write_1__SEL_1: m_vrg_source_busy_16$D_IN = 1'd0;
MUX_m_vrg_source_busy_16$write_1__SEL_2: m_vrg_source_busy_16$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_16$D_IN = 1'd0;
default: m_vrg_source_busy_16$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_16$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd16 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd16 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_2
always@(MUX_m_vrg_source_busy_2$write_1__SEL_1 or
MUX_m_vrg_source_busy_2$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_2$write_1__SEL_1: m_vrg_source_busy_2$D_IN = 1'd0;
MUX_m_vrg_source_busy_2$write_1__SEL_2: m_vrg_source_busy_2$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_2$D_IN = 1'd0;
default: m_vrg_source_busy_2$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_2$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd2 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd2 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_3
always@(MUX_m_vrg_source_busy_3$write_1__SEL_1 or
MUX_m_vrg_source_busy_3$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_3$write_1__SEL_1: m_vrg_source_busy_3$D_IN = 1'd0;
MUX_m_vrg_source_busy_3$write_1__SEL_2: m_vrg_source_busy_3$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_3$D_IN = 1'd0;
default: m_vrg_source_busy_3$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_3$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd3 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd3 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_4
always@(MUX_m_vrg_source_busy_4$write_1__SEL_1 or
MUX_m_vrg_source_busy_4$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_4$write_1__SEL_1: m_vrg_source_busy_4$D_IN = 1'd0;
MUX_m_vrg_source_busy_4$write_1__SEL_2: m_vrg_source_busy_4$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_4$D_IN = 1'd0;
default: m_vrg_source_busy_4$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_4$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd4 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd4 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_5
always@(MUX_m_vrg_source_busy_5$write_1__SEL_1 or
MUX_m_vrg_source_busy_5$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_5$write_1__SEL_1: m_vrg_source_busy_5$D_IN = 1'd0;
MUX_m_vrg_source_busy_5$write_1__SEL_2: m_vrg_source_busy_5$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_5$D_IN = 1'd0;
default: m_vrg_source_busy_5$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_5$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd5 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd5 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_6
always@(MUX_m_vrg_source_busy_6$write_1__SEL_1 or
MUX_m_vrg_source_busy_6$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_6$write_1__SEL_1: m_vrg_source_busy_6$D_IN = 1'd0;
MUX_m_vrg_source_busy_6$write_1__SEL_2: m_vrg_source_busy_6$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_6$D_IN = 1'd0;
default: m_vrg_source_busy_6$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_6$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd6 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd6 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_7
always@(MUX_m_vrg_source_busy_7$write_1__SEL_1 or
MUX_m_vrg_source_busy_7$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_7$write_1__SEL_1: m_vrg_source_busy_7$D_IN = 1'd0;
MUX_m_vrg_source_busy_7$write_1__SEL_2: m_vrg_source_busy_7$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_7$D_IN = 1'd0;
default: m_vrg_source_busy_7$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_7$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd7 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd7 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_8
always@(MUX_m_vrg_source_busy_8$write_1__SEL_1 or
MUX_m_vrg_source_busy_8$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_8$write_1__SEL_1: m_vrg_source_busy_8$D_IN = 1'd0;
MUX_m_vrg_source_busy_8$write_1__SEL_2: m_vrg_source_busy_8$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_8$D_IN = 1'd0;
default: m_vrg_source_busy_8$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_8$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd8 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd8 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_9
always@(MUX_m_vrg_source_busy_9$write_1__SEL_1 or
MUX_m_vrg_source_busy_9$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_9$write_1__SEL_1: m_vrg_source_busy_9$D_IN = 1'd0;
MUX_m_vrg_source_busy_9$write_1__SEL_2: m_vrg_source_busy_9$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_9$D_IN = 1'd0;
default: m_vrg_source_busy_9$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_9$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd9 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd9 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_0
assign m_vrg_source_ip_0$D_IN = 1'd0 ;
assign m_vrg_source_ip_0$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd0 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_1
assign m_vrg_source_ip_1$D_IN =
!MUX_m_vrg_source_busy_1$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_0_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_1$EN =
!m_vrg_source_busy_1 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd1 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_10
assign m_vrg_source_ip_10$D_IN =
!MUX_m_vrg_source_busy_10$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_9_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_10$EN =
!m_vrg_source_busy_10 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd10 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_11
assign m_vrg_source_ip_11$D_IN =
!MUX_m_vrg_source_busy_11$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_10_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_11$EN =
!m_vrg_source_busy_11 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd11 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_12
assign m_vrg_source_ip_12$D_IN =
!MUX_m_vrg_source_busy_12$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_11_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_12$EN =
!m_vrg_source_busy_12 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd12 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_13
assign m_vrg_source_ip_13$D_IN =
!MUX_m_vrg_source_busy_13$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_12_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_13$EN =
!m_vrg_source_busy_13 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd13 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_14
assign m_vrg_source_ip_14$D_IN =
!MUX_m_vrg_source_busy_14$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_13_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_14$EN =
!m_vrg_source_busy_14 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd14 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_15
assign m_vrg_source_ip_15$D_IN =
!MUX_m_vrg_source_busy_15$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_14_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_15$EN =
!m_vrg_source_busy_15 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd15 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_16
assign m_vrg_source_ip_16$D_IN =
!MUX_m_vrg_source_busy_16$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_15_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_16$EN =
!m_vrg_source_busy_16 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd16 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_2
assign m_vrg_source_ip_2$D_IN =
!MUX_m_vrg_source_busy_2$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_1_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_2$EN =
!m_vrg_source_busy_2 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd2 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_3
assign m_vrg_source_ip_3$D_IN =
!MUX_m_vrg_source_busy_3$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_2_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_3$EN =
!m_vrg_source_busy_3 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd3 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_4
assign m_vrg_source_ip_4$D_IN =
!MUX_m_vrg_source_busy_4$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_3_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_4$EN =
!m_vrg_source_busy_4 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd4 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_5
assign m_vrg_source_ip_5$D_IN =
!MUX_m_vrg_source_busy_5$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_4_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_5$EN =
!m_vrg_source_busy_5 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd5 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_6
assign m_vrg_source_ip_6$D_IN =
!MUX_m_vrg_source_busy_6$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_5_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_6$EN =
!m_vrg_source_busy_6 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd6 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_7
assign m_vrg_source_ip_7$D_IN =
!MUX_m_vrg_source_busy_7$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_6_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_7$EN =
!m_vrg_source_busy_7 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd7 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_8
assign m_vrg_source_ip_8$D_IN =
!MUX_m_vrg_source_busy_8$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_7_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_8$EN =
!m_vrg_source_busy_8 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd8 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_9
assign m_vrg_source_ip_9$D_IN =
!MUX_m_vrg_source_busy_9$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_8_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_9$EN =
!m_vrg_source_busy_9 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd9 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_0
assign m_vrg_source_prio_0$D_IN =
MUX_m_vrg_source_prio_0$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_0$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
addr_offset__h27245[11:2] == 10'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d826 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_1
assign m_vrg_source_prio_1$D_IN =
MUX_m_vrg_source_prio_1$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_1$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d837 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_10
assign m_vrg_source_prio_10$D_IN =
MUX_m_vrg_source_prio_10$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_10$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d855 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_11
assign m_vrg_source_prio_11$D_IN =
MUX_m_vrg_source_prio_11$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_11$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d857 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_12
assign m_vrg_source_prio_12$D_IN =
MUX_m_vrg_source_prio_12$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_12$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d859 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_13
assign m_vrg_source_prio_13$D_IN =
MUX_m_vrg_source_prio_13$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_13$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d861 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_14
assign m_vrg_source_prio_14$D_IN =
MUX_m_vrg_source_prio_14$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_14$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d863 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_15
assign m_vrg_source_prio_15$D_IN =
MUX_m_vrg_source_prio_15$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_15$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d865 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_16
assign m_vrg_source_prio_16$D_IN =
MUX_m_vrg_source_prio_16$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_16$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d867 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_2
assign m_vrg_source_prio_2$D_IN =
MUX_m_vrg_source_prio_2$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_2$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d839 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_3
assign m_vrg_source_prio_3$D_IN =
MUX_m_vrg_source_prio_3$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_3$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d841 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_4
assign m_vrg_source_prio_4$D_IN =
MUX_m_vrg_source_prio_4$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_4$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d843 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_5
assign m_vrg_source_prio_5$D_IN =
MUX_m_vrg_source_prio_5$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_5$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d845 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_6
assign m_vrg_source_prio_6$D_IN =
MUX_m_vrg_source_prio_6$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_6$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d847 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_7
assign m_vrg_source_prio_7$D_IN =
MUX_m_vrg_source_prio_7$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_7$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d849 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_8
assign m_vrg_source_prio_8$D_IN =
MUX_m_vrg_source_prio_8$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_8$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d851 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_9
assign m_vrg_source_prio_9$D_IN =
MUX_m_vrg_source_prio_9$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_9$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d853 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_target_threshold_0
assign m_vrg_target_threshold_0$D_IN =
MUX_m_vrg_target_threshold_0$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd7 ;
assign m_vrg_target_threshold_0$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2860 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_target_threshold_1
assign m_vrg_target_threshold_1$D_IN =
MUX_m_vrg_target_threshold_1$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd7 ;
assign m_vrg_target_threshold_1$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2862 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_0
assign m_vvrg_ie_0_0$D_IN =
MUX_m_vvrg_ie_0_0$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_0$write_1__VAL_1 ;
assign m_vvrg_ie_0_0$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_1
assign m_vvrg_ie_0_1$D_IN =
MUX_m_vvrg_ie_0_1$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_1$write_1__VAL_1 ;
assign m_vvrg_ie_0_1$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_10
assign m_vvrg_ie_0_10$D_IN =
MUX_m_vvrg_ie_0_10$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_10$write_1__VAL_1 ;
assign m_vvrg_ie_0_10$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_11
assign m_vvrg_ie_0_11$D_IN =
MUX_m_vvrg_ie_0_11$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_11$write_1__VAL_1 ;
assign m_vvrg_ie_0_11$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_12
assign m_vvrg_ie_0_12$D_IN =
MUX_m_vvrg_ie_0_12$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_12$write_1__VAL_1 ;
assign m_vvrg_ie_0_12$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_13
assign m_vvrg_ie_0_13$D_IN =
MUX_m_vvrg_ie_0_13$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_13$write_1__VAL_1 ;
assign m_vvrg_ie_0_13$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_14
assign m_vvrg_ie_0_14$D_IN =
MUX_m_vvrg_ie_0_14$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_14$write_1__VAL_1 ;
assign m_vvrg_ie_0_14$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_15
assign m_vvrg_ie_0_15$D_IN =
MUX_m_vvrg_ie_0_15$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_15$write_1__VAL_1 ;
assign m_vvrg_ie_0_15$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_16
assign m_vvrg_ie_0_16$D_IN =
MUX_m_vvrg_ie_0_16$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_16$write_1__VAL_1 ;
assign m_vvrg_ie_0_16$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_2
assign m_vvrg_ie_0_2$D_IN =
MUX_m_vvrg_ie_0_2$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_2$write_1__VAL_1 ;
assign m_vvrg_ie_0_2$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_3
assign m_vvrg_ie_0_3$D_IN =
MUX_m_vvrg_ie_0_3$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_3$write_1__VAL_1 ;
assign m_vvrg_ie_0_3$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_4
assign m_vvrg_ie_0_4$D_IN =
MUX_m_vvrg_ie_0_4$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_4$write_1__VAL_1 ;
assign m_vvrg_ie_0_4$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_5
assign m_vvrg_ie_0_5$D_IN =
MUX_m_vvrg_ie_0_5$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_5$write_1__VAL_1 ;
assign m_vvrg_ie_0_5$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_6
assign m_vvrg_ie_0_6$D_IN =
MUX_m_vvrg_ie_0_6$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_6$write_1__VAL_1 ;
assign m_vvrg_ie_0_6$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_7
assign m_vvrg_ie_0_7$D_IN =
MUX_m_vvrg_ie_0_7$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_7$write_1__VAL_1 ;
assign m_vvrg_ie_0_7$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_8
assign m_vvrg_ie_0_8$D_IN =
MUX_m_vvrg_ie_0_8$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_8$write_1__VAL_1 ;
assign m_vvrg_ie_0_8$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_9
assign m_vvrg_ie_0_9$D_IN =
MUX_m_vvrg_ie_0_9$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_9$write_1__VAL_1 ;
assign m_vvrg_ie_0_9$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_0
assign m_vvrg_ie_1_0$D_IN =
MUX_m_vvrg_ie_1_0$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_0$write_1__VAL_1 ;
assign m_vvrg_ie_1_0$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_1
assign m_vvrg_ie_1_1$D_IN =
MUX_m_vvrg_ie_1_1$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_1$write_1__VAL_1 ;
assign m_vvrg_ie_1_1$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_10
assign m_vvrg_ie_1_10$D_IN =
MUX_m_vvrg_ie_1_10$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_10$write_1__VAL_1 ;
assign m_vvrg_ie_1_10$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_11
assign m_vvrg_ie_1_11$D_IN =
MUX_m_vvrg_ie_1_11$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_11$write_1__VAL_1 ;
assign m_vvrg_ie_1_11$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_12
assign m_vvrg_ie_1_12$D_IN =
MUX_m_vvrg_ie_1_12$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_12$write_1__VAL_1 ;
assign m_vvrg_ie_1_12$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_13
assign m_vvrg_ie_1_13$D_IN =
MUX_m_vvrg_ie_1_13$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_13$write_1__VAL_1 ;
assign m_vvrg_ie_1_13$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_14
assign m_vvrg_ie_1_14$D_IN =
MUX_m_vvrg_ie_1_14$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_14$write_1__VAL_1 ;
assign m_vvrg_ie_1_14$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_15
assign m_vvrg_ie_1_15$D_IN =
MUX_m_vvrg_ie_1_15$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_15$write_1__VAL_1 ;
assign m_vvrg_ie_1_15$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_16
assign m_vvrg_ie_1_16$D_IN =
MUX_m_vvrg_ie_1_16$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_16$write_1__VAL_1 ;
assign m_vvrg_ie_1_16$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_2
assign m_vvrg_ie_1_2$D_IN =
MUX_m_vvrg_ie_1_2$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_2$write_1__VAL_1 ;
assign m_vvrg_ie_1_2$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_3
assign m_vvrg_ie_1_3$D_IN =
MUX_m_vvrg_ie_1_3$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_3$write_1__VAL_1 ;
assign m_vvrg_ie_1_3$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_4
assign m_vvrg_ie_1_4$D_IN =
MUX_m_vvrg_ie_1_4$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_4$write_1__VAL_1 ;
assign m_vvrg_ie_1_4$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_5
assign m_vvrg_ie_1_5$D_IN =
MUX_m_vvrg_ie_1_5$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_5$write_1__VAL_1 ;
assign m_vvrg_ie_1_5$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_6
assign m_vvrg_ie_1_6$D_IN =
MUX_m_vvrg_ie_1_6$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_6$write_1__VAL_1 ;
assign m_vvrg_ie_1_6$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_7
assign m_vvrg_ie_1_7$D_IN =
MUX_m_vvrg_ie_1_7$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_7$write_1__VAL_1 ;
assign m_vvrg_ie_1_7$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_8
assign m_vvrg_ie_1_8$D_IN =
MUX_m_vvrg_ie_1_8$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_8$write_1__VAL_1 ;
assign m_vvrg_ie_1_8$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_9
assign m_vvrg_ie_1_9$D_IN =
MUX_m_vvrg_ie_1_9$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_9$write_1__VAL_1 ;
assign m_vvrg_ie_1_9$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ||
WILL_FIRE_RL_m_rl_reset ;
// submodule m_f_reset_reqs
assign m_f_reset_reqs$ENQ = EN_server_reset_request_put ;
assign m_f_reset_reqs$DEQ = CAN_FIRE_RL_m_rl_reset ;
assign m_f_reset_reqs$CLR = 1'b0 ;
// submodule m_f_reset_rsps
assign m_f_reset_rsps$ENQ = CAN_FIRE_RL_m_rl_reset ;
assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign m_f_reset_rsps$CLR = 1'b0 ;
// submodule m_slave_xactor_f_rd_addr
assign m_slave_xactor_f_rd_addr$D_IN =
{ axi4_slave_arid,
axi4_slave_araddr,
axi4_slave_arlen,
axi4_slave_arsize,
axi4_slave_arburst,
axi4_slave_arlock,
axi4_slave_arcache,
axi4_slave_arprot,
axi4_slave_arqos,
axi4_slave_arregion } ;
assign m_slave_xactor_f_rd_addr$ENQ =
axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ;
assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ;
assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ;
// submodule m_slave_xactor_f_rd_data
assign m_slave_xactor_f_rd_data$D_IN =
{ m_slave_xactor_f_rd_addr$D_OUT[96:93],
x__h26677,
rresp__h26521,
1'd1 } ;
assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ;
assign m_slave_xactor_f_rd_data$DEQ =
axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ;
assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ;
// submodule m_slave_xactor_f_wr_addr
assign m_slave_xactor_f_wr_addr$D_IN =
{ axi4_slave_awid,
axi4_slave_awaddr,
axi4_slave_awlen,
axi4_slave_awsize,
axi4_slave_awburst,
axi4_slave_awlock,
axi4_slave_awcache,
axi4_slave_awprot,
axi4_slave_awqos,
axi4_slave_awregion } ;
assign m_slave_xactor_f_wr_addr$ENQ =
axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ;
assign m_slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_m_rl_process_wr_req ;
assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ;
// submodule m_slave_xactor_f_wr_data
assign m_slave_xactor_f_wr_data$D_IN =
{ axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ;
assign m_slave_xactor_f_wr_data$ENQ =
axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ;
assign m_slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_m_rl_process_wr_req ;
assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ;
// submodule m_slave_xactor_f_wr_resp
assign m_slave_xactor_f_wr_resp$D_IN =
{ m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h27250 } ;
assign m_slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_m_rl_process_wr_req ;
assign m_slave_xactor_f_wr_resp$DEQ =
axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ;
assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ;
// remaining internal signals
assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d748 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ?
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ||
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 :
x__h23928 != 32'h00200000 && x__h23928 != 32'h00200004 ||
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ;
assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ?
addr_offset__h13465[11:2] == 10'd0 ||
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 :
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ?
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 :
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d748) ;
assign IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2874 =
wdata32__h27246[9:0] <= 10'd17 ;
assign IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2950 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 ?
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 ||
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 :
x__h76716 != 32'h00200000 && x__h76716 != 32'h00200004 ||
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 ;
assign IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 ?
addr_offset__h27245[11:2] == 10'd0 ||
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 :
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 ?
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 :
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2950) ;
assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3037 =
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3036 ?
m_vrg_source_prio_10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3032 ;
assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3131 =
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3130 ?
m_vrg_source_prio_10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3126 ;
assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 =
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ?
m_vrg_source_prio_10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3042 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3041 ?
m_vrg_source_prio_11 :
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3037 ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3078 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3041 ?
5'd11 :
(m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3036 ?
5'd10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3076) ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3136 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3135 ?
m_vrg_source_prio_11 :
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3131 ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3172 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3135 ?
5'd11 :
(m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3130 ?
5'd10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3170) ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ?
m_vrg_source_prio_11 :
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ?
5'd11 :
(m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ?
5'd10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ;
assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3047 =
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3046 ?
m_vrg_source_prio_12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3042 ;
assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3141 =
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3140 ?
m_vrg_source_prio_12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3136 ;
assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 =
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ?
m_vrg_source_prio_12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3052 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3051 ?
m_vrg_source_prio_13 :
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3047 ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3080 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3051 ?
5'd13 :
(m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3046 ?
5'd12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3078) ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3146 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3145 ?
m_vrg_source_prio_13 :
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3141 ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3174 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3145 ?
5'd13 :
(m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3140 ?
5'd12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3172) ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ?
m_vrg_source_prio_13 :
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ?
5'd13 :
(m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ?
5'd12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ;
assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3057 =
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3056 ?
m_vrg_source_prio_14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3052 ;
assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3151 =
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3150 ?
m_vrg_source_prio_14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3146 ;
assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 =
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ?
m_vrg_source_prio_14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ;
assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3062 =
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3061 ?
m_vrg_source_prio_15 :
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3057 ;
assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3082 =
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3061 ?
5'd15 :
(m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3056 ?
5'd14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3080) ;
assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3156 =
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3155 ?
m_vrg_source_prio_15 :
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3151 ;
assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3176 =
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3155 ?
5'd15 :
(m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3150 ?
5'd14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3174) ;
assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 =
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ?
5'd15 :
(m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ?
5'd14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ;
assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d2992 =
(m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 &&
m_vvrg_ie_0_1) ?
m_vrg_source_prio_1 :
3'd0 ;
assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3086 =
(m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 &&
m_vvrg_ie_1_1) ?
m_vrg_source_prio_1 :
3'd0 ;
assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 =
m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ?
m_vrg_source_prio_1 :
3'd0 ;
assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d2997 =
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d2996 ?
m_vrg_source_prio_2 :
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d2992 ;
assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3091 =
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3090 ?
m_vrg_source_prio_2 :
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3086 ;
assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 =
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ?
m_vrg_source_prio_2 :
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3002 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3001 ?
m_vrg_source_prio_3 :
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d2997 ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3070 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3001 ?
5'd3 :
(m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d2996 ?
5'd2 :
((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 &&
m_vvrg_ie_0_1) ?
5'd1 :
5'd0)) ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3096 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3095 ?
m_vrg_source_prio_3 :
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3091 ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3164 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3095 ?
5'd3 :
(m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3090 ?
5'd2 :
((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 &&
m_vvrg_ie_1_1) ?
5'd1 :
5'd0)) ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ?
m_vrg_source_prio_3 :
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ?
5'd3 :
(m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ?
5'd2 :
(m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ?
5'd1 :
5'd0)) ;
assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3007 =
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3006 ?
m_vrg_source_prio_4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3002 ;
assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3101 =
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3100 ?
m_vrg_source_prio_4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3096 ;
assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 =
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ?
m_vrg_source_prio_4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3012 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3011 ?
m_vrg_source_prio_5 :
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3007 ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3072 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3011 ?
5'd5 :
(m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3006 ?
5'd4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3070) ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3106 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3105 ?
m_vrg_source_prio_5 :
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3101 ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3166 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3105 ?
5'd5 :
(m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3100 ?
5'd4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3164) ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ?
m_vrg_source_prio_5 :
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ?
5'd5 :
(m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ?
5'd4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ;
assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3017 =
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3016 ?
m_vrg_source_prio_6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3012 ;
assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3111 =
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3110 ?
m_vrg_source_prio_6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3106 ;
assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 =
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ?
m_vrg_source_prio_6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3022 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3021 ?
m_vrg_source_prio_7 :
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3017 ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3074 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3021 ?
5'd7 :
(m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3016 ?
5'd6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3072) ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3116 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3115 ?
m_vrg_source_prio_7 :
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3111 ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3168 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3115 ?
5'd7 :
(m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3110 ?
5'd6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3166) ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ?
m_vrg_source_prio_7 :
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ?
5'd7 :
(m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ?
5'd6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ;
assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3027 =
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3026 ?
m_vrg_source_prio_8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3022 ;
assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3121 =
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3120 ?
m_vrg_source_prio_8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3116 ;
assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 =
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ?
m_vrg_source_prio_8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3032 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3031 ?
m_vrg_source_prio_9 :
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3027 ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3076 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3031 ?
5'd9 :
(m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3026 ?
5'd8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3074) ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3126 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3125 ?
m_vrg_source_prio_9 :
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3121 ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3170 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3125 ?
5'd9 :
(m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3120 ?
5'd8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3168) ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ?
m_vrg_source_prio_9 :
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ?
5'd9 :
(m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ?
5'd8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ;
assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ;
assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 =
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 =
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 &&
x__h23928 == 32'h00200000 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 =
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 &&
x__h23928 == 32'h00200004 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 &&
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d689 ;
assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d733 =
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 &&
x__h23928 == 32'h00200004 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 =
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h31729 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h33225 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h34721 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h36217 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h37713 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h39209 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h40705 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h42201 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h43697 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h45193 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h46689 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h48185 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h49681 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h51177 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h52673 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h54169 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h55665 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h57161 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h58657 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h60153 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h61649 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h63145 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h64641 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h66137 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h67633 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h69129 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h70625 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h72121 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h73617 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h75113 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2844 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2857 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
x__h76716 == 32'h00200000 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2868 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
x__h76716 == 32'h00200000 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
x__h76716 == 32'h00200004 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 &&
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2874 &&
SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2923 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
x__h76716 == 32'h00200004 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 &&
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2874 &&
SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2935 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
x__h76716 == 32'h00200004 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 &&
(!IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2874 ||
!SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878) &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d826 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
addr_offset__h27245[11:2] != 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d880 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d892 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h30233 <= 10'd16 ;
assign NOT_m_vrg_source_busy_10_983_284_AND_NOT_m_cfg_ETC___d3288 =
!m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_11_984_292_AND_NOT_m_cfg_ETC___d3296 =
!m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_11 !=
v_sources_10_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_12_985_300_AND_NOT_m_cfg_ETC___d3304 =
!m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_12 !=
v_sources_11_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_13_986_308_AND_NOT_m_cfg_ETC___d3312 =
!m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_13 !=
v_sources_12_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_14_987_316_AND_NOT_m_cfg_ETC___d3320 =
!m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_14 !=
v_sources_13_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_15_988_324_AND_NOT_m_cfg_ETC___d3328 =
!m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_15 !=
v_sources_14_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_16_989_332_AND_NOT_m_cfg_ETC___d3336 =
!m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_16 !=
v_sources_15_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_1_974_213_AND_NOT_m_cfg__ETC___d3217 =
!m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_2_975_220_AND_NOT_m_cfg__ETC___d3224 =
!m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_3_976_228_AND_NOT_m_cfg__ETC___d3232 =
!m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_4_977_236_AND_NOT_m_cfg__ETC___d3240 =
!m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_5_978_244_AND_NOT_m_cfg__ETC___d3248 =
!m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_6_979_252_AND_NOT_m_cfg__ETC___d3256 =
!m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_7_980_260_AND_NOT_m_cfg__ETC___d3264 =
!m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_8_981_268_AND_NOT_m_cfg__ETC___d3272 =
!m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_9_982_276_AND_NOT_m_cfg__ETC___d3280 =
!m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ;
assign _dfoo1 =
source_id__h73617 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo10 =
(source_id__h73617 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo100 =
(source_id__h72121 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo32 ;
assign _dfoo1000 =
(source_id__h52673 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo932 ;
assign _dfoo1001 =
source_id__h52673 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo865 ;
assign _dfoo1002 =
(source_id__h52673 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo934 ;
assign _dfoo1003 =
source_id__h52673 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo867 ;
assign _dfoo1004 =
(source_id__h52673 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo936 ;
assign _dfoo1005 =
source_id__h52673 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo869 ;
assign _dfoo1006 =
(source_id__h52673 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo938 ;
assign _dfoo1007 =
source_id__h52673 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo871 ;
assign _dfoo1008 =
(source_id__h52673 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo940 ;
assign _dfoo1009 =
source_id__h52673 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo873 ;
assign _dfoo1010 =
(source_id__h52673 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo942 ;
assign _dfoo1011 =
source_id__h52673 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo875 ;
assign _dfoo1012 =
(source_id__h52673 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo944 ;
assign _dfoo1013 =
source_id__h52673 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo877 ;
assign _dfoo1014 =
(source_id__h52673 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo946 ;
assign _dfoo1015 =
source_id__h52673 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo879 ;
assign _dfoo1016 =
(source_id__h52673 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo948 ;
assign _dfoo1017 =
source_id__h52673 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo881 ;
assign _dfoo1018 =
(source_id__h52673 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo950 ;
assign _dfoo1019 =
source_id__h52673 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo883 ;
assign _dfoo102 =
(source_id__h72121 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo34 ;
assign _dfoo1020 =
(source_id__h52673 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo952 ;
assign _dfoo1022 =
(source_id__h51177 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo954 ;
assign _dfoo1024 =
(source_id__h51177 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo956 ;
assign _dfoo1026 =
(source_id__h51177 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo958 ;
assign _dfoo1028 =
(source_id__h51177 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo960 ;
assign _dfoo1030 =
(source_id__h51177 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo962 ;
assign _dfoo1032 =
(source_id__h51177 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo964 ;
assign _dfoo1034 =
(source_id__h51177 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo966 ;
assign _dfoo1036 =
(source_id__h51177 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo968 ;
assign _dfoo1038 =
(source_id__h51177 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo970 ;
assign _dfoo104 =
(source_id__h72121 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo36 ;
assign _dfoo1040 =
(source_id__h51177 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo972 ;
assign _dfoo1042 =
(source_id__h51177 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo974 ;
assign _dfoo1044 =
(source_id__h51177 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo976 ;
assign _dfoo1046 =
(source_id__h51177 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo978 ;
assign _dfoo1048 =
(source_id__h51177 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo980 ;
assign _dfoo1050 =
(source_id__h51177 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo982 ;
assign _dfoo1052 =
(source_id__h51177 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo984 ;
assign _dfoo1054 =
(source_id__h51177 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo986 ;
assign _dfoo1056 =
(source_id__h51177 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo988 ;
assign _dfoo1058 =
(source_id__h51177 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo990 ;
assign _dfoo106 =
(source_id__h72121 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo38 ;
assign _dfoo1060 =
(source_id__h51177 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo992 ;
assign _dfoo1062 =
(source_id__h51177 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo994 ;
assign _dfoo1064 =
(source_id__h51177 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo996 ;
assign _dfoo1066 =
(source_id__h51177 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo998 ;
assign _dfoo1068 =
(source_id__h51177 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1000 ;
assign _dfoo1070 =
(source_id__h51177 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1002 ;
assign _dfoo1072 =
(source_id__h51177 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1004 ;
assign _dfoo1074 =
(source_id__h51177 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1006 ;
assign _dfoo1076 =
(source_id__h51177 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1008 ;
assign _dfoo1078 =
(source_id__h51177 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1010 ;
assign _dfoo108 =
(source_id__h72121 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo40 ;
assign _dfoo1080 =
(source_id__h51177 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1012 ;
assign _dfoo1082 =
(source_id__h51177 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1014 ;
assign _dfoo1084 =
(source_id__h51177 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1016 ;
assign _dfoo1086 =
(source_id__h51177 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1018 ;
assign _dfoo1088 =
(source_id__h51177 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1020 ;
assign _dfoo1089 =
source_id__h49681 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo953 ;
assign _dfoo1090 =
(source_id__h49681 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1022 ;
assign _dfoo1091 =
source_id__h49681 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo955 ;
assign _dfoo1092 =
(source_id__h49681 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1024 ;
assign _dfoo1093 =
source_id__h49681 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo957 ;
assign _dfoo1094 =
(source_id__h49681 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1026 ;
assign _dfoo1095 =
source_id__h49681 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo959 ;
assign _dfoo1096 =
(source_id__h49681 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1028 ;
assign _dfoo1097 =
source_id__h49681 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo961 ;
assign _dfoo1098 =
(source_id__h49681 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1030 ;
assign _dfoo1099 =
source_id__h49681 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo963 ;
assign _dfoo11 =
source_id__h73617 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo110 =
(source_id__h72121 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo42 ;
assign _dfoo1100 =
(source_id__h49681 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1032 ;
assign _dfoo1101 =
source_id__h49681 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo965 ;
assign _dfoo1102 =
(source_id__h49681 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1034 ;
assign _dfoo1103 =
source_id__h49681 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo967 ;
assign _dfoo1104 =
(source_id__h49681 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1036 ;
assign _dfoo1105 =
source_id__h49681 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo969 ;
assign _dfoo1106 =
(source_id__h49681 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1038 ;
assign _dfoo1107 =
source_id__h49681 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo971 ;
assign _dfoo1108 =
(source_id__h49681 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1040 ;
assign _dfoo1109 =
source_id__h49681 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo973 ;
assign _dfoo1110 =
(source_id__h49681 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1042 ;
assign _dfoo1111 =
source_id__h49681 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo975 ;
assign _dfoo1112 =
(source_id__h49681 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1044 ;
assign _dfoo1113 =
source_id__h49681 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo977 ;
assign _dfoo1114 =
(source_id__h49681 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1046 ;
assign _dfoo1115 =
source_id__h49681 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo979 ;
assign _dfoo1116 =
(source_id__h49681 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1048 ;
assign _dfoo1117 =
source_id__h49681 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo981 ;
assign _dfoo1118 =
(source_id__h49681 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1050 ;
assign _dfoo1119 =
source_id__h49681 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo983 ;
assign _dfoo112 =
(source_id__h72121 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo44 ;
assign _dfoo1120 =
(source_id__h49681 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1052 ;
assign _dfoo1121 =
source_id__h49681 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo985 ;
assign _dfoo1122 =
(source_id__h49681 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1054 ;
assign _dfoo1123 =
source_id__h49681 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo987 ;
assign _dfoo1124 =
(source_id__h49681 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1056 ;
assign _dfoo1125 =
source_id__h49681 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo989 ;
assign _dfoo1126 =
(source_id__h49681 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1058 ;
assign _dfoo1127 =
source_id__h49681 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo991 ;
assign _dfoo1128 =
(source_id__h49681 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1060 ;
assign _dfoo1129 =
source_id__h49681 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo993 ;
assign _dfoo1130 =
(source_id__h49681 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1062 ;
assign _dfoo1131 =
source_id__h49681 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo995 ;
assign _dfoo1132 =
(source_id__h49681 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1064 ;
assign _dfoo1133 =
source_id__h49681 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo997 ;
assign _dfoo1134 =
(source_id__h49681 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1066 ;
assign _dfoo1135 =
source_id__h49681 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo999 ;
assign _dfoo1136 =
(source_id__h49681 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1068 ;
assign _dfoo1137 =
source_id__h49681 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1001 ;
assign _dfoo1138 =
(source_id__h49681 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1070 ;
assign _dfoo1139 =
source_id__h49681 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1003 ;
assign _dfoo114 =
(source_id__h72121 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo46 ;
assign _dfoo1140 =
(source_id__h49681 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1072 ;
assign _dfoo1141 =
source_id__h49681 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1005 ;
assign _dfoo1142 =
(source_id__h49681 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1074 ;
assign _dfoo1143 =
source_id__h49681 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1007 ;
assign _dfoo1144 =
(source_id__h49681 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1076 ;
assign _dfoo1145 =
source_id__h49681 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1009 ;
assign _dfoo1146 =
(source_id__h49681 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1078 ;
assign _dfoo1147 =
source_id__h49681 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1011 ;
assign _dfoo1148 =
(source_id__h49681 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1080 ;
assign _dfoo1149 =
source_id__h49681 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1013 ;
assign _dfoo1150 =
(source_id__h49681 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1082 ;
assign _dfoo1151 =
source_id__h49681 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1015 ;
assign _dfoo1152 =
(source_id__h49681 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1084 ;
assign _dfoo1153 =
source_id__h49681 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1017 ;
assign _dfoo1154 =
(source_id__h49681 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1086 ;
assign _dfoo1155 =
source_id__h49681 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1019 ;
assign _dfoo1156 =
(source_id__h49681 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1088 ;
assign _dfoo1158 =
(source_id__h48185 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1090 ;
assign _dfoo116 =
(source_id__h72121 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo48 ;
assign _dfoo1160 =
(source_id__h48185 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1092 ;
assign _dfoo1162 =
(source_id__h48185 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1094 ;
assign _dfoo1164 =
(source_id__h48185 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1096 ;
assign _dfoo1166 =
(source_id__h48185 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1098 ;
assign _dfoo1168 =
(source_id__h48185 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1100 ;
assign _dfoo1170 =
(source_id__h48185 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1102 ;
assign _dfoo1172 =
(source_id__h48185 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1104 ;
assign _dfoo1174 =
(source_id__h48185 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1106 ;
assign _dfoo1176 =
(source_id__h48185 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1108 ;
assign _dfoo1178 =
(source_id__h48185 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1110 ;
assign _dfoo118 =
(source_id__h72121 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo50 ;
assign _dfoo1180 =
(source_id__h48185 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1112 ;
assign _dfoo1182 =
(source_id__h48185 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1114 ;
assign _dfoo1184 =
(source_id__h48185 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1116 ;
assign _dfoo1186 =
(source_id__h48185 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1118 ;
assign _dfoo1188 =
(source_id__h48185 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1120 ;
assign _dfoo1190 =
(source_id__h48185 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1122 ;
assign _dfoo1192 =
(source_id__h48185 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1124 ;
assign _dfoo1194 =
(source_id__h48185 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1126 ;
assign _dfoo1196 =
(source_id__h48185 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1128 ;
assign _dfoo1198 =
(source_id__h48185 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1130 ;
assign _dfoo12 =
(source_id__h73617 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo120 =
(source_id__h72121 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo52 ;
assign _dfoo1200 =
(source_id__h48185 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1132 ;
assign _dfoo1202 =
(source_id__h48185 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1134 ;
assign _dfoo1204 =
(source_id__h48185 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1136 ;
assign _dfoo1206 =
(source_id__h48185 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1138 ;
assign _dfoo1208 =
(source_id__h48185 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1140 ;
assign _dfoo1210 =
(source_id__h48185 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1142 ;
assign _dfoo1212 =
(source_id__h48185 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1144 ;
assign _dfoo1214 =
(source_id__h48185 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1146 ;
assign _dfoo1216 =
(source_id__h48185 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1148 ;
assign _dfoo1218 =
(source_id__h48185 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1150 ;
assign _dfoo122 =
(source_id__h72121 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo54 ;
assign _dfoo1220 =
(source_id__h48185 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1152 ;
assign _dfoo1222 =
(source_id__h48185 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1154 ;
assign _dfoo1224 =
(source_id__h48185 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1156 ;
assign _dfoo1225 =
source_id__h46689 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1089 ;
assign _dfoo1226 =
(source_id__h46689 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1158 ;
assign _dfoo1227 =
source_id__h46689 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1091 ;
assign _dfoo1228 =
(source_id__h46689 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1160 ;
assign _dfoo1229 =
source_id__h46689 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1093 ;
assign _dfoo1230 =
(source_id__h46689 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1162 ;
assign _dfoo1231 =
source_id__h46689 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1095 ;
assign _dfoo1232 =
(source_id__h46689 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1164 ;
assign _dfoo1233 =
source_id__h46689 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1097 ;
assign _dfoo1234 =
(source_id__h46689 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1166 ;
assign _dfoo1235 =
source_id__h46689 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1099 ;
assign _dfoo1236 =
(source_id__h46689 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1168 ;
assign _dfoo1237 =
source_id__h46689 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1101 ;
assign _dfoo1238 =
(source_id__h46689 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1170 ;
assign _dfoo1239 =
source_id__h46689 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1103 ;
assign _dfoo124 =
(source_id__h72121 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo56 ;
assign _dfoo1240 =
(source_id__h46689 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1172 ;
assign _dfoo1241 =
source_id__h46689 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1105 ;
assign _dfoo1242 =
(source_id__h46689 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1174 ;
assign _dfoo1243 =
source_id__h46689 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1107 ;
assign _dfoo1244 =
(source_id__h46689 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1176 ;
assign _dfoo1245 =
source_id__h46689 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1109 ;
assign _dfoo1246 =
(source_id__h46689 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1178 ;
assign _dfoo1247 =
source_id__h46689 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1111 ;
assign _dfoo1248 =
(source_id__h46689 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1180 ;
assign _dfoo1249 =
source_id__h46689 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1113 ;
assign _dfoo1250 =
(source_id__h46689 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1182 ;
assign _dfoo1251 =
source_id__h46689 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1115 ;
assign _dfoo1252 =
(source_id__h46689 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1184 ;
assign _dfoo1253 =
source_id__h46689 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1117 ;
assign _dfoo1254 =
(source_id__h46689 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1186 ;
assign _dfoo1255 =
source_id__h46689 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1119 ;
assign _dfoo1256 =
(source_id__h46689 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1188 ;
assign _dfoo1257 =
source_id__h46689 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1121 ;
assign _dfoo1258 =
(source_id__h46689 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1190 ;
assign _dfoo1259 =
source_id__h46689 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1123 ;
assign _dfoo126 =
(source_id__h72121 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo58 ;
assign _dfoo1260 =
(source_id__h46689 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1192 ;
assign _dfoo1261 =
source_id__h46689 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1125 ;
assign _dfoo1262 =
(source_id__h46689 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1194 ;
assign _dfoo1263 =
source_id__h46689 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1127 ;
assign _dfoo1264 =
(source_id__h46689 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1196 ;
assign _dfoo1265 =
source_id__h46689 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1129 ;
assign _dfoo1266 =
(source_id__h46689 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1198 ;
assign _dfoo1267 =
source_id__h46689 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1131 ;
assign _dfoo1268 =
(source_id__h46689 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1200 ;
assign _dfoo1269 =
source_id__h46689 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1133 ;
assign _dfoo1270 =
(source_id__h46689 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1202 ;
assign _dfoo1271 =
source_id__h46689 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1135 ;
assign _dfoo1272 =
(source_id__h46689 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1204 ;
assign _dfoo1273 =
source_id__h46689 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1137 ;
assign _dfoo1274 =
(source_id__h46689 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1206 ;
assign _dfoo1275 =
source_id__h46689 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1139 ;
assign _dfoo1276 =
(source_id__h46689 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1208 ;
assign _dfoo1277 =
source_id__h46689 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1141 ;
assign _dfoo1278 =
(source_id__h46689 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1210 ;
assign _dfoo1279 =
source_id__h46689 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1143 ;
assign _dfoo128 =
(source_id__h72121 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo60 ;
assign _dfoo1280 =
(source_id__h46689 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1212 ;
assign _dfoo1281 =
source_id__h46689 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1145 ;
assign _dfoo1282 =
(source_id__h46689 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1214 ;
assign _dfoo1283 =
source_id__h46689 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1147 ;
assign _dfoo1284 =
(source_id__h46689 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1216 ;
assign _dfoo1285 =
source_id__h46689 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1149 ;
assign _dfoo1286 =
(source_id__h46689 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1218 ;
assign _dfoo1287 =
source_id__h46689 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1151 ;
assign _dfoo1288 =
(source_id__h46689 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1220 ;
assign _dfoo1289 =
source_id__h46689 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1153 ;
assign _dfoo1290 =
(source_id__h46689 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1222 ;
assign _dfoo1291 =
source_id__h46689 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1155 ;
assign _dfoo1292 =
(source_id__h46689 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1224 ;
assign _dfoo1294 =
(source_id__h45193 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1226 ;
assign _dfoo1296 =
(source_id__h45193 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1228 ;
assign _dfoo1298 =
(source_id__h45193 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1230 ;
assign _dfoo13 =
source_id__h73617 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo130 =
(source_id__h72121 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo62 ;
assign _dfoo1300 =
(source_id__h45193 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1232 ;
assign _dfoo1302 =
(source_id__h45193 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1234 ;
assign _dfoo1304 =
(source_id__h45193 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1236 ;
assign _dfoo1306 =
(source_id__h45193 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1238 ;
assign _dfoo1308 =
(source_id__h45193 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1240 ;
assign _dfoo1310 =
(source_id__h45193 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1242 ;
assign _dfoo1312 =
(source_id__h45193 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1244 ;
assign _dfoo1314 =
(source_id__h45193 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1246 ;
assign _dfoo1316 =
(source_id__h45193 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1248 ;
assign _dfoo1318 =
(source_id__h45193 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1250 ;
assign _dfoo132 =
(source_id__h72121 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo64 ;
assign _dfoo1320 =
(source_id__h45193 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1252 ;
assign _dfoo1322 =
(source_id__h45193 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1254 ;
assign _dfoo1324 =
(source_id__h45193 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1256 ;
assign _dfoo1326 =
(source_id__h45193 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1258 ;
assign _dfoo1328 =
(source_id__h45193 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1260 ;
assign _dfoo1330 =
(source_id__h45193 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1262 ;
assign _dfoo1332 =
(source_id__h45193 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1264 ;
assign _dfoo1334 =
(source_id__h45193 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1266 ;
assign _dfoo1336 =
(source_id__h45193 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1268 ;
assign _dfoo1338 =
(source_id__h45193 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1270 ;
assign _dfoo134 =
(source_id__h72121 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo66 ;
assign _dfoo1340 =
(source_id__h45193 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1272 ;
assign _dfoo1342 =
(source_id__h45193 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1274 ;
assign _dfoo1344 =
(source_id__h45193 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1276 ;
assign _dfoo1346 =
(source_id__h45193 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1278 ;
assign _dfoo1348 =
(source_id__h45193 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1280 ;
assign _dfoo1350 =
(source_id__h45193 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1282 ;
assign _dfoo1352 =
(source_id__h45193 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1284 ;
assign _dfoo1354 =
(source_id__h45193 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1286 ;
assign _dfoo1356 =
(source_id__h45193 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1288 ;
assign _dfoo1358 =
(source_id__h45193 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1290 ;
assign _dfoo136 =
(source_id__h72121 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo68 ;
assign _dfoo1360 =
(source_id__h45193 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1292 ;
assign _dfoo1361 =
source_id__h43697 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1225 ;
assign _dfoo1362 =
(source_id__h43697 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1294 ;
assign _dfoo1363 =
source_id__h43697 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1227 ;
assign _dfoo1364 =
(source_id__h43697 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1296 ;
assign _dfoo1365 =
source_id__h43697 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1229 ;
assign _dfoo1366 =
(source_id__h43697 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1298 ;
assign _dfoo1367 =
source_id__h43697 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1231 ;
assign _dfoo1368 =
(source_id__h43697 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1300 ;
assign _dfoo1369 =
source_id__h43697 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1233 ;
assign _dfoo137 =
source_id__h70625 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo1 ;
assign _dfoo1370 =
(source_id__h43697 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1302 ;
assign _dfoo1371 =
source_id__h43697 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1235 ;
assign _dfoo1372 =
(source_id__h43697 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1304 ;
assign _dfoo1373 =
source_id__h43697 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1237 ;
assign _dfoo1374 =
(source_id__h43697 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1306 ;
assign _dfoo1375 =
source_id__h43697 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1239 ;
assign _dfoo1376 =
(source_id__h43697 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1308 ;
assign _dfoo1377 =
source_id__h43697 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1241 ;
assign _dfoo1378 =
(source_id__h43697 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1310 ;
assign _dfoo1379 =
source_id__h43697 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1243 ;
assign _dfoo138 =
(source_id__h70625 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo70 ;
assign _dfoo1380 =
(source_id__h43697 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1312 ;
assign _dfoo1381 =
source_id__h43697 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1245 ;
assign _dfoo1382 =
(source_id__h43697 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1314 ;
assign _dfoo1383 =
source_id__h43697 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1247 ;
assign _dfoo1384 =
(source_id__h43697 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1316 ;
assign _dfoo1385 =
source_id__h43697 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1249 ;
assign _dfoo1386 =
(source_id__h43697 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1318 ;
assign _dfoo1387 =
source_id__h43697 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1251 ;
assign _dfoo1388 =
(source_id__h43697 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1320 ;
assign _dfoo1389 =
source_id__h43697 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1253 ;
assign _dfoo139 =
source_id__h70625 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo3 ;
assign _dfoo1390 =
(source_id__h43697 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1322 ;
assign _dfoo1391 =
source_id__h43697 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1255 ;
assign _dfoo1392 =
(source_id__h43697 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1324 ;
assign _dfoo1393 =
source_id__h43697 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1257 ;
assign _dfoo1394 =
(source_id__h43697 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1326 ;
assign _dfoo1395 =
source_id__h43697 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1259 ;
assign _dfoo1396 =
(source_id__h43697 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1328 ;
assign _dfoo1397 =
source_id__h43697 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1261 ;
assign _dfoo1398 =
(source_id__h43697 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1330 ;
assign _dfoo1399 =
source_id__h43697 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1263 ;
assign _dfoo14 =
(source_id__h73617 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo140 =
(source_id__h70625 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo72 ;
assign _dfoo1400 =
(source_id__h43697 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1332 ;
assign _dfoo1401 =
source_id__h43697 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1265 ;
assign _dfoo1402 =
(source_id__h43697 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1334 ;
assign _dfoo1403 =
source_id__h43697 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1267 ;
assign _dfoo1404 =
(source_id__h43697 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1336 ;
assign _dfoo1405 =
source_id__h43697 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1269 ;
assign _dfoo1406 =
(source_id__h43697 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1338 ;
assign _dfoo1407 =
source_id__h43697 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1271 ;
assign _dfoo1408 =
(source_id__h43697 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1340 ;
assign _dfoo1409 =
source_id__h43697 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1273 ;
assign _dfoo141 =
source_id__h70625 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo5 ;
assign _dfoo1410 =
(source_id__h43697 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1342 ;
assign _dfoo1411 =
source_id__h43697 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1275 ;
assign _dfoo1412 =
(source_id__h43697 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1344 ;
assign _dfoo1413 =
source_id__h43697 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1277 ;
assign _dfoo1414 =
(source_id__h43697 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1346 ;
assign _dfoo1415 =
source_id__h43697 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1279 ;
assign _dfoo1416 =
(source_id__h43697 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1348 ;
assign _dfoo1417 =
source_id__h43697 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1281 ;
assign _dfoo1418 =
(source_id__h43697 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1350 ;
assign _dfoo1419 =
source_id__h43697 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1283 ;
assign _dfoo142 =
(source_id__h70625 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo74 ;
assign _dfoo1420 =
(source_id__h43697 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1352 ;
assign _dfoo1421 =
source_id__h43697 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1285 ;
assign _dfoo1422 =
(source_id__h43697 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1354 ;
assign _dfoo1423 =
source_id__h43697 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1287 ;
assign _dfoo1424 =
(source_id__h43697 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1356 ;
assign _dfoo1425 =
source_id__h43697 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1289 ;
assign _dfoo1426 =
(source_id__h43697 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1358 ;
assign _dfoo1427 =
source_id__h43697 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1291 ;
assign _dfoo1428 =
(source_id__h43697 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1360 ;
assign _dfoo143 =
source_id__h70625 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo7 ;
assign _dfoo1430 =
(source_id__h42201 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1362 ;
assign _dfoo1432 =
(source_id__h42201 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1364 ;
assign _dfoo1434 =
(source_id__h42201 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1366 ;
assign _dfoo1436 =
(source_id__h42201 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1368 ;
assign _dfoo1438 =
(source_id__h42201 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1370 ;
assign _dfoo144 =
(source_id__h70625 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo76 ;
assign _dfoo1440 =
(source_id__h42201 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1372 ;
assign _dfoo1442 =
(source_id__h42201 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1374 ;
assign _dfoo1444 =
(source_id__h42201 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1376 ;
assign _dfoo1446 =
(source_id__h42201 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1378 ;
assign _dfoo1448 =
(source_id__h42201 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1380 ;
assign _dfoo145 =
source_id__h70625 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo9 ;
assign _dfoo1450 =
(source_id__h42201 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1382 ;
assign _dfoo1452 =
(source_id__h42201 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1384 ;
assign _dfoo1454 =
(source_id__h42201 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1386 ;
assign _dfoo1456 =
(source_id__h42201 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1388 ;
assign _dfoo1458 =
(source_id__h42201 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1390 ;
assign _dfoo146 =
(source_id__h70625 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo78 ;
assign _dfoo1460 =
(source_id__h42201 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1392 ;
assign _dfoo1462 =
(source_id__h42201 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1394 ;
assign _dfoo1464 =
(source_id__h42201 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1396 ;
assign _dfoo1466 =
(source_id__h42201 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1398 ;
assign _dfoo1468 =
(source_id__h42201 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1400 ;
assign _dfoo147 =
source_id__h70625 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo11 ;
assign _dfoo1470 =
(source_id__h42201 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1402 ;
assign _dfoo1472 =
(source_id__h42201 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1404 ;
assign _dfoo1474 =
(source_id__h42201 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1406 ;
assign _dfoo1476 =
(source_id__h42201 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1408 ;
assign _dfoo1478 =
(source_id__h42201 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1410 ;
assign _dfoo148 =
(source_id__h70625 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo80 ;
assign _dfoo1480 =
(source_id__h42201 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1412 ;
assign _dfoo1482 =
(source_id__h42201 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1414 ;
assign _dfoo1484 =
(source_id__h42201 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1416 ;
assign _dfoo1486 =
(source_id__h42201 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1418 ;
assign _dfoo1488 =
(source_id__h42201 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1420 ;
assign _dfoo149 =
source_id__h70625 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo13 ;
assign _dfoo1490 =
(source_id__h42201 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1422 ;
assign _dfoo1492 =
(source_id__h42201 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1424 ;
assign _dfoo1494 =
(source_id__h42201 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1426 ;
assign _dfoo1496 =
(source_id__h42201 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1428 ;
assign _dfoo1497 =
source_id__h40705 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1361 ;
assign _dfoo1498 =
(source_id__h40705 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1430 ;
assign _dfoo1499 =
source_id__h40705 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1363 ;
assign _dfoo15 =
source_id__h73617 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo150 =
(source_id__h70625 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo82 ;
assign _dfoo1500 =
(source_id__h40705 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1432 ;
assign _dfoo1501 =
source_id__h40705 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1365 ;
assign _dfoo1502 =
(source_id__h40705 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1434 ;
assign _dfoo1503 =
source_id__h40705 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1367 ;
assign _dfoo1504 =
(source_id__h40705 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1436 ;
assign _dfoo1505 =
source_id__h40705 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1369 ;
assign _dfoo1506 =
(source_id__h40705 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1438 ;
assign _dfoo1507 =
source_id__h40705 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1371 ;
assign _dfoo1508 =
(source_id__h40705 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1440 ;
assign _dfoo1509 =
source_id__h40705 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1373 ;
assign _dfoo151 =
source_id__h70625 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo15 ;
assign _dfoo1510 =
(source_id__h40705 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1442 ;
assign _dfoo1511 =
source_id__h40705 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1375 ;
assign _dfoo1512 =
(source_id__h40705 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1444 ;
assign _dfoo1513 =
source_id__h40705 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1377 ;
assign _dfoo1514 =
(source_id__h40705 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1446 ;
assign _dfoo1515 =
source_id__h40705 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1379 ;
assign _dfoo1516 =
(source_id__h40705 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1448 ;
assign _dfoo1517 =
source_id__h40705 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1381 ;
assign _dfoo1518 =
(source_id__h40705 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1450 ;
assign _dfoo1519 =
source_id__h40705 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1383 ;
assign _dfoo152 =
(source_id__h70625 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo84 ;
assign _dfoo1520 =
(source_id__h40705 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1452 ;
assign _dfoo1521 =
source_id__h40705 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1385 ;
assign _dfoo1522 =
(source_id__h40705 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1454 ;
assign _dfoo1523 =
source_id__h40705 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1387 ;
assign _dfoo1524 =
(source_id__h40705 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1456 ;
assign _dfoo1525 =
source_id__h40705 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1389 ;
assign _dfoo1526 =
(source_id__h40705 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1458 ;
assign _dfoo1527 =
source_id__h40705 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1391 ;
assign _dfoo1528 =
(source_id__h40705 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1460 ;
assign _dfoo1529 =
source_id__h40705 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1393 ;
assign _dfoo153 =
source_id__h70625 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo17 ;
assign _dfoo1530 =
(source_id__h40705 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1462 ;
assign _dfoo1531 =
source_id__h40705 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1395 ;
assign _dfoo1532 =
(source_id__h40705 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1464 ;
assign _dfoo1533 =
source_id__h40705 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1397 ;
assign _dfoo1534 =
(source_id__h40705 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1466 ;
assign _dfoo1535 =
source_id__h40705 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1399 ;
assign _dfoo1536 =
(source_id__h40705 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1468 ;
assign _dfoo1537 =
source_id__h40705 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1401 ;
assign _dfoo1538 =
(source_id__h40705 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1470 ;
assign _dfoo1539 =
source_id__h40705 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1403 ;
assign _dfoo154 =
(source_id__h70625 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo86 ;
assign _dfoo1540 =
(source_id__h40705 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1472 ;
assign _dfoo1541 =
source_id__h40705 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1405 ;
assign _dfoo1542 =
(source_id__h40705 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1474 ;
assign _dfoo1543 =
source_id__h40705 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1407 ;
assign _dfoo1544 =
(source_id__h40705 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1476 ;
assign _dfoo1545 =
source_id__h40705 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1409 ;
assign _dfoo1546 =
(source_id__h40705 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1478 ;
assign _dfoo1547 =
source_id__h40705 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1411 ;
assign _dfoo1548 =
(source_id__h40705 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1480 ;
assign _dfoo1549 =
source_id__h40705 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1413 ;
assign _dfoo155 =
source_id__h70625 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo19 ;
assign _dfoo1550 =
(source_id__h40705 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1482 ;
assign _dfoo1551 =
source_id__h40705 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1415 ;
assign _dfoo1552 =
(source_id__h40705 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1484 ;
assign _dfoo1553 =
source_id__h40705 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1417 ;
assign _dfoo1554 =
(source_id__h40705 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1486 ;
assign _dfoo1555 =
source_id__h40705 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1419 ;
assign _dfoo1556 =
(source_id__h40705 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1488 ;
assign _dfoo1557 =
source_id__h40705 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1421 ;
assign _dfoo1558 =
(source_id__h40705 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1490 ;
assign _dfoo1559 =
source_id__h40705 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1423 ;
assign _dfoo156 =
(source_id__h70625 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo88 ;
assign _dfoo1560 =
(source_id__h40705 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1492 ;
assign _dfoo1561 =
source_id__h40705 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1425 ;
assign _dfoo1562 =
(source_id__h40705 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1494 ;
assign _dfoo1563 =
source_id__h40705 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1427 ;
assign _dfoo1564 =
(source_id__h40705 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1496 ;
assign _dfoo1566 =
(source_id__h39209 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1498 ;
assign _dfoo1568 =
(source_id__h39209 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1500 ;
assign _dfoo157 =
source_id__h70625 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo21 ;
assign _dfoo1570 =
(source_id__h39209 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1502 ;
assign _dfoo1572 =
(source_id__h39209 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1504 ;
assign _dfoo1574 =
(source_id__h39209 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1506 ;
assign _dfoo1576 =
(source_id__h39209 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1508 ;
assign _dfoo1578 =
(source_id__h39209 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1510 ;
assign _dfoo158 =
(source_id__h70625 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo90 ;
assign _dfoo1580 =
(source_id__h39209 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1512 ;
assign _dfoo1582 =
(source_id__h39209 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1514 ;
assign _dfoo1584 =
(source_id__h39209 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1516 ;
assign _dfoo1586 =
(source_id__h39209 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1518 ;
assign _dfoo1588 =
(source_id__h39209 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1520 ;
assign _dfoo159 =
source_id__h70625 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo23 ;
assign _dfoo1590 =
(source_id__h39209 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1522 ;
assign _dfoo1592 =
(source_id__h39209 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1524 ;
assign _dfoo1594 =
(source_id__h39209 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1526 ;
assign _dfoo1596 =
(source_id__h39209 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1528 ;
assign _dfoo1598 =
(source_id__h39209 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1530 ;
assign _dfoo16 =
(source_id__h73617 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo160 =
(source_id__h70625 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo92 ;
assign _dfoo1600 =
(source_id__h39209 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1532 ;
assign _dfoo1602 =
(source_id__h39209 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1534 ;
assign _dfoo1604 =
(source_id__h39209 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1536 ;
assign _dfoo1606 =
(source_id__h39209 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1538 ;
assign _dfoo1608 =
(source_id__h39209 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1540 ;
assign _dfoo161 =
source_id__h70625 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo25 ;
assign _dfoo1610 =
(source_id__h39209 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1542 ;
assign _dfoo1612 =
(source_id__h39209 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1544 ;
assign _dfoo1614 =
(source_id__h39209 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1546 ;
assign _dfoo1616 =
(source_id__h39209 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1548 ;
assign _dfoo1618 =
(source_id__h39209 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1550 ;
assign _dfoo162 =
(source_id__h70625 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo94 ;
assign _dfoo1620 =
(source_id__h39209 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1552 ;
assign _dfoo1622 =
(source_id__h39209 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1554 ;
assign _dfoo1624 =
(source_id__h39209 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1556 ;
assign _dfoo1626 =
(source_id__h39209 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1558 ;
assign _dfoo1628 =
(source_id__h39209 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1560 ;
assign _dfoo163 =
source_id__h70625 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo27 ;
assign _dfoo1630 =
(source_id__h39209 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1562 ;
assign _dfoo1632 =
(source_id__h39209 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1564 ;
assign _dfoo1633 =
source_id__h37713 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1497 ;
assign _dfoo1634 =
(source_id__h37713 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1566 ;
assign _dfoo1635 =
source_id__h37713 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1499 ;
assign _dfoo1636 =
(source_id__h37713 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1568 ;
assign _dfoo1637 =
source_id__h37713 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1501 ;
assign _dfoo1638 =
(source_id__h37713 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1570 ;
assign _dfoo1639 =
source_id__h37713 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1503 ;
assign _dfoo164 =
(source_id__h70625 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo96 ;
assign _dfoo1640 =
(source_id__h37713 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1572 ;
assign _dfoo1641 =
source_id__h37713 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1505 ;
assign _dfoo1642 =
(source_id__h37713 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1574 ;
assign _dfoo1643 =
source_id__h37713 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1507 ;
assign _dfoo1644 =
(source_id__h37713 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1576 ;
assign _dfoo1645 =
source_id__h37713 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1509 ;
assign _dfoo1646 =
(source_id__h37713 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1578 ;
assign _dfoo1647 =
source_id__h37713 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1511 ;
assign _dfoo1648 =
(source_id__h37713 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1580 ;
assign _dfoo1649 =
source_id__h37713 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1513 ;
assign _dfoo165 =
source_id__h70625 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo29 ;
assign _dfoo1650 =
(source_id__h37713 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1582 ;
assign _dfoo1651 =
source_id__h37713 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1515 ;
assign _dfoo1652 =
(source_id__h37713 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1584 ;
assign _dfoo1653 =
source_id__h37713 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1517 ;
assign _dfoo1654 =
(source_id__h37713 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1586 ;
assign _dfoo1655 =
source_id__h37713 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1519 ;
assign _dfoo1656 =
(source_id__h37713 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1588 ;
assign _dfoo1657 =
source_id__h37713 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1521 ;
assign _dfoo1658 =
(source_id__h37713 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1590 ;
assign _dfoo1659 =
source_id__h37713 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1523 ;
assign _dfoo166 =
(source_id__h70625 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo98 ;
assign _dfoo1660 =
(source_id__h37713 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1592 ;
assign _dfoo1661 =
source_id__h37713 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1525 ;
assign _dfoo1662 =
(source_id__h37713 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1594 ;
assign _dfoo1663 =
source_id__h37713 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1527 ;
assign _dfoo1664 =
(source_id__h37713 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1596 ;
assign _dfoo1665 =
source_id__h37713 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1529 ;
assign _dfoo1666 =
(source_id__h37713 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1598 ;
assign _dfoo1667 =
source_id__h37713 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1531 ;
assign _dfoo1668 =
(source_id__h37713 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1600 ;
assign _dfoo1669 =
source_id__h37713 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1533 ;
assign _dfoo167 =
source_id__h70625 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo31 ;
assign _dfoo1670 =
(source_id__h37713 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1602 ;
assign _dfoo1671 =
source_id__h37713 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1535 ;
assign _dfoo1672 =
(source_id__h37713 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1604 ;
assign _dfoo1673 =
source_id__h37713 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1537 ;
assign _dfoo1674 =
(source_id__h37713 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1606 ;
assign _dfoo1675 =
source_id__h37713 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1539 ;
assign _dfoo1676 =
(source_id__h37713 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1608 ;
assign _dfoo1677 =
source_id__h37713 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1541 ;
assign _dfoo1678 =
(source_id__h37713 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1610 ;
assign _dfoo1679 =
source_id__h37713 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1543 ;
assign _dfoo168 =
(source_id__h70625 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo100 ;
assign _dfoo1680 =
(source_id__h37713 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1612 ;
assign _dfoo1681 =
source_id__h37713 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1545 ;
assign _dfoo1682 =
(source_id__h37713 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1614 ;
assign _dfoo1683 =
source_id__h37713 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1547 ;
assign _dfoo1684 =
(source_id__h37713 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1616 ;
assign _dfoo1685 =
source_id__h37713 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1549 ;
assign _dfoo1686 =
(source_id__h37713 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1618 ;
assign _dfoo1687 =
source_id__h37713 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1551 ;
assign _dfoo1688 =
(source_id__h37713 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1620 ;
assign _dfoo1689 =
source_id__h37713 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1553 ;
assign _dfoo169 =
source_id__h70625 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo33 ;
assign _dfoo1690 =
(source_id__h37713 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1622 ;
assign _dfoo1691 =
source_id__h37713 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1555 ;
assign _dfoo1692 =
(source_id__h37713 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1624 ;
assign _dfoo1693 =
source_id__h37713 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1557 ;
assign _dfoo1694 =
(source_id__h37713 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1626 ;
assign _dfoo1695 =
source_id__h37713 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1559 ;
assign _dfoo1696 =
(source_id__h37713 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1628 ;
assign _dfoo1697 =
source_id__h37713 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1561 ;
assign _dfoo1698 =
(source_id__h37713 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1630 ;
assign _dfoo1699 =
source_id__h37713 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1563 ;
assign _dfoo17 =
source_id__h73617 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo170 =
(source_id__h70625 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo102 ;
assign _dfoo1700 =
(source_id__h37713 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1632 ;
assign _dfoo1702 =
(source_id__h36217 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1634 ;
assign _dfoo1704 =
(source_id__h36217 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1636 ;
assign _dfoo1706 =
(source_id__h36217 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1638 ;
assign _dfoo1708 =
(source_id__h36217 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1640 ;
assign _dfoo171 =
source_id__h70625 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo35 ;
assign _dfoo1710 =
(source_id__h36217 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1642 ;
assign _dfoo1712 =
(source_id__h36217 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1644 ;
assign _dfoo1714 =
(source_id__h36217 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1646 ;
assign _dfoo1716 =
(source_id__h36217 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1648 ;
assign _dfoo1718 =
(source_id__h36217 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1650 ;
assign _dfoo172 =
(source_id__h70625 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo104 ;
assign _dfoo1720 =
(source_id__h36217 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1652 ;
assign _dfoo1722 =
(source_id__h36217 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1654 ;
assign _dfoo1724 =
(source_id__h36217 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1656 ;
assign _dfoo1726 =
(source_id__h36217 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1658 ;
assign _dfoo1728 =
(source_id__h36217 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1660 ;
assign _dfoo173 =
source_id__h70625 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo37 ;
assign _dfoo1730 =
(source_id__h36217 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1662 ;
assign _dfoo1732 =
(source_id__h36217 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1664 ;
assign _dfoo1734 =
(source_id__h36217 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1666 ;
assign _dfoo1736 =
(source_id__h36217 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1668 ;
assign _dfoo1738 =
(source_id__h36217 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1670 ;
assign _dfoo174 =
(source_id__h70625 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo106 ;
assign _dfoo1740 =
(source_id__h36217 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1672 ;
assign _dfoo1742 =
(source_id__h36217 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1674 ;
assign _dfoo1744 =
(source_id__h36217 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1676 ;
assign _dfoo1746 =
(source_id__h36217 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1678 ;
assign _dfoo1748 =
(source_id__h36217 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1680 ;
assign _dfoo175 =
source_id__h70625 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo39 ;
assign _dfoo1750 =
(source_id__h36217 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1682 ;
assign _dfoo1752 =
(source_id__h36217 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1684 ;
assign _dfoo1754 =
(source_id__h36217 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1686 ;
assign _dfoo1756 =
(source_id__h36217 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1688 ;
assign _dfoo1758 =
(source_id__h36217 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1690 ;
assign _dfoo176 =
(source_id__h70625 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo108 ;
assign _dfoo1760 =
(source_id__h36217 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1692 ;
assign _dfoo1762 =
(source_id__h36217 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1694 ;
assign _dfoo1764 =
(source_id__h36217 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1696 ;
assign _dfoo1766 =
(source_id__h36217 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1698 ;
assign _dfoo1768 =
(source_id__h36217 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1700 ;
assign _dfoo1769 =
source_id__h34721 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1633 ;
assign _dfoo177 =
source_id__h70625 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo41 ;
assign _dfoo1770 =
(source_id__h34721 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1702 ;
assign _dfoo1771 =
source_id__h34721 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1635 ;
assign _dfoo1772 =
(source_id__h34721 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1704 ;
assign _dfoo1773 =
source_id__h34721 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1637 ;
assign _dfoo1774 =
(source_id__h34721 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1706 ;
assign _dfoo1775 =
source_id__h34721 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1639 ;
assign _dfoo1776 =
(source_id__h34721 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1708 ;
assign _dfoo1777 =
source_id__h34721 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1641 ;
assign _dfoo1778 =
(source_id__h34721 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1710 ;
assign _dfoo1779 =
source_id__h34721 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1643 ;
assign _dfoo178 =
(source_id__h70625 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo110 ;
assign _dfoo1780 =
(source_id__h34721 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1712 ;
assign _dfoo1781 =
source_id__h34721 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1645 ;
assign _dfoo1782 =
(source_id__h34721 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1714 ;
assign _dfoo1783 =
source_id__h34721 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1647 ;
assign _dfoo1784 =
(source_id__h34721 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1716 ;
assign _dfoo1785 =
source_id__h34721 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1649 ;
assign _dfoo1786 =
(source_id__h34721 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1718 ;
assign _dfoo1787 =
source_id__h34721 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1651 ;
assign _dfoo1788 =
(source_id__h34721 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1720 ;
assign _dfoo1789 =
source_id__h34721 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1653 ;
assign _dfoo179 =
source_id__h70625 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo43 ;
assign _dfoo1790 =
(source_id__h34721 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1722 ;
assign _dfoo1791 =
source_id__h34721 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1655 ;
assign _dfoo1792 =
(source_id__h34721 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1724 ;
assign _dfoo1793 =
source_id__h34721 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1657 ;
assign _dfoo1794 =
(source_id__h34721 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1726 ;
assign _dfoo1795 =
source_id__h34721 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1659 ;
assign _dfoo1796 =
(source_id__h34721 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1728 ;
assign _dfoo1797 =
source_id__h34721 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1661 ;
assign _dfoo1798 =
(source_id__h34721 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1730 ;
assign _dfoo1799 =
source_id__h34721 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1663 ;
assign _dfoo18 =
(source_id__h73617 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo180 =
(source_id__h70625 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo112 ;
assign _dfoo1800 =
(source_id__h34721 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1732 ;
assign _dfoo1801 =
source_id__h34721 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1665 ;
assign _dfoo1802 =
(source_id__h34721 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1734 ;
assign _dfoo1803 =
source_id__h34721 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1667 ;
assign _dfoo1804 =
(source_id__h34721 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1736 ;
assign _dfoo1805 =
source_id__h34721 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1669 ;
assign _dfoo1806 =
(source_id__h34721 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1738 ;
assign _dfoo1807 =
source_id__h34721 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1671 ;
assign _dfoo1808 =
(source_id__h34721 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1740 ;
assign _dfoo1809 =
source_id__h34721 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1673 ;
assign _dfoo181 =
source_id__h70625 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo45 ;
assign _dfoo1810 =
(source_id__h34721 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1742 ;
assign _dfoo1811 =
source_id__h34721 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1675 ;
assign _dfoo1812 =
(source_id__h34721 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1744 ;
assign _dfoo1813 =
source_id__h34721 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1677 ;
assign _dfoo1814 =
(source_id__h34721 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1746 ;
assign _dfoo1815 =
source_id__h34721 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1679 ;
assign _dfoo1816 =
(source_id__h34721 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1748 ;
assign _dfoo1817 =
source_id__h34721 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1681 ;
assign _dfoo1818 =
(source_id__h34721 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1750 ;
assign _dfoo1819 =
source_id__h34721 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1683 ;
assign _dfoo182 =
(source_id__h70625 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo114 ;
assign _dfoo1820 =
(source_id__h34721 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1752 ;
assign _dfoo1821 =
source_id__h34721 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1685 ;
assign _dfoo1822 =
(source_id__h34721 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1754 ;
assign _dfoo1823 =
source_id__h34721 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1687 ;
assign _dfoo1824 =
(source_id__h34721 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1756 ;
assign _dfoo1825 =
source_id__h34721 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1689 ;
assign _dfoo1826 =
(source_id__h34721 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1758 ;
assign _dfoo1827 =
source_id__h34721 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1691 ;
assign _dfoo1828 =
(source_id__h34721 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1760 ;
assign _dfoo1829 =
source_id__h34721 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1693 ;
assign _dfoo183 =
source_id__h70625 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo47 ;
assign _dfoo1830 =
(source_id__h34721 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1762 ;
assign _dfoo1831 =
source_id__h34721 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1695 ;
assign _dfoo1832 =
(source_id__h34721 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1764 ;
assign _dfoo1833 =
source_id__h34721 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1697 ;
assign _dfoo1834 =
(source_id__h34721 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1766 ;
assign _dfoo1835 =
source_id__h34721 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1699 ;
assign _dfoo1836 =
(source_id__h34721 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1768 ;
assign _dfoo1838 =
(source_id__h33225 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1770 ;
assign _dfoo184 =
(source_id__h70625 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo116 ;
assign _dfoo1840 =
(source_id__h33225 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1772 ;
assign _dfoo1842 =
(source_id__h33225 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1774 ;
assign _dfoo1844 =
(source_id__h33225 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1776 ;
assign _dfoo1846 =
(source_id__h33225 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1778 ;
assign _dfoo1848 =
(source_id__h33225 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1780 ;
assign _dfoo185 =
source_id__h70625 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo49 ;
assign _dfoo1850 =
(source_id__h33225 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1782 ;
assign _dfoo1852 =
(source_id__h33225 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1784 ;
assign _dfoo1854 =
(source_id__h33225 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1786 ;
assign _dfoo1856 =
(source_id__h33225 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1788 ;
assign _dfoo1858 =
(source_id__h33225 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1790 ;
assign _dfoo186 =
(source_id__h70625 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo118 ;
assign _dfoo1860 =
(source_id__h33225 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1792 ;
assign _dfoo1862 =
(source_id__h33225 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1794 ;
assign _dfoo1864 =
(source_id__h33225 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1796 ;
assign _dfoo1866 =
(source_id__h33225 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1798 ;
assign _dfoo1868 =
(source_id__h33225 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1800 ;
assign _dfoo187 =
source_id__h70625 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo51 ;
assign _dfoo1870 =
(source_id__h33225 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1802 ;
assign _dfoo1872 =
(source_id__h33225 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1804 ;
assign _dfoo1874 =
(source_id__h33225 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1806 ;
assign _dfoo1876 =
(source_id__h33225 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1808 ;
assign _dfoo1878 =
(source_id__h33225 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1810 ;
assign _dfoo188 =
(source_id__h70625 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo120 ;
assign _dfoo1880 =
(source_id__h33225 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1812 ;
assign _dfoo1882 =
(source_id__h33225 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1814 ;
assign _dfoo1884 =
(source_id__h33225 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1816 ;
assign _dfoo1886 =
(source_id__h33225 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1818 ;
assign _dfoo1888 =
(source_id__h33225 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1820 ;
assign _dfoo189 =
source_id__h70625 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo53 ;
assign _dfoo1890 =
(source_id__h33225 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1822 ;
assign _dfoo1892 =
(source_id__h33225 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1824 ;
assign _dfoo1894 =
(source_id__h33225 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1826 ;
assign _dfoo1896 =
(source_id__h33225 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1828 ;
assign _dfoo1898 =
(source_id__h33225 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1830 ;
assign _dfoo19 =
source_id__h73617 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo190 =
(source_id__h70625 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo122 ;
assign _dfoo1900 =
(source_id__h33225 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1832 ;
assign _dfoo1902 =
(source_id__h33225 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1834 ;
assign _dfoo1904 =
(source_id__h33225 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1836 ;
assign _dfoo1905 =
source_id__h31729 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1769 ;
assign _dfoo1906 =
(source_id__h31729 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1838 ;
assign _dfoo1907 =
source_id__h31729 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1771 ;
assign _dfoo1908 =
(source_id__h31729 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1840 ;
assign _dfoo1909 =
source_id__h31729 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1773 ;
assign _dfoo191 =
source_id__h70625 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo55 ;
assign _dfoo1910 =
(source_id__h31729 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1842 ;
assign _dfoo1911 =
source_id__h31729 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1775 ;
assign _dfoo1912 =
(source_id__h31729 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1844 ;
assign _dfoo1913 =
source_id__h31729 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1777 ;
assign _dfoo1914 =
(source_id__h31729 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1846 ;
assign _dfoo1915 =
source_id__h31729 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1779 ;
assign _dfoo1916 =
(source_id__h31729 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1848 ;
assign _dfoo1917 =
source_id__h31729 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1781 ;
assign _dfoo1918 =
(source_id__h31729 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1850 ;
assign _dfoo1919 =
source_id__h31729 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1783 ;
assign _dfoo192 =
(source_id__h70625 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo124 ;
assign _dfoo1920 =
(source_id__h31729 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1852 ;
assign _dfoo1921 =
source_id__h31729 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1785 ;
assign _dfoo1922 =
(source_id__h31729 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1854 ;
assign _dfoo1923 =
source_id__h31729 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1787 ;
assign _dfoo1924 =
(source_id__h31729 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1856 ;
assign _dfoo1925 =
source_id__h31729 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1789 ;
assign _dfoo1926 =
(source_id__h31729 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1858 ;
assign _dfoo1927 =
source_id__h31729 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1791 ;
assign _dfoo1928 =
(source_id__h31729 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1860 ;
assign _dfoo1929 =
source_id__h31729 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1793 ;
assign _dfoo193 =
source_id__h70625 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo57 ;
assign _dfoo1930 =
(source_id__h31729 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1862 ;
assign _dfoo1931 =
source_id__h31729 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1795 ;
assign _dfoo1932 =
(source_id__h31729 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1864 ;
assign _dfoo1933 =
source_id__h31729 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1797 ;
assign _dfoo1934 =
(source_id__h31729 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1866 ;
assign _dfoo1935 =
source_id__h31729 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1799 ;
assign _dfoo1936 =
(source_id__h31729 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1868 ;
assign _dfoo1937 =
source_id__h31729 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1801 ;
assign _dfoo1938 =
(source_id__h31729 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1870 ;
assign _dfoo1939 =
source_id__h31729 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1803 ;
assign _dfoo194 =
(source_id__h70625 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo126 ;
assign _dfoo1940 =
(source_id__h31729 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1872 ;
assign _dfoo1941 =
source_id__h31729 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1805 ;
assign _dfoo1942 =
(source_id__h31729 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1874 ;
assign _dfoo1943 =
source_id__h31729 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1807 ;
assign _dfoo1944 =
(source_id__h31729 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1876 ;
assign _dfoo1945 =
source_id__h31729 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1809 ;
assign _dfoo1946 =
(source_id__h31729 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1878 ;
assign _dfoo1947 =
source_id__h31729 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1811 ;
assign _dfoo1948 =
(source_id__h31729 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1880 ;
assign _dfoo1949 =
source_id__h31729 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1813 ;
assign _dfoo195 =
source_id__h70625 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo59 ;
assign _dfoo1950 =
(source_id__h31729 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1882 ;
assign _dfoo1951 =
source_id__h31729 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1815 ;
assign _dfoo1952 =
(source_id__h31729 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1884 ;
assign _dfoo1953 =
source_id__h31729 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1817 ;
assign _dfoo1954 =
(source_id__h31729 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1886 ;
assign _dfoo1955 =
source_id__h31729 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1819 ;
assign _dfoo1956 =
(source_id__h31729 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1888 ;
assign _dfoo1957 =
source_id__h31729 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1821 ;
assign _dfoo1958 =
(source_id__h31729 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1890 ;
assign _dfoo1959 =
source_id__h31729 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1823 ;
assign _dfoo196 =
(source_id__h70625 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo128 ;
assign _dfoo1960 =
(source_id__h31729 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1892 ;
assign _dfoo1961 =
source_id__h31729 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1825 ;
assign _dfoo1962 =
(source_id__h31729 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1894 ;
assign _dfoo1963 =
source_id__h31729 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1827 ;
assign _dfoo1964 =
(source_id__h31729 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1896 ;
assign _dfoo1965 =
source_id__h31729 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1829 ;
assign _dfoo1966 =
(source_id__h31729 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1898 ;
assign _dfoo1967 =
source_id__h31729 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1831 ;
assign _dfoo1968 =
(source_id__h31729 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1900 ;
assign _dfoo1969 =
source_id__h31729 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1833 ;
assign _dfoo197 =
source_id__h70625 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo61 ;
assign _dfoo1970 =
(source_id__h31729 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1902 ;
assign _dfoo1971 =
source_id__h31729 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1835 ;
assign _dfoo1972 =
(source_id__h31729 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1904 ;
assign _dfoo1974 =
(source_id__h30233 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1906 ;
assign _dfoo1976 =
(source_id__h30233 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1908 ;
assign _dfoo1978 =
(source_id__h30233 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1910 ;
assign _dfoo198 =
(source_id__h70625 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo130 ;
assign _dfoo1980 =
(source_id__h30233 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1912 ;
assign _dfoo1982 =
(source_id__h30233 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1914 ;
assign _dfoo1984 =
(source_id__h30233 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1916 ;
assign _dfoo1986 =
(source_id__h30233 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1918 ;
assign _dfoo1988 =
(source_id__h30233 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1920 ;
assign _dfoo199 =
source_id__h70625 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo63 ;
assign _dfoo1990 =
(source_id__h30233 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1922 ;
assign _dfoo1992 =
(source_id__h30233 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1924 ;
assign _dfoo1994 =
(source_id__h30233 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1926 ;
assign _dfoo1996 =
(source_id__h30233 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1928 ;
assign _dfoo1998 =
(source_id__h30233 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1930 ;
assign _dfoo2 =
(source_id__h73617 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo20 =
(source_id__h73617 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo200 =
(source_id__h70625 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo132 ;
assign _dfoo2000 =
(source_id__h30233 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1932 ;
assign _dfoo2002 =
(source_id__h30233 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1934 ;
assign _dfoo2004 =
(source_id__h30233 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1936 ;
assign _dfoo2006 =
(source_id__h30233 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1938 ;
assign _dfoo2008 =
(source_id__h30233 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1940 ;
assign _dfoo201 =
source_id__h70625 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo65 ;
assign _dfoo2010 =
(source_id__h30233 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1942 ;
assign _dfoo2012 =
(source_id__h30233 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1944 ;
assign _dfoo2014 =
(source_id__h30233 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1946 ;
assign _dfoo2016 =
(source_id__h30233 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1948 ;
assign _dfoo2018 =
(source_id__h30233 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1950 ;
assign _dfoo202 =
(source_id__h70625 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo134 ;
assign _dfoo2020 =
(source_id__h30233 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1952 ;
assign _dfoo2022 =
(source_id__h30233 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1954 ;
assign _dfoo2024 =
(source_id__h30233 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1956 ;
assign _dfoo2026 =
(source_id__h30233 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1958 ;
assign _dfoo2028 =
(source_id__h30233 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1960 ;
assign _dfoo203 =
source_id__h70625 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo67 ;
assign _dfoo2030 =
(source_id__h30233 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1962 ;
assign _dfoo2032 =
(source_id__h30233 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1964 ;
assign _dfoo2034 =
(source_id__h30233 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1966 ;
assign _dfoo2036 =
(source_id__h30233 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1968 ;
assign _dfoo2038 =
(source_id__h30233 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1970 ;
assign _dfoo204 =
(source_id__h70625 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo136 ;
assign _dfoo2040 =
(source_id__h30233 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1972 ;
assign _dfoo2041 =
source_id_base__h28620 == 10'd16 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1905 ;
assign _dfoo2043 =
source_id_base__h28620 == 10'd15 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1907 ;
assign _dfoo2045 =
source_id_base__h28620 == 10'd14 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1909 ;
assign _dfoo2047 =
source_id_base__h28620 == 10'd13 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1911 ;
assign _dfoo2049 =
source_id_base__h28620 == 10'd12 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1913 ;
assign _dfoo2051 =
source_id_base__h28620 == 10'd11 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1915 ;
assign _dfoo2053 =
source_id_base__h28620 == 10'd10 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1917 ;
assign _dfoo2055 =
source_id_base__h28620 == 10'd9 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1919 ;
assign _dfoo2057 =
source_id_base__h28620 == 10'd8 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1921 ;
assign _dfoo2059 =
source_id_base__h28620 == 10'd7 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1923 ;
assign _dfoo206 =
(source_id__h69129 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo138 ;
assign _dfoo2061 =
source_id_base__h28620 == 10'd6 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1925 ;
assign _dfoo2063 =
source_id_base__h28620 == 10'd5 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1927 ;
assign _dfoo2065 =
source_id_base__h28620 == 10'd4 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1929 ;
assign _dfoo2067 =
source_id_base__h28620 == 10'd3 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1931 ;
assign _dfoo2069 =
source_id_base__h28620 == 10'd2 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1933 ;
assign _dfoo2071 =
source_id_base__h28620 == 10'd1 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1935 ;
assign _dfoo2073 =
source_id_base__h28620 == 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1937 ;
assign _dfoo2075 =
source_id_base__h28620 == 10'd16 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1939 ;
assign _dfoo2077 =
source_id_base__h28620 == 10'd15 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1941 ;
assign _dfoo2079 =
source_id_base__h28620 == 10'd14 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1943 ;
assign _dfoo208 =
(source_id__h69129 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo140 ;
assign _dfoo2081 =
source_id_base__h28620 == 10'd13 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1945 ;
assign _dfoo2083 =
source_id_base__h28620 == 10'd12 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1947 ;
assign _dfoo2085 =
source_id_base__h28620 == 10'd11 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1949 ;
assign _dfoo2087 =
source_id_base__h28620 == 10'd10 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1951 ;
assign _dfoo2089 =
source_id_base__h28620 == 10'd9 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1953 ;
assign _dfoo2091 =
source_id_base__h28620 == 10'd8 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1955 ;
assign _dfoo2093 =
source_id_base__h28620 == 10'd7 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1957 ;
assign _dfoo2095 =
source_id_base__h28620 == 10'd6 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1959 ;
assign _dfoo2097 =
source_id_base__h28620 == 10'd5 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1961 ;
assign _dfoo2099 =
source_id_base__h28620 == 10'd4 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1963 ;
assign _dfoo21 =
source_id__h73617 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo210 =
(source_id__h69129 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo142 ;
assign _dfoo2101 =
source_id_base__h28620 == 10'd3 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1965 ;
assign _dfoo2103 =
source_id_base__h28620 == 10'd2 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1967 ;
assign _dfoo2105 =
source_id_base__h28620 == 10'd1 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1969 ;
assign _dfoo2107 =
source_id_base__h28620 == 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1971 ;
assign _dfoo212 =
(source_id__h69129 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo144 ;
assign _dfoo214 =
(source_id__h69129 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo146 ;
assign _dfoo216 =
(source_id__h69129 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo148 ;
assign _dfoo218 =
(source_id__h69129 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo150 ;
assign _dfoo22 =
(source_id__h73617 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo220 =
(source_id__h69129 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo152 ;
assign _dfoo222 =
(source_id__h69129 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo154 ;
assign _dfoo224 =
(source_id__h69129 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo156 ;
assign _dfoo226 =
(source_id__h69129 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo158 ;
assign _dfoo228 =
(source_id__h69129 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo160 ;
assign _dfoo23 =
source_id__h73617 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo230 =
(source_id__h69129 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo162 ;
assign _dfoo232 =
(source_id__h69129 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo164 ;
assign _dfoo234 =
(source_id__h69129 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo166 ;
assign _dfoo236 =
(source_id__h69129 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo168 ;
assign _dfoo238 =
(source_id__h69129 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo170 ;
assign _dfoo24 =
(source_id__h73617 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo240 =
(source_id__h69129 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo172 ;
assign _dfoo242 =
(source_id__h69129 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo174 ;
assign _dfoo244 =
(source_id__h69129 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo176 ;
assign _dfoo246 =
(source_id__h69129 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo178 ;
assign _dfoo248 =
(source_id__h69129 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo180 ;
assign _dfoo25 =
source_id__h73617 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo250 =
(source_id__h69129 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo182 ;
assign _dfoo252 =
(source_id__h69129 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo184 ;
assign _dfoo254 =
(source_id__h69129 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo186 ;
assign _dfoo256 =
(source_id__h69129 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo188 ;
assign _dfoo258 =
(source_id__h69129 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo190 ;
assign _dfoo26 =
(source_id__h73617 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo260 =
(source_id__h69129 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo192 ;
assign _dfoo262 =
(source_id__h69129 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo194 ;
assign _dfoo264 =
(source_id__h69129 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo196 ;
assign _dfoo266 =
(source_id__h69129 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo198 ;
assign _dfoo268 =
(source_id__h69129 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo200 ;
assign _dfoo27 =
source_id__h73617 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo270 =
(source_id__h69129 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo202 ;
assign _dfoo272 =
(source_id__h69129 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo204 ;
assign _dfoo273 =
source_id__h67633 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo137 ;
assign _dfoo274 =
(source_id__h67633 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo206 ;
assign _dfoo275 =
source_id__h67633 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo139 ;
assign _dfoo276 =
(source_id__h67633 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo208 ;
assign _dfoo277 =
source_id__h67633 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo141 ;
assign _dfoo278 =
(source_id__h67633 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo210 ;
assign _dfoo279 =
source_id__h67633 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo143 ;
assign _dfoo28 =
(source_id__h73617 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo280 =
(source_id__h67633 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo212 ;
assign _dfoo281 =
source_id__h67633 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo145 ;
assign _dfoo282 =
(source_id__h67633 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo214 ;
assign _dfoo283 =
source_id__h67633 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo147 ;
assign _dfoo284 =
(source_id__h67633 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo216 ;
assign _dfoo285 =
source_id__h67633 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo149 ;
assign _dfoo286 =
(source_id__h67633 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo218 ;
assign _dfoo287 =
source_id__h67633 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo151 ;
assign _dfoo288 =
(source_id__h67633 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo220 ;
assign _dfoo289 =
source_id__h67633 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo153 ;
assign _dfoo29 =
source_id__h73617 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo290 =
(source_id__h67633 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo222 ;
assign _dfoo291 =
source_id__h67633 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo155 ;
assign _dfoo292 =
(source_id__h67633 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo224 ;
assign _dfoo293 =
source_id__h67633 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo157 ;
assign _dfoo294 =
(source_id__h67633 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo226 ;
assign _dfoo295 =
source_id__h67633 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo159 ;
assign _dfoo296 =
(source_id__h67633 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo228 ;
assign _dfoo297 =
source_id__h67633 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo161 ;
assign _dfoo298 =
(source_id__h67633 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo230 ;
assign _dfoo299 =
source_id__h67633 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo163 ;
assign _dfoo3 =
source_id__h73617 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo30 =
(source_id__h73617 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo300 =
(source_id__h67633 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo232 ;
assign _dfoo301 =
source_id__h67633 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo165 ;
assign _dfoo302 =
(source_id__h67633 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo234 ;
assign _dfoo303 =
source_id__h67633 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo167 ;
assign _dfoo304 =
(source_id__h67633 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo236 ;
assign _dfoo305 =
source_id__h67633 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo169 ;
assign _dfoo306 =
(source_id__h67633 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo238 ;
assign _dfoo307 =
source_id__h67633 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo171 ;
assign _dfoo308 =
(source_id__h67633 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo240 ;
assign _dfoo309 =
source_id__h67633 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo173 ;
assign _dfoo31 =
source_id__h73617 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo310 =
(source_id__h67633 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo242 ;
assign _dfoo311 =
source_id__h67633 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo175 ;
assign _dfoo312 =
(source_id__h67633 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo244 ;
assign _dfoo313 =
source_id__h67633 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo177 ;
assign _dfoo314 =
(source_id__h67633 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo246 ;
assign _dfoo315 =
source_id__h67633 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo179 ;
assign _dfoo316 =
(source_id__h67633 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo248 ;
assign _dfoo317 =
source_id__h67633 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo181 ;
assign _dfoo318 =
(source_id__h67633 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo250 ;
assign _dfoo319 =
source_id__h67633 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo183 ;
assign _dfoo32 =
(source_id__h73617 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo320 =
(source_id__h67633 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo252 ;
assign _dfoo321 =
source_id__h67633 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo185 ;
assign _dfoo322 =
(source_id__h67633 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo254 ;
assign _dfoo323 =
source_id__h67633 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo187 ;
assign _dfoo324 =
(source_id__h67633 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo256 ;
assign _dfoo325 =
source_id__h67633 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo189 ;
assign _dfoo326 =
(source_id__h67633 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo258 ;
assign _dfoo327 =
source_id__h67633 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo191 ;
assign _dfoo328 =
(source_id__h67633 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo260 ;
assign _dfoo329 =
source_id__h67633 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo193 ;
assign _dfoo33 =
source_id__h73617 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo330 =
(source_id__h67633 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo262 ;
assign _dfoo331 =
source_id__h67633 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo195 ;
assign _dfoo332 =
(source_id__h67633 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo264 ;
assign _dfoo333 =
source_id__h67633 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo197 ;
assign _dfoo334 =
(source_id__h67633 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo266 ;
assign _dfoo335 =
source_id__h67633 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo199 ;
assign _dfoo336 =
(source_id__h67633 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo268 ;
assign _dfoo337 =
source_id__h67633 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo201 ;
assign _dfoo338 =
(source_id__h67633 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo270 ;
assign _dfoo339 =
source_id__h67633 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo203 ;
assign _dfoo34 =
(source_id__h73617 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo340 =
(source_id__h67633 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo272 ;
assign _dfoo342 =
(source_id__h66137 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo274 ;
assign _dfoo344 =
(source_id__h66137 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo276 ;
assign _dfoo346 =
(source_id__h66137 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo278 ;
assign _dfoo348 =
(source_id__h66137 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo280 ;
assign _dfoo35 =
source_id__h73617 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo350 =
(source_id__h66137 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo282 ;
assign _dfoo352 =
(source_id__h66137 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo284 ;
assign _dfoo354 =
(source_id__h66137 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo286 ;
assign _dfoo356 =
(source_id__h66137 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo288 ;
assign _dfoo358 =
(source_id__h66137 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo290 ;
assign _dfoo36 =
(source_id__h73617 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo360 =
(source_id__h66137 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo292 ;
assign _dfoo362 =
(source_id__h66137 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo294 ;
assign _dfoo364 =
(source_id__h66137 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo296 ;
assign _dfoo366 =
(source_id__h66137 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo298 ;
assign _dfoo368 =
(source_id__h66137 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo300 ;
assign _dfoo37 =
source_id__h73617 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo370 =
(source_id__h66137 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo302 ;
assign _dfoo372 =
(source_id__h66137 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo304 ;
assign _dfoo374 =
(source_id__h66137 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo306 ;
assign _dfoo376 =
(source_id__h66137 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo308 ;
assign _dfoo378 =
(source_id__h66137 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo310 ;
assign _dfoo38 =
(source_id__h73617 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo380 =
(source_id__h66137 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo312 ;
assign _dfoo382 =
(source_id__h66137 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo314 ;
assign _dfoo384 =
(source_id__h66137 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo316 ;
assign _dfoo386 =
(source_id__h66137 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo318 ;
assign _dfoo388 =
(source_id__h66137 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo320 ;
assign _dfoo39 =
source_id__h73617 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo390 =
(source_id__h66137 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo322 ;
assign _dfoo392 =
(source_id__h66137 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo324 ;
assign _dfoo394 =
(source_id__h66137 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo326 ;
assign _dfoo396 =
(source_id__h66137 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo328 ;
assign _dfoo398 =
(source_id__h66137 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo330 ;
assign _dfoo4 =
(source_id__h73617 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo40 =
(source_id__h73617 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo400 =
(source_id__h66137 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo332 ;
assign _dfoo402 =
(source_id__h66137 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo334 ;
assign _dfoo404 =
(source_id__h66137 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo336 ;
assign _dfoo406 =
(source_id__h66137 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo338 ;
assign _dfoo408 =
(source_id__h66137 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo340 ;
assign _dfoo409 =
source_id__h64641 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo273 ;
assign _dfoo41 =
source_id__h73617 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo410 =
(source_id__h64641 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo342 ;
assign _dfoo411 =
source_id__h64641 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo275 ;
assign _dfoo412 =
(source_id__h64641 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo344 ;
assign _dfoo413 =
source_id__h64641 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo277 ;
assign _dfoo414 =
(source_id__h64641 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo346 ;
assign _dfoo415 =
source_id__h64641 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo279 ;
assign _dfoo416 =
(source_id__h64641 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo348 ;
assign _dfoo417 =
source_id__h64641 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo281 ;
assign _dfoo418 =
(source_id__h64641 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo350 ;
assign _dfoo419 =
source_id__h64641 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo283 ;
assign _dfoo42 =
(source_id__h73617 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo420 =
(source_id__h64641 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo352 ;
assign _dfoo421 =
source_id__h64641 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo285 ;
assign _dfoo422 =
(source_id__h64641 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo354 ;
assign _dfoo423 =
source_id__h64641 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo287 ;
assign _dfoo424 =
(source_id__h64641 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo356 ;
assign _dfoo425 =
source_id__h64641 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo289 ;
assign _dfoo426 =
(source_id__h64641 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo358 ;
assign _dfoo427 =
source_id__h64641 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo291 ;
assign _dfoo428 =
(source_id__h64641 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo360 ;
assign _dfoo429 =
source_id__h64641 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo293 ;
assign _dfoo43 =
source_id__h73617 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo430 =
(source_id__h64641 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo362 ;
assign _dfoo431 =
source_id__h64641 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo295 ;
assign _dfoo432 =
(source_id__h64641 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo364 ;
assign _dfoo433 =
source_id__h64641 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo297 ;
assign _dfoo434 =
(source_id__h64641 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo366 ;
assign _dfoo435 =
source_id__h64641 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo299 ;
assign _dfoo436 =
(source_id__h64641 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo368 ;
assign _dfoo437 =
source_id__h64641 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo301 ;
assign _dfoo438 =
(source_id__h64641 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo370 ;
assign _dfoo439 =
source_id__h64641 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo303 ;
assign _dfoo44 =
(source_id__h73617 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo440 =
(source_id__h64641 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo372 ;
assign _dfoo441 =
source_id__h64641 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo305 ;
assign _dfoo442 =
(source_id__h64641 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo374 ;
assign _dfoo443 =
source_id__h64641 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo307 ;
assign _dfoo444 =
(source_id__h64641 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo376 ;
assign _dfoo445 =
source_id__h64641 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo309 ;
assign _dfoo446 =
(source_id__h64641 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo378 ;
assign _dfoo447 =
source_id__h64641 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo311 ;
assign _dfoo448 =
(source_id__h64641 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo380 ;
assign _dfoo449 =
source_id__h64641 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo313 ;
assign _dfoo45 =
source_id__h73617 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo450 =
(source_id__h64641 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo382 ;
assign _dfoo451 =
source_id__h64641 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo315 ;
assign _dfoo452 =
(source_id__h64641 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo384 ;
assign _dfoo453 =
source_id__h64641 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo317 ;
assign _dfoo454 =
(source_id__h64641 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo386 ;
assign _dfoo455 =
source_id__h64641 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo319 ;
assign _dfoo456 =
(source_id__h64641 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo388 ;
assign _dfoo457 =
source_id__h64641 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo321 ;
assign _dfoo458 =
(source_id__h64641 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo390 ;
assign _dfoo459 =
source_id__h64641 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo323 ;
assign _dfoo46 =
(source_id__h73617 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo460 =
(source_id__h64641 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo392 ;
assign _dfoo461 =
source_id__h64641 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo325 ;
assign _dfoo462 =
(source_id__h64641 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo394 ;
assign _dfoo463 =
source_id__h64641 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo327 ;
assign _dfoo464 =
(source_id__h64641 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo396 ;
assign _dfoo465 =
source_id__h64641 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo329 ;
assign _dfoo466 =
(source_id__h64641 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo398 ;
assign _dfoo467 =
source_id__h64641 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo331 ;
assign _dfoo468 =
(source_id__h64641 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo400 ;
assign _dfoo469 =
source_id__h64641 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo333 ;
assign _dfoo47 =
source_id__h73617 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo470 =
(source_id__h64641 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo402 ;
assign _dfoo471 =
source_id__h64641 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo335 ;
assign _dfoo472 =
(source_id__h64641 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo404 ;
assign _dfoo473 =
source_id__h64641 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo337 ;
assign _dfoo474 =
(source_id__h64641 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo406 ;
assign _dfoo475 =
source_id__h64641 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo339 ;
assign _dfoo476 =
(source_id__h64641 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo408 ;
assign _dfoo478 =
(source_id__h63145 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo410 ;
assign _dfoo48 =
(source_id__h73617 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo480 =
(source_id__h63145 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo412 ;
assign _dfoo482 =
(source_id__h63145 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo414 ;
assign _dfoo484 =
(source_id__h63145 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo416 ;
assign _dfoo486 =
(source_id__h63145 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo418 ;
assign _dfoo488 =
(source_id__h63145 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo420 ;
assign _dfoo49 =
source_id__h73617 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo490 =
(source_id__h63145 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo422 ;
assign _dfoo492 =
(source_id__h63145 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo424 ;
assign _dfoo494 =
(source_id__h63145 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo426 ;
assign _dfoo496 =
(source_id__h63145 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo428 ;
assign _dfoo498 =
(source_id__h63145 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo430 ;
assign _dfoo5 =
source_id__h73617 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo50 =
(source_id__h73617 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo500 =
(source_id__h63145 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo432 ;
assign _dfoo502 =
(source_id__h63145 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo434 ;
assign _dfoo504 =
(source_id__h63145 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo436 ;
assign _dfoo506 =
(source_id__h63145 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo438 ;
assign _dfoo508 =
(source_id__h63145 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo440 ;
assign _dfoo51 =
source_id__h73617 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo510 =
(source_id__h63145 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo442 ;
assign _dfoo512 =
(source_id__h63145 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo444 ;
assign _dfoo514 =
(source_id__h63145 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo446 ;
assign _dfoo516 =
(source_id__h63145 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo448 ;
assign _dfoo518 =
(source_id__h63145 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo450 ;
assign _dfoo52 =
(source_id__h73617 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo520 =
(source_id__h63145 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo452 ;
assign _dfoo522 =
(source_id__h63145 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo454 ;
assign _dfoo524 =
(source_id__h63145 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo456 ;
assign _dfoo526 =
(source_id__h63145 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo458 ;
assign _dfoo528 =
(source_id__h63145 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo460 ;
assign _dfoo53 =
source_id__h73617 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo530 =
(source_id__h63145 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo462 ;
assign _dfoo532 =
(source_id__h63145 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo464 ;
assign _dfoo534 =
(source_id__h63145 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo466 ;
assign _dfoo536 =
(source_id__h63145 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo468 ;
assign _dfoo538 =
(source_id__h63145 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo470 ;
assign _dfoo54 =
(source_id__h73617 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo540 =
(source_id__h63145 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo472 ;
assign _dfoo542 =
(source_id__h63145 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo474 ;
assign _dfoo544 =
(source_id__h63145 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo476 ;
assign _dfoo545 =
source_id__h61649 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo409 ;
assign _dfoo546 =
(source_id__h61649 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo478 ;
assign _dfoo547 =
source_id__h61649 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo411 ;
assign _dfoo548 =
(source_id__h61649 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo480 ;
assign _dfoo549 =
source_id__h61649 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo413 ;
assign _dfoo55 =
source_id__h73617 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo550 =
(source_id__h61649 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo482 ;
assign _dfoo551 =
source_id__h61649 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo415 ;
assign _dfoo552 =
(source_id__h61649 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo484 ;
assign _dfoo553 =
source_id__h61649 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo417 ;
assign _dfoo554 =
(source_id__h61649 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo486 ;
assign _dfoo555 =
source_id__h61649 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo419 ;
assign _dfoo556 =
(source_id__h61649 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo488 ;
assign _dfoo557 =
source_id__h61649 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo421 ;
assign _dfoo558 =
(source_id__h61649 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo490 ;
assign _dfoo559 =
source_id__h61649 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo423 ;
assign _dfoo56 =
(source_id__h73617 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo560 =
(source_id__h61649 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo492 ;
assign _dfoo561 =
source_id__h61649 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo425 ;
assign _dfoo562 =
(source_id__h61649 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo494 ;
assign _dfoo563 =
source_id__h61649 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo427 ;
assign _dfoo564 =
(source_id__h61649 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo496 ;
assign _dfoo565 =
source_id__h61649 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo429 ;
assign _dfoo566 =
(source_id__h61649 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo498 ;
assign _dfoo567 =
source_id__h61649 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo431 ;
assign _dfoo568 =
(source_id__h61649 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo500 ;
assign _dfoo569 =
source_id__h61649 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo433 ;
assign _dfoo57 =
source_id__h73617 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo570 =
(source_id__h61649 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo502 ;
assign _dfoo571 =
source_id__h61649 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo435 ;
assign _dfoo572 =
(source_id__h61649 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo504 ;
assign _dfoo573 =
source_id__h61649 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo437 ;
assign _dfoo574 =
(source_id__h61649 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo506 ;
assign _dfoo575 =
source_id__h61649 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo439 ;
assign _dfoo576 =
(source_id__h61649 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo508 ;
assign _dfoo577 =
source_id__h61649 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo441 ;
assign _dfoo578 =
(source_id__h61649 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo510 ;
assign _dfoo579 =
source_id__h61649 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo443 ;
assign _dfoo58 =
(source_id__h73617 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo580 =
(source_id__h61649 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo512 ;
assign _dfoo581 =
source_id__h61649 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo445 ;
assign _dfoo582 =
(source_id__h61649 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo514 ;
assign _dfoo583 =
source_id__h61649 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo447 ;
assign _dfoo584 =
(source_id__h61649 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo516 ;
assign _dfoo585 =
source_id__h61649 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo449 ;
assign _dfoo586 =
(source_id__h61649 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo518 ;
assign _dfoo587 =
source_id__h61649 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo451 ;
assign _dfoo588 =
(source_id__h61649 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo520 ;
assign _dfoo589 =
source_id__h61649 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo453 ;
assign _dfoo59 =
source_id__h73617 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo590 =
(source_id__h61649 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo522 ;
assign _dfoo591 =
source_id__h61649 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo455 ;
assign _dfoo592 =
(source_id__h61649 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo524 ;
assign _dfoo593 =
source_id__h61649 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo457 ;
assign _dfoo594 =
(source_id__h61649 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo526 ;
assign _dfoo595 =
source_id__h61649 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo459 ;
assign _dfoo596 =
(source_id__h61649 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo528 ;
assign _dfoo597 =
source_id__h61649 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo461 ;
assign _dfoo598 =
(source_id__h61649 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo530 ;
assign _dfoo599 =
source_id__h61649 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo463 ;
assign _dfoo6 =
(source_id__h73617 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo60 =
(source_id__h73617 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo600 =
(source_id__h61649 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo532 ;
assign _dfoo601 =
source_id__h61649 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo465 ;
assign _dfoo602 =
(source_id__h61649 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo534 ;
assign _dfoo603 =
source_id__h61649 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo467 ;
assign _dfoo604 =
(source_id__h61649 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo536 ;
assign _dfoo605 =
source_id__h61649 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo469 ;
assign _dfoo606 =
(source_id__h61649 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo538 ;
assign _dfoo607 =
source_id__h61649 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo471 ;
assign _dfoo608 =
(source_id__h61649 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo540 ;
assign _dfoo609 =
source_id__h61649 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo473 ;
assign _dfoo61 =
source_id__h73617 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo610 =
(source_id__h61649 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo542 ;
assign _dfoo611 =
source_id__h61649 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo475 ;
assign _dfoo612 =
(source_id__h61649 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo544 ;
assign _dfoo614 =
(source_id__h60153 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo546 ;
assign _dfoo616 =
(source_id__h60153 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo548 ;
assign _dfoo618 =
(source_id__h60153 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo550 ;
assign _dfoo62 =
(source_id__h73617 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo620 =
(source_id__h60153 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo552 ;
assign _dfoo622 =
(source_id__h60153 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo554 ;
assign _dfoo624 =
(source_id__h60153 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo556 ;
assign _dfoo626 =
(source_id__h60153 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo558 ;
assign _dfoo628 =
(source_id__h60153 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo560 ;
assign _dfoo63 =
source_id__h73617 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo630 =
(source_id__h60153 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo562 ;
assign _dfoo632 =
(source_id__h60153 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo564 ;
assign _dfoo634 =
(source_id__h60153 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo566 ;
assign _dfoo636 =
(source_id__h60153 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo568 ;
assign _dfoo638 =
(source_id__h60153 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo570 ;
assign _dfoo64 =
(source_id__h73617 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo640 =
(source_id__h60153 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo572 ;
assign _dfoo642 =
(source_id__h60153 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo574 ;
assign _dfoo644 =
(source_id__h60153 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo576 ;
assign _dfoo646 =
(source_id__h60153 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo578 ;
assign _dfoo648 =
(source_id__h60153 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo580 ;
assign _dfoo65 =
source_id__h73617 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo650 =
(source_id__h60153 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo582 ;
assign _dfoo652 =
(source_id__h60153 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo584 ;
assign _dfoo654 =
(source_id__h60153 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo586 ;
assign _dfoo656 =
(source_id__h60153 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo588 ;
assign _dfoo658 =
(source_id__h60153 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo590 ;
assign _dfoo66 =
(source_id__h73617 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo660 =
(source_id__h60153 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo592 ;
assign _dfoo662 =
(source_id__h60153 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo594 ;
assign _dfoo664 =
(source_id__h60153 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo596 ;
assign _dfoo666 =
(source_id__h60153 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo598 ;
assign _dfoo668 =
(source_id__h60153 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo600 ;
assign _dfoo67 =
source_id__h73617 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo670 =
(source_id__h60153 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo602 ;
assign _dfoo672 =
(source_id__h60153 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo604 ;
assign _dfoo674 =
(source_id__h60153 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo606 ;
assign _dfoo676 =
(source_id__h60153 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo608 ;
assign _dfoo678 =
(source_id__h60153 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo610 ;
assign _dfoo68 =
(source_id__h73617 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo680 =
(source_id__h60153 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo612 ;
assign _dfoo681 =
source_id__h58657 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo545 ;
assign _dfoo682 =
(source_id__h58657 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo614 ;
assign _dfoo683 =
source_id__h58657 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo547 ;
assign _dfoo684 =
(source_id__h58657 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo616 ;
assign _dfoo685 =
source_id__h58657 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo549 ;
assign _dfoo686 =
(source_id__h58657 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo618 ;
assign _dfoo687 =
source_id__h58657 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo551 ;
assign _dfoo688 =
(source_id__h58657 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo620 ;
assign _dfoo689 =
source_id__h58657 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo553 ;
assign _dfoo690 =
(source_id__h58657 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo622 ;
assign _dfoo691 =
source_id__h58657 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo555 ;
assign _dfoo692 =
(source_id__h58657 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo624 ;
assign _dfoo693 =
source_id__h58657 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo557 ;
assign _dfoo694 =
(source_id__h58657 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo626 ;
assign _dfoo695 =
source_id__h58657 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo559 ;
assign _dfoo696 =
(source_id__h58657 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo628 ;
assign _dfoo697 =
source_id__h58657 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo561 ;
assign _dfoo698 =
(source_id__h58657 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo630 ;
assign _dfoo699 =
source_id__h58657 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo563 ;
assign _dfoo7 =
source_id__h73617 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo70 =
(source_id__h72121 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo2 ;
assign _dfoo700 =
(source_id__h58657 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo632 ;
assign _dfoo701 =
source_id__h58657 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo565 ;
assign _dfoo702 =
(source_id__h58657 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo634 ;
assign _dfoo703 =
source_id__h58657 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo567 ;
assign _dfoo704 =
(source_id__h58657 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo636 ;
assign _dfoo705 =
source_id__h58657 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo569 ;
assign _dfoo706 =
(source_id__h58657 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo638 ;
assign _dfoo707 =
source_id__h58657 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo571 ;
assign _dfoo708 =
(source_id__h58657 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo640 ;
assign _dfoo709 =
source_id__h58657 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo573 ;
assign _dfoo710 =
(source_id__h58657 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo642 ;
assign _dfoo711 =
source_id__h58657 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo575 ;
assign _dfoo712 =
(source_id__h58657 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo644 ;
assign _dfoo713 =
source_id__h58657 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo577 ;
assign _dfoo714 =
(source_id__h58657 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo646 ;
assign _dfoo715 =
source_id__h58657 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo579 ;
assign _dfoo716 =
(source_id__h58657 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo648 ;
assign _dfoo717 =
source_id__h58657 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo581 ;
assign _dfoo718 =
(source_id__h58657 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo650 ;
assign _dfoo719 =
source_id__h58657 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo583 ;
assign _dfoo72 =
(source_id__h72121 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo4 ;
assign _dfoo720 =
(source_id__h58657 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo652 ;
assign _dfoo721 =
source_id__h58657 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo585 ;
assign _dfoo722 =
(source_id__h58657 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo654 ;
assign _dfoo723 =
source_id__h58657 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo587 ;
assign _dfoo724 =
(source_id__h58657 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo656 ;
assign _dfoo725 =
source_id__h58657 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo589 ;
assign _dfoo726 =
(source_id__h58657 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo658 ;
assign _dfoo727 =
source_id__h58657 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo591 ;
assign _dfoo728 =
(source_id__h58657 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo660 ;
assign _dfoo729 =
source_id__h58657 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo593 ;
assign _dfoo730 =
(source_id__h58657 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo662 ;
assign _dfoo731 =
source_id__h58657 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo595 ;
assign _dfoo732 =
(source_id__h58657 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo664 ;
assign _dfoo733 =
source_id__h58657 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo597 ;
assign _dfoo734 =
(source_id__h58657 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo666 ;
assign _dfoo735 =
source_id__h58657 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo599 ;
assign _dfoo736 =
(source_id__h58657 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo668 ;
assign _dfoo737 =
source_id__h58657 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo601 ;
assign _dfoo738 =
(source_id__h58657 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo670 ;
assign _dfoo739 =
source_id__h58657 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo603 ;
assign _dfoo74 =
(source_id__h72121 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo6 ;
assign _dfoo740 =
(source_id__h58657 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo672 ;
assign _dfoo741 =
source_id__h58657 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo605 ;
assign _dfoo742 =
(source_id__h58657 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo674 ;
assign _dfoo743 =
source_id__h58657 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo607 ;
assign _dfoo744 =
(source_id__h58657 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo676 ;
assign _dfoo745 =
source_id__h58657 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo609 ;
assign _dfoo746 =
(source_id__h58657 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo678 ;
assign _dfoo747 =
source_id__h58657 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo611 ;
assign _dfoo748 =
(source_id__h58657 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo680 ;
assign _dfoo750 =
(source_id__h57161 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo682 ;
assign _dfoo752 =
(source_id__h57161 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo684 ;
assign _dfoo754 =
(source_id__h57161 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo686 ;
assign _dfoo756 =
(source_id__h57161 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo688 ;
assign _dfoo758 =
(source_id__h57161 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo690 ;
assign _dfoo76 =
(source_id__h72121 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo8 ;
assign _dfoo760 =
(source_id__h57161 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo692 ;
assign _dfoo762 =
(source_id__h57161 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo694 ;
assign _dfoo764 =
(source_id__h57161 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo696 ;
assign _dfoo766 =
(source_id__h57161 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo698 ;
assign _dfoo768 =
(source_id__h57161 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo700 ;
assign _dfoo770 =
(source_id__h57161 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo702 ;
assign _dfoo772 =
(source_id__h57161 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo704 ;
assign _dfoo774 =
(source_id__h57161 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo706 ;
assign _dfoo776 =
(source_id__h57161 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo708 ;
assign _dfoo778 =
(source_id__h57161 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo710 ;
assign _dfoo78 =
(source_id__h72121 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo10 ;
assign _dfoo780 =
(source_id__h57161 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo712 ;
assign _dfoo782 =
(source_id__h57161 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo714 ;
assign _dfoo784 =
(source_id__h57161 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo716 ;
assign _dfoo786 =
(source_id__h57161 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo718 ;
assign _dfoo788 =
(source_id__h57161 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo720 ;
assign _dfoo790 =
(source_id__h57161 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo722 ;
assign _dfoo792 =
(source_id__h57161 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo724 ;
assign _dfoo794 =
(source_id__h57161 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo726 ;
assign _dfoo796 =
(source_id__h57161 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo728 ;
assign _dfoo798 =
(source_id__h57161 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo730 ;
assign _dfoo8 =
(source_id__h73617 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo80 =
(source_id__h72121 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo12 ;
assign _dfoo800 =
(source_id__h57161 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo732 ;
assign _dfoo802 =
(source_id__h57161 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo734 ;
assign _dfoo804 =
(source_id__h57161 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo736 ;
assign _dfoo806 =
(source_id__h57161 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo738 ;
assign _dfoo808 =
(source_id__h57161 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo740 ;
assign _dfoo810 =
(source_id__h57161 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo742 ;
assign _dfoo812 =
(source_id__h57161 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo744 ;
assign _dfoo814 =
(source_id__h57161 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo746 ;
assign _dfoo816 =
(source_id__h57161 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo748 ;
assign _dfoo817 =
source_id__h55665 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo681 ;
assign _dfoo818 =
(source_id__h55665 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo750 ;
assign _dfoo819 =
source_id__h55665 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo683 ;
assign _dfoo82 =
(source_id__h72121 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo14 ;
assign _dfoo820 =
(source_id__h55665 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo752 ;
assign _dfoo821 =
source_id__h55665 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo685 ;
assign _dfoo822 =
(source_id__h55665 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo754 ;
assign _dfoo823 =
source_id__h55665 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo687 ;
assign _dfoo824 =
(source_id__h55665 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo756 ;
assign _dfoo825 =
source_id__h55665 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo689 ;
assign _dfoo826 =
(source_id__h55665 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo758 ;
assign _dfoo827 =
source_id__h55665 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo691 ;
assign _dfoo828 =
(source_id__h55665 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo760 ;
assign _dfoo829 =
source_id__h55665 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo693 ;
assign _dfoo830 =
(source_id__h55665 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo762 ;
assign _dfoo831 =
source_id__h55665 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo695 ;
assign _dfoo832 =
(source_id__h55665 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo764 ;
assign _dfoo833 =
source_id__h55665 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo697 ;
assign _dfoo834 =
(source_id__h55665 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo766 ;
assign _dfoo835 =
source_id__h55665 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo699 ;
assign _dfoo836 =
(source_id__h55665 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo768 ;
assign _dfoo837 =
source_id__h55665 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo701 ;
assign _dfoo838 =
(source_id__h55665 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo770 ;
assign _dfoo839 =
source_id__h55665 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo703 ;
assign _dfoo84 =
(source_id__h72121 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo16 ;
assign _dfoo840 =
(source_id__h55665 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo772 ;
assign _dfoo841 =
source_id__h55665 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo705 ;
assign _dfoo842 =
(source_id__h55665 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo774 ;
assign _dfoo843 =
source_id__h55665 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo707 ;
assign _dfoo844 =
(source_id__h55665 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo776 ;
assign _dfoo845 =
source_id__h55665 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo709 ;
assign _dfoo846 =
(source_id__h55665 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo778 ;
assign _dfoo847 =
source_id__h55665 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo711 ;
assign _dfoo848 =
(source_id__h55665 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo780 ;
assign _dfoo849 =
source_id__h55665 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo713 ;
assign _dfoo850 =
(source_id__h55665 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo782 ;
assign _dfoo851 =
source_id__h55665 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo715 ;
assign _dfoo852 =
(source_id__h55665 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo784 ;
assign _dfoo853 =
source_id__h55665 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo717 ;
assign _dfoo854 =
(source_id__h55665 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo786 ;
assign _dfoo855 =
source_id__h55665 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo719 ;
assign _dfoo856 =
(source_id__h55665 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo788 ;
assign _dfoo857 =
source_id__h55665 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo721 ;
assign _dfoo858 =
(source_id__h55665 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo790 ;
assign _dfoo859 =
source_id__h55665 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo723 ;
assign _dfoo86 =
(source_id__h72121 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo18 ;
assign _dfoo860 =
(source_id__h55665 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo792 ;
assign _dfoo861 =
source_id__h55665 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo725 ;
assign _dfoo862 =
(source_id__h55665 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo794 ;
assign _dfoo863 =
source_id__h55665 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo727 ;
assign _dfoo864 =
(source_id__h55665 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo796 ;
assign _dfoo865 =
source_id__h55665 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo729 ;
assign _dfoo866 =
(source_id__h55665 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo798 ;
assign _dfoo867 =
source_id__h55665 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo731 ;
assign _dfoo868 =
(source_id__h55665 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo800 ;
assign _dfoo869 =
source_id__h55665 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo733 ;
assign _dfoo870 =
(source_id__h55665 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo802 ;
assign _dfoo871 =
source_id__h55665 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo735 ;
assign _dfoo872 =
(source_id__h55665 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo804 ;
assign _dfoo873 =
source_id__h55665 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo737 ;
assign _dfoo874 =
(source_id__h55665 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo806 ;
assign _dfoo875 =
source_id__h55665 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo739 ;
assign _dfoo876 =
(source_id__h55665 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo808 ;
assign _dfoo877 =
source_id__h55665 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo741 ;
assign _dfoo878 =
(source_id__h55665 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo810 ;
assign _dfoo879 =
source_id__h55665 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo743 ;
assign _dfoo88 =
(source_id__h72121 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo20 ;
assign _dfoo880 =
(source_id__h55665 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo812 ;
assign _dfoo881 =
source_id__h55665 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo745 ;
assign _dfoo882 =
(source_id__h55665 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo814 ;
assign _dfoo883 =
source_id__h55665 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo747 ;
assign _dfoo884 =
(source_id__h55665 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo816 ;
assign _dfoo886 =
(source_id__h54169 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo818 ;
assign _dfoo888 =
(source_id__h54169 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo820 ;
assign _dfoo890 =
(source_id__h54169 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo822 ;
assign _dfoo892 =
(source_id__h54169 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo824 ;
assign _dfoo894 =
(source_id__h54169 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo826 ;
assign _dfoo896 =
(source_id__h54169 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo828 ;
assign _dfoo898 =
(source_id__h54169 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo830 ;
assign _dfoo9 =
source_id__h73617 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo90 =
(source_id__h72121 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo22 ;
assign _dfoo900 =
(source_id__h54169 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo832 ;
assign _dfoo902 =
(source_id__h54169 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo834 ;
assign _dfoo904 =
(source_id__h54169 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo836 ;
assign _dfoo906 =
(source_id__h54169 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo838 ;
assign _dfoo908 =
(source_id__h54169 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo840 ;
assign _dfoo910 =
(source_id__h54169 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo842 ;
assign _dfoo912 =
(source_id__h54169 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo844 ;
assign _dfoo914 =
(source_id__h54169 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo846 ;
assign _dfoo916 =
(source_id__h54169 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo848 ;
assign _dfoo918 =
(source_id__h54169 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo850 ;
assign _dfoo92 =
(source_id__h72121 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo24 ;
assign _dfoo920 =
(source_id__h54169 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo852 ;
assign _dfoo922 =
(source_id__h54169 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo854 ;
assign _dfoo924 =
(source_id__h54169 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo856 ;
assign _dfoo926 =
(source_id__h54169 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo858 ;
assign _dfoo928 =
(source_id__h54169 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo860 ;
assign _dfoo930 =
(source_id__h54169 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo862 ;
assign _dfoo932 =
(source_id__h54169 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo864 ;
assign _dfoo934 =
(source_id__h54169 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo866 ;
assign _dfoo936 =
(source_id__h54169 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo868 ;
assign _dfoo938 =
(source_id__h54169 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo870 ;
assign _dfoo94 =
(source_id__h72121 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo26 ;
assign _dfoo940 =
(source_id__h54169 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo872 ;
assign _dfoo942 =
(source_id__h54169 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo874 ;
assign _dfoo944 =
(source_id__h54169 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo876 ;
assign _dfoo946 =
(source_id__h54169 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo878 ;
assign _dfoo948 =
(source_id__h54169 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo880 ;
assign _dfoo950 =
(source_id__h54169 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo882 ;
assign _dfoo952 =
(source_id__h54169 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo884 ;
assign _dfoo953 =
source_id__h52673 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo817 ;
assign _dfoo954 =
(source_id__h52673 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo886 ;
assign _dfoo955 =
source_id__h52673 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo819 ;
assign _dfoo956 =
(source_id__h52673 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo888 ;
assign _dfoo957 =
source_id__h52673 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo821 ;
assign _dfoo958 =
(source_id__h52673 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo890 ;
assign _dfoo959 =
source_id__h52673 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo823 ;
assign _dfoo96 =
(source_id__h72121 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo28 ;
assign _dfoo960 =
(source_id__h52673 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo892 ;
assign _dfoo961 =
source_id__h52673 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo825 ;
assign _dfoo962 =
(source_id__h52673 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo894 ;
assign _dfoo963 =
source_id__h52673 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo827 ;
assign _dfoo964 =
(source_id__h52673 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo896 ;
assign _dfoo965 =
source_id__h52673 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo829 ;
assign _dfoo966 =
(source_id__h52673 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo898 ;
assign _dfoo967 =
source_id__h52673 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo831 ;
assign _dfoo968 =
(source_id__h52673 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo900 ;
assign _dfoo969 =
source_id__h52673 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo833 ;
assign _dfoo970 =
(source_id__h52673 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo902 ;
assign _dfoo971 =
source_id__h52673 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo835 ;
assign _dfoo972 =
(source_id__h52673 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo904 ;
assign _dfoo973 =
source_id__h52673 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo837 ;
assign _dfoo974 =
(source_id__h52673 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo906 ;
assign _dfoo975 =
source_id__h52673 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo839 ;
assign _dfoo976 =
(source_id__h52673 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo908 ;
assign _dfoo977 =
source_id__h52673 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo841 ;
assign _dfoo978 =
(source_id__h52673 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo910 ;
assign _dfoo979 =
source_id__h52673 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo843 ;
assign _dfoo98 =
(source_id__h72121 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo30 ;
assign _dfoo980 =
(source_id__h52673 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo912 ;
assign _dfoo981 =
source_id__h52673 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo845 ;
assign _dfoo982 =
(source_id__h52673 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo914 ;
assign _dfoo983 =
source_id__h52673 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo847 ;
assign _dfoo984 =
(source_id__h52673 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo916 ;
assign _dfoo985 =
source_id__h52673 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo849 ;
assign _dfoo986 =
(source_id__h52673 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo918 ;
assign _dfoo987 =
source_id__h52673 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo851 ;
assign _dfoo988 =
(source_id__h52673 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo920 ;
assign _dfoo989 =
source_id__h52673 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo853 ;
assign _dfoo990 =
(source_id__h52673 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo922 ;
assign _dfoo991 =
source_id__h52673 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo855 ;
assign _dfoo992 =
(source_id__h52673 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo924 ;
assign _dfoo993 =
source_id__h52673 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo857 ;
assign _dfoo994 =
(source_id__h52673 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo926 ;
assign _dfoo995 =
source_id__h52673 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo859 ;
assign _dfoo996 =
(source_id__h52673 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo928 ;
assign _dfoo997 =
source_id__h52673 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo861 ;
assign _dfoo998 =
(source_id__h52673 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo930 ;
assign _dfoo999 =
source_id__h52673 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo863 ;
assign a__h81740 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3066 ?
m_vrg_source_prio_16 :
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3062 ;
assign a__h83894 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3160 ?
m_vrg_source_prio_16 :
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3156 ;
assign addr_offset__h13465 =
m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ;
assign addr_offset__h27245 =
m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ;
assign b__h81741 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3066 ?
5'd16 :
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3082 ;
assign b__h83895 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3160 ?
5'd16 :
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3176 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 =
addr_offset__h13465 < 64'h0000000000003000 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 =
addr_offset__h13465[11:7] <= 5'd1 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 =
m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 =
addr_offset__h13465 < 64'h0000000000001000 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 =
addr_offset__h13465[11:2] <= 10'd16 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
addr_offset__h13465[11:2] != 10'd0 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 &&
m_cfg_verbosity != 4'd0 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 =
addr_offset__h13465[16:12] <= 5'd1 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 =
addr_offset__h13465 < 64'h0000000000002000 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 =
source_id_base__h13893 <= 10'd16 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 =
addr_offset__h27245[16:12] <= 5'd1 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2860 =
addr_offset__h27245[16:12] == 5'd0 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2857 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2862 =
addr_offset__h27245[16:12] == 5'd1 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2857 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 =
m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 =
addr_offset__h27245 < 64'h0000000000001000 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 =
addr_offset__h27245[11:2] <= 10'd16 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d837 =
addr_offset__h27245[11:2] == 10'd1 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d839 =
addr_offset__h27245[11:2] == 10'd2 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d841 =
addr_offset__h27245[11:2] == 10'd3 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d843 =
addr_offset__h27245[11:2] == 10'd4 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d845 =
addr_offset__h27245[11:2] == 10'd5 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d847 =
addr_offset__h27245[11:2] == 10'd6 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d849 =
addr_offset__h27245[11:2] == 10'd7 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d851 =
addr_offset__h27245[11:2] == 10'd8 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d853 =
addr_offset__h27245[11:2] == 10'd9 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d855 =
addr_offset__h27245[11:2] == 10'd10 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d857 =
addr_offset__h27245[11:2] == 10'd11 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d859 =
addr_offset__h27245[11:2] == 10'd12 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d861 =
addr_offset__h27245[11:2] == 10'd13 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d863 =
addr_offset__h27245[11:2] == 10'd14 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d865 =
addr_offset__h27245[11:2] == 10'd15 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d867 =
addr_offset__h27245[11:2] == 10'd16 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d869 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
addr_offset__h27245[11:2] != 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 &&
m_cfg_verbosity != 4'd0 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 =
addr_offset__h27245 < 64'h0000000000002000 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 =
source_id_base__h28620 <= 10'd16 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 =
addr_offset__h27245 < 64'h0000000000003000 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 =
addr_offset__h27245[11:7] <= 5'd1 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 =
addr_offset__h27245[11:7] == 5'd0 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d892 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 =
addr_offset__h27245[11:7] == 5'd1 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d892 ;
assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3036 =
m_vrg_source_ip_10 &&
m_vrg_source_prio_10 >
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3032 &&
m_vvrg_ie_0_10 ;
assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3130 =
m_vrg_source_ip_10 &&
m_vrg_source_prio_10 >
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3126 &&
m_vvrg_ie_1_10 ;
assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 =
m_vrg_source_ip_10 &&
m_vrg_source_prio_10 >
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ;
assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3041 =
m_vrg_source_ip_11 &&
m_vrg_source_prio_11 >
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3037 &&
m_vvrg_ie_0_11 ;
assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3135 =
m_vrg_source_ip_11 &&
m_vrg_source_prio_11 >
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3131 &&
m_vvrg_ie_1_11 ;
assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 =
m_vrg_source_ip_11 &&
m_vrg_source_prio_11 >
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ;
assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3046 =
m_vrg_source_ip_12 &&
m_vrg_source_prio_12 >
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3042 &&
m_vvrg_ie_0_12 ;
assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3140 =
m_vrg_source_ip_12 &&
m_vrg_source_prio_12 >
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3136 &&
m_vvrg_ie_1_12 ;
assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 =
m_vrg_source_ip_12 &&
m_vrg_source_prio_12 >
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ;
assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3051 =
m_vrg_source_ip_13 &&
m_vrg_source_prio_13 >
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3047 &&
m_vvrg_ie_0_13 ;
assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3145 =
m_vrg_source_ip_13 &&
m_vrg_source_prio_13 >
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3141 &&
m_vvrg_ie_1_13 ;
assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 =
m_vrg_source_ip_13 &&
m_vrg_source_prio_13 >
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ;
assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d686 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ||
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ||
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ||
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ||
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ||
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ||
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d680 ;
assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3056 =
m_vrg_source_ip_14 &&
m_vrg_source_prio_14 >
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3052 &&
m_vvrg_ie_0_14 ;
assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3150 =
m_vrg_source_ip_14 &&
m_vrg_source_prio_14 >
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3146 &&
m_vvrg_ie_1_14 ;
assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 =
m_vrg_source_ip_14 &&
m_vrg_source_prio_14 >
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ;
assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3061 =
m_vrg_source_ip_15 &&
m_vrg_source_prio_15 >
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3057 &&
m_vvrg_ie_0_15 ;
assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3155 =
m_vrg_source_ip_15 &&
m_vrg_source_prio_15 >
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3151 &&
m_vvrg_ie_1_15 ;
assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 =
m_vrg_source_ip_15 &&
m_vrg_source_prio_15 >
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ;
assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3066 =
m_vrg_source_ip_16 &&
m_vrg_source_prio_16 >
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3062 &&
m_vvrg_ie_0_16 ;
assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3160 =
m_vrg_source_ip_16 &&
m_vrg_source_prio_16 >
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3156 &&
m_vvrg_ie_1_16 ;
assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 =
m_vrg_source_ip_16 &&
!m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ;
assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d689 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ||
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ||
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ||
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d686 ;
assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 =
m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ;
assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d2996 =
m_vrg_source_ip_2 &&
m_vrg_source_prio_2 >
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d2992 &&
m_vvrg_ie_0_2 ;
assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3090 =
m_vrg_source_ip_2 &&
m_vrg_source_prio_2 >
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3086 &&
m_vvrg_ie_1_2 ;
assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 =
m_vrg_source_ip_2 &&
m_vrg_source_prio_2 >
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ;
assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3001 =
m_vrg_source_ip_3 &&
m_vrg_source_prio_3 >
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d2997 &&
m_vvrg_ie_0_3 ;
assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3095 =
m_vrg_source_ip_3 &&
m_vrg_source_prio_3 >
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3091 &&
m_vvrg_ie_1_3 ;
assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 =
m_vrg_source_ip_3 &&
m_vrg_source_prio_3 >
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ;
assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3006 =
m_vrg_source_ip_4 &&
m_vrg_source_prio_4 >
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3002 &&
m_vvrg_ie_0_4 ;
assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3100 =
m_vrg_source_ip_4 &&
m_vrg_source_prio_4 >
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3096 &&
m_vvrg_ie_1_4 ;
assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 =
m_vrg_source_ip_4 &&
m_vrg_source_prio_4 >
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ;
assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3011 =
m_vrg_source_ip_5 &&
m_vrg_source_prio_5 >
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3007 &&
m_vvrg_ie_0_5 ;
assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3105 =
m_vrg_source_ip_5 &&
m_vrg_source_prio_5 >
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3101 &&
m_vvrg_ie_1_5 ;
assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 =
m_vrg_source_ip_5 &&
m_vrg_source_prio_5 >
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ;
assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3016 =
m_vrg_source_ip_6 &&
m_vrg_source_prio_6 >
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3012 &&
m_vvrg_ie_0_6 ;
assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3110 =
m_vrg_source_ip_6 &&
m_vrg_source_prio_6 >
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3106 &&
m_vvrg_ie_1_6 ;
assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 =
m_vrg_source_ip_6 &&
m_vrg_source_prio_6 >
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ;
assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3021 =
m_vrg_source_ip_7 &&
m_vrg_source_prio_7 >
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3017 &&
m_vvrg_ie_0_7 ;
assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3115 =
m_vrg_source_ip_7 &&
m_vrg_source_prio_7 >
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3111 &&
m_vvrg_ie_1_7 ;
assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 =
m_vrg_source_ip_7 &&
m_vrg_source_prio_7 >
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ;
assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d680 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ||
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ||
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ||
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ||
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ||
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ||
m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ;
assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3026 =
m_vrg_source_ip_8 &&
m_vrg_source_prio_8 >
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3022 &&
m_vvrg_ie_0_8 ;
assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3120 =
m_vrg_source_ip_8 &&
m_vrg_source_prio_8 >
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3116 &&
m_vvrg_ie_1_8 ;
assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 =
m_vrg_source_ip_8 &&
m_vrg_source_prio_8 >
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ;
assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3031 =
m_vrg_source_ip_9 &&
m_vrg_source_prio_9 >
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3027 &&
m_vvrg_ie_0_9 ;
assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3125 =
m_vrg_source_ip_9 &&
m_vrg_source_prio_9 >
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3121 &&
m_vvrg_ie_1_9 ;
assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 =
m_vrg_source_ip_9 &&
m_vrg_source_prio_9 >
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ;
assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 =
m_vrg_source_prio_16 <=
(m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ?
m_vrg_source_prio_15 :
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ;
assign max_id__h24210 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ?
5'd16 :
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ;
assign rdata___1__h26714 = { rdata__h26520[31:0], 32'h0 } ;
assign rdata__h26520 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ?
64'd0 :
y_avValue_fst__h26512 ;
assign rresp__h26521 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ?
2'b11 :
y_avValue_snd__h26513 ;
assign source_id__h15937 = { addr_offset__h13465[4:0], 5'd31 } ;
assign source_id__h16044 = { addr_offset__h13465[4:0], 5'd30 } ;
assign source_id__h16117 = { addr_offset__h13465[4:0], 5'd29 } ;
assign source_id__h16190 = { addr_offset__h13465[4:0], 5'd28 } ;
assign source_id__h16263 = { addr_offset__h13465[4:0], 5'd27 } ;
assign source_id__h16336 = { addr_offset__h13465[4:0], 5'd26 } ;
assign source_id__h16409 = { addr_offset__h13465[4:0], 5'd25 } ;
assign source_id__h16482 = { addr_offset__h13465[4:0], 5'd24 } ;
assign source_id__h16555 = { addr_offset__h13465[4:0], 5'd23 } ;
assign source_id__h16628 = { addr_offset__h13465[4:0], 5'd22 } ;
assign source_id__h16701 = { addr_offset__h13465[4:0], 5'd21 } ;
assign source_id__h16774 = { addr_offset__h13465[4:0], 5'd20 } ;
assign source_id__h16847 = { addr_offset__h13465[4:0], 5'd19 } ;
assign source_id__h16920 = { addr_offset__h13465[4:0], 5'd18 } ;
assign source_id__h16993 = { addr_offset__h13465[4:0], 5'd17 } ;
assign source_id__h17066 = { addr_offset__h13465[4:0], 5'd16 } ;
assign source_id__h17139 = { addr_offset__h13465[4:0], 5'd15 } ;
assign source_id__h17212 = { addr_offset__h13465[4:0], 5'd14 } ;
assign source_id__h17285 = { addr_offset__h13465[4:0], 5'd13 } ;
assign source_id__h17358 = { addr_offset__h13465[4:0], 5'd12 } ;
assign source_id__h17431 = { addr_offset__h13465[4:0], 5'd11 } ;
assign source_id__h17504 = { addr_offset__h13465[4:0], 5'd10 } ;
assign source_id__h17577 = { addr_offset__h13465[4:0], 5'd9 } ;
assign source_id__h17650 = { addr_offset__h13465[4:0], 5'd8 } ;
assign source_id__h17723 = { addr_offset__h13465[4:0], 5'd7 } ;
assign source_id__h17796 = { addr_offset__h13465[4:0], 5'd6 } ;
assign source_id__h17869 = { addr_offset__h13465[4:0], 5'd5 } ;
assign source_id__h17942 = { addr_offset__h13465[4:0], 5'd4 } ;
assign source_id__h18015 = { addr_offset__h13465[4:0], 5'd3 } ;
assign source_id__h18088 = { addr_offset__h13465[4:0], 5'd2 } ;
assign source_id__h18161 = { addr_offset__h13465[4:0], 5'd1 } ;
assign source_id__h20405 = 10'd31 + source_id_base__h13893 ;
assign source_id__h20581 = 10'd30 + source_id_base__h13893 ;
assign source_id__h20689 = 10'd29 + source_id_base__h13893 ;
assign source_id__h20797 = 10'd28 + source_id_base__h13893 ;
assign source_id__h20905 = 10'd27 + source_id_base__h13893 ;
assign source_id__h21013 = 10'd26 + source_id_base__h13893 ;
assign source_id__h21121 = 10'd25 + source_id_base__h13893 ;
assign source_id__h21229 = 10'd24 + source_id_base__h13893 ;
assign source_id__h21337 = 10'd23 + source_id_base__h13893 ;
assign source_id__h21445 = 10'd22 + source_id_base__h13893 ;
assign source_id__h21553 = 10'd21 + source_id_base__h13893 ;
assign source_id__h21661 = 10'd20 + source_id_base__h13893 ;
assign source_id__h21769 = 10'd19 + source_id_base__h13893 ;
assign source_id__h21877 = 10'd18 + source_id_base__h13893 ;
assign source_id__h21985 = 10'd17 + source_id_base__h13893 ;
assign source_id__h22093 = 10'd16 + source_id_base__h13893 ;
assign source_id__h22201 = 10'd15 + source_id_base__h13893 ;
assign source_id__h22309 = 10'd14 + source_id_base__h13893 ;
assign source_id__h22417 = 10'd13 + source_id_base__h13893 ;
assign source_id__h22525 = 10'd12 + source_id_base__h13893 ;
assign source_id__h22633 = 10'd11 + source_id_base__h13893 ;
assign source_id__h22741 = 10'd10 + source_id_base__h13893 ;
assign source_id__h22849 = 10'd9 + source_id_base__h13893 ;
assign source_id__h22957 = 10'd8 + source_id_base__h13893 ;
assign source_id__h23065 = 10'd7 + source_id_base__h13893 ;
assign source_id__h23173 = 10'd6 + source_id_base__h13893 ;
assign source_id__h23281 = 10'd5 + source_id_base__h13893 ;
assign source_id__h23389 = 10'd4 + source_id_base__h13893 ;
assign source_id__h23497 = 10'd3 + source_id_base__h13893 ;
assign source_id__h23605 = 10'd2 + source_id_base__h13893 ;
assign source_id__h23713 = 10'd1 + source_id_base__h13893 ;
assign source_id__h30233 = { addr_offset__h27245[4:0], 5'd1 } ;
assign source_id__h31729 = { addr_offset__h27245[4:0], 5'd2 } ;
assign source_id__h33225 = { addr_offset__h27245[4:0], 5'd3 } ;
assign source_id__h34721 = { addr_offset__h27245[4:0], 5'd4 } ;
assign source_id__h36217 = { addr_offset__h27245[4:0], 5'd5 } ;
assign source_id__h37713 = { addr_offset__h27245[4:0], 5'd6 } ;
assign source_id__h39209 = { addr_offset__h27245[4:0], 5'd7 } ;
assign source_id__h40705 = { addr_offset__h27245[4:0], 5'd8 } ;
assign source_id__h42201 = { addr_offset__h27245[4:0], 5'd9 } ;
assign source_id__h43697 = { addr_offset__h27245[4:0], 5'd10 } ;
assign source_id__h45193 = { addr_offset__h27245[4:0], 5'd11 } ;
assign source_id__h46689 = { addr_offset__h27245[4:0], 5'd12 } ;
assign source_id__h48185 = { addr_offset__h27245[4:0], 5'd13 } ;
assign source_id__h49681 = { addr_offset__h27245[4:0], 5'd14 } ;
assign source_id__h51177 = { addr_offset__h27245[4:0], 5'd15 } ;
assign source_id__h52673 = { addr_offset__h27245[4:0], 5'd16 } ;
assign source_id__h54169 = { addr_offset__h27245[4:0], 5'd17 } ;
assign source_id__h55665 = { addr_offset__h27245[4:0], 5'd18 } ;
assign source_id__h57161 = { addr_offset__h27245[4:0], 5'd19 } ;
assign source_id__h58657 = { addr_offset__h27245[4:0], 5'd20 } ;
assign source_id__h60153 = { addr_offset__h27245[4:0], 5'd21 } ;
assign source_id__h61649 = { addr_offset__h27245[4:0], 5'd22 } ;
assign source_id__h63145 = { addr_offset__h27245[4:0], 5'd23 } ;
assign source_id__h64641 = { addr_offset__h27245[4:0], 5'd24 } ;
assign source_id__h66137 = { addr_offset__h27245[4:0], 5'd25 } ;
assign source_id__h67633 = { addr_offset__h27245[4:0], 5'd26 } ;
assign source_id__h69129 = { addr_offset__h27245[4:0], 5'd27 } ;
assign source_id__h70625 = { addr_offset__h27245[4:0], 5'd28 } ;
assign source_id__h72121 = { addr_offset__h27245[4:0], 5'd29 } ;
assign source_id__h73617 = { addr_offset__h27245[4:0], 5'd30 } ;
assign source_id__h75113 = { addr_offset__h27245[4:0], 5'd31 } ;
assign source_id_base__h13893 = { addr_offset__h13465[4:0], 5'h0 } ;
assign source_id_base__h28620 = { addr_offset__h27245[4:0], 5'h0 } ;
assign v__h13689 = { 61'd0, x__h13769 } ;
assign v__h13934 = { 32'd0, v_ip__h13937 } ;
assign v__h18403 = { 32'd0, v_ie__h18406 } ;
assign v__h24016 = { 61'd0, x__h24096 } ;
assign v__h24251 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d689 ?
v__h25556 :
64'd0 ;
assign v__h25556 = { 59'd0, max_id__h24210 } ;
assign v__h27250 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ?
2'b11 :
v__h27435 ;
assign v__h27435 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 ?
v__h27448 :
v__h28425 ;
assign v__h27448 =
(addr_offset__h27245[11:2] != 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823) ?
2'b0 :
2'b10 ;
assign v__h28425 =
(!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874) ?
v__h28444 :
v__h28597 ;
assign v__h28444 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 ?
2'b0 :
2'b10 ;
assign v__h28597 =
(!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888) ?
v__h28616 :
v__h76713 ;
assign v__h28616 =
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889) ?
2'b0 :
2'b10 ;
assign v__h76750 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 ?
2'b0 :
2'b10 ;
assign v_ie__h18406 =
{ source_id__h20405 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1,
source_id__h20581 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2,
source_id__h20689 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3,
source_id__h20797 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4,
source_id__h20905 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5,
source_id__h21013 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6,
source_id__h21121 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7,
source_id__h21229 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8,
source_id__h21337 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9,
source_id__h21445 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10,
source_id__h21553 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11,
source_id__h21661 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12,
source_id__h21769 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13,
source_id__h21877 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14,
source_id__h21985 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15,
source_id__h22093 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16,
source_id__h22201 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17,
source_id__h22309 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18,
source_id__h22417 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19,
source_id__h22525 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20,
source_id__h22633 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21,
source_id__h22741 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22,
source_id__h22849 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23,
source_id__h22957 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24,
source_id__h23065 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25,
source_id__h23173 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26,
source_id__h23281 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27,
source_id__h23389 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28,
source_id__h23497 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29,
source_id__h23605 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30,
source_id__h23713 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ;
assign v_ip__h13937 =
{ source_id__h15937 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98,
source_id__h16044 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102,
source_id__h16117 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107,
source_id__h16190 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111,
source_id__h16263 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116,
source_id__h16336 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120,
source_id__h16409 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125,
source_id__h16482 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129,
source_id__h16555 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134,
source_id__h16628 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138,
source_id__h16701 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143,
source_id__h16774 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147,
source_id__h16847 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152,
source_id__h16920 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156,
source_id__h16993 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161,
source_id__h17066 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165,
source_id__h17139 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170,
source_id__h17212 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174,
source_id__h17285 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179,
source_id__h17358 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183,
source_id__h17431 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188,
source_id__h17504 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192,
source_id__h17577 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197,
source_id__h17650 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201,
source_id__h17723 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206,
source_id__h17796 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210,
source_id__h17869 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215,
source_id__h17942 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219,
source_id__h18015 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224,
source_id__h18088 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228,
source_id__h18161 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ;
assign wdata32__h27246 =
(addr_offset__h27245[2:0] == 3'd4) ?
m_slave_xactor_f_wr_data$D_OUT[72:41] :
m_slave_xactor_f_wr_data$D_OUT[40:9] ;
assign x__h23928 =
{ addr_offset__h13465[31:16], 4'd0, addr_offset__h13465[11:0] } ;
assign x__h26677 =
(addr_offset__h13465[2:0] == 3'd4) ?
rdata___1__h26714 :
rdata__h26520 ;
assign x__h76716 =
{ addr_offset__h27245[31:16], 4'd0, addr_offset__h27245[11:0] } ;
assign y_avValue_fst__h26433 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ?
v__h24251 :
64'd0 ;
assign y_avValue_fst__h26445 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ?
v__h24016 :
64'd0 ;
assign y_avValue_fst__h26461 =
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ?
v__h18403 :
64'd0 ;
assign y_avValue_fst__h26477 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ?
v__h13934 :
64'd0 ;
assign y_avValue_fst__h26482 =
(!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ?
y_avValue_fst__h26461 :
y_avValue_fst__h26466 ;
assign y_avValue_fst__h26493 =
(addr_offset__h13465[11:2] != 10'd0 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ?
v__h13689 :
64'd0 ;
assign y_avValue_fst__h26498 =
(!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ?
y_avValue_fst__h26477 :
y_avValue_fst__h26482 ;
assign y_avValue_fst__h26512 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ?
y_avValue_fst__h26493 :
y_avValue_fst__h26498 ;
assign y_avValue_snd__h26446 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ?
2'b0 :
2'b10 ;
assign y_avValue_snd__h26462 =
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ?
2'b0 :
2'b10 ;
assign y_avValue_snd__h26478 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ?
2'b0 :
2'b10 ;
assign y_avValue_snd__h26483 =
(!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ?
y_avValue_snd__h26462 :
y_avValue_snd__h26467 ;
assign y_avValue_snd__h26494 =
(addr_offset__h13465[11:2] != 10'd0 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ?
2'b0 :
2'b10 ;
assign y_avValue_snd__h26499 =
(!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ?
y_avValue_snd__h26478 :
y_avValue_snd__h26483 ;
assign y_avValue_snd__h26513 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ?
y_avValue_snd__h26494 :
y_avValue_snd__h26499 ;
always@(addr_offset__h13465 or
m_vrg_source_prio_0 or
m_vrg_source_prio_1 or
m_vrg_source_prio_2 or
m_vrg_source_prio_3 or
m_vrg_source_prio_4 or
m_vrg_source_prio_5 or
m_vrg_source_prio_6 or
m_vrg_source_prio_7 or
m_vrg_source_prio_8 or
m_vrg_source_prio_9 or
m_vrg_source_prio_10 or
m_vrg_source_prio_11 or
m_vrg_source_prio_12 or
m_vrg_source_prio_13 or
m_vrg_source_prio_14 or
m_vrg_source_prio_15 or m_vrg_source_prio_16)
begin
case (addr_offset__h13465[11:2])
10'd0: x__h13769 = m_vrg_source_prio_0;
10'd1: x__h13769 = m_vrg_source_prio_1;
10'd2: x__h13769 = m_vrg_source_prio_2;
10'd3: x__h13769 = m_vrg_source_prio_3;
10'd4: x__h13769 = m_vrg_source_prio_4;
10'd5: x__h13769 = m_vrg_source_prio_5;
10'd6: x__h13769 = m_vrg_source_prio_6;
10'd7: x__h13769 = m_vrg_source_prio_7;
10'd8: x__h13769 = m_vrg_source_prio_8;
10'd9: x__h13769 = m_vrg_source_prio_9;
10'd10: x__h13769 = m_vrg_source_prio_10;
10'd11: x__h13769 = m_vrg_source_prio_11;
10'd12: x__h13769 = m_vrg_source_prio_12;
10'd13: x__h13769 = m_vrg_source_prio_13;
10'd14: x__h13769 = m_vrg_source_prio_14;
10'd15: x__h13769 = m_vrg_source_prio_15;
10'd16: x__h13769 = m_vrg_source_prio_16;
default: x__h13769 = 3'b010 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
m_vrg_target_threshold_0 or m_vrg_target_threshold_1)
begin
case (addr_offset__h13465[16:12])
5'd0: x__h24096 = m_vrg_target_threshold_0;
5'd1: x__h24096 = m_vrg_target_threshold_1;
default: x__h24096 = 3'b010 /* unspecified value */ ;
endcase
end
always@(source_id_base__h13893 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id_base__h13893)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20581 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h20581)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20405 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h20405)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20405 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h20405)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20581 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h20581)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h15937 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h15937)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20689 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h20689)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20689 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h20689)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20797 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h20797)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16044 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16044)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20797 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h20797)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20905 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h20905)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20905 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h20905)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21013 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21013)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21013 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21013)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16117 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16117)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16190 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16190)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21121 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21121)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21121 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21121)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21229 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21229)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16263 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16263)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21229 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21229)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16336 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16336)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21337 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21337)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21337 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21337)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21445 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21445)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16409 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16409)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21445 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21445)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16482 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16482)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21553 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21553)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21553 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21553)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21661 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21661)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16555 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16555)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21661 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21661)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16628 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16628)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21769 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21769)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21769 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21769)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21877 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21877)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16701 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16701)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21877 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21877)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17358 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17358)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16774 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16774)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21985 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21985)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21985 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21985)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22093 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22093)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16847 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16847)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22093 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22093)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16920 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16920)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22201 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22201)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22201 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22201)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22309 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22309)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16993 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16993)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22309 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22309)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17066 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17066)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22417 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22417)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22417 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22417)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22525 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22525)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17139 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17139)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22525 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22525)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17212 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17212)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22633 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22633)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22633 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22633)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22741 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22741)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17285 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17285)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22741 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22741)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22849 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22849)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22849 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22849)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22957 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22957)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17431 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17431)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22957 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22957)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17504 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17504)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23065 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23065)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23065 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23065)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23173 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23173)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17577 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17577)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23173 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23173)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17650 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17650)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23281 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23281)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23281 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23281)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23389 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23389)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17723 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17723)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23389 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23389)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17796 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17796)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23497 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23497)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23497 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23497)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23605 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23605)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17869 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17869)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23605 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23605)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17942 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17942)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23713 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23713)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23713 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23713)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id_base__h13893 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id_base__h13893)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h18015 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h18015)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id_base__h13893 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id_base__h13893)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h18088 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h18088)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h18161 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h18161)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
1'b0 /* unspecified value */ ;
endcase
end
always@(x__h23928 or y_avValue_snd__h26446)
begin
case (x__h23928)
32'h00200000, 32'h00200004:
y_avValue_snd__h26467 = y_avValue_snd__h26446;
default: y_avValue_snd__h26467 = 2'b10;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 =
m_vvrg_ie_0_1;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 =
m_vvrg_ie_1_1;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 =
m_vvrg_ie_0_2;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 =
m_vvrg_ie_1_2;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 =
m_vvrg_ie_0_3;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 =
m_vvrg_ie_1_3;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 =
m_vvrg_ie_0_4;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 =
m_vvrg_ie_1_4;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 =
m_vvrg_ie_0_5;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 =
m_vvrg_ie_1_5;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 =
m_vvrg_ie_0_6;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 =
m_vvrg_ie_1_6;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 =
m_vvrg_ie_0_7;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 =
m_vvrg_ie_1_7;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 =
m_vvrg_ie_0_8;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 =
m_vvrg_ie_1_8;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 =
m_vvrg_ie_0_9;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 =
m_vvrg_ie_1_9;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 =
m_vvrg_ie_0_10;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 =
m_vvrg_ie_1_10;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 =
m_vvrg_ie_0_11;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 =
m_vvrg_ie_1_11;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 =
m_vvrg_ie_0_12;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 =
m_vvrg_ie_1_12;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 =
m_vvrg_ie_0_13;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 =
m_vvrg_ie_1_13;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 =
m_vvrg_ie_0_14;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 =
m_vvrg_ie_1_14;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 =
m_vvrg_ie_0_15;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 =
m_vvrg_ie_1_15;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 =
m_vvrg_ie_0_16;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 =
m_vvrg_ie_1_16;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 =
1'b0 /* unspecified value */ ;
endcase
end
always@(x__h23928 or y_avValue_fst__h26445 or y_avValue_fst__h26433)
begin
case (x__h23928)
32'h00200000: y_avValue_fst__h26466 = y_avValue_fst__h26445;
32'h00200004: y_avValue_fst__h26466 = y_avValue_fst__h26433;
default: y_avValue_fst__h26466 = 64'd0;
endcase
end
always@(x__h76716 or v__h76750)
begin
case (x__h76716)
32'h00200000, 32'h00200004: v__h76713 = v__h76750;
default: v__h76713 = 2'b10;
endcase
end
always@(wdata32__h27246 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (wdata32__h27246[9:0])
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
1'b0 /* unspecified value */ ;
endcase
end
always@(wdata32__h27246 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (wdata32__h27246[9:0])
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h27245 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876)
begin
case (addr_offset__h27245[16:12])
5'd0:
SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875;
5'd1:
SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876;
default: SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878 =
1'b0 /* unspecified value */ ;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY 3'd7;
m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY 3'd7;
m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (m_cfg_verbosity$EN)
m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN;
if (m_vrg_source_busy_0$EN)
m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_0$D_IN;
if (m_vrg_source_busy_1$EN)
m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_1$D_IN;
if (m_vrg_source_busy_10$EN)
m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_10$D_IN;
if (m_vrg_source_busy_11$EN)
m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_11$D_IN;
if (m_vrg_source_busy_12$EN)
m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_12$D_IN;
if (m_vrg_source_busy_13$EN)
m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_13$D_IN;
if (m_vrg_source_busy_14$EN)
m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_14$D_IN;
if (m_vrg_source_busy_15$EN)
m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_15$D_IN;
if (m_vrg_source_busy_16$EN)
m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_16$D_IN;
if (m_vrg_source_busy_2$EN)
m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_2$D_IN;
if (m_vrg_source_busy_3$EN)
m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_3$D_IN;
if (m_vrg_source_busy_4$EN)
m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_4$D_IN;
if (m_vrg_source_busy_5$EN)
m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_5$D_IN;
if (m_vrg_source_busy_6$EN)
m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_6$D_IN;
if (m_vrg_source_busy_7$EN)
m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_7$D_IN;
if (m_vrg_source_busy_8$EN)
m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_8$D_IN;
if (m_vrg_source_busy_9$EN)
m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_9$D_IN;
if (m_vrg_source_ip_0$EN)
m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_0$D_IN;
if (m_vrg_source_ip_1$EN)
m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_1$D_IN;
if (m_vrg_source_ip_10$EN)
m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_10$D_IN;
if (m_vrg_source_ip_11$EN)
m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_11$D_IN;
if (m_vrg_source_ip_12$EN)
m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_12$D_IN;
if (m_vrg_source_ip_13$EN)
m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_13$D_IN;
if (m_vrg_source_ip_14$EN)
m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_14$D_IN;
if (m_vrg_source_ip_15$EN)
m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_15$D_IN;
if (m_vrg_source_ip_16$EN)
m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_16$D_IN;
if (m_vrg_source_ip_2$EN)
m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_2$D_IN;
if (m_vrg_source_ip_3$EN)
m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_3$D_IN;
if (m_vrg_source_ip_4$EN)
m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_4$D_IN;
if (m_vrg_source_ip_5$EN)
m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_5$D_IN;
if (m_vrg_source_ip_6$EN)
m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_6$D_IN;
if (m_vrg_source_ip_7$EN)
m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_7$D_IN;
if (m_vrg_source_ip_8$EN)
m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_8$D_IN;
if (m_vrg_source_ip_9$EN)
m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_9$D_IN;
if (m_vrg_source_prio_0$EN)
m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_0$D_IN;
if (m_vrg_source_prio_1$EN)
m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_1$D_IN;
if (m_vrg_source_prio_10$EN)
m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_10$D_IN;
if (m_vrg_source_prio_11$EN)
m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_11$D_IN;
if (m_vrg_source_prio_12$EN)
m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_12$D_IN;
if (m_vrg_source_prio_13$EN)
m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_13$D_IN;
if (m_vrg_source_prio_14$EN)
m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_14$D_IN;
if (m_vrg_source_prio_15$EN)
m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_15$D_IN;
if (m_vrg_source_prio_16$EN)
m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_16$D_IN;
if (m_vrg_source_prio_2$EN)
m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_2$D_IN;
if (m_vrg_source_prio_3$EN)
m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_3$D_IN;
if (m_vrg_source_prio_4$EN)
m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_4$D_IN;
if (m_vrg_source_prio_5$EN)
m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_5$D_IN;
if (m_vrg_source_prio_6$EN)
m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_6$D_IN;
if (m_vrg_source_prio_7$EN)
m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_7$D_IN;
if (m_vrg_source_prio_8$EN)
m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_8$D_IN;
if (m_vrg_source_prio_9$EN)
m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_9$D_IN;
if (m_vrg_target_threshold_0$EN)
m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY
m_vrg_target_threshold_0$D_IN;
if (m_vrg_target_threshold_1$EN)
m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY
m_vrg_target_threshold_1$D_IN;
if (m_vvrg_ie_0_0$EN)
m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_0$D_IN;
if (m_vvrg_ie_0_1$EN)
m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_1$D_IN;
if (m_vvrg_ie_0_10$EN)
m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_10$D_IN;
if (m_vvrg_ie_0_11$EN)
m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_11$D_IN;
if (m_vvrg_ie_0_12$EN)
m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_12$D_IN;
if (m_vvrg_ie_0_13$EN)
m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_13$D_IN;
if (m_vvrg_ie_0_14$EN)
m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_14$D_IN;
if (m_vvrg_ie_0_15$EN)
m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_15$D_IN;
if (m_vvrg_ie_0_16$EN)
m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_16$D_IN;
if (m_vvrg_ie_0_2$EN)
m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_2$D_IN;
if (m_vvrg_ie_0_3$EN)
m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_3$D_IN;
if (m_vvrg_ie_0_4$EN)
m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_4$D_IN;
if (m_vvrg_ie_0_5$EN)
m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_5$D_IN;
if (m_vvrg_ie_0_6$EN)
m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_6$D_IN;
if (m_vvrg_ie_0_7$EN)
m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_7$D_IN;
if (m_vvrg_ie_0_8$EN)
m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_8$D_IN;
if (m_vvrg_ie_0_9$EN)
m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_9$D_IN;
if (m_vvrg_ie_1_0$EN)
m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_0$D_IN;
if (m_vvrg_ie_1_1$EN)
m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_1$D_IN;
if (m_vvrg_ie_1_10$EN)
m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_10$D_IN;
if (m_vvrg_ie_1_11$EN)
m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_11$D_IN;
if (m_vvrg_ie_1_12$EN)
m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_12$D_IN;
if (m_vvrg_ie_1_13$EN)
m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_13$D_IN;
if (m_vvrg_ie_1_14$EN)
m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_14$D_IN;
if (m_vvrg_ie_1_15$EN)
m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_15$D_IN;
if (m_vvrg_ie_1_16$EN)
m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_16$D_IN;
if (m_vvrg_ie_1_2$EN)
m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_2$D_IN;
if (m_vvrg_ie_1_3$EN)
m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_3$D_IN;
if (m_vvrg_ie_1_4$EN)
m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_4$D_IN;
if (m_vvrg_ie_1_5$EN)
m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_5$D_IN;
if (m_vvrg_ie_1_6$EN)
m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_6$D_IN;
if (m_vvrg_ie_1_7$EN)
m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_7$D_IN;
if (m_vvrg_ie_1_8$EN)
m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_8$D_IN;
if (m_vvrg_ie_1_9$EN)
m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_9$D_IN;
end
if (m_rg_addr_base$EN)
m_rg_addr_base <= `BSV_ASSIGNMENT_DELAY m_rg_addr_base$D_IN;
if (m_rg_addr_lim$EN)
m_rg_addr_lim <= `BSV_ASSIGNMENT_DELAY m_rg_addr_lim$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_cfg_verbosity = 4'hA;
m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA;
m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA;
m_vrg_source_busy_0 = 1'h0;
m_vrg_source_busy_1 = 1'h0;
m_vrg_source_busy_10 = 1'h0;
m_vrg_source_busy_11 = 1'h0;
m_vrg_source_busy_12 = 1'h0;
m_vrg_source_busy_13 = 1'h0;
m_vrg_source_busy_14 = 1'h0;
m_vrg_source_busy_15 = 1'h0;
m_vrg_source_busy_16 = 1'h0;
m_vrg_source_busy_2 = 1'h0;
m_vrg_source_busy_3 = 1'h0;
m_vrg_source_busy_4 = 1'h0;
m_vrg_source_busy_5 = 1'h0;
m_vrg_source_busy_6 = 1'h0;
m_vrg_source_busy_7 = 1'h0;
m_vrg_source_busy_8 = 1'h0;
m_vrg_source_busy_9 = 1'h0;
m_vrg_source_ip_0 = 1'h0;
m_vrg_source_ip_1 = 1'h0;
m_vrg_source_ip_10 = 1'h0;
m_vrg_source_ip_11 = 1'h0;
m_vrg_source_ip_12 = 1'h0;
m_vrg_source_ip_13 = 1'h0;
m_vrg_source_ip_14 = 1'h0;
m_vrg_source_ip_15 = 1'h0;
m_vrg_source_ip_16 = 1'h0;
m_vrg_source_ip_2 = 1'h0;
m_vrg_source_ip_3 = 1'h0;
m_vrg_source_ip_4 = 1'h0;
m_vrg_source_ip_5 = 1'h0;
m_vrg_source_ip_6 = 1'h0;
m_vrg_source_ip_7 = 1'h0;
m_vrg_source_ip_8 = 1'h0;
m_vrg_source_ip_9 = 1'h0;
m_vrg_source_prio_0 = 3'h2;
m_vrg_source_prio_1 = 3'h2;
m_vrg_source_prio_10 = 3'h2;
m_vrg_source_prio_11 = 3'h2;
m_vrg_source_prio_12 = 3'h2;
m_vrg_source_prio_13 = 3'h2;
m_vrg_source_prio_14 = 3'h2;
m_vrg_source_prio_15 = 3'h2;
m_vrg_source_prio_16 = 3'h2;
m_vrg_source_prio_2 = 3'h2;
m_vrg_source_prio_3 = 3'h2;
m_vrg_source_prio_4 = 3'h2;
m_vrg_source_prio_5 = 3'h2;
m_vrg_source_prio_6 = 3'h2;
m_vrg_source_prio_7 = 3'h2;
m_vrg_source_prio_8 = 3'h2;
m_vrg_source_prio_9 = 3'h2;
m_vrg_target_threshold_0 = 3'h2;
m_vrg_target_threshold_1 = 3'h2;
m_vvrg_ie_0_0 = 1'h0;
m_vvrg_ie_0_1 = 1'h0;
m_vvrg_ie_0_10 = 1'h0;
m_vvrg_ie_0_11 = 1'h0;
m_vvrg_ie_0_12 = 1'h0;
m_vvrg_ie_0_13 = 1'h0;
m_vvrg_ie_0_14 = 1'h0;
m_vvrg_ie_0_15 = 1'h0;
m_vvrg_ie_0_16 = 1'h0;
m_vvrg_ie_0_2 = 1'h0;
m_vvrg_ie_0_3 = 1'h0;
m_vvrg_ie_0_4 = 1'h0;
m_vvrg_ie_0_5 = 1'h0;
m_vvrg_ie_0_6 = 1'h0;
m_vvrg_ie_0_7 = 1'h0;
m_vvrg_ie_0_8 = 1'h0;
m_vvrg_ie_0_9 = 1'h0;
m_vvrg_ie_1_0 = 1'h0;
m_vvrg_ie_1_1 = 1'h0;
m_vvrg_ie_1_10 = 1'h0;
m_vvrg_ie_1_11 = 1'h0;
m_vvrg_ie_1_12 = 1'h0;
m_vvrg_ie_1_13 = 1'h0;
m_vvrg_ie_1_14 = 1'h0;
m_vvrg_ie_1_15 = 1'h0;
m_vvrg_ie_1_16 = 1'h0;
m_vvrg_ie_1_2 = 1'h0;
m_vvrg_ie_1_3 = 1'h0;
m_vvrg_ie_1_4 = 1'h0;
m_vvrg_ie_1_5 = 1'h0;
m_vvrg_ie_1_6 = 1'h0;
m_vvrg_ie_1_7 = 1'h0;
m_vvrg_ie_1_8 = 1'h0;
m_vvrg_ie_1_9 = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $display("----------------");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write("Src IPs :");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_2);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_3);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_4);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_5);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_6);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_8);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_9);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_10);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_12);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_13);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_14);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_15);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_16);
if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write("Src Prios:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_2);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_3);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_4);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_5);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_6);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_8);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_9);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_10);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_12);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_13);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_14);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_15);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_16);
if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write("Src busy :");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_2);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_3);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_4);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_5);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_6);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_8);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_9);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_10);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_12);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_13);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_14);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_15);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_16);
if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_2);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_3);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_4);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_5);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_6);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_8);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_9);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_10);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_12);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_13);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_14);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_15);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_16);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state)
$display(" MaxPri %0d, Thresh %0d, MaxId %0d",
a__h81740,
m_vrg_target_threshold_0,
b__h81741);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_2);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_3);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_4);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_5);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_6);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_8);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_9);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_10);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_12);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_13);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_14);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_15);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_16);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state)
$display(" MaxPri %0d, Thresh %0d, MaxId %0d",
a__h83894,
m_vrg_target_threshold_1,
b__h83895);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_1_974_213_AND_NOT_m_cfg__ETC___d3217)
begin
v__h86248 = $stime;
#0;
end
v__h86242 = v__h86248 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_1_974_213_AND_NOT_m_cfg__ETC___d3217)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h86242,
$signed(32'd1),
v_sources_0_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_2_975_220_AND_NOT_m_cfg__ETC___d3224)
begin
v__h86443 = $stime;
#0;
end
v__h86437 = v__h86443 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_2_975_220_AND_NOT_m_cfg__ETC___d3224)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h86437,
$signed(32'd2),
v_sources_1_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_3_976_228_AND_NOT_m_cfg__ETC___d3232)
begin
v__h86638 = $stime;
#0;
end
v__h86632 = v__h86638 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_3_976_228_AND_NOT_m_cfg__ETC___d3232)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h86632,
$signed(32'd3),
v_sources_2_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_4_977_236_AND_NOT_m_cfg__ETC___d3240)
begin
v__h86833 = $stime;
#0;
end
v__h86827 = v__h86833 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_4_977_236_AND_NOT_m_cfg__ETC___d3240)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h86827,
$signed(32'd4),
v_sources_3_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_5_978_244_AND_NOT_m_cfg__ETC___d3248)
begin
v__h87028 = $stime;
#0;
end
v__h87022 = v__h87028 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_5_978_244_AND_NOT_m_cfg__ETC___d3248)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87022,
$signed(32'd5),
v_sources_4_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_6_979_252_AND_NOT_m_cfg__ETC___d3256)
begin
v__h87223 = $stime;
#0;
end
v__h87217 = v__h87223 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_6_979_252_AND_NOT_m_cfg__ETC___d3256)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87217,
$signed(32'd6),
v_sources_5_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_7_980_260_AND_NOT_m_cfg__ETC___d3264)
begin
v__h87418 = $stime;
#0;
end
v__h87412 = v__h87418 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_7_980_260_AND_NOT_m_cfg__ETC___d3264)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87412,
$signed(32'd7),
v_sources_6_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_8_981_268_AND_NOT_m_cfg__ETC___d3272)
begin
v__h87613 = $stime;
#0;
end
v__h87607 = v__h87613 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_8_981_268_AND_NOT_m_cfg__ETC___d3272)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87607,
$signed(32'd8),
v_sources_7_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_9_982_276_AND_NOT_m_cfg__ETC___d3280)
begin
v__h87808 = $stime;
#0;
end
v__h87802 = v__h87808 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_9_982_276_AND_NOT_m_cfg__ETC___d3280)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87802,
$signed(32'd9),
v_sources_8_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_10_983_284_AND_NOT_m_cfg_ETC___d3288)
begin
v__h88003 = $stime;
#0;
end
v__h87997 = v__h88003 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_10_983_284_AND_NOT_m_cfg_ETC___d3288)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87997,
$signed(32'd10),
v_sources_9_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_11_984_292_AND_NOT_m_cfg_ETC___d3296)
begin
v__h88198 = $stime;
#0;
end
v__h88192 = v__h88198 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_11_984_292_AND_NOT_m_cfg_ETC___d3296)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h88192,
$signed(32'd11),
v_sources_10_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_12_985_300_AND_NOT_m_cfg_ETC___d3304)
begin
v__h88393 = $stime;
#0;
end
v__h88387 = v__h88393 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_12_985_300_AND_NOT_m_cfg_ETC___d3304)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h88387,
$signed(32'd12),
v_sources_11_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_13_986_308_AND_NOT_m_cfg_ETC___d3312)
begin
v__h88588 = $stime;
#0;
end
v__h88582 = v__h88588 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_13_986_308_AND_NOT_m_cfg_ETC___d3312)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h88582,
$signed(32'd13),
v_sources_12_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_14_987_316_AND_NOT_m_cfg_ETC___d3320)
begin
v__h88783 = $stime;
#0;
end
v__h88777 = v__h88783 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_14_987_316_AND_NOT_m_cfg_ETC___d3320)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h88777,
$signed(32'd14),
v_sources_13_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_15_988_324_AND_NOT_m_cfg_ETC___d3328)
begin
v__h88978 = $stime;
#0;
end
v__h88972 = v__h88978 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_15_988_324_AND_NOT_m_cfg_ETC___d3328)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h88972,
$signed(32'd15),
v_sources_14_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_16_989_332_AND_NOT_m_cfg_ETC___d3336)
begin
v__h89173 = $stime;
#0;
end
v__h89167 = v__h89173 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_16_989_332_AND_NOT_m_cfg_ETC___d3336)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h89167,
$signed(32'd16),
v_sources_15_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0)
begin
v__h5962 = $stime;
#0;
end
v__h5956 = v__h5962 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0)
$display("%0d: PLIC.rl_reset", v__h5956);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
begin
v__h13331 = $stime;
#0;
end
v__h13325 = v__h13331 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$display("%0d: PLIC.rl_process_rd_req:", v__h13325);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
begin
v__h13514 = $stime;
#0;
end
v__h13508 = v__h13514 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr",
v__h13508);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43)
begin
v__h13730 = $stime;
#0;
end
v__h13724 = v__h13730 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43)
$display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h",
v__h13724,
addr_offset__h13465[11:2],
v__h13689);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74)
begin
v__h13976 = $stime;
#0;
end
v__h13970 = v__h13976 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74)
$display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h",
v__h13970,
source_id_base__h13893,
v__h13934);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248)
begin
v__h18445 = $stime;
#0;
end
v__h18439 = v__h18445 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248)
$display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h",
v__h18439,
source_id_base__h13893,
v__h18403);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538)
begin
v__h24057 = $stime;
#0;
end
v__h24051 = v__h24057 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538)
$display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h",
v__h24051,
addr_offset__h13465[16:12],
v__h24016);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d733)
begin
v__h26355 = $stime;
#0;
end
v__h26349 = v__h26355 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d733)
$display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h",
v__h26349,
addr_offset__h13465[16:12],
v__h24251);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
begin
v__h26568 = $stime;
#0;
end
v__h26562 = v__h26568 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr",
v__h26562);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
begin
v__h26773 = $stime;
#0;
end
v__h26767 = v__h26773 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$display("%0d: PLIC.rl_process_rd_req", v__h26767);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", x__h26677);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", rresp__h26521);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
begin
v__h27053 = $stime;
#0;
end
v__h27047 = v__h27053 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$display("%0d: PLIC.rl_process_wr_req", v__h27047);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16 &&
m_slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16 &&
!m_slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
begin
v__h27284 = $stime;
#0;
end
v__h27278 = v__h27284 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr",
v__h27278);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d869)
begin
v__h28359 = $stime;
#0;
end
v__h28353 = v__h28359 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d869)
$display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h",
v__h28353,
addr_offset__h27245[11:2],
wdata32__h27246);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d880)
begin
v__h28531 = $stime;
#0;
end
v__h28525 = v__h28531 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d880)
$display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d",
v__h28525,
source_id_base__h28620);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2844)
begin
v__h76647 = $stime;
#0;
end
v__h76641 = v__h76647 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2844)
$display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h",
v__h76641,
addr_offset__h27245[11:7],
source_id_base__h28620,
wdata32__h27246);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2868)
begin
v__h76947 = $stime;
#0;
end
v__h76941 = v__h76947 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2868)
$display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h",
v__h76941,
addr_offset__h27245[16:12],
wdata32__h27246);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2923)
begin
v__h77579 = $stime;
#0;
end
v__h77573 = v__h77579 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2923)
$display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h",
v__h77573,
addr_offset__h27245[16:12],
wdata32__h27246[9:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2935)
begin
v__h77673 = $stime;
#0;
end
v__h77667 = v__h77673 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2935)
$display("%0d: PLIC.rl_process_wr_req: ignoring completion for target %0d for source 0x%0h",
v__h77667,
addr_offset__h27245[16:12],
wdata32__h27246[9:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
begin
v__h77844 = $stime;
#0;
end
v__h77838 = v__h77844 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr",
v__h77838);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952) &&
m_slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952) &&
!m_slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
begin
v__h78064 = $stime;
#0;
end
v__h78058 = v__h78064 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$display("%0d: PLIC.AXI4.rl_process_wr_req", v__h78058);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16 &&
m_slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16 &&
!m_slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", v__h27250);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0)
begin
v__h85245 = $stime;
#0;
end
v__h85239 = v__h85245 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0)
$display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned",
v__h85239,
set_addr_map_addr_base);
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0)
begin
v__h85351 = $stime;
#0;
end
v__h85345 = v__h85351 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0)
$display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned",
v__h85345,
set_addr_map_addr_lim);
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && m_cfg_verbosity != 4'd0)
begin
v__h85478 = $stime;
#0;
end
v__h85472 = v__h85478 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && m_cfg_verbosity != 4'd0)
$display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h",
v__h85472,
set_addr_map_addr_base,
set_addr_map_addr_lim);
end
// synopsys translate_on
endmodule // mkPLIC_16_2_7
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for lfsr_crc32
*/
module test_lfsr_crc32;
// Parameters
parameter LFSR_WIDTH = 32;
parameter LFSR_POLY = 32'h4c11db7;
parameter LFSR_CONFIG = "GALOIS";
parameter LFSR_FEED_FORWARD = 0;
parameter REVERSE = 1;
parameter DATA_WIDTH = 8;
parameter STYLE = "AUTO";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg [LFSR_WIDTH-1:0] state_in = 0;
// Outputs
wire [DATA_WIDTH-1:0] data_out = 0;
wire [LFSR_WIDTH-1:0] state_out;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
data_in,
state_in
);
$to_myhdl(
data_out,
state_out
);
// dump file
$dumpfile("test_lfsr_crc32.lxt");
$dumpvars(0, test_lfsr_crc32);
end
lfsr #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_CONFIG(LFSR_CONFIG),
.LFSR_FEED_FORWARD(LFSR_FEED_FORWARD),
.REVERSE(REVERSE),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
UUT (
.data_in(data_in),
.state_in(state_in),
.data_out(data_out),
.state_out(state_out)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pipe_wrapper.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_pipe_wrapper.v
// Description : PIPE Wrapper for 7 Series Transceiver
// Version : 20.2
//------------------------------------------------------------------------------
//---------- PIPE Wrapper Hierarchy --------------------------------------------
// pipe_wrapper.v
// pipe_clock.v
// pipe_reset.v or gtp_pipe_reset.v
// qpll_reset.v
// * Generate GTXE2_CHANNEL for every lane.
// pipe_user.v
// pipe_rate.v or gtp_pipe_rate.v
// pipe_sync.v
// pipe_drp.v or gtp_pipe_drp.v
// pipe_eq.v
// rxeq_scan.v
// gt_wrapper.v
// GTXE2_CHANNEL or GTHE2_CHANNEL or GTPE2_CHANNEL
// GTXE2_COMMON or GTHE2_COMMON or GTPE2_CHANNEL
// * Generate GTXE2_COMMON for every quad.
// qpll_drp.v
// qpll_wrapper.v
//------------------------------------------------------------------------------
//---------- PIPE Wrapper Parameter Encoding -----------------------------------
// PCIE_SIM_MODE : "FALSE" = Normal mode (default)
// : "TRUE" = Simulation only
// PCIE_SIM_TX_EIDLE_DRIVE_LEVEL : "0", "1" (default), "X" simulation TX electrical idle drive level
// PCIE_GT_DEVICE : "GTX" (default)
// : "GTH"
// : "GTP"
// PCIE_USE_MODE : "1.0" = GTX IES 325T or GTP IES/GES use mode.
// : "1.1" = GTX IES 485T use mode.
// : "2.0" = GTH IES 690T use mode for 1.0 silicon.
// : "2.1" = GTH GES 690T use mode for 1.2 and 2.0 silicon. SW model use "2.0"
// : "3.0" = GTX GES 325T or 485T use mode (default).
// PCIE_PLL_SEL : "CPLL" (default)
// : "QPLL"
// PCIE_AUX_CDR_GEN3_EN : "FALSE" Use Primary CDR for Gen3 only (GTH 2.0)
// : "TRUE" Use AUX CDR for Gen3 only (default) (GTH 2.0)
// PCIE_LPM_DFE : "DFE" for Gen1/Gen2 only (GTX, GTH)
// : "LPM" for Gen1/Gen2 only (default) (GTX, GTH)
// PCIE_LPM_DFE_GEN3 : "DFE" for Gen3 only (GTX, GTH)
// : "LPM" for Gen3 only (default) (GTX, GTH)
// PCIE_EXT_CLK : "FALSE" = Use internal clock module(default)
// : "TRUE" = Use external clock module
// PCIE_POWER_SAVING : "FALSE" = Disable PLL power saving
// : "TRUE" = Enable PLL power saving (default)
// PCIE_ASYNC_EN : "FALSE" = Synchronous mode (default)
// : "TRUE" = Asynchronous mode.
// PCIE_TXBUF_EN : "FALSE" = TX buffer bypass for Gen1/Gen2 only (default)
// : "TRUE" = TX buffer use for Gen1/Gen2 only (for debug only)
// PCIE_RXBUF_EN : "FALSE" = RX buffer bypass for Gen3 only (not supported)
// : "TRUE" = RX buffer use for Gen3 only (default)
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default) (GTX, GTH)
// : 1 = Auto TX sync (GTH)
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default) (GTX, GTH)
// : 1 = Auto RX sync (GTH)
// PCIE_CHAN_BOND : 0 = One-Hop (default)
// : 1 = Daisy-Chain
// : 2 = Binary-Tree
// PCIE_CHAN_BOND_EN : "FALSE" = Channel bonding disable for Gen1/Gen2 only
// : "TRUE" = Channel bonding enable for Gen1/Gen2 only
// PCIE_LANE : 1 (default), 2, 4, or 8
// PCIE_LINK_SPEED : 1 = PCIe Gen1 Mode
// : 2 = PCIe Gen1/Gen2 Mode (default)
// : 3 = PCIe Gen1/Gen2/Gen3 Mode
// PCIE_REFCLK_FREQ : 0 = 100 MHz (default)
// : 1 = 125 MHz
// : 2 = 250 MHz
// PCIE_USERCLK[1/2]_FREQ : 0 = Disable user clock
// : 1 = 31.25 MHz
// : 2 = 62.50 MHz (default)
// : 3 = 125.00 MHz
// : 4 = 250.00 MHz
// : 5 = 500.00 MHz
// PCIE_TX_EIDLE_ASSERT_DELAY : 3'd0 to 3'd7 (default = 3'd4)
// PCIE_RXEQ_MODE_GEN3 : 0 = Return same TX coefficients
// : 1 = Return TX preset #5
// PCIE_OOBCLK_MODE : 0 = Reference clock
// : 1 = 62.50 MHz (default)
// : 2 = 50.00 MHz (requires 1 BUFG)
// PCIE_JTAG_MODE : 0 = Normal operation (default)
// : 1 = JTAG mode (for debug only)
// PCIE_DEBUG_MODE : 0 = Normal operation (default)
// : 1 = Debug mode (for debug only)
//------------------------------------------------------------------------------
//---------- Notes -------------------------------------------------------------
// Notes within the PIPE Wrapper RTL files are for internal use only.
// Data Width : This PIPE Wrapper supports a 32-bit [TX/RX]DATA interface.
// In Gen1/Gen2 modes, only 16-bits [15:0] are used.
// In Gen3 mode, all 32-bits are used.
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Wrapper ------------------------------------------------------
module pcie3_7x_0_pipe_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 (GTX/GTH) only
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR for Gen3 (GTH 2.0) only
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
parameter PCIE_EXT_CLK = "FALSE", // PCIe external clock
parameter PCIE_EXT_GT_COMMON = "FALSE", // PCIe external GT COMMON
parameter EXT_CH_GT_DRP = "FALSE", // PCIe external CH DRP
parameter TX_MARGIN_FULL_0 = 7'b1001111, // 1000 mV
parameter TX_MARGIN_FULL_1 = 7'b1001110, // 950 mV
parameter TX_MARGIN_FULL_2 = 7'b1001101, // 900 mV
parameter TX_MARGIN_FULL_3 = 7'b1001100, // 850 mV
parameter TX_MARGIN_FULL_4 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_0 = 7'b1000101, // 500 mV
parameter TX_MARGIN_LOW_1 = 7'b1000110 , // 450 mV
parameter TX_MARGIN_LOW_2 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_3 = 7'b1000010 , // 350 mV
parameter TX_MARGIN_LOW_4 = 7'b1000000 ,
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_CHAN_BOND = 1, // PCIe channel bonding mode
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter PCIE_JTAG_MODE = 0, // PCIe JTAG mode
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
)
//--------------------------------------
( // Gen1/Gen2 | Gen3
//--------------------------------------
//---------- PIPE Clock & Reset Ports ------------------
input PIPE_CLK, // Reference clock that drives MMCM
input PIPE_RESET_N, // PCLK | PCLK
output PIPE_PCLK, // Drives [TX/RX]USRCLK in Gen1/Gen2
// Drives TXUSRCLK in Gen3
// Drives RXUSRCLK in Gen3 async mode only
//---------- PIPE TX Data Ports ------------------------
input [(PCIE_LANE*32)-1:0]PIPE_TXDATA, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXDATAK, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_TXP, // Serial data
output [PCIE_LANE-1:0] PIPE_TXN, // Serial data
//---------- PIPE RX Data Ports ------------------------
input [PCIE_LANE-1:0] PIPE_RXP, // Serial data
input [PCIE_LANE-1:0] PIPE_RXN, // Serial data
output [(PCIE_LANE*32)-1:0]PIPE_RXDATA, // PCLK | RXUSRCLK
output [(PCIE_LANE*4)-1:0] PIPE_RXDATAK, // PCLK | RXUSRCLK
//---------- PIPE Command Ports ------------------------
input PIPE_TXDETECTRX, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXELECIDLE, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXCOMPLIANCE, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXPOLARITY, // PCLK | RXUSRCLK
input [(PCIE_LANE*2)-1:0] PIPE_POWERDOWN, // PCLK | PCLK
input [ 1:0] PIPE_RATE, // PCLK | PCLK
//---------- PIPE Electrical Command Ports -------------
input [ 2:0] PIPE_TXMARGIN, // Async | Async
input PIPE_TXSWING, // Async | Async
input [PCIE_LANE-1:0] PIPE_TXDEEMPH, // Async/PCLK | Async/PCLK
input [(PCIE_LANE*2)-1:0] PIPE_TXEQ_CONTROL, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET_DEFAULT,// PCLK | PCLK
input [(PCIE_LANE*6)-1:0] PIPE_TXEQ_DEEMPH, // PCLK | PCLK
input [(PCIE_LANE*2)-1:0] PIPE_RXEQ_CONTROL, // PCLK | PCLK
input [(PCIE_LANE*3)-1:0] PIPE_RXEQ_PRESET, // PCLK | PCLK
input [(PCIE_LANE*6)-1:0] PIPE_RXEQ_LFFS, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_RXEQ_TXPRESET, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_EN, // PCLK | PCLK
input [(PCIE_LANE*18)-1:0]PIPE_RXEQ_USER_TXCOEFF, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_MODE, // PCLK | PCLK
output [ 5:0] PIPE_TXEQ_FS, // Async | Async
output [ 5:0] PIPE_TXEQ_LF, // Async | Async
output [(PCIE_LANE*18)-1:0]PIPE_TXEQ_COEFF, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_TXEQ_DONE, // PCLK | PCLK
output [(PCIE_LANE*18)-1:0]PIPE_RXEQ_NEW_TXCOEFF, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_LFFS_SEL, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_ADAPT_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_CONVERGE, // PCLK | PCLK
//---------- PIPE Status Ports -------------------------
output [PCIE_LANE-1:0] PIPE_RXVALID, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_PHYSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_PHYSTATUS_RST, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXELECIDLE, // Async | Async
output [PCIE_LANE-1:0] PIPE_EYESCANDATAERROR, // Async | Async
output [(PCIE_LANE*3)-1:0] PIPE_RXSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXPMARESETDONE, // Async | Async
output [(PCIE_LANE*3)-1:0] PIPE_RXBUFSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_TXPHALIGNDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_TXPHINITDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_TXDLYSRESETDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXPHALIGNDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXDLYSRESETDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXSYNCDONE, // PCLK | RXUSRCLK
output [(PCIE_LANE*8)-1:0] PIPE_RXDISPERR, // PCLK | RXUSRCLK
output [(PCIE_LANE*8)-1:0] PIPE_RXNOTINTABLE, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXCOMMADET, // PCLK | RXUSRCLK
//---------- PIPE User Ports ---------------------------
input PIPE_MMCM_RST_N, // Async | Async
input [PCIE_LANE-1:0] PIPE_RXSLIDE, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_CPLL_LOCK, // Async | Async
output [(PCIE_LANE-1)>>2:0]PIPE_QPLL_LOCK, // Async | Async
output PIPE_PCLK_LOCK, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXCDRLOCK, // Async | Async
output PIPE_USERCLK1, // Optional user clock
output PIPE_USERCLK2, // Optional user clock
output PIPE_RXUSRCLK, // RXUSRCLK
// Equivalent to PCLK in Gen1/Gen2
// Equivalent to RXOUTCLK[0] in Gen3
output [PCIE_LANE-1:0] PIPE_RXOUTCLK, // RX recovered clock (for debug only)
output [PCIE_LANE-1:0] PIPE_TXSYNC_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXSYNC_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_GEN3_RDY, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXCHANISALIGNED,
output [PCIE_LANE-1:0] PIPE_ACTIVE_LANE,
// Shared Logic Internal
output INT_PCLK_OUT_SLAVE, // PCLK | PCLK
output INT_RXUSRCLK_OUT, // RXUSERCLK
output [PCIE_LANE-1:0 ] INT_RXOUTCLK_OUT, // RX recovered clock
output INT_DCLK_OUT, // DCLK | DCLK
output INT_USERCLK1_OUT, // Optional user clock
output INT_USERCLK2_OUT, // Optional user clock
output INT_OOBCLK_OUT, // OOB | OOB
output INT_MMCM_LOCK_OUT, // Async | Async
output [1:0] INT_QPLLLOCK_OUT,
output [1:0] INT_QPLLOUTCLK_OUT,
output [1:0] INT_QPLLOUTREFCLK_OUT,
input [PCIE_LANE-1:0] INT_PCLK_SEL_SLAVE,
// Shared Logic External
//---------- External Clock Ports ----------------------
input PIPE_PCLK_IN, // PCLK | PCLK
input PIPE_RXUSRCLK_IN, // RXUSERCLK
// Equivalent to PCLK in Gen1/Gen2
// Equivalent to RXOUTCLK[0] in Gen3
input [PCIE_LANE-1:0] PIPE_RXOUTCLK_IN, // RX recovered clock
input PIPE_DCLK_IN, // DCLK | DCLK
input PIPE_USERCLK1_IN, // Optional user clock
input PIPE_USERCLK2_IN, // Optional user clock
input PIPE_OOBCLK_IN, // OOB | OOB
input PIPE_MMCM_LOCK_IN, // Async | Async
output PIPE_TXOUTCLK_OUT, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXOUTCLK_OUT, // RX recovered clock (for debug only)
output [PCIE_LANE-1:0] PIPE_PCLK_SEL_OUT, // PCLK | PCLK
output PIPE_GEN3_OUT, // PCLK | PCLK
//---------- External GT COMMON Ports ----------------------
input [11:0] QPLL_DRP_CRSCODE,
input [17:0] QPLL_DRP_FSM,
input [1:0] QPLL_DRP_DONE,
input [1:0] QPLL_DRP_RESET,
input [1:0] QPLL_QPLLLOCK,
input [1:0] QPLL_QPLLOUTCLK,
input [1:0] QPLL_QPLLOUTREFCLK,
output QPLL_QPLLPD,
output [1:0] QPLL_QPLLRESET,
output QPLL_DRP_CLK,
output QPLL_DRP_RST_N,
output QPLL_DRP_OVRD,
output QPLL_DRP_GEN3,
output QPLL_DRP_START,
//---------- TRANSCEIVER DEBUG -----------------------
input [ 2:0] PIPE_TXPRBSSEL, // PCLK | PCLK
input [ 2:0] PIPE_RXPRBSSEL, // PCLK | PCLK
input PIPE_TXPRBSFORCEERR, // PCLK | PCLK
input PIPE_RXPRBSCNTRESET, // PCLK | PCLK
input [ 2:0] PIPE_LOOPBACK, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXPRBSERR, // PCLK | PCLK
output [(PCIE_LANE*6)-1:0] PIPE_TXEQ_FSM, // PCLK | PCLK
output [(PCIE_LANE*6)-1:0] PIPE_RXEQ_FSM, // PCLK | PCLK
output [((((PCIE_LANE-1)>>2)+1)*9)-1:0]PIPE_QDRP_FSM, // DCLK | DCLK
output [4:0] PIPE_RST_FSM, // PCLK | PCLK
output [11:0] PIPE_QRST_FSM, // PCLK | PCLK
output [(PCIE_LANE*5)-1:0] PIPE_RATE_FSM, // PCLK | PCLK
output [(PCIE_LANE*6)-1:0] PIPE_SYNC_FSM_TX, // PCLK | PCLK
output [(PCIE_LANE*7)-1:0] PIPE_SYNC_FSM_RX, // PCLK | PCLK
output [(PCIE_LANE*7)-1:0] PIPE_DRP_FSM, // DCLK | DCLK
output PIPE_RST_IDLE, // PCLK | PCLK
output PIPE_QRST_IDLE, // PCLK | PCLK
output PIPE_RATE_IDLE, // PCLK | PCLK
//----------- Channel DRP----------------------------
output EXT_CH_GT_DRPCLK,
input [(PCIE_LANE*9)-1:0] EXT_CH_GT_DRPADDR,
input [PCIE_LANE-1:0] EXT_CH_GT_DRPEN,
input [(PCIE_LANE*16)-1:0]EXT_CH_GT_DRPDI,
input [PCIE_LANE-1:0] EXT_CH_GT_DRPWE,
output [(PCIE_LANE*16)-1:0]EXT_CH_GT_DRPDO,
output [PCIE_LANE-1:0] EXT_CH_GT_DRPRDY,
//---------- JTAG Ports --------------------------------
input PIPE_JTAG_EN, // DCLK | DCLK
output [PCIE_LANE-1:0] PIPE_JTAG_RDY, // DCLK | DCLK
//---------- Debug Ports -------------------------------
output [PCIE_LANE-1:0] PIPE_DEBUG_0, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_1, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_2, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_3, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_4, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_5, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_6, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_7, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_8, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_9, // Async | Async
output [31:0] PIPE_DEBUG, // Async | Async
output [(PCIE_LANE*15)-1:0] PIPE_DMONITOROUT // DMONITORCLK
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg2;
//---------- PIPE Clock Module Output ------------------
wire clk_pclk;
wire clk_rxusrclk;
wire [PCIE_LANE-1:0] clk_rxoutclk;
wire clk_dclk;
wire clk_oobclk;
wire clk_mmcm_lock;
//---------- PIPE Reset Module Output ------------------
wire rst_cpllreset;
wire rst_cpllpd;
wire rst_rxusrclk_reset;
wire rst_dclk_reset;
wire rst_gtreset;
wire rst_drp_start;
wire rst_drp_x16x20_mode;
wire rst_drp_x16;
wire rst_userrdy;
wire rst_txsync_start;
wire rst_idle;
wire [4:0] rst_fsm;
//------------------------------------------------------
wire gtp_rst_qpllreset; // GTP
wire gtp_rst_qpllpd; // GTP
//---------- QPLL Reset Module Output ------------------
wire qrst_ovrd;
wire qrst_drp_start;
wire qrst_qpllreset;
wire qrst_qpllpd;
wire qrst_idle;
wire [11:0] qrst_fsm;
//------------------QPLL Reset and Power-down--------------------------------
wire [(PCIE_LANE-1)>>2:0]qpllreset;
wire qpllpd;
//---------- PIPE_JTAG Master Module Output ------------
wire [(PCIE_LANE*37)-1:0] jtag_sl_iport;
wire [(PCIE_LANE*17)-1:0] jtag_sl_oport;
//---------- PIPE User Module Output -------------------
wire [PCIE_LANE-1:0] gt_txpmareset_i;
wire [PCIE_LANE-1:0] gt_rxpmareset_i;
wire [PCIE_LANE-1:0] user_oobclk;
wire [PCIE_LANE-1:0] user_resetovrd;
wire [PCIE_LANE-1:0] user_txpmareset;
wire [PCIE_LANE-1:0] user_rxpmareset;
wire [PCIE_LANE-1:0] user_rxcdrreset;
wire [PCIE_LANE-1:0] user_rxcdrfreqreset;
wire [PCIE_LANE-1:0] user_rxdfelpmreset;
wire [PCIE_LANE-1:0] user_eyescanreset;
wire [PCIE_LANE-1:0] user_txpcsreset;
wire [PCIE_LANE-1:0] user_rxpcsreset;
wire [PCIE_LANE-1:0] user_rxbufreset;
wire [PCIE_LANE-1:0] user_resetovrd_done;
wire [PCIE_LANE-1:0] user_active_lane;
wire [PCIE_LANE-1:0] user_resetdone;
wire [PCIE_LANE-1:0] user_rxcdrlock;
wire [PCIE_LANE-1:0] user_rx_converge;
//---------- PIPE Rate Module Output -------------------
wire [PCIE_LANE-1:0] rate_cpllpd;
wire [PCIE_LANE-1:0] rate_qpllpd;
wire [PCIE_LANE-1:0] rate_cpllreset;
wire [PCIE_LANE-1:0] rate_qpllreset;
wire [PCIE_LANE-1:0] rate_txpmareset;
wire [PCIE_LANE-1:0] rate_rxpmareset;
wire [(PCIE_LANE*2)-1:0] rate_sysclksel;
wire [PCIE_LANE-1:0] rate_pclk_sel;
wire [PCIE_LANE-1:0] rate_drp_start;
wire [PCIE_LANE-1:0] rate_drp_x16x20_mode;
wire [PCIE_LANE-1:0] rate_drp_x16;
wire [PCIE_LANE-1:0] rate_gen3;
wire [(PCIE_LANE*3)-1:0] rate_rate;
wire [PCIE_LANE-1:0] rate_resetovrd_start;
wire [PCIE_LANE-1:0] rate_txsync_start;
wire [PCIE_LANE-1:0] rate_done;
wire [PCIE_LANE-1:0] rate_rxsync_start;
wire [PCIE_LANE-1:0] rate_rxsync;
wire [PCIE_LANE-1:0] rate_idle;
wire [(PCIE_LANE*5)-1:0] rate_fsm;
//---------- PIPE Sync Module Output -------------------
wire [PCIE_LANE-1:0] sync_txphdlyreset;
wire [PCIE_LANE-1:0] sync_txphalign;
wire [PCIE_LANE-1:0] sync_txphalignen;
wire [PCIE_LANE-1:0] sync_txphinit;
wire [PCIE_LANE-1:0] sync_txdlybypass;
wire [PCIE_LANE-1:0] sync_txdlysreset;
wire [PCIE_LANE-1:0] sync_txdlyen;
wire [PCIE_LANE-1:0] sync_txsync_done;
wire [(PCIE_LANE*6)-1:0] sync_fsm_tx;
wire [PCIE_LANE-1:0] sync_rxphalign;
wire [PCIE_LANE-1:0] sync_rxphalignen;
wire [PCIE_LANE-1:0] sync_rxdlybypass;
wire [PCIE_LANE-1:0] sync_rxdlysreset;
wire [PCIE_LANE-1:0] sync_rxdlyen;
wire [PCIE_LANE-1:0] sync_rxddien;
wire [PCIE_LANE-1:0] sync_rxsync_done;
wire [PCIE_LANE-1:0] sync_rxsync_donem;
wire [(PCIE_LANE*7)-1:0] sync_fsm_rx;
wire [PCIE_LANE-1:0] txdlysresetdone;
wire [PCIE_LANE-1:0] txphaligndone;
wire [PCIE_LANE-1:0] rxdlysresetdone;
wire [PCIE_LANE-1:0] rxphaligndone_s;
wire txsyncallin; // GTH
wire rxsyncallin; // GTH
//---------- PIPE DRP Module Output --------------------
wire [(PCIE_LANE*9)-1:0] drp_addr;
wire [PCIE_LANE-1:0] drp_en;
wire [(PCIE_LANE*16)-1:0]drp_di;
wire [PCIE_LANE-1:0] drp_we;
wire [PCIE_LANE-1:0] drp_done;
wire [(PCIE_LANE*7)-1:0] drp_fsm;
//---------- PIPE JTAG Slave Module Output--------------
wire [(PCIE_LANE*17)-1:0]jtag_sl_addr;
wire [PCIE_LANE-1:0] jtag_sl_den;
wire [PCIE_LANE-1:0] jtag_sl_en;
wire [(PCIE_LANE*16)-1:0]jtag_sl_di;
wire [PCIE_LANE-1:0] jtag_sl_we;
//---------- PIPE DRP MUX Output -----------------------
wire [(PCIE_LANE*9)-1:0] drp_mux_addr;
wire [PCIE_LANE-1:0] drp_mux_en;
wire [(PCIE_LANE*16)-1:0]drp_mux_di;
wire [PCIE_LANE-1:0] drp_mux_we;
//---------- PIPE EQ Module Output ---------------------
wire [PCIE_LANE-1:0] eq_txeq_deemph;
wire [(PCIE_LANE*5)-1:0] eq_txeq_precursor;
wire [(PCIE_LANE*7)-1:0] eq_txeq_maincursor;
wire [(PCIE_LANE*5)-1:0] eq_txeq_postcursor;
wire [PCIE_LANE-1:0] eq_rxeq_adapt_done;
//---------- PIPE DRP Module Output --------------------
wire [(PCIE_LANE-1)>>2:0] qdrp_done;
wire [(PCIE_LANE-1)>>2:0] qdrp_qpllreset;
wire [((((PCIE_LANE-1)>>2)+1)*6)-1:0] qdrp_crscode;
wire [((((PCIE_LANE-1)>>2)+1)*9)-1:0] qdrp_fsm;
//---------- QPLL Wrapper Output -----------------------
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutclk;
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutrefclk;
wire [(PCIE_LANE-1)>>2:0] qpll_qplllock;
//---------- GTX Wrapper Output ------------------------
wire [PCIE_LANE-1:0] gt_txoutclk;
wire [PCIE_LANE-1:0] gt_rxoutclk;
wire [PCIE_LANE-1:0] gt_cplllock;
wire [PCIE_LANE-1:0] gt_rxcdrlock;
wire [PCIE_LANE-1:0] gt_eyescandataerror;
wire [PCIE_LANE-1:0] gt_txresetdone;
wire [PCIE_LANE-1:0] gt_rxresetdone;
wire [PCIE_LANE-1:0] gt_rxpmaresetdone;
wire [(PCIE_LANE*8)-1:0] gt_rxdisperr;
wire [(PCIE_LANE*8)-1:0] gt_rxnotintable;
wire [PCIE_LANE-1:0] gt_rxvalid;
wire [PCIE_LANE-1:0] gt_phystatus;
wire [(PCIE_LANE*3)-1:0] gt_rxstatus;
wire [(PCIE_LANE*3)-1:0] gt_rxbufstatus;
wire [PCIE_LANE-1:0] gt_rxelecidle;
wire [PCIE_LANE-1:0] gt_txratedone;
wire [PCIE_LANE-1:0] gt_rxratedone;
wire [(PCIE_LANE*16)-1:0]gt_do;
wire [PCIE_LANE-1:0] gt_rdy;
wire [PCIE_LANE-1:0] gt_txphinitdone;
wire [PCIE_LANE-1:0] gt_txdlysresetdone;
wire [PCIE_LANE-1:0] gt_txphaligndone;
wire [PCIE_LANE-1:0] gt_rxdlysresetdone;
wire [PCIE_LANE:0] gt_rxphaligndone; // Custom width for calculation
wire [PCIE_LANE-1:0] gt_txsyncout; // GTH
wire [PCIE_LANE-1:0] gt_txsyncdone; // GTH
wire [PCIE_LANE-1:0] gt_rxsyncout; // GTH
wire [PCIE_LANE-1:0] gt_rxsyncdone; // GTH
wire [PCIE_LANE-1:0] gt_rxcommadet;
wire [(PCIE_LANE*4)-1:0] gt_rxchariscomma;
wire [PCIE_LANE-1:0] gt_rxbyteisaligned;
wire [PCIE_LANE-1:0] gt_rxbyterealign;
wire [ 4:0] gt_rxchbondi [PCIE_LANE:0];
wire [(PCIE_LANE*3)-1:0] gt_rxchbondlevel;
wire [ 4:0] gt_rxchbondo [PCIE_LANE:0];
wire [PCIE_LANE-1:0] rxchbonden;
wire [PCIE_LANE-1:0] rxchbondmaster;
wire [PCIE_LANE-1:0] rxchbondslave;
wire [PCIE_LANE-1:0] oobclk;
//---------- TX EQ -------------------------------------
localparam TXEQ_FS = 6'd40; // TX equalization full swing
localparam TXEQ_LF = 6'd15; // TX equalization low frequency
//---------- Select JTAG Slave Type ----------------------------------------
localparam GC_XSDB_SLAVE_TYPE = (PCIE_GT_DEVICE == "GTP") ? 16'h0400 : (PCIE_GT_DEVICE == "GTH") ? 16'h004A : 16'h0046;
//---------- Generate Per-Lane Signals -----------------
genvar i; // Index for per-lane signals
//---------- Assignments -------------------------------------------------------
assign gt_rxchbondo[0] = 5'd0; // Initialize rxchbond for lane 0
assign gt_rxphaligndone[PCIE_LANE] = 1'd1; // Mot used
assign txsyncallin = &(gt_txphaligndone | (~user_active_lane));
assign rxsyncallin = &(gt_rxphaligndone | (~user_active_lane));
//---------- Reset Synchronizer ------------------------------------------------
always @ (posedge clk_pclk or negedge PIPE_RESET_N)
begin
if (!PIPE_RESET_N)
begin
reset_n_reg1 <= 1'd0;
reset_n_reg2 <= 1'd0;
end
else
begin
reset_n_reg1 <= 1'd1;
reset_n_reg2 <= reset_n_reg1;
end
end
//---------- PIPE Clock Module -------------------------------------------------
generate
begin : pipe_clock_int
pcie3_7x_0_pipe_clock #
(
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE), // PCIe number of lanes
.PCIE_LINK_SPEED (PCIE_LINK_SPEED), // PCIe link speed
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ (PCIE_USERCLK1_FREQ), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ (PCIE_USERCLK2_FREQ), // PCIe user clock 2 frequency
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK (PIPE_CLK),
.CLK_TXOUTCLK (gt_txoutclk[0]), // Reference clock from lane 0
.CLK_RXOUTCLK_IN (gt_rxoutclk),
//.CLK_RST_N (1'b1),
.CLK_RST_N (PIPE_MMCM_RST_N), // Allow system reset for error recovery
.CLK_PCLK_SEL (rate_pclk_sel),
.CLK_PCLK_SEL_SLAVE ( INT_PCLK_SEL_SLAVE ),
.CLK_GEN3 (rate_gen3[0]),
//---------- Output ------------------------------------
.CLK_PCLK (clk_pclk),
.CLK_PCLK_SLAVE ( INT_PCLK_OUT_SLAVE),
.CLK_RXUSRCLK (clk_rxusrclk),
.CLK_RXOUTCLK_OUT (clk_rxoutclk),
.CLK_DCLK (clk_dclk),
.CLK_USERCLK1 (PIPE_USERCLK1),
.CLK_USERCLK2 (PIPE_USERCLK2),
.CLK_OOBCLK (clk_oobclk),
.CLK_MMCM_LOCK (clk_mmcm_lock)
);
assign INT_RXUSRCLK_OUT = clk_rxusrclk;
assign INT_RXOUTCLK_OUT = clk_rxoutclk;
assign INT_DCLK_OUT = clk_dclk;
assign INT_USERCLK1_OUT = PIPE_USERCLK1;
assign INT_USERCLK2_OUT = PIPE_USERCLK2;
assign INT_OOBCLK_OUT = clk_oobclk;
assign INT_MMCM_LOCK_OUT = clk_mmcm_lock;
end
endgenerate
//---------- PIPE Reset Module -------------------------------------------------
//---------- PIPE Reset Module -----------------------------------------
pcie3_7x_0_pipe_reset #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // PCIe power saving
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
pipe_reset_i
(
//---------- Input -----------------------------
.RST_CLK (clk_pclk),
.RST_RXUSRCLK (clk_rxusrclk),
.RST_DCLK (clk_dclk),
.RST_RST_N (reset_n_reg2),
.RST_DRP_DONE (drp_done),
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
.RST_CPLLLOCK (gt_cplllock),
.RST_QPLL_IDLE (qrst_idle),
.RST_RATE_IDLE (rate_idle),
.RST_RXCDRLOCK (user_rxcdrlock),
.RST_MMCM_LOCK (clk_mmcm_lock),
.RST_RESETDONE (user_resetdone),
.RST_PHYSTATUS (gt_phystatus),
.RST_TXSYNC_DONE (sync_txsync_done),
//---------- Output ----------------------------
.RST_CPLLRESET (rst_cpllreset),
.RST_CPLLPD (rst_cpllpd),
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
.RST_DCLK_RESET (rst_dclk_reset),
.RST_GTRESET (rst_gtreset),
.RST_DRP_START (rst_drp_start),
.RST_DRP_X16X20_MODE (rst_drp_x16x20_mode),
.RST_DRP_X16 (rst_drp_x16),
.RST_USERRDY (rst_userrdy),
.RST_TXSYNC_START (rst_txsync_start),
.RST_IDLE (rst_idle),
.RST_FSM (rst_fsm[4:0])
);
//---------- Default ---------------------------------------------------
assign gtp_rst_qpllreset = 1'd0;
assign gtp_rst_qpllpd = 1'd0;
//---------- QPLL Reset Module -------------------------------------------------
generate
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL"))
begin : qpll_reset
pcie3_7x_0_qpll_reset #
(
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
qpll_reset_i
(
//---------- Input ---------------------------------
.QRST_CLK (clk_pclk),
.QRST_RST_N (reset_n_reg2),
.QRST_MMCM_LOCK (clk_mmcm_lock),
.QRST_CPLLLOCK (gt_cplllock),
.QRST_DRP_DONE (qdrp_done),
.QRST_QPLLLOCK (qpll_qplllock),
.QRST_RATE (PIPE_RATE),
.QRST_QPLLRESET_IN (rate_qpllreset),
.QRST_QPLLPD_IN (rate_qpllpd),
//---------- Output --------------------------------
.QRST_OVRD (qrst_ovrd),
.QRST_DRP_START (qrst_drp_start),
.QRST_QPLLRESET_OUT (qrst_qpllreset),
.QRST_QPLLPD_OUT (qrst_qpllpd),
.QRST_IDLE (qrst_idle),
.QRST_FSM (qrst_fsm)
);
end
else
//---------- QPLL Reset Defaults ---------------------------------------
begin : qpll_reset_disable
assign qrst_ovrd = 1'd0;
assign qrst_drp_start = 1'd0;
assign qrst_qpllreset = 1'd0;
assign qrst_qpllpd = 1'd0;
assign qrst_idle = 1'd0;
assign qrst_fsm = 12'd1;
end
endgenerate
assign jtag_sl_iport = {PCIE_LANE{37'd0}};
//---------- Generate PIPE Lane ------------------------------------------------
generate for (i=0; i<PCIE_LANE; i=i+1)
begin : pipe_lane
//---------- PIPE User Module ----------------------------------------------
pcie3_7x_0_pipe_user #
(
.PCIE_USE_MODE (PCIE_USE_MODE),
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE)
)
pipe_user_i
(
//---------- Input ---------------------------------
.USER_TXUSRCLK (clk_pclk),
.USER_RXUSRCLK (clk_rxusrclk),
.USER_OOBCLK_IN (clk_oobclk),
.USER_RST_N (!rst_cpllreset),
.USER_RXUSRCLK_RST_N (!rst_rxusrclk_reset),
.USER_PCLK_SEL (rate_pclk_sel[i]),
.USER_RESETOVRD_START (rate_resetovrd_start[i]),
.USER_TXRESETDONE (gt_txresetdone[i]),
.USER_RXRESETDONE (gt_rxresetdone[i]),
.USER_TXELECIDLE (PIPE_TXELECIDLE[i]),
.USER_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
.USER_RXCDRLOCK_IN (gt_rxcdrlock[i]),
.USER_RXVALID_IN (gt_rxvalid[i]),
.USER_RXSTATUS_IN (gt_rxstatus[(3*i)+2]),
.USER_PHYSTATUS_IN (gt_phystatus[i]),
.USER_RATE_DONE (rate_done[i]),
.USER_RST_IDLE (rst_idle),
.USER_RATE_RXSYNC (rate_rxsync[i]),
.USER_RATE_IDLE (rate_idle[i]),
.USER_RATE_GEN3 (rate_gen3[i]),
.USER_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
//---------- Output --------------------------------
.USER_OOBCLK (user_oobclk[i]),
.USER_RESETOVRD (user_resetovrd[i]),
.USER_TXPMARESET (user_txpmareset[i]),
.USER_RXPMARESET (user_rxpmareset[i]),
.USER_RXCDRRESET (user_rxcdrreset[i]),
.USER_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
.USER_RXDFELPMRESET (user_rxdfelpmreset[i]),
.USER_EYESCANRESET (user_eyescanreset[i]),
.USER_TXPCSRESET (user_txpcsreset[i]),
.USER_RXPCSRESET (user_rxpcsreset[i]),
.USER_RXBUFRESET (user_rxbufreset[i]),
.USER_RESETOVRD_DONE (user_resetovrd_done[i]),
.USER_RESETDONE (user_resetdone[i]),
.USER_ACTIVE_LANE (user_active_lane[i]),
.USER_RXCDRLOCK_OUT (user_rxcdrlock[i]),
.USER_RXVALID_OUT (PIPE_RXVALID[i]),
.USER_PHYSTATUS_OUT (PIPE_PHYSTATUS[i]),
.USER_PHYSTATUS_RST (PIPE_PHYSTATUS_RST[i]),
.USER_GEN3_RDY (PIPE_GEN3_RDY[i]),
.USER_RX_CONVERGE (user_rx_converge[i])
);
//---------- PIPE Rate Module ----------------------------------------------
pcie3_7x_0_pipe_rate #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // PCIe RX buffer enable for Gen3 only
)
pipe_rate_i
(
//---------- Input ---------------------------------
.RATE_CLK (clk_pclk),
.RATE_RST_N (!rst_cpllreset),
.RATE_RST_IDLE (rst_idle),
.RATE_ACTIVE_LANE (user_active_lane[i]),
.RATE_RATE_IN (PIPE_RATE),
.RATE_CPLLLOCK (gt_cplllock[i]),
.RATE_QPLLLOCK (qpll_qplllock[i>>2]),
.RATE_MMCM_LOCK (clk_mmcm_lock),
.RATE_DRP_DONE (drp_done[i]),
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
.RATE_TXRESETDONE (gt_txresetdone[i]),
.RATE_RXRESETDONE (gt_rxresetdone[i]),
.RATE_TXRATEDONE (gt_txratedone[i]),
.RATE_RXRATEDONE (gt_rxratedone[i]),
.RATE_PHYSTATUS (gt_phystatus[i]),
.RATE_RESETOVRD_DONE (user_resetovrd_done[i]),
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
.RATE_RXSYNC_DONE (sync_rxsync_done[i]),
//---------- Output --------------------------------
.RATE_CPLLPD (rate_cpllpd[i]),
.RATE_QPLLPD (rate_qpllpd[i]),
.RATE_CPLLRESET (rate_cpllreset[i]),
.RATE_QPLLRESET (rate_qpllreset[i]),
.RATE_TXPMARESET (rate_txpmareset[i]),
.RATE_RXPMARESET (rate_rxpmareset[i]),
.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.RATE_DRP_START (rate_drp_start[i]),
.RATE_DRP_X16X20_MODE (rate_drp_x16x20_mode[i]),
.RATE_DRP_X16 (rate_drp_x16[i]),
.RATE_PCLK_SEL (rate_pclk_sel[i]),
.RATE_GEN3 (rate_gen3[i]),
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
.RATE_RESETOVRD_START (rate_resetovrd_start[i]),
.RATE_TXSYNC_START (rate_txsync_start[i]),
.RATE_DONE (rate_done[i]),
.RATE_RXSYNC_START (rate_rxsync_start[i]),
.RATE_RXSYNC (rate_rxsync[i]),
.RATE_IDLE (rate_idle[i]),
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
);
//---------- PIPE Sync Module ----------------------------------------------
pcie3_7x_0_pipe_sync #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
.PCIE_LANE (PCIE_LANE), // PCIe lane
.PCIE_LINK_SPEED (PCIE_LINK_SPEED) // PCIe link speed
)
pipe_sync_i
(
//---------- Input ---------------------------------
.SYNC_CLK (clk_pclk),
.SYNC_RST_N (!rst_cpllreset),
.SYNC_SLAVE (i > 0),
.SYNC_GEN3 (rate_gen3[i]),
.SYNC_RATE_IDLE (rate_idle[i]),
.SYNC_MMCM_LOCK (clk_mmcm_lock),
.SYNC_RXELECIDLE (gt_rxelecidle[i]),
.SYNC_RXCDRLOCK (user_rxcdrlock[i]),
.SYNC_ACTIVE_LANE (user_active_lane[i]),
.SYNC_TXSYNC_START (rate_txsync_start[i] || rst_txsync_start),
.SYNC_TXPHINITDONE (&(gt_txphinitdone | (~user_active_lane))),
.SYNC_TXDLYSRESETDONE (txdlysresetdone[i]),
.SYNC_TXPHALIGNDONE (txphaligndone[i]),
.SYNC_TXSYNCDONE (gt_txsyncdone[i]), // GTH
.SYNC_RXSYNC_START (rate_rxsync_start[i]),
.SYNC_RXDLYSRESETDONE (rxdlysresetdone[i]),
.SYNC_RXPHALIGNDONE_M (gt_rxphaligndone[0]),
.SYNC_RXPHALIGNDONE_S (rxphaligndone_s[i]),
.SYNC_RXSYNC_DONEM_IN (sync_rxsync_donem[0]),
.SYNC_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
//---------- Output --------------------------------
.SYNC_TXPHDLYRESET (sync_txphdlyreset[i]),
.SYNC_TXPHALIGN (sync_txphalign[i]),
.SYNC_TXPHALIGNEN (sync_txphalignen[i]),
.SYNC_TXPHINIT (sync_txphinit[i]),
.SYNC_TXDLYBYPASS (sync_txdlybypass[i]),
.SYNC_TXDLYSRESET (sync_txdlysreset[i]),
.SYNC_TXDLYEN (sync_txdlyen[i]),
.SYNC_TXSYNC_DONE (sync_txsync_done[i]),
.SYNC_FSM_TX (sync_fsm_tx[(6*i)+5:(6*i)]),
.SYNC_RXPHALIGN (sync_rxphalign[i]),
.SYNC_RXPHALIGNEN (sync_rxphalignen[i]),
.SYNC_RXDLYBYPASS (sync_rxdlybypass[i]),
.SYNC_RXDLYSRESET (sync_rxdlysreset[i]),
.SYNC_RXDLYEN (sync_rxdlyen[i]),
.SYNC_RXDDIEN (sync_rxddien[i]),
.SYNC_RXSYNC_DONEM_OUT (sync_rxsync_donem[i]),
.SYNC_RXSYNC_DONE (sync_rxsync_done[i]),
.SYNC_FSM_RX (sync_fsm_rx[(7*i)+6:(7*i)])
);
//---------- PIPE Sync Assignments -----------------------------------------
assign txdlysresetdone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txdlysresetdone[i] : >_txdlysresetdone;
assign txphaligndone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txphaligndone[i] : &(gt_txphaligndone | (~user_active_lane));
assign rxdlysresetdone[i] = (PCIE_RXSYNC_MODE == 1) ? gt_rxdlysresetdone[i] : >_rxdlysresetdone;
assign rxphaligndone_s[i] = (PCIE_LANE == 1) ? 1'd0 : >_rxphaligndone[PCIE_LANE:1];
//---------- PIPE DRP Module -------------------------------------------
pcie3_7x_0_pipe_drp #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_AUX_CDR_GEN3_EN (PCIE_AUX_CDR_GEN3_EN), // PCIe AUX CDR Gen3 enable
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // PCIe RX sync mode
)
pipe_drp_i
(
//---------- Input ---------------------------------
.DRP_CLK (clk_dclk),
.DRP_RST_N (!rst_dclk_reset),
.DRP_GTXRESET (rst_gtreset),
.DRP_RATE (PIPE_RATE),
.DRP_X16X20_MODE (rst_drp_x16x20_mode || rate_drp_x16x20_mode[i]),
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
.DRP_START (rst_drp_start || rate_drp_start[i]),
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
.DRP_RDY (gt_rdy[i]),
//---------- Output --------------------------------
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
.DRP_EN (drp_en[i]),
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
.DRP_WE (drp_we[i]),
.DRP_DONE (drp_done[i]),
.DRP_FSM (drp_fsm[(7*i)+6:(7*i)])
);
//---------- PIPE JTAG Slave Default ----------------------------------
assign jtag_sl_oport[((i+1)*17)-1 : (i*17)] = 17'd0;
assign jtag_sl_addr[(17*i)+16:(17*i)] = 17'd0;
assign jtag_sl_den[i] = 1'd0;
assign jtag_sl_di[(16*i)+15:(16*i)] = 16'd0;
assign jtag_sl_we[i] = 1'd0;
//---------- Generate DRP MUX ----------------------------------------------
assign PIPE_JTAG_RDY[i] = drp_fsm[7*i];
assign jtag_sl_en[i] = (jtag_sl_addr[(17*i)+16:(17*i)+9] == 8'd0) ? jtag_sl_den[i] : 1'd0;
// Channel DRP
assign drp_mux_en[i] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPEN[i] : drp_en[i];
assign drp_mux_di[(16*i)+15:(16*i)] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPDI[(16*i)+15:(16*i)] : drp_di[(16*i)+15:(16*i)];
assign drp_mux_addr[(9*i)+8:(9*i)] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPADDR[(9*i)+8:(9*i)] : drp_addr[(9*i)+8:(9*i)];
assign drp_mux_we[i] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPWE[i] : drp_we[i];
//---------- Generate PIPE EQ ----------------------------------------------
if (PCIE_LINK_SPEED == 3)
begin : pipe_eq
//---------- PIPE EQ Module --------------------------------------------
pcie3_7x_0_pipe_eq #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3) // PCIe RX equalization mode
)
pipe_eq_i
(
//---------- Input -----------------------------
.EQ_CLK (clk_pclk),
.EQ_RST_N (!rst_cpllreset),
.EQ_GEN3 (rate_gen3[i]),
.EQ_TXEQ_CONTROL (PIPE_TXEQ_CONTROL[(2*i)+1:(2*i)]),
.EQ_TXEQ_PRESET (PIPE_TXEQ_PRESET[(4*i)+3:(4*i)]),
.EQ_TXEQ_PRESET_DEFAULT (PIPE_TXEQ_PRESET_DEFAULT[(4*i)+3:(4*i)]),
.EQ_TXEQ_DEEMPH_IN (PIPE_TXEQ_DEEMPH[(6*i)+5:(6*i)]), // renamed
.EQ_RXEQ_CONTROL (PIPE_RXEQ_CONTROL[(2*i)+1:(2*i)]),
.EQ_RXEQ_PRESET (PIPE_RXEQ_PRESET[(3*i)+2:(3*i)]),
.EQ_RXEQ_LFFS (PIPE_RXEQ_LFFS[(6*i)+5:(6*i)]),
.EQ_RXEQ_TXPRESET (PIPE_RXEQ_TXPRESET[(4*i)+3:(4*i)]),
.EQ_RXEQ_USER_EN (PIPE_RXEQ_USER_EN[i]),
.EQ_RXEQ_USER_TXCOEFF (PIPE_RXEQ_USER_TXCOEFF[(18*i)+17:(18*i)]),
.EQ_RXEQ_USER_MODE (PIPE_RXEQ_USER_MODE[i]),
//---------- Output ----------------------------
.EQ_TXEQ_DEEMPH (eq_txeq_deemph[i]),
.EQ_TXEQ_PRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
.EQ_TXEQ_MAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
.EQ_TXEQ_POSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
.EQ_TXEQ_DEEMPH_OUT (PIPE_TXEQ_COEFF[(18*i)+17:(18*i)]),// renamed
.EQ_TXEQ_DONE (PIPE_TXEQ_DONE[i]),
.EQ_TXEQ_FSM (PIPE_TXEQ_FSM[(6*i)+5:(6*i)]),
.EQ_RXEQ_NEW_TXCOEFF (PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)]),
.EQ_RXEQ_LFFS_SEL (PIPE_RXEQ_LFFS_SEL[i]),
.EQ_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
.EQ_RXEQ_DONE (PIPE_RXEQ_DONE[i]),
.EQ_RXEQ_FSM (PIPE_RXEQ_FSM[(6*i)+5:(6*i)])
);
end
else
//---------- PIPE EQ Defaults ------------------------------------------
begin : pipe_eq_disable
assign eq_txeq_deemph[i] = 1'd0;
assign eq_txeq_precursor[(5*i)+4:(5*i)] = 5'h00;
assign eq_txeq_maincursor[(7*i)+6:(7*i)] = 7'h00;
assign eq_txeq_postcursor[(5*i)+4:(5*i)] = 5'h00;
assign eq_rxeq_adapt_done[i] = 1'd0;
assign PIPE_TXEQ_COEFF[(18*i)+17:(18*i)] = 18'd0;
assign PIPE_TXEQ_DONE[i] = 1'd0;
assign PIPE_TXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
assign PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)] = 18'd0;
assign PIPE_RXEQ_LFFS_SEL[i] = 1'd0;
assign PIPE_RXEQ_ADAPT_DONE[i] = 1'd0;
assign PIPE_RXEQ_DONE[i] = 1'd0;
assign PIPE_RXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
end
//---------- Generate PIPE Common Per Quad for Gen3 ------------------------
if ((i%4)==0)
begin : pipe_quad
//---------- Generate QPLL Powerdown and Reset -------------------------
assign qpllpd = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllpd : qrst_qpllpd;
assign qpllreset[i>>2] = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllreset : (qrst_qpllreset || qdrp_qpllreset[i>>2]);
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL") || (PCIE_GT_DEVICE == "GTP"))
begin : gt_common_enabled
if (PCIE_EXT_GT_COMMON == "FALSE")
begin : gt_common_int
//---------- GT COMMON INTERNAL Module ---------------------------------------
pcie3_7x_0_gt_common #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
gt_common_i
(
//---------- Input -------------------------
.PIPE_CLK (PIPE_CLK),
.QPLL_QPLLPD (qpllpd),
.QPLL_QPLLRESET (qpllreset[i>>2]),
.QPLL_DRP_CLK (clk_dclk),
.QPLL_DRP_RST_N (rst_dclk_reset),
.QPLL_DRP_OVRD (qrst_ovrd),
.QPLL_DRP_GEN3 (&rate_gen3),
.QPLL_DRP_START (qrst_drp_start),
.QPLL_DRP_CRSCODE (qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))]),
.QPLL_DRP_FSM (qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))]),
.QPLL_DRP_DONE (qdrp_done[i>>2]),
.QPLL_DRP_RESET (qdrp_qpllreset[i>>2]),
.QPLL_QPLLOUTCLK (qpll_qplloutclk[i>>2]),
.QPLL_QPLLOUTREFCLK (qpll_qplloutrefclk[i>>2]),
.QPLL_QPLLLOCK (qpll_qplllock[i>>2])
);
assign QPLL_QPLLPD = 1'b0;
assign QPLL_QPLLRESET[i>>2] = 1'b0;
assign QPLL_DRP_CLK = 1'b0;
assign QPLL_DRP_RST_N = 1'b0;
assign QPLL_DRP_OVRD = 1'b0;
assign QPLL_DRP_GEN3 = 1'b0;
assign QPLL_DRP_START = 1'b0;
assign INT_QPLLLOCK_OUT[i>>2] = qpll_qplllock[i>>2] ;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = qpll_qplloutrefclk[i>>2];
assign INT_QPLLOUTCLK_OUT[i>>2] = qpll_qplloutclk[i>>2];
end
else
begin : gt_common_ext
assign qdrp_done[i>>2] = QPLL_DRP_DONE[i>>2];
assign qdrp_qpllreset[i>>2] = QPLL_DRP_RESET[i>>2];
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = QPLL_DRP_CRSCODE[(6*(i>>2))+5:(6*(i>>2))];
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = QPLL_DRP_FSM[(9*(i>>2))+8:(9*(i>>2))];
assign qpll_qplloutclk[i>>2] = QPLL_QPLLOUTCLK[i>>2];
assign qpll_qplloutrefclk[i>>2] = QPLL_QPLLOUTREFCLK[i>>2];
assign qpll_qplllock[i>>2] = QPLL_QPLLLOCK[i>>2];
assign QPLL_QPLLPD = qpllpd;
assign QPLL_QPLLRESET[i>>2] = qpllreset[i>>2];
assign QPLL_DRP_CLK = clk_dclk;
assign QPLL_DRP_RST_N = rst_dclk_reset;
assign QPLL_DRP_OVRD = qrst_ovrd;
assign QPLL_DRP_GEN3 = &rate_gen3;
assign QPLL_DRP_START = qrst_drp_start;
assign INT_QPLLLOCK_OUT[i>>2] = 1'b0 ;
assign INT_QPLLOUTCLK_OUT[i>>2] = 1'b0 ;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = 1'b0 ;
end
end
else
//---------- PIPE Common Defaults ----------------------------------
begin : gt_common_disabled
assign qdrp_done[i>>2] = 1'd0;
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = 6'd0;
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = 9'd0;
assign qpll_qplloutclk[i>>2] = 1'd0;
assign qpll_qplloutrefclk[i>>2] = 1'd0;
assign qpll_qplllock[i>>2] = 1'd0;
assign QPLL_QPLLPD = 1'b0;
assign QPLL_QPLLRESET[i>>2] = 1'b0;
assign QPLL_DRP_CLK = 1'b0;
assign QPLL_DRP_RST_N = 1'b0;
assign QPLL_DRP_OVRD = 1'b0;
assign QPLL_DRP_GEN3 = 1'b0;
assign QPLL_DRP_START = 1'b0;
assign INT_QPLLLOCK_OUT[i>>2] = 1'b0 ;
assign INT_QPLLOUTCLK_OUT[i>>2] = 1'b0 ;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = 1'b0 ;
end
end
//---------- GT Wrapper ----------------------------------------------------
assign gt_txpmareset_i[i] = (user_txpmareset[i] || rate_txpmareset[i]);
assign gt_rxpmareset_i[i] = (user_rxpmareset[i] || rate_rxpmareset[i]);
pcie3_7x_0_gt_wrapper #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
.PCIE_SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // PCIe sim TX electrical idle drive level
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_LPM_DFE (PCIE_LPM_DFE), // PCIe LPM or DFE mode for Gen1/Gen2 only
.PCIE_LPM_DFE_GEN3 (PCIE_LPM_DFE_GEN3), // PCIe LPM or DFE mode for Gen3 only
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
.PCIE_CHAN_BOND (PCIE_CHAN_BOND), // PCIe Channel bonding mode
.PCIE_CHAN_BOND_EN (PCIE_CHAN_BOND_EN), // PCIe Channel bonding enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE), // PCIe number of lane
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
.PCIE_TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // PCIe TX electrical idle assert delay
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
)
gt_wrapper_i
(
//---------- GT User Ports -------------------------
.GT_MASTER (i == 0),
.GT_GEN3 (rate_gen3[i]),
.GT_RX_CONVERGE (&user_rx_converge),
//---------- GT Clock Ports ------------------------
.GT_GTREFCLK0 (PIPE_CLK),
.GT_QPLLCLK (qpll_qplloutclk[i>>2]),
.GT_QPLLREFCLK (qpll_qplloutrefclk[i>>2]),
.GT_TXUSRCLK (clk_pclk),
.GT_RXUSRCLK (clk_rxusrclk),
.GT_TXUSRCLK2 (clk_pclk),
.GT_RXUSRCLK2 (clk_rxusrclk),
.GT_OOBCLK (oobclk[i]),
.GT_TXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.GT_RXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.GT_TXOUTCLK (gt_txoutclk[i]),
.GT_RXOUTCLK (gt_rxoutclk[i]),
.GT_CPLLLOCK (gt_cplllock[i]),
.GT_RXCDRLOCK (gt_rxcdrlock[i]),
//---------- GT Reset Ports ------------------------
.GT_CPLLPD (rst_cpllpd || rate_cpllpd[i]),
.GT_CPLLRESET (rst_cpllreset || rate_cpllreset[i]),
.GT_TXUSERRDY (rst_userrdy),
.GT_RXUSERRDY (rst_userrdy),
.GT_RESETOVRD (user_resetovrd[i]),
.GT_GTTXRESET (rst_gtreset),
.GT_GTRXRESET (rst_gtreset),
.GT_TXPMARESET (gt_txpmareset_i[i]), // (user_txpmareset[i] || rate_txpmareset[i]),
.GT_RXPMARESET (gt_rxpmareset_i[i]), // (user_rxpmareset[i] || rate_rxpmareset[i]),
.GT_RXCDRRESET (user_rxcdrreset[i]),
.GT_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
.GT_RXDFELPMRESET (user_rxdfelpmreset[i]),
.GT_EYESCANRESET (user_eyescanreset[i]),
.GT_TXPCSRESET (user_txpcsreset[i]),
.GT_RXPCSRESET (user_rxpcsreset[i]),
.GT_RXBUFRESET (user_rxbufreset[i]),
.GT_EYESCANDATAERROR (gt_eyescandataerror[i]),
.GT_TXRESETDONE (gt_txresetdone[i]),
.GT_RXRESETDONE (gt_rxresetdone[i]),
.GT_RXPMARESETDONE (gt_rxpmaresetdone[i]),
//---------- GT TX Data Ports ----------------------
.GT_TXDATA (PIPE_TXDATA[(32*i)+31:(32*i)]),
.GT_TXDATAK (PIPE_TXDATAK[(4*i)+3:(4*i)]),
.GT_TXP (PIPE_TXP[i]),
.GT_TXN (PIPE_TXN[i]),
//---------- GT RX Data Ports ----------------------
.GT_RXP (PIPE_RXP[i]),
.GT_RXN (PIPE_RXN[i]),
.GT_RXDATA (PIPE_RXDATA[(32*i)+31:(32*i)]),
.GT_RXDATAK (PIPE_RXDATAK[(4*i)+3:(4*i)]),
//---------- GT Command Ports ----------------------
.GT_TXDETECTRX (PIPE_TXDETECTRX),
.GT_TXELECIDLE (PIPE_TXELECIDLE[i]),
.GT_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
.GT_RXPOLARITY (PIPE_RXPOLARITY[i]),
.GT_TXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
.GT_RXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
.GT_TXRATE (rate_rate[(3*i)+2:(3*i)]),
.GT_RXRATE (rate_rate[(3*i)+2:(3*i)]),
//---------- GT Electrical Command Ports -----------
.GT_TXMARGIN (PIPE_TXMARGIN),
.GT_TXSWING (PIPE_TXSWING),
.GT_TXDEEMPH (PIPE_TXDEEMPH[i]),
.GT_TXPRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
.GT_TXMAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
.GT_TXPOSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
//---------- GT Status Ports -----------------------
.GT_RXVALID (gt_rxvalid[i]),
.GT_PHYSTATUS (gt_phystatus[i]),
.GT_RXELECIDLE (gt_rxelecidle[i]),
.GT_RXSTATUS (gt_rxstatus[(3*i)+2:(3*i)]),
.GT_RXBUFSTATUS (gt_rxbufstatus[(3*i)+2:(3*i)]),
.GT_TXRATEDONE (gt_txratedone[i]),
.GT_RXRATEDONE (gt_rxratedone[i]),
.GT_RXDISPERR (gt_rxdisperr[(8*i)+7:(8*i)]),
.GT_RXNOTINTABLE (gt_rxnotintable[(8*i)+7:(8*i)]),
//---------- GT DRP Ports --------------------------
.GT_DRPCLK (clk_dclk),
.GT_DRPADDR (drp_mux_addr[(9*i)+8:(9*i)]),
.GT_DRPEN (drp_mux_en[i]),
.GT_DRPDI (drp_mux_di[(16*i)+15:(16*i)]),
.GT_DRPWE (drp_mux_we[i]),
.GT_DRPDO (gt_do[(16*i)+15:(16*i)]),
.GT_DRPRDY (gt_rdy[i]),
//---------- GT TX Sync Ports ----------------------
.GT_TXPHALIGN (sync_txphalign[i]),
.GT_TXPHALIGNEN (sync_txphalignen[i]),
.GT_TXPHINIT (sync_txphinit[i]),
.GT_TXDLYBYPASS (sync_txdlybypass[i]),
.GT_TXDLYSRESET (sync_txdlysreset[i]),
.GT_TXDLYEN (sync_txdlyen[i]),
.GT_TXDLYSRESETDONE (gt_txdlysresetdone[i]),
.GT_TXPHINITDONE (gt_txphinitdone[i]),
.GT_TXPHALIGNDONE (gt_txphaligndone[i]),
.GT_TXPHDLYRESET (sync_txphdlyreset[i]),
.GT_TXSYNCMODE (i == 0), // GTH, GTP
.GT_TXSYNCIN (gt_txsyncout[0]), // GTH, GTP
.GT_TXSYNCALLIN (txsyncallin), // GTH, GTP
.GT_TXSYNCOUT (gt_txsyncout[i]), // GTH, GTP
.GT_TXSYNCDONE (gt_txsyncdone[i]), // GTH, GTP
//---------- GT RX Sync Ports ----------------------
.GT_RXPHALIGN (sync_rxphalign[i]),
.GT_RXPHALIGNEN (sync_rxphalignen[i]),
.GT_RXDLYBYPASS (sync_rxdlybypass[i]),
.GT_RXDLYSRESET (sync_rxdlysreset[i]),
.GT_RXDLYEN (sync_rxdlyen[i]),
.GT_RXDDIEN (sync_rxddien[i]),
.GT_RXDLYSRESETDONE (gt_rxdlysresetdone[i]),
.GT_RXPHALIGNDONE (gt_rxphaligndone[i]),
.GT_RXSYNCMODE (i == 0), // GTH
.GT_RXSYNCIN (gt_rxsyncout[0]), // GTH
.GT_RXSYNCALLIN (rxsyncallin), // GTH
.GT_RXSYNCOUT (gt_rxsyncout[i]), // GTH
.GT_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
//---------- GT Comma Alignment Ports --------------
.GT_RXSLIDE (PIPE_RXSLIDE[i]),
.GT_RXCOMMADET (gt_rxcommadet[i]),
.GT_RXCHARISCOMMA (gt_rxchariscomma[(4*i)+3:(4*i)]),
.GT_RXBYTEISALIGNED (gt_rxbyteisaligned[i]),
.GT_RXBYTEREALIGN (gt_rxbyterealign[i]),
//---------- GT Channel Bonding Ports --------------
.GT_RXCHANISALIGNED (PIPE_RXCHANISALIGNED[i]),
.GT_RXCHBONDEN (rxchbonden[i]),
.GT_RXCHBONDI (gt_rxchbondi[i]),
.GT_RXCHBONDLEVEL (gt_rxchbondlevel[(3*i)+2:(3*i)]),
.GT_RXCHBONDMASTER (rxchbondmaster[i]),
.GT_RXCHBONDSLAVE (rxchbondslave[i]),
.GT_RXCHBONDO (gt_rxchbondo[i+1]),
//---------- GT PRBS/Loopback Ports ----------------
.GT_TXPRBSSEL (PIPE_TXPRBSSEL),
.GT_RXPRBSSEL (PIPE_RXPRBSSEL),
.GT_TXPRBSFORCEERR (PIPE_TXPRBSFORCEERR),
.GT_RXPRBSCNTRESET (PIPE_RXPRBSCNTRESET),
.GT_LOOPBACK (PIPE_LOOPBACK),
.GT_RXPRBSERR (PIPE_RXPRBSERR[i]),
//---------- GT Debug Port -------------------------
.GT_DMONITOROUT (PIPE_DMONITOROUT[(15*i)+14:(15*i)])
);
//---------- GT Wrapper Assignments ----------------------------------------
assign oobclk[i] = (PCIE_OOBCLK_MODE == 1) ? user_oobclk[i] : clk_oobclk;
//---------- Channel Bonding Master Slave Enable ---------------------------
if (PCIE_CHAN_BOND_EN == "FALSE")
begin : channel_bonding_ms_disable
assign rxchbonden[i] = 1'd0;
assign rxchbondmaster[i] = 1'd0;
assign rxchbondslave[i] = 1'd0;
end
else
begin : channel_bonding_ms_enable
assign rxchbonden[i] = (PCIE_LANE > 1) && (PCIE_CHAN_BOND_EN == "TRUE") ? !rate_gen3[i] : 1'd0;
assign rxchbondmaster[i] = rate_gen3[i] ? 1'd0 : (i == 0);
assign rxchbondslave[i] = rate_gen3[i] ? 1'd0 : (i > 0);
end
//---------- Channel Bonding Input Connection ------------------------------
if (PCIE_CHAN_BOND_EN == "FALSE")
begin : channel_bonding_in_disable
assign gt_rxchbondi[i] = 5'd0;
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
end
else
begin : channel_bonding_in_enable
//---------- Channel Bonding (2: Binary-Tree) --------------------------
if (PCIE_CHAN_BOND == 2)
begin : channel_bonding_a
case (i)
//---------- Lane 0 --------------------------------
0 :
begin
assign gt_rxchbondi[0] = gt_rxchbondo[0];
assign gt_rxchbondlevel[2:0] = (PCIE_LANE == 4'd8) ? 3'd4 :
(PCIE_LANE > 4'd5) ? 3'd3 :
(PCIE_LANE > 4'd3) ? 3'd2 :
(PCIE_LANE > 4'd1) ? 3'd1 : 3'd0;
end
//---------- Lane 1 --------------------------------
1 :
begin
assign gt_rxchbondi[1] = gt_rxchbondo[1];
assign gt_rxchbondlevel[5:3] = (PCIE_LANE == 4'd8) ? 3'd3 :
(PCIE_LANE > 4'd5) ? 3'd2 :
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
end
//---------- Lane 2 --------------------------------
2 :
begin
assign gt_rxchbondi[2] = gt_rxchbondo[1];
assign gt_rxchbondlevel[8:6] = (PCIE_LANE == 4'd8) ? 3'd3 :
(PCIE_LANE > 4'd5) ? 3'd2 :
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
end
//---------- Lane 3 --------------------------------
3 :
begin
assign gt_rxchbondi[3] = gt_rxchbondo[3];
assign gt_rxchbondlevel[11:9] = (PCIE_LANE == 4'd8) ? 3'd2 :
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
end
//---------- Lane 4 --------------------------------
4 :
begin
assign gt_rxchbondi[4] = gt_rxchbondo[3];
assign gt_rxchbondlevel[14:12] = (PCIE_LANE == 4'd8) ? 3'd2 :
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
end
//---------- Lane 5 --------------------------------
5 :
begin
assign gt_rxchbondi[5] = gt_rxchbondo[5];
assign gt_rxchbondlevel[17:15] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
end
//---------- Lane 6 --------------------------------
6 :
begin
assign gt_rxchbondi[6] = gt_rxchbondo[5];
assign gt_rxchbondlevel[20:18] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
end
//---------- Lane 7 --------------------------------
7 :
begin
assign gt_rxchbondi[7] = gt_rxchbondo[7];
assign gt_rxchbondlevel[23:21] = 3'd0;
end
//---------- Default -------------------------------
default :
begin
assign gt_rxchbondi[i] = gt_rxchbondo[7];
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
end
endcase
end
//---------- Channel Bonding (0: One-Hop, 1: Daisy Chain) --------------
else
begin : channel_bonding_b
assign gt_rxchbondi[i] = (PCIE_CHAN_BOND == 1) ? gt_rxchbondo[i] : ((i == 0) ? gt_rxchbondo[0] : gt_rxchbondo[1]);
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = (PCIE_CHAN_BOND == 1) ? (PCIE_LANE-1)-i : ((PCIE_LANE > 1) && (i == 0));
end
end
end
endgenerate
//---------- PIPE Wrapper Output -----------------------------------------------
assign PIPE_TXEQ_FS = TXEQ_FS;
assign PIPE_TXEQ_LF = TXEQ_LF;
assign PIPE_RXELECIDLE = gt_rxelecidle;
assign PIPE_RXSTATUS = gt_rxstatus;
assign PIPE_RXDISPERR = gt_rxdisperr;
assign PIPE_RXNOTINTABLE = gt_rxnotintable;
assign PIPE_RXPMARESETDONE = gt_rxpmaresetdone;
assign PIPE_RXBUFSTATUS = gt_rxbufstatus;
assign PIPE_TXPHALIGNDONE = gt_txphaligndone;
assign PIPE_TXPHINITDONE = gt_txphinitdone;
assign PIPE_TXDLYSRESETDONE = gt_txdlysresetdone;
assign PIPE_RXPHALIGNDONE = gt_rxphaligndone;
assign PIPE_RXDLYSRESETDONE = gt_rxdlysresetdone;
assign PIPE_RXSYNCDONE = gt_rxsyncdone;
assign PIPE_RXCOMMADET = gt_rxcommadet;
assign PIPE_QPLL_LOCK = qpll_qplllock;
assign PIPE_CPLL_LOCK = gt_cplllock;
assign PIPE_PCLK = clk_pclk;
assign PIPE_PCLK_LOCK = clk_mmcm_lock;
assign PIPE_RXCDRLOCK = user_rxcdrlock;
assign PIPE_RXUSRCLK = clk_rxusrclk;
assign PIPE_RXOUTCLK = clk_rxoutclk;
assign PIPE_TXSYNC_DONE = sync_txsync_done;
assign PIPE_RXSYNC_DONE = sync_rxsync_done;
assign PIPE_ACTIVE_LANE = user_active_lane;
assign PIPE_TXOUTCLK_OUT = gt_txoutclk[0];
assign PIPE_RXOUTCLK_OUT = gt_rxoutclk;
assign PIPE_PCLK_SEL_OUT = rate_pclk_sel;
assign PIPE_GEN3_OUT = rate_gen3[0];
assign PIPE_RXEQ_CONVERGE = user_rx_converge;
assign PIPE_RXEQ_ADAPT_DONE = (PCIE_GT_DEVICE == "GTP") ? {PCIE_LANE{1'd0}} : eq_rxeq_adapt_done;
assign PIPE_EYESCANDATAERROR = gt_eyescandataerror;
assign PIPE_RST_FSM = rst_fsm;
assign PIPE_QRST_FSM = qrst_fsm;
assign PIPE_RATE_FSM = rate_fsm;
assign PIPE_SYNC_FSM_TX = sync_fsm_tx;
assign PIPE_SYNC_FSM_RX = sync_fsm_rx;
assign PIPE_DRP_FSM = drp_fsm;
assign PIPE_QDRP_FSM = qdrp_fsm;
assign PIPE_RST_IDLE = &rst_idle;
assign PIPE_QRST_IDLE = &qrst_idle;
assign PIPE_RATE_IDLE = &rate_idle;
assign EXT_CH_GT_DRPDO = gt_do[(PCIE_LANE*16)-1:0];
assign EXT_CH_GT_DRPRDY = gt_rdy[(PCIE_LANE-1):0];
assign EXT_CH_GT_DRPCLK = clk_dclk;
assign PIPE_DEBUG_0 = (PCIE_DEBUG_MODE == 1) ? gt_txresetdone : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_1 = (PCIE_DEBUG_MODE == 1) ? gt_rxresetdone : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_2 = (PCIE_DEBUG_MODE == 1) ? gt_phystatus : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_3 = (PCIE_DEBUG_MODE == 1) ? gt_rxvalid : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_4 = (PCIE_DEBUG_MODE == 1) ? clk_dclk : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_5 = (PCIE_DEBUG_MODE == 1) ? drp_mux_en : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_6 = (PCIE_DEBUG_MODE == 1) ? drp_mux_we : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_7 = (PCIE_DEBUG_MODE == 1) ? gt_rdy : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_8 = (PCIE_DEBUG_MODE == 1) ? user_rx_converge : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_9 = (PCIE_DEBUG_MODE == 1) ? PIPE_TXELECIDLE : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG[ 1:0] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_CONTROL[1:0] : 2'd0;
assign PIPE_DEBUG[ 5:2] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_PRESET[3:0] : 4'd0;
assign PIPE_DEBUG[31:6] = 26'd0;
endmodule
|
`timescale 1ns/1ns
// 32-bit Arithmetic Logic Unit with 4-bit Selector
module ALU32 (
input [3:0] sel,
input [31:0] x,
input [31:0] y,
output reg [31:0] o,
output reg v,
output reg z,
output reg s,
output reg c
);
parameter ADD = 4'b0000;
parameter SUB = 4'b0001;
parameter AND = 4'b0010;
parameter OR = 4'b0011;
parameter XOR = 4'b0100;
parameter SSLT = 4'b0101;
parameter USLT = 4'b0110;
parameter SLL = 4'b0111;
parameter SLR = 4'b1000;
parameter SRA = 4'b1001;
always @ (sel or x or y)
begin
c = 0; v = 0;
case (sel)
ADD: begin {c, o} = x + y; v = c ^ x[31] ^ y[31] ^ o[31]; end // Addition: output = x + y
SUB: begin o = x - y; v = c ^ x[31] ^ y[31] ^ o[31]; end // Subtraction: output = x - y
AND: o = x & y; // Bitwise AND: output = x & y
OR: o = x | y; // Bitwise OR: output = x | y
XOR: o = x ^ y; // Bitwise XOR: output = x ^ y
SSLT: o = ($signed(x) < $signed(y))? 32'h00000001 : 32'h00000000; // Signed Less Than: output = (x < y)? 1 : 0
USLT: o = (x < y)? 32'h00000001 : 32'h00000000; // Unsigned Less Than: output = (x < y)? 1 : 0
SLL: o = x << y[4:0]; // Logical Shift Left: output = x << y[4:0]
SLR: o = x >> y[4:0]; // Logical Shift Right: output = x >> y[4:0]
SRA: o = $signed(x) >>> y[4:0]; // Arithmetic Shift Right
default: o = 32'hxxxxxxxx; // Default case
endcase
s = o[31];
z = (o == 1'b0)? 32'h00000001 : 32'h00000000;
end
endmodule
|
//********************************************************************************************************************************
// POWER DEBUG DISPLAY
//********************************************************************************************************************************
`ifdef DEBUG_POWER
///////////////////////////////
// MBus Power-On
///////////////////////////////
always @(negedge `TB_INSTNAME.mbc_sleep) if (checking & ~(`TB_INSTNAME.mbc_isolate & `TB_INSTNAME.mbc_reset & `TB_INSTNAME.lc_sleep & `TB_INSTNAME.lc_isolate & ~`TB_INSTNAME.lc_reset_b & ~`TB_INSTNAME.lc_clken))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] MBC POWER-ON FAILURE... ", $time); `_RESET; failure; end
always @(negedge `TB_INSTNAME.mbc_isolate) if (checking & ~(~`TB_INSTNAME.mbc_sleep & `TB_INSTNAME.mbc_reset & `TB_INSTNAME.lc_sleep & `TB_INSTNAME.lc_isolate & ~`TB_INSTNAME.lc_reset_b & ~`TB_INSTNAME.lc_clken))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] MBC UN-ISOLATE FAILURE... ", $time); `_RESET; failure; end
always @(negedge `TB_INSTNAME.mbc_reset) begin
`_GREEN; $display("\n*** Time %0dns: MBC POWERED-ON... ", $time); `_RESET;
if (checking & ~(~`TB_INSTNAME.mbc_sleep & ~`TB_INSTNAME.mbc_isolate & `TB_INSTNAME.lc_sleep & `TB_INSTNAME.lc_isolate & ~`TB_INSTNAME.lc_reset_b & ~`TB_INSTNAME.lc_clken))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] MBC RESET RELEASE FAILURE... ", $time); `_RESET; failure; end
end
///////////////////////////////
// Layer Controller Power-On
///////////////////////////////
always @(negedge `TB_INSTNAME.lc_sleep) if (checking & ~(~`TB_INSTNAME.mbc_sleep & ~`TB_INSTNAME.mbc_isolate & ~`TB_INSTNAME.mbc_reset & `TB_INSTNAME.lc_isolate & ~`TB_INSTNAME.lc_reset_b & ~`TB_INSTNAME.lc_clken))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] LAYER_CTRL POWER-ON FAILURE... ", $time); `_RESET; failure; end
always @(negedge `TB_INSTNAME.lc_isolate) if (checking & ~(~`TB_INSTNAME.mbc_sleep & ~`TB_INSTNAME.mbc_isolate & ~`TB_INSTNAME.mbc_reset & ~`TB_INSTNAME.lc_sleep & ~`TB_INSTNAME.lc_reset_b & ~`TB_INSTNAME.lc_clken))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] LAYER_CTRL UN-ISOLATE FAILURE... ", $time); `_RESET; failure; end
always @(posedge `TB_INSTNAME.lc_reset_b) if (checking & ~(~`TB_INSTNAME.mbc_sleep & ~`TB_INSTNAME.mbc_isolate & ~`TB_INSTNAME.mbc_reset & ~`TB_INSTNAME.lc_sleep & ~`TB_INSTNAME.lc_isolate & ~`TB_INSTNAME.lc_clken))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] LAYER_CTRL RESET RELEASE FAILURE... ", $time); `_RESET; failure; end
always @(posedge `TB_INSTNAME.lc_clken) begin
`_GREEN; $display("\n*** Time %0dns: LAYER_CTRL POWERED-ON AND CLOCK STARTED RUNNING... ", $time); `_RESET;
if (checking & ~(~`TB_INSTNAME.mbc_sleep & ~`TB_INSTNAME.mbc_isolate & ~`TB_INSTNAME.mbc_reset & ~`TB_INSTNAME.lc_sleep & ~`TB_INSTNAME.lc_isolate & `TB_INSTNAME.lc_reset_b))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] LAYER_CTRL CLOCK START FAILURE... ", $time); `_RESET; failure; end
end
///////////////////////////////
// MBus Power-Off
///////////////////////////////
always @(posedge `TB_INSTNAME.mbc_isolate) if (checking & ~(~`TB_INSTNAME.mbc_sleep & ~`TB_INSTNAME.mbc_reset & ~`TB_INSTNAME.lc_sleep & `TB_INSTNAME.lc_isolate & `TB_INSTNAME.lc_reset_b & `TB_INSTNAME.lc_clken))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] MBC ISOLATE FAILURE... ", $time); `_RESET; failure; end
always @(posedge `TB_INSTNAME.mbc_reset) if (checking & ~(`TB_INSTNAME.mbc_isolate & `TB_INSTNAME.lc_isolate))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] MBC RESET FAILURE... ", $time); `_RESET; failure; end
always @(posedge `TB_INSTNAME.mbc_sleep) begin
`_MAGENTA; $display("\n*** Time %0dns: MBC POWERED-OFF... ", $time); `_RESET;
if (checking & ~(`TB_INSTNAME.mbc_isolate & `TB_INSTNAME.lc_isolate))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] MBC POWER-OFF FAILURE... ", $time); `_RESET; failure; end
end
///////////////////////////////
// Layer Controller Power-Off
///////////////////////////////
always @(posedge `TB_INSTNAME.lc_isolate) if (checking & ~(~`TB_INSTNAME.mbc_sleep & ~`TB_INSTNAME.mbc_isolate & ~`TB_INSTNAME.mbc_reset & ~`TB_INSTNAME.lc_sleep & `TB_INSTNAME.lc_reset_b & `TB_INSTNAME.lc_clken))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] LAYER_CTRL ISOLATE FAILURE... ", $time); `_RESET; failure; end
always @(negedge `TB_INSTNAME.lc_reset_b) if (checking & ~(`TB_INSTNAME.mbc_isolate & `TB_INSTNAME.lc_isolate))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] LAYER_CTRL RESET FAILURE... ", $time); `_RESET; failure; end
always @(negedge `TB_INSTNAME.lc_clken) if (checking & ~(`TB_INSTNAME.mbc_isolate & `TB_INSTNAME.lc_isolate))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] LAYER_CTRL CLOCK STOP FAILURE... ", $time); `_RESET; failure; end
always @(posedge `TB_INSTNAME.lc_sleep) begin
`_MAGENTA; $display("\n*** Time %0dns: LAYER_CTRL POWERED-OFF... ", $time); `_RESET;
if (checking & ~(`TB_INSTNAME.mbc_isolate & `TB_INSTNAME.lc_isolate))
begin `_RED_B; $display("\n*** Time %0dns: [ERROR] LAYER_CTRL POWER-OFF FAILURE... ", $time); `_RESET; failure; end
end
`endif
//********************************************************************************************************************************
// MBUS REGISTER FILE DEBUG DISPLAY
//********************************************************************************************************************************
`ifdef DEBUG_RF
`ifdef FLPv3L
`include "/afs/eecs.umich.edu/vlsida/projects/m3_hdk/layer/FLP/FLPv3L/verilog/genRF/FLPv3L_rf_debug.v"
`elsif FLPv3S
`include "/afs/eecs.umich.edu/vlsida/projects/m3_hdk/layer/FLP/FLPv3S/verilog/genRF/FLPv3S_rf_debug.v"
`endif
`endif
//********************************************************************************************************************************
// FLP CTRL DEBUG DISPLAY
//********************************************************************************************************************************
`ifdef DEBUG_CTRL
`ifndef APR
wire db_clk, db_resetn, db_is_reg_wr_fls;
wire [`STATE_WIDTH-1:0] db_state, db_next_state;
wire [31:0] db_flsh_rd_dout_32, db_bt_reg_chksum, db_bt_mem_chksum, db_bt_mem_addr;
wire [`OP_ECC_EFF_WIDTH-1:0]db_flsh_rd_dout_32_ecc;
wire [23:0] db_bt_reg_data;
wire [7:0] db_bt_reg_addr;
wire [3:0] db_bt_short_prefix, db_enum_short_prefix;
wire [19:0] db_bt_layer_addr;
wire [17:0] db_bt_cnt, db_bt_mem_length_1;
wire [`SRAM_ADDR_WIDTH-1:0] db_bt_sram_addr;
assign db_clk = `TB_INSTNAME.`TB_CTRL_NAME.CLK;
assign db_resetn = `TB_INSTNAME.`TB_CTRL_NAME.RESETn;
assign db_state = `TB_INSTNAME.`TB_CTRL_NAME.state;
assign db_next_state = `TB_INSTNAME.`TB_CTRL_NAME.next_state;
assign db_flsh_rd_dout_32 = `TB_INSTNAME.`TB_CTRL_NAME.flsh_rd_dout_32;
assign db_flsh_rd_dout_32_ecc = `TB_INSTNAME.`TB_CTRL_NAME.flsh_rd_dout_32_ecc;
assign db_bt_reg_addr = `TB_INSTNAME.`TB_CTRL_NAME.bt_reg_addr;
assign db_bt_reg_data = `TB_INSTNAME.`TB_CTRL_NAME.bt_reg_data;
assign db_bt_short_prefix = `TB_INSTNAME.`TB_CTRL_NAME.bt_short_prefix;
assign db_bt_reg_chksum = `TB_INSTNAME.`TB_CTRL_NAME.bt_reg_chksum;
assign db_bt_mem_chksum = `TB_INSTNAME.`TB_CTRL_NAME.bt_mem_chksum;
assign db_bt_layer_addr = `TB_INSTNAME.`TB_CTRL_NAME.bt_layer_addr;
assign db_bt_mem_addr = `TB_INSTNAME.`TB_CTRL_NAME.bt_mem_addr;
assign db_bt_sram_addr = `TB_INSTNAME.`TB_CTRL_NAME.bt_sram_addr;
assign db_enum_short_prefix = `TB_INSTNAME.`TB_CTRL_NAME.enum_short_prefix;
assign db_is_reg_wr_fls = `TB_INSTNAME.`TB_CTRL_NAME.is_reg_wr_fls;
assign db_bt_cnt = `TB_INSTNAME.`TB_CTRL_NAME.bt_cnt;
assign db_bt_mem_length_1 = `TB_INSTNAME.`TB_CTRL_NAME.bt_mem_length_1;
always @(posedge db_clk or negedge db_resetn) begin
if (db_state != db_next_state) begin
if (db_next_state == `BT_MANUAL_0) $display ("*** Time %0dns: [NOTE] BOOT-UP || [MANUAL] STARTING MANUAL BOOT-UP", $time);
else if ((db_next_state == `BT_RD_FLSH_0) && (db_state == `BT_CHK_HEAD_1))
$display ("*** Time %0dns: [NOTE] BOOT-UP || [HEADER] HEADER PATTERN MATCHED (0x%8h)", $time, `BOOT_HEADER);
else if (db_next_state == `BT_PS_CMND_0) $display ("*** Time %0dns: [NOTE] BOOT-UP || [NEW_COMMAND] CODE:0x%8h ECC_DECODED:0x%8h", $time, db_flsh_rd_dout_32, db_flsh_rd_dout_32_ecc);
else if (db_next_state == `BT_REG_WR_4) begin
if (db_is_reg_wr_fls ) begin $display ("*** Time %0dns: [OPER] BOOT-UP || [REG_WRITE] REG:0x%2h DATA:0x%6h", $time, db_bt_reg_addr, db_bt_reg_data); end
else begin $display ("*** Time %0dns: [OPER] BOOT-UP || [REG_WRITE] PREFIX:0x%1h REG:0x%2h DATA:0x%6h", $time, db_bt_short_prefix, db_bt_reg_addr, db_bt_reg_data); end
end
else if (db_next_state == `BT_EOP) begin $display ("*** Time %0dns: [OPER] BOOT-UP || [REG_WRITE] BOOT_FLAG_SUCCESS=1 || SUCCESSFUL END OF BOOT-UP SEQUENCE", $time); end
else if (db_next_state == `BT_EOP_PWDN_0)begin $display ("*** Time %0dns: [OPER] BOOT-UP || [REG_WRITE] BOOT_FLAG_PWDN=1 BOOT_FLAG_SUCCESS=1 || SUCCESSFUL END OF BOOT-UP SEQUENCE", $time); end
else if (db_next_state == `BT_EOP_SLP) begin $display ("*** Time %0dns: [OPER] BOOT-UP || [REG_WRITE] BOOT_FLAG_SLEEP=1 BOOT_FLAG_SUCCESS=1 || SUCCESSFUL END OF BOOT-UP SEQUENCE", $time); end
else if (db_next_state == `BT_CHKSUM_ERR)begin
if (db_state == `BT_REG_WR_3) begin $display ("*** Time %0dns: [OPER] BOOT-UP || [REG_WRITE] BOOT_FLAG_CHKSUM_ERROR=1 || FAILURE: WRONG CHKSUM || EXPECTED:0x%8h CODE:0x%8h", $time, db_bt_reg_chksum, db_flsh_rd_dout_32); end
else if (db_state == `BT_MEM_WR_6) begin $display ("*** Time %0dns: [OPER] BOOT-UP || [MEM_WRITE] BOOT_FLAG_CHKSUM_ERROR=1 || FAILURE: WRONG CHKSUM || EXPECTED:0x%8h CODE:0x%8h", $time, db_bt_mem_chksum, db_flsh_rd_dout_32); end
end
else if (db_next_state == `BT_INVLD_CMND)begin $display ("*** Time %0dns: [OPER] BOOT-UP || [REG_WRITE] BOOT_FLAG_INVALID_CMND=1 || FAILURE: INVALID COMMAND || CODE:0x%8h", $time, db_flsh_rd_dout_32); end
else if (db_next_state == `BT_WRONG_HEAD)begin $display ("*** Time %0dns: [OPER] BOOT-UP || [REG_WRITE] BOOT_FLAG_WRONG_HEADER=1 || FAILURE: WRONG HEADER || EXPECTED:0x%8h CODE:0x%8h", $time, `BOOT_HEADER, db_flsh_rd_dout_32); end
else if (db_next_state == `BT_ECC_ERR) begin $display ("*** Time %0dns: [OPER] BOOT-UP || [REG_WRITE] BOOT_FLAG_ECC_ERR=1 || FAILURE: ECC DOUBLE ERROR DETECTED || CODE:0x%8h", $time, db_flsh_rd_dout_32); end
else if (db_next_state == `SLEEP) $display ("*** Time %0dns: [NOTE] BOOT-UP || [INFO] TURNING OFF FLASH TO GO TO SLEEP", $time);
else if (db_next_state == `TX_MBUS_SLEEP)begin $display ("*** Time %0dns: [OPER] BOOT-UP || [MBUS] SENDING MBUS SLEEP MESSAGE", $time); end
else if ((db_next_state == `BT_MEM_WR_3) && (db_bt_cnt == db_bt_mem_length_1))
$display ("*** Time %0dns: [NOTE] BOOT-UP || [MEM_WRITE] SETTING UP || DEST_LAYER:0x%5h DEST_ADDR:0x%8h", $time, db_bt_layer_addr, db_bt_mem_addr);
else if ((db_next_state == `WR_SRAM_0) && (db_state == `BT_MEM_WR_3))
$display ("*** Time %0dns: [NOTE] BOOT-UP || [MEM_WRITE] WRITE INTO SRAM || ADDR: 0x%3h, CODE:0x%8h", $time, db_bt_sram_addr, db_flsh_rd_dout_32);
else if (db_next_state == `BT_MEM_WR_7) $display ("*** Time %0dns: [NOTE] BOOT-UP || [MEM_WRITE] STARTING MEM COPY", $time);
else if (db_state == `BT_ENUM_0) begin $display ("*** Time %0dns: [OPER] BOOT-UP || [MBUS] SENDING ENUMERATE MESSAGE || SHORT_PREFIX = 0x%1h", $time, db_enum_short_prefix); end
if ((db_next_state == `BT_EOP) || (db_next_state == `BT_EOP_PWDN_0) ||(db_next_state == `BT_EOP_SLP)) begin
`_BLUE;
$display ("*******************************************************");
$display ("*******************************************************");
$display ("********* BOOT-UP SUCCESSFUL!! ************");
$display ("*******************************************************");
$display ("*******************************************************");
`_RESET;
end
else if ((db_next_state == `BT_CHKSUM_ERR) || (db_next_state == `BT_INVLD_CMND) || (db_next_state == `BT_WRONG_HEAD) || (db_next_state == `BT_ECC_ERR)) begin
`_RED;
$display ("*******************************************************");
$display ("*******************************************************");
$display ("*********** BOOT-UP FAILURE!! *************");
$display ("*******************************************************");
$display ("*******************************************************");
`_RESET;
end
end
else if (db_state == `BT_NOP_0) $display ("*** Time %0dns: [NOTE] BOOT-UP || [NOP]", $time);
end
always @ (`TB_INSTNAME.`TB_CTRL_NAME.flsh_isoln
or `TB_INSTNAME.`TB_CTRL_NAME.Flash_0.ABUF_EN
or `TB_INSTNAME.`TB_CTRL_NAME.Flash_0.RESETB
or `TB_INSTNAME.`TB_CTRL_NAME.Flash_0.HVCP_EN
or `TB_INSTNAME.`TB_CTRL_NAME.Flash_0.MVCP_EN
or `TB_INSTNAME.`TB_CTRL_NAME.Flash_0.SC_EN
) begin
if ( `TB_INSTNAME.`TB_CTRL_NAME.flsh_isoln // Unisolated
& ( ~`TB_INSTNAME.`TB_CTRL_NAME.Flash_0.ABUF_EN
| ~`TB_INSTNAME.`TB_CTRL_NAME.Flash_0.RESETB
| ~`TB_INSTNAME.`TB_CTRL_NAME.Flash_0.HVCP_EN
| ~`TB_INSTNAME.`TB_CTRL_NAME.Flash_0.MVCP_EN
| ~`TB_INSTNAME.`TB_CTRL_NAME.Flash_0.SC_EN
)
) begin
`_RED_B;
$display("*** Time %0dns: [FLASH OPER ERROR] Incorrect Insolation!! ", $time);
`_RESET;
failure;
end
end
`endif // APR
`endif // DEBUG_CTRL
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/03/2015 04:15:25 PM
// Design Name:
// Module Name: sink
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
module sink #(parameter Thold = 5)
(
input wire clk,
input wire done_strobe_din,
input wire [0:63] ciphertext_din
);
integer fp;
initial
fp = $fopen("/home/hcabrera/Dropbox/tesis/noc/work/verilog/project_lancetfish/processing_node/des_engine/verif/results_mem.dat");
always
@(posedge done_strobe_din)
begin
#(Thold);
$fdisplayh(fp, "", ciphertext_din[0 : 7]);
$fdisplayh(fp, "", ciphertext_din[8 :15]);
$fdisplayh(fp, "", ciphertext_din[16:23]);
$fdisplayh(fp, "", ciphertext_din[24:31]);
$fdisplayh(fp, "", ciphertext_din[32:39]);
$fdisplayh(fp, "", ciphertext_din[40:47]);
$fdisplayh(fp, "", ciphertext_din[48:55]);
$fdisplayh(fp, "", ciphertext_din[56:63]);
$display("ciphertext:", ciphertext_din);
end
endmodule // sink
/* -- Plantilla de instancia ------------------------------------- >>>>>
sink
#(
.Thold(Thold)
)
receptor_datos
(
.clk(clk),
// -- inputs ------------------------------------------------- >>>>>
.done_strobe_din(done_strobe_din),
.ciphertext_din(ciphertext_din)
);
*/ |
/*
* Milkymist VJ SoC fjmem flasher
* Copyright (C) 2010 Michael Walle
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module system(
input clk50,
/* flash */
output [23:0] flash_adr,
inout [15:0] flash_d,
output flash_oe_n,
output flash_we_n,
output flash_ce_n,
output flash_rst_n,
input flash_sts,
/* debug */
output led1,
output led2
);
/* clock and reset */
wire sys_rst;
wire sys_clk;
assign sys_clk = clk50;
assign sys_rst = 1'b0;
/* flash control pins */
assign flash_ce_n = 1'b0;
assign flash_rst_n = 1'b1;
/* debug */
wire fjmem_update;
reg [25:0] counter;
always @(posedge sys_clk)
counter <= counter + 1'd1;
assign led1 = counter[25];
assign led2 = fjmem_update;
fjmem #(
.adr_width(24)
) fjmem (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.flash_adr(flash_adr),
.flash_d(flash_d),
.flash_oe_n(flash_oe_n),
.flash_we_n(flash_we_n),
.fjmem_update(fjmem_update)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : example_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:36:27 $
// \ \ / \ Date Created : Fri Jan 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : QDRII+ SDRAM
// Purpose :
// Top-level module. This module serves as an example,
// and allows the user to synthesize a self-contained design,
// which they can be used to test their hardware.
// In addition to the memory controller, the module instantiates:
// 1. Synthesizable testbench - used to model user's backend logic
// and generate different traffic patterns
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module example_top #
(
parameter MEM_TYPE = "QDR2PLUS",
// # of CK/CK# outputs to memory.
parameter DATA_WIDTH = 36,
// # of DQ (data)
parameter BW_WIDTH = 4,
// # of byte writes (data_width/9)
parameter ADDR_WIDTH = 19,
// Address Width
// parameter NUM_DEVICES = 1,
// # of memory components connected
// parameter MEM_RD_LATENCY = 2.5,
// Value of Memory part read latency
// parameter CPT_CLK_CQ_ONLY = "TRUE",
// whether CQ and its inverse are used for the data capture
// parameter INTER_BANK_SKEW = 0,
// Clock skew between two adjacent banks
// parameter PHY_CONTROL_MASTER_BANK = 1,
// The bank index where master PHY_CONTROL resides,
// equal to the PLL residing bank
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter BURST_LEN = 4,
// Burst Length of the design (4 or 2).
// parameter FIXED_LATENCY_MODE = 0,
// Enable Fixed Latency
// parameter PHY_LATENCY = 0,
// Value for Fixed Latency Mode
// Expected Latency
//***************************************************************************
// The following parameters are multiplier and divisor factors for MMCM.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
// parameter CLKIN_PERIOD = 5000,
// Input Clock Period
// parameter CLKFBOUT_MULT = 4,
// write PLL VCO multiplier
// parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
// parameter CLKOUT0_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT0)
// parameter CLKOUT1_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT1)
// parameter CLKOUT2_DIVIDE = 32,
// VCO output divisor for PLL output clock (CLKOUT2)
// parameter CLKOUT3_DIVIDE = 4,
// VCO output divisor for PLL output clock (CLKOUT3)
//***************************************************************************
// Simulation parameters
//***************************************************************************
// parameter SIM_BYPASS_INIT_CAL = "OFF",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "FAST" - Skip memory init & use
// abbreviated calib sequence
parameter SIMULATION = "FALSE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
// parameter BYTE_LANES_B0 = 4'b1111,
// // Byte lanes used in an IO column.
// parameter BYTE_LANES_B1 = 4'b1111,
// // Byte lanes used in an IO column.
// parameter BYTE_LANES_B2 = 4'b1100,
// // Byte lanes used in an IO column.
// parameter BYTE_LANES_B3 = 4'b0000,
// // Byte lanes used in an IO column.
// parameter BYTE_LANES_B4 = 4'b0000,
// // Byte lanes used in an IO column.
// parameter DATA_CTL_B0 = 4'b1111,
// // Indicates Byte lane is data byte lane
// // or control Byte lane. '1' in a bit
// // position indicates a data byte lane and
// // a '0' indicates a control byte lane
// parameter DATA_CTL_B1 = 4'b1111,
// // Indicates Byte lane is data byte lane
// // or control Byte lane. '1' in a bit
// // position indicates a data byte lane and
// // a '0' indicates a control byte lane
// parameter DATA_CTL_B2 = 4'b0000,
// // Indicates Byte lane is data byte lane
// // or control Byte lane. '1' in a bit
// // position indicates a data byte lane and
// // a '0' indicates a control byte lane
// parameter DATA_CTL_B3 = 4'b0000,
// // Indicates Byte lane is data byte lane
// // or control Byte lane. '1' in a bit
// // position indicates a data byte lane and
// // a '0' indicates a control byte lane
// parameter DATA_CTL_B4 = 4'b0000,
// // Indicates Byte lane is data byte lane
// // or control Byte lane. '1' in a bit
// // position indicates a data byte lane and
// // a '0' indicates a control byte lane
//
// // this parameter specifies the location of the capture clock with respect
// // to read data.
// // Each byte refers to the information needed for data capture in the corresponding byte lane
// // Lower order nibble - is either 4'h1 or 4'h2. This refers to the capture clock in T1 or T2 byte lane
// // Higher order nibble - 4'h0 refers to clock present in the bank below the read data,
// // 4'h1 refers to clock present in the same bank as the read data,
// // 4'h2 refers to clock present in the bank above the read data.
// parameter CPT_CLK_SEL_B0 = 32'h11_11_11_11,
// parameter CPT_CLK_SEL_B1 = 32'h00_00_00_00,
// parameter CPT_CLK_SEL_B2 = 32'h00_00_00_00,
//
// parameter PHY_0_BITLANES = 48'hFF8_FF1_D3F_EFC,
// // The bits used inside the Bank0 out of 48 pins.
// parameter PHY_1_BITLANES = 48'h3FE_FFE_CFF_FFC,
// // The bits used inside the Bank1 out of 48 pins.
// parameter PHY_2_BITLANES = 48'hEFE_FFD_000_000,
// // The bits used inside the Bank2 out of 48 pins.
// parameter PHY_3_BITLANES = 48'h000_000_000_000,
// // The bits used inside the Bank3 out of 48 pins.
// parameter PHY_4_BITLANES = 48'h000_000_000_000,
// // The bits used inside the Bank4 out of 48 pins.
//
// // Differentiates the INPUT and OUTPUT bytelates (1-input, 0-output)
// parameter BYTE_GROUP_TYPE_B0 = 4'b1111,
// parameter BYTE_GROUP_TYPE_B1 = 4'b0000,
// parameter BYTE_GROUP_TYPE_B2 = 4'b0000,
// parameter BYTE_GROUP_TYPE_B3 = 4'b0000,
// parameter BYTE_GROUP_TYPE_B4 = 4'b0000,
//
// // mapping for K/K# clocks. This parameter needs to have an 8-bit value per component
// // since the phy drives a K/K# clock pair to each memory it interfaces to. A 3 component
// // interface is supported for now. This parameter needs to be used in conjunction with
// // NUM_DEVICES parameter which provides information on the number. of components being
// // interfaced to.
// // the 8 bit for each component is defined as follows:
// // [7:4] - bank number ; [3:0] - byte lane number
// parameter K_MAP = 48'h00_00_00_00_00_13,
//
// // mapping for CQ/CQ# clocks. This parameter needs to have an 4-bit value per component
// // since the phy drives a CQ/CQ# clock pair to each memory it interfaces to. A 3 component
// // interface is supported for now. This parameter needs to be used in conjunction with
// // NUM_DEVICES parameter which provides information on the number. of components being
// // interfaced to.
// // the 4 bit for each component is defined as follows:
// // [3:0] - bank number
// parameter CQ_MAP = 48'h00_00_00_00_00_01,
//
// //**********************************************************************************************
// // Each of the following parameter contains the byte_lane and bit position information for
// // the address/control, data write and data read signals. Each bit has 12 bits and the details are
// // [3:0] - Bit position within a byte lane .
// // [7:4] - Byte lane position within a bank. [5:4] have the byte lane position and others reserved.
// // [11:8] - Bank position. [10:8] have the bank position. [11] tied to zero .
// //**********************************************************************************************
//
// // Mapping for address and control signals.
//
// parameter RD_MAP = 12'h220, // Mapping for read enable signal
// parameter WR_MAP = 12'h222, // Mapping for write enable signal
//
// // Mapping for address signals. Supports upto 22 bits of address bits (22*12)
// parameter ADD_MAP = 264'h000_000_000_223_236_22B_23B_235_234_225_229_224_232_228_23A_231_237_239_233_227_22A_226,
//
// // Mapping for the byte lanes used for address/control signals. Supports a maximum of 3 banks.
// parameter ADDR_CTL_MAP = 32'h00_00_23_22,
//
// // Mapping for data WRITE signals
//
// // Mapping for data write bytes (9*12)
// parameter D0_MAP = 108'h137_134_136_135_132_133_131_138_139, //byte 0
// parameter D1_MAP = 108'h121_124_125_122_126_127_12A_123_12B, //byte 1
// parameter D2_MAP = 108'h102_103_108_104_106_105_107_10A_10B, //byte 2
// parameter D3_MAP = 108'h116_117_115_11A_114_113_111_112_110, //byte 3
// parameter D4_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 4
// parameter D5_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 5
// parameter D6_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 6
// parameter D7_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 7
//
// // Mapping for byte write signals (8*12)
// parameter BW_MAP = 84'h000_000_000_11B_109_128_129,
//
// // Mapping for data READ signals
//
// // Mapping for data read bytes (9*12)
// parameter Q0_MAP = 108'h033_039_034_036_035_03A_03B_037_038, //byte 0
// parameter Q1_MAP = 108'h029_020_028_026_027_02A_02B_024_025, //byte 1
// parameter Q2_MAP = 108'h015_014_01A_01B_011_010_013_012_018, //byte 2
// parameter Q3_MAP = 108'h00B_003_007_002_005_004_009_006_00A, //byte 3
// parameter Q4_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 4
// parameter Q5_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 5
// parameter Q6_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 6
// parameter Q7_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 7
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
// parameter IODELAY_HP_MODE = "ON",
// // to phy_top
// parameter IBUF_LPWR_MODE = "OFF",
// // to phy_top
parameter TCQ = 100,
//parameter IODELAY_GRP = "MIG_7SERIES_0_IODELAY_MIG",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency.
// parameter SYSCLK_TYPE = "SINGLE_ENDED",
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
// parameter REFCLK_TYPE = "USE_SYSTEM_CLOCK",
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
// parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
// Number of taps in target IDELAY
parameter integer DEVICE_TAPS = 32,
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
// parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
// parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination for idelay
// reference clock input pins
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
// parameter CLK_PERIOD = 2500,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 2,
// # of memory CKs per fabric CLK
// parameter DIFF_TERM_SYSCLK = "FALSE",
// Differential Termination for System
// clock input pins
//***************************************************************************
// Traffic Gen related parameters
//***************************************************************************
parameter BL_WIDTH = 8,
parameter PORT_MODE = "BI_MODE",
parameter DATA_MODE = 4'b0010,
parameter EYE_TEST = "FALSE",
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter DATA_PATTERN = "DGEN_ALL",
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL",
// "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
parameter CMD_WDT = 'h3FF,
parameter WR_WDT = 'h1FFF,
parameter RD_WDT = 'h3FF,
parameter BEGIN_ADDRESS = 32'h00000000,
parameter END_ADDRESS = 32'h00000fff,
parameter PRBS_EADDR_MASK_POS = 32'hfffff000,
//***************************************************************************
// Wait period for the read strobe (CQ) to become stable
//***************************************************************************
//parameter CLK_STABLE = (20*1000*1000/(CLK_PERIOD*2)),
// Cycles till CQ/CQ# is stable
//***************************************************************************
// Debug parameter
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
parameter RST_ACT_LOW = 1
// =1 for active low reset,
// =0 for active high.
)
(
// Single-ended system clock
input sys_clk_i,
input [0:0] qdriip_cq_p, //Memory Interface
input [0:0] qdriip_cq_n,
input [35:0] qdriip_q,
output wire [0:0] qdriip_k_p,
output wire [0:0] qdriip_k_n,
output wire [35:0] qdriip_d,
output wire [18:0] qdriip_sa,
output wire qdriip_w_n,
output wire qdriip_r_n,
output wire [3:0] qdriip_bw_n,
output wire qdriip_dll_off_n,
output tg_compare_error,
output init_calib_complete,
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
// clogb2 function - ceiling of log base 2
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
localparam APP_DATA_WIDTH = BURST_LEN*DATA_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 9;
// Number of bits needed to represent DEVICE_TAPS
localparam integer TAP_BITS = clogb2(DEVICE_TAPS - 1);
// Number of bits to represent number of cq/cq#'s
localparam integer CQ_BITS = clogb2(DATA_WIDTH/9 - 1);
// Number of bits needed to represent number of q's
localparam integer Q_BITS = clogb2(DATA_WIDTH - 1);
// Wire declarations
wire clk;
wire rst_clk;
wire cmp_err;
wire dbg_clear_error;
wire app_wr_cmd0;
wire app_wr_cmd1;
wire [ADDR_WIDTH-1:0] app_wr_addr0;
wire [ADDR_WIDTH-1:0] app_wr_addr1;
wire app_rd_cmd0;
wire app_rd_cmd1;
wire [ADDR_WIDTH-1:0] app_rd_addr0;
wire [ADDR_WIDTH-1:0] app_rd_addr1;
wire [(BURST_LEN*DATA_WIDTH)-1:0] app_wr_data0;
wire [(DATA_WIDTH*2)-1:0] app_wr_data1;
wire [(BURST_LEN*BW_WIDTH)-1:0] app_wr_bw_n0;
wire [(BW_WIDTH*2)-1:0] app_wr_bw_n1;
wire app_cal_done;
wire app_rd_valid0;
wire app_rd_valid1;
wire [(BURST_LEN*DATA_WIDTH)-1:0] app_rd_data0;
wire [(DATA_WIDTH*2)-1:0] app_rd_data1;
wire [(ADDR_WIDTH*2)-1:0] tg_addr;
wire [APP_DATA_WIDTH-1:0] cmp_data;
wire [47:0] wr_data_counts;
wire [47:0] rd_data_counts;
(*mark_debug = "TRUE" *) wire vio_modify_enable;
(*mark_debug = "TRUE" *) wire [3:0] vio_data_mode_value;
(*mark_debug = "TRUE" *) wire vio_pause_traffic;
(*mark_debug = "TRUE" *) wire [2:0] vio_addr_mode_value;
(*mark_debug = "TRUE" *) wire [3:0] vio_instr_mode_value;
(*mark_debug = "TRUE" *) wire [1:0] vio_bl_mode_value;
(*mark_debug = "TRUE" *) wire [7:0] vio_fixed_bl_value;
(*mark_debug = "TRUE" *) wire [2:0] vio_fixed_instr_value;
(*mark_debug = "TRUE" *) wire vio_data_mask_gen;
//***************************************************************************
// Start of User Design top instance
//***************************************************************************
// The User design is instantiated below. The memory interface ports are
// connected to the top-level and the application interface ports are
// connected to the traffic generator module. This provides a reference
// for connecting the memory controller to system.
//***************************************************************************
mig_7series_0 //#
// (
// #parameters_mapping_user_design_top_instance#
// .RST_ACT_LOW (RST_ACT_LOW)
// )
u_mig_7series_0
(
// Memory interface ports
.qdriip_cq_p (qdriip_cq_p),
.qdriip_cq_n (qdriip_cq_n),
.qdriip_q (qdriip_q),
.qdriip_k_p (qdriip_k_p),
.qdriip_k_n (qdriip_k_n),
.qdriip_d (qdriip_d),
.qdriip_sa (qdriip_sa),
.qdriip_w_n (qdriip_w_n),
.qdriip_r_n (qdriip_r_n),
.qdriip_bw_n (qdriip_bw_n),
.qdriip_dll_off_n (qdriip_dll_off_n),
.init_calib_complete (init_calib_complete),
// Application interface ports
.app_wr_cmd0 (app_wr_cmd0),
.app_wr_cmd1 (1'b0),
.app_wr_addr0 (app_wr_addr0),
.app_wr_addr1 ({ADDR_WIDTH{1'b0}}),
.app_rd_cmd0 (app_rd_cmd0),
.app_rd_cmd1 (1'b0),
.app_rd_addr0 (app_rd_addr0),
.app_rd_addr1 ({ADDR_WIDTH{1'b0}}),
.app_wr_data0 (app_wr_data0),
.app_wr_data1 ({DATA_WIDTH*2{1'b0}}),
.app_wr_bw_n0 ({BURST_LEN*BW_WIDTH{1'b0}}),
.app_wr_bw_n1 ({2*BW_WIDTH{1'b0}}),
.app_rd_valid0 (app_rd_valid0),
.app_rd_valid1 (app_rd_valid1),
.app_rd_data0 (app_rd_data0),
.app_rd_data1 (app_rd_data1),
.clk (clk),
.rst_clk (rst_clk),
// System Clock Ports
.sys_clk_i (sys_clk_i),
.sys_rst (sys_rst)
);
// End of User Design top instance
//***************************************************************************
// The traffic generation module instantiated below drives traffic (patterns)
// on the application interface of the memory controller
//***************************************************************************
assign app_wr_addr0 = tg_addr[ADDR_WIDTH-1:0];
assign app_rd_addr0 = tg_addr[ADDR_WIDTH-1:0];
mig_7series_v2_0_traffic_gen_top #
(
.TCQ (TCQ),
.SIMULATION (SIMULATION),
.FAMILY ("VIRTEX7"),
.MEM_TYPE (MEM_TYPE),
//.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.NUM_DQ_PINS (DATA_WIDTH),
.MEM_BURST_LEN (BURST_LEN),
.PORT_MODE (PORT_MODE),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.DATA_WIDTH (APP_DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.DATA_MODE (DATA_MODE),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.CMD_WDT (CMD_WDT),
.RD_WDT (RD_WDT),
.WR_WDT (WR_WDT),
.EYE_TEST (EYE_TEST)
)
u_traffic_gen_top
(
.clk (clk),
.rst (rst_clk),
.tg_only_rst (rst_clk),
.manual_clear_error (dbg_clear_error),
.memc_init_done (init_calib_complete),
.memc_cmd_full (1'b0),
.memc_cmd_en (),
.memc_cmd_instr (),
.memc_cmd_bl (),
.memc_cmd_addr (tg_addr[31:0]),
.memc_wr_en (),
.memc_wr_end (),
.memc_wr_mask (),
.memc_wr_data (app_wr_data0),
.memc_wr_full (1'b0),
.memc_rd_en (),
.memc_rd_data (app_rd_data0),
.memc_rd_empty (~app_rd_valid0),
.qdr_wr_cmd_o (app_wr_cmd0),
.qdr_rd_cmd_o (app_rd_cmd0),
.vio_pause_traffic (vio_pause_traffic),
.vio_modify_enable (vio_modify_enable),
.vio_data_mode_value (vio_data_mode_value),
.vio_addr_mode_value (vio_addr_mode_value),
.vio_instr_mode_value (vio_instr_mode_value),
.vio_bl_mode_value (vio_bl_mode_value),
.vio_fixed_bl_value (vio_fixed_bl_value),
.vio_fixed_instr_value(vio_fixed_instr_value),
.vio_data_mask_gen (vio_data_mask_gen),
.fixed_addr_i (32'b0),
.fixed_data_i (32'b0),
.simple_data0 (32'b0),
.simple_data1 (32'b0),
.simple_data2 (32'b0),
.simple_data3 (32'b0),
.simple_data4 (32'b0),
.simple_data5 (32'b0),
.simple_data6 (32'b0),
.simple_data7 (32'b0),
.wdt_en_i (1'b1),
.bram_cmd_i (39'b0),
.bram_valid_i (1'b0),
.bram_rdy_o (),
.cmp_data (cmp_data),
.cmp_data_valid (),
.cmp_error (dbg_cmp_err),
.wr_data_counts (wr_data_counts),
.rd_data_counts (rd_data_counts),
.cumlative_dq_lane_error (),
.cmd_wdt_err_o (),
.wr_wdt_err_o (),
.rd_wdt_err_o (),
.mem_pattern_init_done(),
.error (tg_compare_error),
.error_status ()
);
//*****************************************************************
// Default values are assigned to the debug inputs of the traffic
// generator
//*****************************************************************
assign vio_modify_enable = 1'b0;
assign vio_data_mode_value = 4'b0010;
assign vio_addr_mode_value = 3'b011;
assign vio_instr_mode_value = 4'b0010;
assign vio_bl_mode_value = 2'b10;
assign vio_fixed_bl_value = 8'd32;
assign vio_data_mask_gen = 1'b0;
assign vio_pause_traffic = 1'b0;
assign vio_fixed_instr_value = 3'b001;
assign dbg_clear_error = 1'b0;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_alt_lvds_rx (
// physical interface (receive)
rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
// data interface
clk,
rx_frame,
rx_data_0,
rx_data_1,
rx_data_2,
rx_data_3,
rx_locked);
// physical interface (receive)
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
// data interface
output clk;
output [ 3:0] rx_frame;
output [ 5:0] rx_data_0;
output [ 5:0] rx_data_1;
output [ 5:0] rx_data_2;
output [ 5:0] rx_data_3;
output rx_locked;
// internal signals
wire [27:0] rx_data_s;
// instantiations
assign rx_frame[3] = rx_data_s[24];
assign rx_frame[2] = rx_data_s[25];
assign rx_frame[1] = rx_data_s[26];
assign rx_frame[0] = rx_data_s[27];
assign rx_data_3[5] = rx_data_s[20];
assign rx_data_3[4] = rx_data_s[16];
assign rx_data_3[3] = rx_data_s[12];
assign rx_data_3[2] = rx_data_s[ 8];
assign rx_data_3[1] = rx_data_s[ 4];
assign rx_data_3[0] = rx_data_s[ 0];
assign rx_data_2[5] = rx_data_s[21];
assign rx_data_2[4] = rx_data_s[17];
assign rx_data_2[3] = rx_data_s[13];
assign rx_data_2[2] = rx_data_s[ 9];
assign rx_data_2[1] = rx_data_s[ 5];
assign rx_data_2[0] = rx_data_s[ 1];
assign rx_data_1[5] = rx_data_s[22];
assign rx_data_1[4] = rx_data_s[18];
assign rx_data_1[3] = rx_data_s[14];
assign rx_data_1[2] = rx_data_s[10];
assign rx_data_1[1] = rx_data_s[ 6];
assign rx_data_1[0] = rx_data_s[ 2];
assign rx_data_0[5] = rx_data_s[23];
assign rx_data_0[4] = rx_data_s[19];
assign rx_data_0[3] = rx_data_s[15];
assign rx_data_0[2] = rx_data_s[11];
assign rx_data_0[1] = rx_data_s[ 7];
assign rx_data_0[0] = rx_data_s[ 3];
altlvds_rx #(
.buffer_implementation ("RAM"),
.cds_mode ("UNUSED"),
.common_rx_tx_pll ("ON"),
.data_align_rollover (4),
.data_rate ("500.0 Mbps"),
.deserialization_factor (4),
.dpa_initial_phase_value (0),
.dpll_lock_count (0),
.dpll_lock_window (0),
.enable_clock_pin_mode ("UNUSED"),
.enable_dpa_align_to_rising_edge_only ("OFF"),
.enable_dpa_calibration ("ON"),
.enable_dpa_fifo ("UNUSED"),
.enable_dpa_initial_phase_selection ("OFF"),
.enable_dpa_mode ("OFF"),
.enable_dpa_pll_calibration ("OFF"),
.enable_soft_cdr_mode ("OFF"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (4000),
.inclock_phase_shift (0),
.input_data_rate (500),
.intended_device_family ("Cyclone V"),
.lose_lock_on_one_change ("UNUSED"),
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_rx"),
.lpm_type ("altlvds_rx"),
.number_of_channels (7),
.outclock_resource ("Regional clock"),
.pll_operation_mode ("NORMAL"),
.pll_self_reset_on_loss_lock ("UNUSED"),
.port_rx_channel_data_align ("PORT_UNUSED"),
.port_rx_data_align ("PORT_UNUSED"),
.refclk_frequency ("250.000000 MHz"),
.registered_data_align_input ("UNUSED"),
.registered_output ("ON"),
.reset_fifo_at_first_lock ("UNUSED"),
.rx_align_data_reg ("RISING_EDGE"),
.sim_dpa_is_negative_ppm_drift ("OFF"),
.sim_dpa_net_ppm_variation (0),
.sim_dpa_output_clock_phase_shift (0),
.use_coreclock_input ("OFF"),
.use_dpll_rawperror ("OFF"),
.use_external_pll ("OFF"),
.use_no_phase_shift ("ON"),
.x_on_bitslip ("ON"),
.clk_src_is_pll ("off"))
i_altlvds_rx (
.rx_inclock (rx_clk_in_p),
.rx_in ({rx_frame_in_p, rx_data_in_p}),
.rx_outclock (clk),
.rx_out (rx_data_s),
.rx_locked (rx_locked),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_areset (1'b0),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
.pll_phaseupdown (),
.pll_scanclk (),
.rx_cda_max (),
.rx_cda_reset ({7{1'b0}}),
.rx_channel_data_align ({7{1'b0}}),
.rx_coreclk ({7{1'b1}}),
.rx_data_align (1'b0),
.rx_data_align_reset (1'b0),
.rx_data_reset (1'b0),
.rx_deskew (1'b0),
.rx_divfwdclk (),
.rx_dpa_lock_reset ({7{1'b0}}),
.rx_dpa_locked (),
.rx_dpaclock (1'b0),
.rx_dpll_enable ({7{1'b1}}),
.rx_dpll_hold ({7{1'b0}}),
.rx_dpll_reset ({7{1'b0}}),
.rx_enable (1'b1),
.rx_fifo_reset ({7{1'b0}}),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_reset ({7{1'b0}}),
.rx_syncclock (1'b0));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAP_SYMBOL_V
`define SKY130_FD_SC_LP__DECAP_SYMBOL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAP_SYMBOL_V
|
module dct_ctrl(
clk,
rst,
i_valid,
i_transize,
i_valid_4,
i_transize_1,
i_transize_2,
i_transize_3,
i_transize_4
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk;
input rst;
input i_valid;
input [1:0] i_transize;
output reg i_valid_4;
output reg [1:0] i_transize_1;
output reg [1:0] i_transize_2;
output reg [1:0] i_transize_3;
output reg [1:0] i_transize_4;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg i_valid_1;
reg i_valid_2;
reg i_valid_3;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always@(posedge clk or negedge rst)
if(!rst)
i_transize_1<=2'b00;
else
i_transize_1<=i_transize;
always@(posedge clk or negedge rst)
if(!rst)
i_transize_2<=2'b00;
else
i_transize_2<=i_transize_1;
always@(posedge clk or negedge rst)
if(!rst)
i_transize_3<=2'b00;
else
i_transize_3<=i_transize_2;
always@(posedge clk or negedge rst)
if(!rst)
i_transize_4<=2'b00;
else
i_transize_4<=i_transize_3;
always@(posedge clk or negedge rst)
if(!rst)
i_valid_1<=1'b0;
else
i_valid_1<=i_valid;
always@(posedge clk or negedge rst)
if(!rst)
i_valid_2<=1'b0;
else
i_valid_2<=i_valid_1;
always@(posedge clk or negedge rst)
if(!rst)
i_valid_3<=1'b0;
else
i_valid_3<=i_valid_2;
always@(posedge clk or negedge rst)
if(!rst)
i_valid_4<=1'b0;
else
i_valid_4<=i_valid_3;
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
Set Universe Polymorphism.
Definition crelation (A : Type) := A -> A -> Type.
Definition arrow (A B : Type) := A -> B.
Definition flip {A B C : Type} (f : A -> B -> C) := fun x y => f y x.
Definition iffT (A B : Type) := ((A -> B) * (B -> A))%type.
(** We allow to unfold the [crelation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind crelational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : crelation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : crelation A) : crelation A :=
fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement iffT.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : crelation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : crelation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : crelation A) :=
asymmetry : forall {x y}, R x y -> (complement R y x : Type).
Class Transitive (R : crelation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : crelation A) := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : crelation A) := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence crelation is Symmetric and Transitive. *)
Class PER (R : crelation A) := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence crelations. *)
Class Equivalence (R : crelation A) := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(Equivalence R) : PER R | 10 :=
{ PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive }.
(** We can now define antisymmetry w.r.t. an equivalence crelation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : crelation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : crelation A) :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric crelation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros x y H'. red in H'. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite crelation on a given support: declares a crelation as a rewrite
crelation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
crelations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : crelation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite crelation. *)
Global Instance equivalence_rewrite_crelation `(Equivalence eqA) : RewriteRelation eqA.
Defined.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence crelation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite crelations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Defined.
Instance: RewriteRelation iff.
Defined.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for crelations. *)
Ltac solve_crelation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_crelation : crelations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_crelation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_crelation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence crelation. *)
Program Instance iff_equivalence : Equivalence iff.
Program Instance arrow_Reflexive : Reflexive arrow.
Program Instance arrow_Transitive : Transitive arrow.
Instance iffT_Reflexive : Reflexive iffT.
Proof. firstorder. Defined.
Instance iffT_Symmetric : Symmetric iffT.
Proof. firstorder. Defined.
Instance iffT_Transitive : Transitive iffT.
Proof. firstorder. Defined.
(** We now develop a generalization of results on crelations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary crelations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(** We define the various operations which define the algebra on binary crelations *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : crelation (crelation A) :=
fun R R' => forall x y, iffT (R x y) (R' x y).
Global Instance: RewriteRelation relation_equivalence.
Defined.
Definition relation_conjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => prod (R x y) (R' x y).
Definition relation_disjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => sum (R x y) (R' x y).
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof. split; red; unfold relation_equivalence, iffT. firstorder.
firstorder.
intros. specialize (X x0 y0). specialize (X0 x0 y0). firstorder.
Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. firstorder. Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence crelation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
apply H. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof. unfold flip; constructor; unfold flip. intros. apply H. apply symmetry. apply X.
unfold relation_conjunction. intros [H1 H2]. apply H. constructor; assumption. Qed.
End Binary.
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and crelation equivalence. *)
(* Program Instance subrelation_partial_order : *)
(* ! PartialOrder (crelation A) relation_equivalence subrelation. *)
(* Obligation Tactic := idtac. *)
(* Next Obligation. *)
(* Proof. *)
(* intros x. refine (fun x => x). *)
(* Qed. *)
Typeclasses Opaque relation_equivalence.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_PP_SYMBOL_V
`define SKY130_FD_SC_HD__INV_PP_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__inv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_PP_SYMBOL_V
|
(** * Maps: Total and Partial Maps *)
(** Maps (or dictionaries) are ubiquitous data structures, both in
software construction generally and in the theory of programming
languages in particular; we're going to need them in many places
in the coming chapters. They also make a nice case study using
ideas we've seen in previous chapters, including building data
structures out of higher-order functions (from [Basics] and
[Poly]) and the use of reflection to streamline proofs (from
[IndProp]).
We'll define two flavors of maps: _total_ maps, which include a
"default" element to be returned when a key being looked up
doesn't exist, and _partial_ maps, which return an [option] to
indicate success or failure. The latter is defined in terms of
the former, using [None] as the default element. *)
(* ################################################################# *)
(** * The Coq Standard Library *)
(** One small digression before we start.
Unlike the chapters we have seen so far, this one does not
[Require Import] the chapter before it (and, transitively, all the
earlier chapters). Instead, in this chapter and from now, on
we're going to import the definitions and theorems we need
directly from Coq's standard library stuff. You should not notice
much difference, though, because we've been careful to name our
own definitions and theorems the same as their counterparts in the
standard library, wherever they overlap. *)
Require Import Coq.Arith.Arith.
Require Import Coq.Bool.Bool.
Require Import Coq.Logic.FunctionalExtensionality.
(** Documentation for the standard library can be found at
http://coq.inria.fr/library/.
The [SearchAbout] command is a good way to look for theorems
involving objects of specific types. *)
(* ################################################################# *)
(** * Identifiers *)
(** First, we need a type for the keys that we use to index into our
maps. For this purpose, we again use the type [id] from the
[Lists] chapter. To make this chapter self contained, we repeat
its definition here, together with the equality comparison
function for [id]s and its fundamental property. *)
Inductive id : Type :=
| Id : nat -> id.
Definition beq_id id1 id2 :=
match id1,id2 with
| Id n1, Id n2 => beq_nat n1 n2
end.
Theorem beq_id_refl : forall id, true = beq_id id id.
Proof.
intros [n]. simpl. rewrite <- beq_nat_refl.
reflexivity. Qed.
(** The following useful property of [beq_id] follows from an
analogous lemma about numbers: *)
Theorem beq_id_true_iff : forall id1 id2 : id,
beq_id id1 id2 = true <-> id1 = id2.
Proof.
intros [n1] [n2].
unfold beq_id.
rewrite beq_nat_true_iff.
split.
- (* -> *) intros H. rewrite H. reflexivity.
- (* <- *) intros H. inversion H. reflexivity.
Qed.
(** Similarly: *)
Theorem beq_id_false_iff : forall x y : id,
beq_id x y = false
<-> x <> y.
Proof.
intros x y. rewrite <- beq_id_true_iff.
rewrite not_true_iff_false. reflexivity. Qed.
(** This useful variant follows just by rewriting: *)
Theorem false_beq_id : forall x y : id,
x <> y
-> beq_id x y = false.
Proof.
intros x y. rewrite beq_id_false_iff.
intros H. apply H. Qed.
(* ################################################################# *)
(** * Total Maps *)
(** Our main job in this chapter will be to build a definition of
partial maps that is similar in behavior to the one we saw in the
[Lists] chapter, plus accompanying lemmas about their behavior.
This time around, though, we're going to use _functions_, rather
than lists of key-value pairs, to build maps. The advantage of
this representation is that it offers a more _extensional_ view of
maps, where two maps that respond to queries in the same way will
be represented as literally the same thing (the same function),
rather than just "equivalent" data structures. This, in turn,
simplifies proofs that use maps.
We build partial maps in two steps. First, we define a type of
_total maps_ that return a default value when we look up a key
that is not present in the map. *)
Definition total_map (A:Type) := id -> A.
(** Intuitively, a total map over an element type [A] _is_ just a
function that can be used to look up [id]s, yielding [A]s.
The function [t_empty] yields an empty total map, given a default
element; this map always returns the default element when applied
to any id. *)
Definition t_empty {A:Type} (v : A) : total_map A :=
(fun _ => v).
(** More interesting is the [update] function, which (as before) takes
a map [m], a key [x], and a value [v] and returns a new map that
takes [x] to [v] and takes every other key to whatever [m] does. *)
Definition t_update {A:Type} (m : total_map A)
(x : id) (v : A) :=
fun x' => if beq_id x x' then v else m x'.
(** This definition is a nice example of higher-order programming.
The [t_update] function takes a _function_ [m] and yields a new
function [fun x' => ...] that behaves like the desired map.
For example, we can build a map taking [id]s to [bool]s, where [Id
3] is mapped to [true] and every other key is mapped to [false],
like this: *)
Definition examplemap :=
t_update (t_update (t_empty false) (Id 1) false)
(Id 3) true.
(** This completes the definition of total maps. Note that we don't
need to define a [find] operation because it is just function
application! *)
Example update_example1 : examplemap (Id 0) = false.
Proof. reflexivity. Qed.
Example update_example2 : examplemap (Id 1) = false.
Proof. reflexivity. Qed.
Example update_example3 : examplemap (Id 2) = false.
Proof. reflexivity. Qed.
Example update_example4 : examplemap (Id 3) = true.
Proof. reflexivity. Qed.
(** To use maps in later chapters, we'll need several fundamental
facts about how they behave. Even if you don't work the following
exercises, make sure you thoroughly understand the statements of
the lemmas! (Some of the proofs require the functional
extensionality axiom discussed in the [Logic] chapter, which is
also included in the standard library.) *)
(** **** Exercise: 2 stars, optional (t_update_eq) *)
(** First, if we update a map [m] at a key [x] with a new value [v]
and then look up [x] in the map resulting from the [update], we
get back [v]: *)
Lemma t_update_eq : forall A (m: total_map A) x v,
(t_update m x v) x = v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_neq) *)
(** On the other hand, if we update a map [m] at a key [x1] and then
look up a _different_ key [x2] in the resulting map, we get the
same result that [m] would have given: *)
Theorem t_update_neq : forall (X:Type) v x1 x2
(m : total_map X),
x1 <> x2 ->
(t_update m x1 v) x2 = m x2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_shadow) *)
(** If we update a map [m] at a key [x] with a value [v1] and then
update again with the same key [x] and another value [v2], the
resulting map behaves the same (gives the same result when applied
to any key) as the simpler map obtained by performing just
the second [update] on [m]: *)
Lemma t_update_shadow : forall A (m: total_map A) v1 v2 x,
t_update (t_update m x v1) x v2
= t_update m x v2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** For the final two lemmas about total maps, it's convenient to use
the reflection idioms introduced in chapter [IndProp]. We begin
by proving a fundamental _reflection lemma_ relating the equality
proposition on [id]s with the boolean function [beq_id]. *)
(** **** Exercise: 2 stars (beq_idP) *)
(** Use the proof of [beq_natP] in chapter [IndProp] as a template to
prove the following: *)
Lemma beq_idP : forall x y, reflect (x = y) (beq_id x y).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Now, given [id]s [x1] and [x2], we can use the [destruct (beq_idP
x1 x2)] to simultaneously perform case analysis on the result of
[beq_id x1 x2] and generate hypotheses about the equality (in the
sense of [=]) of [x1] and [x2]. *)
(** **** Exercise: 2 stars (t_update_same) *)
(** Using the example in chapter [IndProp] as a template, use
[beq_idP] to prove the following theorem, which states that if we
update a map to assign key [x] the same value as it already has in
[m], then the result is equal to [m]: *)
Theorem t_update_same : forall X x (m : total_map X),
t_update m x (m x) = m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, recommended (t_update_permute) *)
(** Use [beq_idP] to prove one final property of the [update]
function: If we update a map [m] at two distinct keys, it doesn't
matter in which order we do the updates. *)
Theorem t_update_permute : forall (X:Type) v1 v2 x1 x2
(m : total_map X),
x2 <> x1 ->
(t_update (t_update m x2 v2) x1 v1)
= (t_update (t_update m x1 v1) x2 v2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Partial maps *)
(** Finally, we define _partial maps_ on top of total maps. A partial
map with elements of type [A] is simply a total map with elements
of type [option A] and default element [None]. *)
Definition partial_map (A:Type) := total_map (option A).
Definition empty {A:Type} : partial_map A :=
t_empty None.
Definition update {A:Type} (m : partial_map A)
(x : id) (v : A) :=
t_update m x (Some v).
(** We can now lift all of the basic lemmas about total maps to
partial maps. *)
Lemma update_eq : forall A (m: partial_map A) x v,
(update m x v) x = Some v.
Proof.
intros. unfold update. rewrite t_update_eq.
reflexivity.
Qed.
Theorem update_neq : forall (X:Type) v x1 x2
(m : partial_map X),
x2 <> x1 ->
(update m x2 v) x1 = m x1.
Proof.
intros X v x1 x2 m H.
unfold update. rewrite t_update_neq. reflexivity.
apply H. Qed.
Lemma update_shadow : forall A (m: partial_map A) v1 v2 x,
update (update m x v1) x v2 = update m x v2.
Proof.
intros A m v1 v2 x1. unfold update. rewrite t_update_shadow.
reflexivity.
Qed.
Theorem update_same : forall X v x (m : partial_map X),
m x = Some v ->
update m x v = m.
Proof.
intros X v x m H. unfold update. rewrite <- H.
apply t_update_same.
Qed.
Theorem update_permute : forall (X:Type) v1 v2 x1 x2
(m : partial_map X),
x2 <> x1 ->
(update (update m x2 v2) x1 v1)
= (update (update m x1 v1) x2 v2).
Proof.
intros X v1 v2 x1 x2 m. unfold update.
apply t_update_permute.
Qed.
(** $Date: 2015-12-11 17:17:29 -0500 (Fri, 11 Dec 2015) $ *)
|
`default_nettype none
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y, CO;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BX = B_buf;
wire [Y_WIDTH:0] ALM_CARRY;
// Start of carry chain
generate
if (_TECHMAP_CONSTMSK_CI_ == 1) begin
assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
end else begin
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)
) alm_start (
.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
.CI(1'b0),
.CO(ALM_CARRY[0])
);
end
endgenerate
// Carry chain
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
// TODO: mwk suggests that a pass could merge pre-adder logic into this.
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b1100_0011_1100_0011), // Q = C ? B : ~B (LUT1's input to the adder is inverted)
) alm_i (
.A(AA[i]), .B(BX[i]), .C(BI), .D0(1'b1), .D1(1'b1),
.CI(ALM_CARRY[i]),
.SO(Y[i]),
.CO(ALM_CARRY[i+1])
);
// ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed.
assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
end endgenerate
assign X = AA ^ BB;
endmodule
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream broadcaster
*/
module axis_broadcast #
(
// Number of AXI stream outputs
parameter M_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI outputs
*/
output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep,
output wire [M_COUNT-1:0] m_axis_tvalid,
input wire [M_COUNT-1:0] m_axis_tready,
output wire [M_COUNT-1:0] m_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser
);
parameter CL_M_COUNT = $clog2(M_COUNT);
// datapath registers
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}}, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// // datapath control
reg store_axis_input_to_output;
reg store_axis_input_to_temp;
reg store_axis_temp_to_output;
assign s_axis_tready = s_axis_tready_reg;
assign m_axis_tdata = {M_COUNT{m_axis_tdata_reg}};
assign m_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_axis_tkeep_reg}} : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = LAST_ENABLE ? {M_COUNT{m_axis_tlast_reg}} : {M_COUNT{1'b1}};
assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !s_axis_tvalid));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg & ~m_axis_tready;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_input_to_output = 1'b0;
store_axis_input_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (s_axis_tready_reg) begin
// input is ready
if (((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || !m_axis_tvalid) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = {M_COUNT{s_axis_tvalid}};
store_axis_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = s_axis_tvalid;
store_axis_input_to_temp = 1'b1;
end
end else if ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) begin
// input is not ready, but output is ready
m_axis_tvalid_next = {M_COUNT{temp_m_axis_tvalid_reg}};
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
s_axis_tready_reg <= 1'b0;
m_axis_tvalid_reg <= {M_COUNT{1'b0}};
temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
end else begin
s_axis_tready_reg <= s_axis_tready_early;
m_axis_tvalid_reg <= m_axis_tvalid_next;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_input_to_output) begin
m_axis_tdata_reg <= s_axis_tdata;
m_axis_tkeep_reg <= s_axis_tkeep;
m_axis_tlast_reg <= s_axis_tlast;
m_axis_tid_reg <= s_axis_tid;
m_axis_tdest_reg <= s_axis_tdest;
m_axis_tuser_reg <= s_axis_tuser;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_input_to_temp) begin
temp_m_axis_tdata_reg <= s_axis_tdata;
temp_m_axis_tkeep_reg <= s_axis_tkeep;
temp_m_axis_tlast_reg <= s_axis_tlast;
temp_m_axis_tid_reg <= s_axis_tid;
temp_m_axis_tdest_reg <= s_axis_tdest;
temp_m_axis_tuser_reg <= s_axis_tuser;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Fri Oct 28 10:03:51 2016
/////////////////////////////////////////////////////////////
module mult_SW24 ( clk, Data_A_i, Data_B_i, Data_S_o );
input [23:0] Data_A_i;
input [23:0] Data_B_i;
output [47:0] Data_S_o;
input clk;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15,
N16, N17, N18, N19, N20, N21, N22, N23, N24, N25, N26, N27, N28, N29,
N30, N31, N32, N33, N34, N35, N36, N37, N38, N39, N40, N41, N42, N43,
N44, N45, N46, N47, mult_x_1_n1366, mult_x_1_n1365, mult_x_1_n1364,
mult_x_1_n1363, mult_x_1_n1361, mult_x_1_n1360, mult_x_1_n1359,
mult_x_1_n1358, mult_x_1_n1357, mult_x_1_n1356, mult_x_1_n1355,
mult_x_1_n1354, mult_x_1_n1353, mult_x_1_n1352, mult_x_1_n1351,
mult_x_1_n1350, mult_x_1_n1342, mult_x_1_n1341, mult_x_1_n1340,
mult_x_1_n1339, mult_x_1_n1338, mult_x_1_n1337, mult_x_1_n1336,
mult_x_1_n1335, mult_x_1_n1334, mult_x_1_n1333, mult_x_1_n1332,
mult_x_1_n1331, mult_x_1_n1330, mult_x_1_n1329, mult_x_1_n1328,
mult_x_1_n1327, mult_x_1_n1326, mult_x_1_n1325, mult_x_1_n1324,
mult_x_1_n1323, mult_x_1_n1318, mult_x_1_n1317, mult_x_1_n1316,
mult_x_1_n1315, mult_x_1_n1314, mult_x_1_n1312, mult_x_1_n1311,
mult_x_1_n1310, mult_x_1_n1309, mult_x_1_n1307, mult_x_1_n1306,
mult_x_1_n1305, mult_x_1_n1304, mult_x_1_n1303, mult_x_1_n1302,
mult_x_1_n1301, mult_x_1_n1300, mult_x_1_n1299, mult_x_1_n1298,
mult_x_1_n1297, mult_x_1_n1296, mult_x_1_n1288, mult_x_1_n1287,
mult_x_1_n1286, mult_x_1_n1285, mult_x_1_n1284, mult_x_1_n1283,
mult_x_1_n1282, mult_x_1_n1281, mult_x_1_n1280, mult_x_1_n1279,
mult_x_1_n1278, mult_x_1_n1277, mult_x_1_n1276, mult_x_1_n1275,
mult_x_1_n1274, mult_x_1_n1273, mult_x_1_n1272, mult_x_1_n1271,
mult_x_1_n1270, mult_x_1_n1269, mult_x_1_n1264, mult_x_1_n1263,
mult_x_1_n1262, mult_x_1_n1261, mult_x_1_n1260, mult_x_1_n1258,
mult_x_1_n1257, mult_x_1_n1256, mult_x_1_n1255, mult_x_1_n1253,
mult_x_1_n1252, mult_x_1_n1251, mult_x_1_n1250, mult_x_1_n1249,
mult_x_1_n1248, mult_x_1_n1247, mult_x_1_n1246, mult_x_1_n1245,
mult_x_1_n1244, mult_x_1_n1243, mult_x_1_n1242, mult_x_1_n1234,
mult_x_1_n1233, mult_x_1_n1232, mult_x_1_n1231, mult_x_1_n1230,
mult_x_1_n1229, mult_x_1_n1228, mult_x_1_n1226, mult_x_1_n1225,
mult_x_1_n1224, mult_x_1_n1223, mult_x_1_n1222, mult_x_1_n1221,
mult_x_1_n1220, mult_x_1_n1219, mult_x_1_n1218, mult_x_1_n1217,
mult_x_1_n1210, mult_x_1_n1209, mult_x_1_n1208, mult_x_1_n1207,
mult_x_1_n1206, mult_x_1_n1204, mult_x_1_n1203, mult_x_1_n1202,
mult_x_1_n1201, mult_x_1_n1200, mult_x_1_n1199, mult_x_1_n1198,
mult_x_1_n1197, mult_x_1_n1196, mult_x_1_n1195, mult_x_1_n1194,
mult_x_1_n1193, mult_x_1_n1192, mult_x_1_n1191, mult_x_1_n1190,
mult_x_1_n1189, mult_x_1_n1188, mult_x_1_n1181, mult_x_1_n1179,
mult_x_1_n1178, mult_x_1_n1177, mult_x_1_n1176, mult_x_1_n1175,
mult_x_1_n1172, mult_x_1_n1171, mult_x_1_n1170, mult_x_1_n1169,
mult_x_1_n1168, mult_x_1_n1167, mult_x_1_n1166, mult_x_1_n1165,
mult_x_1_n1164, mult_x_1_n1163, mult_x_1_n907, mult_x_1_n906,
mult_x_1_n905, mult_x_1_n901, mult_x_1_n900, mult_x_1_n899,
mult_x_1_n895, mult_x_1_n894, mult_x_1_n893, mult_x_1_n874,
mult_x_1_n871, mult_x_1_n869, mult_x_1_n868, mult_x_1_n867,
mult_x_1_n866, mult_x_1_n864, mult_x_1_n863, mult_x_1_n862,
mult_x_1_n861, mult_x_1_n859, mult_x_1_n858, mult_x_1_n857,
mult_x_1_n854, mult_x_1_n853, mult_x_1_n852, mult_x_1_n851,
mult_x_1_n850, mult_x_1_n847, mult_x_1_n846, mult_x_1_n845,
mult_x_1_n844, mult_x_1_n843, mult_x_1_n841, mult_x_1_n840,
mult_x_1_n839, mult_x_1_n838, mult_x_1_n837, mult_x_1_n836,
mult_x_1_n835, mult_x_1_n833, mult_x_1_n832, mult_x_1_n831,
mult_x_1_n830, mult_x_1_n829, mult_x_1_n828, mult_x_1_n827,
mult_x_1_n825, mult_x_1_n824, mult_x_1_n823, mult_x_1_n822,
mult_x_1_n821, mult_x_1_n820, mult_x_1_n819, mult_x_1_n817,
mult_x_1_n816, mult_x_1_n815, mult_x_1_n814, mult_x_1_n813,
mult_x_1_n812, mult_x_1_n809, mult_x_1_n808, mult_x_1_n807,
mult_x_1_n806, mult_x_1_n805, mult_x_1_n804, mult_x_1_n803,
mult_x_1_n802, mult_x_1_n799, mult_x_1_n798, mult_x_1_n797,
mult_x_1_n796, mult_x_1_n795, mult_x_1_n794, mult_x_1_n793,
mult_x_1_n792, mult_x_1_n790, mult_x_1_n789, mult_x_1_n788,
mult_x_1_n787, mult_x_1_n786, mult_x_1_n785, mult_x_1_n784,
mult_x_1_n783, mult_x_1_n782, mult_x_1_n781, mult_x_1_n779,
mult_x_1_n778, mult_x_1_n777, mult_x_1_n776, mult_x_1_n775,
mult_x_1_n774, mult_x_1_n773, mult_x_1_n772, mult_x_1_n771,
mult_x_1_n770, mult_x_1_n768, mult_x_1_n767, mult_x_1_n766,
mult_x_1_n765, mult_x_1_n764, mult_x_1_n763, mult_x_1_n762,
mult_x_1_n761, mult_x_1_n760, mult_x_1_n759, mult_x_1_n757,
mult_x_1_n756, mult_x_1_n755, mult_x_1_n754, mult_x_1_n753,
mult_x_1_n752, mult_x_1_n751, mult_x_1_n750, mult_x_1_n749,
mult_x_1_n748, mult_x_1_n747, mult_x_1_n746, mult_x_1_n745,
mult_x_1_n744, mult_x_1_n743, mult_x_1_n742, mult_x_1_n741,
mult_x_1_n740, mult_x_1_n739, mult_x_1_n738, mult_x_1_n737,
mult_x_1_n736, mult_x_1_n735, mult_x_1_n734, mult_x_1_n733,
mult_x_1_n732, mult_x_1_n731, mult_x_1_n730, mult_x_1_n729,
mult_x_1_n728, mult_x_1_n727, mult_x_1_n726, mult_x_1_n725,
mult_x_1_n724, mult_x_1_n723, mult_x_1_n722, mult_x_1_n721,
mult_x_1_n720, mult_x_1_n719, mult_x_1_n718, mult_x_1_n717,
mult_x_1_n716, mult_x_1_n715, mult_x_1_n714, mult_x_1_n713,
mult_x_1_n712, mult_x_1_n711, mult_x_1_n710, mult_x_1_n709,
mult_x_1_n708, mult_x_1_n707, mult_x_1_n706, mult_x_1_n705,
mult_x_1_n704, mult_x_1_n703, mult_x_1_n702, mult_x_1_n701,
mult_x_1_n700, mult_x_1_n699, mult_x_1_n698, mult_x_1_n697,
mult_x_1_n696, mult_x_1_n695, mult_x_1_n694, mult_x_1_n693,
mult_x_1_n692, mult_x_1_n691, mult_x_1_n690, mult_x_1_n689,
mult_x_1_n688, mult_x_1_n687, mult_x_1_n686, mult_x_1_n685,
mult_x_1_n684, mult_x_1_n683, mult_x_1_n682, mult_x_1_n681,
mult_x_1_n680, mult_x_1_n679, mult_x_1_n678, mult_x_1_n677,
mult_x_1_n676, mult_x_1_n675, mult_x_1_n674, mult_x_1_n673,
mult_x_1_n671, mult_x_1_n670, mult_x_1_n669, mult_x_1_n668,
mult_x_1_n667, mult_x_1_n666, mult_x_1_n665, mult_x_1_n664,
mult_x_1_n663, mult_x_1_n662, mult_x_1_n661, mult_x_1_n660,
mult_x_1_n659, mult_x_1_n658, mult_x_1_n657, mult_x_1_n656,
mult_x_1_n655, mult_x_1_n654, mult_x_1_n652, mult_x_1_n651,
mult_x_1_n650, mult_x_1_n649, mult_x_1_n648, mult_x_1_n647,
mult_x_1_n646, mult_x_1_n645, mult_x_1_n643, mult_x_1_n642,
mult_x_1_n641, mult_x_1_n640, mult_x_1_n639, mult_x_1_n638,
mult_x_1_n637, mult_x_1_n636, mult_x_1_n635, mult_x_1_n634,
mult_x_1_n633, mult_x_1_n632, mult_x_1_n631, mult_x_1_n630,
mult_x_1_n629, mult_x_1_n628, mult_x_1_n627, mult_x_1_n626,
mult_x_1_n625, mult_x_1_n624, mult_x_1_n623, mult_x_1_n622,
mult_x_1_n621, mult_x_1_n619, mult_x_1_n618, mult_x_1_n617,
mult_x_1_n616, mult_x_1_n615, mult_x_1_n614, mult_x_1_n613,
mult_x_1_n612, mult_x_1_n611, mult_x_1_n610, mult_x_1_n609,
mult_x_1_n608, mult_x_1_n606, mult_x_1_n605, mult_x_1_n604,
mult_x_1_n603, mult_x_1_n602, mult_x_1_n600, mult_x_1_n599,
mult_x_1_n598, mult_x_1_n597, mult_x_1_n596, mult_x_1_n595,
mult_x_1_n594, mult_x_1_n593, mult_x_1_n592, mult_x_1_n591,
mult_x_1_n590, mult_x_1_n589, mult_x_1_n588, mult_x_1_n587,
mult_x_1_n585, mult_x_1_n584, mult_x_1_n583, mult_x_1_n582,
mult_x_1_n581, mult_x_1_n580, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24,
n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38,
n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52,
n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66,
n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80,
n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94,
n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106,
n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128,
n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139,
n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150,
n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161,
n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172,
n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194,
n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205,
n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216,
n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227,
n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238,
n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249,
n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260,
n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271,
n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282,
n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370,
n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381,
n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414,
n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425,
n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436,
n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458,
n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480,
n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491,
n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502,
n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513,
n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535,
n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351;
DFFQX1TS Data_S_o_reg_47_ ( .D(N47), .CK(clk), .Q(Data_S_o[47]) );
DFFQX1TS Data_S_o_reg_46_ ( .D(N46), .CK(clk), .Q(Data_S_o[46]) );
DFFQX1TS Data_S_o_reg_45_ ( .D(N45), .CK(clk), .Q(Data_S_o[45]) );
DFFQX1TS Data_S_o_reg_44_ ( .D(N44), .CK(clk), .Q(Data_S_o[44]) );
DFFQX1TS Data_S_o_reg_43_ ( .D(N43), .CK(clk), .Q(Data_S_o[43]) );
DFFQX1TS Data_S_o_reg_42_ ( .D(N42), .CK(clk), .Q(Data_S_o[42]) );
DFFQX1TS Data_S_o_reg_41_ ( .D(N41), .CK(clk), .Q(Data_S_o[41]) );
DFFQX1TS Data_S_o_reg_40_ ( .D(N40), .CK(clk), .Q(Data_S_o[40]) );
DFFQX1TS Data_S_o_reg_39_ ( .D(N39), .CK(clk), .Q(Data_S_o[39]) );
DFFQX1TS Data_S_o_reg_38_ ( .D(N38), .CK(clk), .Q(Data_S_o[38]) );
DFFQX1TS Data_S_o_reg_37_ ( .D(N37), .CK(clk), .Q(Data_S_o[37]) );
DFFQX1TS Data_S_o_reg_36_ ( .D(N36), .CK(clk), .Q(Data_S_o[36]) );
DFFQX1TS Data_S_o_reg_35_ ( .D(N35), .CK(clk), .Q(Data_S_o[35]) );
DFFQX1TS Data_S_o_reg_33_ ( .D(N33), .CK(clk), .Q(Data_S_o[33]) );
DFFQX1TS Data_S_o_reg_32_ ( .D(N32), .CK(clk), .Q(Data_S_o[32]) );
DFFQX1TS Data_S_o_reg_31_ ( .D(N31), .CK(clk), .Q(Data_S_o[31]) );
DFFQX1TS Data_S_o_reg_30_ ( .D(N30), .CK(clk), .Q(Data_S_o[30]) );
DFFQX1TS Data_S_o_reg_29_ ( .D(N29), .CK(clk), .Q(Data_S_o[29]) );
DFFQX1TS Data_S_o_reg_28_ ( .D(N28), .CK(clk), .Q(Data_S_o[28]) );
DFFQX1TS Data_S_o_reg_27_ ( .D(N27), .CK(clk), .Q(Data_S_o[27]) );
DFFQX1TS Data_S_o_reg_26_ ( .D(N26), .CK(clk), .Q(Data_S_o[26]) );
DFFQX1TS Data_S_o_reg_25_ ( .D(N25), .CK(clk), .Q(Data_S_o[25]) );
DFFQX1TS Data_S_o_reg_24_ ( .D(N24), .CK(clk), .Q(Data_S_o[24]) );
DFFQX1TS Data_S_o_reg_23_ ( .D(N23), .CK(clk), .Q(Data_S_o[23]) );
DFFQX1TS Data_S_o_reg_22_ ( .D(N22), .CK(clk), .Q(Data_S_o[22]) );
DFFQX1TS Data_S_o_reg_21_ ( .D(N21), .CK(clk), .Q(Data_S_o[21]) );
DFFQX1TS Data_S_o_reg_20_ ( .D(N20), .CK(clk), .Q(Data_S_o[20]) );
DFFQX1TS Data_S_o_reg_19_ ( .D(N19), .CK(clk), .Q(Data_S_o[19]) );
DFFQX1TS Data_S_o_reg_18_ ( .D(N18), .CK(clk), .Q(Data_S_o[18]) );
DFFQX1TS Data_S_o_reg_17_ ( .D(N17), .CK(clk), .Q(Data_S_o[17]) );
DFFQX1TS Data_S_o_reg_16_ ( .D(N16), .CK(clk), .Q(Data_S_o[16]) );
DFFQX1TS Data_S_o_reg_15_ ( .D(N15), .CK(clk), .Q(Data_S_o[15]) );
DFFQX1TS Data_S_o_reg_14_ ( .D(N14), .CK(clk), .Q(Data_S_o[14]) );
DFFQX1TS Data_S_o_reg_13_ ( .D(N13), .CK(clk), .Q(Data_S_o[13]) );
DFFQX1TS Data_S_o_reg_12_ ( .D(N12), .CK(clk), .Q(Data_S_o[12]) );
DFFQX1TS Data_S_o_reg_11_ ( .D(N11), .CK(clk), .Q(Data_S_o[11]) );
DFFQX1TS Data_S_o_reg_10_ ( .D(N10), .CK(clk), .Q(Data_S_o[10]) );
DFFQX1TS Data_S_o_reg_9_ ( .D(N9), .CK(clk), .Q(Data_S_o[9]) );
DFFQX1TS Data_S_o_reg_8_ ( .D(N8), .CK(clk), .Q(Data_S_o[8]) );
DFFQX1TS Data_S_o_reg_7_ ( .D(N7), .CK(clk), .Q(Data_S_o[7]) );
DFFQX1TS Data_S_o_reg_6_ ( .D(N6), .CK(clk), .Q(Data_S_o[6]) );
DFFQX1TS Data_S_o_reg_5_ ( .D(N5), .CK(clk), .Q(Data_S_o[5]) );
DFFQX1TS Data_S_o_reg_4_ ( .D(N4), .CK(clk), .Q(Data_S_o[4]) );
DFFQX1TS Data_S_o_reg_3_ ( .D(N3), .CK(clk), .Q(Data_S_o[3]) );
DFFQX1TS Data_S_o_reg_2_ ( .D(N2), .CK(clk), .Q(Data_S_o[2]) );
DFFQX1TS Data_S_o_reg_1_ ( .D(N1), .CK(clk), .Q(Data_S_o[1]) );
DFFQX1TS Data_S_o_reg_0_ ( .D(N0), .CK(clk), .Q(Data_S_o[0]) );
DFFQX1TS Data_S_o_reg_34_ ( .D(N34), .CK(clk), .Q(Data_S_o[34]) );
CMPR42X1TS mult_x_1_U735 ( .A(mult_x_1_n861), .B(mult_x_1_n1340), .C(
mult_x_1_n1316), .D(mult_x_1_n1364), .ICI(mult_x_1_n862), .S(
mult_x_1_n859), .ICO(mult_x_1_n857), .CO(mult_x_1_n858) );
CMPR42X1TS mult_x_1_U732 ( .A(mult_x_1_n1315), .B(mult_x_1_n1363), .C(
mult_x_1_n1339), .D(mult_x_1_n854), .ICI(mult_x_1_n857), .S(
mult_x_1_n852), .ICO(mult_x_1_n850), .CO(mult_x_1_n851) );
CMPR42X1TS mult_x_1_U729 ( .A(mult_x_1_n1338), .B(mult_x_1_n1314), .C(
mult_x_1_n853), .D(mult_x_1_n850), .ICI(mult_x_1_n847), .S(
mult_x_1_n845), .ICO(mult_x_1_n843), .CO(mult_x_1_n844) );
CMPR42X2TS mult_x_1_U726 ( .A(mult_x_1_n1361), .B(mult_x_1_n1337), .C(
mult_x_1_n846), .D(mult_x_1_n840), .ICI(mult_x_1_n843), .S(
mult_x_1_n838), .ICO(mult_x_1_n836), .CO(mult_x_1_n837) );
CMPR42X1TS mult_x_1_U724 ( .A(mult_x_1_n835), .B(mult_x_1_n1264), .C(
mult_x_1_n841), .D(mult_x_1_n1288), .ICI(mult_x_1_n1312), .S(
mult_x_1_n833), .ICO(mult_x_1_n831), .CO(mult_x_1_n832) );
CMPR42X2TS mult_x_1_U718 ( .A(mult_x_1_n819), .B(mult_x_1_n1286), .C(
mult_x_1_n1310), .D(mult_x_1_n1334), .ICI(mult_x_1_n823), .S(
mult_x_1_n817), .ICO(mult_x_1_n815), .CO(mult_x_1_n816) );
CMPR42X1TS mult_x_1_U714 ( .A(mult_x_1_n1261), .B(mult_x_1_n1309), .C(
mult_x_1_n1333), .D(mult_x_1_n1285), .ICI(mult_x_1_n815), .S(
mult_x_1_n807), .ICO(mult_x_1_n805), .CO(mult_x_1_n806) );
CMPR42X1TS mult_x_1_U709 ( .A(mult_x_1_n1332), .B(mult_x_1_n805), .C(
mult_x_1_n806), .D(mult_x_1_n797), .ICI(mult_x_1_n802), .S(
mult_x_1_n794), .ICO(mult_x_1_n792), .CO(mult_x_1_n793) );
CMPR42X1TS mult_x_1_U706 ( .A(mult_x_1_n1307), .B(mult_x_1_n1283), .C(
mult_x_1_n1331), .D(mult_x_1_n1355), .ICI(mult_x_1_n795), .S(
mult_x_1_n787), .ICO(mult_x_1_n785), .CO(mult_x_1_n786) );
CMPR42X2TS mult_x_1_U698 ( .A(mult_x_1_n1233), .B(mult_x_1_n1305), .C(
mult_x_1_n777), .D(mult_x_1_n1353), .ICI(mult_x_1_n778), .S(
mult_x_1_n765), .ICO(mult_x_1_n763), .CO(mult_x_1_n764) );
CMPR42X1TS mult_x_1_U694 ( .A(mult_x_1_n1208), .B(mult_x_1_n1328), .C(
mult_x_1_n1352), .D(mult_x_1_n1304), .ICI(mult_x_1_n766), .S(
mult_x_1_n754), .ICO(mult_x_1_n752), .CO(mult_x_1_n753) );
CMPR42X2TS mult_x_1_U686 ( .A(mult_x_1_n1206), .B(mult_x_1_n1278), .C(
mult_x_1_n1302), .D(mult_x_1_n744), .ICI(mult_x_1_n737), .S(
mult_x_1_n732), .ICO(mult_x_1_n730), .CO(mult_x_1_n731) );
CMPR42X1TS mult_x_1_U678 ( .A(mult_x_1_n1228), .B(mult_x_1_n1300), .C(
mult_x_1_n1276), .D(mult_x_1_n715), .ICI(mult_x_1_n722), .S(
mult_x_1_n710), .ICO(mult_x_1_n708), .CO(mult_x_1_n709) );
CMPR42X2TS mult_x_1_U674 ( .A(mult_x_1_n1179), .B(mult_x_1_n1251), .C(
mult_x_1_n1275), .D(mult_x_1_n704), .ICI(mult_x_1_n711), .S(
mult_x_1_n699), .ICO(mult_x_1_n697), .CO(mult_x_1_n698) );
CMPR42X2TS mult_x_1_U666 ( .A(mult_x_1_n1297), .B(mult_x_1_n1249), .C(
mult_x_1_n1273), .D(mult_x_1_n689), .ICI(mult_x_1_n681), .S(
mult_x_1_n678), .ICO(mult_x_1_n676), .CO(mult_x_1_n677) );
CMPR42X1TS mult_x_1_U663 ( .A(mult_x_1_n906), .B(mult_x_1_n682), .C(
mult_x_1_n1200), .D(mult_x_1_n1176), .ICI(mult_x_1_n1296), .S(
mult_x_1_n671), .ICO(mult_x_1_n669), .CO(mult_x_1_n670) );
CMPR42X1TS mult_x_1_U662 ( .A(mult_x_1_n1224), .B(mult_x_1_n1272), .C(
mult_x_1_n1248), .D(mult_x_1_n679), .ICI(mult_x_1_n680), .S(
mult_x_1_n668), .ICO(mult_x_1_n666), .CO(mult_x_1_n667) );
CMPR42X2TS mult_x_1_U661 ( .A(mult_x_1_n676), .B(mult_x_1_n671), .C(
mult_x_1_n677), .D(mult_x_1_n668), .ICI(mult_x_1_n673), .S(
mult_x_1_n665), .ICO(mult_x_1_n663), .CO(mult_x_1_n664) );
CMPR42X2TS mult_x_1_U658 ( .A(mult_x_1_n666), .B(mult_x_1_n670), .C(
mult_x_1_n667), .D(mult_x_1_n659), .ICI(mult_x_1_n663), .S(
mult_x_1_n656), .ICO(mult_x_1_n654), .CO(mult_x_1_n655) );
CMPR42X1TS mult_x_1_U655 ( .A(mult_x_1_n1198), .B(mult_x_1_n1222), .C(
mult_x_1_n1246), .D(mult_x_1_n1270), .ICI(mult_x_1_n661), .S(
mult_x_1_n650), .ICO(mult_x_1_n648), .CO(mult_x_1_n649) );
CMPR42X2TS mult_x_1_U651 ( .A(mult_x_1_n1269), .B(mult_x_1_n1197), .C(
mult_x_1_n1245), .D(mult_x_1_n1221), .ICI(mult_x_1_n648), .S(
mult_x_1_n641), .ICO(mult_x_1_n639), .CO(mult_x_1_n640) );
CMPR42X1TS mult_x_1_U650 ( .A(mult_x_1_n651), .B(mult_x_1_n643), .C(
mult_x_1_n641), .D(mult_x_1_n649), .ICI(mult_x_1_n645), .S(
mult_x_1_n638), .ICO(mult_x_1_n636), .CO(mult_x_1_n637) );
CMPR42X1TS mult_x_1_U648 ( .A(mult_x_1_n635), .B(mult_x_1_n1172), .C(
mult_x_1_n1244), .D(mult_x_1_n1196), .ICI(mult_x_1_n1220), .S(
mult_x_1_n633), .ICO(mult_x_1_n631), .CO(mult_x_1_n632) );
CMPR42X2TS mult_x_1_U647 ( .A(mult_x_1_n642), .B(mult_x_1_n639), .C(
mult_x_1_n640), .D(mult_x_1_n633), .ICI(mult_x_1_n636), .S(
mult_x_1_n630), .ICO(mult_x_1_n628), .CO(mult_x_1_n629) );
CMPR42X2TS mult_x_1_U641 ( .A(mult_x_1_n1194), .B(mult_x_1_n624), .C(
mult_x_1_n625), .D(mult_x_1_n619), .ICI(mult_x_1_n621), .S(
mult_x_1_n616), .ICO(mult_x_1_n614), .CO(mult_x_1_n615) );
CMPR42X1TS mult_x_1_U640 ( .A(n1350), .B(mult_x_1_n901), .C(mult_x_1_n899),
.D(mult_x_1_n1193), .ICI(mult_x_1_n1217), .S(mult_x_1_n613), .ICO(
mult_x_1_n611), .CO(mult_x_1_n612) );
CMPR42X2TS mult_x_1_U639 ( .A(mult_x_1_n1169), .B(mult_x_1_n617), .C(
mult_x_1_n618), .D(mult_x_1_n613), .ICI(mult_x_1_n614), .S(
mult_x_1_n610), .ICO(mult_x_1_n608), .CO(mult_x_1_n609) );
CMPR42X1TS mult_x_1_U631 ( .A(mult_x_1_n595), .B(mult_x_1_n1190), .C(
mult_x_1_n1166), .D(mult_x_1_n599), .ICI(mult_x_1_n596), .S(
mult_x_1_n593), .ICO(mult_x_1_n591), .CO(mult_x_1_n592) );
CMPR42X2TS mult_x_1_U713 ( .A(mult_x_1_n809), .B(mult_x_1_n1357), .C(
mult_x_1_n816), .D(mult_x_1_n807), .ICI(mult_x_1_n812), .S(
mult_x_1_n804), .ICO(mult_x_1_n802), .CO(mult_x_1_n803) );
CMPR42X2TS mult_x_1_U687 ( .A(mult_x_1_n1230), .B(mult_x_1_n1350), .C(
mult_x_1_n747), .D(mult_x_1_n1326), .ICI(mult_x_1_n741), .S(
mult_x_1_n735), .ICO(mult_x_1_n733), .CO(mult_x_1_n734) );
CMPR42X2TS mult_x_1_U644 ( .A(mult_x_1_n1195), .B(mult_x_1_n631), .C(
mult_x_1_n632), .D(mult_x_1_n626), .ICI(mult_x_1_n628), .S(
mult_x_1_n623), .ICO(mult_x_1_n621), .CO(mult_x_1_n622) );
CMPR42X2TS mult_x_1_U673 ( .A(mult_x_1_n712), .B(mult_x_1_n702), .C(
mult_x_1_n709), .D(mult_x_1_n699), .ICI(mult_x_1_n705), .S(
mult_x_1_n696), .ICO(mult_x_1_n694), .CO(mult_x_1_n695) );
CMPR42X2TS mult_x_1_U679 ( .A(mult_x_1_n1252), .B(mult_x_1_n1204), .C(
mult_x_1_n725), .D(mult_x_1_n1324), .ICI(mult_x_1_n719), .S(
mult_x_1_n713), .ICO(mult_x_1_n711), .CO(mult_x_1_n712) );
CMPR42X2TS mult_x_1_U690 ( .A(mult_x_1_n748), .B(mult_x_1_n1351), .C(
mult_x_1_n1303), .D(mult_x_1_n755), .ICI(mult_x_1_n756), .S(
mult_x_1_n743), .ICO(mult_x_1_n741), .CO(mult_x_1_n742) );
CMPR42X2TS mult_x_1_U681 ( .A(mult_x_1_n734), .B(mult_x_1_n731), .C(
mult_x_1_n724), .D(mult_x_1_n721), .ICI(mult_x_1_n727), .S(
mult_x_1_n718), .ICO(mult_x_1_n716), .CO(mult_x_1_n717) );
CMPR42X2TS mult_x_1_U710 ( .A(mult_x_1_n1284), .B(mult_x_1_n1260), .C(
mult_x_1_n808), .D(mult_x_1_n1356), .ICI(mult_x_1_n799), .S(
mult_x_1_n797), .ICO(mult_x_1_n795), .CO(mult_x_1_n796) );
CMPR42X2TS mult_x_1_U723 ( .A(mult_x_1_n1360), .B(mult_x_1_n1336), .C(
mult_x_1_n839), .D(mult_x_1_n836), .ICI(mult_x_1_n833), .S(
mult_x_1_n830), .ICO(mult_x_1_n828), .CO(mult_x_1_n829) );
CMPR42X2TS mult_x_1_U670 ( .A(mult_x_1_n1298), .B(mult_x_1_n1274), .C(
mult_x_1_n703), .D(mult_x_1_n700), .ICI(mult_x_1_n691), .S(
mult_x_1_n688), .ICO(mult_x_1_n686), .CO(mult_x_1_n687) );
CMPR42X2TS mult_x_1_U682 ( .A(mult_x_1_n1277), .B(mult_x_1_n1325), .C(
mult_x_1_n726), .D(mult_x_1_n736), .ICI(mult_x_1_n733), .S(
mult_x_1_n721), .ICO(mult_x_1_n719), .CO(mult_x_1_n720) );
CMPR42X2TS mult_x_1_U667 ( .A(mult_x_1_n682), .B(mult_x_1_n692), .C(
mult_x_1_n1201), .D(mult_x_1_n1177), .ICI(mult_x_1_n1225), .S(
mult_x_1_n681), .ICO(mult_x_1_n679), .CO(mult_x_1_n680) );
CMPR42X2TS mult_x_1_U665 ( .A(mult_x_1_n686), .B(mult_x_1_n690), .C(
mult_x_1_n687), .D(mult_x_1_n678), .ICI(mult_x_1_n683), .S(
mult_x_1_n675), .ICO(mult_x_1_n673), .CO(mult_x_1_n674) );
CMPR42X2TS mult_x_1_U717 ( .A(mult_x_1_n1262), .B(mult_x_1_n1358), .C(
mult_x_1_n824), .D(mult_x_1_n820), .ICI(mult_x_1_n817), .S(
mult_x_1_n814), .ICO(mult_x_1_n812), .CO(mult_x_1_n813) );
CMPR42X2TS mult_x_1_U675 ( .A(mult_x_1_n1203), .B(mult_x_1_n1323), .C(
mult_x_1_n714), .D(mult_x_1_n1299), .ICI(mult_x_1_n708), .S(
mult_x_1_n702), .ICO(mult_x_1_n700), .CO(mult_x_1_n701) );
CMPR42X2TS mult_x_1_U669 ( .A(mult_x_1_n697), .B(mult_x_1_n701), .C(
mult_x_1_n698), .D(mult_x_1_n688), .ICI(mult_x_1_n694), .S(
mult_x_1_n685), .ICO(mult_x_1_n683), .CO(mult_x_1_n684) );
CMPR42X2TS mult_x_1_U671 ( .A(mult_x_1_n693), .B(mult_x_1_n1178), .C(
mult_x_1_n1202), .D(mult_x_1_n1226), .ICI(mult_x_1_n1250), .S(
mult_x_1_n691), .ICO(mult_x_1_n689), .CO(mult_x_1_n690) );
CMPR42X2TS mult_x_1_U739 ( .A(mult_x_1_n871), .B(mult_x_1_n1318), .C(
mult_x_1_n874), .D(mult_x_1_n1342), .ICI(mult_x_1_n1366), .S(
mult_x_1_n869), .ICO(mult_x_1_n867), .CO(mult_x_1_n868) );
CMPR42X2TS mult_x_1_U685 ( .A(mult_x_1_n745), .B(mult_x_1_n735), .C(
mult_x_1_n732), .D(mult_x_1_n742), .ICI(mult_x_1_n738), .S(
mult_x_1_n729), .ICO(mult_x_1_n727), .CO(mult_x_1_n728) );
CMPR42X2TS mult_x_1_U677 ( .A(mult_x_1_n723), .B(mult_x_1_n713), .C(
mult_x_1_n720), .D(mult_x_1_n710), .ICI(mult_x_1_n716), .S(
mult_x_1_n707), .ICO(mult_x_1_n705), .CO(mult_x_1_n706) );
CMPR42X2TS mult_x_1_U705 ( .A(mult_x_1_n798), .B(mult_x_1_n789), .C(
mult_x_1_n796), .D(mult_x_1_n787), .ICI(mult_x_1_n792), .S(
mult_x_1_n784), .ICO(mult_x_1_n782), .CO(mult_x_1_n783) );
CMPR42X2TS mult_x_1_U695 ( .A(mult_x_1_n759), .B(mult_x_1_n1232), .C(
mult_x_1_n1280), .D(mult_x_1_n1256), .ICI(mult_x_1_n763), .S(
mult_x_1_n757), .ICO(mult_x_1_n755), .CO(mult_x_1_n756) );
CMPR42X2TS mult_x_1_U697 ( .A(mult_x_1_n774), .B(mult_x_1_n768), .C(
mult_x_1_n775), .D(mult_x_1_n765), .ICI(mult_x_1_n771), .S(
mult_x_1_n762), .ICO(mult_x_1_n760), .CO(mult_x_1_n761) );
CMPR42X2TS mult_x_1_U693 ( .A(mult_x_1_n767), .B(mult_x_1_n757), .C(
mult_x_1_n764), .D(mult_x_1_n754), .ICI(mult_x_1_n760), .S(
mult_x_1_n751), .ICO(mult_x_1_n749), .CO(mult_x_1_n750) );
CMPR42X2TS mult_x_1_U689 ( .A(mult_x_1_n1327), .B(mult_x_1_n746), .C(
mult_x_1_n753), .D(mult_x_1_n743), .ICI(mult_x_1_n749), .S(
mult_x_1_n740), .ICO(mult_x_1_n738), .CO(mult_x_1_n739) );
CMPR42X1TS mult_x_1_U683 ( .A(mult_x_1_n1181), .B(mult_x_1_n1253), .C(
mult_x_1_n1229), .D(mult_x_1_n1301), .ICI(mult_x_1_n730), .S(
mult_x_1_n724), .ICO(mult_x_1_n722), .CO(mult_x_1_n723) );
CMPR42X1TS mult_x_1_U633 ( .A(mult_x_1_n1191), .B(mult_x_1_n1167), .C(
mult_x_1_n600), .D(mult_x_1_n605), .ICI(mult_x_1_n602), .S(
mult_x_1_n598), .ICO(mult_x_1_n596), .CO(mult_x_1_n597) );
CMPR42X1TS mult_x_1_U702 ( .A(mult_x_1_n1306), .B(mult_x_1_n1282), .C(
mult_x_1_n1330), .D(mult_x_1_n1354), .ICI(mult_x_1_n785), .S(
mult_x_1_n776), .ICO(mult_x_1_n774), .CO(mult_x_1_n775) );
CMPR42X1TS mult_x_1_U659 ( .A(mult_x_1_n1271), .B(mult_x_1_n1223), .C(
mult_x_1_n1247), .D(mult_x_1_n669), .ICI(mult_x_1_n662), .S(
mult_x_1_n659), .ICO(mult_x_1_n657), .CO(mult_x_1_n658) );
XNOR2X1TS U3 ( .A(n477), .B(n476), .Y(N47) );
XNOR2X1TS U4 ( .A(n499), .B(n498), .Y(N36) );
OAI21X1TS U5 ( .A0(n6), .A1(n465), .B0(n464), .Y(n477) );
OAI21X1TS U6 ( .A0(n6), .A1(n445), .B0(n444), .Y(n448) );
OAI21X1TS U7 ( .A0(n6), .A1(n481), .B0(n480), .Y(n485) );
NOR2X1TS U8 ( .A(n556), .B(n1185), .Y(n548) );
NOR2X1TS U9 ( .A(n1209), .B(n562), .Y(n1192) );
OAI21X1TS U10 ( .A0(n1209), .A1(n1205), .B0(n1210), .Y(n1194) );
AOI21X1TS U11 ( .A0(n433), .A1(n69), .B0(n226), .Y(n368) );
NAND2X1TS U12 ( .A(mult_x_1_n773), .B(mult_x_1_n783), .Y(n1205) );
NAND2X1TS U13 ( .A(mult_x_1_n762), .B(mult_x_1_n772), .Y(n1210) );
NOR2X1TS U14 ( .A(mult_x_1_n773), .B(mult_x_1_n783), .Y(n562) );
NOR2X1TS U15 ( .A(n507), .B(n516), .Y(n213) );
NOR2X1TS U16 ( .A(mult_x_1_n707), .B(mult_x_1_n717), .Y(n539) );
CMPR42X1TS U17 ( .A(mult_x_1_n652), .B(mult_x_1_n657), .C(mult_x_1_n658),
.D(mult_x_1_n650), .ICI(mult_x_1_n654), .S(mult_x_1_n647), .ICO(
mult_x_1_n645), .CO(mult_x_1_n646) );
CMPR42X1TS U18 ( .A(mult_x_1_n590), .B(mult_x_1_n594), .C(mult_x_1_n1189),
.D(mult_x_1_n1165), .ICI(mult_x_1_n591), .S(mult_x_1_n589), .ICO(
mult_x_1_n587), .CO(mult_x_1_n588) );
CMPR42X1TS U19 ( .A(mult_x_1_n770), .B(mult_x_1_n1209), .C(mult_x_1_n1257),
.D(mult_x_1_n1281), .ICI(mult_x_1_n1329), .S(mult_x_1_n768), .ICO(
mult_x_1_n766), .CO(mult_x_1_n767) );
CLKXOR2X2TS U20 ( .A(n649), .B(n648), .Y(n1278) );
CMPR32X2TS U21 ( .A(n151), .B(n150), .C(n149), .CO(n152), .S(n136) );
CMPR32X2TS U22 ( .A(n183), .B(n182), .C(n181), .CO(n184), .S(n153) );
ADDHX1TS U23 ( .A(n1237), .B(n974), .CO(n322), .S(mult_x_1_n871) );
XOR2X1TS U24 ( .A(n793), .B(n792), .Y(n1217) );
XOR2X1TS U25 ( .A(n826), .B(n825), .Y(n1253) );
NOR2BX1TS U26 ( .AN(n295), .B(n294), .Y(n1224) );
INVX2TS U27 ( .A(Data_A_i[23]), .Y(n233) );
NAND2BX1TS U28 ( .AN(n317), .B(n318), .Y(n1053) );
NOR2X1TS U29 ( .A(n1108), .B(n33), .Y(n692) );
XNOR2X2TS U30 ( .A(Data_A_i[20]), .B(Data_A_i[21]), .Y(n288) );
XOR2X1TS U31 ( .A(Data_A_i[14]), .B(Data_A_i[13]), .Y(n308) );
CLKBUFX2TS U32 ( .A(Data_B_i[18]), .Y(n1273) );
CLKBUFX2TS U33 ( .A(Data_B_i[20]), .Y(n1310) );
INVX2TS U34 ( .A(n31), .Y(n32) );
INVX2TS U35 ( .A(n34), .Y(n35) );
INVX2TS U36 ( .A(n26), .Y(n27) );
CLKBUFX2TS U37 ( .A(Data_B_i[22]), .Y(n1232) );
CLKBUFX2TS U38 ( .A(Data_B_i[21]), .Y(n1294) );
XNOR2X1TS U39 ( .A(Data_A_i[17]), .B(Data_A_i[18]), .Y(n317) );
BUFX3TS U40 ( .A(Data_B_i[15]), .Y(n1108) );
INVX2TS U41 ( .A(n632), .Y(n1106) );
INVX2TS U42 ( .A(Data_A_i[2]), .Y(n632) );
NOR2XLTS U43 ( .A(n303), .B(n280), .Y(n246) );
INVX2TS U44 ( .A(n700), .Y(n687) );
NOR2XLTS U45 ( .A(n686), .B(n705), .Y(n689) );
INVX2TS U46 ( .A(n705), .Y(n707) );
NOR2XLTS U47 ( .A(n1108), .B(n1073), .Y(n680) );
INVX2TS U48 ( .A(n123), .Y(n125) );
INVX2TS U49 ( .A(n163), .Y(n92) );
INVX2TS U50 ( .A(n31), .Y(n33) );
OAI21XLTS U51 ( .A0(n60), .A1(n1252), .B0(n292), .Y(n293) );
OAI21XLTS U52 ( .A0(n1018), .A1(n991), .B0(n990), .Y(n993) );
OAI21XLTS U53 ( .A0(n1270), .A1(n1269), .B0(n1268), .Y(n1272) );
OAI21XLTS U54 ( .A0(n1139), .A1(n1177), .B0(n1138), .Y(n1141) );
NAND2X1TS U55 ( .A(n1112), .B(n8), .Y(n55) );
AOI222XLTS U56 ( .A0(n932), .A1(n900), .B0(n1111), .B1(n386), .C0(n1142),
.C1(Data_B_i[0]), .Y(n80) );
OAI21XLTS U57 ( .A0(n390), .A1(n976), .B0(n268), .Y(n269) );
XOR2X1TS U58 ( .A(n626), .B(n625), .Y(n1126) );
OAI21XLTS U59 ( .A0(n1018), .A1(n1167), .B0(n1017), .Y(n1020) );
INVX2TS U60 ( .A(n1024), .Y(n321) );
XOR2X1TS U61 ( .A(n293), .B(n1292), .Y(n332) );
OAI21XLTS U62 ( .A0(n1222), .A1(n1227), .B0(n796), .Y(n797) );
OAI21XLTS U63 ( .A0(n1222), .A1(n1053), .B0(n761), .Y(n762) );
OAI21XLTS U64 ( .A0(n1126), .A1(n1317), .B0(n627), .Y(n628) );
BUFX3TS U65 ( .A(Data_B_i[16]), .Y(n1073) );
XOR2X2TS U66 ( .A(n284), .B(n283), .Y(n1301) );
OAI21XLTS U67 ( .A0(n1035), .A1(n1077), .B0(n179), .Y(n180) );
OAI21XLTS U68 ( .A0(n1217), .A1(n1155), .B0(n955), .Y(n956) );
OAI21XLTS U69 ( .A0(n1217), .A1(n1114), .B0(n924), .Y(n925) );
OAI21XLTS U70 ( .A0(n1284), .A1(n1317), .B0(n1283), .Y(n1285) );
OAI21XLTS U71 ( .A0(n355), .A1(n482), .B0(n356), .Y(n227) );
NAND2X1TS U72 ( .A(Data_B_i[1]), .B(Data_B_i[0]), .Y(n87) );
OAI21XLTS U73 ( .A0(n1244), .A1(n1155), .B0(n97), .Y(n98) );
NOR2X1TS U74 ( .A(mult_x_1_n630), .B(mult_x_1_n637), .Y(n441) );
CMPR42X1TS U75 ( .A(mult_x_1_n1192), .B(mult_x_1_n1168), .C(mult_x_1_n606),
.D(mult_x_1_n612), .ICI(mult_x_1_n608), .S(mult_x_1_n604), .ICO(
mult_x_1_n602), .CO(mult_x_1_n603) );
INVX2TS U76 ( .A(n417), .Y(n419) );
INVX2TS U77 ( .A(n585), .Y(n134) );
INVX2TS U78 ( .A(n574), .Y(n1304) );
INVX2TS U79 ( .A(n565), .Y(n567) );
OAI21XLTS U80 ( .A0(n1197), .A1(n1196), .B0(n1195), .Y(n1198) );
INVX2TS U81 ( .A(n543), .Y(n545) );
INVX2TS U82 ( .A(n507), .Y(n509) );
OR2X1TS U83 ( .A(mult_x_1_n610), .B(mult_x_1_n615), .Y(n489) );
INVX2TS U84 ( .A(n401), .Y(n404) );
OR2X1TS U85 ( .A(mult_x_1_n581), .B(n256), .Y(n364) );
NOR2XLTS U86 ( .A(n43), .B(n1348), .Y(n593) );
OAI21XLTS U87 ( .A0(n1325), .A1(n1321), .B0(n1322), .Y(n581) );
INVX2TS U88 ( .A(n564), .Y(n1259) );
OAI21XLTS U89 ( .A0(n506), .A1(n3), .B0(n505), .Y(n511) );
OAI21XLTS U90 ( .A0(n7), .A1(n936), .B0(n58), .Y(N0) );
XNOR2X1TS U91 ( .A(n735), .B(n683), .Y(n1) );
OR2X1TS U92 ( .A(n115), .B(n114), .Y(n2) );
CLKINVX2TS U93 ( .A(n486), .Y(n434) );
XOR2X1TS U94 ( .A(n1331), .B(n1330), .Y(N11) );
CLKINVX1TS U95 ( .A(n1194), .Y(n1197) );
CLKINVX1TS U96 ( .A(n1040), .Y(n1042) );
CLKINVX2TS U97 ( .A(n437), .Y(n226) );
CLKINVX1TS U98 ( .A(n405), .Y(n407) );
INVX1TS U99 ( .A(n577), .Y(n579) );
XOR2X1TS U100 ( .A(n1347), .B(n1346), .Y(N4) );
XOR2X1TS U101 ( .A(n1147), .B(n36), .Y(mult_x_1_n1329) );
XOR2X1TS U102 ( .A(n1020), .B(n1019), .Y(n1021) );
XOR2X1TS U103 ( .A(n993), .B(n992), .Y(n994) );
XOR2X1TS U104 ( .A(n917), .B(n1115), .Y(mult_x_1_n1334) );
XOR2X1TS U105 ( .A(n981), .B(Data_A_i[2]), .Y(n982) );
OAI21X1TS U106 ( .A0(n1139), .A1(n991), .B0(n816), .Y(n817) );
OAI21X1TS U107 ( .A0(n1284), .A1(n1105), .B0(n1098), .Y(n1100) );
OAI21X1TS U108 ( .A0(n1139), .A1(n1105), .B0(n951), .Y(n952) );
OAI21X1TS U109 ( .A0(n1318), .A1(n1105), .B0(n1104), .Y(n1107) );
OAI21X1TS U110 ( .A0(n1018), .A1(n1105), .B0(n980), .Y(n981) );
OAI21X1TS U111 ( .A0(n1078), .A1(n1177), .B0(n746), .Y(n747) );
OAI21X1TS U112 ( .A0(n1146), .A1(n1096), .B0(n878), .Y(n879) );
OAI21X1TS U113 ( .A0(n1), .A1(n922), .B0(n912), .Y(n913) );
OAI21X1TS U114 ( .A0(n1278), .A1(n1096), .B0(n876), .Y(n877) );
OAI21X1TS U115 ( .A0(n1318), .A1(n1235), .B0(n841), .Y(n842) );
OAI21X1TS U116 ( .A0(n1121), .A1(n1096), .B0(n1095), .Y(n1097) );
OAI21X1TS U117 ( .A0(n1301), .A1(n1096), .B0(n872), .Y(n873) );
OAI21X1TS U118 ( .A0(n1270), .A1(n1167), .B0(n884), .Y(n885) );
OAI21X1TS U119 ( .A0(n1178), .A1(n1167), .B0(n1166), .Y(n1168) );
OAI21X1TS U120 ( .A0(n1), .A1(n1096), .B0(n882), .Y(n883) );
OAI21X1TS U121 ( .A0(n1270), .A1(n1177), .B0(n750), .Y(n751) );
OAI21X1TS U122 ( .A0(n1270), .A1(n936), .B0(n949), .Y(n950) );
OAI21X1TS U123 ( .A0(n1121), .A1(n936), .B0(n944), .Y(n945) );
OAI21X1TS U124 ( .A0(n1), .A1(n936), .B0(n947), .Y(n948) );
OAI21X1TS U125 ( .A0(n1121), .A1(n1317), .B0(n678), .Y(n679) );
OAI21X1TS U126 ( .A0(n1018), .A1(n719), .B0(n617), .Y(n618) );
OAI21X1TS U127 ( .A0(n1078), .A1(n991), .B0(n810), .Y(n811) );
XOR2X2TS U128 ( .A(n677), .B(n676), .Y(n1121) );
XOR2X1TS U129 ( .A(n1254), .B(n1319), .Y(mult_x_1_n1176) );
XOR2X1TS U130 ( .A(n298), .B(Data_A_i[17]), .Y(mult_x_1_n1233) );
XOR2X2TS U131 ( .A(n616), .B(n615), .Y(n1018) );
XOR2X1TS U132 ( .A(n1157), .B(n1156), .Y(mult_x_1_n1366) );
XOR2X2TS U133 ( .A(n740), .B(n739), .Y(n1284) );
XOR2X2TS U134 ( .A(n696), .B(n695), .Y(n1270) );
OAI21X1TS U135 ( .A0(n934), .A1(n1252), .B0(n715), .Y(n716) );
OAI21X1TS U136 ( .A0(n934), .A1(n861), .B0(n867), .Y(n868) );
OAI21X1TS U137 ( .A0(n1222), .A1(n1114), .B0(n928), .Y(n929) );
OAI21X1TS U138 ( .A0(n1126), .A1(n922), .B0(n920), .Y(n921) );
OAI21X1TS U139 ( .A0(n934), .A1(n1114), .B0(n933), .Y(n935) );
XOR2X1TS U140 ( .A(n1228), .B(n1271), .Y(mult_x_1_n1234) );
OAI21X1TS U141 ( .A0(n1253), .A1(n1114), .B0(n926), .Y(n927) );
OAI21X1TS U142 ( .A0(n1222), .A1(n1155), .B0(n1154), .Y(n1157) );
OAI21X1TS U143 ( .A0(n1035), .A1(n1269), .B0(n1034), .Y(n1036) );
INVX1TS U144 ( .A(n372), .Y(n250) );
OAI21X1TS U145 ( .A0(n275), .A1(n303), .B0(n304), .Y(n276) );
INVX1TS U146 ( .A(n663), .Y(n666) );
INVX2TS U147 ( .A(n267), .Y(n1089) );
INVX1TS U148 ( .A(n673), .Y(n675) );
INVX1TS U149 ( .A(n623), .Y(n609) );
NOR2X1TS U150 ( .A(n680), .B(n673), .Y(n663) );
INVX1TS U151 ( .A(n680), .Y(n682) );
INVX1TS U152 ( .A(n656), .Y(n658) );
INVX1TS U153 ( .A(n303), .Y(n305) );
XOR2X1TS U154 ( .A(n1106), .B(Data_A_i[1]), .Y(n96) );
NAND2XLTS U155 ( .A(n743), .B(n8), .Y(n68) );
INVX1TS U156 ( .A(n789), .Y(n791) );
NOR2X1TS U157 ( .A(n1073), .B(n35), .Y(n673) );
INVX1TS U158 ( .A(n164), .Y(n143) );
INVX6TS U159 ( .A(Data_A_i[8]), .Y(n9) );
NOR2X1TS U160 ( .A(Data_B_i[6]), .B(Data_B_i[7]), .Y(n164) );
XOR2XLTS U161 ( .A(n257), .B(n52), .Y(N45) );
XOR2X1TS U162 ( .A(n3), .B(n1188), .Y(N25) );
OAI21X1TS U163 ( .A0(n3), .A1(n534), .B0(n533), .Y(n538) );
OAI21X1TS U164 ( .A0(n3), .A1(n551), .B0(n550), .Y(n555) );
OAI21X1TS U165 ( .A0(n3), .A1(n1185), .B0(n1186), .Y(n560) );
OAI21X1TS U166 ( .A0(n3), .A1(n515), .B0(n514), .Y(n520) );
OAI21X1TS U167 ( .A0(n3), .A1(n542), .B0(n541), .Y(n547) );
XOR2X1TS U168 ( .A(n1265), .B(n1264), .Y(N18) );
XOR2X1TS U169 ( .A(n1259), .B(n1258), .Y(N19) );
XOR2X1TS U170 ( .A(n1309), .B(n1308), .Y(N15) );
INVX1TS U171 ( .A(n425), .Y(n340) );
INVX1TS U172 ( .A(n478), .Y(n481) );
OR2X2TS U173 ( .A(n487), .B(n463), .Y(n465) );
INVX1TS U174 ( .A(n402), .Y(n403) );
INVX1TS U175 ( .A(n479), .Y(n480) );
INVX1TS U176 ( .A(n421), .Y(n341) );
XOR2X1TS U177 ( .A(n1325), .B(n1324), .Y(N12) );
INVX1TS U178 ( .A(n487), .Y(n432) );
INVX1TS U179 ( .A(n493), .Y(n494) );
INVX1TS U180 ( .A(n492), .Y(n495) );
CLKINVX2TS U181 ( .A(n216), .Y(n217) );
INVX1TS U182 ( .A(n349), .Y(n338) );
NOR2X1TS U183 ( .A(n1193), .B(n1196), .Y(n1199) );
INVX1TS U184 ( .A(n534), .Y(n522) );
OAI21X1TS U185 ( .A0(n502), .A1(n516), .B0(n517), .Y(n503) );
INVX1TS U186 ( .A(n548), .Y(n551) );
OAI21X1TS U187 ( .A0(n230), .A1(n406), .B0(n229), .Y(n365) );
INVX1TS U188 ( .A(n410), .Y(n439) );
AOI21X1TS U189 ( .A0(n512), .A1(n213), .B0(n212), .Y(n214) );
INVX2TS U190 ( .A(n411), .Y(n442) );
NAND2X2TS U191 ( .A(n497), .B(n447), .Y(n223) );
INVX1TS U192 ( .A(n345), .Y(n339) );
INVX1TS U193 ( .A(n1192), .Y(n1193) );
XOR2X1TS U194 ( .A(n1336), .B(n1335), .Y(N8) );
INVX1TS U195 ( .A(n496), .Y(n443) );
INVX1TS U196 ( .A(n1306), .Y(n196) );
INVX1TS U197 ( .A(n1205), .Y(n1206) );
NOR2X1TS U198 ( .A(n361), .B(n405), .Y(n345) );
OAI21X2TS U199 ( .A0(n1041), .A1(n417), .B0(n418), .Y(n411) );
INVX1TS U200 ( .A(n1185), .Y(n1187) );
INVX1TS U201 ( .A(n1209), .Y(n1211) );
INVX1TS U202 ( .A(n446), .Y(n221) );
INVX1TS U203 ( .A(n1196), .Y(n1189) );
INVX1TS U204 ( .A(n552), .Y(n540) );
INVX1TS U205 ( .A(n441), .Y(n412) );
INVX1TS U206 ( .A(n516), .Y(n518) );
OAI21X1TS U207 ( .A0(n422), .A1(n428), .B0(n429), .Y(n347) );
OAI21X1TS U208 ( .A0(n577), .A1(n1322), .B0(n578), .Y(n194) );
NOR2X2TS U209 ( .A(mult_x_1_n762), .B(mult_x_1_n772), .Y(n1209) );
OR2X2TS U210 ( .A(mult_x_1_n838), .B(mult_x_1_n844), .Y(n64) );
INVX1TS U211 ( .A(n1328), .Y(n191) );
INVX1TS U212 ( .A(n1262), .Y(n201) );
INVX1TS U213 ( .A(n582), .Y(n1326) );
INVX1TS U214 ( .A(n422), .Y(n423) );
INVX1TS U215 ( .A(n1321), .Y(n1323) );
INVX1TS U216 ( .A(n428), .Y(n430) );
INVX1TS U217 ( .A(n482), .Y(n352) );
INVX1TS U218 ( .A(n362), .Y(n363) );
INVX1TS U219 ( .A(n355), .Y(n357) );
OR2X2TS U220 ( .A(mult_x_1_n604), .B(mult_x_1_n609), .Y(n69) );
NOR2X1TS U221 ( .A(mult_x_1_n593), .B(mult_x_1_n597), .Y(n342) );
INVX1TS U222 ( .A(n1332), .Y(n1334) );
NOR2X1TS U223 ( .A(mult_x_1_n603), .B(mult_x_1_n598), .Y(n405) );
AND2X2TS U224 ( .A(n364), .B(n362), .Y(n52) );
INVX1TS U225 ( .A(n961), .Y(n190) );
OR2X2TS U226 ( .A(mult_x_1_n864), .B(mult_x_1_n868), .Y(n62) );
NOR2X1TS U227 ( .A(n346), .B(n355), .Y(n228) );
INVX1TS U228 ( .A(n458), .Y(n459) );
NOR2X1TS U229 ( .A(mult_x_1_n582), .B(mult_x_1_n584), .Y(n355) );
INVX1TS U230 ( .A(n971), .Y(n154) );
OR2X2TS U231 ( .A(n380), .B(n379), .Y(n460) );
OR2X2TS U232 ( .A(n153), .B(n152), .Y(n5) );
OR2X2TS U233 ( .A(n473), .B(n472), .Y(n475) );
INVX1TS U234 ( .A(n1337), .Y(n1339) );
ADDFX1TS U235 ( .A(n273), .B(n272), .CI(n271), .CO(mult_x_1_n853), .S(
mult_x_1_n854) );
XOR2X1TS U236 ( .A(n312), .B(n1163), .Y(mult_x_1_n1245) );
XOR2X1TS U237 ( .A(n945), .B(n1099), .Y(mult_x_1_n1358) );
XOR2X1TS U238 ( .A(n1293), .B(n1292), .Y(mult_x_1_n1163) );
XOR2XLTS U239 ( .A(n1122), .B(n1163), .Y(mult_x_1_n1250) );
XOR2X1TS U240 ( .A(n1179), .B(Data_A_i[20]), .Y(mult_x_1_n1188) );
XOR2X1TS U241 ( .A(n618), .B(n713), .Y(n619) );
XOR2X1TS U242 ( .A(n858), .B(n1245), .Y(mult_x_1_n1281) );
XOR2X1TS U243 ( .A(n745), .B(n1132), .Y(mult_x_1_n1194) );
XOR2X1TS U244 ( .A(n747), .B(n1132), .Y(mult_x_1_n1195) );
XOR2X1TS U245 ( .A(n913), .B(n36), .Y(mult_x_1_n1332) );
XOR2X1TS U246 ( .A(n1285), .B(n1292), .Y(mult_x_1_n1165) );
XOR2X1TS U247 ( .A(n941), .B(n1106), .Y(mult_x_1_n1351) );
XOR2X1TS U248 ( .A(n915), .B(n1115), .Y(mult_x_1_n1333) );
XOR2X1TS U249 ( .A(n943), .B(n1099), .Y(mult_x_1_n1357) );
XOR2XLTS U250 ( .A(n1288), .B(n1302), .Y(mult_x_1_n1218) );
XOR2X1TS U251 ( .A(n255), .B(n1292), .Y(n371) );
XOR2X1TS U252 ( .A(n1320), .B(n1319), .Y(mult_x_1_n1164) );
INVX1TS U253 ( .A(n1342), .Y(n116) );
XOR2XLTS U254 ( .A(n1279), .B(n1302), .Y(mult_x_1_n1220) );
XOR2X1TS U255 ( .A(n948), .B(n1099), .Y(mult_x_1_n1359) );
XOR2X1TS U256 ( .A(n286), .B(n1237), .Y(mult_x_1_n1271) );
XOR2X1TS U257 ( .A(n651), .B(n713), .Y(mult_x_1_n1166) );
XOR2X1TS U258 ( .A(n679), .B(n713), .Y(mult_x_1_n1169) );
XOR2X1TS U259 ( .A(n952), .B(Data_A_i[2]), .Y(mult_x_1_n1361) );
XOR2X1TS U260 ( .A(n378), .B(Data_A_i[23]), .Y(n466) );
XOR2X1TS U261 ( .A(n844), .B(n1237), .Y(mult_x_1_n1273) );
XOR2X1TS U262 ( .A(n1184), .B(n36), .Y(mult_x_1_n1327) );
XOR2X1TS U263 ( .A(n672), .B(n1292), .Y(mult_x_1_n1168) );
XOR2X1TS U264 ( .A(n950), .B(n1099), .Y(mult_x_1_n1360) );
XOR2XLTS U265 ( .A(n1272), .B(n1271), .Y(mult_x_1_n1225) );
XOR2X1TS U266 ( .A(n742), .B(n1132), .Y(mult_x_1_n1192) );
NOR2BX2TS U267 ( .AN(n1005), .B(n1004), .Y(n1006) );
OAI21X1TS U268 ( .A0(n1), .A1(n1227), .B0(n781), .Y(n782) );
OAI21X1TS U269 ( .A0(n1121), .A1(n1235), .B0(n851), .Y(n852) );
OAI21X1TS U270 ( .A0(n1178), .A1(n1105), .B0(n937), .Y(n938) );
OAI21X1TS U271 ( .A0(n1178), .A1(n1177), .B0(n1176), .Y(n1179) );
OAI21X1TS U272 ( .A0(n1301), .A1(n1317), .B0(n1291), .Y(n1293) );
OAI21X1TS U273 ( .A0(n1301), .A1(n1114), .B0(n908), .Y(n909) );
OAI21X1TS U274 ( .A0(n1), .A1(n1235), .B0(n969), .Y(n970) );
OAI21X1TS U275 ( .A0(n1236), .A1(n1114), .B0(n1071), .Y(n1072) );
OAI21X1TS U276 ( .A0(n1121), .A1(n1227), .B0(n779), .Y(n780) );
OAI21X1TS U277 ( .A0(n1236), .A1(n1235), .B0(n1234), .Y(n1238) );
INVX1TS U278 ( .A(n592), .Y(n594) );
OAI21X1TS U279 ( .A0(n1146), .A1(n1131), .B0(n744), .Y(n745) );
OAI21X1TS U280 ( .A0(n1121), .A1(n1131), .B0(n1109), .Y(n1110) );
OAI21X1TS U281 ( .A0(n1236), .A1(n1317), .B0(n254), .Y(n255) );
OAI21X1TS U282 ( .A0(n1278), .A1(n1317), .B0(n650), .Y(n651) );
OAI21X1TS U283 ( .A0(n1301), .A1(n1131), .B0(n724), .Y(n725) );
OAI21X1TS U284 ( .A0(n1270), .A1(n991), .B0(n814), .Y(n815) );
OR2X2TS U285 ( .A(n113), .B(n112), .Y(n1344) );
OAI21X1TS U286 ( .A0(n1146), .A1(n1227), .B0(n775), .Y(n776) );
OAI21X1TS U287 ( .A0(n1178), .A1(n1077), .B0(n906), .Y(n907) );
OAI21X1TS U288 ( .A0(n1318), .A1(n1317), .B0(n1316), .Y(n1320) );
OAI21X1TS U289 ( .A0(n1236), .A1(n1131), .B0(n722), .Y(n723) );
OAI21X1TS U290 ( .A0(n1121), .A1(n1114), .B0(n1062), .Y(n1063) );
OAI21X1TS U291 ( .A0(n1301), .A1(n1105), .B0(n1068), .Y(n1069) );
OAI21X1TS U292 ( .A0(n1178), .A1(n976), .B0(n839), .Y(n840) );
OAI21X1TS U293 ( .A0(n1318), .A1(n1096), .B0(n1060), .Y(n1061) );
OAI21X1TS U294 ( .A0(n1284), .A1(n1096), .B0(n874), .Y(n875) );
OAI21X1TS U295 ( .A0(n1236), .A1(n1105), .B0(n940), .Y(n941) );
OAI21X1TS U296 ( .A0(n1278), .A1(n1105), .B0(n1086), .Y(n1087) );
OAI21X1TS U297 ( .A0(n1146), .A1(n1235), .B0(n847), .Y(n848) );
XOR2X1TS U298 ( .A(n895), .B(n11), .Y(mult_x_1_n1314) );
XOR2X1TS U299 ( .A(n628), .B(n1319), .Y(n629) );
XOR2XLTS U300 ( .A(n1174), .B(n11), .Y(mult_x_1_n1312) );
XOR2X1TS U301 ( .A(n178), .B(n1156), .Y(n187) );
XOR2X1TS U302 ( .A(n264), .B(n1245), .Y(n272) );
XOR2X1TS U303 ( .A(n868), .B(Data_A_i[11]), .Y(mult_x_1_n1287) );
XOR2X1TS U304 ( .A(n148), .B(n1156), .Y(n181) );
XOR2X1TS U305 ( .A(n921), .B(n36), .Y(mult_x_1_n1336) );
XOR2X1TS U306 ( .A(n925), .B(n36), .Y(mult_x_1_n1337) );
XOR2X1TS U307 ( .A(n927), .B(n36), .Y(mult_x_1_n1338) );
XOR2X1TS U308 ( .A(n828), .B(Data_A_i[14]), .Y(mult_x_1_n1257) );
XOR2X1TS U309 ( .A(n866), .B(Data_A_i[11]), .Y(mult_x_1_n1286) );
XOR2X1TS U310 ( .A(n98), .B(n1156), .Y(n135) );
XOR2X1TS U311 ( .A(n954), .B(n1156), .Y(mult_x_1_n1363) );
XOR2X1TS U312 ( .A(n929), .B(n36), .Y(mult_x_1_n1339) );
XOR2X1TS U313 ( .A(n956), .B(n1156), .Y(mult_x_1_n1364) );
XOR2X2TS U314 ( .A(n709), .B(n708), .Y(n1139) );
XOR2X1TS U315 ( .A(n129), .B(n1156), .Y(n133) );
XOR2X1TS U316 ( .A(n891), .B(n11), .Y(mult_x_1_n1310) );
XOR2X1TS U317 ( .A(n768), .B(n1140), .Y(mult_x_1_n1208) );
OAI21X1TS U318 ( .A0(n934), .A1(n1227), .B0(n297), .Y(n298) );
OAI21X1TS U319 ( .A0(n934), .A1(n1053), .B0(n763), .Y(n764) );
INVX1TS U320 ( .A(n1009), .Y(n315) );
INVX1TS U321 ( .A(N0), .Y(n111) );
XOR2X1TS U322 ( .A(n834), .B(n992), .Y(mult_x_1_n1262) );
XOR2X1TS U323 ( .A(n1031), .B(Data_A_i[14]), .Y(n1038) );
XOR2X1TS U324 ( .A(n897), .B(n1019), .Y(mult_x_1_n1315) );
XOR2X1TS U325 ( .A(n1036), .B(n1271), .Y(n1037) );
OAI21X1TS U326 ( .A0(n1126), .A1(n1155), .B0(n953), .Y(n954) );
XOR2X1TS U327 ( .A(n931), .B(Data_A_i[5]), .Y(mult_x_1_n1340) );
XOR2X1TS U328 ( .A(n899), .B(n1019), .Y(mult_x_1_n1316) );
OAI21X1TS U329 ( .A0(n1253), .A1(n1155), .B0(n957), .Y(n958) );
XOR2X1TS U330 ( .A(n180), .B(n1115), .Y(n186) );
XOR2X1TS U331 ( .A(n397), .B(n1245), .Y(n398) );
OAI21X1TS U332 ( .A0(n934), .A1(n1155), .B0(n147), .Y(n148) );
XOR2X1TS U333 ( .A(n145), .B(n144), .Y(n934) );
XOR2X1TS U334 ( .A(n836), .B(n992), .Y(mult_x_1_n1263) );
OAI21X1TS U335 ( .A0(n1035), .A1(n991), .B0(n833), .Y(n834) );
INVX1TS U336 ( .A(n373), .Y(n249) );
XOR2X1TS U337 ( .A(n1014), .B(n1271), .Y(n1022) );
XOR2X1TS U338 ( .A(n141), .B(n1115), .Y(n182) );
XOR2X1TS U339 ( .A(n78), .B(n1115), .Y(n150) );
OAI21X1TS U340 ( .A0(n390), .A1(n1252), .B0(n61), .Y(n289) );
OAI21X1TS U341 ( .A0(n687), .A1(n705), .B0(n706), .Y(n688) );
XOR2X1TS U342 ( .A(n388), .B(n992), .Y(n454) );
XOR2X1TS U343 ( .A(n772), .B(n1140), .Y(mult_x_1_n1210) );
OAI21X1TS U344 ( .A0(n390), .A1(n1177), .B0(n67), .Y(n314) );
INVX1TS U345 ( .A(n702), .Y(n686) );
INVX1TS U346 ( .A(n664), .Y(n665) );
INVX1TS U347 ( .A(n819), .Y(n820) );
INVX1TS U348 ( .A(n818), .Y(n821) );
NAND2BX1TS U349 ( .AN(n94), .B(n96), .Y(n936) );
AND3X2TS U350 ( .A(n96), .B(n95), .C(n94), .Y(n1153) );
INVX1TS U351 ( .A(n300), .Y(n274) );
INVX1TS U352 ( .A(n299), .Y(n275) );
NOR2X1TS U353 ( .A(n261), .B(n260), .Y(n267) );
INVX1TS U354 ( .A(n612), .Y(n614) );
INVX1TS U355 ( .A(n756), .Y(n758) );
INVX1TS U356 ( .A(n736), .Y(n738) );
AND2X2TS U357 ( .A(n985), .B(n28), .Y(mult_x_1_n901) );
INVX1TS U358 ( .A(n729), .Y(n730) );
AND2X2TS U359 ( .A(n644), .B(n1108), .Y(n596) );
CLKAND2X2TS U360 ( .A(n985), .B(n30), .Y(mult_x_1_n900) );
AND2X2TS U361 ( .A(n713), .B(Data_B_i[9]), .Y(n607) );
INVX1TS U362 ( .A(n667), .Y(n653) );
NOR2X1TS U363 ( .A(n23), .B(Data_B_i[8]), .Y(n756) );
AND2X2TS U364 ( .A(n644), .B(n1294), .Y(n470) );
AND2X2TS U365 ( .A(n644), .B(n1273), .Y(mult_x_1_n895) );
NAND2XLTS U366 ( .A(n385), .B(n8), .Y(n66) );
AND2X2TS U367 ( .A(n713), .B(n18), .Y(mult_x_1_n907) );
INVX1TS U368 ( .A(n823), .Y(n786) );
CLKAND2X2TS U369 ( .A(n985), .B(n16), .Y(n637) );
INVX1TS U370 ( .A(n280), .Y(n282) );
NOR2BX2TS U371 ( .AN(n317), .B(n316), .Y(n1051) );
NOR2X1TS U372 ( .A(Data_B_i[23]), .B(n1232), .Y(n280) );
NOR2X1TS U373 ( .A(n1294), .B(n1310), .Y(n736) );
NOR2X1TS U374 ( .A(n1280), .B(n1310), .Y(n647) );
INVX1TS U375 ( .A(n755), .Y(n174) );
INVX1TS U376 ( .A(n87), .Y(n91) );
INVX1TS U377 ( .A(n119), .Y(n120) );
INVX1TS U378 ( .A(n99), .Y(n121) );
NOR2X1TS U379 ( .A(Data_B_i[7]), .B(Data_B_i[8]), .Y(n755) );
OAI21X1TS U380 ( .A0(n390), .A1(n991), .B0(n45), .Y(n391) );
XOR2X2TS U381 ( .A(n334), .B(n332), .Y(mult_x_1_n759) );
ADDFHX2TS U382 ( .A(n400), .B(n399), .CI(n398), .CO(mult_x_1_n839), .S(
mult_x_1_n840) );
OAI21X2TS U383 ( .A0(n565), .A1(n1256), .B0(n566), .Y(n204) );
AOI222X1TS U384 ( .A0(n1250), .A1(n900), .B0(n1290), .B1(n386), .C0(n986),
.C1(Data_B_i[0]), .Y(n292) );
CLKINVX1TS U385 ( .A(n549), .Y(n550) );
OAI21X1TS U386 ( .A0(n1217), .A1(n1252), .B0(n1216), .Y(n1218) );
NOR2X1TS U387 ( .A(n99), .B(n123), .Y(n165) );
NOR2X1TS U388 ( .A(Data_B_i[4]), .B(Data_B_i[5]), .Y(n123) );
NOR2X1TS U389 ( .A(Data_B_i[3]), .B(Data_B_i[4]), .Y(n99) );
NOR2X2TS U390 ( .A(mult_x_1_n696), .B(mult_x_1_n706), .Y(n543) );
NOR2X2TS U391 ( .A(n612), .B(n608), .Y(n702) );
OAI21X2TS U392 ( .A0(n1336), .A1(n1332), .B0(n1333), .Y(n962) );
AOI21X2TS U393 ( .A0(n1263), .A1(n1260), .B0(n201), .Y(n202) );
XOR2X1TS U394 ( .A(n770), .B(n1140), .Y(mult_x_1_n1209) );
NOR2X1TS U395 ( .A(n1080), .B(Data_B_i[11]), .Y(n789) );
NOR2X2TS U396 ( .A(mult_x_1_n656), .B(mult_x_1_n664), .Y(n507) );
CLKINVX1TS U397 ( .A(n573), .Y(n1305) );
XOR2X1TS U398 ( .A(n109), .B(n1099), .Y(n592) );
XOR2X1TS U399 ( .A(n797), .B(Data_A_i[17]), .Y(mult_x_1_n1231) );
NOR2X4TS U400 ( .A(mult_x_1_n740), .B(mult_x_1_n750), .Y(n1200) );
XOR2X2TS U401 ( .A(n251), .B(n469), .Y(n1236) );
NOR2X1TS U402 ( .A(n652), .B(n656), .Y(n244) );
NOR2X1TS U403 ( .A(n1273), .B(n1280), .Y(n656) );
OAI21X1TS U404 ( .A0(n1301), .A1(n1235), .B0(n285), .Y(n286) );
OAI21X1TS U405 ( .A0(n442), .A1(n441), .B0(n440), .Y(n493) );
NOR2X2TS U406 ( .A(mult_x_1_n739), .B(mult_x_1_n729), .Y(n1185) );
OAI21X1TS U407 ( .A0(n368), .A1(n405), .B0(n406), .Y(n349) );
XOR2X1TS U408 ( .A(n698), .B(n1319), .Y(mult_x_1_n1171) );
CMPR42X2TS U409 ( .A(mult_x_1_n788), .B(mult_x_1_n779), .C(mult_x_1_n786),
.D(mult_x_1_n776), .ICI(mult_x_1_n782), .S(mult_x_1_n773), .ICO(
mult_x_1_n771), .CO(mult_x_1_n772) );
CLKINVX1TS U410 ( .A(n1255), .Y(n1257) );
OAI21XLTS U411 ( .A0(n1236), .A1(n326), .B0(n602), .Y(n603) );
OAI21XLTS U412 ( .A0(n1284), .A1(n326), .B0(n773), .Y(n774) );
OAI21X1TS U413 ( .A0(n326), .A1(n7), .B0(n53), .Y(n327) );
NAND2BX1TS U414 ( .AN(n295), .B(n296), .Y(n326) );
AOI21X4TS U415 ( .A0(n411), .A1(n225), .B0(n224), .Y(n486) );
XNOR2X2TS U416 ( .A(n359), .B(n358), .Y(N44) );
NOR2X2TS U417 ( .A(n288), .B(n287), .Y(n717) );
XOR2X1TS U418 ( .A(n416), .B(n415), .Y(mult_x_1_n770) );
NOR2X2TS U419 ( .A(n1200), .B(n1196), .Y(n207) );
NOR2X1TS U420 ( .A(mult_x_1_n592), .B(mult_x_1_n589), .Y(n428) );
NOR2X1TS U421 ( .A(n342), .B(n428), .Y(n348) );
XOR2X1TS U422 ( .A(n725), .B(n1132), .Y(mult_x_1_n1190) );
NOR2X2TS U423 ( .A(n223), .B(n441), .Y(n225) );
XOR2X1TS U424 ( .A(n774), .B(n1302), .Y(mult_x_1_n1219) );
NOR2X2TS U425 ( .A(n30), .B(n32), .Y(n705) );
CLKBUFX2TS U426 ( .A(n936), .Y(n1155) );
OAI21XLTS U427 ( .A0(n60), .A1(n976), .B0(n265), .Y(n266) );
CLKBUFX2TS U428 ( .A(n719), .Y(n1252) );
NOR2X1TS U429 ( .A(n295), .B(n296), .Y(n1286) );
CLKBUFX2TS U430 ( .A(n1173), .Y(n1096) );
OAI21XLTS U431 ( .A0(n1244), .A1(n1151), .B0(n831), .Y(n832) );
CLKBUFX2TS U432 ( .A(n1173), .Y(n1167) );
INVX2TS U433 ( .A(n1349), .Y(n1140) );
OAI21X2TS U434 ( .A0(n173), .A1(n172), .B0(n171), .Y(n241) );
AOI21X1TS U435 ( .A0(n170), .A1(n169), .B0(n168), .Y(n171) );
INVX2TS U436 ( .A(n1351), .Y(n1019) );
XOR2XLTS U437 ( .A(n977), .B(n1245), .Y(n984) );
OAI21XLTS U438 ( .A0(n56), .A1(n976), .B0(n262), .Y(n264) );
XOR2X1TS U439 ( .A(n395), .B(n11), .Y(n399) );
OAI21XLTS U440 ( .A0(n1035), .A1(n976), .B0(n396), .Y(n397) );
CLKAND2X2TS U441 ( .A(n985), .B(Data_B_i[17]), .Y(n595) );
INVX2TS U442 ( .A(Data_A_i[20]), .Y(n1349) );
INVX2TS U443 ( .A(n233), .Y(n1292) );
INVX2TS U444 ( .A(n632), .Y(n1099) );
XOR2XLTS U445 ( .A(n84), .B(n1115), .Y(n104) );
OAI21XLTS U446 ( .A0(n44), .A1(n1155), .B0(n101), .Y(n102) );
XOR2X1TS U447 ( .A(n289), .B(n1319), .Y(n416) );
AND2X2TS U448 ( .A(n416), .B(n415), .Y(n334) );
XNOR2X1TS U449 ( .A(Data_A_i[14]), .B(Data_A_i[15]), .Y(n295) );
OAI21XLTS U450 ( .A0(n60), .A1(n991), .B0(n387), .Y(n388) );
NAND3XLTS U451 ( .A(n261), .B(n260), .C(n259), .Y(n4) );
XOR2X1TS U452 ( .A(n314), .B(n1140), .Y(n1009) );
OAI21XLTS U453 ( .A0(n1253), .A1(n1252), .B0(n1251), .Y(n1254) );
XNOR2X1TS U454 ( .A(n142), .B(n93), .Y(n1244) );
ADDHXLTS U455 ( .A(n162), .B(n161), .CO(n959), .S(n183) );
XOR2XLTS U456 ( .A(n138), .B(n1019), .Y(n162) );
OAI21XLTS U457 ( .A0(n390), .A1(n1167), .B0(n137), .Y(n138) );
CLKBUFX2TS U458 ( .A(n922), .Y(n1077) );
INVX2TS U459 ( .A(n633), .Y(n1115) );
OAI21XLTS U460 ( .A0(n56), .A1(n1155), .B0(n105), .Y(n106) );
OAI21XLTS U461 ( .A0(n60), .A1(n1105), .B0(n108), .Y(n109) );
ADDHXLTS U462 ( .A(n979), .B(n978), .CO(n453), .S(n983) );
XOR2XLTS U463 ( .A(n391), .B(n992), .Y(n979) );
OAI21XLTS U464 ( .A0(n1126), .A1(n1096), .B0(n888), .Y(n889) );
OAI21XLTS U465 ( .A0(n1222), .A1(n861), .B0(n1090), .Y(n1091) );
OAI21XLTS U466 ( .A0(n44), .A1(n1269), .B0(n1013), .Y(n1014) );
NOR2BX1TS U467 ( .AN(n1010), .B(n315), .Y(n1025) );
XOR2X1TS U468 ( .A(n320), .B(n1140), .Y(n1024) );
OAI21XLTS U469 ( .A0(n60), .A1(n1177), .B0(n319), .Y(n320) );
AOI222XLTS U470 ( .A0(n1137), .A1(n900), .B0(n1136), .B1(n386), .C0(n1134),
.C1(Data_B_i[0]), .Y(n319) );
OAI21XLTS U471 ( .A0(n1126), .A1(n1162), .B0(n1125), .Y(n1127) );
INVX2TS U472 ( .A(n263), .Y(n1245) );
CLKAND2X2TS U473 ( .A(n985), .B(n8), .Y(n337) );
NOR2BX2TS U474 ( .AN(n334), .B(n333), .Y(n335) );
CLKAND2X2TS U475 ( .A(n985), .B(n13), .Y(n996) );
CLKAND2X2TS U476 ( .A(n713), .B(n14), .Y(n641) );
XOR2X1TS U477 ( .A(n639), .B(Data_A_i[20]), .Y(n640) );
OAI21XLTS U478 ( .A0(n1030), .A1(n1053), .B0(n638), .Y(n639) );
OAI21XLTS U479 ( .A0(n1030), .A1(n1252), .B0(n712), .Y(n714) );
CLKAND2X2TS U480 ( .A(n713), .B(n17), .Y(n631) );
INVX2TS U481 ( .A(n324), .Y(n1271) );
CLKBUFX2TS U482 ( .A(n861), .Y(n1235) );
CLKAND2X2TS U483 ( .A(n1094), .B(n1229), .Y(n869) );
INVX2TS U484 ( .A(n263), .Y(n1237) );
OAI21X1TS U485 ( .A0(n1078), .A1(n1269), .B0(n777), .Y(n778) );
CLKAND2X2TS U486 ( .A(n713), .B(Data_B_i[8]), .Y(mult_x_1_n905) );
XOR2XLTS U487 ( .A(n1141), .B(n1140), .Y(mult_x_1_n1199) );
INVX2TS U488 ( .A(n324), .Y(n1302) );
NOR2X1TS U489 ( .A(n705), .B(n692), .Y(n237) );
OAI21XLTS U490 ( .A0(n1030), .A1(n1155), .B0(n177), .Y(n178) );
OAI21XLTS U491 ( .A0(n60), .A1(n1167), .B0(n159), .Y(n160) );
OAI21XLTS U492 ( .A0(n934), .A1(n1173), .B0(n894), .Y(n895) );
CMPR42X1TS U493 ( .A(mult_x_1_n827), .B(mult_x_1_n1263), .C(mult_x_1_n1335),
.D(mult_x_1_n1311), .ICI(mult_x_1_n831), .S(mult_x_1_n825), .ICO(
mult_x_1_n823), .CO(mult_x_1_n824) );
XOR2XLTS U494 ( .A(n893), .B(n11), .Y(mult_x_1_n1311) );
XOR2XLTS U495 ( .A(n919), .B(n1115), .Y(mult_x_1_n1335) );
INVX2TS U496 ( .A(n1350), .Y(n992) );
CLKAND2X2TS U497 ( .A(n985), .B(n1073), .Y(n600) );
INVX2TS U498 ( .A(n233), .Y(n713) );
ADDHXLTS U499 ( .A(n131), .B(n130), .CO(n149), .S(n132) );
XOR2XLTS U500 ( .A(n81), .B(n1115), .Y(n131) );
OAI21XLTS U501 ( .A0(n60), .A1(n1077), .B0(n80), .Y(n81) );
OAI21X2TS U502 ( .A0(n193), .A1(n583), .B0(n192), .Y(n576) );
AOI21X1TS U503 ( .A0(n1329), .A1(n1326), .B0(n191), .Y(n192) );
INVX2TS U504 ( .A(n532), .Y(n524) );
CLKAND2X2TS U505 ( .A(n644), .B(n1280), .Y(mult_x_1_n894) );
CLKBUFX2TS U506 ( .A(Data_B_i[22]), .Y(n1314) );
INVX2TS U507 ( .A(n233), .Y(n644) );
OAI21XLTS U508 ( .A0(n390), .A1(n936), .B0(n59), .Y(n110) );
OAI21X1TS U509 ( .A0(n118), .A1(n590), .B0(n117), .Y(n587) );
OR2X1TS U510 ( .A(n133), .B(n132), .Y(n586) );
OR2X2TS U511 ( .A(mult_x_1_n859), .B(mult_x_1_n863), .Y(n1329) );
NOR2X1TS U512 ( .A(mult_x_1_n852), .B(mult_x_1_n858), .Y(n1321) );
NAND2X1TS U513 ( .A(mult_x_1_n814), .B(mult_x_1_n821), .Y(n571) );
NOR2X1TS U514 ( .A(mult_x_1_n794), .B(mult_x_1_n803), .Y(n1255) );
INVX4TS U515 ( .A(n9), .Y(n10) );
OAI21XLTS U516 ( .A0(n56), .A1(n1252), .B0(n330), .Y(n331) );
OAI21XLTS U517 ( .A0(n44), .A1(n1252), .B0(n987), .Y(n988) );
OAI21XLTS U518 ( .A0(n1126), .A1(n1131), .B0(n1056), .Y(n1057) );
OAI21XLTS U519 ( .A0(n1222), .A1(n1252), .B0(n1221), .Y(n1223) );
OAI21XLTS U520 ( .A0(n44), .A1(n976), .B0(n975), .Y(n977) );
XOR2XLTS U521 ( .A(n258), .B(n992), .Y(n392) );
OAI21X1TS U522 ( .A0(n1162), .A1(n7), .B0(n66), .Y(n258) );
OAI21XLTS U523 ( .A0(n56), .A1(n991), .B0(n837), .Y(n838) );
OAI21XLTS U524 ( .A0(n1244), .A1(n861), .B0(n1243), .Y(n1246) );
OAI21XLTS U525 ( .A0(n1222), .A1(n1173), .B0(n1172), .Y(n1174) );
OAI21XLTS U526 ( .A0(n44), .A1(n991), .B0(n835), .Y(n836) );
OAI21XLTS U527 ( .A0(n1018), .A1(n1077), .B0(n918), .Y(n919) );
OAI21XLTS U528 ( .A0(n1253), .A1(n1173), .B0(n892), .Y(n893) );
OAI21XLTS U529 ( .A0(n1217), .A1(n1173), .B0(n890), .Y(n891) );
OAI21XLTS U530 ( .A0(n1030), .A1(n861), .B0(n865), .Y(n866) );
OAI21XLTS U531 ( .A0(n1139), .A1(n1077), .B0(n916), .Y(n917) );
INVX2TS U532 ( .A(n1003), .Y(n1004) );
OAI21XLTS U533 ( .A0(n934), .A1(n1151), .B0(n829), .Y(n830) );
OAI21XLTS U534 ( .A0(n1253), .A1(n861), .B0(n1064), .Y(n1065) );
XOR2XLTS U535 ( .A(n291), .B(n1292), .Y(n642) );
OAI21XLTS U536 ( .A0(n1244), .A1(n1227), .B0(n1226), .Y(n1228) );
OAI21XLTS U537 ( .A0(n1222), .A1(n1151), .B0(n1150), .Y(n1152) );
OAI21XLTS U538 ( .A0(n1217), .A1(n861), .B0(n863), .Y(n864) );
OAI21XLTS U539 ( .A0(n1126), .A1(n1235), .B0(n859), .Y(n860) );
OAI21XLTS U540 ( .A0(n1139), .A1(n976), .B0(n855), .Y(n856) );
OAI21XLTS U541 ( .A0(n1217), .A1(n1151), .B0(n1083), .Y(n1084) );
OAI21XLTS U542 ( .A0(n1018), .A1(n976), .B0(n857), .Y(n858) );
OAI21XLTS U543 ( .A0(n1253), .A1(n1151), .B0(n827), .Y(n828) );
OAI21XLTS U544 ( .A0(n1146), .A1(n922), .B0(n1145), .Y(n1147) );
OAI21XLTS U545 ( .A0(n44), .A1(n1177), .B0(n769), .Y(n770) );
OAI21XLTS U546 ( .A0(n1035), .A1(n1177), .B0(n767), .Y(n768) );
CLKAND2X2TS U547 ( .A(n1102), .B(n1229), .Y(n939) );
OAI21XLTS U548 ( .A0(n1253), .A1(n1227), .B0(n1047), .Y(n1048) );
OAI21XLTS U549 ( .A0(n1318), .A1(n922), .B0(n1058), .Y(n1059) );
OAI21XLTS U550 ( .A0(n1217), .A1(n1227), .B0(n794), .Y(n795) );
OAI21XLTS U551 ( .A0(n1035), .A1(n719), .B0(n718), .Y(n720) );
OAI21XLTS U552 ( .A0(n1126), .A1(n1227), .B0(n1081), .Y(n1082) );
CLKAND2X2TS U553 ( .A(n1181), .B(n1229), .Y(n1070) );
OAI21XLTS U554 ( .A0(n1253), .A1(n1053), .B0(n1052), .Y(n1054) );
ADDFHX2TS U555 ( .A(n1106), .B(n452), .CI(n451), .CO(mult_x_1_n714), .S(
mult_x_1_n715) );
CLKAND2X2TS U556 ( .A(n985), .B(n15), .Y(n452) );
XOR2XLTS U557 ( .A(n450), .B(n1292), .Y(n451) );
OAI21XLTS U558 ( .A0(n1244), .A1(n1252), .B0(n449), .Y(n450) );
OAI21XLTS U559 ( .A0(n1), .A1(n1162), .B0(n812), .Y(n813) );
OAI21XLTS U560 ( .A0(n1217), .A1(n1053), .B0(n1049), .Y(n1050) );
OAI21XLTS U561 ( .A0(n1139), .A1(n1269), .B0(n783), .Y(n784) );
OAI21XLTS U562 ( .A0(n1121), .A1(n1162), .B0(n1120), .Y(n1122) );
OAI21XLTS U563 ( .A0(n1146), .A1(n1162), .B0(n808), .Y(n809) );
OAI21XLTS U564 ( .A0(n1278), .A1(n1162), .B0(n806), .Y(n807) );
CLKAND2X2TS U565 ( .A(n1230), .B(n1229), .Y(n1231) );
OAI21XLTS U566 ( .A0(n1284), .A1(n1162), .B0(n804), .Y(n805) );
OAI21XLTS U567 ( .A0(n1301), .A1(n1162), .B0(n802), .Y(n803) );
OAI21XLTS U568 ( .A0(n1278), .A1(n326), .B0(n1277), .Y(n1279) );
OAI21XLTS U569 ( .A0(n1139), .A1(n719), .B0(n710), .Y(n711) );
OAI21XLTS U570 ( .A0(n1318), .A1(n1162), .B0(n311), .Y(n312) );
OAI21XLTS U571 ( .A0(n1270), .A1(n719), .B0(n697), .Y(n698) );
OAI21XLTS U572 ( .A0(n1236), .A1(n1162), .B0(n1161), .Y(n1164) );
CLKAND2X2TS U573 ( .A(n1158), .B(n1229), .Y(n1159) );
CLKAND2X2TS U574 ( .A(n644), .B(Data_B_i[11]), .Y(n606) );
OAI21XLTS U575 ( .A0(n1318), .A1(n326), .B0(n1287), .Y(n1288) );
CLKAND2X2TS U576 ( .A(n1297), .B(n1229), .Y(n601) );
AOI21X1TS U577 ( .A0(n237), .A1(n700), .B0(n236), .Y(n238) );
OAI21XLTS U578 ( .A0(n56), .A1(n1167), .B0(n904), .Y(n905) );
OAI21XLTS U579 ( .A0(n1244), .A1(n1114), .B0(n1113), .Y(n1116) );
OAI21XLTS U580 ( .A0(n44), .A1(n1167), .B0(n901), .Y(n902) );
OAI21XLTS U581 ( .A0(n1030), .A1(n1114), .B0(n930), .Y(n931) );
OAI21XLTS U582 ( .A0(n1035), .A1(n1167), .B0(n898), .Y(n899) );
OAI21XLTS U583 ( .A0(n1244), .A1(n1173), .B0(n896), .Y(n897) );
XOR2XLTS U584 ( .A(n1091), .B(Data_A_i[11]), .Y(mult_x_1_n1285) );
XOR2X1TS U585 ( .A(n1010), .B(n1009), .Y(n1023) );
CMPR42X1TS U586 ( .A(mult_x_1_n781), .B(mult_x_1_n1210), .C(mult_x_1_n790),
.D(mult_x_1_n1234), .ICI(mult_x_1_n1258), .S(mult_x_1_n779), .ICO(
mult_x_1_n777), .CO(mult_x_1_n778) );
XOR2XLTS U587 ( .A(n1152), .B(n1163), .Y(mult_x_1_n1258) );
NOR2BX2TS U588 ( .AN(n1025), .B(n321), .Y(mult_x_1_n790) );
XOR2X1TS U589 ( .A(n1025), .B(n1024), .Y(n1039) );
XOR2XLTS U590 ( .A(n1127), .B(Data_A_i[14]), .Y(mult_x_1_n1255) );
CLKAND2X2TS U591 ( .A(n985), .B(n19), .Y(mult_x_1_n906) );
XOR2XLTS U592 ( .A(n1168), .B(n11), .Y(mult_x_1_n1296) );
XOR2X1TS U593 ( .A(n670), .B(n669), .Y(n1078) );
CLKAND2X2TS U594 ( .A(n985), .B(n1080), .Y(n620) );
CMPR42X1TS U595 ( .A(mult_x_1_n627), .B(mult_x_1_n634), .C(mult_x_1_n1171),
.D(mult_x_1_n1219), .ICI(mult_x_1_n1243), .S(mult_x_1_n626), .ICO(
mult_x_1_n624), .CO(mult_x_1_n625) );
XOR2XLTS U596 ( .A(n1164), .B(n1163), .Y(mult_x_1_n1243) );
CLKAND2X2TS U597 ( .A(n644), .B(n32), .Y(mult_x_1_n899) );
XOR2XLTS U598 ( .A(n1303), .B(n1302), .Y(mult_x_1_n1217) );
OAI21XLTS U599 ( .A0(n1146), .A1(n1317), .B0(n661), .Y(n662) );
CLKAND2X2TS U600 ( .A(n1128), .B(n1229), .Y(n721) );
CLKBUFX2TS U601 ( .A(Data_B_i[19]), .Y(n1280) );
INVX2TS U602 ( .A(n233), .Y(n1319) );
CLKAND2X2TS U603 ( .A(n1313), .B(n1298), .Y(n253) );
NAND2X1TS U604 ( .A(n82), .B(n87), .Y(n390) );
XOR2XLTS U605 ( .A(n85), .B(n1115), .Y(n107) );
OAI21XLTS U606 ( .A0(n1035), .A1(n1155), .B0(n128), .Y(n129) );
OAI21XLTS U607 ( .A0(n56), .A1(n1077), .B0(n77), .Y(n78) );
CLKAND2X2TS U608 ( .A(n644), .B(n1310), .Y(mult_x_1_n893) );
CLKAND2X2TS U609 ( .A(n644), .B(n1314), .Y(n468) );
OAI21XLTS U610 ( .A0(n1178), .A1(n719), .B0(n377), .Y(n378) );
XOR3X1TS U611 ( .A(n233), .B(n471), .C(n470), .Y(n472) );
CLKAND2X2TS U612 ( .A(n644), .B(n1229), .Y(n471) );
CLKAND2X2TS U613 ( .A(n419), .B(n418), .Y(n46) );
XOR2XLTS U614 ( .A(n43), .B(n1348), .Y(N1) );
XOR2XLTS U615 ( .A(n1341), .B(n1340), .Y(N6) );
OAI21XLTS U616 ( .A0(n1259), .A1(n1255), .B0(n1256), .Y(n569) );
XOR2XLTS U617 ( .A(n1213), .B(n1212), .Y(N22) );
XOR2XLTS U618 ( .A(n1191), .B(n1190), .Y(N23) );
XOR2XLTS U619 ( .A(n1204), .B(n1203), .Y(N24) );
INVX2TS U620 ( .A(n1200), .Y(n1202) );
XOR2XLTS U621 ( .A(n6), .B(n1043), .Y(N33) );
CLKAND2X2TS U622 ( .A(n447), .B(n446), .Y(n47) );
CLKAND2X2TS U623 ( .A(n69), .B(n437), .Y(n48) );
CLKAND2X2TS U624 ( .A(n430), .B(n429), .Y(n49) );
OA21X4TS U625 ( .A0(n561), .A1(n209), .B0(n208), .Y(n3) );
AOI21X2TS U626 ( .A0(n207), .A1(n1194), .B0(n206), .Y(n208) );
OAI21XLTS U627 ( .A0(n1078), .A1(n936), .B0(n942), .Y(n943) );
OAI21XLTS U628 ( .A0(n1078), .A1(n719), .B0(n671), .Y(n672) );
OAI21XLTS U629 ( .A0(n1078), .A1(n1167), .B0(n880), .Y(n881) );
OAI21XLTS U630 ( .A0(n1078), .A1(n976), .B0(n849), .Y(n850) );
OAI21XLTS U631 ( .A0(n1078), .A1(n1077), .B0(n1076), .Y(n1079) );
NOR2X1TS U632 ( .A(n96), .B(n94), .Y(n146) );
NOR2X1TS U633 ( .A(n158), .B(n157), .Y(n155) );
INVX2TS U634 ( .A(Data_B_i[0]), .Y(n7) );
INVX2TS U635 ( .A(n11), .Y(n1351) );
INVX2TS U636 ( .A(n9), .Y(n11) );
AOI21X4TS U637 ( .A0(n967), .A1(n965), .B0(n200), .Y(n570) );
INVX2TS U638 ( .A(Data_A_i[14]), .Y(n1350) );
CLKINVX6TS U639 ( .A(n219), .Y(n6) );
CLKINVX6TS U640 ( .A(n219), .Y(n1044) );
INVX2TS U641 ( .A(n7), .Y(n8) );
INVX2TS U642 ( .A(n4), .Y(n12) );
CLKBUFX2TS U643 ( .A(Data_B_i[1]), .Y(n13) );
OR2X1TS U644 ( .A(Data_B_i[1]), .B(n8), .Y(n82) );
CLKBUFX2TS U645 ( .A(Data_B_i[2]), .Y(n14) );
CLKBUFX2TS U646 ( .A(Data_B_i[3]), .Y(n15) );
CLKBUFX2TS U647 ( .A(Data_B_i[4]), .Y(n16) );
CLKBUFX2TS U648 ( .A(Data_B_i[5]), .Y(n17) );
CLKBUFX2TS U649 ( .A(Data_B_i[6]), .Y(n18) );
CLKBUFX2TS U650 ( .A(Data_B_i[7]), .Y(n19) );
INVX2TS U651 ( .A(Data_B_i[8]), .Y(n20) );
INVX2TS U652 ( .A(n20), .Y(n21) );
INVX2TS U653 ( .A(Data_B_i[9]), .Y(n22) );
INVX2TS U654 ( .A(n22), .Y(n23) );
INVX2TS U655 ( .A(Data_B_i[11]), .Y(n24) );
INVX2TS U656 ( .A(n24), .Y(n25) );
INVX2TS U657 ( .A(Data_B_i[12]), .Y(n26) );
INVX2TS U658 ( .A(n26), .Y(n28) );
INVX2TS U659 ( .A(Data_B_i[13]), .Y(n29) );
INVX2TS U660 ( .A(n29), .Y(n30) );
INVX2TS U661 ( .A(Data_B_i[14]), .Y(n31) );
INVX2TS U662 ( .A(Data_B_i[17]), .Y(n34) );
INVX2TS U663 ( .A(n633), .Y(n36) );
INVX2TS U664 ( .A(Data_A_i[5]), .Y(n633) );
INVX2TS U665 ( .A(n1089), .Y(n37) );
INVX2TS U666 ( .A(n1089), .Y(n38) );
INVX2TS U667 ( .A(n155), .Y(n1171) );
INVX2TS U668 ( .A(n1171), .Y(n39) );
INVX2TS U669 ( .A(n1171), .Y(n40) );
OAI21X1TS U670 ( .A0(n1044), .A1(n487), .B0(n486), .Y(n491) );
INVX2TS U671 ( .A(n1153), .Y(n1101) );
INVX2TS U672 ( .A(n1101), .Y(n41) );
INVX2TS U673 ( .A(n1101), .Y(n42) );
XNOR2X1TS U674 ( .A(n110), .B(n1099), .Y(n43) );
XOR2X1TS U675 ( .A(n122), .B(n100), .Y(n44) );
AOI22X1TS U676 ( .A0(n1149), .A1(n389), .B0(n1119), .B1(Data_B_i[1]), .Y(n45) );
NAND2X1TS U677 ( .A(n37), .B(n8), .Y(n50) );
NAND2X1TS U678 ( .A(n39), .B(n8), .Y(n51) );
CLKBUFX2TS U679 ( .A(n936), .Y(n1105) );
NAND2X1TS U680 ( .A(n1286), .B(n389), .Y(n53) );
AOI22X1TS U681 ( .A0(n1224), .A1(n389), .B0(n1286), .B1(Data_B_i[1]), .Y(n54) );
CLKBUFX2TS U682 ( .A(n922), .Y(n1114) );
INVX2TS U683 ( .A(n86), .Y(n71) );
XOR2X1TS U684 ( .A(n73), .B(n72), .Y(n56) );
OR2X1TS U685 ( .A(Data_B_i[1]), .B(Data_B_i[2]), .Y(n57) );
NAND2X1TS U686 ( .A(n1103), .B(n8), .Y(n58) );
AOI22X1TS U687 ( .A0(n1103), .A1(n13), .B0(n1102), .B1(n389), .Y(n59) );
XNOR2X1TS U688 ( .A(n79), .B(n87), .Y(n60) );
AOI22X1TS U689 ( .A0(n1313), .A1(n389), .B0(n717), .B1(Data_B_i[1]), .Y(n61)
);
OR2X2TS U690 ( .A(mult_x_1_n869), .B(n189), .Y(n63) );
OR2X2TS U691 ( .A(mult_x_1_n814), .B(mult_x_1_n821), .Y(n65) );
AOI22X1TS U692 ( .A0(n1128), .A1(n389), .B0(n743), .B1(n13), .Y(n67) );
AOI21X1TS U693 ( .A0(n701), .A1(n624), .B0(n609), .Y(n610) );
AOI21X1TS U694 ( .A0(n71), .A1(n91), .B0(n90), .Y(n172) );
INVX2TS U695 ( .A(n692), .Y(n694) );
INVX2TS U696 ( .A(Data_A_i[1]), .Y(n95) );
INVX2TS U697 ( .A(n241), .Y(n822) );
OAI21XLTS U698 ( .A0(n60), .A1(n1269), .B0(n328), .Y(n329) );
NAND2BX1TS U699 ( .AN(n309), .B(n308), .Y(n1151) );
NAND2BX1TS U700 ( .AN(n75), .B(n76), .Y(n922) );
CLKBUFX2TS U701 ( .A(n326), .Y(n1227) );
CLKBUFX2TS U702 ( .A(n861), .Y(n976) );
AOI21X1TS U703 ( .A0(n122), .A1(n165), .B0(n169), .Y(n142) );
NAND2BX1TS U704 ( .AN(n157), .B(n158), .Y(n1173) );
CLKBUFX2TS U705 ( .A(n1151), .Y(n991) );
OAI21XLTS U706 ( .A0(n1146), .A1(n1105), .B0(n1092), .Y(n1093) );
OAI21XLTS U707 ( .A0(n56), .A1(n1177), .B0(n771), .Y(n772) );
OAI21XLTS U708 ( .A0(n1030), .A1(n1227), .B0(n798), .Y(n799) );
INVX2TS U709 ( .A(n1350), .Y(n1163) );
OAI21XLTS U710 ( .A0(n1301), .A1(n326), .B0(n1300), .Y(n1303) );
CLKBUFX2TS U711 ( .A(n1053), .Y(n1177) );
OAI21XLTS U712 ( .A0(n922), .A1(n7), .B0(n55), .Y(n85) );
OAI21XLTS U713 ( .A0(n44), .A1(n1077), .B0(n140), .Y(n141) );
INVX2TS U714 ( .A(n1349), .Y(n1132) );
INVX2TS U715 ( .A(n632), .Y(n1156) );
CMPR42X1TS U716 ( .A(mult_x_1_n1207), .B(mult_x_1_n1279), .C(mult_x_1_n1231),
.D(mult_x_1_n1255), .ICI(mult_x_1_n752), .S(mult_x_1_n746), .ICO(
mult_x_1_n744), .CO(mult_x_1_n745) );
CMPR42X1TS U717 ( .A(mult_x_1_n900), .B(mult_x_1_n627), .C(mult_x_1_n1242),
.D(mult_x_1_n1170), .ICI(mult_x_1_n1218), .S(mult_x_1_n619), .ICO(
mult_x_1_n617), .CO(mult_x_1_n618) );
CMPR42X1TS U718 ( .A(mult_x_1_n866), .B(mult_x_1_n1317), .C(mult_x_1_n1365),
.D(mult_x_1_n1341), .ICI(mult_x_1_n867), .S(mult_x_1_n864), .ICO(
mult_x_1_n862), .CO(mult_x_1_n863) );
CMPR42X1TS U719 ( .A(mult_x_1_n1287), .B(mult_x_1_n1359), .C(mult_x_1_n828),
.D(mult_x_1_n832), .ICI(mult_x_1_n825), .S(mult_x_1_n822), .ICO(
mult_x_1_n820), .CO(mult_x_1_n821) );
INVX2TS U720 ( .A(n562), .Y(n1207) );
INVX2TS U721 ( .A(n570), .Y(n1261) );
INVX2TS U722 ( .A(Data_A_i[0]), .Y(n94) );
CLKBUFX2TS U723 ( .A(n146), .Y(n1103) );
NOR2X1TS U724 ( .A(mult_x_1_n685), .B(mult_x_1_n695), .Y(n521) );
NOR2X2TS U725 ( .A(mult_x_1_n675), .B(mult_x_1_n684), .Y(n527) );
NOR2X1TS U726 ( .A(n521), .B(n527), .Y(n513) );
NOR2X2TS U727 ( .A(mult_x_1_n665), .B(mult_x_1_n674), .Y(n516) );
NAND2X2TS U728 ( .A(n513), .B(n213), .Y(n215) );
NOR2X2TS U729 ( .A(mult_x_1_n718), .B(mult_x_1_n728), .Y(n556) );
NOR2X1TS U730 ( .A(n539), .B(n543), .Y(n211) );
NAND2X1TS U731 ( .A(n548), .B(n211), .Y(n534) );
NOR2X1TS U732 ( .A(n215), .B(n534), .Y(n218) );
NOR2X2TS U733 ( .A(mult_x_1_n845), .B(mult_x_1_n851), .Y(n577) );
NOR2X1TS U734 ( .A(n577), .B(n1321), .Y(n195) );
NAND2X1TS U735 ( .A(n1329), .B(n62), .Y(n193) );
XNOR2X1TS U736 ( .A(Data_A_i[5]), .B(Data_A_i[6]), .Y(n157) );
XOR2X1TS U737 ( .A(n10), .B(Data_A_i[7]), .Y(n158) );
OAI21X1TS U738 ( .A0(n1096), .A1(n7), .B0(n51), .Y(n70) );
XOR2X1TS U739 ( .A(n70), .B(n1019), .Y(n139) );
NAND2X1TS U740 ( .A(Data_B_i[1]), .B(Data_B_i[2]), .Y(n88) );
NAND2X1TS U741 ( .A(n88), .B(n87), .Y(n73) );
NOR2X1TS U742 ( .A(Data_B_i[2]), .B(Data_B_i[3]), .Y(n86) );
NAND2X1TS U743 ( .A(Data_B_i[2]), .B(Data_B_i[3]), .Y(n89) );
NAND2X1TS U744 ( .A(n71), .B(n89), .Y(n72) );
XNOR2X1TS U745 ( .A(Data_A_i[2]), .B(Data_A_i[3]), .Y(n75) );
XOR2X1TS U746 ( .A(Data_A_i[5]), .B(Data_A_i[4]), .Y(n76) );
NOR2X1TS U747 ( .A(n76), .B(n75), .Y(n1112) );
CLKBUFX2TS U748 ( .A(n1112), .Y(n932) );
CLKBUFX2TS U749 ( .A(Data_B_i[3]), .Y(n1000) );
XNOR2X1TS U750 ( .A(Data_A_i[3]), .B(Data_A_i[4]), .Y(n74) );
NOR2BX1TS U751 ( .AN(n75), .B(n74), .Y(n923) );
CLKBUFX2TS U752 ( .A(n923), .Y(n1111) );
CLKBUFX2TS U753 ( .A(Data_B_i[2]), .Y(n999) );
AND3X2TS U754 ( .A(n76), .B(n75), .C(n74), .Y(n1180) );
CLKBUFX2TS U755 ( .A(n1180), .Y(n1142) );
CLKBUFX2TS U756 ( .A(Data_B_i[1]), .Y(n998) );
AOI222XLTS U757 ( .A0(n932), .A1(n1000), .B0(n1111), .B1(n999), .C0(n1142),
.C1(n998), .Y(n77) );
NAND2X1TS U758 ( .A(n57), .B(n88), .Y(n79) );
CLKBUFX2TS U759 ( .A(Data_B_i[2]), .Y(n900) );
CLKBUFX2TS U760 ( .A(Data_B_i[1]), .Y(n386) );
CLKBUFX2TS U761 ( .A(n923), .Y(n1181) );
INVX2TS U762 ( .A(n7), .Y(n389) );
CLKBUFX2TS U763 ( .A(n1112), .Y(n1182) );
AOI22X1TS U764 ( .A0(n1181), .A1(n389), .B0(n1182), .B1(n998), .Y(n83) );
OAI21X1TS U765 ( .A0(n390), .A1(n1077), .B0(n83), .Y(n84) );
NAND2X1TS U766 ( .A(n89), .B(n88), .Y(n90) );
INVX2TS U767 ( .A(n172), .Y(n122) );
NAND2X1TS U768 ( .A(Data_B_i[4]), .B(Data_B_i[5]), .Y(n124) );
NAND2X1TS U769 ( .A(Data_B_i[3]), .B(Data_B_i[4]), .Y(n119) );
NAND2X1TS U770 ( .A(n124), .B(n119), .Y(n169) );
NOR2X1TS U771 ( .A(Data_B_i[6]), .B(Data_B_i[5]), .Y(n163) );
NAND2X1TS U772 ( .A(Data_B_i[6]), .B(Data_B_i[5]), .Y(n166) );
NAND2X1TS U773 ( .A(n92), .B(n166), .Y(n93) );
CLKBUFX2TS U774 ( .A(n146), .Y(n1067) );
CLKBUFX2TS U775 ( .A(Data_B_i[6]), .Y(n1225) );
NOR2BX1TS U776 ( .AN(n94), .B(n95), .Y(n176) );
CLKBUFX2TS U777 ( .A(n176), .Y(n1066) );
CLKBUFX2TS U778 ( .A(Data_B_i[5]), .Y(n1239) );
CLKBUFX2TS U779 ( .A(Data_B_i[4]), .Y(n1012) );
AOI222XLTS U780 ( .A0(n1067), .A1(n1225), .B0(n1066), .B1(n1239), .C0(n41),
.C1(n1012), .Y(n97) );
NOR2X1TS U781 ( .A(n136), .B(n135), .Y(n1337) );
NAND2X1TS U782 ( .A(n121), .B(n119), .Y(n100) );
CLKBUFX2TS U783 ( .A(Data_B_i[3]), .Y(n1011) );
AOI222XLTS U784 ( .A0(n1067), .A1(n1012), .B0(n1066), .B1(n1011), .C0(n42),
.C1(n900), .Y(n101) );
XOR2X1TS U785 ( .A(n102), .B(n1156), .Y(n115) );
ADDHXLTS U786 ( .A(n104), .B(n103), .CO(n130), .S(n114) );
AOI222XLTS U787 ( .A0(n1067), .A1(n1000), .B0(n1066), .B1(n999), .C0(n41),
.C1(n998), .Y(n105) );
XOR2X1TS U788 ( .A(n106), .B(n1156), .Y(n113) );
ADDHXLTS U789 ( .A(Data_A_i[5]), .B(n107), .CO(n103), .S(n112) );
NAND2X1TS U790 ( .A(n2), .B(n1344), .Y(n118) );
AOI222XLTS U791 ( .A0(n1067), .A1(n900), .B0(n1066), .B1(n386), .C0(n42),
.C1(Data_B_i[0]), .Y(n108) );
CLKBUFX2TS U792 ( .A(n176), .Y(n1102) );
NAND2X1TS U793 ( .A(n111), .B(Data_A_i[2]), .Y(n1348) );
NAND2X1TS U794 ( .A(n592), .B(n593), .Y(n590) );
NAND2X1TS U795 ( .A(n113), .B(n112), .Y(n589) );
INVX2TS U796 ( .A(n589), .Y(n1343) );
NAND2X1TS U797 ( .A(n115), .B(n114), .Y(n1342) );
AOI21X1TS U798 ( .A0(n2), .A1(n1343), .B0(n116), .Y(n117) );
AOI21X1TS U799 ( .A0(n122), .A1(n121), .B0(n120), .Y(n127) );
NAND2X1TS U800 ( .A(n125), .B(n124), .Y(n126) );
XNOR2X1TS U801 ( .A(n127), .B(n126), .Y(n1035) );
CLKBUFX2TS U802 ( .A(Data_B_i[5]), .Y(n1033) );
CLKBUFX2TS U803 ( .A(Data_B_i[4]), .Y(n1032) );
AOI222XLTS U804 ( .A0(n1067), .A1(n1033), .B0(n1066), .B1(n1032), .C0(n41),
.C1(n1000), .Y(n128) );
NAND2X1TS U805 ( .A(n133), .B(n132), .Y(n585) );
AOI21X1TS U806 ( .A0(n587), .A1(n586), .B0(n134), .Y(n1340) );
NAND2X1TS U807 ( .A(n136), .B(n135), .Y(n1338) );
OAI21X1TS U808 ( .A0(n1337), .A1(n1340), .B0(n1338), .Y(n972) );
XNOR2X1TS U809 ( .A(Data_A_i[6]), .B(Data_A_i[7]), .Y(n156) );
NOR2BX1TS U810 ( .AN(n157), .B(n156), .Y(n393) );
CLKBUFX2TS U811 ( .A(n393), .Y(n1094) );
AOI22X1TS U812 ( .A0(n1094), .A1(n389), .B0(n39), .B1(n998), .Y(n137) );
ADDHXLTS U813 ( .A(n11), .B(n139), .CO(n161), .S(n151) );
AOI222XLTS U814 ( .A0(n932), .A1(n1012), .B0(n1111), .B1(n1011), .C0(n1142),
.C1(Data_B_i[2]), .Y(n140) );
OAI21X1TS U815 ( .A0(n142), .A1(n163), .B0(n166), .Y(n145) );
NAND2X1TS U816 ( .A(Data_B_i[6]), .B(Data_B_i[7]), .Y(n167) );
NAND2X1TS U817 ( .A(n143), .B(n167), .Y(n144) );
CLKBUFX2TS U818 ( .A(Data_B_i[7]), .Y(n1169) );
CLKBUFX2TS U819 ( .A(Data_B_i[6]), .Y(n1241) );
AOI222XLTS U820 ( .A0(n146), .A1(n1169), .B0(n1066), .B1(n1241), .C0(n41),
.C1(n1033), .Y(n147) );
NAND2X1TS U821 ( .A(n153), .B(n152), .Y(n971) );
AOI21X1TS U822 ( .A0(n972), .A1(n5), .B0(n154), .Y(n1336) );
CLKBUFX2TS U823 ( .A(n393), .Y(n1015) );
AND3X2TS U824 ( .A(n158), .B(n157), .C(n156), .Y(n1165) );
CLKBUFX2TS U825 ( .A(n1165), .Y(n903) );
AOI222XLTS U826 ( .A0(n40), .A1(n900), .B0(n1015), .B1(n386), .C0(n903),
.C1(Data_B_i[0]), .Y(n159) );
XOR2X1TS U827 ( .A(n160), .B(n1019), .Y(n960) );
NOR2X1TS U828 ( .A(n164), .B(n163), .Y(n170) );
NAND2X1TS U829 ( .A(n165), .B(n170), .Y(n173) );
NAND2X1TS U830 ( .A(n167), .B(n166), .Y(n168) );
NAND2X1TS U831 ( .A(Data_B_i[7]), .B(n21), .Y(n754) );
NAND2X1TS U832 ( .A(n174), .B(n754), .Y(n175) );
XNOR2X2TS U833 ( .A(n822), .B(n175), .Y(n1030) );
CLKBUFX2TS U834 ( .A(n21), .Y(n1028) );
CLKBUFX2TS U835 ( .A(Data_B_i[7]), .Y(n1027) );
AOI222XLTS U836 ( .A0(n146), .A1(n1028), .B0(n176), .B1(n1027), .C0(n42),
.C1(n1225), .Y(n177) );
AOI222XLTS U837 ( .A0(n1182), .A1(n1033), .B0(n1111), .B1(n1032), .C0(n1142),
.C1(n15), .Y(n179) );
NOR2X1TS U838 ( .A(n185), .B(n184), .Y(n1332) );
NAND2X1TS U839 ( .A(n185), .B(n184), .Y(n1333) );
CMPR32X2TS U840 ( .A(n188), .B(n187), .C(n186), .CO(n189), .S(n185) );
NAND2X1TS U841 ( .A(mult_x_1_n869), .B(n189), .Y(n961) );
AOI21X2TS U842 ( .A0(n962), .A1(n63), .B0(n190), .Y(n583) );
NAND2X1TS U843 ( .A(mult_x_1_n864), .B(mult_x_1_n868), .Y(n582) );
NAND2X1TS U844 ( .A(mult_x_1_n859), .B(mult_x_1_n863), .Y(n1328) );
NAND2X1TS U845 ( .A(mult_x_1_n852), .B(mult_x_1_n858), .Y(n1322) );
NAND2X1TS U846 ( .A(mult_x_1_n845), .B(mult_x_1_n851), .Y(n578) );
AOI21X2TS U847 ( .A0(n195), .A1(n576), .B0(n194), .Y(n573) );
OR2X4TS U848 ( .A(mult_x_1_n830), .B(mult_x_1_n837), .Y(n1307) );
NAND2X1TS U849 ( .A(n1307), .B(n64), .Y(n198) );
NAND2X1TS U850 ( .A(mult_x_1_n838), .B(mult_x_1_n844), .Y(n574) );
NAND2X1TS U851 ( .A(mult_x_1_n830), .B(mult_x_1_n837), .Y(n1306) );
AOI21X1TS U852 ( .A0(n1307), .A1(n1304), .B0(n196), .Y(n197) );
OAI21X2TS U853 ( .A0(n573), .A1(n198), .B0(n197), .Y(n967) );
NOR2X1TS U854 ( .A(mult_x_1_n822), .B(mult_x_1_n829), .Y(n199) );
INVX2TS U855 ( .A(n199), .Y(n965) );
NAND2X1TS U856 ( .A(mult_x_1_n822), .B(mult_x_1_n829), .Y(n964) );
INVX2TS U857 ( .A(n964), .Y(n200) );
OR2X4TS U858 ( .A(mult_x_1_n804), .B(mult_x_1_n813), .Y(n1263) );
NAND2X2TS U859 ( .A(n1263), .B(n65), .Y(n203) );
INVX2TS U860 ( .A(n571), .Y(n1260) );
NAND2X1TS U861 ( .A(mult_x_1_n804), .B(mult_x_1_n813), .Y(n1262) );
OAI21X2TS U862 ( .A0(n570), .A1(n203), .B0(n202), .Y(n564) );
NOR2X1TS U863 ( .A(mult_x_1_n784), .B(mult_x_1_n793), .Y(n565) );
NOR2X1TS U864 ( .A(n565), .B(n1255), .Y(n205) );
NAND2X1TS U865 ( .A(mult_x_1_n794), .B(mult_x_1_n803), .Y(n1256) );
NAND2X1TS U866 ( .A(mult_x_1_n784), .B(mult_x_1_n793), .Y(n566) );
AOI21X4TS U867 ( .A0(n564), .A1(n205), .B0(n204), .Y(n561) );
NOR2X2TS U868 ( .A(mult_x_1_n751), .B(mult_x_1_n761), .Y(n1196) );
NAND2X1TS U869 ( .A(n207), .B(n1192), .Y(n209) );
NAND2X1TS U870 ( .A(mult_x_1_n751), .B(mult_x_1_n761), .Y(n1195) );
NAND2X1TS U871 ( .A(mult_x_1_n740), .B(mult_x_1_n750), .Y(n1201) );
OAI21X1TS U872 ( .A0(n1200), .A1(n1195), .B0(n1201), .Y(n206) );
OAI21X2TS U873 ( .A0(n561), .A1(n209), .B0(n208), .Y(n501) );
NAND2X2TS U874 ( .A(mult_x_1_n729), .B(mult_x_1_n739), .Y(n1186) );
NAND2X1TS U875 ( .A(mult_x_1_n718), .B(mult_x_1_n728), .Y(n557) );
OAI21X2TS U876 ( .A0(n556), .A1(n1186), .B0(n557), .Y(n549) );
NAND2X1TS U877 ( .A(mult_x_1_n707), .B(mult_x_1_n717), .Y(n552) );
NAND2X1TS U878 ( .A(mult_x_1_n696), .B(mult_x_1_n706), .Y(n544) );
OAI21X1TS U879 ( .A0(n543), .A1(n552), .B0(n544), .Y(n210) );
AOI21X2TS U880 ( .A0(n549), .A1(n211), .B0(n210), .Y(n532) );
NAND2X1TS U881 ( .A(mult_x_1_n685), .B(mult_x_1_n695), .Y(n535) );
NAND2X1TS U882 ( .A(mult_x_1_n675), .B(mult_x_1_n684), .Y(n528) );
OAI21X1TS U883 ( .A0(n527), .A1(n535), .B0(n528), .Y(n512) );
NAND2X1TS U884 ( .A(mult_x_1_n665), .B(mult_x_1_n674), .Y(n517) );
NAND2X1TS U885 ( .A(mult_x_1_n656), .B(mult_x_1_n664), .Y(n508) );
OAI21X1TS U886 ( .A0(n507), .A1(n517), .B0(n508), .Y(n212) );
OAI21X2TS U887 ( .A0(n532), .A1(n215), .B0(n214), .Y(n216) );
OAI2BB1X4TS U888 ( .A0N(n218), .A1N(n501), .B0(n217), .Y(n219) );
NOR2X1TS U889 ( .A(mult_x_1_n647), .B(mult_x_1_n655), .Y(n1040) );
NOR2X2TS U890 ( .A(mult_x_1_n638), .B(mult_x_1_n646), .Y(n417) );
NOR2X1TS U891 ( .A(n1040), .B(n417), .Y(n410) );
OR2X2TS U892 ( .A(mult_x_1_n623), .B(mult_x_1_n629), .Y(n497) );
NOR2X1TS U893 ( .A(mult_x_1_n622), .B(mult_x_1_n616), .Y(n220) );
INVX2TS U894 ( .A(n220), .Y(n447) );
NAND2X2TS U895 ( .A(n410), .B(n225), .Y(n487) );
NAND2X2TS U896 ( .A(n489), .B(n69), .Y(n361) );
NOR2X1TS U897 ( .A(n487), .B(n361), .Y(n401) );
NOR2X1TS U898 ( .A(mult_x_1_n585), .B(mult_x_1_n588), .Y(n346) );
NAND2X1TS U899 ( .A(n348), .B(n228), .Y(n230) );
NOR2X1TS U900 ( .A(n405), .B(n230), .Y(n360) );
NAND2X1TS U901 ( .A(n401), .B(n360), .Y(n232) );
NAND2X2TS U902 ( .A(mult_x_1_n647), .B(mult_x_1_n655), .Y(n1041) );
NAND2X1TS U903 ( .A(mult_x_1_n638), .B(mult_x_1_n646), .Y(n418) );
NAND2X1TS U904 ( .A(mult_x_1_n630), .B(mult_x_1_n637), .Y(n440) );
NAND2X1TS U905 ( .A(mult_x_1_n623), .B(mult_x_1_n629), .Y(n496) );
NAND2X1TS U906 ( .A(mult_x_1_n622), .B(mult_x_1_n616), .Y(n446) );
AOI21X1TS U907 ( .A0(n443), .A1(n447), .B0(n221), .Y(n222) );
OAI21X1TS U908 ( .A0(n223), .A1(n440), .B0(n222), .Y(n224) );
NAND2X1TS U909 ( .A(mult_x_1_n610), .B(mult_x_1_n615), .Y(n488) );
INVX2TS U910 ( .A(n488), .Y(n433) );
NAND2X1TS U911 ( .A(mult_x_1_n604), .B(mult_x_1_n609), .Y(n437) );
OAI21X1TS U912 ( .A0(n486), .A1(n361), .B0(n368), .Y(n402) );
NAND2X1TS U913 ( .A(mult_x_1_n603), .B(mult_x_1_n598), .Y(n406) );
NAND2X1TS U914 ( .A(mult_x_1_n593), .B(mult_x_1_n597), .Y(n422) );
NAND2X1TS U915 ( .A(mult_x_1_n592), .B(mult_x_1_n589), .Y(n429) );
NAND2X1TS U916 ( .A(mult_x_1_n585), .B(mult_x_1_n588), .Y(n482) );
NAND2X1TS U917 ( .A(mult_x_1_n582), .B(mult_x_1_n584), .Y(n356) );
AOI21X1TS U918 ( .A0(n347), .A1(n228), .B0(n227), .Y(n229) );
AOI21X1TS U919 ( .A0(n402), .A1(n360), .B0(n365), .Y(n231) );
OAI21X1TS U920 ( .A0(n1044), .A1(n232), .B0(n231), .Y(n257) );
INVX2TS U921 ( .A(n470), .Y(n467) );
NOR2X1TS U922 ( .A(n755), .B(n756), .Y(n818) );
BUFX3TS U923 ( .A(Data_B_i[10]), .Y(n1080) );
NOR2X1TS U924 ( .A(n23), .B(n1080), .Y(n785) );
NOR2X1TS U925 ( .A(n785), .B(n789), .Y(n235) );
NAND2X1TS U926 ( .A(n818), .B(n235), .Y(n622) );
NOR2X1TS U927 ( .A(n28), .B(Data_B_i[13]), .Y(n612) );
NOR2X1TS U928 ( .A(n27), .B(n25), .Y(n608) );
NAND2X1TS U929 ( .A(n702), .B(n237), .Y(n239) );
NOR2X2TS U930 ( .A(n622), .B(n239), .Y(n242) );
NAND2X1TS U931 ( .A(Data_B_i[9]), .B(n21), .Y(n757) );
NAND2X1TS U932 ( .A(n757), .B(n754), .Y(n819) );
NAND2X1TS U933 ( .A(n1080), .B(Data_B_i[11]), .Y(n790) );
NAND2X1TS U934 ( .A(Data_B_i[9]), .B(n1080), .Y(n823) );
NAND2X1TS U935 ( .A(n790), .B(n823), .Y(n234) );
AOI21X2TS U936 ( .A0(n235), .A1(n819), .B0(n234), .Y(n621) );
NAND2X1TS U937 ( .A(n28), .B(n30), .Y(n613) );
NAND2X1TS U938 ( .A(n27), .B(n25), .Y(n623) );
NAND2X1TS U939 ( .A(n613), .B(n623), .Y(n700) );
NAND2X1TS U940 ( .A(n1108), .B(n33), .Y(n693) );
NAND2X1TS U941 ( .A(Data_B_i[13]), .B(n32), .Y(n706) );
NAND2X1TS U942 ( .A(n693), .B(n706), .Y(n236) );
OAI21X2TS U943 ( .A0(n621), .A1(n239), .B0(n238), .Y(n240) );
AOI21X4TS U944 ( .A0(n242), .A1(n241), .B0(n240), .Y(n735) );
NOR2X1TS U945 ( .A(n1273), .B(Data_B_i[17]), .Y(n652) );
NAND2X1TS U946 ( .A(n663), .B(n244), .Y(n646) );
NOR2X1TS U947 ( .A(n647), .B(n736), .Y(n300) );
NOR2X1TS U948 ( .A(n1294), .B(n1232), .Y(n303) );
NAND2X1TS U949 ( .A(n300), .B(n246), .Y(n248) );
NOR2X1TS U950 ( .A(n646), .B(n248), .Y(n372) );
NAND2X1TS U951 ( .A(n1073), .B(n35), .Y(n674) );
NAND2X1TS U952 ( .A(n1108), .B(n1073), .Y(n681) );
NAND2X1TS U953 ( .A(n674), .B(n681), .Y(n664) );
NAND2X1TS U954 ( .A(n1273), .B(n1280), .Y(n657) );
NAND2X1TS U955 ( .A(n1273), .B(Data_B_i[17]), .Y(n667) );
NAND2X1TS U956 ( .A(n657), .B(n667), .Y(n243) );
AOI21X1TS U957 ( .A0(n244), .A1(n664), .B0(n243), .Y(n645) );
NAND2X1TS U958 ( .A(n1294), .B(n1310), .Y(n737) );
NAND2X1TS U959 ( .A(n1280), .B(n1310), .Y(n729) );
NAND2X1TS U960 ( .A(n737), .B(n729), .Y(n299) );
NAND2X1TS U961 ( .A(Data_B_i[23]), .B(n1314), .Y(n281) );
NAND2X1TS U962 ( .A(n1294), .B(n1314), .Y(n304) );
NAND2X1TS U963 ( .A(n281), .B(n304), .Y(n245) );
AOI21X1TS U964 ( .A0(n246), .A1(n299), .B0(n245), .Y(n247) );
OAI21X1TS U965 ( .A0(n248), .A1(n645), .B0(n247), .Y(n373) );
OAI21X1TS U966 ( .A0(n735), .A1(n250), .B0(n249), .Y(n251) );
INVX2TS U967 ( .A(Data_B_i[23]), .Y(n469) );
XOR2X1TS U968 ( .A(Data_A_i[23]), .B(Data_A_i[22]), .Y(n287) );
NAND2BX2TS U969 ( .AN(n288), .B(n287), .Y(n719) );
BUFX3TS U970 ( .A(n719), .Y(n1317) );
XNOR2X1TS U971 ( .A(Data_A_i[21]), .B(Data_A_i[22]), .Y(n252) );
AND3X2TS U972 ( .A(n287), .B(n288), .C(n252), .Y(n1311) );
NOR2BX1TS U973 ( .AN(n288), .B(n252), .Y(n1248) );
CLKBUFX2TS U974 ( .A(n1248), .Y(n1313) );
INVX2TS U975 ( .A(n469), .Y(n1298) );
AOI21X1TS U976 ( .A0(n1311), .A1(n1232), .B0(n253), .Y(n254) );
NAND2X1TS U977 ( .A(mult_x_1_n581), .B(n256), .Y(n362) );
XNOR2X4TS U978 ( .A(Data_A_i[11]), .B(Data_A_i[12]), .Y(n309) );
BUFX3TS U979 ( .A(n1151), .Y(n1162) );
NOR2X1TS U980 ( .A(n308), .B(n309), .Y(n385) );
XNOR2X2TS U981 ( .A(n10), .B(Data_A_i[9]), .Y(n260) );
XOR2X1TS U982 ( .A(Data_A_i[11]), .B(Data_A_i[10]), .Y(n261) );
NAND2BX2TS U983 ( .AN(n260), .B(n261), .Y(n861) );
CLKBUFX2TS U984 ( .A(n267), .Y(n1242) );
XNOR2X1TS U985 ( .A(Data_A_i[9]), .B(Data_A_i[10]), .Y(n259) );
NOR2BX1TS U986 ( .AN(n260), .B(n259), .Y(n862) );
CLKBUFX2TS U987 ( .A(n862), .Y(n1240) );
AOI222X1TS U988 ( .A0(n1242), .A1(n1011), .B0(n1240), .B1(n999), .C0(n1088),
.C1(n998), .Y(n262) );
INVX2TS U989 ( .A(Data_A_i[11]), .Y(n263) );
AOI222X1TS U990 ( .A0(n1242), .A1(n999), .B0(n1240), .B1(n386), .C0(n12),
.C1(Data_B_i[0]), .Y(n265) );
XOR2X1TS U991 ( .A(n266), .B(n1245), .Y(n456) );
CLKBUFX2TS U992 ( .A(n862), .Y(n1230) );
AOI22X1TS U993 ( .A0(n1230), .A1(n389), .B0(n38), .B1(n998), .Y(n268) );
XOR2X1TS U994 ( .A(n269), .B(n1245), .Y(n323) );
OAI21X1TS U995 ( .A0(n1235), .A1(n7), .B0(n50), .Y(n270) );
XOR2X1TS U996 ( .A(n270), .B(n1245), .Y(n974) );
NOR2X1TS U997 ( .A(n274), .B(n303), .Y(n277) );
INVX2TS U998 ( .A(n646), .Y(n728) );
NAND2X1TS U999 ( .A(n277), .B(n728), .Y(n279) );
INVX2TS U1000 ( .A(n645), .Y(n732) );
AOI21X1TS U1001 ( .A0(n732), .A1(n277), .B0(n276), .Y(n278) );
OAI21X1TS U1002 ( .A0(n735), .A1(n279), .B0(n278), .Y(n284) );
NAND2X1TS U1003 ( .A(n282), .B(n281), .Y(n283) );
CLKBUFX2TS U1004 ( .A(Data_B_i[22]), .Y(n1296) );
CLKBUFX2TS U1005 ( .A(n12), .Y(n1233) );
AOI222XLTS U1006 ( .A0(n1242), .A1(n1298), .B0(n1240), .B1(n1296), .C0(n1233), .C1(n1294), .Y(n285) );
NAND2X1TS U1007 ( .A(n717), .B(n8), .Y(n290) );
OAI21X1TS U1008 ( .A0(n1317), .A1(n7), .B0(n290), .Y(n291) );
CLKBUFX2TS U1009 ( .A(n717), .Y(n1250) );
CLKBUFX2TS U1010 ( .A(n1248), .Y(n1290) );
CLKBUFX2TS U1011 ( .A(n1311), .Y(n986) );
XOR2X1TS U1012 ( .A(Data_A_i[17]), .B(Data_A_i[16]), .Y(n296) );
CLKBUFX2TS U1013 ( .A(n1286), .Y(n1046) );
XNOR2X1TS U1014 ( .A(Data_A_i[15]), .B(Data_A_i[16]), .Y(n294) );
CLKBUFX2TS U1015 ( .A(n1224), .Y(n1045) );
AND3X2TS U1016 ( .A(n296), .B(n295), .C(n294), .Y(n1295) );
CLKBUFX2TS U1017 ( .A(n1295), .Y(n1266) );
AOI222XLTS U1018 ( .A0(n1046), .A1(n1169), .B0(n1045), .B1(n1241), .C0(n1266), .C1(n17), .Y(n297) );
NAND2X1TS U1019 ( .A(n728), .B(n300), .Y(n302) );
AOI21X1TS U1020 ( .A0(n732), .A1(n300), .B0(n299), .Y(n301) );
OAI21X1TS U1021 ( .A0(n735), .A1(n302), .B0(n301), .Y(n307) );
NAND2X1TS U1022 ( .A(n305), .B(n304), .Y(n306) );
XOR2X2TS U1023 ( .A(n307), .B(n306), .Y(n1318) );
CLKBUFX2TS U1024 ( .A(n385), .Y(n1119) );
XNOR2X1TS U1025 ( .A(Data_A_i[12]), .B(Data_A_i[13]), .Y(n310) );
NOR2BX1TS U1026 ( .AN(n309), .B(n310), .Y(n1158) );
CLKBUFX2TS U1027 ( .A(Data_B_i[21]), .Y(n1312) );
AND3X2TS U1028 ( .A(n310), .B(n309), .C(n308), .Y(n1148) );
CLKBUFX2TS U1029 ( .A(n1148), .Y(n1160) );
CLKBUFX2TS U1030 ( .A(Data_B_i[20]), .Y(n1276) );
AOI222XLTS U1031 ( .A0(n1119), .A1(n1314), .B0(n1158), .B1(n1312), .C0(n1160), .C1(n1276), .Y(n311) );
XOR2X1TS U1032 ( .A(Data_A_i[20]), .B(Data_A_i[19]), .Y(n318) );
BUFX3TS U1033 ( .A(n1053), .Y(n1131) );
NOR2X1TS U1034 ( .A(n318), .B(n317), .Y(n743) );
OAI21X1TS U1035 ( .A0(n1131), .A1(n7), .B0(n68), .Y(n313) );
XOR2X1TS U1036 ( .A(n313), .B(n1140), .Y(n997) );
XNOR2X1TS U1037 ( .A(Data_A_i[18]), .B(Data_A_i[19]), .Y(n316) );
CLKBUFX2TS U1038 ( .A(n1051), .Y(n1128) );
CLKBUFX2TS U1039 ( .A(n743), .Y(n1137) );
CLKBUFX2TS U1040 ( .A(n1051), .Y(n1136) );
AND3X2TS U1041 ( .A(n318), .B(n317), .C(n316), .Y(n1134) );
CMPR22X2TS U1042 ( .A(n323), .B(n322), .CO(n455), .S(mult_x_1_n866) );
BUFX3TS U1043 ( .A(n326), .Y(n1269) );
OAI21X1TS U1044 ( .A0(n390), .A1(n1269), .B0(n54), .Y(n325) );
INVX2TS U1045 ( .A(Data_A_i[17]), .Y(n324) );
XOR2X1TS U1046 ( .A(n325), .B(n1271), .Y(n384) );
XOR2X1TS U1047 ( .A(n327), .B(n1271), .Y(n643) );
CLKBUFX2TS U1048 ( .A(n1286), .Y(n1299) );
AOI222X1TS U1049 ( .A0(n1299), .A1(n900), .B0(n1045), .B1(n386), .C0(n1266),
.C1(n389), .Y(n328) );
XOR2X1TS U1050 ( .A(n329), .B(n1271), .Y(n1003) );
XOR2X1TS U1051 ( .A(n1005), .B(n1003), .Y(mult_x_1_n819) );
INVX2TS U1052 ( .A(n233), .Y(n985) );
AOI222X1TS U1053 ( .A0(n1250), .A1(n1000), .B0(n1290), .B1(n999), .C0(n986),
.C1(n386), .Y(n330) );
XOR2X1TS U1054 ( .A(n331), .B(n1292), .Y(n336) );
INVX2TS U1055 ( .A(n332), .Y(n333) );
ADDFHX2TS U1056 ( .A(n337), .B(n336), .CI(n335), .CO(mult_x_1_n747), .S(
mult_x_1_n748) );
NOR2X1TS U1057 ( .A(n487), .B(n339), .Y(n421) );
OAI21X1TS U1058 ( .A0(n486), .A1(n339), .B0(n338), .Y(n425) );
OAI21X1TS U1059 ( .A0(n1044), .A1(n341), .B0(n340), .Y(n344) );
INVX2TS U1060 ( .A(n342), .Y(n424) );
NAND2X1TS U1061 ( .A(n424), .B(n422), .Y(n343) );
XNOR2X1TS U1062 ( .A(n344), .B(n343), .Y(N41) );
NAND2X1TS U1063 ( .A(n345), .B(n348), .Y(n351) );
NOR2X1TS U1064 ( .A(n487), .B(n351), .Y(n478) );
INVX2TS U1065 ( .A(n346), .Y(n483) );
NAND2X1TS U1066 ( .A(n478), .B(n483), .Y(n354) );
AOI21X1TS U1067 ( .A0(n349), .A1(n348), .B0(n347), .Y(n350) );
OAI21X1TS U1068 ( .A0(n486), .A1(n351), .B0(n350), .Y(n479) );
AOI21X1TS U1069 ( .A0(n479), .A1(n483), .B0(n352), .Y(n353) );
OAI21X1TS U1070 ( .A0(n1044), .A1(n354), .B0(n353), .Y(n359) );
NAND2X1TS U1071 ( .A(n357), .B(n356), .Y(n358) );
NAND2X1TS U1072 ( .A(n360), .B(n364), .Y(n367) );
NOR2X1TS U1073 ( .A(n361), .B(n367), .Y(n457) );
NAND2X1TS U1074 ( .A(n432), .B(n457), .Y(n370) );
AOI21X1TS U1075 ( .A0(n365), .A1(n364), .B0(n363), .Y(n366) );
OAI21X1TS U1076 ( .A0(n368), .A1(n367), .B0(n366), .Y(n461) );
AOI21X1TS U1077 ( .A0(n434), .A1(n457), .B0(n461), .Y(n369) );
OAI21X1TS U1078 ( .A0(n1044), .A1(n370), .B0(n369), .Y(n382) );
CMPR32X2TS U1079 ( .A(n467), .B(mult_x_1_n580), .C(n371), .CO(n380), .S(n256) );
NAND2X1TS U1080 ( .A(n372), .B(n1298), .Y(n375) );
NAND2X1TS U1081 ( .A(n373), .B(Data_B_i[23]), .Y(n374) );
OAI21X1TS U1082 ( .A0(n735), .A1(n375), .B0(n374), .Y(n376) );
INVX2TS U1083 ( .A(n376), .Y(n1178) );
NAND2X1TS U1084 ( .A(n1311), .B(Data_B_i[23]), .Y(n377) );
NAND2X1TS U1085 ( .A(n380), .B(n379), .Y(n458) );
NAND2X1TS U1086 ( .A(n460), .B(n458), .Y(n381) );
XNOR2X1TS U1087 ( .A(n382), .B(n381), .Y(N46) );
ADDHXLTS U1088 ( .A(n384), .B(n383), .CO(n1005), .S(mult_x_1_n827) );
CLKBUFX2TS U1089 ( .A(n385), .Y(n1124) );
CLKBUFX2TS U1090 ( .A(n1158), .Y(n989) );
CLKBUFX2TS U1091 ( .A(n1148), .Y(n1026) );
AOI222X1TS U1092 ( .A0(n1124), .A1(n900), .B0(n989), .B1(n386), .C0(n1026),
.C1(Data_B_i[0]), .Y(n387) );
CLKBUFX2TS U1093 ( .A(n1158), .Y(n1149) );
ADDHXLTS U1094 ( .A(Data_A_i[14]), .B(n392), .CO(n978), .S(n273) );
AOI222XLTS U1095 ( .A0(n40), .A1(n1028), .B0(n393), .B1(n1027), .C0(n903),
.C1(n1225), .Y(n394) );
OAI21XLTS U1096 ( .A0(n1030), .A1(n1173), .B0(n394), .Y(n395) );
AOI222XLTS U1097 ( .A0(n1242), .A1(n1239), .B0(n1240), .B1(n1032), .C0(n12),
.C1(Data_B_i[3]), .Y(n396) );
OAI21X1TS U1098 ( .A0(n1044), .A1(n404), .B0(n403), .Y(n409) );
NAND2X1TS U1099 ( .A(n407), .B(n406), .Y(n408) );
XNOR2X1TS U1100 ( .A(n409), .B(n408), .Y(N40) );
OAI21X1TS U1101 ( .A0(n1044), .A1(n439), .B0(n442), .Y(n414) );
NAND2X1TS U1102 ( .A(n412), .B(n440), .Y(n413) );
XNOR2X1TS U1103 ( .A(n414), .B(n413), .Y(N35) );
OAI21X1TS U1104 ( .A0(n6), .A1(n1040), .B0(n1041), .Y(n420) );
XOR2XLTS U1105 ( .A(n420), .B(n46), .Y(N34) );
NAND2X1TS U1106 ( .A(n421), .B(n424), .Y(n427) );
AOI21X1TS U1107 ( .A0(n425), .A1(n424), .B0(n423), .Y(n426) );
OAI21X1TS U1108 ( .A0(n6), .A1(n427), .B0(n426), .Y(n431) );
XOR2XLTS U1109 ( .A(n431), .B(n49), .Y(N42) );
NAND2X1TS U1110 ( .A(n432), .B(n489), .Y(n436) );
AOI21X1TS U1111 ( .A0(n434), .A1(n489), .B0(n433), .Y(n435) );
OAI21X1TS U1112 ( .A0(n6), .A1(n436), .B0(n435), .Y(n438) );
XOR2XLTS U1113 ( .A(n438), .B(n48), .Y(N39) );
NOR2X1TS U1114 ( .A(n439), .B(n441), .Y(n492) );
NAND2X1TS U1115 ( .A(n492), .B(n497), .Y(n445) );
AOI21X1TS U1116 ( .A0(n493), .A1(n497), .B0(n443), .Y(n444) );
XOR2XLTS U1117 ( .A(n448), .B(n47), .Y(N37) );
AOI222XLTS U1118 ( .A0(n1250), .A1(n1225), .B0(n1290), .B1(n1239), .C0(n986),
.C1(Data_B_i[4]), .Y(n449) );
ADDHX1TS U1119 ( .A(n454), .B(n453), .CO(mult_x_1_n841), .S(n400) );
CMPR22X2TS U1120 ( .A(n456), .B(n455), .CO(n271), .S(mult_x_1_n861) );
NAND2X1TS U1121 ( .A(n457), .B(n460), .Y(n463) );
AOI21X1TS U1122 ( .A0(n461), .A1(n460), .B0(n459), .Y(n462) );
OA21XLTS U1123 ( .A0(n486), .A1(n463), .B0(n462), .Y(n464) );
CMPR32X2TS U1124 ( .A(n468), .B(n467), .C(n466), .CO(n473), .S(n379) );
INVX2TS U1125 ( .A(n469), .Y(n1229) );
NAND2X1TS U1126 ( .A(n473), .B(n472), .Y(n474) );
NAND2X1TS U1127 ( .A(n475), .B(n474), .Y(n476) );
NAND2X1TS U1128 ( .A(n483), .B(n482), .Y(n484) );
XNOR2X1TS U1129 ( .A(n485), .B(n484), .Y(N43) );
NAND2X1TS U1130 ( .A(n489), .B(n488), .Y(n490) );
XNOR2X1TS U1131 ( .A(n491), .B(n490), .Y(N38) );
OAI21X1TS U1132 ( .A0(n6), .A1(n495), .B0(n494), .Y(n499) );
NAND2X1TS U1133 ( .A(n497), .B(n496), .Y(n498) );
CLKINVX1TS U1134 ( .A(n513), .Y(n500) );
NOR2X1TS U1135 ( .A(n500), .B(n516), .Y(n504) );
NAND2X1TS U1136 ( .A(n504), .B(n522), .Y(n506) );
CLKINVX1TS U1137 ( .A(n512), .Y(n502) );
AOI21X1TS U1138 ( .A0(n504), .A1(n524), .B0(n503), .Y(n505) );
NAND2X1TS U1139 ( .A(n509), .B(n508), .Y(n510) );
XNOR2X1TS U1140 ( .A(n511), .B(n510), .Y(N32) );
NAND2X1TS U1141 ( .A(n522), .B(n513), .Y(n515) );
AOI21X1TS U1142 ( .A0(n524), .A1(n513), .B0(n512), .Y(n514) );
NAND2X1TS U1143 ( .A(n518), .B(n517), .Y(n519) );
XNOR2X1TS U1144 ( .A(n520), .B(n519), .Y(N31) );
INVX2TS U1145 ( .A(n521), .Y(n536) );
NAND2X1TS U1146 ( .A(n522), .B(n536), .Y(n526) );
CLKINVX1TS U1147 ( .A(n535), .Y(n523) );
AOI21X1TS U1148 ( .A0(n524), .A1(n536), .B0(n523), .Y(n525) );
OAI21X1TS U1149 ( .A0(n3), .A1(n526), .B0(n525), .Y(n531) );
CLKINVX1TS U1150 ( .A(n527), .Y(n529) );
NAND2X1TS U1151 ( .A(n529), .B(n528), .Y(n530) );
XNOR2X1TS U1152 ( .A(n531), .B(n530), .Y(N30) );
CLKBUFX2TS U1153 ( .A(n532), .Y(n533) );
NAND2X1TS U1154 ( .A(n536), .B(n535), .Y(n537) );
XNOR2X1TS U1155 ( .A(n538), .B(n537), .Y(N29) );
INVX2TS U1156 ( .A(n539), .Y(n553) );
NAND2X1TS U1157 ( .A(n548), .B(n553), .Y(n542) );
AOI21X1TS U1158 ( .A0(n553), .A1(n549), .B0(n540), .Y(n541) );
NAND2X1TS U1159 ( .A(n545), .B(n544), .Y(n546) );
XNOR2X1TS U1160 ( .A(n547), .B(n546), .Y(N28) );
NAND2X1TS U1161 ( .A(n553), .B(n552), .Y(n554) );
XNOR2X1TS U1162 ( .A(n555), .B(n554), .Y(N27) );
CLKINVX1TS U1163 ( .A(n556), .Y(n558) );
NAND2X1TS U1164 ( .A(n558), .B(n557), .Y(n559) );
XNOR2X1TS U1165 ( .A(n560), .B(n559), .Y(N26) );
INVX2TS U1166 ( .A(n561), .Y(n1208) );
NAND2X1TS U1167 ( .A(n1207), .B(n1205), .Y(n563) );
XNOR2X1TS U1168 ( .A(n1208), .B(n563), .Y(N21) );
NAND2X1TS U1169 ( .A(n567), .B(n566), .Y(n568) );
XNOR2X1TS U1170 ( .A(n569), .B(n568), .Y(N20) );
NAND2X1TS U1171 ( .A(n65), .B(n571), .Y(n572) );
XNOR2X1TS U1172 ( .A(n1261), .B(n572), .Y(N17) );
NAND2X1TS U1173 ( .A(n64), .B(n574), .Y(n575) );
XNOR2X1TS U1174 ( .A(n1305), .B(n575), .Y(N14) );
INVX2TS U1175 ( .A(n576), .Y(n1325) );
NAND2X1TS U1176 ( .A(n579), .B(n578), .Y(n580) );
XNOR2X1TS U1177 ( .A(n581), .B(n580), .Y(N13) );
NAND2X1TS U1178 ( .A(n62), .B(n582), .Y(n584) );
INVX2TS U1179 ( .A(n583), .Y(n1327) );
XNOR2X1TS U1180 ( .A(n584), .B(n1327), .Y(N10) );
NAND2X1TS U1181 ( .A(n586), .B(n585), .Y(n588) );
XNOR2X1TS U1182 ( .A(n588), .B(n587), .Y(N5) );
NAND2X1TS U1183 ( .A(n1344), .B(n589), .Y(n591) );
INVX2TS U1184 ( .A(n590), .Y(n1345) );
XNOR2X1TS U1185 ( .A(n591), .B(n1345), .Y(N3) );
XNOR2X1TS U1186 ( .A(n594), .B(n593), .Y(N2) );
CMPR32X2TS U1187 ( .A(n324), .B(n596), .C(n595), .CO(mult_x_1_n594), .S(
mult_x_1_n595) );
INVX2TS U1188 ( .A(n596), .Y(n605) );
NAND2X1TS U1189 ( .A(n1295), .B(Data_B_i[23]), .Y(n597) );
OAI21X1TS U1190 ( .A0(n1178), .A1(n1269), .B0(n597), .Y(n598) );
XOR2X1TS U1191 ( .A(n598), .B(Data_A_i[17]), .Y(n599) );
CMPR32X2TS U1192 ( .A(n600), .B(n605), .C(n599), .CO(mult_x_1_n599), .S(
mult_x_1_n600) );
CLKBUFX2TS U1193 ( .A(n1224), .Y(n1297) );
AOI21X1TS U1194 ( .A0(n1295), .A1(n1232), .B0(n601), .Y(n602) );
XOR2X1TS U1195 ( .A(n603), .B(n1302), .Y(n604) );
CMPR32X2TS U1196 ( .A(n605), .B(mult_x_1_n611), .C(n604), .CO(mult_x_1_n605),
.S(mult_x_1_n606) );
CMPR32X2TS U1197 ( .A(n263), .B(n607), .C(n606), .CO(mult_x_1_n634), .S(
mult_x_1_n635) );
INVX2TS U1198 ( .A(n607), .Y(n630) );
INVX2TS U1199 ( .A(n622), .Y(n699) );
INVX2TS U1200 ( .A(n608), .Y(n624) );
NAND2X1TS U1201 ( .A(n699), .B(n624), .Y(n611) );
INVX2TS U1202 ( .A(n621), .Y(n701) );
OAI21X1TS U1203 ( .A0(n822), .A1(n611), .B0(n610), .Y(n616) );
NAND2X1TS U1204 ( .A(n614), .B(n613), .Y(n615) );
CLKBUFX2TS U1205 ( .A(n717), .Y(n1315) );
CLKBUFX2TS U1206 ( .A(n1135), .Y(n1016) );
CLKBUFX2TS U1207 ( .A(n1311), .Y(n1289) );
AOI222XLTS U1208 ( .A0(n1315), .A1(n1016), .B0(n1290), .B1(Data_B_i[12]),
.C0(n1289), .C1(Data_B_i[11]), .Y(n617) );
CMPR32X2TS U1209 ( .A(n620), .B(n630), .C(n619), .CO(mult_x_1_n642), .S(
mult_x_1_n643) );
OAI21X1TS U1210 ( .A0(n822), .A1(n622), .B0(n621), .Y(n626) );
NAND2X1TS U1211 ( .A(n624), .B(n623), .Y(n625) );
CLKBUFX2TS U1212 ( .A(n25), .Y(n1123) );
AOI222XLTS U1213 ( .A0(n717), .A1(n27), .B0(n1313), .B1(n1123), .C0(n1289),
.C1(n1080), .Y(n627) );
CMPR32X2TS U1214 ( .A(n630), .B(mult_x_1_n660), .C(n629), .CO(mult_x_1_n651),
.S(mult_x_1_n652) );
CMPR32X2TS U1215 ( .A(n633), .B(n632), .C(n631), .CO(mult_x_1_n692), .S(
mult_x_1_n693) );
CLKBUFX2TS U1216 ( .A(n1295), .Y(n1274) );
AOI222XLTS U1217 ( .A0(n1299), .A1(n1016), .B0(n1045), .B1(n28), .C0(n1274),
.C1(n25), .Y(n634) );
OAI21X1TS U1218 ( .A0(n1018), .A1(n1269), .B0(n634), .Y(n635) );
XOR2X1TS U1219 ( .A(n635), .B(n1271), .Y(n636) );
CMPR32X2TS U1220 ( .A(Data_A_i[2]), .B(n637), .C(n636), .CO(mult_x_1_n703),
.S(mult_x_1_n704) );
CLKBUFX2TS U1221 ( .A(n743), .Y(n1129) );
AOI222XLTS U1222 ( .A0(n1129), .A1(n1028), .B0(n1051), .B1(n1027), .C0(n1134), .C1(Data_B_i[6]), .Y(n638) );
CMPR32X2TS U1223 ( .A(Data_A_i[2]), .B(n641), .C(n640), .CO(mult_x_1_n725),
.S(mult_x_1_n726) );
ADDHXLTS U1224 ( .A(n644), .B(n642), .CO(n415), .S(mult_x_1_n781) );
ADDHXLTS U1225 ( .A(n1302), .B(n643), .CO(n383), .S(mult_x_1_n835) );
OAI21X1TS U1226 ( .A0(n735), .A1(n646), .B0(n645), .Y(n649) );
INVX2TS U1227 ( .A(n647), .Y(n731) );
NAND2X1TS U1228 ( .A(n731), .B(n729), .Y(n648) );
CLKBUFX2TS U1229 ( .A(Data_B_i[19]), .Y(n1275) );
AOI222XLTS U1230 ( .A0(n1315), .A1(n1276), .B0(n1313), .B1(n1275), .C0(n1289), .C1(n1273), .Y(n650) );
INVX2TS U1231 ( .A(n652), .Y(n668) );
NAND2X1TS U1232 ( .A(n663), .B(n668), .Y(n655) );
AOI21X1TS U1233 ( .A0(n664), .A1(n668), .B0(n653), .Y(n654) );
OAI21X1TS U1234 ( .A0(n735), .A1(n655), .B0(n654), .Y(n660) );
NAND2X1TS U1235 ( .A(n658), .B(n657), .Y(n659) );
XOR2X1TS U1236 ( .A(n660), .B(n659), .Y(n1146) );
CLKBUFX2TS U1237 ( .A(Data_B_i[19]), .Y(n1144) );
CLKBUFX2TS U1238 ( .A(Data_B_i[18]), .Y(n1143) );
AOI222XLTS U1239 ( .A0(n1315), .A1(n1144), .B0(n1313), .B1(n1143), .C0(n986),
.C1(n35), .Y(n661) );
XOR2X1TS U1240 ( .A(n662), .B(n713), .Y(mult_x_1_n1167) );
OAI21X1TS U1241 ( .A0(n735), .A1(n666), .B0(n665), .Y(n670) );
NAND2X1TS U1242 ( .A(n668), .B(n667), .Y(n669) );
CLKBUFX2TS U1243 ( .A(Data_B_i[18]), .Y(n1085) );
CLKBUFX2TS U1244 ( .A(n35), .Y(n1075) );
AOI222XLTS U1245 ( .A0(n1315), .A1(n1085), .B0(n1290), .B1(n1075), .C0(n1311), .C1(n1073), .Y(n671) );
OAI21X1TS U1246 ( .A0(n735), .A1(n680), .B0(n681), .Y(n677) );
NAND2X1TS U1247 ( .A(n675), .B(n674), .Y(n676) );
CLKBUFX2TS U1248 ( .A(n1075), .Y(n1118) );
CLKBUFX2TS U1249 ( .A(Data_B_i[16]), .Y(n1117) );
AOI222XLTS U1250 ( .A0(n1315), .A1(n1118), .B0(n1313), .B1(n1117), .C0(n1289), .C1(n1108), .Y(n678) );
NAND2X1TS U1251 ( .A(n682), .B(n681), .Y(n683) );
CLKBUFX2TS U1252 ( .A(Data_B_i[16]), .Y(n946) );
CLKBUFX2TS U1253 ( .A(Data_B_i[15]), .Y(n968) );
AOI222XLTS U1254 ( .A0(n1315), .A1(n946), .B0(n1313), .B1(n968), .C0(n1289),
.C1(n32), .Y(n684) );
OAI21X1TS U1255 ( .A0(n1), .A1(n1317), .B0(n684), .Y(n685) );
XOR2X1TS U1256 ( .A(n685), .B(n1319), .Y(mult_x_1_n1170) );
NAND2X1TS U1257 ( .A(n689), .B(n699), .Y(n691) );
AOI21X1TS U1258 ( .A0(n701), .A1(n689), .B0(n688), .Y(n690) );
OAI21X1TS U1259 ( .A0(n822), .A1(n691), .B0(n690), .Y(n696) );
NAND2X1TS U1260 ( .A(n694), .B(n693), .Y(n695) );
CLKBUFX2TS U1261 ( .A(Data_B_i[15]), .Y(n1267) );
AOI222XLTS U1262 ( .A0(n717), .A1(n1267), .B0(n1313), .B1(n33), .C0(n986),
.C1(Data_B_i[13]), .Y(n697) );
NAND2X1TS U1263 ( .A(n699), .B(n702), .Y(n704) );
AOI21X1TS U1264 ( .A0(n702), .A1(n701), .B0(n700), .Y(n703) );
OAI21X1TS U1265 ( .A0(n822), .A1(n704), .B0(n703), .Y(n709) );
NAND2X1TS U1266 ( .A(n707), .B(n706), .Y(n708) );
CLKBUFX2TS U1267 ( .A(n30), .Y(n1135) );
AOI222XLTS U1268 ( .A0(n717), .A1(Data_B_i[14]), .B0(n1290), .B1(n1135),
.C0(n986), .C1(n27), .Y(n710) );
XOR2X1TS U1269 ( .A(n711), .B(n1292), .Y(mult_x_1_n1172) );
AOI222XLTS U1270 ( .A0(n1250), .A1(n1028), .B0(n1248), .B1(n1027), .C0(n986),
.C1(Data_B_i[6]), .Y(n712) );
XOR2X1TS U1271 ( .A(n714), .B(n713), .Y(mult_x_1_n1178) );
AOI222XLTS U1272 ( .A0(n1250), .A1(n1169), .B0(n1290), .B1(n1241), .C0(n986),
.C1(Data_B_i[5]), .Y(n715) );
XOR2X1TS U1273 ( .A(n716), .B(n1319), .Y(mult_x_1_n1179) );
AOI222XLTS U1274 ( .A0(n717), .A1(n1033), .B0(n1290), .B1(n1032), .C0(n986),
.C1(Data_B_i[3]), .Y(n718) );
XOR2X1TS U1275 ( .A(n720), .B(n1292), .Y(mult_x_1_n1181) );
CLKBUFX2TS U1276 ( .A(n1134), .Y(n1175) );
AOI21X1TS U1277 ( .A0(n1175), .A1(n1232), .B0(n721), .Y(n722) );
XOR2X1TS U1278 ( .A(n723), .B(n1132), .Y(mult_x_1_n1189) );
AOI222XLTS U1279 ( .A0(n1137), .A1(n1298), .B0(n1136), .B1(n1296), .C0(n1175), .C1(n1294), .Y(n724) );
AOI222XLTS U1280 ( .A0(n1129), .A1(n1314), .B0(n1128), .B1(n1312), .C0(n1175), .C1(n1310), .Y(n726) );
OAI21X1TS U1281 ( .A0(n1318), .A1(n1131), .B0(n726), .Y(n727) );
XOR2X1TS U1282 ( .A(n727), .B(n1132), .Y(mult_x_1_n1191) );
NAND2X1TS U1283 ( .A(n728), .B(n731), .Y(n734) );
AOI21X1TS U1284 ( .A0(n732), .A1(n731), .B0(n730), .Y(n733) );
OAI21X1TS U1285 ( .A0(n735), .A1(n734), .B0(n733), .Y(n740) );
NAND2X1TS U1286 ( .A(n738), .B(n737), .Y(n739) );
CLKBUFX2TS U1287 ( .A(Data_B_i[21]), .Y(n1282) );
CLKBUFX2TS U1288 ( .A(Data_B_i[20]), .Y(n1281) );
AOI222XLTS U1289 ( .A0(n743), .A1(n1282), .B0(n1128), .B1(n1281), .C0(n1175),
.C1(n1280), .Y(n741) );
OAI21X1TS U1290 ( .A0(n1284), .A1(n1131), .B0(n741), .Y(n742) );
AOI222XLTS U1291 ( .A0(n743), .A1(n1144), .B0(n1128), .B1(n1143), .C0(n1134),
.C1(n35), .Y(n744) );
AOI222XLTS U1292 ( .A0(n1129), .A1(n1085), .B0(n1136), .B1(n1075), .C0(n1175), .C1(n1073), .Y(n746) );
AOI222XLTS U1293 ( .A0(n1129), .A1(n946), .B0(n1128), .B1(n968), .C0(n1175),
.C1(n33), .Y(n748) );
OAI21X1TS U1294 ( .A0(n1), .A1(n1131), .B0(n748), .Y(n749) );
XOR2X1TS U1295 ( .A(n749), .B(n1132), .Y(mult_x_1_n1197) );
AOI222XLTS U1296 ( .A0(n1137), .A1(n1267), .B0(n1128), .B1(n32), .C0(n1134),
.C1(n30), .Y(n750) );
XOR2X1TS U1297 ( .A(n751), .B(n1140), .Y(mult_x_1_n1198) );
AOI222XLTS U1298 ( .A0(n1137), .A1(n1016), .B0(n1136), .B1(n28), .C0(n1175),
.C1(Data_B_i[11]), .Y(n752) );
OAI21X1TS U1299 ( .A0(n1018), .A1(n1177), .B0(n752), .Y(n753) );
XOR2X1TS U1300 ( .A(n753), .B(n1140), .Y(mult_x_1_n1200) );
OAI21X1TS U1301 ( .A0(n822), .A1(n755), .B0(n754), .Y(n760) );
NAND2X1TS U1302 ( .A(n758), .B(n757), .Y(n759) );
XOR2X1TS U1303 ( .A(n760), .B(n759), .Y(n1222) );
CLKBUFX2TS U1304 ( .A(n23), .Y(n1220) );
CLKBUFX2TS U1305 ( .A(Data_B_i[8]), .Y(n1219) );
CLKBUFX2TS U1306 ( .A(n1134), .Y(n1055) );
AOI222XLTS U1307 ( .A0(n1129), .A1(n1220), .B0(n1051), .B1(n1219), .C0(n1055), .C1(Data_B_i[7]), .Y(n761) );
XOR2X1TS U1308 ( .A(n762), .B(Data_A_i[20]), .Y(mult_x_1_n1204) );
AOI222XLTS U1309 ( .A0(n1129), .A1(n1169), .B0(n1136), .B1(n1241), .C0(n1055), .C1(Data_B_i[5]), .Y(n763) );
XOR2X1TS U1310 ( .A(n764), .B(Data_A_i[20]), .Y(mult_x_1_n1206) );
AOI222XLTS U1311 ( .A0(n1137), .A1(n1225), .B0(n1136), .B1(n1239), .C0(n1055), .C1(Data_B_i[4]), .Y(n765) );
OAI21XLTS U1312 ( .A0(n1244), .A1(n1053), .B0(n765), .Y(n766) );
XOR2X1TS U1313 ( .A(n766), .B(n1140), .Y(mult_x_1_n1207) );
AOI222XLTS U1314 ( .A0(n1137), .A1(n1033), .B0(n1136), .B1(n1032), .C0(n1055), .C1(Data_B_i[3]), .Y(n767) );
AOI222XLTS U1315 ( .A0(n1137), .A1(n1012), .B0(n1136), .B1(n1011), .C0(n1055), .C1(n14), .Y(n769) );
AOI222XLTS U1316 ( .A0(n1137), .A1(n1000), .B0(n1136), .B1(n999), .C0(n1134),
.C1(n998), .Y(n771) );
AOI222XLTS U1317 ( .A0(n1046), .A1(n1282), .B0(n1297), .B1(n1281), .C0(n1274), .C1(n1280), .Y(n773) );
AOI222XLTS U1318 ( .A0(n1046), .A1(n1144), .B0(n1297), .B1(n1143), .C0(n1266), .C1(n35), .Y(n775) );
XOR2X1TS U1319 ( .A(n776), .B(n1302), .Y(mult_x_1_n1221) );
AOI222XLTS U1320 ( .A0(n1046), .A1(n1085), .B0(n1224), .B1(n1075), .C0(n1274), .C1(n1073), .Y(n777) );
XOR2X1TS U1321 ( .A(n778), .B(n1302), .Y(mult_x_1_n1222) );
AOI222XLTS U1322 ( .A0(n1046), .A1(n1118), .B0(n1297), .B1(n1117), .C0(n1274), .C1(n1108), .Y(n779) );
XOR2X1TS U1323 ( .A(n780), .B(n1302), .Y(mult_x_1_n1223) );
AOI222XLTS U1324 ( .A0(n1046), .A1(n946), .B0(n1297), .B1(n968), .C0(n1274),
.C1(n32), .Y(n781) );
XOR2X1TS U1325 ( .A(n782), .B(n1302), .Y(mult_x_1_n1224) );
AOI222XLTS U1326 ( .A0(n1299), .A1(Data_B_i[14]), .B0(n1045), .B1(n1135),
.C0(n1266), .C1(n28), .Y(n783) );
XOR2X1TS U1327 ( .A(n784), .B(n1271), .Y(mult_x_1_n1226) );
INVX2TS U1328 ( .A(n785), .Y(n824) );
NAND2X1TS U1329 ( .A(n818), .B(n824), .Y(n788) );
AOI21X1TS U1330 ( .A0(n819), .A1(n824), .B0(n786), .Y(n787) );
OAI21X1TS U1331 ( .A0(n822), .A1(n788), .B0(n787), .Y(n793) );
NAND2X1TS U1332 ( .A(n791), .B(n790), .Y(n792) );
CLKBUFX2TS U1333 ( .A(n1123), .Y(n1215) );
CLKBUFX2TS U1334 ( .A(Data_B_i[10]), .Y(n1214) );
AOI222XLTS U1335 ( .A0(n1046), .A1(n1215), .B0(n1045), .B1(n1214), .C0(n1274), .C1(n23), .Y(n794) );
XOR2X1TS U1336 ( .A(n795), .B(Data_A_i[17]), .Y(mult_x_1_n1229) );
AOI222XLTS U1337 ( .A0(n1046), .A1(n1220), .B0(n1045), .B1(n1219), .C0(n1274), .C1(Data_B_i[7]), .Y(n796) );
AOI222XLTS U1338 ( .A0(n1046), .A1(n1028), .B0(n1045), .B1(n1027), .C0(n1266), .C1(n18), .Y(n798) );
XOR2X1TS U1339 ( .A(n799), .B(Data_A_i[17]), .Y(mult_x_1_n1232) );
NAND2X1TS U1340 ( .A(n1160), .B(n1229), .Y(n800) );
OAI21X1TS U1341 ( .A0(n1178), .A1(n991), .B0(n800), .Y(n801) );
XOR2X1TS U1342 ( .A(n801), .B(Data_A_i[14]), .Y(mult_x_1_n1242) );
AOI222XLTS U1343 ( .A0(n1124), .A1(n1298), .B0(n989), .B1(n1296), .C0(n1160),
.C1(n1282), .Y(n802) );
XOR2X1TS U1344 ( .A(n803), .B(n1163), .Y(mult_x_1_n1244) );
AOI222XLTS U1345 ( .A0(n1119), .A1(n1282), .B0(n1158), .B1(n1281), .C0(n1160), .C1(n1144), .Y(n804) );
XOR2X1TS U1346 ( .A(n805), .B(n1163), .Y(mult_x_1_n1246) );
AOI222XLTS U1347 ( .A0(n1119), .A1(n1276), .B0(n1158), .B1(n1275), .C0(n1160), .C1(n1085), .Y(n806) );
XOR2X1TS U1348 ( .A(n807), .B(n1163), .Y(mult_x_1_n1247) );
AOI222XLTS U1349 ( .A0(n1119), .A1(n1144), .B0(n1149), .B1(n1143), .C0(n1026), .C1(n1118), .Y(n808) );
XOR2X1TS U1350 ( .A(n809), .B(n1163), .Y(mult_x_1_n1248) );
AOI222XLTS U1351 ( .A0(n1119), .A1(n1085), .B0(n989), .B1(n1075), .C0(n1160),
.C1(n946), .Y(n810) );
XOR2X1TS U1352 ( .A(n811), .B(n1163), .Y(mult_x_1_n1249) );
AOI222XLTS U1353 ( .A0(n1119), .A1(n946), .B0(n1149), .B1(n968), .C0(n1160),
.C1(n33), .Y(n812) );
XOR2X1TS U1354 ( .A(n813), .B(n1163), .Y(mult_x_1_n1251) );
AOI222XLTS U1355 ( .A0(n1124), .A1(n1267), .B0(n1149), .B1(n32), .C0(n1026),
.C1(n1016), .Y(n814) );
XOR2X1TS U1356 ( .A(n815), .B(n992), .Y(mult_x_1_n1252) );
AOI222XLTS U1357 ( .A0(n1124), .A1(n33), .B0(n989), .B1(n1135), .C0(n1026),
.C1(Data_B_i[12]), .Y(n816) );
XOR2X1TS U1358 ( .A(n817), .B(n992), .Y(mult_x_1_n1253) );
OAI21X1TS U1359 ( .A0(n822), .A1(n821), .B0(n820), .Y(n826) );
NAND2X1TS U1360 ( .A(n824), .B(n823), .Y(n825) );
CLKBUFX2TS U1361 ( .A(Data_B_i[10]), .Y(n1249) );
CLKBUFX2TS U1362 ( .A(n23), .Y(n1247) );
AOI222XLTS U1363 ( .A0(n385), .A1(n1249), .B0(n1149), .B1(n1247), .C0(n1148),
.C1(n1028), .Y(n827) );
AOI222XLTS U1364 ( .A0(n1119), .A1(n1169), .B0(n989), .B1(n1241), .C0(n1026),
.C1(n1033), .Y(n829) );
XOR2X1TS U1365 ( .A(n830), .B(Data_A_i[14]), .Y(mult_x_1_n1260) );
AOI222XLTS U1366 ( .A0(n1124), .A1(n1225), .B0(n989), .B1(n1239), .C0(n1026),
.C1(n1012), .Y(n831) );
XOR2X1TS U1367 ( .A(n832), .B(n992), .Y(mult_x_1_n1261) );
AOI222XLTS U1368 ( .A0(n1124), .A1(n1033), .B0(n989), .B1(n1032), .C0(n1026),
.C1(n1000), .Y(n833) );
AOI222XLTS U1369 ( .A0(n1124), .A1(n1012), .B0(n989), .B1(n1011), .C0(n1026),
.C1(n900), .Y(n835) );
AOI222XLTS U1370 ( .A0(n1124), .A1(n1000), .B0(n989), .B1(n999), .C0(n1026),
.C1(n998), .Y(n837) );
XOR2X1TS U1371 ( .A(n838), .B(n992), .Y(mult_x_1_n1264) );
NAND2X1TS U1372 ( .A(n1233), .B(Data_B_i[23]), .Y(n839) );
XOR2X1TS U1373 ( .A(n840), .B(Data_A_i[11]), .Y(mult_x_1_n1269) );
AOI222XLTS U1374 ( .A0(n38), .A1(n1296), .B0(n1230), .B1(n1312), .C0(n1233),
.C1(n1310), .Y(n841) );
XOR2X1TS U1375 ( .A(n842), .B(n1237), .Y(mult_x_1_n1272) );
AOI222XLTS U1376 ( .A0(n37), .A1(n1312), .B0(n1230), .B1(n1281), .C0(n1233),
.C1(n1280), .Y(n843) );
OAI21X1TS U1377 ( .A0(n1284), .A1(n1235), .B0(n843), .Y(n844) );
AOI222XLTS U1378 ( .A0(n38), .A1(n1281), .B0(n1230), .B1(n1275), .C0(n1233),
.C1(n1273), .Y(n845) );
OAI21X1TS U1379 ( .A0(n1278), .A1(n1235), .B0(n845), .Y(n846) );
XOR2X1TS U1380 ( .A(n846), .B(n1237), .Y(mult_x_1_n1274) );
AOI222XLTS U1381 ( .A0(n38), .A1(n1275), .B0(n1230), .B1(n1143), .C0(n1088),
.C1(Data_B_i[17]), .Y(n847) );
XOR2X1TS U1382 ( .A(n848), .B(n1237), .Y(mult_x_1_n1275) );
AOI222XLTS U1383 ( .A0(n37), .A1(n1143), .B0(n1240), .B1(n1075), .C0(n1233),
.C1(n1073), .Y(n849) );
XOR2X1TS U1384 ( .A(n850), .B(n1237), .Y(mult_x_1_n1276) );
AOI222XLTS U1385 ( .A0(n38), .A1(n1075), .B0(n1230), .B1(n1117), .C0(n1233),
.C1(n1108), .Y(n851) );
XOR2X1TS U1386 ( .A(n852), .B(n1237), .Y(mult_x_1_n1277) );
AOI222XLTS U1387 ( .A0(n1242), .A1(n968), .B0(n1230), .B1(Data_B_i[14]),
.C0(n1088), .C1(Data_B_i[13]), .Y(n853) );
OAI21X1TS U1388 ( .A0(n1270), .A1(n976), .B0(n853), .Y(n854) );
XOR2X1TS U1389 ( .A(n854), .B(n1245), .Y(mult_x_1_n1279) );
AOI222XLTS U1390 ( .A0(n1242), .A1(n32), .B0(n1240), .B1(n1135), .C0(n12),
.C1(n27), .Y(n855) );
XOR2X1TS U1391 ( .A(n856), .B(n1245), .Y(mult_x_1_n1280) );
AOI222XLTS U1392 ( .A0(n1242), .A1(n1135), .B0(n1240), .B1(Data_B_i[12]),
.C0(n1233), .C1(n25), .Y(n857) );
CLKBUFX2TS U1393 ( .A(n12), .Y(n1088) );
AOI222XLTS U1394 ( .A0(n1242), .A1(Data_B_i[12]), .B0(n1230), .B1(n1123),
.C0(n1088), .C1(n1080), .Y(n859) );
XOR2X1TS U1395 ( .A(n860), .B(Data_A_i[11]), .Y(mult_x_1_n1282) );
AOI222XLTS U1396 ( .A0(n37), .A1(n1123), .B0(n862), .B1(n1214), .C0(n1088),
.C1(n23), .Y(n863) );
XOR2X1TS U1397 ( .A(n864), .B(Data_A_i[11]), .Y(mult_x_1_n1283) );
AOI222XLTS U1398 ( .A0(n38), .A1(n1219), .B0(n862), .B1(n1027), .C0(n12),
.C1(n18), .Y(n865) );
AOI222XLTS U1399 ( .A0(n38), .A1(n1027), .B0(n1240), .B1(n1241), .C0(n12),
.C1(n17), .Y(n867) );
AOI21X1TS U1400 ( .A0(n1165), .A1(n1232), .B0(n869), .Y(n870) );
OAI21X1TS U1401 ( .A0(n1236), .A1(n1096), .B0(n870), .Y(n871) );
XOR2X1TS U1402 ( .A(n871), .B(Data_A_i[8]), .Y(mult_x_1_n1297) );
CLKBUFX2TS U1403 ( .A(n1165), .Y(n1170) );
AOI222XLTS U1404 ( .A0(n155), .A1(n1298), .B0(n1015), .B1(n1296), .C0(n1170),
.C1(n1282), .Y(n872) );
XOR2X1TS U1405 ( .A(n873), .B(Data_A_i[8]), .Y(mult_x_1_n1298) );
AOI222XLTS U1406 ( .A0(n40), .A1(n1282), .B0(n1094), .B1(n1281), .C0(n1170),
.C1(n1144), .Y(n874) );
XOR2X1TS U1407 ( .A(n875), .B(n11), .Y(mult_x_1_n1300) );
AOI222XLTS U1408 ( .A0(n39), .A1(n1276), .B0(n1094), .B1(n1275), .C0(n1170),
.C1(n1085), .Y(n876) );
XOR2X1TS U1409 ( .A(n877), .B(Data_A_i[8]), .Y(mult_x_1_n1301) );
AOI222XLTS U1410 ( .A0(n40), .A1(n1144), .B0(n1094), .B1(n1143), .C0(n903),
.C1(n1118), .Y(n878) );
XOR2X1TS U1411 ( .A(n879), .B(Data_A_i[8]), .Y(mult_x_1_n1302) );
AOI222XLTS U1412 ( .A0(n39), .A1(n1085), .B0(n1015), .B1(n1075), .C0(n1170),
.C1(n946), .Y(n880) );
XOR2X1TS U1413 ( .A(n881), .B(Data_A_i[8]), .Y(mult_x_1_n1303) );
AOI222XLTS U1414 ( .A0(n39), .A1(n946), .B0(n1094), .B1(n968), .C0(n1170),
.C1(Data_B_i[14]), .Y(n882) );
XOR2X1TS U1415 ( .A(n883), .B(Data_A_i[8]), .Y(mult_x_1_n1305) );
AOI222XLTS U1416 ( .A0(n39), .A1(n1267), .B0(n1094), .B1(Data_B_i[14]), .C0(
n903), .C1(n1016), .Y(n884) );
XOR2X1TS U1417 ( .A(n885), .B(n1019), .Y(mult_x_1_n1306) );
AOI222XLTS U1418 ( .A0(n40), .A1(n33), .B0(n1015), .B1(n1135), .C0(n903),
.C1(n27), .Y(n886) );
OAI21X1TS U1419 ( .A0(n1139), .A1(n1167), .B0(n886), .Y(n887) );
XOR2X1TS U1420 ( .A(n887), .B(n1019), .Y(mult_x_1_n1307) );
AOI222XLTS U1421 ( .A0(n40), .A1(Data_B_i[12]), .B0(n1094), .B1(n1123), .C0(
n1170), .C1(n1249), .Y(n888) );
XOR2X1TS U1422 ( .A(n889), .B(n11), .Y(mult_x_1_n1309) );
AOI222XLTS U1423 ( .A0(n40), .A1(n1215), .B0(n393), .B1(n1214), .C0(n1170),
.C1(n1220), .Y(n890) );
AOI222XLTS U1424 ( .A0(n40), .A1(n1249), .B0(n393), .B1(n1247), .C0(n1170),
.C1(n1028), .Y(n892) );
AOI222XLTS U1425 ( .A0(n39), .A1(n1169), .B0(n1015), .B1(n1241), .C0(n903),
.C1(n1033), .Y(n894) );
AOI222XLTS U1426 ( .A0(n155), .A1(n1225), .B0(n1015), .B1(n1239), .C0(n903),
.C1(n1012), .Y(n896) );
AOI222XLTS U1427 ( .A0(n155), .A1(n1033), .B0(n1015), .B1(n1032), .C0(n903),
.C1(n1000), .Y(n898) );
AOI222XLTS U1428 ( .A0(n39), .A1(n1012), .B0(n1015), .B1(n1011), .C0(n903),
.C1(n900), .Y(n901) );
XOR2X1TS U1429 ( .A(n902), .B(n1019), .Y(mult_x_1_n1317) );
AOI222XLTS U1430 ( .A0(n39), .A1(n1000), .B0(n1015), .B1(n999), .C0(n903),
.C1(n998), .Y(n904) );
XOR2X1TS U1431 ( .A(n905), .B(n1019), .Y(mult_x_1_n1318) );
NAND2X1TS U1432 ( .A(n1180), .B(Data_B_i[23]), .Y(n906) );
XOR2X1TS U1433 ( .A(n907), .B(Data_A_i[5]), .Y(mult_x_1_n1323) );
CLKBUFX2TS U1434 ( .A(n1180), .Y(n1074) );
AOI222XLTS U1435 ( .A0(n932), .A1(n1298), .B0(n1111), .B1(n1296), .C0(n1074),
.C1(n1294), .Y(n908) );
XOR2X1TS U1436 ( .A(n909), .B(Data_A_i[5]), .Y(mult_x_1_n1325) );
AOI222XLTS U1437 ( .A0(n1182), .A1(n1276), .B0(n1181), .B1(n1275), .C0(n1074), .C1(n1273), .Y(n910) );
OAI21X1TS U1438 ( .A0(n1278), .A1(n1114), .B0(n910), .Y(n911) );
XOR2X1TS U1439 ( .A(n911), .B(Data_A_i[5]), .Y(mult_x_1_n1328) );
AOI222XLTS U1440 ( .A0(n1182), .A1(n946), .B0(n1181), .B1(n968), .C0(n1180),
.C1(n33), .Y(n912) );
AOI222XLTS U1441 ( .A0(n932), .A1(n1267), .B0(n1181), .B1(n32), .C0(n1142),
.C1(n30), .Y(n914) );
OAI21X1TS U1442 ( .A0(n1270), .A1(n1077), .B0(n914), .Y(n915) );
AOI222XLTS U1443 ( .A0(n1112), .A1(Data_B_i[14]), .B0(n1111), .B1(n1135),
.C0(n1142), .C1(n27), .Y(n916) );
AOI222XLTS U1444 ( .A0(n932), .A1(n1016), .B0(n1111), .B1(Data_B_i[12]),
.C0(n1074), .C1(n25), .Y(n918) );
AOI222XLTS U1445 ( .A0(n1112), .A1(n27), .B0(n1181), .B1(n1123), .C0(n1074),
.C1(n1080), .Y(n920) );
AOI222XLTS U1446 ( .A0(n1182), .A1(n1215), .B0(n923), .B1(n1214), .C0(n1074),
.C1(Data_B_i[9]), .Y(n924) );
AOI222XLTS U1447 ( .A0(n932), .A1(n1249), .B0(n923), .B1(n1247), .C0(n1074),
.C1(n21), .Y(n926) );
AOI222XLTS U1448 ( .A0(n932), .A1(n1220), .B0(n923), .B1(n1219), .C0(n1074),
.C1(n19), .Y(n928) );
AOI222XLTS U1449 ( .A0(n932), .A1(n1028), .B0(n923), .B1(n1027), .C0(n1142),
.C1(Data_B_i[6]), .Y(n930) );
AOI222XLTS U1450 ( .A0(n932), .A1(n1169), .B0(n1111), .B1(n1241), .C0(n1142),
.C1(Data_B_i[5]), .Y(n933) );
XOR2X1TS U1451 ( .A(n935), .B(Data_A_i[5]), .Y(mult_x_1_n1341) );
NAND2X1TS U1452 ( .A(n42), .B(n1229), .Y(n937) );
XOR2X1TS U1453 ( .A(n938), .B(Data_A_i[2]), .Y(mult_x_1_n1350) );
AOI21X1TS U1454 ( .A0(n42), .A1(n1232), .B0(n939), .Y(n940) );
AOI222XLTS U1455 ( .A0(n1103), .A1(n1085), .B0(n1066), .B1(n1075), .C0(n41),
.C1(n946), .Y(n942) );
AOI222XLTS U1456 ( .A0(n1103), .A1(n1118), .B0(n1102), .B1(n1117), .C0(n42),
.C1(n1267), .Y(n944) );
AOI222XLTS U1457 ( .A0(n1103), .A1(n946), .B0(n1102), .B1(n968), .C0(n41),
.C1(Data_B_i[14]), .Y(n947) );
AOI222XLTS U1458 ( .A0(n1067), .A1(n1267), .B0(n1102), .B1(n33), .C0(n42),
.C1(n1016), .Y(n949) );
AOI222XLTS U1459 ( .A0(n1067), .A1(Data_B_i[14]), .B0(n1066), .B1(n1135),
.C0(n42), .C1(n27), .Y(n951) );
AOI222XLTS U1460 ( .A0(n1067), .A1(n28), .B0(n1102), .B1(n1123), .C0(n1153),
.C1(n1249), .Y(n953) );
AOI222XLTS U1461 ( .A0(n1103), .A1(n1215), .B0(n176), .B1(n1214), .C0(n1153),
.C1(n1220), .Y(n955) );
AOI222XLTS U1462 ( .A0(n146), .A1(n1249), .B0(n176), .B1(n1247), .C0(n1153),
.C1(n1028), .Y(n957) );
XOR2X1TS U1463 ( .A(n958), .B(n1156), .Y(mult_x_1_n1365) );
ADDHXLTS U1464 ( .A(n960), .B(n959), .CO(mult_x_1_n874), .S(n188) );
NAND2X1TS U1465 ( .A(n63), .B(n961), .Y(n963) );
XNOR2X1TS U1466 ( .A(n963), .B(n962), .Y(N9) );
NAND2X1TS U1467 ( .A(n965), .B(n964), .Y(n966) );
XNOR2X1TS U1468 ( .A(n967), .B(n966), .Y(N16) );
AOI222XLTS U1469 ( .A0(n37), .A1(n1117), .B0(n1230), .B1(n968), .C0(n1233),
.C1(n33), .Y(n969) );
XOR2X1TS U1470 ( .A(n970), .B(n1237), .Y(mult_x_1_n1278) );
NAND2X1TS U1471 ( .A(n5), .B(n971), .Y(n973) );
XNOR2X1TS U1472 ( .A(n973), .B(n972), .Y(N7) );
AOI222XLTS U1473 ( .A0(n1242), .A1(n1032), .B0(n1240), .B1(n1011), .C0(n12),
.C1(Data_B_i[2]), .Y(n975) );
AOI222XLTS U1474 ( .A0(n1067), .A1(n1016), .B0(n1066), .B1(n28), .C0(n41),
.C1(n1215), .Y(n980) );
CMPR32X2TS U1475 ( .A(n984), .B(n983), .C(n982), .CO(mult_x_1_n846), .S(
mult_x_1_n847) );
AOI222XLTS U1476 ( .A0(n1250), .A1(n1012), .B0(n1290), .B1(n1011), .C0(n986),
.C1(Data_B_i[2]), .Y(n987) );
XOR2X1TS U1477 ( .A(n988), .B(n1319), .Y(n995) );
AOI222XLTS U1478 ( .A0(n1124), .A1(n1016), .B0(n989), .B1(n28), .C0(n1160),
.C1(n1215), .Y(n990) );
CMPR32X2TS U1479 ( .A(n996), .B(n995), .C(n994), .CO(mult_x_1_n736), .S(
mult_x_1_n737) );
ADDHXLTS U1480 ( .A(Data_A_i[20]), .B(n997), .CO(n1010), .S(n1008) );
AOI222X1TS U1481 ( .A0(n1299), .A1(n1000), .B0(n1045), .B1(n999), .C0(n1266),
.C1(n998), .Y(n1001) );
OAI21X1TS U1482 ( .A0(n56), .A1(n1269), .B0(n1001), .Y(n1002) );
XOR2X1TS U1483 ( .A(n1002), .B(n1271), .Y(n1007) );
CMPR32X2TS U1484 ( .A(n1008), .B(n1007), .C(n1006), .CO(mult_x_1_n808), .S(
mult_x_1_n809) );
AOI222XLTS U1485 ( .A0(n1299), .A1(n1012), .B0(n1045), .B1(n1011), .C0(n1266), .C1(n14), .Y(n1013) );
AOI222XLTS U1486 ( .A0(n155), .A1(n1016), .B0(n1015), .B1(Data_B_i[12]),
.C0(n1165), .C1(n1215), .Y(n1017) );
CMPR32X2TS U1487 ( .A(n1023), .B(n1022), .C(n1021), .CO(mult_x_1_n798), .S(
mult_x_1_n799) );
AOI222XLTS U1488 ( .A0(n385), .A1(n1028), .B0(n1149), .B1(n1027), .C0(n1026),
.C1(n1225), .Y(n1029) );
OAI21XLTS U1489 ( .A0(n1030), .A1(n1151), .B0(n1029), .Y(n1031) );
AOI222XLTS U1490 ( .A0(n1299), .A1(n1033), .B0(n1224), .B1(n1032), .C0(n1266), .C1(n15), .Y(n1034) );
CMPR32X2TS U1491 ( .A(n1039), .B(n1038), .C(n1037), .CO(mult_x_1_n788), .S(
mult_x_1_n789) );
NAND2X1TS U1492 ( .A(n1042), .B(n1041), .Y(n1043) );
AOI222XLTS U1493 ( .A0(n1046), .A1(n1249), .B0(n1045), .B1(n1247), .C0(n1274), .C1(Data_B_i[8]), .Y(n1047) );
XOR2X1TS U1494 ( .A(n1048), .B(Data_A_i[17]), .Y(mult_x_1_n1230) );
AOI222XLTS U1495 ( .A0(n1129), .A1(n1215), .B0(n1051), .B1(n1214), .C0(n1055), .C1(Data_B_i[9]), .Y(n1049) );
XOR2X1TS U1496 ( .A(n1050), .B(Data_A_i[20]), .Y(mult_x_1_n1202) );
AOI222XLTS U1497 ( .A0(n1129), .A1(n1249), .B0(n1051), .B1(n1247), .C0(n1055), .C1(n21), .Y(n1052) );
XOR2X1TS U1498 ( .A(n1054), .B(n1132), .Y(mult_x_1_n1203) );
AOI222XLTS U1499 ( .A0(n1137), .A1(Data_B_i[12]), .B0(n1128), .B1(n1123),
.C0(n1055), .C1(n1080), .Y(n1056) );
XOR2X1TS U1500 ( .A(n1057), .B(Data_A_i[20]), .Y(mult_x_1_n1201) );
AOI222XLTS U1501 ( .A0(n1182), .A1(n1314), .B0(n1181), .B1(n1312), .C0(n1074), .C1(n1310), .Y(n1058) );
XOR2X1TS U1502 ( .A(n1059), .B(n36), .Y(mult_x_1_n1326) );
AOI222XLTS U1503 ( .A0(n39), .A1(n1314), .B0(n1094), .B1(n1312), .C0(n1170),
.C1(n1276), .Y(n1060) );
XOR2X1TS U1504 ( .A(n1061), .B(Data_A_i[8]), .Y(mult_x_1_n1299) );
AOI222XLTS U1505 ( .A0(n1182), .A1(n1118), .B0(n1181), .B1(n1117), .C0(n1074), .C1(n1108), .Y(n1062) );
XOR2X1TS U1506 ( .A(n1063), .B(Data_A_i[5]), .Y(mult_x_1_n1331) );
AOI222XLTS U1507 ( .A0(n37), .A1(n1214), .B0(n862), .B1(n1247), .C0(n1088),
.C1(n21), .Y(n1064) );
XOR2X1TS U1508 ( .A(n1065), .B(Data_A_i[11]), .Y(mult_x_1_n1284) );
AOI222XLTS U1509 ( .A0(n1067), .A1(n1298), .B0(n1066), .B1(n1296), .C0(n41),
.C1(n1282), .Y(n1068) );
XOR2X1TS U1510 ( .A(n1069), .B(n1106), .Y(mult_x_1_n1352) );
AOI21X1TS U1511 ( .A0(n1180), .A1(n1232), .B0(n1070), .Y(n1071) );
XOR2X1TS U1512 ( .A(n1072), .B(n36), .Y(mult_x_1_n1324) );
AOI222XLTS U1513 ( .A0(n1182), .A1(n1085), .B0(n1111), .B1(n1075), .C0(n1074), .C1(n1073), .Y(n1076) );
XOR2X1TS U1514 ( .A(n1079), .B(n36), .Y(mult_x_1_n1330) );
AOI222XLTS U1515 ( .A0(n1299), .A1(Data_B_i[12]), .B0(n1297), .B1(n1123),
.C0(n1274), .C1(n1080), .Y(n1081) );
XOR2X1TS U1516 ( .A(n1082), .B(Data_A_i[17]), .Y(mult_x_1_n1228) );
AOI222XLTS U1517 ( .A0(n1119), .A1(n1215), .B0(n1149), .B1(n1214), .C0(n1148), .C1(n1220), .Y(n1083) );
XOR2X1TS U1518 ( .A(n1084), .B(Data_A_i[14]), .Y(mult_x_1_n1256) );
AOI222XLTS U1519 ( .A0(n1103), .A1(n1276), .B0(n1102), .B1(n1275), .C0(n42),
.C1(n1085), .Y(n1086) );
XOR2X1TS U1520 ( .A(n1087), .B(n1099), .Y(mult_x_1_n1355) );
AOI222XLTS U1521 ( .A0(n37), .A1(n1247), .B0(n862), .B1(n1219), .C0(n1088),
.C1(n19), .Y(n1090) );
AOI222XLTS U1522 ( .A0(n1103), .A1(n1144), .B0(n1102), .B1(n1143), .C0(n41),
.C1(n1118), .Y(n1092) );
XOR2X1TS U1523 ( .A(n1093), .B(n1099), .Y(mult_x_1_n1356) );
AOI222XLTS U1524 ( .A0(n40), .A1(n1118), .B0(n1094), .B1(n1117), .C0(n1165),
.C1(n1267), .Y(n1095) );
XOR2X1TS U1525 ( .A(n1097), .B(Data_A_i[8]), .Y(mult_x_1_n1304) );
AOI222XLTS U1526 ( .A0(n1103), .A1(n1282), .B0(n1102), .B1(n1281), .C0(n42),
.C1(n1144), .Y(n1098) );
XOR2X1TS U1527 ( .A(n1100), .B(n1099), .Y(mult_x_1_n1354) );
AOI222XLTS U1528 ( .A0(n1103), .A1(n1314), .B0(n1102), .B1(n1312), .C0(n41),
.C1(n1276), .Y(n1104) );
XOR2X1TS U1529 ( .A(n1107), .B(n1106), .Y(mult_x_1_n1353) );
AOI222XLTS U1530 ( .A0(n1129), .A1(n1118), .B0(n1128), .B1(n1117), .C0(n1175), .C1(n1108), .Y(n1109) );
XOR2X1TS U1531 ( .A(n1110), .B(n1132), .Y(mult_x_1_n1196) );
AOI222XLTS U1532 ( .A0(n1112), .A1(n1225), .B0(n1111), .B1(n1239), .C0(n1142), .C1(n16), .Y(n1113) );
XOR2X1TS U1533 ( .A(n1116), .B(n1115), .Y(mult_x_1_n1342) );
AOI222XLTS U1534 ( .A0(n1119), .A1(n1118), .B0(n1158), .B1(n1117), .C0(n1160), .C1(n1267), .Y(n1120) );
AOI222XLTS U1535 ( .A0(n1124), .A1(n27), .B0(n1149), .B1(n1123), .C0(n1148),
.C1(n1249), .Y(n1125) );
AOI222XLTS U1536 ( .A0(n1129), .A1(n1276), .B0(n1128), .B1(n1275), .C0(n1175), .C1(n1273), .Y(n1130) );
OAI21X1TS U1537 ( .A0(n1278), .A1(n1131), .B0(n1130), .Y(n1133) );
XOR2X1TS U1538 ( .A(n1133), .B(n1132), .Y(mult_x_1_n1193) );
AOI222XLTS U1539 ( .A0(n1137), .A1(Data_B_i[14]), .B0(n1136), .B1(n1135),
.C0(n1134), .C1(n28), .Y(n1138) );
AOI222XLTS U1540 ( .A0(n1182), .A1(n1144), .B0(n1181), .B1(n1143), .C0(n1142), .C1(Data_B_i[17]), .Y(n1145) );
AOI222XLTS U1541 ( .A0(n385), .A1(n1220), .B0(n1149), .B1(n1219), .C0(n1148),
.C1(n1169), .Y(n1150) );
AOI222XLTS U1542 ( .A0(n146), .A1(n1220), .B0(n176), .B1(n1219), .C0(n1153),
.C1(n1169), .Y(n1154) );
AOI21X1TS U1543 ( .A0(n1160), .A1(n1232), .B0(n1159), .Y(n1161) );
NAND2X1TS U1544 ( .A(n1165), .B(Data_B_i[23]), .Y(n1166) );
AOI222XLTS U1545 ( .A0(n40), .A1(n1220), .B0(n393), .B1(n1219), .C0(n1170),
.C1(n1169), .Y(n1172) );
NAND2X1TS U1546 ( .A(n1175), .B(Data_B_i[23]), .Y(n1176) );
AOI222XLTS U1547 ( .A0(n1182), .A1(n1282), .B0(n1181), .B1(n1281), .C0(n1180), .C1(n1280), .Y(n1183) );
OAI21X1TS U1548 ( .A0(n1284), .A1(n922), .B0(n1183), .Y(n1184) );
NAND2X1TS U1549 ( .A(n1187), .B(n1186), .Y(n1188) );
AOI21X1TS U1550 ( .A0(n1208), .A1(n1192), .B0(n1194), .Y(n1191) );
NAND2X1TS U1551 ( .A(n1195), .B(n1189), .Y(n1190) );
AOI21X1TS U1552 ( .A0(n1208), .A1(n1199), .B0(n1198), .Y(n1204) );
NAND2X1TS U1553 ( .A(n1202), .B(n1201), .Y(n1203) );
AOI21X1TS U1554 ( .A0(n1208), .A1(n1207), .B0(n1206), .Y(n1213) );
NAND2X1TS U1555 ( .A(n1211), .B(n1210), .Y(n1212) );
AOI222XLTS U1556 ( .A0(n1315), .A1(n1215), .B0(n1248), .B1(n1214), .C0(n1289), .C1(n1247), .Y(n1216) );
XOR2X1TS U1557 ( .A(n1218), .B(n1319), .Y(mult_x_1_n1175) );
AOI222XLTS U1558 ( .A0(n1250), .A1(n1220), .B0(n1248), .B1(n1219), .C0(n1289), .C1(Data_B_i[7]), .Y(n1221) );
XOR2X1TS U1559 ( .A(n1223), .B(n1319), .Y(mult_x_1_n1177) );
AOI222XLTS U1560 ( .A0(n1299), .A1(n1225), .B0(n1224), .B1(n1239), .C0(n1266), .C1(Data_B_i[4]), .Y(n1226) );
AOI21X1TS U1561 ( .A0(n1233), .A1(n1232), .B0(n1231), .Y(n1234) );
XOR2X1TS U1562 ( .A(n1238), .B(n1237), .Y(mult_x_1_n1270) );
AOI222XLTS U1563 ( .A0(n1242), .A1(n1241), .B0(n1240), .B1(n1239), .C0(n1088), .C1(n16), .Y(n1243) );
XOR2X1TS U1564 ( .A(n1246), .B(n1245), .Y(mult_x_1_n1288) );
AOI222XLTS U1565 ( .A0(n1250), .A1(n1249), .B0(n1248), .B1(n1247), .C0(n1289), .C1(Data_B_i[8]), .Y(n1251) );
NAND2X1TS U1566 ( .A(n1257), .B(n1256), .Y(n1258) );
AOI21X1TS U1567 ( .A0(n1261), .A1(n65), .B0(n1260), .Y(n1265) );
NAND2X1TS U1568 ( .A(n1263), .B(n1262), .Y(n1264) );
AOI222XLTS U1569 ( .A0(n1299), .A1(n1267), .B0(n1297), .B1(n32), .C0(n1266),
.C1(Data_B_i[13]), .Y(n1268) );
AOI222XLTS U1570 ( .A0(n1286), .A1(n1276), .B0(n1297), .B1(n1275), .C0(n1274), .C1(n1273), .Y(n1277) );
AOI222XLTS U1571 ( .A0(n1315), .A1(n1282), .B0(n1313), .B1(n1281), .C0(n1289), .C1(n1280), .Y(n1283) );
AOI222XLTS U1572 ( .A0(n1286), .A1(n1314), .B0(n1297), .B1(n1312), .C0(n1295), .C1(n1310), .Y(n1287) );
AOI222XLTS U1573 ( .A0(n1315), .A1(n1298), .B0(n1290), .B1(n1296), .C0(n1289), .C1(n1294), .Y(n1291) );
AOI222XLTS U1574 ( .A0(n1299), .A1(n1298), .B0(n1297), .B1(n1296), .C0(n1295), .C1(n1294), .Y(n1300) );
AOI21X1TS U1575 ( .A0(n1305), .A1(n64), .B0(n1304), .Y(n1309) );
NAND2X1TS U1576 ( .A(n1307), .B(n1306), .Y(n1308) );
AOI222XLTS U1577 ( .A0(n1315), .A1(n1314), .B0(n1313), .B1(n1312), .C0(n1311), .C1(n1310), .Y(n1316) );
INVX2TS U1578 ( .A(mult_x_1_n907), .Y(mult_x_1_n682) );
NAND2X1TS U1579 ( .A(n1323), .B(n1322), .Y(n1324) );
INVX2TS U1580 ( .A(mult_x_1_n901), .Y(mult_x_1_n627) );
AOI21X1TS U1581 ( .A0(n1327), .A1(n62), .B0(n1326), .Y(n1331) );
NAND2X1TS U1582 ( .A(n1329), .B(n1328), .Y(n1330) );
INVX2TS U1583 ( .A(mult_x_1_n895), .Y(mult_x_1_n590) );
NAND2X1TS U1584 ( .A(n1334), .B(n1333), .Y(n1335) );
NAND2X1TS U1585 ( .A(n1339), .B(n1338), .Y(n1341) );
NAND2X1TS U1586 ( .A(n2), .B(n1342), .Y(n1347) );
AOI21X1TS U1587 ( .A0(n1345), .A1(n1344), .B0(n1343), .Y(n1346) );
CMPR42X1TS U1588 ( .A(n1351), .B(mult_x_1_n907), .C(mult_x_1_n905), .D(
mult_x_1_n1175), .ICI(mult_x_1_n1199), .S(mult_x_1_n662), .ICO(
mult_x_1_n660), .CO(mult_x_1_n661) );
CMPR42X1TS U1589 ( .A(n1349), .B(mult_x_1_n895), .C(mult_x_1_n893), .D(
mult_x_1_n1163), .ICI(mult_x_1_n583), .S(mult_x_1_n582), .ICO(
mult_x_1_n580), .CO(mult_x_1_n581) );
CMPR42X1TS U1590 ( .A(mult_x_1_n894), .B(mult_x_1_n590), .C(mult_x_1_n1188),
.D(mult_x_1_n1164), .ICI(mult_x_1_n587), .S(mult_x_1_n585), .ICO(
mult_x_1_n583), .CO(mult_x_1_n584) );
initial $sdf_annotate("mult_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_1_V
`define SKY130_FD_SC_HD__A21BO_1_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD1_TB_V
`define SKY130_FD_SC_MS__DLYGATE4SD1_TB_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlygate4sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__dlygate4sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD1_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_pwrgood_pp$G (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2_4_V
`define SKY130_FD_SC_LS__OR2_4_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTN_1_V
`define SKY130_FD_SC_MS__DFRTN_1_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTN_1_V
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- An automatic page fetching system. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
`include "zap_defines.vh"
module zap_tlb_fsm #(
// Pass from top.
parameter LPAGE_TLB_ENTRIES = 8,
parameter SPAGE_TLB_ENTRIES = 8,
parameter SECTION_TLB_ENTRIES = 8,
parameter FPAGE_TLB_ENTRIES = 8
)(
/* Clock and Reset */
input wire i_clk,
input wire i_reset,
/* From CP15 */
input wire i_mmu_en,
input wire [31:0] i_baddr,
/* From cache FSM */
input wire [31:0] i_address,
/* From TLB check unit */
input wire i_walk,
input wire [7:0] i_fsr,
input wire [31:0] i_far,
input wire i_cacheable,
input wire [31:0] i_phy_addr,
/* To main cache FSM */
output reg [7:0] o_fsr,
output reg [31:0] o_far,
output reg o_fault,
output reg [31:0] o_phy_addr,
output reg o_cacheable,
output reg o_busy,
/* To TLBs */
output reg [`SECTION_TLB_WDT-1:0] o_setlb_wdata,
output reg o_setlb_wen,
output reg [`SPAGE_TLB_WDT-1:0] o_sptlb_wdata,
output reg o_sptlb_wen,
output reg [`LPAGE_TLB_WDT-1:0] o_lptlb_wdata,
output reg o_lptlb_wen,
output reg [`FPAGE_TLB_WDT-1:0] o_fptlb_wdata,
output reg o_fptlb_wen,
output reg [31:0] o_address,
/* Wishbone signals NXT */
output wire o_wb_cyc_nxt,
output wire o_wb_stb_nxt,
output wire [31:0] o_wb_adr_nxt,
/* Wishbone Signals */
output wire o_wb_cyc,
output wire o_wb_stb,
output wire o_wb_wen,
output wire [3:0] o_wb_sel, o_wb_sel_nxt,
output wire [31:0] o_wb_adr,
input wire [31:0] i_wb_dat,
input wire i_wb_ack,
// Unused.
output wire o_unused_ok
);
`include "zap_localparams.vh"
`include "zap_defines.vh"
`include "zap_functions.vh"
// ----------------------------------------------------------------------------
/* States */
localparam IDLE = 0; /* Idle State */
localparam FETCH_L1_DESC = 1; /* Fetch L1 descriptor */
localparam FETCH_L2_DESC = 2; /* Fetch L2 descriptor */
localparam FETCH_L1_DESC_0 = 3;
localparam FETCH_L2_DESC_0 = 4;
localparam NUMBER_OF_STATES = 5;
// ----------------------------------------------------------------------------
reg [3:0] dac_ff, dac_nxt; /* Scratchpad register */
reg [$clog2(NUMBER_OF_STATES)-1:0] state_ff, state_nxt; /* State register */
/* Wishbone related */
reg wb_stb_nxt, wb_stb_ff;
reg wb_cyc_nxt, wb_cyc_ff;
reg [31:0] wb_adr_nxt, wb_adr_ff;
reg [31:0] address;
// ----------------------------------------------------------------------------
/* Tie output flops to ports. */
assign o_wb_cyc = wb_cyc_ff;
assign o_wb_stb = wb_stb_ff;
assign o_wb_adr = wb_adr_ff;
assign o_wb_cyc_nxt = wb_cyc_nxt;
assign o_wb_stb_nxt = wb_stb_nxt;
assign o_wb_adr_nxt = wb_adr_nxt;
reg [3:0] wb_sel_nxt, wb_sel_ff;
/* Tied PORTS */
assign o_wb_wen = 1'd0;
assign o_wb_sel = wb_sel_ff;
assign o_wb_sel_nxt = wb_sel_nxt;
assign o_unused_ok = 0 || i_baddr[13:0];
reg [31:0] dff, dnxt; /* Wishbone memory buffer. */
always @ ( posedge i_clk ) if ( state_ff == IDLE ) address <= i_address;
always @*
o_address = address;
/* Combinational logic */
always @*
begin: blk1
o_fsr = 0;
o_far = 0;
o_fault = 0;
o_busy = 0;
o_phy_addr = i_phy_addr;
o_cacheable = i_cacheable;
o_setlb_wen = 0;
o_lptlb_wen = 0;
o_sptlb_wen = 0;
o_setlb_wdata = 0;
o_sptlb_wdata = 0;
o_lptlb_wdata = 0;
o_fptlb_wdata = 0;
o_fptlb_wen = 0;
/* Kill wishbone access unless overridden */
wb_stb_nxt = 0;
wb_cyc_nxt = 0;
wb_adr_nxt = 0;
wb_sel_nxt = 0;
dac_nxt = dac_ff;
state_nxt = state_ff;
dnxt = dff;
case ( state_ff )
IDLE:
begin
if ( i_mmu_en )
begin
if ( i_walk )
begin
o_busy = 1'd1;
/*
* We need to page walk to get the page table.
* Call for access to L1 level page table.
*/
tsk_prpr_wb_rd({i_baddr[`VA__TRANSLATION_BASE],
i_address[`VA__TABLE_INDEX], 2'd0});
state_nxt = FETCH_L1_DESC_0;
end
else if ( i_fsr[3:0] != 4'b0000 ) /* Access Violation. */
begin
o_fault = 1'd1;
o_busy = 1'd0;
o_fsr = i_fsr;
o_far = i_far;
end
end
end
FETCH_L1_DESC_0:
begin
o_busy = 1;
if ( i_wb_ack )
begin
dnxt = i_wb_dat;
state_nxt = FETCH_L1_DESC;
end
else
begin
tsk_hold_wb_access;
end
end
FETCH_L1_DESC:
begin
/*
* What we would have fetched is the L1 descriptor.
* Examine it. dff holds the L1 descriptor.
*/
o_busy = 1'd1;
case ( dff[`ID] )
SECTION_ID:
begin
/*
* It is a section itself so there is no need
* for another fetch. Simply reload the TLB
* and we are good.
*/
o_setlb_wen = 1'd1;
o_setlb_wdata = {address[`VA__SECTION_TAG],
dff};
state_nxt = IDLE;
$display($time, " - %m :: #########################################################");
$display($time, " - %m :: SECTION DESCRIPTOR DETAILS #");
$display($time, " - %m :: #########################################################");
$display($time, " - %m :: # BASE ADDRESS = 0x%x ", o_setlb_wdata[`SECTION_TLB__BASE]);
$display($time, " - %m :: # DAC = 0b%b", o_setlb_wdata[`SECTION_TLB__DAC_SEL]);
$display($time, " - %m :: # AP bits = 0b%b", o_setlb_wdata[`SECTION_TLB__AP]);
$display($time, " - %m :: # Cacheable = 0b%b", o_setlb_wdata[`SECTION_TLB__CB] >> 1);
$display($time, " - %m :: # Bufferable = 0b%b", o_setlb_wdata[`SECTION_TLB__CB] & 2'b01);
$display($time, " - %m :: #########################################################");
end
PAGE_ID:
begin
/*
* Page ID requires that DAC from current
* descriptor is remembered because when we
* reload the TLB, it would be useful. Anyway,
* we need to initiate another access.
*/
dac_nxt = dff[`L1_PAGE__DAC_SEL]; // dac register holds the dac sel for future use.
state_nxt = FETCH_L2_DESC_0;
tsk_prpr_wb_rd({dff[`L1_PAGE__PTBR],
address[`VA__L2_TABLE_INDEX], 2'd0});
end
FINE_ID:
begin
/*
* Page ID requires DAC from current descriptor.
*/
dac_nxt = dff[`L1_PAGE__DAC_SEL];
state_nxt = FETCH_L2_DESC_0;
tsk_prpr_wb_rd({dff[`L1_FINE__PTBR],
address[`VA__L2_TABLE_INDEX], 2'd0});
end
default: /* Generate section translation fault. Fault Class II */
begin
o_fsr = FSR_SECTION_TRANSLATION_FAULT;
o_fsr = {dff[`L1_SECTION__DAC_SEL], o_fsr[3:0]};
o_far = address;
o_fault = 1'd1;
o_busy = 1'd0;
state_nxt = IDLE;
end
endcase
end
FETCH_L2_DESC_0:
begin
o_busy = 1;
if ( i_wb_ack )
begin
dnxt = i_wb_dat;
state_nxt = FETCH_L2_DESC;
end
else
begin
tsk_hold_wb_access;
end
end
FETCH_L2_DESC:
begin
o_busy = 1'd1;
case ( dff[`ID] ) // dff holds L2 descriptor. dac_ff holds L1 descriptor DAC.
SPAGE_ID:
begin
/* Update TLB */
o_sptlb_wen = 1'd1;
/* Define TLB fields to write */
o_sptlb_wdata[`SPAGE_TLB__TAG] = address[`VA__SPAGE_TAG];
o_sptlb_wdata[`SPAGE_TLB__DAC_SEL] = dac_ff; /* DAC selector from L1. */
o_sptlb_wdata[`SPAGE_TLB__AP] = dff[`L2_SPAGE__AP];
o_sptlb_wdata[`SPAGE_TLB__CB] = dff[`L2_SPAGE__CB];
o_sptlb_wdata[`SPAGE_TLB__BASE] = dff[`L2_SPAGE__BASE];
$display($time, " - %m :: #########################################################");
$display($time, " - %m :: SPAGE DESCRIPTOR DETAILS #");
$display($time, " - %m :: #########################################################");
$display($time, " - %m :: # BASE ADDRESS = 0x%x ", o_sptlb_wdata[`SPAGE_TLB__BASE]);
$display($time, " - %m :: # DAC = 0b%b", o_sptlb_wdata[`SPAGE_TLB__DAC_SEL]);
$display($time, " - %m :: # AP bits = 0b%b", o_sptlb_wdata[`SPAGE_TLB__AP]);
$display($time, " - %m :: # Cacheable = 0b%b", o_sptlb_wdata[`SPAGE_TLB__CB] >> 1);
$display($time, " - %m :: # Bufferable = 0b%b", o_sptlb_wdata[`SPAGE_TLB__CB] & 2'b01);
$display($time, " - %m :: #########################################################");
/* Go to IDLE */
state_nxt = IDLE;
end
LPAGE_ID:
begin
/* Update TLB */
o_lptlb_wen = 1'd1;
/* DAC is inserted in between to save bits */
o_lptlb_wdata = {address[`VA__LPAGE_TAG], dac_ff, dff};
$display($time, " - %m :: #########################################################");
$display($time, " - %m :: LPAGE DESCRIPTOR DETAILS #");
$display($time, " - %m :: #########################################################");
$display($time, " - %m :: # BASE ADDRESS = 0x%x ", o_lptlb_wdata[`LPAGE_TLB__BASE]);
$display($time, " - %m :: # DAC = 0b%b", o_lptlb_wdata[`LPAGE_TLB__DAC_SEL]);
$display($time, " - %m :: # AP bits = 0b%b", o_lptlb_wdata[`LPAGE_TLB__AP]);
$display($time, " - %m :: # Cacheable = 0b%b", o_lptlb_wdata[`LPAGE_TLB__CB] >> 1);
$display($time, " - %m :: # Bufferable = 0b%b", o_lptlb_wdata[`LPAGE_TLB__CB] & 2'b01);
$display($time, " - %m :: #########################################################");
/* Go to IDLE */
state_nxt = IDLE;
end
FPAGE_ID:
begin
/* Update TLB */
o_fptlb_wen = 1'd1;
/* Define TLB fields to write */
o_fptlb_wdata[`FPAGE_TLB__TAG] = address[`VA__FPAGE_TAG];
o_fptlb_wdata[`FPAGE_TLB__DAC_SEL] = dac_ff; /* DAC selector from L1. */
o_fptlb_wdata[`FPAGE_TLB__AP] = dff[`L2_FPAGE__AP];
o_fptlb_wdata[`FPAGE_TLB__CB] = dff[`L2_FPAGE__CB];
o_fptlb_wdata[`FPAGE_TLB__BASE] = dff[`L2_FPAGE__BASE];
$display($time, " - %m :: #########################################################");
$display($time, " - %m :: FPAGE DESCRIPTOR DETAILS #");
$display($time, " - %m :: #########################################################");
$display($time, " - %m :: # BASE ADDRESS = 0x%x ", o_fptlb_wdata[`FPAGE_TLB__BASE]);
$display($time, " - %m :: # DAC = 0b%b", o_fptlb_wdata[`FPAGE_TLB__DAC_SEL]);
$display($time, " - %m :: # AP bits = 0b%b", o_fptlb_wdata[`FPAGE_TLB__AP]);
$display($time, " - %m :: # Cacheable = 0b%b", o_fptlb_wdata[`FPAGE_TLB__CB] >> 1);
$display($time, " - %m :: # Bufferable = 0b%b", o_fptlb_wdata[`FPAGE_TLB__CB] & 2'b01);
$display($time, " - %m :: #########################################################");
/* Go to IDLE */
state_nxt = IDLE;
end
default: /* Fault Class II */
begin
o_busy = 1'd0;
o_fault = 1'd1;
o_fsr = FSR_PAGE_TRANSLATION_FAULT;
o_fsr = {1'd0, dac_ff, o_fsr[3:0]};
o_far = address;
state_nxt = IDLE;
end
endcase
end
endcase
end
// ----------------------------------------------------------------------------
// Clocked Logic.
always @ (posedge i_clk)
begin
if ( i_reset )
begin
state_ff <= IDLE;
wb_stb_ff <= 0;
wb_cyc_ff <= 0;
wb_adr_ff <= 0;
dac_ff <= 0;
wb_sel_ff <= 0;
dff <= 0;
end
else
begin
state_ff <= state_nxt;
wb_stb_ff <= wb_stb_nxt;
wb_cyc_ff <= wb_cyc_nxt;
wb_adr_ff <= wb_adr_nxt;
dac_ff <= dac_nxt;
wb_sel_ff <= wb_sel_nxt;
dff <= dnxt;
end
end
// ----------------------------------------------------------------------------
task tsk_hold_wb_access;
begin
wb_stb_nxt = wb_stb_ff;
wb_cyc_nxt = wb_cyc_ff;
wb_adr_nxt = wb_adr_ff;
wb_sel_nxt = wb_sel_ff;
end
endtask
task tsk_prpr_wb_rd ( input [31:0] adr );
begin
wb_stb_nxt = 1'd1;
wb_cyc_nxt = 1'd1;
wb_adr_nxt = adr;
wb_sel_nxt[3:0] = 4'b1111;
end
endtask
endmodule // zap_tlb_fsm.v
`default_nettype wire
// ----------------------------------------------------------------------------
// END OF FILE
// ----------------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBP_1_V
`define SKY130_FD_SC_HS__DFBBP_1_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog wrapper for dfbbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfbbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXBP_TB_V
`define SKY130_FD_SC_HD__SDFXBP_TB_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfxbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXBP_TB_V
|
// Fast Multisource Pulse Registration System
// Module:
// Flexible, 3-fifo multidirectional FX2 USB-2 interface
// (c) Ben Gamari (2010)
module reg_manager(
clk,
cmd_wr, cmd_in,
reply_out, reply_rdy, reply_ack, reply_end,
reg_addr, reg_data, reg_wr
);
// fx2bidir interface
input clk;
input cmd_wr;
input [7:0] cmd_in;
output [7:0] reply_out;
output reply_rdy;
input reply_ack;
output reply_end;
// Internal interface
output [15:0] reg_addr;
inout [31:0] reg_data;
output reg_wr;
reg [15:0] addr;
reg [31:0] data;
reg [4:0] state;
reg wants_wr;
initial state = 0;
always @(posedge clk)
case (state)
0: if (cmd_wr && cmd_in == 8'hAA) // Read magic number
state <= 1;
1: if (cmd_wr) // Read message type (read/write)
begin
wants_wr <= cmd_in[0];
state <= 2;
end
// Read address
2: if (cmd_wr) // 1st byte
begin
addr[7:0] <= cmd_in;
state <= 3;
end
3: if (cmd_wr) // 2nd byte
begin
addr[15:8] <= cmd_in;
state <= 4;
end
// Read value
4: if (cmd_wr) // 1st byte
begin
data[7:0] <= cmd_in;
state <= 5;
end
5: if (cmd_wr) // 2nd byte
begin
data[15:8] <= cmd_in;
state <= 6;
end
6: if (cmd_wr) // 3rd byte
begin
data[23:16] <= cmd_in;
state <= 7;
end
7: if (cmd_wr) // 4th byte
begin
data[31:24] <= cmd_in;
state <= 8;
end
// Write new value to register (if needed)
8: state <= 9;
// Write reply to host
9: if (reply_ack) // 1st byte
state <= 10;
10: if (reply_ack) // 2nd byte
state <= 11;
11: if (reply_ack) // 3rd byte
state <= 12;
12: if (reply_ack) // 4th byte
state <= 0;
default:
state <= 0;
endcase
assign reg_addr = (state==8 || state==9 || state==10 || state==11 || state==12) ? addr : 16'hXX;
assign reg_data = (state==8) ? data : 32'hZZ;
assign reg_wr = (state==8) && wants_wr;
assign reply_out = (state==9) ? reg_data[7:0] :
(state==10) ? reg_data[15:8] :
(state==11) ? reg_data[23:16] :
(state==12) ? reg_data[31:24] : 8'hZZ;
assign reply_rdy = state==9 || state==10 || state==11 || state==12;
assign reply_end = state==12;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_2_V
`define SKY130_FD_SC_LP__AND4BB_2_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4bb_2 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4bb_2 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_2_V
|
// spw_babasu_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.1 593
`timescale 1 ps / 1 ps
module spw_babasu_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
spw_babasu_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Xilinx Virtex RAM 32x8D ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Virtex dual-port memory ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_xcv_ram32x8d.v,v $
// Revision 1.2 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
`ifdef OR1200_XILINX_RAM32X1D
`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
module or1200_xcv_ram32x8d
(
DPO,
SPO,
A,
D,
DPRA,
WCLK,
WE
);
output [7:0] DPO;
output [7:0] SPO;
input [4:0] A;
input [4:0] DPRA;
input [7:0] D;
input WCLK;
input WE;
wire [7:0] DPO_0;
wire [7:0] SPO_0;
wire [7:0] DPO_1;
wire [7:0] SPO_1;
wire WE_0 ;
wire WE_1 ;
assign DPO = DPRA[4] ? DPO_1 : DPO_0 ;
assign SPO = A[4] ? SPO_1 : SPO_0 ;
assign WE_0 = !A[4] && WE ;
assign WE_1 = A[4] && WE ;
RAM16X1D ram32x1d_0_0(
.DPO(DPO_0[0]),
.SPO(SPO_0[0]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[0]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
//
// Instantiation of block 1
//
RAM16X1D ram32x1d_0_1(
.DPO(DPO_0[1]),
.SPO(SPO_0[1]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[1]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
//
// Instantiation of block 2
//
RAM16X1D ram32x1d_0_2(
.DPO(DPO_0[2]),
.SPO(SPO_0[2]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[2]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
//
// Instantiation of block 3
//
RAM16X1D ram32x1d_0_3(
.DPO(DPO_0[3]),
.SPO(SPO_0[3]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[3]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
//
// Instantiation of block 4
//
RAM16X1D ram32x1d_0_4(
.DPO(DPO_0[4]),
.SPO(SPO_0[4]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[4]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
//
// Instantiation of block 5
//
RAM16X1D ram32x1d_0_5(
.DPO(DPO_0[5]),
.SPO(SPO_0[5]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[5]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
//
// Instantiation of block 6
//
RAM16X1D ram32x1d_0_6(
.DPO(DPO_0[6]),
.SPO(SPO_0[6]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[6]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
//
// Instantiation of block 7
//
RAM16X1D ram32x1d_0_7(
.DPO(DPO_0[7]),
.SPO(SPO_0[7]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[7]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
RAM16X1D ram32x1d_1_0(
.DPO(DPO_1[0]),
.SPO(SPO_1[0]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[0]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
//
// Instantiation of block 1
//
RAM16X1D ram32x1d_1_1(
.DPO(DPO_1[1]),
.SPO(SPO_1[1]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[1]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
//
// Instantiation of block 2
//
RAM16X1D ram32x1d_1_2(
.DPO(DPO_1[2]),
.SPO(SPO_1[2]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[2]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
//
// Instantiation of block 3
//
RAM16X1D ram32x1d_1_3(
.DPO(DPO_1[3]),
.SPO(SPO_1[3]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[3]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
//
// Instantiation of block 4
//
RAM16X1D ram32x1d_1_4(
.DPO(DPO_1[4]),
.SPO(SPO_1[4]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[4]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
//
// Instantiation of block 5
//
RAM16X1D ram32x1d_1_5(
.DPO(DPO_1[5]),
.SPO(SPO_1[5]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[5]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
//
// Instantiation of block 6
//
RAM16X1D ram32x1d_1_6(
.DPO(DPO_1[6]),
.SPO(SPO_1[6]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[6]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
//
// Instantiation of block 7
//
RAM16X1D ram32x1d_1_7(
.DPO(DPO_1[7]),
.SPO(SPO_1[7]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[7]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
endmodule
`else
module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
//
// I/O
//
output [7:0] DPO;
output [7:0] SPO;
input [4:0] A;
input [4:0] DPRA;
input [7:0] D;
input WCLK;
input WE;
//
// Instantiation of block 0
//
RAM32X1D ram32x1d_0(
.DPO(DPO[0]),
.SPO(SPO[0]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.A4(A[4]),
.D(D[0]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.DPRA4(DPRA[4]),
.WCLK(WCLK),
.WE(WE)
);
//
// Instantiation of block 1
//
RAM32X1D ram32x1d_1(
.DPO(DPO[1]),
.SPO(SPO[1]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.A4(A[4]),
.D(D[1]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.DPRA4(DPRA[4]),
.WCLK(WCLK),
.WE(WE)
);
//
// Instantiation of block 2
//
RAM32X1D ram32x1d_2(
.DPO(DPO[2]),
.SPO(SPO[2]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.A4(A[4]),
.D(D[2]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.DPRA4(DPRA[4]),
.WCLK(WCLK),
.WE(WE)
);
//
// Instantiation of block 3
//
RAM32X1D ram32x1d_3(
.DPO(DPO[3]),
.SPO(SPO[3]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.A4(A[4]),
.D(D[3]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.DPRA4(DPRA[4]),
.WCLK(WCLK),
.WE(WE)
);
//
// Instantiation of block 4
//
RAM32X1D ram32x1d_4(
.DPO(DPO[4]),
.SPO(SPO[4]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.A4(A[4]),
.D(D[4]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.DPRA4(DPRA[4]),
.WCLK(WCLK),
.WE(WE)
);
//
// Instantiation of block 5
//
RAM32X1D ram32x1d_5(
.DPO(DPO[5]),
.SPO(SPO[5]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.A4(A[4]),
.D(D[5]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.DPRA4(DPRA[4]),
.WCLK(WCLK),
.WE(WE)
);
//
// Instantiation of block 6
//
RAM32X1D ram32x1d_6(
.DPO(DPO[6]),
.SPO(SPO[6]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.A4(A[4]),
.D(D[6]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.DPRA4(DPRA[4]),
.WCLK(WCLK),
.WE(WE)
);
//
// Instantiation of block 7
//
RAM32X1D ram32x1d_7(
.DPO(DPO[7]),
.SPO(SPO[7]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.A4(A[4]),
.D(D[7]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.DPRA4(DPRA[4]),
.WCLK(WCLK),
.WE(WE)
);
endmodule
`endif
`endif
|
`include "defines.v"
`timescale 1ns/1ps
module openmips_min_sopc_tb();
reg CLOCK_50;
reg rst;
//integer file_output;
initial begin
//file_output = $fopen("D:/Computer Architecture/My-CPU/TestResult/beq.txt");
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = `RstEnable;
#195 rst= `RstDisable;
#1000000000 $stop;
end
openmips_min_sopc openmips_min_sopc0(
.clk(CLOCK_50),
.rst(rst)
);
/*always@(posedge CLOCK_50) begin
$fdisplay(file_output,"pc = %h", openmips_min_sopc0.openmips0.id0.pc_i);
$fdisplay(file_output,"instr = %h", openmips_min_sopc0.openmips0.id0.inst_i);
$fdisplay(file_output,"regfiles0 = %h", openmips_min_sopc0.openmips0.regfile1.regs[0]);
$fdisplay(file_output,"regfiles1 = %h", openmips_min_sopc0.openmips0.regfile1.regs[1]);
$fdisplay(file_output,"regfiles2 = %h", openmips_min_sopc0.openmips0.regfile1.regs[2]);
$fdisplay(file_output,"regfiles3 = %h", openmips_min_sopc0.openmips0.regfile1.regs[3]);
$fdisplay(file_output,"regfiles4 = %h", openmips_min_sopc0.openmips0.regfile1.regs[4]);
$fdisplay(file_output,"regfiles5 = %h", openmips_min_sopc0.openmips0.regfile1.regs[5]);
$fdisplay(file_output,"regfiles6 = %h", openmips_min_sopc0.openmips0.regfile1.regs[6]);
$fdisplay(file_output,"regfiles7 = %h", openmips_min_sopc0.openmips0.regfile1.regs[7]);
$fdisplay(file_output,"regfiles8 = %h", openmips_min_sopc0.openmips0.regfile1.regs[8]);
$fdisplay(file_output,"regfiles9 = %h", openmips_min_sopc0.openmips0.regfile1.regs[9]);
$fdisplay(file_output,"regfiles10 = %h", openmips_min_sopc0.openmips0.regfile1.regs[10]);
$fdisplay(file_output,"regfiles11 = %h", openmips_min_sopc0.openmips0.regfile1.regs[11]);
$fdisplay(file_output,"regfiles12 = %h", openmips_min_sopc0.openmips0.regfile1.regs[12]);
$fdisplay(file_output,"regfiles13 = %h", openmips_min_sopc0.openmips0.regfile1.regs[13]);
$fdisplay(file_output,"regfiles14 = %h", openmips_min_sopc0.openmips0.regfile1.regs[14]);
$fdisplay(file_output,"regfiles15 = %h", openmips_min_sopc0.openmips0.regfile1.regs[15]);
$fdisplay(file_output,"regfiles16 = %h", openmips_min_sopc0.openmips0.regfile1.regs[16]);
$fdisplay(file_output,"regfiles17 = %h", openmips_min_sopc0.openmips0.regfile1.regs[17]);
$fdisplay(file_output,"regfiles18 = %h", openmips_min_sopc0.openmips0.regfile1.regs[18]);
$fdisplay(file_output,"regfiles19 = %h", openmips_min_sopc0.openmips0.regfile1.regs[19]);
$fdisplay(file_output,"regfiles20 = %h", openmips_min_sopc0.openmips0.regfile1.regs[20]);
$fdisplay(file_output,"regfiles21 = %h", openmips_min_sopc0.openmips0.regfile1.regs[21]);
$fdisplay(file_output,"regfiles22 = %h", openmips_min_sopc0.openmips0.regfile1.regs[22]);
$fdisplay(file_output,"regfiles23 = %h", openmips_min_sopc0.openmips0.regfile1.regs[23]);
$fdisplay(file_output,"regfiles24 = %h", openmips_min_sopc0.openmips0.regfile1.regs[24]);
$fdisplay(file_output,"regfiles25 = %h", openmips_min_sopc0.openmips0.regfile1.regs[25]);
$fdisplay(file_output,"regfiles26 = %h", openmips_min_sopc0.openmips0.regfile1.regs[26]);
$fdisplay(file_output,"regfiles27 = %h", openmips_min_sopc0.openmips0.regfile1.regs[27]);
$fdisplay(file_output,"regfiles28 = %h", openmips_min_sopc0.openmips0.regfile1.regs[28]);
$fdisplay(file_output,"regfiles29 = %h", openmips_min_sopc0.openmips0.regfile1.regs[29]);
$fdisplay(file_output,"regfiles30 = %h", openmips_min_sopc0.openmips0.regfile1.regs[30]);
$fdisplay(file_output,"regfiles31 = %h", openmips_min_sopc0.openmips0.regfile1.regs[31]);
end
*/
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O22AI_FUNCTIONAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_FUNCTIONAL_PP_V |
module opicorv32_mul_wrap (
pcpi_rs2,
pcpi_rs1,
pcpi_insn,
pcpi_valid,
resetn,
clk,
pcpi_wr,
pcpi_rd,
pcpi_wait,
pcpi_ready
);
input [31:0] pcpi_rs2;
input [31:0] pcpi_rs1;
input [31:0] pcpi_insn;
input pcpi_valid;
input resetn;
input clk;
output pcpi_wr;
output [31:0] pcpi_rd;
output pcpi_wait;
output pcpi_ready;
/* signal declarations */
wire _1746;
wire _1742;
wire compare_pcpi_ready;
wire _1748;
wire _1749;
wire _1743;
wire compare_pcpi_wait;
wire _1751;
wire [31:0] _1752;
wire [31:0] _1744;
wire [31:0] compare_pcpi_rd;
wire [31:0] _1754;
wire [34:0] _1739;
wire _1755;
wire [34:0] _1741;
wire _1745;
wire compare_pcpi_wr;
wire _1757;
/* logic */
assign _1746 = _1739[34:34];
assign _1742 = _1741[34:34];
assign compare_pcpi_ready = _1742 ^ _1746;
assign _1748 = compare_pcpi_ready ^ _1746;
assign _1749 = _1739[33:33];
assign _1743 = _1741[33:33];
assign compare_pcpi_wait = _1743 ^ _1749;
assign _1751 = compare_pcpi_wait ^ _1749;
assign _1752 = _1739[32:1];
assign _1744 = _1741[32:1];
assign compare_pcpi_rd = _1744 ^ _1752;
assign _1754 = compare_pcpi_rd ^ _1752;
picorv32_mul
the_picorv32_mul
( .clk(clk), .resetn(resetn), .pcpi_valid(pcpi_valid), .pcpi_insn(pcpi_insn), .pcpi_rs1(pcpi_rs1), .pcpi_rs2(pcpi_rs2), .pcpi_ready(_1739[34:34]), .pcpi_wait(_1739[33:33]), .pcpi_rd(_1739[32:1]), .pcpi_wr(_1739[0:0]) );
assign _1755 = _1739[0:0];
opicorv32_mul
the_opicorv32_mul
( .clk(clk), .resetn(resetn), .pcpi_valid(pcpi_valid), .pcpi_insn(pcpi_insn), .pcpi_rs1(pcpi_rs1), .pcpi_rs2(pcpi_rs2), .pcpi_ready(_1741[34:34]), .pcpi_wait(_1741[33:33]), .pcpi_rd(_1741[32:1]), .pcpi_wr(_1741[0:0]) );
assign _1745 = _1741[0:0];
assign compare_pcpi_wr = _1745 ^ _1755;
assign _1757 = compare_pcpi_wr ^ _1755;
/* aliases */
/* output assignments */
assign pcpi_wr = _1757;
assign pcpi_rd = _1754;
assign pcpi_wait = _1751;
assign pcpi_ready = _1748;
endmodule
|
// -*- Mode: Verilog -*-
// Filename : testbench_testing_wb_slave.v
// Description : Testbench for testing Wishbone Slave module
// Author : Philip Tracton
// Created On : Fri Nov 27 13:49:59 2015
// Last Modified By: Philip Tracton
// Last Modified On: Fri Nov 27 13:49:59 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`include "timescale.v"
module testbench_testing_wb_slave (/*AUTOARG*/ ) ;
`include "test_management.v"
wire wb_clk;
wire wb_rst;
syscon system_controller(
// Outputs
.wb_clk_o(wb_clk),
.wb_rst_o(wb_rst),
// Inputs
.clk_pad_i(clk),
.rst_pad_i(reset)
) ;
`include "wb_switch1.vh"
wb_bfm_master master0(
.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst),
.wb_adr_o(wb_m2s_master0_adr),
.wb_dat_o(wb_m2s_master0_dat),
.wb_sel_o(wb_m2s_master0_sel),
.wb_we_o(wb_m2s_master0_we),
.wb_cyc_o(wb_m2s_master0_cyc),
.wb_stb_o(wb_m2s_master0_stb),
.wb_cti_o(wb_m2s_master0_cti),
.wb_bte_o(wb_m2s_master0_bte),
.wb_dat_i(wb_s2m_master0_dat),
.wb_ack_i(wb_s2m_master0_ack),
.wb_err_i(wb_s2m_master0_err),
.wb_rty_i(wb_s2m_master0_rty));
testing_wb_slave slave0 (/*AUTOARG*/
// Outputs
.wb_dat_o(wb_s2m_wb_slave0_dat),
.wb_ack_o(wb_s2m_wb_slave0_ack),
.wb_err_o(wb_s2m_wb_slave0_err),
.wb_rty_o(wb_s2m_wb_slave0_rty),
// Inputs
.wb_clk(wb_clk),
.wb_rst(wb_rst),
.wb_adr_i(wb_m2s_wb_slave0_adr),
.wb_dat_i(wb_m2s_wb_slave0_dat),
.wb_sel_i(wb_m2s_wb_slave0_sel),
.wb_we_i(wb_m2s_wb_slave0_we),
.wb_cyc_i(wb_m2s_wb_slave0_cyc),
.wb_stb_i(wb_m2s_wb_slave0_stb),
.wb_cti_i(wb_m2s_wb_slave0_cti),
.wb_bte_i(wb_m2s_wb_slave0_bte)
) ;
testing_wb_slave slave1 (/*AUTOARG*/
// Outputs
.wb_dat_o(wb_s2m_wb_slave1_dat),
.wb_ack_o(wb_s2m_wb_slave1_ack),
.wb_err_o(wb_s2m_wb_slave1_err),
.wb_rty_o(wb_s2m_wb_slave1_rty),
// Inputs
.wb_clk(wb_clk),
.wb_rst(wb_rst),
.wb_adr_i(wb_m2s_wb_slave1_adr),
.wb_dat_i(wb_m2s_wb_slave1_dat),
.wb_sel_i(wb_m2s_wb_slave1_sel),
.wb_we_i(wb_m2s_wb_slave1_we),
.wb_cyc_i(wb_m2s_wb_slave1_cyc),
.wb_stb_i(wb_m2s_wb_slave1_stb),
.wb_cti_i(wb_m2s_wb_slave1_cti),
.wb_bte_i(wb_m2s_wb_slave1_bte)
) ;
reg err;
reg [31:0] data_out;
initial begin
#100 $display("Simulation Running");
master0.reset();
master0.write(32'h9000_0000, 32'hdead_beef, 4'hF, err);
master0.write(32'h9000_0004, 32'hf00d_d00f, 4'hF, err);
master0.write(32'h9000_0008, 32'h0123_4567, 4'hF, err);
master0.write(32'h9000_000C, 32'h89AB_CDEF, 4'hF, err);
master0.read_burst(32'h9000_0000, data_out, 4'hF, 32'h0, 4'h0, err);
@(posedge wb_clk);
master0.read_burst(32'h9000_0004, data_out, 4'hF, 32'h0, 4'h0, err);
@(posedge wb_clk);
master0.read_burst(32'h9000_0008, data_out, 4'hF, 32'h0, 4'h0, err);
@(posedge wb_clk);
master0.read_burst(32'h9000_000C, data_out, 4'hF, 32'h0, 4'h0, err);
@(posedge wb_clk);
master0.write(32'h9000_0000, 32'h0000_0011, 4'h1, err);
master0.read_burst(32'h9000_0000, data_out, 4'h1, 32'h1, 4'h0, err);
@(posedge wb_clk);
if (data_out != 32'hdead_be11)begin
test_failed <= 1;
end
master0.write(32'h9000_0000, 32'h0000_2200, 4'h2, err);
master0.read_burst(32'h9000_0000, data_out, 4'h2, 32'h1, 4'h0, err);
@(posedge wb_clk);
if (data_out != 32'hdead_2211)begin
test_failed <= 1;
end
master0.write(32'h9000_0000, 32'h0033_0000, 4'h4, err);
master0.read_burst(32'h9000_0000, data_out, 4'h4, 32'h1, 4'h0, err);
@(posedge wb_clk);
if (data_out != 32'hde33_2211)begin
test_failed <= 1;
end
master0.write(32'h9000_0000, 32'h4400_0000, 4'h8, err);
master0.read_burst(32'h9000_0000, data_out, 4'h8, 32'h1, 4'h0, err);
@(posedge wb_clk);
if (data_out != 32'h4433_2211)begin
test_failed <= 1;
end
#1000 $finish;
end
endmodule // testbench_testing_wb_slave
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 1ns/100ps
module InstructionTest;
reg clk_50mhz;
reg clk_1mhz;
reg rst_x;
reg r_init;
reg r_rdy;
reg r_irq_x;
reg r_nmi_x;
reg [15:0] r_cycle;
reg [15:0] r_decode_cycle;
reg [15:0] r_decode_pc;
wire w_2ram_write_x;
wire [15:0] w_2ram_addr;
wire [ 7:0] w_2ram_data;
wire [ 7:0] w_ram2_data;
wire [ 7:0] w_dut_db;
wire w_dut2_clk1;
wire w_dut2_clk2;
wire w_dut2_sync;
wire [15:0] w_dut2_addr;
wire w_dut2_write_x;
integer i_addr;
integer i_data;
RAM_64Kx8 ram(
.i_addr (w_2ram_addr ),
.i_enable_x(1'b0 ),
.i_write_x (w_2ram_write_x ),
.i_data (w_2ram_data ),
.o_data (w_ram2_data ));
MC6502 dut(
.clk (clk_1mhz ),
.rst_x (rst_x ),
.i_rdy (r_rdy ),
.i_irq_x (r_irq_x ),
.i_nmi_x (r_nmi_x ),
.io_db (w_dut_db ),
.o_clk1 (w_dut2_clk1 ),
.o_clk2 (w_dut2_clk2 ),
.o_sync (w_dut2_sync ),
.o_rw (w_dut2_write_x ),
.o_ab (w_dut2_addr ));
assign w_2ram_addr = r_init ? i_addr[15:0] : w_dut2_addr;
assign w_2ram_data = r_init ? i_data[7:0] : w_dut_db;
assign w_2ram_write_x = r_init ? 1'b0 : w_dut2_write_x;
assign w_dut_db = w_dut2_write_x ? w_ram2_data : 8'hzz;
always #10 clk_50mhz = !clk_50mhz; // 20ns cycle
always #500 clk_1mhz = !clk_1mhz; // 1ms cycle
always @ (posedge clk_1mhz or negedge rst_x) begin
if (!rst_x) begin
r_cycle <= 16'h0000;
r_decode_cycle <= 16'h0000;
r_decode_pc <= 16'h0000;
end else begin
if (!r_init) begin
r_cycle <= r_cycle + 16'h0001;
end
if (w_dut2_sync) begin
r_decode_cycle <= r_cycle;
r_decode_pc <= { dut.rf.r_pch, dut.rf.r_pcl };
end
end
end
always @ (posedge clk_1mhz) begin
if (!r_init) begin
if (w_dut2_sync) begin
$display("[%04x]: +%1dt", r_cycle, r_cycle - r_decode_cycle);
$display({ "[%04x]: *** dump *** PC=$%04x A=$%02x X=$%02x Y=$%02x ",
"SP=$%02x NPC=$%04x NV-B_DIZC=%04b_%04b" }, r_cycle,
r_decode_pc, dut.rf.r_a, dut.rf.r_x, dut.rf.r_y,
dut.rf.r_sp, { dut.rf.r_pch, dut.rf.r_pcl },
dut.rf.w_psr[7:4], dut.rf.w_psr[3:0]);
if (w_ram2_data == 8'hff) begin
$finish;
end
end // if (w_dut2_sync)
if (w_2ram_write_x) begin
$display("[%04x]: $%04x => $%02x", r_cycle, w_dut2_addr, w_ram2_data);
end else begin
$display("[%04x]: $%04x <= $%02x", r_cycle, w_dut2_addr, w_2ram_data);
end // if (w_2ram_write_x)
if (w_dut2_sync) begin
$display("[%04x]: decode: $%02x (%04b_%04b)", r_cycle, w_ram2_data,
w_ram2_data[7:4], w_ram2_data[3:0]);
if (dut.id.w_unknown_instruction) begin
$display("[%04x]: unknown instruction", r_cycle);
$finish;
end
if ((r_decode_pc != 16'h0000) & (r_decode_pc == dut.w_rf2mc_pc)) begin
$display("[%04x]: infinite loop", r_cycle);
$finish;
end
end // if (w_dut2_sync)
end
end
initial begin
clk_50mhz <= 1'b0;
clk_1mhz <= 1'b0;
end
initial $readmemb(`TEST, ram.ram.r_ram);
initial begin
// Set RESET vector to 16'h0000
i_addr <= 16'hfffc;
i_data <= 8'h00;
#1000
i_addr <= 16'hfffd;
i_data <= 8'h00;
#1000
r_init <= 1'b0;
end
initial begin
$dumpfile({`TEST, ".vcd"});
$dumpvars(0, clk_50mhz);
$dumpvars(0, clk_1mhz);
$dumpvars(0, r_init);
$dumpvars(0, ram);
$dumpvars(0, dut);
r_rdy <= 1'b1;
r_irq_x <= 1'b1;
r_nmi_x <= 1'b1;
rst_x <= 1'b0;
r_init <= 1'b1;
#1000
while (r_init != 1'b0) begin
#1000
rst_x <= 1'b0;
end
rst_x <= 1'b1;
#100000
$finish;
end
endmodule // InstructionTest
|
`timescale 1ns / 1ps
module TB_BRAM;
// Inputs
reg clka;
reg [0:0] wea;
reg [3:0] addra;
reg [7:0] dina;
// Outputs
wire [7:0] douta;
// Instantiate the Unit Under Test (UUT)
bram_16x8 uut (
.clka(clka),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta)
);
initial begin
// Initialize Inputs
clka = 0;
wea = 0;
addra = 0;
dina = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
$display("LEEMOS");
wea = 0;
addra=4'h0; #100;
addra=4'h1; #100;
addra=4'h2; #100;
addra=4'h3; #100;
addra=4'h4; #100;
addra=4'h5; #100;
addra=4'h6; #100;
addra=4'h7; #100;
addra=4'h8; #100;
addra=4'h9; #100;
addra=4'hA; #100;
addra=4'hB; #100;
addra=4'hC; #100;
addra=4'hD; #100;
addra=4'hE; #100;
addra=4'hF; #100;
$display("ESCRIBIMOS");
wea = 1;
addra=4'h0; dina = 8'd0; #100;
addra=4'h1; dina = 8'd1; #100;
addra=4'h2; dina = 8'd2; #100;
addra=4'h3; dina = 8'd3; #100;
addra=4'h4; dina = 8'd4; #100;
addra=4'h5; dina = 8'd5; #100;
addra=4'h6; dina = 8'd6; #100;
addra=4'h7; dina = 8'd7; #100;
addra=4'h8; dina = 8'd8; #100;
addra=4'h9; dina = 8'd9; #100;
addra=4'hA; dina = 8'd10; #100;
addra=4'hB; dina = 8'd11; #100;
addra=4'hC; dina = 8'd12; #100;
addra=4'hD; dina = 8'd13; #100;
addra=4'hE; dina = 8'd14; #100;
addra=4'hF; dina = 8'd15; #100;
$display("LEEMOS");
wea = 0;
addra=4'h0; #100;
addra=4'h1; #100;
addra=4'h2; #100;
addra=4'h3; #100;
addra=4'h4; #100;
addra=4'h5; #100;
addra=4'h6; #100;
addra=4'h7; #100;
addra=4'h8; #100;
addra=4'h9; #100;
addra=4'hA; #100;
addra=4'hB; #100;
addra=4'hC; #100;
addra=4'hD; #100;
addra=4'hE; #100;
addra=4'hF; #100;
$stop ;
end
always
#10 clka = ! clka;
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// SIMULATION - UNUSED
// Latches and buffers on the 68K bus for MVS cab I/Os
// 273s and 245s on the verification board
// Signals: nBITWD0, nDIPRD0, nLED_LATCH, nLED_DATA
module cab_io(
input [7:4] M68K_ADDR,
inout [7:0] M68K_DATA,
output [3:0] EL_OUT,
output [8:0] LED_OUT1,
output [8:0] LED_OUT2
);
assign EL_OUT = {LEDLATCH[0], LEDDATA[2:0]};
assign LED_OUT1 = {LEDLATCH[1], LEDDATA};
assign LED_OUT2 = {LEDLATCH[2], LEDDATA};
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:57:13 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87,
n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166,
n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n187, n188, n189,
n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200,
n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211,
n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222,
n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244,
n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266,
n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299,
n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310,
n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321,
n322, n323, n324, n325, n326, n327, n328, n329, n330, n331, n332,
n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, n343,
n344, n345, n346, n347, n348, n349, n350, n351, n352, n353;
NAND2X1TS U35 ( .A(n62), .B(n195), .Y(n192) );
INVX2TS U36 ( .A(n52), .Y(n207) );
NAND2X1TS U37 ( .A(n205), .B(n204), .Y(n206) );
NAND2X1TS U38 ( .A(n239), .B(n238), .Y(n240) );
NAND2X1TS U39 ( .A(n245), .B(n244), .Y(n246) );
NAND2X1TS U40 ( .A(n252), .B(n251), .Y(n253) );
AOI21X2TS U41 ( .A0(n258), .A1(n243), .B0(n242), .Y(n247) );
AOI21X2TS U42 ( .A0(n258), .A1(n256), .B0(n249), .Y(n254) );
CMPR32X2TS U43 ( .A(in1[6]), .B(n328), .C(n320), .CO(n318), .S(res[6]) );
NAND2X1TS U44 ( .A(n202), .B(in1[31]), .Y(n203) );
CLKINVX1TS U45 ( .A(n232), .Y(n245) );
NOR2X1TS U46 ( .A(n336), .B(in1[8]), .Y(n349) );
NAND2X4TS U47 ( .A(n59), .B(n184), .Y(n58) );
NAND2X1TS U48 ( .A(n182), .B(in1[28]), .Y(n212) );
INVX4TS U49 ( .A(n164), .Y(n59) );
CLKMX2X2TS U50 ( .A(in2[30]), .B(n190), .S0(add_sub), .Y(n191) );
MX2X1TS U51 ( .A(in2[29]), .B(n187), .S0(add_sub), .Y(n188) );
CMPR32X2TS U52 ( .A(in1[1]), .B(n70), .C(n69), .CO(n300), .S(res[1]) );
CLKMX2X2TS U53 ( .A(in2[5]), .B(n316), .S0(n315), .Y(n323) );
NAND2X2TS U54 ( .A(n158), .B(in1[22]), .Y(n251) );
NAND2X2TS U55 ( .A(n137), .B(in1[19]), .Y(n265) );
CLKMX2X2TS U56 ( .A(in2[27]), .B(n174), .S0(n315), .Y(n180) );
NOR2X4TS U57 ( .A(n137), .B(in1[19]), .Y(n264) );
NAND2BX1TS U58 ( .AN(in2[29]), .B(n189), .Y(n199) );
CLKMX2X4TS U59 ( .A(in2[21]), .B(n151), .S0(n315), .Y(n157) );
NOR2X2TS U60 ( .A(n147), .B(n185), .Y(n176) );
NOR3X4TS U61 ( .A(n147), .B(in2[28]), .C(n185), .Y(n189) );
NOR2X2TS U62 ( .A(n147), .B(n175), .Y(n173) );
NAND2X4TS U63 ( .A(n65), .B(n270), .Y(n128) );
OR2X6TS U64 ( .A(n123), .B(in1[17]), .Y(n65) );
NAND2X1TS U65 ( .A(n172), .B(n171), .Y(n175) );
NOR2X2TS U66 ( .A(n153), .B(n152), .Y(n154) );
NOR2X2TS U67 ( .A(n153), .B(in2[20]), .Y(n150) );
NOR2X4TS U68 ( .A(n147), .B(in2[24]), .Y(n168) );
NAND2X6TS U69 ( .A(n101), .B(in1[13]), .Y(n290) );
NOR2X6TS U70 ( .A(n101), .B(in1[13]), .Y(n289) );
NOR2X2TS U71 ( .A(in2[25]), .B(in2[24]), .Y(n172) );
CLKINVX2TS U72 ( .A(n147), .Y(n165) );
MX2X4TS U73 ( .A(in2[13]), .B(n98), .S0(n302), .Y(n101) );
MXI2X2TS U74 ( .A(n105), .B(n100), .S0(n302), .Y(n102) );
NOR2X2TS U75 ( .A(n14), .B(n13), .Y(n95) );
NAND2X8TS U76 ( .A(n146), .B(n145), .Y(n147) );
NOR2X2TS U77 ( .A(n22), .B(n47), .Y(n14) );
NOR2X2TS U78 ( .A(n22), .B(n7), .Y(n12) );
NAND2X2TS U79 ( .A(n89), .B(in1[11]), .Y(n341) );
OR2X4TS U80 ( .A(n83), .B(in1[9]), .Y(n339) );
OR2X2TS U81 ( .A(in2[21]), .B(in2[20]), .Y(n152) );
NAND2X1TS U82 ( .A(n105), .B(n111), .Y(n112) );
NAND2X6TS U83 ( .A(n99), .B(n107), .Y(n113) );
NOR2X1TS U84 ( .A(in2[19]), .B(in2[18]), .Y(n133) );
INVX2TS U85 ( .A(in2[14]), .Y(n105) );
BUFX4TS U86 ( .A(add_sub), .Y(n302) );
INVX2TS U87 ( .A(n306), .Y(n71) );
INVX8TS U88 ( .A(add_sub), .Y(n88) );
AND2X6TS U89 ( .A(n80), .B(n306), .Y(n81) );
INVX8TS U90 ( .A(in2[2]), .Y(n44) );
NOR2X2TS U91 ( .A(in2[11]), .B(in2[10]), .Y(n91) );
NOR2X1TS U92 ( .A(n71), .B(n79), .Y(n74) );
INVX2TS U93 ( .A(n315), .Y(n47) );
CLKXOR2X2TS U94 ( .A(n168), .B(in2[25]), .Y(n169) );
NOR2X1TS U95 ( .A(n309), .B(in2[6]), .Y(n307) );
NAND2X2TS U96 ( .A(n16), .B(n18), .Y(n15) );
MXI2X2TS U97 ( .A(n136), .B(n135), .S0(add_sub), .Y(n138) );
CLKMX2X2TS U98 ( .A(in2[28]), .B(n177), .S0(add_sub), .Y(n182) );
NAND2X1TS U99 ( .A(n138), .B(in1[20]), .Y(n260) );
INVX2TS U100 ( .A(n237), .Y(n239) );
AOI21X1TS U101 ( .A0(n65), .A1(n35), .B0(n268), .Y(n272) );
ADDHXLTS U102 ( .A(in2[0]), .B(in1[0]), .CO(n69), .S(res[0]) );
NOR2X4TS U103 ( .A(n264), .B(n259), .Y(n140) );
XNOR2X2TS U104 ( .A(n166), .B(in2[26]), .Y(n167) );
NAND2X2TS U105 ( .A(n165), .B(n172), .Y(n166) );
NOR2X4TS U106 ( .A(in2[13]), .B(in2[12]), .Y(n107) );
INVX2TS U107 ( .A(in2[15]), .Y(n111) );
XOR2X1TS U108 ( .A(n241), .B(n240), .Y(res[24]) );
NOR2X2TS U109 ( .A(n10), .B(n204), .Y(n27) );
INVX2TS U110 ( .A(n195), .Y(n196) );
INVX2TS U111 ( .A(n62), .Y(n10) );
NAND2X2TS U112 ( .A(n62), .B(n205), .Y(n198) );
OR2X4TS U113 ( .A(n191), .B(in1[30]), .Y(n62) );
OAI21X2TS U114 ( .A0(n265), .A1(n259), .B0(n260), .Y(n139) );
NOR2X2TS U115 ( .A(n129), .B(in2[18]), .Y(n130) );
NAND2X2TS U116 ( .A(n51), .B(n86), .Y(n50) );
INVX2TS U117 ( .A(n21), .Y(n13) );
INVX12TS U118 ( .A(n88), .Y(n315) );
CLKINVX6TS U119 ( .A(in2[8]), .Y(n42) );
OR2X4TS U120 ( .A(n197), .B(n56), .Y(n53) );
NOR2X4TS U121 ( .A(n210), .B(n211), .Y(n184) );
NOR2X4TS U122 ( .A(n196), .B(n27), .Y(n197) );
NOR2X2TS U123 ( .A(n198), .B(n56), .Y(n55) );
NAND2X4TS U124 ( .A(n216), .B(n64), .Y(n210) );
INVX8TS U125 ( .A(n128), .Y(n37) );
MX2X2TS U126 ( .A(in2[31]), .B(n201), .S0(add_sub), .Y(n202) );
NAND3X6TS U127 ( .A(n17), .B(n294), .C(n15), .Y(n283) );
NOR2X4TS U128 ( .A(n248), .B(n250), .Y(n243) );
NOR2X4TS U129 ( .A(n158), .B(in1[22]), .Y(n250) );
INVX2TS U130 ( .A(n269), .Y(n125) );
NAND2X4TS U131 ( .A(n336), .B(in1[8]), .Y(n350) );
XOR2X1TS U132 ( .A(n314), .B(in2[5]), .Y(n316) );
CLKMX2X2TS U133 ( .A(in2[3]), .B(n299), .S0(n315), .Y(n305) );
OR2X2TS U134 ( .A(n47), .B(in1[12]), .Y(n7) );
XOR2X1TS U135 ( .A(n254), .B(n253), .Y(res[22]) );
INVX6TS U136 ( .A(n31), .Y(n30) );
OAI21X2TS U137 ( .A0(n209), .A1(n211), .B0(n212), .Y(n183) );
AND2X2TS U138 ( .A(n224), .B(n223), .Y(n9) );
NAND2X6TS U139 ( .A(n36), .B(n127), .Y(n34) );
XOR2X1TS U140 ( .A(n293), .B(n292), .Y(res[13]) );
NAND2X6TS U141 ( .A(n37), .B(n117), .Y(n36) );
NAND2X2TS U142 ( .A(n191), .B(in1[30]), .Y(n195) );
AND2X2TS U143 ( .A(n64), .B(n220), .Y(n8) );
XOR2X1TS U144 ( .A(n296), .B(n295), .Y(res[12]) );
INVX2TS U145 ( .A(n250), .Y(n252) );
XOR2X1TS U146 ( .A(n348), .B(n347), .Y(res[10]) );
OR2X4TS U147 ( .A(n180), .B(in1[27]), .Y(n64) );
NAND3X4TS U148 ( .A(n3), .B(n18), .C(n24), .Y(n17) );
NOR2X4TS U149 ( .A(n138), .B(in1[20]), .Y(n259) );
NAND2X4TS U150 ( .A(n19), .B(n341), .Y(n16) );
XOR2X1TS U151 ( .A(n353), .B(n352), .Y(res[8]) );
NAND2X4TS U152 ( .A(n95), .B(in1[12]), .Y(n294) );
OR2X2TS U153 ( .A(n116), .B(in1[16]), .Y(n63) );
NAND2X2TS U154 ( .A(n102), .B(in1[14]), .Y(n285) );
NOR2X2TS U155 ( .A(n118), .B(in2[16]), .Y(n119) );
NAND2X4TS U156 ( .A(n339), .B(n85), .Y(n25) );
NOR2X1TS U157 ( .A(n323), .B(in1[5]), .Y(n326) );
MX2X2TS U158 ( .A(in2[7]), .B(n308), .S0(n315), .Y(n329) );
NOR4X4TS U159 ( .A(n144), .B(n152), .C(in2[23]), .D(in2[22]), .Y(n145) );
INVX8TS U160 ( .A(n208), .Y(n230) );
XOR2X1TS U161 ( .A(n221), .B(n8), .Y(res[27]) );
NAND2X4TS U162 ( .A(n162), .B(n243), .Y(n164) );
NAND2X4TS U163 ( .A(n342), .B(n20), .Y(n19) );
XOR2X4TS U164 ( .A(n51), .B(in2[10]), .Y(n45) );
XOR2X1TS U165 ( .A(n225), .B(n9), .Y(res[26]) );
AOI21X2TS U166 ( .A0(n258), .A1(n236), .B0(n235), .Y(n241) );
INVX6TS U167 ( .A(n231), .Y(n258) );
AOI21X4TS U168 ( .A0(n162), .A1(n242), .B0(n161), .Y(n163) );
OAI21X2TS U169 ( .A0(n244), .A1(n237), .B0(n238), .Y(n161) );
NOR2X4TS U170 ( .A(n94), .B(n90), .Y(n51) );
XOR2X2TS U171 ( .A(n154), .B(in2[22]), .Y(n155) );
NOR2X6TS U172 ( .A(in2[7]), .B(in2[6]), .Y(n80) );
NOR2X4TS U173 ( .A(n102), .B(in1[14]), .Y(n284) );
OAI21X4TS U174 ( .A0(n250), .A1(n255), .B0(n251), .Y(n242) );
NAND2X2TS U175 ( .A(n110), .B(in1[15]), .Y(n280) );
MX2X4TS U176 ( .A(in2[15]), .B(n109), .S0(n302), .Y(n110) );
XOR2X2TS U177 ( .A(n108), .B(in2[15]), .Y(n109) );
NAND2X2TS U178 ( .A(n106), .B(n96), .Y(n97) );
XOR2X1TS U179 ( .A(n272), .B(n271), .Y(res[18]) );
NAND2X6TS U180 ( .A(n277), .B(n63), .Y(n39) );
MXI2X4TS U181 ( .A(n42), .B(n82), .S0(n302), .Y(n336) );
MXI2X4TS U182 ( .A(n171), .B(n167), .S0(n302), .Y(n179) );
XNOR2X1TS U183 ( .A(n150), .B(in2[21]), .Y(n151) );
XNOR2X2TS U184 ( .A(n207), .B(n206), .Y(res[29]) );
XNOR2X4TS U185 ( .A(n193), .B(n192), .Y(res[30]) );
NOR2X4TS U186 ( .A(n124), .B(in1[18]), .Y(n126) );
MXI2X4TS U187 ( .A(n122), .B(n121), .S0(n302), .Y(n124) );
XNOR2X2TS U188 ( .A(n129), .B(in2[18]), .Y(n121) );
NAND2X4TS U189 ( .A(n157), .B(in1[21]), .Y(n255) );
OAI21X4TS U190 ( .A0(n230), .A1(n226), .B0(n227), .Y(n225) );
MXI2X4TS U191 ( .A(n156), .B(n155), .S0(n302), .Y(n158) );
NOR2X4TS U192 ( .A(n222), .B(n226), .Y(n216) );
MXI2X4TS U193 ( .A(n170), .B(n169), .S0(n315), .Y(n178) );
NOR2X2TS U194 ( .A(n232), .B(n237), .Y(n162) );
XNOR2X1TS U195 ( .A(n94), .B(in2[8]), .Y(n82) );
XNOR2X1TS U196 ( .A(add_sub), .B(in2[9]), .Y(n77) );
OR3X1TS U197 ( .A(n306), .B(n88), .C(in2[9]), .Y(n76) );
NOR4BX1TS U198 ( .AN(n80), .B(n79), .C(in2[9]), .D(n72), .Y(n78) );
NAND2X1TS U199 ( .A(n47), .B(in2[11]), .Y(n46) );
INVX2TS U200 ( .A(in2[11]), .Y(n49) );
XNOR2X1TS U201 ( .A(n113), .B(in2[14]), .Y(n100) );
NAND2X4TS U202 ( .A(n87), .B(in1[10]), .Y(n346) );
OR2X4TS U203 ( .A(n89), .B(in1[11]), .Y(n342) );
NOR2X2TS U204 ( .A(n182), .B(in1[28]), .Y(n211) );
INVX2TS U205 ( .A(n220), .Y(n181) );
NAND2X2TS U206 ( .A(n134), .B(n133), .Y(n144) );
NAND3XLTS U207 ( .A(n107), .B(n106), .C(n105), .Y(n108) );
MX2X4TS U208 ( .A(in2[17]), .B(n120), .S0(n315), .Y(n123) );
XNOR2X1TS U209 ( .A(n173), .B(in2[27]), .Y(n174) );
XOR2X1TS U210 ( .A(n199), .B(in2[30]), .Y(n190) );
OAI21X1TS U211 ( .A0(n332), .A1(n331), .B0(n330), .Y(n333) );
INVX2TS U212 ( .A(n346), .Y(n20) );
NOR2X1TS U213 ( .A(n21), .B(in1[12]), .Y(n11) );
NAND2X4TS U214 ( .A(n338), .B(n25), .Y(n24) );
INVX2TS U215 ( .A(n350), .Y(n85) );
INVX2TS U216 ( .A(n283), .Y(n293) );
OAI21X2TS U217 ( .A0(n284), .A1(n290), .B0(n285), .Y(n103) );
NOR2X2TS U218 ( .A(n289), .B(n284), .Y(n104) );
NOR2X4TS U219 ( .A(n110), .B(in1[15]), .Y(n279) );
NAND2X2TS U220 ( .A(n124), .B(in1[18]), .Y(n269) );
INVX2TS U221 ( .A(n126), .Y(n270) );
NAND2X4TS U222 ( .A(n123), .B(in1[17]), .Y(n273) );
NAND2X1TS U223 ( .A(n39), .B(n275), .Y(n35) );
INVX2TS U224 ( .A(n34), .Y(n28) );
NAND2X2TS U225 ( .A(n38), .B(n37), .Y(n29) );
NOR2X4TS U226 ( .A(n179), .B(in1[26]), .Y(n222) );
NAND2X2TS U227 ( .A(n178), .B(in1[25]), .Y(n227) );
NOR2X2TS U228 ( .A(n178), .B(in1[25]), .Y(n226) );
NAND2X2TS U229 ( .A(n179), .B(in1[26]), .Y(n223) );
NAND2X2TS U230 ( .A(n180), .B(in1[27]), .Y(n220) );
INVX2TS U231 ( .A(n217), .Y(n218) );
INVX2TS U232 ( .A(n194), .Y(n205) );
NOR2X2TS U233 ( .A(n188), .B(in1[29]), .Y(n194) );
NAND2X2TS U234 ( .A(n188), .B(in1[29]), .Y(n204) );
OR2X4TS U235 ( .A(in2[9]), .B(in2[8]), .Y(n90) );
NAND3X2TS U236 ( .A(n42), .B(n41), .C(n40), .Y(n72) );
CLKBUFX2TS U237 ( .A(n99), .Y(n106) );
NAND2X2TS U238 ( .A(n134), .B(n146), .Y(n129) );
NAND3X4TS U239 ( .A(n38), .B(n37), .C(n140), .Y(n31) );
NAND2X2TS U240 ( .A(n34), .B(n140), .Y(n33) );
NOR2X2TS U241 ( .A(n329), .B(in1[7]), .Y(n332) );
NAND2X2TS U242 ( .A(n47), .B(n96), .Y(n21) );
NOR2X2TS U243 ( .A(n157), .B(in1[21]), .Y(n248) );
XNOR2X1TS U244 ( .A(n309), .B(in2[6]), .Y(n310) );
INVX2TS U245 ( .A(n248), .Y(n256) );
INVX2TS U246 ( .A(n255), .Y(n249) );
NAND2X2TS U247 ( .A(n159), .B(in1[23]), .Y(n244) );
NOR2X4TS U248 ( .A(n160), .B(in1[24]), .Y(n237) );
NOR2X1TS U249 ( .A(n233), .B(n232), .Y(n236) );
INVX2TS U250 ( .A(n243), .Y(n233) );
NAND2X2TS U251 ( .A(n160), .B(in1[24]), .Y(n238) );
INVX2TS U252 ( .A(n5), .Y(n56) );
NAND2X1TS U253 ( .A(n351), .B(n350), .Y(n352) );
NAND2X1TS U254 ( .A(n339), .B(n338), .Y(n337) );
NAND2X1TS U255 ( .A(n342), .B(n341), .Y(n343) );
OAI21X1TS U256 ( .A0(n348), .A1(n345), .B0(n346), .Y(n344) );
NAND2X1TS U257 ( .A(n18), .B(n294), .Y(n296) );
AOI21X1TS U258 ( .A0(n3), .A1(n24), .B0(n16), .Y(n295) );
NAND2X1TS U259 ( .A(n291), .B(n290), .Y(n292) );
INVX2TS U260 ( .A(n289), .Y(n291) );
NAND2X1TS U261 ( .A(n286), .B(n285), .Y(n287) );
OAI21XLTS U262 ( .A0(n293), .A1(n289), .B0(n290), .Y(n288) );
INVX2TS U263 ( .A(n284), .Y(n286) );
NAND2X1TS U264 ( .A(n281), .B(n280), .Y(n282) );
INVX2TS U265 ( .A(n279), .Y(n281) );
NAND2X1TS U266 ( .A(n63), .B(n275), .Y(n276) );
XNOR2X1TS U267 ( .A(n274), .B(n35), .Y(res[17]) );
NAND2X1TS U268 ( .A(n65), .B(n273), .Y(n274) );
INVX2TS U269 ( .A(n273), .Y(n268) );
XOR2XLTS U270 ( .A(n4), .B(n267), .Y(res[19]) );
NAND2X1TS U271 ( .A(n266), .B(n265), .Y(n267) );
XNOR2X1TS U272 ( .A(n263), .B(n262), .Y(res[20]) );
NAND2X1TS U273 ( .A(n261), .B(n260), .Y(n262) );
OAI21X1TS U274 ( .A0(n4), .A1(n264), .B0(n265), .Y(n263) );
INVX2TS U275 ( .A(n259), .Y(n261) );
XNOR2X1TS U276 ( .A(n258), .B(n257), .Y(res[21]) );
NAND2X1TS U277 ( .A(n256), .B(n255), .Y(n257) );
XOR2X1TS U278 ( .A(n230), .B(n229), .Y(res[25]) );
NAND2X1TS U279 ( .A(n228), .B(n227), .Y(n229) );
INVX2TS U280 ( .A(n226), .Y(n228) );
INVX2TS U281 ( .A(n222), .Y(n224) );
INVX2TS U282 ( .A(n216), .Y(n219) );
XNOR2X1TS U283 ( .A(n215), .B(n214), .Y(res[28]) );
NAND2X1TS U284 ( .A(n213), .B(n212), .Y(n214) );
INVX2TS U285 ( .A(n211), .Y(n213) );
NAND3X2TS U286 ( .A(n54), .B(n203), .C(n53), .Y(res[32]) );
OAI21X1TS U287 ( .A0(n234), .A1(n232), .B0(n244), .Y(n235) );
NOR2X4TS U288 ( .A(n87), .B(in1[10]), .Y(n345) );
MXI2X4TS U289 ( .A(n86), .B(n45), .S0(n302), .Y(n87) );
AOI21X4TS U290 ( .A0(n283), .A1(n104), .B0(n103), .Y(n278) );
AND2X4TS U291 ( .A(n23), .B(n342), .Y(n3) );
NOR2X4TS U292 ( .A(n159), .B(in1[23]), .Y(n232) );
AND2X2TS U293 ( .A(n29), .B(n28), .Y(n4) );
OR2X2TS U294 ( .A(n202), .B(in1[31]), .Y(n5) );
INVX2TS U295 ( .A(n338), .Y(n84) );
NAND2X2TS U296 ( .A(n83), .B(in1[9]), .Y(n338) );
INVX2TS U297 ( .A(n275), .Y(n117) );
NAND2X2TS U298 ( .A(n116), .B(in1[16]), .Y(n275) );
AND2X2TS U299 ( .A(n5), .B(n203), .Y(n6) );
NOR2X4TS U300 ( .A(n12), .B(n11), .Y(n18) );
INVX2TS U301 ( .A(in2[10]), .Y(n86) );
INVX2TS U302 ( .A(n345), .Y(n23) );
XOR2X1TS U303 ( .A(n329), .B(n319), .Y(res[7]) );
MXI2X1TS U304 ( .A(n66), .B(n40), .S0(n88), .Y(n70) );
XNOR2X2TS U305 ( .A(in2[0]), .B(in2[1]), .Y(n66) );
ADDFHX2TS U306 ( .A(in1[4]), .B(n322), .CI(n317), .CO(n321), .S(res[4]) );
XOR2X4TS U307 ( .A(n26), .B(n6), .Y(res[31]) );
INVX4TS U308 ( .A(n92), .Y(n93) );
CLKXOR2X2TS U309 ( .A(n141), .B(in2[23]), .Y(n142) );
OAI21X4TS U310 ( .A0(n52), .A1(n194), .B0(n204), .Y(n193) );
XNOR2X4TS U311 ( .A(n106), .B(in2[12]), .Y(n22) );
OAI21X4TS U312 ( .A0(n52), .A1(n198), .B0(n197), .Y(n26) );
NOR2X8TS U313 ( .A(n60), .B(n57), .Y(n52) );
NOR2X8TS U314 ( .A(n32), .B(n30), .Y(n231) );
NAND2BX4TS U315 ( .AN(n139), .B(n33), .Y(n32) );
INVX8TS U316 ( .A(n39), .Y(n38) );
OAI21X4TS U317 ( .A0(n278), .A1(n279), .B0(n280), .Y(n277) );
INVX12TS U318 ( .A(in2[1]), .Y(n40) );
INVX12TS U319 ( .A(in2[0]), .Y(n41) );
NOR2X8TS U320 ( .A(n297), .B(n79), .Y(n313) );
NAND2X8TS U321 ( .A(n44), .B(n43), .Y(n79) );
INVX12TS U322 ( .A(in2[3]), .Y(n43) );
NAND2X8TS U323 ( .A(n40), .B(n41), .Y(n297) );
OAI21X4TS U324 ( .A0(n231), .A1(n164), .B0(n163), .Y(n208) );
OAI21X4TS U325 ( .A0(n48), .A1(n47), .B0(n46), .Y(n89) );
XOR2X4TS U326 ( .A(n50), .B(n49), .Y(n48) );
NOR2X4TS U327 ( .A(n231), .B(n58), .Y(n57) );
NAND2BX4TS U328 ( .AN(n52), .B(n55), .Y(n54) );
NAND2BX4TS U329 ( .AN(n183), .B(n61), .Y(n60) );
NAND2BX4TS U330 ( .AN(n163), .B(n184), .Y(n61) );
XOR2X1TS U331 ( .A(n247), .B(n246), .Y(res[23]) );
NOR2X8TS U332 ( .A(in2[5]), .B(in2[4]), .Y(n306) );
NAND2BX4TS U333 ( .AN(n144), .B(n146), .Y(n153) );
AOI21X2TS U334 ( .A0(n335), .A1(n334), .B0(n333), .Y(n353) );
NOR2X1TS U335 ( .A(n327), .B(n332), .Y(n334) );
XOR2X4TS U336 ( .A(n97), .B(in2[13]), .Y(n98) );
INVX2TS U337 ( .A(n264), .Y(n266) );
NAND2X1TS U338 ( .A(n270), .B(n269), .Y(n271) );
XNOR2X1TS U339 ( .A(n297), .B(in2[2]), .Y(n68) );
INVX2TS U340 ( .A(in2[2]), .Y(n67) );
MXI2X1TS U341 ( .A(n68), .B(n67), .S0(n88), .Y(n301) );
INVX2TS U342 ( .A(n72), .Y(n73) );
NAND4X1TS U343 ( .A(n74), .B(n80), .C(in2[9]), .D(n73), .Y(n75) );
OAI211X4TS U344 ( .A0(n78), .A1(n77), .B0(n76), .C0(n75), .Y(n83) );
NAND2X8TS U345 ( .A(n313), .B(n81), .Y(n94) );
INVX2TS U346 ( .A(in2[12]), .Y(n96) );
NOR2BX4TS U347 ( .AN(n91), .B(n90), .Y(n92) );
NOR2X8TS U348 ( .A(n94), .B(n93), .Y(n99) );
INVX2TS U349 ( .A(in2[16]), .Y(n115) );
NOR2X8TS U350 ( .A(n113), .B(n112), .Y(n146) );
XOR2X1TS U351 ( .A(n146), .B(in2[16]), .Y(n114) );
MXI2X2TS U352 ( .A(n115), .B(n114), .S0(n302), .Y(n116) );
INVX2TS U353 ( .A(n146), .Y(n118) );
XNOR2X1TS U354 ( .A(n119), .B(in2[17]), .Y(n120) );
INVX2TS U355 ( .A(in2[18]), .Y(n122) );
NOR2X2TS U356 ( .A(in2[17]), .B(in2[16]), .Y(n134) );
AOI2BB1X4TS U357 ( .A0N(n273), .A1N(n126), .B0(n125), .Y(n127) );
INVX2TS U358 ( .A(in2[19]), .Y(n132) );
XOR2X1TS U359 ( .A(n130), .B(in2[19]), .Y(n131) );
MXI2X4TS U360 ( .A(n132), .B(n131), .S0(n315), .Y(n137) );
INVX2TS U361 ( .A(in2[20]), .Y(n136) );
XNOR2X1TS U362 ( .A(n153), .B(in2[20]), .Y(n135) );
INVX2TS U363 ( .A(in2[23]), .Y(n143) );
NOR3X4TS U364 ( .A(n153), .B(in2[22]), .C(n152), .Y(n141) );
MXI2X4TS U365 ( .A(n143), .B(n142), .S0(n315), .Y(n159) );
INVX2TS U366 ( .A(in2[24]), .Y(n149) );
XNOR2X1TS U367 ( .A(n147), .B(in2[24]), .Y(n148) );
MXI2X2TS U368 ( .A(n149), .B(n148), .S0(add_sub), .Y(n160) );
INVX2TS U369 ( .A(in2[22]), .Y(n156) );
INVX2TS U370 ( .A(in2[26]), .Y(n171) );
INVX2TS U371 ( .A(in2[25]), .Y(n170) );
OR2X2TS U372 ( .A(n175), .B(in2[27]), .Y(n185) );
XNOR2X1TS U373 ( .A(n176), .B(in2[28]), .Y(n177) );
OAI21X4TS U374 ( .A0(n227), .A1(n222), .B0(n223), .Y(n217) );
AOI21X4TS U375 ( .A0(n217), .A1(n64), .B0(n181), .Y(n209) );
XNOR2X1TS U376 ( .A(n189), .B(in2[29]), .Y(n187) );
NOR2X2TS U377 ( .A(n199), .B(in2[30]), .Y(n200) );
XNOR2X1TS U378 ( .A(n200), .B(in2[31]), .Y(n201) );
OAI21X4TS U379 ( .A0(n230), .A1(n210), .B0(n209), .Y(n215) );
OAI21X4TS U380 ( .A0(n230), .A1(n219), .B0(n218), .Y(n221) );
INVX2TS U381 ( .A(n242), .Y(n234) );
XNOR2X1TS U382 ( .A(n277), .B(n276), .Y(res[16]) );
XOR2XLTS U383 ( .A(n278), .B(n282), .Y(res[15]) );
XNOR2X1TS U384 ( .A(n288), .B(n287), .Y(res[14]) );
NOR2X1TS U385 ( .A(n297), .B(in2[2]), .Y(n298) );
XNOR2X1TS U386 ( .A(n298), .B(in2[3]), .Y(n299) );
ADDFHX2TS U387 ( .A(n301), .B(in1[2]), .CI(n300), .CO(n304), .S(res[2]) );
INVX2TS U388 ( .A(in2[4]), .Y(n312) );
XNOR2X1TS U389 ( .A(n313), .B(n312), .Y(n303) );
MXI2X2TS U390 ( .A(n312), .B(n303), .S0(n302), .Y(n322) );
CMPR32X2TS U391 ( .A(in1[3]), .B(n305), .C(n304), .CO(n317), .S(res[3]) );
NAND2X1TS U392 ( .A(n313), .B(n306), .Y(n309) );
XNOR2X1TS U393 ( .A(n307), .B(in2[7]), .Y(n308) );
INVX2TS U394 ( .A(in2[6]), .Y(n311) );
MXI2X2TS U395 ( .A(n311), .B(n310), .S0(add_sub), .Y(n328) );
NAND2X1TS U396 ( .A(n313), .B(n312), .Y(n314) );
XOR2X4TS U397 ( .A(in1[7]), .B(n318), .Y(n319) );
CMPR32X2TS U398 ( .A(in1[5]), .B(n323), .C(n321), .CO(n320), .S(res[5]) );
NAND2X1TS U399 ( .A(n322), .B(in1[4]), .Y(n325) );
NAND2X1TS U400 ( .A(n323), .B(in1[5]), .Y(n324) );
OAI21X1TS U401 ( .A0(n326), .A1(n325), .B0(n324), .Y(n335) );
NOR2X1TS U402 ( .A(n328), .B(in1[6]), .Y(n327) );
NAND2X1TS U403 ( .A(n328), .B(in1[6]), .Y(n331) );
NAND2X1TS U404 ( .A(n329), .B(in1[7]), .Y(n330) );
OAI21X4TS U405 ( .A0(n353), .A1(n349), .B0(n350), .Y(n340) );
XNOR2X1TS U406 ( .A(n340), .B(n337), .Y(res[9]) );
AOI21X4TS U407 ( .A0(n340), .A1(n339), .B0(n84), .Y(n348) );
XNOR2X1TS U408 ( .A(n344), .B(n343), .Y(res[11]) );
NAND2X1TS U409 ( .A(n23), .B(n346), .Y(n347) );
INVX2TS U410 ( .A(n349), .Y(n351) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_GeArN16R4P4_syn.sdf");
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
sys_clk,
sys_resetn,
// ddr3
ddr3_clk_p,
ddr3_clk_n,
ddr3_a,
ddr3_ba,
ddr3_cke,
ddr3_cs_n,
ddr3_odt,
ddr3_reset_n,
ddr3_we_n,
ddr3_ras_n,
ddr3_cas_n,
ddr3_dqs_p,
ddr3_dqs_n,
ddr3_dq,
ddr3_dm,
ddr3_rzq,
ddr3_ref_clk,
// ethernet
eth_ref_clk,
eth_rxd,
eth_txd,
eth_mdc,
eth_mdio,
eth_resetn,
eth_intn,
// board gpio
gpio_bd,
// lane interface
rx_ref_clk,
rx_sysref,
rx_sync,
rx_data,
tx_ref_clk,
tx_sysref,
tx_sync,
tx_data,
// gpio
trig,
adc_fdb,
adc_fda,
dac_irq,
clkd_status,
adc_pd,
dac_txen,
dac_reset,
clkd_sync,
// spi
spi_csn_clk,
spi_csn_dac,
spi_csn_adc,
spi_clk,
spi_sdio,
spi_dir);
// clock and resets
input sys_clk;
input sys_resetn;
// ddr3
output ddr3_clk_p;
output ddr3_clk_n;
output [ 14:0] ddr3_a;
output [ 2:0] ddr3_ba;
output ddr3_cke;
output ddr3_cs_n;
output ddr3_odt;
output ddr3_reset_n;
output ddr3_we_n;
output ddr3_ras_n;
output ddr3_cas_n;
inout [ 7:0] ddr3_dqs_p;
inout [ 7:0] ddr3_dqs_n;
inout [ 63:0] ddr3_dq;
output [ 7:0] ddr3_dm;
input ddr3_rzq;
input ddr3_ref_clk;
// ethernet
input eth_ref_clk;
input eth_rxd;
output eth_txd;
output eth_mdc;
inout eth_mdio;
output eth_resetn;
input eth_intn;
// board gpio
inout [ 26:0] gpio_bd;
// lane interface
input rx_ref_clk;
input rx_sysref;
output rx_sync;
input [ 3:0] rx_data;
input tx_ref_clk;
input tx_sysref;
input tx_sync;
output [ 3:0] tx_data;
// gpio
input trig;
inout adc_fdb;
inout adc_fda;
inout dac_irq;
inout [ 1:0] clkd_status;
inout adc_pd;
inout dac_txen;
inout dac_reset;
inout clkd_sync;
// spi
output spi_csn_clk;
output spi_csn_dac;
output spi_csn_adc;
output spi_clk;
inout spi_sdio;
output spi_dir;
// internal signals
wire eth_mdio_i;
wire eth_mdio_o;
wire eth_mdio_t;
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire spi_miso_s;
wire spi_mosi_s;
wire [ 7:0] spi_csn_s;
wire xcvr_pll_locked;
wire [ 3:0] xcvr_rx_ready;
wire [ 3:0] xcvr_tx_ready;
// daq2
assign spi_csn_adc = spi_csn_s[2];
assign spi_csn_dac = spi_csn_s[1];
assign spi_csn_clk = spi_csn_s[0];
daq2_spi i_daq2_spi (
.spi_csn (spi_csn_s[2:0]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi_s),
.spi_miso (spi_miso_s),
.spi_sdio (spi_sdio),
.spi_dir (spi_dir));
assign gpio_i[63:60] = xcvr_tx_ready;
assign gpio_i[59:56] = xcvr_rx_ready;
assign gpio_i[55:55] = xcvr_pll_locked;
assign gpio_i[54:44] = 11'd0;
assign gpio_i[43:43] = trig;
assign gpio_i[39:39] = 1'd0;
assign gpio_i[37:37] = 1'd0;
ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
.dio_t ({3'h0, 1'h0, 5'h1f}),
.dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
.dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
.dio_p ({ adc_pd, // 42
dac_txen, // 41
dac_reset, // 40
clkd_sync, // 38
adc_fdb, // 36
adc_fda, // 35
dac_irq, // 34
clkd_status})); // 32
// board stuff
assign eth_resetn = 1'b1;
assign eth_mdio_i = eth_mdio;
assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
assign gpio_i[31] = 1'd0;
assign gpio_i[30] = 1'd0;
assign gpio_i[29] = 1'd0;
assign gpio_i[28] = 1'd0;
assign gpio_i[27] = 1'd0;
ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
.dio_t ({11'h7ff, 16'h0}),
.dio_i (gpio_o[26:0]),
.dio_o (gpio_i[26:0]),
.dio_p (gpio_bd));
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
.sys_ddr3_cntrl_mem_mem_a (ddr3_a),
.sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
.sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
.sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
.sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
.sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
.sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
.sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
.sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
.sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
.sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
.sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
.sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
.sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
.sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
.sys_ethernet_mdio_mdc (eth_mdc),
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_ethernet_ref_clk_clk (eth_ref_clk),
.sys_ethernet_sgmii_rxp_0 (eth_rxd),
.sys_ethernet_sgmii_txp_0 (eth_txd),
.sys_gpio_in_port (gpio_i[63:32]),
.sys_gpio_out_port (gpio_o[63:32]),
.sys_gpio_bd_in_port (gpio_i[31:0]),
.sys_gpio_bd_out_port (gpio_o[31:0]),
.sys_reset_reset_n (sys_resetn),
.sys_spi_MISO (spi_miso_s),
.sys_spi_MOSI (spi_mosi_s),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn_s),
.sys_xcvr_rstcntrl_pll_locked_pll_locked (xcvr_pll_locked),
.sys_xcvr_rstcntrl_rx_ready_rx_ready (xcvr_rx_ready),
.sys_xcvr_rstcntrl_tx_ready_tx_ready (xcvr_tx_ready),
.sys_xcvr_rx_ref_clk_clk (rx_ref_clk),
.sys_xcvr_rx_sync_n_export (rx_sync),
.sys_xcvr_rx_sysref_export (rx_sysref),
.sys_xcvr_rxd_rx_serial_data (rx_data),
.sys_xcvr_tx_ref_clk_clk (tx_ref_clk),
.sys_xcvr_tx_sync_n_export (tx_sync),
.sys_xcvr_tx_sysref_export (tx_sysref),
.sys_xcvr_txd_tx_serial_data (tx_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
system1_jtag_uart_0_sim_scfifo_w the_system1_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
system1_jtag_uart_0_sim_scfifo_r the_system1_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
system1_jtag_uart_0_scfifo_w the_system1_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
system1_jtag_uart_0_scfifo_r the_system1_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic system1_jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam system1_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// system1_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// system1_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// system1_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine Top Level
// File : de_top.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module Corresponds to the top level of Silverhammer. It will
// Contain only 2D functionality.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module de_top
#(parameter BYTES = 16)
(
// Inputs
input de_clk, // drawing engine clock input. */
input sys_locked, // drawing engine clock input. */
// Host inputs
input hb_clk, // host bus clock input
input hb_rstn, // reset input
input [8:2] dlp_adr, // host bus address through DLP
input [13:2] hb_adr_bp1, // " " bypass DLP for DED
input [8:2] hb_adr_bp2, // " " bypass DLP for DER readback
input hb_wstrb, // host bus write strobe for DED
input [3:0] hb_ben, // host bus byte enables
input [31:0] hb_din, // host bus data, not swizzled
input hb_csn_de, // chip select for de registers
input hb_xyw_csn, // chip select for XY window.
// Input from MC
input mclock, // Memory controller clock.
input mc_popen, // Memory controller pop enable.
input mc_push, // push data into the fifo.
mc_eop, // end of page indicator.
mc_eop4, // end of page indicator.(high last 4 pages)
input [53:0] dl_rdback, // DLP readback data.
input mw_de_fip, // Memory window flush in progress.
input hb_write, // Host write enable.
input de_pc_pop, // Pop from the pixcache
input mc_busy, // Memory Controller busy.
input busy_dlp, // Busy Feed Back from the DLP
// Output
output [31:0] hb_dout, // host bus read back data.
output [31:0] dr_hbdout, // Drawing engine registers to HB
output busy_hb, // drawing pipeline busy.
output interrupt, // Host interrupt.
// ded_ca_top ram interface
`ifdef BYTE16 output [3:0] ca_enable,
`elsif BYTE8 output [1:0] ca_enable,
`else output ca_enable, `endif
output [4:0] hb_ram_addr,
output [4:0] ca_ram_addr0,
output [4:0] ca_ram_addr1,
input [(BYTES*8)-1:0] hb_dout_ram,
input [(BYTES<<3)-1:0] ca_dout0,
input [(BYTES<<3)-1:0] ca_dout1,
// Output MC
output [BYTES-1:0] dd_pixel_msk, // pixel dr_mask bits
output [(BYTES<<3)-1:0] dd_fb_out, // data output to the frame buffer
output [(BYTES<<2)-1:0] dd_fb_a, // data output to the frame buffer
output de_pc_empty, // FIFO flag to MC
output [2:0] hdf_1, // host data format to HBI module.
output [1:0] ps_4, // Output the pixel size for the MC.
output [31:0] de_mc_address, // Line/ Blt linear address
output de_mc_read,
output de_mc_rmw,
output [3:0] de_mc_wcnt,
output line_actv_4,
output [3:0] bsrcr_4, // Source blending function.
output [2:0] bdstr_4, // Destination blending function.
output blend_en_4, // Blending enable.
output [1:0] blend_reg_en_4,// Blending enable.
output [7:0] bsrc_alpha_4, // Source alpha data.
output [7:0] bdst_alpha_4, // Destination alpha data.
output [3:0] rop_4, // Raster operation.
output [31:0] kcol_4, // Key Color.
output [2:0] key_ctrl_4, // Key control.
output dr_org_md_2,
output [6:0] mem_offset,
output [3:0] sorg_upper,
output ca_busy,
output de_ddint_tog, // drawing done pulse.
output de_clint_tog, // clipping interrupt pulse.
output dx_clp, // last command was clipped.
output dx_deb, // drawing engine busy.
output [4:0] z_ctrl_4,
output [31:0] z_address_4,
output [(BYTES*8)-1:0] z_out,
//
// Outputs to PCI bus
output pipe_pending, // pipeline has data in it
// TC Signals To/from the Memory controller.
input mc_tc_push,
input [(BYTES<<3)-1:0] mc_tc_data,
input mc_tc_ack,
input mc_pal_ack,
input mc_pal_push,
// Outputs.
output mc_tc_req,
output [5:0] mc_tc_page,
output [31:0] mc_tc_address,
output mc_pal_req,
output mc_pal_half,
output [31:0] mc_pal_address
);
// Internal Signals
wire [20:0] tporg_2; // palette origin
wire cmd_done_3d; // Last pixel done for current command.
wire [1:0] ps_15; // DSIZE bits
wire [3:0] opc_1;
wire [3:0] opc_15;
wire [3:0] rop_1;
wire [1:0] dr_apat_2;
wire [1:0] stpl_2;
wire [2:0] dr_clp_2;
wire [31:0] dr_fore_2;
wire [31:0] dr_back_2;
wire [31:0] dr_lpat_1;
wire [15:0] dr_pctrl_1;
wire [31:0] dr_clptl_1;
wire [31:0] dr_clpbr_1;
wire [159:0] dr_xydat_1;
wire [15:0] dx_xalu;
wire [15:0] dx_srcx,
dx_srcy,
dx_dstx,
dx_dsty;
wire [15:0] dx_lpat_state;
wire [31:0] dx_clpx_bus_2; // clipping X values.
wire [3:0] fx_1;
wire [15:0] real_dstx;
wire [15:0] real_dsty;
wire [31:0] de_dorg_2;
wire [31:0] de_sorg_2;
wire [1:0] chng_stat_1;
wire [27:0] dr_sorg_2;
wire [27:0] dr_dorg_2;
wire [11:0] dr_sptch_2;
wire [11:0] dr_dptch_2;
wire load_actvn;
wire [2:0] frst8;
wire pc_mc_busy;
// wire [1:0] pss_2;
// wire [1:0] ps_2;
// wire [1:0] nc2_0;
/* this renaming stuff stays */
wire tc_xyw_sel_1;
wire force8_2;
wire [11:0] dr_buf_ctrl_2;
wire dr_sen_2;
wire [31:0] kcol_2;
wire [2:0] key_ctrl_2;
assign {
dr_sen_2, // [11]
// pss_2, // [10:9]
// ps_2, // [8:7]
// nc2_0, // [6:5]
dr_org_md_2, // [4]
force8_2, // [3]
key_ctrl_2 // [2:0]
} = {dr_buf_ctrl_2[11], dr_buf_ctrl_2[4:0]};
wire dr_sfd_2;
assign dr_sfd_2 = dr_sen_2;
wire solid_2; /* solid bit*/
wire [4:0] dr_style_2;
assign solid_2 = dr_style_2[0]; /* solid bit */
wire de_edi_2; /* edge inclusion mode bit */
assign de_edi_2 = dr_style_2[4]; /* edge inclusion mode bit */
wire [1:0] bc_lvl_2;
reg [4:0] flow;
reg [4:0] flow_d;
always @(posedge hb_clk) begin
flow <= flow_d;
flow_d <= {
pipe_pending,
ca_busy,
dx_clp,
(mc_busy | pc_mc_busy | ca_busy),
dx_deb
};
end
/******************************************************************************/
/* syncronize the drawing done signal. */
wire [4:0] xpat_ofs;
wire [4:0] ypat_ofs;
// New Inputs
wire [1:0] dither_op; /* Dither Control Bits */
wire [17:0] acntrl_2;
wire [15:0] alpha_2;
wire [23:0] de_key_2;
wire cmdcpyclr;
wire de_rstn;
wire solid_1;
wire dr_prst_1;
wire dr_nlst_2;
wire dr_apat_1;
wire der_stpl_1;
wire ca_rdy;
wire ps16s_2;
wire cmd_trig_comb;
wire de_trnsp_2;
wire pc_mc_rdy;
wire pcbusy;
wire ps8_2, ps16_2, ps32_2;
wire pc_dirty;
wire de_pad8_2;
wire mw_fip;
wire deb;
wire bound;
wire dx_pc_ld;
wire rmw;
wire dx_ld_wcnt;
wire line_actv_2;
wire dx_blt_actv_2;
wire dx_fg_bgn;
wire dx_rstn_wad;
wire dx_ld_rad, dx_ld_rad_e;
wire dx_sol_2, eol_2;
wire dx_ld_msk;
wire clip;
wire y_clip_2;
wire src_lte_dst;
wire dx_ld_initial;
wire pc_msk_last;
wire frst_pix;
wire last_pixel;
wire wb_clip_ind;
wire stpl_pk_4;
wire dx_mem_req;
wire line_actv_1;
wire blt_actv_1;
wire [3:0] de_pln_msk_2;
wire dx_mem_rd;
wire [3:0] rop_2;
wire pc_empty;
wire valid_3d;
wire fg_bgn_3d;
wire [15:0] x_out_3d;
wire [15:0] y_out_3d;
wire last_3d;
wire [31:0] pixel_3d;
wire [31:0] z_3d;
wire [4:0] z_ctrl;
wire [7:0] alpha_3d;
wire [31:0] hb_dout_2d;
wire sup_done;
wire abort_cmd;
wire go_sup;
wire dex_busy;
wire goline;
wire goblt;
wire pal_load;
wire tc_inv_cmd;
wire load_actv_3d;
wire line_actv_3d;
wire pc_last;
wire [27:0] zorg_2;
wire [11:0] zptch_2;
wire active_3d_2;
wire [31:0] clptl_2;
wire [31:0] clpbr_2;
wire load_15;
wire pc_busy_3d;
wire msk_last_3d;
wire l3_incpat;
wire abort_cmd_flag;
// Drawing Engine Registers
der_top u_der_top
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.hb_clk (hb_clk),
.hb_rstn (hb_rstn),
.hb_din (hb_din),
.dlp_adr (dlp_adr[8:2]),
.hb_adr_r (hb_adr_bp2[8:2]),
.hb_wstrb (hb_wstrb),
.hb_ben (hb_ben),
.hb_csn (hb_csn_de),
.lpat_state (dx_lpat_state),
.dl_rdback (dl_rdback),
.flow (flow),
.busy_dlp (busy_dlp),
.de_clint_tog (de_clint_tog),
.de_ddint_tog (de_ddint_tog),
.sup_done (sup_done),
.abort_cmd (abort_cmd),
.dex_busy (dex_busy),
.pc_last (pc_last),
.cmd_done_3d (cmd_done_3d),
.goline (goline),
.goblt (goblt),
.pal_load (pal_load),
.tc_inv_cmd (tc_inv_cmd),
.go_sup (go_sup),
.load_actv_3d (load_actv_3d),
.cmdcpyclr (cmdcpyclr),
.load_actvn (load_actvn),
.tc_xyw_sel (tc_xyw_sel_1),
.buf_ctrl_2 (dr_buf_ctrl_2),
.ps_1 (ps_15),
.sorg_2 (dr_sorg_2),
.dorg_2 (dr_dorg_2),
.de_sorg_2 (de_sorg_2),
.de_dorg_2 (de_dorg_2),
.sptch_2 (dr_sptch_2),
.dptch_2 (dr_dptch_2),
.opc_1 (opc_1),
.opc_15 (opc_15),
.rop_1 (rop_1),
.rop_2 (rop_2),
.style_2 (dr_style_2),
.solid_1 (solid_1),
.prst_1 (dr_prst_1),
.nlst_2 (dr_nlst_2),
.or_apat_1 (dr_apat_1),
.apat_2 (dr_apat_2),
.hdf_1 (hdf_1),
.clp_2 (dr_clp_2),
.fore_2 (dr_fore_2),
.back_2 (dr_back_2),
.mask_2 (de_pln_msk_2),
.lpat_1 (dr_lpat_1),
.pctrl_1 (dr_pctrl_1),
.clptl_1 (dr_clptl_1),
.clpbr_1 (dr_clpbr_1),
.de_key_2 (de_key_2),
.xydat_1 (dr_xydat_1),
.alpha_2 (alpha_2),
.acntrl_2 (acntrl_2),
.hb_dout (hb_dout_2d),
.busy_hb (busy_hb),
.stpl_1 (der_stpl_1),
.de_ca_rdy (ca_rdy),
.ps16s_2 (ps16s_2),
.cmd_trig_comb (cmd_trig_comb),
.bc_lvl_2 (bc_lvl_2),
.interrupt (interrupt),
.mem_offset (mem_offset),
.sorg_upper (sorg_upper),
.load_15 (load_15),
.busy_3d (busy_3d),
.abort_cmd_flag (abort_cmd_flag)
);
/***************************************************************************/
/* Drawing Execution Module */
/***************************************************************************/
dex_top u_dex_top
(
.de_clk (de_clk),
.mclock (mclock),
.rstn (de_rstn),
.de_sorg_2 (de_sorg_2),
.de_dorg_2 (de_dorg_2),
.opc_1 (opc_1),
.opc_15 (opc_15),
.rop_1 (rop_1),
.rop_2 (rop_2),
.solid_1 (solid_1),
.solid_2 (solid_2),
.trnsp_2 (de_trnsp_2),
.stpl_1 (der_stpl_1),
.stpl_2 (stpl_2),
.apat_1 (dr_apat_1),
.apat_2 (dr_apat_2),
.sfd_2 (dr_sfd_2),
.edi_2 (de_edi_2),
.prst (dr_prst_1),
.nlst_2 (dr_nlst_2),
.clp_2 (dr_clp_2),
.lpat_1 (dr_lpat_1),
.pctrl_1 (dr_pctrl_1),
.clptl_1 (dr_clptl_1),
.clpbr_1 (dr_clpbr_1),
.xydat_1 (dr_xydat_1),
.pc_mcrdy (pc_mc_rdy),
.pcbusy (pc_busy_3d),
.ps_1 (ps_15),
.ps8_2 (ps8_2),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.pc_dirty (pc_dirty),
.ca_rdy (ca_rdy),
.pad8_2 (de_pad8_2),
.force8 (force8_2),
.mw_fip (mw_fip),
.load_actvn (load_actvn),
.load_actv_3d (load_actv_3d),
.cmdcpyclr (cmdcpyclr),
.goline (goline),
.goblt (goblt),
.l3_incpat (l3_incpat),
.busy_3d (busy_3d),
.busy (deb),
.bound (bound),
.pc_ld (dx_pc_ld),
.mem_req (dx_mem_req),
.mem_rd (dx_mem_rd),
.mem_rmw (rmw),
.ld_wcnt (dx_ld_wcnt),
.fx (dx_xalu),
.srcx (dx_srcx),
.srcy (dx_srcy),
.dstx (dx_dstx),
.dsty (dx_dsty),
.line_actv_2 (line_actv_2),
.blt_actv_2 (dx_blt_actv_2),
.fg_bgn (dx_fg_bgn),
.lpat_state (dx_lpat_state),
.clpx_bus_2 (dx_clpx_bus_2),
.rstn_wad (dx_rstn_wad),
.ld_rad (dx_ld_rad),
.ld_rad_e (dx_ld_rad_e),
.sol_2 (dx_sol_2),
.eol_2 (eol_2),
.ld_msk (dx_ld_msk),
.fx_1 (fx_1),
.clip (clip),
.y_clip_2 (y_clip_2),
.src_lte_dst (src_lte_dst),
.xpat_ofs (xpat_ofs),
.ypat_ofs (ypat_ofs),
.real_dstx (real_dstx),
.real_dsty (real_dsty),
.xchng (),
.ychng (),
.ld_initial (dx_ld_initial),
.next_x (), // remove_me
.next_y (), // remove_me
.pc_msk_last (pc_msk_last),
.frst_pix (), // remove_me
.last_pixel (last_pixel),
.line_actv_1 (line_actv_1),
.blt_actv_1 (blt_actv_1),
.frst8 (frst8),
.dex_busy (dex_busy),
.clptl_2 (clptl_2),
.clpbr_2 (clpbr_2)
);
/*********************************************************************** ***/
/* Drawing Data Path Module */
/***************************************************************************/
ded_top #
(
.BYTES (BYTES)
) D_DED
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.hb_clk (hb_clk),
.hb_rstn (hb_rstn),
.hb_adr (hb_adr_bp1[12:2]),
.hb_we (hb_wstrb),
.hb_xyw_csn (hb_xyw_csn),
.dx_mem_req (dx_mem_req),
.dx_mem_rd (dx_mem_rd),
.dx_line_actv_2 (line_actv_2),
.dx_blt_actv_2 (dx_blt_actv_2),
.dx_pc_ld (dx_pc_ld),
.dx_clpx_bus_2 (dx_clpx_bus_2),
.dx_rstn_wad (dx_rstn_wad),
.dx_ld_rad (dx_ld_rad),
.dx_ld_rad_e (dx_ld_rad_e),
.dx_sol_2 (dx_sol_2),
.dx_eol_2 (eol_2),
.dx_ld_msk (dx_ld_msk),
.dx_xalu (dx_xalu[9:0]),
.srcx (dx_srcx),
.srcy (dx_srcy),
.dsty (dx_dsty),
.dx_dstx (dx_dstx),
.dx_fg_bgn (dx_fg_bgn),
.sorg_2 (dr_sorg_2),
.dorg_2 (dr_dorg_2),
.z_org (zorg_2),
.sptch_2 (dr_sptch_2),
.dptch_2 (dr_dptch_2),
.z_ptch (zptch_2),
.ps_2 (dr_buf_ctrl_2[8:7]),
.bsrcr_2 (acntrl_2[3:0]),
.bdstr_2 (acntrl_2[6:4]),
.blend_en_2 (acntrl_2[10]),
.blend_reg_en_2 (acntrl_2[9:8]),
.bsrc_alpha_2 (alpha_2[7:0]),
.bdst_alpha_2 (alpha_2[15:8]),
.rop_2 (rop_2),
.kcol_2 (kcol_2),
.key_ctrl_2 (key_ctrl_2),
.frst8_2 (frst8),
.clip (clip),
.xpat_ofs (xpat_ofs),
.ypat_ofs (ypat_ofs),
.real_dstx (real_dstx),
.real_dsty (real_dsty),
.ld_initial (dx_ld_initial),
.pc_msk_last (pc_msk_last),
.last_pixel (last_pixel),
.mclock (mclock),
.mc_popen (mc_popen),
.mc_push (mc_push),
.mc_eop (mc_eop),
.mc_eop4 (mc_eop4),
.de_pc_pop (de_pc_pop),
.ld_wcnt (dx_ld_wcnt),
.fx_1 (fx_1),
.rmw (rmw),
.de_pln_msk_2 (de_pln_msk_2),
.dr_solid_2 (solid_2),
.dr_trnsp_2 (de_trnsp_2),
.stpl_2 (stpl_2),
.dr_apat_2 (dr_apat_2),
.dr_clp_2 (dr_clp_2[1:0]),
.fore_2 (dr_fore_2),
.back_2 (dr_back_2),
.dr_sen_2 (dr_sen_2),
.y_clip_2 (y_clip_2),
.ps8_2 (ps8_2),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.bc_lvl_2 (bc_lvl_2),
.hb_write (hb_write),
.mc_pixel_msk (dd_pixel_msk),
.mc_fb_out (dd_fb_out),
.mc_fb_a (dd_fb_a),
.pc_mc_busy (pc_mc_busy),
.de_pc_empty (de_pc_empty),
.pc_empty (pc_empty),
.de_mc_address (de_mc_address),
.de_mc_read (de_mc_read),
.de_mc_rmw (de_mc_rmw),
.de_mc_wcnt (de_mc_wcnt),
.hb_dout (hb_dout),
.pc_dirty (pc_dirty),
.clip_ind (wb_clip_ind),
.stpl_pk_4 (stpl_pk_4),
.pc_mc_rdy (pc_mc_rdy),
.pipe_pending (pipe_pending),
.line_actv_4 (line_actv_4),
.ps_4 (ps_4),
.bsrcr_4 (bsrcr_4),
.bdstr_4 (bdstr_4),
.blend_en_4 (blend_en_4),
.blend_reg_en_4 (blend_reg_en_4),
.bsrc_alpha_4 (bsrc_alpha_4),
.bdst_alpha_4 (bdst_alpha_4),
.rop_4 (rop_4),
.kcol_4 (kcol_4),
.key_ctrl_4 (key_ctrl_4),
.ca_enable (ca_enable),
.hb_ram_addr (hb_ram_addr),
.ca_ram_addr0 (ca_ram_addr0),
.ca_ram_addr1 (ca_ram_addr1),
.hb_dout_ram (hb_dout_ram),
.ca_dout0 (ca_dout0),
.ca_dout1 (ca_dout1),
// 3D Interface.
.pc_busy_3d (pc_busy_3d),
.valid_3d (valid_3d),
.fg_bgn_3d (fg_bgn_3d),
.msk_last_3d (msk_last_3d),
.x_out_3d (x_out_3d),
.y_out_3d (y_out_3d),
.last_3d (last_3d),
.pixel_3d (pixel_3d),
.z_3d (z_3d),
.z_ctrl (z_ctrl),
.active_3d_2 (active_3d_2),
.alpha_3d (alpha_3d),
.pc_last (pc_last),
.z_ctrl_4 (z_ctrl_4),
.z_address_4 (z_address_4),
.z_out (z_out)
);
/***************************************************************************/
/* All the random stuff that used to be inferred at this level */
/***************************************************************************/
de_top_misc D_MISC
(
.de_clk (de_clk),
.sys_locked (sys_locked),
.hb_clk (hb_clk),
.hb_rstn (hb_rstn),
.ps_2 (dr_buf_ctrl_2[8:7]),
.pc_mc_rdy (pc_mc_rdy),
.busy_hb (busy_hb),
.mw_de_fip (mw_de_fip),
.dr_style_2 (dr_style_2),
.dx_blt_actv_2 (dx_blt_actv_2),
.load_actvn (load_actvn),
.line_actv_2 (line_actv_2),
.wb_clip_ind (wb_clip_ind),
.clip (clip),
.cmd_trig_comb (cmd_trig_comb),
.line_actv_1 (line_actv_1),
.blt_actv_1 (blt_actv_1),
.de_key_2 (de_key_2),
.deb (deb),
.cmdcpyclr (cmdcpyclr),
.pc_empty (pc_empty),
.abort_cmd_flag (abort_cmd_flag),
.opc_1 (opc_1),
// outputs
.mw_fip (mw_fip),
.ca_busy (ca_busy),
.ps8_2 (ps8_2),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.de_pad8_2 (de_pad8_2),
.stpl_2 (stpl_2),
.de_rstn (de_rstn),
.dx_clp (dx_clp),
.dx_deb (dx_deb),
.de_trnsp_2 (de_trnsp_2),
.kcol_2 (kcol_2),
.de_clint_tog (de_clint_tog),
.de_ddint_tog (de_ddint_tog)
);
// assign dx_mem_rmw = 1'b0;
`ifdef CORE_3D
/***************************************************************************/
/* 3D Core if included. */
/***************************************************************************/
wire [31:0] hb_dout_3d;
de3d_top
#(.fract (9),
.BYTES (BYTES)
)
u_de3d_top
(
.hb_clk (hb_clk),
.hb_rstn (hb_rstn),
.hb_din (hb_din),
.dlp_adr (dlp_adr[8:2]),
.hb_adr_r (hb_adr_bp2[8:2]),
.hb_wstrb (hb_wstrb),
.hb_ben (hb_ben),
.hb_cp_csn (hb_csn_de),
.cp_hb_dout (hb_dout_3d),
.de_clk (de_clk),
.de_rstn (de_rstn),
// 2D Engine Interface.
.back_2 (dr_back_2),
.fore_2 (dr_fore_2),
.solid_2 (solid_2),
.ps_15 (ps_15),
.ps_2 (dr_buf_ctrl_2[8:7]),
.trnsp_2 (de_trnsp_2),
.mcrdy (1'b0),
.stpl_2 (stpl_2),
.stpl_pk_1 (1'b0),
.apat32_2 (1'b0),
.nlst_2 (dr_nlst_2),
.mw_fip (mw_fip),
.pal_load (pal_load),
.tc_inv_cmd (tc_inv_cmd),
.clp_2 (dr_clp_2),
.clptl_2 (clptl_2),
.clpbr_2 (clpbr_2),
.load_15 (load_15),
.load_actvn (load_actvn),
.l3_fg_bgn (dx_fg_bgn),
// Setup engine control..
.go_sup (go_sup),
.load_actv_3d (load_actv_3d),
.sup_done (sup_done),
.abort_cmd (abort_cmd),
// Pixel Cache Interface.
// .pc_busy (~pc_mc_rdy),
.pc_busy (pc_busy_3d),
.pc_valid (valid_3d),
.pc_fg_bgn (fg_bgn_3d),
.pc_x_out (x_out_3d),
.pc_y_out (y_out_3d),
.pc_last (last_3d),
.pc_msk_last (msk_last_3d),
.pc_formatted_pixel (pixel_3d),
.pc_formatted_z (z_3d),
.pc_z_ctrl (z_ctrl),
.pc_active_3d_2 (active_3d_2),
.pc_current_alpha (alpha_3d),
.pc_zorg_2 (zorg_2),
.pc_zptch_2 (zptch_2),
.tporg_2 (tporg_2),
// TC MC Signals.
.mclock (mclock),
.mc_tc_push (mc_tc_push),
.mc_tc_data (mc_tc_data),
.mc_tc_ack (mc_tc_ack),
.mc_pal_ack (mc_pal_ack),
.mc_pal_push (mc_pal_push),
// Outputs.
.mc_tc_req (mc_tc_req),
.mc_tc_page (mc_tc_page),
.mc_tc_address (mc_tc_address),
.mc_pal_req (mc_pal_req),
.mc_pal_half (mc_pal_half),
//
.last_pixel_g0 (cmd_done_3d),
.l3_incpat (l3_incpat)
);
assign mc_pal_address = {11'b0, tporg_2};
assign dr_hbdout = hb_dout_3d | hb_dout_2d;
`else
assign dr_hbdout = hb_dout_2d;
`endif
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: FIFO_SUM_IN_SQUARED.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module FIFO_SUM_IN_SQUARED (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [25:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [25:0] q;
wire sub_wire0;
wire sub_wire1;
wire [25:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [25:0] q = sub_wire2[25:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.sclr (sclr),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.aclr (),
.almost_empty (),
.almost_full (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 26,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "26"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "26"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "26"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 26 0 INPUT NODEFVAL "data[25..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 26 0 OUTPUT NODEFVAL "q[25..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 26 0 data 0 0 26 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 26 0 @q 0 0 26 0
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`include "bsg_defines.v"
`timescale 1ps/1ps
// This module is a behavioral model of the clock generator ring
// oscillator. A TSMC 250nm hardened implementation of this module
// can be found at:
//
// bsg_ip_cores/hard/bsg_clk_gen/bsg_clk_gen_osc.v
//
// This module should be replaced by the hardened version
// when being synthesized.
`include "bsg_clk_gen.vh"
module bsg_clk_gen_osc
import bsg_tag_pkg::bsg_tag_s;
#(parameter num_adgs_p=1)
(
input async_reset_i
,input bsg_tag_s bsg_tag_i
,input bsg_tag_s bsg_tag_trigger_i
,output logic clk_o
);
`declare_bsg_clk_gen_osc_tag_payload_s(num_adgs_p)
bsg_clk_gen_osc_tag_payload_s fb_tag_r;
bsg_tag_client_unsync
#(.width_p($bits(bsg_clk_gen_osc_tag_payload_s))
,.harden_p(0)
) btc
(.bsg_tag_i(bsg_tag_i)
,.data_async_r_o(fb_tag_r)
);
logic trig_r;
bsg_tag_client_unsync
#(.width_p(1)
,.harden_p(0)
) btc_trigger
(.bsg_tag_i(bsg_tag_trigger_i)
,.data_async_r_o(trig_r)
);
wire [1:0] cdt = fb_tag_r.cdt;
wire [1:0] fdt = fb_tag_r.fdt;
wire [num_adgs_p-1:0] adg_ctrl = fb_tag_r.adg;
logic [4+num_adgs_p-1:0] ctrl_rrr;
always @(clk_o or async_reset_i)
if (async_reset_i)
ctrl_rrr <= '0;
else
if (trig_r)
ctrl_rrr <= {adg_ctrl, cdt, fdt};
always
begin
#1000
if (ctrl_rrr !== 'X)
# (
((1 << $bits(ctrl_rrr)) - ctrl_rrr)*100
)
clk_o <= ~(clk_o | async_reset_i);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22O_SYMBOL_V
`define SKY130_FD_SC_MS__A22O_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22O_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O32AI_PP_SYMBOL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o32ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_PP_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : round_robin_arb.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// A simple round robin arbiter implemented in a not so simple
// way. Two things make this special. First, it takes width as
// a parameter and secondly it's constructed in a way to work with
// restrictions synthesis programs.
//
// Consider each req/grant pair to be a
// "channel". The arbiter computes a grant response to a request
// on a channel by channel basis.
//
// The arbiter implementes a "round robin" algorithm. Ie, the granting
// process is totally fair and symmetric. Each requester is given
// equal priority. If all requests are asserted, the arbiter will
// work sequentially around the list of requesters, giving each a grant.
//
// Grant priority is based on the "last_master". The last_master
// vector stores the channel receiving the most recent grant. The
// next higher numbered channel (wrapping around to zero) has highest
// priority in subsequent cycles. Relative priority wraps around
// the request vector with the last_master channel having lowest priority.
//
// At the highest implementation level, a per channel inhibit signal is computed.
// This inhibit is bit-wise AND'ed with the incoming requests to
// generate the grant.
//
// There will be at most a single grant per state. The logic
// of the arbiter depends on this.
//
// Once a grant is given, it is stored as the last_master. The
// last_master vector is initialized at reset to the zero'th channel.
// Although the particular channel doesn't matter, it does matter
// that the last_master contains a valid grant pattern.
//
// The heavy lifting is in computing the per channel inhibit signals.
// This is accomplished in the generate statement.
//
// The first "for" loop in the generate statement steps through the channels.
//
// The second "for" loop steps through the last mast_master vector
// for each channel. For each last_master bit, an inh_group is generated.
// Following the end of the second "for" loop, the inh_group signals are OR'ed
// together to generate the overall inhibit bit for the channel.
//
// For a four bit wide arbiter, this is what's generated for channel zero:
//
// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
//
// For req[0], last_master[3] is ignored because channel zero is highest priority
// if last_master[3] is true.
//
`timescale 1ps/1ps
module mig_7series_v2_0_round_robin_arb
#(
parameter TCQ = 100,
parameter WIDTH = 3
)
(
/*AUTOARG*/
// Outputs
grant_ns, grant_r,
// Inputs
clk, rst, req, disable_grant, current_master, upd_last_master
);
input clk;
input rst;
input [WIDTH-1:0] req;
wire [WIDTH-1:0] last_master_ns;
reg [WIDTH*2-1:0] dbl_last_master_ns;
always @(/*AS*/last_master_ns)
dbl_last_master_ns = {last_master_ns, last_master_ns};
reg [WIDTH*2-1:0] dbl_req;
always @(/*AS*/req) dbl_req = {req, req};
reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
genvar i;
genvar j;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : channel
wire [WIDTH-1:1] inh_group;
for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
assign inh_group[j+1] =
dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
end
always @(/*AS*/inh_group) inhibit[i] = |inh_group;
end
endgenerate
input disable_grant;
output wire [WIDTH-1:0] grant_ns;
assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
output reg [WIDTH-1:0] grant_r;
always @(posedge clk) grant_r <= #TCQ grant_ns;
input [WIDTH-1:0] current_master;
input upd_last_master;
reg [WIDTH-1:0] last_master_r;
localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
//A '1' in the LSB of the last_master_r
//signal gives a low priority to req[0]
//after reset. To avoid this made MSB as
//'1' at reset.
assign last_master_ns = rst
? ONE[0+:WIDTH]
: upd_last_master
? current_master
: last_master_r;
always @(posedge clk) last_master_r <= #TCQ last_master_ns;
`ifdef MC_SVA
grant_is_one_hot_zero:
assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
last_master_r_is_one_hot:
assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__AND4B_FUNCTIONAL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and4b (
X ,
A_N,
B ,
C ,
D
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
input D ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B, C, D);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4B_FUNCTIONAL_V |
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// This module only used for simulation, break the loop and injecting the
// glitch
module mbus_err_inject(
input CLK_FAST,
input RESETn,
input CLK_IN,
output reg CLK_OUT,
input DIN,
output reg DOUT,
input [2:0] ERR_TYPE,
input inject_start);
reg [2:0] err_state;
reg [2:0] error_type;
wire int_flag;
reg swap0_rstn;
reg clk_ctrl;
`define ERR_DELAY #500
always @ (posedge CLK_FAST or negedge RESETn)
begin
if (~RESETn)
begin
err_state <= 0;
clk_ctrl <= 0;
error_type <= 0;
end
else
begin
case (err_state)
0:
begin
if (inject_start)
err_state <= 1;
end
1:
begin
case (ERR_TYPE)
// clk glitch
0:
begin
error_type <= 0;
if (~CLK_IN)
err_state <= 2;
end
// missing clk edge
1:
begin
error_type <= 1;
if (~CLK_IN)
err_state <= 2;
end
// clk glitch after interrupt
2:
begin
error_type <= 0;
if (int_flag & (~CLK_IN))
err_state <= 2;
end
// missing clk edge after interrupt
3:
begin
error_type <= 1;
if (int_flag & (~CLK_IN))
err_state <= 2;
end
// clock stuck at 0
4:
begin
error_type <= 2;
if (~CLK_IN)
err_state <= 2;
end
// clock stuck at 1
5:
begin
error_type <= 3;
if (~CLK_IN)
err_state <= 2;
end
endcase
end
2:
begin
err_state <= 3;
case (error_type)
0:
begin
clk_ctrl <= `ERR_DELAY 1;
end
1:
begin
clk_ctrl <= `ERR_DELAY 0;
end
2:
begin
clk_ctrl <= `ERR_DELAY 0;
end
3:
begin
clk_ctrl <= `ERR_DELAY 1;
end
endcase
end
3:
begin
case (error_type)
0:
begin
if (CLK_OUT)
begin
clk_ctrl <= #100 0;
err_state <= 4;
end
end
1:
begin
if (CLK_IN)
begin
err_state <= 4;
end
end
2:
begin
if (~inject_start)
err_state <= 0;
end
3:
begin
if (~inject_start)
err_state <= 0;
end
endcase
end
4:
begin
case (error_type)
0:
begin
if (~CLK_OUT)
err_state <= 5;
end
1:
begin
if (~CLK_IN)
err_state <= 5;
end
endcase
end
5:
begin
if (~inject_start)
err_state <= 0;
end
endcase
end
end
always @ *
begin
CLK_OUT = CLK_IN;
DOUT = DIN;
if ((err_state>1)&&(err_state<5))
begin
case(error_type)
0:
begin
CLK_OUT = (CLK_IN | clk_ctrl);
end
1:
begin
CLK_OUT = (CLK_IN & clk_ctrl);
end
2:
begin
CLK_OUT = (CLK_IN & clk_ctrl);
end
3:
begin
CLK_OUT = (CLK_IN | clk_ctrl);
end
endcase
end
end
mbus_swapper swap0(
.CLK(CLK_IN),
.RESETn(RESETn),
.DATA(DIN),
.INT_FLAG_RESETn(swap0_rstn),
//Outputs
.LAST_CLK(),
.INT_FLAG(int_flag));
always @ (posedge CLK_IN or negedge RESETn)
begin
if (~RESETn)
swap0_rstn <= 1;
else
begin
if (int_flag)
swap0_rstn <= #500 0;
else if (~swap0_rstn)
swap0_rstn <= #500 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_SYMBOL_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2hv_lh (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input LOWHVPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_SYMBOL_V
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module ZynqDesign_processing_system7_0_0 (
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB,
);
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100),
.C_FCLK_CLK1_FREQ(142),
.C_FCLK_CLK2_FREQ(50),
.C_FCLK_CLK3_FREQ(50)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_PP_SYMBOL_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_PP_SYMBOL_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_defines.v
//
// *Module Description:
// openMSP430 Configuration file
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
//`define OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
//============================================================================
//============================================================================
// BASIC SYSTEM CONFIGURATION
//============================================================================
//============================================================================
//
// Note: the sum of program, data and peripheral memory spaces must not
// exceed 64 kB
//
// Program Memory Size:
// Uncomment the required memory size
//-------------------------------------------------------
//`define PMEM_SIZE_CUSTOM
//`define PMEM_SIZE_59_KB
//`define PMEM_SIZE_55_KB
//`define PMEM_SIZE_54_KB
//`define PMEM_SIZE_51_KB
//`define PMEM_SIZE_48_KB
//`define PMEM_SIZE_41_KB
//`define PMEM_SIZE_32_KB
//`define PMEM_SIZE_24_KB
//`define PMEM_SIZE_16_KB
//`define PMEM_SIZE_12_KB
//`define PMEM_SIZE_8_KB
`define PMEM_SIZE_4_KB
//`define PMEM_SIZE_2_KB
//`define PMEM_SIZE_1_KB
// Data Memory Size:
// Uncomment the required memory size
//-------------------------------------------------------
//`define DMEM_SIZE_CUSTOM
//`define DMEM_SIZE_32_KB
//`define DMEM_SIZE_24_KB
//`define DMEM_SIZE_16_KB
//`define DMEM_SIZE_10_KB
//`define DMEM_SIZE_8_KB
//`define DMEM_SIZE_5_KB
//`define DMEM_SIZE_4_KB
//`define DMEM_SIZE_2p5_KB
//`define DMEM_SIZE_2_KB
//`define DMEM_SIZE_1_KB
//`define DMEM_SIZE_512_B
`define DMEM_SIZE_256_B
//`define DMEM_SIZE_128_B
// Include/Exclude Hardware Multiplier
//`define MULTIPLIER
// Include/Exclude Serial Debug interface
`define DBG_EN
//============================================================================
//============================================================================
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
//============================================================================
//============================================================================
//-------------------------------------------------------
// Custom user version number
//-------------------------------------------------------
// This 5 bit field can be freely used in order to allow
// custom identification of the system through the debug
// interface.
// (see CPU_ID.USER_VERSION field in the documentation)
//-------------------------------------------------------
`define USER_VERSION 5'b00011
//-------------------------------------------------------
// Include/Exclude Watchdog timer
//-------------------------------------------------------
// When excluded, the following functionality will be
// lost:
// - Watchog (both interval and watchdog modes)
// - NMI interrupt edge selection
// - Possibility to generate a software PUC reset
//-------------------------------------------------------
`define WATCHDOG
//-------------------------------------------------------
// Include/Exclude DMA interface support
//-------------------------------------------------------
//`define DMA_IF_EN
//-------------------------------------------------------
// Include/Exclude Non-Maskable-Interrupt support
//-------------------------------------------------------
`define NMI
//-------------------------------------------------------
// Number of available IRQs
//-------------------------------------------------------
// Indicates the number of interrupt vectors supported
// (16, 32 or 64).
//-------------------------------------------------------
`define IRQ_16
//`define IRQ_32
//`define IRQ_64
//-------------------------------------------------------
// Input synchronizers
//-------------------------------------------------------
// In some cases, the asynchronous input ports might
// already be synchronized externally.
// If an extensive CDC design review showed that this
// is really the case, the individual synchronizers
// can be disabled with the following defines.
//
// Notes:
// - all three signals are all sampled in the MCLK domain
//
// - the dbg_en signal reset the debug interface
// when 0. Therefore make sure it is glitch free.
//
//-------------------------------------------------------
`define SYNC_NMI
`define SYNC_CPU_EN
`define SYNC_DBG_EN
//-------------------------------------------------------
// Peripheral Memory Space:
//-------------------------------------------------------
// The original MSP430 architecture map the peripherals
// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
// The following defines allow you to expand this space
// up to 32 kB (i.e. from 0x0000 to 0x7fff).
// As a consequence, the data memory mapping will be
// shifted up and a custom linker script will therefore
// be required by the GCC compiler.
//-------------------------------------------------------
//`define PER_SIZE_CUSTOM
//`define PER_SIZE_32_KB
//`define PER_SIZE_16_KB
//`define PER_SIZE_8_KB
//`define PER_SIZE_4_KB
//`define PER_SIZE_2_KB
//`define PER_SIZE_1_KB
`define PER_SIZE_512_B
//-------------------------------------------------------
// Defines the debugger CPU_CTL.RST_BRK_EN reset value
// (CPU break on PUC reset)
//-------------------------------------------------------
// When defined, the CPU will automatically break after
// a PUC occurrence by default. This is typically useful
// when the program memory can only be initialized through
// the serial debug interface.
//-------------------------------------------------------
`define DBG_RST_BRK_EN
//============================================================================
//============================================================================
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//============================================================================
//============================================================================
//
// IMPORTANT NOTE: Please update following configuration options ONLY if
// you have a good reason to do so... and if you know what
// you are doing :-P
//
//============================================================================
//-------------------------------------------------------
// Select serial debug interface protocol
//-------------------------------------------------------
// DBG_UART -> Enable UART (8N1) debug interface
// DBG_I2C -> Enable I2C debug interface
//-------------------------------------------------------
`define DBG_UART
//`define DBG_I2C
//-------------------------------------------------------
// Enable the I2C broadcast address
//-------------------------------------------------------
// For multicore systems, a common I2C broadcast address
// can be given to all oMSP cores in order to
// synchronously RESET, START, STOP, or STEP all CPUs
// at once with a single I2C command.
// If you have a single openMSP430 in your system,
// this option can stay commented-out.
//-------------------------------------------------------
//`define DBG_I2C_BROADCAST
//-------------------------------------------------------
// Number of hardware breakpoint/watchpoint units
// (each unit contains two hardware addresses available
// for breakpoints or watchpoints):
// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//-------------------------------------------------------
// Please keep in mind that hardware breakpoints only
// make sense whenever the program memory is not an SRAM
// (i.e. Flash/OTP/ROM/...) or when you are interested
// in data breakpoints.
//-------------------------------------------------------
//`define DBG_HWBRK_0
//`define DBG_HWBRK_1
//`define DBG_HWBRK_2
//`define DBG_HWBRK_3
//-------------------------------------------------------
// Enable/Disable the hardware breakpoint RANGE mode
//-------------------------------------------------------
// When enabled this feature allows the hardware breakpoint
// units to stop the cpu whenever an instruction or data
// access lays within an address range.
// Note that this feature is not supported by GDB.
//-------------------------------------------------------
//`define DBG_HWBRK_RANGE
//-------------------------------------------------------
// Custom Program/Data and Peripheral Memory Spaces
//-------------------------------------------------------
// The following values are valid only if the
// corresponding *_SIZE_CUSTOM defines are uncommented:
//
// - *_SIZE : size of the section in bytes.
// - *_AWIDTH : address port width, this value must allow
// to address all WORDS of the section
// (i.e. the *_SIZE divided by 2)
//-------------------------------------------------------
// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
`define PMEM_CUSTOM_AWIDTH 10
`define PMEM_CUSTOM_SIZE 2048
// Custom Data memory (enabled with DMEM_SIZE_CUSTOM)
`define DMEM_CUSTOM_AWIDTH 6
`define DMEM_CUSTOM_SIZE 128
// Custom Peripheral memory (enabled with PER_SIZE_CUSTOM)
`define PER_CUSTOM_AWIDTH 8
`define PER_CUSTOM_SIZE 512
//-------------------------------------------------------
// ASIC version
//-------------------------------------------------------
// When uncommented, this define will enable the
// ASIC system configuration section (see below) and
// will activate scan support for production test.
//
// WARNING: if you target an FPGA, leave this define
// commented.
//-------------------------------------------------------
//`define ASIC
//============================================================================
//============================================================================
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
//============================================================================
//============================================================================
`ifdef ASIC
//===============================================================
// FINE GRAINED CLOCK GATING
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the fine
// grained clock gating of all registers in the core.
//-------------------------------------------------------
`define CLOCK_GATING
//===============================================================
// ASIC CLOCKING
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the ASIC
// architectural clock gating as well as the advanced low
// power modes support (most common).
// Comment this out in order to get FPGA-like clocking.
//-------------------------------------------------------
`define ASIC_CLOCKING
`ifdef ASIC_CLOCKING
//===============================================================
// LFXT CLOCK DOMAIN
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the lfxt_clk
// clock domain.
// When commented out, the whole chip is clocked with dco_clk.
//-------------------------------------------------------
`define LFXT_DOMAIN
//===============================================================
// CLOCK MUXES
//===============================================================
//-------------------------------------------------------
// MCLK: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// MCLK clock MUX allowing the selection between
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
// When commented, DCO_CLK is selected.
//-------------------------------------------------------
`define MCLK_MUX
//-------------------------------------------------------
// SMCLK: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// SMCLK clock MUX allowing the selection between
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
// When commented, DCO_CLK is selected.
//-------------------------------------------------------
`define SMCLK_MUX
//-------------------------------------------------------
// WATCHDOG: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// Watchdog clock MUX allowing the selection between
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
// When commented out, ACLK is selected if the
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
// selected otherwise.
//-------------------------------------------------------
`define WATCHDOG_MUX
//`define WATCHDOG_NOMUX_ACLK
//===============================================================
// CLOCK DIVIDERS
//===============================================================
//-------------------------------------------------------
// MCLK: Clock divider
//-------------------------------------------------------
// When uncommented, this define will enable the
// MCLK clock divider (/1/2/4/8)
//-------------------------------------------------------
`define MCLK_DIVIDER
//-------------------------------------------------------
// SMCLK: Clock divider (/1/2/4/8)
//-------------------------------------------------------
// When uncommented, this define will enable the
// SMCLK clock divider
//-------------------------------------------------------
`define SMCLK_DIVIDER
//-------------------------------------------------------
// ACLK: Clock divider (/1/2/4/8)
//-------------------------------------------------------
// When uncommented, this define will enable the
// ACLK clock divider
//-------------------------------------------------------
`define ACLK_DIVIDER
//===============================================================
// LOW POWER MODES
//===============================================================
//-------------------------------------------------------
// LOW POWER MODE: CPUOFF
//-------------------------------------------------------
// When uncommented, this define will include the
// clock gate allowing to switch off MCLK in
// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4
//-------------------------------------------------------
`define CPUOFF_EN
//-------------------------------------------------------
// LOW POWER MODE: SCG0
//-------------------------------------------------------
// When uncommented, this define will enable the
// DCO_ENABLE/WKUP port control (always 1 when commented).
// This allows to switch off the DCO oscillator in the
// following low power modes: LPM1, LPM3, LPM4
//-------------------------------------------------------
`define SCG0_EN
//-------------------------------------------------------
// LOW POWER MODE: SCG1
//-------------------------------------------------------
// When uncommented, this define will include the
// clock gate allowing to switch off SMCLK in
// the following low power modes: LPM2, LPM3, LPM4
//-------------------------------------------------------
`define SCG1_EN
//-------------------------------------------------------
// LOW POWER MODE: OSCOFF
//-------------------------------------------------------
// When uncommented, this define will include the
// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP
// port control (always 1 when commented).
// This allows to switch off the low frequency oscillator
// in the following low power modes: LPM4
//-------------------------------------------------------
`define OSCOFF_EN
//-------------------------------------------------------
// SCAN REPAIR NEG-EDGE CLOCKED FLIP-FLOPS
//-------------------------------------------------------
// When uncommented, a scan mux will be infered to
// replace all inverted clocks with regular ones when
// in scan mode.
//
// Note: standard scan insertion tool can usually deal
// with mixed rising/falling edge FF... so there
// is usually no need to uncomment this.
//-------------------------------------------------------
//`define SCAN_REPAIR_INV_CLOCKS
`endif
`endif
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//
// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
//==================================================
// Program Memory Size
`ifdef PMEM_SIZE_59_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 60416
`endif
`ifdef PMEM_SIZE_55_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 56320
`endif
`ifdef PMEM_SIZE_54_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 55296
`endif
`ifdef PMEM_SIZE_51_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 52224
`endif
`ifdef PMEM_SIZE_48_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 49152
`endif
`ifdef PMEM_SIZE_41_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 41984
`endif
`ifdef PMEM_SIZE_32_KB
`define PMEM_AWIDTH 14
`define PMEM_SIZE 32768
`endif
`ifdef PMEM_SIZE_24_KB
`define PMEM_AWIDTH 14
`define PMEM_SIZE 24576
`endif
`ifdef PMEM_SIZE_16_KB
`define PMEM_AWIDTH 13
`define PMEM_SIZE 16384
`endif
`ifdef PMEM_SIZE_12_KB
`define PMEM_AWIDTH 13
`define PMEM_SIZE 12288
`endif
`ifdef PMEM_SIZE_8_KB
`define PMEM_AWIDTH 12
`define PMEM_SIZE 8192
`endif
`ifdef PMEM_SIZE_4_KB
`define PMEM_AWIDTH 11
`define PMEM_SIZE 4096
`endif
`ifdef PMEM_SIZE_2_KB
`define PMEM_AWIDTH 10
`define PMEM_SIZE 2048
`endif
`ifdef PMEM_SIZE_1_KB
`define PMEM_AWIDTH 9
`define PMEM_SIZE 1024
`endif
`ifdef PMEM_SIZE_CUSTOM
`define PMEM_AWIDTH `PMEM_CUSTOM_AWIDTH
`define PMEM_SIZE `PMEM_CUSTOM_SIZE
`endif
// Data Memory Size
`ifdef DMEM_SIZE_32_KB
`define DMEM_AWIDTH 14
`define DMEM_SIZE 32768
`endif
`ifdef DMEM_SIZE_24_KB
`define DMEM_AWIDTH 14
`define DMEM_SIZE 24576
`endif
`ifdef DMEM_SIZE_16_KB
`define DMEM_AWIDTH 13
`define DMEM_SIZE 16384
`endif
`ifdef DMEM_SIZE_10_KB
`define DMEM_AWIDTH 13
`define DMEM_SIZE 10240
`endif
`ifdef DMEM_SIZE_8_KB
`define DMEM_AWIDTH 12
`define DMEM_SIZE 8192
`endif
`ifdef DMEM_SIZE_5_KB
`define DMEM_AWIDTH 12
`define DMEM_SIZE 5120
`endif
`ifdef DMEM_SIZE_4_KB
`define DMEM_AWIDTH 11
`define DMEM_SIZE 4096
`endif
`ifdef DMEM_SIZE_2p5_KB
`define DMEM_AWIDTH 11
`define DMEM_SIZE 2560
`endif
`ifdef DMEM_SIZE_2_KB
`define DMEM_AWIDTH 10
`define DMEM_SIZE 2048
`endif
`ifdef DMEM_SIZE_1_KB
`define DMEM_AWIDTH 9
`define DMEM_SIZE 1024
`endif
`ifdef DMEM_SIZE_512_B
`define DMEM_AWIDTH 8
`define DMEM_SIZE 512
`endif
`ifdef DMEM_SIZE_256_B
`define DMEM_AWIDTH 7
`define DMEM_SIZE 256
`endif
`ifdef DMEM_SIZE_128_B
`define DMEM_AWIDTH 6
`define DMEM_SIZE 128
`endif
`ifdef DMEM_SIZE_CUSTOM
`define DMEM_AWIDTH `DMEM_CUSTOM_AWIDTH
`define DMEM_SIZE `DMEM_CUSTOM_SIZE
`endif
// Peripheral Memory Size
`ifdef PER_SIZE_32_KB
`define PER_AWIDTH 14
`define PER_SIZE 32768
`endif
`ifdef PER_SIZE_16_KB
`define PER_AWIDTH 13
`define PER_SIZE 16384
`endif
`ifdef PER_SIZE_8_KB
`define PER_AWIDTH 12
`define PER_SIZE 8192
`endif
`ifdef PER_SIZE_4_KB
`define PER_AWIDTH 11
`define PER_SIZE 4096
`endif
`ifdef PER_SIZE_2_KB
`define PER_AWIDTH 10
`define PER_SIZE 2048
`endif
`ifdef PER_SIZE_1_KB
`define PER_AWIDTH 9
`define PER_SIZE 1024
`endif
`ifdef PER_SIZE_512_B
`define PER_AWIDTH 8
`define PER_SIZE 512
`endif
`ifdef PER_SIZE_CUSTOM
`define PER_AWIDTH `PER_CUSTOM_AWIDTH
`define PER_SIZE `PER_CUSTOM_SIZE
`endif
// Data Memory Base Adresses
`define DMEM_BASE `PER_SIZE
// Program & Data Memory most significant address bit (for 16 bit words)
`define PMEM_MSB `PMEM_AWIDTH-1
`define DMEM_MSB `DMEM_AWIDTH-1
`define PER_MSB `PER_AWIDTH-1
// Number of available IRQs
`ifdef IRQ_16
`define IRQ_NR 16
`endif
`ifdef IRQ_32
`define IRQ_NR 32
`define IRQ_NR_GE_32
`endif
`ifdef IRQ_64
`define IRQ_NR 64
`define IRQ_NR_GE_32
`endif
//
// STATES, REGISTER FIELDS, ...
//======================================
// Instructions type
`define INST_SO 0
`define INST_JMP 1
`define INST_TO 2
// Single-operand arithmetic
`define RRC 0
`define SWPB 1
`define RRA 2
`define SXT 3
`define PUSH 4
`define CALL 5
`define RETI 6
`define IRQ 7
// Conditional jump
`define JNE 0
`define JEQ 1
`define JNC 2
`define JC 3
`define JN 4
`define JGE 5
`define JL 6
`define JMP 7
// Two-operand arithmetic
`define MOV 0
`define ADD 1
`define ADDC 2
`define SUBC 3
`define SUB 4
`define CMP 5
`define DADD 6
`define BIT 7
`define BIC 8
`define BIS 9
`define XOR 10
`define AND 11
// Addressing modes
`define DIR 0
`define IDX 1
`define INDIR 2
`define INDIR_I 3
`define SYMB 4
`define IMM 5
`define ABS 6
`define CONST 7
// Instruction state machine
`define I_IRQ_FETCH 3'h0
`define I_IRQ_DONE 3'h1
`define I_DEC 3'h2
`define I_EXT1 3'h3
`define I_EXT2 3'h4
`define I_IDLE 3'h5
// Execution state machine
// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
`define E_IRQ_0 4'h2
`define E_IRQ_1 4'h1
`define E_IRQ_2 4'h0
`define E_IRQ_3 4'h3
`define E_IRQ_4 4'h4
`define E_SRC_AD 4'h5
`define E_SRC_RD 4'h6
`define E_SRC_WR 4'h7
`define E_DST_AD 4'h8
`define E_DST_RD 4'h9
`define E_DST_WR 4'hA
`define E_EXEC 4'hB
`define E_JUMP 4'hC
`define E_IDLE 4'hD
// ALU control signals
`define ALU_SRC_INV 0
`define ALU_INC 1
`define ALU_INC_C 2
`define ALU_ADD 3
`define ALU_AND 4
`define ALU_OR 5
`define ALU_XOR 6
`define ALU_DADD 7
`define ALU_STAT_7 8
`define ALU_STAT_F 9
`define ALU_SHIFT 10
`define EXEC_NO_WR 11
// Debug interface
`define DBG_UART_WR 18
`define DBG_UART_BW 17
`define DBG_UART_ADDR 16:11
// Debug interface CPU_CTL register
`define HALT 0
`define RUN 1
`define ISTEP 2
`define SW_BRK_EN 3
`define FRZ_BRK_EN 4
`define RST_BRK_EN 5
`define CPU_RST 6
// Debug interface CPU_STAT register
`define HALT_RUN 0
`define PUC_PND 1
`define SWBRK_PND 3
`define HWBRK0_PND 4
`define HWBRK1_PND 5
// Debug interface BRKx_CTL register
`define BRK_MODE_RD 0
`define BRK_MODE_WR 1
`define BRK_MODE 1:0
`define BRK_EN 2
`define BRK_I_EN 3
`define BRK_RANGE 4
// Basic clock module: BCSCTL1 Control Register
`define DIVAx 5:4
`define DMA_CPUOFF 0
`define DMA_OSCOFF 1
`define DMA_SCG0 2
`define DMA_SCG1 3
// Basic clock module: BCSCTL2 Control Register
`define SELMx 7
`define DIVMx 5:4
`define SELS 3
`define DIVSx 2:1
// MCLK Clock gate
`ifdef CPUOFF_EN
`define MCLK_CGATE
`else
`ifdef MCLK_DIVIDER
`define MCLK_CGATE
`endif
`endif
// SMCLK Clock gate
`ifdef SCG1_EN
`define SMCLK_CGATE
`else
`ifdef SMCLK_DIVIDER
`define SMCLK_CGATE
`endif
`endif
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
// Debug interface: CPU version
// 1 - FPGA support only (Pre-BSD licence era)
// 2 - Add ASIC support
// 3 - Add DMA interface support
`define CPU_VERSION 3'h3
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
`define DBG_UART_AUTO_SYNC
// Debug UART interface data rate
// In order to properly setup the UART debug interface, you
// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
// the chosen BAUD rate from the UART interface.
//
//`define DBG_UART_BAUD 9600
//`define DBG_UART_BAUD 19200
//`define DBG_UART_BAUD 38400
//`define DBG_UART_BAUD 57600
//`define DBG_UART_BAUD 115200
//`define DBG_UART_BAUD 230400
//`define DBG_UART_BAUD 460800
//`define DBG_UART_BAUD 576000
//`define DBG_UART_BAUD 921600
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ 20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
// Debug interface input synchronizer
`define SYNC_DBG_UART_RXD
// Enable/Disable the hardware breakpoint RANGE mode
`ifdef DBG_HWBRK_RANGE
`define HWBRK_RANGE 1'b1
`else
`define HWBRK_RANGE 1'b0
`endif
// Counter width for the debug interface UART
`define DBG_UART_XFER_CNT_W 16
// Check configuration
`ifdef DBG_EN
`ifdef DBG_UART
`ifdef DBG_I2C
CONFIGURATION ERROR: I2C AND UART DEBUG INTERFACE ARE BOTH ENABLED
`endif
`else
`ifdef DBG_I2C
`else
CONFIGURATION ERROR: I2C OR UART DEBUG INTERFACE SHOULD BE ENABLED
`endif
`endif
`endif
//
// MULTIPLIER CONFIGURATION
//======================================
// If uncommented, the following define selects
// the 16x16 multiplier (1 cycle) instead of the
// default 16x8 multplier (2 cycles)
//`define MPY_16x16
//======================================
// CONFIGURATION CHECKS
//======================================
`ifdef IRQ_16
`ifdef IRQ_32
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`ifdef IRQ_64
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`endif
`ifdef IRQ_32
`ifdef IRQ_64
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`endif
`ifdef LFXT_DOMAIN
`else
`ifdef MCLK_MUX
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`ifdef SMCLK_MUX
CONFIGURATION ERROR: THE SMCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`ifdef WATCHDOG_MUX
CONFIGURATION ERROR: THE WATCHDOG_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`else
`ifdef WATCHDOG_NOMUX_ACLK
CONFIGURATION ERROR: THE WATCHDOG_NOMUX_ACLK CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`endif
`ifdef OSCOFF_EN
CONFIGURATION ERROR: THE OSCOFF LOW POWER MODE CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`endif
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// mem512b is 512 bytes synchronous memory, which maps directly to the EAB memory block of ACEX1K.
// rdaddr is read address, dataout is the data read. Data is read with 1-clock latency, i.e. it
// appears after the positive clock edge, which locked rdaddr.
// wraddr is write address, datain is data to be written. we enables write to memory: when it
// locks as being 1 at positive clock edge, data contained at datain is written to wraddr location.
//
// clk __/``\__/``\__/``\__/``\__/``
// rdaddr |addr1|addr2|
// dataout |data1|data2|
// wraddr |addr3|addr4|
// datain |data3|data4|
// we _________/```````````\_______
//
// data1 is the data read from addr1, data2 is read from addr2
// data3 is written to addr3, data4 is written to addr4
//
// simultaneous write and read to the same memory address lead to undefined read data.
module mem512b
(
input wire clk,
input wire re,
input wire [8:0] rdaddr,
output reg [7:0] dataout,
input wire we,
input wire [8:0] wraddr,
input wire [7:0] datain
);
reg [7:0] mem[0:511]; // memory block
always @(posedge clk)
if( re )
dataout <= mem[rdaddr];
always @(posedge clk)
if( we )
mem[wraddr] <= datain;
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.