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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_4_V
`define SKY130_FD_SC_LS__CLKINV_4_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_4_V
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`timescale 1ns/1ns
module unitTestOVL();
reg clk;
wire rst;
reg a;
reg b;
wire inv;
wire assert_edge, assert_always;
initial begin
clk = 1'b0;
a = 1'b0;
b = 1'b0;
end
assign rst = 1'b0;
assign inv = 1'b0;
//b 0 to 1 then back
//a 0 to 1 directly followed by b 0 to 1 then b back
//a 1 to 0
//a 0 to 1 while b stays at 0
always begin
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
b = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
b = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
a = 1;
b = 1;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
b = 0;
#10 clk = ~clk;
#10 clk = ~clk;
a = 0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
a = 1;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
a = 0;
b = 1;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
end
ovl_always_on_edge_wrapped oaoew(
.clk(clk),
.rst(rst),
.sampling_event(a),
.test_expr(b),
.prevConfigInvalid(inv),
.out(assert_edge)
);
ovl_always_wrapped oaw(
.clk(clk),
.rst(rst),
.test_expr(b),
.prevConfigInvalid(inv),
.out(assert_always)
);
endmodule |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// this is a sine function (approximate), the basic idea is to approximate sine as a
// polynomial function (there are a lot of stuff about this on the web)
`timescale 1ns/100ps
module ad_sine (
// sine = sin(angle)
clk,
angle,
sine,
ddata_in,
ddata_out);
// parameters
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// sine = sin(angle)
input clk;
input [15:0] angle;
output [15:0] sine;
input [DW:0] ddata_in;
output [DW:0] ddata_out;
// internal registers
reg [DW:0] ddata_s2_i = 'd0;
reg data_msb_s2_i = 'd0;
reg [15:0] data_delay_s2_i = 'd0;
reg [15:0] data_sine_s2_i = 'd0;
reg [DW:0] ddata_s2 = 'd0;
reg data_msb_s2 = 'd0;
reg [15:0] data_sine_s2 = 'd0;
reg [DW:0] ddata_s3_i = 'd0;
reg data_msb_s3_i = 'd0;
reg [15:0] data_delay_s3_i = 'd0;
reg [15:0] data_sine_s3_i = 'd0;
reg [DW:0] ddata_out = 'd0;
reg [15:0] sine = 'd0;
// internal signals
wire [DW:0] ddata_s1_s;
wire data_msb_s1_s;
wire [31:0] data_sine_s1_s;
wire [DW:0] ddata_s2_i_s;
wire data_msb_s2_i_s;
wire [15:0] data_delay_s2_i_s;
wire [31:0] data_sine_s2_i_s;
wire [DW:0] ddata_s2_s;
wire data_msb_s2_s;
wire [31:0] data_sine_s2_s;
wire [DW:0] ddata_s3_i_s;
wire data_msb_s3_i_s;
wire [15:0] data_delay_s3_i_s;
wire [31:0] data_sine_s3_i_s;
wire [DW:0] ddata_s3_s;
wire data_msb_s3_s;
wire [31:0] data_sine_s3_s;
// level 1 (intermediate) A*x;
mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s1 (
.clk (clk),
.data_a ({1'b0, angle[14:0]}),
.data_b (16'hc90f),
.data_p (data_sine_s1_s),
.ddata_in ({ddata_in, angle[15]}),
.ddata_out ({ddata_s1_s, data_msb_s1_s}));
// level 1, (final) B*x;
mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s2_i (
.clk (clk),
.data_a (data_sine_s1_s[30:15]),
.data_b (16'h19f0),
.data_p (data_sine_s2_i_s),
.ddata_in ({ddata_s1_s, data_msb_s1_s, data_sine_s1_s[30:15]}),
.ddata_out ({ddata_s2_i_s, data_msb_s2_i_s, data_delay_s2_i_s}));
// level 2 inputs, B*x and (1-A*x)
always @(posedge clk) begin
ddata_s2_i <= ddata_s2_i_s;
data_msb_s2_i <= data_msb_s2_i_s;
data_delay_s2_i <= data_delay_s2_i_s;
data_sine_s2_i <= 16'ha2f9 - data_sine_s2_i_s[28:13];
end
// level 2, second order (A*x2 + B*x)
mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s2 (
.clk (clk),
.data_a (data_delay_s2_i),
.data_b (data_sine_s2_i),
.data_p (data_sine_s2_s),
.ddata_in ({ddata_s2_i, data_msb_s2_i}),
.ddata_out ({ddata_s2_s, data_msb_s2_s}));
always @(posedge clk) begin
ddata_s2 <= ddata_s2_s;
data_msb_s2 <= data_msb_s2_s;
if (data_sine_s2_s[31:29] == 0) begin
data_sine_s2 <= data_sine_s2_s[28:13];
end else begin
data_sine_s2 <= 16'hffff;
end
end
// level 2, intermediate (B*y)
mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s3_i (
.clk (clk),
.data_a (data_sine_s2),
.data_b (16'h3999),
.data_p (data_sine_s3_i_s),
.ddata_in ({ddata_s2, data_msb_s2, data_sine_s2}),
.ddata_out ({ddata_s3_i_s, data_msb_s3_i_s, data_delay_s3_i_s}));
always @(posedge clk) begin
ddata_s3_i <= ddata_s3_i_s;
data_msb_s3_i <= data_msb_s3_i_s;
data_delay_s3_i <= data_delay_s3_i_s;
data_sine_s3_i <= 16'hc666 + data_sine_s3_i_s[31:16];
end
// level 2, second order (A*y2 + B*y)
mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s3 (
.clk (clk),
.data_a (data_delay_s3_i),
.data_b (data_sine_s3_i),
.data_p (data_sine_s3_s),
.ddata_in ({ddata_s3_i, data_msb_s3_i}),
.ddata_out ({ddata_s3_s, data_msb_s3_s}));
always @(posedge clk) begin
ddata_out <= ddata_s3_s;
sine <= {data_msb_s3_s, data_sine_s3_s[31:17]};
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__O21AI_PP_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o21ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_PP_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / General Clock Buffer
// /___/ /\ Filename : BUFG.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFG
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output O,
input I
);
// define constants
localparam MODULE_NAME = "BUFG";
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
buf B1 (O, I);
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninja3.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ninja3 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/ninja3.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/ninja3.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 08 17:42:47 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_rgb888_to_rgb565_0_0 -prefix
// system_rgb888_to_rgb565_0_0_ system_rgb888_to_rgb565_0_0_sim_netlist.v
// Design : system_rgb888_to_rgb565_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "rgb888_to_rgb565,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rgb888_to_rgb565_0_0
(rgb_888,
rgb_565);
input [23:0]rgb_888;
output [15:0]rgb_565;
wire [23:0]rgb_888;
assign rgb_565[15:11] = rgb_888[23:19];
assign rgb_565[10:5] = rgb_888[15:10];
assign rgb_565[4:0] = rgb_888[7:3];
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4BB_BLACKBOX_V
`define SKY130_FD_SC_HS__OR4BB_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4BB_BLACKBOX_V
|
//`include "../common/fpga_regs_common.v"
//`include "../common/fpga_regs_standard.v"
module rx_buffer_inband
( input usbclk,
input bus_reset,
input reset, // DSP side reset (used here), do not reset registers
input reset_regs, //Only reset registers
output [15:0] usbdata,
input RD,
output wire have_pkt_rdy,
output reg rx_overrun,
input wire [3:0] channels,
input wire [15:0] ch_0,
input wire [15:0] ch_1,
input wire [15:0] ch_2,
input wire [15:0] ch_3,
input wire [15:0] ch_4,
input wire [15:0] ch_5,
input wire [15:0] ch_6,
input wire [15:0] ch_7,
input rxclk,
input rxstrobe,
input clear_status,
input [6:0] serial_addr,
input [31:0] serial_data,
input serial_strobe,
output wire [15:0] debugbus,
//Connection with tx_inband
input rx_WR,
input [15:0] rx_databus,
input rx_WR_done,
output reg rx_WR_enabled,
//signal strength
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
input wire [1:0] tx_underrun
);
parameter NUM_CHAN = 1;
genvar i ;
// FX2 Bug Fix
reg [8:0] read_count;
always @(negedge usbclk)
if(bus_reset)
read_count <= #1 9'd0;
else if(RD & ~read_count[8])
read_count <= #1 read_count + 9'd1;
else
read_count <= #1 RD ? read_count : 9'b0;
// Time counter
reg [31:0] timestamp_clock;
always @(posedge rxclk)
if (reset)
timestamp_clock <= 0;
else
timestamp_clock <= timestamp_clock + 1;
// USB side fifo
wire [11:0] rdusedw;
wire [11:0] wrusedw;
wire [15:0] fifodata;
wire [15:0] fifodata_il[0:NUM_CHAN];
wire WR;
wire have_space;
reg sel;
reg wr;
always@(posedge rxclk)
begin
if(reset)
begin
sel<=1;
wr<=0;
end
else if(rxstrobe)
begin
sel<=0;
wr<=1;
end
else if(wr&~sel)
sel<=1;
else if(wr&sel)
wr<=0;
else
wr<=0;
end
assign fifodata_il[0] = (sel)?ch_1:ch_0;
assign fifodata_il[1] = (sel)?ch_3:ch_2;
fifo_4kx16_dc rx_usb_fifo (
.aclr ( reset ),
.data ( fifodata ),
.rdclk ( ~usbclk ),
.rdreq ( RD & ~read_count[8] ),
.wrclk ( rxclk ),
.wrreq ( WR ),
.q ( usbdata ),
.rdempty ( ),
.rdusedw ( rdusedw ),
.wrfull ( ),
.wrusedw ( wrusedw ) );
assign have_pkt_rdy = (rdusedw >= 12'd256);
assign have_space = (wrusedw < 12'd760);
// Rx side fifos
// These are of size [NUM_CHAN:0] because the extra channel is used for the
// RX command channel. If there were no command channel, they would be
// NUM_CHAN-1.
wire chan_rdreq;
wire [15:0] chan_fifodata;
wire [9:0] chan_usedw;
wire [NUM_CHAN:0] chan_empty;
wire [3:0] rd_select;
wire [NUM_CHAN:0] rx_full;
packet_builder #(NUM_CHAN) rx_pkt_builer (
.rxclk ( rxclk ),
.reset ( reset ),
.timestamp_clock ( timestamp_clock ),
.channels ( NUM_CHAN ),
.chan_rdreq ( chan_rdreq ),
.chan_fifodata ( chan_fifodata ),
.chan_empty ( chan_empty ),
.rd_select ( rd_select ),
.chan_usedw ( chan_usedw ),
.WR ( WR ),
.fifodata ( fifodata ),
.have_space ( have_space ),
.rssi_0(rssi_0), .rssi_1(rssi_1),
.rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
.underrun(tx_underrun));
// Detect overrun
always @(posedge rxclk)
if(reset)
rx_overrun <= 1'b0;
else if(rx_full[0])
rx_overrun <= 1'b1;
else if(clear_status)
rx_overrun <= 1'b0;
// FIXME: what is the purpose of these two lines?
wire [15:0]ch[NUM_CHAN:0];
assign ch[0] = ch_0;
wire cmd_empty;
always @(posedge rxclk)
if(reset)
rx_WR_enabled <= 1;
else if(cmd_empty)
rx_WR_enabled <= 1;
else if(rx_WR_done)
rx_WR_enabled <= 0;
// Of Size 0:NUM_CHAN due to extra command channel.
wire [15:0] dataout [0:NUM_CHAN];
wire [9:0] usedw [0:NUM_CHAN];
wire empty[0:NUM_CHAN];
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_fifos
wire rdreq;
assign rdreq = (rd_select == i) & chan_rdreq;
fifo_1kx16 rx_chan_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( fifodata_il[i] ),
.rdreq ( rdreq ),
.wrreq ( ~rx_full[i] & wr),
.empty (empty[i]),
.full (rx_full[i]),
.q ( dataout[i]),
.usedw ( usedw[i]),
.almost_empty(chan_empty[i])
);
end
endgenerate
wire [7:0] debug;
fifo_1kx16 rx_cmd_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( rx_databus ),
.rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
.wrreq ( rx_WR & rx_WR_enabled),
.empty ( cmd_empty),
.full ( rx_full[NUM_CHAN] ),
.q ( dataout[NUM_CHAN]),
.usedw ( usedw[NUM_CHAN] )
);
assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
assign chan_fifodata = dataout[rd_select];
assign chan_usedw = usedw[rd_select];
assign debugbus = {4'd0, rxclk, rxstrobe, rx_full[0], rx_full[1], sel, wr};
endmodule
|
module dmem_tb;
parameter DATA_WIDTH = 32;
parameter BUS_WIDTH = 24;
reg clk;
reg re;
reg we;
reg [DATA_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] wdata;
wire [DATA_WIDTH-1:0] rdata;
dmem #(
.DATA_WIDTH(DATA_WIDTH),
.BUS_WIDTH(BUS_WIDTH)
) dmem (
.clk(clk),
.re(re),
.we(we),
.addr(addr[BUS_WIDTH+1:2]),
.wdata(wdata),
.rdata(rdata)
);
always begin
clk <= ~clk;
#5;
end
initial begin
$dumpfile("vcd/dmem_tb.vcd");
$dumpvars(0, dmem_tb);
$display("clk,\taddr,\t\tre,\twe,\twdata,\t\trdata");
$monitor("%x,\t%x,\t%x,\t%x,\t%x,\t%x",clk, addr, re, we, wdata, rdata);
clk <= 1'b0;
re <= 1'b0;
we <= 1'b0;
addr <= 7'd0;
@(posedge clk);
wdata <= 32'habcdfe01;
addr <= 7'd0;
re <= 1'b0;
we <= 1'b1;
@(posedge clk);
re <= 1'b1;
we <= 1'b0;
@(posedge clk);
wdata <= 32'hffffaaaa;
addr <= 7'd1;
re <= 1'b0;
we <= 1'b1;
@(posedge clk);
re <= 1'b1;
we <= 1'b0;
addr <= 7'd0;
@(posedge clk);
re <= 1'b1;
we <= 1'b0;
addr <= 7'd1;
@(posedge clk);
re <= 1'b1;
we <= 1'b1;
wdata <= 32'hFEFEFEFE;
addr <= 7'd0;
@(posedge clk);
$finish;
end
endmodule |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Mar 31 18:24:55 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top mig_wrap_proc_sys_reset_1_0 -prefix
// mig_wrap_proc_sys_reset_1_0_ mig_wrap_proc_sys_reset_0_0_sim_netlist.v
// Design : mig_wrap_proc_sys_reset_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module mig_wrap_proc_sys_reset_1_0_cdc_sync
(lpf_exr_reg,
scndry_out,
ext_reset_in,
mb_debug_sys_rst,
lpf_exr,
p_3_out,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input ext_reset_in;
input mb_debug_sys_rst;
input lpf_exr;
input [2:0]p_3_out;
input slowest_sync_clk;
wire exr_d1;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(exr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(ext_reset_in),
.I1(mb_debug_sys_rst),
.O(exr_d1));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module mig_wrap_proc_sys_reset_1_0_cdc_sync_0
(lpf_asr_reg,
scndry_out,
aux_reset_in,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input aux_reset_in;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule
module mig_wrap_proc_sys_reset_1_0_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
ext_reset_in,
mb_debug_sys_rst,
aux_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input ext_reset_in;
input mb_debug_sys_rst;
input aux_reset_in;
wire \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
mig_wrap_proc_sys_reset_1_0_cdc_sync \ACTIVE_HIGH_EXT.ACT_HI_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
mig_wrap_proc_sys_reset_1_0_cdc_sync_0 \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFFD))
lpf_int0
(.I0(dcm_locked),
.I1(Q),
.I2(lpf_exr),
.I3(lpf_asr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "mig_wrap_proc_sys_reset_0_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
(* NotValidForBitStream *)
module mig_wrap_proc_sys_reset_1_0
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b1" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "virtex7" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
mig_wrap_proc_sys_reset_1_0_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b1" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "virtex7" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
module mig_wrap_proc_sys_reset_1_0_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Core;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire bsr;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire pr;
wire slowest_sync_clk;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr),
.Q(bus_struct_reset),
.R(1'b0));
mig_wrap_proc_sys_reset_1_0_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\PR_OUT_DFF[0].peripheral_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr),
.Q(peripheral_reset),
.R(1'b0));
mig_wrap_proc_sys_reset_1_0_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] (SEQ_n_4),
.Core(Core),
.bsr(bsr),
.lpf_int(lpf_int),
.pr(pr),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
mb_reset_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core),
.Q(mb_reset),
.R(1'b0));
endmodule
module mig_wrap_proc_sys_reset_1_0_sequence_psr
(Core,
bsr,
pr,
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ,
lpf_int,
slowest_sync_clk);
output Core;
output bsr;
output pr;
output \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
output \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
wire Core;
wire Core_i_1_n_0;
wire bsr;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1
(.I0(bsr),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1
(.I0(pr),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(Core),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b0))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(Core),
.S(lpf_int));
mig_wrap_proc_sys_reset_1_0_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(bsr),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b0))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(bsr),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(Core),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(pr),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b0))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(pr),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
module mig_wrap_proc_sys_reset_1_0_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ns / 1ps
`default_nettype none
module qmca_clk_gen(
input CLKIN, // 48M
output BUS_CLK, // BUS_CLK is 48M output from 1. DCM
output SPI_CLK, // SPI_CLK is 12 MHz (48M / 4 = 12M) output from 1. DCM
output ADC_ENC, // ADC_ENC is 10 MHz ( 80M / 8 = 10 M) output from 2. DCM
output ADC_CLK, // ADC_CLK is 160 MHz ( 80M * 2 = 160 M) output from 1. DCM
output LOCKED
);
wire GND_BIT;
assign GND_BIT = 0;
wire CLKD10MHZ;
wire CLKFX_BUF, CLKOUTFX, CLKDV, CLKDV_BUF;
wire CLK0_BUF; // Buffered input of DCM1
wire CLKFX_160FB; // Feedback to DCM2 (buffered input of DCM2)
wire CLKOUT160, CLKDV_10;
wire CLK2_0;
wire CLKFX_40;
wire CLKFX_160;
wire U2_RST_IN;
wire CLK0_XU2_BUF;
assign ADC_ENC = CLKD10MHZ;
//assign ADC_CLK = CLKFX_160FB; //CLK0_XU2_BUF
//assign ADC_CLK = CLK0_XU2_BUF;
assign ADC_CLK = CLKOUT160;
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), .O(CLKOUTFX));
BUFG CLKFB_BUFG_INST (.I(CLK0_BUF), .O(BUS_CLK));
BUFG CLKDV_BUFG_INST (.I(CLKDV), .O(CLKDV_BUF));
assign SPI_CLK = CLKDV_BUF;
wire LOCKED_U1;
// First DCM gets 48 MHz clock
// --> Makes 160 MHz output on CLKFX (48 * 10/3) for next DCM as input and for ADC_CLK
DCM #(
.CLKDV_DIVIDE(16), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(3), // Can be any Integer from 1 to 32
.CLKFX_MULTIPLY(10), // Can be any Integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(20.833), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an Integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'h8080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
) DCM_BUS (
.CLKFB(BUS_CLK),
.CLKIN(CLKIN),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV),
.CLKFX(CLKFX_160),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_U1),
.PSDONE(),
.STATUS());
// buffer 160 M output from DCM1 and use buffered 160 M as input to DCM2
BUFG CLKFX_2_BUFG_INST (.I(CLKFX_160), .O(CLKOUT160));
BUFG CLKDV_2_BUFG_INST (.I(CLKDV_10), .O(CLKD10MHZ));
// buffer input to DCM2 (160 MHz) and use as feedback for DCM2
BUFG CLKFB_2_BUFG_INST (.I(CLK2_0), .O(CLKFX_160FB));
wire CLK0_XU2;
BUFG CLKFB_2_BUFG_CLK0_XU2 (.I(CLK0_XU2), .O(CLK0_XU2_BUF));
// Second DCM gets 160 MHz clock
// --> Makes 320 MHz output on CLK2X for TDC_320_CLK
// --> Makes 40 MHz output on CLKFX (1 / 4) for TDC_40_CLK
// --> Makes 10 MHz output on CLKDV (1 / 16) for ADC_ENC
DCM #(
.CLKDV_DIVIDE(16), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(8), // Can be any Integer from 1 to 32
.CLKFX_MULTIPLY(2), // Can be any Integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(25.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an Integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'h8080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
) DCM_CMD (
.DSSEN(GND_BIT),
.CLK0(CLK2_0), // 0 degree DCM_SP CLK output
.CLK180(), // 180 degree DCM_SP CLK output
.CLK270(), // 270 degree DCM_SP CLK output
.CLK2X(), // 2X DCM_SP CLK output
.CLK2X180(), // 2X, 180 degree DCM_SP CLK out
.CLK90(CLK0_XU2), // 90 degree DCM_SP CLK output
.CLKDV(CLKDV_10), // Divided DCM_SP CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM_SP CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM_SP LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM_SP status bits output
.CLKFB(CLKFX_160FB), // DCM_SP clock feedback
.CLKIN(CLKOUT160), // Clock input (from IBUFG, BUFG or DCM_SP)
.PSCLK(GND_BIT), // Dynamic phase adjust clock input
.PSEN(GND_BIT), // Dynamic phase adjust enable input
.PSINCDEC(GND_BIT), // Dynamic phase adjust increment/decrement
.RST(U2_RST_IN)// // DCM_SP asynchronous reset input
);
reg [3:0] rst_dly;
initial rst_dly = 0;
always@(posedge BUS_CLK)
rst_dly <= {rst_dly[2:0], !LOCKED_U1};
assign U2_RST_IN = rst_dly[3];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BOI_1_V
`define SKY130_FD_SC_LS__A21BOI_1_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BOI_1_V
|
// DE0_NANO_SOC_QSYS_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 209 at 2014.12.18.15:53:15
`timescale 1 ps / 1 ps
module DE0_NANO_SOC_QSYS_mm_interconnect_0 (
input wire pll_sys_outclk0_clk, // pll_sys_outclk0.clk
input wire nios2_qsys_reset_n_reset_bridge_in_reset_reset, // nios2_qsys_reset_n_reset_bridge_in_reset.reset
input wire onchip_memory2_reset1_reset_bridge_in_reset_reset, // onchip_memory2_reset1_reset_bridge_in_reset.reset
input wire [19:0] nios2_qsys_data_master_address, // nios2_qsys_data_master.address
output wire nios2_qsys_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_qsys_data_master_byteenable, // .byteenable
input wire nios2_qsys_data_master_read, // .read
output wire [31:0] nios2_qsys_data_master_readdata, // .readdata
output wire nios2_qsys_data_master_readdatavalid, // .readdatavalid
input wire nios2_qsys_data_master_write, // .write
input wire [31:0] nios2_qsys_data_master_writedata, // .writedata
input wire nios2_qsys_data_master_debugaccess, // .debugaccess
input wire [19:0] nios2_qsys_instruction_master_address, // nios2_qsys_instruction_master.address
output wire nios2_qsys_instruction_master_waitrequest, // .waitrequest
input wire nios2_qsys_instruction_master_read, // .read
output wire [31:0] nios2_qsys_instruction_master_readdata, // .readdata
output wire nios2_qsys_instruction_master_readdatavalid, // .readdatavalid
output wire [0:0] adc_ltc2308_slave_address, // adc_ltc2308_slave.address
output wire adc_ltc2308_slave_write, // .write
output wire adc_ltc2308_slave_read, // .read
input wire [15:0] adc_ltc2308_slave_readdata, // .readdata
output wire [15:0] adc_ltc2308_slave_writedata, // .writedata
output wire adc_ltc2308_slave_chipselect, // .chipselect
output wire [0:0] jtag_uart_avalon_jtag_slave_address, // jtag_uart_avalon_jtag_slave.address
output wire jtag_uart_avalon_jtag_slave_write, // .write
output wire jtag_uart_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_avalon_jtag_slave_chipselect, // .chipselect
output wire [8:0] nios2_qsys_jtag_debug_module_address, // nios2_qsys_jtag_debug_module.address
output wire nios2_qsys_jtag_debug_module_write, // .write
output wire nios2_qsys_jtag_debug_module_read, // .read
input wire [31:0] nios2_qsys_jtag_debug_module_readdata, // .readdata
output wire [31:0] nios2_qsys_jtag_debug_module_writedata, // .writedata
output wire [3:0] nios2_qsys_jtag_debug_module_byteenable, // .byteenable
input wire nios2_qsys_jtag_debug_module_waitrequest, // .waitrequest
output wire nios2_qsys_jtag_debug_module_debugaccess, // .debugaccess
output wire [15:0] onchip_memory2_s1_address, // onchip_memory2_s1.address
output wire onchip_memory2_s1_write, // .write
input wire [31:0] onchip_memory2_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_s1_byteenable, // .byteenable
output wire onchip_memory2_s1_chipselect, // .chipselect
output wire onchip_memory2_s1_clken, // .clken
output wire [1:0] sw_s1_address, // sw_s1.address
output wire sw_s1_write, // .write
input wire [31:0] sw_s1_readdata, // .readdata
output wire [31:0] sw_s1_writedata, // .writedata
output wire sw_s1_chipselect, // .chipselect
output wire [0:0] sysid_qsys_control_slave_address, // sysid_qsys_control_slave.address
input wire [31:0] sysid_qsys_control_slave_readdata // .readdata
);
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_instruction_master_agent:av_waitrequest -> nios2_qsys_instruction_master_translator:uav_waitrequest
wire [2:0] nios2_qsys_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_instruction_master_translator:uav_burstcount -> nios2_qsys_instruction_master_agent:av_burstcount
wire [31:0] nios2_qsys_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_instruction_master_translator:uav_writedata -> nios2_qsys_instruction_master_agent:av_writedata
wire [19:0] nios2_qsys_instruction_master_translator_avalon_universal_master_0_address; // nios2_qsys_instruction_master_translator:uav_address -> nios2_qsys_instruction_master_agent:av_address
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_lock; // nios2_qsys_instruction_master_translator:uav_lock -> nios2_qsys_instruction_master_agent:av_lock
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_write; // nios2_qsys_instruction_master_translator:uav_write -> nios2_qsys_instruction_master_agent:av_write
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_read; // nios2_qsys_instruction_master_translator:uav_read -> nios2_qsys_instruction_master_agent:av_read
wire [31:0] nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_instruction_master_agent:av_readdata -> nios2_qsys_instruction_master_translator:uav_readdata
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_instruction_master_translator:uav_debugaccess -> nios2_qsys_instruction_master_agent:av_debugaccess
wire [3:0] nios2_qsys_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_instruction_master_translator:uav_byteenable -> nios2_qsys_instruction_master_agent:av_byteenable
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_instruction_master_agent:av_readdatavalid -> nios2_qsys_instruction_master_translator:uav_readdatavalid
wire nios2_qsys_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_data_master_agent:av_waitrequest -> nios2_qsys_data_master_translator:uav_waitrequest
wire [2:0] nios2_qsys_data_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_data_master_translator:uav_burstcount -> nios2_qsys_data_master_agent:av_burstcount
wire [31:0] nios2_qsys_data_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_data_master_translator:uav_writedata -> nios2_qsys_data_master_agent:av_writedata
wire [19:0] nios2_qsys_data_master_translator_avalon_universal_master_0_address; // nios2_qsys_data_master_translator:uav_address -> nios2_qsys_data_master_agent:av_address
wire nios2_qsys_data_master_translator_avalon_universal_master_0_lock; // nios2_qsys_data_master_translator:uav_lock -> nios2_qsys_data_master_agent:av_lock
wire nios2_qsys_data_master_translator_avalon_universal_master_0_write; // nios2_qsys_data_master_translator:uav_write -> nios2_qsys_data_master_agent:av_write
wire nios2_qsys_data_master_translator_avalon_universal_master_0_read; // nios2_qsys_data_master_translator:uav_read -> nios2_qsys_data_master_agent:av_read
wire [31:0] nios2_qsys_data_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_data_master_agent:av_readdata -> nios2_qsys_data_master_translator:uav_readdata
wire nios2_qsys_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_data_master_translator:uav_debugaccess -> nios2_qsys_data_master_agent:av_debugaccess
wire [3:0] nios2_qsys_data_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_data_master_translator:uav_byteenable -> nios2_qsys_data_master_agent:av_byteenable
wire nios2_qsys_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_data_master_agent:av_readdatavalid -> nios2_qsys_data_master_translator:uav_readdatavalid
wire nios2_qsys_jtag_debug_module_agent_m0_waitrequest; // nios2_qsys_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_jtag_debug_module_agent:m0_waitrequest
wire [2:0] nios2_qsys_jtag_debug_module_agent_m0_burstcount; // nios2_qsys_jtag_debug_module_agent:m0_burstcount -> nios2_qsys_jtag_debug_module_translator:uav_burstcount
wire [31:0] nios2_qsys_jtag_debug_module_agent_m0_writedata; // nios2_qsys_jtag_debug_module_agent:m0_writedata -> nios2_qsys_jtag_debug_module_translator:uav_writedata
wire [19:0] nios2_qsys_jtag_debug_module_agent_m0_address; // nios2_qsys_jtag_debug_module_agent:m0_address -> nios2_qsys_jtag_debug_module_translator:uav_address
wire nios2_qsys_jtag_debug_module_agent_m0_write; // nios2_qsys_jtag_debug_module_agent:m0_write -> nios2_qsys_jtag_debug_module_translator:uav_write
wire nios2_qsys_jtag_debug_module_agent_m0_lock; // nios2_qsys_jtag_debug_module_agent:m0_lock -> nios2_qsys_jtag_debug_module_translator:uav_lock
wire nios2_qsys_jtag_debug_module_agent_m0_read; // nios2_qsys_jtag_debug_module_agent:m0_read -> nios2_qsys_jtag_debug_module_translator:uav_read
wire [31:0] nios2_qsys_jtag_debug_module_agent_m0_readdata; // nios2_qsys_jtag_debug_module_translator:uav_readdata -> nios2_qsys_jtag_debug_module_agent:m0_readdata
wire nios2_qsys_jtag_debug_module_agent_m0_readdatavalid; // nios2_qsys_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_jtag_debug_module_agent:m0_readdatavalid
wire nios2_qsys_jtag_debug_module_agent_m0_debugaccess; // nios2_qsys_jtag_debug_module_agent:m0_debugaccess -> nios2_qsys_jtag_debug_module_translator:uav_debugaccess
wire [3:0] nios2_qsys_jtag_debug_module_agent_m0_byteenable; // nios2_qsys_jtag_debug_module_agent:m0_byteenable -> nios2_qsys_jtag_debug_module_translator:uav_byteenable
wire nios2_qsys_jtag_debug_module_agent_rf_source_endofpacket; // nios2_qsys_jtag_debug_module_agent:rf_source_endofpacket -> nios2_qsys_jtag_debug_module_agent_rsp_fifo:in_endofpacket
wire nios2_qsys_jtag_debug_module_agent_rf_source_valid; // nios2_qsys_jtag_debug_module_agent:rf_source_valid -> nios2_qsys_jtag_debug_module_agent_rsp_fifo:in_valid
wire nios2_qsys_jtag_debug_module_agent_rf_source_startofpacket; // nios2_qsys_jtag_debug_module_agent:rf_source_startofpacket -> nios2_qsys_jtag_debug_module_agent_rsp_fifo:in_startofpacket
wire [96:0] nios2_qsys_jtag_debug_module_agent_rf_source_data; // nios2_qsys_jtag_debug_module_agent:rf_source_data -> nios2_qsys_jtag_debug_module_agent_rsp_fifo:in_data
wire nios2_qsys_jtag_debug_module_agent_rf_source_ready; // nios2_qsys_jtag_debug_module_agent_rsp_fifo:in_ready -> nios2_qsys_jtag_debug_module_agent:rf_source_ready
wire nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_endofpacket; // nios2_qsys_jtag_debug_module_agent_rsp_fifo:out_endofpacket -> nios2_qsys_jtag_debug_module_agent:rf_sink_endofpacket
wire nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_valid; // nios2_qsys_jtag_debug_module_agent_rsp_fifo:out_valid -> nios2_qsys_jtag_debug_module_agent:rf_sink_valid
wire nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_startofpacket; // nios2_qsys_jtag_debug_module_agent_rsp_fifo:out_startofpacket -> nios2_qsys_jtag_debug_module_agent:rf_sink_startofpacket
wire [96:0] nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_data; // nios2_qsys_jtag_debug_module_agent_rsp_fifo:out_data -> nios2_qsys_jtag_debug_module_agent:rf_sink_data
wire nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_ready; // nios2_qsys_jtag_debug_module_agent:rf_sink_ready -> nios2_qsys_jtag_debug_module_agent_rsp_fifo:out_ready
wire nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_valid; // nios2_qsys_jtag_debug_module_agent:rdata_fifo_src_valid -> nios2_qsys_jtag_debug_module_agent:rdata_fifo_sink_valid
wire [33:0] nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_data; // nios2_qsys_jtag_debug_module_agent:rdata_fifo_src_data -> nios2_qsys_jtag_debug_module_agent:rdata_fifo_sink_data
wire nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_ready; // nios2_qsys_jtag_debug_module_agent:rdata_fifo_sink_ready -> nios2_qsys_jtag_debug_module_agent:rdata_fifo_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> nios2_qsys_jtag_debug_module_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> nios2_qsys_jtag_debug_module_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> nios2_qsys_jtag_debug_module_agent:cp_startofpacket
wire [95:0] cmd_mux_src_data; // cmd_mux:src_data -> nios2_qsys_jtag_debug_module_agent:cp_data
wire [5:0] cmd_mux_src_channel; // cmd_mux:src_channel -> nios2_qsys_jtag_debug_module_agent:cp_channel
wire cmd_mux_src_ready; // nios2_qsys_jtag_debug_module_agent:cp_ready -> cmd_mux:src_ready
wire onchip_memory2_s1_agent_m0_waitrequest; // onchip_memory2_s1_translator:uav_waitrequest -> onchip_memory2_s1_agent:m0_waitrequest
wire [2:0] onchip_memory2_s1_agent_m0_burstcount; // onchip_memory2_s1_agent:m0_burstcount -> onchip_memory2_s1_translator:uav_burstcount
wire [31:0] onchip_memory2_s1_agent_m0_writedata; // onchip_memory2_s1_agent:m0_writedata -> onchip_memory2_s1_translator:uav_writedata
wire [19:0] onchip_memory2_s1_agent_m0_address; // onchip_memory2_s1_agent:m0_address -> onchip_memory2_s1_translator:uav_address
wire onchip_memory2_s1_agent_m0_write; // onchip_memory2_s1_agent:m0_write -> onchip_memory2_s1_translator:uav_write
wire onchip_memory2_s1_agent_m0_lock; // onchip_memory2_s1_agent:m0_lock -> onchip_memory2_s1_translator:uav_lock
wire onchip_memory2_s1_agent_m0_read; // onchip_memory2_s1_agent:m0_read -> onchip_memory2_s1_translator:uav_read
wire [31:0] onchip_memory2_s1_agent_m0_readdata; // onchip_memory2_s1_translator:uav_readdata -> onchip_memory2_s1_agent:m0_readdata
wire onchip_memory2_s1_agent_m0_readdatavalid; // onchip_memory2_s1_translator:uav_readdatavalid -> onchip_memory2_s1_agent:m0_readdatavalid
wire onchip_memory2_s1_agent_m0_debugaccess; // onchip_memory2_s1_agent:m0_debugaccess -> onchip_memory2_s1_translator:uav_debugaccess
wire [3:0] onchip_memory2_s1_agent_m0_byteenable; // onchip_memory2_s1_agent:m0_byteenable -> onchip_memory2_s1_translator:uav_byteenable
wire onchip_memory2_s1_agent_rf_source_endofpacket; // onchip_memory2_s1_agent:rf_source_endofpacket -> onchip_memory2_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_s1_agent_rf_source_valid; // onchip_memory2_s1_agent:rf_source_valid -> onchip_memory2_s1_agent_rsp_fifo:in_valid
wire onchip_memory2_s1_agent_rf_source_startofpacket; // onchip_memory2_s1_agent:rf_source_startofpacket -> onchip_memory2_s1_agent_rsp_fifo:in_startofpacket
wire [96:0] onchip_memory2_s1_agent_rf_source_data; // onchip_memory2_s1_agent:rf_source_data -> onchip_memory2_s1_agent_rsp_fifo:in_data
wire onchip_memory2_s1_agent_rf_source_ready; // onchip_memory2_s1_agent_rsp_fifo:in_ready -> onchip_memory2_s1_agent:rf_source_ready
wire onchip_memory2_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_s1_agent:rf_sink_endofpacket
wire onchip_memory2_s1_agent_rsp_fifo_out_valid; // onchip_memory2_s1_agent_rsp_fifo:out_valid -> onchip_memory2_s1_agent:rf_sink_valid
wire onchip_memory2_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_s1_agent:rf_sink_startofpacket
wire [96:0] onchip_memory2_s1_agent_rsp_fifo_out_data; // onchip_memory2_s1_agent_rsp_fifo:out_data -> onchip_memory2_s1_agent:rf_sink_data
wire onchip_memory2_s1_agent_rsp_fifo_out_ready; // onchip_memory2_s1_agent:rf_sink_ready -> onchip_memory2_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_s1_agent_rdata_fifo_src_valid; // onchip_memory2_s1_agent:rdata_fifo_src_valid -> onchip_memory2_s1_agent:rdata_fifo_sink_valid
wire [33:0] onchip_memory2_s1_agent_rdata_fifo_src_data; // onchip_memory2_s1_agent:rdata_fifo_src_data -> onchip_memory2_s1_agent:rdata_fifo_sink_data
wire onchip_memory2_s1_agent_rdata_fifo_src_ready; // onchip_memory2_s1_agent:rdata_fifo_sink_ready -> onchip_memory2_s1_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> onchip_memory2_s1_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> onchip_memory2_s1_agent:cp_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> onchip_memory2_s1_agent:cp_startofpacket
wire [95:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> onchip_memory2_s1_agent:cp_data
wire [5:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> onchip_memory2_s1_agent:cp_channel
wire cmd_mux_001_src_ready; // onchip_memory2_s1_agent:cp_ready -> cmd_mux_001:src_ready
wire sysid_qsys_control_slave_agent_m0_waitrequest; // sysid_qsys_control_slave_translator:uav_waitrequest -> sysid_qsys_control_slave_agent:m0_waitrequest
wire [2:0] sysid_qsys_control_slave_agent_m0_burstcount; // sysid_qsys_control_slave_agent:m0_burstcount -> sysid_qsys_control_slave_translator:uav_burstcount
wire [31:0] sysid_qsys_control_slave_agent_m0_writedata; // sysid_qsys_control_slave_agent:m0_writedata -> sysid_qsys_control_slave_translator:uav_writedata
wire [19:0] sysid_qsys_control_slave_agent_m0_address; // sysid_qsys_control_slave_agent:m0_address -> sysid_qsys_control_slave_translator:uav_address
wire sysid_qsys_control_slave_agent_m0_write; // sysid_qsys_control_slave_agent:m0_write -> sysid_qsys_control_slave_translator:uav_write
wire sysid_qsys_control_slave_agent_m0_lock; // sysid_qsys_control_slave_agent:m0_lock -> sysid_qsys_control_slave_translator:uav_lock
wire sysid_qsys_control_slave_agent_m0_read; // sysid_qsys_control_slave_agent:m0_read -> sysid_qsys_control_slave_translator:uav_read
wire [31:0] sysid_qsys_control_slave_agent_m0_readdata; // sysid_qsys_control_slave_translator:uav_readdata -> sysid_qsys_control_slave_agent:m0_readdata
wire sysid_qsys_control_slave_agent_m0_readdatavalid; // sysid_qsys_control_slave_translator:uav_readdatavalid -> sysid_qsys_control_slave_agent:m0_readdatavalid
wire sysid_qsys_control_slave_agent_m0_debugaccess; // sysid_qsys_control_slave_agent:m0_debugaccess -> sysid_qsys_control_slave_translator:uav_debugaccess
wire [3:0] sysid_qsys_control_slave_agent_m0_byteenable; // sysid_qsys_control_slave_agent:m0_byteenable -> sysid_qsys_control_slave_translator:uav_byteenable
wire sysid_qsys_control_slave_agent_rf_source_endofpacket; // sysid_qsys_control_slave_agent:rf_source_endofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_endofpacket
wire sysid_qsys_control_slave_agent_rf_source_valid; // sysid_qsys_control_slave_agent:rf_source_valid -> sysid_qsys_control_slave_agent_rsp_fifo:in_valid
wire sysid_qsys_control_slave_agent_rf_source_startofpacket; // sysid_qsys_control_slave_agent:rf_source_startofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_startofpacket
wire [96:0] sysid_qsys_control_slave_agent_rf_source_data; // sysid_qsys_control_slave_agent:rf_source_data -> sysid_qsys_control_slave_agent_rsp_fifo:in_data
wire sysid_qsys_control_slave_agent_rf_source_ready; // sysid_qsys_control_slave_agent_rsp_fifo:in_ready -> sysid_qsys_control_slave_agent:rf_source_ready
wire sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket; // sysid_qsys_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_qsys_control_slave_agent:rf_sink_endofpacket
wire sysid_qsys_control_slave_agent_rsp_fifo_out_valid; // sysid_qsys_control_slave_agent_rsp_fifo:out_valid -> sysid_qsys_control_slave_agent:rf_sink_valid
wire sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket; // sysid_qsys_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_qsys_control_slave_agent:rf_sink_startofpacket
wire [96:0] sysid_qsys_control_slave_agent_rsp_fifo_out_data; // sysid_qsys_control_slave_agent_rsp_fifo:out_data -> sysid_qsys_control_slave_agent:rf_sink_data
wire sysid_qsys_control_slave_agent_rsp_fifo_out_ready; // sysid_qsys_control_slave_agent:rf_sink_ready -> sysid_qsys_control_slave_agent_rsp_fifo:out_ready
wire sysid_qsys_control_slave_agent_rdata_fifo_src_valid; // sysid_qsys_control_slave_agent:rdata_fifo_src_valid -> sysid_qsys_control_slave_agent:rdata_fifo_sink_valid
wire [33:0] sysid_qsys_control_slave_agent_rdata_fifo_src_data; // sysid_qsys_control_slave_agent:rdata_fifo_src_data -> sysid_qsys_control_slave_agent:rdata_fifo_sink_data
wire sysid_qsys_control_slave_agent_rdata_fifo_src_ready; // sysid_qsys_control_slave_agent:rdata_fifo_sink_ready -> sysid_qsys_control_slave_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sysid_qsys_control_slave_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sysid_qsys_control_slave_agent:cp_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sysid_qsys_control_slave_agent:cp_startofpacket
wire [95:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sysid_qsys_control_slave_agent:cp_data
wire [5:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sysid_qsys_control_slave_agent:cp_channel
wire cmd_mux_002_src_ready; // sysid_qsys_control_slave_agent:cp_ready -> cmd_mux_002:src_ready
wire jtag_uart_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
wire [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
wire [19:0] jtag_uart_avalon_jtag_slave_agent_m0_address; // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
wire jtag_uart_avalon_jtag_slave_agent_m0_write; // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
wire jtag_uart_avalon_jtag_slave_agent_m0_lock; // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
wire jtag_uart_avalon_jtag_slave_agent_m0_read; // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
wire [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire [96:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
wire [96:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
wire [95:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
wire [5:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_003_src_ready; // jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux_003:src_ready
wire adc_ltc2308_slave_agent_m0_waitrequest; // adc_ltc2308_slave_translator:uav_waitrequest -> adc_ltc2308_slave_agent:m0_waitrequest
wire [2:0] adc_ltc2308_slave_agent_m0_burstcount; // adc_ltc2308_slave_agent:m0_burstcount -> adc_ltc2308_slave_translator:uav_burstcount
wire [31:0] adc_ltc2308_slave_agent_m0_writedata; // adc_ltc2308_slave_agent:m0_writedata -> adc_ltc2308_slave_translator:uav_writedata
wire [19:0] adc_ltc2308_slave_agent_m0_address; // adc_ltc2308_slave_agent:m0_address -> adc_ltc2308_slave_translator:uav_address
wire adc_ltc2308_slave_agent_m0_write; // adc_ltc2308_slave_agent:m0_write -> adc_ltc2308_slave_translator:uav_write
wire adc_ltc2308_slave_agent_m0_lock; // adc_ltc2308_slave_agent:m0_lock -> adc_ltc2308_slave_translator:uav_lock
wire adc_ltc2308_slave_agent_m0_read; // adc_ltc2308_slave_agent:m0_read -> adc_ltc2308_slave_translator:uav_read
wire [31:0] adc_ltc2308_slave_agent_m0_readdata; // adc_ltc2308_slave_translator:uav_readdata -> adc_ltc2308_slave_agent:m0_readdata
wire adc_ltc2308_slave_agent_m0_readdatavalid; // adc_ltc2308_slave_translator:uav_readdatavalid -> adc_ltc2308_slave_agent:m0_readdatavalid
wire adc_ltc2308_slave_agent_m0_debugaccess; // adc_ltc2308_slave_agent:m0_debugaccess -> adc_ltc2308_slave_translator:uav_debugaccess
wire [3:0] adc_ltc2308_slave_agent_m0_byteenable; // adc_ltc2308_slave_agent:m0_byteenable -> adc_ltc2308_slave_translator:uav_byteenable
wire adc_ltc2308_slave_agent_rf_source_endofpacket; // adc_ltc2308_slave_agent:rf_source_endofpacket -> adc_ltc2308_slave_agent_rsp_fifo:in_endofpacket
wire adc_ltc2308_slave_agent_rf_source_valid; // adc_ltc2308_slave_agent:rf_source_valid -> adc_ltc2308_slave_agent_rsp_fifo:in_valid
wire adc_ltc2308_slave_agent_rf_source_startofpacket; // adc_ltc2308_slave_agent:rf_source_startofpacket -> adc_ltc2308_slave_agent_rsp_fifo:in_startofpacket
wire [96:0] adc_ltc2308_slave_agent_rf_source_data; // adc_ltc2308_slave_agent:rf_source_data -> adc_ltc2308_slave_agent_rsp_fifo:in_data
wire adc_ltc2308_slave_agent_rf_source_ready; // adc_ltc2308_slave_agent_rsp_fifo:in_ready -> adc_ltc2308_slave_agent:rf_source_ready
wire adc_ltc2308_slave_agent_rsp_fifo_out_endofpacket; // adc_ltc2308_slave_agent_rsp_fifo:out_endofpacket -> adc_ltc2308_slave_agent:rf_sink_endofpacket
wire adc_ltc2308_slave_agent_rsp_fifo_out_valid; // adc_ltc2308_slave_agent_rsp_fifo:out_valid -> adc_ltc2308_slave_agent:rf_sink_valid
wire adc_ltc2308_slave_agent_rsp_fifo_out_startofpacket; // adc_ltc2308_slave_agent_rsp_fifo:out_startofpacket -> adc_ltc2308_slave_agent:rf_sink_startofpacket
wire [96:0] adc_ltc2308_slave_agent_rsp_fifo_out_data; // adc_ltc2308_slave_agent_rsp_fifo:out_data -> adc_ltc2308_slave_agent:rf_sink_data
wire adc_ltc2308_slave_agent_rsp_fifo_out_ready; // adc_ltc2308_slave_agent:rf_sink_ready -> adc_ltc2308_slave_agent_rsp_fifo:out_ready
wire adc_ltc2308_slave_agent_rdata_fifo_src_valid; // adc_ltc2308_slave_agent:rdata_fifo_src_valid -> adc_ltc2308_slave_agent:rdata_fifo_sink_valid
wire [33:0] adc_ltc2308_slave_agent_rdata_fifo_src_data; // adc_ltc2308_slave_agent:rdata_fifo_src_data -> adc_ltc2308_slave_agent:rdata_fifo_sink_data
wire adc_ltc2308_slave_agent_rdata_fifo_src_ready; // adc_ltc2308_slave_agent:rdata_fifo_sink_ready -> adc_ltc2308_slave_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> adc_ltc2308_slave_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> adc_ltc2308_slave_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> adc_ltc2308_slave_agent:cp_startofpacket
wire [95:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> adc_ltc2308_slave_agent:cp_data
wire [5:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> adc_ltc2308_slave_agent:cp_channel
wire cmd_mux_004_src_ready; // adc_ltc2308_slave_agent:cp_ready -> cmd_mux_004:src_ready
wire sw_s1_agent_m0_waitrequest; // sw_s1_translator:uav_waitrequest -> sw_s1_agent:m0_waitrequest
wire [2:0] sw_s1_agent_m0_burstcount; // sw_s1_agent:m0_burstcount -> sw_s1_translator:uav_burstcount
wire [31:0] sw_s1_agent_m0_writedata; // sw_s1_agent:m0_writedata -> sw_s1_translator:uav_writedata
wire [19:0] sw_s1_agent_m0_address; // sw_s1_agent:m0_address -> sw_s1_translator:uav_address
wire sw_s1_agent_m0_write; // sw_s1_agent:m0_write -> sw_s1_translator:uav_write
wire sw_s1_agent_m0_lock; // sw_s1_agent:m0_lock -> sw_s1_translator:uav_lock
wire sw_s1_agent_m0_read; // sw_s1_agent:m0_read -> sw_s1_translator:uav_read
wire [31:0] sw_s1_agent_m0_readdata; // sw_s1_translator:uav_readdata -> sw_s1_agent:m0_readdata
wire sw_s1_agent_m0_readdatavalid; // sw_s1_translator:uav_readdatavalid -> sw_s1_agent:m0_readdatavalid
wire sw_s1_agent_m0_debugaccess; // sw_s1_agent:m0_debugaccess -> sw_s1_translator:uav_debugaccess
wire [3:0] sw_s1_agent_m0_byteenable; // sw_s1_agent:m0_byteenable -> sw_s1_translator:uav_byteenable
wire sw_s1_agent_rf_source_endofpacket; // sw_s1_agent:rf_source_endofpacket -> sw_s1_agent_rsp_fifo:in_endofpacket
wire sw_s1_agent_rf_source_valid; // sw_s1_agent:rf_source_valid -> sw_s1_agent_rsp_fifo:in_valid
wire sw_s1_agent_rf_source_startofpacket; // sw_s1_agent:rf_source_startofpacket -> sw_s1_agent_rsp_fifo:in_startofpacket
wire [96:0] sw_s1_agent_rf_source_data; // sw_s1_agent:rf_source_data -> sw_s1_agent_rsp_fifo:in_data
wire sw_s1_agent_rf_source_ready; // sw_s1_agent_rsp_fifo:in_ready -> sw_s1_agent:rf_source_ready
wire sw_s1_agent_rsp_fifo_out_endofpacket; // sw_s1_agent_rsp_fifo:out_endofpacket -> sw_s1_agent:rf_sink_endofpacket
wire sw_s1_agent_rsp_fifo_out_valid; // sw_s1_agent_rsp_fifo:out_valid -> sw_s1_agent:rf_sink_valid
wire sw_s1_agent_rsp_fifo_out_startofpacket; // sw_s1_agent_rsp_fifo:out_startofpacket -> sw_s1_agent:rf_sink_startofpacket
wire [96:0] sw_s1_agent_rsp_fifo_out_data; // sw_s1_agent_rsp_fifo:out_data -> sw_s1_agent:rf_sink_data
wire sw_s1_agent_rsp_fifo_out_ready; // sw_s1_agent:rf_sink_ready -> sw_s1_agent_rsp_fifo:out_ready
wire sw_s1_agent_rdata_fifo_src_valid; // sw_s1_agent:rdata_fifo_src_valid -> sw_s1_agent:rdata_fifo_sink_valid
wire [33:0] sw_s1_agent_rdata_fifo_src_data; // sw_s1_agent:rdata_fifo_src_data -> sw_s1_agent:rdata_fifo_sink_data
wire sw_s1_agent_rdata_fifo_src_ready; // sw_s1_agent:rdata_fifo_sink_ready -> sw_s1_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> sw_s1_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> sw_s1_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> sw_s1_agent:cp_startofpacket
wire [95:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> sw_s1_agent:cp_data
wire [5:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> sw_s1_agent:cp_channel
wire cmd_mux_005_src_ready; // sw_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire nios2_qsys_instruction_master_agent_cp_endofpacket; // nios2_qsys_instruction_master_agent:cp_endofpacket -> router:sink_endofpacket
wire nios2_qsys_instruction_master_agent_cp_valid; // nios2_qsys_instruction_master_agent:cp_valid -> router:sink_valid
wire nios2_qsys_instruction_master_agent_cp_startofpacket; // nios2_qsys_instruction_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [95:0] nios2_qsys_instruction_master_agent_cp_data; // nios2_qsys_instruction_master_agent:cp_data -> router:sink_data
wire nios2_qsys_instruction_master_agent_cp_ready; // router:sink_ready -> nios2_qsys_instruction_master_agent:cp_ready
wire nios2_qsys_data_master_agent_cp_endofpacket; // nios2_qsys_data_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire nios2_qsys_data_master_agent_cp_valid; // nios2_qsys_data_master_agent:cp_valid -> router_001:sink_valid
wire nios2_qsys_data_master_agent_cp_startofpacket; // nios2_qsys_data_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire [95:0] nios2_qsys_data_master_agent_cp_data; // nios2_qsys_data_master_agent:cp_data -> router_001:sink_data
wire nios2_qsys_data_master_agent_cp_ready; // router_001:sink_ready -> nios2_qsys_data_master_agent:cp_ready
wire nios2_qsys_jtag_debug_module_agent_rp_endofpacket; // nios2_qsys_jtag_debug_module_agent:rp_endofpacket -> router_002:sink_endofpacket
wire nios2_qsys_jtag_debug_module_agent_rp_valid; // nios2_qsys_jtag_debug_module_agent:rp_valid -> router_002:sink_valid
wire nios2_qsys_jtag_debug_module_agent_rp_startofpacket; // nios2_qsys_jtag_debug_module_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [95:0] nios2_qsys_jtag_debug_module_agent_rp_data; // nios2_qsys_jtag_debug_module_agent:rp_data -> router_002:sink_data
wire nios2_qsys_jtag_debug_module_agent_rp_ready; // router_002:sink_ready -> nios2_qsys_jtag_debug_module_agent:rp_ready
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire [95:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire [5:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire onchip_memory2_s1_agent_rp_endofpacket; // onchip_memory2_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire onchip_memory2_s1_agent_rp_valid; // onchip_memory2_s1_agent:rp_valid -> router_003:sink_valid
wire onchip_memory2_s1_agent_rp_startofpacket; // onchip_memory2_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [95:0] onchip_memory2_s1_agent_rp_data; // onchip_memory2_s1_agent:rp_data -> router_003:sink_data
wire onchip_memory2_s1_agent_rp_ready; // router_003:sink_ready -> onchip_memory2_s1_agent:rp_ready
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire [95:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire [5:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire sysid_qsys_control_slave_agent_rp_endofpacket; // sysid_qsys_control_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire sysid_qsys_control_slave_agent_rp_valid; // sysid_qsys_control_slave_agent:rp_valid -> router_004:sink_valid
wire sysid_qsys_control_slave_agent_rp_startofpacket; // sysid_qsys_control_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [95:0] sysid_qsys_control_slave_agent_rp_data; // sysid_qsys_control_slave_agent:rp_data -> router_004:sink_data
wire sysid_qsys_control_slave_agent_rp_ready; // router_004:sink_ready -> sysid_qsys_control_slave_agent:rp_ready
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire [95:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire [5:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire jtag_uart_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_005:sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_valid; // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_005:sink_valid
wire jtag_uart_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [95:0] jtag_uart_avalon_jtag_slave_agent_rp_data; // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_005:sink_data
wire jtag_uart_avalon_jtag_slave_agent_rp_ready; // router_005:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire [95:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire [5:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire adc_ltc2308_slave_agent_rp_endofpacket; // adc_ltc2308_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
wire adc_ltc2308_slave_agent_rp_valid; // adc_ltc2308_slave_agent:rp_valid -> router_006:sink_valid
wire adc_ltc2308_slave_agent_rp_startofpacket; // adc_ltc2308_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [95:0] adc_ltc2308_slave_agent_rp_data; // adc_ltc2308_slave_agent:rp_data -> router_006:sink_data
wire adc_ltc2308_slave_agent_rp_ready; // router_006:sink_ready -> adc_ltc2308_slave_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [95:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire [5:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire sw_s1_agent_rp_endofpacket; // sw_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire sw_s1_agent_rp_valid; // sw_s1_agent:rp_valid -> router_007:sink_valid
wire sw_s1_agent_rp_startofpacket; // sw_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire [95:0] sw_s1_agent_rp_data; // sw_s1_agent:rp_data -> router_007:sink_data
wire sw_s1_agent_rp_ready; // router_007:sink_ready -> sw_s1_agent:rp_ready
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [95:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire [5:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> nios2_qsys_instruction_master_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> nios2_qsys_instruction_master_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> nios2_qsys_instruction_master_limiter:cmd_sink_startofpacket
wire [95:0] router_src_data; // router:src_data -> nios2_qsys_instruction_master_limiter:cmd_sink_data
wire [5:0] router_src_channel; // router:src_channel -> nios2_qsys_instruction_master_limiter:cmd_sink_channel
wire router_src_ready; // nios2_qsys_instruction_master_limiter:cmd_sink_ready -> router:src_ready
wire nios2_qsys_instruction_master_limiter_cmd_src_endofpacket; // nios2_qsys_instruction_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_qsys_instruction_master_limiter_cmd_src_startofpacket; // nios2_qsys_instruction_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [95:0] nios2_qsys_instruction_master_limiter_cmd_src_data; // nios2_qsys_instruction_master_limiter:cmd_src_data -> cmd_demux:sink_data
wire [5:0] nios2_qsys_instruction_master_limiter_cmd_src_channel; // nios2_qsys_instruction_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire nios2_qsys_instruction_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> nios2_qsys_instruction_master_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_qsys_instruction_master_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_qsys_instruction_master_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_qsys_instruction_master_limiter:rsp_sink_startofpacket
wire [95:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_qsys_instruction_master_limiter:rsp_sink_data
wire [5:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_qsys_instruction_master_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // nios2_qsys_instruction_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire nios2_qsys_instruction_master_limiter_rsp_src_endofpacket; // nios2_qsys_instruction_master_limiter:rsp_src_endofpacket -> nios2_qsys_instruction_master_agent:rp_endofpacket
wire nios2_qsys_instruction_master_limiter_rsp_src_valid; // nios2_qsys_instruction_master_limiter:rsp_src_valid -> nios2_qsys_instruction_master_agent:rp_valid
wire nios2_qsys_instruction_master_limiter_rsp_src_startofpacket; // nios2_qsys_instruction_master_limiter:rsp_src_startofpacket -> nios2_qsys_instruction_master_agent:rp_startofpacket
wire [95:0] nios2_qsys_instruction_master_limiter_rsp_src_data; // nios2_qsys_instruction_master_limiter:rsp_src_data -> nios2_qsys_instruction_master_agent:rp_data
wire [5:0] nios2_qsys_instruction_master_limiter_rsp_src_channel; // nios2_qsys_instruction_master_limiter:rsp_src_channel -> nios2_qsys_instruction_master_agent:rp_channel
wire nios2_qsys_instruction_master_limiter_rsp_src_ready; // nios2_qsys_instruction_master_agent:rp_ready -> nios2_qsys_instruction_master_limiter:rsp_src_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> nios2_qsys_data_master_limiter:cmd_sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> nios2_qsys_data_master_limiter:cmd_sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> nios2_qsys_data_master_limiter:cmd_sink_startofpacket
wire [95:0] router_001_src_data; // router_001:src_data -> nios2_qsys_data_master_limiter:cmd_sink_data
wire [5:0] router_001_src_channel; // router_001:src_channel -> nios2_qsys_data_master_limiter:cmd_sink_channel
wire router_001_src_ready; // nios2_qsys_data_master_limiter:cmd_sink_ready -> router_001:src_ready
wire nios2_qsys_data_master_limiter_cmd_src_endofpacket; // nios2_qsys_data_master_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire nios2_qsys_data_master_limiter_cmd_src_startofpacket; // nios2_qsys_data_master_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire [95:0] nios2_qsys_data_master_limiter_cmd_src_data; // nios2_qsys_data_master_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire [5:0] nios2_qsys_data_master_limiter_cmd_src_channel; // nios2_qsys_data_master_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire nios2_qsys_data_master_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> nios2_qsys_data_master_limiter:cmd_src_ready
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_qsys_data_master_limiter:rsp_sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_qsys_data_master_limiter:rsp_sink_valid
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_qsys_data_master_limiter:rsp_sink_startofpacket
wire [95:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_qsys_data_master_limiter:rsp_sink_data
wire [5:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_qsys_data_master_limiter:rsp_sink_channel
wire rsp_mux_001_src_ready; // nios2_qsys_data_master_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire nios2_qsys_data_master_limiter_rsp_src_endofpacket; // nios2_qsys_data_master_limiter:rsp_src_endofpacket -> nios2_qsys_data_master_agent:rp_endofpacket
wire nios2_qsys_data_master_limiter_rsp_src_valid; // nios2_qsys_data_master_limiter:rsp_src_valid -> nios2_qsys_data_master_agent:rp_valid
wire nios2_qsys_data_master_limiter_rsp_src_startofpacket; // nios2_qsys_data_master_limiter:rsp_src_startofpacket -> nios2_qsys_data_master_agent:rp_startofpacket
wire [95:0] nios2_qsys_data_master_limiter_rsp_src_data; // nios2_qsys_data_master_limiter:rsp_src_data -> nios2_qsys_data_master_agent:rp_data
wire [5:0] nios2_qsys_data_master_limiter_rsp_src_channel; // nios2_qsys_data_master_limiter:rsp_src_channel -> nios2_qsys_data_master_agent:rp_channel
wire nios2_qsys_data_master_limiter_rsp_src_ready; // nios2_qsys_data_master_agent:rp_ready -> nios2_qsys_data_master_limiter:rsp_src_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [95:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [5:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [95:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire [5:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire [95:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire [5:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire [95:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire [5:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [95:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink0_data
wire [5:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux_001:src2_ready
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [95:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink0_data
wire [5:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux_001:src3_ready
wire cmd_demux_001_src4_endofpacket; // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_001_src4_valid; // cmd_demux_001:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_001_src4_startofpacket; // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [95:0] cmd_demux_001_src4_data; // cmd_demux_001:src4_data -> cmd_mux_004:sink0_data
wire [5:0] cmd_demux_001_src4_channel; // cmd_demux_001:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_001_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux_001:src4_ready
wire cmd_demux_001_src5_endofpacket; // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_001_src5_valid; // cmd_demux_001:src5_valid -> cmd_mux_005:sink0_valid
wire cmd_demux_001_src5_startofpacket; // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [95:0] cmd_demux_001_src5_data; // cmd_demux_001:src5_data -> cmd_mux_005:sink0_data
wire [5:0] cmd_demux_001_src5_channel; // cmd_demux_001:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_001_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux_001:src5_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [95:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [5:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire [95:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire [5:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire [95:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire [5:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire [95:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire [5:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux_001:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
wire [95:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux_001:sink2_data
wire [5:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux_001:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
wire [95:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux_001:sink3_data
wire [5:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux_001:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux_001:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux_001:sink4_startofpacket
wire [95:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux_001:sink4_data
wire [5:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux_001:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux_001:sink4_ready -> rsp_demux_004:src0_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux_001:sink5_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux_001:sink5_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux_001:sink5_startofpacket
wire [95:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux_001:sink5_data
wire [5:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux_001:sink5_channel
wire rsp_demux_005_src0_ready; // rsp_mux_001:sink5_ready -> rsp_demux_005:src0_ready
wire [5:0] nios2_qsys_instruction_master_limiter_cmd_valid_data; // nios2_qsys_instruction_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire [5:0] nios2_qsys_data_master_limiter_cmd_valid_data; // nios2_qsys_data_master_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_qsys_instruction_master_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_qsys_instruction_master_read), // .read
.av_readdata (nios2_qsys_instruction_master_readdata), // .readdata
.av_readdatavalid (nios2_qsys_instruction_master_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_qsys_data_master_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_qsys_data_master_byteenable), // .byteenable
.av_read (nios2_qsys_data_master_read), // .read
.av_readdata (nios2_qsys_data_master_readdata), // .readdata
.av_readdatavalid (nios2_qsys_data_master_readdatavalid), // .readdatavalid
.av_write (nios2_qsys_data_master_write), // .write
.av_writedata (nios2_qsys_data_master_writedata), // .writedata
.av_debugaccess (nios2_qsys_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_qsys_jtag_debug_module_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_jtag_debug_module_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_qsys_jtag_debug_module_agent_m0_burstcount), // .burstcount
.uav_read (nios2_qsys_jtag_debug_module_agent_m0_read), // .read
.uav_write (nios2_qsys_jtag_debug_module_agent_m0_write), // .write
.uav_waitrequest (nios2_qsys_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_jtag_debug_module_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_jtag_debug_module_agent_m0_readdata), // .readdata
.uav_writedata (nios2_qsys_jtag_debug_module_agent_m0_writedata), // .writedata
.uav_lock (nios2_qsys_jtag_debug_module_agent_m0_lock), // .lock
.uav_debugaccess (nios2_qsys_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_qsys_jtag_debug_module_address), // avalon_anti_slave_0.address
.av_write (nios2_qsys_jtag_debug_module_write), // .write
.av_read (nios2_qsys_jtag_debug_module_read), // .read
.av_readdata (nios2_qsys_jtag_debug_module_readdata), // .readdata
.av_writedata (nios2_qsys_jtag_debug_module_writedata), // .writedata
.av_byteenable (nios2_qsys_jtag_debug_module_byteenable), // .byteenable
.av_waitrequest (nios2_qsys_jtag_debug_module_waitrequest), // .waitrequest
.av_debugaccess (nios2_qsys_jtag_debug_module_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (16),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_s1_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_s1_write), // .write
.av_readdata (onchip_memory2_s1_readdata), // .readdata
.av_writedata (onchip_memory2_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_qsys_control_slave_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sysid_qsys_control_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_qsys_control_slave_agent_m0_burstcount), // .burstcount
.uav_read (sysid_qsys_control_slave_agent_m0_read), // .read
.uav_write (sysid_qsys_control_slave_agent_m0_write), // .write
.uav_waitrequest (sysid_qsys_control_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_qsys_control_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_qsys_control_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_qsys_control_slave_agent_m0_readdata), // .readdata
.uav_writedata (sysid_qsys_control_slave_agent_m0_writedata), // .writedata
.uav_lock (sysid_qsys_control_slave_agent_m0_lock), // .lock
.uav_debugaccess (sysid_qsys_control_slave_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_qsys_control_slave_address), // avalon_anti_slave_0.address
.av_readdata (sysid_qsys_control_slave_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_avalon_jtag_slave_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) adc_ltc2308_slave_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (adc_ltc2308_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (adc_ltc2308_slave_agent_m0_burstcount), // .burstcount
.uav_read (adc_ltc2308_slave_agent_m0_read), // .read
.uav_write (adc_ltc2308_slave_agent_m0_write), // .write
.uav_waitrequest (adc_ltc2308_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (adc_ltc2308_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (adc_ltc2308_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (adc_ltc2308_slave_agent_m0_readdata), // .readdata
.uav_writedata (adc_ltc2308_slave_agent_m0_writedata), // .writedata
.uav_lock (adc_ltc2308_slave_agent_m0_lock), // .lock
.uav_debugaccess (adc_ltc2308_slave_agent_m0_debugaccess), // .debugaccess
.av_address (adc_ltc2308_slave_address), // avalon_anti_slave_0.address
.av_write (adc_ltc2308_slave_write), // .write
.av_read (adc_ltc2308_slave_read), // .read
.av_readdata (adc_ltc2308_slave_readdata), // .readdata
.av_writedata (adc_ltc2308_slave_writedata), // .writedata
.av_chipselect (adc_ltc2308_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_s1_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_s1_agent_m0_burstcount), // .burstcount
.uav_read (sw_s1_agent_m0_read), // .read
.uav_write (sw_s1_agent_m0_write), // .write
.uav_waitrequest (sw_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_s1_agent_m0_readdata), // .readdata
.uav_writedata (sw_s1_agent_m0_writedata), // .writedata
.uav_lock (sw_s1_agent_m0_lock), // .lock
.uav_debugaccess (sw_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sw_s1_address), // avalon_anti_slave_0.address
.av_write (sw_s1_write), // .write
.av_readdata (sw_s1_readdata), // .readdata
.av_writedata (sw_s1_writedata), // .writedata
.av_chipselect (sw_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BEGIN_BURST (75),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_BURST_TYPE_H (72),
.PKT_BURST_TYPE_L (71),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_TRANS_EXCLUSIVE (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_THREAD_ID_H (83),
.PKT_THREAD_ID_L (83),
.PKT_CACHE_H (90),
.PKT_CACHE_L (87),
.PKT_DATA_SIDEBAND_H (74),
.PKT_DATA_SIDEBAND_L (74),
.PKT_QOS_H (76),
.PKT_QOS_L (76),
.PKT_ADDR_SIDEBAND_H (73),
.PKT_ADDR_SIDEBAND_L (73),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_DATA_W (96),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_instruction_master_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_instruction_master_agent_cp_ready), // .ready
.rp_valid (nios2_qsys_instruction_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_qsys_instruction_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_qsys_instruction_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_qsys_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_qsys_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_qsys_instruction_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BEGIN_BURST (75),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_BURST_TYPE_H (72),
.PKT_BURST_TYPE_L (71),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_TRANS_EXCLUSIVE (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_THREAD_ID_H (83),
.PKT_THREAD_ID_L (83),
.PKT_CACHE_H (90),
.PKT_CACHE_L (87),
.PKT_DATA_SIDEBAND_H (74),
.PKT_DATA_SIDEBAND_L (74),
.PKT_QOS_H (76),
.PKT_QOS_L (76),
.PKT_ADDR_SIDEBAND_H (73),
.PKT_ADDR_SIDEBAND_L (73),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_DATA_W (96),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_data_master_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_data_master_agent_cp_ready), // .ready
.rp_valid (nios2_qsys_data_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_qsys_data_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_qsys_data_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_qsys_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_qsys_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_qsys_data_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_jtag_debug_module_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_qsys_jtag_debug_module_agent_m0_address), // m0.address
.m0_burstcount (nios2_qsys_jtag_debug_module_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_qsys_jtag_debug_module_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_qsys_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_qsys_jtag_debug_module_agent_m0_lock), // .lock
.m0_readdata (nios2_qsys_jtag_debug_module_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_qsys_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_qsys_jtag_debug_module_agent_m0_read), // .read
.m0_waitrequest (nios2_qsys_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_qsys_jtag_debug_module_agent_m0_writedata), // .writedata
.m0_write (nios2_qsys_jtag_debug_module_agent_m0_write), // .write
.rp_endofpacket (nios2_qsys_jtag_debug_module_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_qsys_jtag_debug_module_agent_rp_ready), // .ready
.rp_valid (nios2_qsys_jtag_debug_module_agent_rp_valid), // .valid
.rp_data (nios2_qsys_jtag_debug_module_agent_rp_data), // .data
.rp_startofpacket (nios2_qsys_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_qsys_jtag_debug_module_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_qsys_jtag_debug_module_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_qsys_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_qsys_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_qsys_jtag_debug_module_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_qsys_jtag_debug_module_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_qsys_jtag_debug_module_agent_rf_source_data), // in.data
.in_valid (nios2_qsys_jtag_debug_module_agent_rf_source_valid), // .valid
.in_ready (nios2_qsys_jtag_debug_module_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_qsys_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_qsys_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) onchip_memory2_s1_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (onchip_memory2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (onchip_memory2_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (onchip_memory2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_s1_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sysid_qsys_control_slave_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sysid_qsys_control_slave_agent_m0_address), // m0.address
.m0_burstcount (sysid_qsys_control_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_qsys_control_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_qsys_control_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_qsys_control_slave_agent_m0_lock), // .lock
.m0_readdata (sysid_qsys_control_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_qsys_control_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_qsys_control_slave_agent_m0_read), // .read
.m0_waitrequest (sysid_qsys_control_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_qsys_control_slave_agent_m0_writedata), // .writedata
.m0_write (sysid_qsys_control_slave_agent_m0_write), // .write
.rp_endofpacket (sysid_qsys_control_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_qsys_control_slave_agent_rp_ready), // .ready
.rp_valid (sysid_qsys_control_slave_agent_rp_valid), // .valid
.rp_data (sysid_qsys_control_slave_agent_rp_data), // .data
.rp_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (sysid_qsys_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_qsys_control_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_qsys_control_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_qsys_control_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_qsys_control_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_qsys_control_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_qsys_control_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sysid_qsys_control_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_qsys_control_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_control_slave_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_qsys_control_slave_agent_rf_source_data), // in.data
.in_valid (sysid_qsys_control_slave_agent_rf_source_valid), // .valid
.in_ready (sysid_qsys_control_slave_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_qsys_control_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_qsys_control_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_qsys_control_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_qsys_control_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_avalon_jtag_slave_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) adc_ltc2308_slave_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (adc_ltc2308_slave_agent_m0_address), // m0.address
.m0_burstcount (adc_ltc2308_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (adc_ltc2308_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (adc_ltc2308_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (adc_ltc2308_slave_agent_m0_lock), // .lock
.m0_readdata (adc_ltc2308_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (adc_ltc2308_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (adc_ltc2308_slave_agent_m0_read), // .read
.m0_waitrequest (adc_ltc2308_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (adc_ltc2308_slave_agent_m0_writedata), // .writedata
.m0_write (adc_ltc2308_slave_agent_m0_write), // .write
.rp_endofpacket (adc_ltc2308_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (adc_ltc2308_slave_agent_rp_ready), // .ready
.rp_valid (adc_ltc2308_slave_agent_rp_valid), // .valid
.rp_data (adc_ltc2308_slave_agent_rp_data), // .data
.rp_startofpacket (adc_ltc2308_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (adc_ltc2308_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (adc_ltc2308_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (adc_ltc2308_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (adc_ltc2308_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (adc_ltc2308_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (adc_ltc2308_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (adc_ltc2308_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (adc_ltc2308_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (adc_ltc2308_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (adc_ltc2308_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (adc_ltc2308_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (adc_ltc2308_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (adc_ltc2308_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (adc_ltc2308_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (adc_ltc2308_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (adc_ltc2308_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) adc_ltc2308_slave_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (adc_ltc2308_slave_agent_rf_source_data), // in.data
.in_valid (adc_ltc2308_slave_agent_rf_source_valid), // .valid
.in_ready (adc_ltc2308_slave_agent_rf_source_ready), // .ready
.in_startofpacket (adc_ltc2308_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (adc_ltc2308_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (adc_ltc2308_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (adc_ltc2308_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (adc_ltc2308_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (adc_ltc2308_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (adc_ltc2308_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sw_s1_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_s1_agent_m0_address), // m0.address
.m0_burstcount (sw_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_s1_agent_m0_lock), // .lock
.m0_readdata (sw_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_s1_agent_m0_read), // .read
.m0_waitrequest (sw_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_s1_agent_m0_writedata), // .writedata
.m0_write (sw_s1_agent_m0_write), // .write
.rp_endofpacket (sw_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_s1_agent_rp_ready), // .ready
.rp_valid (sw_s1_agent_rp_valid), // .valid
.rp_data (sw_s1_agent_rp_data), // .data
.rp_startofpacket (sw_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (sw_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sw_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sw_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sw_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sw_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_s1_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_s1_agent_rf_source_data), // in.data
.in_valid (sw_s1_agent_rf_source_valid), // .valid
.in_ready (sw_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sw_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router router (
.sink_ready (nios2_qsys_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_qsys_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_data_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_data_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002 router_002 (
.sink_ready (nios2_qsys_jtag_debug_module_agent_rp_ready), // sink.ready
.sink_valid (nios2_qsys_jtag_debug_module_agent_rp_valid), // .valid
.sink_data (nios2_qsys_jtag_debug_module_agent_rp_data), // .data
.sink_startofpacket (nios2_qsys_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_jtag_debug_module_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002 router_003 (
.sink_ready (onchip_memory2_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_s1_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004 router_004 (
.sink_ready (sysid_qsys_control_slave_agent_rp_ready), // sink.ready
.sink_valid (sysid_qsys_control_slave_agent_rp_valid), // .valid
.sink_data (sysid_qsys_control_slave_agent_rp_data), // .data
.sink_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_qsys_control_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004 router_005 (
.sink_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004 router_006 (
.sink_ready (adc_ltc2308_slave_agent_rp_ready), // sink.ready
.sink_valid (adc_ltc2308_slave_agent_rp_valid), // .valid
.sink_data (adc_ltc2308_slave_agent_rp_data), // .data
.sink_startofpacket (adc_ltc2308_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (adc_ltc2308_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004 router_007 (
.sink_ready (sw_s1_agent_rp_ready), // sink.ready
.sink_valid (sw_s1_agent_rp_valid), // .valid
.sink_data (sw_s1_agent_rp_data), // .data
.sink_startofpacket (sw_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_s1_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (96),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) nios2_qsys_instruction_master_limiter (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_qsys_instruction_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_qsys_instruction_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_qsys_instruction_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_qsys_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_qsys_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_qsys_instruction_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_qsys_instruction_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_qsys_instruction_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_qsys_instruction_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_qsys_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_qsys_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_qsys_instruction_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (96),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) nios2_qsys_data_master_limiter (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_qsys_data_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_qsys_data_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_qsys_data_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_qsys_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_qsys_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_qsys_data_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_qsys_data_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_qsys_data_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_qsys_data_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_qsys_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_qsys_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_qsys_data_master_limiter_cmd_valid_data) // cmd_valid.data
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_demux cmd_demux (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_qsys_instruction_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_qsys_instruction_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_qsys_instruction_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_qsys_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_qsys_instruction_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_qsys_data_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_qsys_data_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_qsys_data_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_qsys_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_qsys_data_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_demux_001_src4_valid), // .valid
.src4_data (cmd_demux_001_src4_data), // .data
.src4_channel (cmd_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_demux_001_src5_valid), // .valid
.src5_data (cmd_demux_001_src5_data), // .data
.src5_channel (cmd_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_001_src5_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux cmd_mux (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src2_valid), // .valid
.sink0_channel (cmd_demux_001_src2_channel), // .channel
.sink0_data (cmd_demux_001_src2_data), // .data
.sink0_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux_002 cmd_mux_003 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src3_valid), // .valid
.sink0_channel (cmd_demux_001_src3_channel), // .channel
.sink0_data (cmd_demux_001_src3_data), // .data
.sink0_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux_002 cmd_mux_004 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src4_valid), // .valid
.sink0_channel (cmd_demux_001_src4_channel), // .channel
.sink0_data (cmd_demux_001_src4_data), // .data
.sink0_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src4_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux_002 cmd_mux_005 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src5_valid), // .valid
.sink0_channel (cmd_demux_001_src5_channel), // .channel
.sink0_data (cmd_demux_001_src5_data), // .data
.sink0_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src5_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux rsp_demux (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux_002 rsp_demux_003 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux_002 rsp_demux_004 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux_002 rsp_demux_005 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_mux rsp_mux (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
endmodule
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:gcd:1.0
// IP Revision: 1909171525
(* X_CORE_INFO = "gcd,Vivado 2018.2" *)
(* CHECK_LICENSE_TYPE = "gcd_zynq_snick_gcd_0_0,gcd,{}" *)
(* CORE_GENERATION_INFO = "gcd_zynq_snick_gcd_0_0,gcd,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=gcd,x_ipVersion=1.0,x_ipCoreRevision=1909171525,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_GCD_BUS_ADDR_WIDTH=6,C_S_AXI_GCD_BUS_DATA_WIDTH=32}" *)
(* IP_DEFINITION_SOURCE = "HLS" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module gcd_zynq_snick_gcd_0_0 (
s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_AWREADY,
s_axi_gcd_bus_WDATA,
s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID,
s_axi_gcd_bus_WREADY,
s_axi_gcd_bus_BRESP,
s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_ARADDR,
s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_RDATA,
s_axi_gcd_bus_RRESP,
s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY,
ap_clk,
ap_rst_n,
interrupt
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWADDR" *)
input wire [5 : 0] s_axi_gcd_bus_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWVALID" *)
input wire s_axi_gcd_bus_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWREADY" *)
output wire s_axi_gcd_bus_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WDATA" *)
input wire [31 : 0] s_axi_gcd_bus_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WSTRB" *)
input wire [3 : 0] s_axi_gcd_bus_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WVALID" *)
input wire s_axi_gcd_bus_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WREADY" *)
output wire s_axi_gcd_bus_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BRESP" *)
output wire [1 : 0] s_axi_gcd_bus_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BVALID" *)
output wire s_axi_gcd_bus_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BREADY" *)
input wire s_axi_gcd_bus_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARADDR" *)
input wire [5 : 0] s_axi_gcd_bus_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARVALID" *)
input wire s_axi_gcd_bus_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARREADY" *)
output wire s_axi_gcd_bus_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RDATA" *)
output wire [31 : 0] s_axi_gcd_bus_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RRESP" *)
output wire [1 : 0] s_axi_gcd_bus_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RVALID" *)
output wire s_axi_gcd_bus_RVALID;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_gcd_bus, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 49999947, I\
D_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RREADY" *)
input wire s_axi_gcd_bus_RREADY;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_gcd_bus, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN g\
cd_zynq_snick_processing_system7_0_0_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
gcd #(
.C_S_AXI_GCD_BUS_ADDR_WIDTH(6),
.C_S_AXI_GCD_BUS_DATA_WIDTH(32)
) inst (
.s_axi_gcd_bus_AWADDR(s_axi_gcd_bus_AWADDR),
.s_axi_gcd_bus_AWVALID(s_axi_gcd_bus_AWVALID),
.s_axi_gcd_bus_AWREADY(s_axi_gcd_bus_AWREADY),
.s_axi_gcd_bus_WDATA(s_axi_gcd_bus_WDATA),
.s_axi_gcd_bus_WSTRB(s_axi_gcd_bus_WSTRB),
.s_axi_gcd_bus_WVALID(s_axi_gcd_bus_WVALID),
.s_axi_gcd_bus_WREADY(s_axi_gcd_bus_WREADY),
.s_axi_gcd_bus_BRESP(s_axi_gcd_bus_BRESP),
.s_axi_gcd_bus_BVALID(s_axi_gcd_bus_BVALID),
.s_axi_gcd_bus_BREADY(s_axi_gcd_bus_BREADY),
.s_axi_gcd_bus_ARADDR(s_axi_gcd_bus_ARADDR),
.s_axi_gcd_bus_ARVALID(s_axi_gcd_bus_ARVALID),
.s_axi_gcd_bus_ARREADY(s_axi_gcd_bus_ARREADY),
.s_axi_gcd_bus_RDATA(s_axi_gcd_bus_RDATA),
.s_axi_gcd_bus_RRESP(s_axi_gcd_bus_RRESP),
.s_axi_gcd_bus_RVALID(s_axi_gcd_bus_RVALID),
.s_axi_gcd_bus_RREADY(s_axi_gcd_bus_RREADY),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:15:12 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_1_sim_netlist.v
// Design : bram_1024_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bram_1024_1,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clka,
ena,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [9:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [19:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [19:0]douta;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [19:0]NLW_U0_doutb_UNCONNECTED;
wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [19:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "10" *)
(* C_ADDRB_WIDTH = "10" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bram_1024_1.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_1.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *)
(* C_READ_DEPTH_B = "1024" *)
(* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *)
(* C_WRITE_DEPTH_B = "1024" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "20" *)
(* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[19:0]),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[19:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000001E0000001A00000016000000120000000E0000000A0000000600000002),
.INIT_01(256'h0000011E0000011A00000116000001120000010E0000010A0000010600000102),
.INIT_02(256'h0000021E0000021A00000216000002120000020E0000020A0000020600000202),
.INIT_03(256'h0000031E0000031A00000316000003120000030E0000030A0000030600000302),
.INIT_04(256'h0000041E0000041A00000416000004120000040E0000040A0000040600000402),
.INIT_05(256'h0000051E0000051A00000516000005120000050E0000050A0000050600000502),
.INIT_06(256'h0000061E0000061A00000616000006120000060E0000060A0000060600000602),
.INIT_07(256'h0000071E0000071A00000716000007120000070E0000070A0000070600000702),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,dina[19:15],1'b0,1'b0,1'b0,dina[14:10],1'b0,1'b0,1'b0,dina[9:5],1'b0,1'b0,1'b0,dina[4:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ,douta[19:15],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ,douta[14:10],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ,douta[9:5],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ,douta[4:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "10" *) (* C_ADDRB_WIDTH = "10" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bram_1024_1.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_1.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *) (* C_READ_DEPTH_B = "1024" *) (* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *) (* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "20" *) (* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *) (* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [9:0]addrb;
input [19:0]dinb;
output [19:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [9:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [19:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [19:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [9:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[19] = \<const0> ;
assign doutb[18] = \<const0> ;
assign doutb[17] = \<const0> ;
assign doutb[16] = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_PR_TB_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_PR_TB_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_dlatch_pr.v"
module top();
// Inputs are registered
reg D;
reg RESET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 D = 1'b1;
#80 RESET = 1'b1;
#100 D = 1'b0;
#120 RESET = 1'b0;
#140 RESET = 1'b1;
#160 D = 1'b1;
#180 RESET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hdll__udp_dlatch$PR dut (.D(D), .RESET(RESET), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_PR_TB_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_velocityControlHdl.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_velocityControlHdl
// Source Path: velocityControlHdl
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_velocityControlHdl
(
CLK_IN,
reset,
enb_1_2000_0,
reset_1,
command,
measured,
phase_currents_0,
phase_currents_1,
electrical_position,
param_velocity_p_gain,
param_velocity_i_gain,
param_current_p_gain,
param_current_i_gain,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2,
dq_currents_0,
dq_currents_1
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input reset_1;
input signed [17:0] command; // sfix18_En8
input signed [17:0] measured; // sfix18_En8
input signed [17:0] phase_currents_0; // sfix18_En15
input signed [17:0] phase_currents_1; // sfix18_En15
input signed [17:0] electrical_position; // sfix18_En14
input signed [17:0] param_velocity_p_gain; // sfix18_En16
input signed [17:0] param_velocity_i_gain; // sfix18_En15
input signed [17:0] param_current_p_gain; // sfix18_En10
input signed [17:0] param_current_i_gain; // sfix18_En2
output signed [19:0] phase_voltages_0; // sfix20_En12
output signed [19:0] phase_voltages_1; // sfix20_En12
output signed [19:0] phase_voltages_2; // sfix20_En12
output signed [17:0] dq_currents_0; // sfix18_En15
output signed [17:0] dq_currents_1; // sfix18_En15
wire signed [17:0] Control_Velocity_out1; // sfix18_En15
wire signed [17:0] sin_coefficient; // sfix18_En16
wire signed [17:0] cos_coefficient; // sfix18_En16
wire signed [17:0] d_current; // sfix18_En15
wire signed [17:0] q_current; // sfix18_En15
wire signed [17:0] d_voltage; // sfix18_En12
wire signed [17:0] q_voltage; // sfix18_En12
wire signed [17:0] Transform_dq_to_ABC_out1_0; // sfix18_En13
wire signed [17:0] Transform_dq_to_ABC_out1_1; // sfix18_En13
wire signed [17:0] Transform_dq_to_ABC_out1_2; // sfix18_En13
wire signed [19:0] Space_Vector_Modulation_out1_0; // sfix20_En12
wire signed [19:0] Space_Vector_Modulation_out1_1; // sfix20_En12
wire signed [19:0] Space_Vector_Modulation_out1_2; // sfix20_En12
// Velocity Control HDL
//
// Outer velocity control with inner loop current control.
// <Root>/Control_Velocity
velocityControlHdl_Control_Velocity u_Control_Velocity (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(reset_1),
.velocity_command(command), // sfix18_En8
.velocity_measured(measured), // sfix18_En8
.param_velocity_p_gain(param_velocity_p_gain), // sfix18_En16
.param_velocity_i_gain(param_velocity_i_gain), // sfix18_En15
.q_command(Control_Velocity_out1) // sfix18_En15
);
// <Root>/Sin_Cos1
velocityControlHdl_Sin_Cos1 u_Sin_Cos1 (.x(electrical_position), // sfix18_En14
.sin(sin_coefficient), // sfix18_En16
.cos(cos_coefficient) // sfix18_En16
);
// <Root>/Transform_ABC_to_dq
//
// <Root>/Mux
velocityControlHdl_Transform_ABC_to_dq u_Transform_ABC_to_dq (.phase_currents_0(phase_currents_0), // sfix18_En15
.phase_currents_1(phase_currents_1), // sfix18_En15
.sin_coefficient(sin_coefficient), // sfix18_En16
.cos_coefficient(cos_coefficient), // sfix18_En16
.d_current(d_current), // sfix18_En15
.q_current(q_current) // sfix18_En15
);
// Linear Current Controllers
//
// PID Blocks used for Control Design of Current Loop controllers.
//
// <Root>/Control_DQ_Currents
velocityControlHdl_Control_DQ_Currents u_Control_DQ_Currents (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(reset_1),
.q_current_command(Control_Velocity_out1), // sfix18_En15
.d_current_measured(d_current), // sfix18_En15
.q_current_measured(q_current), // sfix18_En15
.param_current_p_gain(param_current_p_gain), // sfix18_En10
.param_current_i_gain(param_current_i_gain), // sfix18_En2
.d_voltage(d_voltage), // sfix18_En12
.q_voltage(q_voltage) // sfix18_En12
);
// <Root>/Transform_dq_to_ABC
velocityControlHdl_Transform_dq_to_ABC u_Transform_dq_to_ABC (.d(d_voltage), // sfix18_En12
.q(q_voltage), // sfix18_En12
.sin(sin_coefficient), // sfix18_En16
.cos(cos_coefficient), // sfix18_En16
.ABC_0(Transform_dq_to_ABC_out1_0), // sfix18_En13
.ABC_1(Transform_dq_to_ABC_out1_1), // sfix18_En13
.ABC_2(Transform_dq_to_ABC_out1_2) // sfix18_En13
);
// <Root>/Space_Vector_Modulation
velocityControlHdl_Space_Vector_Modulation u_Space_Vector_Modulation (.Vabc_Raw_0(Transform_dq_to_ABC_out1_0), // sfix18_En13
.Vabc_Raw_1(Transform_dq_to_ABC_out1_1), // sfix18_En13
.Vabc_Raw_2(Transform_dq_to_ABC_out1_2), // sfix18_En13
.phase_voltages_0(Space_Vector_Modulation_out1_0), // sfix20_En12
.phase_voltages_1(Space_Vector_Modulation_out1_1), // sfix20_En12
.phase_voltages_2(Space_Vector_Modulation_out1_2) // sfix20_En12
);
assign phase_voltages_0 = Space_Vector_Modulation_out1_0;
assign phase_voltages_1 = Space_Vector_Modulation_out1_1;
assign phase_voltages_2 = Space_Vector_Modulation_out1_2;
assign dq_currents_0 = d_current;
assign dq_currents_1 = q_current;
endmodule // velocityControlHdl_velocityControlHdl
|
// Double buffering with dual-port RAM
// Uses single-port RAM to write switches to a section while reading from the same section to control LEDs,
// so each switch acts as if connected directly to the corresponding LED.
// Flip SW0 to change sections.
module top (
input clk,
input [15:0] sw,
output [15:0] led,
// not used
input rx,
output tx
);
assign tx = rx; // TODO(#658): Remove this work-around
wire [4:0] addr;
wire ram_out;
wire ram_in;
RAM_SHIFTER #(
.IO_WIDTH(16),
.ADDR_WIDTH(5)
) shifter (
.clk(clk),
.in(sw),
.out(led),
.addr(addr),
.ram_out(ram_out),
.ram_in(ram_in)
);
RAM64X1S #(
.INIT(64'h96A5_96A5_96A5_96A5)
) ram0 (
.WCLK(clk),
.A5(sw[0]),
.A4(addr[4]),
.A3(addr[3]),
.A2(addr[2]),
.A1(addr[1]),
.A0(addr[0]),
.O(ram_out),
.D(ram_in),
.WE(1'b1)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFRTP_PP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTP_PP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:29:02 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_stub.v
// Design : system_vga_sync_reset_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync_reset,Vivado 2016.4" *)
module system_vga_sync_reset_0_0(clk, rst, active, hsync, vsync, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
`include "defines.v"
//////////////////////////////////////////////////////////////////////////////////
// Company: WSIZ Copernicus
// Engineer: Darek B.
//
// Create Date: 18.05.2017 17:42:28
// Design Name:
// Module Name: wyswietlacz_4x7seg
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
/*
MULTIPLEXOWANY, CZTEROSEGMENTOWY WYWIETLACZ 7SEG Z KROPK¥
*/
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module wyswietlacz_4x7seg(
input wire clk, // zegar (nie mniej, ni¿ 250Hz)
input wire [4:0] L_1, // liczba segement 1 (6 bit = kropka)
input wire [4:0] L_2, // liczba segement 2 (6 bit = kropka)
input wire [4:0] L_3, // liczba segement 3 (6 bit = kropka)
input wire [4:0] L_4, // liczba segement 4 (6 bit = kropka)
output reg [3:0] segment_out, // wskanik wywietlanej liczby (0-wywietlany, 1-zgaszony)
output reg seg_um, // góra, rodek
output reg seg_ul, // góra, lewo
output reg seg_ur, // góra, prawo
output reg seg_mm, // rodek, rodek
output reg seg_dl, // dó³, lewo
output reg seg_dr, // dó³, prawo
output reg seg_dm, // dól, rodek
output reg seg_dot // kropka
);
function [7:0]liczbaNAsygnaly;
input [4:0]liczba;
begin
case (liczba[3:0])
default: liczbaNAsygnaly = ~8'b00000000; // nic nie wieci
4'b0000: liczbaNAsygnaly = ~{liczba[4:4],7'b1110111}; // 0
4'b0001: liczbaNAsygnaly = ~{liczba[4:4],7'b0010010}; // 1
4'b0010: liczbaNAsygnaly = ~{liczba[4:4],7'b1011101}; // 2
4'b0011: liczbaNAsygnaly = ~{liczba[4:4],7'b1011011}; // 3
4'b0100: liczbaNAsygnaly = ~{liczba[4:4],7'b0111010}; // 4
4'b0101: liczbaNAsygnaly = ~{liczba[4:4],7'b1101011}; // 5
4'b0110: liczbaNAsygnaly = ~{liczba[4:4],7'b1101111}; // 6
4'b0111: liczbaNAsygnaly = ~{liczba[4:4],7'b1010010}; // 7
4'b1000: liczbaNAsygnaly = ~{liczba[4:4],7'b1111111}; // 8
4'b1001: liczbaNAsygnaly = ~{liczba[4:4],7'b1111011}; // 9
4'b1010: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000}; // -
4'b1011: liczbaNAsygnaly = ~{liczba[4:4],7'b1000000}; // um
4'b1100: liczbaNAsygnaly = ~{liczba[4:4],7'b0010000}; // ur
4'b1101: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000}; // mm
4'b1110: liczbaNAsygnaly = ~{liczba[4:4],7'b0100000}; // ul
4'b1111: liczbaNAsygnaly = ~{liczba[4:4],7'b0000000}; // nic
endcase
end
endfunction
always @(negedge clk)
begin
case (segment_out)
default: begin segment_out <= ~4'b0001; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_1); end // inicjalizacja - pierwszy segment zapalony
4'b1110: begin segment_out <= ~4'b0010; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_2); end // z ka¿dym pe³nym cyklem zmieniamy wywietlany segment
4'b1101: begin segment_out <= ~4'b0100; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_3); end // z ka¿dym pe³nym cyklem zmieniamy wywietlany segment
4'b1011: begin segment_out <= ~4'b1000; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_4); end // z ka¿dym pe³nym cyklem zmieniamy wywietlany segment
4'b0111: begin segment_out <= ~4'b0001; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_1); end // ustawiamy wyswietlany segment na pierwszy
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2B_2_V
`define SKY130_FD_SC_HDLL__AND2B_2_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2b_2 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2b_2 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_2_V
`define SKY130_FD_SC_MS__O311A_2_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311a_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_2_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_next_state (clock, reset, enable, test_expr, curr_state, next_state, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter next_count = 1;
parameter width = 1;
parameter min_hold = 1;
parameter max_hold = 1;
parameter disallow = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1 : 0] test_expr;
input [width-1 : 0] curr_state;
input [next_count*width-1:0] next_state;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "ASSERT_NEXT_STATE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_next_state_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_next_state
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 12:15:15
// Design Name:
// Module Name: rca_to_7segment_dataflow_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rca_to_7segment_dataflow_tb(
);
reg [3:0] a;
reg [3:0] b;
reg cin;
wire z;
wire [6:0] seg;
integer i;
integer j;
rca_to_7segment_dataflow DUT (.a(a), .b(b), .cin(cin), .z(z), .seg(seg));
initial begin
a = 0; b = 0; cin = 0;
for (i = 0 ; i < 16; i = i + 1) begin
#10 a = i;
for (j = 0; j < 16; j = j + 1) begin
#10 b = j;
end
end
#10 cin = 1;
for (i = 0 ; i < 16; i = i + 1) begin
#10 a = i;
for (j = 0; j < 16; j = j + 1) begin
#10 b = j;
end
end
#20;
end
endmodule
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for fpga_core
*/
module test_fpga_core;
// Parameters
parameter TARGET = "SIM";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg btnu = 0;
reg btnl = 0;
reg btnd = 0;
reg btnr = 0;
reg btnc = 0;
reg [7:0] sw = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
reg phy_rx_clk = 0;
reg [7:0] phy_rxd = 0;
reg phy_rx_dv = 0;
reg phy_rx_er = 0;
reg phy_tx_clk = 0;
reg phy_int_n = 1;
reg uart_rxd = 1;
reg uart_cts = 1;
// Outputs
wire [7:0] led;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
wire phy_gtx_clk;
wire [7:0] phy_txd;
wire phy_tx_en;
wire phy_tx_er;
wire phy_reset_n;
wire uart_txd;
wire uart_rts;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
btnu,
btnl,
btnd,
btnr,
btnc,
sw,
i2c_scl_i,
i2c_sda_i,
phy_rx_clk,
phy_rxd,
phy_rx_dv,
phy_rx_er,
phy_tx_clk,
phy_int_n,
uart_rxd,
uart_cts
);
$to_myhdl(
led,
i2c_scl_o,
i2c_scl_t,
i2c_sda_o,
i2c_sda_t,
phy_gtx_clk,
phy_txd,
phy_tx_en,
phy_tx_er,
phy_reset_n,
uart_txd,
uart_rts
);
// dump file
$dumpfile("test_fpga_core.lxt");
$dumpvars(0, test_fpga_core);
end
fpga_core #(
.TARGET(TARGET)
)
UUT (
.clk(clk),
.rst(rst),
.btnu(btnu),
.btnl(btnl),
.btnd(btnd),
.btnr(btnr),
.btnc(btnc),
.sw(sw),
.led(led),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts)
);
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
* Copyright (C) 2007 Das Labor
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart_transceiver(
input sys_rst,
input sys_clk,
input uart_rx,
output reg uart_tx,
input [15:0] divisor,
output reg [7:0] rx_data,
output reg rx_done,
input [7:0] tx_data,
input tx_wr,
output reg tx_done
);
//-----------------------------------------------------------------
// enable16 generator
//-----------------------------------------------------------------
reg [15:0] enable16_counter;
wire enable16;
assign enable16 = (enable16_counter == 16'd0);
always @(posedge sys_clk) begin
if(sys_rst)
enable16_counter <= divisor - 16'b1;
else begin
enable16_counter <= enable16_counter - 16'd1;
if(enable16)
enable16_counter <= divisor - 16'b1;
end
end
//-----------------------------------------------------------------
// Synchronize uart_rx
//-----------------------------------------------------------------
reg uart_rx1;
reg uart_rx2;
always @(posedge sys_clk) begin
uart_rx1 <= uart_rx;
uart_rx2 <= uart_rx1;
end
//-----------------------------------------------------------------
// UART RX Logic
//-----------------------------------------------------------------
reg rx_busy;
reg [3:0] rx_count16;
reg [3:0] rx_bitcount;
reg [7:0] rx_reg;
always @(posedge sys_clk) begin
if(sys_rst) begin
rx_done <= 1'b0;
rx_busy <= 1'b0;
rx_count16 <= 4'd0;
rx_bitcount <= 4'd0;
end else begin
rx_done <= 1'b0;
if(enable16) begin
if(~rx_busy) begin // look for start bit
if(~uart_rx2) begin // start bit found
rx_busy <= 1'b1;
rx_count16 <= 4'd7;
rx_bitcount <= 4'd0;
end
end else begin
rx_count16 <= rx_count16 + 4'd1;
if(rx_count16 == 4'd0) begin // sample
rx_bitcount <= rx_bitcount + 4'd1;
if(rx_bitcount == 4'd0) begin // verify startbit
if(uart_rx2)
rx_busy <= 1'b0;
end else if(rx_bitcount == 4'd9) begin
rx_busy <= 1'b0;
if(uart_rx2) begin // stop bit ok
rx_data <= rx_reg;
rx_done <= 1'b1;
end // ignore RX error
end else
rx_reg <= {uart_rx2, rx_reg[7:1]};
end
end
end
end
end
//-----------------------------------------------------------------
// UART TX Logic
//-----------------------------------------------------------------
reg tx_busy;
reg [3:0] tx_bitcount;
reg [3:0] tx_count16;
reg [7:0] tx_reg;
always @(posedge sys_clk) begin
if(sys_rst) begin
tx_done <= 1'b0;
tx_busy <= 1'b0;
uart_tx <= 1'b1;
end else begin
tx_done <= 1'b0;
if(tx_wr) begin
tx_reg <= tx_data;
tx_bitcount <= 4'd0;
tx_count16 <= 4'd1;
tx_busy <= 1'b1;
uart_tx <= 1'b0;
`ifdef SIMULATION
$display("UART: %c", tx_data);
`endif
end else if(enable16 && tx_busy) begin
tx_count16 <= tx_count16 + 4'd1;
if(tx_count16 == 4'd0) begin
tx_bitcount <= tx_bitcount + 4'd1;
if(tx_bitcount == 4'd8) begin
uart_tx <= 1'b1;
end else if(tx_bitcount == 4'd9) begin
uart_tx <= 1'b1;
tx_busy <= 1'b0;
tx_done <= 1'b1;
end else begin
uart_tx <= tx_reg[0];
tx_reg <= {1'b0, tx_reg[7:1]};
end
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A311OI_BEHAVIORAL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire B1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_BEHAVIORAL_V |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bcam_bhv.v: Behavioral description of Binary Content Addressasble Memory (BCAM)//
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module bcam_bhv
#( parameter CAMD = 512, // CAM depth
parameter CAMW = 32 , // CAM/pattern width
parameter INOM = 1 ) // binary / Initial CAM with no match (has priority over IFILE)
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(CAMD)-1:0] wAddr , // write address
input [ CAMW -1:0] wPatt , // write pattern
input [ CAMW -1:0] mPatt , // patern to match
output reg match , // match indicator
output reg [`log2(CAMD)-1:0] mAddr ); // matched address
// assign memory array
reg [CAMW-1:0] mem [0:CAMD-1];
// valid bit
reg [CAMD-1:0] vld;
// initialize memory, with zeros if INOM or file if IFILE.
integer i;
initial
if (INOM)
for (i=0; i<CAMD; i=i+1)
{vld[i],mem[i]} = {1'b0,{CAMW{1'b0}}};
always @(posedge clk) begin
// write to memory
if (wEnb)
{vld[wAddr],mem[wAddr]} = {1'b1,wPatt};
// search memory
match = 0;
mAddr = 0;
match = (mem[mAddr]==mPatt) && vld[mAddr];
while ((!match) && (mAddr<(CAMD-1))) begin
mAddr=mAddr+1;
match = (mem[mAddr]==mPatt) && vld[mAddr];
end
end
endmodule
|
`timescale 1ns/100ps
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 11864 $
// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
module
BFMA1l1OII
(
HCLK
,
HRESETN
,
HSEL
,
HWRITE
,
HADDR
,
HWDATA
,
HRDATA
,
HREADYIN
,
HREADYOUT
,
HTRANS
,
HSIZE
,
HBURST
,
HMASTLOCK
,
HPROT
,
HRESP
,
PSEL
,
PADDR
,
PWRITE
,
PENABLE
,
PWDATA
,
PRDATA
,
PREADY
,
PSLVERR
)
;
parameter
TPD
=
1
;
input
HCLK
;
input
HRESETN
;
input
HSEL
;
input
HWRITE
;
input
[
31
:
0
]
HADDR
;
input
[
31
:
0
]
HWDATA
;
output
[
31
:
0
]
HRDATA
;
wire
[
31
:
0
]
HRDATA
;
input
HREADYIN
;
output
HREADYOUT
;
wire
HREADYOUT
;
input
[
1
:
0
]
HTRANS
;
input
[
2
:
0
]
HSIZE
;
input
[
2
:
0
]
HBURST
;
input
HMASTLOCK
;
input
[
3
:
0
]
HPROT
;
output
HRESP
;
wire
HRESP
;
output
[
15
:
0
]
PSEL
;
wire
[
15
:
0
]
PSEL
;
output
[
31
:
0
]
PADDR
;
wire
[
31
:
0
]
PADDR
;
output
PWRITE
;
wire
PWRITE
;
output
PENABLE
;
wire
PENABLE
;
output
[
31
:
0
]
PWDATA
;
wire
[
31
:
0
]
PWDATA
;
input
[
31
:
0
]
PRDATA
;
input
PREADY
;
input
PSLVERR
;
parameter
[
1
:
0
]
BFMA1OOIII
=
0
;
parameter
[
1
:
0
]
BFMA1IOIII
=
1
;
parameter
[
1
:
0
]
BFMA1lOIII
=
2
;
parameter
[
1
:
0
]
BFMA1OIIII
=
3
;
reg
[
1
:
0
]
BFMA1IIIII
;
reg
BFMA1lIIII
;
reg
BFMA1OlIII
;
reg
[
15
:
0
]
BFMA1IlIII
;
reg
[
31
:
0
]
BFMA1llIII
;
reg
BFMA1O0III
;
reg
BFMA1I0III
;
reg
[
31
:
0
]
BFMA1l0III
;
wire
[
31
:
0
]
BFMA1O1III
;
reg
BFMA1I1III
;
reg
BFMA1l1III
;
always
@
(
posedge
HCLK
or
negedge
HRESETN
)
begin
if
(
HRESETN
==
1
'b
0
)
begin
BFMA1IIIII
<=
BFMA1OOIII
;
BFMA1lIIII
<=
1
'b
1
;
BFMA1llIII
<=
{
32
{
1
'b
0
}
}
;
BFMA1l0III
<=
{
32
{
1
'b
0
}
}
;
BFMA1O0III
<=
1
'b
0
;
BFMA1I0III
<=
1
'b
0
;
BFMA1OlIII
<=
1
'b
0
;
BFMA1I1III
<=
1
'b
0
;
BFMA1l1III
<=
1
'b
0
;
end
else
begin
BFMA1OlIII
<=
1
'b
0
;
BFMA1lIIII
<=
1
'b
0
;
BFMA1I1III
<=
1
'b
0
;
case
(
BFMA1IIIII
)
BFMA1OOIII
:
begin
if
(
HSEL
==
1
'b
1
&
HREADYIN
==
1
'b
1
&
(
HTRANS
[
1
]
)
==
1
'b
1
)
begin
BFMA1IIIII
<=
BFMA1IOIII
;
BFMA1llIII
<=
HADDR
;
BFMA1O0III
<=
HWRITE
;
BFMA1l0III
<=
HWDATA
;
BFMA1I0III
<=
1
'b
0
;
BFMA1I1III
<=
HWRITE
;
BFMA1l1III
<=
1
'b
1
;
end
else
begin
BFMA1lIIII
<=
1
'b
1
;
end
end
BFMA1IOIII
:
begin
BFMA1I0III
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1lOIII
;
end
BFMA1lOIII
:
begin
if
(
PREADY
==
1
'b
1
)
begin
BFMA1I0III
<=
1
'b
0
;
BFMA1l1III
<=
1
'b
0
;
if
(
PSLVERR
==
1
'b
0
)
begin
BFMA1IIIII
<=
BFMA1OOIII
;
if
(
HSEL
==
1
'b
1
&
HREADYIN
==
1
'b
1
&
(
HTRANS
[
1
]
)
==
1
'b
1
)
begin
BFMA1IIIII
<=
BFMA1IOIII
;
BFMA1llIII
<=
HADDR
;
BFMA1O0III
<=
HWRITE
;
BFMA1I1III
<=
HWRITE
;
BFMA1l1III
<=
1
'b
1
;
end
end
else
begin
BFMA1OlIII
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1OIIII
;
end
end
end
BFMA1OIIII
:
begin
BFMA1OlIII
<=
1
'b
1
;
BFMA1lIIII
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1OOIII
;
end
endcase
if
(
BFMA1I1III
==
1
'b
1
)
begin
BFMA1l0III
<=
HWDATA
;
end
end
end
always
@
(
BFMA1llIII
or
BFMA1l1III
)
begin
BFMA1IlIII
<=
{
16
{
1
'b
0
}
}
;
if
(
BFMA1l1III
==
1
'b
1
)
begin
begin
:
BFMA1IO10
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
15
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1IlIII
[
BFMA1I0I0
]
<=
(
BFMA1llIII
[
27
:
24
]
==
BFMA1I0I0
)
;
end
end
end
end
assign
BFMA1O1III
=
(
BFMA1I1III
==
1
'b
1
)
?
HWDATA
:
BFMA1l0III
;
assign
#
TPD
HRDATA
=
PRDATA
;
assign
#
TPD
HREADYOUT
=
BFMA1lIIII
|
(
PREADY
&
BFMA1l1III
&
BFMA1I0III
&
~
PSLVERR
)
;
assign
#
TPD
HRESP
=
BFMA1OlIII
;
assign
#
TPD
PSEL
=
BFMA1IlIII
;
assign
#
TPD
PADDR
=
BFMA1llIII
;
assign
#
TPD
PWRITE
=
BFMA1O0III
;
assign
#
TPD
PENABLE
=
BFMA1I0III
;
assign
#
TPD
PWDATA
=
BFMA1O1III
;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A22O_BEHAVIORAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFINV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__BUFINV_BEHAVIORAL_PP_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFINV_BEHAVIORAL_PP_V |
// part of NeoGS project (c) 2007-2008 NedoPC
//
// interrupt controller for Z80
module timer(
input wire clk_24mhz,
input wire clk_z80,
input wire [2:0] rate, // z80 clocked
// 3'b000 -- 37500/1
// 3'b001 -- 37500/2
// 3'b010 -- 37500/4
// 3'b011 -- 37500/8
// 3'b100 -- 37500/16
// 3'b101 -- 37500/64
// 3'b110 -- 37500/256
// 3'b111 -- 37500/1024
output reg int_stb
);
reg [ 2:0] ctr5;
reg [16:0] ctr128k;
reg ctrsel;
reg int_sync1,int_sync2,int_sync3;
always @(posedge clk_24mhz)
begin
if( !ctr5[2] )
ctr5 <= ctr5 + 3'd1;
else
ctr5 <= 3'd0;
end
//
initial
ctr128k = 'd0;
always @(posedge clk_24mhz)
begin
if( ctr5[2] )
ctr128k <= ctr128k + 17'd1;
end
always @*
case( rate )
3'b000: ctrsel = ctr128k[6];
3'b001: ctrsel = ctr128k[7];
3'b010: ctrsel = ctr128k[8];
3'b011: ctrsel = ctr128k[9];
3'b100: ctrsel = ctr128k[10];
3'b101: ctrsel = ctr128k[12];
3'b110: ctrsel = ctr128k[14];
3'b111: ctrsel = ctr128k[16];
endcase
// generate interrupt signal in clk_z80 domain
always @(posedge clk_z80)
begin
int_sync3 <= int_sync2;
int_sync2 <= int_sync1;
int_sync1 <= ctrsel;
end
always @(posedge clk_z80)
if( !int_sync2 && int_sync3 )
int_stb <= 1'b1;
else
int_stb <= 1'b0;
endmodule
|
// RFID Reader for testing epc class 1 gen 2 tags.
// rigidly assume clock = 7.812mhz. (this makes our divide ratios work out nicely)
// for an 8mhz crystal, we are off by about 2%
`timescale 1ns/1ns
module rfid_reader_packet_rxtx (
// basic setup connections
reset, clk, tag_backscatter, reader_modulation,
// modulation settings
miller, trext, divide_ratio, tari_ns, trcal_ns,
// tag state settings
slot_q, q_adj, session, target, select,
// command to send, posedge send trigger
send_packet_type, start_tx, reader_done, rx_timeout, rx_packet_complete, reader_running,
// tx payload info
tx_handle,
// rx payload info
rx_handle
);
input reset, clk, tag_backscatter;
output reader_modulation;
input [2:0] miller;
input trext;
input divide_ratio;
input [15:0] tari_ns;
input [15:0] trcal_ns;
input [2:0] q_adj;
input [3:0] slot_q;
input [1:0] session;
input [1:0] select;
input target;
input [3:0] send_packet_type;
input start_tx;
output reader_done, rx_timeout, rx_packet_complete, reader_running;
input [15:0] tx_handle;
output [15:0] rx_handle;
// Packets (valid tx_cmd values)
parameter QUERYREP = 0;
parameter ACK = 1;
parameter QUERY = 2;
parameter QUERYADJ = 3;
parameter SELECT = 4;
parameter NACK = 5;
parameter REQRN = 6;
parameter READ = 7;
parameter WRITE = 8;
parameter KILL = 9;
parameter LOCK = 10;
parameter ACCESS = 11;
parameter BLOCKWRITE = 12;
parameter BLOCKERASE = 13;
// divide time periods by 128 ns via shift right 7 to get clock cycles
parameter CLK_EXP = 7;
wire [15:0] delim_counts;
wire [15:0] pw_counts;
wire [15:0] tari_counts;
wire [15:0] rtcal_counts;
wire [15:0] trcal_counts;
assign delim_counts = 16'd15000 >> CLK_EXP;
assign pw_counts = 16'd1000 >> CLK_EXP;
assign tari_counts = (tari_ns >> CLK_EXP) - pw_counts;
assign rtcal_counts = (tari_ns >> (CLK_EXP-1)) + tari_counts - pw_counts;
assign trcal_counts = (trcal_ns >> CLK_EXP) - pw_counts;
wire rx_done, tx_done, tx_reader_running, send_trcal;
reg rx_reset, tx_go;
reg reader_done;
wire tag_found, rx_timeout;
reg [6:0] tx_packet_length;
reg [127:0] tx_packet_data;
wire [1023:0] rx_data;
wire [9:0] rx_dataidx;
wire rx_packet_complete;
assign rx_packet_complete = ((send_packet_type == QUERYREP && rx_dataidx >= 16 ) || // QueryRep
(send_packet_type == ACK && rx_dataidx >= 112) || // Ack
(send_packet_type == QUERY && rx_dataidx >= 16 ) || // Query
(send_packet_type == QUERYADJ && rx_dataidx >= 16 ) || // QueryAdj
(send_packet_type == SELECT && rx_dataidx >= 0 ) || // Select
(send_packet_type == NACK && rx_dataidx >= 0 ) || // Nack
(send_packet_type == REQRN && rx_dataidx >= 32 ) || // ReqRN
(send_packet_type == READ && rx_dataidx >= 49 ) || // Read
(send_packet_type == WRITE && rx_dataidx >= 33 )); // Write
assign send_trcal = (send_packet_type == QUERY);
rfid_reader_tx U_TX (
// basic signals
reset, clk, reader_modulation,
// control signals
tx_done, tx_reader_running, tx_go, send_trcal,
// timing information
delim_counts, pw_counts, rtcal_counts, trcal_counts, tari_counts,
// payload information
tx_packet_length, tx_packet_data
);
rfid_reader_rx U_RX (
// basic signals
rx_reset, clk, tag_backscatter,
// logistics
rx_done, rx_timeout,
// modulation infomation
miller, trext, divide_ratio,
// timing information
rtcal_counts, trcal_counts, tari_counts,
// received data
rx_data, rx_dataidx
);
// All the things we can receive from tags
// and their endian-correct outputs
reg [15:0] handlein;
wire [15:0] rx_handle;
endianflip16 U_FLIP_HANDLE(handlein, rx_handle);
reg [5:0] reader_state;
parameter STATE_IDLE = 0;
parameter STATE_TX = 1;
parameter STATE_RX = 2;
reg [15:0] count;
assign reader_running = (reader_state != STATE_IDLE) && (!reader_done);
always @ (posedge clk or posedge reset) begin
if (reset) begin
reader_state <= 0;
rx_reset <= 0;
reader_done <= 0;
count <= 0;
handlein <= 0;
end else begin
case(reader_state)
STATE_IDLE: begin
rx_reset <= 1;
if(start_tx) begin
reader_state <= STATE_TX;
reader_done <= 0;
end
end
STATE_TX: begin
rx_reset <= 1;
if(tx_done) begin
tx_go <= 0;
reader_state <= STATE_RX;
end else if(!tx_reader_running) begin
tx_go <= 1;
end else begin
end
end
STATE_RX: begin
rx_reset <= 0;
if (rx_packet_complete) begin // packet complete
if (send_packet_type == REQRN) begin
handlein <= rx_data[15:0];
end
if (send_packet_type == QUERY || send_packet_type == QUERYREP || send_packet_type == QUERYADJ) begin
handlein <= rx_data[15:0];
end
end
if (rx_timeout) begin
reader_done <= 1;
end
if (start_tx) begin
reader_state <= STATE_IDLE; // reset
$display(" ");
end
end
default: begin
reader_state <= 0;
end
endcase
end
end
always @ (send_packet_type) begin
// Construct packet:
case(send_packet_type)
QUERYREP: begin
$display("Sending QueryRep...");
tx_packet_length <= 4;
tx_packet_data[127:4] <= 0;
tx_packet_data[3:2] <= 2'b 00;
tx_packet_data[1:0] <= session;
end
ACK: begin
$display("Sending Ack...");
tx_packet_length <= 18;
tx_packet_data[127:18] <= 0;
tx_packet_data[17:16] <= 2'b01;
tx_packet_data[15:0] <= tx_handle;
end
QUERY: begin
$display("Sending Query...");
tx_packet_length <= 22;
tx_packet_data[127:22] <= 0;
tx_packet_data[21:18] <= 4'b 1000;
tx_packet_data[17:5] <= {divide_ratio,miller,trext,select,session,target,slot_q};
tx_packet_data[4:0] <= 5'd0; // todo: crc
end
QUERYADJ: begin
$display("Sending Query Adj...");
tx_packet_length <= 9;
tx_packet_data[127:9] <= 0;
tx_packet_data[8:5] <= 4'b 1001; // cmd
tx_packet_data[4:3] <= session;
tx_packet_data[2:0] <= q_adj; // Q up/down
end
SELECT: begin
$display("Sending Select...");
tx_packet_length <= 45;
tx_packet_data[127:45] <= 0;
tx_packet_data[44:41] <= 4'b 1010;
tx_packet_data[40:30] <= 11'b 10101010111; // TODO
tx_packet_data[29:0] <= 0;
end
NACK: begin
$display("Sending Nack...");
tx_packet_length <= 8;
tx_packet_data[127:8] <= 0;
tx_packet_data[7:0] <= 8'b 11000000;
end
REQRN: begin
$display("Sending Req_rn...");
tx_packet_length <= 40;
tx_packet_data[127:40] <= 0;
tx_packet_data[39:32] <= 8'b11000001;
tx_packet_data[31:16] <= tx_handle;
tx_packet_data[15:0] <= 15'd0; // todo: crc
end
READ: begin
$display("Sending Read...");
tx_packet_length <= 58;
tx_packet_data[127:58] <= 0;
tx_packet_data[57:50] <= 8'b 11000010;
tx_packet_data[49:48] <= 2'b 11; // bank
tx_packet_data[47:40] <= 8'd0; // ebv ptr
tx_packet_data[39:32] <= 8'd1; // word count
tx_packet_data[31:16] <= tx_handle;
tx_packet_data[15:0] <= 15'd0; // todo: crc
end
WRITE: begin
$display("Sending Write...");
tx_packet_length <= 59;
tx_packet_data[127:58] <= 0;
tx_packet_data[58:51] <= 8'b 11000011;
tx_packet_data[50:40] <= 11'b 10101010111;
tx_packet_data[39:0] <= 0;
end
KILL: begin
$display("Sending Kill...");
tx_packet_length <= 59;
tx_packet_data[127:59] <= 0;
tx_packet_data[58:51] <= 8'b 11000100;
tx_packet_data[50:40] <= 11'b 10101010111;
tx_packet_data[39:0] <= 0;
end
LOCK: begin
$display("Sending Lock...");
tx_packet_length <= 60;
tx_packet_data[127:60] <= 0;
tx_packet_data[59:52] <= 8'b 11000101;
tx_packet_data[51:41] <= 11'b 10101010111;
tx_packet_data[40:0] <= 0;
end
ACCESS: begin
$display("Sending Access...");
tx_packet_length <= 56;
tx_packet_data[127:56] <= 0;
tx_packet_data[55:48] <= 8'b 11000110;
tx_packet_data[47:37] <= 11'b 10101010111;
tx_packet_data[36:0] <= 0;
end
BLOCKWRITE: begin
$display("Sending Block Write...");
tx_packet_length <= 59;
tx_packet_data[127:59] <= 0;
tx_packet_data[58:51] <= 8'b 11000110;
tx_packet_data[50:40] <= 11'b 10101010111;
tx_packet_data[39:0] <= 0;
end
BLOCKERASE: begin
$display("Sending Block Erase...");
tx_packet_length <= 59;
tx_packet_data[127:59] <= 0;
tx_packet_data[58:51] <= 8'b 11000100;
tx_packet_data[50:40] <= 11'b 10101010111;
tx_packet_data[39:0] <= 0;
end
default: begin
tx_packet_length <= 0;
tx_packet_data[127:0] <= 0;
end
endcase // case(mode)
end
endmodule
// The rx gets bits msb first
// but stores them reverse endian
// which minimizes the overhead in the rx
// module. Unfortunately, we have to flip
// the results afterwards.
module endianflip16(flipin, flipout);
input [15:0] flipin;
output [15:0] flipout;
assign flipout[15] = flipin[0];
assign flipout[14] = flipin[1];
assign flipout[13] = flipin[2];
assign flipout[12] = flipin[3];
assign flipout[11] = flipin[4];
assign flipout[10] = flipin[5];
assign flipout[9] = flipin[6];
assign flipout[8] = flipin[7];
assign flipout[7] = flipin[8];
assign flipout[6] = flipin[9];
assign flipout[5] = flipin[10];
assign flipout[4] = flipin[11];
assign flipout[3] = flipin[12];
assign flipout[2] = flipin[13];
assign flipout[1] = flipin[14];
assign flipout[0] = flipin[15];
endmodule
|
// MBT 8-28-14
//
// sequence through all of the tests.
//
// for each test, assert a prepare line for prepare_time_p cycles
// then wait for either 1) all channels to pass that test
// or 2) one channel passes and things have stabilized
// for timeout_time_p cycles
//
//
`include "bsg_defines.v"
module bsg_source_sync_channel_control_master_master
#(parameter `BSG_INV_PARAM( link_channels_p )
, parameter `BSG_INV_PARAM(tests_p )
, parameter `BSG_INV_PARAM(prepare_cycles_p )
, parameter `BSG_INV_PARAM(timeout_cycles_p ))
(input clk_i
, input reset_i
, input start_i
, input [tests_p+1-1:0][link_channels_p-1:0] test_scoreboard_i
, output [$clog2(tests_p+1)-1:0] test_index_r_o
, output prepare_o
, output done_o
);
logic [$clog2(tests_p+1)-1:0] test_index_n, test_index_r;
logic [tests_p+1-1:0][link_channels_p-1:0] test_scoreboard_r;
wire prep_done, timeout_wait_done;
logic prep_actiwait;
assign test_index_r_o = test_index_r;
assign prepare_o = ~prep_done;
logic done_r, done_n;
assign done_o = done_r;
wire final_test = (test_index_r == tests_p);
bsg_wait_cycles #(.cycles_p(prepare_cycles_p)) bwc
(.clk_i (clk_i)
,.reset_i (reset_i)
,.activate_i (prep_actiwait)
,.ready_r_o (prep_done)
);
// reactivate the timeout if the channels that pass change
// this timeout is not really for handling intermittant operation
// but more to deal with slight amounts of skew between channel
// wakeup times.
//
// note: this means that we could potentially loop indefinitely
// if things are intermittant; i.e. a channel oscillates between
// going active and being inactive.
//
// fixme: this is okay for FPGA (we can fix the code after the fact)
// but not for ASIC.
//
bsg_wait_cycles #(.cycles_p(timeout_cycles_p)) bwc2
(.clk_i (clk_i)
,.reset_i (reset_i)
,.activate_i(test_scoreboard_i[test_index_r] != test_scoreboard_r[test_index_r])
,.ready_r_o( timeout_wait_done)
);
always_ff @(posedge clk_i)
begin
if (reset_i)
test_index_r <= { ($clog2(tests_p+1)) { 1'b0 } };
else
test_index_r <= test_index_n;
if (reset_i)
test_scoreboard_r <= { link_channels_p*(tests_p+1) { 1'b0 } };
else
test_scoreboard_r <= test_scoreboard_i;
if (reset_i)
done_r <= 1'b0;
else
done_r <= done_n;
end
always_comb
begin
done_n = done_r;
test_index_n = test_index_r;
prep_actiwait = 0;
if (start_i)
begin
done_n = 1'b0;
test_index_n = 0;
prep_actiwait = 1'b1;
end
else
if (prep_done & ~done_r) // if we're done preparing for the tests,
begin // or haven't finished them all...
if ( (& test_scoreboard_r[test_index_r]) // all chanls passed the test
| ( (| test_scoreboard_r[test_index_r]) // or if at least one has
& timeout_wait_done // and we have timed out
)
)
begin
if (final_test)
done_n = 1'b1;
else
begin
// if we've already passed all tests
// then go directly to the last test.
// "temporary fix" for accelerating simulation 5/1/17 mbt
if (&test_scoreboard_r[tests_p-1:0])
test_index_n = tests_p;
else
test_index_n = test_index_r + 1'b1;
prep_actiwait = 1'b1;
end
end
end
end // always_comb
endmodule
`BSG_ABSTRACT_MODULE(bsg_source_sync_channel_control_master_master)
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_tlfragmenter_qspi_1(
input clock,
input reset,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [1:0] io_in_0_a_bits_source,
input [29:0] io_in_0_a_bits_address,
input io_in_0_a_bits_mask,
input [7:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [1:0] io_in_0_b_bits_source,
output [29:0] io_in_0_b_bits_address,
output io_in_0_b_bits_mask,
output [7:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [1:0] io_in_0_c_bits_source,
input [29:0] io_in_0_c_bits_address,
input [7:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [1:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output io_in_0_d_bits_addr_lo,
output [7:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
input io_out_0_a_ready,
output io_out_0_a_valid,
output [2:0] io_out_0_a_bits_opcode,
output [2:0] io_out_0_a_bits_param,
output [2:0] io_out_0_a_bits_size,
output [6:0] io_out_0_a_bits_source,
output [29:0] io_out_0_a_bits_address,
output io_out_0_a_bits_mask,
output [7:0] io_out_0_a_bits_data,
output io_out_0_b_ready,
input io_out_0_b_valid,
input [2:0] io_out_0_b_bits_opcode,
input [1:0] io_out_0_b_bits_param,
input [2:0] io_out_0_b_bits_size,
input [6:0] io_out_0_b_bits_source,
input [29:0] io_out_0_b_bits_address,
input io_out_0_b_bits_mask,
input [7:0] io_out_0_b_bits_data,
input io_out_0_c_ready,
output io_out_0_c_valid,
output [2:0] io_out_0_c_bits_opcode,
output [2:0] io_out_0_c_bits_param,
output [2:0] io_out_0_c_bits_size,
output [6:0] io_out_0_c_bits_source,
output [29:0] io_out_0_c_bits_address,
output [7:0] io_out_0_c_bits_data,
output io_out_0_c_bits_error,
output io_out_0_d_ready,
input io_out_0_d_valid,
input [2:0] io_out_0_d_bits_opcode,
input [1:0] io_out_0_d_bits_param,
input [2:0] io_out_0_d_bits_size,
input [6:0] io_out_0_d_bits_source,
input io_out_0_d_bits_sink,
input io_out_0_d_bits_addr_lo,
input [7:0] io_out_0_d_bits_data,
input io_out_0_d_bits_error,
input io_out_0_e_ready,
output io_out_0_e_valid,
output io_out_0_e_bits_sink
);
reg [4:0] acknum;
reg [31:0] GEN_25;
reg [2:0] dOrig;
reg [31:0] GEN_26;
wire [4:0] dFragnum;
wire dFirst;
wire [7:0] T_1410;
wire T_1411;
wire dsizeOH1;
wire T_1414;
wire [4:0] GEN_5;
wire [4:0] T_1415;
wire T_1417;
wire T_1418;
wire T_1419;
wire T_1421;
wire [4:0] dFirst_acknum;
wire [5:0] GEN_8;
wire [5:0] T_1428;
wire [5:0] T_1430;
wire [5:0] T_1432;
wire [5:0] T_1433;
wire [5:0] T_1434;
wire [1:0] T_1435;
wire [3:0] T_1436;
wire T_1438;
wire [3:0] GEN_9;
wire [3:0] T_1439;
wire [1:0] T_1440;
wire [1:0] T_1441;
wire T_1443;
wire [1:0] T_1444;
wire T_1445;
wire [1:0] T_1446;
wire [2:0] dFirst_size;
wire T_1447;
wire [5:0] T_1448;
wire [4:0] T_1449;
wire [4:0] T_1450;
wire [2:0] GEN_0;
wire [4:0] GEN_1;
wire [2:0] GEN_2;
wire T_1459;
wire T_1460;
wire [1:0] T_1461;
reg r_error;
reg [31:0] GEN_27;
wire d_error;
wire GEN_3;
wire repeater_clock;
wire repeater_reset;
wire repeater_io_repeat;
wire repeater_io_full;
wire repeater_io_enq_ready;
wire repeater_io_enq_valid;
wire [2:0] repeater_io_enq_bits_opcode;
wire [2:0] repeater_io_enq_bits_param;
wire [2:0] repeater_io_enq_bits_size;
wire [1:0] repeater_io_enq_bits_source;
wire [29:0] repeater_io_enq_bits_address;
wire repeater_io_enq_bits_mask;
wire [7:0] repeater_io_enq_bits_data;
wire repeater_io_deq_ready;
wire repeater_io_deq_valid;
wire [2:0] repeater_io_deq_bits_opcode;
wire [2:0] repeater_io_deq_bits_param;
wire [2:0] repeater_io_deq_bits_size;
wire [1:0] repeater_io_deq_bits_source;
wire [29:0] repeater_io_deq_bits_address;
wire repeater_io_deq_bits_mask;
wire [7:0] repeater_io_deq_bits_data;
wire find_0;
wire T_1494;
wire [2:0] aFrag;
wire [11:0] T_1497;
wire [4:0] T_1498;
wire [4:0] aOrigOH1;
wire [7:0] T_1501;
wire T_1502;
wire aFragOH1;
reg [4:0] gennum;
reg [31:0] GEN_28;
wire aFirst;
wire [5:0] T_1511;
wire [4:0] T_1512;
wire [4:0] old_gennum1;
wire [4:0] T_1513;
wire [4:0] GEN_10;
wire [4:0] T_1515;
wire [4:0] new_gennum;
wire T_1520;
wire [4:0] GEN_4;
wire T_1524;
wire [4:0] T_1526;
wire [4:0] T_1528;
wire [29:0] GEN_12;
wire [29:0] T_1529;
wire [6:0] T_1530;
wire T_1532;
wire T_1541;
wire T_1542;
wire T_1543;
wire T_1545;
wire T_1546;
wire [2:0] GEN_6 = 3'b0;
reg [31:0] GEN_29;
wire [1:0] GEN_7 = 2'b0;
reg [31:0] GEN_30;
wire [2:0] GEN_11 = 3'b0;
reg [31:0] GEN_31;
wire [1:0] GEN_13 = 2'b0;
reg [31:0] GEN_32;
wire [29:0] GEN_14 = 30'b0;
reg [31:0] GEN_33;
wire GEN_15 = 1'b0;
reg [31:0] GEN_34;
wire [7:0] GEN_16 = 8'b0;
reg [31:0] GEN_35;
wire [2:0] GEN_17 = 3'b0;
reg [31:0] GEN_36;
wire [2:0] GEN_18 = 3'b0;
reg [31:0] GEN_37;
wire [2:0] GEN_19 = 3'b0;
reg [31:0] GEN_38;
wire [6:0] GEN_20 = 7'b0;
reg [31:0] GEN_39;
wire [29:0] GEN_21 = 30'b0;
reg [31:0] GEN_40;
wire [7:0] GEN_22 = 8'b0;
reg [31:0] GEN_41;
wire GEN_23 = 1'b0;
reg [31:0] GEN_42;
wire GEN_24 = 1'b0;
reg [31:0] GEN_43;
sirv_repeater_6 u_repeater (
.clock(repeater_clock),
.reset(repeater_reset),
.io_repeat(repeater_io_repeat),
.io_full(repeater_io_full),
.io_enq_ready(repeater_io_enq_ready),
.io_enq_valid(repeater_io_enq_valid),
.io_enq_bits_opcode(repeater_io_enq_bits_opcode),
.io_enq_bits_param(repeater_io_enq_bits_param),
.io_enq_bits_size(repeater_io_enq_bits_size),
.io_enq_bits_source(repeater_io_enq_bits_source),
.io_enq_bits_address(repeater_io_enq_bits_address),
.io_enq_bits_mask(repeater_io_enq_bits_mask),
.io_enq_bits_data(repeater_io_enq_bits_data),
.io_deq_ready(repeater_io_deq_ready),
.io_deq_valid(repeater_io_deq_valid),
.io_deq_bits_opcode(repeater_io_deq_bits_opcode),
.io_deq_bits_param(repeater_io_deq_bits_param),
.io_deq_bits_size(repeater_io_deq_bits_size),
.io_deq_bits_source(repeater_io_deq_bits_source),
.io_deq_bits_address(repeater_io_deq_bits_address),
.io_deq_bits_mask(repeater_io_deq_bits_mask),
.io_deq_bits_data(repeater_io_deq_bits_data)
);
assign io_in_0_a_ready = repeater_io_enq_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_6;
assign io_in_0_b_bits_param = GEN_7;
assign io_in_0_b_bits_size = GEN_11;
assign io_in_0_b_bits_source = GEN_13;
assign io_in_0_b_bits_address = GEN_14;
assign io_in_0_b_bits_mask = GEN_15;
assign io_in_0_b_bits_data = GEN_16;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = io_out_0_d_valid;
assign io_in_0_d_bits_opcode = io_out_0_d_bits_opcode;
assign io_in_0_d_bits_param = io_out_0_d_bits_param;
assign io_in_0_d_bits_size = GEN_0;
assign io_in_0_d_bits_source = T_1461;
assign io_in_0_d_bits_sink = io_out_0_d_bits_sink;
assign io_in_0_d_bits_addr_lo = T_1460;
assign io_in_0_d_bits_data = io_out_0_d_bits_data;
assign io_in_0_d_bits_error = d_error;
assign io_in_0_e_ready = 1'h1;
assign io_out_0_a_valid = repeater_io_deq_valid;
assign io_out_0_a_bits_opcode = repeater_io_deq_bits_opcode;
assign io_out_0_a_bits_param = repeater_io_deq_bits_param;
assign io_out_0_a_bits_size = aFrag;
assign io_out_0_a_bits_source = T_1530;
assign io_out_0_a_bits_address = T_1529;
assign io_out_0_a_bits_mask = T_1546;
assign io_out_0_a_bits_data = io_in_0_a_bits_data;
assign io_out_0_b_ready = 1'h1;
assign io_out_0_c_valid = 1'h0;
assign io_out_0_c_bits_opcode = GEN_17;
assign io_out_0_c_bits_param = GEN_18;
assign io_out_0_c_bits_size = GEN_19;
assign io_out_0_c_bits_source = GEN_20;
assign io_out_0_c_bits_address = GEN_21;
assign io_out_0_c_bits_data = GEN_22;
assign io_out_0_c_bits_error = GEN_23;
assign io_out_0_d_ready = io_in_0_d_ready;
assign io_out_0_e_valid = 1'h0;
assign io_out_0_e_bits_sink = GEN_24;
assign dFragnum = io_out_0_d_bits_source[4:0];
assign dFirst = acknum == 5'h0;
assign T_1410 = 8'h1 << io_out_0_d_bits_size;
assign T_1411 = T_1410[0];
assign dsizeOH1 = ~ T_1411;
assign T_1414 = io_out_0_d_valid == 1'h0;
assign GEN_5 = {{4'd0}, dsizeOH1};
assign T_1415 = dFragnum & GEN_5;
assign T_1417 = T_1415 == 5'h0;
assign T_1418 = T_1414 | T_1417;
assign T_1419 = T_1418 | reset;
assign T_1421 = T_1419 == 1'h0;
assign dFirst_acknum = dFragnum | GEN_5;
assign GEN_8 = {{1'd0}, dFirst_acknum};
assign T_1428 = GEN_8 << 1;
assign T_1430 = T_1428 | 6'h1;
assign T_1432 = {1'h0,dFirst_acknum};
assign T_1433 = ~ T_1432;
assign T_1434 = T_1430 & T_1433;
assign T_1435 = T_1434[5:4];
assign T_1436 = T_1434[3:0];
assign T_1438 = T_1435 != 2'h0;
assign GEN_9 = {{2'd0}, T_1435};
assign T_1439 = GEN_9 | T_1436;
assign T_1440 = T_1439[3:2];
assign T_1441 = T_1439[1:0];
assign T_1443 = T_1440 != 2'h0;
assign T_1444 = T_1440 | T_1441;
assign T_1445 = T_1444[1];
assign T_1446 = {T_1443,T_1445};
assign dFirst_size = {T_1438,T_1446};
assign T_1447 = io_out_0_d_ready & io_out_0_d_valid;
assign T_1448 = acknum - 5'h1;
assign T_1449 = T_1448[4:0];
assign T_1450 = dFirst ? dFirst_acknum : T_1449;
assign GEN_0 = dFirst ? dFirst_size : dOrig;
assign GEN_1 = T_1447 ? T_1450 : acknum;
assign GEN_2 = T_1447 ? GEN_0 : dOrig;
assign T_1459 = ~ dsizeOH1;
assign T_1460 = io_out_0_d_bits_addr_lo & T_1459;
assign T_1461 = io_out_0_d_bits_source[6:5];
assign d_error = r_error | io_out_0_d_bits_error;
assign GEN_3 = T_1447 ? 1'h0 : r_error;
assign repeater_clock = clock;
assign repeater_reset = reset;
assign repeater_io_repeat = T_1524;
assign repeater_io_enq_valid = io_in_0_a_valid;
assign repeater_io_enq_bits_opcode = io_in_0_a_bits_opcode;
assign repeater_io_enq_bits_param = io_in_0_a_bits_param;
assign repeater_io_enq_bits_size = io_in_0_a_bits_size;
assign repeater_io_enq_bits_source = io_in_0_a_bits_source;
assign repeater_io_enq_bits_address = io_in_0_a_bits_address;
assign repeater_io_enq_bits_mask = io_in_0_a_bits_mask;
assign repeater_io_enq_bits_data = io_in_0_a_bits_data;
assign repeater_io_deq_ready = io_out_0_a_ready;
assign find_0 = 1'h1;
assign T_1494 = repeater_io_deq_bits_size > 3'h0;
assign aFrag = T_1494 ? 3'h0 : repeater_io_deq_bits_size;
assign T_1497 = 12'h1f << repeater_io_deq_bits_size;
assign T_1498 = T_1497[4:0];
assign aOrigOH1 = ~ T_1498;
assign T_1501 = 8'h1 << aFrag;
assign T_1502 = T_1501[0];
assign aFragOH1 = ~ T_1502;
assign aFirst = gennum == 5'h0;
assign T_1511 = gennum - 5'h1;
assign T_1512 = T_1511[4:0];
assign old_gennum1 = aFirst ? aOrigOH1 : T_1512;
assign T_1513 = ~ old_gennum1;
assign GEN_10 = {{4'd0}, aFragOH1};
assign T_1515 = T_1513 | GEN_10;
assign new_gennum = ~ T_1515;
assign T_1520 = io_out_0_a_ready & io_out_0_a_valid;
assign GEN_4 = T_1520 ? new_gennum : gennum;
assign T_1524 = new_gennum != 5'h0;
assign T_1526 = ~ new_gennum;
assign T_1528 = T_1526 & aOrigOH1;
assign GEN_12 = {{25'd0}, T_1528};
assign T_1529 = repeater_io_deq_bits_address | GEN_12;
assign T_1530 = {repeater_io_deq_bits_source,new_gennum};
assign T_1532 = repeater_io_full == 1'h0;
assign T_1541 = repeater_io_deq_bits_mask;
assign T_1542 = T_1532 | T_1541;
assign T_1543 = T_1542 | reset;
assign T_1545 = T_1543 == 1'h0;
assign T_1546 = repeater_io_full ? 1'h1 : io_in_0_a_bits_mask;
always @(posedge clock or posedge reset)
if (reset) begin
acknum <= 5'h0;
end else begin
if (T_1447) begin
if (dFirst) begin
acknum <= dFirst_acknum;
end else begin
acknum <= T_1449;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
dOrig <= 3'b0;
end
else begin
if (T_1447) begin
if (dFirst) begin
dOrig <= dFirst_size;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
r_error <= 1'h0;
end else begin
if (T_1447) begin
r_error <= 1'h0;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
gennum <= 5'h0;
end else begin
if (T_1520) begin
gennum <= new_gennum;
end
end
// `ifndef SYNTHESIS
// `ifdef PRINTF_COND
// if (`PRINTF_COND) begin
// `endif
// if (T_1421) begin
// $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:149 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n");
// end
// `ifdef PRINTF_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef STOP_COND
// if (`STOP_COND) begin
// `endif
// if (T_1421) begin
// $fatal;
// end
// `ifdef STOP_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef PRINTF_COND
// if (`PRINTF_COND) begin
// `endif
// if (1'h0) begin
// $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:237 assert (!repeater.io.full || !aHasData)\n");
// end
// `ifdef PRINTF_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef STOP_COND
// if (`STOP_COND) begin
// `endif
// if (1'h0) begin
// $fatal;
// end
// `ifdef STOP_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef PRINTF_COND
// if (`PRINTF_COND) begin
// `endif
// if (T_1545) begin
// $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:240 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n");
// end
// `ifdef PRINTF_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef STOP_COND
// if (`STOP_COND) begin
// `endif
// if (T_1545) begin
// $fatal;
// end
// `ifdef STOP_COND
// end
// `endif
// `endif
//synopsys translate_off
always @(posedge clock or posedge reset) begin
if (T_1421) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:149 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n");
end
if (T_1545) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:240 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n");
end
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:237 assert (!repeater.io.full || !aHasData)\n");
end
end
//synopsys translate_on
endmodule
|
## Skeleton config file for RetroArch
# Save all save files (*.srm) to this directory. This includes related files like .bsv, .rtc, .psrm, etc ...
# This will be overridden by explicit command line options.
# savefile_directory =
# Save all save states (*.state) to this directory.
# This will be overridden by explicit command line options.
# savestate_directory =
# If set to a directory, Content which is temporarily extracted
# will be extracted to this directory.
cache_directory = "/tmp/retroarch"
# Save all input remapping files to this directory.
# input_remapping_directory =
# Save all playlist files to this directory.
# playlist_directory =
# If set to a directory, the content history playlist will be saved
# to this directory.
# content_history_dir =
# Automatically saves a savestate at the end of RetroArch's lifetime.
# The path is $SRAM_PATH.auto.
# RetroArch will automatically load any savestate with this path on startup if savestate_auto_load is set.
# savestate_auto_save = false
# savestate_auto_load = true
# Load libretro from a dynamic location for dynamically built RetroArch.
# This option is mandatory.
# Path to a libretro implementation.
# libretro_path = "/path/to/libretro.so"
# A directory for where to search for libretro core implementations.
# libretro_directory =
# A directory for where to search for libretro core information.
# libretro_info_path =
# Sets log level for libretro cores (GET_LOG_INTERFACE).
# If a log level issued by a libretro core is below libretro_log_level, it is ignored.
# DEBUG logs are always ignored unless verbose mode is activated (--verbose).
# DEBUG = 0, INFO = 1, WARN = 2, ERROR = 3.
# libretro_log_level = 0
# Enable or disable verbosity level of frontend.
# log_verbosity = false
# If this option is enabled, every content file loaded in RetroArch will be
# automatically added to a history list.
# history_list_enable = true
# Enable or disable RetroArch performance counters
# perfcnt_enable = false
# Path to core options config file.
# This config file is used to expose core-specific options.
# It will be written to by RetroArch.
# A default path will be assigned if not set.
core_options_path = "/opt/retropie/configs/all/retroarch-core-options.cfg"
# Path to content load history file.
# RetroArch keeps track of all content loaded in the menu and from CLI directly for convenient quick loading.
# A default path will be assigned if not set.
# content_history_path =
# Number of entries that will be kept in content history file.
# content_history_size = 100
# Sets the "system" directory.
# Implementations can query for this directory to load BIOSes, system-specific configs, etc.
system_directory = "/home/pi/RetroPie/BIOS"
# Sets start directory for menu content browser.
# rgui_browser_directory =
# Content directory. Interacts with RETRO_ENVIRONMENT_GET_CONTENT_DIRECTORY.
# Usually set by developers who bundle libretro/RetroArch apps to point to assets.
# content_directory =
# Assets directory. This location is queried by default when menu interfaces try to look for
# loadable assets, etc.
assets_directory = "/opt/retropie/emulators/retroarch/assets"
# Dynamic wallpapers directory. The place to store the wallpapers dynamically
# loaded by the menu depending on context.
# dynamic_wallpapers_directory =
# Thumbnails directory. To store thumbnail PNG files.
# thumbnails_directory =
# Sets start directory for menu config browser.
# rgui_config_directory =
# Show startup screen in menu.
# Is automatically set to false when seen for the first time.
# This is only updated in config if config_save_on_exit is set to true, however.
# rgui_show_start_screen = true
# Flushes config to disk on exit. Useful for menu as settings can be modified.
# Overwrites the config. #include's and comments are not preserved.
config_save_on_exit = "false"
# Load up a specific config file based on the core being used.
# core_specific_config = false
#### Video
# Video driver to use. "gl", "xvideo", "sdl"
# video_driver = "gl"
# Which OpenGL context implementation to use.
# Possible ones for desktop are: glx, x-egl, kms-egl, sdl-gl, wgl.
# By default, tries to use first suitable driver.
# video_context_driver =
# Windowed x resolution scale and y resolution scale
# (Real x res: base_size * xscale * aspect_ratio, real y res: base_size * yscale)
# video_scale = 3.0
# Fullscreen resolution. Resolution of 0 uses the resolution of the desktop.
# video_fullscreen_x = ""
# video_fullscreen_y = 0
# Start in fullscreen. Can be changed at runtime.
# video_fullscreen = false
# If fullscreen, prefer using a windowed fullscreen mode.
# video_windowed_fullscreen = true
# Which monitor to prefer. 0 (default) means no particular monitor is preferred, 1 and up (1 being first monitor),
# suggests RetroArch to use that particular monitor.
# video_monitor_index = 0
# Forcibly disable composition. Only works in Windows Vista/7 for now.
# video_disable_composition = false
# Video vsync.
# video_vsync = true
# Video swapchain images.
# video_max_swapchain_images = 3
# Forcibly disable sRGB FBO support. Some Intel OpenGL drivers on Windows
# have video problems with sRGB FBO support enabled.
# video_force_srgb_disable = false
# Attempts to hard-synchronize CPU and GPU. Can reduce latency at cost of performance.
# video_hard_sync = false
# Sets how many frames CPU can run ahead of GPU when using video_hard_sync.
# Maximum is 3.
# video_hard_sync_frames = 0
# Sets how many milliseconds to delay after VSync before running the core.
# Can reduce latency at cost of higher risk of stuttering.
# Maximum is 15.
# video_frame_delay = 0
# Inserts a black frame inbetween frames.
# Useful for 120 Hz monitors who want to play 60 Hz material with eliminated ghosting.
# video_refresh_rate should still be configured as if it is a 60 Hz monitor (divide refresh rate by 2).
# video_black_frame_insertion = false
# Use threaded video driver. Using this might improve performance at possible cost of latency and more video stuttering.
video_threaded = "true"
# Use a shared context for HW rendered libretro cores.
# Avoids having to assume HW state changes inbetween frames.
# video_shared_context = false
# Smoothens picture with bilinear filtering. Should be disabled if using pixel shaders.
video_smooth = "false"
# Forces rendering area to stay equal to content aspect ratio or as defined in video_aspect_ratio.
# video_force_aspect = ""
# Only scales video in integer steps.
# The base size depends on system-reported geometry and aspect ratio.
# If video_force_aspect is not set, X/Y will be integer scaled independently.
# video_scale_integer = false
# A floating point value for video aspect ratio (width / height).
# If this is not set, aspect ratio is assumed to be automatic.
# Behavior then is defined by video_aspect_ratio_auto.
video_aspect_ratio = "1.25"
# If this is true and video_aspect_ratio is not set,
# aspect ratio is decided by libretro implementation.
# If this is false, 1:1 PAR will always be assumed if video_aspect_ratio is not set.
video_aspect_ratio_auto = "false"
# Forces cropping of overscanned frames.
# Exact behavior of this option is implementation specific.
# video_crop_overscan = true
# Path to shader. Shader can be either Cg, CGP (Cg preset) or GLSL, GLSLP (GLSL preset)
# video_shader = "/path/to/shader.{cg,cgp,glsl,glslp}"
# Load video_shader on startup.
# Other shaders can still be loaded later in runtime.
# video_shader_enable = false
# Defines a directory where shaders (Cg, CGP, GLSL) are kept for easy access.
video_shader_dir = "/opt/retropie/emulators/retroarch/shader/"
# CPU-based video filter. Path to a dynamic library.
# video_filter =
# Defines a directory where CPU-based video filters are kept.
# video_filter_dir =
# Path to a font used for rendering messages. This path must be defined to enable fonts.
# Do note that the _full_ path of the font is necessary!
# video_font_path =
# Size of the font rendered.
video_font_size = "12"
# Enable usage of OSD messages.
# video_font_enable = true
# Offset for where messages will be placed on screen. Values are in range 0.0 to 1.0 for both x and y values.
# [0.0, 0.0] maps to the lower left corner of the screen.
# video_message_pos_x = 0.05
# video_message_pos_y = 0.05
# Color for message. The value is treated as a hexadecimal value.
# It is a regular RGB hex number, i.e. red is "ff0000".
# video_message_color = ffffff
# Video refresh rate of your monitor.
# Used to calculate a suitable audio input rate.
# video_refresh_rate = 59.95
# Allows libretro cores to set rotation modes.
# Setting this to false will honor, but ignore this request.
# This is useful for vertically oriented content where one manually rotates the monitor.
# video_allow_rotate = true
# Forces a certain rotation of the screen.
# The rotation is added to rotations which the libretro core sets (see video_allow_rotate).
# The angle is <value> * 90 degrees counter-clockwise.
video_rotation = "3"
#### Audio
# Enable audio.
# audio_enable = true
# Mutes audio.
# audio_mute_enable = false
# Audio output samplerate.
# audio_out_rate = 48000
# Audio resampler backend. Which audio resampler to use.
# Default will use "sinc".
# audio_resampler =
# Audio driver backend. Depending on configuration possible candidates are: alsa, pulse, oss, jack, rsound, roar, openal, sdl, xaudio.
# audio_driver =
# Override the default audio device the audio_driver uses. This is driver dependant. E.g. ALSA wants a PCM device, OSS wants a path (e.g. /dev/dsp), Jack wants portnames (e.g. system:playback1,system:playback_2), and so on ...
# audio_device =
# Audio DSP plugin that processes audio before it's sent to the driver. Path to a dynamic library.
# audio_dsp_plugin =
# Directory where DSP plugins are kept.
# audio_filter_dir =
# Will sync (block) on audio. Recommended.
# audio_sync = true
# Desired audio latency in milliseconds. Might not be honored if driver can't provide given latency.
# audio_latency = 64
# Enable audio rate control.
# audio_rate_control = true
# Controls audio rate control delta. Defines how much input rate can be adjusted dynamically.
# Input rate = in_rate * (1.0 +/- audio_rate_control_delta)
# audio_rate_control_delta = 0.005
# Controls maximum audio timing skew. Defines the maximum change in input rate.
# Input rate = in_rate * (1.0 +/- max_timing_skew)
# audio_max_timing_skew = 0.05
# Audio volume. Volume is expressed in dB.
# 0 dB is normal volume. No gain will be applied.
# Gain can be controlled in runtime with input_volume_up/input_volume_down.
# audio_volume = 0.0
#### Overlay
# Defines a directory where overlays are kept for easy access.
overlay_directory = "/opt/retropie/emulators/retroarch/overlays"
# Enable or disable the current overlay.
# input_overlay_enable = true
# Hide the current overlay from appearing in menu screens.
# input_overlay_hide_in_menu = true
# Path to input overlay
# input_overlay =
# Overlay opacity
# input_overlay_opacity = 1.0
# Overlay scale
# input_overlay_scale = 1.0
#### OSK (Onscreen Keyboard) Overlay
# Defines a directory where overlays are kept for easy access.
# osk_overlay_directory =
# Enable OSK overlay.
# input_osk_overlay_enable = true
# Path to OSK overlay
# input_osk_overlay =
# OSK Overlay opacity
# input_osk_overlay_opacity = 1.0
# OSK Overlay scale
# input_osk_overlay_scale = 1.0
#### Input
# Input driver. Depending on video driver, it might force a different input driver.
# input_driver = sdl
# Input device driver. (Valid: linuxraw, sdl, dinput)
input_joypad_driver = "udev"
# Path to input remapping file.
# input_remapping_path =
# Input bind timer timeout.
# Amount of seconds to wait until proceeding to the next bind. Default: 5, minimum: 1
# input_bind_timeout = 1
# If enabled, overrides the input binds with the remapped binds set for the current core.
# input_remap_binds_enable = true
# Maximum amount of users supported by RetroArch.
# input_max_users = 16
# Keyboard layout for input driver if applicable (udev/evdev for now).
# Syntax is either just layout (e.g. "no"), or a layout and variant separated with colon ("no:nodeadkeys").
# input_keyboard_layout =
# Defines axis threshold. Possible values are [0.0, 1.0]
# input_axis_threshold = 0.5
# Enable input auto-detection. Will attempt to autoconfigure
# joypads, Plug-and-Play style.
input_autodetect_enable = "true"
# Show the input descriptors set by the core instead of the
# default ones.
# input_descriptor_label_show = true
# Hide input descriptors that were not set by the core.
# input_descriptor_hide_unbound = false
# Influence how input polling is done inside RetroArch.
# 0 : Early - Input polling is performed before call to retro_run.
# 1 : Normal - Input polling is performend when retro_input_poll is
# requested.
# 2 : Late - Input polling is performed on first call to retro_input_state
# per frame
#
# Setting it to 0 or 2 can result in less latency depending on
# your configuration.
#
# When netplay is enabled, the default polling behavior (1) will
# be used regardless of the value set here.
# input_poll_type_behavior = 1
# Directory for joypad autoconfigs.
# If a joypad is plugged in, that joypad will be autoconfigured if a config file
# corresponding to that joypad is present in joypad_autoconfig_dir.
# Input binds which are made explicit (input_playerN_*_btn/axis) will take priority over autoconfigs.
# Autoconfigs can be created with retroarch-joyconfig, manually, or with a frontend.
# Requires input_autodetect_enable to be enabled.
joypad_autoconfig_dir = "/opt/retropie/configs/all/retroarch-joypads/"
# Sets which libretro device is used for a user.
# Devices are indentified with a number.
# This is normally saved by the menu.
# Device IDs are found in libretro.h.
# These settings are overridden by explicit command-line arguments which refer to input devices.
# None: 0
# Joypad (RetroPad): 1
# Mouse: 2
# Keyboard: 3
# Generic Lightgun: 4
# Joypad w/ Analog (RetroPad + Analog sticks): 5
# Multitap (SNES specific): 257
# Super Scope (SNES specific): 260
# Justifier (SNES specific): 516
# Justifiers (SNES specific): 772
# input_libretro_device_p1 =
# input_libretro_device_p2 =
# input_libretro_device_p3 =
# input_libretro_device_p4 =
# input_libretro_device_p5 =
# input_libretro_device_p6 =
# input_libretro_device_p7 =
# input_libretro_device_p8 =
# Keyboard input. Will recognize letters ("a" to "z") and the following special keys (where "kp_"
# is for keypad keys):
#
# left, right, up, down, enter, kp_enter, tab, insert, del, end, home,
# rshift, shift, ctrl, alt, space, escape, add, subtract, kp_plus, kp_minus,
# f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12,
# num0, num1, num2, num3, num4, num5, num6, num7, num8, num9, pageup, pagedown,
# keypad0, keypad1, keypad2, keypad3, keypad4, keypad5, keypad6, keypad7, keypad8, keypad9,
# period, capslock, numlock, backspace, multiply, divide, print_screen, scroll_lock,
# tilde, backquote, pause, quote, comma, minus, slash, semicolon, equals, leftbracket,
# backslash, rightbracket, kp_period, kp_equals, rctrl, ralt
#
# Keyboard input, Joypad and Joyaxis will all obey the "nul" bind, which disables the bind completely,
# rather than relying on a default.
input_player1_a = "a"
input_player1_b = "b"
input_player1_y = "y"
input_player1_x = "x"
input_player1_start = "backquote"
input_player1_select = "tab"
input_player1_l = "l"
input_player1_r = "r"
input_player1_left = "left"
input_player1_right = "right"
input_player1_up = "up"
input_player1_down = "down"
# input_player1_l2 =
# input_player1_r2 =
# input_player1_l3 =
input_player1_r3 = "enter"
# Two analog sticks (DualShock-esque).
# Bound as usual, however, if a real analog axis is bound,
# it can be read as a true analog.
# Positive X axis is right, Positive Y axis is down.
# input_player1_l_x_plus =
# input_player1_l_x_minus =
# input_player1_l_y_plus =
# input_player1_l_y_minus =
# input_player1_r_x_plus =
# input_player1_r_x_minus =
# input_player1_r_y_plus =
# input_player1_r_y_minus =
# If desired, it is possible to override which joypads are being used for user 1 through 8.
# First joypad available is 0.
# input_player1_joypad_index = 0
# input_player2_joypad_index = 1
# input_player3_joypad_index = 2
# input_player4_joypad_index = 3
# input_player5_joypad_index = 4
# input_player6_joypad_index = 5
# input_player7_joypad_index = 6
# input_player8_joypad_index = 7
# Input device buttons.
# Figure these out by using RetroArch-Phoenix or retroarch-joyconfig.
# You can use joypad hats with hnxx, where n is the hat, and xx is a string representing direction.
# E.g. "h0up"
# input_player1_a_btn =
# input_player1_b_btn =
# input_player1_y_btn =
# input_player1_x_btn =
# input_player1_start_btn =
# input_player1_select_btn =
# input_player1_l_btn =
# input_player1_r_btn =
# input_player1_left_btn =
# input_player1_right_btn =
# input_player1_up_btn =
# input_player1_down_btn =
# input_player1_l2_btn =
# input_player1_r2_btn =
# input_player1_l3_btn =
# input_player1_r3_btn =
# Menu buttons.
# menu_ok_btn =
# menu_cancel_btn =
# menu_search_btn =
# menu_info_btn =
# menu_default_btn =
# menu_scroll_down_btn =
# menu_scroll_up_btn =
# Axis for RetroArch D-Pad.
# Needs to be either '+' or '-' in the first character signaling either positive or negative direction of the axis, then the axis number.
# Do note that every other input option has the corresponding _btn and _axis binds as well; they are omitted here for clarity.
# input_player1_left_axis =
# input_player1_right_axis =
# input_player1_up_axis =
# input_player1_down_axis =
# Holding the turbo while pressing another button will let the button enter a turbo mode
# where the button state is modulated with a periodic signal.
# The modulation stops when the button itself (not turbo button) is released.
# input_player1_turbo =
# Describes the period and how long of that period a turbo-enabled button should behave.
# Numbers are described in frames.
# input_turbo_period = 6
# input_turbo_duty_cycle = 3
# This goes all the way to user 8 (*_player2_*, *_player3_*, etc), but omitted for clarity.
# All input binds have corresponding binds for keyboard (none), joykeys (_btn) and joyaxes (_axis) as well.
# Toggles fullscreen.
# input_toggle_fullscreen = f
# Saves state.
# input_save_state = f2
# Loads state.
# input_load_state = f4
# State slots. With slot set to 0, save state name is *.state (or whatever defined on commandline).
# When slot is != 0, path will be $path%d, where %d is slot number.
input_state_slot_increase = "right"
input_state_slot_decrease = "left"
# Toggles between fast-forwarding and normal speed.
# input_toggle_fast_forward = space
# Hold for fast-forward. Releasing button disables fast-forward.
# input_hold_fast_forward = l
# Key to exit RetroArch cleanly.
# Killing it in any hard way (SIGKILL, etc) will terminate RetroArch without saving RAM, etc.
# On Unix-likes, SIGINT/SIGTERM allows a clean deinitialization.
input_exit_emulator = "backquote"
# Applies next and previous shader in directory.
input_shader_next = "m"
input_shader_prev = "n"
# Hold button down to rewind. Rewinding must be enabled.
input_rewind = "r"
# Toggle between recording and not.
# input_movie_record_toggle = o
# Toggle between paused and non-paused state
# input_pause_toggle = p
# Frame advance when content is paused
# input_frame_advance = k
# Reset the content.
input_reset = "b"
# Cheats.
# input_cheat_index_plus = y
# input_cheat_index_minus = t
# input_cheat_toggle = u
# Mute/unmute audio
# input_audio_mute = f9
# Take screenshot
# input_screenshot = f8
# Netplay flip users.
# input_netplay_flip_players = i
# Hold for slowmotion.
# input_slowmotion = e
# Enable other hotkeys.
# If this hotkey is bound to either keyboard, joybutton or joyaxis,
# all other hotkeys will be disabled unless this hotkey is also held at the same time.
# This is useful for RETRO_KEYBOARD centric implementations
# which query a large area of the keyboard, where it is not desirable
# that hotkeys get in the way.
# Alternatively, all hotkeys for keyboard could be disabled by the user.
# input_enable_hotkey_btn =
# Increases audio volume.
# input_volume_up = kp_plus
# Decreases audio volume.
# input_volume_down = kp_minus
# Toggles to next overlay. Wraps around.
# input_overlay_next =
# Toggles eject for disks. Used for multiple-disk content.
# input_disk_eject_toggle =
# Cycles through disk images. Use after ejecting.
# Complete by toggling eject again.
# input_disk_next =
# Toggles menu.
input_menu_toggle = "x"
# RetroPad button combination to toggle menu
# 0 = none, 1 = L + R + Y + D-Pad Down, 2 = L3 + R3, 3 = Start + Select
# input_menu_toggle_gamepad_combo = 0
# Toggles mouse grab. When mouse is grabbed, RetroArch hides the mouse,
# and keeps the mouse pointer inside the window to allow relative mouse input
# to work better.
# input_grab_mouse_toggle = f11
#### Menu
# Menu driver to use. "rgui", "lakka", etc.
# menu_driver = "rgui"
# If enabled, the libretro core will keep running in the background when we
# are in the menu.
# menu_pause_libretro = false
# Enable mouse input inside the menu.
# menu_mouse_enable = false
# Enable touch input inside the menu.
# menu_pointer_enable = false
# Shows current date and/or time inside menu.
# menu_timedate_enable = true
# Shows current core inside menu.
# menu_core_enable = true
# Path to a .png image to set as menu wallpaper.
# menu_wallpaper =
# Dynamically load a new wallpaper depending on context.
# menu_dynamic_wallpaper_enable = false
# Type of thumbnail to display. 0 = none, 1 = snaps, 2 = titles, 3 = boxarts
# menu_thumbnails = 0
# Wrap-around toe beginning and/or end if boundary of list reached horizontally
# menu_navigation_wraparound_horizontal_enable = false
# Wrap-around to beginning and/or end if boundary of list reached vertically
# menu_navigation_wraparound_vertical_enable = false
# Filter files being show in 'Load Content' by supported extensions
# menu_navigation_browser_filter_supported_extensions_enable = true
# Collapse subgroup settings into main group to create one big listing of settings
# per category.
# menu_collapse_subgroups_enable = false
#### UI
# Suspends the screensaver if set to true. Is a hint that does not necessarily have to be honored
# by video driver.
# suspend_screensaver_enable = true
# Start UI companion driver's interface on boot (if available).
# ui_companion_start_on_boot = true
#### Camera
# Override the default camera device the camera driver uses. This is driver dependant.
# camera_device =
# Override the default privacy permission for cores that want to access camera services. Is "false" by default.
# camera_allow = false
#### Location
# Override the default privacy permission for cores that want to access location services. Is "false" by default.
# location_allow = false
#### Core Updater
# URL to core update directory on buildbot.
# core_updater_buildbot_url = "http://buildbot.libretro.com"
# URL to assets update directory on buildbot.
# core_updater_buildbot_assets_url = "http://buildbot.libretro.com/assets/"
# Automatically extract archives that the cores are contained in to the libretro cores directory.
# core_updater_auto_extract_archive = true
#### Network
# When being client over netplay, use keybinds for user 1.
# netplay_client_swap_input = false
# The username of the person running RetroArch. This will be used for playing online, for instance.
# netplay_nickname =
# The amount of delay frames to use for netplay. Increasing this value will increase
# performance, but introduce more latency.
# netplay_delay_frames = 0
# Netplay mode for the current user.
# false is Server, true is Client.
# netplay_mode = false
# Enable or disable spectator mode for the user during netplay.
# netplay_spectator_mode_enable = false
# The IP Address of the host to connect to.
# netplay_ip_address =
# The port of the host IP Address. Can be either a TCP or an UDP port.
# netplay_ip_port = 55435
#### Misc
# Enable rewinding. This will take a performance hit when playing, so it is disabled by default.
rewind_enable = "false"
# Rewinding buffer size in megabytes. Bigger rewinding buffer means you can rewind longer.
# The buffer should be approx. 20MB per minute of buffer time.
rewind_buffer_size = "10"
# Rewind granularity. When rewinding defined number of frames, you can rewind several frames at a time, increasing the rewinding speed.
rewind_granularity = "2"
# Pause gameplay when window focus is lost.
# pause_nonactive = true
# Autosaves the non-volatile SRAM at a regular interval. This is disabled by default unless set otherwise.
# The interval is measured in seconds. A value of 0 disables autosave.
# autosave_interval =
# Path to content database directory.
# content_database_path =
# Path to cheat database directory.
# cheat_database_path =
# Path to XML cheat config, a file which keeps track of which
# cheat settings are used for individual games.
# If the file does not exist, it will be created.
# cheat_settings_path =
# Directory to dump screenshots to.
# screenshot_directory =
# Records video after CPU video filter.
# video_post_filter_record = false
# Records output of GPU shaded material if available.
# video_gpu_record = false
# Screenshots output of GPU shaded material if available.
video_gpu_screenshot = "true"
# Block SRAM from being overwritten when loading save states.
# Might potentially lead to buggy games.
# block_sram_overwrite = false
# When saving a savestate, save state index is automatically increased before
# it is saved.
# Also, when loading content, the index will be set to the highest existing index.
# There is no upper bound on the index.
# savestate_auto_index = false
# Slowmotion ratio. When slowmotion, content will slow down by factor.
# slowmotion_ratio = 3.0
# The maximum rate at which content will be run when using fast forward. (E.g. 5.0 for 60 fps content => 300 fps cap).
# RetroArch will go to sleep to ensure that the maximum rate will not be exceeded.
# Do not rely on this cap to be perfectly accurate.
# If this is set at 0, then fastforward ratio is unlimited (no FPS cap)
# fastforward_ratio = 0.0
# Enable stdin/network command interface.
# network_cmd_enable = false
# network_cmd_port = 55355
# stdin_cmd_enable = false
input_enable_hotkey = "tab"
auto_remaps_enable = "true"
# aspect_ratio_index = ""
# game_specific_options = ""
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A41O_PP_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41O_PP_BLACKBOX_V
|
module scratch_pad_gold_tb;
`include "log2.vh"
`define PORTS 16
`define WIDTH 64
`define DEPTH `PORTS*512
`define ADDR_WIDTH log2(`DEPTH-1)
reg rst, clk;
reg [0:`PORTS-1] rd_en, wr_en;
reg [`PORTS*`WIDTH-1:0] d;
wire [`PORTS*`WIDTH-1:0] q;
reg [`PORTS*`ADDR_WIDTH-1:0] addr;
reg [0:`PORTS-1] stall;
wire [0:`PORTS - 1] valid, full;
scratch_pad_gold #(`PORTS, `WIDTH) dut(rst, clk, rd_en, wr_en, d, q, addr, stall, valid, full);
initial begin
clk = 0;
forever #5 clk = !clk;
end
initial begin
$monitor(valid[0]);
rst = 1;
rd_en = 0;
wr_en = 0;
d = 0;
addr = 0;
stall = 0;
#101 rst = 0;
#100 wr_en[0] = 1;
d[`PORTS*`WIDTH-1 -: `WIDTH] = 42;
#10 wr_en = 0;
#100 rd_en[0] = 1;
#10 rd_en = 0;
#100 $finish;
end
initial #10000 $finish;
integer i;
always @(posedge clk) begin
for(i = 0; i < 8; i = i + 1)
if(valid[i])
$display("read output: %d", q[`PORTS*`WIDTH-1 -: `WIDTH ]);
for(i = 0; i < 8; i = i + 1) begin
if(rd_en[i] || wr_en[i])
$display("using address: %d", addr[`PORTS*`ADDR_WIDTH-1 -: `ADDR_WIDTH ]);
if(wr_en[i])
$display("writing: %d", d[`PORTS*`WIDTH - 1 -: `WIDTH]);
end
end
always @(posedge clk) begin
end
endmodule
|
/*******************************************************************************
*
* NetFPGA-10G http://www.netfpga.org
*
* File:
* packet_counter.v
*
* Library:
* hw/osnt/pcores/osnt_10g_interface_v1_11_a
*
* Module:
* packet_generator
*
* Author:
* Antonis Gavaletakis
*
*
* Copyright (C) 2015 - HPCN-UAM High Performance Computing and Networking
*
* Licence:
* This file is part of the HPCN-NetFPGA 10G development base package.
*
* This file is free code: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 2.0 as
* published by the Free Software Foundation.
*
* This package is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with the NetFPGA source package. If not, see
* http://www.gnu.org/licenses/.
*
*/
module packet_counter
#(
// TIMESTAMP_WIDTH
parameter TIMESTAMP_WIDTH = 64,
//Master AXI Stream Data Width
parameter C_M_AXIS_DATA_WIDTH=256,
parameter C_S_AXIS_DATA_WIDTH=256,
parameter C_M_AXIS_TUSER_WIDTH=128,
parameter C_S_AXIS_TUSER_WIDTH=128,
parameter SRC_PORT_POS=16,
parameter DST_PORT_POS=24,
// Master AXI Stream Data Width
parameter C_FAMILY = "virtex5",
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_USE_WSTRB = 0,
parameter C_DPHASE_TIMEOUT = 0,
parameter C_BASEADDR = 32'hFFFFFFFF,
parameter C_HIGHADDR = 32'h00000000,
parameter C_S_AXI_ACLK_FREQ_HZ = 100
)
(
input [TIMESTAMP_WIDTH-1:0] stamp_counter,
// Global Ports
input axi_aclk,
input axi_resetn,
// Master Stream Ports (interface to data path)
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tstrb,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
// Slave AXI Ports
input S_AXI_ACLK,
input S_AXI_ARESETN,
input [C_S_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input S_AXI_WVALID,
input S_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input S_AXI_ARVALID,
input S_AXI_RREADY,
output S_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output S_AXI_AWREADY
);
///////////////////////////////////////////////////////////
localparam NUM_RW_REGS = 13;
localparam NUM_RO_REGS = 8;
//////////////////////////////////////////////////////////////
wire Bus2IP_Clk;
wire Bus2IP_Resetn;
wire [C_S_AXI_ADDR_WIDTH-1:0] Bus2IP_Addr;
wire [0:0] Bus2IP_CS;
wire Bus2IP_RNW;
wire [C_S_AXI_DATA_WIDTH-1:0] Bus2IP_Data;
wire [C_S_AXI_DATA_WIDTH/8-1:0] Bus2IP_BE;
wire [C_S_AXI_DATA_WIDTH-1:0] IP2Bus_Data;
wire IP2Bus_RdAck;
wire IP2Bus_WrAck;
wire IP2Bus_Error;
wire [NUM_RW_REGS*C_S_AXI_DATA_WIDTH-1:0] rw_regs;
wire [NUM_RO_REGS*C_S_AXI_DATA_WIDTH-1:0] ro_regs;
wire [31:0]generated_packets;
//////////////////////////////////////////
wire [31:0] num_packets;
wire [31:0] payload_size;
wire user_register_write;
wire [48:0] mac_dstaddress;
wire [48:0] mac_srcaddress;
// wire [31:0] ip_length;
wire [31:0] ip_srcip;
wire [31:0] ip_dstip;
// wire [31:0] ip_checksum;
wire [15:0] udp_srcport;
wire [15:0] udp_dstport;
// wire [15:0] udp_length;
//wire [63:0] time_stamp;
wire [31:0] limit;
wire [31:0] packet_generated_gen;
wire [31:0] packet_left;
wire [31:0] state;
wire [31:0] new_packet_generated;
wire my_reset;
wire my_start;
wire [35:0] CONTROL0;
// assign mac_dstaddress = {rw_regs[63:32],rw_regs[15:0]};
// assign mac_srcaddress = {rw_regs[127:96],rw_regs[79:64]};
//
// assign ip_length = rw_regs[159:128];
// assign ip_srcip = rw_regs[191:160];
// assign ip_dstip = rw_regs[223:192];
// assign ip_checksum= rw_regs[255:224];
//
// assign udp_srcport= rw_regs[287:256];
// assign udp_dstport= rw_regs[319:288];
// assign udp_length= rw_regs[351:320];
//
// assign time_stamp= {rw_regs[415:384],rw_regs[383:352]};
//
// assign num_packets = rw_regs[447:416];
// assign payload_size = rw_regs[479:448];
// //assign user_register_write = ;
//
// assign limit = rw_regs[511:480];
// assign my_reset = rw_regs[512];
//assign mac_dstaddress = 48'h06c626da70316;
//assign mac_srcaddress = 48'h06c626da70316;
//assign ip_length = 32'had; //USELESS
//assign ip_srcip = 32'h4137df2d;
//assign ip_dstip = 32'h4137df2e;
//assign ip_checksum= 32'h7a75; //USELESS
//assign udp_srcport= 1'h9c59;
//assign udp_dstport= 16'h9c59;
//assign udp_length= 16'ha;
//assign time_stamp= 64'h4137df2d4137df2d;
//assign num_packets = 32'd1000;
//assign payload_size = 32'd50;
//assign user_register_write = ;
assign my_reset = rw_regs[0];
assign my_start = rw_regs[32];
assign limit = rw_regs[95:64];//32'hA;
assign payload_size = rw_regs[127:96];
assign ip_srcip = rw_regs[159:128];
assign ip_dstip = rw_regs[191:160];
assign udp_srcport= rw_regs[223:192];
assign udp_dstport= rw_regs[255:224];
assign mac_dstaddress = {rw_regs[319:288],rw_regs[287:256]};
assign mac_srcaddress = {rw_regs[383:352],rw_regs[351:320]};
assign num_packets = rw_regs[415:384];
/*
assign ro_regs[31:0] = 32'h06c626da70316];
assign ro_regs[63:32] =rw_regs[63:32];
assign ro_regs[95:64] = rw_regs[95:64];
assign ro_regs[127:96] = rw_regs[127:96] ;
assign ro_regs[159:128] = rw_regs[159:128];
assign ro_regs[191:160] = rw_regs[191:160];
assign ro_regs[223:192] = rw_regs[223:192];
assign ro_regs[255:224] = rw_regs[255:224];
assign ro_regs[287:256] = rw_regs[287:256];
assign ro_regs[319:288] = rw_regs[319:288];
assign ro_regs[351:320] = rw_regs[351:320];
assign ro_regs[383:352] = rw_regs[383:352];
assign ro_regs[415:384] = rw_regs[415:384];
assign ro_regs[447:416] = rw_regs[447:416];
assign ro_regs[479:448] = rw_regs[479:448];
assign ro_regs[511:480] = rw_regs[511:480];
assign ro_regs[543:512] = generated_packets; //rater
assign ro_regs[575:544] = packet_generated_gen; // generator
assign ro_regs[607:576] = packet_left;
assign ro_regs[639:608] = state;
assign ro_regs[671:640] = new_packet_generated;
*/
assign ro_regs[31:0] = 32'h06c626da;
assign ro_regs[63:32] = generated_packets; //rater
assign ro_regs[95:64] = packet_generated_gen; // generator
assign ro_regs[127:96] = packet_left;
assign ro_regs[159:128] = state;
assign ro_regs[191:160] = new_packet_generated;
assign ro_regs[223:192] = stamp_counter[63:32];
assign ro_regs[255:224] = stamp_counter[31:0];
/*
always @(*)
begin
if(S_AXI_ARADDR == C_BASEADDR+'h3C)
user_register_write = S_AXI_WVALID;
else
user_register_write =0;
end
*/
wire signal_in;
wire edge_detected;
reg signal_d;
assign signal_in = my_start;
always @(posedge axi_aclk)
begin
if(!axi_resetn)
signal_d <= 1'b0;
else
signal_d <= signal_in;
end
assign user_register_write = signal_in & (~signal_d);
//////////////////////////chip scope
/*
chipscope_icon ICON (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
chipscope_ila ILA(
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(axi_aclk), // IN
.TRIG0(m_axis_tdata), // IN BUS [255:0]
.TRIG1(m_axis_tstrb), // IN BUS [31:0]
.TRIG2(m_axis_tuser), // IN BUS [127:0]
.TRIG3(m_axis_tvalid), // IN BUS [0:0]
.TRIG4(m_axis_tready), // IN BUS [0:0]
.TRIG5(m_axis_tlast), // IN BUS [0:0]
.TRIG6(new_packet_generated) // IN BUS [31:0]
);
*/
// -- AXILITE IPIF
axi_lite_ipif_1bar
#(
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_USE_WSTRB (C_USE_WSTRB),
.C_DPHASE_TIMEOUT (C_DPHASE_TIMEOUT),
.C_BAR0_BASEADDR (C_BASEADDR),
.C_BAR0_HIGHADDR (C_HIGHADDR))
axi_lite_ipif_inst
(
.S_AXI_ACLK (S_AXI_ACLK),
.S_AXI_ARESETN (S_AXI_ARESETN),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_ARADDR (S_AXI_ARADDR),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_RREADY (S_AXI_RREADY),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RVALID (S_AXI_RVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Controls to the IP/IPIF modules
.Bus2IP_Clk (Bus2IP_Clk),
.Bus2IP_Resetn (Bus2IP_Resetn),
.Bus2IP_Addr (Bus2IP_Addr),
.Bus2IP_RNW (Bus2IP_RNW),
.Bus2IP_BE (Bus2IP_BE),
.Bus2IP_CS (Bus2IP_CS),
.Bus2IP_Data (Bus2IP_Data),
.IP2Bus_Data (IP2Bus_Data),
.IP2Bus_WrAck (IP2Bus_WrAck),
.IP2Bus_RdAck (IP2Bus_RdAck),
.IP2Bus_Error (IP2Bus_Error));
// -- IPIF REGS
ipif_regs
#(
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH ),
.NUM_RW_REGS (NUM_RW_REGS ),
.NUM_RO_REGS (NUM_RO_REGS ))
ipif_regs_inst (
.Bus2IP_Clk (Bus2IP_Clk),
.Bus2IP_Resetn (Bus2IP_Resetn),
.Bus2IP_Addr (Bus2IP_Addr),
.Bus2IP_CS (Bus2IP_CS[0]),
.Bus2IP_RNW (Bus2IP_RNW),
.Bus2IP_Data (Bus2IP_Data),
.Bus2IP_BE (Bus2IP_BE),
.IP2Bus_Data (IP2Bus_Data),
.IP2Bus_RdAck (IP2Bus_RdAck),
.IP2Bus_WrAck (IP2Bus_WrAck),
.IP2Bus_Error (IP2Bus_Error),
.rw_regs (rw_regs),
.ro_regs (ro_regs));
rater rater1 (
.limit(limit),
.clk(axi_aclk),
.reset(!axi_resetn),
.generate_pulse(generate_pulse),
.generated_packets(generated_packets),
.my_reset(my_reset)
);
// Instantiate the Unit Under Test (UUT)
generator gen (
.axi_aclk(axi_aclk),
.axi_resetn(axi_resetn),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(m_axis_tstrb),
.m_axis_tuser(m_axis_tuser),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.num_packets(num_packets),
.payload_size(payload_size),
.user_register_write(user_register_write),
.generate_pulse(generate_pulse),
// .ip_length(ip_length),
.ip_srcip(ip_srcip),
.ip_dstip(ip_dstip),
// .ip_checksum(ip_checksum),
.mac_dstaddress(mac_dstaddress),
.mac_srcaddress(mac_srcaddress),
.udp_srcport(udp_srcport),
.udp_dstport(udp_dstport),
// .udp_length(udp_length),
//.time_stamp(64'hAAAAAAAAAAAAAAAA),
.time_stamp(64'hFFFFFFFFFFFFFFFF),
.packet_generated (packet_generated_gen),
.packet_left (packet_left),
.state(state),
.new_packet_generated(new_packet_generated),
.my_reset(my_reset),
.my_start(my_start)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_TB_V
`define SKY130_FD_SC_HS__A222OI_TB_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a222oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 C1 = 1'b1;
#280 C2 = 1'b1;
#300 VGND = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 C1 = 1'b0;
#440 C2 = 1'b0;
#460 VGND = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VGND = 1'b1;
#540 C2 = 1'b1;
#560 C1 = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VGND = 1'bx;
#700 C2 = 1'bx;
#720 C1 = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hs__a222oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A21O_BLACKBOX_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21o (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_BLACKBOX_V
|
// soc_system_fpga_only_master.v
// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_system_fpga_only_master #(
parameter USE_PLI = 0,
parameter PLI_PORT = 50000,
parameter FIFO_DEPTHS = 2
) (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (USE_PLI != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_pli_check ( .error(1'b1) );
end
if (PLI_PORT != 50000)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
pli_port_check ( .error(1'b1) );
end
if (FIFO_DEPTHS != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.EXPORT_JTAG (0),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.sink_data (p2b_out_bytes_stream_data), // sink.data
.sink_valid (p2b_out_bytes_stream_valid), // .valid
.sink_ready (p2b_out_bytes_stream_ready), // .ready
.resetrequest (master_reset_reset), // resetrequest.reset
.source_ready (1'b1), // (terminated)
.mgmt_valid (), // (terminated)
.mgmt_channel (), // (terminated)
.mgmt_data (), // (terminated)
.jtag_tck (1'b0), // (terminated)
.jtag_tms (1'b0), // (terminated)
.jtag_tdi (1'b0), // (terminated)
.jtag_tdo (), // (terminated)
.jtag_ena (1'b0), // (terminated)
.jtag_usr1 (1'b0), // (terminated)
.jtag_clr (1'b0), // (terminated)
.jtag_clrn (1'b0), // (terminated)
.jtag_state_tlr (1'b0), // (terminated)
.jtag_state_rti (1'b0), // (terminated)
.jtag_state_sdrs (1'b0), // (terminated)
.jtag_state_cdr (1'b0), // (terminated)
.jtag_state_sdr (1'b0), // (terminated)
.jtag_state_e1dr (1'b0), // (terminated)
.jtag_state_pdr (1'b0), // (terminated)
.jtag_state_e2dr (1'b0), // (terminated)
.jtag_state_udr (1'b0), // (terminated)
.jtag_state_sirs (1'b0), // (terminated)
.jtag_state_cir (1'b0), // (terminated)
.jtag_state_sir (1'b0), // (terminated)
.jtag_state_e1ir (1'b0), // (terminated)
.jtag_state_pir (1'b0), // (terminated)
.jtag_state_e2ir (1'b0), // (terminated)
.jtag_state_uir (1'b0), // (terminated)
.jtag_ir_in (3'b000), // (terminated)
.jtag_irq (), // (terminated)
.jtag_ir_out () // (terminated)
);
soc_system_fpga_only_master_timing_adt timing_adt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // in.data
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.out_data (timing_adt_out_data), // out.data
.out_valid (timing_adt_out_valid), // .valid
.out_ready (timing_adt_out_ready) // .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timing_adt_out_data), // in.data
.in_valid (timing_adt_out_valid), // .valid
.in_ready (timing_adt_out_ready), // .ready
.out_data (fifo_out_data), // out.data
.out_valid (fifo_out_valid), // .valid
.out_ready (fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // .ready
.out_valid (b2p_out_packets_stream_valid), // .valid
.out_data (b2p_out_packets_stream_data), // .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_ready (fifo_out_ready), // in_bytes_stream.ready
.in_valid (fifo_out_valid), // .valid
.in_data (fifo_out_data) // .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // .valid
.in_data (p2b_adapter_out_data), // .data
.in_channel (p2b_adapter_out_channel), // .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // .valid
.out_data (p2b_out_bytes_stream_data) // .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // out_stream.ready
.out_valid (transacto_out_stream_valid), // .valid
.out_data (transacto_out_stream_data), // .data
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.in_ready (b2p_adapter_out_ready), // in_stream.ready
.in_valid (b2p_adapter_out_valid), // .valid
.in_data (b2p_adapter_out_data), // .data
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
.address (master_address), // avalon_master.address
.readdata (master_readdata), // .readdata
.read (master_read), // .read
.write (master_write), // .write
.writedata (master_writedata), // .writedata
.waitrequest (master_waitrequest), // .waitrequest
.readdatavalid (master_readdatavalid), // .readdatavalid
.byteenable (master_byteenable) // .byteenable
);
soc_system_fpga_only_master_b2p_adapter b2p_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (b2p_out_packets_stream_data), // in.data
.in_valid (b2p_out_packets_stream_valid), // .valid
.in_ready (b2p_out_packets_stream_ready), // .ready
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_channel (b2p_out_packets_stream_channel), // .channel
.out_data (b2p_adapter_out_data), // out.data
.out_valid (b2p_adapter_out_valid), // .valid
.out_ready (b2p_adapter_out_ready), // .ready
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
);
soc_system_fpga_only_master_p2b_adapter p2b_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (transacto_out_stream_data), // in.data
.in_valid (transacto_out_stream_valid), // .valid
.in_ready (transacto_out_stream_ready), // .ready
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.out_data (p2b_adapter_out_data), // out.data
.out_valid (p2b_adapter_out_valid), // .valid
.out_ready (p2b_adapter_out_ready), // .ready
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_channel (p2b_adapter_out_channel) // .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 11:21:36 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_util_ds_buf_0_0 -prefix
// system_util_ds_buf_0_0_ system_util_ds_buf_0_0_stub.v
// Design : system_util_ds_buf_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "util_ds_buf,Vivado 2016.4" *)
module system_util_ds_buf_0_0(BUFG_I, BUFG_O)
/* synthesis syn_black_box black_box_pad_pin="BUFG_I[0:0],BUFG_O[0:0]" */;
input [0:0]BUFG_I;
output [0:0]BUFG_O;
endmodule
|
/*
* fdc.v Floppy disk emulator controller
*
* This emulates the uPD765 floppy controller used in the CPC
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module fdc (
// CPC CPU Interface
input clk_i,
input reset_i,
input enable_i,
input [7:0] data_i,
output [7:0] data_o,
input regsel_i, // 0 = status, 1 = data
input rd_i,
input wr_i,
output activity_o,
input motor_i,
// Support CPU interface
input sup_clk_i,
input [3:0] A,
input [7:0] D_i,
output [7:0] D_o,
input sup_rd_i,
input sup_wr_i,
input sup_enable_i,
output sup_int_o // Interrupt
);
// States
parameter IDLE = 6'd0, PARAM = 6'd1, READ_WRITE = 6'd2, EXEC = 6'd3, PRERESULT = 6'd4, RESULT = 6'd5, REPEAT = 6'd6;
// Parameter table width
parameter PT_WIDTH = 18;
parameter P_WAIT_TO = 22; // Wait time out - counter size bits 22 = approx 1s at 4MHz
// Wire definitions ===========================================================================
wire p_inval, p_rd, p_wr, p_rpt;
wire [4:0] p_cp;
wire [3:0] p_cr;
wire [1:0] p_rptn; // Results pattern
wire [2:0] p_pptn; // Parameter pattern
wire [0:PT_WIDTH-1] pt;
wire [7:0] status_main;
wire rd_rise, wr_rise;
wire srd_rise, swr_rise;
// Fifo management
wire rdbuf_empty, rdbuf_full;
wire wrbuf_empty, wrbuf_full;
// Support status register
wire [7:0] support_status, D, s2c_dout, c2s_dout;
wire data_reg = (A == 4'd0);
// Work out if we're on track 0 for our selected drive
wire track0;
// Registers ==================================================================================
reg [7:0] S0 = 0, S1 = 0, S2 = 0, S3 = 0;
reg [4:0] opcode;
reg MT, SK;
reg [5:0] state, pr_count; // Parameter or result counter
reg [0:PT_WIDTH-1] op_param;
reg [9:0] data_cntr = 0;
reg [P_WAIT_TO-1:0] wait_timeout = 0;
reg [4:0] param_ptr;
reg [1:0] track_rd = 0, track_wr = 0;
reg [1:0] track_srd = 0, track_swr = 0;
reg [3:0] drive_active = 0, seek_end = 0;
// Wait handlers
reg support_wait_flag = 0; // Signal from support CPU to wait
reg cpc_wait_flag = 0; // Signal from CPC to follow support cpu
wire should_wait = (support_wait_flag != cpc_wait_flag);
// Delay buffer empty flags
reg [1:0] rdbuf_empty_delay = 0;
// Empty flag is set on falling edge of clock, so sample on rising
// This suits Z80 CPU read too, which samples data on falling edge
always @(posedge clk_i) rdbuf_empty_delay <= {rdbuf_empty_delay[0],rdbuf_empty};
// Control registers
reg [7:0] HU = 8'D0, TR = 8'd0, HD = 8'd0, NM = 8'd0, LS = 8'h0, TP = 8'h0, SC = 8'h0, FB = 8'he5, HRESULT = 0, READID = 0;
reg [7:0] result_register = 0;
reg [7:0] current_track0 = 0, current_track1 = 0, current_track2 = 0, current_track3 = 0;
// Function definitions ===========================================================================
// Command table attributes
// INVAL = Invalid command code
// C_P = Count of parameters
// RD = Read command
// WR = Write command
// C_R = Count of result bytes (not data)
// RPT = Repeating instruction
// PPTN = Parameter byte sequence
// RPTN = Result byte sequence
function [0:PT_WIDTH-1] param_table (
input [4:0] cmd
);
case( cmd )
// INVAL C_P RD WR C_R RPT PPTN RPTN
5'h02: param_table = { 1'b0, 5'd8, 1'b1, 1'b0, 4'd7, 1'b1, 3'd0, 2'd0 }; // doesn't really repeat, but used for status code
5'h03: param_table = { 1'b0, 5'd2, 1'b0, 1'b0, 4'd0, 1'b0, 3'd1, 2'd0 };
5'h04: param_table = { 1'b0, 5'd1, 1'b0, 1'b0, 4'd1, 1'b0, 3'd2, 2'd1 };
5'h05: param_table = { 1'b0, 5'd8, 1'b0, 1'b1, 4'd7, 1'b1, 3'd3, 2'd2 };
5'h06: param_table = { 1'b0, 5'd8, 1'b1, 1'b0, 4'd7, 1'b1, 3'd3, 2'd2 };
5'h07: param_table = { 1'b0, 5'd1, 1'b0, 1'b0, 4'd0, 1'b0, 3'd2, 2'd0 };
5'h08: param_table = { 1'b0, 5'd0, 1'b0, 1'b0, 4'd2, 1'b0, 3'd7, 2'd3 };
5'h09: param_table = { 1'b0, 5'd8, 1'b0, 1'b1, 4'd7, 1'b1, 3'd3, 2'd2 };
5'h0a: param_table = { 1'b0, 5'd1, 1'b0, 1'b0, 4'd7, 1'b0, 3'd2, 2'd2 };
5'h0c: param_table = { 1'b0, 5'd8, 1'b1, 1'b0, 4'd7, 1'b1, 3'd3, 2'd2 };
5'h0d: param_table = { 1'b0, 5'd5, 1'b0, 1'b1, 4'd7, 1'b0, 3'd4, 2'd2 };
5'h0f: param_table = { 1'b0, 5'd2, 1'b0, 1'b0, 4'd0, 1'b0, 3'd5, 2'd0 };
5'h11: param_table = { 1'b0, 5'd8, 1'b0, 1'b1, 4'd7, 1'b0, 3'd3, 2'd2 };
5'h19: param_table = { 1'b0, 5'd8, 1'b0, 1'b1, 4'd7, 1'b0, 3'd3, 2'd2 };
5'h1d: param_table = { 1'b0, 5'd8, 1'b0, 1'b1, 4'd7, 1'b0, 3'd3, 2'd2 };
5'h1f: param_table = { 1'b1, 5'd0, 1'b0, 1'b0, 4'd1, 1'b0, 3'd7, 2'd0 }; // Invalid opcode structure
default: param_table = ((2**PT_WIDTH)-1); // Invalid
endcase
endfunction
// Parameter pattern table
function [0:31] param_ptn_table (
input [2:0] ptn
);
case( ptn )
3'd0 : param_ptn_table = {4'd2, 4'd4, 4'd3, 4'hf, 4'hf, 4'd12, 4'hf, 4'hf};
// 1 Not used, will default
3'd2 : param_ptn_table = {4'd2, 28'b_1111_1111_1111_1111_1111_1111_1111};
3'd3 : param_ptn_table = {4'd2, 4'd4, 4'd3, 4'd5, 4'hf, 4'd6, 4'hf, 4'hf};
3'd4 : param_ptn_table = {4'd2, 4'hf, 4'd12, 4'hf, 4'd7, 12'b_1111_1111_1111};
3'd5 : param_ptn_table = {4'd2, 4'd13, 24'b_1111_1111_1111_1111_1111_1111};
// 7 Not used, will default
default: param_ptn_table = 32'hffffffff;
endcase
endfunction
// Results pattern table
function [0:27] result_ptn_table (
input [1:0] ptn
);
case( ptn )
2'd0: result_ptn_table = {4'd8, 4'd9, 4'd10, 4'd04, 4'd03, 4'd12, 4'd00};
2'd1: result_ptn_table = {4'd11, 4'd15, 4'd15, 4'd15, 4'd15, 4'd15, 4'd15};
2'd2: result_ptn_table = {4'd8, 4'd9, 4'd10, 4'd04, 4'd03, 4'd6, 4'd00};
2'd3: result_ptn_table = {4'd8, 4'd13, 4'd15, 4'd15, 4'd15, 4'd15, 4'd15};
endcase
endfunction
// Write a register by reference should match below for clarity, not function
task write_register(
input [3:0] register,
input [7:0] data
);
case( register )
// 00 is a fake register, fixed to 2
// 01 if a fake register, dynamically set
4'd02 : HU <= data;
4'd03 : HD <= data;
4'd04 : TR <= data;
4'd05 : SC <= data;
4'd06 : LS <= data;
4'd07 : FB <= data;
4'd08 : S0 <= data;
4'd09 : S1 <= data;
4'd10 : S2 <= data;
4'd11 : S3 <= data;
4'd12 : NM <= data;
4'd13 : TP <= data;
// 14 is HRESULT but not written using this routine
// 15 is not used a NOP
endcase
endtask
// Register access matrix should match list above for clarity
function [7:0] read_register(
input [3:0] register
);
case( register )
4'd00 : read_register = 2'd2; // Fake register SZ = 2
4'd01 : read_register = support_status;
4'd02 : read_register = HU;
4'd03 : read_register = HD;
4'd04 : read_register = TR;
4'd05 : read_register = SC;
4'd06 : read_register = LS;
4'd07 : read_register = FB;
4'd08 : read_register = S0;
4'd09 : read_register = S1;
4'd10 : read_register = S2;
4'd11 : read_register = S3;
4'd12 : read_register = NM;
4'd13 : read_register = TP;
4'd14 : read_register = HRESULT;
default: read_register = 8'hff;
endcase
endfunction
// Split param_pattern
function [3:0] split(
input [0:31] source,
input [2:0] item
);
case( item )
3'd0 : split = source[0:3];
3'd1 : split = source[4:7];
3'd2 : split = source[8:11];
3'd3 : split = source[12:15];
3'd4 : split = source[16:19];
3'd5 : split = source[20:23];
3'd6 : split = source[24:27];
3'd7 : split = source[28:31];
endcase
endfunction
// Assignments ================================================================================
// Main CPC data output
assign data_o = !regsel_i ? status_main :
(state == EXEC) ? ((rdbuf_empty_delay == 2'b11) ? 8'hff : s2c_dout) :
(state == RESULT) ? result_register :
8'hff; // Default when not in-cycle
// Activity light indicator
assign activity_o = (state == READ_WRITE) && should_wait; //enable_i & (rd_i | wr_i) & regsel_i;
// Get operation codes
assign pt = param_table( data_i[4:0] );
// Decode operation codes, either with a live wire, or a register, depending upon the state
assign {p_inval, p_cp, p_rd, p_wr, p_cr, p_rpt, p_pptn, p_rptn} = (state == IDLE) ? pt : op_param;
// Maintain the support interface status register
assign support_status = {motor_i, should_wait, SK, opcode};
// Maintain the main status flag
assign status_main = {
// Ready flag
((state == IDLE) || (state == PARAM) || (state == EXEC) || (state == RESULT)),
// Read/Write Flag
(state == RESULT) || ((state == EXEC) & p_rd),
// In exec state
(state == EXEC),
// Active controller
(state != IDLE),
// Indicate drive activity 3-0
drive_active};
// Track RD+WR rise
assign rd_rise = (track_rd == 2'b01);
assign wr_rise = (track_wr == 2'b01);
assign srd_rise = (track_srd == 2'b01);
assign swr_rise = (track_swr == 2'b01);
// Support data connection
assign D_o = (A == 4'd0) ? c2s_dout : read_register(A);
// Work out if we're on track 0
assign track0 = (HU[1:0] == 2'd0) ? (current_track0 == 8'd0) :
(HU[1:0] == 2'd1) ? (current_track1 == 8'd0) :
(HU[1:0] == 2'd2) ? (current_track2 == 8'd0) :
(HU[1:0] == 2'd3) ? (current_track3 == 8'd0) : 1'b0;
// Module connections =========================================================================
// FIFO buffers
// Read fifo
fifo #(
.log2_addr(9), // 512 bytes
.data_width(8)
) s2c (
.n_reset_i(~reset_i && (state > IDLE)), // Reset at idle
.wclk_i(sup_clk_i), // Support connection
.data_i(/*xxx*/D_i),
.wr_i(swr_rise /*&& (state == READ_WRITE)*/), // TODO: Does the state matter? Can write anytime when not in IDLE?
.rclk_i(clk_i), //CPC Connection
.data_o(s2c_dout),
.rd_i(rd_rise && (state == EXEC)), // Note that data is delayed by 1 clock
.fifo_empty_o(rdbuf_empty),
.fifo_full_o(rdbuf_full)
);
// Write fifo
fifo #(
.log2_addr(9), // 512 bytes
.data_width(8)
) c2s (
.n_reset_i(~reset_i && (state > IDLE)), // reset at idle
.wclk_i(clk_i), // CPC connection
.data_i(data_i),
.wr_i(wr_rise && (state == EXEC)),
.rclk_i(sup_clk_i), // Support connection
.data_o(c2s_dout),
.rd_i(srd_rise),
.fifo_empty_o(wrbuf_empty),
.fifo_full_o(wrbuf_full)
);
// Simulation branches and control ============================================================
// Other logic ================================================================================
// FSM output logic
always @(posedge clk_i)
begin
if( reset_i )
begin
state <= IDLE;
cpc_wait_flag <= 0;
end
else case( state )
IDLE: // Record the opcode if it's valid
if ( wr_rise /*& enable_i*/ ) begin
opcode <= data_i[4:0]; // Store the opcode
MT <= data_i[7]; // And associated command bits
SK <= data_i[5];
op_param <= pt; // Store the code structure
param_ptr <= 1'b0; // Pointer
// Valid Opcode
if ( ~p_inval )
begin
// Set next state
if( p_cp > 0 )
begin
pr_count <= p_cp; // Store the parameter count
state <= PARAM;
end
else begin // Only SenseInt has no parameters
pr_count <= p_cr; // Store the result count
state <= READ_WRITE; // Only sense.int without parameters
end
// Set data counter, for if it's needed
data_cntr <= (p_rd|p_wr) ? 10'd512 : 1'b0; // What about format?
// Set wait timeout for if it's needed
wait_timeout <= ((2**P_WAIT_TO)-1);
end
// Invalid Opcode
else state <= PRERESULT;
end
PARAM: // Get the params
begin
if( wr_rise & enable_i & regsel_i) begin
write_register( split( param_ptn_table( p_pptn ), param_ptr ), data_i );
if( pr_count == 1 ) // i.e. Last parameter
begin
if( ~should_wait & ~p_wr ) cpc_wait_flag <= ~cpc_wait_flag; // Toggle the wait flag if read op
// wait_timeout <= (2**P_WAIT_TO)-1;
// If read operation, go to read, otherwise goto exec to get data, idle is fail safe
state <= p_wr ? EXEC : READ_WRITE;
// if( p_wr ) data_cntr <= 10'd512;
end
else begin
pr_count <= pr_count - 1'b1;
param_ptr <= param_ptr + 1'b1;
end
end
end
READ_WRITE:
begin // Wait until the master has processed params or filled the buffer
if( ( wait_timeout == 0 ) || ~should_wait )
begin
if( p_rd )
begin
// data_cntr <= (p_rd) ? 10'd512 : 1'b0; // What about format?
state <= EXEC;
end
else // Write operation, so straight to result
state <= PRERESULT;
end
else wait_timeout <= wait_timeout - 1'b1;
end
EXEC: // CPC reads in/out data_cntr bytes
begin
if( data_cntr == 0 ) begin
state <= p_wr ? READ_WRITE : PRERESULT; // Set next status
if( ~should_wait & p_wr ) cpc_wait_flag <= ~cpc_wait_flag; // Toggle the wait flag if write op
end
else if( rd_rise | wr_rise ) data_cntr <= data_cntr - 1'b1;
end
PRERESULT:
begin // Here we set up all the response codes
// Set the next state
if( p_cr > 0 )
state <= RESULT;
else
state <= IDLE;
// Result count setup
pr_count <= (~p_inval) ? p_cr : 1'd1; // How many results, only S0 for error
param_ptr <= 1'b0; // Pointer
// Set seek/recalib
if( ( opcode == 5'h0f ) /*seek*/ || ( opcode == 5'h07 ) /* recalib */ )
begin
// First set TR - TR and TP must be the same - no special formats!
TR <= ( opcode[3] ) ? TP : 8'd0;
seek_end <= 1'b1;
// Then set track 0 signal
case( HU[1:0] )
2'd00: begin
drive_active[0] <= 1;
if( opcode[3] ) // If seek
current_track0 <= TP;
else
current_track0 <= 8'd0;
end
2'd01: begin
drive_active[1] <= 1;
if( opcode[3] ) // If seek
current_track1 <= TP;
else
current_track1 <= 8'd0;
end
2'd02: begin
drive_active[2] <= 1;
if( opcode[3] ) // If seek
current_track2 <= TP;
else
current_track2 <= 8'd0;
end
2'd03: begin
drive_active[3] <= 1;
if( opcode[3] ) // If seek
current_track3 <= TP;
else
current_track3 <= 8'd0;
end
endcase
end
// If sense.int, then clear busy flags
if( opcode == 5'h08 ) drive_active <= 4'd0;
// If read ID, then populate LS with ID
if( opcode == 5'h0a )
begin
LS <= READID;
TR <= 8'd0;
HD <= 8'd0;
end
// Set status regs ===========================================
S0 <= {
// Set error codes for bit 6+7
p_inval ? 2'b10 : // Invalid opcode
HRESULT[0] ? 2'b11 : // Drive not ready
p_rpt ? 2'd01 : // Aborted/read fail because operation repeat not terminated (normal for a CPC)
2'd0, // All OK
// Bit 5 - seek end
(seek_end) ? 1'b1 : ((opcode == 5'h08)||(opcode == 5'h0a)) ? 1'b0 : S0[5],
// Bit 4 Equip / recal fail,
HRESULT[1],
// 3 not ready
HRESULT[0],
// 2-hd, 1:0 Unit
HU[2:0]
};
// End-of-track, ----, Write prot, sector id not found
S1 <= {(p_rd|p_wr), 4'd0, HRESULT[2], HRESULT[3], HRESULT[2]};
S2 <= 8'd0; //{3'd0,HRESULT[2],1'b0,HRESULT[2],HRESULT[2],HRESULT[2]};
S3 <= {1'b0, HRESULT[3], 1'b1, track0, 1'b0, HU[2:0]};
end
RESULT:
begin
// Reset seek_end flag - no results stage for seek/recal commands, so OK to reset here
seek_end <= 0;
// Read out the results, only progress if RD is active and data reg accessed
if( rd_rise ) begin
result_register <= read_register( split( {result_ptn_table( p_rptn ),4'd0}, param_ptr ) );
if( pr_count != 0 ) begin
// Shift result register
pr_count <= pr_count - 1'b1;
param_ptr <= param_ptr + 1'b1;
end
end
else
if( pr_count == 0 ) begin
state <= IDLE; // TODO: repeat
end
end
default: state <= IDLE;
endcase
end
// Toggle Support Flag if needed
always @(posedge sup_clk_i)
begin
if( reset_i )
support_wait_flag <= 0;
else
if( (A == 4'd1) && D_i[0] && sup_wr_i && sup_enable_i && should_wait )
support_wait_flag <= ~support_wait_flag;
end
// Track the CPC read/write cycle so that we don't accidentally empty the FIFOs
always @(negedge clk_i)
begin
track_rd <= {track_rd[0], enable_i & regsel_i & rd_i};
track_wr <= {track_wr[0], enable_i & regsel_i & wr_i};
end
// Track the RD/WR signal for support connection to FIFO
always @(negedge sup_clk_i)
begin
track_srd <= {track_srd[0], sup_enable_i & data_reg & sup_rd_i};
track_swr <= {track_swr[0], sup_enable_i & data_reg & sup_wr_i};
end
// Handle Host Status Reg Write
always @(posedge sup_clk_i)
begin
if( (A == 4'd14) && sup_wr_i && sup_enable_i) HRESULT <= D_i;
end
// Handle Read ID Write
always @(posedge sup_clk_i)
begin
if( (A == 4'd15) && sup_wr_i && sup_enable_i) READID <= D_i;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3B_2_V
`define SKY130_FD_SC_HDLL__OR3B_2_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or3b_2 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or3b_2 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_SYMBOL_V
`define SKY130_FD_SC_HVL__DECAP_SYMBOL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFRTN_PP_SYMBOL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFINV_TB_V
`define SKY130_FD_SC_HS__BUFINV_TB_V
/**
* bufinv: Buffer followed by inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__bufinv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__bufinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFINV_TB_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_outputcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:46 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.4 2002/07/09 20:11:59 mohor
// Comment removed.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`timescale 1ns/10ps
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
parameter Tp = 1;
input Clk; // Host Clock
input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
input NoPre; // No Preamble (no 32-bit preamble)
input InProgress; // Operation in progress
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
input [6:0] BitCounter; // Bit Counter
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
wire SerialEn;
reg MdoEn_2d;
reg MdoEn_d;
reg MdoEn;
reg Mdo_2d;
reg Mdo_d;
reg Mdo; // MII Management Data Output
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
MdoEn_2d <= #Tp 1'b0;
MdoEn_d <= #Tp 1'b0;
MdoEn <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
MdoEn_d <= #Tp MdoEn_2d;
MdoEn <= #Tp MdoEn_d;
end
end
end
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
Mdo_2d <= #Tp 1'b0;
Mdo_d <= #Tp 1'b0;
Mdo <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
Mdo_d <= #Tp ShiftedBit | Mdo_2d;
Mdo <= #Tp Mdo_d;
end
end
end
endmodule
|
// 32-bit adder
// Using Carry Lookahead adders
module adder
(
input wire [31:0] op1,
input wire [31:0] op2,
input wire cin,
output wire [31:0] sum,
output wire carry,
output wire v_flag
);
wire[6:0] cout;
assign v_flag = carry ^ cout[6];
carry_lookahead_adder CLA1(op1[3:0], op2[3:0], cin, sum[3:0], cout[0]);
carry_lookahead_adder CLA2(op1[7:4], op2[7:4], cout[0], sum[7:4], cout[1]);
carry_lookahead_adder CLA3(op1[11:8], op2[11:8], cout[1], sum[11:8], cout[2]);
carry_lookahead_adder CLA4(op1[15:12], op2[15:12], cout[2], sum[15:12], cout[3]);
carry_lookahead_adder CLA5(op1[19:16], op2[19:16], cout[3], sum[19:16], cout[4]);
carry_lookahead_adder CLA6(op1[23:20], op2[23:20], cout[4], sum[23:20], cout[5]);
carry_lookahead_adder CLA7(op1[27:24], op2[27:24], cout[5], sum[27:24], cout[6]);
carry_lookahead_adder CLA8(op1[31:28], op2[31:28], cout[6], sum[31:28], carry);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_V
`define SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_V |
/******************************************************************************
*
* File Name : decode.v
* Version : 0.1
* Date : Feb 20, 2008
* Description : LZS decode algorithm top module
* Dependencies :
*
* Company : Beijing Soul
* Author : Hu Gang
*
*****************************************************************************/
module decode(/*AUTOARG*/
// Outputs
valid_o, m_src_getn, done_o, data_o,
// Inputs
src_empty, rst, m_last, fo_full, fi, clk, ce
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [15:0] data_o; // From decode_out of decode_out.v
output done_o; // From decode_out of decode_out.v
output m_src_getn; // From decode_in of decode_in.v
output valid_o; // From decode_out of decode_out.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input ce; // To decode_in of decode_in.v, ...
input clk; // To decode_in of decode_in.v, ...
input [63:0] fi; // To decode_in of decode_in.v
input fo_full; // To decode_in of decode_in.v, ...
input m_last; // To decode_in of decode_in.v
input rst; // To decode_in of decode_in.v, ...
input src_empty; // To decode_in of decode_in.v
// End of automatics
/*AUTOREG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] out_data; // From decode_ctl of decode_ctl.v
wire out_done; // From decode_ctl of decode_ctl.v
wire out_valid; // From decode_ctl of decode_ctl.v
wire stream_ack; // From decode_ctl of decode_ctl.v
wire [12:0] stream_data; // From decode_in of decode_in.v
wire stream_done; // From decode_in of decode_in.v
wire stream_valid; // From decode_in of decode_in.v
wire [3:0] stream_width; // From decode_ctl of decode_ctl.v
// End of automatics
/* Local variable */
// End definition
decode_in decode_in (/*AUTOINST*/
// Outputs
.m_src_getn (m_src_getn),
.stream_data (stream_data[12:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
// Inputs
.clk (clk),
.rst (rst),
.ce (ce),
.m_last (m_last),
.fo_full (fo_full),
.src_empty (src_empty),
.fi (fi[63:0]),
.stream_width (stream_width[3:0]),
.stream_ack (stream_ack));
decode_ctl decode_ctl (/*AUTOINST*/
// Outputs
.stream_width (stream_width[3:0]),
.stream_ack (stream_ack),
.out_data (out_data[7:0]),
.out_valid (out_valid),
.out_done (out_done),
// Inputs
.clk (clk),
.rst (rst),
.ce (ce),
.fo_full (fo_full),
.stream_data (stream_data[12:0]),
.stream_valid (stream_valid),
.stream_done (stream_done));
decode_out decode_out (/*AUTOINST*/
// Outputs
.data_o (data_o[15:0]),
.valid_o (valid_o),
.done_o (done_o),
// Inputs
.clk (clk),
.rst (rst),
.out_valid (out_valid),
.out_done (out_done),
.out_data (out_data[7:0]));
endmodule // decode
// Local Variables:
// verilog-library-directories:("." "../../state_machine/src/" "../../copy_ref/src/" "../../output_token/src/" "../../history_ram/src/")
// verilog-library-extensions:(".v" ".h")
// End:
|
module delta_rom (clock, address, delta_out);
input clock;
input [9:0] address;
output [31:0] delta_out;
reg [31:0] delta_out;
always@(posedge clock)
begin
case(address)
10'd0: delta_out = 32'b00010000000000000000000000000000;
10'd1: delta_out = 32'b00010000001000000000000000000000;
10'd2: delta_out = 32'b00010000010000000000000000000000;
10'd3: delta_out = 32'b00010000011000000000000000000000;
10'd4: delta_out = 32'b00010000100000000000000000000000;
10'd5: delta_out = 32'b00010000101000000000000000000000;
10'd6: delta_out = 32'b00010000110000000000000000000000;
10'd7: delta_out = 32'b00010000111000000000000000000000;
10'd8: delta_out = 32'b00010001000000000000000000000000;
10'd9: delta_out = 32'b00010001001000000000000000000000;
10'd10: delta_out = 32'b00010001010000000000000000000000;
10'd11: delta_out = 32'b00010001011000000000000000000000;
10'd12: delta_out = 32'b00010001100000000000000000000000;
10'd13: delta_out = 32'b00010001101000000000000000000000;
10'd14: delta_out = 32'b00010001110000000000000000000000;
10'd15: delta_out = 32'b00010001111000000000000000000000;
10'd16: delta_out = 32'b00010010000000000000000000000000;
10'd17: delta_out = 32'b00010010001000000000000000000000;
10'd18: delta_out = 32'b00010010010000000000000000000000;
10'd19: delta_out = 32'b00010010011000000000000000000000;
10'd20: delta_out = 32'b00010010100000000000000000000000;
10'd21: delta_out = 32'b00010010101000000000000000000000;
10'd22: delta_out = 32'b00010010110000000000000000000000;
10'd23: delta_out = 32'b00010010111000000000000000000000;
10'd24: delta_out = 32'b00010011000000000000000000000000;
10'd25: delta_out = 32'b00010011001000000000000000000000;
10'd26: delta_out = 32'b00010011010000000000000000000000;
10'd27: delta_out = 32'b00010011011000000000000000000000;
10'd28: delta_out = 32'b00010011100000000000000000000000;
10'd29: delta_out = 32'b00010011101000000000000000000000;
10'd30: delta_out = 32'b00010011110000000000000000000000;
10'd31: delta_out = 32'b00010011111000000000000000000000;
10'd32: delta_out = 32'b00010100000000000000000000000000;
10'd33: delta_out = 32'b00010100001000000000000000000000;
10'd34: delta_out = 32'b00010100010000000000000000000000;
10'd35: delta_out = 32'b00010100011000000000000000000000;
10'd36: delta_out = 32'b00010100100000000000000000000000;
10'd37: delta_out = 32'b00010100101000000000000000000000;
10'd38: delta_out = 32'b00010100110000000000000000000000;
10'd39: delta_out = 32'b00010100111000000000000000000000;
10'd40: delta_out = 32'b00010101000000000000000000000000;
10'd41: delta_out = 32'b00010101001000000000000000000000;
10'd42: delta_out = 32'b00010101010000000000000000000000;
10'd43: delta_out = 32'b00010101011000000000000000000000;
10'd44: delta_out = 32'b00010101100000000000000000000000;
10'd45: delta_out = 32'b00010101101000000000000000000000;
10'd46: delta_out = 32'b00010101110000000000000000000000;
10'd47: delta_out = 32'b00010101111000000000000000000000;
10'd48: delta_out = 32'b00010110000000000000000000000000;
10'd49: delta_out = 32'b00010110001000000000000000000000;
10'd50: delta_out = 32'b00010110010000000000000000000000;
10'd51: delta_out = 32'b00010110011000000000000000000000;
10'd52: delta_out = 32'b00010110100000000000000000000000;
10'd53: delta_out = 32'b00010110101000000000000000000000;
10'd54: delta_out = 32'b00010110110000000000000000000000;
10'd55: delta_out = 32'b00010110111000000000000000000000;
10'd56: delta_out = 32'b00010111000000000000000000000000;
10'd57: delta_out = 32'b00010111001000000000000000000000;
10'd58: delta_out = 32'b00010111010000000000000000000000;
10'd59: delta_out = 32'b00010111011000000000000000000000;
10'd60: delta_out = 32'b00010111100000000000000000000000;
10'd61: delta_out = 32'b00010111101000000000000000000000;
10'd62: delta_out = 32'b00010111110000000000000000000000;
10'd63: delta_out = 32'b00010111111000000000000000000000;
10'd64: delta_out = 32'b00011000000000000000000000000000;
10'd65: delta_out = 32'b00011000001000000000000000000000;
10'd66: delta_out = 32'b00011000010000000000000000000000;
10'd67: delta_out = 32'b00011000011000000000000000000000;
10'd68: delta_out = 32'b00011000100000000000000000000000;
10'd69: delta_out = 32'b00011000101000000000000000000000;
10'd70: delta_out = 32'b00011000110000000000000000000000;
10'd71: delta_out = 32'b00011000111000000000000000000000;
10'd72: delta_out = 32'b00011001000000000000000000000000;
10'd73: delta_out = 32'b00011001001000000000000000000000;
10'd74: delta_out = 32'b00011001010000000000000000000000;
10'd75: delta_out = 32'b00011001011000000000000000000000;
10'd76: delta_out = 32'b00011001100000000000000000000000;
10'd77: delta_out = 32'b00011001101000000000000000000000;
10'd78: delta_out = 32'b00011001110000000000000000000000;
10'd79: delta_out = 32'b00011001111000000000000000000000;
10'd80: delta_out = 32'b00011010000000000000000000000000;
10'd81: delta_out = 32'b00011010001000000000000000000000;
10'd82: delta_out = 32'b00011010010000000000000000000000;
10'd83: delta_out = 32'b00011010011000000000000000000000;
10'd84: delta_out = 32'b00011010100000000000000000000000;
10'd85: delta_out = 32'b00011010101000000000000000000000;
10'd86: delta_out = 32'b00011010110000000000000000000000;
10'd87: delta_out = 32'b00011010111000000000000000000000;
10'd88: delta_out = 32'b00011011000000000000000000000000;
10'd89: delta_out = 32'b00011011001000000000000000000000;
10'd90: delta_out = 32'b00011011010000000000000000000000;
10'd91: delta_out = 32'b00011011011000000000000000000000;
10'd92: delta_out = 32'b00011011100000000000000000000000;
10'd93: delta_out = 32'b00011011101000000000000000000000;
10'd94: delta_out = 32'b00011011110000000000000000000000;
10'd95: delta_out = 32'b00011011111000000000000000000000;
10'd96: delta_out = 32'b00011100000000000000000000000000;
10'd97: delta_out = 32'b00011100001000000000000000000000;
10'd98: delta_out = 32'b00011100010000000000000000000000;
10'd99: delta_out = 32'b00011100011000000000000000000000;
10'd100: delta_out = 32'b00011100100000000000000000000000;
10'd101: delta_out = 32'b00011100101000000000000000000000;
10'd102: delta_out = 32'b00011100110000000000000000000000;
10'd103: delta_out = 32'b00011100111000000000000000000000;
10'd104: delta_out = 32'b00011101000000000000000000000000;
10'd105: delta_out = 32'b00011101001000000000000000000000;
10'd106: delta_out = 32'b00011101010000000000000000000000;
10'd107: delta_out = 32'b00011101011000000000000000000000;
10'd108: delta_out = 32'b00011101100000000000000000000000;
10'd109: delta_out = 32'b00011101101000000000000000000000;
10'd110: delta_out = 32'b00011101110000000000000000000000;
10'd111: delta_out = 32'b00011101111000000000000000000000;
10'd112: delta_out = 32'b00011110000000000000000000000000;
10'd113: delta_out = 32'b00011110001000000000000000000000;
10'd114: delta_out = 32'b00011110010000000000000000000000;
10'd115: delta_out = 32'b00011110011000000000000000000000;
10'd116: delta_out = 32'b00011110100000000000000000000000;
10'd117: delta_out = 32'b00011110101000000000000000000000;
10'd118: delta_out = 32'b00011110110000000000000000000000;
10'd119: delta_out = 32'b00011110111000000000000000000000;
10'd120: delta_out = 32'b00011111000000000000000000000000;
10'd121: delta_out = 32'b00011111001000000000000000000000;
10'd122: delta_out = 32'b00011111010000000000000000000000;
10'd123: delta_out = 32'b00011111011000000000000000000000;
10'd124: delta_out = 32'b00011111100000000000000000000000;
10'd125: delta_out = 32'b00011111101000000000000000000000;
10'd126: delta_out = 32'b00011111110000000000000000000000;
10'd127: delta_out = 32'b00011111111000000000000000000000;
10'd128: delta_out = 32'b00100000000000000000000000000000;
10'd129: delta_out = 32'b00100000001000000000000000000000;
10'd130: delta_out = 32'b00100000010000000000000000000000;
10'd131: delta_out = 32'b00100000011000000000000000000000;
10'd132: delta_out = 32'b00100000100000000000000000000000;
10'd133: delta_out = 32'b00100000101000000000000000000000;
10'd134: delta_out = 32'b00100000110000000000000000000000;
10'd135: delta_out = 32'b00100000111000000000000000000000;
10'd136: delta_out = 32'b00100001000000000000000000000000;
10'd137: delta_out = 32'b00100001001000000000000000000000;
10'd138: delta_out = 32'b00100001010000000000000000000000;
10'd139: delta_out = 32'b00100001011000000000000000000000;
10'd140: delta_out = 32'b00100001100000000000000000000000;
10'd141: delta_out = 32'b00100001101000000000000000000000;
10'd142: delta_out = 32'b00100001110000000000000000000000;
10'd143: delta_out = 32'b00100001111000000000000000000000;
10'd144: delta_out = 32'b00100010000000000000000000000000;
10'd145: delta_out = 32'b00100010001000000000000000000000;
10'd146: delta_out = 32'b00100010010000000000000000000000;
10'd147: delta_out = 32'b00100010011000000000000000000000;
10'd148: delta_out = 32'b00100010100000000000000000000000;
10'd149: delta_out = 32'b00100010101000000000000000000000;
10'd150: delta_out = 32'b00100010110000000000000000000000;
10'd151: delta_out = 32'b00100010111000000000000000000000;
10'd152: delta_out = 32'b00100011000000000000000000000000;
10'd153: delta_out = 32'b00100011001000000000000000000000;
10'd154: delta_out = 32'b00100011010000000000000000000000;
10'd155: delta_out = 32'b00100011011000000000000000000000;
10'd156: delta_out = 32'b00100011100000000000000000000000;
10'd157: delta_out = 32'b00100011101000000000000000000000;
10'd158: delta_out = 32'b00100011110000000000000000000000;
10'd159: delta_out = 32'b00100011111000000000000000000000;
10'd160: delta_out = 32'b00100100000000000000000000000000;
10'd161: delta_out = 32'b00100100001000000000000000000000;
10'd162: delta_out = 32'b00100100010000000000000000000000;
10'd163: delta_out = 32'b00100100011000000000000000000000;
10'd164: delta_out = 32'b00100100100000000000000000000000;
10'd165: delta_out = 32'b00100100101000000000000000000000;
10'd166: delta_out = 32'b00100100110000000000000000000000;
10'd167: delta_out = 32'b00100100111000000000000000000000;
10'd168: delta_out = 32'b00100101000000000000000000000000;
10'd169: delta_out = 32'b00100101001000000000000000000000;
10'd170: delta_out = 32'b00100101010000000000000000000000;
10'd171: delta_out = 32'b00100101011000000000000000000000;
10'd172: delta_out = 32'b00100101100000000000000000000000;
10'd173: delta_out = 32'b00100101101000000000000000000000;
10'd174: delta_out = 32'b00100101110000000000000000000000;
10'd175: delta_out = 32'b00100101111000000000000000000000;
10'd176: delta_out = 32'b00100110000000000000000000000000;
10'd177: delta_out = 32'b00100110001000000000000000000000;
10'd178: delta_out = 32'b00100110010000000000000000000000;
10'd179: delta_out = 32'b00100110011000000000000000000000;
10'd180: delta_out = 32'b00100110100000000000000000000000;
10'd181: delta_out = 32'b00100110101000000000000000000000;
10'd182: delta_out = 32'b00100110110000000000000000000000;
10'd183: delta_out = 32'b00100110111000000000000000000000;
10'd184: delta_out = 32'b00100111000000000000000000000000;
10'd185: delta_out = 32'b00100111001000000000000000000000;
10'd186: delta_out = 32'b00100111010000000000000000000000;
10'd187: delta_out = 32'b00100111011000000000000000000000;
10'd188: delta_out = 32'b00100111100000000000000000000000;
10'd189: delta_out = 32'b00100111101000000000000000000000;
10'd190: delta_out = 32'b00100111110000000000000000000000;
10'd191: delta_out = 32'b00100111111000000000000000000000;
10'd192: delta_out = 32'b00101000000000000000000000000000;
10'd193: delta_out = 32'b00101000001000000000000000000000;
10'd194: delta_out = 32'b00101000010000000000000000000000;
10'd195: delta_out = 32'b00101000011000000000000000000000;
10'd196: delta_out = 32'b00101000100000000000000000000000;
10'd197: delta_out = 32'b00101000101000000000000000000000;
10'd198: delta_out = 32'b00101000110000000000000000000000;
10'd199: delta_out = 32'b00101000111000000000000000000000;
10'd200: delta_out = 32'b00101001000000000000000000000000;
10'd201: delta_out = 32'b00101001001000000000000000000000;
10'd202: delta_out = 32'b00101001010000000000000000000000;
10'd203: delta_out = 32'b00101001011000000000000000000000;
10'd204: delta_out = 32'b00101001100000000000000000000000;
10'd205: delta_out = 32'b00101001101000000000000000000000;
10'd206: delta_out = 32'b00101001110000000000000000000000;
10'd207: delta_out = 32'b00101001111000000000000000000000;
10'd208: delta_out = 32'b00101010000000000000000000000000;
10'd209: delta_out = 32'b00101010001000000000000000000000;
10'd210: delta_out = 32'b00101010010000000000000000000000;
10'd211: delta_out = 32'b00101010011000000000000000000000;
10'd212: delta_out = 32'b00101010100000000000000000000000;
10'd213: delta_out = 32'b00101010101000000000000000000000;
10'd214: delta_out = 32'b00101010110000000000000000000000;
10'd215: delta_out = 32'b00101010111000000000000000000000;
10'd216: delta_out = 32'b00101011000000000000000000000000;
10'd217: delta_out = 32'b00101011001000000000000000000000;
10'd218: delta_out = 32'b00101011010000000000000000000000;
10'd219: delta_out = 32'b00101011011000000000000000000000;
10'd220: delta_out = 32'b00101011100000000000000000000000;
10'd221: delta_out = 32'b00101011101000000000000000000000;
10'd222: delta_out = 32'b00101011110000000000000000000000;
10'd223: delta_out = 32'b00101011111000000000000000000000;
10'd224: delta_out = 32'b00101100000000000000000000000000;
10'd225: delta_out = 32'b00101100001000000000000000000000;
10'd226: delta_out = 32'b00101100010000000000000000000000;
10'd227: delta_out = 32'b00101100011000000000000000000000;
10'd228: delta_out = 32'b00101100100000000000000000000000;
10'd229: delta_out = 32'b00101100101000000000000000000000;
10'd230: delta_out = 32'b00101100110000000000000000000000;
10'd231: delta_out = 32'b00101100111000000000000000000000;
10'd232: delta_out = 32'b00101101000000000000000000000000;
10'd233: delta_out = 32'b00101101001000000000000000000000;
10'd234: delta_out = 32'b00101101010000000000000000000000;
10'd235: delta_out = 32'b00101101011000000000000000000000;
10'd236: delta_out = 32'b00101101100000000000000000000000;
10'd237: delta_out = 32'b00101101101000000000000000000000;
10'd238: delta_out = 32'b00101101110000000000000000000000;
10'd239: delta_out = 32'b00101101111000000000000000000000;
10'd240: delta_out = 32'b00101110000000000000000000000000;
10'd241: delta_out = 32'b00101110001000000000000000000000;
10'd242: delta_out = 32'b00101110010000000000000000000000;
10'd243: delta_out = 32'b00101110011000000000000000000000;
10'd244: delta_out = 32'b00101110100000000000000000000000;
10'd245: delta_out = 32'b00101110101000000000000000000000;
10'd246: delta_out = 32'b00101110110000000000000000000000;
10'd247: delta_out = 32'b00101110111000000000000000000000;
10'd248: delta_out = 32'b00101111000000000000000000000000;
10'd249: delta_out = 32'b00101111001000000000000000000000;
10'd250: delta_out = 32'b00101111010000000000000000000000;
10'd251: delta_out = 32'b00101111011000000000000000000000;
10'd252: delta_out = 32'b00101111100000000000000000000000;
10'd253: delta_out = 32'b00101111101000000000000000000000;
10'd254: delta_out = 32'b00101111110000000000000000000000;
10'd255: delta_out = 32'b00101111111000000000000000000000;
10'd256: delta_out = 32'b00110000000000000000000000000000;
10'd257: delta_out = 32'b00101111111000000000000000000000;
10'd258: delta_out = 32'b00101111110000000000000000000000;
10'd259: delta_out = 32'b00101111101000000000000000000000;
10'd260: delta_out = 32'b00101111100000000000000000000000;
10'd261: delta_out = 32'b00101111011000000000000000000000;
10'd262: delta_out = 32'b00101111010000000000000000000000;
10'd263: delta_out = 32'b00101111001000000000000000000000;
10'd264: delta_out = 32'b00101111000000000000000000000000;
10'd265: delta_out = 32'b00101110111000000000000000000000;
10'd266: delta_out = 32'b00101110110000000000000000000000;
10'd267: delta_out = 32'b00101110101000000000000000000000;
10'd268: delta_out = 32'b00101110100000000000000000000000;
10'd269: delta_out = 32'b00101110011000000000000000000000;
10'd270: delta_out = 32'b00101110010000000000000000000000;
10'd271: delta_out = 32'b00101110001000000000000000000000;
10'd272: delta_out = 32'b00101110000000000000000000000000;
10'd273: delta_out = 32'b00101101111000000000000000000000;
10'd274: delta_out = 32'b00101101110000000000000000000000;
10'd275: delta_out = 32'b00101101101000000000000000000000;
10'd276: delta_out = 32'b00101101100000000000000000000000;
10'd277: delta_out = 32'b00101101011000000000000000000000;
10'd278: delta_out = 32'b00101101010000000000000000000000;
10'd279: delta_out = 32'b00101101001000000000000000000000;
10'd280: delta_out = 32'b00101101000000000000000000000000;
10'd281: delta_out = 32'b00101100111000000000000000000000;
10'd282: delta_out = 32'b00101100110000000000000000000000;
10'd283: delta_out = 32'b00101100101000000000000000000000;
10'd284: delta_out = 32'b00101100100000000000000000000000;
10'd285: delta_out = 32'b00101100011000000000000000000000;
10'd286: delta_out = 32'b00101100010000000000000000000000;
10'd287: delta_out = 32'b00101100001000000000000000000000;
10'd288: delta_out = 32'b00101100000000000000000000000000;
10'd289: delta_out = 32'b00101011111000000000000000000000;
10'd290: delta_out = 32'b00101011110000000000000000000000;
10'd291: delta_out = 32'b00101011101000000000000000000000;
10'd292: delta_out = 32'b00101011100000000000000000000000;
10'd293: delta_out = 32'b00101011011000000000000000000000;
10'd294: delta_out = 32'b00101011010000000000000000000000;
10'd295: delta_out = 32'b00101011001000000000000000000000;
10'd296: delta_out = 32'b00101011000000000000000000000000;
10'd297: delta_out = 32'b00101010111000000000000000000000;
10'd298: delta_out = 32'b00101010110000000000000000000000;
10'd299: delta_out = 32'b00101010101000000000000000000000;
10'd300: delta_out = 32'b00101010100000000000000000000000;
10'd301: delta_out = 32'b00101010011000000000000000000000;
10'd302: delta_out = 32'b00101010010000000000000000000000;
10'd303: delta_out = 32'b00101010001000000000000000000000;
10'd304: delta_out = 32'b00101010000000000000000000000000;
10'd305: delta_out = 32'b00101001111000000000000000000000;
10'd306: delta_out = 32'b00101001110000000000000000000000;
10'd307: delta_out = 32'b00101001101000000000000000000000;
10'd308: delta_out = 32'b00101001100000000000000000000000;
10'd309: delta_out = 32'b00101001011000000000000000000000;
10'd310: delta_out = 32'b00101001010000000000000000000000;
10'd311: delta_out = 32'b00101001001000000000000000000000;
10'd312: delta_out = 32'b00101001000000000000000000000000;
10'd313: delta_out = 32'b00101000111000000000000000000000;
10'd314: delta_out = 32'b00101000110000000000000000000000;
10'd315: delta_out = 32'b00101000101000000000000000000000;
10'd316: delta_out = 32'b00101000100000000000000000000000;
10'd317: delta_out = 32'b00101000011000000000000000000000;
10'd318: delta_out = 32'b00101000010000000000000000000000;
10'd319: delta_out = 32'b00101000001000000000000000000000;
10'd320: delta_out = 32'b00101000000000000000000000000000;
10'd321: delta_out = 32'b00100111111000000000000000000000;
10'd322: delta_out = 32'b00100111110000000000000000000000;
10'd323: delta_out = 32'b00100111101000000000000000000000;
10'd324: delta_out = 32'b00100111100000000000000000000000;
10'd325: delta_out = 32'b00100111011000000000000000000000;
10'd326: delta_out = 32'b00100111010000000000000000000000;
10'd327: delta_out = 32'b00100111001000000000000000000000;
10'd328: delta_out = 32'b00100111000000000000000000000000;
10'd329: delta_out = 32'b00100110111000000000000000000000;
10'd330: delta_out = 32'b00100110110000000000000000000000;
10'd331: delta_out = 32'b00100110101000000000000000000000;
10'd332: delta_out = 32'b00100110100000000000000000000000;
10'd333: delta_out = 32'b00100110011000000000000000000000;
10'd334: delta_out = 32'b00100110010000000000000000000000;
10'd335: delta_out = 32'b00100110001000000000000000000000;
10'd336: delta_out = 32'b00100110000000000000000000000000;
10'd337: delta_out = 32'b00100101111000000000000000000000;
10'd338: delta_out = 32'b00100101110000000000000000000000;
10'd339: delta_out = 32'b00100101101000000000000000000000;
10'd340: delta_out = 32'b00100101100000000000000000000000;
10'd341: delta_out = 32'b00100101011000000000000000000000;
10'd342: delta_out = 32'b00100101010000000000000000000000;
10'd343: delta_out = 32'b00100101001000000000000000000000;
10'd344: delta_out = 32'b00100101000000000000000000000000;
10'd345: delta_out = 32'b00100100111000000000000000000000;
10'd346: delta_out = 32'b00100100110000000000000000000000;
10'd347: delta_out = 32'b00100100101000000000000000000000;
10'd348: delta_out = 32'b00100100100000000000000000000000;
10'd349: delta_out = 32'b00100100011000000000000000000000;
10'd350: delta_out = 32'b00100100010000000000000000000000;
10'd351: delta_out = 32'b00100100001000000000000000000000;
10'd352: delta_out = 32'b00100100000000000000000000000000;
10'd353: delta_out = 32'b00100011111000000000000000000000;
10'd354: delta_out = 32'b00100011110000000000000000000000;
10'd355: delta_out = 32'b00100011101000000000000000000000;
10'd356: delta_out = 32'b00100011100000000000000000000000;
10'd357: delta_out = 32'b00100011011000000000000000000000;
10'd358: delta_out = 32'b00100011010000000000000000000000;
10'd359: delta_out = 32'b00100011001000000000000000000000;
10'd360: delta_out = 32'b00100011000000000000000000000000;
10'd361: delta_out = 32'b00100010111000000000000000000000;
10'd362: delta_out = 32'b00100010110000000000000000000000;
10'd363: delta_out = 32'b00100010101000000000000000000000;
10'd364: delta_out = 32'b00100010100000000000000000000000;
10'd365: delta_out = 32'b00100010011000000000000000000000;
10'd366: delta_out = 32'b00100010010000000000000000000000;
10'd367: delta_out = 32'b00100010001000000000000000000000;
10'd368: delta_out = 32'b00100010000000000000000000000000;
10'd369: delta_out = 32'b00100001111000000000000000000000;
10'd370: delta_out = 32'b00100001110000000000000000000000;
10'd371: delta_out = 32'b00100001101000000000000000000000;
10'd372: delta_out = 32'b00100001100000000000000000000000;
10'd373: delta_out = 32'b00100001011000000000000000000000;
10'd374: delta_out = 32'b00100001010000000000000000000000;
10'd375: delta_out = 32'b00100001001000000000000000000000;
10'd376: delta_out = 32'b00100001000000000000000000000000;
10'd377: delta_out = 32'b00100000111000000000000000000000;
10'd378: delta_out = 32'b00100000110000000000000000000000;
10'd379: delta_out = 32'b00100000101000000000000000000000;
10'd380: delta_out = 32'b00100000100000000000000000000000;
10'd381: delta_out = 32'b00100000011000000000000000000000;
10'd382: delta_out = 32'b00100000010000000000000000000000;
10'd383: delta_out = 32'b00100000001000000000000000000000;
10'd384: delta_out = 32'b00100000000000000000000000000000;
10'd385: delta_out = 32'b00011111111000000000000000000000;
10'd386: delta_out = 32'b00011111110000000000000000000000;
10'd387: delta_out = 32'b00011111101000000000000000000000;
10'd388: delta_out = 32'b00011111100000000000000000000000;
10'd389: delta_out = 32'b00011111011000000000000000000000;
10'd390: delta_out = 32'b00011111010000000000000000000000;
10'd391: delta_out = 32'b00011111001000000000000000000000;
10'd392: delta_out = 32'b00011111000000000000000000000000;
10'd393: delta_out = 32'b00011110111000000000000000000000;
10'd394: delta_out = 32'b00011110110000000000000000000000;
10'd395: delta_out = 32'b00011110101000000000000000000000;
10'd396: delta_out = 32'b00011110100000000000000000000000;
10'd397: delta_out = 32'b00011110011000000000000000000000;
10'd398: delta_out = 32'b00011110010000000000000000000000;
10'd399: delta_out = 32'b00011110001000000000000000000000;
10'd400: delta_out = 32'b00011110000000000000000000000000;
10'd401: delta_out = 32'b00011101111000000000000000000000;
10'd402: delta_out = 32'b00011101110000000000000000000000;
10'd403: delta_out = 32'b00011101101000000000000000000000;
10'd404: delta_out = 32'b00011101100000000000000000000000;
10'd405: delta_out = 32'b00011101011000000000000000000000;
10'd406: delta_out = 32'b00011101010000000000000000000000;
10'd407: delta_out = 32'b00011101001000000000000000000000;
10'd408: delta_out = 32'b00011101000000000000000000000000;
10'd409: delta_out = 32'b00011100111000000000000000000000;
10'd410: delta_out = 32'b00011100110000000000000000000000;
10'd411: delta_out = 32'b00011100101000000000000000000000;
10'd412: delta_out = 32'b00011100100000000000000000000000;
10'd413: delta_out = 32'b00011100011000000000000000000000;
10'd414: delta_out = 32'b00011100010000000000000000000000;
10'd415: delta_out = 32'b00011100001000000000000000000000;
10'd416: delta_out = 32'b00011100000000000000000000000000;
10'd417: delta_out = 32'b00011011111000000000000000000000;
10'd418: delta_out = 32'b00011011110000000000000000000000;
10'd419: delta_out = 32'b00011011101000000000000000000000;
10'd420: delta_out = 32'b00011011100000000000000000000000;
10'd421: delta_out = 32'b00011011011000000000000000000000;
10'd422: delta_out = 32'b00011011010000000000000000000000;
10'd423: delta_out = 32'b00011011001000000000000000000000;
10'd424: delta_out = 32'b00011011000000000000000000000000;
10'd425: delta_out = 32'b00011010111000000000000000000000;
10'd426: delta_out = 32'b00011010110000000000000000000000;
10'd427: delta_out = 32'b00011010101000000000000000000000;
10'd428: delta_out = 32'b00011010100000000000000000000000;
10'd429: delta_out = 32'b00011010011000000000000000000000;
10'd430: delta_out = 32'b00011010010000000000000000000000;
10'd431: delta_out = 32'b00011010001000000000000000000000;
10'd432: delta_out = 32'b00011010000000000000000000000000;
10'd433: delta_out = 32'b00011001111000000000000000000000;
10'd434: delta_out = 32'b00011001110000000000000000000000;
10'd435: delta_out = 32'b00011001101000000000000000000000;
10'd436: delta_out = 32'b00011001100000000000000000000000;
10'd437: delta_out = 32'b00011001011000000000000000000000;
10'd438: delta_out = 32'b00011001010000000000000000000000;
10'd439: delta_out = 32'b00011001001000000000000000000000;
10'd440: delta_out = 32'b00011001000000000000000000000000;
10'd441: delta_out = 32'b00011000111000000000000000000000;
10'd442: delta_out = 32'b00011000110000000000000000000000;
10'd443: delta_out = 32'b00011000101000000000000000000000;
10'd444: delta_out = 32'b00011000100000000000000000000000;
10'd445: delta_out = 32'b00011000011000000000000000000000;
10'd446: delta_out = 32'b00011000010000000000000000000000;
10'd447: delta_out = 32'b00011000001000000000000000000000;
10'd448: delta_out = 32'b00011000000000000000000000000000;
10'd449: delta_out = 32'b00010111111000000000000000000000;
10'd450: delta_out = 32'b00010111110000000000000000000000;
10'd451: delta_out = 32'b00010111101000000000000000000000;
10'd452: delta_out = 32'b00010111100000000000000000000000;
10'd453: delta_out = 32'b00010111011000000000000000000000;
10'd454: delta_out = 32'b00010111010000000000000000000000;
10'd455: delta_out = 32'b00010111001000000000000000000000;
10'd456: delta_out = 32'b00010111000000000000000000000000;
10'd457: delta_out = 32'b00010110111000000000000000000000;
10'd458: delta_out = 32'b00010110110000000000000000000000;
10'd459: delta_out = 32'b00010110101000000000000000000000;
10'd460: delta_out = 32'b00010110100000000000000000000000;
10'd461: delta_out = 32'b00010110011000000000000000000000;
10'd462: delta_out = 32'b00010110010000000000000000000000;
10'd463: delta_out = 32'b00010110001000000000000000000000;
10'd464: delta_out = 32'b00010110000000000000000000000000;
10'd465: delta_out = 32'b00010101111000000000000000000000;
10'd466: delta_out = 32'b00010101110000000000000000000000;
10'd467: delta_out = 32'b00010101101000000000000000000000;
10'd468: delta_out = 32'b00010101100000000000000000000000;
10'd469: delta_out = 32'b00010101011000000000000000000000;
10'd470: delta_out = 32'b00010101010000000000000000000000;
10'd471: delta_out = 32'b00010101001000000000000000000000;
10'd472: delta_out = 32'b00010101000000000000000000000000;
10'd473: delta_out = 32'b00010100111000000000000000000000;
10'd474: delta_out = 32'b00010100110000000000000000000000;
10'd475: delta_out = 32'b00010100101000000000000000000000;
10'd476: delta_out = 32'b00010100100000000000000000000000;
10'd477: delta_out = 32'b00010100011000000000000000000000;
10'd478: delta_out = 32'b00010100010000000000000000000000;
10'd479: delta_out = 32'b00010100001000000000000000000000;
10'd480: delta_out = 32'b00010100000000000000000000000000;
10'd481: delta_out = 32'b00010011111000000000000000000000;
10'd482: delta_out = 32'b00010011110000000000000000000000;
10'd483: delta_out = 32'b00010011101000000000000000000000;
10'd484: delta_out = 32'b00010011100000000000000000000000;
10'd485: delta_out = 32'b00010011011000000000000000000000;
10'd486: delta_out = 32'b00010011010000000000000000000000;
10'd487: delta_out = 32'b00010011001000000000000000000000;
10'd488: delta_out = 32'b00010011000000000000000000000000;
10'd489: delta_out = 32'b00010010111000000000000000000000;
10'd490: delta_out = 32'b00010010110000000000000000000000;
10'd491: delta_out = 32'b00010010101000000000000000000000;
10'd492: delta_out = 32'b00010010100000000000000000000000;
10'd493: delta_out = 32'b00010010011000000000000000000000;
10'd494: delta_out = 32'b00010010010000000000000000000000;
10'd495: delta_out = 32'b00010010001000000000000000000000;
10'd496: delta_out = 32'b00010010000000000000000000000000;
10'd497: delta_out = 32'b00010001111000000000000000000000;
10'd498: delta_out = 32'b00010001110000000000000000000000;
10'd499: delta_out = 32'b00010001101000000000000000000000;
10'd500: delta_out = 32'b00010001100000000000000000000000;
10'd501: delta_out = 32'b00010001011000000000000000000000;
10'd502: delta_out = 32'b00010001010000000000000000000000;
10'd503: delta_out = 32'b00010001001000000000000000000000;
10'd504: delta_out = 32'b00010001000000000000000000000000;
10'd505: delta_out = 32'b00010000111000000000000000000000;
10'd506: delta_out = 32'b00010000110000000000000000000000;
10'd507: delta_out = 32'b00010000101000000000000000000000;
10'd508: delta_out = 32'b00010000100000000000000000000000;
10'd509: delta_out = 32'b00010000011000000000000000000000;
10'd510: delta_out = 32'b00010000010000000000000000000000;
10'd511: delta_out = 32'b00010000001000000000000000000000;
10'd512: delta_out = 32'b00010000000000000000000000000000;
10'd513: delta_out = 32'b00001111111000000000000000000000;
endcase
end
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_transmitFIFODataIn (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 8: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 8: 0] data_out;
wire [ 8: 0] out_port;
wire [ 8: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {9 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[8 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
// HPS.v
// Generated using ACDS version 14.0 200 at 2018.12.24.16:01:26
`timescale 1 ps / 1 ps
module HPS (
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
inout wire hps_io_hps_io_gpio_inst_LOANIO01, // hps_io.hps_io_gpio_inst_LOANIO01
inout wire hps_io_hps_io_gpio_inst_LOANIO02, // .hps_io_gpio_inst_LOANIO02
inout wire hps_io_hps_io_gpio_inst_LOANIO03, // .hps_io_gpio_inst_LOANIO03
inout wire hps_io_hps_io_gpio_inst_LOANIO04, // .hps_io_gpio_inst_LOANIO04
inout wire hps_io_hps_io_gpio_inst_LOANIO05, // .hps_io_gpio_inst_LOANIO05
inout wire hps_io_hps_io_gpio_inst_LOANIO06, // .hps_io_gpio_inst_LOANIO06
inout wire hps_io_hps_io_gpio_inst_LOANIO07, // .hps_io_gpio_inst_LOANIO07
inout wire hps_io_hps_io_gpio_inst_LOANIO08, // .hps_io_gpio_inst_LOANIO08
inout wire hps_io_hps_io_gpio_inst_LOANIO10, // .hps_io_gpio_inst_LOANIO10
inout wire hps_io_hps_io_gpio_inst_LOANIO11, // .hps_io_gpio_inst_LOANIO11
inout wire hps_io_hps_io_gpio_inst_LOANIO12, // .hps_io_gpio_inst_LOANIO12
inout wire hps_io_hps_io_gpio_inst_LOANIO13, // .hps_io_gpio_inst_LOANIO13
inout wire hps_io_hps_io_gpio_inst_LOANIO42, // .hps_io_gpio_inst_LOANIO42
inout wire hps_io_hps_io_gpio_inst_LOANIO49, // .hps_io_gpio_inst_LOANIO49
inout wire hps_io_hps_io_gpio_inst_LOANIO50, // .hps_io_gpio_inst_LOANIO50
output wire [66:0] loanio_in, // loanio.in
input wire [66:0] loanio_out, // .out
input wire [66:0] loanio_oe, // .oe
input wire [31:0] hps_gp_gp_in, // hps_gp.gp_in
output wire [31:0] hps_gp_gp_out // .gp_out
);
HPS_hps_0 #(
.F2S_Width (0),
.S2F_Width (0)
) hps_0 (
.h2f_loan_in (loanio_in), // h2f_loan_io.in
.h2f_loan_out (loanio_out), // .out
.h2f_loan_oe (loanio_oe), // .oe
.h2f_gp_in (hps_gp_gp_in), // h2f_gp.gp_in
.h2f_gp_out (hps_gp_gp_out), // .gp_out
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_gpio_inst_LOANIO01 (hps_io_hps_io_gpio_inst_LOANIO01), // hps_io.hps_io_gpio_inst_LOANIO01
.hps_io_gpio_inst_LOANIO02 (hps_io_hps_io_gpio_inst_LOANIO02), // .hps_io_gpio_inst_LOANIO02
.hps_io_gpio_inst_LOANIO03 (hps_io_hps_io_gpio_inst_LOANIO03), // .hps_io_gpio_inst_LOANIO03
.hps_io_gpio_inst_LOANIO04 (hps_io_hps_io_gpio_inst_LOANIO04), // .hps_io_gpio_inst_LOANIO04
.hps_io_gpio_inst_LOANIO05 (hps_io_hps_io_gpio_inst_LOANIO05), // .hps_io_gpio_inst_LOANIO05
.hps_io_gpio_inst_LOANIO06 (hps_io_hps_io_gpio_inst_LOANIO06), // .hps_io_gpio_inst_LOANIO06
.hps_io_gpio_inst_LOANIO07 (hps_io_hps_io_gpio_inst_LOANIO07), // .hps_io_gpio_inst_LOANIO07
.hps_io_gpio_inst_LOANIO08 (hps_io_hps_io_gpio_inst_LOANIO08), // .hps_io_gpio_inst_LOANIO08
.hps_io_gpio_inst_LOANIO10 (hps_io_hps_io_gpio_inst_LOANIO10), // .hps_io_gpio_inst_LOANIO10
.hps_io_gpio_inst_LOANIO11 (hps_io_hps_io_gpio_inst_LOANIO11), // .hps_io_gpio_inst_LOANIO11
.hps_io_gpio_inst_LOANIO12 (hps_io_hps_io_gpio_inst_LOANIO12), // .hps_io_gpio_inst_LOANIO12
.hps_io_gpio_inst_LOANIO13 (hps_io_hps_io_gpio_inst_LOANIO13), // .hps_io_gpio_inst_LOANIO13
.hps_io_gpio_inst_LOANIO42 (hps_io_hps_io_gpio_inst_LOANIO42), // .hps_io_gpio_inst_LOANIO42
.hps_io_gpio_inst_LOANIO49 (hps_io_hps_io_gpio_inst_LOANIO49), // .hps_io_gpio_inst_LOANIO49
.hps_io_gpio_inst_LOANIO50 (hps_io_hps_io_gpio_inst_LOANIO50), // .hps_io_gpio_inst_LOANIO50
.h2f_rst_n () // h2f_reset.reset_n
);
endmodule
|
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_divide
// ============================================================
// File Name: DIV.v
// Megafunction Name(s):
// lpm_divide
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module DIV (
aclr,
clock,
denom,
numer,
quotient,
remain);
input aclr;
input clock;
input [3:0] denom;
input [9:0] numer;
output [9:0] quotient;
output [3:0] remain;
wire [9:0] sub_wire0;
wire [3:0] sub_wire1;
wire [9:0] quotient = sub_wire0[9:0];
wire [3:0] remain = sub_wire1[3:0];
lpm_divide lpm_divide_component (
.denom (denom),
.aclr (aclr),
.clock (clock),
.numer (numer),
.quotient (sub_wire0),
.remain (sub_wire1),
.clken (1'b1));
defparam
lpm_divide_component.lpm_drepresentation = "UNSIGNED",
lpm_divide_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
lpm_divide_component.lpm_nrepresentation = "UNSIGNED",
lpm_divide_component.lpm_pipeline = 1,
lpm_divide_component.lpm_type = "LPM_DIVIDE",
lpm_divide_component.lpm_widthd = 4,
lpm_divide_component.lpm_widthn = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "10"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: denom 0 0 4 0 INPUT NODEFVAL denom[3..0]
// Retrieval info: USED_PORT: numer 0 0 10 0 INPUT NODEFVAL numer[9..0]
// Retrieval info: USED_PORT: quotient 0 0 10 0 OUTPUT NODEFVAL quotient[9..0]
// Retrieval info: USED_PORT: remain 0 0 4 0 OUTPUT NODEFVAL remain[3..0]
// Retrieval info: CONNECT: @numer 0 0 10 0 numer 0 0 10 0
// Retrieval info: CONNECT: @denom 0 0 4 0 denom 0 0 4 0
// Retrieval info: CONNECT: quotient 0 0 10 0 @quotient 0 0 10 0
// Retrieval info: CONNECT: remain 0 0 4 0 @remain 0 0 4 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PR_TB_V
`define SKY130_FD_SC_LP__UDP_DFF_PR_TB_V
/**
* udp_dff$PR: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dff_pr.v"
module top();
// Inputs are registered
reg D;
reg RESET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 D = 1'b1;
#80 RESET = 1'b1;
#100 D = 1'b0;
#120 RESET = 1'b0;
#140 RESET = 1'b1;
#160 D = 1'b1;
#180 RESET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__udp_dff$PR dut (.D(D), .RESET(RESET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PR_TB_V
|
// iverilog -y .. -o tb-Fork2.vvp tb-Fork2.v
// vvp tb-Fork2.vvp
`timescale 1ns/1ns
module tb;
localparam W = 8;
localparam CYC = 10;
reg clk, rst;
reg idata_vld;
wire idata_rdy;
reg [W-1:0] idata;
wire odata0_vld, odata1_vld;
reg odata0_rdy, odata1_rdy;
wire [W-1:0] odata0, odata1;
Fork2#(W) dut(clk, rst, idata_vld, idata_rdy, idata, odata0_vld, odata0_rdy, odata0, odata1_vld, odata1_rdy, odata1);
initial begin
#0;
rst = 1'b1;
#(10*CYC+CYC/3);
rst = 1'b0;
end
initial begin
#0;
clk = 1'b0;
#(CYC);
forever begin
clk = 1'b1;
#(CYC/2);
clk = 1'b0;
#(CYC-CYC/2);
end
end
task wait_reset_release;
begin
@(posedge clk);
while (rst) @(posedge clk);
end
endtask
event idata_update_event;
reg idata_update_ctrl;
initial begin :ivld
reg [31:0] rngseed, rnum;
integer n;
#0;
idata_vld = 1'b0;
wait_reset_release;
rngseed = 32'h01234567;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
idata_vld <= 1'b0;
idata_update_ctrl = 1'b0;
-> idata_update_event;
repeat (n) @(posedge clk);
end
idata_vld <= 1'b1;
idata_update_ctrl = 1'b1;
-> idata_update_event;
@(posedge clk);
while (~idata_rdy) @(posedge clk);
end
end
initial begin :idat
reg [31:0] rngseed, rnum;
#0;
idata = {W{1'b0}};
rngseed = 32'h12345678;
forever begin
@(idata_update_event);
if (idata_update_ctrl) begin
rnum = $random(rngseed);
idata <= rnum[W-1:0];
end else begin
idata <= {W{1'bx}};
end
end
end
initial begin :ordy0
reg [31:0] rngseed, rnum;
integer n;
#0;
odata0_rdy = 1'b0;
wait_reset_release;
rngseed = 32'h23456789;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
odata0_rdy <= 1'b0;
repeat (n) @(posedge clk);
end
odata0_rdy <= 1'b1;
@(posedge clk);
end
end
initial begin :ordy1
reg [31:0] rngseed, rnum;
integer n;
#0;
odata1_rdy = 1'b0;
wait_reset_release;
rngseed = 32'h3456789a;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
odata1_rdy <= 1'b0;
repeat (n) @(posedge clk);
end
odata1_rdy <= 1'b1;
@(posedge clk);
end
end
initial begin
$dumpfile("tb-Fork2.vcd");
$dumpvars(0, dut);
#(1000*CYC);
$display("Simulated 1000 cycles.");
$finish;
end
initial begin :verify_idata
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h12345678;
forever begin
if (idata_vld & idata_rdy) begin
rnum = $random(rngseed);
if (idata !== rnum[W-1:0]) begin
$display("%0t: Error: idata %h != %h", $time, idata, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, idata);
end
@(posedge clk);
end
end
initial begin :verify_odata0
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h12345678;
forever begin
if (odata0_vld & odata0_rdy) begin
rnum = $random(rngseed);
if (odata0 !== rnum[W-1:0]) begin
$display("%0t: Error: odata0 %h != %h", $time, odata0, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, odata0);
end
@(posedge clk);
end
end
initial begin :verify_odata1
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h12345678;
forever begin
if (odata1_vld & odata1_rdy) begin
rnum = $random(rngseed);
if (odata1 !== rnum[W-1:0]) begin
$display("%0t: Error: odata1 %h != %h", $time, odata1, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, odata1);
end
@(posedge clk);
end
end
endmodule
|
/*
i0 i1 i2 i3
1 [ 29, 55, 74, 84 ] i0
2 [ 74, 74, 0 , -74 ] i1
3 [ 84, -29, -74, 55 ] ? i2
4 [ 55, -84, 74, -29 ] i3
*/
module dst(
clk,
rst,
inverse,
i_0,
i_1,
i_2,
i_3,
o_0,
o_1,
o_2,
o_3
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk;
input rst;
input inverse;
input signed [18:0] i_0;
input signed [18:0] i_1;
input signed [18:0] i_2;
input signed [18:0] i_3;
output reg signed [27:0] o_0;
output reg signed [27:0] o_1;
output reg signed [27:0] o_2;
output reg signed [27:0] o_3;
// **********************************************
//
// Wire DECLARATION
//
// **********************************************
wire signed [26:0] w0_00;
wire signed [26:0] w0_01;
wire signed [26:0] w0_10;
wire signed [26:0] w0_11;
wire signed [26:0] w0_20;
wire signed [26:0] w0_21;
wire signed [26:0] w0_30;
wire signed [26:0] w0_31;
wire signed [26:0] w1_00;
wire signed [26:0] w1_01;
wire signed [26:0] w1_10;
wire signed [26:0] w1_11;
wire signed [26:0] w1_20;
wire signed [26:0] w1_21;
wire signed [26:0] w1_30;
wire signed [26:0] w1_31;
// **********************************************
//
// REG DECLARATION
//
// **********************************************
reg signed [26:0] o_00;
reg signed [26:0] o_01;
reg signed [26:0] o_10;
reg signed [26:0] o_11;
reg signed [26:0] o_20;
reg signed [26:0] o_21;
reg signed [26:0] o_30;
reg signed [26:0] o_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign w0_00=29*i_0+55*i_1;
assign w0_01=74*i_2+84*i_3;
assign w0_10=74*i_0+74*i_1;
assign w0_11= -74*i_3;
assign w0_20=84*i_0-29*i_1;
assign w0_21=-74*i_2+55*i_3;
assign w0_30=55*i_0-84*i_1;
assign w0_31=74*i_2-29*i_3;
assign w1_00=29*i_0+74*i_1;
assign w1_01=84*i_2+55*i_3;
assign w1_10=55*i_0+74*i_1;
assign w1_11= -29*i_2-84*i_3;
assign w1_20=74*i_0;
assign w1_21=-74*i_2+74*i_3;
assign w1_30=84*i_0-74*i_1;
assign w1_31=55*i_2-29*i_3;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @(posedge clk or negedge rst)
if(!rst) begin
o_00<='b0; o_01<='b0;
o_10<='b0; o_11<='b0;
o_20<='b0; o_21<='b0;
o_30<='b0; o_31<='b0;
end
else
if(inverse) begin
o_00<=w1_00; o_01<=w1_01;
o_10<=w1_10; o_11<=w1_11;
o_20<=w1_20; o_21<=w1_21;
o_30<=w1_30; o_31<=w1_31;
end
else begin
o_00<=w0_00; o_01<=w0_01;
o_10<=w0_10; o_11<=w0_11;
o_20<=w0_20; o_21<=w0_21;
o_30<=w0_30; o_31<=w0_31;
end
always @(posedge clk or negedge rst)
if(!rst) begin
o_0<='b0; o_1<='b0;
o_2<='b0; o_3<='b0;
end
else begin
o_0<=o_00+o_01;o_1<=o_10+o_11;
o_2<=o_20+o_21;o_3<=o_30+o_31;
end
endmodule
|
// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_sync_clock_converter
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_clock_converter_v2_1_8_axic_sync_clock_converter # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex6",
parameter integer C_PAYLOAD_WIDTH = 32,
parameter integer C_S_ACLK_RATIO = 1,
parameter integer C_M_ACLK_RATIO = 1 ,
parameter integer C_MODE = 0 // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SAMPLE_CYCLE_EARLY,
input wire SAMPLE_CYCLE,
// Slave side
input wire S_ACLK,
input wire S_ARESETN,
input wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,
input wire S_VALID,
output wire S_READY,
// Master side
input wire M_ACLK,
input wire M_ARESETN,
output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,
output wire M_VALID,
input wire M_READY
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam [1:0] ZERO = 2'b10;
localparam [1:0] ONE = 2'b11;
localparam [1:0] TWO = 2'b01;
localparam [1:0] INIT = 2'b00;
localparam integer P_LIGHT_WT = 0;
localparam integer P_FULLY_REG = 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru
assign M_PAYLOAD = S_PAYLOAD;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end else begin : gen_sync_clock_converter
wire s_sample_cycle;
wire s_sample_cycle_early;
wire m_sample_cycle;
wire m_sample_cycle_early;
wire slow_aclk;
wire slow_areset;
wire s_areset_r;
wire m_areset_r;
reg s_tready_r;
wire s_tready_ns;
reg m_tvalid_r;
wire m_tvalid_ns;
reg [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;
reg [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;
wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns;
wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns;
reg m_tready_hold;
wire m_tready_sample;
wire load_tpayload;
wire load_tstorage;
wire load_tpayload_from_tstorage;
reg [1:0] state;
reg [1:0] next_state;
reg s_aresetn_r = 1'b0; // Reset delay register
always @(posedge S_ACLK) begin
if (~S_ARESETN | ~M_ARESETN) begin
s_aresetn_r <= 1'b0;
end else begin
s_aresetn_r <= S_ARESETN & M_ARESETN;
end
end
assign s_areset_r = ~s_aresetn_r;
reg m_aresetn_r = 1'b0; // Reset delay register
always @(posedge M_ACLK) begin
if (~S_ARESETN | ~M_ARESETN) begin
m_aresetn_r <= 1'b0;
end else begin
m_aresetn_r <= S_ARESETN & M_ARESETN;
end
end
assign m_areset_r = ~m_aresetn_r;
if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi
assign slow_aclk = M_ACLK;
end else begin : gen_slowclk_si
assign slow_aclk = S_ACLK;
end
assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;
assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;
assign s_sample_cycle = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;
assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;
assign m_sample_cycle = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;
// Output flop for S_READY, value is encoded into state machine.
assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];
always @(posedge S_ACLK) begin
if (s_areset_r) begin
s_tready_r <= 1'b0;
end
else begin
s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;
end
end
assign S_READY = s_tready_r;
// Output flop for M_VALID
assign m_tvalid_ns = next_state[0];
always @(posedge M_ACLK) begin
if (m_areset_r) begin
m_tvalid_r <= 1'b0;
end
else begin
m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;
end
end
assign M_VALID = m_tvalid_r;
// Hold register for M_READY when M_ACLK is fast.
always @(posedge M_ACLK) begin
if (m_areset_r) begin
m_tready_hold <= 1'b0;
end
else begin
m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;
end
end
assign m_tready_sample = (M_READY ) | m_tready_hold;
// Output/storage flops for PAYLOAD
assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :
load_tpayload_from_tstorage ? m_tstorage_r :
S_PAYLOAD;
assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;
always @(posedge slow_aclk) begin
m_tpayload_r <= m_tpayload_ns;
m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;
end
assign M_PAYLOAD = m_tpayload_r;
// load logic
assign load_tstorage = C_MODE && (state != TWO);
assign load_tpayload = m_tready_sample || (state == ZERO);
assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;
// State machine
always @(posedge slow_aclk) begin
state <= next_state;
end
always @* begin
if (slow_areset) begin
next_state = INIT;
end else begin
case (state)
INIT: begin
next_state = ZERO;
end
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
next_state = C_MODE ? ONE : TWO; // Push from empty
end
else begin
next_state = ZERO;
end
end
// One transaction stored locally
ONE: begin
if (C_MODE == 0) begin
next_state = TWO; // State ONE is inaccessible when C_MODE=0
end
else if (m_tready_sample & ~S_VALID) begin
next_state = ZERO; // Read out one so move to ZERO
end
else if (~m_tready_sample & S_VALID) begin
next_state = TWO; // Got another one so move to TWO
end
else begin
next_state = ONE;
end
end
// Storage registers full
TWO: begin
if (m_tready_sample) begin
next_state = C_MODE ? ONE : ZERO; // Pop from full
end
else begin
next_state = TWO;
end
end
endcase // case (state)
end
end
end // gen_sync_clock_converter
endgenerate
endmodule
`default_nettype wire
|
////////////////////////////////////////////////////////////////////////////////
//
// PS2-to-SAM Mouse
// (C) 2016 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
////////////////////////////////////////////////////////////////////////////////
module mouse
(
input clk_sys,
input ce_6mp,
input reset,
input [24:0] ps2_mouse,
input rd,
output [4:0] dout
);
assign dout = {1'b1, data};
reg [3:0] button;
reg [11:0] dx,ldx;
reg [11:0] dy,ldy;
wire [11:0] mdx = {{4{ps2_mouse[4]}},ps2_mouse[15:8]};
wire [11:0] mdy = {{4{ps2_mouse[5]}},ps2_mouse[23:16]};
wire [11:0] newdx = dx + mdx;
wire [11:0] newdy = dy + mdy;
reg [3:0] queue;
reg [3:0] data;
always @* begin
case({~rd, queue})
2: data = ~button;
3: data = ldy[11:8];
4: data = ldy[7:4];
5: data = ldy[3:0];
6: data = ldx[11:8];
7: data = ldx[7:4];
8: data = ldx[3:0];
default: data = 'hF;
endcase
end
always @(posedge clk_sys) begin
reg old_rd;
reg [7:0] timout;
reg old_stb;
if(reset) begin
dx <= 0;
dy <= 0;
button <= 0;
queue <= 0;
timout <= 0;
old_rd <= 0;
end else begin
old_rd <= rd;
if(old_rd & ~rd) queue <= (queue == 8) ? 4'd1 : queue + 1'd1;
if(~old_rd & rd) begin
timout <= 0;
if(queue == 2) begin
ldx <= dx;
ldy <= dy;
end
if(queue == 8) begin
dx <= dx - ldx;
dy <= dy - ldy;
end
end else begin
old_stb <= ps2_mouse[24];
if(old_stb != ps2_mouse[24]) begin
button <= ps2_mouse[2:0];
dx <= mdx[11] ? ((dx[11] & ~newdx[11]) ? 12'h800 : newdx) : ((~dx[11] & newdx[11]) ? 12'h7FF : newdx);
dy <= mdy[11] ? ((dy[11] & ~newdy[11]) ? 12'h800 : newdy) : ((~dy[11] & newdy[11]) ? 12'h7FF : newdy);
end
if(ce_6mp) begin
if(timout < 181) timout <= timout + 1'd1;
if(timout == 180) queue <= 0;
end
end
end
end
endmodule
|
module microfono_TB;
reg reset, clk;
reg micData;
microfono uut(.reset(reset),.micData(micData),.clk(clk));
always
begin
clk =1'b1;
#2;
clk=1'b0;
#2;
end
initial
begin
reset =1'b1;
#10000;
reset =1'b0;
end
/*initial
begin
rd = 1'b0;
wr = 1'b0;
#10000 wr = 1'b1;
#150000 wr = 1'b0;
#15010 rd = 1'b1;
end
*/
initial begin
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
end
initial begin: TEST_CASE
$dumpfile("microfono_TB.vcd");
$dumpvars(-1, uut);
#(1000000) $finish;
end
endmodule //
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:08:01 02/19/2016
// Design Name: tp_final
// Module Name: /home/poche002/Desktop/ArqComp/Trabajo_final/arquitectura_tpf/tp_final_tb.v
// Project Name: arquitectura_tpf
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: tp_final
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tp_final_tb;
// Inputs
reg clk;
reg reset;
reg rx;
// Outputs
wire tx;
//Para test
//wire [1:0] op;
//wire ena_pip_test;
//wire [31:0] pc_PC_out_test;
//wire [31:0] instruction_IF_test;
//wire [31:0] write_data_WB_out_test;
//wire stallF_HZ_out_test;
//wire [2:0] state_reg_test;
//wire rx_empty_test;
//wire rx_done_tick_test;
//wire [7:0] rx_data_out_test;
//wire [7:0] write_data_test;
//wire [3:0] byteN_test;
//wire [7:0] reg_0;
//wire [7:0] reg_1;
//wire [7:0] reg_2;
//wire [7:0] reg_3;
//wire tick_test;
integer ciclo;
//wire [7:0] fifo_data;
//wire fifo_full;
//wire [1:0] state_test;
wire [7:0] led;
// Instantiate the Unit Under Test (UUT)
tp_final uut (
.clk(clk),
.reset(reset),
.rx(rx),
.tx(tx),
.led(led)
//.op(op),
//.ena_pip_test(ena_pip_test),
//.pc_incrementado_PC_out_test(pc_PC_out_test),
//.instruction_IF_test(instruction_IF_test),
//.write_data_WB_out_test(write_data_WB_out_test)
//.stallF_HZ_out_test(stallF_HZ_out_test)
//.state_reg_test(state_reg_test)
//.rx_empty_test(rx_empty_test),
//.btn_read_reg_test(btn_read_reg_test),
//.write_data_test(write_data_test),
//.byteN_test(byteN_test)
//.reg_0(reg_0),
//.reg_1(reg_1),
//.reg_2(reg_2),
//.reg_3(reg_3),
//.rx_done_tick_test(rx_done_tick_test),
//.rx_data_out_test(rx_data_out_test),
//.tick_test(tick_test),
//.fifo_data(fifo_data),
//.fifo_full(fifo_full),
//.state_test(state_test)
);
initial begin
// Initialize Inputs
clk = 0;
rx = 1;
reset = 0;
ciclo= 0;
// Wait 100 ns for global reset to finish
#1 reset = 1;
#1 reset = 0;
//1 byte 0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
//0000_0011
/*
#64 rx=0;
#64 rx=1;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
*/
//#10000 reset = 1'b1;
//#2 reset = 1'b0;
// Add stimulus here
end
always
begin
#1
clk=~clk;
#1
clk=~clk;
ciclo = ciclo + 1;
end
endmodule
|
`include "bsg_cache.vh"
module testbench();
import bsg_cache_pkg::*;
// clock/reset
bit clk;
bit reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(20)
) cg (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(10)
) rg (
.clk_i(clk)
,.async_reset_o(reset)
);
// parameters
localparam addr_width_p = 30;
localparam data_width_p = 32;
localparam block_size_in_words_p = 8;
localparam sets_p = 128;
localparam ways_p = 8;
localparam mem_size_p = 2**17;
integer status;
integer wave;
string checker;
initial begin
status = $value$plusargs("wave=%d",wave);
status = $value$plusargs("checker=%s",checker);
$display("checker=%s", checker);
if (wave) $vcdpluson;
end
`declare_bsg_cache_pkt_s(addr_width_p,data_width_p);
`declare_bsg_cache_dma_pkt_s(addr_width_p);
bsg_cache_pkt_s cache_pkt;
logic v_li;
logic ready_lo;
logic [data_width_p-1:0] cache_data_lo;
logic v_lo;
logic yumi_li;
bsg_cache_dma_pkt_s dma_pkt;
logic dma_pkt_v_lo;
logic dma_pkt_yumi_li;
logic [data_width_p-1:0] dma_data_li;
logic dma_data_v_li;
logic dma_data_ready_lo;
logic [data_width_p-1:0] dma_data_lo;
logic dma_data_v_lo;
logic dma_data_yumi_li;
// DUT
bsg_cache #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
,.amo_support_p(amo_support_level_arithmetic_lp)
) DUT (
.clk_i(clk)
,.reset_i(reset)
,.cache_pkt_i(cache_pkt)
,.v_i(v_li)
,.ready_o(ready_lo)
,.data_o(cache_data_lo)
,.v_o(v_lo)
,.yumi_i(yumi_li)
,.dma_pkt_o(dma_pkt)
,.dma_pkt_v_o(dma_pkt_v_lo)
,.dma_pkt_yumi_i(dma_pkt_yumi_li)
,.dma_data_i(dma_data_li)
,.dma_data_v_i(dma_data_v_li)
,.dma_data_ready_o(dma_data_ready_lo)
,.dma_data_o(dma_data_lo)
,.dma_data_v_o(dma_data_v_lo)
,.dma_data_yumi_i(dma_data_yumi_li)
,.v_we_o()
);
// random yumi generator
bsg_nonsynth_random_yumi_gen #(
.yumi_min_delay_p(`YUMI_MIN_DELAY_P)
,.yumi_max_delay_p(`YUMI_MAX_DELAY_P)
) yumi_gen (
.clk_i(clk)
,.reset_i(reset)
,.v_i(v_lo)
,.yumi_o(yumi_li)
);
// DMA model
bsg_nonsynth_dma_model #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.els_p(mem_size_p)
,.read_delay_p(`DMA_READ_DELAY_P)
,.write_delay_p(`DMA_WRITE_DELAY_P)
,.dma_req_delay_p(`DMA_REQ_DELAY_P)
,.dma_data_delay_p(`DMA_DATA_DELAY_P)
) dma0 (
.clk_i(clk)
,.reset_i(reset)
,.dma_pkt_i(dma_pkt)
,.dma_pkt_v_i(dma_pkt_v_lo)
,.dma_pkt_yumi_o(dma_pkt_yumi_li)
,.dma_data_o(dma_data_li)
,.dma_data_v_o(dma_data_v_li)
,.dma_data_ready_i(dma_data_ready_lo)
,.dma_data_i(dma_data_lo)
,.dma_data_v_i(dma_data_v_lo)
,.dma_data_yumi_o(dma_data_yumi_li)
);
// trace replay
localparam rom_addr_width_lp = 26;
localparam ring_width_lp = `bsg_cache_pkt_width(addr_width_p,data_width_p);
logic [rom_addr_width_lp-1:0] trace_rom_addr;
logic [ring_width_lp+4-1:0] trace_rom_data;
logic tr_v_lo;
logic [ring_width_lp-1:0] tr_data_lo;
logic tr_yumi_li;
logic done;
bsg_trace_replay #(
.payload_width_p(ring_width_lp)
,.rom_addr_width_p(rom_addr_width_lp)
) trace_replay (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(trace_rom_addr)
,.rom_data_i(trace_rom_data)
,.done_o(done)
,.error_o()
);
bsg_nonsynth_test_rom #(
.filename_p("trace.tr")
,.data_width_p(ring_width_lp+4)
,.addr_width_p(rom_addr_width_lp)
) trom (
.addr_i(trace_rom_addr)
,.data_o(trace_rom_data)
);
assign cache_pkt = tr_data_lo;
assign v_li = tr_v_lo;
assign tr_yumi_li = tr_v_lo & ready_lo;
// basic checker is used to check correctness
bind bsg_cache basic_checker_32 #(
.data_width_p(data_width_p)
,.addr_width_p(addr_width_p)
,.mem_size_p($root.testbench.mem_size_p)
) basic_check (
.*
,.en_i($root.testbench.checker == "basic")
);
// wait for all responses to be received.
integer sent_r, recv_r;
bind DUT lru_stats #(
.ways_p(ways_p)
) lru_stats (
.clk_i(DUT.clk_i)
,.reset_i(DUT.reset_i)
,.stat_mem_v_i(DUT.miss_stat_mem_v_lo)
,.stat_mem_w_i(DUT.miss_stat_mem_w_lo)
,.chosen_way_i(DUT.chosen_way_lo)
);
always_ff @ (posedge clk) begin
if (reset) begin
sent_r <= '0;
recv_r <= '0;
end
else begin
if (v_li & ready_lo)
sent_r <= sent_r + 1;
if (v_lo & yumi_li)
recv_r <= recv_r + 1;
end
end
initial begin
wait(done & (sent_r == recv_r));
$display("[BSG_FINISH] Test Successful.");
#500;
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:36:46 09/06/2015
// Design Name:
// Module Name: FPU_Multiplication_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_Multiplication_Function
//SINGLE PRECISION PARAMETERS
/*# (parameter W = 32, parameter EW = 8, parameter SW = 23) // */
//DOUBLE PRECISION PARAMETERS
# (parameter W = 64, parameter EW = 11, parameter SW = 52) // */
(
input wire clk,
input wire rst,
input wire beg_FSM,
input wire ack_FSM,
input wire [W-1:0] Data_MX,
input wire [W-1:0] Data_MY,
input wire [1:0] round_mode,
output wire overflow_flag,
output wire underflow_flag,
output wire ready,
output wire [W-1:0] final_result_ieee
);
//GENERAL
wire rst_int; //**
//FSM_load_signals
wire FSM_first_phase_load; //**
wire FSM_load_first_step; /*Zero flag, Exp operation underflow, Sgf operation first reg,
sign result reg*/
wire FSM_exp_operation_load_result; //Exp operation result,
wire FSM_load_second_step; //Exp operation Overflow, Sgf operation second reg
wire FSM_barrel_shifter_load;
wire FSM_adder_round_norm_load;
wire FSM_final_result_load;
//ZERO FLAG
//Op_MX;
//Op_MY
wire zero_flag;
wire FSM_Shift_Value;
wire FSM_selector_C;
//FIRST PHASE
wire [W-1:0] Op_MX;
wire [W-1:0] Op_MY;
//Mux S-> exp_operation OPER_A_i//////////
wire FSM_selector_A;
//D0=Op_MX[W-2:W-EW-1]
//D1=exp_oper_result
wire [EW:0] S_Oper_A_exp;
//Mux S-> exp_operation OPER_B_i//////////
wire [1:0] FSM_selector_B;
//D0=Op_MY[W-2:W-EW-1]
//D1=LZA_output
//D2=1
wire [EW-1:0] S_Oper_B_exp;
///////////exp_operation///////////////////////////
wire FSM_exp_operation_A_S;
//oper_A= S_Oper_A_exp
//oper_B= S_Oper_B_exp
wire [EW:0] exp_oper_result;
//Sgf operation//////////////////
//Op_A={1'b1, Op_MX[SW-1:0]}
//Op_B={1'b1, Op_MY[SW-1:0]}
wire [2*SW+1:0] P_Sgf;
wire[SW:0] significand;
wire[SW-1:0] non_significand;
//Sign Operation
wire sign_final_result;
//barrel shifter multiplexers
wire [SW:0] S_Data_Shift;
//barrel shifter
wire [SW:0] Sgf_normalized_result;
//adder rounding
wire FSM_add_overflow_flag;
//Oper_A_i=norm result
//Oper_B_i=1
wire [SW:0] Add_result;
//round decoder
wire FSM_round_flag;
//Selecto moltiplexers
wire selector_A;
wire [1:0] selector_B;
wire load_b;
wire selector_C;
//Barrel shifter multiplexer
/////////////////////////////////////////FSM////////////////////////////////////////////
FSM_Mult_Function FS_Module (
.clk(clk), //**
.rst(rst), //**
.beg_FSM(beg_FSM), //**
.ack_FSM(ack_FSM), //**
.zero_flag_i(zero_flag),
.Mult_shift_i(P_Sgf[2*SW+1]),
.round_flag_i(FSM_round_flag),
.Add_Overflow_i(FSM_add_overflow_flag),
.load_0_o(FSM_first_phase_load),
.load_1_o(FSM_load_first_step),
.load_2_o(FSM_exp_operation_load_result),
.load_3_o(FSM_load_second_step),
.load_4_o(FSM_adder_round_norm_load),
.load_5_o(FSM_final_result_load),
.load_6_o(FSM_barrel_shifter_load),
.ctrl_select_a_o(selector_A),
.ctrl_select_b_o(load_b),
.selector_b_o(selector_B),
.ctrl_select_c_o(selector_C),
.exp_op_o(FSM_exp_operation_A_S),
.shift_value_o(FSM_Shift_Value),
.rst_int(rst_int), //
.ready(ready)
);
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////Selector's registers//////////////////////////////
RegisterAdd #(.W(1)) Sel_A ( //Selector_A register
.clk(clk),
.rst(rst_int),
.load(selector_A),
.D(1'b1),
.Q(FSM_selector_A)
);
RegisterAdd #(.W(1)) Sel_C ( //Selector_C register
.clk(clk),
.rst(rst_int),
.load(selector_C),
.D(1'b1),
.Q(FSM_selector_C)
);
RegisterAdd #(.W(2)) Sel_B ( //Selector_B register
.clk(clk),
.rst(rst_int),
.load(load_b),
.D(selector_B),
.Q(FSM_selector_B)
);
///////////////////////////////////////////////////////////////////////////////////////////
First_Phase_M #(.W(W)) Operands_load_reg ( //
.clk(clk), //**
.rst(rst_int), //**
.load(FSM_first_phase_load), //**
.Data_MX(Data_MX), //**
.Data_MY(Data_MY), //**
.Op_MX(Op_MX),
.Op_MY(Op_MY)
);
Zero_InfMult_Unit #(.W(W)) Zero_Result_Detect (
.clk(clk),
.rst(rst_int),
.load(FSM_load_first_step),
.Data_A(Op_MX [W-2:0]),
.Data_B(Op_MY [W-2:0]),
.zero_m_flag(zero_flag)
);
///////////Mux exp_operation OPER_A_i//////////
Multiplexer_AC #(.W(EW+1)) Exp_Oper_A_mux(
.ctrl(FSM_selector_A),
.D0 ({1'b0,Op_MX[W-2:W-EW-1]}),
.D1 (exp_oper_result),
.S (S_Oper_A_exp)
);
///////////Mux exp_operation OPER_B_i//////////
wire [EW-1:0] Exp_oper_B_D1, Exp_oper_B_D2;
Mux_3x1 #(.W(EW)) Exp_Oper_B_mux(
.ctrl(FSM_selector_B),
.D0 (Op_MY[W-2:W-EW-1]),
.D1 (Exp_oper_B_D1),
.D2 (Exp_oper_B_D2),
.S(S_Oper_B_exp)
);
generate
case(EW)
8:begin : BLK1EXP
assign Exp_oper_B_D1 = 8'd127;
assign Exp_oper_B_D2 = 8'd1;
end
default:begin : BLK2EXP
assign Exp_oper_B_D1 = 11'd1023;
assign Exp_oper_B_D2 = 11'd1;
end
endcase
endgenerate
///////////exp_operation///////////////////////////
Exp_Operation_m #(.EW(EW)) Exp_module (
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_load_first_step),
.load_b_i(FSM_load_second_step),
.load_c_i(FSM_exp_operation_load_result),
.Data_A_i(S_Oper_A_exp),
.Data_B_i({1'b0,S_Oper_B_exp}),
.Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag)
);
////////Sign_operation//////////////////////////////
XOR_M Sign_operation (
.Sgn_X(Op_MX[W-1]),
.Sgn_Y(Op_MY[W-1]),
.Sgn_Info(sign_final_result)
);
/////Significant_Operation//////////////////////////
// Sgf_Multiplication #(.SW(SW+1)) Sgf_operation (
// .clk(clk),
// .rst(rst),
// .load_b_i(FSM_load_second_step),
// .Data_A_i({1'b1,Op_MX[SW-1:0]}),
// .Data_B_i({1'b1,Op_MY[SW-1:0]}),
// .sgf_result_o(P_Sgf)
// );
`ifdef KOA_1STAGE
Simple_KOA_STAGE_1 #(
.SW(SW+1)
) Sgf_operation (
.clk (clk),
.rst (rst),
.load_b_i (FSM_load_second_step),
.Data_A_i ({1'b1,Op_MX[SW-1:0]}),
.Data_B_i ({1'b1,Op_MY[SW-1:0]}),
.sgf_result_o (P_Sgf)
);
`endif
`ifdef RKOA_1STAGE
RecursiveKOA_STAGE_1 #(
.SW(SW+1)
) Sgf_operation (
.clk (clk),
.rst (rst),
.load_b_i (FSM_load_second_step),
.Data_A_i ({1'b1,Op_MX[SW-1:0]}),
.Data_B_i ({1'b1,Op_MY[SW-1:0]}),
.sgf_result_o (P_Sgf)
);
`endif
`ifdef DW_1STAGE
DW_mult #(
.SW(SW+1)
) Sgf_operation (
.clk (clk),
.rst (rst),
.load_b_i (FSM_load_second_step),
.Data_A_i ({1'b1,Op_MX[SW-1:0]}),
.Data_B_i ({1'b1,Op_MY[SW-1:0]}),
.sgf_result_o (P_Sgf)
);
`endif
`ifdef KOA_2STAGE
Simple_KOA_STAGE_2 #(
.SW(SW+1)
) Sgf_operation (
.clk (clk),
.rst (rst),
.load_b_i (FSM_load_second_step),
.Data_A_i ({1'b1,Op_MX[SW-1:0]}),
.Data_B_i ({1'b1,Op_MY[SW-1:0]}),
.sgf_result_o (P_Sgf)
);
`endif
`ifdef RKOA_2STAGE
RecursiveKOA_STAGE_2 #(
.SW(SW+1)
) Sgf_operation (
.clk (clk),
.rst (rst),
.load_b_i (FSM_load_second_step),
.Data_A_i ({1'b1,Op_MX[SW-1:0]}),
.Data_B_i ({1'b1,Op_MY[SW-1:0]}),
.sgf_result_o (P_Sgf)
);
`endif
//////////Mux Barrel shifter shift_Value/////////////////
assign significand = P_Sgf [2*SW:SW];
assign non_significand = P_Sgf [SW-1:0];
///////////Mux Barrel shifter Data_in//////
Multiplexer_AC #(.W(SW+1)) Barrel_Shifter_D_I_mux(
.ctrl(FSM_selector_C),
.D0 (significand),
.D1 (Add_result),
.S (S_Data_Shift)
);
///////////Barrel_Shifter//////////////////////////
Barrel_Shifter_M #(.SW(SW+1)) Barrel_Shifter_module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_barrel_shifter_load),
.Shift_Value_i(FSM_Shift_Value),
.Shift_Data_i(S_Data_Shift),
.N_mant_o(Sgf_normalized_result)
);
////Round decoder/////////////////////////////////
Round_decoder_M #(.SW(SW)) Round_Decoder (
.Round_Bits_i(non_significand),
.Round_Mode_i(round_mode),
.Sign_Result_i(sign_final_result),
.Round_Flag_o(FSM_round_flag)
);
//rounding_adder
wire [SW:0] Add_Sgf_Oper_B;
assign Add_Sgf_Oper_B = (SW)*1'b1;
Adder_Round #(.SW(SW+1)) Adder_M (
.clk(clk),
.rst(rst_int),
.load_i(FSM_adder_round_norm_load),
.Data_A_i(Sgf_normalized_result),
.Data_B_i(Add_Sgf_Oper_B),
.Data_Result_o(Add_result),
.FSM_C_o(FSM_add_overflow_flag)
);
////Final Result///////////////////////////////
Tenth_Phase #(.W(W),.EW(EW),.SW(SW)) final_result_ieee_Module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_final_result_load),
.sel_a_i(overflow_flag),
.sel_b_i(underflow_flag),
.sign_i(sign_final_result),
.exp_ieee_i(exp_oper_result[EW-1:0]),
.sgf_ieee_i(Sgf_normalized_result[SW-1:0]),
.final_result_ieee_o(final_result_ieee)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVP_SYMBOL_V
`define SKY130_FD_SC_LS__EINVP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVP_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp_macb_r.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of PCX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp_macb_r(/*AUTOARG*/
// Outputs
data_out_px_l, scan_out, shiftenable_buf,
// Inputs
arb_pcxdp_qsel1_pa, arb_pcxdp_qsel0_pa, arb_pcxdp_grant_pa,
arb_pcxdp_shift_px, arb_pcxdp_q0_hold_pa, src_pcx_data_pa,
data_prev_px_l, rclk, scan_in, shiftenable
);
output [129:0] data_out_px_l; // pcx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_pcxdp_qsel1_pa; // queue write sel
input arb_pcxdp_qsel0_pa; // queue write sel
input arb_pcxdp_grant_pa;//grant signal
input arb_pcxdp_shift_px;//grant signal
input arb_pcxdp_q0_hold_pa;//grant signal
input [129:0] src_pcx_data_pa; // spache to pcx data
input [129:0] data_prev_px_l;
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_px;
wire [129:0] q0_datain_pa;
wire [129:0] q1_dataout, q0_dataout;
wire [129:0] data_px_l;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_pcxdp_q0_hold_pa),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_pcxdp_qsel1_pa),
.tmb_l(se_l));
// Latch and drive grant signal
// Generate write selects
dff_s #(1) dff_pcx_grin_r(
.din (arb_pcxdp_grant_pa),
.q (grant_px),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(130) dff_pcx_datain_q1(
.din (src_pcx_data_pa[129:0]),
.q (q1_dataout[129:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
/*
mux2ds #(`PCX_WIDTH) mx2ds_pcx_datain_q0(
.dout (q0_datain_pa[`PCX_WIDTH-1:0]),
.in0 (q1_dataout[`PCX_WIDTH-1:0]),
.in1 (src_pcx_data_pa[`PCX_WIDTH-1:0]),
.sel0 (arb_pcxdp_shift_px),
.sel1 (arb_pcxdp_qsel0_pa));
*/
assign q0_datain_pa[129:0] =
(arb_pcxdp_qsel0_pa ? src_pcx_data_pa[129:0] : 130'd0) |
(arb_pcxdp_shift_px ? q1_dataout[129:0] : 130'd0) ;
dff_s #(130) dff_pcx_datain_q0(
.din (q0_datain_pa[129:0]),
.q (q0_dataout[129:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_px_l[129:0] = ~(grant_px ? q0_dataout[129:0]:130'd0);
assign data_out_px_l[129:0] = data_px_l[129:0] & data_prev_px_l[129:0];
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule
|
(** * Tutorial for Mtac. *)
(**
Author: Beta Ziliani <[email protected]>
*)
(**
* Introduction
Mtac is a typechecked language for proof automation. It consists of a
monadic type [M A] for a type [A], which is interpreted via the new
operator [Mrun]. The best way of understanding the type [M A] is as
_maybe_ [A], so, for instance, a function of type [M nat] _may_ return
a natural number. It can also fail or loop forever, but it can never
produce a value of a different type (that is, it is sound). We call
functions of type [M A] _Mtactics_, to distinguish them from the usual
tactics provided by Coq. *)
(** One of the key aspects of Mtac is that it subsumes Gallina, the
language of Coq, and it inherits from Coq the beta delta iota zeta
reduction rules. This makes programming tactics very pleasant, since
developers only need to learn the new features and their semantics,
since the rest is _exactly the same_. These new features are:
- Exceptions,
- Unbounded fixpoints,
- Unification match,
- Fresh name generation,
- ML style references,
- And more.
*)
(** In this tutorial we illustrate some of these features, building up from
simple examples. In order to execute the code in this file you will
need to install Mtac's plugin. For details on how to do that, follow the
link: #<a href="http://plv.mpi-sws.org/mtac/">Mtac home page</a>#
*)
(** * Simple examples *)
(** To begin working with the new language we need to import the [M]
type. *)
Require Import Mtac.Mtac.
Import MtacNotations.
(** In addition, we import a couple of modules from the standard
library that we are going to use in some examples. *)
Require Import Arith.Arith Arith.Div2.
Require Import Lists.List.
Require Import Strings.String.
Set Implicit Arguments.
Notation "x == y" := (beq_nat x y) (at level 60).
(** We start by showing the standard _unit_ and _bind_ operators,
which in our language are called [ret] (for return) and [bind]. The
language also defines the standard notation [x <- a; b] for
[bind]. This example computes the value [1] by passing the result of
computing [0] to the successor.
*)
Definition produces_a_value :=
x <- ret 0;
ret (S x).
(** We check the type of the definition. It has type [M nat]. *)
Check produces_a_value.
(** Let's execute it using the new keyword [Mrun] and print the
result. *)
Definition the_value := Mrun produces_a_value.
Print the_value.
(** The result should be [the_value = 1 : nat]. As you can see,
[Mrun produces_a_value] was replaced by the effect of computing the
code in [produces_a_value]. Mathematically, [Mrun] is a partial
function from type [M A] to type [A]. *)
(** ** Exceptions *)
(** The monad includes exceptions, like the following silly example
illustrates. [Exception]s are constructed with the constructor
[exception]. In order to make distinguishable exceptions we make them
opaque, sealing the definition with the [Qed] word. *)
Definition AnException : Exception.
exact exception.
Qed.
(* They can be parametrized as well. *)
Definition MyException (s : string) : Exception.
exact exception.
Qed.
(** Note how they are equal to [exception], but we can still
differentiate them. *)
Definition test_ex e :=
mtry raise e : M string
with
| AnException => ret ""%string
| MyException "hello"%string => ret "world"%string
| [? s] MyException s => ret s
end.
Definition empty_string := Mrun (test_ex AnException).
Definition world_string := Mrun (test_ex (MyException "hello"%string)).
Definition other_string := Mrun (test_ex (MyException "other"%string)).
Print empty_string.
Print world_string.
Print other_string.
(** Results should be the empty string, the string "world" and the
string "other" respectively. *)
(** If an exception is not caught, then we get a meaningful error.
The [Fail] command below will show the exception thrown by the code: *)
Fail Check (Mrun (@raise nat (MyException "This is printed out"%string))).
(** Note that we have to specify the returning type (we put the arbitrary
type [nat]). *)
(** ** Unbounded fixpoints *)
(** Fixpoints in Coq should terminate to ensure soundness. Checking
termination is hard, so Coq relies on a pretty restrictive syntactic
condition to ensure termination. We allow non-termination in our
language via an unbounded fixpoint, which we call [mfix1], [mfix2], ...
where the number specifies the number of arguments of the function.
For instance, an endless loop can be written simply as: *)
Definition endless_loop := mfix1 f (n : nat) : M False := f n.
(** In this definition we decided to add the type annotation
[M False], since otherwise it is impossible for the type inference
mechanism to guess the type. It is important to note that the body of
[mfix1] should always be of type [M]. *)
(** Uncomment the code below and execute it: it will loop forever! You
will have to interrupt the proof assistant (C-c C-c in Emacs). *)
(**[
Check (Mrun (endless_loop 0)).
]*)
(** *** Endless loop... Is it still safe? *)
(** The key to understanding why it is perfectly safe to allow for
such effects is to notice that [Mrun] is not a function living in the
kernel typechecker of Coq. That is, for [t] of type [M A], [Mrun t]
constructs a witness for [A] only if it's safe to do so, but _it
itself is not a witness for [A]_. Take as example the definitions we
constructed so far: we used [run] but when we printed them we saw no
[Mrun] in their proof terms.
As an exercise, we can try to break soundness of Coq by constructing an
element of type [False] without any further hypothesis. Take the
function [endless_loop] above, which has type [nat -> M False]. To
get an element of type [False] we have to execute it through [Mrun] as
in the commented code. Since it will not terminate, [Mrun
(endless_loop 0)] doesn't produce an offending witness. *)
(** *** Constructing Collatz sequences *)
(** To show the use of this unbounded fixpoint we define a function
computing the #<a
href="http://en.wikipedia.org/wiki/Collatz_conjecture">Collatz
sequence</a>#, which cannot be defined in vanilla Coq since its
termination is a conjecture. *)
(* begin hide *)
Fixpoint is_even n :=
match n with
0 => true
| S n' => negb (is_even n')
end.
(* end hide *)
Definition collatz :=
mfix1 f (n : _) : M _ :=
let rest :=
if n == 1 then
ret nil
else if is_even n then
f (div2 n)
else
f (3 * n + 1)
in
s <- rest;
ret (n :: s).
(** We try it with the value [6]. *)
Definition the_sequence_6 := (Mrun (collatz 6)).
Print the_sequence_6.
(** Result: [(6
:: Nat.div2 6
:: 3 * Nat.div2 6 + 1
:: Nat.div2 (3 * Nat.div2 6 + 1)
:: 3 * Nat.div2 (3 * Nat.div2 6 + 1) + 1
:: Nat.div2 (3 * Nat.div2 (3 * Nat.div2 6 + 1) + 1)
:: Nat.div2 (Nat.div2 (3 * Nat.div2 (3 * Nat.div2 6 + 1) + 1))
:: Nat.div2
(Nat.div2
(Nat.div2 (3 * Nat.div2 (3 * Nat.div2 6 + 1) + 1)))
:: Nat.div2
(Nat.div2
(Nat.div2
(Nat.div2
(3 * Nat.div2 (3 * Nat.div2 6 + 1) + 1))))
:: nil) : list nat] *)
(** That doesn't look nice. We'd like to have a list of numbers, not a list of
computations. We have two alternatives, eiter we "compute" the result, or
we produce the values in the Mtactic already simplified. The first one is done
with the standard compute tactic. *)
Eval compute in the_sequence_6.
(** Result: [(6 :: 3 :: 10 :: 5 :: 16 :: 8 :: 4 :: 2 :: 1 :: nil) : list nat] *)
(** The second option, to simplify the results on the fly, requires a small change
in the original tactic: *)
Definition collatz_simpl :=
mfix1 f (n : _) : M _ :=
let rest :=
if n == 1 then
ret nil
else if is_even n then
f (div2 n)
else
f (3 * n + 1)
in
s <- rest;
retS (n :: s).
(** Can you spot the difference? *)
Definition the_sequence_6_simpl := (Mrun (collatz_simpl 6)).
Print the_sequence_6_simpl.
(** Result: [(6 :: 3 :: 10 :: 5 :: 16 :: 8 :: 4 :: 2 :: 1 :: nil) : list nat] *)
(** Mtac defines different unit operators, each operating on the term prior to
its return:
- [ret] does nothing.
- [retS] simplifies the term.
- [retW] weak head reduces the term.
- [retO] performs one step of reduction.
*)
(** ** Unification match *)
(** Mtac provides a powerful new construct: the unification
match. Unlike the native Coq pattern matching, the unification match
let us specify any term as a pattern, even patterns containing
variables bound in the context.
For instance, the code below shows a function that searches for an
element in a list. *)
Definition NotFound : Exception.
exact exception.
Qed.
Definition inlist A (x : A) :=
mfix1 f (s : list A) : M (In x s) :=
mmatch s with
| [? s'] (x :: s') => ret (in_eq _ _)
| [? y s'] (y :: s') =>
r <- f s';
ret (in_cons y _ _ r)
| _ => raise NotFound
end.
Check inlist.
(** We also depart from the standard notation for patterns: since they
may now refer to variables in the context, we need to specify a list
of pattern variables, like [[s']] in the first pattern. All the
variables not included in this list should be bound by the context,
like [x] in the same pattern, which is bound to the argument of the
definition. That is, this pattern matches a list containing the
element [x] in the head.
*)
(** So far we have constructed the proof terms directly, without using
the interactive mode of Coq. We can use any standard tactic ([apply],
[refine], [exact], [set], ...) with [Mrun], although [Mrun] is not always
suitable if we want to avoid writing inferable arguments. For
instance, if we have to prove a goal of the form [In x s] for some
list [s] and some element [x], then we would like to use [Mrun (inlist
_ _)], that is, without specifying the arguments. This will help us
build more robust proof scripts, since tomorrow we may replace [x] by
some other element in the list and still get a valid proof script. In
order to avoid writing the arguments, we can use the tactic [rrun]
already imported with the Mtac package: *)
Example x_in_zyx (x y z : nat) : In x (z :: y :: x :: nil).
Proof.
rrun (inlist _ _).
Qed.
Example y_in_zyx (x y z : nat) : In y (z :: y :: x :: nil).
Proof.
Fail apply (Mrun (inlist _ _)).
Abort.
(** [Fail] above shows that indeed it has failed to apply the Mtactic. *)
(** Of course, we can always provide the proof term directly instead
of going into interactive mode. In this case we don't need to
explicitly provide the arguments. [Mrun] is in fact notation for the
application of the tactic [rrun] with the [$(...)$] extension in Coq 8.5
to use tactics to build terms. *)
Example z_in_xyz (x y z : nat) : In z (x :: y :: z :: nil)
:= ltac:(rrun (inlist _ _)).
(** An alternative is to use [eval], which is similar to [Mrun], except
that it performs the execution of the Mtactic after the type inference
mechanism of Coq has done its job: *)
Example y_in_zyx (x y z : nat) : In y (z :: y :: x :: nil).
Proof.
apply (eval (inlist _ _)).
Qed.
(** *** Interaction with [Program] *)
(** When writing tactics, we can use [Program] to avoid having to
write the proof terms ourselves. As an example, we will extend our
[inlist] function to handle list concatenation in order to handle more
cases and get shorter proof terms. By using [Program], Coq will ask us
to provide (interactively) the proof terms for the cases where there is
a hole ([_]) and it cannot guess what to fill in that hole.
*)
Program Definition inlist' A (x : A) :=
mfix1 f (s : list A) : M (In x s) :=
mmatch s with
| [? l r] l ++ r =>
mtry
il <- f l;
ret _ : M (In _ (_ ++ _))
with _ =>
ir <- f r;
ret _ : M (In _ (_ ++ _))
end
| [? s'] (x :: s') => ret (in_eq _ _)
| [? y s'] (y :: s') =>
r <- f s';
ret (in_cons y _ _ r)
| _ => raise NotFound
end.
Next Obligation.
apply in_or_app; left; assumption.
Qed.
Next Obligation.
apply in_or_app; right; assumption.
Qed.
(** If the list is a concatenation of two lists [l] and [r], we first
try to search for the element on [l] and, if it fails, on [r]. Notice
that the pattern is not a constructor, but the application of the
function [++] to two lists. As mentioned before, we can use _any_ Coq term
as a pattern! It is important to make this case the first case of the
match, as the unification of the scrutinee with the pattern takes into
account beta delta iota zeta reductions. That is, if the concatenation case were
put third in the match, then the list [(x :: nil) ++ (z :: nil)] will
be matched against the pattern [(x :: s')], by reducing it to [(x :: z
:: nil)]. *)
(** One problem with [Program] is that it generates big proof terms.
Let's look at the proof terms generated in the obligations and plug
those terms into the holes. *)
Print inlist'_obligation_1.
Print inlist'_obligation_2.
(** The important bits are [in_or_app l r x (or_introl H)] and
[in_or_app l r x (or_intror H)]. We write our function again filling
in the holes with these two terms. *)
Definition inlist'' A (x : A) :=
mfix1 f (s : list A) : M (In x s) :=
mmatch s with
| [? l r] l ++ r =>
mtry
il <- f l;
ret (in_or_app _ _ _ (or_introl il))
with _ =>
ir <- f r;
ret (in_or_app _ _ _ (or_intror ir))
end
| [? s'] (x :: s') => ret (in_eq _ _)
| [? y s'] (y :: s') =>
r <- f s';
ret (in_cons y _ _ r)
| _ => raise NotFound
end.
(** Let's prove an example using the three functions just created to
compare the proof terms they generate.
*)
Example ex_inlist (x y z : nat) : In x ((y :: z :: nil)++(x :: z :: nil)).
Proof.
rrun (inlist _ _).
Qed.
Example ex_inlist' (x y z : nat) : In x ((y :: z :: nil)++(x :: z :: nil)).
Proof.
rrun (inlist' _ _).
Qed.
Example ex_inlist'' (x y z : nat) : In x ((y :: z :: nil)++(x :: z :: nil)).
Proof.
rrun (inlist'' _ _).
Qed.
Print ex_inlist.
Print ex_inlist'.
Print ex_inlist''.
(** Inspect the result. The last example has the shortest proof term. *)
(** * A simple tautology prover *)
(** We show by example some useful constructs for dealing with Higher
Order Abstract Syntax (HOAS). As the driving example we will write a
rudimentary tautology prover similar to that found in VeriML [[1]] and
CPDT [[2]]. Compared to VeriML, our approach has the benefit that it
doesn't require any special context treatment, since for us a context is
nothing more than a Coq list. And unlike in the Ltac version
presented in [[2]], we have meaningful types to prevent ourselves from
shooting ourselves in the foot.
*)
(** ** Warming the engine: a simple propositional prover *)
(** We start with a very simple propositional prover. It considers
only three cases:
- The proposition is [True]. In this case, it returns the trivial proof [I].
- The proposition is a conjunction of [p1] and [p2]. In this case, it proves both propositions and returns the introduction form of the conjunction.
- The proposition is a disjunction of [p1] and [p2]. In this case, it tries to prove the proposition [p1], and if it fails it tries to prove the proposition [p2]. The corresponding introduction form of the disjunction is returned.
- In any other case, it raises an exception, since no proof could be found.
*)
Definition simpl_prop_auto :=
mfix1 f (p : Prop) : M (p : Prop) :=
mmatch p as p' return M (p':Prop) with
| True => ret I
| [? p1 p2 ] p1 /\ p2 =>
r1 <- f p1 ;
r2 <- f p2 ;
ret (conj r1 r2)
| [? p1 p2] p1 \/ p2 =>
mtry
r1 <- f p1 ;
ret (or_introl r1)
with _ =>
r2 <- f p2 ;
ret (or_intror r2)
end
| _ => raise NotFound
end.
(** Given this definition we can easily discharge the following example. *)
Example ex1 : True /\ (False \/ True).
Proof.
rrun (simpl_prop_auto _).
Qed.
Print ex1.
(** The proof term is exactly what we would have written by hand:
[ex1 = conj I (or_intror I)] *)
(** ** Adding a context *)
(** Our previous function is very limited since it cannot prove
tautologies as simple as [P -> P]. To handle implications we need a
list of hypotheses where we can search for a proof of the atom we are
considering. We create a record type containing a proposition and a
witness for the proposition. *)
Record dyn := Dyn { prop : Prop ; elem : prop }.
(** We will need to search a list of [dyn]s to find a witness for some
proposition. The [search] function below is similar to the [inlist] above,
but keying on the [prop] projector of the record. We have to prepend [Program]
because it calls a more agressive typechecker, otherwise it fails to notice
that the element in the body of the first case should return a [P]. *)
Definition search (P : Prop) :=
mfix1 f (s:list dyn) : M P :=
mmatch s with
| [? (x:P) s'] (Dyn x) :: s' => ret x
| [? d s'] d :: s' => f s'
| _ => raise NotFound
end.
(** The proposition in the [Dyn] constructor is implicit, since it can
be inferred from the element, so we write [Dyn x] instead of [Dyn A
x]. *)
(** The tautology prover takes a context [c] (e.g., a list of [dyn]s)
and a proposition. The first three cases are the same as before. *)
Definition prop_auto' :=
mfix2 f (c : list dyn) (p : Prop) : M p :=
mmatch p as p' return M (p':Prop) with
| True => ret I
| [? p1 p2 ] p1 /\ p2 =>
r1 <- f c p1 ;
r2 <- f c p2 ;
ret (conj r1 r2)
| [? p1 p2] p1 \/ p2 =>
mtry
r1 <- f c p1 ;
ret (or_introl r1)
with _ =>
r2 <- f c p2 ;
ret (or_intror r2)
end
| [? (p1 p2 : Prop)] p1 -> p2 =>
nu (x:p1),
r <- f (Dyn x :: c) p2;
abs x r
| [? p':Prop] p' => search p' c
end.
(** Let's look at the new case for handling the implication. We need
to return an element of type [M (p1 -> p2)], that is, _maybe_ a
function from [p1] to [p2]. Of course, we cannot simply write
[ret (fun x:p1 => f (Dyn x :: c) p2)]
since this code has type [M (p1 -> M p2)] which is not what we
want. Instead, we use two new operators: [nu] and [abs]. The first one
is analogous to the nu operator in [[3]] and [[4]].
[nu] has type [forall A B, (A -> M B) -> M B] where [A] and [B] are
left implicit. The effect of computing [nu (fun x=>b)], where [b : T
B], is the result of executing [b], replacing any occurrence of [x]
with a fresh _parameter_ [a]. If the execution results in a term [ret
t] for some [t] with [a] not appearing free in it, then the value [ret
t] is used as result for [nu (fun x => b)]. Otherwise, a failure is
raised. Intuitively, the idea is that it is safe to execute the body
of a function as long as it doesn't get stuck (i.e., it shouldn't
inspect its argument), and the returning value doesn't return the
argument (i.e., it shouldn't violate the context).
[abs] abstracts over parameters created by [nu]. It has type [forall A
P (x : A), P x -> M (forall x, P x)] where [A] and [P] are left
implicit. If [a] is a parameter created by [nu] and [t] is a term with
[a] appearing free in it, then [abs a t] is replaced by [ret
(fun x=>r)], where [r] is [t] with [a] replaced by [x]. That is, [a]
is abstracted from [t].
Coming back to the implication case, we use [nu] to create a parameter
[x] as a witness for [p1]. Then we add it to the list of hypothesis to
prove [p2] and get the result [r], which may refer to [x]. Therefore,
we use [abs x r] to abstract [x] from the result. We encourage the
reader to check that the type of the whole expression returned in the
implication case has type [M (p1 -> p2)].
Finally, we changed the last case of the algorithm: instead of throwing
an error, now we search for a witness for the proposition in the list
using the [search] function defined before.
*)
(** We create a definition to avoid passing the empty list *)
Definition prop_auto P :=
@prop_auto' nil P.
(** We can now easily prove this tautology. *)
Example ex_with_implication (p q : Prop) : p -> q -> p /\ q.
Proof.
rrun (prop_auto _).
Qed.
(** Again, the proof term generated is exactly what we would expect
for such a proof. *)
Print ex_with_implication.
(** Result:
[ex_with_implication = fun (p q : Prop) (H : p) (H0 : q) => conj H H0] *)
(** * Getting first order *)
(** We can generalize our algorithm very easily to deal with [forall] and
[exists]. Below is the code, where the first four cases and the last one
are the same as before. *)
Definition tauto' :=
mfix2 f (c : list dyn) (p : Prop) : M p :=
mmatch p as p' return M (p':Prop) with
| True => ret I
| [? p1 p2] p1 /\ p2 =>
r1 <- f c p1 ;
r2 <- f c p2 ;
ret (conj r1 r2)
| [? p1 p2] p1 \/ p2 =>
mtry
r1 <- f c p1 ;
ret (or_introl r1)
with _ =>
r2 <- f c p2 ;
ret (or_intror r2)
end
| [? (p1 p2 : Prop)] p1 -> p2 =>
nu (x:p1),
r <- f (Dyn x :: c) p2;
abs x r
| [? A (q:A -> Prop)] (forall x:A, q x) =>
nu (x:A),
r <- f c (q x);
abs x r
| [? A (q:A -> Prop)] (exists x:A, q x) =>
X <- evar A;
r <- f c (q X) ;
b <- is_evar X;
if b then
raise NotFound
else
ret (ex_intro q X r)
| [? p':Prop] p' => search p' c
end.
(** The [forall] case is similar to the implication case from before but taking
into account the following:
- The type of [x] is any type [A], not just [Prop].
- The possible dependency of [x] in [q], the body of the [forall]. This dependency is marked by making [q] a function from [A] to [Prop]. The unification algorithm used to unify the pattern with the proposition [p] will take care of instantiating [q] with a function taking an element of type [A] and returning the body of the [forall].
- The context is not extended.
For the existential case, we create a fresh meta-variable [X] via the
command [evar], which takes a type (in this case [A]) and returns a
new meta-variable of that type. Then, we call the function recursively
with the body [q] of the existential, replacing the argument [x] with
[X]. Hopefully, the result will instantiate [X] and we return this as
the witness for the existential. If not, that is, if [X] is still
an uninstantiated meta-variable, then we raise an error.
As before, we create a definition to avoid passing the empty list:
*)
Definition tauto P :=
@tauto' nil P.
(** Here is an example to test [tauto]: *)
Example ex_first_order (p q : nat -> Prop) :
forall x, p x -> q x -> exists y, p y /\ q y.
Proof.
rrun (tauto _).
Qed.
(** If we cannot instantiate an existential, then an error is thrown. *)
Example ex_fail (p q : nat -> Prop) :
exists y, p y /\ q y.
Proof.
Fail rrun (tauto _).
Abort.
(** Actually, we can omit the check for the existential and let the
user come up with the witness by itself. *)
(** * Delayed execution via [eval] *)
(** We mentioned brefly that with [eval] we can delay the execution of
the Mtactic in order to get arguments from the goal. However, one
must use it with care, as the proof term generated is bigger than with
[Mrun]: *)
Print y_in_zyx.
(** Note how the procedure executed [inlist ...] is included in the proof
term. *)
(** The function [eval] is particularly useful when rewriting
procedures returning equalities. Here is an example using boolean
equality of natural numbers. Notice how we use the [[H]] notation
after the right arrow in the pattern. The name [H] will be
instantiated with a proof of equality of the scrutinee with the
pattern. *)
Program Definition eq_nats :=
mfix2 f (x : nat) (y : nat) : M (x == y = true) :=
mmatch (x, y) with
| (x, x) => [H] ret _
| [? x1 x2] (x1 + x2, x2 + x1) => [H]
ret _
end.
Next Obligation.
symmetry; apply beq_nat_refl.
Qed.
Next Obligation.
rewrite beq_nat_true_iff.
now apply plus_comm.
Qed.
Example plus_S n m : n + m == m + n = true /\ m == m = true /\ n == n = true.
Proof.
rewrite !(eval (eq_nats _ _)).
now auto.
Qed.
(** * Now you have to read the paper
You've seen the main characteristics of Mtac, but this doesn't include all
what you can do. Moreover, Mtac is still being developed, with new ideas
being incorporated all the time. You're invited to visit the web page and
to follow Mtac on Twitter or Facebook to keep updated.
#<a href="http://plv.mpi-sws.org/mtac/">Mtac home page</a>#
*)
(** * References *)
(**
[[1]] VeriML: Typed Computation of Logical Terms inside a Language
with Effects. Antonis Stampoulis and Zhong Shao. In Proc. 2010 ACM
SIGPLAN International Conference on Functional Programming (ICFP'10).
[[2]] http://adam.chlipala.net/cpdt/
[[3]] Aleksandar Nanevski. Meta-programming with names and
necessity. In Proceedings of the seventh ACM SIGPLAN international
conference on Functional programming, ICFP'02, pages 206-217, New
York, NY, USA, 2002. ACM.
[[4]] Carsten Schuermann, Adam Poswolsky, and Jeffrey Sarnat. The
nabla-calculus. functional programming with higher-order encodings. In
Proceedings of the 7th international conference on Typed Lambda
Calculi and Applications, TLCA'05, pages 339-353, Berlin, Heidelberg,
2005. Springer-Verlag.
[[5]] http://www.msr-inria.inria.fr/Projects/math-components
*)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111O_BLACKBOX_V
`define SKY130_FD_SC_HD__A2111O_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111O_BLACKBOX_V
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 18148 $
// $Date: 2009-10-20 18:25:16 +0000 (Tue, 20 Oct 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Sized fifo. Model has output register which improves timing
module SizedFIFO(CLK, RST_N, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter guarded = 1;
input CLK;
input RST_N;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
// synthesis attribute ram_style of arr is distributed
reg [p1width - 1 : 0] arr[0: ((p2depth >= 2) ? (p2depth-2) : 0)];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth - 'd2 ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2[p3cntr_width-1:0] ) ? 'b0 : incr_head ;
assign next_tail = (tail == depthLess2[p3cntr_width-1:0] ) ? 'b0 : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
integer i;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth - 2 && p2depth > 2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK /* or negedge RST_N */ )
begin
if (!RST_N)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
// Following section initializes the data registers which
// may be desired only in some situations.
// Uncomment to initialize array
/*
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
for (i = 0; i <= p2depth - 2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
*/
end // if (RST_N == 0)
else
begin
// Update arr[tail] once, since some FPGA synthesis tools are unable
// to infer good RAM placement when there are multiple separate
// writes of arr[tail] <= D_IN
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
if (CLR)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (DEQ && ENQ )
begin
if (ring_empty)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end
else
begin
// moved into combined write above
// arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head];
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
end // if (DEQ && ENQ )
else if ( DEQ )
begin
if (ring_empty)
begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head];
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
end // if ( DEQ )
else if (ENQ)
begin
if (! hasodata)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
// moved into combined write above
// arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN; // drop the old element
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end // if (ENQ)
end // else: !if(RST_N == 0)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( RST_N )
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 2 )
begin
ok = 0;
$display ( "ERROR SizedFIFO.v: depth parameter must be greater than 2" ) ;
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFO.v: width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:05:32 12/18/2016
// Design Name:
// Module Name: debounce
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module debounce(
input clk,
input binput,
output boutput
);
parameter PERIOD=1000000;
reg [23:0] counter;
reg d_button_state;
reg pressed;
assign boutput=d_button_state;
always@(posedge clk)begin
if(binput==0)begin
counter<=0;
if(d_button_state) pressed=1;else pressed=0;
end
else begin
counter<=counter+1;
end
end
always@(posedge clk)begin
if(counter==PERIOD && pressed==0)begin
d_button_state<=1;
end
else begin
d_button_state<=(binput==0)?0:boutput;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module dsp_t1_20x18x64 (
input [19:0] a_i,
input [17:0] b_i,
input [ 5:0] acc_fir_i,
output [37:0] z_o,
output [17:0] dly_b_o,
input clock_i,
input reset_i,
input [2:0] feedback_i,
input load_acc_i,
input unsigned_a_i,
input unsigned_b_i,
input [2:0] output_select_i,
input saturate_enable_i,
input [5:0] shift_right_i,
input round_i,
input subtract_i,
input register_inputs_i
);
parameter [19:0] COEFF_0 = 20'd0;
parameter [19:0] COEFF_1 = 20'd0;
parameter [19:0] COEFF_2 = 20'd0;
parameter [19:0] COEFF_3 = 20'd0;
QL_DSP2 # (
.MODE_BITS ({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
) _TECHMAP_REPLACE_ (
.a (a_i),
.b (b_i),
.acc_fir (acc_fir_i),
.z (z_o),
.dly_b (dly_b_o),
.clk (clock_i),
.reset (reset_i),
.feedback (feedback_i),
.load_acc (load_acc_i),
.unsigned_a (unsigned_a_i),
.unsigned_b (unsigned_b_i),
.f_mode (1'b0), // No fracturation
.output_select (output_select_i),
.saturate_enable (saturate_enable_i),
.shift_right (shift_right_i),
.round (round_i),
.subtract (subtract_i),
.register_inputs (register_inputs_i)
);
endmodule
module dsp_t1_10x9x32 (
input [ 9:0] a_i,
input [ 8:0] b_i,
input [ 5:0] acc_fir_i,
output [18:0] z_o,
output [ 8:0] dly_b_o,
(* clkbuf_sink *)
input clock_i,
input reset_i,
input [2:0] feedback_i,
input load_acc_i,
input unsigned_a_i,
input unsigned_b_i,
input [2:0] output_select_i,
input saturate_enable_i,
input [5:0] shift_right_i,
input round_i,
input subtract_i,
input register_inputs_i
);
parameter [9:0] COEFF_0 = 10'd0;
parameter [9:0] COEFF_1 = 10'd0;
parameter [9:0] COEFF_2 = 10'd0;
parameter [9:0] COEFF_3 = 10'd0;
wire [37:0] z;
wire [17:0] dly_b;
QL_DSP2 # (
.MODE_BITS ({10'd0, COEFF_3,
10'd0, COEFF_2,
10'd0, COEFF_1,
10'd0, COEFF_0})
) _TECHMAP_REPLACE_ (
.a ({10'd0, a_i}),
.b ({ 9'd0, b_i}),
.acc_fir (acc_fir_i),
.z (z),
.dly_b (dly_b),
.clk (clock_i),
.reset (reset_i),
.feedback (feedback_i),
.load_acc (load_acc_i),
.unsigned_a (unsigned_a_i),
.unsigned_b (unsigned_b_i),
.f_mode (1'b1), // Enable fractuation, Use the lower half
.output_select (output_select_i),
.saturate_enable (saturate_enable_i),
.shift_right (shift_right_i),
.round (round_i),
.subtract (subtract_i),
.register_inputs (register_inputs_i)
);
assign z_o = z[18:0];
assign dly_b_o = dly_b_o[8:0];
endmodule
|
// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
//*****************************************************************************
// Filename : axi4lite_mst.v
// Description : This module is a simple AXI4-Lite Master
//
// Available user tasks :
// wr(<addr>, <data>) -> Perform AXI4-Lite Write Transaction
// rd(<addr>, <data>) -> Perform AXI4-Lite Read Transaction
// debug_on() -> turn on debug displays
// debug_off() -> turn off debug displays
// on() -> enable module
// off() -> disable module
//
// Limitations :
// - bready_d0 & rready_d0 are always asserted
// - wstrb_d0 is always 4'b1111
// - awprot_d0 is always 3'b010
// - arprot_d0 is always 3'b010
//
//-----------------------------------------------------------------------------
// Ver Date Modified by Modification
//-----------------------------------------------------------------------------
// 1.0 09/11/2011 reinald Initial code.
// 1.1 13/12/2011 reinald Modified wvalid_d0 to assert together with
// awvalid_d0 in address phase
// 1.2 14/12/2011 reinald Added additional port "aclken" that masks
// aclk and suspends module operation.
// 1.3 14/05/2012 reinald Added configurable drive delay for all
// output ports.
// Fixed Sampling edge to clock rise.
// Driving edge configurable by parameter.
// Modified for iSim & ncsim support.
// 1.4 30/05/2012 reinald added task wr_get_resp & read_get_resp.
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module axi4lite_mst
#(
parameter module_id = "AXI4-Lite Master 1",
parameter drive_edge = "rise", //only "rise" or "fall" is valid
parameter datawidth = 32, //only 32 or 64 is valid
parameter addrwidth = 32,
parameter drive_dly = 0 //drive delay for output ports
)
(
input aclk,
input aclken,
input aresetn,
input awready,
output reg awvalid,
output reg [addrwidth-1:0] awaddr,
output reg [2:0] awprot,
input wready,
output reg wvalid,
output reg [datawidth-1:0] wdata,
output reg [(datawidth/8)-1:0] wstrb,
input bvalid,
input [1:0] bresp,
output reg bready,
input arready,
output reg arvalid,
output reg [addrwidth-1:0] araddr,
output reg [2:0] arprot,
input rvalid,
input [datawidth-1:0] rdata,
input [1:0] rresp,
output reg rready
);
reg awvalid_d0;
reg [addrwidth-1:0] awaddr_d0;
reg [2:0] awprot_d0;
reg wvalid_d0;
reg [datawidth-1:0] wdata_d0;
reg [(datawidth/8)-1:0] wstrb_d0;
reg bready_d0;
reg arvalid_d0;
reg [addrwidth-1:0] araddr_d0;
reg [2:0] arprot_d0;
reg rready_d0;
always @(awvalid_d0) #(drive_dly) awvalid = awvalid_d0;
always @(awaddr_d0) #(drive_dly) awaddr = awaddr_d0;
always @(awprot_d0 ) #(drive_dly) awprot = awprot_d0;
always @(wvalid_d0) #(drive_dly) wvalid = wvalid_d0;
always @(wdata_d0) #(drive_dly) wdata = wdata_d0;
always @(wstrb_d0) #(drive_dly) wstrb = wstrb_d0;
always @(bready_d0) #(drive_dly) bready = bready_d0;
always @(arvalid_d0) #(drive_dly) arvalid = arvalid_d0;
always @(araddr_d0) #(drive_dly) araddr = araddr_d0;
always @(arprot_d0) #(drive_dly) arprot = arprot_d0;
always @(rready_d0) #(drive_dly) rready = rready_d0;
// module control
reg enable = 1;
reg debug = 1;
reg throttle = 0;
reg [31:0] throttlewidth = 10;
reg [31:0] throttlewait = 5;
// container for read data
reg [datawidth-1:0] read_data_t = 0;
reg [datawidth-1:0] write_data_t = 0;
reg [addrwidth-1:0] read_addr_t = 0;
reg [addrwidth-1:0] write_addr_t = 0;
reg [1:0] bresp_t = 0;
reg [1:0] rresp_t = 0;
// variables for flow control
integer throttle_data_cnt;
integer throttle_wait_cnt;
integer pending_wr_tx = 0;
integer pending_rd_tx = 0;
//transaction events
event mst_write_req_evt;
event mst_write_done_evt;
event mst_read_req_evt;
event mst_read_done_evt;
event slv_write_rdy_evt;
event slv_write_ack_evt;
event slv_write_resp_evt;
event slv_read_rdy_evt;
event slv_read_resp_evt;
//clock events
event aclk_rise;
event aclk_fall;
event aresetn_rise;
event aresetn_fall;
always @(posedge aclk) if(aclken) -> aclk_rise;
always @(negedge aclk) if(aclken) -> aclk_fall;
always @(posedge aresetn) -> aresetn_rise;
always @(negedge aresetn) -> aresetn_fall;
always @(aclk_rise) if(awready && awvalid) -> slv_write_rdy_evt;
always @(aclk_rise) if(wready && wvalid) -> slv_write_ack_evt;
always @(aclk_rise) if(bready && bvalid) -> slv_write_resp_evt;
always @(aclk_rise) if(arready && arvalid) -> slv_read_rdy_evt;
always @(aclk_rise) if(rready && rvalid) -> slv_read_resp_evt;
always @(mst_write_req_evt)
begin
if(drive_edge == "fall") @aclk_fall;
pending_wr_tx = 1;
awaddr_d0 = write_addr_t;
awvalid_d0 = 1;
wdata_d0 = write_data_t;
wvalid_d0 = 1;
end
always @(slv_write_rdy_evt)
begin
if(drive_edge == "fall") @aclk_fall;
awaddr_d0 = 0;
awvalid_d0 = 0;
end
always @(slv_write_ack_evt)
begin
if(drive_edge == "fall") @aclk_fall;
wdata_d0 = 0;
wvalid_d0 = 0;
bready_d0 = 1;
end
always @(slv_write_resp_evt)
begin
if(drive_edge == "fall") @aclk_fall;
bresp_t = bresp;
//IF NEEDED.
//DO ERROR CHECKING HERE FOR RESPONSE
-> mst_write_done_evt;
pending_wr_tx = 0;
end
always @(mst_read_req_evt)
begin
if(drive_edge == "fall") @aclk_fall;
pending_rd_tx = 1;
araddr = read_addr_t;
arvalid_d0 = 1;
end
always @(slv_read_rdy_evt)
begin
if(drive_edge == "fall") @aclk_fall;
araddr = 0;
arvalid_d0 = 0;
rready_d0 = 1;
end
always @(slv_read_resp_evt)
begin
if(drive_edge == "fall") @aclk_fall;
read_data_t = rdata;
rresp_t = rresp;
//IF NEEDED.
//DO ERROR CHECKING HERE FOR RESPONSE
-> mst_read_done_evt;
pending_rd_tx = 0;
end
initial
begin
on;
throttle_data_cnt = throttlewidth;
throttle_wait_cnt = throttlewait;
if((drive_edge != "rise")&&(drive_edge != "fall"))
begin
$display("@%10t : [%s] \"%s\" is not a valid drive_edge parameter value ...", $time, module_id, drive_edge);
$finish;
end
end
//=============//
// USER TASKS //
//=============//
task init_ports;
begin
//output port initialization
awvalid_d0 = 0;
awaddr_d0 = 0;
awprot_d0 = 3'b010;
wvalid_d0 = 0;
wdata_d0 = 0;
wstrb_d0 = 4'b1111;
bready_d0 = 1;
arvalid_d0 = 0;
araddr = 0;
arprot_d0 = 3'b010;
rready_d0 = 1;
end
endtask
task init_vars;
begin
read_data_t = 0;
read_addr_t = 0;
write_data_t = 0;
write_addr_t = 0;
pending_wr_tx = 0;
pending_rd_tx = 0;
throttle_data_cnt = 0;
throttle_wait_cnt = 0;
end
endtask
task on;
begin
enable = 1;
init_ports;
init_vars;
$display("@%10t : [%s] Enabled.", $time, module_id);
end
endtask
task off;
begin
enable = 0;
init_ports;
$display("@%10t : [%s] Disabled.", $time, module_id);
end
endtask
task debug_on;
begin
debug = 1;
end
endtask
task debug_off;
begin
debug = 0;
end
endtask
task throttle_on;
begin
if(debug)
begin
$display("@%10t : [%s] Data Throttle Turned ON", $time, module_id);
end
throttle = 1;
throttle_data_cnt = throttlewidth;
throttle_wait_cnt = throttlewait;
end
endtask
task throttle_off;
begin
if(debug)
begin
$display("@%10t : [%s] Data Throttle Turned OFF", $time, module_id);
end
throttle = 0;
end
endtask
task set_throttle_valid;
input [31:0] width;
begin
if(debug)
begin
$display("@%10t : [%s] Data Throttle Width set to %d", $time, module_id, width);
end
throttlewidth = width;
throttle_data_cnt = width;
end
endtask
task set_throttle_wait;
input [31:0] width;
begin
if(debug)
begin
$display("@%10t : [%s] Data Throttle Wait set to %d", $time, module_id, width);
end
throttlewait = width;
throttle_wait_cnt = width;
end
endtask
//=================================//
// TASK TO ISSUE WRITE TRANSACTION //
//=================================//
task wr;
input [addrwidth-1:0] useraddr;
input [datawidth-1:0] userdata;
begin
if(enable)
begin
if(debug) $display("@%10t : [%s] Write Start [ADDR = %8x , DATA = %8x]", $time, module_id, useraddr, userdata);
wait(pending_wr_tx == 0);
write_addr_t = useraddr;
write_data_t = userdata;
@(aclk_rise);
-> mst_write_req_evt;
@(mst_write_done_evt);
if(debug) $display("@%10t : [%s] Write Done [ADDR = %8x , DATA = %8x]", $time, module_id, useraddr, userdata);
end
else
begin
if(debug) $display("@%10t : [%s] Module disabled. Write Transaction NOT done. ", $time, module_id);
end
end
endtask
task wr_get_resp;
input [addrwidth-1:0] useraddr;
input [datawidth-1:0] userdata;
output [1:0] userrsp;
begin
wr(useraddr, userdata);
userrsp = bresp_t;
end
endtask
//=================================//
// TASK TO ISSUE READ TRANSACTION //
//=================================//
task rd;
input [addrwidth-1:0] useraddr;
output [datawidth-1:0] userdata;
begin
if(enable)
begin
if(debug) $display("@%10t : [%s] Read Start [ADDR = %8x]", $time, module_id, useraddr);
wait(pending_rd_tx == 0);
read_addr_t = useraddr;
@(aclk_rise);
-> mst_read_req_evt;
@(mst_read_done_evt);
userdata = read_data_t;
if(debug) $display("@%10t : [%s] Read Done [ADDR = %8x, DATA = %8x]", $time, module_id, useraddr, userdata);
end
else
begin
if(debug) $display("@%10t : [%s] Module disabled. Read Transaction NOT done. ", $time, module_id);
end
end
endtask
task rd_get_resp;
input [addrwidth-1:0] useraddr;
output [datawidth-1:0] userdata;
output [1:0] userrsp;
begin
rd(useraddr, userdata);
userrsp = rresp_t;
end
endtask
//=================//
// RESET DETECTION //
//=================//
always @(aresetn_fall)
begin
//aresetn assertion//
if(debug == 1)
begin
$display("@%10t : [%s] RESET asserted...", $time, module_id);
end
off;
-> mst_read_done_evt;
-> mst_write_done_evt;
pending_rd_tx = 0;
pending_wr_tx = 0;
@aresetn_rise;
if(debug == 1)
begin
$display("@%10t : [%s] RESET deasserted...", $time, module_id);
end
on;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_SYMBOL_V
/**
* udp_dff$P_pp$PKG$s: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_SYMBOL_V
|
module cov_tl_stage
import bsg_cache_non_blocking_pkg::*;
(
input clk_i
, input reset_i
, input ld_st_miss
, input mhu_miss_match
, input dma_miss_match
, input ld_st_hit
, input data_mem_pkt_ready_i
, input stat_mem_pkt_ready_i
, input v_i
, input bsg_cache_non_blocking_decode_s decode_i
, input miss_fifo_ready_i
, input recover_i
, input v_tl_r
, input mhu_tag_mem_pkt_v_i
, input mhu_idle_i
);
wire decode_mgmt_op = decode_i.mgmt_op;
covergroup cg_miss_match @ (negedge clk_i iff ld_st_miss);
coverpoint mhu_miss_match;
coverpoint dma_miss_match;
cross mhu_miss_match, dma_miss_match {
ignore_bins both_match = binsof(mhu_miss_match) intersect {1'b1}
&& binsof(dma_miss_match) intersect {1'b1};
}
endgroup
covergroup cg_ld_st_hit @ (negedge clk_i iff ld_st_hit);
coverpoint v_i;
coverpoint data_mem_pkt_ready_i;
coverpoint stat_mem_pkt_ready_i;
coverpoint decode_mgmt_op;
cross v_i, data_mem_pkt_ready_i, stat_mem_pkt_ready_i, decode_mgmt_op {
ignore_bins invalid_mgmt_op = binsof(v_i) intersect {1'b0}
&& binsof(decode_mgmt_op) intersect {1'b1};
}
endgroup
covergroup cg_ld_st_miss @ (negedge clk_i iff ld_st_miss);
coverpoint miss_fifo_ready_i;
coverpoint v_i;
coverpoint decode_mgmt_op;
cross v_i, miss_fifo_ready_i, decode_mgmt_op {
ignore_bins invalid_mgmt_op = binsof(v_i) intersect {1'b0}
&& binsof(decode_mgmt_op) intersect {1'b1};
}
endgroup
covergroup cg_tl_empty @ (negedge clk_i iff ~v_tl_r);
coverpoint recover_i;
coverpoint mhu_tag_mem_pkt_v_i;
coverpoint decode_mgmt_op;
coverpoint v_i;
coverpoint mhu_idle_i;
cross v_i, recover_i, mhu_tag_mem_pkt_v_i, decode_mgmt_op, mhu_idle_i {
ignore_bins invalid_mgmt_op = binsof(v_i) intersect {1'b0}
&& binsof(decode_mgmt_op) intersect {1'b1};
ignore_bins recover_mhu_pkt = binsof(recover_i) intersect {1'b1}
&& binsof(mhu_tag_mem_pkt_v_i) intersect {1'b1};
ignore_bins mhu_idle = (binsof(recover_i) intersect {1'b1} || binsof(mhu_tag_mem_pkt_v_i) intersect {1'b1})
&& binsof(mhu_idle_i) intersect {1'b1};
}
endgroup
initial begin
cg_miss_match mm = new;
cg_ld_st_hit ls = new;
cg_ld_st_miss lsm = new;
cg_tl_empty te = new;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXBP_BLACKBOX_V
`define SKY130_FD_SC_MS__SEDFXBP_BLACKBOX_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXBP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
module image_capture_manager_testbench #
( parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
input wire aclk,
input wire aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] awaddr,
input wire [2 : 0] awprot,
input wire awvalid,
input wire awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] wstrb,
input wire wvalid,
input wire wready,
output wire [1 : 0] bresp,
output wire bvalid,
input wire bready,
output wire enable,
output wire clear_memory
);
image_capture_manager test(.s00_axi_aclk(aclk), .s00_axi_aresetn(aresetn), .s00_axi_awaddr(awaddr),
.s00_axi_awprot(awprot), .s00_axi_awvalid(awvalid), .s00_axi_awready(awready),
.s00_axi_wdata(wdata), .s00_axi_wstrb(wstrb), .s00_axi_wvalid(wvalid), .s00_axi_wready(wready),
.s00_axi_bresp(bresp), .s00_axi_bvalid(bvalid), .s00_axi_bready(bready),
.image_capture_enabled(enable), .clear_memory(clear_memory));
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V
/**
* lpflow_inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso0n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Name Output Other arguments
and and0 (X , A, SLEEP_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V |
module decode(clock, insn, pc, opcode_out, rs_out, rt_out, rd_out,
sa_out, func_out, imm_out, enable_decode, pc_out,
insn_out, ALUOp, rsOut_regfile, rtOut_regfile, dVal_regfile, we_regfile, imm_out_sx, rdIn);
/****************OPCODES******************/
// R-Type FUNC Codes
parameter ADD = 6'b100000; //ADD;
parameter ADDU = 6'b100001; //ADDU;
parameter SUB = 6'b100010; //SUB;
parameter SUBU = 6'b100011; //SUBU;
parameter MULT = 6'b011000; //MULT;
parameter MULTU = 6'b011001; //MULTU;
parameter DIV = 6'b011010; //DIV;
parameter DIVU = 6'b011011; //DIVU;
parameter MFHI = 6'b010000; //MFHI;
parameter MFLO = 6'b010010; //MFLO;
parameter SLT = 6'b101010; //SLT;
parameter SLTU = 6'b101011; //SLTU;
parameter SLL = 6'b000000; //SLL;
parameter SLLV = 6'b000100; //SLLV;
parameter SRL = 6'b000010; //SRL;
parameter SRLV = 6'b000110; //SRLV;
parameter SRA = 6'b000011; //SRA;
parameter SRAV = 6'b000111; //SRAV;
parameter AND = 6'b100100; //AND;
parameter OR = 6'b100101; //OR;
parameter XOR = 6'b100110; //XOR;
parameter NOR = 6'b100111; //NOR
parameter JALR = 6'b001001; //JALR;
parameter JR = 6'b001000; //JR;
// MUL R-TYPE Opcode
parameter MUL_OP = 6'b011100; //MUL OPCODE
parameter MUL_FUNC = 6'b000010; //MUL FUNCTION CODE
// I-Type Opcodes
parameter ADDI = 6'b001000; //ADDI (LI)
parameter ADDIU = 6'b001001; //ADDIU
parameter SLTI = 6'b001010; //SLTI
parameter SLTIU = 6'b001011; //SLTIU
parameter ORI = 6'b001101; //ORI
parameter XORI = 6'b001110; //XORI
parameter LW = 6'b100011; //LW
parameter SW = 6'b101011; //SW
parameter LB = 6'b100000; //LB
parameter LUI = 6'b001111; //LUI
parameter SB = 6'b101000; //SB
parameter LBU = 6'b100100; //LBU
parameter BEQ = 6'b000100; //BEQ
parameter BNE = 6'b000101; //BNE
parameter BGTZ = 6'b000111; //BGTZ
parameter BLEZ = 6'b000110; //BLEZ
// REGIMM Opcodes
parameter BLTZ = 5'b00000; // BLTZ
parameter BGEZ = 5'b00001; // BGEZ
// J-Type Opcodes
parameter J = 6'b000010;
parameter JAL = 6'b000011;
// Other
parameter NOP = 6'b000000;
parameter RTYPE = 6'b000000;
/******************************************/
// Control Registers
output reg [5:0] ALUOp;
// Input ports
input wire clock;
input wire [31:0] insn;
input wire [31:0] pc;
input wire enable_decode;
input wire [4:0] rdIn;
// Registers
reg [31:0] pc_reg;
// Output
output reg [5:0] opcode_out;
output reg [4:0] rs_out;
output reg [4:0] rt_out;
output reg [4:0] rd_out;
output reg [4:0] sa_out;
output reg [5:0] func_out;
output reg [25:0] imm_out;
output reg [31:0] pc_out;
output reg [31:0] insn_out;
output reg [31:0] imm_out_sx;
// Register File Logic
parameter NUM_REGS = 32;
parameter WIDTH = 32;
parameter REG_WIDTH = 5;
reg [REG_WIDTH - 1:0] rsIn_regfile, rtIn_regfile, rdIn_regfile;
input [WIDTH - 1:0] dVal_regfile;
input we_regfile;
output [WIDTH - 1:0] rsOut_regfile, rtOut_regfile;
reg [WIDTH - 1:0] REGFILE [NUM_REGS - 1:0];
integer i_regfile;
// Combinationally write to rsOut and rtOut
assign rsOut_regfile = REGFILE[rsIn_regfile];
assign rtOut_regfile = REGFILE[rtIn_regfile];
// Used for initializing REGFILE with values
initial
begin
for (i_regfile = 0; i_regfile < NUM_REGS; i_regfile = i_regfile + 1) begin
REGFILE[i_regfile] = i_regfile;
end
REGFILE[29] = 32'h80120000; // stack pointer
end
always @(posedge clock)
begin : DECODE
if (enable_decode) begin
pc_out <= pc;
insn_out <= insn;
if (insn[31:26] == RTYPE || insn[31:26] == MUL_OP) begin
// Instruction is R-type
// Further need to clasify function (add, sub, etc..)
opcode_out = RTYPE;
case (insn[5:0])
ADD: begin // Used for MOVE pseudoinsn
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = insn[10:6];
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = ADD;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
ADDU: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = insn[10:6];
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = ADDU;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
SUB: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = insn[10:6];
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = SUB;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
SUBU: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = insn[10:6];
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = SUBU;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
MUL_FUNC: begin
opcode_out = MUL_OP;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = MUL_FUNC;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
MULT: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'b0;
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = MULT;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
MULTU: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'b0;
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = MULTU;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
DIV: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'b0;
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = DIV;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
DIVU: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'b0;
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = DIVU;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
MFHI: begin
rs_out = 5'b0;
rt_out = 5'b0;
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = MFHI;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
MFLO: begin
rs_out = 5'b0;
rt_out = 5'b0;
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = MFLO;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
SLT: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = SLT;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
SLTU: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = SLTU;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
SLL: begin
rs_out = 5'b0;
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = insn[15:6];
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = SLL;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
SLLV: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = SLLV;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
SRL: begin
rs_out = 5'b0;
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = insn[10:6];
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = SRL;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
SRLV: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = SRLV;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
SRA: begin
rs_out = 5'b0;
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = insn[10:6];
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = SRA;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
SRAV: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = SRAV;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
AND: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = AND;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
OR: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = OR;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
NOR: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = NOR;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
JALR: begin
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = insn[15:11];
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = JALR;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
JR: begin
rs_out = insn[25:21];
rt_out = 5'b0;
rd_out = 5'b0;
sa_out = 5'b0;
imm_out = 26'hx;
func_out = insn[5:0];
ALUOp = JR;
rsIn_regfile = rs_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] = 32'hx;
end
endcase
end else if (insn[31:26] != 6'b000000 && insn[31:27] != 5'b00001 && insn[31:26] != 6'b000001) begin
// Instruction is I-Type
// Further need to classify function (addiu, diviu, etc...)
case (insn[31:26])
ADDI: begin
opcode_out = ADDI;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = rt_out;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0];
func_out = 6'hx;
ALUOp = ADDI;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] = { { 16{ insn[15] } }, insn[15:0] };
end
ADDIU: begin
opcode_out = ADDIU;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = rt_out;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0]; // Most significant 16-bits are immediate target
func_out = 6'hx;
ALUOp = ADDIU;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] = { { 16{ insn[15] } }, insn[15:0] };
end
SLTI: begin
opcode_out = SLTI;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0]; // Most significant 16-bits are immediate target
func_out = 6'hx;
ALUOp = SLTI;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
SLTIU: begin
opcode_out = SLTIU;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0]; // Most significant 16-bits are immediate target
func_out = 6'hx;
ALUOp = SLTIU;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
ORI: begin
opcode_out = ORI;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0]; // Most significant 16-bits are immediate target
func_out = 6'hx;
ALUOp = ORI;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
XORI: begin
opcode_out = XORI;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0]; // Most significant 16-bits are immediate target
func_out = 6'hx;
ALUOp = XORI;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
LW: begin
opcode_out = LW;
rs_out = insn[25:21]; // BASE
rt_out = insn[20:16]; // RT
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0]; // OFFSET
func_out = 6'hx;
ALUOp = LW;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
SW: begin
opcode_out = SW;
rs_out = insn[25:21]; // BASE
rt_out = insn[20:16]; // RT
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0]; // OFFSET
func_out = 6'hx;
ALUOp = SW;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
LB: begin
opcode_out = LB;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0];
func_out = 6'hx;
ALUOp = LB;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
LUI: begin
opcode_out = LUI;
rs_out = 5'b00000;
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0];
func_out = 6'hx;
ALUOp = LUI;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
SB: begin
opcode_out = SB;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0];
func_out = 6'hx;
ALUOp = SB;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
LBU: begin
opcode_out = LBU;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0];
func_out = 6'hx;
ALUOp = LBU;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
BEQ: begin
opcode_out = BEQ;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0];
func_out = 6'hx;
ALUOp = BEQ;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
BNE: begin
opcode_out = BNE;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0];
func_out = 6'hx;
ALUOp = BNE;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
BGTZ: begin
opcode_out = BGTZ;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0];
func_out = 6'hx;
ALUOp = BGTZ;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
BLEZ: begin
opcode_out = BLEZ;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0];
func_out = 6'hx;
ALUOp = BLEZ;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
endcase
end else if (insn[31:6] == 6'b000001) begin
// REGIMM
case (insn[20:16])
BLTZ: begin
opcode_out = BLTZ;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0];
func_out = 6'hx;
ALUOp = BLTZ;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
BGEZ: begin
opcode_out = BGEZ;
rs_out = insn[25:21];
rt_out = insn[20:16];
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:10] = insn[15:0];
func_out = 6'hx;
ALUOp = BGEZ;
rsIn_regfile = rs_out;
rdIn_regfile = rt_out;
imm_out_sx[31:0] <= { { 16{ insn[15] } }, insn[15:0] };
end
endcase
end else if (insn[31:27] == 5'b00001) begin
// Instruction is J-Type
case (insn[31:26])
J: begin
opcode_out = J;
rs_out = 5'hx;
rt_out = 5'hx;
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:0] = insn[25:0];
func_out = 6'hx;
ALUOp = J;
rsIn_regfile = imm_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] <= { {6{1'b0}}, insn[25:0] };
end
JAL: begin
opcode_out = JAL;
rs_out = 5'hx;
rt_out = 5'hx;
rd_out = 5'hx;
sa_out = 5'hx;
imm_out[25:0] = insn[25:0];
func_out = 6'hx;
ALUOp = JAL;
rsIn_regfile = imm_out;
rtIn_regfile = rt_out;
rdIn_regfile = rd_out;
imm_out_sx[31:0] <= { {6{1'b0}}, insn[25:0] };
end
endcase
end else if (insn[31:0] == 32'h00000000) begin
opcode_out = NOP;
rs_out = 5'b00000;
rt_out = 5'b00000;
rd_out = 5'b00000;
sa_out = 5'b00000;
imm_out = 26'hx;
func_out = 6'b000000;
ALUOp = NOP;
end
end
end
// Clocked write of writeback data
always @(posedge clock)
begin: REG_WRITE
if (we_regfile == 1) begin
REGFILE [rdIn] = dVal_regfile;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_rq_rdq_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Request Dqta Queue Buffer
// Top level Module: jbi_min_rdq_buf
// Where Instantiated: jbi_min_rdq
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_min_rq_rdq_buf(/*AUTOARG*/
// Outputs
rdq_rdata,
// Inputs
clk, cpu_clk, arst_l, hold, rst_tri_en, rdq_wr_en, rdq_rd_en,
rdq_waddr, rdq_raddr, wdq_rdq_wdata
);
input clk;
input cpu_clk;
input arst_l;
input hold;
input rst_tri_en;
input rdq_wr_en;
input rdq_rd_en;
input [`JBI_RDQ_ADDR_WIDTH-1:0] rdq_waddr;
input [`JBI_RDQ_ADDR_WIDTH-1:0] rdq_raddr;
input [`JBI_RDQ_WIDTH-1:0] wdq_rdq_wdata;
output [`JBI_RDQ_WIDTH-1:0] rdq_rdata;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_RDQ_WIDTH-1:0] rdq_rdata;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
///////////////////////////////////////////////////////////////////////
wire [3:0] dangle;
//
// Code start here
//
jbi_1r1w_16x160 u_rdq_buf
(// outputs
.dout ( {dangle[3:0],
rdq_rdata} ),
// read inputs
.rdclk (cpu_clk),
.read_en (rdq_rd_en),
.rd_adr (rdq_raddr),
// write inputs
.wrclk (clk),
.wr_en (rdq_wr_en),
.wr_adr (rdq_waddr),
.din ( {4'b0000,
wdq_rdq_wdata} ),
// other inputs
.rst_l (arst_l),
.hold (hold),
.testmux_sel (1'b1), // always want data from FF
.rst_tri_en (rst_tri_en)
);
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/mem/rtl/")
// verilog-auto-sense-defines-constant:t
// End:
|
(** * Rel: Properties of Relations *)
(* $Date: 2013-04-01 09:15:45 -0400 (Mon, 01 Apr 2013) $ *)
Require Export SfLib.
(** A (binary) _relation_ is just a parameterized proposition. As you know
from your undergraduate discrete math course, there are a lot of
ways of discussing and describing relations _in general_ -- ways
of classifying relations (are they reflexive, transitive, etc.),
theorems that can be proved generically about classes of
relations, constructions that build one relation from another,
etc. Let us pause here to review a few that will be useful in
what follows. *)
(** A (binary) relation _on_ a set [X] is a proposition parameterized by two
[X]s -- i.e., it is a logical assertion involving two values from
the set [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Somewhat confusingly, the Coq standard library hijacks the generic
term "relation" for this specific instance. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, while the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-that-or-equal-to
relation which we usually write like this [n1 <= n2]. *)
Print le.
(* ====>
Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m
*)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(* ######################################################### *)
(** * Basic Properties of Relations *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., if [R x
y1] and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined in Logic.v is a
partial function. *)
(* Print next_nat.
(* ====>
Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n)
*)
Check next_nat : relation nat.
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity. Qed. *)
(** However, the [<=] relation on numbers is not a partial function.
This can be shown by contradiction. In short: Assume, for a
contradiction, that [<=] is a partial function. But then, since
[0 <= 0] and [0 <= 1], it follows that [0 = 1]. This is nonsense,
so our assumption was contradictory. *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense.
Case "Proof of assertion".
apply Hc with (x := 0).
apply le_n.
apply le_S. apply le_n.
inversion Nonsense. Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in Logic.v is not a partial
function. *)
Theorem total_relation_not_a_partial_function:
~ (partial_function total_relation).
Proof.
unfold not. unfold partial_function.
intros Hc.
assert (0 = 1) as BS.
apply Hc with (x:=0). apply tot. apply tot. inversion BS.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] defined in Logic.v is a partial
function. *)
Theorem empty_relation_partial_function:
partial_function empty_relation.
Proof.
unfold partial_function. intros.
inversion H.
Qed.
(** [] *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans' :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
Case "le_n". apply Hnm.
Case "le_S". apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans' with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using le_trans. Do this.*)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
apply le_S. apply Hnm.
apply le_S. apply IHHm'o.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
inversion Hmo.
apply le_S. inversion Hmo. subst. apply Hnm.
subst. apply IHo'. apply H0.
Qed.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
apply le_S. apply le_n.
apply H. Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
intros.
inversion H. apply le_n.
subst. apply le_Sn_le. apply H1.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~(S n <= n)]
A formal proof of this is an optional exercise below, but try
the informal proof without doing the formal proof first.
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
intros n.
induction n.
unfold not. intros. inversion H.
unfold not. intros. inversion H.
unfold not in IHn. apply le_Sn_le in H.
assert ((S n <= S n) -> (S n <= n)).
intros. rewrite -> H1 at 1. apply le_n.
apply IHn. apply H0. apply H.
subst. unfold not in IHn. apply IHn.
apply le_Sn_le in H1. apply H1.
Qed.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, here are a few more common ones.
A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
unfold not.
unfold symmetric.
intros.
assert (0 <= 1 -> 1 <= 0).
apply H.
assert (0 <= 1).
apply le_S. apply le_n.
apply H0 in H1.
inversion H1.
Qed.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
unfold antisymmetric.
intros.
inversion H. reflexivity. subst.
assert (S m <= m).
apply le_trans with (m:= a). apply H0. apply H1.
assert (False -> a = S m).
intros. inversion H3.
apply H3.
apply le_Sn_n in H2. apply H2.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
intros.
Case "p >=0".
intros.
inversion H. subst. apply le_S_n. apply H0.
subst.
apply le_S_n.
apply le_trans with (m:=S m0).
apply le_S. apply H1. apply H0.
Qed.
(** [] *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
Case "refl". apply le_reflexive.
split.
Case "antisym". apply le_antisymmetric.
Case "transitive.". apply le_trans'. Qed.
(* ########################################################### *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y ->
clos_refl_trans R y z ->
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
Case "->".
intro H. induction H.
SCase "le_n". apply rt_refl.
SCase "le_S".
apply rt_trans with m. apply IHle. apply rt_step. apply nn.
Case "<-".
intro H. induction H.
SCase "rt_step". inversion H. apply le_S. apply le_n.
SCase "rt_refl". apply le_n.
SCase "rt_trans".
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is
natural -- it says, explicitly, that the reflexive and transitive
closure of [R] is the least relation that includes [R] and that is
closed under rules of reflexivity and transitivity. But it turns
out that this definition is not very convenient for doing
proofs -- the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions.
Here is a more useful definition... *)
Inductive refl_step_closure {X:Type} (R: relation X) : relation X :=
| rsc_refl : forall (x : X), refl_step_closure R x x
| rsc_step : forall (x y z : X),
R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
(** (Note that, aside from the naming of the constructors, this
definition is the same as the [multi] step relation used in many
other chapters.) *)
(** (The following [Tactic Notation] definitions are explained in
Imp.v. You can ignore them if you haven't read that chapter
yet.) *)
Tactic Notation "rt_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rt_step" | Case_aux c "rt_refl"
| Case_aux c "rt_trans" ].
Tactic Notation "rsc_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rsc_refl" | Case_aux c "rsc_step" ].
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [refl_step_closure] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Theorem rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> refl_step_closure R x y.
Proof.
intros X R x y H.
apply rsc_step with y. apply H. apply rsc_refl. Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Theorem rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
refl_step_closure R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
Proof.
intros.
induction H. apply H0. apply rsc_step with y. apply H.
apply IHrefl_step_closure. apply H0.
Qed.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> refl_step_closure R x y.
Proof.
intros.
split.
intros.
induction H.
apply rsc_R. apply H.
apply rsc_refl.
apply rsc_trans with y. apply IHclos_refl_trans1. apply IHclos_refl_trans2.
intros.
induction H.
apply rt_refl.
apply rt_trans with y.
apply rt_step. apply H.
apply IHrefl_step_closure.
Qed.
(** [] *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, C1, B1, and0_out, D1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: top_nto1_ddr_se_rx.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: June 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: Example single ended input receiver for DDR clock and data using 2 x BUFIO2
// Serdes factor and number of data lines are set by constants in the code
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
//
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module top_nto1_ddr_se_rx (
input reset, // reset (active high)
input [7:0] datain, // single ended data inputs
input clkin1, clkin2, // TWO single ended clock input
output [63:0] dummy_out) ; // dummy outputs
// Parameters for serdes factor and number of IO pins
parameter integer S = 8 ; // Set the serdes factor to 8
parameter integer D = 8 ; // Set the number of inputs and outputs
parameter integer DS = (D*S)-1 ; // Used for bus widths = serdes factor * number of inputs - 1
wire rst ;
wire [DS:0] rxd ; // Data from serdeses
reg [DS:0] rxr ; // Registered Data from serdeses
reg state ;
reg bslip ;
reg [3:0] count ;
assign rst = reset ; // active high reset pin
assign dummy_out = rxr ;
// Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_ddr_s8_se #(
.S (S))
inst_clkin (
.clkin1 (clkin1),
.clkin2 (clkin2),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_x1 (rx_bufg_x1));
// Data Inputs
serdes_1_to_n_data_ddr_s8_se #(
.S (S),
.D (D),
.USE_PD ("TRUE")) // Enables use of the phase detector - will require 2 input serdes whatever the serdes ratio required
inst_datain (
.use_phase_detector (1'b1), // '1' enables the phase detector logic
.datain (datain),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bslip),
.reset (rst),
.data_out (rxd),
.debug_in (2'b00),
.debug ());
always @ (posedge rx_bufg_x1 or posedge rst) // example bitslip logic, if required
begin
if (rst == 1'b1) begin
state <= 0 ;
bslip <= 1'b0 ;
count <= 4'b0000 ;
end
else begin
if (state == 0) begin
if (rxd[63:60] != 4'h3) begin
bslip <= 1'b1 ; // bitslip needed
state <= 1 ;
count <= 4'b0000 ;
end
end
else if (state == 1) begin
bslip <= 1'b0 ; // bitslip low
count <= count + 4'b0001 ;
if (count == 4'b1111) begin
state <= 0;
end
end
end
end
always @ (posedge rx_bufg_x1) // process received data
begin
rxr <= rxd ;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLYGATE4SD3_PP_SYMBOL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlygate4sd3 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_PP_SYMBOL_V
|
/**
* mcrom_tb.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "microcodedefs.v"
module mcrom_tb;
/* input and signals */
reg [ 5 : 0] offset;
reg clk;
/* output */
wire [`MCROM_WIDTH - 1 : 0] mc_word;
/* unit under testing */
microcode_rom uut (
.offset(offset),
.mc_word(mc_word)
);
initial begin
/* initialize signals */
offset = 0;
clk = 0;
/* end simulation after 1000 ticks */
#1000 $finish;
end
always
#50 clk = ~clk;
always @(posedge clk)
offset = offset + 1;
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
/*************************************************************************
* This file is part of Stierlitz: *
* https://github.com/asciilifeform/Stierlitz *
*************************************************************************/
/**************************************************************************
* (c) Copyright 2012 Stanislav Datskovskiy *
* http://www.loper-os.org *
**************************************************************************
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
* *
*************************************************************************/
/**************************************************************************/
module stierlitz
(clk,
reset,
enable,
/* Control wiring */
bus_ready,
bus_address,
bus_data,
bus_rw,
bus_start_op,
/* CY7C67300 wiring */
cy_hpi_address,
cy_hpi_data,
cy_hpi_oen,
cy_hpi_wen,
cy_hpi_csn,
cy_hpi_irq,
cy_hpi_resetn
);
/**************************************************************************/
localparam [1:0] /* The four HPI addresses: */
HPI_REG_DMA_DATA = 2'b00, /* Put or get DMA data. (R/W) */
HPI_REG_MAILBOX = 2'b01, /* Send or receive data using Mailbox. (R/W) */
HPI_REG_DMA_ADDRESS = 2'b10, /* Latch address for start of DMA transaction. (W) */
HPI_REG_STATUS = 2'b11; /* Read chip status register, for free. (R) */
localparam [2:0]
STATE_IDLE = 0,
STATE_MBX_READ_1 = 1,
STATE_MBX_READ_2 = 2,
STATE_MBX_WRITE_1 = 3,
STATE_MBX_WRITE_2 = 4,
STATE_CMD = 5,
STATE_BUS_READ = 6,
STATE_BUS_WRITE = 7;
/**************************************************************************/
/**************************************************************************/
/* System */
input wire clk; /* ? MHz (? x max HPI freq.) */
input wire reset; /* Active-high */
input wire enable; /* Active-high. */
/* Bus interface */
output wire [40:0] bus_address; /* LBA of active block and block offset. */
inout wire [7:0] bus_data; /* Data in/out on bus. */
output wire bus_rw; /* Bus Op type: 1=Read 0=Write*/
output wire bus_start_op; /* Start of operation (active-high.) */
input wire bus_ready; /* Bus is ready (high) if no op is in progress. */
/* Connections to CY7C67300 */
output wire [1:0] cy_hpi_address; /* Select HPI register. */
inout wire [15:0] cy_hpi_data; /* Bidirectional HPI data. */
output wire cy_hpi_oen; /* HPI Read Enable (active-low) */
output wire cy_hpi_wen; /* HPI Write Enable (active-low) */
output wire cy_hpi_csn; /* HPI Chip Select (active-low) */
input wire cy_hpi_irq; /* HPI IRQ line (active-high) */
output wire cy_hpi_resetn; /* HPI Chip Reset (active-low) */
/**************************************************************************/
/**************************************************************************/
/* Bus (user) side */
reg [7:0] LBA [3:0]; /* Current LBA address */
reg [8:0] byte_offset; /* Offset of current byte in block. */
assign bus_address[8:0] = byte_offset;
assign bus_address[16:9] = LBA[0];
assign bus_address[24:17] = LBA[1];
assign bus_address[32:25] = LBA[2];
assign bus_address[40:33] = LBA[3];
reg [7:0] bus_byte_out;
reg bus_rw_control; /* Bus Op type: 1=Read 0=Write*/
assign bus_rw = bus_rw_control;
assign bus_data = bus_rw_control ? 8'bz : bus_byte_out;
reg bus_op;
assign bus_start_op = bus_op;
/**************************************************************************/
/**************************************************************************/
/* HPI side */
assign cy_hpi_csn = ~enable;
assign cy_hpi_resetn = ~reset; /* TODO: proper reset logic? */
assign cy_hpi_address[1:0] = HPI_REG_MAILBOX; /* For now, no DMA support. */
reg read_enable;
reg write_enable;
assign cy_hpi_oen = ~read_enable;
assign cy_hpi_wen = ~write_enable; /* CY latches data on the rising edge of WEN */
wire output_enable;
assign output_enable = write_enable & ~(read_enable) & enable;
reg [15:0] hpi_data_out_reg;
assign cy_hpi_data = output_enable ? hpi_data_out_reg : 16'bz;
reg [15:0] hpi_data_in_reg;
/**************************************************************************/
reg [2:0] hpi_state; /* Current FSM state */
always @(posedge clk, posedge reset)
if (reset)
begin
read_enable <= 0;
write_enable <= 0;
bus_rw_control <= 1;
hpi_data_in_reg <= 0;
hpi_data_out_reg <= 0;
LBA[0] <= 0;
LBA[1] <= 0;
LBA[2] <= 0;
LBA[3] <= 0;
bus_op <= 0;
bus_byte_out <= 0;
byte_offset <= 0;
hpi_state = STATE_IDLE;
end
else
begin
case (hpi_state)
STATE_IDLE:
begin
read_enable <= 0;
write_enable <= 0;
bus_rw_control <= 1;
/* Idle forever until IRQ is received. */
hpi_state = cy_hpi_irq ? STATE_MBX_READ_1 : STATE_IDLE;
end
STATE_MBX_READ_1:
begin
read_enable <= 1;
write_enable <= 0;
hpi_state = STATE_MBX_READ_2;
end
STATE_MBX_READ_2:
begin
read_enable <= 1;
write_enable <= 0;
hpi_data_in_reg <= cy_hpi_data;
hpi_state = STATE_CMD;
end
STATE_MBX_WRITE_1:
begin
read_enable <= 0;
write_enable <= 1;
bus_op <= 0;
hpi_state = STATE_MBX_WRITE_2;
end
STATE_MBX_WRITE_2:
begin
read_enable <= 0;
write_enable <= 0;
/* Increment block offset only if op is done. */
byte_offset <= bus_ready ? (byte_offset + 1) : byte_offset;
hpi_state = STATE_IDLE;
end
STATE_CMD:
begin
read_enable <= 0;
write_enable <= 0;
case (hpi_data_in_reg[15:14])
2'b00:
begin
/* Set nth byte of LBA address (0...3) */
LBA[(hpi_data_in_reg[9:8])] <= hpi_data_in_reg[7:0];
byte_offset <= 0; /* Reset block offset when setting LBA */
hpi_state = STATE_IDLE;
end
2'b10:
begin
/* HPI byte will be written on bus. */
bus_byte_out <= hpi_data_in_reg[7:0];
bus_rw_control <= 0; /* WRITE */
hpi_state = STATE_BUS_WRITE;
end
2'b01:
begin
/* Byte will be read from bus and sent back on HPI. */
bus_rw_control <= 1; /* READ */
bus_op <= 1;
hpi_state = STATE_BUS_READ;
end
default:
begin
/* Malformed command? Do nothing. */
hpi_state = STATE_IDLE;
end
endcase // case (hpi_data_in_reg[15:14])
end
STATE_BUS_READ:
begin
read_enable <= 0;
write_enable <= 0;
hpi_data_out_reg[7:0] <= bus_data; /* Read a byte off the bus. */
/* Spin until the bus is READY again. Then send back the byte read. */
hpi_state = bus_ready ? STATE_MBX_WRITE_1 : STATE_BUS_READ;
end
STATE_BUS_WRITE:
begin
read_enable <= 0;
write_enable <= 0;
bus_op <= 1;
/* Spin until the bus is READY again. Then write back byte written. */
hpi_state = bus_ready ? STATE_MBX_WRITE_1 : STATE_BUS_WRITE;
end
default:
begin
read_enable <= 0;
write_enable <= 0;
hpi_state = STATE_IDLE;
end
endcase // case (state)
end // else: !if(reset)
/**************************************************************************/
endmodule
/**************************************************************************/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_M_V
`define SKY130_FD_SC_LP__OR3_M_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_m (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_m (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_M_V
|
// file: sdram_clk_gen.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______400.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary______________50____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "sdram_clk_gen,clk_wiz_v3_6,{component_name=sdram_clk_gen,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module sdram_clk_gen
(// Clock in ports
input clk_in,
// Clock out ports
output clk_out
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (clk_in));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (1),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf
(.O (clk_out),
.I (clkfx));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD3_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD3_BLACKBOX_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd3 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD3_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// software programmable clock generator (still needs a reference input!)
module axi_clkgen (
// clocks
clk,
clk_0,
clk_1,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_CLKIN_PERIOD = 5.0;
parameter PCORE_VCO_DIV = 11;
parameter PCORE_VCO_MUL = 49;
parameter PCORE_CLK0_DIV = 6;
parameter PCORE_CLK1_DIV = 6;
// clocks
input clk;
output clk_0;
output clk_1;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// reset and clocks
wire mmcm_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// processor interface
up_clkgen i_up_clkgen (
.mmcm_rst (mmcm_rst),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// mmcm instantiations
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (PCORE_CLKIN_PERIOD),
.MMCM_VCO_DIV (PCORE_VCO_DIV),
.MMCM_VCO_MUL (PCORE_VCO_MUL),
.MMCM_CLK0_DIV (PCORE_CLK0_DIV),
.MMCM_CLK1_DIV (PCORE_CLK1_DIV))
i_mmcm_drp (
.clk (clk),
.mmcm_rst (mmcm_rst),
.mmcm_clk_0 (clk_0),
.mmcm_clk_1 (clk_1),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// vim:set shiftwidth=3 softtabstop=3 expandtab:
module register_file (rsel, wsel, rdata, wdata, wen, rst, clk);
input [5:0] rsel, wsel;
output [32:0] rdata;
input [32:0] wdata;
input wen, rst, clk;
register zero(.wen(wen), .rst(rst), .clk(clk));
register at(.wen(wen), .rst(rst), .clk(clk));
register v0(.wen(wen), .rst(rst), .clk(clk));
register v1(.wen(wen), .rst(rst), .clk(clk));
register a0(.wen(wen), .rst(rst), .clk(clk));
register a1(.wen(wen), .rst(rst), .clk(clk));
register a2(.wen(wen), .rst(rst), .clk(clk));
register a3(.wen(wen), .rst(rst), .clk(clk));
register t0(.wen(wen), .rst(rst), .clk(clk));
register t1(.wen(wen), .rst(rst), .clk(clk));
register t2(.wen(wen), .rst(rst), .clk(clk));
register t3(.wen(wen), .rst(rst), .clk(clk));
register t4(.wen(wen), .rst(rst), .clk(clk));
register t5(.wen(wen), .rst(rst), .clk(clk));
register t6(.wen(wen), .rst(rst), .clk(clk));
register t7(.wen(wen), .rst(rst), .clk(clk));
register s0(.wen(wen), .rst(rst), .clk(clk));
register s1(.wen(wen), .rst(rst), .clk(clk));
register s2(.wen(wen), .rst(rst), .clk(clk));
register s3(.wen(wen), .rst(rst), .clk(clk));
register s4(.wen(wen), .rst(rst), .clk(clk));
register s5(.wen(wen), .rst(rst), .clk(clk));
register s6(.wen(wen), .rst(rst), .clk(clk));
register s7(.wen(wen), .rst(rst), .clk(clk));
register t8(.wen(wen), .rst(rst), .clk(clk));
register t9(.wen(wen), .rst(rst), .clk(clk));
register k0(.wen(wen), .rst(rst), .clk(clk));
register k1(.wen(wen), .rst(rst), .clk(clk));
register gp(.wen(wen), .rst(rst), .clk(clk));
register sp(.wen(wen), .rst(rst), .clk(clk));
register fp(.wen(wen), .rst(rst), .clk(clk));
register ra(.wen(wen), .rst(rst), .clk(clk));
assign zero.in = 0;
always @(posedge clk) begin
if(wen) begin
case(wsel)
0: zero.in = wdata;
1: at.in = wdata;
2: v0.in = wdata;
3: v1.in = wdata;
4: a0.in = wdata;
5: a1.in = wdata;
6: a2.in = wdata;
7: a3.in = wdata;
8: t0.in = wdata;
9: t1.in = wdata;
10: t2.in = wdata;
11: t3.in = wdata;
12: t4.in = wdata;
13: t5.in = wdata;
14: t6.in = wdata;
15: t7.in = wdata;
16: s0.in = wdata;
17: s1.in = wdata;
18: s2.in = wdata;
19: s3.in = wdata;
20: s4.in = wdata;
21: s5.in = wdata;
22: s6.in = wdata;
23: s7.in = wdata;
24: t8.in = wdata;
25: t9.in = wdata;
26: k0.in = wdata;
27: k1.in = wdata;
28: gp.in = wdata;
29: sp.in = wdata;
30: fp.in = wdata;
31: ra.in = wdata;
endcase
end else begin
case(rsel)
0: rdata = zero.out;
1: rdata = at.out;
2: rdata = v0.out;
3: rdata = v1.out;
4: rdata = a0.out;
5: rdata = a1.out;
6: rdata = a2.out;
7: rdata = a3.out;
8: rdata = t0.out;
9: rdata = t1.out;
10: rdata = t2.out;
11: rdata = t3.out;
12: rdata = t4.out;
13: rdata = t5.out;
14: rdata = t6.out;
15: rdata = t7.out;
16: rdata = s0.out;
17: rdata = s1.out;
18: rdata = s2.out;
19: rdata = s3.out;
20: rdata = s4.out;
21: rdata = s5.out;
22: rdata = s6.out;
23: rdata = s7.out;
24: rdata = t8.out;
25: rdata = t9.out;
26: rdata = k0.out;
27: rdata = k1.out;
28: rdata = gp.out;
29: rdata = sp.out;
30: rdata = fp.out;
31: rdata = ra.out;
endcase
end
end
endmodule |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 09:37:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_vga_sync_0_0 -prefix
// system_vga_sync_0_0_ system_vga_sync_0_0_sim_netlist.v
// Design : system_vga_sync_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_sync_0_0,vga_sync,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_sync,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_sync_0_0
(clk_25,
rst,
active,
hsync,
vsync,
xaddr,
yaddr);
input clk_25;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
wire active;
wire clk_25;
wire hsync;
wire rst;
wire vsync;
wire [9:0]xaddr;
wire [9:0]yaddr;
system_vga_sync_0_0_vga_sync U0
(.active(active),
.clk_25(clk_25),
.hsync(hsync),
.rst(rst),
.vsync(vsync),
.xaddr(xaddr),
.yaddr(yaddr));
endmodule
module system_vga_sync_0_0_vga_sync
(xaddr,
yaddr,
hsync,
vsync,
active,
clk_25,
rst);
output [9:0]xaddr;
output [9:0]yaddr;
output hsync;
output vsync;
output active;
input clk_25;
input rst;
wire active;
wire active_INST_0_i_1_n_0;
wire clk_25;
wire [9:0]h_count_next;
wire \h_count_reg[4]_i_1_n_0 ;
wire \h_count_reg[5]_i_2_n_0 ;
wire \h_count_reg[9]_i_2_n_0 ;
wire \h_count_reg[9]_i_3_n_0 ;
wire \h_count_reg[9]_i_4_n_0 ;
wire h_sync_next;
wire hsync;
wire [9:0]p_0_in;
wire rst;
wire sel;
wire \v_count_reg[3]_i_2_n_0 ;
wire \v_count_reg[6]_i_1_n_0 ;
wire \v_count_reg[9]_i_3_n_0 ;
wire \v_count_reg[9]_i_4_n_0 ;
wire \v_count_reg[9]_i_5_n_0 ;
wire v_sync_next;
wire vsync;
wire [9:0]xaddr;
wire [9:0]yaddr;
LUT5 #(
.INIT(32'h000002AA))
active_INST_0
(.I0(active_INST_0_i_1_n_0),
.I1(xaddr[8]),
.I2(xaddr[7]),
.I3(xaddr[9]),
.I4(yaddr[9]),
.O(active));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h7FFF))
active_INST_0_i_1
(.I0(yaddr[6]),
.I1(yaddr[5]),
.I2(yaddr[7]),
.I3(yaddr[8]),
.O(active_INST_0_i_1_n_0));
LUT1 #(
.INIT(2'h1))
\h_count_reg[0]_i_1
(.I0(xaddr[0]),
.O(h_count_next[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\h_count_reg[1]_i_1
(.I0(xaddr[0]),
.I1(xaddr[1]),
.O(h_count_next[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h78))
\h_count_reg[2]_i_1
(.I0(xaddr[0]),
.I1(xaddr[1]),
.I2(xaddr[2]),
.O(h_count_next[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h6AAA))
\h_count_reg[3]_i_1
(.I0(xaddr[3]),
.I1(xaddr[0]),
.I2(xaddr[1]),
.I3(xaddr[2]),
.O(h_count_next[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\h_count_reg[4]_i_1
(.I0(xaddr[4]),
.I1(xaddr[2]),
.I2(xaddr[1]),
.I3(xaddr[0]),
.I4(xaddr[3]),
.O(\h_count_reg[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF00000000FFBF))
\h_count_reg[5]_i_1
(.I0(xaddr[6]),
.I1(xaddr[8]),
.I2(xaddr[9]),
.I3(xaddr[7]),
.I4(\h_count_reg[5]_i_2_n_0 ),
.I5(xaddr[5]),
.O(h_count_next[5]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
\h_count_reg[5]_i_2
(.I0(xaddr[2]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[3]),
.I4(xaddr[4]),
.O(\h_count_reg[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hAA6A))
\h_count_reg[6]_i_1
(.I0(xaddr[6]),
.I1(xaddr[4]),
.I2(xaddr[5]),
.I3(\h_count_reg[9]_i_3_n_0 ),
.O(h_count_next[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h9AAAAAAA))
\h_count_reg[7]_i_1
(.I0(xaddr[7]),
.I1(\h_count_reg[9]_i_3_n_0 ),
.I2(xaddr[5]),
.I3(xaddr[4]),
.I4(xaddr[6]),
.O(h_count_next[7]));
LUT5 #(
.INIT(32'hFF0B00B0))
\h_count_reg[8]_i_1
(.I0(\h_count_reg[9]_i_2_n_0 ),
.I1(xaddr[4]),
.I2(\h_count_reg[9]_i_4_n_0 ),
.I3(\h_count_reg[9]_i_3_n_0 ),
.I4(xaddr[8]),
.O(h_count_next[8]));
LUT6 #(
.INIT(64'hF0FBFBFB0B000000))
\h_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_2_n_0 ),
.I1(xaddr[4]),
.I2(\h_count_reg[9]_i_3_n_0 ),
.I3(\h_count_reg[9]_i_4_n_0 ),
.I4(xaddr[8]),
.I5(xaddr[9]),
.O(h_count_next[9]));
LUT5 #(
.INIT(32'hFFFFEFFF))
\h_count_reg[9]_i_2
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(xaddr[7]),
.O(\h_count_reg[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7FFF))
\h_count_reg[9]_i_3
(.I0(xaddr[3]),
.I1(xaddr[0]),
.I2(xaddr[1]),
.I3(xaddr[2]),
.O(\h_count_reg[9]_i_3_n_0 ));
LUT4 #(
.INIT(16'h8000))
\h_count_reg[9]_i_4
(.I0(xaddr[7]),
.I1(xaddr[6]),
.I2(xaddr[5]),
.I3(xaddr[4]),
.O(\h_count_reg[9]_i_4_n_0 ));
FDCE \h_count_reg_reg[0]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[0]),
.Q(xaddr[0]));
FDCE \h_count_reg_reg[1]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[1]),
.Q(xaddr[1]));
FDCE \h_count_reg_reg[2]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[2]),
.Q(xaddr[2]));
FDCE \h_count_reg_reg[3]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[3]),
.Q(xaddr[3]));
FDCE \h_count_reg_reg[4]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(\h_count_reg[4]_i_1_n_0 ),
.Q(xaddr[4]));
FDCE \h_count_reg_reg[5]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[5]),
.Q(xaddr[5]));
FDCE \h_count_reg_reg[6]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[6]),
.Q(xaddr[6]));
FDCE \h_count_reg_reg[7]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[7]),
.Q(xaddr[7]));
FDCE \h_count_reg_reg[8]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[8]),
.Q(xaddr[8]));
FDCE \h_count_reg_reg[9]
(.C(clk_25),
.CE(1'b1),
.CLR(rst),
.D(h_count_next[9]),
.Q(xaddr[9]));
LUT6 #(
.INIT(64'h00002AA800000000))
h_sync_reg_i_1
(.I0(xaddr[7]),
.I1(xaddr[6]),
.I2(xaddr[5]),
.I3(xaddr[4]),
.I4(xaddr[8]),
.I5(xaddr[9]),
.O(h_sync_next));
FDPE #(
.INIT(1'b0))
h_sync_reg_reg
(.C(clk_25),
.CE(1'b1),
.D(h_sync_next),
.PRE(rst),
.Q(hsync));
LUT6 #(
.INIT(64'h5555555545555555))
\v_count_reg[0]_i_1
(.I0(yaddr[0]),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(yaddr[2]),
.I4(yaddr[3]),
.I5(yaddr[7]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\v_count_reg[1]_i_1
(.I0(yaddr[0]),
.I1(yaddr[1]),
.O(p_0_in[1]));
LUT6 #(
.INIT(64'h55AA55AA45AA55AA))
\v_count_reg[2]_i_1
(.I0(\v_count_reg[3]_i_2_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(yaddr[2]),
.I4(yaddr[3]),
.I5(yaddr[7]),
.O(p_0_in[2]));
LUT6 #(
.INIT(64'h55FFAA0045FFAA00))
\v_count_reg[3]_i_1
(.I0(\v_count_reg[3]_i_2_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(yaddr[2]),
.I4(yaddr[3]),
.I5(yaddr[7]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h8))
\v_count_reg[3]_i_2
(.I0(yaddr[0]),
.I1(yaddr[1]),
.O(\v_count_reg[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\v_count_reg[4]_i_1
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[3]),
.I3(yaddr[0]),
.I4(yaddr[1]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\v_count_reg[5]_i_1
(.I0(yaddr[5]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[3]),
.I4(yaddr[2]),
.I5(yaddr[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h6A))
\v_count_reg[6]_i_1
(.I0(yaddr[6]),
.I1(\v_count_reg[9]_i_5_n_0 ),
.I2(yaddr[5]),
.O(\v_count_reg[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h6AAA))
\v_count_reg[7]_i_1
(.I0(yaddr[7]),
.I1(yaddr[5]),
.I2(\v_count_reg[9]_i_5_n_0 ),
.I3(yaddr[6]),
.O(p_0_in[7]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\v_count_reg[8]_i_1
(.I0(yaddr[8]),
.I1(yaddr[6]),
.I2(\v_count_reg[9]_i_5_n_0 ),
.I3(yaddr[5]),
.I4(yaddr[7]),
.O(p_0_in[8]));
LUT6 #(
.INIT(64'h0000000000001000))
\v_count_reg[9]_i_1
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(xaddr[7]),
.I5(\h_count_reg[5]_i_2_n_0 ),
.O(sel));
LUT5 #(
.INIT(32'hD0D00DD0))
\v_count_reg[9]_i_2
(.I0(\v_count_reg[9]_i_3_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(yaddr[9]),
.I3(\v_count_reg[9]_i_5_n_0 ),
.I4(active_INST_0_i_1_n_0),
.O(p_0_in[9]));
LUT4 #(
.INIT(16'h0080))
\v_count_reg[9]_i_3
(.I0(yaddr[9]),
.I1(yaddr[2]),
.I2(yaddr[3]),
.I3(yaddr[7]),
.O(\v_count_reg[9]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\v_count_reg[9]_i_4
(.I0(yaddr[1]),
.I1(yaddr[0]),
.I2(yaddr[6]),
.I3(yaddr[8]),
.I4(yaddr[4]),
.I5(yaddr[5]),
.O(\v_count_reg[9]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h80000000))
\v_count_reg[9]_i_5
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[3]),
.I3(yaddr[0]),
.I4(yaddr[1]),
.O(\v_count_reg[9]_i_5_n_0 ));
FDCE \v_count_reg_reg[0]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[0]),
.Q(yaddr[0]));
FDCE \v_count_reg_reg[1]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[1]),
.Q(yaddr[1]));
FDCE \v_count_reg_reg[2]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[2]),
.Q(yaddr[2]));
FDCE \v_count_reg_reg[3]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[3]),
.Q(yaddr[3]));
FDCE \v_count_reg_reg[4]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[4]),
.Q(yaddr[4]));
FDCE \v_count_reg_reg[5]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[5]),
.Q(yaddr[5]));
FDCE \v_count_reg_reg[6]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(\v_count_reg[6]_i_1_n_0 ),
.Q(yaddr[6]));
FDCE \v_count_reg_reg[7]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[7]),
.Q(yaddr[7]));
FDCE \v_count_reg_reg[8]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[8]),
.Q(yaddr[8]));
FDCE \v_count_reg_reg[9]
(.C(clk_25),
.CE(sel),
.CLR(rst),
.D(p_0_in[9]),
.Q(yaddr[9]));
LUT6 #(
.INIT(64'h0000000000040000))
v_sync_reg_i_1
(.I0(yaddr[9]),
.I1(yaddr[3]),
.I2(yaddr[4]),
.I3(yaddr[2]),
.I4(yaddr[1]),
.I5(active_INST_0_i_1_n_0),
.O(v_sync_next));
FDPE #(
.INIT(1'b0))
v_sync_reg_reg
(.C(clk_25),
.CE(1'b1),
.D(v_sync_next),
.PRE(rst),
.Q(vsync));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_nios2_qsys_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEV",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEV",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SEDFXBP_BLACKBOX_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_BLACKBOX_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:06:25 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n3035, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM,
ZERO_FLAG_NRM, SIGN_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n544, n545, n546, n547, n548,
n549, n550, n551, n552, n553, n554, n575, n578, n579, n580, n581,
n582, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593,
n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604,
n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638,
n639, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650,
n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672,
n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683,
n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694,
n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705,
n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716,
n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727,
n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738,
n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749,
n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760,
n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771,
n772, n773, n774, n775, n776, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816,
n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827,
n828, n829, n830, n831, n832, n833, n834, n835, n842, n843, n844,
n845, n846, n847, n848, n850, n851, n853, n856, n857, n862, n864,
n876, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n617, n953,
n958, n959, n960, n961, n963, n964, n965, n966, n967, n968, n970,
n971, n972, n973, n974, n975, n976, n977, n978, n979, n980, n981,
n982, n983, n984, n985, n986, n987, n988, n989, n990, n991, n992,
n993, n994, n995, n996, n997, n998, n999, n1000, n1005, n1006, n1010,
n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1042,
n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052,
n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1061, n1062, n1063,
n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073,
n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083,
n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093,
n1094, n1095, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396,
n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406,
n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416,
n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426,
n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436,
n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446,
n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456,
n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466,
n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476,
n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486,
n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496,
n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506,
n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516,
n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526,
n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536,
n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1776, n1777,
n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397,
n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407,
n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417,
n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2540,
n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552,
n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562,
n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572,
n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582,
n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592,
n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602,
n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612,
n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622,
n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632,
n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642,
n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652,
n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662,
n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672,
n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682,
n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692,
n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702,
n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712,
n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722,
n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732,
n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742,
n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752,
n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762,
n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772,
n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782,
n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792,
n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802,
n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812,
n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822,
n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832,
n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842,
n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852,
n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862,
n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872,
n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882,
n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892,
n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2901, n2902, n2903,
n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913,
n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923,
n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933,
n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943,
n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953,
n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963,
n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993,
n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003,
n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013,
n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023,
n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033,
n3034;
wire [3:1] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:6] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [3:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [3:0] LZD_output_NRM2_EW;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [13:12] DmP_mant_SFG_SWR_signed;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n952), .CK(clk), .RN(
n2893), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n2643) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n2893), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n2640) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n951), .CK(clk), .RN(
n2893), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n2645) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n950), .CK(clk), .RN(n2893), .Q(
Shift_reg_FLAGS_7_6), .QN(n2638) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n949), .CK(clk), .RN(n2893), .Q(
Shift_reg_FLAGS_7_5), .QN(n2648) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n948), .CK(clk), .RN(n2893), .Q(
n3035), .QN(n2688) );
DFFRX2TS inst_ShiftRegister_Q_reg_3_ ( .D(n947), .CK(clk), .RN(n2893), .Q(
Shift_reg_FLAGS_7[3]), .QN(n2543) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n945), .CK(clk), .RN(n2893), .Q(
Shift_reg_FLAGS_7[1]), .QN(n2859) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n943), .CK(clk), .RN(n2889), .Q(
intDX_EWSW[0]), .QN(n1028) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n941), .CK(clk), .RN(n2890), .Q(
intDX_EWSW[2]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n940), .CK(clk), .RN(n2890), .Q(
intDX_EWSW[3]), .QN(n1283) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n937), .CK(clk), .RN(n2890), .Q(
intDX_EWSW[6]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n936), .CK(clk), .RN(n2890), .Q(
intDX_EWSW[7]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n935), .CK(clk), .RN(n2890), .Q(
intDX_EWSW[8]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n934), .CK(clk), .RN(n2890), .Q(
intDX_EWSW[9]), .QN(n1247) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n933), .CK(clk), .RN(n2890),
.Q(intDX_EWSW[10]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n932), .CK(clk), .RN(n2890),
.Q(intDX_EWSW[11]), .QN(n1222) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n931), .CK(clk), .RN(n2891),
.Q(intDX_EWSW[12]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n930), .CK(clk), .RN(n2891),
.Q(intDX_EWSW[13]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n929), .CK(clk), .RN(n2891),
.Q(intDX_EWSW[14]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n928), .CK(clk), .RN(n2891),
.Q(intDX_EWSW[15]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n927), .CK(clk), .RN(n2891),
.Q(intDX_EWSW[16]), .QN(n1223) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n926), .CK(clk), .RN(n2891),
.Q(intDX_EWSW[17]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n925), .CK(clk), .RN(n2891),
.Q(intDX_EWSW[18]), .QN(n1242) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n924), .CK(clk), .RN(n2891),
.Q(intDX_EWSW[19]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n923), .CK(clk), .RN(n2891),
.Q(intDX_EWSW[20]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n919), .CK(clk), .RN(n2892),
.Q(intDX_EWSW[24]), .QN(n1259) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n917), .CK(clk), .RN(n2892),
.Q(intDX_EWSW[26]), .QN(n1224) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n915), .CK(clk), .RN(n2892),
.Q(intDX_EWSW[28]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n914), .CK(clk), .RN(n2892),
.Q(intDX_EWSW[29]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n913), .CK(clk), .RN(n2892),
.Q(intDX_EWSW[30]) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n910), .CK(clk), .RN(n1372), .Q(
left_right_SHT2), .QN(n1369) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n909), .CK(clk), .RN(n2886), .Q(
intDY_EWSW[0]), .QN(n2608) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n905), .CK(clk), .RN(n2887), .Q(
intDY_EWSW[4]), .QN(n2594) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n904), .CK(clk), .RN(n2887), .Q(
intDY_EWSW[5]), .QN(n2603) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n903), .CK(clk), .RN(n2887), .Q(
intDY_EWSW[6]), .QN(n2598) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n900), .CK(clk), .RN(n2887), .Q(
intDY_EWSW[9]), .QN(n2588) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n899), .CK(clk), .RN(n2887),
.Q(intDY_EWSW[10]), .QN(n2597) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n898), .CK(clk), .RN(n2887),
.Q(intDY_EWSW[11]), .QN(n2592) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n897), .CK(clk), .RN(n2888),
.Q(intDY_EWSW[12]), .QN(n2593) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n896), .CK(clk), .RN(n2888),
.Q(intDY_EWSW[13]), .QN(n2602) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n895), .CK(clk), .RN(n2888),
.Q(intDY_EWSW[14]), .QN(n2584) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n893), .CK(clk), .RN(n2888),
.Q(intDY_EWSW[16]), .QN(n2607) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n891), .CK(clk), .RN(n2888),
.Q(intDY_EWSW[18]), .QN(n2606) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n889), .CK(clk), .RN(n2888),
.Q(intDY_EWSW[20]), .QN(n2605) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n888), .CK(clk), .RN(n2888),
.Q(intDY_EWSW[21]), .QN(n2591) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n887), .CK(clk), .RN(n2889),
.Q(intDY_EWSW[22]), .QN(n2583) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n886), .CK(clk), .RN(n2889),
.Q(intDY_EWSW[23]), .QN(n2590) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n885), .CK(clk), .RN(n2889),
.Q(intDY_EWSW[24]), .QN(n2582) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n884), .CK(clk), .RN(n2889),
.Q(intDY_EWSW[25]), .QN(n2604) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n883), .CK(clk), .RN(n2889),
.Q(intDY_EWSW[26]), .QN(n2599) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n882), .CK(clk), .RN(n2889),
.Q(intDY_EWSW[27]), .QN(n2589) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n881), .CK(clk), .RN(n2889),
.Q(intDY_EWSW[28]), .QN(n2585) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n880), .CK(clk), .RN(n2889),
.Q(intDY_EWSW[29]), .QN(n2601) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n879), .CK(clk), .RN(n2892),
.Q(intDY_EWSW[30]), .QN(n2600) );
DFFRX4TS R_208 ( .D(n851), .CK(clk), .RN(n999), .Q(shift_value_SHT2_EWR[2])
);
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n850), .CK(clk), .RN(n1366), .Q(
shift_value_SHT2_EWR[3]), .QN(n2586) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n843), .CK(clk), .RN(n1372),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_11_ ( .D(n823), .CK(clk), .RN(n997), .Q(
DMP_EXP_EWSW[11]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_13_ ( .D(n821), .CK(clk), .RN(n1364), .Q(
DMP_EXP_EWSW[13]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_16_ ( .D(n818), .CK(clk), .RN(n2868), .Q(
DMP_EXP_EWSW[16]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n811), .CK(clk), .RN(n2882), .Q(
DMP_EXP_EWSW[23]), .QN(n2647) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n810), .CK(clk), .RN(n2883), .Q(
DMP_EXP_EWSW[24]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n808), .CK(clk), .RN(n2884), .Q(
DMP_EXP_EWSW[26]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_28_ ( .D(n806), .CK(clk), .RN(n2885), .Q(
DMP_EXP_EWSW[28]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_29_ ( .D(n805), .CK(clk), .RN(n2886), .Q(
DMP_EXP_EWSW[29]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_30_ ( .D(n804), .CK(clk), .RN(n2886), .Q(
DMP_EXP_EWSW[30]) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n803), .CK(clk), .RN(n2881), .Q(
OP_FLAG_EXP) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n800), .CK(clk), .RN(n1026), .Q(
DMP_SHT1_EWSW[0]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n799), .CK(clk), .RN(n1026), .Q(
DMP_SHT2_EWSW[0]), .QN(n2566) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n798), .CK(clk), .RN(n1026), .Q(
DMP_SFG[0]), .QN(n2630) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n797), .CK(clk), .RN(n2875), .Q(
DMP_SHT1_EWSW[1]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n794), .CK(clk), .RN(n2874), .Q(
DMP_SHT1_EWSW[2]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n793), .CK(clk), .RN(n2874), .Q(
DMP_SHT2_EWSW[2]), .QN(n2568) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n792), .CK(clk), .RN(n2874), .Q(
DMP_SFG[2]), .QN(n2628) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n791), .CK(clk), .RN(n2876), .Q(
DMP_SHT1_EWSW[3]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n790), .CK(clk), .RN(n2876), .Q(
DMP_SHT2_EWSW[3]), .QN(n2624) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n788), .CK(clk), .RN(n2881), .Q(
DMP_SHT1_EWSW[4]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n787), .CK(clk), .RN(n2881), .Q(
DMP_SHT2_EWSW[4]), .QN(n2621) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n785), .CK(clk), .RN(n1362), .Q(
DMP_SHT1_EWSW[5]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n782), .CK(clk), .RN(n2878), .Q(
DMP_SHT1_EWSW[6]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n781), .CK(clk), .RN(n2871), .Q(
DMP_SHT2_EWSW[6]), .QN(n2565) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n780), .CK(clk), .RN(n2873), .Q(
DMP_SFG[6]), .QN(n2627) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n779), .CK(clk), .RN(n1379), .Q(
DMP_SHT1_EWSW[7]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n2874), .Q(
DMP_SHT2_EWSW[7]), .QN(n2626) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n776), .CK(clk), .RN(n2877), .Q(
DMP_SHT1_EWSW[8]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n775), .CK(clk), .RN(n2877), .Q(
DMP_SHT2_EWSW[8]), .QN(n2623) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n773), .CK(clk), .RN(n1379), .Q(
DMP_SHT1_EWSW[9]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n770), .CK(clk), .RN(n2878), .Q(
DMP_SHT1_EWSW[10]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n769), .CK(clk), .RN(n2878), .Q(
DMP_SHT2_EWSW[10]), .QN(n2564) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n768), .CK(clk), .RN(n2878), .Q(
DMP_SFG[10]), .QN(n2684) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n767), .CK(clk), .RN(n997), .Q(
DMP_SHT1_EWSW[11]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n766), .CK(clk), .RN(n998), .Q(
DMP_SHT2_EWSW[11]), .QN(n2622) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n765), .CK(clk), .RN(n2878), .Q(
DMP_SFG[11]), .QN(n2576) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n764), .CK(clk), .RN(n997), .Q(
DMP_SHT1_EWSW[12]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n763), .CK(clk), .RN(n998), .Q(
DMP_SHT2_EWSW[12]), .QN(n2563) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n761), .CK(clk), .RN(n997), .Q(
DMP_SHT1_EWSW[13]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n759), .CK(clk), .RN(n997), .Q(
DMP_SFG[13]), .QN(n2635) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n758), .CK(clk), .RN(n1359), .Q(
DMP_SHT1_EWSW[14]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n757), .CK(clk), .RN(n1359), .Q(
DMP_SHT2_EWSW[14]), .QN(n2575) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n756), .CK(clk), .RN(n2870), .Q(
DMP_SFG[14]), .QN(n2634) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n755), .CK(clk), .RN(n1355), .Q(
DMP_SHT1_EWSW[15]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n754), .CK(clk), .RN(n977), .Q(
DMP_SHT2_EWSW[15]), .QN(n2574) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n752), .CK(clk), .RN(n2868), .Q(
DMP_SHT1_EWSW[16]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n751), .CK(clk), .RN(n2868), .Q(
DMP_SHT2_EWSW[16]), .QN(n2573) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n749), .CK(clk), .RN(n2868), .Q(
DMP_SHT1_EWSW[17]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n748), .CK(clk), .RN(n2868), .Q(
DMP_SHT2_EWSW[17]), .QN(n2572) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n747), .CK(clk), .RN(n2868), .Q(
DMP_SFG[17]), .QN(n2675) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n746), .CK(clk), .RN(n2868), .Q(
DMP_SHT1_EWSW[18]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n745), .CK(clk), .RN(n2868), .Q(
DMP_SHT2_EWSW[18]), .QN(n2571) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n744), .CK(clk), .RN(n2868), .Q(
DMP_SFG[18]), .QN(n2633) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n739), .CK(clk), .RN(n1360), .Q(
DMP_SHT2_EWSW[20]), .QN(n2554) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n737), .CK(clk), .RN(n2873), .Q(
DMP_SHT1_EWSW[21]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n736), .CK(clk), .RN(n2873), .Q(
DMP_SHT2_EWSW[21]), .QN(n2553) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n734), .CK(clk), .RN(n2873), .Q(
DMP_SHT1_EWSW[22]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n733), .CK(clk), .RN(n2873), .Q(
DMP_SHT2_EWSW[22]), .QN(n2552) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n732), .CK(clk), .RN(n1371), .Q(
DMP_SFG[22]), .QN(n2617) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n731), .CK(clk), .RN(n2882), .Q(
DMP_SHT1_EWSW[23]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n2882), .Q(
DMP_SHT2_EWSW[23]), .QN(n2561) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n728), .CK(clk), .RN(n2882), .Q(
DMP_exp_NRM_EW[0]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n727), .CK(clk), .RN(n2882), .Q(
DMP_exp_NRM2_EW[0]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n726), .CK(clk), .RN(n2883), .Q(
DMP_SHT1_EWSW[24]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n723), .CK(clk), .RN(n2882), .Q(
DMP_exp_NRM_EW[1]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n2882), .Q(
DMP_exp_NRM2_EW[1]), .QN(n2858) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n718), .CK(clk), .RN(n2883), .Q(
DMP_exp_NRM_EW[2]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n717), .CK(clk), .RN(n2883), .Q(
DMP_exp_NRM2_EW[2]), .QN(n2854) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n716), .CK(clk), .RN(n2884), .Q(
DMP_SHT1_EWSW[26]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n715), .CK(clk), .RN(n2884), .Q(
DMP_SHT2_EWSW[26]), .QN(n2559) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n713), .CK(clk), .RN(n2883), .Q(
DMP_exp_NRM_EW[3]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n712), .CK(clk), .RN(n2883), .Q(
DMP_exp_NRM2_EW[3]), .QN(n2850) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n711), .CK(clk), .RN(n2884), .Q(
DMP_SHT1_EWSW[27]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n710), .CK(clk), .RN(n2884), .Q(
DMP_SHT2_EWSW[27]), .QN(n2558) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n708), .CK(clk), .RN(n2884), .Q(
DMP_exp_NRM_EW[4]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n2884), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n706), .CK(clk), .RN(n2885), .Q(
DMP_SHT1_EWSW[28]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n705), .CK(clk), .RN(n2885), .Q(
DMP_SHT2_EWSW[28]), .QN(n2557) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n2885), .Q(
DMP_exp_NRM_EW[5]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n2885), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1029) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n701), .CK(clk), .RN(n2886), .Q(
DMP_SHT1_EWSW[29]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n700), .CK(clk), .RN(n2885), .Q(
DMP_SHT2_EWSW[29]), .QN(n2556) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n698), .CK(clk), .RN(n2885), .Q(
DMP_exp_NRM_EW[6]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n697), .CK(clk), .RN(n2885), .Q(
DMP_exp_NRM2_EW[6]), .QN(n2861) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n696), .CK(clk), .RN(n2886), .Q(
DMP_SHT1_EWSW[30]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n695), .CK(clk), .RN(n2886), .Q(
DMP_SHT2_EWSW[30]), .QN(n2555) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n693), .CK(clk), .RN(n2886), .Q(
DMP_exp_NRM_EW[7]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n692), .CK(clk), .RN(n2886), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_0_ ( .D(n691), .CK(clk), .RN(n993), .Q(
DmP_EXP_EWSW[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_1_ ( .D(n689), .CK(clk), .RN(n1355), .Q(
DmP_EXP_EWSW[1]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n680), .CK(clk), .RN(n1362), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n676), .CK(clk), .RN(n977), .Q(
DmP_mant_SHT1_SW[7]), .QN(n2613) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n674), .CK(clk), .RN(n2865), .Q(
DmP_mant_SHT1_SW[8]), .QN(n2673) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n672), .CK(clk), .RN(n977), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_14_ ( .D(n663), .CK(clk), .RN(n2877), .Q(
DmP_EXP_EWSW[14]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n662), .CK(clk), .RN(n2877), .Q(
DmP_mant_SHT1_SW[14]), .QN(n2610) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_16_ ( .D(n659), .CK(clk), .RN(n2875), .Q(
DmP_EXP_EWSW[16]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_19_ ( .D(n653), .CK(clk), .RN(n2878), .Q(
DmP_EXP_EWSW[19]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n652), .CK(clk), .RN(n2878), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n650), .CK(clk), .RN(n1026), .Q(
DmP_mant_SHT1_SW[20]), .QN(n2620) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n648), .CK(clk), .RN(n1026), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_22_ ( .D(n647), .CK(clk), .RN(n2874), .Q(
DmP_EXP_EWSW[22]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n646), .CK(clk), .RN(n2874), .Q(
DmP_mant_SHT1_SW[22]), .QN(n2672) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n645), .CK(clk), .RN(n1359), .Q(
DmP_EXP_EWSW[23]), .QN(n2646) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n643), .CK(clk), .RN(n1359), .Q(
DmP_EXP_EWSW[25]), .QN(n2614) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n641), .CK(clk), .RN(n1371), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n638), .CK(clk), .RN(n984), .Q(
ZERO_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n637), .CK(clk), .RN(n2870), .Q(
ZERO_FLAG_SHT2), .QN(n1552) );
DFFRX2TS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n635), .CK(clk), .RN(n984), .Q(
ZERO_FLAG_NRM) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n632), .CK(clk), .RN(n2881), .Q(
OP_FLAG_SHT1) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n629), .CK(clk), .RN(n2894), .Q(
SIGN_FLAG_SHT1) );
DFFRX2TS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n626), .CK(clk), .RN(n2872), .Q(
SIGN_FLAG_NRM) );
DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n625), .CK(clk), .RN(n2894), .Q(
SIGN_FLAG_SHT1SHT2), .QN(n1554) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n620), .CK(clk), .RN(n2871), .Q(
Raw_mant_NRM_SWR[18]), .QN(n2580) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n613), .CK(clk), .RN(n2871), .Q(
Raw_mant_NRM_SWR[25]), .QN(n2581) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n993), .Q(
Raw_mant_NRM_SWR[1]), .QN(n2615) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n605), .CK(clk), .RN(n1364), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1553) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n999), .Q(
Raw_mant_NRM_SWR[0]), .QN(n2595) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n600), .CK(clk), .RN(n1379), .Q(
Raw_mant_NRM_SWR[2]), .QN(n2545) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n594), .CK(clk), .RN(n2896), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1557) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n2698), .Q(
LZD_output_NRM2_EW[0]), .QN(n2851) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n592), .CK(clk), .RN(n3034), .Q(
DmP_mant_SFG_SWR[4]), .QN(n2651) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n590), .CK(clk), .RN(n2869), .Q(
DmP_mant_SFG_SWR[5]), .QN(n2665) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n589), .CK(clk), .RN(n999), .Q(
Raw_mant_NRM_SWR[7]), .QN(n2846) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n586), .CK(clk), .RN(n2865), .Q(
DmP_mant_SFG_SWR[9]), .QN(n2662) );
DFFRXLTS R_43 ( .D(n584), .CK(clk), .RN(n2896), .QN(n2618) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n581), .CK(clk), .RN(n1366), .Q(
Raw_mant_NRM_SWR[13]), .QN(n2596) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n580), .CK(clk), .RN(n2867), .Q(
DmP_mant_SFG_SWR[11]), .QN(n2653) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n553), .CK(clk), .RN(n2866), .Q(
DmP_mant_SFG_SWR[16]), .QN(n2670) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n552), .CK(clk), .RN(n2866), .Q(
DmP_mant_SFG_SWR[17]), .QN(n2669) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n548), .CK(clk), .RN(n2866), .Q(
DmP_mant_SFG_SWR[21]), .QN(n2657) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n547), .CK(clk), .RN(n2866), .Q(
DmP_mant_SFG_SWR[22]), .QN(n2656) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n546), .CK(clk), .RN(n2866), .Q(
DmP_mant_SFG_SWR[23]), .QN(n2668) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n544), .CK(clk), .RN(n2866), .Q(
DmP_mant_SFG_SWR[25]), .QN(n2616) );
DFFSX1TS R_6 ( .D(n2925), .CK(clk), .SN(n1363), .Q(n2840) );
DFFSX1TS R_5 ( .D(n2924), .CK(clk), .SN(n1371), .Q(n2841) );
DFFSX1TS R_11 ( .D(n2905), .CK(clk), .SN(n1015), .Q(n2836) );
DFFSX2TS R_18 ( .D(n2917), .CK(clk), .SN(n1024), .Q(n2831) );
DFFSX2TS R_19 ( .D(n2918), .CK(clk), .SN(n1000), .Q(n2830) );
DFFSX2TS R_20 ( .D(n2919), .CK(clk), .SN(n1372), .Q(n2829) );
DFFSX1TS R_23 ( .D(n2856), .CK(clk), .SN(n3034), .Q(n2826) );
DFFSX1TS R_25 ( .D(n2914), .CK(clk), .SN(n1364), .Q(n2824) );
DFFSX1TS R_24 ( .D(n2915), .CK(clk), .SN(n1024), .Q(n2825) );
DFFRX4TS R_34 ( .D(n2904), .CK(clk), .RN(n2867), .Q(n2818) );
DFFRX4TS R_44 ( .D(n2810), .CK(clk), .RN(n1359), .Q(
DmP_mant_SFG_SWR_signed[12]) );
DFFSX1TS R_45 ( .D(n2929), .CK(clk), .SN(n2897), .Q(n2809) );
DFFSX2TS R_47 ( .D(n2928), .CK(clk), .SN(n1355), .Q(n2807) );
DFFSX2TS R_48 ( .D(n2931), .CK(clk), .SN(n2695), .Q(n2806) );
DFFSX2TS R_59 ( .D(n2935), .CK(clk), .SN(n1365), .Q(n2800) );
DFFSX1TS R_68 ( .D(n2948), .CK(clk), .SN(n2696), .Q(n2793) );
DFFSX1TS R_70 ( .D(n2946), .CK(clk), .SN(n2894), .Q(n2791) );
DFFSX1TS R_69 ( .D(n2947), .CK(clk), .SN(n994), .Q(n2792) );
DFFSX2TS R_86 ( .D(n2909), .CK(clk), .SN(n2896), .Q(n2781) );
DFFSX2TS R_88 ( .D(n2908), .CK(clk), .SN(n2871), .Q(n2780) );
DFFSX2TS R_89 ( .D(n2945), .CK(clk), .SN(n995), .Q(n2779) );
DFFSX2TS R_91 ( .D(n2944), .CK(clk), .SN(n994), .Q(n2778) );
DFFSX1TS R_105 ( .D(n2963), .CK(clk), .SN(n1366), .Q(n2770) );
DFFSX1TS R_106 ( .D(n2962), .CK(clk), .SN(n1366), .Q(n2769) );
DFFSX2TS R_108 ( .D(n2943), .CK(clk), .SN(n1024), .Q(n2767) );
DFFSX2TS R_109 ( .D(n2942), .CK(clk), .SN(n1365), .Q(n2766) );
DFFSX2TS R_110 ( .D(n2941), .CK(clk), .SN(n994), .Q(n2765) );
DFFSX1TS R_111 ( .D(n2954), .CK(clk), .SN(n2869), .Q(n2764) );
DFFSX1TS R_113 ( .D(n2952), .CK(clk), .SN(n985), .Q(n2762) );
DFFSX1TS R_112 ( .D(n2953), .CK(clk), .SN(n2896), .Q(n2763) );
DFFSX2TS R_115 ( .D(n2950), .CK(clk), .SN(n2869), .Q(n2760) );
DFFSX2TS R_116 ( .D(n2949), .CK(clk), .SN(n2896), .Q(n2759) );
DFFSX4TS R_130 ( .D(n3033), .CK(clk), .SN(n1371), .Q(n2752) );
DFFRX4TS R_135 ( .D(n630), .CK(clk), .RN(n3034), .Q(n2898), .QN(n1294) );
DFFSX2TS R_177 ( .D(n2932), .CK(clk), .SN(n1000), .Q(n2728) );
DFFSX2TS R_181 ( .D(n2910), .CK(clk), .SN(n1360), .Q(n2725) );
DFFSX1TS R_194 ( .D(n2973), .CK(clk), .SN(n1364), .Q(n2716) );
DFFSX1TS R_192 ( .D(n2975), .CK(clk), .SN(n1363), .Q(n2718) );
DFFRX4TS R_205 ( .D(n2711), .CK(clk), .RN(n1359), .Q(
DmP_mant_SFG_SWR_signed[13]), .QN(n2641) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n724), .CK(clk), .RN(n2882), .Q(
DMP_SFG[24]), .QN(n2682) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n719), .CK(clk), .RN(n2883), .Q(
DMP_SFG[25]), .QN(n2681) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n714), .CK(clk), .RN(n2884), .Q(
DMP_SFG[26]), .QN(n2680) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n709), .CK(clk), .RN(n2884), .Q(
DMP_SFG[27]), .QN(n2679) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n704), .CK(clk), .RN(n2885), .Q(
DMP_SFG[28]), .QN(n2678) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n699), .CK(clk), .RN(n2885), .Q(
DMP_SFG[29]), .QN(n2677) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n694), .CK(clk), .RN(n2886), .Q(
DMP_SFG[30]), .QN(n2676) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n846), .CK(clk), .RN(n2877),
.Q(Shift_amount_SHT1_EWR[1]), .QN(n2661) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n627), .CK(clk), .RN(n2897), .Q(
SIGN_FLAG_SFG), .QN(n2578) );
DFFRX4TS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n802), .CK(clk), .RN(n2870), .Q(
ZERO_FLAG_EXP), .QN(n2550) );
DFFSX2TS R_3 ( .D(n3026), .CK(clk), .SN(n2691), .Q(n2842) );
DFFSX2TS R_29 ( .D(n3006), .CK(clk), .SN(n2870), .Q(n2822) );
DFFSX2TS R_52 ( .D(n2982), .CK(clk), .SN(n2698), .Q(n2804) );
DFFSX2TS R_56 ( .D(n2984), .CK(clk), .SN(n2865), .Q(n2802) );
DFFSX2TS R_63 ( .D(n3022), .CK(clk), .SN(n2869), .Q(n2798) );
DFFSX2TS R_74 ( .D(n3000), .CK(clk), .SN(n2870), .Q(n2789) );
DFFSX2TS R_78 ( .D(n2996), .CK(clk), .SN(n2696), .Q(n2787) );
DFFSX2TS R_95 ( .D(n3016), .CK(clk), .SN(n2870), .Q(n2776) );
DFFSX2TS R_99 ( .D(n3024), .CK(clk), .SN(n2691), .Q(n2774) );
DFFSX2TS R_103 ( .D(n3008), .CK(clk), .SN(n2695), .Q(n2772) );
DFFSX2TS R_120 ( .D(n3012), .CK(clk), .SN(n2695), .Q(n2757) );
DFFSX2TS R_124 ( .D(n2990), .CK(clk), .SN(n2696), .Q(n2755) );
DFFSX2TS R_128 ( .D(n2986), .CK(clk), .SN(n2696), .Q(n2753) );
DFFSX2TS R_139 ( .D(n2994), .CK(clk), .SN(n2697), .Q(n2750) );
DFFSX2TS R_143 ( .D(n3014), .CK(clk), .SN(n2694), .Q(n2748) );
DFFSX2TS R_147 ( .D(n2992), .CK(clk), .SN(n2697), .Q(n2746) );
DFFSX2TS R_151 ( .D(n3002), .CK(clk), .SN(n2694), .Q(n2744) );
DFFSX2TS R_155 ( .D(n3018), .CK(clk), .SN(n2691), .Q(n2742) );
DFFSX2TS R_165 ( .D(n3010), .CK(clk), .SN(n2694), .Q(n2735) );
DFFSX2TS R_169 ( .D(n3020), .CK(clk), .SN(n2692), .Q(n2733) );
DFFSX2TS R_173 ( .D(n2988), .CK(clk), .SN(n2698), .Q(n2731) );
DFFSX2TS R_187 ( .D(n3004), .CK(clk), .SN(n2693), .Q(n2722) );
DFFSX2TS R_198 ( .D(n2998), .CK(clk), .SN(n2693), .Q(n2714) );
DFFSX2TS R_1 ( .D(n963), .CK(clk), .SN(n2693), .Q(n2843) );
DFFSX2TS R_27 ( .D(n3007), .CK(clk), .SN(n2870), .Q(n2823) );
DFFSX2TS R_50 ( .D(n2983), .CK(clk), .SN(n2698), .Q(n2805) );
DFFSX2TS R_54 ( .D(n2985), .CK(clk), .SN(n2896), .Q(n2803) );
DFFSX2TS R_61 ( .D(n3023), .CK(clk), .SN(n2697), .Q(n2799) );
DFFSX2TS R_72 ( .D(n3001), .CK(clk), .SN(n2870), .Q(n2790) );
DFFSX2TS R_76 ( .D(n2997), .CK(clk), .SN(n2696), .Q(n2788) );
DFFSX2TS R_93 ( .D(n3017), .CK(clk), .SN(n2695), .Q(n2777) );
DFFSX2TS R_97 ( .D(n3025), .CK(clk), .SN(n2691), .Q(n2775) );
DFFSX2TS R_101 ( .D(n3009), .CK(clk), .SN(n2695), .Q(n2773) );
DFFSX2TS R_118 ( .D(n3013), .CK(clk), .SN(n2695), .Q(n2758) );
DFFSX2TS R_122 ( .D(n2991), .CK(clk), .SN(n2696), .Q(n2756) );
DFFSX2TS R_126 ( .D(n2987), .CK(clk), .SN(n2697), .Q(n2754) );
DFFSX2TS R_137 ( .D(n2995), .CK(clk), .SN(n2697), .Q(n2751) );
DFFSX2TS R_141 ( .D(n3015), .CK(clk), .SN(n2694), .Q(n2749) );
DFFSX2TS R_145 ( .D(n2993), .CK(clk), .SN(n2697), .Q(n2747) );
DFFSX2TS R_149 ( .D(n3003), .CK(clk), .SN(n2694), .Q(n2745) );
DFFSX2TS R_153 ( .D(n3019), .CK(clk), .SN(n2691), .Q(n2743) );
DFFSX2TS R_163 ( .D(n3011), .CK(clk), .SN(n2693), .Q(n2736) );
DFFSX2TS R_167 ( .D(n3021), .CK(clk), .SN(n2692), .Q(n2734) );
DFFSX2TS R_171 ( .D(n2989), .CK(clk), .SN(n2698), .Q(n2732) );
DFFSX2TS R_185 ( .D(n3005), .CK(clk), .SN(n2693), .Q(n2723) );
DFFSX2TS R_196 ( .D(n2999), .CK(clk), .SN(n2693), .Q(n2715) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n835), .CK(clk), .RN(n2894), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n624), .CK(clk), .RN(n2894), .Q(
final_result_ieee[31]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n912), .CK(clk), .RN(n2881),
.Q(intDX_EWSW[31]), .QN(n2619) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n842), .CK(clk), .RN(n2693), .Q(
final_result_ieee[23]) );
DFFSX1TS R_157 ( .D(n3032), .CK(clk), .SN(n3034), .Q(n2741) );
DFFSX2TS R_183 ( .D(n3030), .CK(clk), .SN(n2692), .Q(n2724) );
DFFSX2TS R_207 ( .D(n3031), .CK(clk), .SN(n2692), .Q(n2710) );
DFFRX1TS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n633), .CK(clk), .RN(n984), .Q(
zero_flag) );
DFFSX2TS R_200 ( .D(n3029), .CK(clk), .SN(n2694), .Q(n2713) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n720), .CK(clk), .RN(n2883), .QN(
n2577) );
DFFSX2TS R_238 ( .D(n2687), .CK(clk), .SN(n1365), .Q(n2702) );
DFFSX2TS R_242 ( .D(n2690), .CK(clk), .SN(n2894), .Q(n2700) );
DFFSX2TS R_158 ( .D(n2969), .CK(clk), .SN(n1016), .Q(n2740) );
DFFSX2TS R_223 ( .D(n862), .CK(clk), .SN(n2692), .Q(n2706) );
DFFSX2TS R_231 ( .D(n857), .CK(clk), .SN(n1365), .Q(n2704) );
DFFSX2TS R_239 ( .D(n853), .CK(clk), .SN(n1360), .Q(n2701) );
DFFSX1TS R_65 ( .D(n2959), .CK(clk), .SN(n1355), .Q(n2796) );
DFFSX1TS R_83 ( .D(n2853), .CK(clk), .SN(n2896), .Q(n2784) );
DFFSX1TS R_64 ( .D(n2960), .CK(clk), .SN(n2870), .Q(n2797) );
DFFSX2TS R_221 ( .D(n2977), .CK(clk), .SN(n1381), .Q(n2708) );
DFFSX2TS R_220 ( .D(n1037), .CK(clk), .SN(n1381), .Q(n2709) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n774), .CK(clk), .RN(n2877), .Q(
DMP_SFG[8]), .QN(n2546) );
DFFSX2TS R_31 ( .D(n2980), .CK(clk), .SN(n1381), .Q(n2821) );
DFFSX2TS R_159 ( .D(n2972), .CK(clk), .SN(n1359), .Q(n2739) );
DFFSX2TS R_32 ( .D(n2979), .CK(clk), .SN(n2873), .Q(n2820) );
DFFSX2TS R_33 ( .D(n2978), .CK(clk), .SN(n991), .Q(n2819) );
DFFSX2TS R_161 ( .D(n2971), .CK(clk), .SN(n1016), .Q(n2737) );
DFFSX2TS R_16 ( .D(n2938), .CK(clk), .SN(n2694), .Q(n2833) );
DFFSX2TS R_17 ( .D(n2937), .CK(clk), .SN(n3034), .Q(n2832) );
DFFSX2TS R_14 ( .D(n2940), .CK(clk), .SN(n1354), .Q(n2835) );
DFFSX2TS R_222 ( .D(n2976), .CK(clk), .SN(n1381), .Q(n2707) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n601), .CK(clk), .RN(n993), .Q(
DmP_mant_SFG_SWR[2]), .QN(n2663) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n598), .CK(clk), .RN(n987), .Q(
LZD_output_NRM2_EW[3]), .QN(n2587) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n795), .CK(clk), .RN(n1026), .Q(
DMP_SFG[1]), .QN(n2549) );
DFFSX2TS R_37 ( .D(n2901), .CK(clk), .SN(n1016), .Q(n2815) );
DFFSX2TS R_191 ( .D(n2920), .CK(clk), .SN(n1364), .Q(n2719) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n587), .CK(clk), .RN(n1024), .Q(
Raw_mant_NRM_SWR[9]), .QN(n2860) );
DFFRX4TS R_13 ( .D(n630), .CK(clk), .RN(n1363), .Q(n2848) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n607), .CK(clk), .RN(n990), .Q(
LZD_output_NRM2_EW[2]) );
DFFSX2TS R_67 ( .D(n2957), .CK(clk), .SN(n985), .Q(n2794) );
DFFSX2TS R_36 ( .D(n2902), .CK(clk), .SN(n1016), .Q(n2816) );
DFFRX4TS R_38 ( .D(n2968), .CK(clk), .RN(n1364), .Q(n2814) );
DFFSX2TS R_85 ( .D(n2955), .CK(clk), .SN(n2869), .Q(n2782) );
DFFSX4TS R_209 ( .D(n1332), .CK(clk), .SN(n988), .Q(n2913) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n789), .CK(clk), .RN(n2876), .Q(
DMP_SFG[3]), .QN(n2548) );
DFFSX2TS R_84 ( .D(n2956), .CK(clk), .SN(n1360), .Q(n2783) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n549), .CK(clk), .RN(n2866), .Q(
DmP_mant_SFG_SWR[20]), .QN(n2658) );
DFFSX2TS R_41 ( .D(n2965), .CK(clk), .SN(n1366), .Q(n2811) );
DFFSX2TS R_188 ( .D(n2923), .CK(clk), .SN(n1362), .Q(n2721) );
DFFSX2TS R_35 ( .D(n2903), .CK(clk), .SN(n1016), .Q(n2817) );
DFFSX2TS R_66 ( .D(n2958), .CK(clk), .SN(n2896), .Q(n2795) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n591), .CK(clk), .RN(n2869), .Q(
Raw_mant_NRM_SWR[5]), .QN(n2845) );
DFFSX2TS R_40 ( .D(n2966), .CK(clk), .SN(n1366), .Q(n2812) );
DFFRHQX2TS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n721), .CK(clk), .RN(n991), .Q(
n2540) );
DFFSX1TS R_202 ( .D(n3028), .CK(clk), .SN(n2692), .Q(n2712) );
DFFSRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n684), .CK(clk), .SN(1'b1),
.RN(n990), .Q(DmP_mant_SHT1_SW[3]) );
DFFRHQX4TS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n844), .CK(clk), .RN(n999),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRHQX2TS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n636), .CK(clk), .RN(n988), .Q(
ZERO_FLAG_SFG) );
DFFSX4TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1555), .CK(clk), .SN(n1381),
.QN(intDY_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n725), .CK(clk), .RN(n2882), .Q(
DMP_SHT2_EWSW[24]), .QN(n2560) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n631), .CK(clk), .RN(n2881), .Q(
OP_FLAG_SHT2), .QN(n2551) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n545), .CK(clk), .RN(n2866), .Q(
DmP_mant_SFG_SWR[24]), .QN(n2655) );
DFFSX1TS R_234 ( .D(n2689), .CK(clk), .SN(n2867), .Q(n2703) );
DFFSX2TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1556), .CK(clk), .SN(n991), .Q(n2547)
);
DFFRX4TS R_104 ( .D(n2964), .CK(clk), .RN(n1371), .Q(n2771) );
DFFSRHQX4TS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n628), .CK(clk), .SN(1'b1), .RN(
n988), .Q(SIGN_FLAG_SHT2) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_18_ ( .D(n655), .CK(clk), .RN(n1371), .Q(
DmP_EXP_EWSW[18]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_10_ ( .D(n671), .CK(clk), .RN(n2873), .Q(
DmP_EXP_EWSW[10]) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n946), .CK(clk), .RN(n2893), .Q(
Shift_reg_FLAGS_7[2]), .QN(n2642) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n809), .CK(clk), .RN(n2883), .Q(
n1349) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n942), .CK(clk), .RN(n2889),
.Q(n1348) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n922), .CK(clk), .RN(n2891),
.Q(n1344) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n921), .CK(clk), .RN(n2892),
.Q(n1343) );
DFFRHQX2TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n604), .CK(clk), .RN(n2698),
.Q(n1340) );
DFFRHQX8TS R_203 ( .D(n630), .CK(clk), .RN(n1364), .Q(n1334) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n920), .CK(clk), .RN(n2892),
.Q(n1328) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n617), .CK(clk), .RN(n2877),
.Q(n1326) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_10_ ( .D(n824), .CK(clk), .RN(n2878), .Q(
n1325) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_4_ ( .D(n830), .CK(clk), .RN(n2881), .Q(n1324) );
DFFSX2TS R_82 ( .D(n2852), .CK(clk), .SN(n2869), .Q(n2785) );
DFFRX2TS R_8 ( .D(n2907), .CK(clk), .RN(n1015), .Q(n2839) );
DFFSX1TS R_46 ( .D(n2930), .CK(clk), .SN(n995), .Q(n2808) );
DFFRX1TS R_204 ( .D(n582), .CK(clk), .RN(n1366), .QN(n2849) );
DFFRX4TS R_9 ( .D(n2857), .CK(clk), .RN(n1015), .Q(n2838) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_8_ ( .D(n826), .CK(clk), .RN(n2877), .Q(n1312) );
DFFSX1TS R_114 ( .D(n2951), .CK(clk), .SN(n991), .Q(n2761) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n618), .CK(clk), .RN(n2871),
.Q(n1266) );
DFFSX1TS R_22 ( .D(n2855), .CK(clk), .SN(n1024), .Q(n2827) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n907), .CK(clk), .RN(n2887),
.Q(n1264) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n892), .CK(clk), .RN(n2888),
.Q(n1260) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n916), .CK(clk), .RN(n2892),
.Q(n1258) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n890), .CK(clk), .RN(n2888),
.Q(n1255) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n918), .CK(clk), .RN(n2892),
.Q(n1254) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n611), .CK(clk), .RN(n1372),
.Q(n1251) );
DFFRHQX8TS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n610), .CK(clk), .RN(n999),
.Q(n1245) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n908), .CK(clk), .RN(n2886),
.Q(n1243) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n622), .CK(clk), .RN(n2871),
.Q(n1240) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n616), .CK(clk), .RN(n999), .Q(
n1238) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n614), .CK(clk), .RN(n2877),
.Q(n1235) );
DFFRHQX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n848), .CK(clk), .RN(n1359),
.Q(n1230) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n901), .CK(clk), .RN(n2887),
.Q(n1228) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n902), .CK(clk), .RN(n2887),
.Q(n1225) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n894), .CK(clk), .RN(n2888),
.Q(n1220) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n807), .CK(clk), .RN(n2884), .Q(
n1219) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_17_ ( .D(n817), .CK(clk), .RN(n2868), .Q(
n1218) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_4_ ( .D(n683), .CK(clk), .RN(n1371), .Q(n1217) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_12_ ( .D(n667), .CK(clk), .RN(n987), .Q(n1216) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_5_ ( .D(n681), .CK(clk), .RN(n2873), .Q(n1214) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_15_ ( .D(n661), .CK(clk), .RN(n1378), .Q(
DmP_EXP_EWSW[15]) );
DFFSX2TS R_160 ( .D(n2970), .CK(clk), .SN(n978), .Q(n2738) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1359), .Q(
n1310) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_2_ ( .D(n687), .CK(clk), .RN(n987), .Q(n1309)
);
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_3_ ( .D(n685), .CK(clk), .RN(n1363), .Q(n1215) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_3_ ( .D(n831), .CK(clk), .RN(n2876), .Q(n1210) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_9_ ( .D(n825), .CK(clk), .RN(n1018), .Q(n1209) );
DFFSX2TS R_254 ( .D(n1748), .CK(clk), .SN(n2876), .Q(n1207) );
DFFRX2TS R_253 ( .D(n1384), .CK(clk), .RN(n2874), .Q(n1208) );
DFFSX2TS R_256 ( .D(n1930), .CK(clk), .SN(n2875), .Q(n1205) );
DFFRX2TS R_255 ( .D(n1385), .CK(clk), .RN(n2875), .Q(n1206) );
DFFSX2TS R_257 ( .D(n1659), .CK(clk), .SN(n1354), .Q(n1204) );
DFFSX2TS R_258 ( .D(n1660), .CK(clk), .SN(n1354), .Q(n1203) );
DFFSX2TS R_259 ( .D(n1658), .CK(clk), .SN(n1354), .Q(n1202) );
DFFSX2TS R_260 ( .D(n1742), .CK(clk), .SN(n990), .Q(n1201) );
DFFSX2TS R_261 ( .D(n1743), .CK(clk), .SN(n990), .Q(n1200) );
DFFSX2TS R_262 ( .D(n1741), .CK(clk), .SN(n1373), .Q(n1199) );
DFFSX2TS R_263 ( .D(n1656), .CK(clk), .SN(n2691), .Q(n1198) );
DFFSX2TS R_264 ( .D(n1657), .CK(clk), .SN(n2691), .Q(n1197) );
DFFSX2TS R_265 ( .D(n1655), .CK(clk), .SN(n2894), .Q(n1196) );
DFFSX2TS R_266 ( .D(n1647), .CK(clk), .SN(n995), .Q(n1195) );
DFFSX2TS R_267 ( .D(n1648), .CK(clk), .SN(n994), .Q(n1194) );
DFFSX2TS R_268 ( .D(n1646), .CK(clk), .SN(n995), .Q(n1193) );
DFFSX2TS R_269 ( .D(n1650), .CK(clk), .SN(n977), .Q(n1192) );
DFFSX2TS R_270 ( .D(n1651), .CK(clk), .SN(n978), .Q(n1191) );
DFFSX2TS R_271 ( .D(n1649), .CK(clk), .SN(n978), .Q(n1190) );
DFFSX2TS R_272 ( .D(n1671), .CK(clk), .SN(n991), .Q(n1189) );
DFFSX2TS R_273 ( .D(n1672), .CK(clk), .SN(n991), .Q(n1188) );
DFFSX2TS R_274 ( .D(n1670), .CK(clk), .SN(n991), .Q(n1187) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n621), .CK(clk), .RN(n2871),
.Q(n1271) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n579), .CK(clk), .RN(n1355),
.Q(n1211) );
DFFRX4TS R_281 ( .D(n1502), .CK(clk), .RN(n1024), .Q(n1183) );
DFFSX4TS R_280 ( .D(DmP_mant_SHT1_SW[9]), .CK(clk), .SN(n1024), .Q(n1184) );
DFFRX4TS R_279 ( .D(n1251), .CK(clk), .RN(n1024), .Q(n1185) );
DFFSX4TS R_278 ( .D(n1268), .CK(clk), .SN(n1024), .Q(n1186) );
DFFSX2TS R_282 ( .D(n1727), .CK(clk), .SN(n1027), .Q(n1182) );
DFFSX2TS R_283 ( .D(n1728), .CK(clk), .SN(n1027), .Q(n1181) );
DFFSX2TS R_284 ( .D(n1726), .CK(clk), .SN(n1027), .Q(n1180) );
DFFSX2TS R_285 ( .D(n2313), .CK(clk), .SN(n998), .Q(n1179) );
DFFSX2TS R_286 ( .D(n2314), .CK(clk), .SN(n998), .Q(n1178) );
DFFSX2TS R_287 ( .D(n2312), .CK(clk), .SN(n998), .Q(n1177) );
DFFRX4TS R_289 ( .D(n1395), .CK(clk), .RN(n1365), .Q(n1175) );
DFFRX4TS R_288 ( .D(n1397), .CK(clk), .RN(n1360), .Q(n1176) );
DFFSX2TS R_290 ( .D(n1644), .CK(clk), .SN(n2875), .Q(n1174) );
DFFSX2TS R_291 ( .D(n1645), .CK(clk), .SN(n2876), .Q(n1173) );
DFFSX2TS R_292 ( .D(n1643), .CK(clk), .SN(n2875), .Q(n1172) );
DFFSX2TS R_293 ( .D(n1751), .CK(clk), .SN(n988), .Q(n1171) );
DFFSX2TS R_294 ( .D(n1752), .CK(clk), .SN(n988), .Q(n1170) );
DFFSX2TS R_295 ( .D(n1750), .CK(clk), .SN(n988), .Q(n1169) );
DFFSX2TS R_296 ( .D(n1724), .CK(clk), .SN(n1027), .Q(n1168) );
DFFSX2TS R_297 ( .D(n1725), .CK(clk), .SN(n1027), .Q(n1167) );
DFFSX2TS R_298 ( .D(n1723), .CK(clk), .SN(n1027), .Q(n1166) );
DFFSX4TS R_299 ( .D(n2398), .CK(clk), .SN(n1364), .Q(n1165) );
DFFSX2TS R_303 ( .D(n1920), .CK(clk), .SN(n1015), .Q(n1164) );
DFFSX2TS R_304 ( .D(n1921), .CK(clk), .SN(n1378), .Q(n1163) );
DFFSX2TS R_305 ( .D(n1919), .CK(clk), .SN(n1372), .Q(n1162) );
DFFSX2TS R_306 ( .D(n1635), .CK(clk), .SN(n1027), .Q(n1161) );
DFFSX2TS R_307 ( .D(n1636), .CK(clk), .SN(n1027), .Q(n1160) );
DFFSX2TS R_308 ( .D(n1634), .CK(clk), .SN(n1027), .Q(n1159) );
DFFSX2TS R_309 ( .D(n1665), .CK(clk), .SN(n1378), .Q(n1158) );
DFFSX2TS R_310 ( .D(n1666), .CK(clk), .SN(n1378), .Q(n1157) );
DFFSX2TS R_311 ( .D(n1664), .CK(clk), .SN(n1362), .Q(n1156) );
DFFSX2TS R_313 ( .D(n2685), .CK(clk), .SN(n985), .Q(n1154) );
DFFSX2TS R_314 ( .D(n2499), .CK(clk), .SN(n985), .Q(n1153) );
DFFSX2TS R_312 ( .D(n2101), .CK(clk), .SN(n985), .Q(n1155) );
DFFSX2TS R_315 ( .D(n1739), .CK(clk), .SN(n1016), .Q(n1152) );
DFFSX2TS R_316 ( .D(n1740), .CK(clk), .SN(n1016), .Q(n1151) );
DFFSX2TS R_317 ( .D(n1738), .CK(clk), .SN(n1016), .Q(n1150) );
DFFSX4TS R_321 ( .D(n2615), .CK(clk), .SN(n999), .Q(n1147) );
DFFSX4TS R_319 ( .D(n2545), .CK(clk), .SN(n999), .Q(n1148) );
DFFSX2TS R_322 ( .D(n1734), .CK(clk), .SN(n2698), .Q(n1146) );
DFFSX2TS R_323 ( .D(n1733), .CK(clk), .SN(n2698), .Q(n1145) );
DFFSX2TS R_324 ( .D(n1732), .CK(clk), .SN(n2698), .Q(n1144) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n578), .CK(clk), .RN(n3034), .Q(
DmP_mant_SFG_SWR[10]), .QN(n2666) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n597), .CK(clk), .RN(n2869), .Q(
DmP_mant_SFG_SWR[3]), .QN(n2664) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n750), .CK(clk), .RN(n1355), .Q(
DMP_SFG[16]), .QN(n2636) );
DFFSX2TS R_332 ( .D(n1038), .CK(clk), .SN(n2693), .Q(n1140) );
DFFSX2TS R_333 ( .D(n1038), .CK(clk), .SN(n2693), .Q(n1139) );
DFFSX2TS R_334 ( .D(n1036), .CK(clk), .SN(n2692), .Q(n1138) );
DFFSX2TS R_335 ( .D(n1287), .CK(clk), .SN(n1365), .Q(n1137) );
DFFSX2TS R_336 ( .D(n1036), .CK(clk), .SN(n2698), .Q(n1136) );
DFFRX4TS R_337 ( .D(n2862), .CK(clk), .RN(n2873), .Q(n1135), .QN(n1117) );
DFFSX2TS R_338 ( .D(n2864), .CK(clk), .SN(n2697), .Q(n1134) );
DFFSX2TS R_339 ( .D(n2844), .CK(clk), .SN(n2876), .Q(n1133), .QN(n1115) );
DFFSX4TS R_340 ( .D(n2596), .CK(clk), .SN(n3034), .Q(n1132) );
DFFSX2TS R_341 ( .D(n2899), .CK(clk), .SN(n1381), .Q(n1131), .QN(ready) );
DFFSX4TS R_343 ( .D(n1253), .CK(clk), .SN(n999), .Q(n1128) );
DFFSX4TS R_344 ( .D(n968), .CK(clk), .SN(n1363), .Q(n1127) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n551), .CK(clk), .RN(n2866),
.Q(n1125) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_1_ ( .D(n833), .CK(clk), .RN(n2875), .Q(n1122) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_18_ ( .D(n816), .CK(clk), .RN(n1015), .Q(
n1119) );
DFFSX4TS R_235 ( .D(n856), .CK(clk), .SN(n1362), .QN(n1116) );
DFFSX2TS R_175 ( .D(n2933), .CK(clk), .SN(n1355), .Q(n2729) );
DFFSX2TS R_10 ( .D(n2906), .CK(clk), .SN(n1015), .Q(n2837) );
DFFSX2TS R_193 ( .D(n2974), .CK(clk), .SN(n1360), .Q(n2717) );
DFFSX2TS R_179 ( .D(n2911), .CK(clk), .SN(n1360), .Q(n2726) );
DFFRX4TS R_57 ( .D(n2936), .CK(clk), .RN(n984), .Q(n2801) );
DFFRHQX8TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n612), .CK(clk), .RN(n1371),
.Q(n1104) );
DFFRX4TS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n801), .CK(clk), .RN(n2867), .Q(
SIGN_FLAG_EXP) );
DFFSX4TS R_318 ( .D(n2863), .CK(clk), .SN(n999), .Q(n1149) );
DFFRX4TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n911), .CK(clk), .RN(n2881), .Q(
intAS) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n619), .CK(clk), .RN(n2872),
.Q(n1269) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n796), .CK(clk), .RN(n1026), .Q(
DMP_SHT2_EWSW[1]), .QN(n2625) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n760), .CK(clk), .RN(n998), .Q(
DMP_SHT2_EWSW[13]), .QN(n2562) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n729), .CK(clk), .RN(n2882), .Q(
DMP_SFG[23]), .QN(n2683) );
DFFRXLTS R_174 ( .D(n2934), .CK(clk), .RN(n1354), .Q(n2730) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n742), .CK(clk), .RN(n1365), .Q(
DMP_SHT2_EWSW[19]), .QN(n2570) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n741), .CK(clk), .RN(n1372), .QN(n2674) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n738), .CK(clk), .RN(n1362), .Q(
DMP_SFG[20]), .QN(n2649) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n735), .CK(clk), .RN(n1360), .Q(
DMP_SFG[21]), .QN(n2650) );
DFFSX2TS R_21 ( .D(n2916), .CK(clk), .SN(n1000), .Q(n2828) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n1018), .Q(
DmP_mant_SFG_SWR[0]), .QN(n2671) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n772), .CK(clk), .RN(n1379), .Q(
DMP_SHT2_EWSW[9]), .QN(n2567) );
DFFRX4TS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n639), .CK(clk), .RN(n985), .Q(
overflow_flag) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n623), .CK(clk), .RN(n2871),
.Q(n967) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n585), .CK(clk), .RN(n1354),
.Q(n964) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_6_ ( .D(n828), .CK(clk), .RN(n2878), .Q(
DMP_EXP_EWSW[6]) );
DFFSX4TS R_227 ( .D(n864), .CK(clk), .SN(n1360), .Q(n2705) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n596), .CK(clk), .RN(n1363), .Q(
Raw_mant_NRM_SWR[4]), .QN(n2847) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n615), .CK(clk), .RN(n2877),
.Q(n971) );
DFFSX4TS R_342 ( .D(n2863), .CK(clk), .SN(n994), .Q(n1129) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n550), .CK(clk), .RN(n2866), .Q(
DmP_mant_SFG_SWR[19]), .QN(n2659) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n762), .CK(clk), .RN(n997), .Q(
DMP_SFG[12]), .QN(n2629) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n554), .CK(clk), .RN(n990), .Q(
DmP_mant_SFG_SWR[15]), .QN(n2654) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n642), .CK(clk), .RN(n1359), .Q(
DmP_EXP_EWSW[26]), .QN(n2639) );
DFFSX2TS R_39 ( .D(n2967), .CK(clk), .SN(n1366), .Q(n2813) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n575), .CK(clk), .RN(n1362),
.Q(n1112) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n599), .CK(clk), .RN(n2896), .Q(
n1316) );
DFFRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n906), .CK(clk), .RN(n2887),
.Q(n1262) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n938), .CK(clk), .RN(n2890),
.Q(n1346) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n939), .CK(clk), .RN(n2890),
.Q(n1339) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n753), .CK(clk), .RN(n1354), .Q(
DMP_SFG[15]), .QN(n2637) );
DFFRX2TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n847), .CK(clk), .RN(n2878),
.Q(Shift_amount_SHT1_EWR[0]), .QN(n2579) );
DFFSX1TS R_15 ( .D(n2939), .CK(clk), .SN(n1372), .Q(n2834) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n588), .CK(clk), .RN(n1362), .Q(
DmP_mant_SFG_SWR[7]), .QN(n2652) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n606), .CK(clk), .RN(n1362), .Q(
DmP_mant_SFG_SWR[8]), .QN(n2667) );
DFFSX1TS R_189 ( .D(n2922), .CK(clk), .SN(n1024), .Q(n2720) );
DFFRHQX4TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n876), .CK(clk), .RN(n1018), .Q(
n1335) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n783), .CK(clk), .RN(n1372), .Q(
DMP_SFG[5]), .QN(n2632) );
DFFRXLTS R_178 ( .D(n2912), .CK(clk), .RN(n1364), .Q(n2727) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n595), .CK(clk), .RN(n1018), .Q(
DmP_mant_SFG_SWR[6]), .QN(n2660) );
DFFSX1TS R_107 ( .D(n2961), .CK(clk), .SN(n1366), .Q(n2768) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n944), .CK(clk), .RN(n2893), .QN(
n2644) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n771), .CK(clk), .RN(n987), .Q(
DMP_SFG[9]), .QN(n2631) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n786), .CK(clk), .RN(n2881), .QN(n2544)
);
DFFSX4TS R_331 ( .D(n1036), .CK(clk), .SN(n2693), .QN(n953) );
DFFSRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n664), .CK(clk), .SN(1'b1),
.RN(n1381), .Q(DmP_mant_SHT1_SW[13]) );
DFFSRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n668), .CK(clk), .SN(1'b1),
.RN(n987), .Q(DmP_mant_SHT1_SW[11]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n688), .CK(clk), .RN(n1354), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n2867), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n660), .CK(clk), .RN(n987), .Q(
DmP_mant_SHT1_SW[15]), .QN(n1301) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n682), .CK(clk), .RN(n1371), .Q(
DmP_mant_SHT1_SW[4]), .QN(n2689) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n686), .CK(clk), .RN(n1366), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n666), .CK(clk), .RN(n1372), .Q(
DmP_mant_SHT1_SW[12]), .QN(n2612) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n654), .CK(clk), .RN(n1364), .Q(
DmP_mant_SHT1_SW[18]), .QN(n2611) );
DFFRX2TS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n845), .CK(clk), .RN(n1018),
.QN(n2609) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n670), .CK(clk), .RN(n2873), .Q(
DmP_mant_SHT1_SW[10]), .QN(n2686) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n690), .CK(clk), .RN(n984), .Q(
DmP_mant_SHT1_SW[0]), .QN(n2690) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_22_ ( .D(n812), .CK(clk), .RN(n990), .Q(n1213) );
DFFSRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n658), .CK(clk), .SN(1'b1),
.RN(n991), .Q(DmP_mant_SHT1_SW[16]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n656), .CK(clk), .RN(n2876), .Q(
DmP_mant_SHT1_SW[17]), .QN(n1315) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_5_ ( .D(n829), .CK(clk), .RN(n3034), .Q(n1118) );
DFFRXLTS R_79 ( .D(underflow_flag), .CK(clk), .RN(n984), .Q(n2786) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n784), .CK(clk), .RN(n1363), .Q(
DMP_SHT2_EWSW[5]), .QN(n2569) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n740), .CK(clk), .RN(n1365), .Q(
DMP_SHT1_EWSW[20]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n743), .CK(clk), .RN(n1360), .Q(
DMP_SHT1_EWSW[19]) );
DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n634), .CK(clk), .RN(n1354), .Q(
ZERO_FLAG_SHT1SHT2) );
CLKINVX3TS U964 ( .A(rst), .Y(n1360) );
INVX2TS U965 ( .A(n1025), .Y(n1027) );
INVX2TS U966 ( .A(n989), .Y(n991) );
CLKBUFX3TS U967 ( .A(n2894), .Y(n2874) );
INVX2TS U968 ( .A(n1014), .Y(n1016) );
CLKINVX2TS U969 ( .A(n983), .Y(n985) );
CLKMX2X3TS U970 ( .A(DMP_SHT1_EWSW[6]), .B(DMP_EXP_EWSW[6]), .S0(n2474), .Y(
n782) );
AOI22X2TS U971 ( .A0(n1268), .A1(n1271), .B0(n1502), .B1(DmP_mant_SHT1_SW[6]), .Y(n2943) );
CLKINVX3TS U972 ( .A(n1353), .Y(n1354) );
INVX3TS U973 ( .A(n1023), .Y(n999) );
CLKINVX2TS U974 ( .A(n996), .Y(n998) );
BUFX8TS U975 ( .A(n2864), .Y(n1038) );
CLKINVX3TS U976 ( .A(n1023), .Y(n1024) );
INVX2TS U977 ( .A(n996), .Y(n997) );
CLKINVX2TS U978 ( .A(n1014), .Y(n1015) );
INVX2TS U979 ( .A(n986), .Y(n987) );
INVX2TS U980 ( .A(n1025), .Y(n1026) );
INVX2TS U981 ( .A(n989), .Y(n990) );
INVX2TS U982 ( .A(n983), .Y(n984) );
CLKINVX2TS U983 ( .A(n1017), .Y(n1018) );
MXI2X2TS U984 ( .A(n2563), .B(n2629), .S0(n2533), .Y(n762) );
CLKINVX2TS U985 ( .A(n976), .Y(n977) );
CLKINVX1TS U986 ( .A(n992), .Y(n993) );
CLKINVX1TS U987 ( .A(n1014), .Y(n1000) );
CLKBUFX2TS U988 ( .A(n2883), .Y(n2695) );
NAND2X1TS U989 ( .A(n2426), .B(n971), .Y(n1984) );
NAND2XLTS U990 ( .A(n1374), .B(n2476), .Y(n2044) );
NAND2X2TS U991 ( .A(n1348), .B(n2440), .Y(n1745) );
NAND2X2TS U992 ( .A(n1109), .B(DmP_mant_SHT1_SW[18]), .Y(n1396) );
NAND2X1TS U993 ( .A(n2426), .B(n1112), .Y(n1718) );
BUFX16TS U994 ( .A(n1290), .Y(n1502) );
NAND2X1TS U995 ( .A(n2276), .B(DmP_EXP_EWSW[15]), .Y(n1640) );
NAND2XLTS U996 ( .A(n2507), .B(n959), .Y(n1966) );
NAND2X1TS U997 ( .A(n2295), .B(DmP_EXP_EWSW[18]), .Y(n2267) );
NAND2X1TS U998 ( .A(n2295), .B(n1213), .Y(n1667) );
NAND2X1TS U999 ( .A(n2276), .B(DmP_EXP_EWSW[16]), .Y(n1720) );
NAND2X1TS U1000 ( .A(n2285), .B(n1216), .Y(n1735) );
NAND2X1TS U1001 ( .A(n2276), .B(n1214), .Y(n2277) );
INVX8TS U1002 ( .A(n1500), .Y(n1351) );
NAND2X4TS U1003 ( .A(n1498), .B(n1944), .Y(n2462) );
NAND2XLTS U1004 ( .A(n2276), .B(n1210), .Y(n1729) );
NAND2XLTS U1005 ( .A(n2276), .B(n1209), .Y(n1761) );
NAND2XLTS U1006 ( .A(n2445), .B(DmP_EXP_EWSW[14]), .Y(n1637) );
NAND2XLTS U1007 ( .A(n2445), .B(DMP_EXP_EWSW[13]), .Y(n2446) );
NAND2XLTS U1008 ( .A(n2445), .B(DMP_EXP_EWSW[6]), .Y(n2299) );
NAND2XLTS U1009 ( .A(n2450), .B(DMP_EXP_EWSW[29]), .Y(n2292) );
NAND2XLTS U1010 ( .A(n2450), .B(DmP_EXP_EWSW[26]), .Y(n2057) );
NOR2X1TS U1011 ( .A(n2411), .B(n2381), .Y(n2382) );
NAND2XLTS U1012 ( .A(n2276), .B(n1122), .Y(n1744) );
NAND2XLTS U1013 ( .A(n2450), .B(n1324), .Y(n2309) );
NAND2XLTS U1014 ( .A(n2445), .B(n1325), .Y(n2302) );
NAND2XLTS U1015 ( .A(n2445), .B(n1312), .Y(n1758) );
BUFX6TS U1016 ( .A(n1337), .Y(n1047) );
OR2X1TS U1017 ( .A(n2259), .B(n2142), .Y(n1300) );
NAND2BX1TS U1018 ( .AN(n1336), .B(n2470), .Y(n1386) );
NAND2X6TS U1019 ( .A(n2440), .B(intDY_EWSW[26]), .Y(n2058) );
NAND2X6TS U1020 ( .A(intDX_EWSW[16]), .B(n1918), .Y(n1049) );
XOR2X2TS U1021 ( .A(n2437), .B(n2436), .Y(n2438) );
XNOR2X1TS U1022 ( .A(n2530), .B(n2529), .Y(n2531) );
NAND2X6TS U1023 ( .A(n1367), .B(intDX_EWSW[0]), .Y(n2272) );
NAND2BXLTS U1024 ( .AN(n2616), .B(n981), .Y(n1056) );
MXI2X2TS U1025 ( .A(n2339), .B(shift_value_SHT2_EWR[2]), .S0(n2470), .Y(
n2340) );
INVX2TS U1026 ( .A(n1373), .Y(n1023) );
NOR2X4TS U1027 ( .A(n1548), .B(n2612), .Y(n1086) );
BUFX12TS U1028 ( .A(n1109), .Y(n961) );
BUFX12TS U1029 ( .A(n2496), .Y(n980) );
INVX2TS U1030 ( .A(n1378), .Y(n1017) );
INVX2TS U1031 ( .A(n2879), .Y(n996) );
INVX2TS U1032 ( .A(n2895), .Y(n983) );
INVX2TS U1033 ( .A(n2875), .Y(n1025) );
INVX2TS U1034 ( .A(n2699), .Y(n992) );
INVX2TS U1035 ( .A(n1379), .Y(n989) );
AOI22X1TS U1036 ( .A0(n2862), .A1(n1356), .B0(n2261), .B1(n2500), .Y(n2263)
);
XOR2X2TS U1037 ( .A(n2185), .B(n2184), .Y(n2186) );
OR2X6TS U1038 ( .A(n2377), .B(n972), .Y(n2374) );
OR2X6TS U1039 ( .A(n2377), .B(n1270), .Y(n2380) );
NOR2X1TS U1040 ( .A(n2609), .B(n1280), .Y(n2339) );
BUFX8TS U1041 ( .A(n2131), .Y(n1427) );
INVX12TS U1042 ( .A(n953), .Y(n1020) );
BUFX16TS U1043 ( .A(n1429), .Y(n1383) );
BUFX6TS U1044 ( .A(n2305), .Y(n2450) );
AO22XLTS U1045 ( .A0(n2383), .A1(DmP_mant_SHT1_SW[19]), .B0(n2384), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1319) );
AO22XLTS U1046 ( .A0(n2383), .A1(DmP_mant_SHT1_SW[11]), .B0(n2384), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1345) );
NAND2X1TS U1047 ( .A(n1976), .B(n1410), .Y(n1968) );
AOI21X2TS U1048 ( .A0(n2421), .A1(n2420), .B0(n2419), .Y(n2425) );
NAND2XLTS U1049 ( .A(n2435), .B(n2434), .Y(n2436) );
NAND2X1TS U1050 ( .A(n2040), .B(n2039), .Y(n1964) );
NOR2X1TS U1051 ( .A(n2334), .B(n2119), .Y(n2121) );
OR2X2TS U1052 ( .A(n2145), .B(n2411), .Y(n975) );
CLKBUFX2TS U1053 ( .A(n1381), .Y(n2895) );
CLKBUFX2TS U1054 ( .A(n2872), .Y(n2879) );
CLKBUFX2TS U1055 ( .A(n1355), .Y(n2699) );
BUFX6TS U1056 ( .A(n2449), .Y(n958) );
BUFX3TS U1057 ( .A(n2899), .Y(n2535) );
BUFX3TS U1058 ( .A(n2496), .Y(n979) );
CLKBUFX3TS U1059 ( .A(n978), .Y(n2865) );
CLKBUFX2TS U1060 ( .A(n1372), .Y(n1379) );
CLKBUFX2TS U1061 ( .A(n1365), .Y(n1378) );
NAND2BXLTS U1062 ( .AN(n2386), .B(n2862), .Y(n1414) );
INVX2TS U1063 ( .A(n1224), .Y(n966) );
NAND3X6TS U1064 ( .A(n2100), .B(n2099), .C(n2098), .Y(n2235) );
OAI21X2TS U1065 ( .A0(n2437), .A1(n1979), .B0(n1978), .Y(n1983) );
INVX4TS U1066 ( .A(rst), .Y(n1372) );
AND2X6TS U1067 ( .A(n1821), .B(n1549), .Y(n1109) );
NOR2X1TS U1068 ( .A(DMP_EXP_EWSW[26]), .B(n2639), .Y(n2219) );
CLKBUFX2TS U1069 ( .A(n2498), .Y(n2496) );
NAND3X1TS U1070 ( .A(n2764), .B(n2763), .C(n2762), .Y(n2391) );
INVX6TS U1071 ( .A(n2529), .Y(n2246) );
INVX4TS U1072 ( .A(n1931), .Y(n2409) );
INVX2TS U1073 ( .A(n2322), .Y(n1535) );
CLKAND2X2TS U1074 ( .A(n1099), .B(n1098), .Y(n2041) );
NAND2X4TS U1075 ( .A(n1033), .B(n2315), .Y(n1537) );
BUFX6TS U1076 ( .A(n2305), .Y(n2445) );
INVX4TS U1077 ( .A(n1369), .Y(n1370) );
INVX4TS U1078 ( .A(n2344), .Y(n1376) );
CLKINVX1TS U1079 ( .A(n1977), .Y(n1974) );
AOI21X1TS U1080 ( .A0(n1976), .A1(n1977), .B0(n1975), .Y(n1978) );
INVX2TS U1081 ( .A(n2259), .Y(n2862) );
NAND2X6TS U1082 ( .A(n1992), .B(n1088), .Y(n1087) );
OR2X4TS U1083 ( .A(n2251), .B(n2255), .Y(n2134) );
INVX2TS U1084 ( .A(n2899), .Y(n1036) );
NAND2X1TS U1085 ( .A(n1289), .B(n2468), .Y(n1894) );
NAND2X1TS U1086 ( .A(n2189), .B(n2404), .Y(n1892) );
NAND2X1TS U1087 ( .A(n1308), .B(n2353), .Y(n1910) );
NAND2X1TS U1088 ( .A(n2188), .B(n2141), .Y(n1893) );
AND2X6TS U1089 ( .A(n2120), .B(n1317), .Y(n1033) );
NAND3X1TS U1090 ( .A(n2793), .B(n2792), .C(n2791), .Y(n2144) );
NAND2X1TS U1091 ( .A(n2236), .B(n1035), .Y(n1903) );
INVX2TS U1092 ( .A(n2242), .Y(n2428) );
NAND2X1TS U1093 ( .A(n2348), .B(n1035), .Y(n1899) );
NAND2X4TS U1094 ( .A(n2149), .B(DMP_SFG[5]), .Y(n2422) );
NOR2X1TS U1095 ( .A(Raw_mant_NRM_SWR[1]), .B(Raw_mant_NRM_SWR[0]), .Y(n1529)
);
INVX6TS U1096 ( .A(n2139), .Y(n1817) );
INVX2TS U1097 ( .A(n2241), .Y(n2429) );
NOR2X2TS U1098 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR_signed[12]), .Y(n2164)
);
INVX2TS U1099 ( .A(n2229), .Y(n2423) );
OAI2BB1X2TS U1100 ( .A0N(n2321), .A1N(n1110), .B0(n2330), .Y(n2322) );
NOR2X6TS U1101 ( .A(n2133), .B(n2847), .Y(n2334) );
NOR2X6TS U1102 ( .A(n1032), .B(n1085), .Y(n2368) );
NAND2X2TS U1103 ( .A(n2096), .B(n2399), .Y(n1891) );
NAND2X2TS U1104 ( .A(n1289), .B(n1335), .Y(n1874) );
NAND2X2TS U1105 ( .A(n2096), .B(n1035), .Y(n1860) );
NAND3X2TS U1106 ( .A(n1470), .B(n1834), .C(n1469), .Y(n1468) );
NAND2X2TS U1107 ( .A(n2190), .B(n864), .Y(n1871) );
NAND2X2TS U1108 ( .A(n2190), .B(n2463), .Y(n2191) );
NAND2X2TS U1109 ( .A(n2190), .B(n2367), .Y(n2026) );
NOR2X4TS U1110 ( .A(n2262), .B(n2344), .Y(n2195) );
NAND3X6TS U1111 ( .A(n2116), .B(n2331), .C(n1774), .Y(n2251) );
NOR2X2TS U1112 ( .A(n1350), .B(DmP_EXP_EWSW[25]), .Y(n2072) );
NOR2X4TS U1113 ( .A(n2133), .B(n2132), .Y(n2255) );
CLKINVX3TS U1114 ( .A(n2206), .Y(n2106) );
NAND2X2TS U1115 ( .A(n2096), .B(n2077), .Y(n2078) );
NAND2X2TS U1116 ( .A(n2190), .B(n2389), .Y(n2173) );
NOR2X4TS U1117 ( .A(n2237), .B(n2262), .Y(n2200) );
NAND2X1TS U1118 ( .A(n2189), .B(n2353), .Y(n2012) );
INVX2TS U1119 ( .A(n1005), .Y(n1006) );
NAND2X2TS U1120 ( .A(n2030), .B(n2385), .Y(n1897) );
NAND2X1TS U1121 ( .A(n2029), .B(n2402), .Y(n1898) );
INVX2TS U1122 ( .A(n986), .Y(n988) );
AND2X6TS U1123 ( .A(n2015), .B(n2262), .Y(n1289) );
AND2X4TS U1124 ( .A(n1959), .B(DMP_SFG[20]), .Y(n1975) );
INVX8TS U1125 ( .A(n2004), .Y(n2188) );
CLKINVX6TS U1126 ( .A(n2532), .Y(n1806) );
NAND2X4TS U1127 ( .A(n2617), .B(n1101), .Y(n2040) );
AND3X2TS U1128 ( .A(n1845), .B(n1824), .C(n1826), .Y(n1473) );
AND3X2TS U1129 ( .A(n1837), .B(n1832), .C(n1823), .Y(n1475) );
CLKINVX6TS U1130 ( .A(n1962), .Y(n1100) );
INVX12TS U1131 ( .A(n1413), .Y(n2131) );
NAND4X4TS U1132 ( .A(n2827), .B(n2826), .C(n2825), .D(n2824), .Y(n2367) );
INVX2TS U1133 ( .A(n2330), .Y(n1464) );
CLKAND2X2TS U1134 ( .A(n1842), .B(n1822), .Y(n1474) );
NAND3X6TS U1135 ( .A(n2781), .B(n1869), .C(n2780), .Y(n864) );
INVX2TS U1136 ( .A(n1316), .Y(n1317) );
NOR2X1TS U1137 ( .A(n1811), .B(DMP_exp_NRM2_EW[7]), .Y(n1788) );
BUFX3TS U1138 ( .A(n2262), .Y(n1356) );
NAND2X4TS U1139 ( .A(n2096), .B(n2385), .Y(n1882) );
NOR2X2TS U1140 ( .A(n1483), .B(n1482), .Y(n1481) );
INVX12TS U1141 ( .A(n1034), .Y(n1035) );
INVX4TS U1142 ( .A(n1525), .Y(n1531) );
NOR2X4TS U1143 ( .A(DMP_EXP_EWSW[24]), .B(n2071), .Y(n2210) );
NAND2X2TS U1144 ( .A(n2468), .B(n1895), .Y(n1876) );
NAND2X2TS U1145 ( .A(n2029), .B(n2404), .Y(n1878) );
NAND2X2TS U1146 ( .A(n2124), .B(n1335), .Y(n1881) );
NOR2X1TS U1147 ( .A(n1678), .B(n1683), .Y(n1110) );
NAND3X2TS U1148 ( .A(n2767), .B(n2766), .C(n2765), .Y(n2077) );
CLKINVX3TS U1149 ( .A(n1322), .Y(n1772) );
AND2X4TS U1150 ( .A(n1237), .B(n2118), .Y(n1525) );
INVX4TS U1151 ( .A(rst), .Y(n1365) );
INVX2TS U1152 ( .A(n976), .Y(n978) );
NAND2X2TS U1153 ( .A(n1960), .B(DMP_SFG[21]), .Y(n1980) );
INVX2TS U1154 ( .A(n1310), .Y(n2071) );
NAND2X2TS U1155 ( .A(n2030), .B(n2353), .Y(n2031) );
OR2X4TS U1156 ( .A(n2674), .B(n1522), .Y(n1993) );
NAND2X6TS U1157 ( .A(n1434), .B(n1436), .Y(n1430) );
BUFX16TS U1158 ( .A(n2259), .Y(n2411) );
XOR2X1TS U1159 ( .A(n1243), .B(n1348), .Y(n1483) );
NAND2X6TS U1160 ( .A(n1682), .B(n2581), .Y(n1678) );
NAND2X2TS U1161 ( .A(n2029), .B(n2468), .Y(n1857) );
NAND2X2TS U1162 ( .A(n2029), .B(n1335), .Y(n1865) );
INVX2TS U1163 ( .A(n1380), .Y(n986) );
BUFX6TS U1164 ( .A(n1858), .Y(n2029) );
INVX2TS U1165 ( .A(n2702), .Y(n1114) );
BUFX3TS U1166 ( .A(n1390), .Y(n1045) );
CLKINVX2TS U1167 ( .A(n1700), .Y(n1769) );
OR2X4TS U1168 ( .A(n1960), .B(DMP_SFG[21]), .Y(n1981) );
CLKBUFX2TS U1169 ( .A(n1362), .Y(n1380) );
AO21X2TS U1170 ( .A0(n1291), .A1(n2243), .B0(n1951), .Y(n1952) );
CLKINVX6TS U1171 ( .A(n2344), .Y(n2237) );
AND2X4TS U1172 ( .A(n1766), .B(n1767), .Y(n1550) );
INVX4TS U1173 ( .A(n1701), .Y(n1820) );
INVX2TS U1174 ( .A(n1273), .Y(n1276) );
NOR2X4TS U1175 ( .A(n1701), .B(n2470), .Y(n1458) );
INVX2TS U1176 ( .A(n2880), .Y(n976) );
INVX4TS U1177 ( .A(n1782), .Y(n1783) );
INVX2TS U1178 ( .A(n1230), .Y(n1231) );
NAND2X2TS U1179 ( .A(n1937), .B(DMP_SFG[13]), .Y(n2510) );
BUFX6TS U1180 ( .A(n1230), .Y(n2262) );
NAND2X4TS U1181 ( .A(n2431), .B(n1291), .Y(n1955) );
CLKBUFX2TS U1182 ( .A(n1371), .Y(n2880) );
NAND2X6TS U1183 ( .A(n1517), .B(n1518), .Y(n1701) );
INVX2TS U1184 ( .A(n1237), .Y(n1408) );
OR2X6TS U1185 ( .A(n1949), .B(DMP_SFG[16]), .Y(n2431) );
NAND2X2TS U1186 ( .A(n1700), .B(n1281), .Y(n1517) );
CLKINVX6TS U1187 ( .A(n1953), .Y(n2528) );
INVX3TS U1188 ( .A(n1946), .Y(n1947) );
NAND2X2TS U1189 ( .A(n1676), .B(n1677), .Y(n1443) );
NAND3X4TS U1190 ( .A(n2320), .B(n1272), .C(n1240), .Y(n1442) );
INVX2TS U1191 ( .A(n1271), .Y(n1272) );
OR2X6TS U1192 ( .A(n2585), .B(intDX_EWSW[28]), .Y(n1066) );
INVX12TS U1193 ( .A(n1053), .Y(n2118) );
INVX8TS U1194 ( .A(n1278), .Y(n1281) );
NAND2X6TS U1195 ( .A(n1697), .B(n1296), .Y(n1767) );
AOI21X2TS U1196 ( .A0(n2845), .A1(Raw_mant_NRM_SWR[4]), .B0(
Raw_mant_NRM_SWR[6]), .Y(n1688) );
INVX2TS U1197 ( .A(n1273), .Y(n1275) );
NAND2X6TS U1198 ( .A(n1699), .B(n1698), .Y(n1765) );
NOR2X6TS U1199 ( .A(n1626), .B(n1076), .Y(n1075) );
INVX2TS U1200 ( .A(n2326), .Y(n1699) );
INVX4TS U1201 ( .A(n1112), .Y(n1113) );
NAND2X2TS U1202 ( .A(n2606), .B(intDX_EWSW[18]), .Y(n1610) );
INVX2TS U1203 ( .A(n1245), .Y(n1246) );
OR2X4TS U1204 ( .A(intDY_EWSW[11]), .B(n1222), .Y(n1579) );
INVX4TS U1205 ( .A(n1683), .Y(n1426) );
AND2X4TS U1206 ( .A(n972), .B(n1524), .Y(n1682) );
NOR2X4TS U1207 ( .A(n2582), .B(intDX_EWSW[24]), .Y(n1076) );
NAND2X2TS U1208 ( .A(n2603), .B(n1346), .Y(n1566) );
NOR2X4TS U1209 ( .A(n2583), .B(n1343), .Y(n1602) );
INVX12TS U1210 ( .A(n2471), .Y(n2500) );
NOR2X2TS U1211 ( .A(n972), .B(n959), .Y(n1674) );
NAND2X1TS U1212 ( .A(n1244), .B(n1348), .Y(n1558) );
NAND2X2TS U1213 ( .A(n2326), .B(n1679), .Y(n1681) );
NAND2X2TS U1214 ( .A(n1261), .B(intDX_EWSW[17]), .Y(n1606) );
AND2X2TS U1215 ( .A(n1698), .B(n1270), .Y(n1296) );
NAND2X4TS U1216 ( .A(n1696), .B(n967), .Y(n1697) );
NOR2X4TS U1217 ( .A(n971), .B(n959), .Y(n2327) );
INVX3TS U1218 ( .A(n1340), .Y(n1341) );
NOR2X4TS U1219 ( .A(n1238), .B(n971), .Y(n1698) );
INVX2TS U1220 ( .A(n1252), .Y(n1120) );
INVX2TS U1221 ( .A(n1260), .Y(n1261) );
INVX2TS U1222 ( .A(n1225), .Y(n1226) );
INVX2TS U1223 ( .A(n1220), .Y(n1221) );
INVX2TS U1224 ( .A(n1264), .Y(n1265) );
INVX2TS U1225 ( .A(n1228), .Y(n1229) );
BUFX16TS U1226 ( .A(intDX_EWSW[20]), .Y(n1390) );
INVX2TS U1227 ( .A(n1559), .Y(n1074) );
NOR2X4TS U1228 ( .A(n1031), .B(n1293), .Y(n1077) );
INVX8TS U1229 ( .A(n1211), .Y(n1212) );
CLKINVX6TS U1230 ( .A(n1251), .Y(n1252) );
NOR2X4TS U1231 ( .A(n1238), .B(n1269), .Y(n1679) );
NAND2X4TS U1232 ( .A(n972), .B(n1078), .Y(n1293) );
INVX4TS U1233 ( .A(n1235), .Y(n1236) );
NOR2X2TS U1234 ( .A(n1271), .B(n967), .Y(n1080) );
NAND2X6TS U1235 ( .A(n1287), .B(n2360), .Y(n842) );
NAND2X8TS U1236 ( .A(n1044), .B(n2352), .Y(n1043) );
NAND3X6TS U1237 ( .A(n1049), .B(n1048), .C(n1913), .Y(n818) );
NAND2X4TS U1238 ( .A(n2136), .B(n2237), .Y(n2137) );
AND2X8TS U1239 ( .A(n2138), .B(n2137), .Y(n2983) );
AND2X8TS U1240 ( .A(n1901), .B(n1061), .Y(n2997) );
AND2X8TS U1241 ( .A(n1905), .B(n1062), .Y(n3011) );
NAND2X4TS U1242 ( .A(n2198), .B(n1376), .Y(n2202) );
NAND2X4TS U1243 ( .A(n2023), .B(n1376), .Y(n2025) );
AOI22X2TS U1244 ( .A0(n1454), .A1(DmP_mant_SHT1_SW[16]), .B0(n2353), .B1(
n2862), .Y(n2967) );
NAND2X2TS U1245 ( .A(n2190), .B(n2353), .Y(n2003) );
AND2X8TS U1246 ( .A(n2240), .B(n2239), .Y(n2985) );
NAND2X4TS U1247 ( .A(n2238), .B(n1376), .Y(n2239) );
NAND4X4TS U1248 ( .A(n1894), .B(n1893), .C(n1892), .D(n1891), .Y(n1902) );
NAND3X6TS U1249 ( .A(n1736), .B(n1737), .C(n1735), .Y(n667) );
NAND2X4TS U1250 ( .A(n958), .B(intDY_EWSW[12]), .Y(n1736) );
NAND2X6TS U1251 ( .A(n2528), .B(n1954), .Y(n2241) );
NOR3X6TS U1252 ( .A(n1530), .B(n1292), .C(n1528), .Y(n1527) );
MXI2X4TS U1253 ( .A(n3007), .B(n1105), .S0(n2492), .Y(n612) );
AND2X8TS U1254 ( .A(n2010), .B(n2009), .Y(n3007) );
NAND2X4TS U1255 ( .A(n961), .B(DmP_mant_SHT1_SW[17]), .Y(n2958) );
NAND3X4TS U1256 ( .A(n1668), .B(n1669), .C(n1667), .Y(n812) );
MX2X4TS U1257 ( .A(n2250), .B(n1269), .S0(n2426), .Y(n619) );
XNOR2X4TS U1258 ( .A(n1717), .B(n1716), .Y(n1719) );
NOR2X2TS U1259 ( .A(n1715), .B(n2162), .Y(n1716) );
AND2X6TS U1260 ( .A(n2197), .B(n2196), .Y(n3021) );
NAND4X6TS U1261 ( .A(n1537), .B(n2332), .C(n1536), .D(n1535), .Y(n2439) );
NAND2X4TS U1262 ( .A(n1396), .B(n1300), .Y(n1395) );
NAND3X4TS U1263 ( .A(n2311), .B(n2310), .C(n2309), .Y(n830) );
NAND2X4TS U1264 ( .A(n2198), .B(n1370), .Y(n2197) );
BUFX16TS U1265 ( .A(n2898), .Y(n1398) );
MX2X4TS U1266 ( .A(Data_X[15]), .B(n1388), .S0(n2524), .Y(n928) );
XOR2X4TS U1267 ( .A(n1334), .B(DmP_mant_SFG_SWR[3]), .Y(n2341) );
NOR2X2TS U1268 ( .A(n2421), .B(n2107), .Y(n2111) );
NAND2X6TS U1269 ( .A(n2102), .B(n2548), .Y(n2206) );
AOI2BB1X4TS U1270 ( .A0N(n1548), .A1N(n2689), .B0(n2393), .Y(n2953) );
INVX6TS U1271 ( .A(n2437), .Y(n1095) );
NAND3X4TS U1272 ( .A(n2091), .B(n1030), .C(n2090), .Y(n809) );
NOR2X2TS U1273 ( .A(n2133), .B(n2545), .Y(n2119) );
NAND3X4TS U1274 ( .A(n2304), .B(n2303), .C(n2302), .Y(n824) );
NAND2X4TS U1275 ( .A(n1314), .B(intDY_EWSW[10]), .Y(n2304) );
NAND3X4TS U1276 ( .A(n2308), .B(n2307), .C(n2306), .Y(n829) );
INVX16TS U1277 ( .A(n1523), .Y(n2326) );
NAND2X8TS U1278 ( .A(n1327), .B(n1524), .Y(n1523) );
NAND2X4TS U1279 ( .A(n2023), .B(n1370), .Y(n1880) );
AND2X8TS U1280 ( .A(n2127), .B(n2126), .Y(n2128) );
NAND3X4TS U1281 ( .A(n1916), .B(n1915), .C(n1914), .Y(n816) );
NAND2X4TS U1282 ( .A(n2104), .B(DMP_SFG[2]), .Y(n2203) );
NOR2X4TS U1283 ( .A(n2104), .B(DMP_SFG[2]), .Y(n2204) );
AND2X8TS U1284 ( .A(n2202), .B(n2201), .Y(n2987) );
INVX4TS U1285 ( .A(n1349), .Y(n1350) );
NAND2X4TS U1286 ( .A(n2458), .B(n1351), .Y(n2961) );
INVX6TS U1287 ( .A(n1858), .Y(n1859) );
NOR2X6TS U1288 ( .A(DMP_EXP_EWSW[23]), .B(n2646), .Y(n2479) );
AND2X6TS U1289 ( .A(n2417), .B(n2340), .Y(n1332) );
NAND2X4TS U1290 ( .A(n1314), .B(intDY_EWSW[22]), .Y(n1669) );
AND2X8TS U1291 ( .A(n2178), .B(n2177), .Y(n3023) );
NAND3X4TS U1292 ( .A(n1759), .B(n1760), .C(n1758), .Y(n826) );
NAND3X4TS U1293 ( .A(n2452), .B(n2453), .C(n2451), .Y(n807) );
NAND2X4TS U1294 ( .A(n1314), .B(intDY_EWSW[27]), .Y(n2453) );
NAND2X8TS U1295 ( .A(n2129), .B(n2128), .Y(n2130) );
NOR2X4TS U1296 ( .A(n2149), .B(DMP_SFG[5]), .Y(n2229) );
NAND2X4TS U1297 ( .A(n2136), .B(n1370), .Y(n2082) );
NAND3X6TS U1298 ( .A(n2709), .B(n2708), .C(n2707), .Y(n2468) );
AND2X8TS U1299 ( .A(n2070), .B(n2069), .Y(n3001) );
OAI21X4TS U1300 ( .A0(n1465), .A1(n1452), .B0(n1456), .Y(n2857) );
CLKINVX12TS U1301 ( .A(n1547), .Y(n1079) );
NAND2X4TS U1302 ( .A(n1046), .B(n1391), .Y(n1645) );
NAND2X4TS U1303 ( .A(n1046), .B(n1394), .Y(n1752) );
NAND2X4TS U1304 ( .A(n1046), .B(intDY_EWSW[12]), .Y(n2314) );
AOI21X2TS U1305 ( .A0(n1455), .A1(DmP_mant_SHT1_SW[9]), .B0(n2371), .Y(n2915) );
NOR2X4TS U1306 ( .A(n1037), .B(n1315), .Y(n1306) );
NAND4X6TS U1307 ( .A(n2785), .B(n2784), .C(n2783), .D(n2782), .Y(n2402) );
AND2X8TS U1308 ( .A(n2159), .B(n2158), .Y(n3009) );
AND2X6TS U1309 ( .A(n2022), .B(n2021), .Y(n2991) );
BUFX20TS U1310 ( .A(n2444), .Y(n1059) );
NOR2X4TS U1311 ( .A(n1441), .B(n1700), .Y(n1440) );
OAI22X4TS U1312 ( .A0(n2398), .A1(n1270), .B0(n2392), .B1(n2411), .Y(n2393)
);
NAND3X6TS U1313 ( .A(n2275), .B(n2274), .C(n2273), .Y(n689) );
AND2X6TS U1314 ( .A(n2037), .B(n2036), .Y(n2993) );
BUFX20TS U1315 ( .A(n1459), .Y(n2863) );
BUFX12TS U1316 ( .A(n2015), .Y(n2030) );
NAND2X2TS U1317 ( .A(n2015), .B(n2402), .Y(n1864) );
NAND2X8TS U1318 ( .A(n2131), .B(n2383), .Y(n1288) );
NAND3X6TS U1319 ( .A(n2278), .B(n2279), .C(n2277), .Y(n681) );
NAND2X4TS U1320 ( .A(n958), .B(intDY_EWSW[5]), .Y(n2278) );
NAND2X4TS U1321 ( .A(n958), .B(intDX_EWSW[3]), .Y(n1730) );
NAND3X6TS U1322 ( .A(n1722), .B(n1721), .C(n1720), .Y(n659) );
AOI2BB2X4TS U1323 ( .B0(n2394), .B1(DmP_mant_SHT1_SW[21]), .A0N(n2844),
.A1N(n2672), .Y(n2979) );
INVX16TS U1324 ( .A(n1037), .Y(n2394) );
CLKINVX12TS U1325 ( .A(n1768), .Y(n1538) );
NAND3X6TS U1326 ( .A(n1639), .B(n1638), .C(n1637), .Y(n663) );
NAND3X6TS U1327 ( .A(n1653), .B(n1654), .C(n1652), .Y(n647) );
NAND3X6TS U1328 ( .A(n2448), .B(n2447), .C(n2446), .Y(n821) );
NAND2X4TS U1329 ( .A(n1534), .B(n1532), .Y(n850) );
NAND3X6TS U1330 ( .A(n2282), .B(n2281), .C(n2280), .Y(n641) );
NAND3X6TS U1331 ( .A(n2298), .B(n2297), .C(n2296), .Y(n806) );
NAND3X6TS U1332 ( .A(n2291), .B(n2290), .C(n2289), .Y(n804) );
NAND3X6TS U1333 ( .A(n2294), .B(n2293), .C(n2292), .Y(n805) );
NAND3X6TS U1334 ( .A(n2301), .B(n2300), .C(n2299), .Y(n828) );
NAND2X4TS U1335 ( .A(n1383), .B(intDY_EWSW[30]), .Y(n2291) );
NAND2X4TS U1336 ( .A(n1383), .B(intDY_EWSW[28]), .Y(n2298) );
NAND2X4TS U1337 ( .A(n1383), .B(intDY_EWSW[29]), .Y(n2294) );
NAND2X4TS U1338 ( .A(n1383), .B(n1348), .Y(n2275) );
NAND2X4TS U1339 ( .A(n1383), .B(intDY_EWSW[6]), .Y(n2301) );
NAND2X4TS U1340 ( .A(n1383), .B(intDY_EWSW[13]), .Y(n2448) );
NAND2X8TS U1341 ( .A(n1367), .B(n1388), .Y(n1642) );
NAND2X6TS U1342 ( .A(n1938), .B(DMP_SFG[14]), .Y(n2527) );
NOR2X8TS U1343 ( .A(n1955), .B(n2242), .Y(n1093) );
BUFX20TS U1344 ( .A(n1367), .Y(n1046) );
OAI21X4TS U1345 ( .A0(n1971), .A1(n2507), .B0(n1970), .Y(n616) );
NAND3X8TS U1346 ( .A(n1642), .B(n1641), .C(n1640), .Y(n661) );
NAND2X6TS U1347 ( .A(n1367), .B(n2522), .Y(n1929) );
NAND2X6TS U1348 ( .A(n1929), .B(n1928), .Y(n1385) );
INVX12TS U1349 ( .A(n1411), .Y(n1425) );
BUFX12TS U1350 ( .A(n1235), .Y(n959) );
NAND2X6TS U1351 ( .A(n960), .B(n2118), .Y(n1708) );
OAI22X4TS U1352 ( .A0(n1706), .A1(n2115), .B0(n2132), .B1(n1705), .Y(n960)
);
NAND2X6TS U1353 ( .A(n1771), .B(n965), .Y(n1704) );
NAND2X6TS U1354 ( .A(n966), .B(n2440), .Y(n2088) );
NAND2X8TS U1355 ( .A(n1367), .B(intDY_EWSW[26]), .Y(n2089) );
NAND3X8TS U1356 ( .A(n2089), .B(n2088), .C(n2087), .Y(n808) );
NAND2X8TS U1357 ( .A(n1420), .B(n1286), .Y(n1419) );
NAND2X8TS U1358 ( .A(n1314), .B(n1264), .Y(n1749) );
AND2X8TS U1359 ( .A(n1880), .B(n1879), .Y(n3013) );
NAND2X1TS U1360 ( .A(n1895), .B(n1335), .Y(n1896) );
CLKINVX1TS U1361 ( .A(n1335), .Y(n1336) );
AOI22X1TS U1362 ( .A0(n2235), .A1(n1370), .B0(n1377), .B1(n1335), .Y(n963)
);
NAND3X6TS U1363 ( .A(n2272), .B(n2271), .C(n2270), .Y(n691) );
AOI2BB2X4TS U1364 ( .B0(n2704), .B1(n1135), .A0N(n1133), .A1N(n2703), .Y(
n1855) );
INVX12TS U1365 ( .A(n964), .Y(n965) );
NAND2X4TS U1366 ( .A(n2352), .B(n1311), .Y(n2864) );
NAND2X6TS U1367 ( .A(n2139), .B(n2352), .Y(n2140) );
INVX8TS U1368 ( .A(n967), .Y(n968) );
BUFX20TS U1369 ( .A(n1429), .Y(n1917) );
BUFX20TS U1370 ( .A(n1927), .Y(n1361) );
BUFX16TS U1371 ( .A(n1927), .Y(n1918) );
BUFX20TS U1372 ( .A(Raw_mant_NRM_SWR[18]), .Y(n970) );
INVX12TS U1373 ( .A(n971), .Y(n972) );
AND2X8TS U1374 ( .A(n1682), .B(n973), .Y(n2320) );
NOR2X4TS U1375 ( .A(n2476), .B(n1683), .Y(n973) );
BUFX20TS U1376 ( .A(Raw_mant_NRM_SWR[25]), .Y(n2476) );
OR2X8TS U1377 ( .A(n2398), .B(n1524), .Y(n974) );
NAND2X8TS U1378 ( .A(n974), .B(n975), .Y(n2146) );
NAND2X6TS U1379 ( .A(n1237), .B(n1770), .Y(n1705) );
MXI2X4TS U1380 ( .A(n2497), .B(n2578), .S0(n980), .Y(n627) );
BUFX12TS U1381 ( .A(n2495), .Y(n981) );
BUFX20TS U1382 ( .A(n2495), .Y(n982) );
MXI2X4TS U1383 ( .A(n2571), .B(n2633), .S0(n982), .Y(n744) );
MXI2X4TS U1384 ( .A(n2573), .B(n2636), .S0(n982), .Y(n750) );
MXI2X4TS U1385 ( .A(n2572), .B(n2675), .S0(n982), .Y(n747) );
MXI2X4TS U1386 ( .A(n2575), .B(n2634), .S0(n982), .Y(n756) );
MXI2X4TS U1387 ( .A(n2570), .B(n2674), .S0(n981), .Y(n741) );
MXI2X4TS U1388 ( .A(n2574), .B(n2637), .S0(n981), .Y(n753) );
BUFX4TS U1389 ( .A(n2498), .Y(n2495) );
INVX2TS U1390 ( .A(n992), .Y(n994) );
INVX2TS U1391 ( .A(n992), .Y(n995) );
INVX2TS U1392 ( .A(n1373), .Y(n1014) );
CLKINVX6TS U1393 ( .A(rst), .Y(n1362) );
INVX2TS U1394 ( .A(n1695), .Y(n1005) );
INVX2TS U1395 ( .A(n2618), .Y(n1010) );
INVX2TS U1396 ( .A(n1010), .Y(n1011) );
NAND2X1TS U1397 ( .A(n2535), .B(final_result_ieee[31]), .Y(n1042) );
CLKINVX12TS U1398 ( .A(n1139), .Y(n1012) );
INVX16TS U1399 ( .A(n1012), .Y(n1013) );
CLKINVX12TS U1400 ( .A(n1140), .Y(n1021) );
INVX16TS U1401 ( .A(n1021), .Y(n1022) );
CLKINVX1TS U1402 ( .A(rst), .Y(n1373) );
INVX2TS U1403 ( .A(n1328), .Y(n1329) );
INVX2TS U1404 ( .A(n1255), .Y(n1256) );
NOR2X1TS U1405 ( .A(n1240), .B(n1271), .Y(n1696) );
NOR2X2TS U1406 ( .A(n1798), .B(DMP_exp_NRM2_EW[5]), .Y(n1799) );
NAND2X2TS U1407 ( .A(n2199), .B(n1356), .Y(n1863) );
NAND2X2TS U1408 ( .A(n2029), .B(n2135), .Y(n2017) );
NAND2X1TS U1409 ( .A(n1291), .B(n2247), .Y(n2248) );
NAND2X1TS U1410 ( .A(n1981), .B(n1980), .Y(n1982) );
NOR2X1TS U1411 ( .A(n2470), .B(n1931), .Y(n1549) );
NOR2X4TS U1412 ( .A(n1037), .B(n1301), .Y(n1416) );
CLKBUFX2TS U1413 ( .A(intDX_EWSW[6]), .Y(n2521) );
MXI2X2TS U1414 ( .A(n2112), .B(n1557), .S0(n2507), .Y(n594) );
NAND2X2TS U1415 ( .A(n2440), .B(n1254), .Y(n1030) );
OR2X8TS U1416 ( .A(Raw_mant_NRM_SWR[18]), .B(n1211), .Y(n1031) );
AND2X4TS U1417 ( .A(n1773), .B(n1526), .Y(n1032) );
AND2X4TS U1418 ( .A(n1450), .B(n1501), .Y(n1499) );
BUFX20TS U1419 ( .A(n1429), .Y(n1257) );
AOI2BB2X4TS U1420 ( .B0(n1455), .B1(DmP_mant_SHT1_SW[2]), .A0N(n1524), .A1N(
n1253), .Y(n2911) );
AOI2BB2X4TS U1421 ( .B0(n2394), .B1(DmP_mant_SHT1_SW[11]), .A0N(n1113),
.A1N(n1253), .Y(n2918) );
NOR2X8TS U1422 ( .A(n1687), .B(Raw_mant_NRM_SWR[2]), .Y(n2335) );
NOR2X6TS U1423 ( .A(Raw_mant_NRM_SWR[1]), .B(n2595), .Y(n1687) );
INVX8TS U1424 ( .A(n2410), .Y(n1034) );
NAND2X4TS U1425 ( .A(n1917), .B(intDX_EWSW[14]), .Y(n1639) );
NAND2X4TS U1426 ( .A(n1917), .B(intDX_EWSW[16]), .Y(n1722) );
NAND2X2TS U1427 ( .A(n1917), .B(n1344), .Y(n1636) );
NAND2X4TS U1428 ( .A(n1917), .B(intDY_EWSW[16]), .Y(n1048) );
XOR2X2TS U1429 ( .A(n2341), .B(n2549), .Y(n2342) );
NAND2X4TS U1430 ( .A(n2449), .B(n1394), .Y(n2441) );
NAND2X4TS U1431 ( .A(n1337), .B(intDX_EWSW[30]), .Y(n2290) );
NAND2X4TS U1432 ( .A(n1337), .B(intDX_EWSW[28]), .Y(n2297) );
NAND2X4TS U1433 ( .A(n1337), .B(intDY_EWSW[27]), .Y(n2281) );
NAND2X4TS U1434 ( .A(n1337), .B(n1391), .Y(n2447) );
NAND2X4TS U1435 ( .A(n1337), .B(n2521), .Y(n2300) );
NAND2X4TS U1436 ( .A(n1337), .B(intDY_EWSW[22]), .Y(n1653) );
AND2X8TS U1437 ( .A(n2025), .B(n2024), .Y(n2995) );
AOI22X2TS U1438 ( .A0(n2348), .A1(n2463), .B0(n2200), .B1(n2097), .Y(n2024)
);
MXI2X8TS U1439 ( .A(n3003), .B(n1011), .S0(n2492), .Y(n584) );
NAND2X4TS U1440 ( .A(n2444), .B(intDY_EWSW[16]), .Y(n1721) );
NAND2X4TS U1441 ( .A(n2444), .B(intDY_EWSW[0]), .Y(n2271) );
NAND2X4TS U1442 ( .A(n2444), .B(n1243), .Y(n2274) );
NAND2X4TS U1443 ( .A(n1058), .B(intDX_EWSW[3]), .Y(n2266) );
NAND4X4TS U1444 ( .A(n2194), .B(n2193), .C(n2192), .D(n2191), .Y(n2198) );
NAND3X6TS U1445 ( .A(n1368), .B(n1991), .C(n1987), .Y(n1854) );
NAND2X4TS U1446 ( .A(n1918), .B(n1220), .Y(n1641) );
NAND2X4TS U1447 ( .A(n1918), .B(intDY_EWSW[10]), .Y(n2287) );
NAND2X4TS U1448 ( .A(n1918), .B(intDY_EWSW[18]), .Y(n2268) );
NAND2X4TS U1449 ( .A(n1918), .B(n1328), .Y(n2093) );
NAND2X4TS U1450 ( .A(n1918), .B(intDY_EWSW[25]), .Y(n2066) );
NAND2X4TS U1451 ( .A(n1361), .B(intDY_EWSW[23]), .Y(n2064) );
NAND2BX4TS U1452 ( .AN(n1382), .B(n2283), .Y(n653) );
NAND2X4TS U1453 ( .A(n1405), .B(n1255), .Y(n2283) );
NAND2X4TS U1454 ( .A(n2605), .B(intDX_EWSW[20]), .Y(n1615) );
INVX12TS U1455 ( .A(n1454), .Y(n1037) );
NAND2X6TS U1456 ( .A(n1311), .B(n1554), .Y(n1044) );
NAND2X6TS U1457 ( .A(n1772), .B(n1526), .Y(n2116) );
NAND4X4TS U1458 ( .A(n1819), .B(n1818), .C(n1817), .D(n1816), .Y(n2358) );
CLKMX2X2TS U1459 ( .A(Data_X[20]), .B(n1045), .S0(n2524), .Y(n923) );
CLKMX2X2TS U1460 ( .A(Data_Y[27]), .B(intDY_EWSW[27]), .S0(n2518), .Y(n882)
);
BUFX6TS U1461 ( .A(n1956), .Y(n2529) );
INVX3TS U1462 ( .A(n2040), .Y(n1091) );
CLKMX2X2TS U1463 ( .A(Data_X[3]), .B(intDX_EWSW[3]), .S0(n2525), .Y(n940) );
INVX4TS U1464 ( .A(n1101), .Y(n1097) );
BUFX12TS U1465 ( .A(n1888), .Y(n1377) );
BUFX16TS U1466 ( .A(n1888), .Y(n2348) );
NOR2X1TS U1467 ( .A(n1036), .B(overflow_flag), .Y(n2351) );
XNOR2X2TS U1468 ( .A(n2342), .B(n2505), .Y(n2343) );
MXI2X2TS U1469 ( .A(n2567), .B(n2631), .S0(n2533), .Y(n771) );
MXI2X2TS U1470 ( .A(n2562), .B(n2635), .S0(n2533), .Y(n759) );
MXI2X2TS U1471 ( .A(n2624), .B(n2548), .S0(n2533), .Y(n789) );
INVX8TS U1472 ( .A(n1884), .Y(n2189) );
NAND2X1TS U1473 ( .A(n2473), .B(n2465), .Y(n952) );
AND2X6TS U1474 ( .A(n1764), .B(n1279), .Y(n1519) );
NAND2X1TS U1475 ( .A(n2295), .B(n813), .Y(n1670) );
INVX2TS U1476 ( .A(n1143), .Y(n1102) );
INVX8TS U1477 ( .A(n2471), .Y(n2472) );
BUFX16TS U1478 ( .A(n2644), .Y(n2899) );
INVX16TS U1479 ( .A(n1277), .Y(n1279) );
NOR2X6TS U1480 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2645), .Y(n2466) );
NAND2X2TS U1481 ( .A(n1415), .B(n1414), .Y(n2388) );
NAND2X2TS U1482 ( .A(n1257), .B(intDY_EWSW[25]), .Y(n2091) );
NAND2X2TS U1483 ( .A(n1361), .B(intDY_EWSW[24]), .Y(n2061) );
NAND2X4TS U1484 ( .A(n1043), .B(n1042), .Y(n624) );
NAND2X6TS U1485 ( .A(n2319), .B(n1425), .Y(n2330) );
INVX4TS U1486 ( .A(n1904), .Y(n1062) );
NOR2X4TS U1487 ( .A(n1546), .B(n1031), .Y(n1703) );
INVX4TS U1488 ( .A(n1900), .Y(n1061) );
NAND2X4TS U1489 ( .A(n2238), .B(n1370), .Y(n2177) );
INVX6TS U1490 ( .A(n1546), .Y(n1081) );
NAND2X2TS U1491 ( .A(n2470), .B(n2469), .Y(n2938) );
NAND2X6TS U1492 ( .A(n1977), .B(n1100), .Y(n1099) );
MXI2X2TS U1493 ( .A(Data_Y[31]), .B(intDY_EWSW[31]), .S0(n2515), .Y(n1555)
);
NOR2X4TS U1494 ( .A(n2241), .B(n1955), .Y(n1957) );
NAND2X6TS U1495 ( .A(n1097), .B(DMP_SFG[22]), .Y(n2039) );
NAND2X6TS U1496 ( .A(n1520), .B(n1993), .Y(n1977) );
NAND4X6TS U1497 ( .A(n1475), .B(n1474), .C(n1473), .D(n1472), .Y(n1471) );
MXI2X2TS U1498 ( .A(n1317), .B(n2343), .S0(n1357), .Y(n599) );
INVX6TS U1499 ( .A(n1083), .Y(n1082) );
INVX16TS U1500 ( .A(n2259), .Y(n2470) );
CLKMX2X2TS U1501 ( .A(Data_X[0]), .B(intDX_EWSW[0]), .S0(n2518), .Y(n943) );
INVX6TS U1502 ( .A(n2381), .Y(n1124) );
AND2X4TS U1503 ( .A(n1841), .B(n1830), .Y(n1472) );
NAND4X4TS U1504 ( .A(n1480), .B(n1479), .C(n1478), .D(n1477), .Y(n1476) );
CLKMX2X2TS U1505 ( .A(n2626), .B(n2547), .S0(n2499), .Y(n1556) );
INVX2TS U1506 ( .A(n2147), .Y(n1711) );
NAND2X6TS U1507 ( .A(n2326), .B(n1270), .Y(n1083) );
MXI2X2TS U1508 ( .A(n2622), .B(n2576), .S0(n2533), .Y(n765) );
NAND2X4TS U1509 ( .A(n1521), .B(n1994), .Y(n1520) );
BUFX6TS U1510 ( .A(n2519), .Y(n2515) );
MXI2X2TS U1511 ( .A(n2564), .B(n2684), .S0(n2533), .Y(n768) );
INVX6TS U1512 ( .A(n2135), .Y(n2381) );
INVX4TS U1513 ( .A(n2430), .Y(n2243) );
CLKMX2X3TS U1514 ( .A(DmP_mant_SHT1_SW[18]), .B(DmP_EXP_EWSW[18]), .S0(n2526), .Y(n654) );
INVX2TS U1515 ( .A(n1809), .Y(n1798) );
CLKMX2X3TS U1516 ( .A(DmP_mant_SHT1_SW[4]), .B(n1217), .S0(n2526), .Y(n682)
);
CLKMX2X2TS U1517 ( .A(DmP_mant_SHT1_SW[13]), .B(n665), .S0(n2482), .Y(n664)
);
CLKMX2X3TS U1518 ( .A(DmP_mant_SHT1_SW[3]), .B(n1215), .S0(n2526), .Y(n684)
);
CLKMX2X3TS U1519 ( .A(DmP_mant_SHT1_SW[2]), .B(n1309), .S0(n2488), .Y(n686)
);
CLKMX2X3TS U1520 ( .A(DmP_mant_SHT1_SW[12]), .B(n1216), .S0(n2488), .Y(n666)
);
CLKMX2X2TS U1521 ( .A(DmP_mant_SHT1_SW[11]), .B(n669), .S0(n2488), .Y(n668)
);
BUFX12TS U1522 ( .A(n2305), .Y(n2276) );
NAND2X1TS U1523 ( .A(n2305), .B(n1217), .Y(n1755) );
CLKMX2X3TS U1524 ( .A(DmP_mant_SHT1_SW[10]), .B(DmP_EXP_EWSW[10]), .S0(n2488), .Y(n670) );
AND2X4TS U1525 ( .A(n1839), .B(n1836), .Y(n1470) );
INVX6TS U1526 ( .A(n1273), .Y(n1039) );
NOR2X4TS U1527 ( .A(n1251), .B(n1240), .Y(n1078) );
INVX6TS U1528 ( .A(n1243), .Y(n1244) );
INVX2TS U1529 ( .A(n1262), .Y(n1263) );
INVX2TS U1530 ( .A(n1238), .Y(n1239) );
INVX2TS U1531 ( .A(n1104), .Y(n1105) );
INVX16TS U1532 ( .A(Shift_reg_FLAGS_7[2]), .Y(n2507) );
NAND2X4TS U1533 ( .A(n1249), .B(n1352), .Y(n2939) );
MX2X2TS U1534 ( .A(n2439), .B(LZD_output_NRM2_EW[3]), .S0(n1274), .Y(n598)
);
NAND3X6TS U1535 ( .A(n2374), .B(n2373), .C(n2372), .Y(n2460) );
NAND3X6TS U1536 ( .A(n2363), .B(n2362), .C(n2361), .Y(n2459) );
NAND3X6TS U1537 ( .A(n2380), .B(n2379), .C(n2378), .Y(n2461) );
INVX2TS U1538 ( .A(n2255), .Y(n2256) );
NAND2X4TS U1539 ( .A(n2332), .B(n2337), .Y(n1462) );
MX2X2TS U1540 ( .A(n2438), .B(n1266), .S0(n2507), .Y(n618) );
NAND3X6TS U1541 ( .A(n1804), .B(n2418), .C(n2534), .Y(n1805) );
NAND3X4TS U1542 ( .A(n1099), .B(n2039), .C(n1098), .Y(n1089) );
MX2X2TS U1543 ( .A(n2531), .B(n1240), .S0(n2426), .Y(n622) );
NOR3X6TS U1544 ( .A(n1476), .B(n1471), .C(n1468), .Y(n1467) );
NAND2X4TS U1545 ( .A(n1956), .B(n1957), .Y(n1094) );
XOR2X2TS U1546 ( .A(n2168), .B(n2167), .Y(n2169) );
NAND2X4TS U1547 ( .A(n1409), .B(n1322), .Y(n1773) );
MX2X2TS U1548 ( .A(n2514), .B(n967), .S0(n2507), .Y(n623) );
OAI2BB1X2TS U1549 ( .A0N(OP_FLAG_EXP), .A1N(n2295), .B0(n2226), .Y(n803) );
NAND2X4TS U1550 ( .A(n2039), .B(n1091), .Y(n1090) );
XOR2X2TS U1551 ( .A(n2074), .B(n2073), .Y(n2075) );
CLKMX2X2TS U1552 ( .A(Data_X[24]), .B(intDX_EWSW[24]), .S0(n2523), .Y(n919)
);
CLKMX2X2TS U1553 ( .A(Data_X[6]), .B(n2521), .S0(n2525), .Y(n937) );
CLKMX2X2TS U1554 ( .A(Data_X[7]), .B(n1392), .S0(n2525), .Y(n936) );
CLKMX2X2TS U1555 ( .A(Data_Y[13]), .B(intDY_EWSW[13]), .S0(n2516), .Y(n896)
);
CLKMX2X2TS U1556 ( .A(Data_Y[30]), .B(intDY_EWSW[30]), .S0(n2523), .Y(n879)
);
CLKMX2X2TS U1557 ( .A(Data_Y[12]), .B(intDY_EWSW[12]), .S0(n2516), .Y(n897)
);
CLKMX2X2TS U1558 ( .A(Data_Y[6]), .B(intDY_EWSW[6]), .S0(n2517), .Y(n903) );
CLKMX2X2TS U1559 ( .A(Data_Y[11]), .B(intDY_EWSW[11]), .S0(n2517), .Y(n898)
);
CLKMX2X2TS U1560 ( .A(Data_Y[10]), .B(intDY_EWSW[10]), .S0(n2517), .Y(n899)
);
CLKMX2X2TS U1561 ( .A(Data_Y[9]), .B(intDY_EWSW[9]), .S0(n2517), .Y(n900) );
AND2X6TS U1562 ( .A(n2038), .B(n2040), .Y(n1088) );
CLKMX2X2TS U1563 ( .A(Data_Y[5]), .B(intDY_EWSW[5]), .S0(n2517), .Y(n904) );
CLKMX2X2TS U1564 ( .A(Data_X[9]), .B(n1399), .S0(n2525), .Y(n934) );
CLKMX2X2TS U1565 ( .A(Data_X[10]), .B(n1389), .S0(n2525), .Y(n933) );
CLKMX2X2TS U1566 ( .A(Data_Y[29]), .B(intDY_EWSW[29]), .S0(n2518), .Y(n880)
);
CLKMX2X2TS U1567 ( .A(Data_Y[4]), .B(intDY_EWSW[4]), .S0(n2517), .Y(n905) );
CLKMX2X2TS U1568 ( .A(Data_X[11]), .B(n1394), .S0(n2525), .Y(n932) );
CLKMX2X2TS U1569 ( .A(Data_Y[14]), .B(intDY_EWSW[14]), .S0(n2516), .Y(n895)
);
CLKMX2X2TS U1570 ( .A(Data_X[12]), .B(intDX_EWSW[12]), .S0(n2524), .Y(n931)
);
CLKMX2X2TS U1571 ( .A(Data_Y[16]), .B(intDY_EWSW[16]), .S0(n2516), .Y(n893)
);
CLKMX2X2TS U1572 ( .A(Data_X[13]), .B(n1391), .S0(n2524), .Y(n930) );
CLKMX2X2TS U1573 ( .A(Data_Y[28]), .B(intDY_EWSW[28]), .S0(n2518), .Y(n881)
);
CLKMX2X2TS U1574 ( .A(Data_X[16]), .B(intDX_EWSW[16]), .S0(n2524), .Y(n927)
);
CLKMX2X2TS U1575 ( .A(Data_Y[26]), .B(intDY_EWSW[26]), .S0(n2518), .Y(n883)
);
CLKMX2X2TS U1576 ( .A(Data_Y[25]), .B(intDY_EWSW[25]), .S0(n2518), .Y(n884)
);
CLKMX2X2TS U1577 ( .A(Data_Y[24]), .B(intDY_EWSW[24]), .S0(n2518), .Y(n885)
);
CLKMX2X2TS U1578 ( .A(Data_X[17]), .B(n2522), .S0(n2524), .Y(n926) );
CLKMX2X2TS U1579 ( .A(Data_X[28]), .B(intDX_EWSW[28]), .S0(n2523), .Y(n915)
);
CLKMX2X2TS U1580 ( .A(Data_X[18]), .B(n2520), .S0(n2524), .Y(n925) );
CLKMX2X2TS U1581 ( .A(Data_Y[22]), .B(intDY_EWSW[22]), .S0(n2518), .Y(n887)
);
CLKMX2X2TS U1582 ( .A(Data_X[19]), .B(n1393), .S0(n2524), .Y(n924) );
CLKMX2X2TS U1583 ( .A(Data_Y[21]), .B(intDY_EWSW[21]), .S0(n2516), .Y(n888)
);
CLKMX2X2TS U1584 ( .A(Data_Y[20]), .B(intDY_EWSW[20]), .S0(n2516), .Y(n889)
);
CLKMX2X2TS U1585 ( .A(Data_Y[15]), .B(n1220), .S0(n2516), .Y(n894) );
CLKMX2X2TS U1586 ( .A(Data_Y[17]), .B(n1260), .S0(n2516), .Y(n892) );
CLKMX2X2TS U1587 ( .A(Data_Y[19]), .B(n1255), .S0(n2516), .Y(n890) );
CLKMX2X2TS U1588 ( .A(Data_X[1]), .B(n1348), .S0(n2518), .Y(n942) );
CLKMX2X2TS U1589 ( .A(Data_X[22]), .B(n1343), .S0(n2523), .Y(n921) );
CLKMX2X2TS U1590 ( .A(Data_Y[2]), .B(n1264), .S0(n2517), .Y(n907) );
CLKMX2X2TS U1591 ( .A(Data_X[4]), .B(n1339), .S0(n2525), .Y(n939) );
CLKMX2X2TS U1592 ( .A(Data_X[25]), .B(n1254), .S0(n2523), .Y(n918) );
CLKMX2X2TS U1593 ( .A(Data_X[5]), .B(n1346), .S0(n2525), .Y(n938) );
CLKMX2X2TS U1594 ( .A(Data_Y[3]), .B(n1262), .S0(n2517), .Y(n906) );
CLKMX2X2TS U1595 ( .A(Data_Y[7]), .B(n1225), .S0(n2517), .Y(n902) );
CLKMX2X2TS U1596 ( .A(Data_X[23]), .B(n1328), .S0(n2523), .Y(n920) );
CLKMX2X2TS U1597 ( .A(Data_X[27]), .B(n1258), .S0(n2523), .Y(n916) );
CLKMX2X2TS U1598 ( .A(Data_Y[8]), .B(n1228), .S0(n2517), .Y(n901) );
NAND2BX2TS U1599 ( .AN(n2671), .B(n979), .Y(n1054) );
NAND2X6TS U1600 ( .A(n1865), .B(n1864), .Y(n2187) );
NAND3X4TS U1601 ( .A(n1898), .B(n1897), .C(n1896), .Y(n2123) );
NAND2X4TS U1602 ( .A(n2017), .B(n2016), .Y(n2172) );
INVX8TS U1603 ( .A(n2384), .Y(n1868) );
INVX12TS U1604 ( .A(n1931), .Y(n2383) );
INVX16TS U1605 ( .A(n1673), .Y(n2259) );
INVX2TS U1606 ( .A(n2148), .Y(n2150) );
NAND2X6TS U1607 ( .A(n2608), .B(n1074), .Y(n1073) );
CLKINVX6TS U1608 ( .A(n2434), .Y(n1521) );
NAND2X6TS U1609 ( .A(n1976), .B(n1981), .Y(n1962) );
CLKMX2X2TS U1610 ( .A(ZERO_FLAG_NRM), .B(ZERO_FLAG_SFG), .S0(n1357), .Y(n635) );
NAND2X4TS U1611 ( .A(n1714), .B(DMP_SFG[9]), .Y(n2161) );
AND2X2TS U1612 ( .A(n2445), .B(DmP_EXP_EWSW[19]), .Y(n1299) );
CLKMX2X2TS U1613 ( .A(DmP_mant_SHT1_SW[15]), .B(DmP_EXP_EWSW[15]), .S0(n2482), .Y(n660) );
INVX8TS U1614 ( .A(n2295), .Y(n1432) );
NAND2X4TS U1615 ( .A(n1704), .B(n1280), .Y(n1706) );
NOR2X2TS U1616 ( .A(n1988), .B(n2295), .Y(n1989) );
NAND2X2TS U1617 ( .A(n2276), .B(n649), .Y(n1634) );
NAND2X2TS U1618 ( .A(n2276), .B(n651), .Y(n1723) );
NAND2X2TS U1619 ( .A(n2285), .B(n665), .Y(n1643) );
NAND2X2TS U1620 ( .A(n2285), .B(n675), .Y(n1732) );
NAND2X2TS U1621 ( .A(n2285), .B(n677), .Y(n1646) );
NAND2X2TS U1622 ( .A(n2445), .B(n822), .Y(n2312) );
NAND2X2TS U1623 ( .A(n2285), .B(n827), .Y(n1741) );
INVX2TS U1624 ( .A(n1975), .Y(n1410) );
INVX4TS U1625 ( .A(n1790), .Y(n1780) );
CLKMX2X2TS U1626 ( .A(DmP_mant_SHT1_SW[17]), .B(n657), .S0(n2474), .Y(n656)
);
NAND2X6TS U1627 ( .A(n1958), .B(DMP_SFG[18]), .Y(n2434) );
NOR3X6TS U1628 ( .A(n2476), .B(n1211), .C(n1269), .Y(n1541) );
XNOR2X1TS U1629 ( .A(n1398), .B(n609), .Y(n2483) );
NAND2X6TS U1630 ( .A(n1522), .B(n2674), .Y(n1994) );
BUFX16TS U1631 ( .A(n2305), .Y(n2295) );
INVX2TS U1632 ( .A(n609), .Y(n2685) );
NOR2X4TS U1633 ( .A(DMP_SFG[8]), .B(n1712), .Y(n2182) );
NOR2X6TS U1634 ( .A(n2225), .B(n2224), .Y(n2503) );
NOR2X2TS U1635 ( .A(n1987), .B(intDX_EWSW[31]), .Y(n1988) );
INVX12TS U1636 ( .A(n2480), .Y(n2474) );
INVX12TS U1637 ( .A(n2507), .Y(n1358) );
AND2X4TS U1638 ( .A(n1106), .B(DMP_SFG[12]), .Y(n1934) );
AND2X4TS U1639 ( .A(n1828), .B(n1825), .Y(n1469) );
NAND2X2TS U1640 ( .A(n1375), .B(n970), .Y(n1050) );
BUFX12TS U1641 ( .A(n2305), .Y(n2285) );
CLKBUFX3TS U1642 ( .A(n978), .Y(n2870) );
INVX2TS U1643 ( .A(n2540), .Y(n2502) );
INVX2TS U1644 ( .A(DmP_mant_SHT1_SW[16]), .Y(n2143) );
INVX12TS U1645 ( .A(n2648), .Y(n2488) );
NAND2BX2TS U1646 ( .AN(n1208), .B(n1207), .Y(n832) );
BUFX4TS U1647 ( .A(intDX_EWSW[18]), .Y(n2520) );
INVX2TS U1648 ( .A(SIGN_FLAG_SHT2), .Y(n2497) );
NOR2X2TS U1649 ( .A(n2640), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2224) );
INVX2TS U1650 ( .A(n2845), .Y(n1108) );
INVX12TS U1651 ( .A(n2688), .Y(n2475) );
NAND2BX2TS U1652 ( .AN(n1206), .B(n1205), .Y(n657) );
CLKINVX6TS U1653 ( .A(LZD_output_NRM2_EW[0]), .Y(n1052) );
BUFX8TS U1654 ( .A(n2642), .Y(n1374) );
INVX8TS U1655 ( .A(n1269), .Y(n1270) );
INVX4TS U1656 ( .A(n1334), .Y(n1709) );
INVX12TS U1657 ( .A(Shift_reg_FLAGS_7_6), .Y(n2305) );
OAI2BB1X2TS U1658 ( .A0N(n2786), .A1N(n1131), .B0(n1137), .Y(underflow_flag)
);
NAND4X4TS U1659 ( .A(n2797), .B(n2796), .C(n2795), .D(n2794), .Y(n2385) );
INVX16TS U1660 ( .A(Shift_reg_FLAGS_7_5), .Y(n2480) );
BUFX8TS U1661 ( .A(n2642), .Y(n1375) );
INVX12TS U1662 ( .A(n1266), .Y(n1524) );
NAND2X6TS U1663 ( .A(DmP_mant_SFG_SWR_signed[12]), .B(DMP_SFG[10]), .Y(n2165) );
INVX16TS U1664 ( .A(n2476), .Y(n1040) );
INVX8TS U1665 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1278) );
NAND2X2TS U1666 ( .A(n1267), .B(intDX_EWSW[26]), .Y(n2059) );
NAND3X6TS U1667 ( .A(n2058), .B(n2059), .C(n2057), .Y(n642) );
NOR2X8TS U1668 ( .A(n2588), .B(intDX_EWSW[9]), .Y(n1578) );
NOR2X6TS U1669 ( .A(n2599), .B(intDX_EWSW[26]), .Y(n1063) );
NAND2X4TS U1670 ( .A(n1257), .B(n1258), .Y(n2282) );
NAND3BX4TS U1671 ( .AN(n1103), .B(n2266), .C(n2265), .Y(n685) );
INVX16TS U1672 ( .A(n1419), .Y(n1543) );
NAND2X4TS U1673 ( .A(n1393), .B(n1267), .Y(n2284) );
NAND2X8TS U1674 ( .A(n1338), .B(n2368), .Y(n1407) );
BUFX12TS U1675 ( .A(n1450), .Y(n1496) );
NAND3BX4TS U1676 ( .AN(n1298), .B(n2441), .C(n2442), .Y(n823) );
OAI21X4TS U1677 ( .A0(n1051), .A1(n1375), .B0(n1050), .Y(n620) );
XNOR2X4TS U1678 ( .A(n2433), .B(n2432), .Y(n1051) );
NAND2X2TS U1679 ( .A(n1257), .B(intDX_EWSW[2]), .Y(n1754) );
NAND3BX4TS U1680 ( .AN(n1123), .B(n1754), .C(n1753), .Y(n687) );
NAND2X2TS U1681 ( .A(DmP_mant_SFG_SWR_signed[13]), .B(DMP_SFG[11]), .Y(n1933) );
AOI2BB2X4TS U1682 ( .B0(n2701), .B1(n1135), .A0N(n1133), .A1N(n2700), .Y(
n2094) );
NAND3X8TS U1683 ( .A(n1424), .B(n1682), .C(n1426), .Y(n1411) );
AND2X8TS U1684 ( .A(n1446), .B(n1006), .Y(n1444) );
NAND2X8TS U1685 ( .A(n1466), .B(n1427), .Y(n1387) );
AOI22X4TS U1686 ( .A0(n1351), .A1(n2454), .B0(n1945), .B1(n1427), .Y(n2909)
);
OAI21X4TS U1687 ( .A0(n1792), .A1(n1793), .B0(n1791), .Y(n1794) );
NOR2X8TS U1688 ( .A(n2587), .B(DMP_exp_NRM2_EW[3]), .Y(n1792) );
NOR2X8TS U1689 ( .A(n1052), .B(DMP_exp_NRM2_EW[0]), .Y(n1248) );
NOR2X6TS U1690 ( .A(intDX_EWSW[2]), .B(n1265), .Y(n1560) );
NAND3X4TS U1691 ( .A(n1445), .B(n1006), .C(n1446), .Y(n1249) );
NAND3X8TS U1692 ( .A(n1079), .B(n1077), .C(n1081), .Y(n1053) );
OAI21X4TS U1693 ( .A0(n1248), .A1(n1782), .B0(n1784), .Y(n1796) );
OR3X6TS U1694 ( .A(n2586), .B(n2913), .C(n2262), .Y(n1884) );
INVX12TS U1695 ( .A(n2131), .Y(n1465) );
NAND2X4TS U1696 ( .A(n2190), .B(n2141), .Y(n1886) );
OAI21X2TS U1697 ( .A0(n1055), .A1(n980), .B0(n1054), .Y(n603) );
AOI22X2TS U1698 ( .A0(n2130), .A1(n1376), .B0(n2236), .B1(n2468), .Y(n1055)
);
OAI21X2TS U1699 ( .A0(n1057), .A1(n982), .B0(n1056), .Y(n544) );
AOI22X2TS U1700 ( .A0(n2130), .A1(n1370), .B0(n2348), .B1(n2468), .Y(n1057)
);
MXI2X4TS U1701 ( .A(n2068), .B(n2067), .S0(n2237), .Y(n2070) );
XOR2X4TS U1702 ( .A(n582), .B(n630), .Y(n2711) );
MXI2X8TS U1703 ( .A(n3005), .B(n2849), .S0(n2492), .Y(n582) );
AOI22X2TS U1704 ( .A0(n2463), .A1(n1308), .B0(n2124), .B1(n864), .Y(n2127)
);
NAND2X6TS U1705 ( .A(n2594), .B(n1339), .Y(n1567) );
BUFX12TS U1706 ( .A(n1368), .Y(n1058) );
NOR2X8TS U1707 ( .A(n1221), .B(intDX_EWSW[15]), .Y(n1590) );
NOR3X6TS U1708 ( .A(n1462), .B(n1461), .C(n2334), .Y(n1460) );
AND2X8TS U1709 ( .A(n2118), .B(n2117), .Y(n2120) );
AOI22X4TS U1710 ( .A0(n1351), .A1(n1945), .B0(n2462), .B1(n1427), .Y(n2945)
);
NAND2X8TS U1711 ( .A(n1539), .B(n1702), .Y(n1768) );
NAND4X4TS U1712 ( .A(n2014), .B(n2013), .C(n2012), .D(n2011), .Y(n2020) );
AOI2BB2X4TS U1713 ( .B0(n2706), .B1(n1135), .A0N(n1129), .A1N(n1127), .Y(
n1906) );
NOR2X8TS U1714 ( .A(n1071), .B(n1063), .Y(n1629) );
NOR2X6TS U1715 ( .A(n2589), .B(n1258), .Y(n1071) );
OAI21X4TS U1716 ( .A0(n1069), .A1(n1633), .B0(n1064), .Y(n1489) );
AOI22X4TS U1717 ( .A0(n1065), .A1(n1067), .B0(intDX_EWSW[30]), .B1(n2600),
.Y(n1064) );
OAI21X4TS U1718 ( .A0(n1632), .A1(n1631), .B0(n1630), .Y(n1065) );
NAND3X8TS U1719 ( .A(n1068), .B(n1067), .C(n1066), .Y(n1633) );
OR2X8TS U1720 ( .A(n2600), .B(intDX_EWSW[30]), .Y(n1067) );
CLKINVX6TS U1721 ( .A(n1632), .Y(n1068) );
AOI21X4TS U1722 ( .A0(n1072), .A1(n1629), .B0(n1070), .Y(n1069) );
OAI21X4TS U1723 ( .A0(n1071), .A1(n1628), .B0(n1627), .Y(n1070) );
OAI21X4TS U1724 ( .A0(n1626), .A1(n1625), .B0(n1624), .Y(n1072) );
NOR2X6TS U1725 ( .A(n2604), .B(n1254), .Y(n1626) );
NAND2X4TS U1726 ( .A(n1405), .B(intDY_EWSW[14]), .Y(n1638) );
NAND2X4TS U1727 ( .A(n1337), .B(intDX_EWSW[29]), .Y(n2293) );
OAI21X4TS U1728 ( .A0(n1073), .A1(n1028), .B0(n1558), .Y(n1516) );
NAND3X8TS U1729 ( .A(n2581), .B(n970), .C(n2327), .Y(n1680) );
NAND2X4TS U1730 ( .A(n2599), .B(intDX_EWSW[26]), .Y(n1628) );
NOR2X4TS U1731 ( .A(n1605), .B(n1633), .Y(n1490) );
NOR2X8TS U1732 ( .A(n2601), .B(intDX_EWSW[29]), .Y(n1632) );
NAND2X8TS U1733 ( .A(n1629), .B(n1075), .Y(n1605) );
NAND3X8TS U1734 ( .A(n2318), .B(n1686), .C(n1080), .Y(n1547) );
NOR2X8TS U1735 ( .A(Raw_mant_NRM_SWR[13]), .B(n1112), .Y(n2318) );
NAND2X8TS U1736 ( .A(n1040), .B(n1082), .Y(n1546) );
CLKINVX12TS U1737 ( .A(n1497), .Y(n1338) );
NAND2X8TS U1738 ( .A(n1282), .B(n1694), .Y(n1497) );
BUFX20TS U1739 ( .A(n1407), .Y(n1084) );
NAND2X8TS U1740 ( .A(n1774), .B(n2331), .Y(n1085) );
AND2X8TS U1741 ( .A(n1283), .B(n1262), .Y(n1563) );
AOI21X4TS U1742 ( .A0(n1502), .A1(DmP_mant_SHT1_SW[11]), .B0(n1086), .Y(
n2856) );
XOR2X4TS U1743 ( .A(DmP_mant_SFG_SWR[19]), .B(n1334), .Y(n1950) );
OAI2BB1X4TS U1744 ( .A0N(n1090), .A1N(n1089), .B0(n1087), .Y(n2043) );
NAND2X8TS U1745 ( .A(n1092), .B(n1094), .Y(n1992) );
NOR2X8TS U1746 ( .A(n1952), .B(n1093), .Y(n1092) );
INVX12TS U1747 ( .A(n1992), .Y(n2437) );
AOI21X4TS U1748 ( .A0(n1975), .A1(n1981), .B0(n1961), .Y(n1098) );
XOR2X4TS U1749 ( .A(DmP_mant_SFG_SWR[24]), .B(n1102), .Y(n1101) );
AND2X4TS U1750 ( .A(n2444), .B(n1262), .Y(n1103) );
NAND3X4TS U1751 ( .A(n1854), .B(n1853), .C(n1852), .Y(n801) );
BUFX16TS U1752 ( .A(n1429), .Y(n1314) );
XOR2X4TS U1753 ( .A(n2848), .B(n1104), .Y(n1106) );
NAND4BX4TS U1754 ( .AN(n1107), .B(n2028), .C(n2027), .D(n2026), .Y(n2035) );
AND2X4TS U1755 ( .A(n1289), .B(n1124), .Y(n1107) );
OAI22X4TS U1756 ( .A0(n2847), .A1(n1428), .B0(n1253), .B1(n1317), .Y(n2904)
);
BUFX6TS U1757 ( .A(n2118), .Y(n1526) );
AOI2BB2X2TS U1758 ( .B0(n2407), .B1(n1108), .A0N(n1084), .A1N(n2846), .Y(
n2920) );
INVX16TS U1759 ( .A(n2375), .Y(n2407) );
INVX6TS U1760 ( .A(n1253), .Y(n2376) );
AOI22X2TS U1761 ( .A0(n2407), .A1(n1316), .B0(n2376), .B1(
Raw_mant_NRM_SWR[5]), .Y(n2969) );
INVX8TS U1762 ( .A(n1109), .Y(n1548) );
NOR2X8TS U1763 ( .A(n1605), .B(n1604), .Y(n1111) );
NAND2X6TS U1764 ( .A(n1600), .B(n1612), .Y(n1604) );
NOR2X6TS U1765 ( .A(n1605), .B(n1604), .Y(n1492) );
BUFX20TS U1766 ( .A(n1267), .Y(n1367) );
AOI2BB2X4TS U1767 ( .B0(n1115), .B1(n1114), .A0N(n1116), .A1N(n1117), .Y(
n2122) );
NAND3X6TS U1768 ( .A(n1121), .B(n1270), .C(n1120), .Y(n1320) );
AND2X8TS U1769 ( .A(n1040), .B(n968), .Y(n1121) );
NAND2X6TS U1770 ( .A(n1488), .B(n1490), .Y(n1433) );
NAND2X4TS U1771 ( .A(n1361), .B(intDX_EWSW[24]), .Y(n2085) );
AND2X4TS U1772 ( .A(n2444), .B(n1264), .Y(n1123) );
AND2X8TS U1773 ( .A(n1821), .B(n1487), .Y(n1290) );
INVX2TS U1774 ( .A(n1125), .Y(n1126) );
INVX12TS U1775 ( .A(n2414), .Y(n1420) );
OAI21X2TS U1776 ( .A0(n1719), .A1(n1375), .B0(n1718), .Y(n575) );
OAI22X2TS U1777 ( .A0(n1165), .A1(n1132), .B0(n1128), .B1(n1127), .Y(n2927)
);
OAI22X2TS U1778 ( .A0(n1134), .A1(n2777), .B0(n1138), .B1(n2776), .Y(
final_result_ieee[17]) );
OAI22X2TS U1779 ( .A0(n1134), .A1(n2754), .B0(n1136), .B1(n2753), .Y(
final_result_ieee[2]) );
MXI2X4TS U1780 ( .A(n3015), .B(n1126), .S0(n980), .Y(n551) );
BUFX8TS U1781 ( .A(n1334), .Y(n1143) );
XOR2X4TS U1782 ( .A(n1334), .B(DmP_mant_SFG_SWR[23]), .Y(n1960) );
XOR2X4TS U1783 ( .A(n1334), .B(DmP_mant_SFG_SWR[17]), .Y(n1939) );
XOR2X4TS U1784 ( .A(n1334), .B(DmP_mant_SFG_SWR[16]), .Y(n1938) );
XOR2X4TS U1785 ( .A(n1334), .B(DmP_mant_SFG_SWR[10]), .Y(n1712) );
NAND2X2TS U1786 ( .A(n2103), .B(DMP_SFG[3]), .Y(n2227) );
XOR2X4TS U1787 ( .A(n1334), .B(n1125), .Y(n1949) );
INVX2TS U1788 ( .A(n1712), .Y(n1142) );
OAI22X4TS U1789 ( .A0(n1149), .A1(n1148), .B0(n1128), .B1(n1147), .Y(n2981)
);
MXI2X2TS U1790 ( .A(n1155), .B(n1154), .S0(n1153), .Y(n609) );
CLKMX2X2TS U1791 ( .A(DMP_SHT1_EWSW[19]), .B(n815), .S0(n2501), .Y(n743) );
NAND2X1TS U1792 ( .A(n2638), .B(n815), .Y(n1664) );
CLKMX2X2TS U1793 ( .A(DMP_SHT1_EWSW[20]), .B(n814), .S0(n2526), .Y(n740) );
NAND2X1TS U1794 ( .A(n2638), .B(n814), .Y(n1919) );
NAND3X2TS U1795 ( .A(n1171), .B(n1170), .C(n1169), .Y(n669) );
NOR2X4TS U1796 ( .A(n2844), .B(n2143), .Y(n1397) );
NAND4X6TS U1797 ( .A(n2721), .B(n2720), .C(n2921), .D(n2719), .Y(n2141) );
NOR2X6TS U1798 ( .A(n1176), .B(n1175), .Y(n2921) );
AOI22X4TS U1799 ( .A0(n1186), .A1(n1185), .B0(n1184), .B1(n1183), .Y(n2926)
);
NAND2BX1TS U1800 ( .AN(n1113), .B(n1543), .Y(n2908) );
MXI2X2TS U1801 ( .A(n1926), .B(n2596), .S0(n2507), .Y(n581) );
OR2X4TS U1802 ( .A(Raw_mant_NRM_SWR[13]), .B(n1251), .Y(n2252) );
NOR2X1TS U1803 ( .A(n2318), .B(n1251), .Y(n2319) );
NAND3X4TS U1804 ( .A(n1451), .B(n2368), .C(Raw_mant_NRM_SWR[13]), .Y(n2369)
);
INVX8TS U1805 ( .A(n1450), .Y(n1495) );
NAND2X2TS U1806 ( .A(n1545), .B(Raw_mant_NRM_SWR[13]), .Y(n2944) );
BUFX12TS U1807 ( .A(n2642), .Y(n2426) );
AOI22X2TS U1808 ( .A0(n1268), .A1(n1211), .B0(n1932), .B1(n1112), .Y(n2914)
);
AOI21X2TS U1809 ( .A0(n1684), .A1(n1212), .B0(n2252), .Y(n1685) );
OAI22X2TS U1810 ( .A0(n1428), .A1(n1113), .B0(n1331), .B1(n2259), .Y(n2964)
);
NOR3X1TS U1811 ( .A(n1113), .B(n1039), .C(n1211), .Y(n2254) );
NOR2X8TS U1812 ( .A(n2253), .B(n2252), .Y(n2323) );
CLKMX2X2TS U1813 ( .A(DMP_SHT1_EWSW[14]), .B(n820), .S0(n2501), .Y(n758) );
NAND2X1TS U1814 ( .A(n2638), .B(n820), .Y(n1655) );
CLKMX2X2TS U1815 ( .A(DMP_SHT1_EWSW[15]), .B(n819), .S0(n2501), .Y(n755) );
NAND2X1TS U1816 ( .A(n2638), .B(n819), .Y(n1658) );
NAND2X4TS U1817 ( .A(n1368), .B(n1343), .Y(n1654) );
NAND2X2TS U1818 ( .A(n1367), .B(intDX_EWSW[24]), .Y(n2062) );
NOR2X8TS U1819 ( .A(n2602), .B(intDX_EWSW[13]), .Y(n1587) );
OAI2BB2X4TS U1820 ( .B0(n968), .B1(n2398), .A0N(n2389), .A1N(n2470), .Y(
n2390) );
OR2X8TS U1821 ( .A(n2333), .B(Raw_mant_NRM_SWR[6]), .Y(n1295) );
NAND2BX4TS U1822 ( .AN(n1299), .B(n2284), .Y(n1382) );
NAND4X6TS U1823 ( .A(n1435), .B(n1434), .C(n1433), .D(n1436), .Y(n1503) );
NOR2X8TS U1824 ( .A(n1274), .B(n1305), .Y(n1304) );
NAND3X2TS U1825 ( .A(n2061), .B(n2062), .C(n2060), .Y(n644) );
BUFX8TS U1826 ( .A(intDX_EWSW[13]), .Y(n1391) );
NOR2X4TS U1827 ( .A(n1402), .B(n1400), .Y(n2970) );
NOR2X4TS U1828 ( .A(n2844), .B(n2611), .Y(n1402) );
OAI21X4TS U1829 ( .A0(n2171), .A1(n2259), .B0(n1401), .Y(n1400) );
NAND2X4TS U1830 ( .A(n1109), .B(DmP_mant_SHT1_SW[20]), .Y(n1401) );
NAND3X6TS U1831 ( .A(n1767), .B(n1519), .C(n1765), .Y(n1518) );
NAND2X4TS U1832 ( .A(n1323), .B(n965), .Y(n1322) );
INVX8TS U1833 ( .A(n1425), .Y(n2253) );
AND2X4TS U1834 ( .A(n1838), .B(n1840), .Y(n1479) );
AND2X4TS U1835 ( .A(n1843), .B(n1844), .Y(n1478) );
AND2X4TS U1836 ( .A(n1831), .B(n1833), .Y(n1477) );
NOR2X4TS U1837 ( .A(n959), .B(n1238), .Y(n1686) );
NAND2X4TS U1838 ( .A(n1422), .B(n1282), .Y(n1421) );
NAND2X2TS U1839 ( .A(n2117), .B(n2847), .Y(n1409) );
XOR2X1TS U1840 ( .A(intDY_EWSW[27]), .B(n1258), .Y(n1485) );
NAND2X4TS U1841 ( .A(n2231), .B(DMP_SFG[6]), .Y(n2147) );
INVX12TS U1842 ( .A(n1884), .Y(n2124) );
INVX12TS U1843 ( .A(n1406), .Y(n1927) );
INVX12TS U1844 ( .A(n2859), .Y(n1273) );
NAND2X6TS U1845 ( .A(n1467), .B(n1850), .Y(n1991) );
NOR2X6TS U1846 ( .A(n2591), .B(n1344), .Y(n1616) );
NOR2X4TS U1847 ( .A(n2597), .B(intDX_EWSW[10]), .Y(n1576) );
AND3X6TS U1848 ( .A(n1835), .B(n1827), .C(n1829), .Y(n1480) );
NAND3X4TS U1849 ( .A(n2337), .B(n2333), .C(n2116), .Y(n1530) );
NAND2X4TS U1850 ( .A(n1484), .B(n1481), .Y(n1849) );
NOR2X4TS U1851 ( .A(n1486), .B(n1485), .Y(n1484) );
NOR2X1TS U1852 ( .A(n1240), .B(n1251), .Y(n2316) );
INVX2TS U1853 ( .A(n2615), .Y(n1447) );
AOI21X2TS U1854 ( .A0(n1711), .A1(n2180), .B0(n2179), .Y(n1713) );
NAND4X4TS U1855 ( .A(n2176), .B(n2175), .C(n2174), .D(n2173), .Y(n2238) );
NAND3X6TS U1856 ( .A(n1449), .B(n1448), .C(n2357), .Y(n2457) );
INVX2TS U1857 ( .A(n1318), .Y(n2099) );
NAND2X1TS U1858 ( .A(n2638), .B(n1218), .Y(n1661) );
NAND2X2TS U1859 ( .A(n1374), .B(n1238), .Y(n1970) );
NAND2X2TS U1860 ( .A(n2862), .B(n2463), .Y(n1456) );
INVX2TS U1861 ( .A(n1453), .Y(n1452) );
NAND2X2TS U1862 ( .A(n1374), .B(n1326), .Y(n1997) );
NAND2X1TS U1863 ( .A(n2450), .B(n1349), .Y(n2090) );
AOI21X2TS U1864 ( .A0(n2181), .A1(n2180), .B0(n2179), .Y(n2185) );
MXI2X2TS U1865 ( .A(n2169), .B(n1212), .S0(n1375), .Y(n579) );
NAND2X2TS U1866 ( .A(n2455), .B(n1427), .Y(n2956) );
AOI2BB2X2TS U1867 ( .B0(n2394), .B1(DmP_mant_SHT1_SW[19]), .A0N(n1288),
.A1N(n2620), .Y(n2902) );
NAND2X2TS U1868 ( .A(n2152), .B(n2180), .Y(n2153) );
NAND2X1TS U1869 ( .A(n2470), .B(n2468), .Y(n2976) );
NAND2X4TS U1870 ( .A(n2459), .B(n1427), .Y(n2940) );
AOI22X2TS U1871 ( .A0(n1545), .A1(n1501), .B0(n1502), .B1(
DmP_mant_SHT1_SW[19]), .Y(n2972) );
AOI21X2TS U1872 ( .A0(n2407), .A1(Raw_mant_NRM_SWR[6]), .B0(n2388), .Y(n2959) );
INVX2TS U1873 ( .A(n1412), .Y(n1415) );
INVX2TS U1874 ( .A(DmP_mant_SHT1_SW[3]), .Y(n2687) );
AOI22X2TS U1875 ( .A0(n1377), .A1(n857), .B0(n2200), .B1(n2187), .Y(n2047)
);
AOI22X2TS U1876 ( .A0(n2348), .A1(n864), .B0(n2236), .B1(n2399), .Y(n1889)
);
NAND2X4TS U1877 ( .A(n2457), .B(n1427), .Y(n2949) );
NAND2X1TS U1878 ( .A(n2470), .B(n2077), .Y(n1437) );
NAND2X2TS U1879 ( .A(n1109), .B(DmP_mant_SHT1_SW[7]), .Y(n1438) );
NAND2X4TS U1880 ( .A(n1932), .B(n1240), .Y(n1439) );
NAND2X4TS U1881 ( .A(n2460), .B(n1427), .Y(n2946) );
AOI2BB2X2TS U1882 ( .B0(n2394), .B1(DmP_mant_SHT1_SW[7]), .A0N(n2844), .A1N(
n2673), .Y(n2925) );
CLKBUFX3TS U1883 ( .A(n1381), .Y(n2869) );
BUFX3TS U1884 ( .A(n1381), .Y(n2896) );
NAND2X2TS U1885 ( .A(n2445), .B(DmP_EXP_EWSW[25]), .Y(n2065) );
NAND2X2TS U1886 ( .A(n2445), .B(DmP_EXP_EWSW[23]), .Y(n2063) );
NAND2X1TS U1887 ( .A(n2285), .B(DmP_EXP_EWSW[22]), .Y(n1652) );
NAND2X2TS U1888 ( .A(n2276), .B(n657), .Y(n1928) );
NAND2X1TS U1889 ( .A(n2295), .B(DmP_EXP_EWSW[0]), .Y(n2270) );
INVX2TS U1890 ( .A(rst), .Y(n3034) );
INVX3TS U1891 ( .A(n1353), .Y(n1359) );
INVX2TS U1892 ( .A(rst), .Y(n1363) );
MXI2X1TS U1893 ( .A(n1986), .B(SIGN_FLAG_EXP), .S0(n2638), .Y(n1852) );
NAND2X1TS U1894 ( .A(n2638), .B(n1119), .Y(n1914) );
NAND2X1TS U1895 ( .A(n2638), .B(DMP_EXP_EWSW[16]), .Y(n1913) );
AND2X2TS U1896 ( .A(n2445), .B(DMP_EXP_EWSW[11]), .Y(n1298) );
NAND2X2TS U1897 ( .A(n2285), .B(n832), .Y(n1747) );
CLKINVX3TS U1898 ( .A(n1353), .Y(n1366) );
AOI21X1TS U1899 ( .A0(n2325), .A1(n1039), .B0(n1533), .Y(n1532) );
NOR2X1TS U1900 ( .A(n2411), .B(n2586), .Y(n1533) );
INVX6TS U1901 ( .A(n1286), .Y(n2377) );
NAND2X6TS U1902 ( .A(n1286), .B(n2131), .Y(n1459) );
NAND3X2TS U1903 ( .A(n1164), .B(n1163), .C(n1162), .Y(n814) );
NAND3X2TS U1904 ( .A(n1158), .B(n1157), .C(n1156), .Y(n815) );
NAND2X4TS U1905 ( .A(n2440), .B(n1388), .Y(n1659) );
OR2X8TS U1906 ( .A(n2377), .B(n2860), .Y(n2366) );
OR2X8TS U1907 ( .A(n2377), .B(n1239), .Y(n2356) );
NAND2X4TS U1908 ( .A(n2444), .B(n1228), .Y(n1733) );
NAND2X6TS U1909 ( .A(n1451), .B(Raw_mant_NRM_SWR[0]), .Y(n1445) );
NAND3X4TS U1910 ( .A(n1731), .B(n1730), .C(n1729), .Y(n831) );
NAND2X8TS U1911 ( .A(n1458), .B(n1544), .Y(n1413) );
AOI22X1TS U1912 ( .A0(n1543), .A1(Raw_mant_NRM_SWR[2]), .B0(n1290), .B1(
DmP_mant_SHT1_SW[21]), .Y(n2903) );
NAND2X4TS U1913 ( .A(n1265), .B(intDX_EWSW[2]), .Y(n1562) );
NAND2X4TS U1914 ( .A(n1577), .B(n1583), .Y(n1505) );
NOR2X4TS U1915 ( .A(n1428), .B(n1252), .Y(n1302) );
NAND3X4TS U1916 ( .A(n2086), .B(n2085), .C(n2084), .Y(n810) );
NAND3X2TS U1917 ( .A(n1662), .B(n1663), .C(n1661), .Y(n817) );
NAND3X2TS U1918 ( .A(n1204), .B(n1203), .C(n1202), .Y(n819) );
AND2X8TS U1919 ( .A(intDY_EWSW[16]), .B(n1223), .Y(n1598) );
NAND2X6TS U1920 ( .A(n2597), .B(intDX_EWSW[10]), .Y(n1580) );
NAND2X6TS U1921 ( .A(n2607), .B(intDX_EWSW[16]), .Y(n1607) );
NOR2X6TS U1922 ( .A(n1505), .B(n1595), .Y(n1504) );
NOR2X6TS U1923 ( .A(n2603), .B(n1346), .Y(n1568) );
AOI2BB2X4TS U1924 ( .B0(n2407), .B1(Raw_mant_NRM_SWR[9]), .A0N(n2863), .A1N(
n1212), .Y(n2916) );
NOR2X4TS U1925 ( .A(n2863), .B(n1327), .Y(n2912) );
NOR2X4TS U1926 ( .A(n1524), .B(n2863), .Y(n2934) );
NAND2X6TS U1927 ( .A(n1511), .B(n1512), .Y(n1510) );
OR2X8TS U1928 ( .A(n1431), .B(n1430), .Y(n1227) );
INVX16TS U1929 ( .A(n1227), .Y(n1267) );
NAND3BX4TS U1930 ( .AN(n1232), .B(n2093), .C(n2092), .Y(n811) );
AND2X4TS U1931 ( .A(intDY_EWSW[23]), .B(n1429), .Y(n1232) );
NAND3BX4TS U1932 ( .AN(n1233), .B(n2066), .C(n2065), .Y(n643) );
AND2X4TS U1933 ( .A(n1254), .B(n1429), .Y(n1233) );
NAND3BX4TS U1934 ( .AN(n1234), .B(n2064), .C(n2063), .Y(n645) );
AND2X4TS U1935 ( .A(n1267), .B(n1328), .Y(n1234) );
BUFX20TS U1936 ( .A(n2113), .Y(n1237) );
INVX8TS U1937 ( .A(n1240), .Y(n1241) );
CLKINVX6TS U1938 ( .A(n2398), .Y(n1932) );
NOR2X4TS U1939 ( .A(n2863), .B(n1557), .Y(n1307) );
OR2X4TS U1940 ( .A(n2863), .B(n2595), .Y(n2977) );
AND2X8TS U1941 ( .A(intDY_EWSW[18]), .B(n1242), .Y(n1599) );
INVX16TS U1942 ( .A(n1497), .Y(n1450) );
NAND2X8TS U1943 ( .A(n1313), .B(n1447), .Y(n1446) );
OAI22X4TS U1944 ( .A0(n1578), .A1(n1403), .B0(n1247), .B1(intDY_EWSW[9]),
.Y(n1584) );
INVX12TS U1945 ( .A(n2120), .Y(n2133) );
NOR2X8TS U1946 ( .A(n1602), .B(n1618), .Y(n1250) );
NOR2X4TS U1947 ( .A(n1602), .B(n1618), .Y(n1621) );
INVX12TS U1948 ( .A(n1347), .Y(n1618) );
BUFX20TS U1949 ( .A(n1407), .Y(n1253) );
NOR2X6TS U1950 ( .A(n965), .B(n1540), .Y(n1539) );
NOR2X4TS U1951 ( .A(n1417), .B(n1416), .Y(n2922) );
OR2X8TS U1952 ( .A(intDY_EWSW[24]), .B(n1259), .Y(n1625) );
XOR2X4TS U1953 ( .A(n1810), .B(n1029), .Y(n2536) );
BUFX20TS U1954 ( .A(n1543), .Y(n1268) );
INVX8TS U1955 ( .A(n1489), .Y(n1436) );
BUFX6TS U1956 ( .A(n1286), .Y(n1313) );
OAI2BB1X1TS U1957 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n1275), .B0(n1495),
.Y(n593) );
AOI2BB1X2TS U1958 ( .A0N(n2844), .A1N(n2686), .B0(n1302), .Y(n2855) );
BUFX20TS U1959 ( .A(n1288), .Y(n2844) );
NOR2X4TS U1960 ( .A(n1560), .B(n1563), .Y(n1515) );
NAND2X4TS U1961 ( .A(n970), .B(n1313), .Y(n1449) );
NAND2X8TS U1962 ( .A(n2134), .B(n1451), .Y(n2375) );
BUFX20TS U1963 ( .A(n1338), .Y(n1451) );
NAND4X8TS U1964 ( .A(n1506), .B(n1504), .C(n1491), .D(n1111), .Y(n1435) );
CLKINVX12TS U1965 ( .A(n1284), .Y(n1424) );
INVX12TS U1966 ( .A(n1273), .Y(n1274) );
INVX8TS U1967 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1277) );
INVX12TS U1968 ( .A(n1277), .Y(n1280) );
INVX12TS U1969 ( .A(n1278), .Y(n1282) );
OR3X6TS U1970 ( .A(n1271), .B(n1326), .C(n971), .Y(n1675) );
NAND2X2TS U1971 ( .A(n2454), .B(n2131), .Y(n2962) );
NAND3X8TS U1972 ( .A(n1418), .B(n2317), .C(n1040), .Y(n1284) );
INVX8TS U1973 ( .A(n1500), .Y(n1352) );
NAND2X4TS U1974 ( .A(n1496), .B(n1251), .Y(n1498) );
BUFX20TS U1975 ( .A(n1543), .Y(n1545) );
NAND2X4TS U1976 ( .A(n1423), .B(n1252), .Y(n1422) );
AO21X4TS U1977 ( .A0(n1496), .A1(n1211), .B0(n1345), .Y(n1945) );
AOI21X2TS U1978 ( .A0(n961), .A1(DmP_mant_SHT1_SW[3]), .B0(n2146), .Y(n2947)
);
CLKBUFX2TS U1979 ( .A(n2869), .Y(n2872) );
AND2X2TS U1980 ( .A(n2409), .B(DmP_mant_SHT1_SW[22]), .Y(n1285) );
NOR2X8TS U1981 ( .A(n1694), .B(n1276), .Y(n1286) );
OR2X8TS U1982 ( .A(n2358), .B(n2899), .Y(n1287) );
BUFX3TS U1983 ( .A(n2897), .Y(n2871) );
INVX2TS U1984 ( .A(n2870), .Y(n1353) );
OR2X8TS U1985 ( .A(n1950), .B(DMP_SFG[17]), .Y(n1291) );
AND2X2TS U1986 ( .A(n1526), .B(n2115), .Y(n1292) );
BUFX4TS U1987 ( .A(n2414), .Y(n1500) );
AND2X2TS U1988 ( .A(n1954), .B(n1946), .Y(n1297) );
INVX2TS U1989 ( .A(n2847), .Y(n1501) );
INVX2TS U1990 ( .A(n1353), .Y(n1355) );
CLKBUFX2TS U1991 ( .A(n2865), .Y(n2867) );
INVX6TS U1992 ( .A(Raw_mant_NRM_SWR[4]), .Y(n1303) );
NAND2X8TS U1993 ( .A(n1303), .B(n1304), .Y(n2132) );
NOR2X8TS U1994 ( .A(n1316), .B(Raw_mant_NRM_SWR[2]), .Y(n1305) );
NOR2X4TS U1995 ( .A(n1307), .B(n1306), .Y(n2971) );
INVX16TS U1996 ( .A(n2004), .Y(n1308) );
NAND3X2TS U1997 ( .A(n1756), .B(n1757), .C(n1755), .Y(n683) );
XOR2X2TS U1998 ( .A(intDY_EWSW[25]), .B(n1254), .Y(n1482) );
NAND4X8TS U1999 ( .A(n1819), .B(n1818), .C(n1817), .D(n1816), .Y(n1311) );
NAND3X2TS U2000 ( .A(n1189), .B(n1188), .C(n1187), .Y(n813) );
NOR2X8TS U2001 ( .A(n2534), .B(n2536), .Y(n1818) );
BUFX20TS U2002 ( .A(n1321), .Y(n1337) );
MX2X1TS U2003 ( .A(Data_X[26]), .B(intDX_EWSW[26]), .S0(n2523), .Y(n917) );
NAND2X4TS U2004 ( .A(n1917), .B(n2520), .Y(n2269) );
BUFX12TS U2005 ( .A(n1927), .Y(n2440) );
NAND2X4TS U2006 ( .A(n1257), .B(n1389), .Y(n2288) );
NOR2X6TS U2007 ( .A(n1790), .B(n1792), .Y(n1795) );
XNOR2X2TS U2008 ( .A(n2851), .B(DMP_exp_NRM2_EW[0]), .Y(n2359) );
OAI21X1TS U2009 ( .A0(n2500), .A1(n1376), .B0(n1039), .Y(n910) );
OAI2BB1X2TS U2010 ( .A0N(n1327), .A1N(n1266), .B0(n1686), .Y(n1676) );
BUFX12TS U2011 ( .A(n1454), .Y(n1455) );
AOI22X4TS U2012 ( .A0(n1502), .A1(DmP_mant_SHT1_SW[7]), .B0(n1240), .B1(
n1545), .Y(n2951) );
NAND2X4TS U2013 ( .A(n1749), .B(n1747), .Y(n1384) );
NAND2X4TS U2014 ( .A(n2459), .B(n1351), .Y(n2955) );
NAND2X4TS U2015 ( .A(n2457), .B(n1351), .Y(n2932) );
NAND2X4TS U2016 ( .A(n2460), .B(n1351), .Y(n2975) );
AOI22X1TS U2017 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1543), .B0(n1290), .B1(
DmP_mant_SHT1_SW[15]), .Y(n2931) );
AOI22X2TS U2018 ( .A0(n1268), .A1(Raw_mant_NRM_SWR[7]), .B0(n1290), .B1(
DmP_mant_SHT1_SW[16]), .Y(n2960) );
NAND2X2TS U2019 ( .A(n1545), .B(n967), .Y(n2905) );
NAND2X2TS U2020 ( .A(n1526), .B(n964), .Y(n1536) );
AO22X2TS U2021 ( .A0(n1308), .A1(n1035), .B0(n2124), .B1(n2399), .Y(n1318)
);
NOR2X8TS U2022 ( .A(DMP_exp_NRM2_EW[2]), .B(n1776), .Y(n1790) );
CLKINVX6TS U2023 ( .A(n1333), .Y(n2086) );
MX2X1TS U2024 ( .A(Data_X[8]), .B(intDX_EWSW[8]), .S0(n2525), .Y(n935) );
NOR2X2TS U2025 ( .A(n1229), .B(intDX_EWSW[8]), .Y(n1575) );
OR2X8TS U2026 ( .A(n1499), .B(n1319), .Y(n2455) );
NAND2X4TS U2027 ( .A(n2456), .B(n1427), .Y(n2952) );
NAND2X4TS U2028 ( .A(n2456), .B(n1352), .Y(n2935) );
NOR2X4TS U2029 ( .A(n2253), .B(n1252), .Y(n1551) );
NAND3X6TS U2030 ( .A(n1460), .B(n1295), .C(n2338), .Y(n1463) );
NOR2X8TS U2031 ( .A(n1320), .B(n1675), .Y(n1441) );
AOI21X4TS U2032 ( .A0(n2407), .A1(Raw_mant_NRM_SWR[1]), .B0(n2406), .Y(n2901) );
NAND2X4TS U2033 ( .A(n2439), .B(n1282), .Y(n1534) );
OAI22X4TS U2034 ( .A0(n1315), .A1(n2844), .B0(n2863), .B1(n2846), .Y(n2968)
);
NOR2X6TS U2035 ( .A(n2598), .B(intDX_EWSW[6]), .Y(n1565) );
NAND2X4TS U2036 ( .A(n2598), .B(intDX_EWSW[6]), .Y(n1570) );
INVX2TS U2037 ( .A(n2408), .Y(n1331) );
CLKINVX12TS U2038 ( .A(n1406), .Y(n1321) );
NAND3X2TS U2039 ( .A(n1198), .B(n1197), .C(n1196), .Y(n820) );
OAI2BB2X2TS U2040 ( .B0(n2405), .B1(n2411), .A0N(n1420), .A1N(n1285), .Y(
n2406) );
NOR2X4TS U2041 ( .A(n1244), .B(n1348), .Y(n1559) );
AOI22X2TS U2042 ( .A0(n1545), .A1(Raw_mant_NRM_SWR[6]), .B0(n1502), .B1(
DmP_mant_SHT1_SW[17]), .Y(n2923) );
NOR2X4TS U2043 ( .A(n1771), .B(n1408), .Y(n1323) );
INVX12TS U2044 ( .A(n1326), .Y(n1327) );
NAND2X4TS U2045 ( .A(n2417), .B(n2340), .Y(n851) );
NAND2X4TS U2046 ( .A(n2449), .B(intDX_EWSW[31]), .Y(n1853) );
NOR3X4TS U2047 ( .A(n2133), .B(n1316), .C(n1529), .Y(n1528) );
NOR2X4TS U2048 ( .A(n2863), .B(n1553), .Y(n1417) );
AND3X8TS U2049 ( .A(n1440), .B(n1442), .C(n1443), .Y(n1330) );
OR2X8TS U2050 ( .A(n2377), .B(n1317), .Y(n2363) );
NAND2X4TS U2051 ( .A(n2461), .B(n1352), .Y(n2910) );
NAND2X4TS U2052 ( .A(n2461), .B(n1427), .Y(n2941) );
NAND2X4TS U2053 ( .A(n1451), .B(n1271), .Y(n1448) );
AND2X4TS U2054 ( .A(intDY_EWSW[24]), .B(n1429), .Y(n1333) );
NAND2X6TS U2055 ( .A(n1387), .B(n1386), .Y(n876) );
NAND2X2TS U2056 ( .A(n2458), .B(n1427), .Y(n2957) );
NOR2X8TS U2057 ( .A(n1601), .B(n1616), .Y(n1603) );
XNOR2X4TS U2058 ( .A(intDY_EWSW[20]), .B(n1045), .Y(n1830) );
NAND3X4TS U2059 ( .A(n1763), .B(n1762), .C(n1761), .Y(n825) );
OAI21X4TS U2060 ( .A0(n1985), .A1(n1374), .B0(n1984), .Y(n615) );
OA21X4TS U2061 ( .A0(n1782), .A1(n1248), .B0(n1784), .Y(n1342) );
AND3X6TS U2062 ( .A(n1808), .B(n1807), .C(n1806), .Y(n1819) );
NAND2X4TS U2063 ( .A(n1451), .B(n1238), .Y(n2372) );
NAND2X4TS U2064 ( .A(n1451), .B(Raw_mant_NRM_SWR[2]), .Y(n2362) );
CLKMX2X2TS U2065 ( .A(Data_X[21]), .B(n1344), .S0(n2524), .Y(n922) );
OAI22X4TS U2066 ( .A0(n2863), .A1(n1236), .B0(n1084), .B1(n972), .Y(n2936)
);
NAND3X4TS U2067 ( .A(n2860), .B(n1113), .C(Raw_mant_NRM_SWR[8]), .Y(n1684)
);
NOR2X4TS U2068 ( .A(n1237), .B(n964), .Y(n2115) );
NAND3X4TS U2069 ( .A(n2596), .B(n1212), .C(n1112), .Y(n1423) );
NAND2X8TS U2070 ( .A(intDY_EWSW[23]), .B(n1329), .Y(n1347) );
NAND2X4TS U2071 ( .A(n2172), .B(n1356), .Y(n2176) );
BUFX20TS U2072 ( .A(n1459), .Y(n1428) );
BUFX3TS U2073 ( .A(n988), .Y(n2873) );
CLKINVX3TS U2074 ( .A(rst), .Y(n1364) );
INVX8TS U2075 ( .A(n2507), .Y(n1357) );
BUFX20TS U2076 ( .A(n1267), .Y(n1368) );
INVX3TS U2077 ( .A(rst), .Y(n1371) );
MXI2X2TS U2078 ( .A(n2002), .B(n2847), .S0(n1374), .Y(n596) );
NAND2X2TS U2079 ( .A(n2426), .B(n1271), .Y(n1941) );
MXI2X2TS U2080 ( .A(n2186), .B(n965), .S0(n2507), .Y(n585) );
NOR2X8TS U2081 ( .A(n2095), .B(n2344), .Y(n1888) );
NAND2X2TS U2082 ( .A(n1399), .B(n2449), .Y(n1762) );
CLKBUFX3TS U2083 ( .A(n1365), .Y(n1381) );
NAND3X4TS U2084 ( .A(n2269), .B(n2268), .C(n2267), .Y(n655) );
NAND3X4TS U2085 ( .A(n2288), .B(n2287), .C(n2286), .Y(n671) );
NAND3X8TS U2086 ( .A(n1693), .B(n1330), .C(n1692), .Y(n1694) );
INVX4TS U2087 ( .A(n1428), .Y(n2416) );
NAND2X4TS U2088 ( .A(n2326), .B(n1541), .Y(n1540) );
NAND3X2TS U2089 ( .A(n1201), .B(n1200), .C(n1199), .Y(n827) );
NAND3X2TS U2090 ( .A(n1192), .B(n1191), .C(n1190), .Y(n673) );
NAND3X2TS U2091 ( .A(n1152), .B(n1151), .C(n1150), .Y(n679) );
NAND3X2TS U2092 ( .A(n1195), .B(n1194), .C(n1193), .Y(n677) );
NAND3X2TS U2093 ( .A(n1161), .B(n1160), .C(n1159), .Y(n649) );
NAND3X2TS U2094 ( .A(n1146), .B(n1145), .C(n1144), .Y(n675) );
NAND3X2TS U2095 ( .A(n1174), .B(n1173), .C(n1172), .Y(n665) );
BUFX20TS U2096 ( .A(n1321), .Y(n2444) );
NAND2X6TS U2097 ( .A(n1229), .B(intDX_EWSW[8]), .Y(n1403) );
BUFX6TS U2098 ( .A(intDX_EWSW[15]), .Y(n1388) );
BUFX6TS U2099 ( .A(intDX_EWSW[10]), .Y(n1389) );
NOR2X8TS U2100 ( .A(n1341), .B(DMP_exp_NRM2_EW[1]), .Y(n1782) );
NAND2X8TS U2101 ( .A(n1444), .B(n1445), .Y(n1466) );
BUFX6TS U2102 ( .A(intDX_EWSW[7]), .Y(n1392) );
BUFX6TS U2103 ( .A(intDX_EWSW[19]), .Y(n1393) );
NAND3X2TS U2104 ( .A(n1746), .B(n1745), .C(n1744), .Y(n833) );
BUFX6TS U2105 ( .A(intDX_EWSW[11]), .Y(n1394) );
AOI22X2TS U2106 ( .A0(n1268), .A1(n1266), .B0(DmP_mant_SHT1_SW[3]), .B1(
n1502), .Y(n2954) );
BUFX6TS U2107 ( .A(intDX_EWSW[9]), .Y(n1399) );
NOR2X8TS U2108 ( .A(n967), .B(n1271), .Y(n2317) );
NOR2X8TS U2109 ( .A(n1565), .B(n1571), .Y(n1511) );
NOR2X8TS U2110 ( .A(Raw_mant_NRM_SWR[7]), .B(Raw_mant_NRM_SWR[6]), .Y(n1771)
);
XOR2X4TS U2111 ( .A(n1294), .B(DmP_mant_SFG_SWR[21]), .Y(n1522) );
NOR2X8TS U2112 ( .A(n1599), .B(n1404), .Y(n1612) );
OAI21X4TS U2113 ( .A0(n1404), .A1(n1610), .B0(n1609), .Y(n1611) );
NOR2X8TS U2114 ( .A(n1256), .B(intDX_EWSW[19]), .Y(n1404) );
BUFX20TS U2115 ( .A(n1321), .Y(n1405) );
NAND2X8TS U2116 ( .A(n1503), .B(Shift_reg_FLAGS_7_6), .Y(n1406) );
XNOR2X4TS U2117 ( .A(n1709), .B(DmP_mant_SFG_SWR[8]), .Y(n2231) );
AOI2BB2X2TS U2118 ( .B0(n1455), .B1(DmP_mant_SHT1_SW[13]), .A0N(n1428),
.A1N(n965), .Y(n2930) );
AOI2BB2X4TS U2119 ( .B0(Shift_amount_SHT1_EWR[1]), .B1(n1275), .A0N(n1411),
.A1N(n1421), .Y(n1707) );
NOR2BX4TS U2120 ( .AN(n2131), .B(n2387), .Y(n1412) );
AND2X8TS U2121 ( .A(n1241), .B(n2580), .Y(n1418) );
AOI22X4TS U2122 ( .A0(n1502), .A1(DmP_mant_SHT1_SW[13]), .B0(n1268), .B1(
n964), .Y(n2919) );
NAND2X8TS U2123 ( .A(n1821), .B(n2411), .Y(n2414) );
BUFX20TS U2124 ( .A(n2443), .Y(n1429) );
NOR2X8TS U2125 ( .A(n1431), .B(n1430), .Y(n2443) );
NAND3X8TS U2126 ( .A(n1435), .B(n1433), .C(n1432), .Y(n1431) );
NAND3X8TS U2127 ( .A(n1597), .B(n1491), .C(n1492), .Y(n1434) );
NAND2X8TS U2128 ( .A(n1450), .B(n2251), .Y(n2398) );
AND3X8TS U2129 ( .A(n1439), .B(n1438), .C(n1437), .Y(n2942) );
NOR2X8TS U2130 ( .A(n1680), .B(n1681), .Y(n1700) );
NOR2BX4TS U2131 ( .AN(DmP_mant_SHT1_SW[6]), .B(n1868), .Y(n1453) );
NOR2X8TS U2132 ( .A(n1465), .B(n1868), .Y(n1454) );
INVX12TS U2133 ( .A(n1457), .Y(n1544) );
NAND2X8TS U2134 ( .A(n1708), .B(n1707), .Y(n1457) );
OAI22X4TS U2135 ( .A0(n2844), .A1(n2613), .B0(n1428), .B1(n1272), .Y(n2907)
);
NAND3BX4TS U2136 ( .AN(n1464), .B(n2331), .C(n2329), .Y(n1461) );
NAND2X8TS U2137 ( .A(n1463), .B(n1281), .Y(n2417) );
OAI2BB1X4TS U2138 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1276), .B0(n2417),
.Y(n607) );
XOR2X4TS U2139 ( .A(n1260), .B(n2522), .Y(n1486) );
NOR2BX4TS U2140 ( .AN(n2411), .B(n1868), .Y(n1487) );
OAI21X4TS U2141 ( .A0(n1494), .A1(n1623), .B0(n1493), .Y(n1488) );
NOR2X8TS U2142 ( .A(n1623), .B(n1633), .Y(n1491) );
AOI21X4TS U2143 ( .A0(n1621), .A1(n1622), .B0(n1620), .Y(n1493) );
AOI21X4TS U2144 ( .A0(n1613), .A1(n1612), .B0(n1611), .Y(n1494) );
AOI2BB2X4TS U2145 ( .B0(n1352), .B1(n2455), .A0N(n1084), .A1N(n1557), .Y(
n2966) );
NAND2X8TS U2146 ( .A(n1592), .B(n1574), .Y(n1595) );
OAI21X4TS U2147 ( .A0(n1513), .A1(n1510), .B0(n1507), .Y(n1506) );
AOI21X4TS U2148 ( .A0(n1509), .A1(n1511), .B0(n1508), .Y(n1507) );
OAI21X4TS U2149 ( .A0(n1571), .A1(n1570), .B0(n1569), .Y(n1508) );
OAI21X4TS U2150 ( .A0(n1568), .A1(n1567), .B0(n1566), .Y(n1509) );
NOR2X8TS U2151 ( .A(n1564), .B(n1568), .Y(n1512) );
AOI21X4TS U2152 ( .A0(n1516), .A1(n1515), .B0(n1514), .Y(n1513) );
OAI21X4TS U2153 ( .A0(n1563), .A1(n1562), .B0(n1561), .Y(n1514) );
OAI2BB1X4TS U2154 ( .A0N(n1527), .A1N(n2121), .B0(n1280), .Y(n2264) );
NAND2BX4TS U2155 ( .AN(n1531), .B(n2114), .Y(n2333) );
AND2X8TS U2156 ( .A(n1236), .B(n1327), .Y(n1542) );
AOI21X4TS U2157 ( .A0(n1425), .A1(n1685), .B0(n1538), .Y(n1693) );
NOR2X8TS U2158 ( .A(n1293), .B(n1547), .Y(n1702) );
NAND2X8TS U2159 ( .A(n1679), .B(n1542), .Y(n1683) );
NAND2X8TS U2160 ( .A(n1544), .B(n1820), .Y(n1821) );
NOR2X8TS U2161 ( .A(n1551), .B(n1550), .Y(n1774) );
BUFX20TS U2162 ( .A(n1875), .Y(n2236) );
BUFX20TS U2163 ( .A(n1875), .Y(n2347) );
NOR2X8TS U2164 ( .A(n1972), .B(n1962), .Y(n2038) );
NOR2X8TS U2165 ( .A(n2108), .B(n2544), .Y(n2419) );
NAND3X4TS U2166 ( .A(n1910), .B(n1909), .C(n1908), .Y(n2156) );
NOR2X4TS U2167 ( .A(n1714), .B(DMP_SFG[9]), .Y(n2162) );
XOR2X4TS U2168 ( .A(n2055), .B(n2054), .Y(n2056) );
AOI21X2TS U2169 ( .A0(n2052), .A1(n2051), .B0(n2050), .Y(n2055) );
MXI2X4TS U2170 ( .A(n2985), .B(n2664), .S0(n2499), .Y(n597) );
NAND4X4TS U2171 ( .A(n2080), .B(n2081), .C(n2079), .D(n2078), .Y(n2136) );
NAND3X6TS U2172 ( .A(n1883), .B(n1882), .C(n1881), .Y(n2345) );
AND2X8TS U2173 ( .A(n1890), .B(n1889), .Y(n3003) );
NAND2X4TS U2174 ( .A(n2029), .B(n2469), .Y(n2032) );
NAND4X6TS U2175 ( .A(n2835), .B(n2834), .C(n2833), .D(n2832), .Y(n2469) );
NAND2X8TS U2176 ( .A(n1895), .B(n1231), .Y(n2004) );
OAI2BB1X4TS U2177 ( .A0N(n2435), .A1N(n1095), .B0(n2434), .Y(n1996) );
NAND2X2TS U2178 ( .A(n2096), .B(n862), .Y(n2011) );
NAND3X6TS U2179 ( .A(n2779), .B(n1906), .C(n2778), .Y(n862) );
AOI22X2TS U2180 ( .A0(n2236), .A1(n857), .B0(n2195), .B1(n2187), .Y(n1866)
);
AOI21X4TS U2181 ( .A0(n2428), .A1(n2431), .B0(n2243), .Y(n2244) );
NAND4BX4TS U2182 ( .AN(n2730), .B(n2729), .C(n1855), .D(n2728), .Y(n857) );
AOI22X2TS U2183 ( .A0(n2235), .A1(n1376), .B0(n1335), .B1(n2347), .Y(n2101)
);
AOI22X2TS U2184 ( .A0(n2347), .A1(n2463), .B0(n2195), .B1(n2097), .Y(n1879)
);
NAND2X4TS U2185 ( .A(n1950), .B(DMP_SFG[17]), .Y(n2247) );
BUFX16TS U2186 ( .A(n1797), .Y(n1814) );
NAND4BX4TS U2187 ( .AN(n2818), .B(n2817), .C(n2816), .D(n2815), .Y(n2404) );
NAND2X2TS U2188 ( .A(n2341), .B(DMP_SFG[1]), .Y(n2105) );
CLKINVX12TS U2189 ( .A(n2418), .Y(n1816) );
XOR2X4TS U2190 ( .A(n1143), .B(DmP_mant_SFG_SWR[2]), .Y(n2506) );
NOR2X8TS U2191 ( .A(shift_value_SHT2_EWR[2]), .B(n2586), .Y(n1895) );
AOI22X1TS U2192 ( .A0(n2323), .A1(n2254), .B0(n1340), .B1(n1274), .Y(n2257)
);
OAI21X2TS U2193 ( .A0(n1713), .A1(n2182), .B0(n1922), .Y(n1717) );
NAND3X2TS U2194 ( .A(n1179), .B(n1178), .C(n1177), .Y(n822) );
NAND2X8TS U2195 ( .A(n1776), .B(DMP_exp_NRM2_EW[2]), .Y(n1793) );
CLKINVX12TS U2196 ( .A(LZD_output_NRM2_EW[2]), .Y(n1776) );
NAND2X4TS U2197 ( .A(n1783), .B(n1784), .Y(n1785) );
NAND4BX4TS U2198 ( .AN(n2814), .B(n2813), .C(n2812), .D(n2811), .Y(n2353) );
XOR2X4TS U2199 ( .A(n1785), .B(n1248), .Y(n2487) );
OA22X4TS U2200 ( .A0(n1428), .A1(n2845), .B0(n2403), .B1(n2259), .Y(n2852)
);
INVX16TS U2201 ( .A(n1870), .Y(n2096) );
OR2X8TS U2202 ( .A(n1859), .B(n2262), .Y(n1870) );
OAI21X2TS U2203 ( .A0(n2230), .A1(n2229), .B0(n2422), .Y(n2233) );
AOI21X2TS U2204 ( .A0(n2228), .A1(n2420), .B0(n2419), .Y(n2230) );
OAI21X4TS U2205 ( .A0(n2148), .A1(n2422), .B0(n2147), .Y(n2181) );
NOR2X4TS U2206 ( .A(n2231), .B(DMP_SFG[6]), .Y(n2148) );
AND2X8TS U2207 ( .A(n2350), .B(n2349), .Y(n3005) );
NAND4BX4TS U2208 ( .AN(n2727), .B(n2726), .C(n2122), .D(n2725), .Y(n856) );
NAND3X6TS U2209 ( .A(n2366), .B(n2365), .C(n2364), .Y(n2458) );
OAI22X2TS U2210 ( .A0(n1991), .A1(n2226), .B0(Shift_reg_FLAGS_7_6), .B1(
n2550), .Y(n802) );
NAND3X2TS U2211 ( .A(n1182), .B(n1181), .C(n1180), .Y(n834) );
NAND3X2TS U2212 ( .A(n1168), .B(n1167), .C(n1166), .Y(n651) );
OAI22X2TS U2213 ( .A0(n1288), .A1(n2610), .B0(n2396), .B1(n2411), .Y(n2397)
);
OAI22X2TS U2214 ( .A0(n1288), .A1(n2612), .B0(n2400), .B1(n2411), .Y(n2401)
);
XOR2X4TS U2215 ( .A(n1398), .B(DmP_mant_SFG_SWR[7]), .Y(n2149) );
OAI21X4TS U2216 ( .A0(n1495), .A1(n965), .B0(n1943), .Y(n2454) );
AOI22X2TS U2217 ( .A0(n1268), .A1(n1326), .B0(n1502), .B1(
DmP_mant_SHT1_SW[2]), .Y(n2948) );
NAND2X4TS U2218 ( .A(n1451), .B(Raw_mant_NRM_SWR[8]), .Y(n2365) );
NAND3X6TS U2219 ( .A(n2356), .B(n2355), .C(n2354), .Y(n2456) );
OR2X8TS U2220 ( .A(n1939), .B(DMP_SFG[15]), .Y(n1954) );
NOR2X8TS U2221 ( .A(DmP_mant_SFG_SWR_signed[13]), .B(DMP_SFG[11]), .Y(n2049)
);
NAND3X2TS U2222 ( .A(n2150), .B(n2423), .C(n2419), .Y(n2151) );
NAND2X1TS U2223 ( .A(n2109), .B(n2420), .Y(n2110) );
MXI2X1TS U2224 ( .A(n2359), .B(final_result_ieee[23]), .S0(n2644), .Y(n2360)
);
MXI2X4TS U2225 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2466), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2490) );
NAND2X8TS U2226 ( .A(n2490), .B(beg_OP), .Y(n2519) );
NAND2X8TS U2227 ( .A(n2644), .B(Shift_reg_FLAGS_7[3]), .Y(n2498) );
BUFX12TS U2228 ( .A(n2498), .Y(n2499) );
NAND2X4TS U2234 ( .A(n1263), .B(intDX_EWSW[3]), .Y(n1561) );
NOR2X4TS U2235 ( .A(n2594), .B(n1339), .Y(n1564) );
NOR2X8TS U2236 ( .A(n1226), .B(intDX_EWSW[7]), .Y(n1571) );
NAND2X2TS U2237 ( .A(n1226), .B(intDX_EWSW[7]), .Y(n1569) );
NOR2X4TS U2238 ( .A(n2593), .B(intDX_EWSW[12]), .Y(n1572) );
NOR2X6TS U2239 ( .A(n1572), .B(n1587), .Y(n1574) );
NOR2X8TS U2240 ( .A(n2584), .B(intDX_EWSW[14]), .Y(n1573) );
NOR2X8TS U2241 ( .A(n1573), .B(n1590), .Y(n1592) );
NOR2X4TS U2242 ( .A(n1575), .B(n1578), .Y(n1577) );
NOR2X8TS U2243 ( .A(n2592), .B(intDX_EWSW[11]), .Y(n1581) );
NOR2X8TS U2244 ( .A(n1576), .B(n1581), .Y(n1583) );
OAI21X4TS U2245 ( .A0(n1581), .A1(n1580), .B0(n1579), .Y(n1582) );
AOI21X4TS U2246 ( .A0(n1583), .A1(n1584), .B0(n1582), .Y(n1596) );
NAND2X4TS U2247 ( .A(n2593), .B(intDX_EWSW[12]), .Y(n1586) );
NAND2X2TS U2248 ( .A(n2602), .B(intDX_EWSW[13]), .Y(n1585) );
OAI21X4TS U2249 ( .A0(n1587), .A1(n1586), .B0(n1585), .Y(n1593) );
NAND2X4TS U2250 ( .A(n2584), .B(intDX_EWSW[14]), .Y(n1589) );
NAND2X2TS U2251 ( .A(n1221), .B(intDX_EWSW[15]), .Y(n1588) );
OAI21X4TS U2252 ( .A0(n1590), .A1(n1589), .B0(n1588), .Y(n1591) );
AOI21X4TS U2253 ( .A0(n1592), .A1(n1593), .B0(n1591), .Y(n1594) );
OAI21X4TS U2254 ( .A0(n1596), .A1(n1595), .B0(n1594), .Y(n1597) );
NOR2X8TS U2255 ( .A(n1261), .B(intDX_EWSW[17]), .Y(n1608) );
NOR2X4TS U2256 ( .A(n1598), .B(n1608), .Y(n1600) );
NOR2X4TS U2257 ( .A(n2605), .B(n1390), .Y(n1601) );
NAND2X8TS U2258 ( .A(n1603), .B(n1250), .Y(n1623) );
OAI21X4TS U2259 ( .A0(n1608), .A1(n1607), .B0(n1606), .Y(n1613) );
NAND2X2TS U2260 ( .A(n1256), .B(intDX_EWSW[19]), .Y(n1609) );
NAND2X2TS U2261 ( .A(n2591), .B(n1344), .Y(n1614) );
OAI21X4TS U2262 ( .A0(n1616), .A1(n1615), .B0(n1614), .Y(n1622) );
NAND2X2TS U2263 ( .A(n2583), .B(n1343), .Y(n1619) );
NAND2X2TS U2264 ( .A(n2590), .B(n1328), .Y(n1617) );
OAI21X4TS U2265 ( .A0(n1619), .A1(n1618), .B0(n1617), .Y(n1620) );
NAND2X2TS U2266 ( .A(n2604), .B(n1254), .Y(n1624) );
NAND2X2TS U2267 ( .A(n2589), .B(n1258), .Y(n1627) );
NAND2X2TS U2268 ( .A(n2585), .B(intDX_EWSW[28]), .Y(n1631) );
NAND2X2TS U2269 ( .A(n2601), .B(intDX_EWSW[29]), .Y(n1630) );
NAND2X2TS U2270 ( .A(n1059), .B(intDY_EWSW[21]), .Y(n1635) );
NAND2X2TS U2271 ( .A(n1405), .B(intDY_EWSW[13]), .Y(n1644) );
NAND2X2TS U2272 ( .A(n1314), .B(n1392), .Y(n1648) );
NAND2X2TS U2273 ( .A(n1361), .B(n1225), .Y(n1647) );
NAND2X2TS U2274 ( .A(n1257), .B(n1399), .Y(n1651) );
NAND2X2TS U2275 ( .A(n1047), .B(intDY_EWSW[9]), .Y(n1650) );
NAND2X2TS U2276 ( .A(n2285), .B(n673), .Y(n1649) );
NAND2X2TS U2277 ( .A(n1314), .B(intDY_EWSW[14]), .Y(n1657) );
NAND2X2TS U2278 ( .A(n1059), .B(intDX_EWSW[14]), .Y(n1656) );
NAND2X2TS U2279 ( .A(n1257), .B(n1220), .Y(n1660) );
NAND2X2TS U2280 ( .A(n1368), .B(n1260), .Y(n1663) );
BUFX4TS U2281 ( .A(intDX_EWSW[17]), .Y(n2522) );
NAND2X2TS U2282 ( .A(n2449), .B(n2522), .Y(n1662) );
NAND2X2TS U2283 ( .A(n1058), .B(n1255), .Y(n1666) );
NAND2X2TS U2284 ( .A(n1059), .B(n1393), .Y(n1665) );
NAND2X2TS U2285 ( .A(n1361), .B(n1343), .Y(n1668) );
NAND2X2TS U2286 ( .A(n1314), .B(intDY_EWSW[21]), .Y(n1672) );
NAND2X2TS U2287 ( .A(n1059), .B(n1344), .Y(n1671) );
INVX12TS U2288 ( .A(n3035), .Y(n2471) );
NOR2X8TS U2289 ( .A(n1279), .B(n2500), .Y(n1673) );
NOR2X2TS U2290 ( .A(n1674), .B(n2476), .Y(n1677) );
NOR2X8TS U2291 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .Y(n2113)
);
AND2X4TS U2292 ( .A(n1237), .B(n2846), .Y(n1691) );
OR2X2TS U2293 ( .A(Raw_mant_NRM_SWR[5]), .B(n1316), .Y(n1689) );
OAI21X4TS U2294 ( .A0(n2335), .A1(n1689), .B0(n1688), .Y(n1690) );
NAND4X4TS U2295 ( .A(n1702), .B(n1690), .C(n1691), .D(n1703), .Y(n1692) );
OR2X8TS U2296 ( .A(n2579), .B(n1280), .Y(n1931) );
AOI21X1TS U2297 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n1039), .B0(n2383), .Y(
n1695) );
NOR2X4TS U2298 ( .A(n2476), .B(n959), .Y(n1764) );
NOR2X4TS U2299 ( .A(Raw_mant_NRM_SWR[5]), .B(n964), .Y(n1770) );
XNOR2X4TS U2300 ( .A(n1143), .B(DmP_mant_SFG_SWR[9]), .Y(n1710) );
NAND2X2TS U2301 ( .A(n1710), .B(n2547), .Y(n2180) );
NOR2X4TS U2302 ( .A(n1710), .B(n2547), .Y(n2179) );
NOR2X4TS U2303 ( .A(n1142), .B(n2546), .Y(n2183) );
INVX6TS U2304 ( .A(n2183), .Y(n1922) );
XOR2X4TS U2305 ( .A(n1398), .B(DmP_mant_SFG_SWR[11]), .Y(n1714) );
INVX2TS U2306 ( .A(n2161), .Y(n1715) );
NAND2X2TS U2307 ( .A(n1058), .B(n1045), .Y(n1725) );
NAND2X2TS U2308 ( .A(n1361), .B(intDY_EWSW[20]), .Y(n1724) );
NAND2X2TS U2309 ( .A(n1917), .B(intDY_EWSW[0]), .Y(n1728) );
NAND2X2TS U2310 ( .A(n1361), .B(intDX_EWSW[0]), .Y(n1727) );
NAND2X2TS U2311 ( .A(n2276), .B(n834), .Y(n1726) );
NAND2X2TS U2312 ( .A(n1314), .B(n1262), .Y(n1731) );
NAND2X2TS U2313 ( .A(n1058), .B(intDX_EWSW[8]), .Y(n1734) );
NAND2X2TS U2314 ( .A(n1917), .B(intDX_EWSW[12]), .Y(n1737) );
NAND2X2TS U2315 ( .A(n1058), .B(n2521), .Y(n1740) );
NAND2X2TS U2316 ( .A(n1405), .B(intDY_EWSW[6]), .Y(n1739) );
NAND2X2TS U2317 ( .A(n2285), .B(n679), .Y(n1738) );
NAND2X2TS U2318 ( .A(n1257), .B(n1225), .Y(n1743) );
NAND2X2TS U2319 ( .A(n1405), .B(n1392), .Y(n1742) );
NAND2X2TS U2320 ( .A(n1368), .B(n1243), .Y(n1746) );
NAND2X2TS U2321 ( .A(n1059), .B(intDX_EWSW[2]), .Y(n1748) );
NAND2X2TS U2322 ( .A(n1047), .B(intDY_EWSW[11]), .Y(n1751) );
NAND2X1TS U2323 ( .A(n2305), .B(n669), .Y(n1750) );
NAND2X1TS U2324 ( .A(n2305), .B(n1309), .Y(n1753) );
NAND2X2TS U2325 ( .A(n1367), .B(n1339), .Y(n1757) );
NAND2X2TS U2326 ( .A(n1361), .B(intDY_EWSW[4]), .Y(n1756) );
NAND2X2TS U2327 ( .A(n1367), .B(n1228), .Y(n1760) );
NAND2X2TS U2328 ( .A(n1405), .B(intDX_EWSW[8]), .Y(n1759) );
NAND2X2TS U2329 ( .A(n1314), .B(intDY_EWSW[9]), .Y(n1763) );
AND2X4TS U2330 ( .A(n1765), .B(n1764), .Y(n1766) );
AND2X4TS U2331 ( .A(n1769), .B(n1768), .Y(n2331) );
AND3X4TS U2332 ( .A(n1237), .B(n1771), .C(n1770), .Y(n2117) );
NAND2X4TS U2333 ( .A(n1341), .B(DMP_exp_NRM2_EW[1]), .Y(n1784) );
OAI21X4TS U2334 ( .A0(n1342), .A1(n1790), .B0(n1793), .Y(n1779) );
INVX2TS U2335 ( .A(n1792), .Y(n1777) );
OR2X6TS U2336 ( .A(LZD_output_NRM2_EW[3]), .B(n2850), .Y(n1791) );
NAND2X2TS U2337 ( .A(n1777), .B(n1791), .Y(n1778) );
XNOR2X4TS U2338 ( .A(n1779), .B(n1778), .Y(n2532) );
NAND2X2TS U2339 ( .A(n1793), .B(n1780), .Y(n1781) );
XOR2X4TS U2340 ( .A(n1342), .B(n1781), .Y(n2504) );
INVX2TS U2341 ( .A(n2359), .Y(n1786) );
NOR2BX4TS U2342 ( .AN(n2487), .B(n1786), .Y(n1789) );
NOR2X2TS U2343 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM2_EW[5]), .Y(n1787)
);
NAND2X6TS U2344 ( .A(n1246), .B(DMP_exp_NRM2_EW[4]), .Y(n1809) );
NAND2X2TS U2345 ( .A(n1787), .B(n1809), .Y(n1811) );
AND4X6TS U2346 ( .A(n2532), .B(n2504), .C(n1789), .D(n1788), .Y(n1804) );
AOI21X4TS U2347 ( .A0(n1796), .A1(n1795), .B0(n1794), .Y(n1797) );
NOR2X8TS U2348 ( .A(n1246), .B(DMP_exp_NRM2_EW[4]), .Y(n1813) );
OAI21X4TS U2349 ( .A0(n1814), .A1(n1813), .B0(n1799), .Y(n1800) );
XNOR2X4TS U2350 ( .A(n1800), .B(n2861), .Y(n1801) );
INVX8TS U2351 ( .A(n1801), .Y(n2418) );
INVX2TS U2352 ( .A(n1813), .Y(n1802) );
NAND2X2TS U2353 ( .A(n1802), .B(n1809), .Y(n1803) );
XOR2X4TS U2354 ( .A(n1814), .B(n1803), .Y(n2534) );
AND2X8TS U2355 ( .A(n1805), .B(n1036), .Y(n2352) );
NOR2X1TS U2356 ( .A(n2487), .B(n2359), .Y(n1808) );
INVX2TS U2357 ( .A(n2504), .Y(n1807) );
OAI21X4TS U2358 ( .A0(n1814), .A1(n1813), .B0(n1809), .Y(n1810) );
INVX2TS U2359 ( .A(n1811), .Y(n1812) );
OAI21X4TS U2360 ( .A0(n1813), .A1(n1814), .B0(n1812), .Y(n1815) );
XNOR2X4TS U2361 ( .A(n1815), .B(DMP_exp_NRM2_EW[7]), .Y(n2139) );
NOR2X8TS U2362 ( .A(Shift_amount_SHT1_EWR[0]), .B(n1281), .Y(n2384) );
XOR2X4TS U2363 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1987) );
XNOR2X1TS U2364 ( .A(n1262), .B(intDX_EWSW[3]), .Y(n1825) );
XNOR2X1TS U2365 ( .A(intDY_EWSW[6]), .B(intDX_EWSW[6]), .Y(n1824) );
XNOR2X1TS U2366 ( .A(intDY_EWSW[5]), .B(n1346), .Y(n1823) );
XNOR2X1TS U2367 ( .A(intDY_EWSW[16]), .B(intDX_EWSW[16]), .Y(n1822) );
XNOR2X1TS U2368 ( .A(intDX_EWSW[0]), .B(intDY_EWSW[0]), .Y(n1829) );
XNOR2X1TS U2369 ( .A(intDY_EWSW[28]), .B(intDX_EWSW[28]), .Y(n1828) );
XNOR2X1TS U2370 ( .A(intDY_EWSW[30]), .B(intDX_EWSW[30]), .Y(n1827) );
XNOR2X2TS U2371 ( .A(n1228), .B(intDX_EWSW[8]), .Y(n1826) );
XNOR2X1TS U2372 ( .A(n1255), .B(n1393), .Y(n1833) );
XNOR2X1TS U2373 ( .A(intDY_EWSW[18]), .B(intDX_EWSW[18]), .Y(n1832) );
XNOR2X1TS U2374 ( .A(intDY_EWSW[21]), .B(n1344), .Y(n1831) );
XNOR2X1TS U2375 ( .A(intDY_EWSW[23]), .B(n1328), .Y(n1837) );
XNOR2X1TS U2376 ( .A(intDY_EWSW[22]), .B(n1343), .Y(n1836) );
XNOR2X1TS U2377 ( .A(intDY_EWSW[10]), .B(n1389), .Y(n1835) );
XNOR2X1TS U2378 ( .A(intDY_EWSW[9]), .B(n1399), .Y(n1834) );
XNOR2X1TS U2379 ( .A(intDY_EWSW[12]), .B(intDX_EWSW[12]), .Y(n1841) );
XNOR2X1TS U2380 ( .A(intDY_EWSW[11]), .B(n1394), .Y(n1840) );
XNOR2X1TS U2381 ( .A(intDY_EWSW[14]), .B(intDX_EWSW[14]), .Y(n1839) );
XNOR2X1TS U2382 ( .A(intDY_EWSW[13]), .B(n1391), .Y(n1838) );
XNOR2X1TS U2383 ( .A(intDY_EWSW[24]), .B(intDX_EWSW[24]), .Y(n1845) );
XNOR2X1TS U2384 ( .A(n1220), .B(n1388), .Y(n1844) );
XNOR2X1TS U2385 ( .A(n1264), .B(intDX_EWSW[2]), .Y(n1843) );
XNOR2X1TS U2386 ( .A(intDY_EWSW[4]), .B(n1339), .Y(n1842) );
XOR2X1TS U2387 ( .A(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n1848) );
XOR2X1TS U2388 ( .A(n1225), .B(n1392), .Y(n1847) );
XOR2X1TS U2389 ( .A(intDY_EWSW[26]), .B(intDX_EWSW[26]), .Y(n1846) );
NOR4X2TS U2390 ( .A(n1849), .B(n1848), .C(n1847), .D(n1846), .Y(n1850) );
INVX2TS U2391 ( .A(n1987), .Y(n1851) );
NOR2X4TS U2392 ( .A(n1851), .B(n2619), .Y(n1986) );
NOR2X8TS U2393 ( .A(n2913), .B(shift_value_SHT2_EWR[3]), .Y(n1858) );
NOR2X8TS U2394 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2015) );
NAND2X2TS U2395 ( .A(n2030), .B(n2404), .Y(n1856) );
NAND2X4TS U2396 ( .A(n1857), .B(n1856), .Y(n2199) );
NAND4X4TS U2397 ( .A(n2831), .B(n2830), .C(n2829), .D(n2828), .Y(n2399) );
NAND2X1TS U2398 ( .A(n1308), .B(n2399), .Y(n1862) );
NAND2X1TS U2399 ( .A(n2124), .B(n2141), .Y(n1861) );
NAND4BX4TS U2400 ( .AN(n2927), .B(n2841), .C(n2840), .D(n2926), .Y(n2410) );
NAND4X4TS U2401 ( .A(n1863), .B(n1862), .C(n1861), .D(n1860), .Y(n2046) );
BUFX20TS U2402 ( .A(left_right_SHT2), .Y(n2344) );
NAND2X2TS U2403 ( .A(n2046), .B(n1370), .Y(n1867) );
NAND2X6TS U2404 ( .A(n2015), .B(n1231), .Y(n2095) );
NOR2X8TS U2405 ( .A(n2095), .B(n2237), .Y(n1875) );
AND2X8TS U2406 ( .A(n1867), .B(n1866), .Y(n3019) );
AOI2BB2X4TS U2407 ( .B0(n2705), .B1(n1135), .A0N(n1129), .A1N(n1132), .Y(
n1869) );
NAND2X1TS U2408 ( .A(n1308), .B(n2385), .Y(n1873) );
NAND2X1TS U2409 ( .A(n2124), .B(n2402), .Y(n1872) );
CLKINVX12TS U2410 ( .A(n1870), .Y(n2190) );
NAND4X4TS U2411 ( .A(n1873), .B(n1874), .C(n1872), .D(n1871), .Y(n2023) );
NAND4BBX4TS U2412 ( .AN(n2839), .BN(n2838), .C(n2837), .D(n2836), .Y(n2463)
);
NAND2X2TS U2413 ( .A(n2030), .B(n2141), .Y(n1877) );
NAND3X4TS U2414 ( .A(n1878), .B(n1877), .C(n1876), .Y(n2097) );
NAND2X2TS U2415 ( .A(n1308), .B(n2402), .Y(n1883) );
NAND2X2TS U2416 ( .A(n1308), .B(n2404), .Y(n1887) );
NAND2X2TS U2417 ( .A(n2189), .B(n2468), .Y(n1885) );
NAND3X6TS U2418 ( .A(n1887), .B(n1886), .C(n1885), .Y(n2346) );
MXI2X4TS U2419 ( .A(n2345), .B(n2346), .S0(n2344), .Y(n1890) );
BUFX12TS U2420 ( .A(n2498), .Y(n2492) );
BUFX12TS U2421 ( .A(n2498), .Y(n2493) );
MXI2X4TS U2422 ( .A(n2551), .B(n1709), .S0(n2493), .Y(n630) );
XOR2X4TS U2423 ( .A(n584), .B(n630), .Y(n2810) );
NAND2X2TS U2424 ( .A(n1902), .B(n2237), .Y(n1901) );
OAI2BB1X4TS U2425 ( .A0N(n2200), .A1N(n2123), .B0(n1899), .Y(n1900) );
MXI2X4TS U2426 ( .A(n2997), .B(n2662), .S0(n2499), .Y(n586) );
NAND2X2TS U2427 ( .A(n1902), .B(n2344), .Y(n1905) );
OAI2BB1X4TS U2428 ( .A0N(n2195), .A1N(n2123), .B0(n1903), .Y(n1904) );
MXI2X4TS U2429 ( .A(n3011), .B(n2670), .S0(n979), .Y(n553) );
NAND4BX4TS U2430 ( .AN(n2981), .B(n2821), .C(n2820), .D(n2819), .Y(n2135) );
NAND4X6TS U2431 ( .A(n2740), .B(n2739), .C(n2738), .D(n2737), .Y(n2170) );
NAND2X1TS U2432 ( .A(n2096), .B(n2170), .Y(n1907) );
OAI21X4TS U2433 ( .A0(n2381), .A1(n2004), .B0(n1907), .Y(n2157) );
NAND4BX4TS U2434 ( .AN(n2771), .B(n2770), .C(n2769), .D(n2768), .Y(n2408) );
NAND2X1TS U2435 ( .A(n2096), .B(n2408), .Y(n1909) );
NAND2X1TS U2436 ( .A(n2124), .B(n2469), .Y(n1908) );
MXI2X4TS U2437 ( .A(n2157), .B(n2156), .S0(n1376), .Y(n1912) );
NAND4X4TS U2438 ( .A(n2809), .B(n2808), .C(n2807), .D(n2806), .Y(n2395) );
AOI22X1TS U2439 ( .A0(n862), .A1(n2348), .B0(n2236), .B1(n2395), .Y(n1911)
);
AND2X8TS U2440 ( .A(n1912), .B(n1911), .Y(n2999) );
NAND2X2TS U2441 ( .A(n1314), .B(intDY_EWSW[18]), .Y(n1916) );
NAND2X2TS U2442 ( .A(n1405), .B(n2520), .Y(n1915) );
NAND2X2TS U2443 ( .A(n1058), .B(intDY_EWSW[20]), .Y(n1921) );
NAND2X2TS U2444 ( .A(n1059), .B(n1045), .Y(n1920) );
NOR3X4TS U2445 ( .A(n1922), .B(n2164), .C(n2162), .Y(n1923) );
OAI21X4TS U2446 ( .A0(n2164), .A1(n2161), .B0(n2165), .Y(n2052) );
NOR2X2TS U2447 ( .A(n1923), .B(n2052), .Y(n1925) );
NOR2X2TS U2448 ( .A(n2641), .B(n2576), .Y(n2050) );
NOR2X1TS U2449 ( .A(n2050), .B(n2049), .Y(n1924) );
XOR2X4TS U2450 ( .A(n1925), .B(n1924), .Y(n1926) );
NAND2X2TS U2451 ( .A(n1361), .B(n1260), .Y(n1930) );
XOR2X4TS U2452 ( .A(n2848), .B(n1104), .Y(n2053) );
OR2X6TS U2453 ( .A(n2053), .B(DMP_SFG[12]), .Y(n1936) );
OAI21X2TS U2454 ( .A0(n2049), .A1(n2165), .B0(n1933), .Y(n1935) );
AOI21X4TS U2455 ( .A0(n1936), .A1(n1935), .B0(n1934), .Y(n2512) );
XOR2X4TS U2456 ( .A(n2898), .B(DmP_mant_SFG_SWR[15]), .Y(n1937) );
NOR2X4TS U2457 ( .A(n1937), .B(DMP_SFG[13]), .Y(n2509) );
OAI21X4TS U2458 ( .A0(n2512), .A1(n2509), .B0(n2510), .Y(n1956) );
NOR2X4TS U2459 ( .A(n1938), .B(DMP_SFG[14]), .Y(n1953) );
INVX8TS U2460 ( .A(n2527), .Y(n1948) );
AOI2BB1X4TS U2461 ( .A0N(n2246), .A1N(n1953), .B0(n1948), .Y(n1940) );
NAND2X4TS U2462 ( .A(n1939), .B(DMP_SFG[15]), .Y(n1946) );
XOR2X4TS U2463 ( .A(n1940), .B(n1297), .Y(n1942) );
OAI21X4TS U2464 ( .A0(n1942), .A1(n1374), .B0(n1941), .Y(n621) );
AOI22X1TS U2465 ( .A0(n2383), .A1(DmP_mant_SHT1_SW[13]), .B0(n2384), .B1(
DmP_mant_SHT1_SW[12]), .Y(n1943) );
AOI22X1TS U2466 ( .A0(n2409), .A1(DmP_mant_SHT1_SW[9]), .B0(n2384), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1944) );
AOI21X4TS U2467 ( .A0(n1954), .A1(n1948), .B0(n1947), .Y(n2242) );
NAND2X4TS U2468 ( .A(DMP_SFG[16]), .B(n1949), .Y(n2430) );
INVX2TS U2469 ( .A(n2247), .Y(n1951) );
XOR2X4TS U2470 ( .A(n2898), .B(DmP_mant_SFG_SWR[20]), .Y(n1958) );
OR2X6TS U2471 ( .A(n1958), .B(DMP_SFG[18]), .Y(n2435) );
NAND2X4TS U2472 ( .A(n2435), .B(n1994), .Y(n1972) );
XOR2X4TS U2473 ( .A(n2898), .B(DmP_mant_SFG_SWR[22]), .Y(n1959) );
OR2X6TS U2474 ( .A(n1959), .B(DMP_SFG[20]), .Y(n1976) );
INVX2TS U2475 ( .A(n2038), .Y(n1963) );
INVX2TS U2476 ( .A(n1980), .Y(n1961) );
OAI21X4TS U2477 ( .A0(n2437), .A1(n1963), .B0(n2041), .Y(n1965) );
XOR2X4TS U2478 ( .A(n1965), .B(n1964), .Y(n1967) );
OAI21X4TS U2479 ( .A0(n1967), .A1(n1374), .B0(n1966), .Y(n614) );
OAI21X4TS U2480 ( .A0(n2437), .A1(n1972), .B0(n1974), .Y(n1969) );
XOR2X4TS U2481 ( .A(n1969), .B(n1968), .Y(n1971) );
INVX2TS U2482 ( .A(n1972), .Y(n1973) );
NAND2X2TS U2483 ( .A(n1973), .B(n1976), .Y(n1979) );
XOR2X4TS U2484 ( .A(n1983), .B(n1982), .Y(n1985) );
INVX2TS U2485 ( .A(n1986), .Y(n1990) );
NAND2X2TS U2486 ( .A(n1990), .B(n1989), .Y(n2226) );
NAND2X2TS U2487 ( .A(n1994), .B(n1993), .Y(n1995) );
XOR2X4TS U2488 ( .A(n1996), .B(n1995), .Y(n1998) );
OAI21X4TS U2489 ( .A0(n1998), .A1(n1375), .B0(n1997), .Y(n617) );
NAND2X6TS U2490 ( .A(n2506), .B(DMP_SFG[0]), .Y(n2505) );
INVX2TS U2491 ( .A(n2505), .Y(n2000) );
NAND2X4TS U2492 ( .A(n2505), .B(n2549), .Y(n1999) );
AOI22X4TS U2493 ( .A0(n2000), .A1(DMP_SFG[1]), .B0(n1999), .B1(n2341), .Y(
n2205) );
XOR2X4TS U2494 ( .A(n1398), .B(DmP_mant_SFG_SWR[4]), .Y(n2104) );
XOR2X1TS U2495 ( .A(n2104), .B(DMP_SFG[2]), .Y(n2001) );
XOR2X4TS U2496 ( .A(n2205), .B(n2001), .Y(n2002) );
INVX2TS U2497 ( .A(n2469), .Y(n2005) );
OAI21X2TS U2498 ( .A0(n2005), .A1(n2004), .B0(n2003), .Y(n2068) );
NAND2X1TS U2499 ( .A(n2188), .B(n2170), .Y(n2008) );
NAND2X1TS U2500 ( .A(n2096), .B(n2395), .Y(n2007) );
NAND2X1TS U2501 ( .A(n2124), .B(n2135), .Y(n2006) );
NAND3X4TS U2502 ( .A(n2008), .B(n2007), .C(n2006), .Y(n2067) );
MXI2X4TS U2503 ( .A(n2068), .B(n2067), .S0(n2344), .Y(n2010) );
AOI22X1TS U2504 ( .A0(n2408), .A1(n1377), .B0(n2347), .B1(n2367), .Y(n2009)
);
NAND2X1TS U2505 ( .A(n1289), .B(n2469), .Y(n2014) );
NAND2X1TS U2506 ( .A(n2188), .B(n2408), .Y(n2013) );
NAND2X2TS U2507 ( .A(n2020), .B(n1370), .Y(n2019) );
NAND2X1TS U2508 ( .A(n2015), .B(n2170), .Y(n2016) );
AOI22X1TS U2509 ( .A0(n2347), .A1(n2077), .B0(n2195), .B1(n2172), .Y(n2018)
);
AND2X4TS U2510 ( .A(n2019), .B(n2018), .Y(n3017) );
MXI2X4TS U2511 ( .A(n3017), .B(n2659), .S0(n980), .Y(n550) );
NAND2X2TS U2512 ( .A(n2020), .B(n1376), .Y(n2022) );
AOI22X1TS U2513 ( .A0(n2348), .A1(n2077), .B0(n2200), .B1(n2172), .Y(n2021)
);
MXI2X4TS U2514 ( .A(n2991), .B(n2660), .S0(n979), .Y(n595) );
MXI2X4TS U2515 ( .A(n3013), .B(n2669), .S0(n979), .Y(n552) );
MXI2X4TS U2516 ( .A(n2995), .B(n2667), .S0(n2492), .Y(n606) );
NAND2X1TS U2517 ( .A(n2188), .B(n2395), .Y(n2028) );
NAND2X1TS U2518 ( .A(n2124), .B(n2170), .Y(n2027) );
NAND2X2TS U2519 ( .A(n2035), .B(n1370), .Y(n2034) );
NAND3X2TS U2520 ( .A(n2761), .B(n2760), .C(n2759), .Y(n2389) );
NAND2X4TS U2521 ( .A(n2032), .B(n2031), .Y(n2076) );
AOI22X1TS U2522 ( .A0(n2236), .A1(n2389), .B0(n2195), .B1(n2076), .Y(n2033)
);
AND2X4TS U2523 ( .A(n2034), .B(n2033), .Y(n3015) );
NAND2X2TS U2524 ( .A(n2035), .B(n1376), .Y(n2037) );
AOI22X1TS U2525 ( .A0(n2076), .A1(n2200), .B0(n2389), .B1(n1377), .Y(n2036)
);
MXI2X4TS U2526 ( .A(n2993), .B(n2652), .S0(n2499), .Y(n588) );
XOR2X1TS U2527 ( .A(n1143), .B(DmP_mant_SFG_SWR[25]), .Y(n2042) );
XOR2X4TS U2528 ( .A(n2043), .B(n2042), .Y(n2045) );
OAI21X4TS U2529 ( .A0(n2045), .A1(n1375), .B0(n2044), .Y(n613) );
NAND2X2TS U2530 ( .A(n2046), .B(n1376), .Y(n2048) );
AND2X8TS U2531 ( .A(n2048), .B(n2047), .Y(n2989) );
INVX2TS U2532 ( .A(n2049), .Y(n2051) );
XOR2X1TS U2533 ( .A(n2053), .B(DMP_SFG[12]), .Y(n2054) );
MXI2X2TS U2534 ( .A(n2056), .B(n1252), .S0(n2426), .Y(n611) );
NAND2X2TS U2535 ( .A(n2450), .B(n1310), .Y(n2060) );
AOI22X1TS U2536 ( .A0(n2408), .A1(n2347), .B0(n2348), .B1(n2367), .Y(n2069)
);
MXI2X4TS U2537 ( .A(n3001), .B(n2653), .S0(n2499), .Y(n580) );
NAND2X2TS U2538 ( .A(n2071), .B(DMP_EXP_EWSW[24]), .Y(n2212) );
OAI21X4TS U2539 ( .A0(n2479), .A1(n2210), .B0(n2212), .Y(n2216) );
OAI22X4TS U2540 ( .A0(n2216), .A1(n2072), .B0(n1349), .B1(n2614), .Y(n2222)
);
NAND2X2TS U2541 ( .A(n2639), .B(DMP_EXP_EWSW[26]), .Y(n2218) );
OAI21X1TS U2542 ( .A0(n2222), .A1(n2219), .B0(n2218), .Y(n2074) );
XOR2X1TS U2543 ( .A(n1219), .B(DmP_EXP_EWSW[27]), .Y(n2073) );
INVX2TS U2544 ( .A(Shift_amount_SHT1_EWR[4]), .Y(n2260) );
MXI2X4TS U2545 ( .A(n2075), .B(n2260), .S0(n2480), .Y(n843) );
AOI22X1TS U2546 ( .A0(n2144), .A1(n2236), .B0(n1377), .B1(n1124), .Y(n2083)
);
NAND2X4TS U2547 ( .A(n2076), .B(n1356), .Y(n2081) );
NAND2X1TS U2548 ( .A(n862), .B(n1308), .Y(n2080) );
NAND2X1TS U2549 ( .A(n2124), .B(n2408), .Y(n2079) );
AND2X8TS U2550 ( .A(n2083), .B(n2082), .Y(n3025) );
BUFX20TS U2551 ( .A(n1927), .Y(n2449) );
NAND2X2TS U2552 ( .A(n2450), .B(DMP_EXP_EWSW[24]), .Y(n2084) );
NAND2X2TS U2553 ( .A(n2450), .B(DMP_EXP_EWSW[26]), .Y(n2087) );
NAND2X2TS U2554 ( .A(n2450), .B(DMP_EXP_EWSW[23]), .Y(n2092) );
NAND3BX2TS U2555 ( .AN(n2801), .B(n2094), .C(n2800), .Y(n853) );
INVX2TS U2556 ( .A(n2095), .Y(n2125) );
AOI22X2TS U2557 ( .A0(n2125), .A1(n853), .B0(n2096), .B1(n857), .Y(n2100) );
NAND2X2TS U2558 ( .A(n2097), .B(n1356), .Y(n2098) );
XOR2X4TS U2559 ( .A(n1334), .B(DmP_mant_SFG_SWR[5]), .Y(n2103) );
INVX2TS U2560 ( .A(n2103), .Y(n2102) );
OAI21X4TS U2561 ( .A0(n2106), .A1(n2203), .B0(n2227), .Y(n2421) );
NOR3X2TS U2562 ( .A(n2106), .B(n2204), .C(n2105), .Y(n2107) );
XNOR2X4TS U2563 ( .A(n1398), .B(DmP_mant_SFG_SWR[6]), .Y(n2108) );
INVX2TS U2564 ( .A(n2419), .Y(n2109) );
NAND2X4TS U2565 ( .A(n2108), .B(n2544), .Y(n2420) );
XNOR2X4TS U2566 ( .A(n2111), .B(n2110), .Y(n2112) );
MXI2X4TS U2567 ( .A(n2999), .B(n2666), .S0(n2492), .Y(n578) );
NOR3X1TS U2568 ( .A(n2845), .B(n964), .C(Raw_mant_NRM_SWR[7]), .Y(n2114) );
NAND2X4TS U2569 ( .A(n2120), .B(n1316), .Y(n2337) );
OAI2BB1X4TS U2570 ( .A0N(n1245), .A1N(n1039), .B0(n2264), .Y(n610) );
MXI2X4TS U2571 ( .A(n2989), .B(n2665), .S0(n2492), .Y(n590) );
NAND2X4TS U2572 ( .A(n2123), .B(n1356), .Y(n2129) );
NAND3X1TS U2573 ( .A(n2718), .B(n2717), .C(n2716), .Y(n2477) );
AOI22X2TS U2574 ( .A0(n2125), .A1(n2477), .B0(n2190), .B1(n856), .Y(n2126)
);
MXI2X4TS U2575 ( .A(n3025), .B(n2668), .S0(n981), .Y(n546) );
AOI22X1TS U2576 ( .A0(n2144), .A1(n1377), .B0(n2347), .B1(n1124), .Y(n2138)
);
MXI2X4TS U2577 ( .A(n2983), .B(n2663), .S0(n2499), .Y(n601) );
MXI2X4TS U2578 ( .A(n3019), .B(n2658), .S0(n979), .Y(n549) );
OAI2BB1X4TS U2579 ( .A0N(final_result_ieee[30]), .A1N(n2535), .B0(n2140),
.Y(n835) );
INVX2TS U2580 ( .A(n2141), .Y(n2142) );
INVX2TS U2581 ( .A(n2144), .Y(n2145) );
NAND2BX4TS U2582 ( .AN(n2181), .B(n2151), .Y(n2154) );
INVX2TS U2583 ( .A(n2179), .Y(n2152) );
XOR2X4TS U2584 ( .A(n2154), .B(n2153), .Y(n2155) );
MXI2X4TS U2585 ( .A(n2155), .B(n2860), .S0(n2507), .Y(n587) );
MXI2X4TS U2586 ( .A(n2157), .B(n2156), .S0(n2344), .Y(n2159) );
AOI22X1TS U2587 ( .A0(n862), .A1(n2347), .B0(n1377), .B1(n2395), .Y(n2158)
);
MXI2X4TS U2588 ( .A(n3009), .B(n2654), .S0(n2492), .Y(n554) );
INVX2TS U2589 ( .A(n2182), .Y(n2160) );
AOI21X2TS U2590 ( .A0(n2160), .A1(n2179), .B0(n2183), .Y(n2163) );
OAI21X2TS U2591 ( .A0(n2163), .A1(n2162), .B0(n2161), .Y(n2168) );
INVX2TS U2592 ( .A(n2164), .Y(n2166) );
NAND2X2TS U2593 ( .A(n2166), .B(n2165), .Y(n2167) );
INVX2TS U2594 ( .A(n2170), .Y(n2171) );
AOI22X1TS U2595 ( .A0(n2469), .A1(n2348), .B0(n2236), .B1(n2391), .Y(n2178)
);
NAND2X1TS U2596 ( .A(n1308), .B(n2367), .Y(n2175) );
NAND2X1TS U2597 ( .A(n2189), .B(n2395), .Y(n2174) );
MXI2X4TS U2598 ( .A(n3023), .B(n2656), .S0(n982), .Y(n547) );
NOR2X1TS U2599 ( .A(n2183), .B(n2182), .Y(n2184) );
NAND2X4TS U2600 ( .A(n2187), .B(n1356), .Y(n2194) );
NAND2X1TS U2601 ( .A(n1308), .B(n864), .Y(n2193) );
NAND2X1TS U2602 ( .A(n2189), .B(n2385), .Y(n2192) );
AOI22X1TS U2603 ( .A0(n2347), .A1(n856), .B0(n2195), .B1(n2199), .Y(n2196)
);
MXI2X4TS U2604 ( .A(n3021), .B(n2657), .S0(n980), .Y(n548) );
AOI22X1TS U2605 ( .A0(n1377), .A1(n856), .B0(n2200), .B1(n2199), .Y(n2201)
);
MXI2X4TS U2606 ( .A(n2987), .B(n2651), .S0(n2499), .Y(n592) );
OAI21X4TS U2607 ( .A0(n2205), .A1(n2204), .B0(n2203), .Y(n2208) );
NAND2X1TS U2608 ( .A(n2227), .B(n2206), .Y(n2207) );
XOR2X4TS U2609 ( .A(n2208), .B(n2207), .Y(n2209) );
MXI2X4TS U2610 ( .A(n2209), .B(n2845), .S0(n1375), .Y(n591) );
CLKBUFX3TS U2611 ( .A(n988), .Y(n2897) );
INVX8TS U2612 ( .A(n2471), .Y(busy) );
INVX2TS U2613 ( .A(n2210), .Y(n2211) );
NAND2X1TS U2614 ( .A(n2212), .B(n2211), .Y(n2213) );
XNOR2X1TS U2615 ( .A(n2213), .B(n2479), .Y(n2214) );
MXI2X1TS U2616 ( .A(n2214), .B(n2661), .S0(n2480), .Y(n846) );
CLKMX2X2TS U2617 ( .A(DMP_exp_NRM_EW[7]), .B(DMP_SFG[30]), .S0(n1357), .Y(
n693) );
CLKMX2X2TS U2618 ( .A(DMP_exp_NRM_EW[4]), .B(DMP_SFG[27]), .S0(n1358), .Y(
n708) );
CLKMX2X2TS U2619 ( .A(SIGN_FLAG_NRM), .B(SIGN_FLAG_SFG), .S0(n1358), .Y(n626) );
CLKMX2X2TS U2620 ( .A(DMP_exp_NRM_EW[1]), .B(DMP_SFG[24]), .S0(n1358), .Y(
n723) );
CLKMX2X2TS U2621 ( .A(DMP_exp_NRM_EW[3]), .B(DMP_SFG[26]), .S0(n1358), .Y(
n713) );
CLKMX2X2TS U2622 ( .A(DMP_exp_NRM_EW[2]), .B(DMP_SFG[25]), .S0(n1358), .Y(
n718) );
CLKMX2X2TS U2623 ( .A(DMP_exp_NRM_EW[5]), .B(DMP_SFG[28]), .S0(n1358), .Y(
n703) );
CLKMX2X2TS U2624 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[23]), .S0(n1358), .Y(
n728) );
CLKMX2X2TS U2625 ( .A(DMP_exp_NRM_EW[6]), .B(DMP_SFG[29]), .S0(n1358), .Y(
n698) );
XNOR2X1TS U2626 ( .A(n1349), .B(DmP_EXP_EWSW[25]), .Y(n2215) );
XNOR2X1TS U2627 ( .A(n2216), .B(n2215), .Y(n2217) );
MXI2X1TS U2628 ( .A(n2217), .B(n2609), .S0(n2480), .Y(n845) );
INVX2TS U2629 ( .A(n2218), .Y(n2220) );
NOR2X1TS U2630 ( .A(n2220), .B(n2219), .Y(n2221) );
XOR2X1TS U2631 ( .A(n2222), .B(n2221), .Y(n2223) );
INVX2TS U2632 ( .A(Shift_amount_SHT1_EWR[3]), .Y(n2324) );
MXI2X2TS U2633 ( .A(n2223), .B(n2324), .S0(n2480), .Y(n844) );
MXI2X2TS U2634 ( .A(n2643), .B(inst_FSM_INPUT_ENABLE_state_reg[1]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2225) );
MXI2X1TS U2635 ( .A(n2543), .B(n2426), .S0(n2503), .Y(n946) );
INVX2TS U2636 ( .A(n2227), .Y(n2228) );
XOR2X1TS U2637 ( .A(n2231), .B(DMP_SFG[6]), .Y(n2232) );
XNOR2X4TS U2638 ( .A(n2233), .B(n2232), .Y(n2234) );
MXI2X2TS U2639 ( .A(n2234), .B(n1553), .S0(n2426), .Y(n605) );
AOI22X4TS U2640 ( .A0(n2235), .A1(n1370), .B0(n1377), .B1(n1335), .Y(n3027)
);
MXI2X2TS U2641 ( .A(n3027), .B(n2655), .S0(n981), .Y(n545) );
AOI22X1TS U2642 ( .A0(n2469), .A1(n2236), .B0(n1377), .B1(n2391), .Y(n2240)
);
NAND2X2TS U2643 ( .A(n2429), .B(n2431), .Y(n2245) );
OAI21X4TS U2644 ( .A0(n2246), .A1(n2245), .B0(n2244), .Y(n2249) );
XNOR2X4TS U2645 ( .A(n2249), .B(n2248), .Y(n2250) );
NAND2X2TS U2646 ( .A(n2251), .B(n1279), .Y(n2258) );
NAND3X2TS U2647 ( .A(n2258), .B(n2257), .C(n2256), .Y(n604) );
NAND2X2TS U2648 ( .A(n1137), .B(n2752), .Y(final_result_ieee[29]) );
NOR2X1TS U2649 ( .A(n2260), .B(n1279), .Y(n2261) );
NAND2X4TS U2650 ( .A(n2264), .B(n2263), .Y(n848) );
NAND2X1TS U2651 ( .A(n2305), .B(n1215), .Y(n2265) );
NAND2X2TS U2652 ( .A(n2295), .B(DmP_EXP_EWSW[1]), .Y(n2273) );
NAND2X2TS U2653 ( .A(n1257), .B(n1346), .Y(n2279) );
NAND2X2TS U2654 ( .A(n2450), .B(DmP_EXP_EWSW[27]), .Y(n2280) );
NAND2X2TS U2655 ( .A(n2285), .B(DmP_EXP_EWSW[10]), .Y(n2286) );
NAND2X2TS U2656 ( .A(n2295), .B(DMP_EXP_EWSW[30]), .Y(n2289) );
NAND2X2TS U2657 ( .A(n2295), .B(DMP_EXP_EWSW[28]), .Y(n2296) );
NAND2X2TS U2658 ( .A(n2449), .B(n1389), .Y(n2303) );
NAND2X2TS U2659 ( .A(n1257), .B(intDY_EWSW[5]), .Y(n2308) );
NAND2X2TS U2660 ( .A(n1405), .B(n1346), .Y(n2307) );
NAND2X1TS U2661 ( .A(n2305), .B(n1118), .Y(n2306) );
NAND2X2TS U2662 ( .A(n1917), .B(intDY_EWSW[4]), .Y(n2311) );
NAND2X2TS U2663 ( .A(n1361), .B(n1339), .Y(n2310) );
NAND2X2TS U2664 ( .A(n1405), .B(intDX_EWSW[12]), .Y(n2313) );
NOR3X1TS U2665 ( .A(n2615), .B(Raw_mant_NRM_SWR[2]), .C(Raw_mant_NRM_SWR[4]),
.Y(n2315) );
AOI21X1TS U2666 ( .A0(n2316), .A1(n2317), .B0(n970), .Y(n2321) );
NAND2X4TS U2667 ( .A(n2323), .B(n1211), .Y(n2332) );
NOR2X1TS U2668 ( .A(n2470), .B(n2324), .Y(n2325) );
NAND2X1TS U2669 ( .A(n2326), .B(n1270), .Y(n2328) );
NAND4X1TS U2670 ( .A(n2328), .B(n2327), .C(n2581), .D(n1239), .Y(n2329) );
INVX2TS U2671 ( .A(n2335), .Y(n2336) );
NAND2X2TS U2672 ( .A(n1033), .B(n2336), .Y(n2338) );
MXI2X4TS U2673 ( .A(n2346), .B(n2345), .S0(n2344), .Y(n2350) );
AOI22X2TS U2674 ( .A0(n2348), .A1(n2399), .B0(n2347), .B1(n864), .Y(n2349)
);
NAND2X2TS U2675 ( .A(n1455), .B(DmP_mant_SHT1_SW[20]), .Y(n2937) );
NAND2BX4TS U2676 ( .AN(n1084), .B(n959), .Y(n2974) );
NOR2X2TS U2677 ( .A(n2352), .B(n2351), .Y(n639) );
AOI22X1TS U2678 ( .A0(n2383), .A1(DmP_mant_SHT1_SW[2]), .B0(n2384), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2355) );
NAND2X2TS U2679 ( .A(n1450), .B(n1326), .Y(n2354) );
AOI22X1TS U2680 ( .A0(n2383), .A1(DmP_mant_SHT1_SW[6]), .B0(n2384), .B1(
DmP_mant_SHT1_SW[5]), .Y(n2357) );
NAND2X2TS U2681 ( .A(n2409), .B(DmP_mant_SHT1_SW[21]), .Y(n2361) );
NAND2X2TS U2682 ( .A(n2409), .B(DmP_mant_SHT1_SW[15]), .Y(n2364) );
INVX2TS U2683 ( .A(n2367), .Y(n2370) );
OAI21X4TS U2684 ( .A0(n2259), .A1(n2370), .B0(n2369), .Y(n2371) );
AOI22X1TS U2685 ( .A0(n2383), .A1(DmP_mant_SHT1_SW[1]), .B0(n2384), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2373) );
AOI22X1TS U2686 ( .A0(n2383), .A1(DmP_mant_SHT1_SW[5]), .B0(n2384), .B1(
DmP_mant_SHT1_SW[4]), .Y(n2379) );
NAND2X4TS U2687 ( .A(n1451), .B(n970), .Y(n2378) );
NOR2X2TS U2688 ( .A(n1290), .B(n2382), .Y(n2980) );
NAND2X2TS U2689 ( .A(n1290), .B(DmP_mant_SHT1_SW[20]), .Y(n2853) );
NAND2X1TS U2690 ( .A(n2384), .B(DmP_mant_SHT1_SW[14]), .Y(n2387) );
INVX2TS U2691 ( .A(n2385), .Y(n2386) );
NAND2X2TS U2692 ( .A(n1290), .B(DmP_mant_SHT1_SW[14]), .Y(n2963) );
NAND2X2TS U2693 ( .A(n1545), .B(Raw_mant_NRM_SWR[0]), .Y(n2978) );
AOI21X2TS U2694 ( .A0(n961), .A1(DmP_mant_SHT1_SW[8]), .B0(n2390), .Y(n2950)
);
NAND2X2TS U2695 ( .A(n1545), .B(Raw_mant_NRM_SWR[5]), .Y(n2965) );
INVX2TS U2696 ( .A(n2391), .Y(n2392) );
AOI2BB2X2TS U2697 ( .B0(n2394), .B1(DmP_mant_SHT1_SW[3]), .A0N(n1084), .A1N(
n1270), .Y(n2933) );
INVX2TS U2698 ( .A(n2395), .Y(n2396) );
AOI21X2TS U2699 ( .A0(n961), .A1(DmP_mant_SHT1_SW[16]), .B0(n2397), .Y(n2929) );
INVX2TS U2700 ( .A(n2399), .Y(n2400) );
AOI21X2TS U2701 ( .A0(n961), .A1(DmP_mant_SHT1_SW[14]), .B0(n2401), .Y(n2917) );
INVX2TS U2702 ( .A(n2402), .Y(n2403) );
INVX2TS U2703 ( .A(n2404), .Y(n2405) );
AOI2BB2X2TS U2704 ( .B0(n2407), .B1(Raw_mant_NRM_SWR[7]), .A0N(n1084), .A1N(
n2860), .Y(n2928) );
OAI22X2TS U2705 ( .A0(n1134), .A1(n2747), .B0(n1020), .B1(n2746), .Y(
final_result_ieee[5]) );
OAI22X2TS U2706 ( .A0(n1022), .A1(n2773), .B0(n1020), .B1(n2772), .Y(
final_result_ieee[13]) );
OAI22X2TS U2707 ( .A0(n1013), .A1(n2743), .B0(n1138), .B1(n2742), .Y(
final_result_ieee[18]) );
OAI22X2TS U2708 ( .A0(n1013), .A1(n2790), .B0(n1020), .B1(n2789), .Y(
final_result_ieee[9]) );
OAI22X2TS U2709 ( .A0(n1022), .A1(n2734), .B0(n1138), .B1(n2733), .Y(
final_result_ieee[19]) );
OAI22X2TS U2710 ( .A0(n1022), .A1(n2843), .B0(n1138), .B1(n2842), .Y(
final_result_ieee[22]) );
OAI22X2TS U2711 ( .A0(n1013), .A1(n2823), .B0(n1020), .B1(n2822), .Y(
final_result_ieee[12]) );
OAI22X2TS U2712 ( .A0(n1022), .A1(n2749), .B0(n1138), .B1(n2748), .Y(
final_result_ieee[16]) );
OAI22X2TS U2713 ( .A0(n1013), .A1(n2758), .B0(n1138), .B1(n2757), .Y(
final_result_ieee[15]) );
OAI22X2TS U2714 ( .A0(n1022), .A1(n2803), .B0(n1136), .B1(n2802), .Y(
final_result_ieee[1]) );
OAI22X2TS U2715 ( .A0(n1022), .A1(n2723), .B0(n1020), .B1(n2722), .Y(
final_result_ieee[11]) );
OAI22X2TS U2716 ( .A0(n1022), .A1(n2745), .B0(n1020), .B1(n2744), .Y(
final_result_ieee[10]) );
OAI22X2TS U2717 ( .A0(n1022), .A1(n2756), .B0(n1136), .B1(n2755), .Y(
final_result_ieee[4]) );
OAI22X2TS U2718 ( .A0(n1134), .A1(n2799), .B0(n1020), .B1(n2798), .Y(
final_result_ieee[20]) );
OAI22X2TS U2719 ( .A0(n1022), .A1(n2788), .B0(n1020), .B1(n2787), .Y(
final_result_ieee[7]) );
OAI22X2TS U2720 ( .A0(n1013), .A1(n2736), .B0(n1138), .B1(n2735), .Y(
final_result_ieee[14]) );
OAI22X2TS U2721 ( .A0(n1013), .A1(n2775), .B0(n1138), .B1(n2774), .Y(
final_result_ieee[21]) );
OAI22X2TS U2722 ( .A0(n1022), .A1(n2715), .B0(n1020), .B1(n2714), .Y(
final_result_ieee[8]) );
OAI22X2TS U2723 ( .A0(n1013), .A1(n2751), .B0(n1020), .B1(n2750), .Y(
final_result_ieee[6]) );
OAI22X2TS U2724 ( .A0(n1013), .A1(n2805), .B0(n1136), .B1(n2804), .Y(
final_result_ieee[0]) );
NAND2X1TS U2725 ( .A(n2409), .B(DmP_mant_SHT1_SW[10]), .Y(n2413) );
INVX2TS U2726 ( .A(n1035), .Y(n2412) );
OAI22X1TS U2727 ( .A0(n2414), .A1(n2413), .B0(n2412), .B1(n2411), .Y(n2415)
);
AOI21X2TS U2728 ( .A0(n2416), .A1(n1240), .B0(n2415), .Y(n2924) );
MXI2X1TS U2729 ( .A(n2418), .B(final_result_ieee[29]), .S0(n2535), .Y(n3033)
);
NAND2X2TS U2730 ( .A(n2423), .B(n2422), .Y(n2424) );
XNOR2X4TS U2731 ( .A(n2425), .B(n2424), .Y(n2427) );
MXI2X2TS U2732 ( .A(n2427), .B(n2846), .S0(n2426), .Y(n589) );
CLKBUFX2TS U2733 ( .A(n2865), .Y(n2697) );
CLKBUFX2TS U2734 ( .A(n2881), .Y(n2694) );
CLKBUFX2TS U2735 ( .A(n2865), .Y(n2696) );
CLKBUFX3TS U2736 ( .A(n2865), .Y(n2693) );
BUFX3TS U2737 ( .A(n2865), .Y(n2866) );
CLKBUFX3TS U2738 ( .A(n2865), .Y(n2698) );
BUFX3TS U2739 ( .A(n2871), .Y(n2890) );
BUFX3TS U2740 ( .A(n978), .Y(n2891) );
BUFX3TS U2741 ( .A(n2897), .Y(n2887) );
BUFX3TS U2742 ( .A(n2872), .Y(n2888) );
BUFX3TS U2743 ( .A(n2871), .Y(n2889) );
BUFX3TS U2744 ( .A(n978), .Y(n2892) );
BUFX3TS U2745 ( .A(n2869), .Y(n2878) );
CLKBUFX3TS U2746 ( .A(n2897), .Y(n2894) );
CLKBUFX3TS U2747 ( .A(n2894), .Y(n2876) );
BUFX3TS U2748 ( .A(n2897), .Y(n2886) );
BUFX3TS U2749 ( .A(n2897), .Y(n2882) );
BUFX3TS U2750 ( .A(n2897), .Y(n2884) );
BUFX3TS U2751 ( .A(n2897), .Y(n2885) );
BUFX3TS U2752 ( .A(n2897), .Y(n2883) );
BUFX3TS U2753 ( .A(n2896), .Y(n2877) );
BUFX3TS U2754 ( .A(n2872), .Y(n2893) );
BUFX3TS U2755 ( .A(n2894), .Y(n2875) );
BUFX3TS U2756 ( .A(n1363), .Y(n2881) );
OAI22X2TS U2757 ( .A0(n1013), .A1(n2732), .B0(n1136), .B1(n2731), .Y(
final_result_ieee[3]) );
AOI21X4TS U2758 ( .A0(n2429), .A1(n2529), .B0(n2428), .Y(n2433) );
NAND2X2TS U2759 ( .A(n2431), .B(n2430), .Y(n2432) );
NAND2X2TS U2760 ( .A(n1267), .B(intDY_EWSW[11]), .Y(n2442) );
NAND2X2TS U2761 ( .A(n2449), .B(n1258), .Y(n2452) );
NAND2X2TS U2762 ( .A(n2450), .B(n1219), .Y(n2451) );
AOI2BB2X2TS U2763 ( .B0(n1352), .B1(n2462), .A0N(n1084), .A1N(n1241), .Y(
n2906) );
CLKBUFX2TS U2764 ( .A(n2696), .Y(n2692) );
CLKBUFX2TS U2765 ( .A(n2872), .Y(n2691) );
BUFX3TS U2766 ( .A(n2867), .Y(n2868) );
INVX2TS U2767 ( .A(final_result_ieee[5]), .Y(n2992) );
INVX2TS U2768 ( .A(final_result_ieee[13]), .Y(n3008) );
INVX2TS U2769 ( .A(final_result_ieee[18]), .Y(n3018) );
INVX2TS U2770 ( .A(final_result_ieee[2]), .Y(n2986) );
INVX2TS U2771 ( .A(final_result_ieee[17]), .Y(n3016) );
INVX2TS U2772 ( .A(final_result_ieee[9]), .Y(n3000) );
INVX2TS U2773 ( .A(final_result_ieee[19]), .Y(n3020) );
INVX2TS U2774 ( .A(final_result_ieee[22]), .Y(n3026) );
INVX2TS U2775 ( .A(final_result_ieee[12]), .Y(n3006) );
INVX2TS U2776 ( .A(final_result_ieee[16]), .Y(n3014) );
INVX2TS U2777 ( .A(final_result_ieee[15]), .Y(n3012) );
INVX2TS U2778 ( .A(final_result_ieee[1]), .Y(n2984) );
INVX2TS U2779 ( .A(final_result_ieee[11]), .Y(n3004) );
INVX2TS U2780 ( .A(final_result_ieee[10]), .Y(n3002) );
INVX2TS U2781 ( .A(final_result_ieee[4]), .Y(n2990) );
INVX2TS U2782 ( .A(final_result_ieee[20]), .Y(n3022) );
INVX2TS U2783 ( .A(final_result_ieee[7]), .Y(n2996) );
INVX2TS U2784 ( .A(final_result_ieee[14]), .Y(n3010) );
INVX2TS U2785 ( .A(final_result_ieee[21]), .Y(n3024) );
INVX2TS U2786 ( .A(final_result_ieee[8]), .Y(n2998) );
INVX2TS U2787 ( .A(final_result_ieee[6]), .Y(n2994) );
INVX2TS U2788 ( .A(final_result_ieee[0]), .Y(n2982) );
INVX2TS U2789 ( .A(final_result_ieee[3]), .Y(n2988) );
INVX2TS U2790 ( .A(n2466), .Y(n2473) );
NOR2X1TS U2791 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2464) );
NAND2X2TS U2792 ( .A(n2464), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(
n2465) );
MXI2X1TS U2793 ( .A(beg_OP), .B(n2643), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2467) );
OAI21X1TS U2794 ( .A0(n2467), .A1(n2466), .B0(n2465), .Y(n951) );
NAND2X2TS U2795 ( .A(n1137), .B(n2713), .Y(final_result_ieee[25]) );
NAND2X2TS U2796 ( .A(n1137), .B(n2712), .Y(final_result_ieee[24]) );
MXI2X1TS U2797 ( .A(n2552), .B(n2617), .S0(n2492), .Y(n732) );
NAND2X2TS U2798 ( .A(n1137), .B(n2724), .Y(final_result_ieee[26]) );
NAND2X2TS U2799 ( .A(n1137), .B(n2710), .Y(final_result_ieee[27]) );
NAND2X2TS U2800 ( .A(n1137), .B(n2741), .Y(final_result_ieee[28]) );
CLKMX2X2TS U2801 ( .A(DMP_SHT1_EWSW[8]), .B(n1312), .S0(n2474), .Y(n776) );
CLKMX2X2TS U2802 ( .A(DMP_SHT1_EWSW[13]), .B(DMP_EXP_EWSW[13]), .S0(n2474),
.Y(n761) );
CLKMX2X2TS U2803 ( .A(DMP_SHT1_EWSW[10]), .B(n1325), .S0(n2474), .Y(n770) );
CLKMX2X2TS U2804 ( .A(DMP_SHT1_EWSW[11]), .B(DMP_EXP_EWSW[11]), .S0(n2474),
.Y(n767) );
CLKMX2X2TS U2805 ( .A(DMP_SHT1_EWSW[12]), .B(n822), .S0(n2474), .Y(n764) );
CLKMX2X2TS U2806 ( .A(DmP_mant_SHT1_SW[14]), .B(DmP_EXP_EWSW[14]), .S0(n2474), .Y(n662) );
CLKMX2X2TS U2807 ( .A(DmP_mant_SHT1_SW[19]), .B(DmP_EXP_EWSW[19]), .S0(n2474), .Y(n652) );
CLKMX2X2TS U2808 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n2472),
.Y(n742) );
CLKMX2X2TS U2809 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SHT1), .S0(n2472), .Y(n631)
);
CLKMX2X2TS U2810 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(busy),
.Y(n700) );
CLKMX2X2TS U2811 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n2472),
.Y(n790) );
CLKMX2X2TS U2812 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(busy),
.Y(n787) );
CLKMX2X2TS U2813 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(n2472),
.Y(n796) );
CLKMX2X2TS U2814 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(busy),
.Y(n725) );
CLKMX2X2TS U2815 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(busy),
.Y(n715) );
CLKMX2X2TS U2816 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(busy),
.Y(n730) );
CLKMX2X2TS U2817 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(busy),
.Y(n705) );
CLKMX2X2TS U2818 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(busy),
.Y(n710) );
CLKMX2X2TS U2819 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n2472),
.Y(n760) );
CLKMX2X2TS U2820 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n2472),
.Y(n769) );
CLKMX2X2TS U2821 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n2472),
.Y(n766) );
CLKMX2X2TS U2822 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n2472),
.Y(n781) );
CLKMX2X2TS U2823 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(n2472),
.Y(n775) );
CLKMX2X2TS U2824 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n2472),
.Y(n763) );
CLKMX2X2TS U2825 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n2500),
.Y(n695) );
CLKMX2X2TS U2826 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n2500),
.Y(n751) );
CLKMX2X2TS U2827 ( .A(ZERO_FLAG_SHT2), .B(ZERO_FLAG_SHT1), .S0(n2500), .Y(
n637) );
CLKMX2X2TS U2828 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n2500),
.Y(n745) );
CLKMX2X2TS U2829 ( .A(SIGN_FLAG_SHT2), .B(SIGN_FLAG_SHT1), .S0(n2500), .Y(
n628) );
CLKMX2X2TS U2830 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n2500),
.Y(n754) );
MXI2X1TS U2831 ( .A(n2473), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
CLKMX2X2TS U2832 ( .A(DmP_mant_SHT1_SW[16]), .B(DmP_EXP_EWSW[16]), .S0(n2474), .Y(n658) );
CLKMX2X2TS U2833 ( .A(SIGN_FLAG_SHT1SHT2), .B(SIGN_FLAG_NRM), .S0(n1281),
.Y(n625) );
CLKMX2X2TS U2834 ( .A(ZERO_FLAG_SHT1SHT2), .B(ZERO_FLAG_NRM), .S0(n1282),
.Y(n634) );
CLKMX2X2TS U2835 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n2475),
.Y(n748) );
CLKMX2X2TS U2836 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n2475),
.Y(n757) );
CLKMX2X2TS U2837 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n2475),
.Y(n778) );
CLKMX2X2TS U2838 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n2475),
.Y(n793) );
CLKMX2X2TS U2839 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(n2475),
.Y(n784) );
CLKMX2X2TS U2840 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n2475),
.Y(n799) );
CLKMX2X2TS U2841 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n2475),
.Y(n736) );
CLKMX2X2TS U2842 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n2475),
.Y(n733) );
CLKMX2X2TS U2843 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n2475),
.Y(n772) );
CLKMX2X2TS U2844 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n2475),
.Y(n739) );
AOI22X1TS U2845 ( .A0(n2862), .A1(n2477), .B0(n2476), .B1(n1279), .Y(n2973)
);
NOR2X1TS U2846 ( .A(n2647), .B(DmP_EXP_EWSW[23]), .Y(n2478) );
NOR2X1TS U2847 ( .A(n2479), .B(n2478), .Y(n2481) );
INVX12TS U2848 ( .A(n2480), .Y(n2501) );
MXI2X1TS U2849 ( .A(n2579), .B(n2481), .S0(n2501), .Y(n847) );
INVX12TS U2850 ( .A(n2480), .Y(n2482) );
CLKMX2X2TS U2851 ( .A(ZERO_FLAG_SHT1), .B(ZERO_FLAG_EXP), .S0(n2482), .Y(
n638) );
CLKMX2X2TS U2852 ( .A(DMP_SHT1_EWSW[9]), .B(n1209), .S0(n2482), .Y(n773) );
INVX12TS U2853 ( .A(n2480), .Y(n2526) );
CLKMX2X2TS U2854 ( .A(DMP_SHT1_EWSW[21]), .B(n813), .S0(n2526), .Y(n737) );
CLKMX2X2TS U2855 ( .A(DMP_SHT1_EWSW[5]), .B(n1118), .S0(n2526), .Y(n785) );
CLKMX2X2TS U2856 ( .A(DMP_SHT1_EWSW[3]), .B(n1210), .S0(n2482), .Y(n791) );
CLKMX2X2TS U2857 ( .A(DMP_SHT1_EWSW[1]), .B(n1122), .S0(n2482), .Y(n797) );
CLKMX2X2TS U2858 ( .A(DMP_SHT1_EWSW[7]), .B(n827), .S0(n2482), .Y(n779) );
CLKMX2X2TS U2859 ( .A(DMP_SHT1_EWSW[22]), .B(n1213), .S0(n2526), .Y(n734) );
CLKMX2X2TS U2860 ( .A(DMP_SHT1_EWSW[0]), .B(n834), .S0(n2482), .Y(n800) );
CLKMX2X2TS U2861 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n1280),
.Y(n692) );
CLKMX2X2TS U2862 ( .A(DMP_SHT1_EWSW[16]), .B(DMP_EXP_EWSW[16]), .S0(n2501),
.Y(n752) );
CLKMX2X2TS U2863 ( .A(DMP_SHT1_EWSW[30]), .B(DMP_EXP_EWSW[30]), .S0(n2501),
.Y(n696) );
CLKMX2X2TS U2864 ( .A(SIGN_FLAG_SHT1), .B(SIGN_FLAG_EXP), .S0(n2501), .Y(
n629) );
CLKMX2X2TS U2865 ( .A(DMP_SHT1_EWSW[17]), .B(n1218), .S0(n2501), .Y(n749) );
CLKMX2X2TS U2866 ( .A(DMP_SHT1_EWSW[18]), .B(n1119), .S0(n2501), .Y(n746) );
CLKMX2X2TS U2867 ( .A(DmP_mant_SHT1_SW[21]), .B(n649), .S0(n2482), .Y(n648)
);
CLKMX2X2TS U2868 ( .A(DmP_mant_SHT1_SW[5]), .B(n1214), .S0(n2526), .Y(n680)
);
CLKMX2X2TS U2869 ( .A(DmP_mant_SHT1_SW[1]), .B(DmP_EXP_EWSW[1]), .S0(n2526),
.Y(n688) );
CLKMX2X2TS U2870 ( .A(DmP_mant_SHT1_SW[20]), .B(n651), .S0(n2482), .Y(n650)
);
MXI2X1TS U2871 ( .A(n2615), .B(n2483), .S0(n1357), .Y(n608) );
CLKMX2X2TS U2872 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n1281),
.Y(n702) );
CLKMX2X2TS U2873 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n1279),
.Y(n727) );
INVX2TS U2874 ( .A(n2858), .Y(n2484) );
CLKMX2X2TS U2875 ( .A(n2484), .B(DMP_exp_NRM_EW[1]), .S0(n1279), .Y(n722) );
CLKMX2X2TS U2876 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1282),
.Y(n712) );
CLKMX2X2TS U2877 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1282),
.Y(n707) );
INVX2TS U2878 ( .A(n2854), .Y(n2485) );
CLKMX2X2TS U2879 ( .A(n2485), .B(DMP_exp_NRM_EW[2]), .S0(n1280), .Y(n717) );
CLKMX2X2TS U2880 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n1281),
.Y(n697) );
INVX8TS U2881 ( .A(n2648), .Y(n2486) );
CLKMX2X2TS U2882 ( .A(DMP_SHT1_EWSW[23]), .B(DMP_EXP_EWSW[23]), .S0(n2486),
.Y(n731) );
CLKMX2X2TS U2883 ( .A(DMP_SHT1_EWSW[24]), .B(DMP_EXP_EWSW[24]), .S0(n2486),
.Y(n726) );
CLKMX2X2TS U2884 ( .A(DMP_SHT1_EWSW[26]), .B(DMP_EXP_EWSW[26]), .S0(n2486),
.Y(n716) );
CLKMX2X2TS U2885 ( .A(DMP_SHT1_EWSW[27]), .B(n1219), .S0(n2486), .Y(n711) );
CLKMX2X2TS U2886 ( .A(OP_FLAG_SHT1), .B(OP_FLAG_EXP), .S0(n2486), .Y(n632)
);
CLKMX2X2TS U2887 ( .A(DMP_SHT1_EWSW[29]), .B(DMP_EXP_EWSW[29]), .S0(n2486),
.Y(n701) );
CLKMX2X2TS U2888 ( .A(DMP_SHT1_EWSW[4]), .B(n1324), .S0(n2486), .Y(n788) );
CLKMX2X2TS U2889 ( .A(DMP_SHT1_EWSW[28]), .B(DMP_EXP_EWSW[28]), .S0(n2486),
.Y(n706) );
MXI2X1TS U2890 ( .A(n2487), .B(final_result_ieee[24]), .S0(n2899), .Y(n3028)
);
CLKMX2X2TS U2891 ( .A(DMP_SHT1_EWSW[2]), .B(n832), .S0(n2488), .Y(n794) );
CLKMX2X2TS U2892 ( .A(DmP_mant_SHT1_SW[22]), .B(DmP_EXP_EWSW[22]), .S0(n2488), .Y(n646) );
CLKMX2X2TS U2893 ( .A(DmP_mant_SHT1_SW[6]), .B(n679), .S0(n2488), .Y(n678)
);
CLKMX2X2TS U2894 ( .A(DmP_mant_SHT1_SW[8]), .B(n675), .S0(n2488), .Y(n674)
);
CLKMX2X2TS U2895 ( .A(DmP_mant_SHT1_SW[9]), .B(n673), .S0(n2488), .Y(n672)
);
CLKMX2X2TS U2896 ( .A(DmP_mant_SHT1_SW[7]), .B(n677), .S0(n2488), .Y(n676)
);
XNOR2X1TS U2897 ( .A(n1143), .B(DmP_mant_SFG_SWR[0]), .Y(n2489) );
MXI2X1TS U2898 ( .A(n2595), .B(n2489), .S0(n1357), .Y(n602) );
CLKMX2X2TS U2899 ( .A(zero_flag), .B(ZERO_FLAG_SHT1SHT2), .S0(n1036), .Y(
n633) );
MXI2X1TS U2900 ( .A(n2638), .B(n2648), .S0(n2503), .Y(n949) );
MXI2X1TS U2901 ( .A(n2648), .B(n2688), .S0(n2503), .Y(n948) );
MXI2X1TS U2902 ( .A(n1275), .B(n2535), .S0(n2503), .Y(n944) );
MXI2X1TS U2903 ( .A(n2688), .B(n2543), .S0(n2503), .Y(n947) );
CLKINVX1TS U2904 ( .A(n2490), .Y(n2491) );
MXI2X1TS U2905 ( .A(n2491), .B(n2638), .S0(n2503), .Y(n950) );
CLKMX2X2TS U2906 ( .A(DmP_mant_SHT1_SW[0]), .B(DmP_EXP_EWSW[0]), .S0(n2526),
.Y(n690) );
MXI2X1TS U2907 ( .A(n2553), .B(n2650), .S0(n2492), .Y(n735) );
MXI2X1TS U2908 ( .A(n2554), .B(n2649), .S0(n2492), .Y(n738) );
MXI2X1TS U2909 ( .A(n2560), .B(n2682), .S0(n2493), .Y(n724) );
MXI2X1TS U2910 ( .A(n2556), .B(n2677), .S0(n2493), .Y(n699) );
MXI2X1TS U2911 ( .A(n2557), .B(n2678), .S0(n2493), .Y(n704) );
MXI2X1TS U2912 ( .A(n2555), .B(n2676), .S0(n2493), .Y(n694) );
MXI2X1TS U2913 ( .A(n2561), .B(n2683), .S0(n2493), .Y(n729) );
MXI2X1TS U2914 ( .A(n2559), .B(n2680), .S0(n2493), .Y(n714) );
MXI2X1TS U2915 ( .A(n2558), .B(n2679), .S0(n2493), .Y(n709) );
MXI2X1TS U2916 ( .A(n2621), .B(n2544), .S0(n2493), .Y(n786) );
MXI2X1TS U2917 ( .A(n2577), .B(n2681), .S0(n2493), .Y(n719) );
INVX2TS U2918 ( .A(ZERO_FLAG_SFG), .Y(n2494) );
MXI2X1TS U2919 ( .A(n1552), .B(n2494), .S0(n980), .Y(n636) );
BUFX12TS U2920 ( .A(n2498), .Y(n2533) );
MXI2X1TS U2921 ( .A(n2623), .B(n2546), .S0(n2533), .Y(n774) );
MXI2X1TS U2922 ( .A(n2569), .B(n2632), .S0(n2499), .Y(n783) );
MXI2X1TS U2923 ( .A(n2568), .B(n2628), .S0(n2499), .Y(n792) );
MXI2X1TS U2924 ( .A(n2566), .B(n2630), .S0(n2533), .Y(n798) );
MXI2X1TS U2925 ( .A(n2565), .B(n2627), .S0(n2533), .Y(n780) );
MXI2X1TS U2926 ( .A(n2577), .B(n2502), .S0(n2500), .Y(n720) );
MXI2X1TS U2927 ( .A(n2502), .B(n1350), .S0(n2501), .Y(n721) );
MXI2X1TS U2928 ( .A(n2426), .B(n1276), .S0(n2503), .Y(n945) );
MXI2X1TS U2929 ( .A(n2504), .B(final_result_ieee[25]), .S0(n2535), .Y(n3029)
);
OAI21X1TS U2930 ( .A0(n2506), .A1(DMP_SFG[0]), .B0(n2505), .Y(n2508) );
MXI2X1TS U2931 ( .A(n2545), .B(n2508), .S0(n1357), .Y(n600) );
CLKMX2X2TS U2932 ( .A(add_subt), .B(intAS), .S0(n2515), .Y(n911) );
CLKMX2X2TS U2933 ( .A(Data_X[31]), .B(intDX_EWSW[31]), .S0(n2515), .Y(n912)
);
INVX2TS U2934 ( .A(n2509), .Y(n2511) );
NAND2X1TS U2935 ( .A(n2511), .B(n2510), .Y(n2513) );
XOR2X1TS U2936 ( .A(n2513), .B(n2512), .Y(n2514) );
CLKMX2X2TS U2937 ( .A(Data_Y[1]), .B(n1243), .S0(n2515), .Y(n908) );
CLKMX2X2TS U2938 ( .A(Data_Y[0]), .B(intDY_EWSW[0]), .S0(n2515), .Y(n909) );
BUFX12TS U2939 ( .A(n2519), .Y(n2517) );
BUFX12TS U2940 ( .A(n2519), .Y(n2516) );
BUFX12TS U2941 ( .A(n2519), .Y(n2518) );
CLKMX2X3TS U2942 ( .A(Data_Y[18]), .B(intDY_EWSW[18]), .S0(n2516), .Y(n891)
);
CLKMX2X3TS U2943 ( .A(Data_Y[23]), .B(intDY_EWSW[23]), .S0(n2518), .Y(n886)
);
BUFX12TS U2944 ( .A(n2519), .Y(n2525) );
CLKMX2X3TS U2945 ( .A(Data_X[2]), .B(intDX_EWSW[2]), .S0(n2525), .Y(n941) );
BUFX12TS U2946 ( .A(n2519), .Y(n2523) );
BUFX12TS U2947 ( .A(n2519), .Y(n2524) );
CLKMX2X2TS U2948 ( .A(Data_X[30]), .B(intDX_EWSW[30]), .S0(n2523), .Y(n913)
);
CLKMX2X3TS U2949 ( .A(Data_X[29]), .B(intDX_EWSW[29]), .S0(n2523), .Y(n914)
);
CLKMX2X3TS U2950 ( .A(Data_X[14]), .B(intDX_EWSW[14]), .S0(n2524), .Y(n929)
);
NAND2X1TS U2951 ( .A(n2528), .B(n2527), .Y(n2530) );
MXI2X1TS U2952 ( .A(n2532), .B(final_result_ieee[26]), .S0(n2535), .Y(n3030)
);
MXI2X1TS U2953 ( .A(n2625), .B(n2549), .S0(n2533), .Y(n795) );
MXI2X1TS U2954 ( .A(n2534), .B(final_result_ieee[27]), .S0(n2535), .Y(n3031)
);
MXI2X1TS U2955 ( .A(n2536), .B(final_result_ieee[28]), .S0(n2535), .Y(n3032)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk1.tcl_ACAIN16Q4_syn.sdf");
endmodule
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