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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:16:04 05/14/2015
// Design Name:
// Module Name: NumIn
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module NumIn(
input clk,
input[7:0] addFlag,
output reg[31:0] number
);
wire[7:0] btn_out;
pbdebounce p0(clk,addFlag[0],btn_out[0]);
pbdebounce p1(clk,addFlag[1],btn_out[1]);
pbdebounce p2(clk,addFlag[2],btn_out[2]);
pbdebounce p3(clk,addFlag[3],btn_out[3]);
pbdebounce p4(clk,addFlag[4],btn_out[4]);
pbdebounce p5(clk,addFlag[5],btn_out[5]);
pbdebounce p6(clk,addFlag[6],btn_out[6]);
pbdebounce p7(clk,addFlag[7],btn_out[7]);
always @(posedge btn_out[0]) number[ 3: 0] <= number[ 3: 0] + 4'd1;
always @(posedge btn_out[1]) number[ 7: 4] <= number[ 7: 4] + 4'd1;
always @(posedge btn_out[2]) number[11: 8] <= number[11: 8] + 4'd1;
always @(posedge btn_out[3]) number[15:12] <= number[15:12] + 4'd1;
always @(posedge btn_out[4]) number[19:16] <= number[19:16] + 4'd1;
always @(posedge btn_out[5]) number[23:20] <= number[23:20] + 4'd1;
always @(posedge btn_out[6]) number[27:24] <= number[27:24] + 4'd1;
always @(posedge btn_out[7]) number[31:28] <= number[31:28] + 4'd1;
endmodule
module pbdebounce
(input wire clk,
input wire button,
output reg pbreg);
reg [7:0] pbshift;
wire clk_1ms;
timer_1ms m0(clk, clk_1ms);
always@(posedge clk_1ms) begin
pbshift <=pbshift<<1;
pbshift[0] <=button;
if (pbshift==0)
pbreg <=0;
if (pbshift==8'hFF)
pbreg <=1;
end
endmodule
module timer_1ms
(input wire clk,
output reg clk_1ms);
reg [15:0] cnt;
initial begin
cnt [15:0] <=0;
clk_1ms <= 0;
end
always@(posedge clk)
if(cnt>=25000) begin
cnt<=0;
clk_1ms <= ~clk_1ms;
end
else begin
cnt<=cnt+1;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; [email protected]. All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// freqmeter.v: Clock freq. meter for 50% duty-cycle clocks; measures clock period//
// divides the reference clock to increase accuracy and allow low freq. sampling //
// //
// Ameer M.S. Abdelhadi ([email protected]; [email protected]), Sept. 2012 //
////////////////////////////////////////////////////////////////////////////////////
// Ameer Abdelhadi, Sept. 2012
// frequency meter for 50% duty-cycle clocks
// measures clock period -T
module freqmeter
( input rst , // system reset
input clk_50 , // sampling clock, 50Mhz
input clk_ref , // reference clock / frequency to measure
output [15:0] frq_bcd); // measured frequency / BCD {thousands,hundreds,tens,ones}
reg clk_div;
reg [6:0] ccnt;
always @(posedge clk_ref)
if (ccnt==7'd99) {ccnt,clk_div} <= {7'd0,!clk_div};
else ccnt <= ccnt+1'b1;
localparam cntW = 16;
reg [cntW-1:0] cntR,cntF,cntR_,cntF_;
always @(posedge clk_50)
if (!clk_div) cntR <= 12'd0;
else cntR <= cntR+1'b1;
always @(negedge clk_50)
if (!clk_div) cntF <= 12'd0;
else cntF <= cntF+1'b1;
always @(negedge clk_div)
{cntR_,cntF_} <= {cntR,cntF};
bin2bcd16 bin2bcd16_00 (cntR_+cntF_,frq_bcd);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2012.2
// Copyright (C) 2012 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="types_float_double_inst,types_float_double,{component_name=types_float_double_inst,HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc6vlx240tff1759-2,HLS_INPUT_CLOCK=2.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.015000,HLS_SYN_LAT=59,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=14,HLS_SYN_FF=8704,HLS_SYN_LUT=5214}" *)
module types_float_double (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
inA,
inB,
inC,
inD,
out1,
out1_ap_vld,
out2,
out2_ap_vld,
out3,
out3_ap_vld,
out4,
out4_ap_vld
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
input [63:0] inA;
input [63:0] inB;
input [63:0] inC;
input [31:0] inD;
output [63:0] out1;
output out1_ap_vld;
output [63:0] out2;
output out2_ap_vld;
output [63:0] out3;
output out3_ap_vld;
output [31:0] out4;
output out4_ap_vld;
reg ap_done;
reg ap_idle;
reg out1_ap_vld;
reg out2_ap_vld;
reg out3_ap_vld;
reg out4_ap_vld;
reg [5:0] ap_CS_fsm = 6'b000000;
wire [63:0] grp_fu_86_p2;
wire [63:0] grp_fu_93_p2;
wire [63:0] grp_fu_100_p2;
wire [31:0] grp_fu_79_p2;
wire [31:0] grp_fu_79_p1;
wire [63:0] grp_fu_86_p0;
wire [63:0] grp_fu_86_p1;
wire [63:0] grp_fu_93_p0;
wire [63:0] grp_fu_93_p1;
wire [63:0] grp_fu_100_p0;
wire [63:0] grp_fu_100_p1;
wire [31:0] grp_fu_79_p0;
wire grp_fu_79_ce;
wire grp_fu_86_ce;
wire grp_fu_93_ce;
wire grp_fu_100_ce;
reg [5:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 6'b000000;
parameter ap_ST_st1_fsm_1 = 6'b000001;
parameter ap_ST_st2_fsm_2 = 6'b000010;
parameter ap_ST_st3_fsm_3 = 6'b000011;
parameter ap_ST_st4_fsm_4 = 6'b000100;
parameter ap_ST_st5_fsm_5 = 6'b000101;
parameter ap_ST_st6_fsm_6 = 6'b000110;
parameter ap_ST_st7_fsm_7 = 6'b000111;
parameter ap_ST_st8_fsm_8 = 6'b001000;
parameter ap_ST_st9_fsm_9 = 6'b001001;
parameter ap_ST_st10_fsm_10 = 6'b001010;
parameter ap_ST_st11_fsm_11 = 6'b001011;
parameter ap_ST_st12_fsm_12 = 6'b001100;
parameter ap_ST_st13_fsm_13 = 6'b001101;
parameter ap_ST_st14_fsm_14 = 6'b001110;
parameter ap_ST_st15_fsm_15 = 6'b001111;
parameter ap_ST_st16_fsm_16 = 6'b010000;
parameter ap_ST_st17_fsm_17 = 6'b010001;
parameter ap_ST_st18_fsm_18 = 6'b010010;
parameter ap_ST_st19_fsm_19 = 6'b010011;
parameter ap_ST_st20_fsm_20 = 6'b010100;
parameter ap_ST_st21_fsm_21 = 6'b010101;
parameter ap_ST_st22_fsm_22 = 6'b010110;
parameter ap_ST_st23_fsm_23 = 6'b010111;
parameter ap_ST_st24_fsm_24 = 6'b011000;
parameter ap_ST_st25_fsm_25 = 6'b011001;
parameter ap_ST_st26_fsm_26 = 6'b011010;
parameter ap_ST_st27_fsm_27 = 6'b011011;
parameter ap_ST_st28_fsm_28 = 6'b011100;
parameter ap_ST_st29_fsm_29 = 6'b011101;
parameter ap_ST_st30_fsm_30 = 6'b011110;
parameter ap_ST_st31_fsm_31 = 6'b011111;
parameter ap_ST_st32_fsm_32 = 6'b100000;
parameter ap_ST_st33_fsm_33 = 6'b100001;
parameter ap_ST_st34_fsm_34 = 6'b100010;
parameter ap_ST_st35_fsm_35 = 6'b100011;
parameter ap_ST_st36_fsm_36 = 6'b100100;
parameter ap_ST_st37_fsm_37 = 6'b100101;
parameter ap_ST_st38_fsm_38 = 6'b100110;
parameter ap_ST_st39_fsm_39 = 6'b100111;
parameter ap_ST_st40_fsm_40 = 6'b101000;
parameter ap_ST_st41_fsm_41 = 6'b101001;
parameter ap_ST_st42_fsm_42 = 6'b101010;
parameter ap_ST_st43_fsm_43 = 6'b101011;
parameter ap_ST_st44_fsm_44 = 6'b101100;
parameter ap_ST_st45_fsm_45 = 6'b101101;
parameter ap_ST_st46_fsm_46 = 6'b101110;
parameter ap_ST_st47_fsm_47 = 6'b101111;
parameter ap_ST_st48_fsm_48 = 6'b110000;
parameter ap_ST_st49_fsm_49 = 6'b110001;
parameter ap_ST_st50_fsm_50 = 6'b110010;
parameter ap_ST_st51_fsm_51 = 6'b110011;
parameter ap_ST_st52_fsm_52 = 6'b110100;
parameter ap_ST_st53_fsm_53 = 6'b110101;
parameter ap_ST_st54_fsm_54 = 6'b110110;
parameter ap_ST_st55_fsm_55 = 6'b110111;
parameter ap_ST_st56_fsm_56 = 6'b111000;
parameter ap_ST_st57_fsm_57 = 6'b111001;
parameter ap_ST_st58_fsm_58 = 6'b111010;
parameter ap_ST_st59_fsm_59 = 6'b111011;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_true = 1'b1;
types_float_double_grp_fu_79_ACMP_fsqrt_1 #(
.ID( 1 ),
.NUM_STAGE( 30 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
types_float_double_grp_fu_79_ACMP_fsqrt_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_79_p0 ),
.din1( grp_fu_79_p1 ),
.ce( grp_fu_79_ce ),
.dout( grp_fu_79_p2 )
);
types_float_double_grp_fu_86_ACMP_dadd_2 #(
.ID( 2 ),
.NUM_STAGE( 16 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
types_float_double_grp_fu_86_ACMP_dadd_2_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_86_p0 ),
.din1( grp_fu_86_p1 ),
.ce( grp_fu_86_ce ),
.dout( grp_fu_86_p2 )
);
types_float_double_grp_fu_93_ACMP_dmul_3 #(
.ID( 3 ),
.NUM_STAGE( 18 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
types_float_double_grp_fu_93_ACMP_dmul_3_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_93_p0 ),
.din1( grp_fu_93_p1 ),
.ce( grp_fu_93_ce ),
.dout( grp_fu_93_p2 )
);
types_float_double_grp_fu_100_ACMP_ddiv_4 #(
.ID( 4 ),
.NUM_STAGE( 59 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
types_float_double_grp_fu_100_ACMP_ddiv_4_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_100_p0 ),
.din1( grp_fu_100_p1 ),
.ce( grp_fu_100_ce ),
.dout( grp_fu_100_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((ap_ST_st59_fsm_59 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_start))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st59_fsm_59;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st58_fsm_58;
end else if ((ap_ST_st56_fsm_56 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st57_fsm_57;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st56_fsm_56;
end else if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st55_fsm_55;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st54_fsm_54;
end else if ((ap_ST_st52_fsm_52 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st53_fsm_53;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st52_fsm_52;
end else if ((ap_ST_st50_fsm_50 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st51_fsm_51;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st50_fsm_50;
end else if ((ap_ST_st48_fsm_48 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st49_fsm_49;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st48_fsm_48;
end else if ((ap_ST_st46_fsm_46 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st47_fsm_47;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st46_fsm_46;
end else if ((ap_ST_st44_fsm_44 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st45_fsm_45;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st44_fsm_44;
end else if ((ap_ST_st42_fsm_42 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st43_fsm_43;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st42_fsm_42;
end else if ((ap_ST_st40_fsm_40 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st41_fsm_41;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st40_fsm_40;
end else if ((ap_ST_st38_fsm_38 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st39_fsm_39;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st38_fsm_38;
end else if ((ap_ST_st36_fsm_36 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st37_fsm_37;
end else if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st36_fsm_36;
end else if ((ap_ST_st34_fsm_34 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st35_fsm_35;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st34_fsm_34;
end else if ((ap_ST_st32_fsm_32 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st33_fsm_33;
end else if ((ap_ST_st31_fsm_31 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st32_fsm_32;
end else if ((ap_ST_st30_fsm_30 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st31_fsm_31;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st30_fsm_30;
end else if ((ap_ST_st28_fsm_28 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st29_fsm_29;
end else if ((ap_ST_st27_fsm_27 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st28_fsm_28;
end else if ((ap_ST_st26_fsm_26 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st27_fsm_27;
end else if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st26_fsm_26;
end else if ((ap_ST_st24_fsm_24 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st25_fsm_25;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st24_fsm_24;
end else if ((ap_ST_st22_fsm_22 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st23_fsm_23;
end else if ((ap_ST_st21_fsm_21 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st22_fsm_22;
end else if ((ap_ST_st20_fsm_20 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st21_fsm_21;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st20_fsm_20;
end else if ((ap_ST_st18_fsm_18 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st19_fsm_19;
end else if ((ap_ST_st17_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st18_fsm_18;
end else if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st17_fsm_17;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st16_fsm_16;
end else if ((ap_ST_st14_fsm_14 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st15_fsm_15;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st14_fsm_14;
end else if ((ap_ST_st12_fsm_12 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st13_fsm_13;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st12_fsm_12;
end else if ((ap_ST_st10_fsm_10 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st11_fsm_11;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st10_fsm_10;
end else if ((ap_ST_st8_fsm_8 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st9_fsm_9;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st8_fsm_8;
end else if ((ap_ST_st6_fsm_6 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st7_fsm_7;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st6_fsm_6;
end else if ((ap_ST_st4_fsm_4 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st5_fsm_5;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st4_fsm_4;
end else if ((ap_ST_st2_fsm_2 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st3_fsm_3;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st2_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_ST_st59_fsm_59 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// out1_ap_vld assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st18_fsm_18 == ap_CS_fsm)) begin
out1_ap_vld = ap_const_logic_1;
end else begin
out1_ap_vld = ap_const_logic_0;
end
end
/// out2_ap_vld assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
out2_ap_vld = ap_const_logic_1;
end else begin
out2_ap_vld = ap_const_logic_0;
end
end
/// out3_ap_vld assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
out3_ap_vld = ap_const_logic_1;
end else begin
out3_ap_vld = ap_const_logic_0;
end
end
/// out4_ap_vld assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
out4_ap_vld = ap_const_logic_1;
end else begin
out4_ap_vld = ap_const_logic_0;
end
end
assign grp_fu_100_ce = ap_const_logic_1;
assign grp_fu_100_p0 = inC;
assign grp_fu_100_p1 = inA;
assign grp_fu_79_ce = ap_const_logic_1;
assign grp_fu_79_p0 = ap_const_lv32_1;
assign grp_fu_79_p1 = inD;
assign grp_fu_86_ce = ap_const_logic_1;
assign grp_fu_86_p0 = inB;
assign grp_fu_86_p1 = inA;
assign grp_fu_93_ce = ap_const_logic_1;
assign grp_fu_93_p0 = inA;
assign grp_fu_93_p1 = inB;
assign out1 = grp_fu_93_p2;
assign out2 = grp_fu_86_p2;
assign out3 = grp_fu_100_p2;
assign out4 = grp_fu_79_p2;
endmodule //types_float_double
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is responsible for accepting 128/256 bit descriptors and
buffering them in descriptor FIFOs. Each bytelane of the descriptor
can be written to individually and writing ot the descriptor 'go' bit
commits the data into the FIFO. Reading that data out of the FIFO
occurs two cycles after the read is asserted as the FIFOs do not support
lookahead mode.
This block must keep local copies of per descriptor information like
the optional sequence number or interrupt masks. When parked mode
is set in the descriptor the same will transfer multiple times when
the descriptor FIFO only contains one descriptor (and this descriptor
will not be popped). Parked mode is useful for video frame buffering.
1.0 - The on-chip memory in the FIFOs are not inferred so there may
be some extra unused bits. In a later Quartus II release the
on-chip memory will be replaced with inferred memory.
1.1 - Shifted all descriptor registers into this block (from the dispatcher
block). Added breakout blocks responsible for re-packing the
information for use by each master.
1.2 - Added the read_early_done_enable bit to the breakout (for debug)
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module descriptor_buffers (
clk,
reset,
writedata,
write,
byteenable,
waitrequest,
read_command_valid,
read_command_ready,
read_command_data,
read_command_empty,
read_command_full,
read_command_used,
write_command_valid,
write_command_ready,
write_command_data,
write_command_empty,
write_command_full,
write_command_used,
stop_issuing_commands,
stop,
sw_reset,
sequence_number,
transfer_complete_IRQ_mask,
early_termination_IRQ_mask,
error_IRQ_mask
);
parameter MODE = 0;
parameter DATA_WIDTH = 256;
parameter BYTE_ENABLE_WIDTH = 32;
parameter FIFO_DEPTH = 128;
parameter FIFO_DEPTH_LOG2 = 7; // top level module can figure this out
input clk;
input reset;
input [DATA_WIDTH-1:0] writedata;
input write;
input [BYTE_ENABLE_WIDTH-1:0] byteenable;
output wire waitrequest;
output wire read_command_valid;
input read_command_ready;
output wire [255:0] read_command_data;
output wire read_command_empty;
output wire read_command_full;
output wire [FIFO_DEPTH_LOG2:0] read_command_used;
output wire write_command_valid;
input write_command_ready;
output wire [255:0] write_command_data;
output wire write_command_empty;
output wire write_command_full;
output wire [FIFO_DEPTH_LOG2:0] write_command_used;
input stop_issuing_commands;
input stop;
input sw_reset;
output wire [31:0] sequence_number;
output wire transfer_complete_IRQ_mask;
output wire early_termination_IRQ_mask;
output wire [7:0] error_IRQ_mask;
/* Internal wires and registers */
reg write_command_empty_d1;
reg write_command_empty_d2;
reg read_command_empty_d1;
reg read_command_empty_d2;
wire push_write_fifo;
wire pop_write_fifo;
wire push_read_fifo;
wire pop_read_fifo;
wire go_bit;
wire read_park;
wire read_park_enable; // park is enabled when read_park is enabled and the read FIFO is empty
wire write_park;
wire write_park_enable; // park is enabled when write_park is enabled and the write FIFO is empty
wire [DATA_WIDTH-1:0] write_fifo_output;
wire [DATA_WIDTH-1:0] read_fifo_output;
wire [15:0] write_sequence_number;
reg [15:0] write_sequence_number_d1;
wire [15:0] read_sequence_number;
reg [15:0] read_sequence_number_d1;
wire read_transfer_complete_IRQ_mask;
reg read_transfer_complete_IRQ_mask_d1;
wire write_transfer_complete_IRQ_mask;
reg write_transfer_complete_IRQ_mask_d1;
wire write_early_termination_IRQ_mask;
reg write_early_termination_IRQ_mask_d1;
wire [7:0] write_error_IRQ_mask;
reg [7:0] write_error_IRQ_mask_d1;
wire issue_write_descriptor; // one cycle strobe used to indicate when there is a valid write descriptor ready to be sent to the write master
wire issue_read_descriptor; // one cycle strobe used to indicate when there is a valid write descriptor ready to be sent to the write master
/* Unused signals that are provided for debug convenience */
wire [31:0] read_address;
wire [31:0] read_length;
wire [7:0] read_transmit_channel;
wire read_generate_sop;
wire read_generate_eop;
wire [7:0] read_burst_count;
wire [15:0] read_stride;
wire [7:0] read_transmit_error;
wire read_early_done_enable;
wire [31:0] write_address;
wire [31:0] write_length;
wire write_end_on_eop;
wire [7:0] write_burst_count;
wire [15:0] write_stride;
/************************************************* Registers *******************************************************/
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
write_sequence_number_d1 <= 0;
write_transfer_complete_IRQ_mask_d1 <= 0;
write_early_termination_IRQ_mask_d1 <= 0;
write_error_IRQ_mask_d1 <= 0;
end
else if (issue_write_descriptor) // if parked mode is enabled and there are no more descriptors buffered then this will not fire when the command is sent out
begin
write_sequence_number_d1 <= write_sequence_number;
write_transfer_complete_IRQ_mask_d1 <= write_transfer_complete_IRQ_mask;
write_early_termination_IRQ_mask_d1 <= write_early_termination_IRQ_mask;
write_error_IRQ_mask_d1 <= write_error_IRQ_mask;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
read_sequence_number_d1 <= 0;
read_transfer_complete_IRQ_mask_d1 <= 0;
end
else if (issue_read_descriptor) // if parked mode is enabled and there are no more descriptors buffered then this will not fire when the command is sent out
begin
read_sequence_number_d1 <= read_sequence_number;
read_transfer_complete_IRQ_mask_d1 <= read_transfer_complete_IRQ_mask;
end
end
// need to use a delayed valid signal since the commmand buffers have two cycles of latency
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
write_command_empty_d1 <= 0;
write_command_empty_d2 <= 0;
read_command_empty_d1 <= 0;
read_command_empty_d2 <= 0;
end
else
begin
write_command_empty_d1 <= write_command_empty;
write_command_empty_d2 <= write_command_empty_d1;
read_command_empty_d1 <= read_command_empty;
read_command_empty_d2 <= read_command_empty_d1;
end
end
/*********************************************** End Registers *****************************************************/
/****************************************** Module Instantiations **************************************************/
/* the write_signal_break module simply takes the output of the descriptor buffer and reformats the data
* to be sent in the command format needed by the master command port. If new features are added to the
* descriptor format then add it to this block. This block also provides the descriptor information
* using a naming convention isn't of bit indexes in a 256 bit wide command signal.
*/
write_signal_breakout the_write_signal_breakout (
.write_command_data_in (write_fifo_output),
.write_command_data_out (write_command_data),
.write_address (write_address),
.write_length (write_length),
.write_park (write_park),
.write_end_on_eop (write_end_on_eop),
.write_transfer_complete_IRQ_mask (write_transfer_complete_IRQ_mask),
.write_early_termination_IRQ_mask (write_early_termination_IRQ_mask),
.write_error_IRQ_mask (write_error_IRQ_mask),
.write_burst_count (write_burst_count),
.write_stride (write_stride),
.write_sequence_number (write_sequence_number),
.write_stop (stop),
.write_sw_reset (sw_reset)
);
defparam the_write_signal_breakout.DATA_WIDTH = DATA_WIDTH;
/* the read_signal_break module simply takes the output of the descriptor buffer and reformats the data
* to be sent in the command format needed by the master command port. If new features are added to the
* descriptor format then add it to this block. This block also provides the descriptor information
* using a naming convention isn't of bit indexes in a 256 bit wide command signal.
*/
read_signal_breakout the_read_signal_breakout (
.read_command_data_in (read_fifo_output),
.read_command_data_out (read_command_data),
.read_address (read_address),
.read_length (read_length),
.read_transmit_channel (read_transmit_channel),
.read_generate_sop (read_generate_sop),
.read_generate_eop (read_generate_eop),
.read_park (read_park),
.read_transfer_complete_IRQ_mask (read_transfer_complete_IRQ_mask),
.read_burst_count (read_burst_count),
.read_stride (read_stride),
.read_sequence_number (read_sequence_number),
.read_transmit_error (read_transmit_error),
.read_early_done_enable (read_early_done_enable),
.read_stop (stop),
.read_sw_reset (sw_reset)
);
defparam the_read_signal_breakout.DATA_WIDTH = DATA_WIDTH;
// Descriptor FIFO allows for each byte lane to be written to and the data is not committed to the FIFO until the 'push' signal is asserted.
// This differs from scfifo which commits the data any time the write signal is asserted.
fifo_with_byteenables the_read_command_FIFO (
.clk (clk),
.areset (reset),
.sreset (sw_reset),
.write_data (writedata),
.write_byteenables (byteenable),
.write (write),
.push (push_read_fifo),
.read_data (read_fifo_output),
.pop (pop_read_fifo),
.used (read_command_used), // this is a 'true used' signal with the full bit accounted for
.full (read_command_full),
.empty (read_command_empty)
);
defparam the_read_command_FIFO.DATA_WIDTH = DATA_WIDTH; // we are not actually going to use all these bits and byte lanes left unconnected at the output will get optimized away
defparam the_read_command_FIFO.FIFO_DEPTH = FIFO_DEPTH;
defparam the_read_command_FIFO.FIFO_DEPTH_LOG2 = FIFO_DEPTH_LOG2;
defparam the_read_command_FIFO.LATENCY = 2;
// Descriptor FIFO allows for each byte lane to be written to and the data is not committed to the FIFO until the 'push' signal is asserted.
// This differs from scfifo which commits the data any time the write signal is asserted.
fifo_with_byteenables the_write_command_FIFO (
.clk (clk),
.areset (reset),
.sreset (sw_reset),
.write_data (writedata),
.write_byteenables (byteenable),
.write (write),
.push (push_write_fifo),
.read_data (write_fifo_output),
.pop (pop_write_fifo),
.used (write_command_used), // this is a 'true used' signal with the full bit accounted for
.full (write_command_full),
.empty (write_command_empty)
);
defparam the_write_command_FIFO.DATA_WIDTH = DATA_WIDTH; // we are not actually going to use all these bits and byte lanes left unconnected at the output will get optimized away
defparam the_write_command_FIFO.FIFO_DEPTH = FIFO_DEPTH;
defparam the_write_command_FIFO.FIFO_DEPTH_LOG2 = FIFO_DEPTH_LOG2;
defparam the_write_command_FIFO.LATENCY = 2;
/**************************************** End Module Instantiations ************************************************/
/****************************************** Combinational Signals **************************************************/
generate // all unnecessary signals and drivers will be optimized away
if (MODE == 0) // MM-->MM
begin
assign waitrequest = (read_command_full == 1) | (write_command_full == 1);
// information for the CSR or response blocks to use
assign sequence_number = {write_sequence_number_d1, read_sequence_number_d1};
assign transfer_complete_IRQ_mask = write_transfer_complete_IRQ_mask_d1;
assign early_termination_IRQ_mask = 1'b0;
assign error_IRQ_mask = 8'h00;
// read buffer flow control
assign push_read_fifo = go_bit;
assign read_park_enable = (read_park == 1) & (read_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign read_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(read_command_empty == 0) & (read_command_empty_d1 == 0) & (read_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_read_descriptor = (read_command_valid == 1) & (read_command_ready == 1);
assign pop_read_fifo = (issue_read_descriptor == 1) & (read_park_enable == 0); // don't want to pop the fifo if we are in parked mode
// write buffer flow control
assign push_write_fifo = go_bit;
assign write_park_enable = (write_park == 1) & (write_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign write_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(write_command_empty == 0) & (write_command_empty_d1 == 0) & (write_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_write_descriptor = (write_command_valid == 1) & (write_command_ready == 1);
assign pop_write_fifo = (issue_write_descriptor == 1) & (write_park_enable == 0); // don't want to pop the fifo if we are in parked mode
end
else if (MODE == 1) // MM-->ST
begin
// information for the CSR or response blocks to use
assign sequence_number = {16'h0000, read_sequence_number_d1};
assign transfer_complete_IRQ_mask = read_transfer_complete_IRQ_mask_d1;
assign early_termination_IRQ_mask = 1'b0;
assign error_IRQ_mask = 8'h00;
assign waitrequest = (read_command_full == 1);
// read buffer flow control
assign push_read_fifo = go_bit;
assign read_park_enable = (read_park == 1) & (read_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign read_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(read_command_empty == 0) & (read_command_empty_d1 == 0) & (read_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_read_descriptor = (read_command_valid == 1) & (read_command_ready == 1);
assign pop_read_fifo = (issue_read_descriptor == 1) & (read_park_enable == 0); // don't want to pop the fifo if we are in parked mode
// write buffer flow control
assign push_write_fifo = 0;
assign write_park_enable = 0;
assign write_command_valid = 0;
assign issue_write_descriptor = 0;
assign pop_write_fifo = 0;
end
else // ST-->MM
begin
// information for the CSR or response blocks to use
assign sequence_number = {write_sequence_number_d1, 16'h0000};
assign transfer_complete_IRQ_mask = write_transfer_complete_IRQ_mask_d1;
assign early_termination_IRQ_mask = write_early_termination_IRQ_mask_d1;
assign error_IRQ_mask = write_error_IRQ_mask_d1;
assign waitrequest = (write_command_full == 1);
// read buffer flow control
assign push_read_fifo = 0;
assign read_park_enable = 0;
assign read_command_valid = 0;
assign issue_read_descriptor = 0;
assign pop_read_fifo = 0;
// write buffer flow control
assign push_write_fifo = go_bit;
assign write_park_enable = (write_park == 1) & (write_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign write_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(write_command_empty == 0) & (write_command_empty_d1 == 0) & (write_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_write_descriptor = (write_command_valid == 1) & (write_command_ready == 1);
assign pop_write_fifo = (issue_write_descriptor == 1) & (write_park_enable == 0); // don't want to pop the fifo if we are in parked mode
end
endgenerate
generate // go bit is in a different location depending on the width of the slave port
if (DATA_WIDTH == 256)
begin
assign go_bit = (writedata[255] == 1) & (write == 1) & (byteenable[31] == 1) & (waitrequest == 0);
end
else
begin
assign go_bit = (writedata[127] == 1) & (write == 1) & (byteenable[15] == 1) & (waitrequest == 0);
end
endgenerate
/**************************************** End Combinational Signals ************************************************/
endmodule
|
//======================================================================
//
// rosc_entropy_core.v
// -------------------
// Digitial ring oscillator based entropy generation core.
// This version implements 32 separate oscillators where each
// oscillator can be enabled or disabled.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module rosc_entropy_core(
input wire clk,
input wire reset_n,
input wire [31 : 0] opa,
input wire [31 : 0] opb,
input wire [31 : 0] rosc_en,
input wire [7 : 0] rosc_cycles,
output wire [31 : 0] raw_entropy,
output wire [31 : 0] rosc_outputs,
output wire [31 : 0] entropy_data,
output wire entropy_valid,
input wire entropy_ack,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Parameters.
//----------------------------------------------------------------
localparam ADDER_WIDTH = 2;
localparam DEBUG_DELAY = 32'h002c4b40;
localparam NUM_SHIFT_BITS = 8'h20;
localparam SAMPLE_CLK_CYCLES = 8'hff;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] ent_shift_reg;
reg [31 : 0] ent_shift_new;
reg ent_shift_we;
reg [31 : 0] entropy_reg;
reg entropy_we;
reg entropy_valid_reg;
reg entropy_valid_new;
reg entropy_valid_we;
reg bit_we_reg;
reg bit_we_new;
reg [7 : 0] bit_ctr_reg;
reg [7 : 0] bit_ctr_new;
reg bit_ctr_inc;
reg bit_ctr_we;
reg [7 : 0] sample_ctr_reg;
reg [7 : 0] sample_ctr_new;
reg [31 : 0] debug_delay_ctr_reg;
reg [31 : 0] debug_delay_ctr_new;
reg debug_delay_ctr_we;
reg [7 : 0] debug_reg;
reg debug_we;
reg debug_update_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] rosc_we;
// Ugly in-line Xilinx attribute to preserve the registers.
(* equivalent_register_removal = "no" *)
wire [31 : 0] rosc_dout;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign rosc_outputs = rosc_dout;
assign raw_entropy = ent_shift_reg;
assign entropy_data = entropy_reg;
assign entropy_valid = entropy_valid_reg;
assign debug = debug_reg;
//----------------------------------------------------------------
// module instantiations.
//
// 32 oscillators each ADDER_WIDTH wide. We want them to run
// as fast as possible to maximize differences over time.
// We also only sample the oscillators SAMPLE_CLK_CYCLES number
// of cycles.
//----------------------------------------------------------------
genvar i;
generate
for(i = 0 ; i < 32 ; i = i + 1)
begin: oscillators
rosc #(.WIDTH(ADDER_WIDTH)) rosc_array(.clk(clk),
.we(rosc_we[i]),
.reset_n(reset_n),
.opa(opa[(ADDER_WIDTH - 1) : 0]),
.opb(opb[(ADDER_WIDTH - 1) : 0]),
.dout(rosc_dout[i])
);
end
endgenerate
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
ent_shift_reg <= 32'h00000000;
entropy_reg <= 32'h00000000;
entropy_valid_reg <= 0;
bit_ctr_reg <= 8'h00;
sample_ctr_reg <= 8'h00;
debug_delay_ctr_reg <= 32'h00000000;
debug_reg <= 8'h00;
debug_update_reg <= 0;
end
else
begin
sample_ctr_reg <= sample_ctr_new;
debug_update_reg <= debug_update;
if (ent_shift_we)
begin
ent_shift_reg <= ent_shift_new;
end
if (bit_ctr_we)
begin
bit_ctr_reg <= bit_ctr_new;
end
if (entropy_we)
begin
entropy_reg <= ent_shift_reg;
end
if (entropy_valid_we)
begin
entropy_valid_reg <= entropy_valid_new;
end
if (debug_delay_ctr_we)
begin
debug_delay_ctr_reg <= debug_delay_ctr_new;
end
if (debug_we)
begin
debug_reg <= ent_shift_reg[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// debug_out
//
// Logic that updates the debug port.
//----------------------------------------------------------------
always @*
begin : debug_out
debug_delay_ctr_new = 32'h00000000;
debug_delay_ctr_we = 0;
debug_we = 0;
if (debug_update_reg)
begin
debug_delay_ctr_new = debug_delay_ctr_reg + 1'b1;
debug_delay_ctr_we = 1;
end
if (debug_delay_ctr_reg == DEBUG_DELAY)
begin
debug_delay_ctr_new = 32'h00000000;
debug_delay_ctr_we = 1;
debug_we = 1;
end
end
//----------------------------------------------------------------
// entropy_out
//
// Logic that implements the random output control. If we have
// added more than NUM_SHIFT_BITS we raise the entropy_valid flag.
// When we detect and ACK, the valid flag is dropped.
//----------------------------------------------------------------
always @*
begin : entropy_out
bit_ctr_new = 8'h00;
bit_ctr_we = 0;
entropy_we = 0;
entropy_valid_new = 0;
entropy_valid_we = 0;
if (bit_ctr_inc)
begin
if (bit_ctr_reg < NUM_SHIFT_BITS)
begin
bit_ctr_new = bit_ctr_reg + 1'b1;
bit_ctr_we = 1;
end
else
begin
entropy_we = 1;
entropy_valid_new = 1;
entropy_valid_we = 1;
end
end
if (entropy_ack)
begin
bit_ctr_new = 8'h00;
bit_ctr_we = 1;
entropy_valid_new = 0;
entropy_valid_we = 1;
end
end
//----------------------------------------------------------------
// entropy_gen
//
// Logic that implements the actual entropy bit value generator
// by XOR mixing the oscillator outputs. These outputs are
// sampled once every SAMPLE_CLK_CYCLES.
//----------------------------------------------------------------
always @*
begin : entropy_gen
reg ent_bit;
bit_ctr_inc = 0;
rosc_we = 32'h00000000;
ent_shift_we = 0;
ent_bit = ^rosc_dout;
ent_shift_new = {ent_shift_reg[30 : 0], ent_bit};
sample_ctr_new = sample_ctr_reg + 1'b1;
if (sample_ctr_reg == SAMPLE_CLK_CYCLES)
begin
sample_ctr_new = 8'h00;
bit_ctr_inc = 1;
rosc_we = rosc_en;
ent_shift_we = 1;
end
end
endmodule // rosc_entropy_core
//======================================================================
// EOF rosc_entropy_core.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_TB_V
`define SKY130_FD_SC_MS__OR4B_TB_V
/**
* or4b: 4-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ms__or4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_TB_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : ram_1p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Single Port Ram Model
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module ram_1p (
clk ,
cen_i ,
oen_i ,
wen_i ,
addr_i ,
data_i ,
data_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width = 32;
parameter Addr_Width = 8;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk; // clock input
input cen_i; // chip enable, low active
input oen_i; // data output enable, low active
input wen_i; // write enable, low active
input [Addr_Width-1:0] addr_i; // address input
input [Word_Width-1:0] data_i; // data input
output [Word_Width-1:0] data_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] data_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// mem write
always @(posedge clk) begin
if(!cen_i && !wen_i)
mem_array[addr_i] <= data_i;
end
// mem read
always @(posedge clk) begin
if (!cen_i && wen_i)
data_r <= mem_array[addr_i];
else
data_r <= 'bx;
end
assign data_o = oen_i ? 'bz : data_r;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TB_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TB_V
/**
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
* well on input buffer, no taps,
* double-row-height cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.v"
module top();
// Inputs are registered
reg A;
reg LOWLVPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
LOWLVPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 LOWLVPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 LOWLVPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 LOWLVPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 LOWLVPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 LOWLVPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell dut (.A(A), .LOWLVPWR(LOWLVPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TB_V
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
| Computes a division or square root for floating-point in recoded form.
| Multiple clock cycles are needed for each division or square-root operation,
| except possibly in special cases.
*----------------------------------------------------------------------------*/
module
divSqrtRecFNToRaw_small#(
parameter expWidth = 3, parameter sigWidth = 3, parameter options = 0
) (
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
input nReset,
input clock,
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
input [(`floatControlWidth - 1):0] control,
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
output inReady,
input inValid,
input sqrtOp,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input [2:0] roundingMode,
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
output outValid,
output sqrtOpOut,
output [2:0] roundingModeOut,
output invalidExc,
output infiniteExc,
output out_isNaN,
output out_isInf,
output out_isZero,
output out_sign,
output signed [(expWidth + 1):0] out_sExp,
output [(sigWidth + 2):0] out_sig
);
`include "HardFloat_localFuncs.vi"
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaNA_S, isInfA_S, isZeroA_S, signA_S;
wire signed [(expWidth + 1):0] sExpA_S;
wire [sigWidth:0] sigA_S;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_a(
a, isNaNA_S, isInfA_S, isZeroA_S, signA_S, sExpA_S, sigA_S);
wire isSigNaNA_S;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA_S);
wire isNaNB_S, isInfB_S, isZeroB_S, signB_S;
wire signed [(expWidth + 1):0] sExpB_S;
wire [sigWidth:0] sigB_S;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_b(
b, isNaNB_S, isInfB_S, isZeroB_S, signB_S, sExpB_S, sigB_S);
wire isSigNaNB_S;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB_S);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire notSigNaNIn_invalidExc_S_div =
(isZeroA_S && isZeroB_S) || (isInfA_S && isInfB_S);
wire notSigNaNIn_invalidExc_S_sqrt = !isNaNA_S && !isZeroA_S && signA_S;
wire majorExc_S =
sqrtOp ? isSigNaNA_S || notSigNaNIn_invalidExc_S_sqrt
: isSigNaNA_S || isSigNaNB_S || notSigNaNIn_invalidExc_S_div
|| (!isNaNA_S && !isInfA_S && isZeroB_S);
wire isNaN_S =
sqrtOp ? isNaNA_S || notSigNaNIn_invalidExc_S_sqrt
: isNaNA_S || isNaNB_S || notSigNaNIn_invalidExc_S_div;
`ifdef HardFloat_propagateNaNPayloads
wire signNaN_S;
wire [(sigWidth - 2):0] fractNaN_S;
propagateFloatNaN_divSqrt#(sigWidth)
propagateNaN(
control,
sqrtOp,
isNaNA_S,
signA_S,
sigA_S[(sigWidth - 2):0],
isNaNB_S,
signB_S,
sigB_S[(sigWidth - 2):0],
signNaN_S,
fractNaN_S
);
`endif
wire isInf_S = sqrtOp ? isInfA_S : isInfA_S || isZeroB_S;
wire isZero_S = sqrtOp ? isZeroA_S : isZeroA_S || isInfB_S;
wire sign_S = signA_S ^ (!sqrtOp && signB_S);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire specialCaseA_S = isNaNA_S || isInfA_S || isZeroA_S;
wire specialCaseB_S = isNaNB_S || isInfB_S || isZeroB_S;
wire normalCase_S_div = !specialCaseA_S && !specialCaseB_S;
wire normalCase_S_sqrt = !specialCaseA_S && !signA_S;
wire normalCase_S = sqrtOp ? normalCase_S_sqrt : normalCase_S_div;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire signed [(expWidth + 2):0] sExpQuot_S_div =
sExpA_S + {{3{sExpB_S[expWidth]}}, ~sExpB_S[(expWidth - 1):0]};
wire signed [(expWidth + 1):0] sSatExpQuot_S_div =
{(7<<(expWidth - 2) <= sExpQuot_S_div) ? 4'b0110
: sExpQuot_S_div[(expWidth + 1):(expWidth - 2)],
sExpQuot_S_div[(expWidth - 3): 0]};
wire evenSqrt_S = sqrtOp && !sExpA_S[0];
wire oddSqrt_S = sqrtOp && sExpA_S[0];
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [(clog2(sigWidth + 3) - 1):0] cycleNum;
reg sqrtOp_Z, majorExc_Z;
reg isNaN_Z, isInf_Z, isZero_Z, sign_Z;
reg signed [(expWidth + 1):0] sExp_Z;
reg [(sigWidth - 2):0] fractB_Z;
reg [2:0] roundingMode_Z;
/*------------------------------------------------------------------------
| (The most-significant and least-significant bits of 'rem_Z' are needed
| only for square roots.)
*------------------------------------------------------------------------*/
reg [(sigWidth + 1):0] rem_Z;
reg notZeroRem_Z;
reg [(sigWidth + 1):0] sigX_Z;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire idle = (cycleNum == 0);
assign inReady = (cycleNum <= 1);
wire entering = inReady && inValid;
wire entering_normalCase = entering && normalCase_S;
wire skipCycle2 = (cycleNum == 3) && sigX_Z[sigWidth + 1];
always @(negedge nReset, posedge clock) begin
if (!nReset) begin
cycleNum <= 0;
end else begin
if (!idle || inValid) begin
cycleNum <=
(entering && !normalCase_S ? 1 : 0)
| (entering_normalCase
? (sqrtOp ? (sExpA_S[0] ? sigWidth : sigWidth + 1)
: sigWidth + 2)
: 0)
| (!idle && !skipCycle2 ? cycleNum - 1 : 0)
| (!idle && skipCycle2 ? 1 : 0);
end
end
end
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
always @(posedge clock) begin
if (entering) begin
sqrtOp_Z <= sqrtOp;
majorExc_Z <= majorExc_S;
isNaN_Z <= isNaN_S;
isInf_Z <= isInf_S;
isZero_Z <= isZero_S;
`ifdef HardFloat_propagateNaNPayloads
sign_Z <= isNaN_S ? signNaN_S : sign_S;
`else
sign_Z <= sign_S;
`endif
end
if (entering_normalCase) begin
sExp_Z <=
sqrtOp ? (sExpA_S>>>1) + (1<<(expWidth - 1))
: sSatExpQuot_S_div;
roundingMode_Z <= roundingMode;
end
if (entering_normalCase && !sqrtOp) begin
fractB_Z <= sigB_S[(sigWidth - 2):0];
end
end
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [1:0] decHiSigA_S = sigA_S[(sigWidth - 1):(sigWidth - 2)] - 1;
wire [(sigWidth + 2):0] rem =
(inReady && !oddSqrt_S ? sigA_S<<1 : 0)
| (inReady && oddSqrt_S
? {decHiSigA_S, sigA_S[(sigWidth - 3):0], 3'b0} : 0)
| (!inReady ? rem_Z<<1 : 0);
wire [sigWidth:0] bitMask = ({{(sigWidth + 2){1'b0}}, 1'b1}<<cycleNum)>>2;
wire [(sigWidth + 1):0] trialTerm =
( inReady && !sqrtOp ? sigB_S<<1 : 0)
| ( inReady && evenSqrt_S ? 1<<sigWidth : 0)
| ( inReady && oddSqrt_S ? 5<<(sigWidth - 1) : 0)
| (!inReady && !sqrtOp_Z ? {1'b1, fractB_Z}<<1 : 0)
| (!inReady && sqrtOp_Z ? sigX_Z<<1 | bitMask : 0);
wire signed [(sigWidth + 3):0] trialRem = rem - trialTerm;
wire newBit = (0 <= trialRem);
always @(posedge clock) begin
if (entering_normalCase || (cycleNum > 2)) begin
rem_Z <= newBit ? trialRem : rem;
end
`ifdef HardFloat_propagateNaNPayloads
if (
(entering && isNaN_S) || entering_normalCase
|| (!inReady && newBit)
) begin
notZeroRem_Z <= (trialRem != 0);
sigX_Z <=
(inReady && isNaN_S ? {1'b1, fractNaN_S, 2'b00} : 0)
| (inReady && !isNaN_S && !sqrtOp ? newBit<<(sigWidth + 1) : 0)
| (inReady && !isNaN_S && sqrtOp ? 1<<sigWidth : 0)
| (inReady && !isNaN_S && oddSqrt_S
? newBit<<(sigWidth - 1) : 0)
| (!inReady ? sigX_Z | bitMask : 0);
end
`else
if (entering_normalCase || (!inReady && newBit)) begin
notZeroRem_Z <= (trialRem != 0);
sigX_Z <=
( inReady && !sqrtOp ? newBit<<(sigWidth + 1) : 0)
| ( inReady && sqrtOp ? 1<<sigWidth : 0)
| ( inReady && oddSqrt_S ? newBit<<(sigWidth - 1) : 0)
| (!inReady ? sigX_Z | bitMask : 0);
end
`endif
end
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
assign outValid = (cycleNum == 1);
assign sqrtOpOut = sqrtOp_Z;
assign roundingModeOut = roundingMode_Z;
assign invalidExc = majorExc_Z && isNaN_Z;
assign infiniteExc = majorExc_Z && !isNaN_Z;
assign out_isNaN = isNaN_Z;
assign out_isInf = isInf_Z;
assign out_isZero = isZero_Z;
assign out_sign = sign_Z;
assign out_sExp = sExp_Z;
assign out_sig = {sigX_Z, notZeroRem_Z};
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
divSqrtRecFN_small#(
parameter expWidth = 3, parameter sigWidth = 3, parameter options = 0
) (
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
input nReset,
input clock,
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
input [(`floatControlWidth - 1):0] control,
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
output inReady,
input inValid,
input sqrtOp,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input [2:0] roundingMode,
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
output outValid,
output sqrtOpOut,
output [(expWidth + sigWidth):0] out,
output [4:0] exceptionFlags
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
//wire sqrtOpOut;
wire [2:0] roundingModeOut;
wire invalidExc, infiniteExc, out_isNaN, out_isInf, out_isZero, out_sign;
wire signed [(expWidth + 1):0] out_sExp;
wire [(sigWidth + 2):0] out_sig;
divSqrtRecFNToRaw_small#(expWidth, sigWidth, options)
divSqrtRecFNToRaw(
nReset,
clock,
control,
inReady,
inValid,
sqrtOp,
a,
b,
roundingMode,
outValid,
sqrtOpOut,
roundingModeOut,
invalidExc,
infiniteExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
roundRawFNToRecFN#(expWidth, sigWidth, 0)
roundRawOut(
control,
invalidExc,
infiniteExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig,
roundingModeOut,
out,
exceptionFlags
);
endmodule
|
`timescale 10ns/1ps
module main(
input clk_pin_i,
input rst_pin_i,
output[7:0] led_o
);
// Logic analyzer part
// -------------------
// This block consists of ICON controller, with 2 submodules: logic analyzer
// (ILA) nad GPIO module (VIO). They use la_ctl0 and la_ctl1 busses
// respectively.
wire[35:0] la_ctl0;
wire[35:0] la_ctl1;
wire[31:0] la_data;
wire[7:0] la_trig;
wire la_trig_out;
wire[7:0] la_async_in = { 8'd0 };
wire[7:0] la_async_out;
wire[7:0] la_sync_in = { 8'd0 };
wire[7:0] la_sync_out;
chipscope_icon la_icon(
.CONTROL0(la_ctl0[35:0]),
.CONTROL1(la_ctl1[35:0]),
.CONTROL2(),
.CONTROL3()
);
chipscope_ila la_ila(
.CONTROL(la_ctl0[35:0]),
.CLK(clk_pin_i),
.DATA(la_data),
.TRIG0(la_trig),
.TRIG_OUT(la_trig_out)
);
chipscope_vio la_vio(
.CONTROL(la_ctl1[35:0]),
.CLK(clk_pin_i),
.ASYNC_IN(la_async_in[7:0]),
.ASYNC_OUT(la_async_out[7:0]),
.SYNC_IN(la_sync_in[7:0]),
.SYNC_OUT(la_sync_out[7:0])
);
`define G_FREQ 25000000
wire clk_i = clk_pin_i;
wire rst_i = rst_pin_i;
// Actual logic gets generated here.
reg[31:0] clkdiv_r = 0;
wire[31:0] clkdiv = (clkdiv_r[31:0] < `G_FREQ) ? (clkdiv_r[31:0] + 1) : 0;
wire led_change = clkdiv_r[31:0] == 0;
reg[3:0] cnt_r = 0;
wire[3:0] cnt = led_change ? cnt_r + 1 : cnt_r;
always @(posedge clk_i) begin
clkdiv_r <= rst_i ? 0 : clkdiv;
cnt_r <= rst_i ? 0 : cnt;
end
wire dna_dout;
wire dna_din;
reg[7:0] dna_cnt_r = 0;
wire dna_ready = dna_cnt_r[7:0] > 57;
wire[7:0] dna_cnt = !dna_ready ? dna_cnt_r[7:0] + 8'd1 : dna_cnt_r[7:0];
wire dna_read = dna_cnt_r[7:0] == 8'd0;
reg dna_read_r = 0;
wire dna_shift = ~dna_read && ~dna_ready;
reg[63:0] dna_reg_r = 64'd0;
wire[63:0] dna_reg_shifted = { dna_reg_r[62:0], (dna_dout === 1'b1) };
// DNA_PORT simulation block puts 1'b1 in the register and you see it while
// simulating. To get rid of that, we ignore gather data at start.
wire dna_start = dna_read_r && dna_shift; // start
wire dna_end = (dna_read | dna_shift) == 0; // finish
wire[63:0] dna_reg = (dna_start || dna_end) ? dna_reg_r : dna_reg_shifted;
initial begin
#1000;
$finish;
end
integer cycle_num = 0;
always @(posedge clk_i) begin
cycle_num <= cycle_num + 1;
dna_cnt_r <= rst_i ? 8'd0 : dna_cnt;
dna_reg_r <= rst_i ? 64'd0 : dna_reg;
dna_read_r <= rst_i ? 1'b0 : dna_read;
$display("%d %d dna_dout=%d dna_read:%d dna_read_r:%d dna_shift:%d dna_cnt_r=%x dna_reg_r=%x",
$time, cycle_num, dna_dout, dna_read, dna_read_r, dna_shift, dna_cnt_r, dna_reg_r);
end
DNA_PORT #(
.SIM_DNA_VALUE(57'habcdef12) // while picking 64-bit literal was easier
) dna (
.CLK(clk_i),
.DOUT(dna_dout),
.READ(dna_read),
.SHIFT(dna_shift),
.DIN(1'd0)
);
assign la_trig[7:0] = { cnt_r[3:0], 2'd0, rst_pin_i, clk_pin_i };
assign la_data[31:0] = { dna_reg_r };
assign led_o[7:0] = { cnt_r[3:0], la_sync_out[3:0] };
endmodule
|
module Rx(CLK,reset,cableReset_L,hardReset_L, message_received_for_Phy, CC_Busy, CC_Idle, Start, Unexpected_goodCRC, Tx_state_Machine, Data_from_I2C,
Tx_Message_Discarded,ALERT,RECEIVE_BYTE_COUNT, GoodCRCtoPhy, address, DataToReg);
localparam Rx_Idle = 4'b0000;
localparam Rx_Wait_For_Phy_Message = 4'b0001;
localparam Rx_Message_Discarded = 4'b0010;
localparam Rx_Send_GoodCRC = 4'b0100;
localparam Rx_Report_SOP = 4'b1000;
input wire RECEIVE_DETECT_I;
input wire CLK;
input wire reset;
input wire cableReset_L;
input wire hardReset_L;
input wire message_received_for_Phy;
input wire CC_Busy;
input wire CC_Idle;
input wire Start;
input Unexpected_goodCRC;
input Tx_state_Machine;
input wire [7:0] Data_from_I2C;
output reg Tx_Message_Discarded;
output reg [15:0] ALERT;
output reg [7:0] RECEIVE_BYTE_COUNT;
output reg GoodCRCtoPhy;
output reg [7:0] address;
output reg [7:0] DataToReg;
reg [7:0] next_address;
reg [7:0] next_RECEIVE_BYTE_COUNT;
reg next_GoodCRCtoPhy;
reg [7:0] next_DATA;
reg [15:0] next_ALERT_OUT;
reg next_Tx_Message_Discarded;
reg[3:0] state;
reg [3:0] next_state;
assign Rx_Reset = !cableReset_L | !hardReset_L;
//assign message_received_for_Phy = RECEIVE_DETECT_I && 8'h01;
assign Rx_Buffer_Overflow = ALERT[10];
//FlipFlops
always@(posedge CLK)
begin
if(~reset)
begin
state <= Rx_Idle;
Tx_Message_Discarded <= 0;
ALERT <= 16'h0000;
RECEIVE_BYTE_COUNT <= 8'h00;
GoodCRCtoPhy <= 0;
address <= 8'h00;
DataToReg <= 8'h00;
end
else
begin
state <= next_state;
Tx_Message_Discarded <= next_Tx_Message_Discarded;
ALERT <= next_ALERT_OUT;
RECEIVE_BYTE_COUNT <= next_RECEIVE_BYTE_COUNT;
GoodCRCtoPhy <= next_GoodCRCtoPhy ;
address <= next_address;
DataToReg <= next_DATA;
end
end
//Logica de estados.
always@(*)
begin
case(state)
Rx_Idle:
if(Rx_Reset || ~Start)
begin
next_state = Rx_Idle;
end
else
begin
next_state = Rx_Wait_For_Phy_Message;
end
Rx_Wait_For_Phy_Message:
begin
if(Rx_Buffer_Overflow)
begin
next_state = Rx_Wait_For_Phy_Message;
end
else
if(message_received_for_Phy)
next_state = Rx_Message_Discarded;
else
next_state = Rx_Wait_For_Phy_Message;
end
Rx_Message_Discarded:
begin
next_state = Unexpected_goodCRC ? Rx_Report_SOP : Rx_Send_GoodCRC ;
end
Rx_Send_GoodCRC:
begin
if(CC_Busy || CC_Idle)
begin
next_state = Rx_Wait_For_Phy_Message;
end else
begin
next_state = Rx_Report_SOP;
end
end
Rx_Report_SOP:
next_state = Rx_Wait_For_Phy_Message;
default:
next_state = state;
endcase
end
//Logica de Salidas.
always @(*)
begin
case(state)
Rx_Message_Discarded:
begin
if(Tx_state_Machine)
begin
next_Tx_Message_Discarded = 1;
next_ALERT_OUT = ALERT | 16'h0020;
end
end
Rx_Send_GoodCRC:
begin
next_GoodCRCtoPhy = 1;
end
Rx_Report_SOP:
begin
next_DATA = Data_from_I2C;
next_RECEIVE_BYTE_COUNT <= RECEIVE_BYTE_COUNT + 1;
next_address = RECEIVE_BYTE_COUNT + 8'h30;
if(RECEIVE_BYTE_COUNT == 31)
begin
next_ALERT_OUT = ALERT | 16'h0404;
next_RECEIVE_BYTE_COUNT <= 0;
end
else
begin
next_ALERT_OUT = ALERT | 16'h0004;
end
end
default:
begin
next_address = address;
next_ALERT_OUT = ALERT;
next_RECEIVE_BYTE_COUNT = RECEIVE_BYTE_COUNT;
next_GoodCRCtoPhy= GoodCRCtoPhy;
next_DATA = DataToReg;
next_Tx_Message_Discarded = Tx_Message_Discarded;
end
endcase
end
endmodule
|
// file regFileBoard.v
module regFileBoard(
input wire clock,
input wire clock_debug,
input wire reset,
input wire WriteEnable,
input wire [4:0] read_address_1,
input wire [4:0] read_address_2,
input wire [4:0] read_address_3,
input wire [31:0] write_data_in,
input wire [4:0] write_address,
input wire [4:0] read_address_debug,
output reg [31:0] data_out_1,
output reg [31:0] data_out_2,
output reg [31:0] data_out_3,
output reg [31:0] data_out_debug);
integer i;
//Array of 32 registers
reg [31:0] register[0:31];
initial begin
for(i=0;i<32;i=i+1)begin
register[i] = i;
end
end
//Write only on rising edge of clock and WriteEnable is high and reset if reset is high
always @(posedge clock) begin
if(WriteEnable &&(write_address != 5'b0))begin
register[write_address] <= write_data_in;
end
if(reset)begin
for(i=0;i<32;i=i+1)begin
register[i] = i;
end
end
end
always @(negedge clock) begin
data_out_1 = register[read_address_1];
data_out_2 = register[read_address_2];
data_out_debug = register[read_address_debug];
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_TB_V
`define SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_TB_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 SET = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 NOTIFIER = 1'b1;
#180 RESET = 1'b1;
#200 SET = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 NOTIFIER = 1'b0;
#300 RESET = 1'b0;
#320 SET = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SET = 1'b1;
#440 RESET = 1'b1;
#460 NOTIFIER = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SET = 1'bx;
#560 RESET = 1'bx;
#580 NOTIFIER = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dut (.SET(SET), .RESET(RESET), .D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_TB_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_solo_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "onchip_mem.hex";
output [ 31: 0] readdata;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 512,
the_altsyncram.numwords_a = 512,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 9;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__EDFXBP_FUNCTIONAL_PP_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_edf_p_pg/sky130_fd_sc_hs__u_edf_p_pg.v"
`celldefine
module sky130_fd_sc_hs__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_edf_p_pg `UNIT_DELAY u_edf_p_pg0 (buf_Q , D, CLK, DE, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_FUNCTIONAL_PP_V |
`timescale 1 ps / 1 ps
module Sobel (
input clk,
input rst,
output [31:0] data_fifo_out,
output data_valid_fifo_out,
input wire [8:0] usedw_fifo_out,
output wire[31:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire[3:0] ram_r_byteenable,
output wire ram_r_read,
input wire[31:0] ram_r_readdata,
output wire[5:0] ram_r_burstcount,
input start,
output endf,
input [31:0] base_add
);
parameter DATA_WIDTH=32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4;
parameter BURST_WIDTH_R = 6;
parameter FIFO_DEPTH = 256;
parameter FIFO_DEPTH_LOG2 = 8;
reg [18:0] pixel_counter;
reg [1:0] run;
always @ (posedge clk or posedge rst) begin
if (rst == 1) begin
run <= 0;
end else begin
if (start == 1) begin
run <= 1;
end else begin
if (pixel_counter == 0) begin
run <= 2;
end
if (endf == 1) begin
run <= 0;
end
end
end
end
always @ (posedge clk) begin
if (start == 1) begin
pixel_counter <= 384000;
end else begin
if (data_valid_fifo_out) begin
pixel_counter <= pixel_counter - 1;
end
end
end
wire [12:0] cache_valid_lines;
wire cache_free_line;
wire [7:0] cache_pixel;
Sobel_cache Sobel_cache_instance (
.clk(clk),
.rst(rst),
.start(start),
.base_add(base_add),
.rdaddress(add_pix_around),
.valid_lines(cache_valid_lines),
.free_line(cache_free_line),
.q(cache_pixel),
.ram_r_address(ram_r_address),
.ram_r_waitrequest(ram_r_waitrequest),
.ram_r_readdatavalid(ram_r_readdatavalid),
.ram_r_byteenable(ram_r_byteenable),
.ram_r_read(ram_r_read),
.ram_r_readdata(ram_r_readdata),
.ram_r_burstcount(ram_r_burstcount)
);
//*********************************************************************Sobel Implementation*************************************************************************
reg [3:0] stage;
wire go_sobel;
assign go_sobel = (stage == 0) & (pixel_counter > 0) & (run == 1) & (usedw_fifo_out < FIFO_DEPTH) & (cache_valid_lines > 13'd2399);
assign cache_free_line = (sobel_col == 799) & (stage == 2) & (sobel_line > 0) & (sobel_line < 478);
reg [9:0] sobel_col;
reg [8:0] sobel_line;
reg [13:0] add_main_pix;
always @(posedge clk) begin
if (start == 1) begin
sobel_col <= 0;
sobel_line <= 0;
add_main_pix <= 0;
end else begin
if (stage == 3) begin
if (sobel_col == 799) begin
sobel_line <= sobel_line + 1;
sobel_col <= 0;
end else begin
sobel_col <= sobel_col + 1;
end
if (add_main_pix == 7999) begin
add_main_pix <= 0;
end else begin
add_main_pix <= add_main_pix + 1;
end
end
end
end
reg [13:0] add_pix_around;
always @(posedge clk) begin
if (go_sobel == 1) begin
if (sobel_col == 0) begin
if (add_main_pix < 800) begin
add_pix_around <= 7200 + add_main_pix;
end else begin
add_pix_around <= add_main_pix - 800;
end
end else begin
if (add_main_pix < 800) begin
add_pix_around <= 7201 + add_main_pix;
end else begin
add_pix_around <= add_main_pix - 799;
end
end
end
if (stage == 1) begin
if (pending_reads != 4) begin
if (add_pix_around > 7199) begin
add_pix_around <= add_pix_around - 7200;
end else begin
add_pix_around <= add_pix_around + 800;
end
end
if (pending_reads == 4) begin
if (add_pix_around > 1598) begin
add_pix_around <= add_pix_around - 1599;
end else begin
add_pix_around <= add_pix_around + 6401;
end
end
end
end
reg [3:0] pending_reads;
always @(posedge clk) begin
if (go_sobel == 1) begin
if (sobel_col == 0) begin
pending_reads <= 6;
end else begin
pending_reads <= 3;
end
end else begin
if (stage == 1) begin
pending_reads <= pending_reads - 1;
end
end
end
reg [2:0] g_col;
reg [2:0] g_line;
always @(posedge clk) begin
if (start == 1) begin
g_col <= 1;
g_line <= 0;
end else begin
if (stage == 1) begin
if (g_line == 2) begin
g_col <= g_col + 1;
g_line <= 0;
end else begin
g_line <= g_line + 1;
end
end
if (stage == 3) begin
if (sobel_col == 799) begin
g_col <= 1;
g_line <= 0;
end else begin
g_col <= 2;
g_line <= 0;
end
end
end
end
wire jump_stage2;
assign jump_stage2 = (pending_reads == 0) & (stage == 1);
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
stage <= 0;
end else begin
if ((start == 1) | (stage == 8)) begin
stage <= 0;
end else begin
if (go_sobel == 1) begin
stage <= 1;
end
if (jump_stage2 == 1) begin
stage <= 2;
end else begin
if (stage > 1) begin
stage <= stage + 1;
end
end
end
end
end
wire out_bound;
assign out_bound = ((sobel_col + g_col - 2) == -1) | ((sobel_col + g_col - 2) == 800) | ((sobel_line + g_line - 2) == -1) | ((sobel_line + g_line - 2) == 480);
reg [10:0] gx;
reg [9:0] gx2;
reg [10:0] gy;
reg [9:0] gy2;
reg [20:0] gxgy;
reg [7:0] sobel_r;
wire[10:0] sqrt_r;
reg [7:0] g[0:2][0:2];
always @(posedge clk) begin
if (go_sobel == 1) begin
if (sobel_col != 0) begin
g[0][0] <= g[1][0];
g[0][1] <= g[1][1];
g[0][2] <= g[1][2];
g[1][0] <= g[2][0];
g[1][1] <= g[2][1];
g[1][2] <= g[2][2];
end else begin
g[0][0] <= 0;
g[0][1] <= 0;
g[0][2] <= 0;
end
end
if (stage == 1) begin
if (out_bound == 0) begin
g[g_col][g_line] <= cache_pixel;
end else begin
g[g_col][g_line] <= 0;
end
end
if (stage == 2) begin
gx <= g[0][0] + {g[0][1], 1'b0} + g[0][2];
gx2 <= g[2][0] + {g[2][1], 1'b0} + g[2][2];
gy <= g[0][0] + {g[1][0], 1'b0} + g[2][0];
gy2 <= g[0][2] + {g[1][2], 1'b0} + g[2][2];
end
if (stage == 3) begin
gx <= (gx > gx2)? gx - gx2 : gx2 - gx; // I need the absolute value
gy <= (gy > gy2)? gy - gy2 : gy2 - gy; //
end
if (stage == 4) begin
gxgy <= gx + gy;
end
if (stage == 5) begin
sobel_r <= gxgy > 255? 255 : gxgy;
end
if (stage == 7) begin
sobel_r <= 255 - sobel_r;
end
end
//------------------------------------------------------------------------------------------------------------------------------------------------------------------
assign data_fifo_out = {8'd0, {3{sobel_r}}};
assign data_valid_fifo_out = (run == 1) & (stage == 8);
assign endf = (run == 2);
endmodule
|
(* src = "../../verilog/slowadt7410.v:1", top = 1 *)
module SlowADT7410 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/slowadt7410.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/slowadt7410.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/slowadt7410.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/slowadt7410.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_ReceiveSend_n", src = "../../verilog/slowadt7410.v:11" *)
output I2C_ReceiveSend_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_ReadCount", src = "../../verilog/slowadt7410.v:13" *)
output[7:0] I2C_ReadCount_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_StartProcess", src = "../../verilog/slowadt7410.v:15" *)
output I2C_StartProcess_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Busy", src = "../../verilog/slowadt7410.v:17" *)
input I2C_Busy_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOReadNext", src = "../../verilog/slowadt7410.v:19" *)
output I2C_FIFOReadNext_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOWrite", src = "../../verilog/slowadt7410.v:21" *)
output I2C_FIFOWrite_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataIn", src = "../../verilog/slowadt7410.v:23" *)
output[7:0] I2C_Data_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataOut", src = "../../verilog/slowadt7410.v:25" *)
input[7:0] I2C_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Error", src = "../../verilog/slowadt7410.v:27" *)
input I2C_Error_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPresetH_i", src = "../../verilog/slowadt7410.v:29" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPresetL_i", src = "../../verilog/slowadt7410.v:31" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/slowadt7410.v:33" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/slowadt7410.v:35" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Word", intersynth_param = "WaitCounterPresetH_i", src = "../../verilog/slowadt7410.v:37" *)
input[15:0] WaitCounterPresetH_i,
(* intersynth_conntype = "Word", intersynth_param = "WaitCounterPresetL_i", src = "../../verilog/slowadt7410.v:39" *)
input[15:0] WaitCounterPresetL_i
);
wire \$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.Overflow_s ;
wire \$techmap\I2CFSM_1.$procmux$1156_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1168_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1169_CMP ;
wire [7:0] \$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.Overflow_s ;
(* src = "../../verilog/i2cfsm.v:10" *)
wire [7:0] \I2CFSM_1.Byte0_o ;
(* src = "../../verilog/i2cfsm.v:11" *)
wire [7:0] \I2CFSM_1.Byte1_o ;
(* src = "../../verilog/i2cfsm.v:8" *)
wire \I2CFSM_1.Done_o ;
(* src = "../../verilog/i2cfsm.v:9" *)
wire \I2CFSM_1.Error_o ;
(* src = "../../verilog/i2cfsm.v:78" *)
wire \I2CFSM_1.I2C_FSM_TimerEnable ;
(* src = "../../verilog/i2cfsm.v:76" *)
wire \I2CFSM_1.I2C_FSM_TimerOvfl ;
(* src = "../../verilog/i2cfsm.v:77" *)
wire \I2CFSM_1.I2C_FSM_TimerPreset ;
(* src = "../../verilog/i2cfsm.v:80" *)
wire \I2CFSM_1.I2C_FSM_Wr0 ;
(* src = "../../verilog/i2cfsm.v:79" *)
wire \I2CFSM_1.I2C_FSM_Wr1 ;
(* src = "../../verilog/i2cfsm.v:7" *)
wire \I2CFSM_1.Start_i ;
(* src = "../../verilog/sensorfsm.v:42" *)
wire [15:0] \SensorFSM_1.AbsDiffResult ;
(* src = "../../verilog/sensorfsm.v:36" *)
wire \SensorFSM_1.SensorFSM_StoreNewValue ;
(* src = "../../verilog/sensorfsm.v:34" *)
wire \SensorFSM_1.SensorFSM_TimerEnable ;
(* src = "../../verilog/sensorfsm.v:32" *)
wire \SensorFSM_1.SensorFSM_TimerOvfl ;
(* src = "../../verilog/sensorfsm.v:33" *)
wire \SensorFSM_1.SensorFSM_TimerPreset ;
(* src = "../../verilog/sensorfsm.v:40" *)
wire [15:0] \SensorFSM_1.SensorValue ;
wire I2CFSM_1_Out14_s;
wire I2CFSM_1_CfgMode_s;
wire I2CFSM_1_CfgClk_s;
wire I2CFSM_1_CfgShift_s;
wire I2CFSM_1_CfgDataIn_s;
wire I2CFSM_1_CfgDataOut_s;
wire SensorFSM_1_Out5_s;
wire SensorFSM_1_Out6_s;
wire SensorFSM_1_Out7_s;
wire SensorFSM_1_Out8_s;
wire SensorFSM_1_Out9_s;
wire SensorFSM_1_CfgMode_s;
wire SensorFSM_1_CfgClk_s;
wire SensorFSM_1_CfgShift_s;
wire SensorFSM_1_CfgDataIn_s;
wire SensorFSM_1_CfgDataOut_s;
Byte2Word \$extract$\Byte2Word$2915 (
.H_i(\I2CFSM_1.Byte1_o ),
.L_i(\I2CFSM_1.Byte0_o ),
.Y_o(\SensorFSM_1.SensorValue )
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2910 (
.A_i(8'b00000000),
.B_i(8'b00000010),
.S_i(I2C_ReceiveSend_n_o),
.Y_o(I2C_ReadCount_o)
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2911 (
.A_i(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ),
.B_i(8'b00000011),
.S_i(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Y_o(I2C_Data_o)
);
ByteMuxQuad \$techmap\I2CFSM_1.$extract$\ByteMuxQuad$2909 (
.A_i(8'b00000000),
.B_i(8'b10010001),
.C_i(8'b10010000),
.D_i(8'b00100000),
.SAB_i(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.SC_i(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ),
.SD_i(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Y_o(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y )
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2906 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr0 ),
.Q_o(\I2CFSM_1.Byte0_o ),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2907 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr1 ),
.Q_o(\I2CFSM_1.Byte1_o ),
.Reset_n_i(Reset_n_i)
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DH_s ),
.DL_o(\$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DL_s ),
.Direction_i(1'b1),
.Enable_i(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Overflow_o(\$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.Overflow_s ),
.PresetValH_i(WaitCounterPresetH_i),
.PresetValL_i(WaitCounterPresetL_i),
.Preset_i(\I2CFSM_1.I2C_FSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\I2CFSM_1.I2C_FSM_TimerOvfl )
);
I2CFSM I2CFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(I2C_Busy_i),
.In1_i(I2C_Error_i),
.In2_i(\I2CFSM_1.I2C_FSM_TimerOvfl ),
.In3_i(\I2CFSM_1.Start_i ),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.Out0_o(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.Out1_o(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Out2_o(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Out3_o(\I2CFSM_1.Done_o ),
.Out4_o(\I2CFSM_1.I2C_FSM_Wr0 ),
.Out5_o(I2C_ReceiveSend_n_o),
.Out6_o(I2C_StartProcess_o),
.Out7_o(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ),
.Out8_o(\I2CFSM_1.Error_o ),
.Out9_o(\I2CFSM_1.I2C_FSM_Wr1 ),
.Out10_o(I2C_FIFOReadNext_o),
.Out11_o(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Out12_o(\I2CFSM_1.I2C_FSM_TimerPreset ),
.Out13_o(I2C_FIFOWrite_o),
.Out14_o(I2CFSM_1_Out14_s),
.CfgMode_i(I2CFSM_1_CfgMode_s),
.CfgClk_i(I2CFSM_1_CfgClk_s),
.CfgShift_i(I2CFSM_1_CfgShift_s),
.CfgDataIn_i(I2CFSM_1_CfgDataIn_s),
.CfgDataOut_o(I2CFSM_1_CfgDataOut_s)
);
AbsDiff \$techmap\SensorFSM_1.$extract$\AbsDiff$2904 (
.A_i(\SensorFSM_1.SensorValue ),
.B_i(SensorValue_o),
.D_o(\SensorFSM_1.AbsDiffResult )
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.ThisAddSubCmp (
.A_i(\SensorFSM_1.AbsDiffResult ),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ),
.D_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ),
.Sign_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ),
.Zero_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s )
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DH_s ),
.DL_o(\$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DL_s ),
.Direction_i(1'b1),
.Enable_i(\SensorFSM_1.SensorFSM_TimerEnable ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.Overflow_s ),
.PresetValH_i(PeriodCounterPresetH_i),
.PresetValL_i(PeriodCounterPresetL_i),
.Preset_i(\SensorFSM_1.SensorFSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\SensorFSM_1.SensorFSM_TimerOvfl )
);
WordRegister \$techmap\SensorFSM_1.$extract$\WordRegister$2905 (
.Clk_i(Clk_i),
.D_i(\SensorFSM_1.SensorValue ),
.Enable_i(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
SensorFSM SensorFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(Enable_i),
.In1_i(\I2CFSM_1.Done_o ),
.In2_i(\I2CFSM_1.Error_o ),
.In3_i(\SensorFSM_1.SensorFSM_TimerOvfl ),
.In4_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ),
.In5_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s ),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(\I2CFSM_1.Start_i ),
.Out1_o(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Out2_o(CpuIntr_o),
.Out3_o(\SensorFSM_1.SensorFSM_TimerEnable ),
.Out4_o(\SensorFSM_1.SensorFSM_TimerPreset ),
.Out5_o(SensorFSM_1_Out5_s),
.Out6_o(SensorFSM_1_Out6_s),
.Out7_o(SensorFSM_1_Out7_s),
.Out8_o(SensorFSM_1_Out8_s),
.Out9_o(SensorFSM_1_Out9_s),
.CfgMode_i(SensorFSM_1_CfgMode_s),
.CfgClk_i(SensorFSM_1_CfgClk_s),
.CfgShift_i(SensorFSM_1_CfgShift_s),
.CfgDataIn_i(SensorFSM_1_CfgDataIn_s),
.CfgDataOut_o(SensorFSM_1_CfgDataOut_s)
);
assign I2CFSM_1_CfgMode_s = 1'b0;
assign I2CFSM_1_CfgClk_s = 1'b0;
assign I2CFSM_1_CfgShift_s = 1'b0;
assign I2CFSM_1_CfgDataIn_s = 1'b0;
assign SensorFSM_1_CfgMode_s = 1'b0;
assign SensorFSM_1_CfgClk_s = 1'b0;
assign SensorFSM_1_CfgShift_s = 1'b0;
assign SensorFSM_1_CfgDataIn_s = 1'b0;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp_maca_l.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of PCX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp_maca_l(/*AUTOARG*/
// Outputs
data_out_px_l, scan_out, shiftenable_buf,
// Inputs
arb_pcxdp_qsel1_pa, arb_pcxdp_qsel0_pa, arb_pcxdp_grant_pa,
arb_pcxdp_shift_px, arb_pcxdp_q0_hold_pa, src_pcx_data_pa, rclk,
scan_in, shiftenable
);
output [129:0] data_out_px_l; // pcx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_pcxdp_qsel1_pa; // queue write sel
input arb_pcxdp_qsel0_pa; // queue write sel
input arb_pcxdp_grant_pa;//grant signal
input arb_pcxdp_shift_px;//grant signal
input arb_pcxdp_q0_hold_pa;//grant signal
input [129:0] src_pcx_data_pa; // spache to pcx data
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_px;
wire [129:0] q0_datain_pa;
wire [129:0] q1_dataout, q0_dataout;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_pcxdp_q0_hold_pa),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_pcxdp_qsel1_pa),
.tmb_l(se_l));
// Latch and drive grant signal
dff_s #(1) dff_pcx_grin_r(
.din (arb_pcxdp_grant_pa),
.q (grant_px),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(130) dff_pcx_datain_q1(
.din (src_pcx_data_pa[129:0]),
.q (q1_dataout[129:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
assign q0_datain_pa[129:0] =
(arb_pcxdp_qsel0_pa ? src_pcx_data_pa[129:0] : 130'd0) |
(arb_pcxdp_shift_px ? q1_dataout[129:0] : 130'd0) ;
dff_s #(130) dff_pcx_datain_q0(
.din (q0_datain_pa[129:0]),
.q (q0_dataout[129:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_out_px_l[129:0] = ~(grant_px ? q0_dataout[129:0]:130'd0);
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_debug_if.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core debug interface. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2001/12/02 ////
//// (See log for the revision history) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.3 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.2 2001/12/12 22:17:30 gorban
// some synthesis bugs fixed
//
// Revision 1.1 2001/12/04 21:14:16 gorban
// committed the debug interface file
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_debug_if (/*AUTOARG*/
// Outputs
wb_dat32_o,
// Inputs
wb_adr_i, ier, iir, fcr, mcr, lcr, msr,
lsr, rf_count, tf_count, tstate, rstate
) ;
input [`UART_ADDR_WIDTH-1:0] wb_adr_i;
output [31:0] wb_dat32_o;
input [3:0] ier;
input [3:0] iir;
input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
input [4:0] mcr;
input [7:0] lcr;
input [7:0] msr;
input [7:0] lsr;
input [`UART_FIFO_COUNTER_W-1:0] rf_count;
input [`UART_FIFO_COUNTER_W-1:0] tf_count;
input [2:0] tstate;
input [3:0] rstate;
wire [`UART_ADDR_WIDTH-1:0] wb_adr_i;
reg [31:0] wb_dat32_o;
always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr
or rf_count or rstate or tf_count or tstate or wb_adr_i)
case (wb_adr_i)
// 8 + 8 + 4 + 4 + 8
5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr};
// 5 + 2 + 5 + 4 + 5 + 3
5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};
default: wb_dat32_o = 0;
endcase // case(wb_adr_i)
endmodule // uart_debug_if
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ae
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ae.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_ae.v,v $
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ae
//
// No user `defines in this module
module ent_ae
//
// Generated Module inst_ae
//
(
port_ae_2, // Use internally test2, no port generated
port_ae_5, // Bus, single bits go to outside
port_ae_6, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_i_ae, // Input Bus
sig_o_ae // Output Bus
);
// Generated Module Inputs:
input [4:0] port_ae_2;
input [3:0] port_ae_5;
input [3:0] port_ae_6;
input [5:0] sig_07;
input [8:2] sig_08;
input [6:0] sig_i_ae;
// Generated Module Outputs:
output [7:0] sig_o_ae;
// Generated Wires:
wire [4:0] port_ae_2;
wire [3:0] port_ae_5;
wire [3:0] port_ae_6;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [6:0] sig_i_ae;
wire [7:0] sig_o_ae;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ae
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// part of NeoGS project
//
// (c) NedoPC 2007-2019
module chan_ctrl
(
input wire clk, // 24.0 MHz
input wire rst_n,
// memory interface
output reg [ 6:0] rd_addr,
input wire [31:0] rd_data,
//
output reg [ 6:0] wr_addr,
output wire [31:0] wr_data,
output reg wr_stb,
// 37500 Hz period strobe (1-cycle strobe)
input wire sync_stb,
// channel enables
input wire [31:0] ch_enas,
// output data
output reg [ 7:0] out_data,
output reg out_stb_addr, // strobes address sequence (addrhi/mid/lo)
output reg out_stb_mix // strobes mix sequence (frac/vl/vr)
// sequence: addrhi, addrmid, addrlo; frac, vl, vr (6 bytes)
);
reg [ 5:0] curr_ch; // current channel number
wire stop = curr_ch[5];
// channel fetch state machine
reg [3:0] st;
reg [3:0] next_st;
// channel enable
wire ch_ena = ch_enas[curr_ch[4:0]];
// offset storage
reg [31:0] offset;
reg off_cy; // extra carry [32th bit]
// offset>=size flag
reg oversize;
// volumes storage
reg [5:0] vol_left;
reg [5:0] vol_right;
// miscellaneous
reg loopena;
reg surround;
// base address
reg [21:0] base;
// emit control
reg [1:0] addr_emit;
///////////////////////
// states definition //
///////////////////////
localparam ST_BEGIN = 4'd0;
localparam ST_GETOFFS = 4'd1; // when offset value arrives
localparam ST_GETADDVOL = 4'd2; // whed add and volumes arrive
localparam ST_GETSIZE = 4'd3; // size and part of base address arrive
localparam ST_GETLOOP = 4'd4; // when loop and last part of base address arrive
localparam ST_SAVEOFFS = 4'd5;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
localparam ST_NEXT = 4'd14;
localparam ST_WAIT = 4'd15;
always @(posedge clk)
if( st==ST_WAIT )
curr_ch[5:0] <= 6'd0;
else if( st==ST_NEXT )
curr_ch[5:0] <= curr_ch[5:0] + 6'd1;
always @(posedge clk, negedge rst_n)
if( !rst_n )
st <= ST_WAIT;
else
st <= next_st;
//
always @*
case( st )
//////////////////////////////////////////////////////////////////////
ST_BEGIN:
if( stop )
next_st = ST_WAIT;
else if( !ch_ena )
next_st = ST_NEXT;
else
next_st = ST_GETOFFS;
///////////////////////////////////////////////////////////////////////
ST_GETOFFS:
next_st = ST_GETADDVOL;
///////////////////////////////////////////////////////////////////////
ST_GETADDVOL:
next_st = ST_GETSIZE;
///////////////////////////////////////////////////////////////////////
ST_GETSIZE:
next_st = ST_GETLOOP;
///////////////////////////////////////////////////////////////////////
ST_GETLOOP:
next_st = ST_SAVEOFFS;
///////////////////////////////////////////////////////////////////////
ST_SAVEOFFS:
next_st = ST_NEXT;
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ST_NEXT:
next_st = ST_BEGIN;
///////////////////////////////////////////////////////////////////////
ST_WAIT:
if( sync_stb )
next_st = ST_BEGIN;
else
next_st = ST_WAIT;
////////////////////////////////////////////////
///////////////////////
default: next_st = ST_WAIT;
///////////////////////////////////////////////////////////////////////
endcase
// state memory address control
always @*
rd_addr[6:2] <= curr_ch[4:0];
always @*
wr_addr[6:2] <= curr_ch[4:0];
always @(posedge clk)
wr_addr[1:0] <= 2'd0;
//
always @(posedge clk)
if( st==ST_NEXT || st==ST_WAIT )
begin
rd_addr[1:0] <= 2'd0;
end
else if( st==ST_BEGIN || st==ST_GETOFFS || st==ST_GETADDVOL )
begin
rd_addr[1:0] <= rd_addr[1:0] + 2'd1;
end
// offset register control
always @(posedge clk)
if( st==ST_GETOFFS )
offset <= rd_data;
else if( st==ST_GETADDVOL )
{off_cy, offset} <= {1'b0, offset} + {1'b0, 14'd0, rd_data[31:14]};
else if( st==ST_GETLOOP )
offset[31:12] <= oversize ? (offset[31:12]+rd_data[27:8]) : offset[31:12]; // TODO: or maybe rd_data & {20{oversize}} ?
// offset overflow control
always @(posedge clk)
if( st==ST_GETSIZE )
oversize <= ( {off_cy,offset[31:12]} >= {1'b0, rd_data[27:8]} );
// offset writeback
always @(posedge clk)
wr_stb <= st==ST_SAVEOFFS;
//
assign wr_data = offset;
// volumes and miscellaneous
always @(posedge clk)
if( st==ST_GETADDVOL )
begin
vol_left <= rd_data[11:6];
vol_right <= rd_data[ 5:0];
loopena <= rd_data[13];
surround <= rd_data[12];
end
// base address calc
always @(posedge clk)
if( st==ST_GETSIZE )
base[15:8] <= rd_data[7:0];
else if( st==ST_GETLOOP )
base[21:16] <= rd_data[5:0];
else if( st==ST_SAVEOFFS )
begin
base[7:0] <= offset[19:12];
base[21:8] <= base[21:8] + {2'd0,offset[31:20]};
end
// emitting data to fifos
always @(posedge clk, negedge rst_n)
if( !rst_n )
addr_emit <= 2'd0;
else
addr_emit[1:0] <= {addr_emit[0], st==ST_NEXT};
//
always @(posedge clk)
if( st==ST_GETSIZE )
out_data <= offset[11:4];
else if( st==ST_GETLOOP )
out_data <= {2'd0, vol_left[5:0]};
else if( st==ST_SAVEOFFS )
out_data <= {2'd0, vol_right[5:0] ^ {6{surround}}};
else if( st==ST_NEXT )
out_data <= {2'd0, base[21:16]};
else if( addr_emit[0] )
out_data <= base[15:8];
else
out_data <= base[7:0];
//
always @(posedge clk, negedge rst_n)
if( !rst_n )
out_stb_mix <= 1'b0;
else
out_stb_mix <= (st==ST_GETSIZE) ||
(st==ST_GETLOOP) ||
(st==ST_SAVEOFFS) ;
//
always @(posedge clk, negedge rst_n)
if( !rst_n )
out_stb_addr <= 1'b0;
else
out_stb_addr <= (st==ST_NEXT) || addr_emit;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 160;
localparam integer DOUT_N = 160;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [159:0] din, output [159:0] dout);
my_PLL
#(
.LOC("PLL_X0Y10")
)
inst_0 (
.clk(clk),
.din(din[ 0 +: 2]),
.dout(dout[ 0 +: 7])
);
endmodule
// ---------------------------------------------------------------------
module my_PLL (input clk, input [1:0] din, output [6:0] dout);
parameter LOC = "";
(* LOC=LOC *)
PLLE4_BASE #(
.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB
.CLKIN_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(1), // Divide amount for CLKOUT0
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0
.CLKOUT1_DIVIDE(1), // Divide amount for CLKOUT1
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT1
.CLKOUTPHY_MODE("VCO_2X"), // Frequency of the CLKOUTPHY
.DIVCLK_DIVIDE(1), // Master division value
.IS_CLKFBIN_INVERTED(1'b0), // Optional inversion for CLKFBIN
.IS_CLKIN_INVERTED(1'b0), // Optional inversion for CLKIN
.IS_PWRDWN_INVERTED(1'b0), // Optional inversion for PWRDWN
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
.REF_JITTER(0.0), // Reference input jitter in UI
.STARTUP_WAIT("FALSE") // Delays DONE until PLL is locked
)
PLLE4_BASE_inst (
.CLKFBOUT(dout[0]), // 1-bit output: Feedback clock
.CLKOUT0(dout[1]), // 1-bit output: General Clock output
.CLKOUT0B(dout[2]), // 1-bit output: Inverted CLKOUT0
.CLKOUT1(dout[3]), // 1-bit output: General Clock output
.CLKOUT1B(dout[4]), // 1-bit output: Inverted CLKOUT1
.CLKOUTPHY(), // 1-bit output: Bitslice clock
.LOCKED(dout[6]), // 1-bit output: LOCK
.CLKFBIN(), // 1-bit input: Feedback clock
.CLKIN(clk), // 1-bit input: Input clock
.CLKOUTPHYEN(1'b1), // 1-bit input: CLKOUTPHY enable
.PWRDWN(din[0]), // 1-bit input: Power-down
.RST(din[1]) // 1-bit input: Reset
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NOR4_BEHAVIORAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4 (
VPWR,
VGND,
Y ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4_BEHAVIORAL_PP_V |
module fifo_128_8(
input wire i_clk,
input wire i_rst_n,
input wire i_slv_valid,
output wire o_slv_rdy,
input wire [63:0] i_slv_data,
output reg [7:0] o_mst_data,
output wire o_mst_valid,
input i_mst_rdy
);
reg [63:0] mem [0:15];
reg [3:0] wr_addr;
reg [6:0] rd_addr;
reg [7:0] data_count;
assign o_mst_valid = (data_count > 0) ? 1'b1 : 1'b0;
assign o_slv_rdy = (data_count < 120) ? 1'b1 : 1'b0;
assign valid_wr = i_slv_valid & o_slv_rdy;
assign valid_rd = o_mst_valid & i_mst_rdy;
always @(posedge i_clk)
begin
if(!i_rst_n)
begin
wr_addr <= 0;
end
else
begin
if(valid_wr)
begin
mem[wr_addr] <= i_slv_data;
wr_addr <= wr_addr + 1;
end
end
end
always @(posedge i_clk)
begin
if(!i_rst_n)
begin
rd_addr <= 0;
end
else
begin
if(valid_rd)
begin
rd_addr <= rd_addr + 1'b1;
end
end
end
always@(*)
begin
case(rd_addr[2:0])
0:begin
o_mst_data <= mem[rd_addr[6:3]][7:0];
end
1:begin
o_mst_data <= mem[rd_addr[6:3]][15:8];
end
2:begin
o_mst_data <= mem[rd_addr[6:3]][23:16];
end
3:begin
o_mst_data <= mem[rd_addr[6:3]][31:24];
end
4:begin
o_mst_data <= mem[rd_addr[6:3]][39:32];
end
5:begin
o_mst_data <= mem[rd_addr[6:3]][47:40];
end
6:begin
o_mst_data <= mem[rd_addr[6:3]][55:48];
end
7:begin
o_mst_data <= mem[rd_addr[6:3]][63:56];
end
endcase
end
always @(posedge i_clk)
begin
if(!i_rst_n)
begin
data_count <= 0;
end
else
begin
if(valid_wr & !valid_rd)
data_count <= data_count + 8;
else if(!valid_wr & valid_rd)
data_count <= data_count - 1'b1;
else if(valid_wr & valid_rd)
data_count <= data_count + 7;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_sync_header.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp
//
//-----------------------------------------------------------------------------
`include "sys.h"
module ctu_sync_header (/*AUTOARG*/
// Outputs
ctu_dram_tx_sync_early, jbus_rx_sync, jbus_tx_sync, so,
// Inputs
cmp_clk, cmp_gclk, ctu_dram_tx_sync, ctu_jbus_rx_sync,
ctu_jbus_tx_sync, se, si, start_clk_early_jl
);
// Beginning of automatic inputs (from unused autoinst inputs)
input cmp_clk; // To u_ctu_cluster_header_sync of cluster_header_sync.v, ...
input cmp_gclk; // To u_ctu_dram_tx_sync_dly1 of dff_ns.v, ...
input ctu_dram_tx_sync; // To u_ctu_dram_tx_sync_dly1 of dff_ns.v
input ctu_jbus_rx_sync; // To u_ctu_jbus_rx_sync_dly1 of dff_ns.v
input ctu_jbus_tx_sync; // To u_ctu_jbus_tx_sync_dly1 of dff_ns.v
input se; // To u_ctu_cluster_header_sync of cluster_header_sync.v
input si; // To u_ctu_cluster_header_sync of cluster_header_sync.v
input start_clk_early_jl;
output ctu_dram_tx_sync_early; // From u_dram_tx_sync of dff_ns.v
// Beginning of automatic outputs (from unused autoinst outputs)
output jbus_rx_sync; // From u_jbus_rx_sync of dff_ns.v
output jbus_tx_sync; // From u_jbus_tx_sync of dff_ns.v
output so; // From u_ctu_cluster_header_sync of cluster_header_sync.v
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire ctu_dram_tx_sync_dly1; // From u_ctu_dram_tx_sync_dly1 of dff_ns.v
wire ctu_dram_tx_sync_dly2; // From u_ctu_dram_tx_sync_dly2 of dff_ns.v
wire ctu_jbus_rx_sync_dly1; // From u_ctu_jbus_rx_sync_dly1 of dff_ns.v
wire ctu_jbus_rx_sync_dly2; // From u_ctu_jbus_rx_sync_dly2 of dff_ns.v
wire ctu_jbus_rx_sync_dly3; // From u_ctu_jbus_rx_sync_dly3 of dff_ns.v
wire ctu_jbus_tx_sync_dly1; // From u_ctu_jbus_tx_sync_dly1 of dff_ns.v
wire ctu_jbus_tx_sync_dly2; // From u_ctu_jbus_tx_sync_dly2 of dff_ns.v
wire ctu_jbus_tx_sync_dly3; // From u_ctu_jbus_tx_sync_dly3 of dff_ns.v
// End of automatics
wire ctu_dram_tx_sync_early_nxt;
wire jbus_tx_sync_nxt;
wire jbus_rx_sync_nxt;
wire jbus_tx_sync_local; // From u_ctu_cluster_header_sync of cluster_header_sync.v
wire jbus_rx_sync_local; // From u_ctu_cluster_header_sync of cluster_header_sync.v
wire dram_tx_sync_local; // From u_ctu_cluster_header_sync of cluster_header_sync.v
wire pulse_cnt_dn_nxt;
wire [2:0] pulse_cnt_nxt;
wire [2:0] pulse_cnt;
wire pulse_filter;
/* dff_ns AUTO_TEMPLATE (
.q(ctu_dram_tx_sync_dly1),
.din(ctu_dram_tx_sync),
.clk(cmp_gclk),
);
*/
dff_ns u_ctu_dram_tx_sync_dly1 (/*AUTOINST*/
// Outputs
.q (ctu_dram_tx_sync_dly1), // Templated
// Inputs
.din(ctu_dram_tx_sync), // Templated
.clk(cmp_gclk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.q(ctu_jbus_tx_sync_dly1),
.din(ctu_jbus_tx_sync),
.clk(cmp_gclk),
);
*/
dff_ns u_ctu_jbus_tx_sync_dly1 (/*AUTOINST*/
// Outputs
.q (ctu_jbus_tx_sync_dly1), // Templated
// Inputs
.din(ctu_jbus_tx_sync), // Templated
.clk(cmp_gclk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.q(ctu_jbus_rx_sync_dly1),
.din(ctu_jbus_rx_sync),
.clk(cmp_gclk),
);
*/
dff_ns u_ctu_jbus_rx_sync_dly1 (/*AUTOINST*/
// Outputs
.q (ctu_jbus_rx_sync_dly1), // Templated
// Inputs
.din(ctu_jbus_rx_sync), // Templated
.clk(cmp_gclk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.q(ctu_dram_tx_sync_dly2),
.din(ctu_dram_tx_sync_dly1),
.clk(cmp_gclk),
);
*/
dff_ns u_ctu_dram_tx_sync_dly2 (/*AUTOINST*/
// Outputs
.q (ctu_dram_tx_sync_dly2), // Templated
// Inputs
.din(ctu_dram_tx_sync_dly1), // Templated
.clk(cmp_gclk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.q(ctu_jbus_tx_sync_dly2),
.din(ctu_jbus_tx_sync_dly1),
.clk(cmp_gclk),
);
*/
dff_ns u_ctu_jbus_tx_sync_dly2 (/*AUTOINST*/
// Outputs
.q (ctu_jbus_tx_sync_dly2), // Templated
// Inputs
.din(ctu_jbus_tx_sync_dly1), // Templated
.clk(cmp_gclk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.q(ctu_jbus_rx_sync_dly2),
.din(ctu_jbus_rx_sync_dly1),
.clk(cmp_gclk),
);
*/
dff_ns u_ctu_jbus_rx_sync_dly2 (/*AUTOINST*/
// Outputs
.q (ctu_jbus_rx_sync_dly2), // Templated
// Inputs
.din(ctu_jbus_rx_sync_dly1), // Templated
.clk(cmp_gclk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.q(ctu_jbus_tx_sync_dly3),
.din(ctu_jbus_tx_sync_dly2),
.clk(cmp_gclk),
);
*/
dff_ns u_ctu_jbus_tx_sync_dly3 (/*AUTOINST*/
// Outputs
.q (ctu_jbus_tx_sync_dly3), // Templated
// Inputs
.din(ctu_jbus_tx_sync_dly2), // Templated
.clk(cmp_gclk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.q(ctu_jbus_rx_sync_dly3),
.din(ctu_jbus_rx_sync_dly2),
.clk(cmp_gclk),
);
*/
dff_ns u_ctu_jbus_rx_sync_dly3 (/*AUTOINST*/
// Outputs
.q (ctu_jbus_rx_sync_dly3), // Templated
// Inputs
.din(ctu_jbus_rx_sync_dly2), // Templated
.clk(cmp_gclk)); // Templated
/* cluster_header_sync AUTO_TEMPLATE (
.dram_rx_sync_global(1'b0),
.dram_tx_sync_global(ctu_dram_tx_sync_dly2),
.jbus_tx_sync_global(ctu_jbus_tx_sync_dly3),
.jbus_rx_sync_global(ctu_jbus_rx_sync_dly3),
.dram_tx_sync_local(dram_tx_sync_local),
.jbus_rx_sync_local(jbus_rx_sync_local),
.jbus_tx_sync_local(jbus_tx_sync_local),
.so(so),
.dram_rx_sync_local(),
.si(si),
.se(se),
.cmp_rclk(cmp_clk),
);
*/
cluster_header_sync u_ctu_cluster_header_sync (
.dram_tx_sync_local(dram_tx_sync_local),
.jbus_rx_sync_local(jbus_rx_sync_local),
.jbus_tx_sync_local(jbus_tx_sync_local),
/*AUTOINST*/
// Outputs
.dram_rx_sync_local(), // Templated
.so(so), // Templated
// Inputs
.dram_rx_sync_global(1'b0), // Templated
.dram_tx_sync_global(ctu_dram_tx_sync_dly2), // Templated
.jbus_rx_sync_global(ctu_jbus_rx_sync_dly3), // Templated
.jbus_tx_sync_global(ctu_jbus_tx_sync_dly3), // Templated
.cmp_gclk(cmp_gclk),
.cmp_rclk(cmp_clk), // Templated
.si(si), // Templated
.se(se)); // Templated
//------------------------------
//
// pulse counter:
//
//------------------------------
assign pulse_cnt_dn_nxt = (pulse_cnt == 3'b111) ;
assign pulse_cnt_nxt = ~pulse_cnt_dn_nxt? pulse_cnt + 3'b001 :
pulse_cnt;
dffrl_async_ns #(3) u_pulse_cnt(
.din ( pulse_cnt_nxt),
.clk (cmp_clk),
.rst_l(start_clk_early_jl),
.q (pulse_cnt));
dffrl_async_ns u_filter_pulse(
.din ( pulse_cnt_dn_nxt),
.clk (cmp_clk),
.rst_l(start_clk_early_jl),
.q (pulse_filter));
assign jbus_rx_sync_nxt = jbus_rx_sync_local & pulse_filter;
/* dff_ns AUTO_TEMPLATE (
.q(jbus_rx_sync),
.din(jbus_rx_sync_nxt),
.clk(cmp_clk),
);
*/
dff_ns u_jbus_rx_sync (/*AUTOINST*/
// Outputs
.q (jbus_rx_sync), // Templated
// Inputs
.din (jbus_rx_sync_nxt), // Templated
.clk (cmp_clk)); // Templated
assign jbus_tx_sync_nxt = jbus_tx_sync_local & pulse_filter;
/* dff_ns AUTO_TEMPLATE (
.q(jbus_tx_sync),
.din(jbus_tx_sync_nxt),
.clk(cmp_clk),
);
*/
dff_ns u_jbus_tx_sync (/*AUTOINST*/
// Outputs
.q (jbus_tx_sync), // Templated
// Inputs
.din (jbus_tx_sync_nxt), // Templated
.clk (cmp_clk)); // Templated
assign ctu_dram_tx_sync_early_nxt = dram_tx_sync_local & pulse_filter;
/* dff_ns AUTO_TEMPLATE (
.q(ctu_dram_tx_sync_early),
.din(ctu_dram_tx_sync_early_nxt ),
.clk(cmp_clk),
);
*/
dff_ns u_dram_tx_sync_early (/*AUTOINST*/
// Outputs
.q (ctu_dram_tx_sync_early), // Templated
// Inputs
.din (ctu_dram_tx_sync_early_nxt ), // Templated
.clk (cmp_clk)); // Templated
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-files:("../../../common/rtl/swrvr_u1_clib.v" "../../../common/rtl/cluster_header_sync.v")
// verilog-auto-sense-defines-constant:t
// End:
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// software programmable clock generator (still needs a reference input!)
module axi_clkgen (
// clocks
clk,
clk_0,
clk_1,
drp_clk,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_CLKIN_PERIOD = 5.0;
parameter PCORE_VCO_DIV = 11;
parameter PCORE_VCO_MUL = 49;
parameter PCORE_CLK0_DIV = 6;
parameter PCORE_CLK1_DIV = 6;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// clocks
input clk;
output clk_0;
output clk_1;
input drp_clk;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// reset and clocks
wire mmcm_rst;
wire drp_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire drp_sel_s;
wire drp_wr_s;
wire [11:0] drp_addr_s;
wire [15:0] drp_wdata_s;
wire [15:0] drp_rdata_s;
wire drp_ack_t_s;
wire drp_locked_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
// processor interface
up_clkgen i_up_clkgen (
.mmcm_rst (mmcm_rst),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel_s),
.drp_wr (drp_wr_s),
.drp_addr (drp_addr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_s),
.drp_ack_t (drp_ack_t_s),
.drp_locked (drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
// mmcm instantiations
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (PCORE_CLKIN_PERIOD),
.MMCM_VCO_DIV (PCORE_VCO_DIV),
.MMCM_VCO_MUL (PCORE_VCO_MUL),
.MMCM_CLK0_DIV (PCORE_CLK0_DIV),
.MMCM_CLK1_DIV (PCORE_CLK1_DIV))
i_mmcm_drp (
.clk (clk),
.mmcm_rst (mmcm_rst),
.mmcm_clk_0 (clk_0),
.mmcm_clk_1 (clk_1),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel_s),
.drp_wr (drp_wr_s),
.drp_addr (drp_addr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_s),
.drp_ack_t (drp_ack_t_s),
.drp_locked (drp_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
Copyright (C) {2014} {Ganesh Ajjanagadde} <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`default_nettype none
`define assert(condition) if(!((|{condition{)===1)) begin $display("FAIL"); $finish(1); end
module pixels_lost_test;
reg[9:0] x1;
reg[8:0] y1;
reg[9:0] x2;
reg[8:0] y2;
reg[9:0] x3;
reg[8:0] y3;
reg[9:0] x4;
reg[8:0] y4;
wire[6:0] percent_lost;
initial begin
x1 = 10'd80;
y1 = 9'd80;
x2 = 10'd80;
y2 = 9'd160;
x3 = 10'd160;
y3 = 9'd160;
x4 = 10'd160;
y4 = 9'd80;
end
reg clock = 0;
pixels_lost pixels_lost(clock, x1, y1, x2, y2, x3, y3, x4, y4, percent_lost);
always #1 clock <= !clock;
always @(posedge clock) begin
$display("%d, %d, %d, %d, %d, %d, %d, %d, %d", x1, y1, x2, y2, x3, y3, x4, y4, percent_lost);
end
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (lin64) Build 1215546 Mon Apr 27 19:07:21 MDT 2015
// Date : Fri Sep 18 12:15:17 2015
// Host : parallella running 64-bit Ubuntu 14.04.3 LTS
// Command : write_verilog -force -mode funcsim
// /home/aolofsson/Work_all/oh/xilibs/ip/fifo_async_104x32/fifo_async_104x32_funcsim.v
// Design : fifo_async_104x32
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z015clg485-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "fifo_async_104x32,fifo_generator_v12_0,{}" *) (* core_generation_info = "fifo_async_104x32,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=5,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=104,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=104,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=1,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=16,C_PROG_FULL_THRESH_NEGATE_VAL=15,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=5,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=5,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
(* NotValidForBitStream *)
module fifo_async_104x32
(wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
dout,
full,
almost_full,
empty,
valid,
prog_full);
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
input wr_rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
input rd_rst;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [103:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [103:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE ALMOST_FULL" *) output almost_full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output valid;
output prog_full;
wire almost_full;
wire [103:0]din;
wire [103:0]dout;
wire empty;
wire full;
wire prog_full;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire valid;
wire wr_clk;
wire wr_en;
wire wr_rst;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [4:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [4:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "5" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "104" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "104" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "zynq" *)
(* C_FULL_FLAGS_RST_VAL = "0" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "1" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "1" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "2" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "512x72" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "16" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "15" *)
(* C_PROG_FULL_TYPE = "1" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "5" *)
(* C_RD_DEPTH = "32" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "5" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "5" *)
(* C_WR_DEPTH = "32" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "5" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
fifo_async_104x32_fifo_generator_v12_0 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(almost_full),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[4:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(prog_full),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[4:0]),
.rd_en(rd_en),
.rd_rst(rd_rst),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(valid),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[4:0]),
.wr_en(wr_en),
.wr_rst(wr_rst),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module fifo_async_104x32_clk_x_pntrs
(ram_empty_i_reg,
Q,
\gdiff.diff_pntr_pad_reg[5] ,
\gc0.count_d1_reg[4] ,
\gic0.gc1.count_d3_reg[4] ,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
D);
output ram_empty_i_reg;
output [4:0]Q;
output [4:0]\gdiff.diff_pntr_pad_reg[5] ;
input [4:0]\gc0.count_d1_reg[4] ;
input [4:0]\gic0.gc1.count_d3_reg[4] ;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [3:0]D;
wire [3:0]D;
wire [4:0]Q;
wire [4:0]\gc0.count_d1_reg[4] ;
wire [4:0]\gdiff.diff_pntr_pad_reg[5] ;
wire [4:0]\gic0.gc1.count_d3_reg[4] ;
wire \gsync_stage[2].rd_stg_inst_n_2 ;
wire \gsync_stage[2].rd_stg_inst_n_3 ;
wire \gsync_stage[2].rd_stg_inst_n_4 ;
wire \gsync_stage[2].wr_stg_inst_n_1 ;
wire \gsync_stage[2].wr_stg_inst_n_2 ;
wire \gsync_stage[2].wr_stg_inst_n_3 ;
wire \gsync_stage[2].wr_stg_inst_n_4 ;
wire p_0_in0;
wire [3:0]p_0_in3_out;
wire [4:4]p_0_out;
wire [4:4]p_1_out;
wire [4:0]p_2_out;
wire [4:0]p_3_out;
wire ram_empty_i_i_5_n_0;
wire ram_empty_i_reg;
wire rd_clk;
wire [4:0]rd_pntr_gc;
wire rd_rst;
wire wr_clk;
wire [4:0]wr_pntr_gc;
wire wr_rst;
fifo_async_104x32_synchronizer_ff \gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.rd_clk(rd_clk),
.rd_rst(rd_rst));
fifo_async_104x32_synchronizer_ff_0 \gsync_stage[1].wr_stg_inst
(.D(p_2_out),
.Q(rd_pntr_gc),
.wr_clk(wr_clk),
.wr_rst(wr_rst));
fifo_async_104x32_synchronizer_ff_1 \gsync_stage[2].rd_stg_inst
(.D(p_3_out),
.out(p_1_out),
.rd_clk(rd_clk),
.rd_rst(rd_rst),
.\wr_pntr_bin_reg[3] ({p_0_in0,\gsync_stage[2].rd_stg_inst_n_2 ,\gsync_stage[2].rd_stg_inst_n_3 ,\gsync_stage[2].rd_stg_inst_n_4 }));
fifo_async_104x32_synchronizer_ff_2 \gsync_stage[2].wr_stg_inst
(.D(p_2_out),
.out(p_0_out),
.\rd_pntr_bin_reg[3] ({\gsync_stage[2].wr_stg_inst_n_1 ,\gsync_stage[2].wr_stg_inst_n_2 ,\gsync_stage[2].wr_stg_inst_n_3 ,\gsync_stage[2].wr_stg_inst_n_4 }),
.wr_clk(wr_clk),
.wr_rst(wr_rst));
LUT5 #(
.INIT(32'h82000082))
ram_empty_i_i_3
(.I0(ram_empty_i_i_5_n_0),
.I1(Q[4]),
.I2(\gc0.count_d1_reg[4] [4]),
.I3(Q[3]),
.I4(\gc0.count_d1_reg[4] [3]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_5
(.I0(Q[2]),
.I1(\gc0.count_d1_reg[4] [2]),
.I2(Q[1]),
.I3(\gc0.count_d1_reg[4] [1]),
.I4(\gc0.count_d1_reg[4] [0]),
.I5(Q[0]),
.O(ram_empty_i_i_5_n_0));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(\gsync_stage[2].wr_stg_inst_n_4 ),
.Q(\gdiff.diff_pntr_pad_reg[5] [0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(\gsync_stage[2].wr_stg_inst_n_3 ),
.Q(\gdiff.diff_pntr_pad_reg[5] [1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(\gsync_stage[2].wr_stg_inst_n_2 ),
.Q(\gdiff.diff_pntr_pad_reg[5] [2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(\gsync_stage[2].wr_stg_inst_n_1 ),
.Q(\gdiff.diff_pntr_pad_reg[5] [3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(p_0_out),
.Q(\gdiff.diff_pntr_pad_reg[5] [4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(D[0]),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(D[1]),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(D[2]),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(D[3]),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(\gc0.count_d1_reg[4] [4]),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(\gsync_stage[2].rd_stg_inst_n_4 ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(\gsync_stage[2].rd_stg_inst_n_3 ),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(\gsync_stage[2].rd_stg_inst_n_2 ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(p_0_in0),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(p_1_out),
.Q(Q[4]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[0]_i_1
(.I0(\gic0.gc1.count_d3_reg[4] [0]),
.I1(\gic0.gc1.count_d3_reg[4] [1]),
.O(p_0_in3_out[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[1]_i_1
(.I0(\gic0.gc1.count_d3_reg[4] [1]),
.I1(\gic0.gc1.count_d3_reg[4] [2]),
.O(p_0_in3_out[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[2]_i_1
(.I0(\gic0.gc1.count_d3_reg[4] [2]),
.I1(\gic0.gc1.count_d3_reg[4] [3]),
.O(p_0_in3_out[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[3]_i_1
(.I0(\gic0.gc1.count_d3_reg[4] [3]),
.I1(\gic0.gc1.count_d3_reg[4] [4]),
.O(p_0_in3_out[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(p_0_in3_out[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(p_0_in3_out[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(p_0_in3_out[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(p_0_in3_out[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(\gic0.gc1.count_d3_reg[4] [4]),
.Q(wr_pntr_gc[4]));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module fifo_async_104x32_dmem
(dout,
E,
rd_clk,
rd_rst,
wr_clk,
wr_pntr_plus1_pad,
din,
\gc0.count_d1_reg[4] ,
Q);
output [103:0]dout;
input [0:0]E;
input rd_clk;
input rd_rst;
input wr_clk;
input [0:0]wr_pntr_plus1_pad;
input [103:0]din;
input [4:0]\gc0.count_d1_reg[4] ;
input [4:0]Q;
wire [0:0]E;
wire [4:0]Q;
wire [103:0]din;
wire [103:0]dout;
wire [4:0]\gc0.count_d1_reg[4] ;
wire [103:0]p_0_out;
wire rd_clk;
wire rd_rst;
wire wr_clk;
wire [0:0]wr_pntr_plus1_pad;
wire [1:0]NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_102_103_DOB_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_102_103_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_102_103_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_60_65_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_66_71_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_72_77_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_78_83_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_84_89_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_90_95_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_31_96_101_DOD_UNCONNECTED;
RAM32M RAM_reg_0_31_0_5
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[1:0]),
.DIB(din[3:2]),
.DIC(din[5:4]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[1:0]),
.DOB(p_0_out[3:2]),
.DOC(p_0_out[5:4]),
.DOD(NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_102_103
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[103:102]),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA(p_0_out[103:102]),
.DOB(NLW_RAM_reg_0_31_102_103_DOB_UNCONNECTED[1:0]),
.DOC(NLW_RAM_reg_0_31_102_103_DOC_UNCONNECTED[1:0]),
.DOD(NLW_RAM_reg_0_31_102_103_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_12_17
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[13:12]),
.DIB(din[15:14]),
.DIC(din[17:16]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[13:12]),
.DOB(p_0_out[15:14]),
.DOC(p_0_out[17:16]),
.DOD(NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_18_23
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[19:18]),
.DIB(din[21:20]),
.DIC(din[23:22]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[19:18]),
.DOB(p_0_out[21:20]),
.DOC(p_0_out[23:22]),
.DOD(NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_24_29
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[25:24]),
.DIB(din[27:26]),
.DIC(din[29:28]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[25:24]),
.DOB(p_0_out[27:26]),
.DOC(p_0_out[29:28]),
.DOD(NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_30_35
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[31:30]),
.DIB(din[33:32]),
.DIC(din[35:34]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[31:30]),
.DOB(p_0_out[33:32]),
.DOC(p_0_out[35:34]),
.DOD(NLW_RAM_reg_0_31_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_36_41
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[37:36]),
.DIB(din[39:38]),
.DIC(din[41:40]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[37:36]),
.DOB(p_0_out[39:38]),
.DOC(p_0_out[41:40]),
.DOD(NLW_RAM_reg_0_31_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_42_47
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[43:42]),
.DIB(din[45:44]),
.DIC(din[47:46]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[43:42]),
.DOB(p_0_out[45:44]),
.DOC(p_0_out[47:46]),
.DOD(NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_48_53
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[49:48]),
.DIB(din[51:50]),
.DIC(din[53:52]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[49:48]),
.DOB(p_0_out[51:50]),
.DOC(p_0_out[53:52]),
.DOD(NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_54_59
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[55:54]),
.DIB(din[57:56]),
.DIC(din[59:58]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[55:54]),
.DOB(p_0_out[57:56]),
.DOC(p_0_out[59:58]),
.DOD(NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_60_65
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[61:60]),
.DIB(din[63:62]),
.DIC(din[65:64]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[61:60]),
.DOB(p_0_out[63:62]),
.DOC(p_0_out[65:64]),
.DOD(NLW_RAM_reg_0_31_60_65_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_66_71
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[67:66]),
.DIB(din[69:68]),
.DIC(din[71:70]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[67:66]),
.DOB(p_0_out[69:68]),
.DOC(p_0_out[71:70]),
.DOD(NLW_RAM_reg_0_31_66_71_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_6_11
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[7:6]),
.DIB(din[9:8]),
.DIC(din[11:10]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[7:6]),
.DOB(p_0_out[9:8]),
.DOC(p_0_out[11:10]),
.DOD(NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_72_77
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[73:72]),
.DIB(din[75:74]),
.DIC(din[77:76]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[73:72]),
.DOB(p_0_out[75:74]),
.DOC(p_0_out[77:76]),
.DOD(NLW_RAM_reg_0_31_72_77_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_78_83
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[79:78]),
.DIB(din[81:80]),
.DIC(din[83:82]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[79:78]),
.DOB(p_0_out[81:80]),
.DOC(p_0_out[83:82]),
.DOD(NLW_RAM_reg_0_31_78_83_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_84_89
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[85:84]),
.DIB(din[87:86]),
.DIC(din[89:88]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[85:84]),
.DOB(p_0_out[87:86]),
.DOC(p_0_out[89:88]),
.DOD(NLW_RAM_reg_0_31_84_89_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_90_95
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[91:90]),
.DIB(din[93:92]),
.DIC(din[95:94]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[91:90]),
.DOB(p_0_out[93:92]),
.DOC(p_0_out[95:94]),
.DOD(NLW_RAM_reg_0_31_90_95_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
RAM32M RAM_reg_0_31_96_101
(.ADDRA(\gc0.count_d1_reg[4] ),
.ADDRB(\gc0.count_d1_reg[4] ),
.ADDRC(\gc0.count_d1_reg[4] ),
.ADDRD(Q),
.DIA(din[97:96]),
.DIB(din[99:98]),
.DIC(din[101:100]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[97:96]),
.DOB(p_0_out[99:98]),
.DOC(p_0_out[101:100]),
.DOD(NLW_RAM_reg_0_31_96_101_DOD_UNCONNECTED[1:0]),
.WCLK(wr_clk),
.WE(wr_pntr_plus1_pad));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[0]),
.Q(dout[0]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[100]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[100]),
.Q(dout[100]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[101]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[101]),
.Q(dout[101]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[102]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[102]),
.Q(dout[102]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[103]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[103]),
.Q(dout[103]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[10]),
.Q(dout[10]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[11]),
.Q(dout[11]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[12]),
.Q(dout[12]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[13]),
.Q(dout[13]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[14]),
.Q(dout[14]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[15]),
.Q(dout[15]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[16]),
.Q(dout[16]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[17]),
.Q(dout[17]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[18]),
.Q(dout[18]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[19]),
.Q(dout[19]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[1]),
.Q(dout[1]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[20]),
.Q(dout[20]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[21]),
.Q(dout[21]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[22]),
.Q(dout[22]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[23]),
.Q(dout[23]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[24]),
.Q(dout[24]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[25]),
.Q(dout[25]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[26]),
.Q(dout[26]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[27]),
.Q(dout[27]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[28]),
.Q(dout[28]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[29]),
.Q(dout[29]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[2]),
.Q(dout[2]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[30]),
.Q(dout[30]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[31]),
.Q(dout[31]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[32]),
.Q(dout[32]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[33]),
.Q(dout[33]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[34]),
.Q(dout[34]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[35]),
.Q(dout[35]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[36]),
.Q(dout[36]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[37]),
.Q(dout[37]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[38]),
.Q(dout[38]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[39]),
.Q(dout[39]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[3]),
.Q(dout[3]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[40]),
.Q(dout[40]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[41]),
.Q(dout[41]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[42]),
.Q(dout[42]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[43]),
.Q(dout[43]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[44]),
.Q(dout[44]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[45]),
.Q(dout[45]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[46]),
.Q(dout[46]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[47]),
.Q(dout[47]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[48]),
.Q(dout[48]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[49]),
.Q(dout[49]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[4]),
.Q(dout[4]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[50]),
.Q(dout[50]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[51]),
.Q(dout[51]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[52]),
.Q(dout[52]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[53]),
.Q(dout[53]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[54]),
.Q(dout[54]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[55]),
.Q(dout[55]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[56]),
.Q(dout[56]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[57]),
.Q(dout[57]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[58]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[58]),
.Q(dout[58]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[59]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[59]),
.Q(dout[59]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[5]),
.Q(dout[5]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[60]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[60]),
.Q(dout[60]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[61]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[61]),
.Q(dout[61]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[62]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[62]),
.Q(dout[62]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[63]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[63]),
.Q(dout[63]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[64]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[64]),
.Q(dout[64]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[65]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[65]),
.Q(dout[65]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[66]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[66]),
.Q(dout[66]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[67]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[67]),
.Q(dout[67]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[68]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[68]),
.Q(dout[68]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[69]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[69]),
.Q(dout[69]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[6]),
.Q(dout[6]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[70]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[70]),
.Q(dout[70]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[71]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[71]),
.Q(dout[71]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[72]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[72]),
.Q(dout[72]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[73]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[73]),
.Q(dout[73]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[74]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[74]),
.Q(dout[74]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[75]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[75]),
.Q(dout[75]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[76]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[76]),
.Q(dout[76]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[77]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[77]),
.Q(dout[77]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[78]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[78]),
.Q(dout[78]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[79]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[79]),
.Q(dout[79]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[7]),
.Q(dout[7]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[80]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[80]),
.Q(dout[80]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[81]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[81]),
.Q(dout[81]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[82]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[82]),
.Q(dout[82]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[83]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[83]),
.Q(dout[83]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[84]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[84]),
.Q(dout[84]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[85]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[85]),
.Q(dout[85]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[86]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[86]),
.Q(dout[86]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[87]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[87]),
.Q(dout[87]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[88]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[88]),
.Q(dout[88]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[89]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[89]),
.Q(dout[89]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[8]),
.Q(dout[8]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[90]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[90]),
.Q(dout[90]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[91]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[91]),
.Q(dout[91]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[92]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[92]),
.Q(dout[92]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[93]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[93]),
.Q(dout[93]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[94]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[94]),
.Q(dout[94]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[95]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[95]),
.Q(dout[95]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[96]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[96]),
.Q(dout[96]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[97]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[97]),
.Q(dout[97]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[98]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[98]),
.Q(dout[98]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[99]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[99]),
.Q(dout[99]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(p_0_out[9]),
.Q(dout[9]));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module fifo_async_104x32_fifo_generator_ramfifo
(empty,
dout,
valid,
full,
almost_full,
prog_full,
rd_en,
wr_en,
rd_clk,
rd_rst,
wr_clk,
wr_rst,
din);
output empty;
output [103:0]dout;
output valid;
output full;
output almost_full;
output prog_full;
input rd_en;
input wr_en;
input rd_clk;
input rd_rst;
input wr_clk;
input wr_rst;
input [103:0]din;
wire almost_full;
wire [103:0]din;
wire [103:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gcx.clkx_n_0 ;
wire \gntv_or_sync_fifo.gl0.rd_n_2 ;
wire \gntv_or_sync_fifo.gl0.rd_n_3 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire [4:0]p_0_out;
wire [4:0]p_1_out;
wire [4:0]p_20_out;
wire [4:0]p_9_out;
wire prog_full;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire valid;
wire wr_clk;
wire wr_en;
wire wr_rst;
fifo_async_104x32_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.D({\gntv_or_sync_fifo.gl0.rd_n_3 ,\gntv_or_sync_fifo.gl0.rd_n_4 ,\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 }),
.Q(p_1_out),
.\gc0.count_d1_reg[4] (p_20_out),
.\gdiff.diff_pntr_pad_reg[5] (p_0_out),
.\gic0.gc1.count_d3_reg[4] (p_9_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_0 ),
.rd_clk(rd_clk),
.rd_rst(rd_rst),
.wr_clk(wr_clk),
.wr_rst(wr_rst));
fifo_async_104x32_rd_logic \gntv_or_sync_fifo.gl0.rd
(.D({\gntv_or_sync_fifo.gl0.rd_n_3 ,\gntv_or_sync_fifo.gl0.rd_n_4 ,\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 }),
.E(\gntv_or_sync_fifo.gl0.rd_n_2 ),
.Q(p_1_out),
.empty(empty),
.rd_clk(rd_clk),
.rd_en(rd_en),
.\rd_pntr_gc_reg[4] (p_20_out),
.rd_rst(rd_rst),
.valid(valid),
.\wr_pntr_bin_reg[4] (\gntv_or_sync_fifo.gcx.clkx_n_0 ));
fifo_async_104x32_wr_logic \gntv_or_sync_fifo.gl0.wr
(.E(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.Q(p_9_out),
.almost_full(almost_full),
.full(full),
.prog_full(prog_full),
.\rd_pntr_bin_reg[4] (p_0_out),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst(wr_rst));
fifo_async_104x32_memory \gntv_or_sync_fifo.mem
(.E(\gntv_or_sync_fifo.gl0.rd_n_2 ),
.Q(p_9_out),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[4] (p_20_out),
.rd_clk(rd_clk),
.rd_rst(rd_rst),
.wr_clk(wr_clk),
.wr_pntr_plus1_pad(\gntv_or_sync_fifo.gl0.wr_n_3 ));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module fifo_async_104x32_fifo_generator_top
(empty,
dout,
valid,
full,
almost_full,
prog_full,
rd_en,
wr_en,
rd_clk,
rd_rst,
wr_clk,
wr_rst,
din);
output empty;
output [103:0]dout;
output valid;
output full;
output almost_full;
output prog_full;
input rd_en;
input wr_en;
input rd_clk;
input rd_rst;
input wr_clk;
input wr_rst;
input [103:0]din;
wire almost_full;
wire [103:0]din;
wire [103:0]dout;
wire empty;
wire full;
wire prog_full;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire valid;
wire wr_clk;
wire wr_en;
wire wr_rst;
fifo_async_104x32_fifo_generator_ramfifo \grf.rf
(.almost_full(almost_full),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rd_rst(rd_rst),
.valid(valid),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst(wr_rst));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "5" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "104" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "104" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "zynq" *)
(* C_FULL_FLAGS_RST_VAL = "0" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "1" *)
(* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "1" *) (* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "2" *)
(* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x72" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "16" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "15" *) (* C_PROG_FULL_TYPE = "1" *) (* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "5" *) (* C_RD_DEPTH = "32" *)
(* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "5" *) (* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "5" *) (* C_WR_DEPTH = "32" *) (* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "5" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v12_0" *)
module fifo_async_104x32_fifo_generator_v12_0
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [103:0]din;
input wr_en;
input rd_en;
input [4:0]prog_empty_thresh;
input [4:0]prog_empty_thresh_assert;
input [4:0]prog_empty_thresh_negate;
input [4:0]prog_full_thresh;
input [4:0]prog_full_thresh_assert;
input [4:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [103:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [4:0]data_count;
output [4:0]rd_data_count;
output [4:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire almost_full;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [103:0]din;
wire [103:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [4:0]prog_empty_thresh;
wire [4:0]prog_empty_thresh_assert;
wire [4:0]prog_empty_thresh_negate;
wire prog_full;
wire [4:0]prog_full_thresh;
wire [4:0]prog_full_thresh_assert;
wire [4:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire valid;
wire wr_clk;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
fifo_async_104x32_fifo_generator_v12_0_synth inst_fifo_gen
(.almost_full(almost_full),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rd_rst(rd_rst),
.valid(valid),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst(wr_rst));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0_synth" *)
module fifo_async_104x32_fifo_generator_v12_0_synth
(empty,
dout,
valid,
full,
almost_full,
prog_full,
rd_en,
wr_en,
rd_clk,
rd_rst,
wr_clk,
wr_rst,
din);
output empty;
output [103:0]dout;
output valid;
output full;
output almost_full;
output prog_full;
input rd_en;
input wr_en;
input rd_clk;
input rd_rst;
input wr_clk;
input wr_rst;
input [103:0]din;
wire almost_full;
wire [103:0]din;
wire [103:0]dout;
wire empty;
wire full;
wire prog_full;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire valid;
wire wr_clk;
wire wr_en;
wire wr_rst;
fifo_async_104x32_fifo_generator_top \gconvfifo.rf
(.almost_full(almost_full),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rd_rst(rd_rst),
.valid(valid),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst(wr_rst));
endmodule
(* ORIG_REF_NAME = "memory" *)
module fifo_async_104x32_memory
(dout,
E,
rd_clk,
rd_rst,
wr_clk,
wr_pntr_plus1_pad,
din,
\gc0.count_d1_reg[4] ,
Q);
output [103:0]dout;
input [0:0]E;
input rd_clk;
input rd_rst;
input wr_clk;
input [0:0]wr_pntr_plus1_pad;
input [103:0]din;
input [4:0]\gc0.count_d1_reg[4] ;
input [4:0]Q;
wire [0:0]E;
wire [4:0]Q;
wire [103:0]din;
wire [103:0]dout;
wire [4:0]\gc0.count_d1_reg[4] ;
wire rd_clk;
wire rd_rst;
wire wr_clk;
wire [0:0]wr_pntr_plus1_pad;
fifo_async_104x32_dmem \gdm.dm
(.E(E),
.Q(Q),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[4] (\gc0.count_d1_reg[4] ),
.rd_clk(rd_clk),
.rd_rst(rd_rst),
.wr_clk(wr_clk),
.wr_pntr_plus1_pad(wr_pntr_plus1_pad));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module fifo_async_104x32_rd_bin_cntr
(D,
\rd_pntr_gc_reg[4] ,
ram_empty_i_reg,
Q,
p_18_out,
rd_en,
\wr_pntr_bin_reg[4] ,
E,
rd_clk,
rd_rst);
output [3:0]D;
output [4:0]\rd_pntr_gc_reg[4] ;
output ram_empty_i_reg;
input [4:0]Q;
input p_18_out;
input rd_en;
input \wr_pntr_bin_reg[4] ;
input [0:0]E;
input rd_clk;
input rd_rst;
wire [3:0]D;
wire [0:0]E;
wire [4:0]Q;
wire p_18_out;
wire [4:0]plusOp__0;
wire ram_empty_i_i_2_n_0;
wire ram_empty_i_i_4_n_0;
wire ram_empty_i_reg;
wire rd_clk;
wire rd_en;
wire [4:0]\rd_pntr_gc_reg[4] ;
wire [4:0]rd_pntr_plus1;
wire rd_rst;
wire \wr_pntr_bin_reg[4] ;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(rd_pntr_plus1[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(rd_pntr_plus1[0]),
.I1(rd_pntr_plus1[1]),
.O(plusOp__0[1]));
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(rd_pntr_plus1[1]),
.I1(rd_pntr_plus1[0]),
.I2(rd_pntr_plus1[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(rd_pntr_plus1[2]),
.I1(rd_pntr_plus1[0]),
.I2(rd_pntr_plus1[1]),
.I3(rd_pntr_plus1[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(rd_pntr_plus1[3]),
.I1(rd_pntr_plus1[1]),
.I2(rd_pntr_plus1[0]),
.I3(rd_pntr_plus1[2]),
.I4(rd_pntr_plus1[4]),
.O(plusOp__0[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(rd_pntr_plus1[0]),
.Q(\rd_pntr_gc_reg[4] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(rd_pntr_plus1[1]),
.Q(\rd_pntr_gc_reg[4] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(rd_pntr_plus1[2]),
.Q(\rd_pntr_gc_reg[4] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(rd_pntr_plus1[3]),
.Q(\rd_pntr_gc_reg[4] [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(rd_pntr_plus1[4]),
.Q(\rd_pntr_gc_reg[4] [4]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp__0[0]),
.PRE(rd_rst),
.Q(rd_pntr_plus1[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(plusOp__0[1]),
.Q(rd_pntr_plus1[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(plusOp__0[2]),
.Q(rd_pntr_plus1[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(plusOp__0[3]),
.Q(rd_pntr_plus1[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(rd_rst),
.D(plusOp__0[4]),
.Q(rd_pntr_plus1[4]));
LUT6 #(
.INIT(64'hFFFFFFFF82000082))
ram_empty_i_i_1
(.I0(ram_empty_i_i_2_n_0),
.I1(rd_pntr_plus1[2]),
.I2(Q[2]),
.I3(rd_pntr_plus1[3]),
.I4(Q[3]),
.I5(\wr_pntr_bin_reg[4] ),
.O(ram_empty_i_reg));
LUT5 #(
.INIT(32'h90090000))
ram_empty_i_i_2
(.I0(Q[4]),
.I1(rd_pntr_plus1[4]),
.I2(Q[1]),
.I3(rd_pntr_plus1[1]),
.I4(ram_empty_i_i_4_n_0),
.O(ram_empty_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0900))
ram_empty_i_i_4
(.I0(rd_pntr_plus1[0]),
.I1(Q[0]),
.I2(p_18_out),
.I3(rd_en),
.O(ram_empty_i_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[0]_i_1
(.I0(\rd_pntr_gc_reg[4] [0]),
.I1(\rd_pntr_gc_reg[4] [1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[1]_i_1
(.I0(\rd_pntr_gc_reg[4] [1]),
.I1(\rd_pntr_gc_reg[4] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[2]_i_1
(.I0(\rd_pntr_gc_reg[4] [2]),
.I1(\rd_pntr_gc_reg[4] [3]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[3]_i_1
(.I0(\rd_pntr_gc_reg[4] [3]),
.I1(\rd_pntr_gc_reg[4] [4]),
.O(D[3]));
endmodule
(* ORIG_REF_NAME = "rd_handshaking_flags" *)
module fifo_async_104x32_rd_handshaking_flags
(valid,
ram_empty_i_reg,
rd_clk,
rd_rst);
output valid;
input ram_empty_i_reg;
input rd_clk;
input rd_rst;
wire ram_empty_i_reg;
wire rd_clk;
wire rd_rst;
wire valid;
FDCE #(
.INIT(1'b0))
\gv.ram_valid_d1_reg
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(ram_empty_i_reg),
.Q(valid));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module fifo_async_104x32_rd_logic
(empty,
valid,
E,
D,
\rd_pntr_gc_reg[4] ,
rd_clk,
rd_rst,
Q,
rd_en,
\wr_pntr_bin_reg[4] );
output empty;
output valid;
output [0:0]E;
output [3:0]D;
output [4:0]\rd_pntr_gc_reg[4] ;
input rd_clk;
input rd_rst;
input [4:0]Q;
input rd_en;
input \wr_pntr_bin_reg[4] ;
wire [3:0]D;
wire [0:0]E;
wire [4:0]Q;
wire empty;
wire \gras.rsts_n_3 ;
wire p_14_out;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire [4:0]\rd_pntr_gc_reg[4] ;
wire rd_rst;
wire rpntr_n_9;
wire valid;
wire \wr_pntr_bin_reg[4] ;
fifo_async_104x32_rd_status_flags_as \gras.rsts
(.E(E),
.empty(empty),
.\gc0.count_d1_reg[4] (p_14_out),
.\gc0.count_reg[2] (rpntr_n_9),
.\gv.ram_valid_d1_reg (\gras.rsts_n_3 ),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rd_rst(rd_rst));
fifo_async_104x32_rd_handshaking_flags \grhf.rhf
(.ram_empty_i_reg(\gras.rsts_n_3 ),
.rd_clk(rd_clk),
.rd_rst(rd_rst),
.valid(valid));
fifo_async_104x32_rd_bin_cntr rpntr
(.D(D),
.E(p_14_out),
.Q(Q),
.p_18_out(p_18_out),
.ram_empty_i_reg(rpntr_n_9),
.rd_clk(rd_clk),
.rd_en(rd_en),
.\rd_pntr_gc_reg[4] (\rd_pntr_gc_reg[4] ),
.rd_rst(rd_rst),
.\wr_pntr_bin_reg[4] (\wr_pntr_bin_reg[4] ));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module fifo_async_104x32_rd_status_flags_as
(empty,
p_18_out,
E,
\gv.ram_valid_d1_reg ,
\gc0.count_d1_reg[4] ,
\gc0.count_reg[2] ,
rd_clk,
rd_rst,
rd_en);
output empty;
output p_18_out;
output [0:0]E;
output \gv.ram_valid_d1_reg ;
output [0:0]\gc0.count_d1_reg[4] ;
input \gc0.count_reg[2] ;
input rd_clk;
input rd_rst;
input rd_en;
wire [0:0]E;
wire empty;
wire [0:0]\gc0.count_d1_reg[4] ;
wire \gc0.count_reg[2] ;
wire \gv.ram_valid_d1_reg ;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire rd_rst;
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[4]_i_1
(.I0(rd_en),
.I1(p_18_out),
.O(\gc0.count_d1_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h2))
\gpr1.dout_i[103]_i_1
(.I0(rd_en),
.I1(p_18_out),
.O(E));
LUT2 #(
.INIT(4'h2))
\gv.ram_valid_d1_i_1
(.I0(rd_en),
.I1(empty),
.O(\gv.ram_valid_d1_reg ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gc0.count_reg[2] ),
.PRE(rd_rst),
.Q(p_18_out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gc0.count_reg[2] ),
.PRE(rd_rst),
.Q(empty));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_async_104x32_synchronizer_ff
(D,
Q,
rd_clk,
rd_rst);
output [4:0]D;
input [4:0]Q;
input rd_clk;
input rd_rst;
wire [4:0]Q;
wire [4:0]Q_reg;
wire rd_clk;
wire rd_rst;
assign D[4:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(Q[4]),
.Q(Q_reg[4]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_async_104x32_synchronizer_ff_0
(D,
Q,
wr_clk,
wr_rst);
output [4:0]D;
input [4:0]Q;
input wr_clk;
input wr_rst;
wire [4:0]Q;
wire [4:0]Q_reg;
wire wr_clk;
wire wr_rst;
assign D[4:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(Q[4]),
.Q(Q_reg[4]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_async_104x32_synchronizer_ff_1
(out,
\wr_pntr_bin_reg[3] ,
D,
rd_clk,
rd_rst);
output [0:0]out;
output [3:0]\wr_pntr_bin_reg[3] ;
input [4:0]D;
input rd_clk;
input rd_rst;
wire [4:0]D;
wire [4:0]Q_reg;
wire rd_clk;
wire rd_rst;
wire [3:0]\wr_pntr_bin_reg[3] ;
assign out[0] = Q_reg[4];
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(rd_rst),
.D(D[4]),
.Q(Q_reg[4]));
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[0]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[0]),
.I2(Q_reg[1]),
.I3(Q_reg[4]),
.I4(Q_reg[3]),
.O(\wr_pntr_bin_reg[3] [0]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(Q_reg[4]),
.I3(Q_reg[3]),
.O(\wr_pntr_bin_reg[3] [1]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[2]_i_1
(.I0(Q_reg[3]),
.I1(Q_reg[2]),
.I2(Q_reg[4]),
.O(\wr_pntr_bin_reg[3] [2]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[3]_i_1
(.I0(Q_reg[3]),
.I1(Q_reg[4]),
.O(\wr_pntr_bin_reg[3] [3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_async_104x32_synchronizer_ff_2
(out,
\rd_pntr_bin_reg[3] ,
D,
wr_clk,
wr_rst);
output [0:0]out;
output [3:0]\rd_pntr_bin_reg[3] ;
input [4:0]D;
input wr_clk;
input wr_rst;
wire [4:0]D;
wire [4:0]Q_reg;
wire [3:0]\rd_pntr_bin_reg[3] ;
wire wr_clk;
wire wr_rst;
assign out[0] = Q_reg[4];
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(D[4]),
.Q(Q_reg[4]));
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[0]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[0]),
.I2(Q_reg[1]),
.I3(Q_reg[4]),
.I4(Q_reg[3]),
.O(\rd_pntr_bin_reg[3] [0]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(Q_reg[4]),
.I3(Q_reg[3]),
.O(\rd_pntr_bin_reg[3] [1]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[2]_i_1
(.I0(Q_reg[3]),
.I1(Q_reg[2]),
.I2(Q_reg[4]),
.O(\rd_pntr_bin_reg[3] [2]));
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[3]_i_1
(.I0(Q_reg[3]),
.I1(Q_reg[4]),
.O(\rd_pntr_bin_reg[3] [3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module fifo_async_104x32_wr_bin_cntr
(S,
Q,
\gdiff.diff_pntr_pad_reg[5] ,
\wr_pntr_gc_reg[4] ,
ram_full_i,
comp2,
\gaf.ram_almost_full_i_reg ,
\rd_pntr_bin_reg[4] ,
E,
wr_clk,
wr_rst,
wr_en,
p_2_out);
output [2:0]S;
output [3:0]Q;
output [1:0]\gdiff.diff_pntr_pad_reg[5] ;
output [4:0]\wr_pntr_gc_reg[4] ;
output ram_full_i;
output comp2;
output \gaf.ram_almost_full_i_reg ;
input [4:0]\rd_pntr_bin_reg[4] ;
input [0:0]E;
input wr_clk;
input wr_rst;
input wr_en;
input p_2_out;
wire [0:0]E;
wire [3:0]Q;
wire [2:0]S;
wire comp2;
wire \gaf.ram_almost_full_i_i_3_n_0 ;
wire \gaf.ram_almost_full_i_i_4_n_0 ;
wire \gaf.ram_almost_full_i_reg ;
wire [1:0]\gdiff.diff_pntr_pad_reg[5] ;
wire p_2_out;
wire [4:4]p_8_out;
wire [4:0]plusOp__1;
wire ram_full_i;
wire ram_full_i_i_2_n_0;
wire ram_full_i_i_4_n_0;
wire ram_full_i_i_5_n_0;
wire ram_full_i_i_6_n_0;
wire [4:0]\rd_pntr_bin_reg[4] ;
wire wr_clk;
wire wr_en;
wire [4:0]\wr_pntr_gc_reg[4] ;
wire [4:0]wr_pntr_plus2;
wire [4:0]wr_pntr_plus3;
wire wr_rst;
LUT6 #(
.INIT(64'h0000100100000000))
\gaf.ram_almost_full_i_i_2
(.I0(\gaf.ram_almost_full_i_i_3_n_0 ),
.I1(\gaf.ram_almost_full_i_i_4_n_0 ),
.I2(\rd_pntr_bin_reg[4] [3]),
.I3(wr_pntr_plus3[3]),
.I4(p_2_out),
.I5(wr_en),
.O(\gaf.ram_almost_full_i_reg ));
LUT4 #(
.INIT(16'h6FF6))
\gaf.ram_almost_full_i_i_3
(.I0(wr_pntr_plus3[4]),
.I1(\rd_pntr_bin_reg[4] [4]),
.I2(wr_pntr_plus3[2]),
.I3(\rd_pntr_bin_reg[4] [2]),
.O(\gaf.ram_almost_full_i_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h6FF6))
\gaf.ram_almost_full_i_i_4
(.I0(wr_pntr_plus3[1]),
.I1(\rd_pntr_bin_reg[4] [1]),
.I2(wr_pntr_plus3[0]),
.I3(\rd_pntr_bin_reg[4] [0]),
.O(\gaf.ram_almost_full_i_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[5]_i_3
(.I0(p_8_out),
.I1(\rd_pntr_bin_reg[4] [4]),
.O(\gdiff.diff_pntr_pad_reg[5] [1]));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[5]_i_4
(.I0(Q[3]),
.I1(\rd_pntr_bin_reg[4] [3]),
.O(\gdiff.diff_pntr_pad_reg[5] [0]));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[5]_i_6
(.I0(Q[2]),
.I1(\rd_pntr_bin_reg[4] [2]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[5]_i_7
(.I0(Q[1]),
.I1(\rd_pntr_bin_reg[4] [1]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[5]_i_8
(.I0(Q[0]),
.I1(\rd_pntr_bin_reg[4] [0]),
.O(S[0]));
LUT1 #(
.INIT(2'h1))
\gic0.gc1.count[0]_i_1
(.I0(wr_pntr_plus3[0]),
.O(plusOp__1[0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\gic0.gc1.count[1]_i_1
(.I0(wr_pntr_plus3[0]),
.I1(wr_pntr_plus3[1]),
.O(plusOp__1[1]));
LUT3 #(
.INIT(8'h78))
\gic0.gc1.count[2]_i_1
(.I0(wr_pntr_plus3[0]),
.I1(wr_pntr_plus3[1]),
.I2(wr_pntr_plus3[2]),
.O(plusOp__1[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc1.count[3]_i_1
(.I0(wr_pntr_plus3[1]),
.I1(wr_pntr_plus3[0]),
.I2(wr_pntr_plus3[2]),
.I3(wr_pntr_plus3[3]),
.O(plusOp__1[3]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc1.count[4]_i_1
(.I0(wr_pntr_plus3[2]),
.I1(wr_pntr_plus3[0]),
.I2(wr_pntr_plus3[1]),
.I3(wr_pntr_plus3[3]),
.I4(wr_pntr_plus3[4]),
.O(plusOp__1[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(wr_pntr_plus3[0]),
.Q(wr_pntr_plus2[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc1.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.D(wr_pntr_plus3[1]),
.PRE(wr_rst),
.Q(wr_pntr_plus2[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(wr_pntr_plus3[2]),
.Q(wr_pntr_plus2[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(wr_pntr_plus3[3]),
.Q(wr_pntr_plus2[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(wr_pntr_plus3[4]),
.Q(wr_pntr_plus2[4]));
FDPE #(
.INIT(1'b1))
\gic0.gc1.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.D(wr_pntr_plus2[0]),
.PRE(wr_rst),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(wr_pntr_plus2[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(wr_pntr_plus2[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(wr_pntr_plus2[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(wr_pntr_plus2[4]),
.Q(p_8_out));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d3_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(Q[0]),
.Q(\wr_pntr_gc_reg[4] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d3_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(Q[1]),
.Q(\wr_pntr_gc_reg[4] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d3_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(Q[2]),
.Q(\wr_pntr_gc_reg[4] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d3_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(Q[3]),
.Q(\wr_pntr_gc_reg[4] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_d3_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(p_8_out),
.Q(\wr_pntr_gc_reg[4] [4]));
FDPE #(
.INIT(1'b1))
\gic0.gc1.count_reg[0]
(.C(wr_clk),
.CE(E),
.D(plusOp__1[0]),
.PRE(wr_rst),
.Q(wr_pntr_plus3[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc1.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__1[1]),
.PRE(wr_rst),
.Q(wr_pntr_plus3[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(plusOp__1[2]),
.Q(wr_pntr_plus3[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(plusOp__1[3]),
.Q(wr_pntr_plus3[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc1.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(wr_rst),
.D(plusOp__1[4]),
.Q(wr_pntr_plus3[4]));
LUT6 #(
.INIT(64'h4141FF4141414141))
ram_full_i_i_1
(.I0(ram_full_i_i_2_n_0),
.I1(\rd_pntr_bin_reg[4] [3]),
.I2(Q[3]),
.I3(wr_en),
.I4(p_2_out),
.I5(comp2),
.O(ram_full_i));
LUT5 #(
.INIT(32'hFFFF6FF6))
ram_full_i_i_2
(.I0(\rd_pntr_bin_reg[4] [2]),
.I1(Q[2]),
.I2(\rd_pntr_bin_reg[4] [4]),
.I3(p_8_out),
.I4(ram_full_i_i_4_n_0),
.O(ram_full_i_i_2_n_0));
LUT4 #(
.INIT(16'h0009))
ram_full_i_i_3
(.I0(wr_pntr_plus2[3]),
.I1(\rd_pntr_bin_reg[4] [3]),
.I2(ram_full_i_i_5_n_0),
.I3(ram_full_i_i_6_n_0),
.O(comp2));
LUT4 #(
.INIT(16'h6FF6))
ram_full_i_i_4
(.I0(Q[1]),
.I1(\rd_pntr_bin_reg[4] [1]),
.I2(Q[0]),
.I3(\rd_pntr_bin_reg[4] [0]),
.O(ram_full_i_i_4_n_0));
LUT4 #(
.INIT(16'h6FF6))
ram_full_i_i_5
(.I0(wr_pntr_plus2[1]),
.I1(\rd_pntr_bin_reg[4] [1]),
.I2(wr_pntr_plus2[0]),
.I3(\rd_pntr_bin_reg[4] [0]),
.O(ram_full_i_i_5_n_0));
LUT4 #(
.INIT(16'h6FF6))
ram_full_i_i_6
(.I0(wr_pntr_plus2[4]),
.I1(\rd_pntr_bin_reg[4] [4]),
.I2(wr_pntr_plus2[2]),
.I3(\rd_pntr_bin_reg[4] [2]),
.O(ram_full_i_i_6_n_0));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module fifo_async_104x32_wr_logic
(full,
almost_full,
prog_full,
E,
Q,
wr_clk,
wr_rst,
wr_en,
\rd_pntr_bin_reg[4] );
output full;
output almost_full;
output prog_full;
output [0:0]E;
output [4:0]Q;
input wr_clk;
input wr_rst;
input wr_en;
input [4:0]\rd_pntr_bin_reg[4] ;
wire [0:0]E;
wire [4:0]Q;
wire almost_full;
wire comp2;
wire full;
wire \gwas.wsts_n_4 ;
wire p_2_out;
wire [3:0]p_8_out;
wire prog_full;
wire ram_full_i;
wire [4:0]\rd_pntr_bin_reg[4] ;
wire wpntr_n_0;
wire wpntr_n_1;
wire wpntr_n_16;
wire wpntr_n_2;
wire wpntr_n_7;
wire wpntr_n_8;
wire wr_clk;
wire wr_en;
wire wr_rst;
fifo_async_104x32_wr_pf_as \gwas.gpf.wrpf
(.S({wpntr_n_0,wpntr_n_1,wpntr_n_2}),
.\gic0.gc1.count_d2_reg[4] ({wpntr_n_7,wpntr_n_8}),
.p_2_out(p_2_out),
.prog_full(prog_full),
.wr_clk(wr_clk),
.wr_pntr_plus1_pad({p_8_out,\gwas.wsts_n_4 }),
.wr_rst(wr_rst));
fifo_async_104x32_wr_status_flags_as \gwas.wsts
(.E(E),
.almost_full(almost_full),
.comp2(comp2),
.full(full),
.p_2_out(p_2_out),
.ram_full_i(ram_full_i),
.\rd_pntr_bin_reg[3] (wpntr_n_16),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pad(\gwas.wsts_n_4 ),
.wr_rst(wr_rst));
fifo_async_104x32_wr_bin_cntr wpntr
(.E(E),
.Q(p_8_out),
.S({wpntr_n_0,wpntr_n_1,wpntr_n_2}),
.comp2(comp2),
.\gaf.ram_almost_full_i_reg (wpntr_n_16),
.\gdiff.diff_pntr_pad_reg[5] ({wpntr_n_7,wpntr_n_8}),
.p_2_out(p_2_out),
.ram_full_i(ram_full_i),
.\rd_pntr_bin_reg[4] (\rd_pntr_bin_reg[4] ),
.wr_clk(wr_clk),
.wr_en(wr_en),
.\wr_pntr_gc_reg[4] (Q),
.wr_rst(wr_rst));
endmodule
(* ORIG_REF_NAME = "wr_pf_as" *)
module fifo_async_104x32_wr_pf_as
(prog_full,
wr_clk,
wr_rst,
p_2_out,
wr_pntr_plus1_pad,
S,
\gic0.gc1.count_d2_reg[4] );
output prog_full;
input wr_clk;
input wr_rst;
input p_2_out;
input [4:0]wr_pntr_plus1_pad;
input [2:0]S;
input [1:0]\gic0.gc1.count_d2_reg[4] ;
wire [2:0]S;
wire \gdiff.diff_pntr_pad_reg[5]_i_1_n_3 ;
wire \gdiff.diff_pntr_pad_reg[5]_i_2_n_0 ;
wire \gdiff.diff_pntr_pad_reg[5]_i_2_n_1 ;
wire \gdiff.diff_pntr_pad_reg[5]_i_2_n_2 ;
wire \gdiff.diff_pntr_pad_reg[5]_i_2_n_3 ;
wire [1:0]\gic0.gc1.count_d2_reg[4] ;
wire \gpf1.prog_full_i_i_1_n_0 ;
wire p_2_out;
wire [5:0]plusOp;
wire prog_full;
wire prog_full_i;
wire wr_clk;
wire [4:0]wr_pntr_plus1_pad;
wire wr_rst;
wire [3:1]\NLW_gdiff.diff_pntr_pad_reg[5]_i_1_CO_UNCONNECTED ;
wire [3:2]\NLW_gdiff.diff_pntr_pad_reg[5]_i_1_O_UNCONNECTED ;
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(plusOp[5]),
.Q(prog_full_i));
CARRY4 \gdiff.diff_pntr_pad_reg[5]_i_1
(.CI(\gdiff.diff_pntr_pad_reg[5]_i_2_n_0 ),
.CO({\NLW_gdiff.diff_pntr_pad_reg[5]_i_1_CO_UNCONNECTED [3:1],\gdiff.diff_pntr_pad_reg[5]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,wr_pntr_plus1_pad[4]}),
.O({\NLW_gdiff.diff_pntr_pad_reg[5]_i_1_O_UNCONNECTED [3:2],plusOp[5:4]}),
.S({1'b0,1'b0,\gic0.gc1.count_d2_reg[4] }));
CARRY4 \gdiff.diff_pntr_pad_reg[5]_i_2
(.CI(1'b0),
.CO({\gdiff.diff_pntr_pad_reg[5]_i_2_n_0 ,\gdiff.diff_pntr_pad_reg[5]_i_2_n_1 ,\gdiff.diff_pntr_pad_reg[5]_i_2_n_2 ,\gdiff.diff_pntr_pad_reg[5]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(wr_pntr_plus1_pad[3:0]),
.O(plusOp[3:0]),
.S({S,1'b0}));
LUT3 #(
.INIT(8'hB8))
\gpf1.prog_full_i_i_1
(.I0(prog_full),
.I1(p_2_out),
.I2(prog_full_i),
.O(\gpf1.prog_full_i_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\gpf1.prog_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(\gpf1.prog_full_i_i_1_n_0 ),
.Q(prog_full));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module fifo_async_104x32_wr_status_flags_as
(full,
p_2_out,
almost_full,
E,
wr_pntr_plus1_pad,
ram_full_i,
wr_clk,
wr_rst,
wr_en,
comp2,
\rd_pntr_bin_reg[3] );
output full;
output p_2_out;
output almost_full;
output [0:0]E;
output [0:0]wr_pntr_plus1_pad;
input ram_full_i;
input wr_clk;
input wr_rst;
input wr_en;
input comp2;
input \rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire almost_full;
wire comp2;
wire full;
wire \gaf.ram_almost_full_i_i_1_n_0 ;
wire p_2_out;
wire ram_full_i;
wire \rd_pntr_bin_reg[3] ;
wire wr_clk;
wire wr_en;
wire [0:0]wr_pntr_plus1_pad;
wire wr_rst;
LUT4 #(
.INIT(16'hBBB8))
\gaf.ram_almost_full_i_i_1
(.I0(almost_full),
.I1(p_2_out),
.I2(comp2),
.I3(\rd_pntr_bin_reg[3] ),
.O(\gaf.ram_almost_full_i_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\gaf.ram_almost_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(\gaf.ram_almost_full_i_i_1_n_0 ),
.Q(almost_full));
LUT2 #(
.INIT(4'h2))
\gdiff.diff_pntr_pad[5]_i_5
(.I0(wr_en),
.I1(p_2_out),
.O(wr_pntr_plus1_pad));
LUT2 #(
.INIT(4'h2))
\gic0.gc1.count_d1[4]_i_1
(.I0(wr_en),
.I1(p_2_out),
.O(E));
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(ram_full_i),
.Q(p_2_out));
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.CLR(wr_rst),
.D(ram_full_i),
.Q(full));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module SevenSegmentLED(
i_data,
o_a,
o_b,
o_c,
o_d,
o_e,
o_f,
o_g);
input [3:0] i_data;
output o_a;
output o_b;
output o_c;
output o_d;
output o_e;
output o_f;
output o_g;
wire [6:0] w_out;
function [6:0] Decode;
input [3:0] data;
begin
case (i_data)
4'h0: Decode = 7'b0000001;
4'h1: Decode = 7'b1001111;
4'h2: Decode = 7'b0010010;
4'h3: Decode = 7'b0000110;
4'h4: Decode = 7'b1001100;
4'h5: Decode = 7'b0100100;
4'h6: Decode = 7'b0100000;
4'h7: Decode = 7'b0001111;
4'h8: Decode = 7'b0000000;
4'h9: Decode = 7'b0000100;
4'ha: Decode = 7'b0001000;
4'hb: Decode = 7'b1100000;
4'hc: Decode = 7'b0110001;
4'hd: Decode = 7'b1000010;
4'he: Decode = 7'b0110000;
4'hf: Decode = 7'b0111000;
endcase
end
endfunction // Decode
assign w_out = Decode(i_data);
assign o_a = w_out[6];
assign o_b = w_out[5];
assign o_c = w_out[4];
assign o_d = w_out[3];
assign o_e = w_out[2];
assign o_f = w_out[1];
assign o_g = w_out[0];
endmodule // SevenSegmentLED
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:01:19 01/02/2014
// Design Name: qmults
// Module Name: F:/FixedPoint/TestMultS.v
// Project Name: FixedPoint
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: qmults
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestMultS;
// Inputs
reg [31:0] i_multiplicand;
reg [31:0] i_multiplier;
reg i_start;
reg i_clk;
// Outputs
wire [31:0] o_result_out;
wire o_complete;
wire o_overflow;
// Instantiate the Unit Under Test (UUT)
qmults uut (
.i_multiplicand(i_multiplicand),
.i_multiplier(i_multiplier),
.i_start(i_start),
.i_clk(i_clk),
.o_result_out(o_result_out),
.o_complete(o_complete),
.o_overflow(o_overflow)
);
reg [10:0] count;
initial begin
// Initialize Inputs
i_multiplicand = 0;
i_multiplier = 0;
i_start = 0;
i_clk = 0;
count = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
forever #2 i_clk = ~i_clk;
end
always @(posedge i_clk) begin
if (count == 47) begin
count <= 0;
i_start <= 1'b1;
end
else begin
count <= count + 1;
i_start <= 1'b0;
end
end
always @(count) begin
if (count == 47) begin
if ( i_multiplier > 32'h1FFFFFFF ) begin
i_multiplier <= 1;
i_multiplicand = (i_multiplicand << 1) + 3;
end
else
i_multiplier = (i_multiplier << 1) + 1;
end
end
always @(posedge o_complete)
$display ("%b,%b,%b,%b", i_multiplicand, i_multiplier, o_result_out, o_overflow); // Monitor the stuff we care about
endmodule
|
module flash_default_tester (
//CONTROL//
input iBUSSW ,
input iTRIKEY ,
input iDEFAULT,
input iCLK_28,
//FL
inout [14:0] FLASH_DQ,
inout FLASH_DQ15_AM1,
output [25:0] oFLASH_A,
output oFLASH_WE_N,
output oFLASH_RST_N,
output oFLASH_WP_N,
input iFLASH_RY_N,
output oFLASH_BYTE_N,
output oFLASH_OE_N,
output oFLASH_CE_N,
output oLCD_ON ,
output oLCD_BLON,
output [7:0] LCD_D,
output oLCD_RW,
output oLCD_EN,
output oLCD_RS,
input iLCD_ON_1 ,
input iLCD_BLON_1,
input [7:0] LCD_D_1,
input iLCD_RW_1,
input iLCD_EN_1,
input iLCD_RS_1,
//TEST PIN//
output TIME_OUT,
output oSTATUS,
output oEND,
output oERASE_STATUS,
output PROG,
output READ,
output ERASE,
output RESET,
output VERIFY_TIME
);
// LCD BUS //
assign oLCD_ON = (LCD_BUS)? oLCD_ON_2 :iLCD_ON_1;
assign oLCD_BLON= (LCD_BUS)? oLCD_BLON_2:iLCD_BLON_1;
assign LCD_D = (LCD_BUS)? LCD_D_2 :LCD_D_1;
assign oLCD_RW = (LCD_BUS)? oLCD_RW_2 :iLCD_RW_1;
assign oLCD_EN = (LCD_BUS)? oLCD_EN_2 :iLCD_EN_1;
assign oLCD_RS = (LCD_BUS)? oLCD_RS_2 :iLCD_RS_1;
// LED DISP //
assign TIME_OUT = timer_1[33] ;
// TimeOUT //
reg [33:0] timer_1;
// Power Up Trigger //
reg [25:0]power_delay ;
reg FLASH_TEST_tr ;
reg LCD_BUS ;
always @( negedge iDEFAULT or posedge iCLK_28 )begin
if (!iDEFAULT ) begin
power_delay = 0;
FLASH_TEST_tr = 1;
LCD_BUS = 0;
timer_1 =34'h3ffffffff;
end
else
begin
if ( !power_delay[25] ) begin
power_delay = power_delay + 1;
FLASH_TEST_tr = iTRIKEY ;
if ( !FLASH_TEST_tr ) begin LCD_BUS = 1; timer_1 =0; end
end
else begin
FLASH_TEST_tr = 1;
if ( !TIME_OUT ) timer_1 = timer_1 + 1;
if ( !iBUSSW ) LCD_BUS = 0;
end
end
end
wire OK ;
wire FAIL ;
wire [21:0]flash_addr ;
wire [3:0]flash_cmd ;
DE2_70_flash_word_tester tester(
.TIME_OUT(TIME_OUT),
.iCLK_28 ( iCLK_28 ),
.iSTART ( FLASH_TEST_tr ),
.oEND ( oEND),
.oERASE_STATUS(oERASE_STATUS),
.oSTATUS (oSTATUS),
.FLASH_DQ (FLASH_DQ ),
.FLASH_DQ15_AM1(FLASH_DQ15_AM1),
.oFLASH_A (oFLASH_A ),
.oFLASH_WE_N (oFLASH_WE_N ),
.oFLASH_RST_N (oFLASH_RST_N ),
.oFLASH_WP_N (oFLASH_WP_N ),
.iFLASH_RY_N (iFLASH_RY_N ),
.oFLASH_BYTE_N (oFLASH_BYTE_N ),
.oFLASH_OE_N (oFLASH_OE_N ),
.oFLASH_CE_N (oFLASH_CE_N ),
//TEST//
.ERASE (ERASE ),
.PROG (PROG ),
.READ (READ ),
.RESET (RESET ),
.OK (OK ),
.FAIL(FAIL),
.VERIFY_TIME(VERIFY_TIME),
.flash_addr (flash_addr ),
.flash_cmd (flash_cmd )
);
// FLASH ROM DATA //
reg [15:0]rn;
always @(posedge oFLASH_OE_N) rn={ FLASH_DQ15_AM1 , FLASH_DQ };
//////text to LCD/////////
wire [7:0] txt1;
wire [7:0] txt2;
wire [7:0] txt3;
wire [7:0] txt4;
wire [7:0] txt5;
wire [7:0] txt6;
wire [7:0] txt7;
assign {txt1[7:0],txt2[7:0],txt3[7:0],txt4[7:0],txt5[7:0],txt6[7:0],txt7[7:0]}=(
(flash_cmd==4)?{8'h20,8'h65,8'h72,8'h61,8'h73,8'h65,8'h2E}:( //"erase."//
(flash_cmd==1)?{8'h20,8'h77,8'h72,8'h69,8'h74,8'h65,8'h2E}:( //"write."//
(flash_cmd==0)?{8'h20,8'h72,8'h65,8'h61,8'h64,8'h2E,8'h2E}:( //"read.."//
(flash_cmd==7)?{8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20}:( //"reset."//
(flash_cmd==8)?{8'h2D,8'h4F,8'h4B,8'h21,8'h2D,8'h2E,8'h20}:( //"-OK!-."//
(flash_cmd==9)?{8'h2D,8'h46,8'h41,8'h49,8'h4C,8'h2D,8'h20}:0 //"-Fail-"//
)))))
);
wire lcd_res= ~ERASE & ~PROG & ~READ & ~RESET & ~OK & ~FAIL;
wire oLCD_ON_2 =1;
wire oLCD_BLON_2=1;
wire [7:0]LCD_D_2 ;
wire oLCD_RW_2 ;
wire oLCD_EN_2 ;
wire oLCD_RS_2 ;
LCD L(
.txt1(txt1),
.txt2(txt2),
.txt3(txt3),
.txt4(txt4),
.txt5(txt5),
.txt6(txt6),
.txt7(txt7),
.iCLK(iCLK_28),
.iRST_N(lcd_res),
.keded(0),
.LCD_DATA(LCD_D_2 ),
.LCD_RW (oLCD_RW_2),
.LCD_EN (oLCD_EN_2),
.LCD_RS (oLCD_RS_2),
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NOR2B_FUNCTIONAL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor2b (
Y ,
A ,
B_N
);
// Module ports
output Y ;
input A ;
input B_N;
// Local signals
wire not0_out ;
wire and0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y, not0_out, B_N );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_4_V
`define SKY130_FD_SC_HD__O31AI_4_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31ai_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NOR2B_FUNCTIONAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor2b (
VPWR,
VGND,
Y ,
A ,
B_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B_N ;
// Local signals
wire Y not0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_FUNCTIONAL_PP_V |
module digital_sound_output (
input clk,
input rst,
input enabled,
input[15:0] left,
input[15:0] right,
output bck,
output sd,
output lrck,
output consume
);
parameter CLK_FREQUENCY = 33868800;
localparam BCK_HALF_PERIOD = (CLK_FREQUENCY / 44100 / 64 / 2);
function integer log2;
input integer value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
reg [log2(BCK_HALF_PERIOD)-1:0] bck_counter_d, bck_counter_q;
reg bck_d, bck_q;
reg sd_d, sd_q;
reg lrck_d, lrck_q;
reg bit_active_d, bit_active_q;
reg [5:0] bit_counter_d, bit_counter_q;
reg [31:0] shiftreg_d, shiftreg_q;
reg consume_d, consume_q;
assign bck = bck_q;
assign sd = sd_q;
assign lrck = lrck_q;
assign consume = consume_q;
always @(*) begin
if (enabled) begin
if (bck_counter_q == BCK_HALF_PERIOD-1) begin
bck_counter_d = 0;
bck_d = ~bck_q;
end else begin
bck_counter_d = bck_counter_q + 1;
bck_d = bck_q;
end
end else begin
bck_counter_d = 0;
bck_d = bck_q;
end
if ((bck_counter_q == BCK_HALF_PERIOD-2) & bck_q & enabled)
bit_active_d = 1'b1;
else
bit_active_d = 1'b0;
shiftreg_d = (enabled? shiftreg_q : 32'h00000000);
consume_d = 1'b0;
if (bit_active_q) begin
if (bit_counter_q[4]) begin
sd_d = shiftreg_q[31];
shiftreg_d = {shiftreg_q[30:0],1'b0};
end else begin
sd_d = 1'b0;
if (bit_counter_q == 0) begin
shiftreg_d = {left, right};
consume_d = 1'b1;
end
end
lrck_d = ~bit_counter_q[5];
bit_counter_d = bit_counter_q+1;
end else begin
sd_d = sd_q;
lrck_d = lrck_q;
bit_counter_d = bit_counter_q;
end
end
always @(posedge clk) begin
if (rst) begin
bck_counter_q <= 0;
bck_q <= 1'b0;
sd_q <= 1'b0;
lrck_q <= 1'b0;
bit_active_q <= 1'b0;
bit_counter_q <= 5'b00000;
shiftreg_q <= 32'h00000000;
consume_q <= 1'b0;
end else begin
bck_counter_q <= bck_counter_d;
bck_q <= bck_d;
sd_q <= sd_d;
lrck_q <= lrck_d;
bit_active_q <= bit_active_d;
bit_counter_q <= bit_counter_d;
shiftreg_q <= shiftreg_d;
consume_q <= consume_d;
end
end
endmodule // digital_sound_output
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_DIODE_2_V
`define SKY130_FD_SC_HS__FILL_DIODE_2_V
/**
* fill_diode: Fill diode.
*
* Verilog wrapper for fill_diode with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fill_diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_diode_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hs__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_diode_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hs__fill_diode base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_DIODE_2_V
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The module for debug ROM program
//
// ====================================================================
module sirv_debug_rom(
input [7-1:2] rom_addr,
output [32-1:0] rom_dout
);
// These ROM contents support only RV32
// See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
// The code assumes only 28 bytes of Debug RAM.
// def xlen32OnlyRomContents : Array[Byte] = Array(
// 0x6f, 0x00, 0xc0, 0x03, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
// 0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
// 0x83, 0x24, 0x80, 0x41, 0x23, 0x2c, 0x80, 0x40, 0x73, 0x24, 0x40, 0xf1,
// 0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00,
// 0x63, 0x1a, 0x04, 0x02, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
// 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
// 0x13, 0x04, 0x04, 0xf4, 0x63, 0x16, 0x04, 0x00, 0x23, 0x2c, 0x90, 0x40,
// 0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
// 0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
// 0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfe).map(_.toByte)
wire [31:0] debug_rom [0:28]; // 29 words in total
assign rom_dout = debug_rom[rom_addr];
// 0x6f, 0x00, 0xc0, 0x03, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
assign debug_rom[ 0][7 : 0] = 8'h6f;
assign debug_rom[ 0][15: 8] = 8'h00;
assign debug_rom[ 0][23:16] = 8'hc0;
assign debug_rom[ 0][31:24] = 8'h03;
assign debug_rom[ 1][7 : 0] = 8'h6f;
assign debug_rom[ 1][15: 8] = 8'h00;
assign debug_rom[ 1][23:16] = 8'hc0;
assign debug_rom[ 1][31:24] = 8'h00;
assign debug_rom[ 2][7 : 0] = 8'h13;
assign debug_rom[ 2][15: 8] = 8'h04;
assign debug_rom[ 2][23:16] = 8'hf0;
assign debug_rom[ 2][31:24] = 8'hff;
// 0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
assign debug_rom[ 3][7 : 0] = 8'h6f;
assign debug_rom[ 3][15: 8] = 8'h00;
assign debug_rom[ 3][23:16] = 8'h80;
assign debug_rom[ 3][31:24] = 8'h00;
assign debug_rom[ 4][7 : 0] = 8'h13;
assign debug_rom[ 4][15: 8] = 8'h04;
assign debug_rom[ 4][23:16] = 8'h00;
assign debug_rom[ 4][31:24] = 8'h00;
assign debug_rom[ 5][7 : 0] = 8'h0f;
assign debug_rom[ 5][15: 8] = 8'h00;
assign debug_rom[ 5][23:16] = 8'hf0;
assign debug_rom[ 5][31:24] = 8'h0f;
// 0x83, 0x24, 0x80, 0x41, 0x23, 0x2c, 0x80, 0x40, 0x73, 0x24, 0x40, 0xf1,
assign debug_rom[ 6][7 : 0] = 8'h83;
assign debug_rom[ 6][15: 8] = 8'h24;
assign debug_rom[ 6][23:16] = 8'h80;
assign debug_rom[ 6][31:24] = 8'h41;
assign debug_rom[ 7][7 : 0] = 8'h23;
assign debug_rom[ 7][15: 8] = 8'h2c;
assign debug_rom[ 7][23:16] = 8'h80;
assign debug_rom[ 7][31:24] = 8'h40;
assign debug_rom[ 8][7 : 0] = 8'h73;
assign debug_rom[ 8][15: 8] = 8'h24;
assign debug_rom[ 8][23:16] = 8'h40;
assign debug_rom[ 8][31:24] = 8'hf1;
// 0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00,
assign debug_rom[ 9][7 : 0] = 8'h23;
assign debug_rom[ 9][15: 8] = 8'h20;
assign debug_rom[ 9][23:16] = 8'h80;
assign debug_rom[ 9][31:24] = 8'h10;
assign debug_rom[10][7 : 0] = 8'h73;
assign debug_rom[10][15: 8] = 8'h24;
assign debug_rom[10][23:16] = 8'h00;
assign debug_rom[10][31:24] = 8'h7b;
assign debug_rom[11][7 : 0] = 8'h13;
assign debug_rom[11][15: 8] = 8'h74;
assign debug_rom[11][23:16] = 8'h84;
assign debug_rom[11][31:24] = 8'h00;
// 0x63, 0x1a, 0x04, 0x02, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
assign debug_rom[12][7 : 0] = 8'h63;
assign debug_rom[12][15: 8] = 8'h1a;
assign debug_rom[12][23:16] = 8'h04;
assign debug_rom[12][31:24] = 8'h02;
assign debug_rom[13][7 : 0] = 8'h73;
assign debug_rom[13][15: 8] = 8'h24;
assign debug_rom[13][23:16] = 8'h20;
assign debug_rom[13][31:24] = 8'h7b;
assign debug_rom[14][7 : 0] = 8'h73;
assign debug_rom[14][15: 8] = 8'h00;
assign debug_rom[14][23:16] = 8'h20;
assign debug_rom[14][31:24] = 8'h7b;
// 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
assign debug_rom[15][7 : 0] = 8'h73;
assign debug_rom[15][15: 8] = 8'h10;
assign debug_rom[15][23:16] = 8'h24;
assign debug_rom[15][31:24] = 8'h7b;
assign debug_rom[16][7 : 0] = 8'h73;
assign debug_rom[16][15: 8] = 8'h24;
assign debug_rom[16][23:16] = 8'h00;
assign debug_rom[16][31:24] = 8'h7b;
assign debug_rom[17][7 : 0] = 8'h13;
assign debug_rom[17][15: 8] = 8'h74;
assign debug_rom[17][23:16] = 8'h04;
assign debug_rom[17][31:24] = 8'h1c;
// 0x13, 0x04, 0x04, 0xf4, 0x63, 0x16, 0x04, 0x00, 0x23, 0x2c, 0x90, 0x40,
assign debug_rom[18][7 : 0] = 8'h13;
assign debug_rom[18][15: 8] = 8'h04;
assign debug_rom[18][23:16] = 8'h04;
assign debug_rom[18][31:24] = 8'hf4;
assign debug_rom[19][7 : 0] = 8'h63;
assign debug_rom[19][15: 8] = 8'h16;
assign debug_rom[19][23:16] = 8'h04;
assign debug_rom[19][31:24] = 8'h00;
assign debug_rom[20][7 : 0] = 8'h23;
assign debug_rom[20][15: 8] = 8'h2c;
assign debug_rom[20][23:16] = 8'h90;
assign debug_rom[20][31:24] = 8'h40;
// 0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
assign debug_rom[21][7 : 0] = 8'h67;
assign debug_rom[21][15: 8] = 8'h00;
assign debug_rom[21][23:16] = 8'h00;
assign debug_rom[21][31:24] = 8'h40;
assign debug_rom[22][7 : 0] = 8'h73;
assign debug_rom[22][15: 8] = 8'h24;
assign debug_rom[22][23:16] = 8'h40;
assign debug_rom[22][31:24] = 8'hf1;
assign debug_rom[23][7 : 0] = 8'h23;
assign debug_rom[23][15: 8] = 8'h26;
assign debug_rom[23][23:16] = 8'h80;
assign debug_rom[23][31:24] = 8'h10;
// 0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
assign debug_rom[24][7 : 0] = 8'h73;
assign debug_rom[24][15: 8] = 8'h60;
assign debug_rom[24][23:16] = 8'h04;
assign debug_rom[24][31:24] = 8'h7b;
assign debug_rom[25][7 : 0] = 8'h73;
assign debug_rom[25][15: 8] = 8'h24;
assign debug_rom[25][23:16] = 8'h00;
assign debug_rom[25][31:24] = 8'h7b;
assign debug_rom[26][7 : 0] = 8'h13;
assign debug_rom[26][15: 8] = 8'h74;
assign debug_rom[26][23:16] = 8'h04;
assign debug_rom[26][31:24] = 8'h02;
// 0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfe).map(_.toByte)
assign debug_rom[27][7 : 0] = 8'he3;
assign debug_rom[27][15: 8] = 8'h0c;
assign debug_rom[27][23:16] = 8'h04;
assign debug_rom[27][31:24] = 8'hfe;
assign debug_rom[28][7 : 0] = 8'h6f;
assign debug_rom[28][15: 8] = 8'hf0;
assign debug_rom[28][23:16] = 8'h1f;
assign debug_rom[28][31:24] = 8'hfe;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22O_TB_V
`define SKY130_FD_SC_HVL__A22O_TB_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__a22o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hvl__a22o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22O_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:18:40 03/03/2016
// Design Name:
// Module Name: register
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module register(clock_in, readReg1,readReg2, writeReg,writeData,regWrite,readData1,readData2);
input clock_in;
input [25:21] readReg1;
input [20:16] readReg2;
input [4:0] writeReg;
input [31:0] writeData;
input regWrite;
output [31:0] readData1;
output [31:0] readData2;
reg[31:0] regFile[31:0];
reg[31:0] readData1;
reg[31:0] readData2;
integer i;
initial //³õʼ»¯
begin
for(i = 0; i < 32; i = i + 1)
regFile[i] = 0;
readData1 = 0;
readData2 = 0;
end
always @ (readReg1 or readReg2) //Ïò¼Ä´æÆ÷¶ÁÊý¾Ý
begin
readData1 = regFile[readReg1];
readData2 = regFile[readReg2];
end
always @ (negedge clock_in) //Ïò¼Ä´æÆ÷дÊý¾Ý
begin
if(regWrite)
regFile[writeReg] = writeData;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_SYMBOL_V
`define SKY130_FD_SC_HDLL__A21O_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXBP_TB_V
`define SKY130_FD_SC_HD__SEDFXBP_TB_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sedfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 DE = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 DE = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 DE = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 DE = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sedfxbp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXBP_TB_V
|
Require Import GeoCoq.Axioms.continuity_axioms.
Require Import GeoCoq.Meta_theory.Dimension_axioms.upper_dim_2.
Require Import GeoCoq.Meta_theory.Dimension_axioms.upper_dim_3.
Require Import GeoCoq.Meta_theory.Continuity.grad.
Section Extension.
Context `{TnEQD:Tarski_neutral_dimensionless_with_decidable_point_equality}.
Lemma line_extension_symmetry : forall {Tm : Tarski_neutral_dimensionless}
(f : @Tpoint Tn -> @Tpoint Tm) P Q, line_extension f P Q -> line_extension f Q P.
Proof.
intros Tm f P Q [HPQ [fInj [fBet fCong]]].
repeat split; auto; intro; intros; [apply fInj|apply fBet|apply fCong]; Col.
Qed.
Lemma line_extension_stability : forall {Tm: Tarski_neutral_dimensionless}
(f : @Tpoint Tn -> @Tpoint Tm) P Q R,
Col P Q R -> P <> R -> line_extension f P Q -> line_extension f P R.
Proof.
intros Tm f P Q R HCol HPR [HPQ [fInj [fBet fCong]]].
repeat split; auto; intro; intros;
[apply fInj|apply fBet|apply fCong]; trivial; apply col_transitivity_1 with R; Col.
Qed.
Lemma line_extension_reverse_bet : forall {Tm: Tarski_neutral_dimensionless}
(f : @Tpoint Tn -> @Tpoint Tm) P Q, line_extension f P Q ->
forall A B C, Col P Q A -> Col P Q B -> Col P Q C -> Bet (f A) (f B) (f C) -> Bet A B C.
Proof.
intros Tm f P Q [HPQ [fInj [fBet fCong]]] A B C HA HB HC HBet.
assert (HCol : Col A B C) by (apply (col3 P Q); assumption).
destruct HCol as [|[HBet'|HBet']]; trivial;
[assert (B = C)|assert (A = B)]; try (subst B; Between);
apply fInj; trivial;
[apply between_equality with (f A)|apply between_equality with (f C)]; Between.
Qed.
Lemma pres_bet_line__col : forall {Tm: Tarski_neutral_dimensionless}
(f : @Tpoint Tn -> @Tpoint Tm) P Q, P <> Q -> pres_bet_line f P Q ->
forall A B C, Col P Q A -> Col P Q B -> Col P Q C -> Col (f A) (f B) (f C).
Proof.
intros Tm f P Q HPQ fBet A B C HA HB HC.
destruct (col3 P Q A B C) as [HBet|[HBet|HBet]]; trivial; apply fBet in HBet; Col.
Qed.
Lemma col2_diff_inj_line__diff : forall {Tm: Tarski_neutral_dimensionless}
(f : @Tpoint Tn -> @Tpoint Tm) P Q, inj_line f P Q ->
forall A B, Col P Q A -> Col P Q B -> A <> B -> f A <> f B.
Proof.
intros Tm f P Q finj A B HA HB HAB Habs.
apply HAB, finj; assumption.
Qed.
Lemma extension__line_extension : forall {Tm: Tarski_neutral_dimensionless}
(f : @Tpoint Tn -> @Tpoint Tm) P Q,
P <> Q -> extension f -> line_extension f P Q.
Proof.
unfold extension, inj, pres_bet, pres_cong, line_extension, inj_line, pres_bet_line, pres_cong_line.
intros Tm f P Q HPQ fext; spliter.
repeat split; auto.
Qed.
Lemma extension_reverse_bet : forall {Tm: Tarski_neutral_dimensionless}
{Tm2 : Tarski_neutral_dimensionless_with_decidable_point_equality Tm}
(f : @Tpoint Tn -> @Tpoint Tm),
extension f ->
forall A B C, Bet (f A) (f B) (f C) -> Bet A B C.
Proof.
intros Tm Tm2 f [finj [fBet fCong]] A B C HBet.
destruct (eq_dec_points (f A) (f B)) as [Heq|].
apply finj in Heq; subst; Between.
destruct (segment_construction A B B C) as [D [HD1 HD2]].
assert (C = D); [|subst; auto].
apply finj.
apply between_cong_3 with (f A) (f B); Cong.
Qed.
Lemma extension_reverse_col : forall {Tm: Tarski_neutral_dimensionless}
{Tm2 : Tarski_neutral_dimensionless_with_decidable_point_equality Tm}
(f : @Tpoint Tn -> @Tpoint Tm),
extension f ->
forall A B C, Col (f A) (f B) (f C) -> Col A B C.
Proof.
unfold Col.
intros Tm Tm2 f fext A B C HCol.
assert (fBetInv := extension_reverse_bet f fext).
destruct HCol as [|[|]]; auto.
Qed.
End Extension.
(** The following section is inspired by Theorem 32 of Hilbert's Foundations of Geometry (10th edition).
It deduces completeness of a 2 or 3-dimensional space from completeness of lines.
The original proof is due to Paul Bernays. *)
Section Completeness.
Context `{TnEQD:Tarski_neutral_dimensionless_with_decidable_point_equality}.
Lemma line_completeness_aux : line_completeness ->
forall (Tm: Tarski_neutral_dimensionless)
(Tm2 : Tarski_neutral_dimensionless_with_decidable_point_equality Tm)
(f : @Tpoint Tn -> @Tpoint Tm),
@archimedes_axiom Tm ->
extension f ->
forall A P Q R, ~ Col P Q R -> Coplanar (f P) (f Q) (f R) A ->
exists B, Coplanar P Q R B /\ f B = A.
Proof.
intros lc Tm Tm2 f archi fext A P Q R HNCol HCop.
assert (fext' := fext).
assert (Haux : forall X Y, X <> Y -> line_extension f X Y).
intros; apply extension__line_extension; assumption.
unfold extension, inj, pres_bet, pres_cong in fext'; spliter.
destruct (@midpoint_existence Tn TnEQD P Q) as [S HS].
assert_diffs.
destruct (col_dec (f R) (f S) A).
{ assert (HB : exists B, Col R S B /\ f B = A).
assert (R <> S) by (intro; subst; apply HNCol; Col).
apply lc; auto.
destruct HB as [B []].
exists B; split; [exists S; left; split|]; Col.
}
destruct (col_dec (f P) (f Q) A).
{ assert (HB : exists B, Col P Q B /\ f B = A) by (apply lc; auto).
destruct HB as [B []].
exists B; split; Cop.
}
destruct (hilbert_s_version_of_pasch (f P) (f Q) (f R) A (f S)) as [X [HX1 HX2]]; trivial.
repeat split; Between.
assert (HY : exists Y, Coplanar P Q R Y /\ f Y = X).
{ destruct HX2 as [[]|[]];
[assert (HY : exists Y, Col P R Y /\ f Y = X)|assert (HY : exists Y, Col Q R Y /\ f Y = X)];
try apply lc; Col;
destruct HY as [Y []]; exists Y; split; Cop.
}
destruct HY as [Y []].
subst X.
assert (S <> Y).
{ intro; treat_equalities.
apply HNCol.
apply (extension_reverse_col f); auto.
assert (Bet P S Q) by Between.
assert (Bet (f P) (f S) (f Q)) by auto.
destruct HX2 as [[HBet []]|[HBet []]];
[|apply col_permutation_4]; apply (col_transitivity_2 (f S)); Col.
}
assert (HB : exists B, Col S Y B /\ f B = A) by (apply lc; Col).
destruct HB as [B []].
exists B.
split; [apply col_cop2__cop with S Y|]; Cop.
Qed.
Lemma line_completeness__completeness_for_planes : line_completeness -> completeness_for_planes.
Proof.
intros lc Tm Tm2 M f archi fext A.
assert (HB : exists B, Coplanar PA PB PC B /\ f B = A).
apply line_completeness_aux; trivial; [exact lower_dim|apply all_coplanar].
destruct HB as [B []].
exists B; assumption.
Qed.
Lemma line_completeness__completeness_for_3d_spaces :
(exists P Q R S, ~ Coplanar P Q R S) ->
line_completeness -> completeness_for_3d_spaces.
Proof.
intros [P [Q [R [S HNCop]]]] lc Tm Tm2 M f archi fext A.
assert (~ Col P Q R) by (apply ncop__ncol with S, HNCop).
assert (Haux : forall X, (exists B, Coplanar P Q X B /\ f B = A) -> exists B, f B = A).
intros X [B []]; exists B; assumption.
destruct (col_dec (f P) (f Q) A).
apply (Haux R), line_completeness_aux; Cop.
assert (pi : plane_intersection_axiom).
{ cut upper_dim_3_axiom.
apply upper_dim_3_equivalent_axioms; simpl; tauto.
unfold upper_dim_3_axiom; exact upper_dim_3.
}
destruct (pi (f P) (f Q) A (f P) (f R) (f S) (f P)) as [X [HX1 [HX2 HX3]]]; Cop.
assert (HY : exists Y, Coplanar P R S Y /\ f Y = X).
apply line_completeness_aux; trivial; apply ncop__ncol with Q; Cop.
destruct HY as [Y []]; subst.
apply (Haux Y), line_completeness_aux; Cop.
intro.
apply HNCop.
apply coplanar_perm_16, col_cop__cop with Y; Col; Cop.
intro; subst; apply HX3; reflexivity.
Qed.
End Completeness.
(** In the following section, we prove that our formalizations of
Hilbert's axiom of completeness
are always true in spaces with dimension respectively greater than 2 and 3.
The next one states the contrapositive lemmas. *)
Section Dimension.
Context `{Tn:Tarski_neutral_dimensionless}.
Lemma extension_to_plane__plane : forall {Tm: Tarski_neutral_dimensionless}
{Tm2 : Tarski_neutral_dimensionless_with_decidable_point_equality Tm}
{M : Tarski_2D Tm2}
(f : @Tpoint Tn -> @Tpoint Tm),
extension f ->
@upper_dim_axiom Tn.
Proof.
intros Tm Tm2 M f fext A B C P Q HPQ H1 H2 H3.
apply (extension_reverse_col f); trivial.
unfold extension, inj, pres_cong in fext; spliter.
unfold Col; apply upper_dim with (f P) (f Q); auto.
Qed.
Lemma nupper_dim__completeness_for_planes : ~ upper_dim_axiom -> completeness_for_planes.
Proof.
intros lowerdim Tm Tm2 M f archi fext A.
exfalso; apply lowerdim.
apply extension_to_plane__plane with f; trivial.
Qed.
Lemma extension_to_3d__upper_dim_3 : forall {Tm: Tarski_neutral_dimensionless}
{Tm2 : Tarski_neutral_dimensionless_with_decidable_point_equality Tm}
{M : Tarski_3D Tm2}
(f : @Tpoint Tn -> @Tpoint Tm),
extension f ->
@upper_dim_3_axiom Tn.
Proof.
intros Tm Tm2 M f fext A B C P Q R; intros.
apply (extension_reverse_col f); trivial.
unfold extension, inj, pres_cong in fext; spliter.
unfold Col; apply upper_dim_3 with (f P) (f Q) (f R); auto.
Qed.
Lemma nupper_dim_3__completeness_for_3d_spaces : ~ upper_dim_3_axiom -> completeness_for_3d_spaces.
Proof.
intros lowerdim Tm Tm2 M f archi fext A.
exfalso; apply lowerdim.
apply extension_to_3d__upper_dim_3 with f; trivial.
Qed.
End Dimension.
Section Dimension'.
Context `{TnEQD:Tarski_neutral_dimensionless_with_decidable_point_equality}.
Lemma ncompleteness_for_planes__upper_dim : ~ completeness_for_planes -> upper_dim_axiom.
Proof.
intro nc.
apply upper_dim_stab.
intro nupper.
apply nc, (nupper_dim__completeness_for_planes nupper).
Qed.
Lemma ncompleteness_for_3d_spaces__upper_dim_3 : ~ completeness_for_3d_spaces -> upper_dim_3_axiom.
Proof.
intro nc.
apply upper_dim_3_stab.
intro nupper.
apply nc, (nupper_dim_3__completeness_for_3d_spaces nupper).
Qed.
End Dimension'.
(** In the following section, we prove that Hilbert's axiom of line completeness
is always true in non-archimedean spaces. *)
Section Archimedes.
Context `{TnEQD:Tarski_neutral_dimensionless_with_decidable_point_equality}.
Lemma archimedes_aux : forall P Q,
(forall R S, Bet P Q R -> Bet P Q S -> Q <> R -> Reach Q R Q S) -> archimedes_axiom.
Proof.
intros P Q Haux A B C D HAB.
destruct (segment_construction P Q A B) as [R []].
destruct (segment_construction P Q C D) as [S []].
destruct (Haux R S) as [R' [HGrad HLe]]; Col.
intro; treat_equalities; auto.
assert (Bet Q R R') by (apply grad__bet, HGrad).
assert (HB' : Le A B Q R') by (apply le_transitivity with Q R; Le).
apply l5_5_1 in HB'.
destruct HB' as [B' []].
exists B'; split.
apply (grad2__grad456 Q R R'), bet_cong2_grad__grad2; trivial.
apply l4_3_1 with Q A; Cong.
apply (l5_6 Q S Q R'); Cong.
Qed.
Lemma not_archimedes__line_completeness : ~ archimedes_axiom -> line_completeness.
Proof.
intros narchi Tm Tm2 P Q f archi Hf.
assert (Hf' := Hf).
destruct Hf' as [HPQ [finj [fBet fCong]]].
assert (Haux := col2_diff_inj_line__diff f P Q finj).
exfalso.
apply narchi, (archimedes_aux P Q).
intros R S HR HS HQR.
remember (f Q) as Q'.
remember (f R) as R'.
remember (f S) as S'.
destruct (archi Q' R' Q' S') as [R0' [HGrad HLe]].
subst; intro; apply HQR, finj; Col.
assert (HBet : Bet Q' S' R0').
{ destruct (eq_dec_points Q S); [subst; Between|].
apply l6_13_1; trivial.
apply l6_7 with R'; subst.
apply l6_2 with (f P); Col; apply fBet; Between; Col.
apply bet_out; Col; apply grad__bet, HGrad.
}
clear HLe.
revert S S' HeqS' HS HBet.
induction HGrad; intros; subst.
{ exists R; split; [apply grad_init|].
apply bet__le1213, (line_extension_reverse_bet f P Q); Col.
}
rename C into C0'.
destruct (eq_dec_points Q S).
subst; exists R; split; [apply grad_init|apply le_trivial].
assert (Hd : Bet (f Q) (f S) C0' \/ Bet (f Q) C0' (f S)).
{ destruct (eq_dec_points C0' (f Q)); [subst; Between|].
apply l6_7 with C'.
apply bet_out; Col.
apply l6_6, bet_out; Col.
}
destruct Hd; [apply IHHGrad with (f S); trivial|].
assert (HS0 : exists S0, Bet Q S0 S /\ Cong S S0 Q R).
{ apply segment_reverse, (line_extension_reverse_bet f P Q); Col.
apply between_exchange4 with C0'; Between.
}
destruct HS0 as [S0 []].
assert (S <> S0) by (intro; treat_equalities; auto).
assert (HC0 : Reach Q R Q S0).
{ assert (Bet P Q S0) by (apply between_inner_transitivity with S; assumption).
apply IHHGrad with (f S0); trivial.
apply between_inner_transitivity with (f S); Col.
destruct (eq_dec_points C0' (f S)); [subst; Between|].
apply between_symmetry, l6_13_1.
apply bet2__out with (f Q); try apply between_symmetry; Col.
apply (l5_6 (f S) C0' C0' C').
apply le_left_comm, bet__le1213, (between_exchange3 (f Q)); assumption.
Cong.
apply cong_symmetry, cong_transitivity with (f Q) (f R); Col.
}
clear IHHGrad.
destruct HC0 as [C0 []].
destruct (segment_construction Q C0 Q R) as [C []].
exists C; split; [apply grad_stab with C0; Cong|].
apply bet__le1213.
destruct (eq_dec_points Q S0).
{ subst S0; assert (R = S) by (apply (between_cong_3 P Q); Cong).
treat_equalities; apply between_exchange4 with C0; Between.
}
assert (Bet Q S0 C0).
{ apply l6_13_1; trivial.
apply l6_7 with S; [Out|].
apply l6_7 with R.
apply l6_2 with P; Between.
apply bet_out; Between.
}
apply outer_transitivity_between2 with S0; auto.
assert (Bet Q S0 C) by (apply between_exchange4 with C0; assumption).
apply l6_13_1.
apply l6_2 with Q; Between; intro; treat_equalities; auto.
apply le_right_comm; exists C0; split.
apply between_inner_transitivity with Q; Between.
apply cong_transitivity with Q R; Cong.
Qed.
End Archimedes.
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 61: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 61: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 61: 0] entry_0;
reg [ 61: 0] entry_1;
wire full;
reg rd_address;
reg [ 61: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_sdram (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 31: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 12: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 31: 0] zs_dq;
output [ 3: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 24: 0] az_addr;
input [ 3: 0] az_be_n;
input az_cs;
input [ 31: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 24: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 31: 0] active_data;
reg [ 3: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 9: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 24: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 31: 0] f_data;
wire [ 3: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 61: 0] fifo_read_data;
reg [ 12: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 12: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 31: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 3: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 13: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 31: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 12: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 31: 0] zs_dq;
wire [ 3: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{32{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
usb_system_sdram_input_efifo_module the_usb_system_sdram_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 4'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[24],f_addr[10]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 10000;
else if (refresh_counter == 0)
refresh_counter <= 390;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {13{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {13{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 0;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 3;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{3{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[24],active_addr[10]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[23 : 11]} == {f_addr[23 : 11]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {3{1'b0}},f_addr[9 : 0] } : { {3{1'b0}},active_addr[9 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 13'b0000000000000;
m_data <= 32'b00000000000000000000000000000000;
m_dqm <= 4'b0000;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 0;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[23 : 11];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 1;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 0;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {13{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 3;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_prim_conv11 (
primitive11_0_params_V_read,
primitive11_1_params_V_read,
primitive11_2_params_V_read,
primitive11_3_params_V_read,
primitive11_4_params_V_read,
primitive11_0_th_mem_V_read,
primitive11_1_th_mem_V_read,
primitive11_2_th_mem_V_read,
primitive11_3_th_mem_V_read,
primitive11_4_th_mem_V_read,
primitive11_5_th_mem_V_read,
primitive11_6_th_mem_V_read,
primitive11_7_th_mem_V_read,
primitive11_8_th_mem_V_read,
primitive11_9_th_mem_V_read,
primitive11_10_th_mem_V_read,
primitive11_11_th_mem_V_read,
primitive11_12_th_mem_V_read,
primitive11_13_th_mem_V_read,
primitive11_14_th_mem_V_read,
primitive11_15_th_mem_V_read,
primitive11_16_th_mem_V_read,
primitive11_17_th_mem_V_read,
primitive11_18_th_mem_V_read,
primitive11_19_th_mem_V_read,
primitive11_20_th_mem_V_read,
primitive11_21_th_mem_V_read,
primitive11_22_th_mem_V_read,
primitive11_23_th_mem_V_read,
primitive11_24_th_mem_V_read,
primitive11_25_th_mem_V_read,
primitive11_26_th_mem_V_read,
primitive11_27_th_mem_V_read,
primitive11_28_th_mem_V_read,
primitive11_29_th_mem_V_read,
primitive11_30_th_mem_V_read,
primitive11_31_th_mem_V_read,
primitive11_32_th_mem_V_read,
primitive11_33_th_mem_V_read,
primitive11_34_th_mem_V_read,
primitive11_35_th_mem_V_read,
primitive11_36_th_mem_V_read,
primitive11_37_th_mem_V_read,
primitive11_38_th_mem_V_read,
primitive11_39_th_mem_V_read,
primitive11_40_th_mem_V_read,
primitive11_41_th_mem_V_read,
primitive11_42_th_mem_V_read,
primitive11_43_th_mem_V_read,
primitive11_44_th_mem_V_read,
primitive11_45_th_mem_V_read,
primitive11_46_th_mem_V_read,
primitive11_47_th_mem_V_read,
primitive11_48_th_mem_V_read,
primitive11_49_th_mem_V_read,
primitive11_50_th_mem_V_read,
primitive11_51_th_mem_V_read,
primitive11_52_th_mem_V_read,
primitive11_53_th_mem_V_read,
primitive11_54_th_mem_V_read,
primitive11_55_th_mem_V_read,
primitive11_56_th_mem_V_read,
primitive11_57_th_mem_V_read,
primitive11_58_th_mem_V_read,
primitive11_59_th_mem_V_read,
primitive11_60_th_mem_V_read,
primitive11_61_th_mem_V_read,
primitive11_62_th_mem_V_read,
primitive11_63_th_mem_V_read,
primitive11_64_th_mem_V_read,
primitive11_65_th_mem_V_read,
primitive11_66_th_mem_V_read,
primitive11_67_th_mem_V_read,
primitive11_68_th_mem_V_read,
primitive11_69_th_mem_V_read,
primitive11_70_th_mem_V_read,
primitive11_71_th_mem_V_read,
primitive11_72_th_mem_V_read,
primitive11_73_th_mem_V_read,
primitive11_74_th_mem_V_read,
primitive11_75_th_mem_V_read,
primitive11_76_th_mem_V_read,
primitive11_77_th_mem_V_read,
primitive11_78_th_mem_V_read,
primitive11_79_th_mem_V_read,
primitive11_80_th_mem_V_read,
primitive11_81_th_mem_V_read,
primitive11_82_th_mem_V_read,
primitive11_83_th_mem_V_read,
primitive11_84_th_mem_V_read,
primitive11_85_th_mem_V_read,
primitive11_86_th_mem_V_read,
primitive11_87_th_mem_V_read,
primitive11_88_th_mem_V_read,
primitive11_89_th_mem_V_read,
primitive11_90_th_mem_V_read,
primitive11_91_th_mem_V_read,
primitive11_92_th_mem_V_read,
primitive11_93_th_mem_V_read,
primitive11_94_th_mem_V_read,
primitive11_95_th_mem_V_read,
primitive11_96_th_mem_V_read,
primitive11_97_th_mem_V_read,
primitive11_98_th_mem_V_read,
primitive11_99_th_mem_V_read,
primitive11_100_th_mem_V_read,
primitive11_101_th_mem_V_read,
primitive11_102_th_mem_V_read,
primitive11_103_th_mem_V_read,
primitive11_104_th_mem_V_read,
primitive11_105_th_mem_V_read,
primitive11_106_th_mem_V_read,
primitive11_107_th_mem_V_read,
primitive11_108_th_mem_V_read,
primitive11_109_th_mem_V_read,
primitive11_110_th_mem_V_read,
primitive11_111_th_mem_V_read,
primitive11_112_th_mem_V_read,
primitive11_113_th_mem_V_read,
primitive11_114_th_mem_V_read,
primitive11_115_th_mem_V_read,
primitive11_116_th_mem_V_read,
primitive11_117_th_mem_V_read,
primitive11_118_th_mem_V_read,
primitive11_119_th_mem_V_read,
primitive11_120_th_mem_V_read,
primitive11_121_th_mem_V_read,
primitive11_122_th_mem_V_read,
primitive11_123_th_mem_V_read,
primitive11_124_th_mem_V_read,
primitive11_125_th_mem_V_read,
primitive11_126_th_mem_V_read,
primitive11_127_th_mem_V_read,
primitive11_0_th_corr_mem_V_read,
primitive11_1_th_corr_mem_V_read,
primitive11_2_th_corr_mem_V_read,
primitive11_3_th_corr_mem_V_read,
primitive11_4_th_corr_mem_V_read,
primitive11_5_th_corr_mem_V_read,
primitive11_6_th_corr_mem_V_read,
primitive11_7_th_corr_mem_V_read,
primitive11_8_th_corr_mem_V_read,
primitive11_9_th_corr_mem_V_read,
primitive11_10_th_corr_mem_V_read,
primitive11_11_th_corr_mem_V_read,
primitive11_12_th_corr_mem_V_read,
primitive11_13_th_corr_mem_V_read,
primitive11_14_th_corr_mem_V_read,
primitive11_15_th_corr_mem_V_read,
primitive11_16_th_corr_mem_V_read,
primitive11_17_th_corr_mem_V_read,
primitive11_18_th_corr_mem_V_read,
primitive11_19_th_corr_mem_V_read,
primitive11_20_th_corr_mem_V_read,
primitive11_21_th_corr_mem_V_read,
primitive11_22_th_corr_mem_V_read,
primitive11_23_th_corr_mem_V_read,
primitive11_24_th_corr_mem_V_read,
primitive11_25_th_corr_mem_V_read,
primitive11_26_th_corr_mem_V_read,
primitive11_27_th_corr_mem_V_read,
primitive11_28_th_corr_mem_V_read,
primitive11_29_th_corr_mem_V_read,
primitive11_30_th_corr_mem_V_read,
primitive11_31_th_corr_mem_V_read,
primitive11_32_th_corr_mem_V_read,
primitive11_33_th_corr_mem_V_read,
primitive11_34_th_corr_mem_V_read,
primitive11_35_th_corr_mem_V_read,
primitive11_36_th_corr_mem_V_read,
primitive11_37_th_corr_mem_V_read,
primitive11_38_th_corr_mem_V_read,
primitive11_39_th_corr_mem_V_read,
primitive11_40_th_corr_mem_V_read,
primitive11_41_th_corr_mem_V_read,
primitive11_42_th_corr_mem_V_read,
primitive11_43_th_corr_mem_V_read,
primitive11_44_th_corr_mem_V_read,
primitive11_45_th_corr_mem_V_read,
primitive11_46_th_corr_mem_V_read,
primitive11_47_th_corr_mem_V_read,
primitive11_48_th_corr_mem_V_read,
primitive11_49_th_corr_mem_V_read,
primitive11_50_th_corr_mem_V_read,
primitive11_51_th_corr_mem_V_read,
primitive11_52_th_corr_mem_V_read,
primitive11_53_th_corr_mem_V_read,
primitive11_54_th_corr_mem_V_read,
primitive11_55_th_corr_mem_V_read,
primitive11_56_th_corr_mem_V_read,
primitive11_57_th_corr_mem_V_read,
primitive11_58_th_corr_mem_V_read,
primitive11_59_th_corr_mem_V_read,
primitive11_60_th_corr_mem_V_read,
primitive11_61_th_corr_mem_V_read,
primitive11_62_th_corr_mem_V_read,
primitive11_63_th_corr_mem_V_read,
primitive11_64_th_corr_mem_V_read,
primitive11_65_th_corr_mem_V_read,
primitive11_66_th_corr_mem_V_read,
primitive11_67_th_corr_mem_V_read,
primitive11_68_th_corr_mem_V_read,
primitive11_69_th_corr_mem_V_read,
primitive11_70_th_corr_mem_V_read,
primitive11_71_th_corr_mem_V_read,
primitive11_72_th_corr_mem_V_read,
primitive11_73_th_corr_mem_V_read,
primitive11_74_th_corr_mem_V_read,
primitive11_75_th_corr_mem_V_read,
primitive11_76_th_corr_mem_V_read,
primitive11_77_th_corr_mem_V_read,
primitive11_78_th_corr_mem_V_read,
primitive11_79_th_corr_mem_V_read,
primitive11_80_th_corr_mem_V_read,
primitive11_81_th_corr_mem_V_read,
primitive11_82_th_corr_mem_V_read,
primitive11_83_th_corr_mem_V_read,
primitive11_84_th_corr_mem_V_read,
primitive11_85_th_corr_mem_V_read,
primitive11_86_th_corr_mem_V_read,
primitive11_87_th_corr_mem_V_read,
primitive11_88_th_corr_mem_V_read,
primitive11_89_th_corr_mem_V_read,
primitive11_90_th_corr_mem_V_read,
primitive11_91_th_corr_mem_V_read,
primitive11_92_th_corr_mem_V_read,
primitive11_93_th_corr_mem_V_read,
primitive11_94_th_corr_mem_V_read,
primitive11_95_th_corr_mem_V_read,
primitive11_96_th_corr_mem_V_read,
primitive11_97_th_corr_mem_V_read,
primitive11_98_th_corr_mem_V_read,
primitive11_99_th_corr_mem_V_read,
primitive11_100_th_corr_mem_V_read,
primitive11_101_th_corr_mem_V_read,
primitive11_102_th_corr_mem_V_read,
primitive11_103_th_corr_mem_V_read,
primitive11_104_th_corr_mem_V_read,
primitive11_105_th_corr_mem_V_read,
primitive11_106_th_corr_mem_V_read,
primitive11_107_th_corr_mem_V_read,
primitive11_108_th_corr_mem_V_read,
primitive11_109_th_corr_mem_V_read,
primitive11_110_th_corr_mem_V_read,
primitive11_111_th_corr_mem_V_read,
primitive11_112_th_corr_mem_V_read,
primitive11_113_th_corr_mem_V_read,
primitive11_114_th_corr_mem_V_read,
primitive11_115_th_corr_mem_V_read,
primitive11_116_th_corr_mem_V_read,
primitive11_117_th_corr_mem_V_read,
primitive11_118_th_corr_mem_V_read,
primitive11_119_th_corr_mem_V_read,
primitive11_120_th_corr_mem_V_read,
primitive11_121_th_corr_mem_V_read,
primitive11_122_th_corr_mem_V_read,
primitive11_123_th_corr_mem_V_read,
primitive11_124_th_corr_mem_V_read,
primitive11_125_th_corr_mem_V_read,
primitive11_126_th_corr_mem_V_read,
primitive11_127_th_corr_mem_V_read,
quality_0_V_read,
quality_1_V_read,
wiregroup_0_V_read,
wiregroup_1_V_read,
hstrip_0_V_read,
hstrip_1_V_read,
clctpat_0_V_read,
clctpat_1_V_read,
endcap_V,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3,
ap_return_4,
ap_return_5
);
parameter ap_const_lv32_7 = 32'b111;
parameter ap_const_lv4_9 = 4'b1001;
parameter ap_const_lv4_8 = 4'b1000;
parameter ap_const_lv4_7 = 4'b111;
parameter ap_const_lv4_6 = 4'b110;
parameter ap_const_lv4_5 = 4'b101;
parameter ap_const_lv4_4 = 4'b100;
parameter ap_const_lv4_3 = 4'b11;
parameter ap_const_lv4_2 = 4'b10;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv12_200 = 12'b1000000000;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv23_6AB = 23'b11010101011;
parameter ap_const_lv23_515 = 23'b10100010101;
parameter ap_const_lv32_A = 32'b1010;
parameter ap_const_lv32_15 = 32'b10101;
parameter ap_const_lv32_F = 32'b1111;
parameter ap_const_lv8_14 = 8'b10100;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv44_0 = 44'b00000000000000000000000000000000000000000000;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv6_2D = 6'b101101;
parameter ap_const_lv7_2C = 7'b101100;
parameter ap_const_lv7_7C = 7'b1111100;
parameter ap_const_lv7_27 = 7'b100111;
parameter ap_const_lv3_0 = 3'b000;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_2 = 32'b10;
input [11:0] primitive11_0_params_V_read;
input [11:0] primitive11_1_params_V_read;
input [11:0] primitive11_2_params_V_read;
input [11:0] primitive11_3_params_V_read;
input [11:0] primitive11_4_params_V_read;
input [5:0] primitive11_0_th_mem_V_read;
input [5:0] primitive11_1_th_mem_V_read;
input [5:0] primitive11_2_th_mem_V_read;
input [5:0] primitive11_3_th_mem_V_read;
input [5:0] primitive11_4_th_mem_V_read;
input [5:0] primitive11_5_th_mem_V_read;
input [5:0] primitive11_6_th_mem_V_read;
input [5:0] primitive11_7_th_mem_V_read;
input [5:0] primitive11_8_th_mem_V_read;
input [5:0] primitive11_9_th_mem_V_read;
input [5:0] primitive11_10_th_mem_V_read;
input [5:0] primitive11_11_th_mem_V_read;
input [5:0] primitive11_12_th_mem_V_read;
input [5:0] primitive11_13_th_mem_V_read;
input [5:0] primitive11_14_th_mem_V_read;
input [5:0] primitive11_15_th_mem_V_read;
input [5:0] primitive11_16_th_mem_V_read;
input [5:0] primitive11_17_th_mem_V_read;
input [5:0] primitive11_18_th_mem_V_read;
input [5:0] primitive11_19_th_mem_V_read;
input [5:0] primitive11_20_th_mem_V_read;
input [5:0] primitive11_21_th_mem_V_read;
input [5:0] primitive11_22_th_mem_V_read;
input [5:0] primitive11_23_th_mem_V_read;
input [5:0] primitive11_24_th_mem_V_read;
input [5:0] primitive11_25_th_mem_V_read;
input [5:0] primitive11_26_th_mem_V_read;
input [5:0] primitive11_27_th_mem_V_read;
input [5:0] primitive11_28_th_mem_V_read;
input [5:0] primitive11_29_th_mem_V_read;
input [5:0] primitive11_30_th_mem_V_read;
input [5:0] primitive11_31_th_mem_V_read;
input [5:0] primitive11_32_th_mem_V_read;
input [5:0] primitive11_33_th_mem_V_read;
input [5:0] primitive11_34_th_mem_V_read;
input [5:0] primitive11_35_th_mem_V_read;
input [5:0] primitive11_36_th_mem_V_read;
input [5:0] primitive11_37_th_mem_V_read;
input [5:0] primitive11_38_th_mem_V_read;
input [5:0] primitive11_39_th_mem_V_read;
input [5:0] primitive11_40_th_mem_V_read;
input [5:0] primitive11_41_th_mem_V_read;
input [5:0] primitive11_42_th_mem_V_read;
input [5:0] primitive11_43_th_mem_V_read;
input [5:0] primitive11_44_th_mem_V_read;
input [5:0] primitive11_45_th_mem_V_read;
input [5:0] primitive11_46_th_mem_V_read;
input [5:0] primitive11_47_th_mem_V_read;
input [5:0] primitive11_48_th_mem_V_read;
input [5:0] primitive11_49_th_mem_V_read;
input [5:0] primitive11_50_th_mem_V_read;
input [5:0] primitive11_51_th_mem_V_read;
input [5:0] primitive11_52_th_mem_V_read;
input [5:0] primitive11_53_th_mem_V_read;
input [5:0] primitive11_54_th_mem_V_read;
input [5:0] primitive11_55_th_mem_V_read;
input [5:0] primitive11_56_th_mem_V_read;
input [5:0] primitive11_57_th_mem_V_read;
input [5:0] primitive11_58_th_mem_V_read;
input [5:0] primitive11_59_th_mem_V_read;
input [5:0] primitive11_60_th_mem_V_read;
input [5:0] primitive11_61_th_mem_V_read;
input [5:0] primitive11_62_th_mem_V_read;
input [5:0] primitive11_63_th_mem_V_read;
input [5:0] primitive11_64_th_mem_V_read;
input [5:0] primitive11_65_th_mem_V_read;
input [5:0] primitive11_66_th_mem_V_read;
input [5:0] primitive11_67_th_mem_V_read;
input [5:0] primitive11_68_th_mem_V_read;
input [5:0] primitive11_69_th_mem_V_read;
input [5:0] primitive11_70_th_mem_V_read;
input [5:0] primitive11_71_th_mem_V_read;
input [5:0] primitive11_72_th_mem_V_read;
input [5:0] primitive11_73_th_mem_V_read;
input [5:0] primitive11_74_th_mem_V_read;
input [5:0] primitive11_75_th_mem_V_read;
input [5:0] primitive11_76_th_mem_V_read;
input [5:0] primitive11_77_th_mem_V_read;
input [5:0] primitive11_78_th_mem_V_read;
input [5:0] primitive11_79_th_mem_V_read;
input [5:0] primitive11_80_th_mem_V_read;
input [5:0] primitive11_81_th_mem_V_read;
input [5:0] primitive11_82_th_mem_V_read;
input [5:0] primitive11_83_th_mem_V_read;
input [5:0] primitive11_84_th_mem_V_read;
input [5:0] primitive11_85_th_mem_V_read;
input [5:0] primitive11_86_th_mem_V_read;
input [5:0] primitive11_87_th_mem_V_read;
input [5:0] primitive11_88_th_mem_V_read;
input [5:0] primitive11_89_th_mem_V_read;
input [5:0] primitive11_90_th_mem_V_read;
input [5:0] primitive11_91_th_mem_V_read;
input [5:0] primitive11_92_th_mem_V_read;
input [5:0] primitive11_93_th_mem_V_read;
input [5:0] primitive11_94_th_mem_V_read;
input [5:0] primitive11_95_th_mem_V_read;
input [5:0] primitive11_96_th_mem_V_read;
input [5:0] primitive11_97_th_mem_V_read;
input [5:0] primitive11_98_th_mem_V_read;
input [5:0] primitive11_99_th_mem_V_read;
input [5:0] primitive11_100_th_mem_V_read;
input [5:0] primitive11_101_th_mem_V_read;
input [5:0] primitive11_102_th_mem_V_read;
input [5:0] primitive11_103_th_mem_V_read;
input [5:0] primitive11_104_th_mem_V_read;
input [5:0] primitive11_105_th_mem_V_read;
input [5:0] primitive11_106_th_mem_V_read;
input [5:0] primitive11_107_th_mem_V_read;
input [5:0] primitive11_108_th_mem_V_read;
input [5:0] primitive11_109_th_mem_V_read;
input [5:0] primitive11_110_th_mem_V_read;
input [5:0] primitive11_111_th_mem_V_read;
input [5:0] primitive11_112_th_mem_V_read;
input [5:0] primitive11_113_th_mem_V_read;
input [5:0] primitive11_114_th_mem_V_read;
input [5:0] primitive11_115_th_mem_V_read;
input [5:0] primitive11_116_th_mem_V_read;
input [5:0] primitive11_117_th_mem_V_read;
input [5:0] primitive11_118_th_mem_V_read;
input [5:0] primitive11_119_th_mem_V_read;
input [5:0] primitive11_120_th_mem_V_read;
input [5:0] primitive11_121_th_mem_V_read;
input [5:0] primitive11_122_th_mem_V_read;
input [5:0] primitive11_123_th_mem_V_read;
input [5:0] primitive11_124_th_mem_V_read;
input [5:0] primitive11_125_th_mem_V_read;
input [5:0] primitive11_126_th_mem_V_read;
input [5:0] primitive11_127_th_mem_V_read;
input [3:0] primitive11_0_th_corr_mem_V_read;
input [3:0] primitive11_1_th_corr_mem_V_read;
input [3:0] primitive11_2_th_corr_mem_V_read;
input [3:0] primitive11_3_th_corr_mem_V_read;
input [3:0] primitive11_4_th_corr_mem_V_read;
input [3:0] primitive11_5_th_corr_mem_V_read;
input [3:0] primitive11_6_th_corr_mem_V_read;
input [3:0] primitive11_7_th_corr_mem_V_read;
input [3:0] primitive11_8_th_corr_mem_V_read;
input [3:0] primitive11_9_th_corr_mem_V_read;
input [3:0] primitive11_10_th_corr_mem_V_read;
input [3:0] primitive11_11_th_corr_mem_V_read;
input [3:0] primitive11_12_th_corr_mem_V_read;
input [3:0] primitive11_13_th_corr_mem_V_read;
input [3:0] primitive11_14_th_corr_mem_V_read;
input [3:0] primitive11_15_th_corr_mem_V_read;
input [3:0] primitive11_16_th_corr_mem_V_read;
input [3:0] primitive11_17_th_corr_mem_V_read;
input [3:0] primitive11_18_th_corr_mem_V_read;
input [3:0] primitive11_19_th_corr_mem_V_read;
input [3:0] primitive11_20_th_corr_mem_V_read;
input [3:0] primitive11_21_th_corr_mem_V_read;
input [3:0] primitive11_22_th_corr_mem_V_read;
input [3:0] primitive11_23_th_corr_mem_V_read;
input [3:0] primitive11_24_th_corr_mem_V_read;
input [3:0] primitive11_25_th_corr_mem_V_read;
input [3:0] primitive11_26_th_corr_mem_V_read;
input [3:0] primitive11_27_th_corr_mem_V_read;
input [3:0] primitive11_28_th_corr_mem_V_read;
input [3:0] primitive11_29_th_corr_mem_V_read;
input [3:0] primitive11_30_th_corr_mem_V_read;
input [3:0] primitive11_31_th_corr_mem_V_read;
input [3:0] primitive11_32_th_corr_mem_V_read;
input [3:0] primitive11_33_th_corr_mem_V_read;
input [3:0] primitive11_34_th_corr_mem_V_read;
input [3:0] primitive11_35_th_corr_mem_V_read;
input [3:0] primitive11_36_th_corr_mem_V_read;
input [3:0] primitive11_37_th_corr_mem_V_read;
input [3:0] primitive11_38_th_corr_mem_V_read;
input [3:0] primitive11_39_th_corr_mem_V_read;
input [3:0] primitive11_40_th_corr_mem_V_read;
input [3:0] primitive11_41_th_corr_mem_V_read;
input [3:0] primitive11_42_th_corr_mem_V_read;
input [3:0] primitive11_43_th_corr_mem_V_read;
input [3:0] primitive11_44_th_corr_mem_V_read;
input [3:0] primitive11_45_th_corr_mem_V_read;
input [3:0] primitive11_46_th_corr_mem_V_read;
input [3:0] primitive11_47_th_corr_mem_V_read;
input [3:0] primitive11_48_th_corr_mem_V_read;
input [3:0] primitive11_49_th_corr_mem_V_read;
input [3:0] primitive11_50_th_corr_mem_V_read;
input [3:0] primitive11_51_th_corr_mem_V_read;
input [3:0] primitive11_52_th_corr_mem_V_read;
input [3:0] primitive11_53_th_corr_mem_V_read;
input [3:0] primitive11_54_th_corr_mem_V_read;
input [3:0] primitive11_55_th_corr_mem_V_read;
input [3:0] primitive11_56_th_corr_mem_V_read;
input [3:0] primitive11_57_th_corr_mem_V_read;
input [3:0] primitive11_58_th_corr_mem_V_read;
input [3:0] primitive11_59_th_corr_mem_V_read;
input [3:0] primitive11_60_th_corr_mem_V_read;
input [3:0] primitive11_61_th_corr_mem_V_read;
input [3:0] primitive11_62_th_corr_mem_V_read;
input [3:0] primitive11_63_th_corr_mem_V_read;
input [3:0] primitive11_64_th_corr_mem_V_read;
input [3:0] primitive11_65_th_corr_mem_V_read;
input [3:0] primitive11_66_th_corr_mem_V_read;
input [3:0] primitive11_67_th_corr_mem_V_read;
input [3:0] primitive11_68_th_corr_mem_V_read;
input [3:0] primitive11_69_th_corr_mem_V_read;
input [3:0] primitive11_70_th_corr_mem_V_read;
input [3:0] primitive11_71_th_corr_mem_V_read;
input [3:0] primitive11_72_th_corr_mem_V_read;
input [3:0] primitive11_73_th_corr_mem_V_read;
input [3:0] primitive11_74_th_corr_mem_V_read;
input [3:0] primitive11_75_th_corr_mem_V_read;
input [3:0] primitive11_76_th_corr_mem_V_read;
input [3:0] primitive11_77_th_corr_mem_V_read;
input [3:0] primitive11_78_th_corr_mem_V_read;
input [3:0] primitive11_79_th_corr_mem_V_read;
input [3:0] primitive11_80_th_corr_mem_V_read;
input [3:0] primitive11_81_th_corr_mem_V_read;
input [3:0] primitive11_82_th_corr_mem_V_read;
input [3:0] primitive11_83_th_corr_mem_V_read;
input [3:0] primitive11_84_th_corr_mem_V_read;
input [3:0] primitive11_85_th_corr_mem_V_read;
input [3:0] primitive11_86_th_corr_mem_V_read;
input [3:0] primitive11_87_th_corr_mem_V_read;
input [3:0] primitive11_88_th_corr_mem_V_read;
input [3:0] primitive11_89_th_corr_mem_V_read;
input [3:0] primitive11_90_th_corr_mem_V_read;
input [3:0] primitive11_91_th_corr_mem_V_read;
input [3:0] primitive11_92_th_corr_mem_V_read;
input [3:0] primitive11_93_th_corr_mem_V_read;
input [3:0] primitive11_94_th_corr_mem_V_read;
input [3:0] primitive11_95_th_corr_mem_V_read;
input [3:0] primitive11_96_th_corr_mem_V_read;
input [3:0] primitive11_97_th_corr_mem_V_read;
input [3:0] primitive11_98_th_corr_mem_V_read;
input [3:0] primitive11_99_th_corr_mem_V_read;
input [3:0] primitive11_100_th_corr_mem_V_read;
input [3:0] primitive11_101_th_corr_mem_V_read;
input [3:0] primitive11_102_th_corr_mem_V_read;
input [3:0] primitive11_103_th_corr_mem_V_read;
input [3:0] primitive11_104_th_corr_mem_V_read;
input [3:0] primitive11_105_th_corr_mem_V_read;
input [3:0] primitive11_106_th_corr_mem_V_read;
input [3:0] primitive11_107_th_corr_mem_V_read;
input [3:0] primitive11_108_th_corr_mem_V_read;
input [3:0] primitive11_109_th_corr_mem_V_read;
input [3:0] primitive11_110_th_corr_mem_V_read;
input [3:0] primitive11_111_th_corr_mem_V_read;
input [3:0] primitive11_112_th_corr_mem_V_read;
input [3:0] primitive11_113_th_corr_mem_V_read;
input [3:0] primitive11_114_th_corr_mem_V_read;
input [3:0] primitive11_115_th_corr_mem_V_read;
input [3:0] primitive11_116_th_corr_mem_V_read;
input [3:0] primitive11_117_th_corr_mem_V_read;
input [3:0] primitive11_118_th_corr_mem_V_read;
input [3:0] primitive11_119_th_corr_mem_V_read;
input [3:0] primitive11_120_th_corr_mem_V_read;
input [3:0] primitive11_121_th_corr_mem_V_read;
input [3:0] primitive11_122_th_corr_mem_V_read;
input [3:0] primitive11_123_th_corr_mem_V_read;
input [3:0] primitive11_124_th_corr_mem_V_read;
input [3:0] primitive11_125_th_corr_mem_V_read;
input [3:0] primitive11_126_th_corr_mem_V_read;
input [3:0] primitive11_127_th_corr_mem_V_read;
input [3:0] quality_0_V_read;
input [3:0] quality_1_V_read;
input [6:0] wiregroup_0_V_read;
input [6:0] wiregroup_1_V_read;
input [7:0] hstrip_0_V_read;
input [7:0] hstrip_1_V_read;
input [3:0] clctpat_0_V_read;
input [3:0] clctpat_1_V_read;
input [0:0] endcap_V;
output [2:0] ap_return_0;
output [43:0] ap_return_1;
output [11:0] ap_return_2;
output [11:0] ap_return_3;
output [3:0] ap_return_4;
output [3:0] ap_return_5;
wire [0:0] sel_tmp14_fu_2328_p2;
wire [0:0] sel_tmp12_fu_2322_p2;
wire [0:0] sel_tmp10_fu_2316_p2;
wire [0:0] sel_tmp8_fu_2310_p2;
wire [0:0] sel_tmp6_fu_2304_p2;
wire [0:0] sel_tmp4_fu_2298_p2;
wire [0:0] sel_tmp2_fu_2292_p2;
wire [0:0] sel_tmp_fu_2286_p2;
wire [0:0] or_cond_fu_2334_p2;
wire [0:0] or_cond6_fu_2340_p2;
wire [0:0] or_cond7_fu_2346_p2;
wire [0:0] or_cond8_fu_2352_p2;
wire [0:0] or_cond9_fu_2358_p2;
wire [0:0] or_cond1_fu_2364_p2;
wire [0:0] sel_tmp23_fu_2376_p2;
wire [0:0] not_sel_tmp_fu_2382_p2;
wire [0:0] sel_tmp25_fu_2388_p2;
wire [0:0] sel_tmp27_fu_2394_p2;
wire [0:0] not_sel_tmp7_fu_2400_p2;
wire [0:0] sel_tmp29_fu_2406_p2;
wire [0:0] tmp_503_fu_2278_p3;
wire [11:0] p_Result_s_fu_2418_p4;
wire [11:0] tmp_597_cast_cast_fu_2428_p3;
wire [0:0] or_cond2_fu_2370_p2;
wire [1:0] tmp_25_fu_2442_p3;
wire [1:0] tmp_136_fu_2450_p3;
wire [11:0] p_s_fu_2436_p2;
wire [11:0] tmp_s_fu_2458_p1;
wire [0:0] p_1_fu_2412_p2;
wire [11:0] tmp_163_fu_2462_p2;
wire [11:0] tmp_166_fu_2468_p2;
wire [11:0] p_Val2_s_fu_2474_p3;
wire signed [22:0] r_V_s_fu_5408_p2;
wire [11:0] primitive11_2_params_V_read_a_fu_2509_p3;
wire [11:0] ph_tmp_V_fu_2500_p4;
wire [6:0] p_Result_138_fu_2523_p4;
wire [7:0] tmp_605_cast_fu_2532_p1;
wire [7:0] tmp_172_fu_2536_p2;
wire [6:0] tmp_173_fu_2546_p4;
wire [6:0] tmp_174_fu_2556_p4;
wire [6:0] tmp_175_fu_2566_p3;
wire [8:0] tmp_610_cast_fu_2574_p1;
wire signed [8:0] tmp_606_cast_fu_2542_p1;
wire [7:0] rhs_V_cast_fu_2590_p1;
wire [7:0] r_V_1_fu_2594_p2;
wire [11:0] tmp_171_fu_2517_p2;
wire [11:0] tmp_176_fu_2584_p2;
wire [8:0] i_assign_fu_2578_p2;
wire [8:0] i_assign_3_cast_fu_2600_p1;
wire [8:0] tmp_137_fu_2612_p3;
wire signed [31:0] tmp_137_cast_fu_2620_p1;
wire [1:0] p_Result_140_fu_2906_p4;
wire [4:0] p_Result_139_fu_2896_p4;
wire [6:0] tmp_140_fu_2924_p129;
wire [3:0] tmp_140_fu_2924_p130;
wire [5:0] tmp_139_fu_2634_p130;
wire [5:0] tmp_141_fu_3186_p1;
wire [5:0] tmp_143_fu_3190_p2;
wire [5:0] tmp_144_fu_3196_p2;
wire [5:0] tmp_145_fu_3202_p3;
wire [6:0] tmp_505_fu_3220_p1;
wire [6:0] th_tmp_V_cast_fu_3210_p1;
wire [6:0] tmp_179_fu_3224_p2;
wire [0:0] tmp_180_fu_3230_p2;
wire [0:0] tmp_181_fu_3240_p2;
wire [2:0] p_Result_141_fu_3246_p3;
wire [2:0] p_Val2_1_fu_3236_p1;
wire [2:0] p_Val2_2_fu_3254_p3;
wire [0:0] tmp_178_fu_3214_p2;
wire [0:0] tmp_182_fu_3262_p2;
wire [0:0] sel_tmp37_fu_3278_p2;
reg [2:0] tmp_506_fu_3268_p4;
wire [2:0] sel_tmp38_fu_3284_p3;
wire [6:0] tmp_146_fu_3314_p129;
wire [3:0] tmp_146_fu_3314_p130;
wire [5:0] tmp_147_fu_3576_p1;
wire [5:0] tmp_149_fu_3580_p2;
wire [5:0] tmp_150_fu_3586_p2;
wire [5:0] tmp_151_fu_3592_p3;
wire [6:0] th_tmp_V_0_1_cast_fu_3600_p1;
wire [6:0] tmp_697_0_1_fu_3610_p2;
wire [2:0] p_01099_6_fu_3292_p3;
wire [0:0] tmp_698_0_1_fu_3616_p2;
reg [2:0] tmp_507_fu_3622_p4;
wire [2:0] p_Val2_259_0_1_fu_3632_p3;
wire [0:0] tmp_701_0_1_fu_3640_p2;
reg [2:0] tmp_508_fu_3646_p4;
wire [2:0] p_Val2_260_0_1_fu_3656_p3;
wire [0:0] tmp_170_fu_2482_p2;
wire [0:0] tmp_689_0_1_fu_3300_p2;
wire [0:0] sel_tmp45_fu_3688_p2;
wire [0:0] sel_tmp46_fu_3694_p2;
wire [3:0] sel_tmp44_fu_3680_p3;
wire [0:0] sel_tmp50_demorgan_fu_3708_p2;
wire [0:0] tmp_693_0_1_fu_3604_p2;
wire [0:0] sel_tmp52_demorgan_fu_3714_p2;
wire [3:0] sel_tmp47_fu_3700_p3;
wire [0:0] tmp_702_0_1_fu_3664_p2;
wire [0:0] sel_tmp56_fu_3728_p2;
wire [0:0] tmp_fu_3734_p2;
wire [0:0] sel_tmp58_fu_3740_p2;
wire [3:0] sel_tmp53_fu_3720_p3;
wire [11:0] fph_V_load_s_fu_2604_p3;
wire [11:0] sel_tmp60_fu_3754_p3;
wire [11:0] sel_tmp63_fu_3762_p3;
wire [11:0] sel_tmp69_fu_3770_p3;
wire [2:0] sel_tmp76_fu_3786_p3;
wire [2:0] sel_tmp79_fu_3794_p3;
reg [2:0] tmp_509_fu_3670_p4;
wire [2:0] sel_tmp85_fu_3802_p3;
reg [43:0] tmp_504_fu_2624_p4;
wire [43:0] sel_tmp92_fu_3818_p3;
wire [43:0] sel_tmp95_fu_3826_p3;
wire [43:0] sel_tmp101_fu_3834_p3;
wire [0:0] sel_tmp124_fu_3900_p2;
wire [0:0] sel_tmp122_fu_3894_p2;
wire [0:0] sel_tmp120_fu_3888_p2;
wire [0:0] sel_tmp118_fu_3882_p2;
wire [0:0] sel_tmp116_fu_3876_p2;
wire [0:0] sel_tmp114_fu_3870_p2;
wire [0:0] sel_tmp112_fu_3864_p2;
wire [0:0] sel_tmp110_fu_3858_p2;
wire [0:0] or_cond3_fu_3906_p2;
wire [0:0] or_cond4_fu_3912_p2;
wire [0:0] or_cond5_fu_3918_p2;
wire [0:0] or_cond10_fu_3924_p2;
wire [0:0] or_cond11_fu_3930_p2;
wire [0:0] or_cond12_fu_3936_p2;
wire [0:0] sel_tmp133_fu_3948_p2;
wire [0:0] not_sel_tmp8_fu_3954_p2;
wire [0:0] sel_tmp135_fu_3960_p2;
wire [0:0] sel_tmp137_fu_3966_p2;
wire [0:0] not_sel_tmp9_fu_3972_p2;
wire [0:0] sel_tmp139_fu_3978_p2;
wire [0:0] tmp_510_fu_3850_p3;
wire [11:0] p_Result_786_1_fu_3990_p4;
wire [11:0] tmp_669_1_cast_cast_fu_4000_p3;
wire [0:0] or_cond13_fu_3942_p2;
wire [1:0] tmp_26_fu_4014_p3;
wire [1:0] tmp_153_fu_4022_p3;
wire [11:0] p_1_73_fu_4008_p2;
wire [11:0] tmp_670_1_fu_4030_p1;
wire [0:0] p_21_1_fu_3984_p2;
wire [11:0] tmp_671_1_fu_4034_p2;
wire [11:0] tmp_673_1_fu_4040_p2;
wire [11:0] p_Val2_255_1_1_fu_4046_p3;
wire signed [22:0] r_V_147_1_fu_5416_p2;
wire [11:0] primitive11_2_params_V_read_a_1_fu_4075_p3;
wire [11:0] ph_tmp_V_1_fu_4066_p4;
wire [6:0] p_Result_790_1_fu_4089_p4;
wire [7:0] tmp_679_1_cast_fu_4098_p1;
wire [7:0] tmp_680_1_fu_4102_p2;
wire [6:0] tmp_184_fu_4112_p3;
wire [8:0] tmp_682_1_cast_fu_4120_p1;
wire signed [8:0] tmp_680_1_cast_fu_4108_p1;
wire [7:0] rhs_V_166_1_cast_fu_4136_p1;
wire [7:0] r_V_143_1_fu_4140_p2;
wire [11:0] tmp_678_1_fu_4083_p2;
wire [11:0] tmp_684_1_fu_4130_p2;
wire [8:0] i_assign_1_fu_4124_p2;
wire [8:0] i_assign_3_1_cast_fu_4146_p1;
wire [8:0] tmp_154_fu_4158_p3;
wire [43:0] p_01111_2_fu_3842_p3;
wire signed [31:0] tmp_154_cast_fu_4166_p1;
wire [1:0] p_Result_798_1_fu_4442_p4;
wire [6:0] tmp_157_fu_4460_p129;
wire [3:0] tmp_157_fu_4460_p130;
wire [5:0] tmp_156_fu_4180_p130;
wire [5:0] tmp_158_fu_4722_p1;
wire [5:0] tmp_160_fu_4726_p2;
wire [5:0] tmp_161_fu_4732_p2;
wire [5:0] tmp_162_fu_4738_p3;
wire [6:0] th_tmp_V_1_cast_fu_4746_p1;
wire [6:0] tmp_697_1_fu_4756_p2;
wire [2:0] p_01099_7_fu_3810_p3;
wire [0:0] tmp_698_1_fu_4762_p2;
reg [2:0] tmp_512_fu_4768_p4;
wire [2:0] p_Val2_259_1_fu_4778_p3;
wire [0:0] tmp_701_1_fu_4786_p2;
reg [2:0] tmp_513_fu_4792_p4;
wire [2:0] p_Val2_260_1_fu_4802_p3;
wire [0:0] tmp_702_1_fu_4810_p2;
wire [0:0] tmp27_fu_4826_p2;
wire [0:0] tmp_693_1_fu_4750_p2;
wire [0:0] sel_tmp150_fu_4832_p2;
reg [2:0] tmp_514_fu_4816_p4;
wire [0:0] sel_tmp154_demorgan_fu_4846_p2;
wire [2:0] sel_tmp151_fu_4838_p3;
wire [2:0] sel_tmp155_fu_4852_p3;
wire [4:0] p_Result_796_1_1_fu_4868_p4;
wire [6:0] tmp_164_fu_4886_p129;
wire [3:0] tmp_164_fu_4886_p130;
wire [5:0] tmp_165_fu_5148_p1;
wire [5:0] tmp_167_fu_5152_p2;
wire [5:0] tmp_168_fu_5158_p2;
wire [5:0] tmp_169_fu_5164_p3;
wire [6:0] th_tmp_V_1_1_cast_fu_5172_p1;
wire [6:0] tmp_697_1_1_fu_5182_p2;
wire [2:0] p_01099_6_1_fu_4860_p3;
wire [0:0] tmp_698_1_1_fu_5188_p2;
reg [2:0] tmp_515_fu_5194_p4;
wire [2:0] p_Val2_259_1_1_fu_5204_p3;
wire [0:0] tmp_701_1_1_fu_5212_p2;
reg [2:0] tmp_516_fu_5218_p4;
wire [2:0] p_Val2_260_1_1_fu_5228_p3;
wire [0:0] tmp_693_1_1_fu_5176_p2;
wire [0:0] sel_tmp163_demorgan_fu_5260_p2;
wire [3:0] sel_tmp157_fu_5252_p3;
wire [0:0] tmp_702_1_1_fu_5236_p2;
wire [0:0] sel_tmp159_fu_5274_p2;
wire [0:0] tmp28_fu_5280_p2;
wire [0:0] sel_tmp160_fu_5286_p2;
wire [3:0] sel_tmp158_fu_5266_p3;
wire [11:0] fph_V_load_4_fu_4150_p3;
wire [11:0] sel_tmp161_fu_5300_p3;
wire [11:0] sel_tmp162_fu_5308_p3;
wire [2:0] sel_tmp163_fu_5324_p3;
reg [2:0] tmp_517_fu_5242_p4;
wire [2:0] sel_tmp164_fu_5332_p3;
reg [43:0] tmp_511_fu_4170_p4;
wire [43:0] sel_tmp165_fu_5348_p3;
wire [43:0] sel_tmp166_fu_5356_p3;
wire [2:0] p_01099_7_1_fu_5340_p3;
wire [43:0] p_01111_2_1_fu_5364_p3;
wire [11:0] ph_0_V_write_assign_fu_3778_p3;
wire [11:0] ph_1_V_write_assign_fu_5316_p3;
wire [3:0] clctpat_r_0_V_write_assign_fu_3746_p3;
wire [3:0] clctpat_r_1_V_write_assign_fu_5292_p3;
wire [11:0] r_V_s_fu_5408_p0;
wire signed [11:0] r_V_s_fu_5408_p1;
wire [11:0] r_V_147_1_fu_5416_p0;
wire signed [11:0] r_V_147_1_fu_5416_p1;
wire [22:0] r_V_147_1_fu_5416_p00;
wire signed [22:0] r_V_147_1_fu_5416_p10;
wire [22:0] r_V_s_fu_5408_p00;
wire signed [22:0] r_V_s_fu_5408_p10;
sp_mux_128to1_sel7_6_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 6 ),
.din2_WIDTH( 6 ),
.din3_WIDTH( 6 ),
.din4_WIDTH( 6 ),
.din5_WIDTH( 6 ),
.din6_WIDTH( 6 ),
.din7_WIDTH( 6 ),
.din8_WIDTH( 6 ),
.din9_WIDTH( 6 ),
.din10_WIDTH( 6 ),
.din11_WIDTH( 6 ),
.din12_WIDTH( 6 ),
.din13_WIDTH( 6 ),
.din14_WIDTH( 6 ),
.din15_WIDTH( 6 ),
.din16_WIDTH( 6 ),
.din17_WIDTH( 6 ),
.din18_WIDTH( 6 ),
.din19_WIDTH( 6 ),
.din20_WIDTH( 6 ),
.din21_WIDTH( 6 ),
.din22_WIDTH( 6 ),
.din23_WIDTH( 6 ),
.din24_WIDTH( 6 ),
.din25_WIDTH( 6 ),
.din26_WIDTH( 6 ),
.din27_WIDTH( 6 ),
.din28_WIDTH( 6 ),
.din29_WIDTH( 6 ),
.din30_WIDTH( 6 ),
.din31_WIDTH( 6 ),
.din32_WIDTH( 6 ),
.din33_WIDTH( 6 ),
.din34_WIDTH( 6 ),
.din35_WIDTH( 6 ),
.din36_WIDTH( 6 ),
.din37_WIDTH( 6 ),
.din38_WIDTH( 6 ),
.din39_WIDTH( 6 ),
.din40_WIDTH( 6 ),
.din41_WIDTH( 6 ),
.din42_WIDTH( 6 ),
.din43_WIDTH( 6 ),
.din44_WIDTH( 6 ),
.din45_WIDTH( 6 ),
.din46_WIDTH( 6 ),
.din47_WIDTH( 6 ),
.din48_WIDTH( 6 ),
.din49_WIDTH( 6 ),
.din50_WIDTH( 6 ),
.din51_WIDTH( 6 ),
.din52_WIDTH( 6 ),
.din53_WIDTH( 6 ),
.din54_WIDTH( 6 ),
.din55_WIDTH( 6 ),
.din56_WIDTH( 6 ),
.din57_WIDTH( 6 ),
.din58_WIDTH( 6 ),
.din59_WIDTH( 6 ),
.din60_WIDTH( 6 ),
.din61_WIDTH( 6 ),
.din62_WIDTH( 6 ),
.din63_WIDTH( 6 ),
.din64_WIDTH( 6 ),
.din65_WIDTH( 6 ),
.din66_WIDTH( 6 ),
.din67_WIDTH( 6 ),
.din68_WIDTH( 6 ),
.din69_WIDTH( 6 ),
.din70_WIDTH( 6 ),
.din71_WIDTH( 6 ),
.din72_WIDTH( 6 ),
.din73_WIDTH( 6 ),
.din74_WIDTH( 6 ),
.din75_WIDTH( 6 ),
.din76_WIDTH( 6 ),
.din77_WIDTH( 6 ),
.din78_WIDTH( 6 ),
.din79_WIDTH( 6 ),
.din80_WIDTH( 6 ),
.din81_WIDTH( 6 ),
.din82_WIDTH( 6 ),
.din83_WIDTH( 6 ),
.din84_WIDTH( 6 ),
.din85_WIDTH( 6 ),
.din86_WIDTH( 6 ),
.din87_WIDTH( 6 ),
.din88_WIDTH( 6 ),
.din89_WIDTH( 6 ),
.din90_WIDTH( 6 ),
.din91_WIDTH( 6 ),
.din92_WIDTH( 6 ),
.din93_WIDTH( 6 ),
.din94_WIDTH( 6 ),
.din95_WIDTH( 6 ),
.din96_WIDTH( 6 ),
.din97_WIDTH( 6 ),
.din98_WIDTH( 6 ),
.din99_WIDTH( 6 ),
.din100_WIDTH( 6 ),
.din101_WIDTH( 6 ),
.din102_WIDTH( 6 ),
.din103_WIDTH( 6 ),
.din104_WIDTH( 6 ),
.din105_WIDTH( 6 ),
.din106_WIDTH( 6 ),
.din107_WIDTH( 6 ),
.din108_WIDTH( 6 ),
.din109_WIDTH( 6 ),
.din110_WIDTH( 6 ),
.din111_WIDTH( 6 ),
.din112_WIDTH( 6 ),
.din113_WIDTH( 6 ),
.din114_WIDTH( 6 ),
.din115_WIDTH( 6 ),
.din116_WIDTH( 6 ),
.din117_WIDTH( 6 ),
.din118_WIDTH( 6 ),
.din119_WIDTH( 6 ),
.din120_WIDTH( 6 ),
.din121_WIDTH( 6 ),
.din122_WIDTH( 6 ),
.din123_WIDTH( 6 ),
.din124_WIDTH( 6 ),
.din125_WIDTH( 6 ),
.din126_WIDTH( 6 ),
.din127_WIDTH( 6 ),
.din128_WIDTH( 6 ),
.din129_WIDTH( 7 ),
.dout_WIDTH( 6 ))
sp_mux_128to1_sel7_6_1_U1(
.din1(primitive11_0_th_mem_V_read),
.din2(primitive11_1_th_mem_V_read),
.din3(primitive11_2_th_mem_V_read),
.din4(primitive11_3_th_mem_V_read),
.din5(primitive11_4_th_mem_V_read),
.din6(primitive11_5_th_mem_V_read),
.din7(primitive11_6_th_mem_V_read),
.din8(primitive11_7_th_mem_V_read),
.din9(primitive11_8_th_mem_V_read),
.din10(primitive11_9_th_mem_V_read),
.din11(primitive11_10_th_mem_V_read),
.din12(primitive11_11_th_mem_V_read),
.din13(primitive11_12_th_mem_V_read),
.din14(primitive11_13_th_mem_V_read),
.din15(primitive11_14_th_mem_V_read),
.din16(primitive11_15_th_mem_V_read),
.din17(primitive11_16_th_mem_V_read),
.din18(primitive11_17_th_mem_V_read),
.din19(primitive11_18_th_mem_V_read),
.din20(primitive11_19_th_mem_V_read),
.din21(primitive11_20_th_mem_V_read),
.din22(primitive11_21_th_mem_V_read),
.din23(primitive11_22_th_mem_V_read),
.din24(primitive11_23_th_mem_V_read),
.din25(primitive11_24_th_mem_V_read),
.din26(primitive11_25_th_mem_V_read),
.din27(primitive11_26_th_mem_V_read),
.din28(primitive11_27_th_mem_V_read),
.din29(primitive11_28_th_mem_V_read),
.din30(primitive11_29_th_mem_V_read),
.din31(primitive11_30_th_mem_V_read),
.din32(primitive11_31_th_mem_V_read),
.din33(primitive11_32_th_mem_V_read),
.din34(primitive11_33_th_mem_V_read),
.din35(primitive11_34_th_mem_V_read),
.din36(primitive11_35_th_mem_V_read),
.din37(primitive11_36_th_mem_V_read),
.din38(primitive11_37_th_mem_V_read),
.din39(primitive11_38_th_mem_V_read),
.din40(primitive11_39_th_mem_V_read),
.din41(primitive11_40_th_mem_V_read),
.din42(primitive11_41_th_mem_V_read),
.din43(primitive11_42_th_mem_V_read),
.din44(primitive11_43_th_mem_V_read),
.din45(primitive11_44_th_mem_V_read),
.din46(primitive11_45_th_mem_V_read),
.din47(primitive11_46_th_mem_V_read),
.din48(primitive11_47_th_mem_V_read),
.din49(primitive11_48_th_mem_V_read),
.din50(primitive11_49_th_mem_V_read),
.din51(primitive11_50_th_mem_V_read),
.din52(primitive11_51_th_mem_V_read),
.din53(primitive11_52_th_mem_V_read),
.din54(primitive11_53_th_mem_V_read),
.din55(primitive11_54_th_mem_V_read),
.din56(primitive11_55_th_mem_V_read),
.din57(primitive11_56_th_mem_V_read),
.din58(primitive11_57_th_mem_V_read),
.din59(primitive11_58_th_mem_V_read),
.din60(primitive11_59_th_mem_V_read),
.din61(primitive11_60_th_mem_V_read),
.din62(primitive11_61_th_mem_V_read),
.din63(primitive11_62_th_mem_V_read),
.din64(primitive11_63_th_mem_V_read),
.din65(primitive11_64_th_mem_V_read),
.din66(primitive11_65_th_mem_V_read),
.din67(primitive11_66_th_mem_V_read),
.din68(primitive11_67_th_mem_V_read),
.din69(primitive11_68_th_mem_V_read),
.din70(primitive11_69_th_mem_V_read),
.din71(primitive11_70_th_mem_V_read),
.din72(primitive11_71_th_mem_V_read),
.din73(primitive11_72_th_mem_V_read),
.din74(primitive11_73_th_mem_V_read),
.din75(primitive11_74_th_mem_V_read),
.din76(primitive11_75_th_mem_V_read),
.din77(primitive11_76_th_mem_V_read),
.din78(primitive11_77_th_mem_V_read),
.din79(primitive11_78_th_mem_V_read),
.din80(primitive11_79_th_mem_V_read),
.din81(primitive11_80_th_mem_V_read),
.din82(primitive11_81_th_mem_V_read),
.din83(primitive11_82_th_mem_V_read),
.din84(primitive11_83_th_mem_V_read),
.din85(primitive11_84_th_mem_V_read),
.din86(primitive11_85_th_mem_V_read),
.din87(primitive11_86_th_mem_V_read),
.din88(primitive11_87_th_mem_V_read),
.din89(primitive11_88_th_mem_V_read),
.din90(primitive11_89_th_mem_V_read),
.din91(primitive11_90_th_mem_V_read),
.din92(primitive11_91_th_mem_V_read),
.din93(primitive11_92_th_mem_V_read),
.din94(primitive11_93_th_mem_V_read),
.din95(primitive11_94_th_mem_V_read),
.din96(primitive11_95_th_mem_V_read),
.din97(primitive11_96_th_mem_V_read),
.din98(primitive11_97_th_mem_V_read),
.din99(primitive11_98_th_mem_V_read),
.din100(primitive11_99_th_mem_V_read),
.din101(primitive11_100_th_mem_V_read),
.din102(primitive11_101_th_mem_V_read),
.din103(primitive11_102_th_mem_V_read),
.din104(primitive11_103_th_mem_V_read),
.din105(primitive11_104_th_mem_V_read),
.din106(primitive11_105_th_mem_V_read),
.din107(primitive11_106_th_mem_V_read),
.din108(primitive11_107_th_mem_V_read),
.din109(primitive11_108_th_mem_V_read),
.din110(primitive11_109_th_mem_V_read),
.din111(primitive11_110_th_mem_V_read),
.din112(primitive11_111_th_mem_V_read),
.din113(primitive11_112_th_mem_V_read),
.din114(primitive11_113_th_mem_V_read),
.din115(primitive11_114_th_mem_V_read),
.din116(primitive11_115_th_mem_V_read),
.din117(primitive11_116_th_mem_V_read),
.din118(primitive11_117_th_mem_V_read),
.din119(primitive11_118_th_mem_V_read),
.din120(primitive11_119_th_mem_V_read),
.din121(primitive11_120_th_mem_V_read),
.din122(primitive11_121_th_mem_V_read),
.din123(primitive11_122_th_mem_V_read),
.din124(primitive11_123_th_mem_V_read),
.din125(primitive11_124_th_mem_V_read),
.din126(primitive11_125_th_mem_V_read),
.din127(primitive11_126_th_mem_V_read),
.din128(primitive11_127_th_mem_V_read),
.din129(wiregroup_0_V_read),
.dout(tmp_139_fu_2634_p130)
);
sp_mux_128to1_sel7_4_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 4 ),
.din2_WIDTH( 4 ),
.din3_WIDTH( 4 ),
.din4_WIDTH( 4 ),
.din5_WIDTH( 4 ),
.din6_WIDTH( 4 ),
.din7_WIDTH( 4 ),
.din8_WIDTH( 4 ),
.din9_WIDTH( 4 ),
.din10_WIDTH( 4 ),
.din11_WIDTH( 4 ),
.din12_WIDTH( 4 ),
.din13_WIDTH( 4 ),
.din14_WIDTH( 4 ),
.din15_WIDTH( 4 ),
.din16_WIDTH( 4 ),
.din17_WIDTH( 4 ),
.din18_WIDTH( 4 ),
.din19_WIDTH( 4 ),
.din20_WIDTH( 4 ),
.din21_WIDTH( 4 ),
.din22_WIDTH( 4 ),
.din23_WIDTH( 4 ),
.din24_WIDTH( 4 ),
.din25_WIDTH( 4 ),
.din26_WIDTH( 4 ),
.din27_WIDTH( 4 ),
.din28_WIDTH( 4 ),
.din29_WIDTH( 4 ),
.din30_WIDTH( 4 ),
.din31_WIDTH( 4 ),
.din32_WIDTH( 4 ),
.din33_WIDTH( 4 ),
.din34_WIDTH( 4 ),
.din35_WIDTH( 4 ),
.din36_WIDTH( 4 ),
.din37_WIDTH( 4 ),
.din38_WIDTH( 4 ),
.din39_WIDTH( 4 ),
.din40_WIDTH( 4 ),
.din41_WIDTH( 4 ),
.din42_WIDTH( 4 ),
.din43_WIDTH( 4 ),
.din44_WIDTH( 4 ),
.din45_WIDTH( 4 ),
.din46_WIDTH( 4 ),
.din47_WIDTH( 4 ),
.din48_WIDTH( 4 ),
.din49_WIDTH( 4 ),
.din50_WIDTH( 4 ),
.din51_WIDTH( 4 ),
.din52_WIDTH( 4 ),
.din53_WIDTH( 4 ),
.din54_WIDTH( 4 ),
.din55_WIDTH( 4 ),
.din56_WIDTH( 4 ),
.din57_WIDTH( 4 ),
.din58_WIDTH( 4 ),
.din59_WIDTH( 4 ),
.din60_WIDTH( 4 ),
.din61_WIDTH( 4 ),
.din62_WIDTH( 4 ),
.din63_WIDTH( 4 ),
.din64_WIDTH( 4 ),
.din65_WIDTH( 4 ),
.din66_WIDTH( 4 ),
.din67_WIDTH( 4 ),
.din68_WIDTH( 4 ),
.din69_WIDTH( 4 ),
.din70_WIDTH( 4 ),
.din71_WIDTH( 4 ),
.din72_WIDTH( 4 ),
.din73_WIDTH( 4 ),
.din74_WIDTH( 4 ),
.din75_WIDTH( 4 ),
.din76_WIDTH( 4 ),
.din77_WIDTH( 4 ),
.din78_WIDTH( 4 ),
.din79_WIDTH( 4 ),
.din80_WIDTH( 4 ),
.din81_WIDTH( 4 ),
.din82_WIDTH( 4 ),
.din83_WIDTH( 4 ),
.din84_WIDTH( 4 ),
.din85_WIDTH( 4 ),
.din86_WIDTH( 4 ),
.din87_WIDTH( 4 ),
.din88_WIDTH( 4 ),
.din89_WIDTH( 4 ),
.din90_WIDTH( 4 ),
.din91_WIDTH( 4 ),
.din92_WIDTH( 4 ),
.din93_WIDTH( 4 ),
.din94_WIDTH( 4 ),
.din95_WIDTH( 4 ),
.din96_WIDTH( 4 ),
.din97_WIDTH( 4 ),
.din98_WIDTH( 4 ),
.din99_WIDTH( 4 ),
.din100_WIDTH( 4 ),
.din101_WIDTH( 4 ),
.din102_WIDTH( 4 ),
.din103_WIDTH( 4 ),
.din104_WIDTH( 4 ),
.din105_WIDTH( 4 ),
.din106_WIDTH( 4 ),
.din107_WIDTH( 4 ),
.din108_WIDTH( 4 ),
.din109_WIDTH( 4 ),
.din110_WIDTH( 4 ),
.din111_WIDTH( 4 ),
.din112_WIDTH( 4 ),
.din113_WIDTH( 4 ),
.din114_WIDTH( 4 ),
.din115_WIDTH( 4 ),
.din116_WIDTH( 4 ),
.din117_WIDTH( 4 ),
.din118_WIDTH( 4 ),
.din119_WIDTH( 4 ),
.din120_WIDTH( 4 ),
.din121_WIDTH( 4 ),
.din122_WIDTH( 4 ),
.din123_WIDTH( 4 ),
.din124_WIDTH( 4 ),
.din125_WIDTH( 4 ),
.din126_WIDTH( 4 ),
.din127_WIDTH( 4 ),
.din128_WIDTH( 4 ),
.din129_WIDTH( 7 ),
.dout_WIDTH( 4 ))
sp_mux_128to1_sel7_4_1_U2(
.din1(primitive11_0_th_corr_mem_V_read),
.din2(primitive11_1_th_corr_mem_V_read),
.din3(primitive11_2_th_corr_mem_V_read),
.din4(primitive11_3_th_corr_mem_V_read),
.din5(primitive11_4_th_corr_mem_V_read),
.din6(primitive11_5_th_corr_mem_V_read),
.din7(primitive11_6_th_corr_mem_V_read),
.din8(primitive11_7_th_corr_mem_V_read),
.din9(primitive11_8_th_corr_mem_V_read),
.din10(primitive11_9_th_corr_mem_V_read),
.din11(primitive11_10_th_corr_mem_V_read),
.din12(primitive11_11_th_corr_mem_V_read),
.din13(primitive11_12_th_corr_mem_V_read),
.din14(primitive11_13_th_corr_mem_V_read),
.din15(primitive11_14_th_corr_mem_V_read),
.din16(primitive11_15_th_corr_mem_V_read),
.din17(primitive11_16_th_corr_mem_V_read),
.din18(primitive11_17_th_corr_mem_V_read),
.din19(primitive11_18_th_corr_mem_V_read),
.din20(primitive11_19_th_corr_mem_V_read),
.din21(primitive11_20_th_corr_mem_V_read),
.din22(primitive11_21_th_corr_mem_V_read),
.din23(primitive11_22_th_corr_mem_V_read),
.din24(primitive11_23_th_corr_mem_V_read),
.din25(primitive11_24_th_corr_mem_V_read),
.din26(primitive11_25_th_corr_mem_V_read),
.din27(primitive11_26_th_corr_mem_V_read),
.din28(primitive11_27_th_corr_mem_V_read),
.din29(primitive11_28_th_corr_mem_V_read),
.din30(primitive11_29_th_corr_mem_V_read),
.din31(primitive11_30_th_corr_mem_V_read),
.din32(primitive11_31_th_corr_mem_V_read),
.din33(primitive11_32_th_corr_mem_V_read),
.din34(primitive11_33_th_corr_mem_V_read),
.din35(primitive11_34_th_corr_mem_V_read),
.din36(primitive11_35_th_corr_mem_V_read),
.din37(primitive11_36_th_corr_mem_V_read),
.din38(primitive11_37_th_corr_mem_V_read),
.din39(primitive11_38_th_corr_mem_V_read),
.din40(primitive11_39_th_corr_mem_V_read),
.din41(primitive11_40_th_corr_mem_V_read),
.din42(primitive11_41_th_corr_mem_V_read),
.din43(primitive11_42_th_corr_mem_V_read),
.din44(primitive11_43_th_corr_mem_V_read),
.din45(primitive11_44_th_corr_mem_V_read),
.din46(primitive11_45_th_corr_mem_V_read),
.din47(primitive11_46_th_corr_mem_V_read),
.din48(primitive11_47_th_corr_mem_V_read),
.din49(primitive11_48_th_corr_mem_V_read),
.din50(primitive11_49_th_corr_mem_V_read),
.din51(primitive11_50_th_corr_mem_V_read),
.din52(primitive11_51_th_corr_mem_V_read),
.din53(primitive11_52_th_corr_mem_V_read),
.din54(primitive11_53_th_corr_mem_V_read),
.din55(primitive11_54_th_corr_mem_V_read),
.din56(primitive11_55_th_corr_mem_V_read),
.din57(primitive11_56_th_corr_mem_V_read),
.din58(primitive11_57_th_corr_mem_V_read),
.din59(primitive11_58_th_corr_mem_V_read),
.din60(primitive11_59_th_corr_mem_V_read),
.din61(primitive11_60_th_corr_mem_V_read),
.din62(primitive11_61_th_corr_mem_V_read),
.din63(primitive11_62_th_corr_mem_V_read),
.din64(primitive11_63_th_corr_mem_V_read),
.din65(primitive11_64_th_corr_mem_V_read),
.din66(primitive11_65_th_corr_mem_V_read),
.din67(primitive11_66_th_corr_mem_V_read),
.din68(primitive11_67_th_corr_mem_V_read),
.din69(primitive11_68_th_corr_mem_V_read),
.din70(primitive11_69_th_corr_mem_V_read),
.din71(primitive11_70_th_corr_mem_V_read),
.din72(primitive11_71_th_corr_mem_V_read),
.din73(primitive11_72_th_corr_mem_V_read),
.din74(primitive11_73_th_corr_mem_V_read),
.din75(primitive11_74_th_corr_mem_V_read),
.din76(primitive11_75_th_corr_mem_V_read),
.din77(primitive11_76_th_corr_mem_V_read),
.din78(primitive11_77_th_corr_mem_V_read),
.din79(primitive11_78_th_corr_mem_V_read),
.din80(primitive11_79_th_corr_mem_V_read),
.din81(primitive11_80_th_corr_mem_V_read),
.din82(primitive11_81_th_corr_mem_V_read),
.din83(primitive11_82_th_corr_mem_V_read),
.din84(primitive11_83_th_corr_mem_V_read),
.din85(primitive11_84_th_corr_mem_V_read),
.din86(primitive11_85_th_corr_mem_V_read),
.din87(primitive11_86_th_corr_mem_V_read),
.din88(primitive11_87_th_corr_mem_V_read),
.din89(primitive11_88_th_corr_mem_V_read),
.din90(primitive11_89_th_corr_mem_V_read),
.din91(primitive11_90_th_corr_mem_V_read),
.din92(primitive11_91_th_corr_mem_V_read),
.din93(primitive11_92_th_corr_mem_V_read),
.din94(primitive11_93_th_corr_mem_V_read),
.din95(primitive11_94_th_corr_mem_V_read),
.din96(primitive11_95_th_corr_mem_V_read),
.din97(primitive11_96_th_corr_mem_V_read),
.din98(primitive11_97_th_corr_mem_V_read),
.din99(primitive11_98_th_corr_mem_V_read),
.din100(primitive11_99_th_corr_mem_V_read),
.din101(primitive11_100_th_corr_mem_V_read),
.din102(primitive11_101_th_corr_mem_V_read),
.din103(primitive11_102_th_corr_mem_V_read),
.din104(primitive11_103_th_corr_mem_V_read),
.din105(primitive11_104_th_corr_mem_V_read),
.din106(primitive11_105_th_corr_mem_V_read),
.din107(primitive11_106_th_corr_mem_V_read),
.din108(primitive11_107_th_corr_mem_V_read),
.din109(primitive11_108_th_corr_mem_V_read),
.din110(primitive11_109_th_corr_mem_V_read),
.din111(primitive11_110_th_corr_mem_V_read),
.din112(primitive11_111_th_corr_mem_V_read),
.din113(primitive11_112_th_corr_mem_V_read),
.din114(primitive11_113_th_corr_mem_V_read),
.din115(primitive11_114_th_corr_mem_V_read),
.din116(primitive11_115_th_corr_mem_V_read),
.din117(primitive11_116_th_corr_mem_V_read),
.din118(primitive11_117_th_corr_mem_V_read),
.din119(primitive11_118_th_corr_mem_V_read),
.din120(primitive11_119_th_corr_mem_V_read),
.din121(primitive11_120_th_corr_mem_V_read),
.din122(primitive11_121_th_corr_mem_V_read),
.din123(primitive11_122_th_corr_mem_V_read),
.din124(primitive11_123_th_corr_mem_V_read),
.din125(primitive11_124_th_corr_mem_V_read),
.din126(primitive11_125_th_corr_mem_V_read),
.din127(primitive11_126_th_corr_mem_V_read),
.din128(primitive11_127_th_corr_mem_V_read),
.din129(tmp_140_fu_2924_p129),
.dout(tmp_140_fu_2924_p130)
);
sp_mux_128to1_sel7_4_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 4 ),
.din2_WIDTH( 4 ),
.din3_WIDTH( 4 ),
.din4_WIDTH( 4 ),
.din5_WIDTH( 4 ),
.din6_WIDTH( 4 ),
.din7_WIDTH( 4 ),
.din8_WIDTH( 4 ),
.din9_WIDTH( 4 ),
.din10_WIDTH( 4 ),
.din11_WIDTH( 4 ),
.din12_WIDTH( 4 ),
.din13_WIDTH( 4 ),
.din14_WIDTH( 4 ),
.din15_WIDTH( 4 ),
.din16_WIDTH( 4 ),
.din17_WIDTH( 4 ),
.din18_WIDTH( 4 ),
.din19_WIDTH( 4 ),
.din20_WIDTH( 4 ),
.din21_WIDTH( 4 ),
.din22_WIDTH( 4 ),
.din23_WIDTH( 4 ),
.din24_WIDTH( 4 ),
.din25_WIDTH( 4 ),
.din26_WIDTH( 4 ),
.din27_WIDTH( 4 ),
.din28_WIDTH( 4 ),
.din29_WIDTH( 4 ),
.din30_WIDTH( 4 ),
.din31_WIDTH( 4 ),
.din32_WIDTH( 4 ),
.din33_WIDTH( 4 ),
.din34_WIDTH( 4 ),
.din35_WIDTH( 4 ),
.din36_WIDTH( 4 ),
.din37_WIDTH( 4 ),
.din38_WIDTH( 4 ),
.din39_WIDTH( 4 ),
.din40_WIDTH( 4 ),
.din41_WIDTH( 4 ),
.din42_WIDTH( 4 ),
.din43_WIDTH( 4 ),
.din44_WIDTH( 4 ),
.din45_WIDTH( 4 ),
.din46_WIDTH( 4 ),
.din47_WIDTH( 4 ),
.din48_WIDTH( 4 ),
.din49_WIDTH( 4 ),
.din50_WIDTH( 4 ),
.din51_WIDTH( 4 ),
.din52_WIDTH( 4 ),
.din53_WIDTH( 4 ),
.din54_WIDTH( 4 ),
.din55_WIDTH( 4 ),
.din56_WIDTH( 4 ),
.din57_WIDTH( 4 ),
.din58_WIDTH( 4 ),
.din59_WIDTH( 4 ),
.din60_WIDTH( 4 ),
.din61_WIDTH( 4 ),
.din62_WIDTH( 4 ),
.din63_WIDTH( 4 ),
.din64_WIDTH( 4 ),
.din65_WIDTH( 4 ),
.din66_WIDTH( 4 ),
.din67_WIDTH( 4 ),
.din68_WIDTH( 4 ),
.din69_WIDTH( 4 ),
.din70_WIDTH( 4 ),
.din71_WIDTH( 4 ),
.din72_WIDTH( 4 ),
.din73_WIDTH( 4 ),
.din74_WIDTH( 4 ),
.din75_WIDTH( 4 ),
.din76_WIDTH( 4 ),
.din77_WIDTH( 4 ),
.din78_WIDTH( 4 ),
.din79_WIDTH( 4 ),
.din80_WIDTH( 4 ),
.din81_WIDTH( 4 ),
.din82_WIDTH( 4 ),
.din83_WIDTH( 4 ),
.din84_WIDTH( 4 ),
.din85_WIDTH( 4 ),
.din86_WIDTH( 4 ),
.din87_WIDTH( 4 ),
.din88_WIDTH( 4 ),
.din89_WIDTH( 4 ),
.din90_WIDTH( 4 ),
.din91_WIDTH( 4 ),
.din92_WIDTH( 4 ),
.din93_WIDTH( 4 ),
.din94_WIDTH( 4 ),
.din95_WIDTH( 4 ),
.din96_WIDTH( 4 ),
.din97_WIDTH( 4 ),
.din98_WIDTH( 4 ),
.din99_WIDTH( 4 ),
.din100_WIDTH( 4 ),
.din101_WIDTH( 4 ),
.din102_WIDTH( 4 ),
.din103_WIDTH( 4 ),
.din104_WIDTH( 4 ),
.din105_WIDTH( 4 ),
.din106_WIDTH( 4 ),
.din107_WIDTH( 4 ),
.din108_WIDTH( 4 ),
.din109_WIDTH( 4 ),
.din110_WIDTH( 4 ),
.din111_WIDTH( 4 ),
.din112_WIDTH( 4 ),
.din113_WIDTH( 4 ),
.din114_WIDTH( 4 ),
.din115_WIDTH( 4 ),
.din116_WIDTH( 4 ),
.din117_WIDTH( 4 ),
.din118_WIDTH( 4 ),
.din119_WIDTH( 4 ),
.din120_WIDTH( 4 ),
.din121_WIDTH( 4 ),
.din122_WIDTH( 4 ),
.din123_WIDTH( 4 ),
.din124_WIDTH( 4 ),
.din125_WIDTH( 4 ),
.din126_WIDTH( 4 ),
.din127_WIDTH( 4 ),
.din128_WIDTH( 4 ),
.din129_WIDTH( 7 ),
.dout_WIDTH( 4 ))
sp_mux_128to1_sel7_4_1_U3(
.din1(primitive11_0_th_corr_mem_V_read),
.din2(primitive11_1_th_corr_mem_V_read),
.din3(primitive11_2_th_corr_mem_V_read),
.din4(primitive11_3_th_corr_mem_V_read),
.din5(primitive11_4_th_corr_mem_V_read),
.din6(primitive11_5_th_corr_mem_V_read),
.din7(primitive11_6_th_corr_mem_V_read),
.din8(primitive11_7_th_corr_mem_V_read),
.din9(primitive11_8_th_corr_mem_V_read),
.din10(primitive11_9_th_corr_mem_V_read),
.din11(primitive11_10_th_corr_mem_V_read),
.din12(primitive11_11_th_corr_mem_V_read),
.din13(primitive11_12_th_corr_mem_V_read),
.din14(primitive11_13_th_corr_mem_V_read),
.din15(primitive11_14_th_corr_mem_V_read),
.din16(primitive11_15_th_corr_mem_V_read),
.din17(primitive11_16_th_corr_mem_V_read),
.din18(primitive11_17_th_corr_mem_V_read),
.din19(primitive11_18_th_corr_mem_V_read),
.din20(primitive11_19_th_corr_mem_V_read),
.din21(primitive11_20_th_corr_mem_V_read),
.din22(primitive11_21_th_corr_mem_V_read),
.din23(primitive11_22_th_corr_mem_V_read),
.din24(primitive11_23_th_corr_mem_V_read),
.din25(primitive11_24_th_corr_mem_V_read),
.din26(primitive11_25_th_corr_mem_V_read),
.din27(primitive11_26_th_corr_mem_V_read),
.din28(primitive11_27_th_corr_mem_V_read),
.din29(primitive11_28_th_corr_mem_V_read),
.din30(primitive11_29_th_corr_mem_V_read),
.din31(primitive11_30_th_corr_mem_V_read),
.din32(primitive11_31_th_corr_mem_V_read),
.din33(primitive11_32_th_corr_mem_V_read),
.din34(primitive11_33_th_corr_mem_V_read),
.din35(primitive11_34_th_corr_mem_V_read),
.din36(primitive11_35_th_corr_mem_V_read),
.din37(primitive11_36_th_corr_mem_V_read),
.din38(primitive11_37_th_corr_mem_V_read),
.din39(primitive11_38_th_corr_mem_V_read),
.din40(primitive11_39_th_corr_mem_V_read),
.din41(primitive11_40_th_corr_mem_V_read),
.din42(primitive11_41_th_corr_mem_V_read),
.din43(primitive11_42_th_corr_mem_V_read),
.din44(primitive11_43_th_corr_mem_V_read),
.din45(primitive11_44_th_corr_mem_V_read),
.din46(primitive11_45_th_corr_mem_V_read),
.din47(primitive11_46_th_corr_mem_V_read),
.din48(primitive11_47_th_corr_mem_V_read),
.din49(primitive11_48_th_corr_mem_V_read),
.din50(primitive11_49_th_corr_mem_V_read),
.din51(primitive11_50_th_corr_mem_V_read),
.din52(primitive11_51_th_corr_mem_V_read),
.din53(primitive11_52_th_corr_mem_V_read),
.din54(primitive11_53_th_corr_mem_V_read),
.din55(primitive11_54_th_corr_mem_V_read),
.din56(primitive11_55_th_corr_mem_V_read),
.din57(primitive11_56_th_corr_mem_V_read),
.din58(primitive11_57_th_corr_mem_V_read),
.din59(primitive11_58_th_corr_mem_V_read),
.din60(primitive11_59_th_corr_mem_V_read),
.din61(primitive11_60_th_corr_mem_V_read),
.din62(primitive11_61_th_corr_mem_V_read),
.din63(primitive11_62_th_corr_mem_V_read),
.din64(primitive11_63_th_corr_mem_V_read),
.din65(primitive11_64_th_corr_mem_V_read),
.din66(primitive11_65_th_corr_mem_V_read),
.din67(primitive11_66_th_corr_mem_V_read),
.din68(primitive11_67_th_corr_mem_V_read),
.din69(primitive11_68_th_corr_mem_V_read),
.din70(primitive11_69_th_corr_mem_V_read),
.din71(primitive11_70_th_corr_mem_V_read),
.din72(primitive11_71_th_corr_mem_V_read),
.din73(primitive11_72_th_corr_mem_V_read),
.din74(primitive11_73_th_corr_mem_V_read),
.din75(primitive11_74_th_corr_mem_V_read),
.din76(primitive11_75_th_corr_mem_V_read),
.din77(primitive11_76_th_corr_mem_V_read),
.din78(primitive11_77_th_corr_mem_V_read),
.din79(primitive11_78_th_corr_mem_V_read),
.din80(primitive11_79_th_corr_mem_V_read),
.din81(primitive11_80_th_corr_mem_V_read),
.din82(primitive11_81_th_corr_mem_V_read),
.din83(primitive11_82_th_corr_mem_V_read),
.din84(primitive11_83_th_corr_mem_V_read),
.din85(primitive11_84_th_corr_mem_V_read),
.din86(primitive11_85_th_corr_mem_V_read),
.din87(primitive11_86_th_corr_mem_V_read),
.din88(primitive11_87_th_corr_mem_V_read),
.din89(primitive11_88_th_corr_mem_V_read),
.din90(primitive11_89_th_corr_mem_V_read),
.din91(primitive11_90_th_corr_mem_V_read),
.din92(primitive11_91_th_corr_mem_V_read),
.din93(primitive11_92_th_corr_mem_V_read),
.din94(primitive11_93_th_corr_mem_V_read),
.din95(primitive11_94_th_corr_mem_V_read),
.din96(primitive11_95_th_corr_mem_V_read),
.din97(primitive11_96_th_corr_mem_V_read),
.din98(primitive11_97_th_corr_mem_V_read),
.din99(primitive11_98_th_corr_mem_V_read),
.din100(primitive11_99_th_corr_mem_V_read),
.din101(primitive11_100_th_corr_mem_V_read),
.din102(primitive11_101_th_corr_mem_V_read),
.din103(primitive11_102_th_corr_mem_V_read),
.din104(primitive11_103_th_corr_mem_V_read),
.din105(primitive11_104_th_corr_mem_V_read),
.din106(primitive11_105_th_corr_mem_V_read),
.din107(primitive11_106_th_corr_mem_V_read),
.din108(primitive11_107_th_corr_mem_V_read),
.din109(primitive11_108_th_corr_mem_V_read),
.din110(primitive11_109_th_corr_mem_V_read),
.din111(primitive11_110_th_corr_mem_V_read),
.din112(primitive11_111_th_corr_mem_V_read),
.din113(primitive11_112_th_corr_mem_V_read),
.din114(primitive11_113_th_corr_mem_V_read),
.din115(primitive11_114_th_corr_mem_V_read),
.din116(primitive11_115_th_corr_mem_V_read),
.din117(primitive11_116_th_corr_mem_V_read),
.din118(primitive11_117_th_corr_mem_V_read),
.din119(primitive11_118_th_corr_mem_V_read),
.din120(primitive11_119_th_corr_mem_V_read),
.din121(primitive11_120_th_corr_mem_V_read),
.din122(primitive11_121_th_corr_mem_V_read),
.din123(primitive11_122_th_corr_mem_V_read),
.din124(primitive11_123_th_corr_mem_V_read),
.din125(primitive11_124_th_corr_mem_V_read),
.din126(primitive11_125_th_corr_mem_V_read),
.din127(primitive11_126_th_corr_mem_V_read),
.din128(primitive11_127_th_corr_mem_V_read),
.din129(tmp_146_fu_3314_p129),
.dout(tmp_146_fu_3314_p130)
);
sp_mux_128to1_sel7_6_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 6 ),
.din2_WIDTH( 6 ),
.din3_WIDTH( 6 ),
.din4_WIDTH( 6 ),
.din5_WIDTH( 6 ),
.din6_WIDTH( 6 ),
.din7_WIDTH( 6 ),
.din8_WIDTH( 6 ),
.din9_WIDTH( 6 ),
.din10_WIDTH( 6 ),
.din11_WIDTH( 6 ),
.din12_WIDTH( 6 ),
.din13_WIDTH( 6 ),
.din14_WIDTH( 6 ),
.din15_WIDTH( 6 ),
.din16_WIDTH( 6 ),
.din17_WIDTH( 6 ),
.din18_WIDTH( 6 ),
.din19_WIDTH( 6 ),
.din20_WIDTH( 6 ),
.din21_WIDTH( 6 ),
.din22_WIDTH( 6 ),
.din23_WIDTH( 6 ),
.din24_WIDTH( 6 ),
.din25_WIDTH( 6 ),
.din26_WIDTH( 6 ),
.din27_WIDTH( 6 ),
.din28_WIDTH( 6 ),
.din29_WIDTH( 6 ),
.din30_WIDTH( 6 ),
.din31_WIDTH( 6 ),
.din32_WIDTH( 6 ),
.din33_WIDTH( 6 ),
.din34_WIDTH( 6 ),
.din35_WIDTH( 6 ),
.din36_WIDTH( 6 ),
.din37_WIDTH( 6 ),
.din38_WIDTH( 6 ),
.din39_WIDTH( 6 ),
.din40_WIDTH( 6 ),
.din41_WIDTH( 6 ),
.din42_WIDTH( 6 ),
.din43_WIDTH( 6 ),
.din44_WIDTH( 6 ),
.din45_WIDTH( 6 ),
.din46_WIDTH( 6 ),
.din47_WIDTH( 6 ),
.din48_WIDTH( 6 ),
.din49_WIDTH( 6 ),
.din50_WIDTH( 6 ),
.din51_WIDTH( 6 ),
.din52_WIDTH( 6 ),
.din53_WIDTH( 6 ),
.din54_WIDTH( 6 ),
.din55_WIDTH( 6 ),
.din56_WIDTH( 6 ),
.din57_WIDTH( 6 ),
.din58_WIDTH( 6 ),
.din59_WIDTH( 6 ),
.din60_WIDTH( 6 ),
.din61_WIDTH( 6 ),
.din62_WIDTH( 6 ),
.din63_WIDTH( 6 ),
.din64_WIDTH( 6 ),
.din65_WIDTH( 6 ),
.din66_WIDTH( 6 ),
.din67_WIDTH( 6 ),
.din68_WIDTH( 6 ),
.din69_WIDTH( 6 ),
.din70_WIDTH( 6 ),
.din71_WIDTH( 6 ),
.din72_WIDTH( 6 ),
.din73_WIDTH( 6 ),
.din74_WIDTH( 6 ),
.din75_WIDTH( 6 ),
.din76_WIDTH( 6 ),
.din77_WIDTH( 6 ),
.din78_WIDTH( 6 ),
.din79_WIDTH( 6 ),
.din80_WIDTH( 6 ),
.din81_WIDTH( 6 ),
.din82_WIDTH( 6 ),
.din83_WIDTH( 6 ),
.din84_WIDTH( 6 ),
.din85_WIDTH( 6 ),
.din86_WIDTH( 6 ),
.din87_WIDTH( 6 ),
.din88_WIDTH( 6 ),
.din89_WIDTH( 6 ),
.din90_WIDTH( 6 ),
.din91_WIDTH( 6 ),
.din92_WIDTH( 6 ),
.din93_WIDTH( 6 ),
.din94_WIDTH( 6 ),
.din95_WIDTH( 6 ),
.din96_WIDTH( 6 ),
.din97_WIDTH( 6 ),
.din98_WIDTH( 6 ),
.din99_WIDTH( 6 ),
.din100_WIDTH( 6 ),
.din101_WIDTH( 6 ),
.din102_WIDTH( 6 ),
.din103_WIDTH( 6 ),
.din104_WIDTH( 6 ),
.din105_WIDTH( 6 ),
.din106_WIDTH( 6 ),
.din107_WIDTH( 6 ),
.din108_WIDTH( 6 ),
.din109_WIDTH( 6 ),
.din110_WIDTH( 6 ),
.din111_WIDTH( 6 ),
.din112_WIDTH( 6 ),
.din113_WIDTH( 6 ),
.din114_WIDTH( 6 ),
.din115_WIDTH( 6 ),
.din116_WIDTH( 6 ),
.din117_WIDTH( 6 ),
.din118_WIDTH( 6 ),
.din119_WIDTH( 6 ),
.din120_WIDTH( 6 ),
.din121_WIDTH( 6 ),
.din122_WIDTH( 6 ),
.din123_WIDTH( 6 ),
.din124_WIDTH( 6 ),
.din125_WIDTH( 6 ),
.din126_WIDTH( 6 ),
.din127_WIDTH( 6 ),
.din128_WIDTH( 6 ),
.din129_WIDTH( 7 ),
.dout_WIDTH( 6 ))
sp_mux_128to1_sel7_6_1_U4(
.din1(primitive11_0_th_mem_V_read),
.din2(primitive11_1_th_mem_V_read),
.din3(primitive11_2_th_mem_V_read),
.din4(primitive11_3_th_mem_V_read),
.din5(primitive11_4_th_mem_V_read),
.din6(primitive11_5_th_mem_V_read),
.din7(primitive11_6_th_mem_V_read),
.din8(primitive11_7_th_mem_V_read),
.din9(primitive11_8_th_mem_V_read),
.din10(primitive11_9_th_mem_V_read),
.din11(primitive11_10_th_mem_V_read),
.din12(primitive11_11_th_mem_V_read),
.din13(primitive11_12_th_mem_V_read),
.din14(primitive11_13_th_mem_V_read),
.din15(primitive11_14_th_mem_V_read),
.din16(primitive11_15_th_mem_V_read),
.din17(primitive11_16_th_mem_V_read),
.din18(primitive11_17_th_mem_V_read),
.din19(primitive11_18_th_mem_V_read),
.din20(primitive11_19_th_mem_V_read),
.din21(primitive11_20_th_mem_V_read),
.din22(primitive11_21_th_mem_V_read),
.din23(primitive11_22_th_mem_V_read),
.din24(primitive11_23_th_mem_V_read),
.din25(primitive11_24_th_mem_V_read),
.din26(primitive11_25_th_mem_V_read),
.din27(primitive11_26_th_mem_V_read),
.din28(primitive11_27_th_mem_V_read),
.din29(primitive11_28_th_mem_V_read),
.din30(primitive11_29_th_mem_V_read),
.din31(primitive11_30_th_mem_V_read),
.din32(primitive11_31_th_mem_V_read),
.din33(primitive11_32_th_mem_V_read),
.din34(primitive11_33_th_mem_V_read),
.din35(primitive11_34_th_mem_V_read),
.din36(primitive11_35_th_mem_V_read),
.din37(primitive11_36_th_mem_V_read),
.din38(primitive11_37_th_mem_V_read),
.din39(primitive11_38_th_mem_V_read),
.din40(primitive11_39_th_mem_V_read),
.din41(primitive11_40_th_mem_V_read),
.din42(primitive11_41_th_mem_V_read),
.din43(primitive11_42_th_mem_V_read),
.din44(primitive11_43_th_mem_V_read),
.din45(primitive11_44_th_mem_V_read),
.din46(primitive11_45_th_mem_V_read),
.din47(primitive11_46_th_mem_V_read),
.din48(primitive11_47_th_mem_V_read),
.din49(primitive11_48_th_mem_V_read),
.din50(primitive11_49_th_mem_V_read),
.din51(primitive11_50_th_mem_V_read),
.din52(primitive11_51_th_mem_V_read),
.din53(primitive11_52_th_mem_V_read),
.din54(primitive11_53_th_mem_V_read),
.din55(primitive11_54_th_mem_V_read),
.din56(primitive11_55_th_mem_V_read),
.din57(primitive11_56_th_mem_V_read),
.din58(primitive11_57_th_mem_V_read),
.din59(primitive11_58_th_mem_V_read),
.din60(primitive11_59_th_mem_V_read),
.din61(primitive11_60_th_mem_V_read),
.din62(primitive11_61_th_mem_V_read),
.din63(primitive11_62_th_mem_V_read),
.din64(primitive11_63_th_mem_V_read),
.din65(primitive11_64_th_mem_V_read),
.din66(primitive11_65_th_mem_V_read),
.din67(primitive11_66_th_mem_V_read),
.din68(primitive11_67_th_mem_V_read),
.din69(primitive11_68_th_mem_V_read),
.din70(primitive11_69_th_mem_V_read),
.din71(primitive11_70_th_mem_V_read),
.din72(primitive11_71_th_mem_V_read),
.din73(primitive11_72_th_mem_V_read),
.din74(primitive11_73_th_mem_V_read),
.din75(primitive11_74_th_mem_V_read),
.din76(primitive11_75_th_mem_V_read),
.din77(primitive11_76_th_mem_V_read),
.din78(primitive11_77_th_mem_V_read),
.din79(primitive11_78_th_mem_V_read),
.din80(primitive11_79_th_mem_V_read),
.din81(primitive11_80_th_mem_V_read),
.din82(primitive11_81_th_mem_V_read),
.din83(primitive11_82_th_mem_V_read),
.din84(primitive11_83_th_mem_V_read),
.din85(primitive11_84_th_mem_V_read),
.din86(primitive11_85_th_mem_V_read),
.din87(primitive11_86_th_mem_V_read),
.din88(primitive11_87_th_mem_V_read),
.din89(primitive11_88_th_mem_V_read),
.din90(primitive11_89_th_mem_V_read),
.din91(primitive11_90_th_mem_V_read),
.din92(primitive11_91_th_mem_V_read),
.din93(primitive11_92_th_mem_V_read),
.din94(primitive11_93_th_mem_V_read),
.din95(primitive11_94_th_mem_V_read),
.din96(primitive11_95_th_mem_V_read),
.din97(primitive11_96_th_mem_V_read),
.din98(primitive11_97_th_mem_V_read),
.din99(primitive11_98_th_mem_V_read),
.din100(primitive11_99_th_mem_V_read),
.din101(primitive11_100_th_mem_V_read),
.din102(primitive11_101_th_mem_V_read),
.din103(primitive11_102_th_mem_V_read),
.din104(primitive11_103_th_mem_V_read),
.din105(primitive11_104_th_mem_V_read),
.din106(primitive11_105_th_mem_V_read),
.din107(primitive11_106_th_mem_V_read),
.din108(primitive11_107_th_mem_V_read),
.din109(primitive11_108_th_mem_V_read),
.din110(primitive11_109_th_mem_V_read),
.din111(primitive11_110_th_mem_V_read),
.din112(primitive11_111_th_mem_V_read),
.din113(primitive11_112_th_mem_V_read),
.din114(primitive11_113_th_mem_V_read),
.din115(primitive11_114_th_mem_V_read),
.din116(primitive11_115_th_mem_V_read),
.din117(primitive11_116_th_mem_V_read),
.din118(primitive11_117_th_mem_V_read),
.din119(primitive11_118_th_mem_V_read),
.din120(primitive11_119_th_mem_V_read),
.din121(primitive11_120_th_mem_V_read),
.din122(primitive11_121_th_mem_V_read),
.din123(primitive11_122_th_mem_V_read),
.din124(primitive11_123_th_mem_V_read),
.din125(primitive11_124_th_mem_V_read),
.din126(primitive11_125_th_mem_V_read),
.din127(primitive11_126_th_mem_V_read),
.din128(primitive11_127_th_mem_V_read),
.din129(wiregroup_1_V_read),
.dout(tmp_156_fu_4180_p130)
);
sp_mux_128to1_sel7_4_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 4 ),
.din2_WIDTH( 4 ),
.din3_WIDTH( 4 ),
.din4_WIDTH( 4 ),
.din5_WIDTH( 4 ),
.din6_WIDTH( 4 ),
.din7_WIDTH( 4 ),
.din8_WIDTH( 4 ),
.din9_WIDTH( 4 ),
.din10_WIDTH( 4 ),
.din11_WIDTH( 4 ),
.din12_WIDTH( 4 ),
.din13_WIDTH( 4 ),
.din14_WIDTH( 4 ),
.din15_WIDTH( 4 ),
.din16_WIDTH( 4 ),
.din17_WIDTH( 4 ),
.din18_WIDTH( 4 ),
.din19_WIDTH( 4 ),
.din20_WIDTH( 4 ),
.din21_WIDTH( 4 ),
.din22_WIDTH( 4 ),
.din23_WIDTH( 4 ),
.din24_WIDTH( 4 ),
.din25_WIDTH( 4 ),
.din26_WIDTH( 4 ),
.din27_WIDTH( 4 ),
.din28_WIDTH( 4 ),
.din29_WIDTH( 4 ),
.din30_WIDTH( 4 ),
.din31_WIDTH( 4 ),
.din32_WIDTH( 4 ),
.din33_WIDTH( 4 ),
.din34_WIDTH( 4 ),
.din35_WIDTH( 4 ),
.din36_WIDTH( 4 ),
.din37_WIDTH( 4 ),
.din38_WIDTH( 4 ),
.din39_WIDTH( 4 ),
.din40_WIDTH( 4 ),
.din41_WIDTH( 4 ),
.din42_WIDTH( 4 ),
.din43_WIDTH( 4 ),
.din44_WIDTH( 4 ),
.din45_WIDTH( 4 ),
.din46_WIDTH( 4 ),
.din47_WIDTH( 4 ),
.din48_WIDTH( 4 ),
.din49_WIDTH( 4 ),
.din50_WIDTH( 4 ),
.din51_WIDTH( 4 ),
.din52_WIDTH( 4 ),
.din53_WIDTH( 4 ),
.din54_WIDTH( 4 ),
.din55_WIDTH( 4 ),
.din56_WIDTH( 4 ),
.din57_WIDTH( 4 ),
.din58_WIDTH( 4 ),
.din59_WIDTH( 4 ),
.din60_WIDTH( 4 ),
.din61_WIDTH( 4 ),
.din62_WIDTH( 4 ),
.din63_WIDTH( 4 ),
.din64_WIDTH( 4 ),
.din65_WIDTH( 4 ),
.din66_WIDTH( 4 ),
.din67_WIDTH( 4 ),
.din68_WIDTH( 4 ),
.din69_WIDTH( 4 ),
.din70_WIDTH( 4 ),
.din71_WIDTH( 4 ),
.din72_WIDTH( 4 ),
.din73_WIDTH( 4 ),
.din74_WIDTH( 4 ),
.din75_WIDTH( 4 ),
.din76_WIDTH( 4 ),
.din77_WIDTH( 4 ),
.din78_WIDTH( 4 ),
.din79_WIDTH( 4 ),
.din80_WIDTH( 4 ),
.din81_WIDTH( 4 ),
.din82_WIDTH( 4 ),
.din83_WIDTH( 4 ),
.din84_WIDTH( 4 ),
.din85_WIDTH( 4 ),
.din86_WIDTH( 4 ),
.din87_WIDTH( 4 ),
.din88_WIDTH( 4 ),
.din89_WIDTH( 4 ),
.din90_WIDTH( 4 ),
.din91_WIDTH( 4 ),
.din92_WIDTH( 4 ),
.din93_WIDTH( 4 ),
.din94_WIDTH( 4 ),
.din95_WIDTH( 4 ),
.din96_WIDTH( 4 ),
.din97_WIDTH( 4 ),
.din98_WIDTH( 4 ),
.din99_WIDTH( 4 ),
.din100_WIDTH( 4 ),
.din101_WIDTH( 4 ),
.din102_WIDTH( 4 ),
.din103_WIDTH( 4 ),
.din104_WIDTH( 4 ),
.din105_WIDTH( 4 ),
.din106_WIDTH( 4 ),
.din107_WIDTH( 4 ),
.din108_WIDTH( 4 ),
.din109_WIDTH( 4 ),
.din110_WIDTH( 4 ),
.din111_WIDTH( 4 ),
.din112_WIDTH( 4 ),
.din113_WIDTH( 4 ),
.din114_WIDTH( 4 ),
.din115_WIDTH( 4 ),
.din116_WIDTH( 4 ),
.din117_WIDTH( 4 ),
.din118_WIDTH( 4 ),
.din119_WIDTH( 4 ),
.din120_WIDTH( 4 ),
.din121_WIDTH( 4 ),
.din122_WIDTH( 4 ),
.din123_WIDTH( 4 ),
.din124_WIDTH( 4 ),
.din125_WIDTH( 4 ),
.din126_WIDTH( 4 ),
.din127_WIDTH( 4 ),
.din128_WIDTH( 4 ),
.din129_WIDTH( 7 ),
.dout_WIDTH( 4 ))
sp_mux_128to1_sel7_4_1_U5(
.din1(primitive11_0_th_corr_mem_V_read),
.din2(primitive11_1_th_corr_mem_V_read),
.din3(primitive11_2_th_corr_mem_V_read),
.din4(primitive11_3_th_corr_mem_V_read),
.din5(primitive11_4_th_corr_mem_V_read),
.din6(primitive11_5_th_corr_mem_V_read),
.din7(primitive11_6_th_corr_mem_V_read),
.din8(primitive11_7_th_corr_mem_V_read),
.din9(primitive11_8_th_corr_mem_V_read),
.din10(primitive11_9_th_corr_mem_V_read),
.din11(primitive11_10_th_corr_mem_V_read),
.din12(primitive11_11_th_corr_mem_V_read),
.din13(primitive11_12_th_corr_mem_V_read),
.din14(primitive11_13_th_corr_mem_V_read),
.din15(primitive11_14_th_corr_mem_V_read),
.din16(primitive11_15_th_corr_mem_V_read),
.din17(primitive11_16_th_corr_mem_V_read),
.din18(primitive11_17_th_corr_mem_V_read),
.din19(primitive11_18_th_corr_mem_V_read),
.din20(primitive11_19_th_corr_mem_V_read),
.din21(primitive11_20_th_corr_mem_V_read),
.din22(primitive11_21_th_corr_mem_V_read),
.din23(primitive11_22_th_corr_mem_V_read),
.din24(primitive11_23_th_corr_mem_V_read),
.din25(primitive11_24_th_corr_mem_V_read),
.din26(primitive11_25_th_corr_mem_V_read),
.din27(primitive11_26_th_corr_mem_V_read),
.din28(primitive11_27_th_corr_mem_V_read),
.din29(primitive11_28_th_corr_mem_V_read),
.din30(primitive11_29_th_corr_mem_V_read),
.din31(primitive11_30_th_corr_mem_V_read),
.din32(primitive11_31_th_corr_mem_V_read),
.din33(primitive11_32_th_corr_mem_V_read),
.din34(primitive11_33_th_corr_mem_V_read),
.din35(primitive11_34_th_corr_mem_V_read),
.din36(primitive11_35_th_corr_mem_V_read),
.din37(primitive11_36_th_corr_mem_V_read),
.din38(primitive11_37_th_corr_mem_V_read),
.din39(primitive11_38_th_corr_mem_V_read),
.din40(primitive11_39_th_corr_mem_V_read),
.din41(primitive11_40_th_corr_mem_V_read),
.din42(primitive11_41_th_corr_mem_V_read),
.din43(primitive11_42_th_corr_mem_V_read),
.din44(primitive11_43_th_corr_mem_V_read),
.din45(primitive11_44_th_corr_mem_V_read),
.din46(primitive11_45_th_corr_mem_V_read),
.din47(primitive11_46_th_corr_mem_V_read),
.din48(primitive11_47_th_corr_mem_V_read),
.din49(primitive11_48_th_corr_mem_V_read),
.din50(primitive11_49_th_corr_mem_V_read),
.din51(primitive11_50_th_corr_mem_V_read),
.din52(primitive11_51_th_corr_mem_V_read),
.din53(primitive11_52_th_corr_mem_V_read),
.din54(primitive11_53_th_corr_mem_V_read),
.din55(primitive11_54_th_corr_mem_V_read),
.din56(primitive11_55_th_corr_mem_V_read),
.din57(primitive11_56_th_corr_mem_V_read),
.din58(primitive11_57_th_corr_mem_V_read),
.din59(primitive11_58_th_corr_mem_V_read),
.din60(primitive11_59_th_corr_mem_V_read),
.din61(primitive11_60_th_corr_mem_V_read),
.din62(primitive11_61_th_corr_mem_V_read),
.din63(primitive11_62_th_corr_mem_V_read),
.din64(primitive11_63_th_corr_mem_V_read),
.din65(primitive11_64_th_corr_mem_V_read),
.din66(primitive11_65_th_corr_mem_V_read),
.din67(primitive11_66_th_corr_mem_V_read),
.din68(primitive11_67_th_corr_mem_V_read),
.din69(primitive11_68_th_corr_mem_V_read),
.din70(primitive11_69_th_corr_mem_V_read),
.din71(primitive11_70_th_corr_mem_V_read),
.din72(primitive11_71_th_corr_mem_V_read),
.din73(primitive11_72_th_corr_mem_V_read),
.din74(primitive11_73_th_corr_mem_V_read),
.din75(primitive11_74_th_corr_mem_V_read),
.din76(primitive11_75_th_corr_mem_V_read),
.din77(primitive11_76_th_corr_mem_V_read),
.din78(primitive11_77_th_corr_mem_V_read),
.din79(primitive11_78_th_corr_mem_V_read),
.din80(primitive11_79_th_corr_mem_V_read),
.din81(primitive11_80_th_corr_mem_V_read),
.din82(primitive11_81_th_corr_mem_V_read),
.din83(primitive11_82_th_corr_mem_V_read),
.din84(primitive11_83_th_corr_mem_V_read),
.din85(primitive11_84_th_corr_mem_V_read),
.din86(primitive11_85_th_corr_mem_V_read),
.din87(primitive11_86_th_corr_mem_V_read),
.din88(primitive11_87_th_corr_mem_V_read),
.din89(primitive11_88_th_corr_mem_V_read),
.din90(primitive11_89_th_corr_mem_V_read),
.din91(primitive11_90_th_corr_mem_V_read),
.din92(primitive11_91_th_corr_mem_V_read),
.din93(primitive11_92_th_corr_mem_V_read),
.din94(primitive11_93_th_corr_mem_V_read),
.din95(primitive11_94_th_corr_mem_V_read),
.din96(primitive11_95_th_corr_mem_V_read),
.din97(primitive11_96_th_corr_mem_V_read),
.din98(primitive11_97_th_corr_mem_V_read),
.din99(primitive11_98_th_corr_mem_V_read),
.din100(primitive11_99_th_corr_mem_V_read),
.din101(primitive11_100_th_corr_mem_V_read),
.din102(primitive11_101_th_corr_mem_V_read),
.din103(primitive11_102_th_corr_mem_V_read),
.din104(primitive11_103_th_corr_mem_V_read),
.din105(primitive11_104_th_corr_mem_V_read),
.din106(primitive11_105_th_corr_mem_V_read),
.din107(primitive11_106_th_corr_mem_V_read),
.din108(primitive11_107_th_corr_mem_V_read),
.din109(primitive11_108_th_corr_mem_V_read),
.din110(primitive11_109_th_corr_mem_V_read),
.din111(primitive11_110_th_corr_mem_V_read),
.din112(primitive11_111_th_corr_mem_V_read),
.din113(primitive11_112_th_corr_mem_V_read),
.din114(primitive11_113_th_corr_mem_V_read),
.din115(primitive11_114_th_corr_mem_V_read),
.din116(primitive11_115_th_corr_mem_V_read),
.din117(primitive11_116_th_corr_mem_V_read),
.din118(primitive11_117_th_corr_mem_V_read),
.din119(primitive11_118_th_corr_mem_V_read),
.din120(primitive11_119_th_corr_mem_V_read),
.din121(primitive11_120_th_corr_mem_V_read),
.din122(primitive11_121_th_corr_mem_V_read),
.din123(primitive11_122_th_corr_mem_V_read),
.din124(primitive11_123_th_corr_mem_V_read),
.din125(primitive11_124_th_corr_mem_V_read),
.din126(primitive11_125_th_corr_mem_V_read),
.din127(primitive11_126_th_corr_mem_V_read),
.din128(primitive11_127_th_corr_mem_V_read),
.din129(tmp_157_fu_4460_p129),
.dout(tmp_157_fu_4460_p130)
);
sp_mux_128to1_sel7_4_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 4 ),
.din2_WIDTH( 4 ),
.din3_WIDTH( 4 ),
.din4_WIDTH( 4 ),
.din5_WIDTH( 4 ),
.din6_WIDTH( 4 ),
.din7_WIDTH( 4 ),
.din8_WIDTH( 4 ),
.din9_WIDTH( 4 ),
.din10_WIDTH( 4 ),
.din11_WIDTH( 4 ),
.din12_WIDTH( 4 ),
.din13_WIDTH( 4 ),
.din14_WIDTH( 4 ),
.din15_WIDTH( 4 ),
.din16_WIDTH( 4 ),
.din17_WIDTH( 4 ),
.din18_WIDTH( 4 ),
.din19_WIDTH( 4 ),
.din20_WIDTH( 4 ),
.din21_WIDTH( 4 ),
.din22_WIDTH( 4 ),
.din23_WIDTH( 4 ),
.din24_WIDTH( 4 ),
.din25_WIDTH( 4 ),
.din26_WIDTH( 4 ),
.din27_WIDTH( 4 ),
.din28_WIDTH( 4 ),
.din29_WIDTH( 4 ),
.din30_WIDTH( 4 ),
.din31_WIDTH( 4 ),
.din32_WIDTH( 4 ),
.din33_WIDTH( 4 ),
.din34_WIDTH( 4 ),
.din35_WIDTH( 4 ),
.din36_WIDTH( 4 ),
.din37_WIDTH( 4 ),
.din38_WIDTH( 4 ),
.din39_WIDTH( 4 ),
.din40_WIDTH( 4 ),
.din41_WIDTH( 4 ),
.din42_WIDTH( 4 ),
.din43_WIDTH( 4 ),
.din44_WIDTH( 4 ),
.din45_WIDTH( 4 ),
.din46_WIDTH( 4 ),
.din47_WIDTH( 4 ),
.din48_WIDTH( 4 ),
.din49_WIDTH( 4 ),
.din50_WIDTH( 4 ),
.din51_WIDTH( 4 ),
.din52_WIDTH( 4 ),
.din53_WIDTH( 4 ),
.din54_WIDTH( 4 ),
.din55_WIDTH( 4 ),
.din56_WIDTH( 4 ),
.din57_WIDTH( 4 ),
.din58_WIDTH( 4 ),
.din59_WIDTH( 4 ),
.din60_WIDTH( 4 ),
.din61_WIDTH( 4 ),
.din62_WIDTH( 4 ),
.din63_WIDTH( 4 ),
.din64_WIDTH( 4 ),
.din65_WIDTH( 4 ),
.din66_WIDTH( 4 ),
.din67_WIDTH( 4 ),
.din68_WIDTH( 4 ),
.din69_WIDTH( 4 ),
.din70_WIDTH( 4 ),
.din71_WIDTH( 4 ),
.din72_WIDTH( 4 ),
.din73_WIDTH( 4 ),
.din74_WIDTH( 4 ),
.din75_WIDTH( 4 ),
.din76_WIDTH( 4 ),
.din77_WIDTH( 4 ),
.din78_WIDTH( 4 ),
.din79_WIDTH( 4 ),
.din80_WIDTH( 4 ),
.din81_WIDTH( 4 ),
.din82_WIDTH( 4 ),
.din83_WIDTH( 4 ),
.din84_WIDTH( 4 ),
.din85_WIDTH( 4 ),
.din86_WIDTH( 4 ),
.din87_WIDTH( 4 ),
.din88_WIDTH( 4 ),
.din89_WIDTH( 4 ),
.din90_WIDTH( 4 ),
.din91_WIDTH( 4 ),
.din92_WIDTH( 4 ),
.din93_WIDTH( 4 ),
.din94_WIDTH( 4 ),
.din95_WIDTH( 4 ),
.din96_WIDTH( 4 ),
.din97_WIDTH( 4 ),
.din98_WIDTH( 4 ),
.din99_WIDTH( 4 ),
.din100_WIDTH( 4 ),
.din101_WIDTH( 4 ),
.din102_WIDTH( 4 ),
.din103_WIDTH( 4 ),
.din104_WIDTH( 4 ),
.din105_WIDTH( 4 ),
.din106_WIDTH( 4 ),
.din107_WIDTH( 4 ),
.din108_WIDTH( 4 ),
.din109_WIDTH( 4 ),
.din110_WIDTH( 4 ),
.din111_WIDTH( 4 ),
.din112_WIDTH( 4 ),
.din113_WIDTH( 4 ),
.din114_WIDTH( 4 ),
.din115_WIDTH( 4 ),
.din116_WIDTH( 4 ),
.din117_WIDTH( 4 ),
.din118_WIDTH( 4 ),
.din119_WIDTH( 4 ),
.din120_WIDTH( 4 ),
.din121_WIDTH( 4 ),
.din122_WIDTH( 4 ),
.din123_WIDTH( 4 ),
.din124_WIDTH( 4 ),
.din125_WIDTH( 4 ),
.din126_WIDTH( 4 ),
.din127_WIDTH( 4 ),
.din128_WIDTH( 4 ),
.din129_WIDTH( 7 ),
.dout_WIDTH( 4 ))
sp_mux_128to1_sel7_4_1_U6(
.din1(primitive11_0_th_corr_mem_V_read),
.din2(primitive11_1_th_corr_mem_V_read),
.din3(primitive11_2_th_corr_mem_V_read),
.din4(primitive11_3_th_corr_mem_V_read),
.din5(primitive11_4_th_corr_mem_V_read),
.din6(primitive11_5_th_corr_mem_V_read),
.din7(primitive11_6_th_corr_mem_V_read),
.din8(primitive11_7_th_corr_mem_V_read),
.din9(primitive11_8_th_corr_mem_V_read),
.din10(primitive11_9_th_corr_mem_V_read),
.din11(primitive11_10_th_corr_mem_V_read),
.din12(primitive11_11_th_corr_mem_V_read),
.din13(primitive11_12_th_corr_mem_V_read),
.din14(primitive11_13_th_corr_mem_V_read),
.din15(primitive11_14_th_corr_mem_V_read),
.din16(primitive11_15_th_corr_mem_V_read),
.din17(primitive11_16_th_corr_mem_V_read),
.din18(primitive11_17_th_corr_mem_V_read),
.din19(primitive11_18_th_corr_mem_V_read),
.din20(primitive11_19_th_corr_mem_V_read),
.din21(primitive11_20_th_corr_mem_V_read),
.din22(primitive11_21_th_corr_mem_V_read),
.din23(primitive11_22_th_corr_mem_V_read),
.din24(primitive11_23_th_corr_mem_V_read),
.din25(primitive11_24_th_corr_mem_V_read),
.din26(primitive11_25_th_corr_mem_V_read),
.din27(primitive11_26_th_corr_mem_V_read),
.din28(primitive11_27_th_corr_mem_V_read),
.din29(primitive11_28_th_corr_mem_V_read),
.din30(primitive11_29_th_corr_mem_V_read),
.din31(primitive11_30_th_corr_mem_V_read),
.din32(primitive11_31_th_corr_mem_V_read),
.din33(primitive11_32_th_corr_mem_V_read),
.din34(primitive11_33_th_corr_mem_V_read),
.din35(primitive11_34_th_corr_mem_V_read),
.din36(primitive11_35_th_corr_mem_V_read),
.din37(primitive11_36_th_corr_mem_V_read),
.din38(primitive11_37_th_corr_mem_V_read),
.din39(primitive11_38_th_corr_mem_V_read),
.din40(primitive11_39_th_corr_mem_V_read),
.din41(primitive11_40_th_corr_mem_V_read),
.din42(primitive11_41_th_corr_mem_V_read),
.din43(primitive11_42_th_corr_mem_V_read),
.din44(primitive11_43_th_corr_mem_V_read),
.din45(primitive11_44_th_corr_mem_V_read),
.din46(primitive11_45_th_corr_mem_V_read),
.din47(primitive11_46_th_corr_mem_V_read),
.din48(primitive11_47_th_corr_mem_V_read),
.din49(primitive11_48_th_corr_mem_V_read),
.din50(primitive11_49_th_corr_mem_V_read),
.din51(primitive11_50_th_corr_mem_V_read),
.din52(primitive11_51_th_corr_mem_V_read),
.din53(primitive11_52_th_corr_mem_V_read),
.din54(primitive11_53_th_corr_mem_V_read),
.din55(primitive11_54_th_corr_mem_V_read),
.din56(primitive11_55_th_corr_mem_V_read),
.din57(primitive11_56_th_corr_mem_V_read),
.din58(primitive11_57_th_corr_mem_V_read),
.din59(primitive11_58_th_corr_mem_V_read),
.din60(primitive11_59_th_corr_mem_V_read),
.din61(primitive11_60_th_corr_mem_V_read),
.din62(primitive11_61_th_corr_mem_V_read),
.din63(primitive11_62_th_corr_mem_V_read),
.din64(primitive11_63_th_corr_mem_V_read),
.din65(primitive11_64_th_corr_mem_V_read),
.din66(primitive11_65_th_corr_mem_V_read),
.din67(primitive11_66_th_corr_mem_V_read),
.din68(primitive11_67_th_corr_mem_V_read),
.din69(primitive11_68_th_corr_mem_V_read),
.din70(primitive11_69_th_corr_mem_V_read),
.din71(primitive11_70_th_corr_mem_V_read),
.din72(primitive11_71_th_corr_mem_V_read),
.din73(primitive11_72_th_corr_mem_V_read),
.din74(primitive11_73_th_corr_mem_V_read),
.din75(primitive11_74_th_corr_mem_V_read),
.din76(primitive11_75_th_corr_mem_V_read),
.din77(primitive11_76_th_corr_mem_V_read),
.din78(primitive11_77_th_corr_mem_V_read),
.din79(primitive11_78_th_corr_mem_V_read),
.din80(primitive11_79_th_corr_mem_V_read),
.din81(primitive11_80_th_corr_mem_V_read),
.din82(primitive11_81_th_corr_mem_V_read),
.din83(primitive11_82_th_corr_mem_V_read),
.din84(primitive11_83_th_corr_mem_V_read),
.din85(primitive11_84_th_corr_mem_V_read),
.din86(primitive11_85_th_corr_mem_V_read),
.din87(primitive11_86_th_corr_mem_V_read),
.din88(primitive11_87_th_corr_mem_V_read),
.din89(primitive11_88_th_corr_mem_V_read),
.din90(primitive11_89_th_corr_mem_V_read),
.din91(primitive11_90_th_corr_mem_V_read),
.din92(primitive11_91_th_corr_mem_V_read),
.din93(primitive11_92_th_corr_mem_V_read),
.din94(primitive11_93_th_corr_mem_V_read),
.din95(primitive11_94_th_corr_mem_V_read),
.din96(primitive11_95_th_corr_mem_V_read),
.din97(primitive11_96_th_corr_mem_V_read),
.din98(primitive11_97_th_corr_mem_V_read),
.din99(primitive11_98_th_corr_mem_V_read),
.din100(primitive11_99_th_corr_mem_V_read),
.din101(primitive11_100_th_corr_mem_V_read),
.din102(primitive11_101_th_corr_mem_V_read),
.din103(primitive11_102_th_corr_mem_V_read),
.din104(primitive11_103_th_corr_mem_V_read),
.din105(primitive11_104_th_corr_mem_V_read),
.din106(primitive11_105_th_corr_mem_V_read),
.din107(primitive11_106_th_corr_mem_V_read),
.din108(primitive11_107_th_corr_mem_V_read),
.din109(primitive11_108_th_corr_mem_V_read),
.din110(primitive11_109_th_corr_mem_V_read),
.din111(primitive11_110_th_corr_mem_V_read),
.din112(primitive11_111_th_corr_mem_V_read),
.din113(primitive11_112_th_corr_mem_V_read),
.din114(primitive11_113_th_corr_mem_V_read),
.din115(primitive11_114_th_corr_mem_V_read),
.din116(primitive11_115_th_corr_mem_V_read),
.din117(primitive11_116_th_corr_mem_V_read),
.din118(primitive11_117_th_corr_mem_V_read),
.din119(primitive11_118_th_corr_mem_V_read),
.din120(primitive11_119_th_corr_mem_V_read),
.din121(primitive11_120_th_corr_mem_V_read),
.din122(primitive11_121_th_corr_mem_V_read),
.din123(primitive11_122_th_corr_mem_V_read),
.din124(primitive11_123_th_corr_mem_V_read),
.din125(primitive11_124_th_corr_mem_V_read),
.din126(primitive11_125_th_corr_mem_V_read),
.din127(primitive11_126_th_corr_mem_V_read),
.din128(primitive11_127_th_corr_mem_V_read),
.din129(tmp_164_fu_4886_p129),
.dout(tmp_164_fu_4886_p130)
);
sp_mul_mul_12ns_12s_23_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 12 ),
.din1_WIDTH( 12 ),
.dout_WIDTH( 23 ))
sp_mul_mul_12ns_12s_23_1_U7(
.din0(r_V_s_fu_5408_p0),
.din1(r_V_s_fu_5408_p1),
.dout(r_V_s_fu_5408_p2)
);
sp_mul_mul_12ns_12s_23_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 12 ),
.din1_WIDTH( 12 ),
.dout_WIDTH( 23 ))
sp_mul_mul_12ns_12s_23_1_U8(
.din0(r_V_147_1_fu_5416_p0),
.din1(r_V_147_1_fu_5416_p1),
.dout(r_V_147_1_fu_5416_p2)
);
assign ap_return_0 = p_01099_7_1_fu_5340_p3;
assign ap_return_1 = p_01111_2_1_fu_5364_p3;
assign ap_return_2 = ph_0_V_write_assign_fu_3778_p3;
assign ap_return_3 = ph_1_V_write_assign_fu_5316_p3;
assign ap_return_4 = clctpat_r_0_V_write_assign_fu_3746_p3;
assign ap_return_5 = clctpat_r_1_V_write_assign_fu_5292_p3;
assign clctpat_r_0_V_write_assign_fu_3746_p3 = ((sel_tmp58_fu_3740_p2[0:0] === 1'b1) ? clctpat_0_V_read : sel_tmp53_fu_3720_p3);
assign clctpat_r_1_V_write_assign_fu_5292_p3 = ((sel_tmp160_fu_5286_p2[0:0] === 1'b1) ? clctpat_1_V_read : sel_tmp158_fu_5266_p3);
assign fph_V_load_4_fu_4150_p3 = ((endcap_V[0:0] === 1'b1) ? tmp_678_1_fu_4083_p2 : tmp_684_1_fu_4130_p2);
assign fph_V_load_s_fu_2604_p3 = ((endcap_V[0:0] === 1'b1) ? tmp_171_fu_2517_p2 : tmp_176_fu_2584_p2);
assign i_assign_1_fu_4124_p2 = ($signed(tmp_682_1_cast_fu_4120_p1) + $signed(tmp_680_1_cast_fu_4108_p1));
assign i_assign_3_1_cast_fu_4146_p1 = r_V_143_1_fu_4140_p2;
assign i_assign_3_cast_fu_2600_p1 = r_V_1_fu_2594_p2;
assign i_assign_fu_2578_p2 = ($signed(tmp_610_cast_fu_2574_p1) + $signed(tmp_606_cast_fu_2542_p1));
assign not_sel_tmp7_fu_2400_p2 = ((clctpat_0_V_read != ap_const_lv4_3) ? 1'b1 : 1'b0);
assign not_sel_tmp8_fu_3954_p2 = ((clctpat_1_V_read != ap_const_lv4_5) ? 1'b1 : 1'b0);
assign not_sel_tmp9_fu_3972_p2 = ((clctpat_1_V_read != ap_const_lv4_3) ? 1'b1 : 1'b0);
assign not_sel_tmp_fu_2382_p2 = ((clctpat_0_V_read != ap_const_lv4_5) ? 1'b1 : 1'b0);
assign or_cond10_fu_3924_p2 = (sel_tmp112_fu_3864_p2 | sel_tmp110_fu_3858_p2);
assign or_cond11_fu_3930_p2 = (or_cond3_fu_3906_p2 | or_cond4_fu_3912_p2);
assign or_cond12_fu_3936_p2 = (or_cond5_fu_3918_p2 | or_cond10_fu_3924_p2);
assign or_cond13_fu_3942_p2 = (or_cond11_fu_3930_p2 | or_cond12_fu_3936_p2);
assign or_cond1_fu_2364_p2 = (or_cond7_fu_2346_p2 | or_cond8_fu_2352_p2);
assign or_cond2_fu_2370_p2 = (or_cond9_fu_2358_p2 | or_cond1_fu_2364_p2);
assign or_cond3_fu_3906_p2 = (sel_tmp124_fu_3900_p2 | sel_tmp122_fu_3894_p2);
assign or_cond4_fu_3912_p2 = (sel_tmp120_fu_3888_p2 | sel_tmp118_fu_3882_p2);
assign or_cond5_fu_3918_p2 = (sel_tmp116_fu_3876_p2 | sel_tmp114_fu_3870_p2);
assign or_cond6_fu_2340_p2 = (sel_tmp10_fu_2316_p2 | sel_tmp8_fu_2310_p2);
assign or_cond7_fu_2346_p2 = (sel_tmp6_fu_2304_p2 | sel_tmp4_fu_2298_p2);
assign or_cond8_fu_2352_p2 = (sel_tmp2_fu_2292_p2 | sel_tmp_fu_2286_p2);
assign or_cond9_fu_2358_p2 = (or_cond_fu_2334_p2 | or_cond6_fu_2340_p2);
assign or_cond_fu_2334_p2 = (sel_tmp14_fu_2328_p2 | sel_tmp12_fu_2322_p2);
assign p_01099_6_1_fu_4860_p3 = ((tmp_170_fu_2482_p2[0:0] === 1'b1) ? p_01099_7_fu_3810_p3 : sel_tmp155_fu_4852_p3);
assign p_01099_6_fu_3292_p3 = ((tmp_178_fu_3214_p2[0:0] === 1'b1) ? sel_tmp38_fu_3284_p3 : ap_const_lv3_0);
assign p_01099_7_1_fu_5340_p3 = ((sel_tmp160_fu_5286_p2[0:0] === 1'b1) ? tmp_517_fu_5242_p4 : sel_tmp164_fu_5332_p3);
assign p_01099_7_fu_3810_p3 = ((sel_tmp58_fu_3740_p2[0:0] === 1'b1) ? tmp_509_fu_3670_p4 : sel_tmp85_fu_3802_p3);
assign p_01111_2_1_fu_5364_p3 = ((sel_tmp160_fu_5286_p2[0:0] === 1'b1) ? tmp_511_fu_4170_p4 : sel_tmp166_fu_5356_p3);
assign p_01111_2_fu_3842_p3 = ((sel_tmp58_fu_3740_p2[0:0] === 1'b1) ? tmp_504_fu_2624_p4 : sel_tmp101_fu_3834_p3);
assign p_1_73_fu_4008_p2 = (p_Result_786_1_fu_3990_p4 - tmp_669_1_cast_cast_fu_4000_p3);
assign p_1_fu_2412_p2 = (sel_tmp14_fu_2328_p2 | sel_tmp29_fu_2406_p2);
assign p_21_1_fu_3984_p2 = (sel_tmp124_fu_3900_p2 | sel_tmp139_fu_3978_p2);
assign p_Result_138_fu_2523_p4 = {{r_V_s_fu_5408_p2[ap_const_lv32_15 : ap_const_lv32_F]}};
assign p_Result_139_fu_2896_p4 = {{p_Val2_s_fu_2474_p3[ap_const_lv32_8 : ap_const_lv32_4]}};
assign p_Result_140_fu_2906_p4 = {{wiregroup_0_V_read[ap_const_lv32_5 : ap_const_lv32_4]}};
assign p_Result_141_fu_3246_p3 = {{ap_const_lv2_2}, {tmp_180_fu_3230_p2}};
assign p_Result_786_1_fu_3990_p4 = {{{{ap_const_lv2_0}, {hstrip_1_V_read}}}, {ap_const_lv2_0}};
assign p_Result_790_1_fu_4089_p4 = {{r_V_147_1_fu_5416_p2[ap_const_lv32_15 : ap_const_lv32_F]}};
assign p_Result_796_1_1_fu_4868_p4 = {{p_Val2_255_1_1_fu_4046_p3[ap_const_lv32_8 : ap_const_lv32_4]}};
assign p_Result_798_1_fu_4442_p4 = {{wiregroup_1_V_read[ap_const_lv32_5 : ap_const_lv32_4]}};
assign p_Result_s_fu_2418_p4 = {{{{ap_const_lv2_0}, {hstrip_0_V_read}}}, {ap_const_lv2_0}};
assign p_Val2_1_fu_3236_p1 = tmp_180_fu_3230_p2;
assign p_Val2_255_1_1_fu_4046_p3 = ((p_21_1_fu_3984_p2[0:0] === 1'b1) ? tmp_671_1_fu_4034_p2 : tmp_673_1_fu_4040_p2);
assign p_Val2_259_0_1_fu_3632_p3 = ((tmp_698_0_1_fu_3616_p2[0:0] === 1'b1) ? tmp_507_fu_3622_p4 : p_01099_6_fu_3292_p3);
assign p_Val2_259_1_1_fu_5204_p3 = ((tmp_698_1_1_fu_5188_p2[0:0] === 1'b1) ? tmp_515_fu_5194_p4 : p_01099_6_1_fu_4860_p3);
assign p_Val2_259_1_fu_4778_p3 = ((tmp_698_1_fu_4762_p2[0:0] === 1'b1) ? tmp_512_fu_4768_p4 : p_01099_7_fu_3810_p3);
assign p_Val2_260_0_1_fu_3656_p3 = ((tmp_701_0_1_fu_3640_p2[0:0] === 1'b1) ? tmp_508_fu_3646_p4 : p_Val2_259_0_1_fu_3632_p3);
assign p_Val2_260_1_1_fu_5228_p3 = ((tmp_701_1_1_fu_5212_p2[0:0] === 1'b1) ? tmp_516_fu_5218_p4 : p_Val2_259_1_1_fu_5204_p3);
assign p_Val2_260_1_fu_4802_p3 = ((tmp_701_1_fu_4786_p2[0:0] === 1'b1) ? tmp_513_fu_4792_p4 : p_Val2_259_1_fu_4778_p3);
assign p_Val2_2_fu_3254_p3 = ((tmp_181_fu_3240_p2[0:0] === 1'b1) ? p_Result_141_fu_3246_p3 : p_Val2_1_fu_3236_p1);
assign p_Val2_s_fu_2474_p3 = ((p_1_fu_2412_p2[0:0] === 1'b1) ? tmp_163_fu_2462_p2 : tmp_166_fu_2468_p2);
assign p_s_fu_2436_p2 = (p_Result_s_fu_2418_p4 - tmp_597_cast_cast_fu_2428_p3);
assign ph_0_V_write_assign_fu_3778_p3 = ((sel_tmp58_fu_3740_p2[0:0] === 1'b1) ? fph_V_load_s_fu_2604_p3 : sel_tmp69_fu_3770_p3);
assign ph_1_V_write_assign_fu_5316_p3 = ((sel_tmp160_fu_5286_p2[0:0] === 1'b1) ? fph_V_load_4_fu_4150_p3 : sel_tmp162_fu_5308_p3);
assign ph_tmp_V_1_fu_4066_p4 = {{r_V_147_1_fu_5416_p2[ap_const_lv32_15 : ap_const_lv32_A]}};
assign ph_tmp_V_fu_2500_p4 = {{r_V_s_fu_5408_p2[ap_const_lv32_15 : ap_const_lv32_A]}};
assign primitive11_2_params_V_read_a_1_fu_4075_p3 = ((tmp_510_fu_3850_p3[0:0] === 1'b1) ? primitive11_2_params_V_read : primitive11_0_params_V_read);
assign primitive11_2_params_V_read_a_fu_2509_p3 = ((tmp_503_fu_2278_p3[0:0] === 1'b1) ? primitive11_2_params_V_read : primitive11_0_params_V_read);
assign r_V_143_1_fu_4140_p2 = (tmp_679_1_cast_fu_4098_p1 + rhs_V_166_1_cast_fu_4136_p1);
assign r_V_147_1_fu_5416_p0 = r_V_147_1_fu_5416_p00;
assign r_V_147_1_fu_5416_p00 = p_Val2_255_1_1_fu_4046_p3;
assign r_V_147_1_fu_5416_p1 = r_V_147_1_fu_5416_p10;
assign r_V_147_1_fu_5416_p10 = ((tmp_510_fu_3850_p3[0:0] === 1'b1) ? ap_const_lv23_6AB : ap_const_lv23_515);
assign r_V_1_fu_2594_p2 = (tmp_605_cast_fu_2532_p1 + rhs_V_cast_fu_2590_p1);
assign r_V_s_fu_5408_p0 = r_V_s_fu_5408_p00;
assign r_V_s_fu_5408_p00 = p_Val2_s_fu_2474_p3;
assign r_V_s_fu_5408_p1 = r_V_s_fu_5408_p10;
assign r_V_s_fu_5408_p10 = ((tmp_503_fu_2278_p3[0:0] === 1'b1) ? ap_const_lv23_6AB : ap_const_lv23_515);
assign rhs_V_166_1_cast_fu_4136_p1 = tmp_184_fu_4112_p3;
assign rhs_V_cast_fu_2590_p1 = tmp_175_fu_2566_p3;
assign sel_tmp101_fu_3834_p3 = ((sel_tmp52_demorgan_fu_3714_p2[0:0] === 1'b1) ? sel_tmp95_fu_3826_p3 : tmp_504_fu_2624_p4);
assign sel_tmp10_fu_2316_p2 = ((clctpat_0_V_read == ap_const_lv4_4) ? 1'b1 : 1'b0);
assign sel_tmp110_fu_3858_p2 = ((clctpat_1_V_read == ap_const_lv4_9) ? 1'b1 : 1'b0);
assign sel_tmp112_fu_3864_p2 = ((clctpat_1_V_read == ap_const_lv4_8) ? 1'b1 : 1'b0);
assign sel_tmp114_fu_3870_p2 = ((clctpat_1_V_read == ap_const_lv4_7) ? 1'b1 : 1'b0);
assign sel_tmp116_fu_3876_p2 = ((clctpat_1_V_read == ap_const_lv4_6) ? 1'b1 : 1'b0);
assign sel_tmp118_fu_3882_p2 = ((clctpat_1_V_read == ap_const_lv4_5) ? 1'b1 : 1'b0);
assign sel_tmp120_fu_3888_p2 = ((clctpat_1_V_read == ap_const_lv4_4) ? 1'b1 : 1'b0);
assign sel_tmp122_fu_3894_p2 = ((clctpat_1_V_read == ap_const_lv4_3) ? 1'b1 : 1'b0);
assign sel_tmp124_fu_3900_p2 = ((clctpat_1_V_read == ap_const_lv4_2) ? 1'b1 : 1'b0);
assign sel_tmp12_fu_2322_p2 = ((clctpat_0_V_read == ap_const_lv4_3) ? 1'b1 : 1'b0);
assign sel_tmp133_fu_3948_p2 = (sel_tmp116_fu_3876_p2 | sel_tmp112_fu_3864_p2);
assign sel_tmp135_fu_3960_p2 = (sel_tmp133_fu_3948_p2 & not_sel_tmp8_fu_3954_p2);
assign sel_tmp137_fu_3966_p2 = (sel_tmp120_fu_3888_p2 | sel_tmp135_fu_3960_p2);
assign sel_tmp139_fu_3978_p2 = (sel_tmp137_fu_3966_p2 & not_sel_tmp9_fu_3972_p2);
assign sel_tmp14_fu_2328_p2 = ((clctpat_0_V_read == ap_const_lv4_2) ? 1'b1 : 1'b0);
assign sel_tmp150_fu_4832_p2 = (tmp27_fu_4826_p2 & tmp_693_1_fu_4750_p2);
assign sel_tmp151_fu_4838_p3 = ((sel_tmp150_fu_4832_p2[0:0] === 1'b1) ? tmp_514_fu_4816_p4 : p_Val2_260_1_fu_4802_p3);
assign sel_tmp154_demorgan_fu_4846_p2 = (tmp_170_fu_2482_p2 | tmp_693_1_fu_4750_p2);
assign sel_tmp155_fu_4852_p3 = ((sel_tmp154_demorgan_fu_4846_p2[0:0] === 1'b1) ? sel_tmp151_fu_4838_p3 : p_01099_7_fu_3810_p3);
assign sel_tmp157_fu_5252_p3 = ((tmp_689_0_1_fu_3300_p2[0:0] === 1'b1) ? ap_const_lv4_0 : clctpat_1_V_read);
assign sel_tmp158_fu_5266_p3 = ((sel_tmp163_demorgan_fu_5260_p2[0:0] === 1'b1) ? sel_tmp157_fu_5252_p3 : clctpat_1_V_read);
assign sel_tmp159_fu_5274_p2 = (tmp_689_0_1_fu_3300_p2 ^ 1'b1);
assign sel_tmp160_fu_5286_p2 = (tmp28_fu_5280_p2 & tmp_693_1_1_fu_5176_p2);
assign sel_tmp161_fu_5300_p3 = ((tmp_689_0_1_fu_3300_p2[0:0] === 1'b1) ? ap_const_lv12_0 : fph_V_load_4_fu_4150_p3);
assign sel_tmp162_fu_5308_p3 = ((sel_tmp163_demorgan_fu_5260_p2[0:0] === 1'b1) ? sel_tmp161_fu_5300_p3 : fph_V_load_4_fu_4150_p3);
assign sel_tmp163_demorgan_fu_5260_p2 = (tmp_689_0_1_fu_3300_p2 | tmp_693_1_1_fu_5176_p2);
assign sel_tmp163_fu_5324_p3 = ((tmp_689_0_1_fu_3300_p2[0:0] === 1'b1) ? p_01099_7_fu_3810_p3 : p_Val2_260_1_1_fu_5228_p3);
assign sel_tmp164_fu_5332_p3 = ((sel_tmp163_demorgan_fu_5260_p2[0:0] === 1'b1) ? sel_tmp163_fu_5324_p3 : p_01099_6_1_fu_4860_p3);
assign sel_tmp165_fu_5348_p3 = ((tmp_689_0_1_fu_3300_p2[0:0] === 1'b1) ? p_01111_2_fu_3842_p3 : tmp_511_fu_4170_p4);
assign sel_tmp166_fu_5356_p3 = ((sel_tmp163_demorgan_fu_5260_p2[0:0] === 1'b1) ? sel_tmp165_fu_5348_p3 : tmp_511_fu_4170_p4);
assign sel_tmp23_fu_2376_p2 = (sel_tmp6_fu_2304_p2 | sel_tmp2_fu_2292_p2);
assign sel_tmp25_fu_2388_p2 = (sel_tmp23_fu_2376_p2 & not_sel_tmp_fu_2382_p2);
assign sel_tmp27_fu_2394_p2 = (sel_tmp10_fu_2316_p2 | sel_tmp25_fu_2388_p2);
assign sel_tmp29_fu_2406_p2 = (sel_tmp27_fu_2394_p2 & not_sel_tmp7_fu_2400_p2);
assign sel_tmp2_fu_2292_p2 = ((clctpat_0_V_read == ap_const_lv4_8) ? 1'b1 : 1'b0);
assign sel_tmp37_fu_3278_p2 = (tmp_178_fu_3214_p2 & tmp_182_fu_3262_p2);
assign sel_tmp38_fu_3284_p3 = ((sel_tmp37_fu_3278_p2[0:0] === 1'b1) ? tmp_506_fu_3268_p4 : p_Val2_2_fu_3254_p3);
assign sel_tmp44_fu_3680_p3 = ((tmp_170_fu_2482_p2[0:0] === 1'b1) ? ap_const_lv4_0 : clctpat_0_V_read);
assign sel_tmp45_fu_3688_p2 = (tmp_170_fu_2482_p2 ^ 1'b1);
assign sel_tmp46_fu_3694_p2 = (tmp_689_0_1_fu_3300_p2 & sel_tmp45_fu_3688_p2);
assign sel_tmp47_fu_3700_p3 = ((sel_tmp46_fu_3694_p2[0:0] === 1'b1) ? clctpat_0_V_read : sel_tmp44_fu_3680_p3);
assign sel_tmp4_fu_2298_p2 = ((clctpat_0_V_read == ap_const_lv4_7) ? 1'b1 : 1'b0);
assign sel_tmp50_demorgan_fu_3708_p2 = (tmp_170_fu_2482_p2 | tmp_689_0_1_fu_3300_p2);
assign sel_tmp52_demorgan_fu_3714_p2 = (sel_tmp50_demorgan_fu_3708_p2 | tmp_693_0_1_fu_3604_p2);
assign sel_tmp53_fu_3720_p3 = ((sel_tmp52_demorgan_fu_3714_p2[0:0] === 1'b1) ? sel_tmp47_fu_3700_p3 : clctpat_0_V_read);
assign sel_tmp56_fu_3728_p2 = (sel_tmp50_demorgan_fu_3708_p2 ^ 1'b1);
assign sel_tmp58_fu_3740_p2 = (tmp_fu_3734_p2 & tmp_693_0_1_fu_3604_p2);
assign sel_tmp60_fu_3754_p3 = ((tmp_170_fu_2482_p2[0:0] === 1'b1) ? ap_const_lv12_0 : fph_V_load_s_fu_2604_p3);
assign sel_tmp63_fu_3762_p3 = ((sel_tmp46_fu_3694_p2[0:0] === 1'b1) ? fph_V_load_s_fu_2604_p3 : sel_tmp60_fu_3754_p3);
assign sel_tmp69_fu_3770_p3 = ((sel_tmp52_demorgan_fu_3714_p2[0:0] === 1'b1) ? sel_tmp63_fu_3762_p3 : fph_V_load_s_fu_2604_p3);
assign sel_tmp6_fu_2304_p2 = ((clctpat_0_V_read == ap_const_lv4_6) ? 1'b1 : 1'b0);
assign sel_tmp76_fu_3786_p3 = ((tmp_170_fu_2482_p2[0:0] === 1'b1) ? ap_const_lv3_0 : p_Val2_260_0_1_fu_3656_p3);
assign sel_tmp79_fu_3794_p3 = ((sel_tmp46_fu_3694_p2[0:0] === 1'b1) ? p_01099_6_fu_3292_p3 : sel_tmp76_fu_3786_p3);
assign sel_tmp85_fu_3802_p3 = ((sel_tmp52_demorgan_fu_3714_p2[0:0] === 1'b1) ? sel_tmp79_fu_3794_p3 : p_01099_6_fu_3292_p3);
assign sel_tmp8_fu_2310_p2 = ((clctpat_0_V_read == ap_const_lv4_5) ? 1'b1 : 1'b0);
assign sel_tmp92_fu_3818_p3 = ((tmp_170_fu_2482_p2[0:0] === 1'b1) ? ap_const_lv44_0 : tmp_504_fu_2624_p4);
assign sel_tmp95_fu_3826_p3 = ((sel_tmp46_fu_3694_p2[0:0] === 1'b1) ? tmp_504_fu_2624_p4 : sel_tmp92_fu_3818_p3);
assign sel_tmp_fu_2286_p2 = ((clctpat_0_V_read == ap_const_lv4_9) ? 1'b1 : 1'b0);
assign th_tmp_V_0_1_cast_fu_3600_p1 = tmp_151_fu_3592_p3;
assign th_tmp_V_1_1_cast_fu_5172_p1 = tmp_169_fu_5164_p3;
assign th_tmp_V_1_cast_fu_4746_p1 = tmp_162_fu_4738_p3;
assign th_tmp_V_cast_fu_3210_p1 = tmp_145_fu_3202_p3;
assign tmp27_fu_4826_p2 = (tmp_702_1_fu_4810_p2 & sel_tmp45_fu_3688_p2);
assign tmp28_fu_5280_p2 = (tmp_702_1_1_fu_5236_p2 & sel_tmp159_fu_5274_p2);
assign tmp_136_fu_2450_p3 = ((or_cond2_fu_2370_p2[0:0] === 1'b1) ? tmp_25_fu_2442_p3 : ap_const_lv2_0);
assign tmp_137_cast_fu_2620_p1 = $signed(tmp_137_fu_2612_p3);
assign tmp_137_fu_2612_p3 = ((endcap_V[0:0] === 1'b1) ? i_assign_fu_2578_p2 : i_assign_3_cast_fu_2600_p1);
assign tmp_140_fu_2924_p129 = {{p_Result_140_fu_2906_p4}, {p_Result_139_fu_2896_p4}};
assign tmp_141_fu_3186_p1 = tmp_140_fu_2924_p130;
assign tmp_143_fu_3190_p2 = (tmp_139_fu_2634_p130 - tmp_141_fu_3186_p1);
assign tmp_144_fu_3196_p2 = (tmp_141_fu_3186_p1 + tmp_139_fu_2634_p130);
assign tmp_145_fu_3202_p3 = ((endcap_V[0:0] === 1'b1) ? tmp_143_fu_3190_p2 : tmp_144_fu_3196_p2);
assign tmp_146_fu_3314_p129 = {{p_Result_140_fu_2906_p4}, {ap_const_lv5_0}};
assign tmp_147_fu_3576_p1 = tmp_146_fu_3314_p130;
assign tmp_149_fu_3580_p2 = (tmp_139_fu_2634_p130 - tmp_147_fu_3576_p1);
assign tmp_150_fu_3586_p2 = (tmp_147_fu_3576_p1 + tmp_139_fu_2634_p130);
assign tmp_151_fu_3592_p3 = ((endcap_V[0:0] === 1'b1) ? tmp_149_fu_3580_p2 : tmp_150_fu_3586_p2);
assign tmp_153_fu_4022_p3 = ((or_cond13_fu_3942_p2[0:0] === 1'b1) ? tmp_26_fu_4014_p3 : ap_const_lv2_0);
assign tmp_154_cast_fu_4166_p1 = $signed(tmp_154_fu_4158_p3);
assign tmp_154_fu_4158_p3 = ((endcap_V[0:0] === 1'b1) ? i_assign_1_fu_4124_p2 : i_assign_3_1_cast_fu_4146_p1);
assign tmp_157_fu_4460_p129 = {{p_Result_798_1_fu_4442_p4}, {p_Result_139_fu_2896_p4}};
assign tmp_158_fu_4722_p1 = tmp_157_fu_4460_p130;
assign tmp_160_fu_4726_p2 = (tmp_156_fu_4180_p130 - tmp_158_fu_4722_p1);
assign tmp_161_fu_4732_p2 = (tmp_158_fu_4722_p1 + tmp_156_fu_4180_p130);
assign tmp_162_fu_4738_p3 = ((endcap_V[0:0] === 1'b1) ? tmp_160_fu_4726_p2 : tmp_161_fu_4732_p2);
assign tmp_163_fu_2462_p2 = (p_s_fu_2436_p2 - tmp_s_fu_2458_p1);
assign tmp_164_fu_4886_p129 = {{p_Result_798_1_fu_4442_p4}, {p_Result_796_1_1_fu_4868_p4}};
assign tmp_165_fu_5148_p1 = tmp_164_fu_4886_p130;
assign tmp_166_fu_2468_p2 = (tmp_s_fu_2458_p1 + p_s_fu_2436_p2);
assign tmp_167_fu_5152_p2 = (tmp_156_fu_4180_p130 - tmp_165_fu_5148_p1);
assign tmp_168_fu_5158_p2 = (tmp_165_fu_5148_p1 + tmp_156_fu_4180_p130);
assign tmp_169_fu_5164_p3 = ((endcap_V[0:0] === 1'b1) ? tmp_167_fu_5152_p2 : tmp_168_fu_5158_p2);
assign tmp_170_fu_2482_p2 = ((quality_0_V_read == ap_const_lv4_0) ? 1'b1 : 1'b0);
assign tmp_171_fu_2517_p2 = (primitive11_2_params_V_read_a_fu_2509_p3 - ph_tmp_V_fu_2500_p4);
assign tmp_172_fu_2536_p2 = (ap_const_lv8_14 - tmp_605_cast_fu_2532_p1);
assign tmp_173_fu_2546_p4 = {{primitive11_3_params_V_read[ap_const_lv32_7 : ap_const_lv32_1]}};
assign tmp_174_fu_2556_p4 = {{primitive11_1_params_V_read[ap_const_lv32_7 : ap_const_lv32_1]}};
assign tmp_175_fu_2566_p3 = ((tmp_503_fu_2278_p3[0:0] === 1'b1) ? tmp_173_fu_2546_p4 : tmp_174_fu_2556_p4);
assign tmp_176_fu_2584_p2 = (ph_tmp_V_fu_2500_p4 + primitive11_2_params_V_read_a_fu_2509_p3);
assign tmp_178_fu_3214_p2 = ((tmp_145_fu_3202_p3 < ap_const_lv6_2D) ? 1'b1 : 1'b0);
assign tmp_179_fu_3224_p2 = (tmp_505_fu_3220_p1 + th_tmp_V_cast_fu_3210_p1);
assign tmp_180_fu_3230_p2 = ((tmp_179_fu_3224_p2 < ap_const_lv7_2C) ? 1'b1 : 1'b0);
assign tmp_181_fu_3240_p2 = ((tmp_179_fu_3224_p2 > ap_const_lv7_7C) ? 1'b1 : 1'b0);
assign tmp_182_fu_3262_p2 = ((tmp_179_fu_3224_p2 > ap_const_lv7_27) ? 1'b1 : 1'b0);
assign tmp_184_fu_4112_p3 = ((tmp_510_fu_3850_p3[0:0] === 1'b1) ? tmp_173_fu_2546_p4 : tmp_174_fu_2556_p4);
assign tmp_25_fu_2442_p3 = ((or_cond9_fu_2358_p2[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_1);
assign tmp_26_fu_4014_p3 = ((or_cond11_fu_3930_p2[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_1);
assign tmp_503_fu_2278_p3 = hstrip_0_V_read[ap_const_lv32_7];
always @ (*) begin
tmp_504_fu_2624_p4 = ap_const_lv44_0;
tmp_504_fu_2624_p4[tmp_137_cast_fu_2620_p1] = |(1'b1);
end
assign tmp_505_fu_3220_p1 = primitive11_4_params_V_read[6:0];
always @ (*) begin
tmp_506_fu_3268_p4 = p_Val2_2_fu_3254_p3;
tmp_506_fu_3268_p4[ap_const_lv32_1] = |(1'b1);
end
always @ (*) begin
tmp_507_fu_3622_p4 = p_01099_6_fu_3292_p3;
tmp_507_fu_3622_p4[ap_const_lv32_0] = |(1'b1);
end
always @ (*) begin
tmp_508_fu_3646_p4 = p_Val2_259_0_1_fu_3632_p3;
tmp_508_fu_3646_p4[ap_const_lv32_2] = |(1'b1);
end
always @ (*) begin
tmp_509_fu_3670_p4 = p_Val2_260_0_1_fu_3656_p3;
tmp_509_fu_3670_p4[ap_const_lv32_1] = |(1'b1);
end
assign tmp_510_fu_3850_p3 = hstrip_1_V_read[ap_const_lv32_7];
always @ (*) begin
tmp_511_fu_4170_p4 = p_01111_2_fu_3842_p3;
tmp_511_fu_4170_p4[tmp_154_cast_fu_4166_p1] = |(1'b1);
end
always @ (*) begin
tmp_512_fu_4768_p4 = p_01099_7_fu_3810_p3;
tmp_512_fu_4768_p4[ap_const_lv32_0] = |(1'b1);
end
always @ (*) begin
tmp_513_fu_4792_p4 = p_Val2_259_1_fu_4778_p3;
tmp_513_fu_4792_p4[ap_const_lv32_2] = |(1'b1);
end
always @ (*) begin
tmp_514_fu_4816_p4 = p_Val2_260_1_fu_4802_p3;
tmp_514_fu_4816_p4[ap_const_lv32_1] = |(1'b1);
end
always @ (*) begin
tmp_515_fu_5194_p4 = p_01099_6_1_fu_4860_p3;
tmp_515_fu_5194_p4[ap_const_lv32_0] = |(1'b1);
end
always @ (*) begin
tmp_516_fu_5218_p4 = p_Val2_259_1_1_fu_5204_p3;
tmp_516_fu_5218_p4[ap_const_lv32_2] = |(1'b1);
end
always @ (*) begin
tmp_517_fu_5242_p4 = p_Val2_260_1_1_fu_5228_p3;
tmp_517_fu_5242_p4[ap_const_lv32_1] = |(1'b1);
end
assign tmp_597_cast_cast_fu_2428_p3 = ((tmp_503_fu_2278_p3[0:0] === 1'b1) ? ap_const_lv12_200 : ap_const_lv12_0);
assign tmp_605_cast_fu_2532_p1 = p_Result_138_fu_2523_p4;
assign tmp_606_cast_fu_2542_p1 = $signed(tmp_172_fu_2536_p2);
assign tmp_610_cast_fu_2574_p1 = tmp_175_fu_2566_p3;
assign tmp_669_1_cast_cast_fu_4000_p3 = ((tmp_510_fu_3850_p3[0:0] === 1'b1) ? ap_const_lv12_200 : ap_const_lv12_0);
assign tmp_670_1_fu_4030_p1 = tmp_153_fu_4022_p3;
assign tmp_671_1_fu_4034_p2 = (p_1_73_fu_4008_p2 - tmp_670_1_fu_4030_p1);
assign tmp_673_1_fu_4040_p2 = (tmp_670_1_fu_4030_p1 + p_1_73_fu_4008_p2);
assign tmp_678_1_fu_4083_p2 = (primitive11_2_params_V_read_a_1_fu_4075_p3 - ph_tmp_V_1_fu_4066_p4);
assign tmp_679_1_cast_fu_4098_p1 = p_Result_790_1_fu_4089_p4;
assign tmp_680_1_cast_fu_4108_p1 = $signed(tmp_680_1_fu_4102_p2);
assign tmp_680_1_fu_4102_p2 = (ap_const_lv8_14 - tmp_679_1_cast_fu_4098_p1);
assign tmp_682_1_cast_fu_4120_p1 = tmp_184_fu_4112_p3;
assign tmp_684_1_fu_4130_p2 = (ph_tmp_V_1_fu_4066_p4 + primitive11_2_params_V_read_a_1_fu_4075_p3);
assign tmp_689_0_1_fu_3300_p2 = ((quality_1_V_read == ap_const_lv4_0) ? 1'b1 : 1'b0);
assign tmp_693_0_1_fu_3604_p2 = ((tmp_151_fu_3592_p3 < ap_const_lv6_2D) ? 1'b1 : 1'b0);
assign tmp_693_1_1_fu_5176_p2 = ((tmp_169_fu_5164_p3 < ap_const_lv6_2D) ? 1'b1 : 1'b0);
assign tmp_693_1_fu_4750_p2 = ((tmp_162_fu_4738_p3 < ap_const_lv6_2D) ? 1'b1 : 1'b0);
assign tmp_697_0_1_fu_3610_p2 = (tmp_505_fu_3220_p1 + th_tmp_V_0_1_cast_fu_3600_p1);
assign tmp_697_1_1_fu_5182_p2 = (tmp_505_fu_3220_p1 + th_tmp_V_1_1_cast_fu_5172_p1);
assign tmp_697_1_fu_4756_p2 = (tmp_505_fu_3220_p1 + th_tmp_V_1_cast_fu_4746_p1);
assign tmp_698_0_1_fu_3616_p2 = ((tmp_697_0_1_fu_3610_p2 < ap_const_lv7_2C) ? 1'b1 : 1'b0);
assign tmp_698_1_1_fu_5188_p2 = ((tmp_697_1_1_fu_5182_p2 < ap_const_lv7_2C) ? 1'b1 : 1'b0);
assign tmp_698_1_fu_4762_p2 = ((tmp_697_1_fu_4756_p2 < ap_const_lv7_2C) ? 1'b1 : 1'b0);
assign tmp_701_0_1_fu_3640_p2 = ((tmp_697_0_1_fu_3610_p2 > ap_const_lv7_7C) ? 1'b1 : 1'b0);
assign tmp_701_1_1_fu_5212_p2 = ((tmp_697_1_1_fu_5182_p2 > ap_const_lv7_7C) ? 1'b1 : 1'b0);
assign tmp_701_1_fu_4786_p2 = ((tmp_697_1_fu_4756_p2 > ap_const_lv7_7C) ? 1'b1 : 1'b0);
assign tmp_702_0_1_fu_3664_p2 = ((tmp_697_0_1_fu_3610_p2 > ap_const_lv7_27) ? 1'b1 : 1'b0);
assign tmp_702_1_1_fu_5236_p2 = ((tmp_697_1_1_fu_5182_p2 > ap_const_lv7_27) ? 1'b1 : 1'b0);
assign tmp_702_1_fu_4810_p2 = ((tmp_697_1_fu_4756_p2 > ap_const_lv7_27) ? 1'b1 : 1'b0);
assign tmp_fu_3734_p2 = (tmp_702_0_1_fu_3664_p2 & sel_tmp56_fu_3728_p2);
assign tmp_s_fu_2458_p1 = tmp_136_fu_2450_p3;
endmodule //sp_prim_conv11
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHETAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DECAPHETAP_BEHAVIORAL_PP_V
/**
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__decaphetap (
VPWR,
VGND,
VPB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHETAP_BEHAVIORAL_PP_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module ad_pnmon #(
parameter DATA_WIDTH = 16) (
// adc interface
input adc_clk,
input adc_valid_in,
input [(DATA_WIDTH-1):0] adc_data_in,
input [(DATA_WIDTH-1):0] adc_data_pn,
// pn out of sync and error
output adc_pn_oos,
output adc_pn_err);
// internal registers
reg adc_valid_d = 'd0;
reg adc_pn_match_d = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_oos_int = 'd0;
reg adc_pn_err_int = 'd0;
reg [ 3:0] adc_pn_oos_count = 'd0;
// internal signals
wire adc_pn_match_d_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// make sure data is not 0, sequence will fail.
assign adc_pn_match_d_s = (adc_data_in == adc_data_pn) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_data_in == 'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d & adc_pn_match_z;
assign adc_pn_update_s = ~(adc_pn_oos_int ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos_int | adc_pn_match_s);
// pn oos and counters (16 to clear and set).
assign adc_pn_oos = adc_pn_oos_int;
assign adc_pn_err = adc_pn_err_int;
always @(posedge adc_clk) begin
adc_valid_d <= adc_valid_in;
adc_pn_match_d <= adc_pn_match_d_s;
adc_pn_match_z <= adc_pn_match_z_s;
if (adc_valid_d == 1'b1) begin
adc_pn_err_int <= adc_pn_err_s;
if ((adc_pn_update_s == 1'b1) && (adc_pn_oos_count >= 15)) begin
adc_pn_oos_int <= ~adc_pn_oos_int;
end
if (adc_pn_update_s == 1'b1) begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
end else begin
adc_pn_oos_count <= 'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 500ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/05/2015 01:48:32 PM
// Design Name:
// Module Name: pwm_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pwm_tb;
reg clk1MHz, rst;
wire pwm;
//reg clk200Hz;
//reg clk1MHz;
wire clk200Hz;
//wire clk1MHz;
//reg [9:0] pos;
wire [9:0] pos;
clk_gen U0 (
.clk1MHz(clk1MHz),
.rst(rst),
.clk200Hz(clk200Hz)
);
SweepPosition U1 (
.pos(pos),
.clk200Hz(clk200Hz),
.rst(rst)
);
AngleToPWM U2 (
.pos(pos),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm)
);
integer i;
reg success_flag;
initial begin
success_flag = 1;
rst = 0;
#5
rst = 1;
#5
rst = 0;
for(i = 0; i < 32'd30_000_000; i=i+1)
begin
#1
clk1MHz = 0;
#1
clk1MHz = 1;
end
/* Simple Position Testing
pos = 0;
#10
for(i = 0; i < 32'd100_000; i=i+1)
begin
#1
clk1MHz = 0;
#1
clk1MHz = 1;
end
pos = 250;
#10
for(i = 0; i < 32'd100_000; i=i+1)
begin
#1
clk1MHz = 0;
#1
clk1MHz = 1;
end
pos = 500;
#10
for(i = 0; i < 32'd100_000; i=i+1)
begin
#1
clk1MHz = 0;
#1
clk1MHz = 1;
end
pos = 750;
#10
for(i = 0; i < 32'd100_000; i=i+1)
begin
#1
clk1MHz = 0;
#1
clk1MHz = 1;
end
pos = 1000;
#10
for(i = 0; i < 32'd100_000; i=i+1)
begin
#1
clk1MHz = 0;
#1
clk1MHz = 1;
end
*/
// for(i = 0; i < 32'd2000; i=i+1)
// begin
// #2
// clk200Hz = 0;
// #2
// clk200Hz = 1;
// end
// pos = 10'd500;
// for(i = 0; i < 32'd25_000; i=i+1)
// begin
// #2
// clk1MHz = 0;
// #2
// clk1MHz = 1;
// end
// pos = 10'd100;
// for(i = 0; i < 32'd25_000; i=i+1)
// begin
// #2
// clk1MHz = 0;
// #2
// clk1MHz = 1;
// end
// pos = 10'd1000;
// for(i = 0; i < 32'd25_000; i=i+1)
// begin
// #2
// clk1MHz = 0;
// #2
// clk1MHz = 1;
// end
// Print out Success/Failure message
if (success_flag == 0) begin
$display("*FAILED** TEST!");
end
else begin
$display("**PASSED** TEST!");
end
#10 $stop;
#5 $finish;
end
endmodule |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:39:19 05/12/2015
// Design Name: data_memory
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_data_memory.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: data_memory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_data_memory;
// Inputs
reg clock;
reg mem_write;
reg [11:0] address;
reg [15:0] data_in;
// Outputs
wire [15:0] data_out;
// Instantiate the Unit Under Test (UUT)
data_memory uut (
.clock(clock),
.mem_write(mem_write),
.address(address),
.data_in(data_in),
.data_out(data_out)
);
initial begin
// Initialize Inputs
clock = 0;
mem_write = 0;
address = 0;
data_in = 0;
// Wait 100 ns for global reset to finish
//#100;
#1;
address = 12'h001;
#2;
address = 12'h002;
#2;
address = 12'h003;
end
always #1 clock = !clock;
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_32_128x16.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_32_128x16 (
byteena_a,
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [3:0] byteena_a;
input [31:0] data;
input [1:0] rdaddress;
input rdclock;
input [3:0] wraddress;
input wrclock;
input wren;
output [127:0] q;
wire [127:0] sub_wire0;
wire [127:0] q = sub_wire0[127:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.byteena_a (byteena_a),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_b ({128{1'b1}}),
.q_a (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16,
altsyncram_component.numwords_b = 4,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 4,
altsyncram_component.widthad_b = 2,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 128,
altsyncram_component.width_byteena_a = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "128"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC byteena_a[3..0]
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: USED_PORT: rdaddress 0 0 2 0 INPUT NODEFVAL rdaddress[1..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_b 0 0 128 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 2 0 rdaddress 0 0 2 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* FrameWriter.v
*
* Created on: 09/10/2012
* Author: Lord_Rafa
*/
`timescale 1ns / 1ps
module FrameWriter (
input clk,
input rst,
input [23:0] din_data,
input din_valid,
output wire din_ready,
input wire din_sop,
input wire din_eop,
output wire [DATA_WIDTH-1:0] data_fifo_out,
output wire data_valid_fifo_out,
input wire [FIFO_DEPTH_LOG2:0] usedw_fifo_out,
input start,
output endf
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 256;
parameter FIFO_DEPTH_LOG2 = 8;
reg video_reg;
wire set_video;
wire reset_video;
reg [1:0] run;
always @ (posedge clk) begin
if (start == 1) begin
video_reg <= 0;
end else begin
if (reset_video == 1) begin
video_reg <= 0;
end
if (set_video == 1) begin
video_reg <= 1;
end
end
end
always @ (posedge clk or posedge rst) begin
if (rst == 1) begin
run <= 0;
end else begin
if (start == 1) begin
run <= 1;
end else begin
if (reset_video == 1) begin
run <= 2;
end
if (endf == 1) begin
run <= 0;
end
end
end
end
assign set_video = (din_sop == 1) & (din_data == 0) & (din_valid == 1) & (run == 1);
assign reset_video = (din_eop == 1) & (din_valid == 1) & (video_reg == 1);
assign data_fifo_out = {8'd0, din_data};
assign data_valid_fifo_out = (video_reg == 1) & (din_valid == 1) & (run == 1);
assign din_ready = (usedw_fifo_out < (FIFO_DEPTH - 1));
assign endf = (run == 2);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cluster_header.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// The cluster header is instatiated as a hard macro.
// This model is for simulation only.
`include "sys.h"
module cluster_header (/*AUTOARG*/
// Outputs
dbginit_l, cluster_grst_l, rclk, so,
// Inputs
gclk, cluster_cken, arst_l, grst_l, adbginit_l, gdbginit_l, si,
se
);
input gclk;
input cluster_cken;
input arst_l;
input grst_l;
input adbginit_l;
input gdbginit_l;
output dbginit_l;
output cluster_grst_l;
output rclk;
input si; // scan ports for reset flop repeaters
input se;
output so;
`ifdef FPGA_SYN
// assign #10 rclk = gclk;
// assign #10 dbginit_l = gdbginit_l;
// assign #10 cluster_grst_l = grst_l;
// assign so = 1'b0;
reg dbginit_l;
reg cluster_grst_l;
assign #10 rclk = gclk;
always @(negedge rclk) begin
dbginit_l <= gdbginit_l;
cluster_grst_l <= grst_l;
end
`else
wire pre_sync_enable;
wire sync_enable;
wire cluster_grst_l;
wire dbginit_l;
wire rst_sync_so;
bw_u1_syncff_4x sync_cluster_master ( // no scan hook-up
.so(),
.q (pre_sync_enable),
.ck (gclk),
.d (cluster_cken),
.sd(1'b0),
.se(1'b0)
);
bw_u1_scanl_2x sync_cluster_slave ( // use scan lock-up latch
.so (sync_enable),
.ck (gclk),
.sd (pre_sync_enable)
);
// NOTE! Pound delay in the below statement is meant to provide 10 ps
// delay between gclk and rclk to allow the synchronizer for rst, dbginit,
// and sync pulses to be modelled accurately. gclk and rclk need to have
// at least one simulator timestep separation to allow the flop->flop
// synchronizer to work correctly.
assign #10 rclk = gclk & sync_enable;
synchronizer_asr rst_repeater (
.sync_out(cluster_grst_l),
.so(rst_sync_so),
.async_in(grst_l),
.gclk(gclk),
.rclk(rclk),
.arst_l(arst_l),
.si(si),
.se(se)
);
synchronizer_asr dbginit_repeater (
.sync_out(dbginit_l),
.so(so),
.async_in(gdbginit_l),
.gclk(gclk),
.rclk(rclk),
.arst_l(adbginit_l),
.si(rst_sync_so),
.se(se)
);
`endif
endmodule // cluster_header
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLRTP_PP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrtp (
RESET_B,
D ,
GATE ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE ;
output Q ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_PP_BLACKBOX_V
|
`timescale 1ps/1ps
module _____00003aT0( );
reg rst;
reg clk1;
reg clk2;
reg clk3;
reg [7:0] idata;
reg [7:0] odata;
wire [7:0] odata2;
reg [3:0] counter;
wire _00003a4;
reg _00003a5;
reg [7:0] _00003a6;
wire _00003a1;
wire [7:0] _00003a2;
reg _00003a3;
wire [7:0] my__ch_00003a0_00003a_00003adata;
wire my__ch_00003a0_00003a_00003areq;
wire my__ch_00003a0_00003a_00003aack;
assign _00003a4 = my__ch_00003a0_00003a_00003areq;
assign _00003a5 = my__ch_00003a0_00003a_00003aack;
assign _00003a6 = my__ch_00003a0_00003a_00003adata;
assign _00003a1 = my__ch_00003a0_00003a_00003aack;
assign _00003a2 = my__ch_00003a0_00003a_00003adata;
assign _00003a3 = my__ch_00003a0_00003a_00003areq;
always @( posedge clk3 ) begin
_00003a5 <= 32'd0;
if (rst) begin
idata <= 32'd0;
end
else begin
if (_00003a4) begin
if (~_00003a5) begin
_00003a6 <= idata;
idata <= (idata + 32'd1);
end
_00003a5 <= 32'd1;
end
end
end
always @( posedge clk2 ) begin
_00003a3 <= 32'd0;
if (rst) begin
counter <= 32'd0;
end
else begin
if ((_00003a1 == 32'd0)) begin
_00003a3 <= 32'd1;
end
else if (_00003a3) begin
odata <= _00003a2;
_00003a3 <= 32'd0;
counter <= (counter + 32'd1);
end
end
end
initial begin
clk1 = 32'd0;
clk2 = 32'd0;
clk3 = 32'd0;
rst = 32'd0;
#10000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
rst = 32'd1;
#3000
clk2 = 32'd1;
#3000
clk3 = 32'd0;
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = 32'd0;
#3000
clk3 = 32'd1;
#2000
rst = 32'd0;
#2000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
clk1 = 32'd1;
#10000
clk1 = 32'd0;
#3000
clk2 = ~clk2;
#3000
if ((clk2 == 32'd0)) begin
clk3 = ~clk3;
end
#4000
end
endmodule |
module hardcaml_lib_add #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output [b-1:0] o
);
assign o = i0 + i1;
endmodule
module hardcaml_lib_sub #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output [b-1:0] o
);
assign o = i0 - i1;
endmodule
module hardcaml_lib_mulu
#(
parameter w0=1,
parameter w1=1
)
(
input [w0-1:0] i0,
input [w1-1:0] i1,
output [w0+w1-1:0] o
);
assign o = i0 * i1;
endmodule
module hardcaml_lib_muls
#(
parameter w0=1,
parameter w1=1
)
(
input [w0-1:0] i0,
input [w1-1:0] i1,
output [w0+w1-1:0] o
);
assign o = $signed(i0) * $signed(i1);
endmodule
module hardcaml_lib_and #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output [b-1:0] o
);
assign o = i0 & i1;
endmodule
module hardcaml_lib_or #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output [b-1:0] o
);
assign o = i0 | i1;
endmodule
module hardcaml_lib_xor #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output [b-1:0] o
);
assign o = i0 ^ i1;
endmodule
module hardcaml_lib_not #(parameter b=1)
(
input [b-1:0] i,
output [b-1:0] o
);
assign o = ~ i;
endmodule
module hardcaml_lib_eq #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output o
);
assign o = i0 == i1;
endmodule
module hardcaml_lib_lt #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output o
);
assign o = i0 < i1;
endmodule
module hardcaml_lib_gnd
(
output o
);
assign o = 1'b0;
endmodule
module hardcaml_lib_vdd
(
output o
);
assign o = 1'b1;
endmodule
module hardcaml_lib_z
(
output o
);
assign o = 1'bz;
endmodule
module hardcaml_lib_concat2
#(
parameter w0=1,
parameter w1=1
)
(
input [w0-1:0] i0,
input [w1-1:0] i1,
output [w0+w1-1:0] o
);
assign o = {i0,i1};
endmodule
module hardcaml_lib_mux2 #(parameter b=1)
(
input sel,
input [b-1:0] d0,
input [b-1:0] d1,
output [b-1:0] o
);
assign o = sel ? d1 : d0;
endmodule
module hardcaml_lib_select
#(
parameter b=1,
parameter h=0,
parameter l=0
)
(
input [b-1:0] i,
output [h-l:0] o
);
assign o=i[h:l];
endmodule
module hardcaml_tristate_buffer
#(
parameter b=1
)
(
input en,
input [b-1:0] i,
output [b-1:0] o,
inout [b-1:0] io
);
assign io = en ? i : {b{1'bz}};
assign o = io;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND2_TB_V
`define SKY130_FD_SC_LP__TAPVGND2_TB_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__tapvgnd2.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_lp__tapvgnd2 dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211A_4_V
`define SKY130_FD_SC_HD__O211A_4_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o211a_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o211a_4 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211A_4_V
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module ReadConfigStruct #(parameter MAX_NUM_CONFIG_CL = 2)
(
input wire clk,
input wire rst_n,
//-------------------------------------------------//
input wire get_config_struct,
input wire [57:0] base_addr,
input wire [31:0] config_struct_length,
// User Module TX RD
output reg [57:0] cs_tx_rd_addr,
output reg [8:0] cs_tx_rd_tag,
output reg cs_tx_rd_valid,
input wire cs_tx_rd_free,
// User Module RX RD
input wire [8:0] cs_rx_rd_tag,
input wire [511:0] cs_rx_rd_data,
input wire cs_rx_rd_valid,
//
output wire [(MAX_NUM_CONFIG_CL<<9)-1:0] afu_config_struct,
output wire afu_config_struct_valid
);
wire rd_done;
wire all_reads_done;
reg [31:0] numReadsSent;
reg [31:0] numReadsDone;
reg [31:0] rd_cnt;
reg [511:0] config_lines[MAX_NUM_CONFIG_CL];
reg config_lines_valid[MAX_NUM_CONFIG_CL];
genvar i;
generate for( i = 0; i < MAX_NUM_CONFIG_CL; i = i + 1) begin: configLines
always@(posedge clk) begin
if(~rst_n) begin
//config_lines[ i ] <= 0;
config_lines_valid[ i ] <= 0;
end
else if(cs_rx_rd_valid) begin
config_lines[ i ] <= (cs_rx_rd_tag[1:0] == i)? cs_rx_rd_data : config_lines[ i ];
config_lines_valid[ i ] <= (cs_rx_rd_tag[1:0] == i)? 1'b1 : config_lines_valid[ i ];
end
end
assign afu_config_struct[512*(i+1) - 1 : 512*i] = config_lines[ i ];
end
endgenerate
/////////////////////////////// Generating Read Requests //////////////////////////////
//
assign all_reads_done = (numReadsSent == numReadsDone) & (numReadsSent != 0);
assign afu_config_struct_valid = rd_done & all_reads_done;
assign rd_done = (rd_cnt == config_struct_length);
always@(posedge clk) begin
if(~rst_n) begin
cs_tx_rd_valid <= 1'b0;
rd_cnt <= 0;
cs_tx_rd_addr <= 0;
cs_tx_rd_tag <= 0;
end
else if(cs_tx_rd_free | ~cs_tx_rd_valid) begin
if( ~rd_done & get_config_struct ) begin
rd_cnt <= rd_cnt + 1'b1;
cs_tx_rd_valid <= 1'b1;
cs_tx_rd_addr <= ({1'b0, base_addr} + {1'b0, rd_cnt});
cs_tx_rd_tag <= rd_cnt[8:0];
end
else begin
cs_tx_rd_valid <= 1'b0;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if(~rst_n) begin
numReadsSent <= 0;
numReadsDone <= 0;
end
else begin
numReadsSent <= (cs_tx_rd_valid & cs_tx_rd_free)? numReadsSent + 1'b1 : numReadsSent;
numReadsDone <= (cs_rx_rd_valid)? numReadsDone + 1'b1 : numReadsDone;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BLACKBOX_V
/**
* lpflow_inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso0p (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Ram Blocks Module
// File : ram_blks.v
// Author : Jim MacLeod
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
//
// This Model contains all the rams used on the core
//
/////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module ram_blks
(
input hclk,
input hresetn,
input wrn,
input pixclk,
input palwr,
input [7:0] pal_cpu_adr,
input [7:0] red2pal,
input [7:0] grn2pal,
input [7:0] blu2pal,
input cpu_pal_one,
input cpu_cursor_one,
input [10:0] idx_inc,
input [7:0] cpu2cursor,
input disp_pal_one,
input disp_cursor_one,
// Address for Palette Display Output.
input [7:0] palr_addr_evn,
input [7:0] palg_addr_evn,
input [7:0] palb_addr_evn,
// Address for Cursor Display Output.
input [7:0] cursor_addr,
output [7:0] palr2dac_evn,
output [7:0] palr2cpu,
output [7:0] palg2dac_evn,
output [7:0] palg2cpu,
output [7:0] palb2dac_evn,
output [7:0] palb2cpu,
output reg [7:0] cursor2cpu,
output [7:0] cursor1_data,
output [7:0] cursor2_data,
output [7:0] cursor3_data,
output [7:0] cursor4_data
);
wire [7:0] curdata1,
curdata2,
curdata3,
curdata4;
reg wr1, wr2;
always @(posedge hclk or negedge hresetn)
if (!hresetn)
begin
wr1 <= 1'b0;
wr2 <= 1'b0;
end
else begin
wr1 <= wrn;
wr2 <= wr1;
end
wire wr_pulse = wr1 & !wr2;
wire cursor1_wr = !idx_inc[10] & !idx_inc[9] & idx_inc[8] & wr_pulse;
wire cursor2_wr = !idx_inc[10] & idx_inc[9] & !idx_inc[8] & wr_pulse;
wire cursor3_wr = !idx_inc[10] & idx_inc[9] & idx_inc[8] & wr_pulse;
wire cursor4_wr = idx_inc[10] & !idx_inc[9] & !idx_inc[8] & wr_pulse;
always @*
begin
case(idx_inc[10:8])
3'b001 : cursor2cpu <= curdata1 ;
3'b010 : cursor2cpu <= curdata2 ;
3'b011 : cursor2cpu <= curdata3 ;
default : cursor2cpu <= curdata4 ;
endcase
end
ram_blk red_ram_blk
(
.hclk (hclk),
.write (palwr),
.cpu_address ({cpu_pal_one,pal_cpu_adr}),
.cpu_data_in (red2pal),
.pixclk (pixclk),
.evn_address ({disp_pal_one, palr_addr_evn}),
.evn_data_out (palr2dac_evn),
.cpu_data_out (palr2cpu)
);
ram_blk green_ram_blk
(
.hclk (hclk),
.write (palwr),
.cpu_address ({cpu_pal_one,pal_cpu_adr}),
.cpu_data_in (grn2pal),
.pixclk (pixclk),
.evn_address ({disp_pal_one, palg_addr_evn}),
.evn_data_out (palg2dac_evn),
.cpu_data_out (palg2cpu)
);
ram_blk blue_ram_blk
(
.hclk (hclk),
.write (palwr),
.cpu_address ({cpu_pal_one,pal_cpu_adr}),
.cpu_data_in (blu2pal),
.pixclk (pixclk),
.evn_address ({disp_pal_one, palb_addr_evn}),
.evn_data_out (palb2dac_evn),
.cpu_data_out (palb2cpu)
);
cur_ram_blk cursor1_ram_blk
(
.hclk (hclk),
.write (cursor1_wr),
.cpu_address ({cpu_cursor_one,idx_inc[7:0]}),
.cpu_data_in (cpu2cursor),
.pixclk (pixclk),
.cur_address ({disp_cursor_one, cursor_addr}),
.cur_data_out (cursor1_data),
.cpu_data_out (curdata1)
);
cur_ram_blk cursor2_ram_blk(
.hclk (hclk),
.write (cursor2_wr),
.cpu_address ({cpu_cursor_one,idx_inc[7:0]}),
.cpu_data_in (cpu2cursor),
.pixclk (pixclk),
.cur_address ({disp_cursor_one, cursor_addr}),
.cur_data_out (cursor2_data),
.cpu_data_out (curdata2)
);
cur_ram_blk cursor3_ram_blk
(
.hclk (hclk),
.write (cursor3_wr),
.cpu_address ({cpu_cursor_one,idx_inc[7:0]}),
.cpu_data_in (cpu2cursor),
.pixclk (pixclk),
.cur_address ({disp_cursor_one, cursor_addr}),
.cur_data_out (cursor3_data),
.cpu_data_out (curdata3)
);
cur_ram_blk cursor4_ram_blk
(
.hclk (hclk),
.write (cursor4_wr),
.cpu_address ({cpu_cursor_one,idx_inc[7:0]}),
.cpu_data_in (cpu2cursor),
.pixclk (pixclk),
.cur_address ({disp_cursor_one, cursor_addr}),
.cur_data_out (cursor4_data),
.cpu_data_out (curdata4)
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//name : user_design
//input : input_switches:16
//input : input_buttons:16
//input : input_socket:16
//input : input_rs232_rx:16
//output : output_rs232_tx:16
//output : output_leds:16
//output : output_socket:16
//source_file : ../source/user_design.c
///===========
///
///Created by C2CHIP
//////////////////////////////////////////////////////////////////////////////
// Register Allocation
// ===================
// Register Name Size
// 0 variable digit_4 2
// 1 variable significant 2
// 2 HTTP_Not_Found return address 2
// 3 variable header_length 2
// 4 array 2
// 5 HTTP_OK return address 2
// 6 array 2
// 7 variable header_length 2
// 8 variable body_length 2
// 9 variable length 2
// 10 variable index 2
// 11 variable packet_count 2
// 12 array 2
// 13 array 2
// 14 find return address 2
// 15 variable find return value 2
// 16 array 2
// 17 variable search 2
// 18 variable start 2
// 19 variable end 2
// 20 variable value 2
// 21 array 2
// 22 array 2
// 23 user_design return address 2
// 24 variable length 2
// 25 variable i 2
// 26 variable index 2
// 27 array 2
// 28 variable word 2
// 29 variable switches 2
// 30 variable buttons 2
// 31 variable leds 2
// 32 variable start 2
// 33 variable end 2
// 34 array 2
// 35 array 2
// 36 array 2
// 37 temporary_register 2
// 38 temporary_register 2
// 39 temporary_register 2
// 40 temporary_register 4
// 41 temporary_register 2
// 42 temporary_register 252
// 43 temporary_register 228
// 44 temporary_register 10
// 45 temporary_register 78
// 46 temporary_register 86
// 47 temporary_register 2
// 48 temporary_register 2920
// 49 temporary_register 2284
// 50 put_socket return address 2
// 51 variable i 2
// 52 stdout_put_char return address 2
// 53 variable i 2
// 54 print_string return address 2
// 55 array 2
// 56 variable i 2
// 57 print_udecimal return address 2
// 58 variable udecimal 2
// 59 variable digit 2
// 60 variable significant 2
// 61 print_decimal return address 2
// 62 variable decimal 2
// 63 variable socket_high 2
// 64 variable socket_data 2
// 65 socket_put_char return address 2
// 66 variable x 2
// 67 socket_flush return address 2
// 68 socket_put_string return address 2
// 69 array 2
// 70 variable i 2
// 71 socket_put_decimal return address 2
// 72 variable value 2
// 73 variable digit_0 2
// 74 variable digit_1 2
// 75 variable digit_2 2
// 76 variable digit_3 2
module user_design(input_switches,input_buttons,input_socket,input_rs232_rx,input_switches_stb,input_buttons_stb,input_socket_stb,input_rs232_rx_stb,output_rs232_tx_ack,output_leds_ack,output_socket_ack,clk,rst,output_rs232_tx,output_leds,output_socket,output_rs232_tx_stb,output_leds_stb,output_socket_stb,input_switches_ack,input_buttons_ack,input_socket_ack,input_rs232_rx_ack);
integer file_count;
real fp_value;
input [15:0] input_switches;
input [15:0] input_buttons;
input [15:0] input_socket;
input [15:0] input_rs232_rx;
input input_switches_stb;
input input_buttons_stb;
input input_socket_stb;
input input_rs232_rx_stb;
input output_rs232_tx_ack;
input output_leds_ack;
input output_socket_ack;
input clk;
input rst;
output [15:0] output_rs232_tx;
output [15:0] output_leds;
output [15:0] output_socket;
output output_rs232_tx_stb;
output output_leds_stb;
output output_socket_stb;
output input_switches_ack;
output input_buttons_ack;
output input_socket_ack;
output input_rs232_rx_ack;
reg [15:0] timer;
reg timer_enable;
reg stage_0_enable;
reg stage_1_enable;
reg stage_2_enable;
reg [10:0] program_counter;
reg [10:0] program_counter_0;
reg [51:0] instruction_0;
reg [5:0] opcode_0;
reg [6:0] dest_0;
reg [6:0] src_0;
reg [6:0] srcb_0;
reg [31:0] literal_0;
reg [10:0] program_counter_1;
reg [5:0] opcode_1;
reg [6:0] dest_1;
reg [31:0] register_1;
reg [31:0] registerb_1;
reg [31:0] literal_1;
reg [6:0] dest_2;
reg [31:0] result_2;
reg write_enable_2;
reg [15:0] address_2;
reg [15:0] data_out_2;
reg [15:0] data_in_2;
reg memory_enable_2;
reg [15:0] address_4;
reg [31:0] data_out_4;
reg [31:0] data_in_4;
reg memory_enable_4;
reg [15:0] s_output_rs232_tx_stb;
reg [15:0] s_output_leds_stb;
reg [15:0] s_output_socket_stb;
reg [15:0] s_output_rs232_tx;
reg [15:0] s_output_leds;
reg [15:0] s_output_socket;
reg [15:0] s_input_switches_ack;
reg [15:0] s_input_buttons_ack;
reg [15:0] s_input_socket_ack;
reg [15:0] s_input_rs232_rx_ack;
reg [15:0] memory_2 [2940:0];
reg [51:0] instructions [1717:0];
reg [31:0] registers [76:0];
//////////////////////////////////////////////////////////////////////////////
// MEMORY INITIALIZATION
//
// In order to reduce program size, array contents have been stored into
// memory at initialization. In an FPGA, this will result in the memory being
// initialized when the FPGA configures.
// Memory will not be re-initialized at reset.
// Dissable this behaviour using the no_initialize_memory switch
initial
begin
memory_2[4] = 72;
memory_2[5] = 84;
memory_2[6] = 84;
memory_2[7] = 80;
memory_2[8] = 47;
memory_2[9] = 49;
memory_2[10] = 46;
memory_2[11] = 49;
memory_2[12] = 32;
memory_2[13] = 52;
memory_2[14] = 48;
memory_2[15] = 52;
memory_2[16] = 32;
memory_2[17] = 78;
memory_2[18] = 111;
memory_2[19] = 116;
memory_2[20] = 32;
memory_2[21] = 70;
memory_2[22] = 111;
memory_2[23] = 117;
memory_2[24] = 110;
memory_2[25] = 100;
memory_2[26] = 13;
memory_2[27] = 10;
memory_2[28] = 68;
memory_2[29] = 97;
memory_2[30] = 116;
memory_2[31] = 101;
memory_2[32] = 58;
memory_2[33] = 32;
memory_2[34] = 84;
memory_2[35] = 104;
memory_2[36] = 117;
memory_2[37] = 32;
memory_2[38] = 79;
memory_2[39] = 99;
memory_2[40] = 116;
memory_2[41] = 32;
memory_2[42] = 51;
memory_2[43] = 49;
memory_2[44] = 32;
memory_2[45] = 49;
memory_2[46] = 57;
memory_2[47] = 58;
memory_2[48] = 49;
memory_2[49] = 54;
memory_2[50] = 58;
memory_2[51] = 48;
memory_2[52] = 48;
memory_2[53] = 32;
memory_2[54] = 50;
memory_2[55] = 48;
memory_2[56] = 49;
memory_2[57] = 51;
memory_2[58] = 13;
memory_2[59] = 10;
memory_2[60] = 83;
memory_2[61] = 101;
memory_2[62] = 114;
memory_2[63] = 118;
memory_2[64] = 101;
memory_2[65] = 114;
memory_2[66] = 58;
memory_2[67] = 32;
memory_2[68] = 99;
memory_2[69] = 104;
memory_2[70] = 105;
memory_2[71] = 112;
memory_2[72] = 115;
memory_2[73] = 45;
memory_2[74] = 119;
memory_2[75] = 101;
memory_2[76] = 98;
memory_2[77] = 47;
memory_2[78] = 48;
memory_2[79] = 46;
memory_2[80] = 48;
memory_2[81] = 13;
memory_2[82] = 10;
memory_2[83] = 67;
memory_2[84] = 111;
memory_2[85] = 110;
memory_2[86] = 116;
memory_2[87] = 101;
memory_2[88] = 110;
memory_2[89] = 116;
memory_2[90] = 45;
memory_2[91] = 84;
memory_2[92] = 121;
memory_2[93] = 112;
memory_2[94] = 101;
memory_2[95] = 58;
memory_2[96] = 32;
memory_2[97] = 116;
memory_2[98] = 101;
memory_2[99] = 120;
memory_2[100] = 116;
memory_2[101] = 47;
memory_2[102] = 104;
memory_2[103] = 116;
memory_2[104] = 109;
memory_2[105] = 108;
memory_2[106] = 13;
memory_2[107] = 10;
memory_2[108] = 67;
memory_2[109] = 111;
memory_2[110] = 110;
memory_2[111] = 116;
memory_2[112] = 101;
memory_2[113] = 110;
memory_2[114] = 116;
memory_2[115] = 45;
memory_2[116] = 76;
memory_2[117] = 101;
memory_2[118] = 110;
memory_2[119] = 103;
memory_2[120] = 116;
memory_2[121] = 104;
memory_2[122] = 58;
memory_2[123] = 32;
memory_2[124] = 48;
memory_2[125] = 13;
memory_2[126] = 10;
memory_2[127] = 13;
memory_2[128] = 10;
memory_2[129] = 0;
memory_2[132] = 72;
memory_2[133] = 84;
memory_2[134] = 84;
memory_2[135] = 80;
memory_2[136] = 47;
memory_2[137] = 49;
memory_2[138] = 46;
memory_2[139] = 49;
memory_2[140] = 32;
memory_2[141] = 50;
memory_2[142] = 48;
memory_2[143] = 48;
memory_2[144] = 32;
memory_2[145] = 79;
memory_2[146] = 75;
memory_2[147] = 13;
memory_2[148] = 10;
memory_2[149] = 68;
memory_2[150] = 97;
memory_2[151] = 116;
memory_2[152] = 101;
memory_2[153] = 58;
memory_2[154] = 32;
memory_2[155] = 84;
memory_2[156] = 104;
memory_2[157] = 117;
memory_2[158] = 32;
memory_2[159] = 79;
memory_2[160] = 99;
memory_2[161] = 116;
memory_2[162] = 32;
memory_2[163] = 51;
memory_2[164] = 49;
memory_2[165] = 32;
memory_2[166] = 49;
memory_2[167] = 57;
memory_2[168] = 58;
memory_2[169] = 49;
memory_2[170] = 54;
memory_2[171] = 58;
memory_2[172] = 48;
memory_2[173] = 48;
memory_2[174] = 32;
memory_2[175] = 50;
memory_2[176] = 48;
memory_2[177] = 49;
memory_2[178] = 51;
memory_2[179] = 13;
memory_2[180] = 10;
memory_2[181] = 83;
memory_2[182] = 101;
memory_2[183] = 114;
memory_2[184] = 118;
memory_2[185] = 101;
memory_2[186] = 114;
memory_2[187] = 58;
memory_2[188] = 32;
memory_2[189] = 99;
memory_2[190] = 104;
memory_2[191] = 105;
memory_2[192] = 112;
memory_2[193] = 115;
memory_2[194] = 45;
memory_2[195] = 119;
memory_2[196] = 101;
memory_2[197] = 98;
memory_2[198] = 47;
memory_2[199] = 48;
memory_2[200] = 46;
memory_2[201] = 48;
memory_2[202] = 13;
memory_2[203] = 10;
memory_2[204] = 67;
memory_2[205] = 111;
memory_2[206] = 110;
memory_2[207] = 116;
memory_2[208] = 101;
memory_2[209] = 110;
memory_2[210] = 116;
memory_2[211] = 45;
memory_2[212] = 84;
memory_2[213] = 121;
memory_2[214] = 112;
memory_2[215] = 101;
memory_2[216] = 58;
memory_2[217] = 32;
memory_2[218] = 116;
memory_2[219] = 101;
memory_2[220] = 120;
memory_2[221] = 116;
memory_2[222] = 47;
memory_2[223] = 104;
memory_2[224] = 116;
memory_2[225] = 109;
memory_2[226] = 108;
memory_2[227] = 13;
memory_2[228] = 10;
memory_2[229] = 67;
memory_2[230] = 111;
memory_2[231] = 110;
memory_2[232] = 116;
memory_2[233] = 101;
memory_2[234] = 110;
memory_2[235] = 116;
memory_2[236] = 45;
memory_2[237] = 76;
memory_2[238] = 101;
memory_2[239] = 110;
memory_2[240] = 103;
memory_2[241] = 116;
memory_2[242] = 104;
memory_2[243] = 58;
memory_2[244] = 32;
memory_2[245] = 0;
memory_2[246] = 13;
memory_2[247] = 10;
memory_2[248] = 13;
memory_2[249] = 10;
memory_2[250] = 0;
memory_2[253] = 10;
memory_2[254] = 0;
memory_2[255] = 10;
memory_2[256] = 0;
memory_2[1717] = 60;
memory_2[1718] = 104;
memory_2[1719] = 116;
memory_2[1720] = 109;
memory_2[1721] = 108;
memory_2[1722] = 62;
memory_2[1723] = 60;
memory_2[1724] = 104;
memory_2[1725] = 101;
memory_2[1726] = 97;
memory_2[1727] = 100;
memory_2[1728] = 62;
memory_2[1729] = 60;
memory_2[1730] = 116;
memory_2[1731] = 105;
memory_2[1732] = 116;
memory_2[1733] = 108;
memory_2[1734] = 101;
memory_2[1735] = 62;
memory_2[1736] = 68;
memory_2[1737] = 101;
memory_2[1738] = 109;
memory_2[1739] = 111;
memory_2[1740] = 32;
memory_2[1741] = 111;
memory_2[1742] = 110;
memory_2[1743] = 32;
memory_2[1744] = 78;
memory_2[1745] = 69;
memory_2[1746] = 88;
memory_2[1747] = 89;
memory_2[1748] = 83;
memory_2[1749] = 51;
memory_2[1750] = 32;
memory_2[1751] = 98;
memory_2[1752] = 111;
memory_2[1753] = 97;
memory_2[1754] = 114;
memory_2[1755] = 100;
memory_2[1756] = 32;
memory_2[1757] = 117;
memory_2[1758] = 115;
memory_2[1759] = 105;
memory_2[1760] = 110;
memory_2[1761] = 103;
memory_2[1762] = 32;
memory_2[1763] = 67;
memory_2[1764] = 104;
memory_2[1765] = 105;
memory_2[1766] = 112;
memory_2[1767] = 115;
memory_2[1768] = 45;
memory_2[1769] = 50;
memory_2[1770] = 46;
memory_2[1771] = 48;
memory_2[1772] = 60;
memory_2[1773] = 47;
memory_2[1774] = 116;
memory_2[1775] = 105;
memory_2[1776] = 116;
memory_2[1777] = 108;
memory_2[1778] = 101;
memory_2[1779] = 62;
memory_2[1780] = 60;
memory_2[1781] = 47;
memory_2[1782] = 104;
memory_2[1783] = 101;
memory_2[1784] = 97;
memory_2[1785] = 100;
memory_2[1786] = 62;
memory_2[1787] = 60;
memory_2[1788] = 98;
memory_2[1789] = 111;
memory_2[1790] = 100;
memory_2[1791] = 121;
memory_2[1792] = 62;
memory_2[1793] = 60;
memory_2[1794] = 104;
memory_2[1795] = 49;
memory_2[1796] = 62;
memory_2[1797] = 87;
memory_2[1798] = 101;
memory_2[1799] = 108;
memory_2[1800] = 99;
memory_2[1801] = 111;
memory_2[1802] = 109;
memory_2[1803] = 101;
memory_2[1804] = 32;
memory_2[1805] = 60;
memory_2[1806] = 47;
memory_2[1807] = 104;
memory_2[1808] = 49;
memory_2[1809] = 62;
memory_2[1810] = 60;
memory_2[1811] = 112;
memory_2[1812] = 62;
memory_2[1813] = 87;
memory_2[1814] = 101;
memory_2[1815] = 108;
memory_2[1816] = 99;
memory_2[1817] = 111;
memory_2[1818] = 109;
memory_2[1819] = 101;
memory_2[1820] = 32;
memory_2[1821] = 116;
memory_2[1822] = 111;
memory_2[1823] = 32;
memory_2[1824] = 116;
memory_2[1825] = 104;
memory_2[1826] = 101;
memory_2[1827] = 32;
memory_2[1828] = 115;
memory_2[1829] = 105;
memory_2[1830] = 109;
memory_2[1831] = 112;
memory_2[1832] = 108;
memory_2[1833] = 101;
memory_2[1834] = 32;
memory_2[1835] = 87;
memory_2[1836] = 101;
memory_2[1837] = 98;
memory_2[1838] = 32;
memory_2[1839] = 97;
memory_2[1840] = 112;
memory_2[1841] = 112;
memory_2[1842] = 108;
memory_2[1843] = 105;
memory_2[1844] = 99;
memory_2[1845] = 97;
memory_2[1846] = 116;
memory_2[1847] = 105;
memory_2[1848] = 111;
memory_2[1849] = 110;
memory_2[1850] = 32;
memory_2[1851] = 111;
memory_2[1852] = 110;
memory_2[1853] = 32;
memory_2[1854] = 70;
memory_2[1855] = 80;
memory_2[1856] = 71;
memory_2[1857] = 65;
memory_2[1858] = 32;
memory_2[1859] = 78;
memory_2[1860] = 101;
memory_2[1861] = 120;
memory_2[1862] = 121;
memory_2[1863] = 115;
memory_2[1864] = 51;
memory_2[1865] = 32;
memory_2[1866] = 98;
memory_2[1867] = 111;
memory_2[1868] = 97;
memory_2[1869] = 114;
memory_2[1870] = 100;
memory_2[1871] = 33;
memory_2[1872] = 60;
memory_2[1873] = 47;
memory_2[1874] = 112;
memory_2[1875] = 62;
memory_2[1876] = 60;
memory_2[1877] = 112;
memory_2[1878] = 62;
memory_2[1879] = 66;
memory_2[1880] = 121;
memory_2[1881] = 32;
memory_2[1882] = 65;
memory_2[1883] = 109;
memory_2[1884] = 101;
memory_2[1885] = 114;
memory_2[1886] = 32;
memory_2[1887] = 65;
memory_2[1888] = 108;
memory_2[1889] = 45;
memory_2[1890] = 67;
memory_2[1891] = 97;
memory_2[1892] = 110;
memory_2[1893] = 97;
memory_2[1894] = 97;
memory_2[1895] = 110;
memory_2[1896] = 44;
memory_2[1897] = 32;
memory_2[1898] = 74;
memory_2[1899] = 117;
memory_2[1900] = 110;
memory_2[1901] = 101;
memory_2[1902] = 32;
memory_2[1903] = 50;
memory_2[1904] = 48;
memory_2[1905] = 49;
memory_2[1906] = 52;
memory_2[1907] = 60;
memory_2[1908] = 47;
memory_2[1909] = 112;
memory_2[1910] = 62;
memory_2[1911] = 60;
memory_2[1912] = 102;
memory_2[1913] = 111;
memory_2[1914] = 114;
memory_2[1915] = 109;
memory_2[1916] = 62;
memory_2[1917] = 9;
memory_2[1918] = 60;
memory_2[1919] = 105;
memory_2[1920] = 110;
memory_2[1921] = 112;
memory_2[1922] = 117;
memory_2[1923] = 116;
memory_2[1924] = 32;
memory_2[1925] = 116;
memory_2[1926] = 121;
memory_2[1927] = 112;
memory_2[1928] = 101;
memory_2[1929] = 61;
memory_2[1930] = 34;
memory_2[1931] = 99;
memory_2[1932] = 104;
memory_2[1933] = 101;
memory_2[1934] = 99;
memory_2[1935] = 107;
memory_2[1936] = 98;
memory_2[1937] = 111;
memory_2[1938] = 120;
memory_2[1939] = 34;
memory_2[1940] = 32;
memory_2[1941] = 110;
memory_2[1942] = 97;
memory_2[1943] = 109;
memory_2[1944] = 101;
memory_2[1945] = 61;
memory_2[1946] = 34;
memory_2[1947] = 108;
memory_2[1948] = 101;
memory_2[1949] = 100;
memory_2[1950] = 49;
memory_2[1951] = 34;
memory_2[1952] = 32;
memory_2[1953] = 118;
memory_2[1954] = 97;
memory_2[1955] = 108;
memory_2[1956] = 117;
memory_2[1957] = 101;
memory_2[1958] = 61;
memory_2[1959] = 34;
memory_2[1960] = 65;
memory_2[1961] = 34;
memory_2[1962] = 62;
memory_2[1963] = 108;
memory_2[1964] = 101;
memory_2[1965] = 100;
memory_2[1966] = 32;
memory_2[1967] = 48;
memory_2[1968] = 60;
memory_2[1969] = 47;
memory_2[1970] = 105;
memory_2[1971] = 110;
memory_2[1972] = 112;
memory_2[1973] = 117;
memory_2[1974] = 116;
memory_2[1975] = 62;
memory_2[1976] = 9;
memory_2[1977] = 60;
memory_2[1978] = 105;
memory_2[1979] = 110;
memory_2[1980] = 112;
memory_2[1981] = 117;
memory_2[1982] = 116;
memory_2[1983] = 32;
memory_2[1984] = 116;
memory_2[1985] = 121;
memory_2[1986] = 112;
memory_2[1987] = 101;
memory_2[1988] = 61;
memory_2[1989] = 34;
memory_2[1990] = 99;
memory_2[1991] = 104;
memory_2[1992] = 101;
memory_2[1993] = 99;
memory_2[1994] = 107;
memory_2[1995] = 98;
memory_2[1996] = 111;
memory_2[1997] = 120;
memory_2[1998] = 34;
memory_2[1999] = 32;
memory_2[2000] = 110;
memory_2[2001] = 97;
memory_2[2002] = 109;
memory_2[2003] = 101;
memory_2[2004] = 61;
memory_2[2005] = 34;
memory_2[2006] = 108;
memory_2[2007] = 101;
memory_2[2008] = 100;
memory_2[2009] = 50;
memory_2[2010] = 34;
memory_2[2011] = 32;
memory_2[2012] = 118;
memory_2[2013] = 97;
memory_2[2014] = 108;
memory_2[2015] = 117;
memory_2[2016] = 101;
memory_2[2017] = 61;
memory_2[2018] = 34;
memory_2[2019] = 66;
memory_2[2020] = 34;
memory_2[2021] = 62;
memory_2[2022] = 108;
memory_2[2023] = 101;
memory_2[2024] = 100;
memory_2[2025] = 32;
memory_2[2026] = 49;
memory_2[2027] = 60;
memory_2[2028] = 47;
memory_2[2029] = 105;
memory_2[2030] = 110;
memory_2[2031] = 112;
memory_2[2032] = 117;
memory_2[2033] = 116;
memory_2[2034] = 62;
memory_2[2035] = 9;
memory_2[2036] = 60;
memory_2[2037] = 105;
memory_2[2038] = 110;
memory_2[2039] = 112;
memory_2[2040] = 117;
memory_2[2041] = 116;
memory_2[2042] = 32;
memory_2[2043] = 116;
memory_2[2044] = 121;
memory_2[2045] = 112;
memory_2[2046] = 101;
memory_2[2047] = 61;
memory_2[2048] = 34;
memory_2[2049] = 99;
memory_2[2050] = 104;
memory_2[2051] = 101;
memory_2[2052] = 99;
memory_2[2053] = 107;
memory_2[2054] = 98;
memory_2[2055] = 111;
memory_2[2056] = 120;
memory_2[2057] = 34;
memory_2[2058] = 32;
memory_2[2059] = 110;
memory_2[2060] = 97;
memory_2[2061] = 109;
memory_2[2062] = 101;
memory_2[2063] = 61;
memory_2[2064] = 34;
memory_2[2065] = 108;
memory_2[2066] = 101;
memory_2[2067] = 100;
memory_2[2068] = 51;
memory_2[2069] = 34;
memory_2[2070] = 32;
memory_2[2071] = 118;
memory_2[2072] = 97;
memory_2[2073] = 108;
memory_2[2074] = 117;
memory_2[2075] = 101;
memory_2[2076] = 61;
memory_2[2077] = 34;
memory_2[2078] = 67;
memory_2[2079] = 34;
memory_2[2080] = 62;
memory_2[2081] = 108;
memory_2[2082] = 101;
memory_2[2083] = 100;
memory_2[2084] = 32;
memory_2[2085] = 50;
memory_2[2086] = 60;
memory_2[2087] = 47;
memory_2[2088] = 105;
memory_2[2089] = 110;
memory_2[2090] = 112;
memory_2[2091] = 117;
memory_2[2092] = 116;
memory_2[2093] = 62;
memory_2[2094] = 9;
memory_2[2095] = 60;
memory_2[2096] = 105;
memory_2[2097] = 110;
memory_2[2098] = 112;
memory_2[2099] = 117;
memory_2[2100] = 116;
memory_2[2101] = 32;
memory_2[2102] = 116;
memory_2[2103] = 121;
memory_2[2104] = 112;
memory_2[2105] = 101;
memory_2[2106] = 61;
memory_2[2107] = 34;
memory_2[2108] = 99;
memory_2[2109] = 104;
memory_2[2110] = 101;
memory_2[2111] = 99;
memory_2[2112] = 107;
memory_2[2113] = 98;
memory_2[2114] = 111;
memory_2[2115] = 120;
memory_2[2116] = 34;
memory_2[2117] = 32;
memory_2[2118] = 110;
memory_2[2119] = 97;
memory_2[2120] = 109;
memory_2[2121] = 101;
memory_2[2122] = 61;
memory_2[2123] = 34;
memory_2[2124] = 108;
memory_2[2125] = 101;
memory_2[2126] = 100;
memory_2[2127] = 52;
memory_2[2128] = 34;
memory_2[2129] = 32;
memory_2[2130] = 118;
memory_2[2131] = 97;
memory_2[2132] = 108;
memory_2[2133] = 117;
memory_2[2134] = 101;
memory_2[2135] = 61;
memory_2[2136] = 34;
memory_2[2137] = 68;
memory_2[2138] = 34;
memory_2[2139] = 62;
memory_2[2140] = 108;
memory_2[2141] = 101;
memory_2[2142] = 100;
memory_2[2143] = 32;
memory_2[2144] = 51;
memory_2[2145] = 60;
memory_2[2146] = 47;
memory_2[2147] = 105;
memory_2[2148] = 110;
memory_2[2149] = 112;
memory_2[2150] = 117;
memory_2[2151] = 116;
memory_2[2152] = 62;
memory_2[2153] = 9;
memory_2[2154] = 60;
memory_2[2155] = 98;
memory_2[2156] = 117;
memory_2[2157] = 116;
memory_2[2158] = 116;
memory_2[2159] = 111;
memory_2[2160] = 110;
memory_2[2161] = 32;
memory_2[2162] = 116;
memory_2[2163] = 121;
memory_2[2164] = 112;
memory_2[2165] = 101;
memory_2[2166] = 61;
memory_2[2167] = 34;
memory_2[2168] = 115;
memory_2[2169] = 117;
memory_2[2170] = 109;
memory_2[2171] = 98;
memory_2[2172] = 105;
memory_2[2173] = 116;
memory_2[2174] = 34;
memory_2[2175] = 32;
memory_2[2176] = 118;
memory_2[2177] = 97;
memory_2[2178] = 108;
memory_2[2179] = 117;
memory_2[2180] = 101;
memory_2[2181] = 61;
memory_2[2182] = 34;
memory_2[2183] = 83;
memory_2[2184] = 117;
memory_2[2185] = 98;
memory_2[2186] = 109;
memory_2[2187] = 105;
memory_2[2188] = 116;
memory_2[2189] = 34;
memory_2[2190] = 62;
memory_2[2191] = 85;
memory_2[2192] = 112;
memory_2[2193] = 100;
memory_2[2194] = 97;
memory_2[2195] = 116;
memory_2[2196] = 101;
memory_2[2197] = 32;
memory_2[2198] = 76;
memory_2[2199] = 69;
memory_2[2200] = 68;
memory_2[2201] = 115;
memory_2[2202] = 60;
memory_2[2203] = 47;
memory_2[2204] = 98;
memory_2[2205] = 117;
memory_2[2206] = 116;
memory_2[2207] = 116;
memory_2[2208] = 111;
memory_2[2209] = 110;
memory_2[2210] = 62;
memory_2[2211] = 60;
memory_2[2212] = 47;
memory_2[2213] = 102;
memory_2[2214] = 111;
memory_2[2215] = 114;
memory_2[2216] = 109;
memory_2[2217] = 62;
memory_2[2218] = 60;
memory_2[2219] = 98;
memory_2[2220] = 114;
memory_2[2221] = 62;
memory_2[2222] = 60;
memory_2[2223] = 104;
memory_2[2224] = 51;
memory_2[2225] = 62;
memory_2[2226] = 83;
memory_2[2227] = 119;
memory_2[2228] = 105;
memory_2[2229] = 116;
memory_2[2230] = 99;
memory_2[2231] = 104;
memory_2[2232] = 32;
memory_2[2233] = 83;
memory_2[2234] = 116;
memory_2[2235] = 97;
memory_2[2236] = 116;
memory_2[2237] = 117;
memory_2[2238] = 115;
memory_2[2239] = 59;
memory_2[2240] = 32;
memory_2[2241] = 48;
memory_2[2242] = 48;
memory_2[2243] = 48;
memory_2[2244] = 48;
memory_2[2245] = 48;
memory_2[2246] = 48;
memory_2[2247] = 48;
memory_2[2248] = 48;
memory_2[2249] = 32;
memory_2[2250] = 32;
memory_2[2251] = 32;
memory_2[2252] = 60;
memory_2[2253] = 47;
memory_2[2254] = 104;
memory_2[2255] = 51;
memory_2[2256] = 62;
memory_2[2257] = 60;
memory_2[2258] = 104;
memory_2[2259] = 51;
memory_2[2260] = 62;
memory_2[2261] = 66;
memory_2[2262] = 117;
memory_2[2263] = 116;
memory_2[2264] = 116;
memory_2[2265] = 111;
memory_2[2266] = 110;
memory_2[2267] = 32;
memory_2[2268] = 83;
memory_2[2269] = 116;
memory_2[2270] = 97;
memory_2[2271] = 116;
memory_2[2272] = 117;
memory_2[2273] = 115;
memory_2[2274] = 59;
memory_2[2275] = 32;
memory_2[2276] = 48;
memory_2[2277] = 48;
memory_2[2278] = 48;
memory_2[2279] = 48;
memory_2[2280] = 32;
memory_2[2281] = 32;
memory_2[2282] = 32;
memory_2[2283] = 32;
memory_2[2284] = 60;
memory_2[2285] = 47;
memory_2[2286] = 104;
memory_2[2287] = 51;
memory_2[2288] = 62;
memory_2[2289] = 60;
memory_2[2290] = 112;
memory_2[2291] = 62;
memory_2[2292] = 84;
memory_2[2293] = 104;
memory_2[2294] = 105;
memory_2[2295] = 115;
memory_2[2296] = 32;
memory_2[2297] = 32;
memory_2[2298] = 32;
memory_2[2299] = 32;
memory_2[2300] = 32;
memory_2[2301] = 32;
memory_2[2302] = 32;
memory_2[2303] = 32;
memory_2[2304] = 60;
memory_2[2305] = 97;
memory_2[2306] = 32;
memory_2[2307] = 104;
memory_2[2308] = 114;
memory_2[2309] = 101;
memory_2[2310] = 102;
memory_2[2311] = 61;
memory_2[2312] = 34;
memory_2[2313] = 104;
memory_2[2314] = 116;
memory_2[2315] = 116;
memory_2[2316] = 112;
memory_2[2317] = 115;
memory_2[2318] = 58;
memory_2[2319] = 92;
memory_2[2320] = 47;
memory_2[2321] = 92;
memory_2[2322] = 47;
memory_2[2323] = 103;
memory_2[2324] = 105;
memory_2[2325] = 116;
memory_2[2326] = 104;
memory_2[2327] = 117;
memory_2[2328] = 98;
memory_2[2329] = 46;
memory_2[2330] = 99;
memory_2[2331] = 111;
memory_2[2332] = 109;
memory_2[2333] = 92;
memory_2[2334] = 47;
memory_2[2335] = 97;
memory_2[2336] = 109;
memory_2[2337] = 101;
memory_2[2338] = 114;
memory_2[2339] = 99;
memory_2[2340] = 92;
memory_2[2341] = 47;
memory_2[2342] = 112;
memory_2[2343] = 104;
memory_2[2344] = 105;
memory_2[2345] = 109;
memory_2[2346] = 105;
memory_2[2347] = 105;
memory_2[2348] = 34;
memory_2[2349] = 62;
memory_2[2350] = 112;
memory_2[2351] = 114;
memory_2[2352] = 111;
memory_2[2353] = 106;
memory_2[2354] = 101;
memory_2[2355] = 99;
memory_2[2356] = 116;
memory_2[2357] = 60;
memory_2[2358] = 47;
memory_2[2359] = 97;
memory_2[2360] = 62;
memory_2[2361] = 32;
memory_2[2362] = 105;
memory_2[2363] = 115;
memory_2[2364] = 32;
memory_2[2365] = 112;
memory_2[2366] = 111;
memory_2[2367] = 119;
memory_2[2368] = 101;
memory_2[2369] = 114;
memory_2[2370] = 101;
memory_2[2371] = 100;
memory_2[2372] = 32;
memory_2[2373] = 98;
memory_2[2374] = 121;
memory_2[2375] = 32;
memory_2[2376] = 60;
memory_2[2377] = 97;
memory_2[2378] = 32;
memory_2[2379] = 104;
memory_2[2380] = 114;
memory_2[2381] = 101;
memory_2[2382] = 102;
memory_2[2383] = 61;
memory_2[2384] = 34;
memory_2[2385] = 104;
memory_2[2386] = 116;
memory_2[2387] = 116;
memory_2[2388] = 112;
memory_2[2389] = 58;
memory_2[2390] = 47;
memory_2[2391] = 47;
memory_2[2392] = 112;
memory_2[2393] = 121;
memory_2[2394] = 97;
memory_2[2395] = 110;
memory_2[2396] = 100;
memory_2[2397] = 99;
memory_2[2398] = 104;
memory_2[2399] = 105;
memory_2[2400] = 112;
memory_2[2401] = 115;
memory_2[2402] = 46;
memory_2[2403] = 111;
memory_2[2404] = 114;
memory_2[2405] = 103;
memory_2[2406] = 34;
memory_2[2407] = 62;
memory_2[2408] = 67;
memory_2[2409] = 104;
memory_2[2410] = 105;
memory_2[2411] = 112;
memory_2[2412] = 115;
memory_2[2413] = 45;
memory_2[2414] = 50;
memory_2[2415] = 46;
memory_2[2416] = 48;
memory_2[2417] = 60;
memory_2[2418] = 47;
memory_2[2419] = 97;
memory_2[2420] = 62;
memory_2[2421] = 46;
memory_2[2422] = 60;
memory_2[2423] = 98;
memory_2[2424] = 114;
memory_2[2425] = 62;
memory_2[2426] = 65;
memory_2[2427] = 109;
memory_2[2428] = 101;
memory_2[2429] = 114;
memory_2[2430] = 32;
memory_2[2431] = 65;
memory_2[2432] = 108;
memory_2[2433] = 45;
memory_2[2434] = 67;
memory_2[2435] = 97;
memory_2[2436] = 110;
memory_2[2437] = 97;
memory_2[2438] = 97;
memory_2[2439] = 110;
memory_2[2440] = 60;
memory_2[2441] = 98;
memory_2[2442] = 114;
memory_2[2443] = 62;
memory_2[2444] = 60;
memory_2[2445] = 105;
memory_2[2446] = 109;
memory_2[2447] = 103;
memory_2[2448] = 32;
memory_2[2449] = 115;
memory_2[2450] = 114;
memory_2[2451] = 99;
memory_2[2452] = 61;
memory_2[2453] = 34;
memory_2[2454] = 100;
memory_2[2455] = 97;
memory_2[2456] = 116;
memory_2[2457] = 97;
memory_2[2458] = 58;
memory_2[2459] = 105;
memory_2[2460] = 109;
memory_2[2461] = 97;
memory_2[2462] = 103;
memory_2[2463] = 101;
memory_2[2464] = 47;
memory_2[2465] = 103;
memory_2[2466] = 105;
memory_2[2467] = 102;
memory_2[2468] = 59;
memory_2[2469] = 98;
memory_2[2470] = 97;
memory_2[2471] = 115;
memory_2[2472] = 101;
memory_2[2473] = 54;
memory_2[2474] = 52;
memory_2[2475] = 44;
memory_2[2476] = 82;
memory_2[2477] = 48;
memory_2[2478] = 108;
memory_2[2479] = 71;
memory_2[2480] = 79;
memory_2[2481] = 68;
memory_2[2482] = 108;
memory_2[2483] = 104;
memory_2[2484] = 70;
memory_2[2485] = 65;
memory_2[2486] = 65;
memory_2[2487] = 100;
memory_2[2488] = 65;
memory_2[2489] = 77;
memory_2[2490] = 73;
memory_2[2491] = 71;
memory_2[2492] = 65;
memory_2[2493] = 65;
memory_2[2494] = 65;
memory_2[2495] = 65;
memory_2[2496] = 65;
memory_2[2497] = 73;
memory_2[2498] = 65;
memory_2[2499] = 65;
memory_2[2500] = 65;
memory_2[2501] = 73;
memory_2[2502] = 67;
memory_2[2503] = 65;
memory_2[2504] = 65;
memory_2[2505] = 73;
memory_2[2506] = 67;
memory_2[2507] = 65;
memory_2[2508] = 47;
memory_2[2509] = 47;
memory_2[2510] = 43;
memory_2[2511] = 65;
memory_2[2512] = 65;
memory_2[2513] = 80;
memory_2[2514] = 43;
memory_2[2515] = 65;
memory_2[2516] = 103;
memory_2[2517] = 80;
memory_2[2518] = 47;
memory_2[2519] = 47;
memory_2[2520] = 47;
memory_2[2521] = 47;
memory_2[2522] = 47;
memory_2[2523] = 47;
memory_2[2524] = 47;
memory_2[2525] = 121;
memory_2[2526] = 72;
memory_2[2527] = 43;
memory_2[2528] = 71;
memory_2[2529] = 107;
memory_2[2530] = 78;
memory_2[2531] = 121;
memory_2[2532] = 90;
memory_2[2533] = 87;
memory_2[2534] = 70;
memory_2[2535] = 48;
memory_2[2536] = 90;
memory_2[2537] = 87;
memory_2[2538] = 81;
memory_2[2539] = 103;
memory_2[2540] = 100;
memory_2[2541] = 50;
memory_2[2542] = 108;
memory_2[2543] = 48;
memory_2[2544] = 97;
memory_2[2545] = 67;
memory_2[2546] = 66;
memory_2[2547] = 72;
memory_2[2548] = 83;
memory_2[2549] = 85;
memory_2[2550] = 49;
memory_2[2551] = 81;
memory_2[2552] = 73;
memory_2[2553] = 71;
memory_2[2554] = 57;
memory_2[2555] = 117;
memory_2[2556] = 73;
memory_2[2557] = 71;
memory_2[2558] = 69;
memory_2[2559] = 103;
memory_2[2560] = 84;
memory_2[2561] = 87;
memory_2[2562] = 70;
memory_2[2563] = 106;
memory_2[2564] = 65;
memory_2[2565] = 67;
memory_2[2566] = 72;
memory_2[2567] = 53;
memory_2[2568] = 66;
memory_2[2569] = 65;
memory_2[2570] = 69;
memory_2[2571] = 75;
memory_2[2572] = 65;
memory_2[2573] = 65;
memory_2[2574] = 99;
memory_2[2575] = 65;
memory_2[2576] = 76;
memory_2[2577] = 65;
memory_2[2578] = 65;
memory_2[2579] = 65;
memory_2[2580] = 65;
memory_2[2581] = 65;
memory_2[2582] = 65;
memory_2[2583] = 85;
memory_2[2584] = 65;
memory_2[2585] = 66;
memory_2[2586] = 48;
memory_2[2587] = 65;
memory_2[2588] = 65;
memory_2[2589] = 65;
memory_2[2590] = 79;
memory_2[2591] = 100;
memory_2[2592] = 71;
memory_2[2593] = 71;
memory_2[2594] = 114;
memory_2[2595] = 99;
memory_2[2596] = 78;
memory_2[2597] = 108;
memory_2[2598] = 66;
memory_2[2599] = 73;
memory_2[2600] = 65;
memory_2[2601] = 83;
memory_2[2602] = 112;
memory_2[2603] = 90;
memory_2[2604] = 68;
memory_2[2605] = 77;
memory_2[2606] = 73;
memory_2[2607] = 119;
memory_2[2608] = 79;
memory_2[2609] = 55;
memory_2[2610] = 49;
memory_2[2611] = 66;
memory_2[2612] = 111;
memory_2[2613] = 119;
memory_2[2614] = 50;
memory_2[2615] = 99;
memory_2[2616] = 74;
memory_2[2617] = 119;
memory_2[2618] = 72;
memory_2[2619] = 71;
memory_2[2620] = 115;
memory_2[2621] = 106;
memory_2[2622] = 69;
memory_2[2623] = 69;
memory_2[2624] = 119;
memory_2[2625] = 90;
memory_2[2626] = 81;
memory_2[2627] = 84;
memory_2[2628] = 111;
memory_2[2629] = 77;
memory_2[2630] = 121;
memory_2[2631] = 104;
memory_2[2632] = 89;
memory_2[2633] = 56;
memory_2[2634] = 99;
memory_2[2635] = 48;
memory_2[2636] = 90;
memory_2[2637] = 106;
memory_2[2638] = 100;
memory_2[2639] = 120;
memory_2[2640] = 66;
memory_2[2641] = 43;
memory_2[2642] = 50;
memory_2[2643] = 79;
memory_2[2644] = 119;
memory_2[2645] = 97;
memory_2[2646] = 107;
memory_2[2647] = 68;
memory_2[2648] = 116;
memory_2[2649] = 66;
memory_2[2650] = 71;
memory_2[2651] = 71;
memory_2[2652] = 107;
memory_2[2653] = 54;
memory_2[2654] = 76;
memory_2[2655] = 106;
memory_2[2656] = 83;
memory_2[2657] = 67;
memory_2[2658] = 69;
memory_2[2659] = 113;
memory_2[2660] = 87;
memory_2[2661] = 85;
memory_2[2662] = 106;
memory_2[2663] = 74;
memory_2[2664] = 69;
memory_2[2665] = 57;
memory_2[2666] = 112;
memory_2[2667] = 77;
memory_2[2668] = 77;
memory_2[2669] = 103;
memory_2[2670] = 114;
memory_2[2671] = 89;
memory_2[2672] = 98;
memory_2[2673] = 74;
memory_2[2674] = 89;
memory_2[2675] = 74;
memory_2[2676] = 69;
memory_2[2677] = 67;
memory_2[2678] = 103;
memory_2[2679] = 69;
memory_2[2680] = 106;
memory_2[2681] = 86;
memory_2[2682] = 97;
memory_2[2683] = 103;
memory_2[2684] = 66;
memory_2[2685] = 102;
memory_2[2686] = 112;
memory_2[2687] = 43;
memory_2[2688] = 88;
memory_2[2689] = 103;
memory_2[2690] = 48;
memory_2[2691] = 97;
memory_2[2692] = 119;
memory_2[2693] = 47;
memory_2[2694] = 83;
memory_2[2695] = 98;
memory_2[2696] = 53;
memory_2[2697] = 103;
memory_2[2698] = 76;
memory_2[2699] = 116;
memory_2[2700] = 53;
memory_2[2701] = 122;
memory_2[2702] = 117;
memory_2[2703] = 117;
memory_2[2704] = 114;
memory_2[2705] = 75;
memory_2[2706] = 88;
memory_2[2707] = 71;
memory_2[2708] = 89;
memory_2[2709] = 75;
memory_2[2710] = 80;
memory_2[2711] = 114;
memory_2[2712] = 84;
memory_2[2713] = 99;
memory_2[2714] = 115;
memory_2[2715] = 118;
memory_2[2716] = 57;
memory_2[2717] = 51;
memory_2[2718] = 119;
memory_2[2719] = 75;
memory_2[2720] = 81;
memory_2[2721] = 110;
memory_2[2722] = 52;
memory_2[2723] = 71;
memory_2[2724] = 90;
memory_2[2725] = 67;
memory_2[2726] = 66;
memory_2[2727] = 101;
memory_2[2728] = 67;
memory_2[2729] = 109;
memory_2[2730] = 75;
memory_2[2731] = 68;
memory_2[2732] = 82;
memory_2[2733] = 87;
memory_2[2734] = 74;
memory_2[2735] = 102;
memory_2[2736] = 90;
memory_2[2737] = 73;
memory_2[2738] = 116;
memory_2[2739] = 65;
memory_2[2740] = 106;
memory_2[2741] = 82;
memory_2[2742] = 120;
memory_2[2743] = 107;
memory_2[2744] = 86;
memory_2[2745] = 106;
memory_2[2746] = 116;
memory_2[2747] = 105;
memory_2[2748] = 69;
memory_2[2749] = 109;
memory_2[2750] = 78;
memory_2[2751] = 105;
memory_2[2752] = 89;
memory_2[2753] = 83;
memory_2[2754] = 49;
memory_2[2755] = 116;
memory_2[2756] = 108;
memory_2[2757] = 119;
memory_2[2758] = 75;
memory_2[2759] = 71;
memory_2[2760] = 104;
memory_2[2761] = 73;
memory_2[2762] = 86;
memory_2[2763] = 109;
memory_2[2764] = 69;
memory_2[2765] = 122;
memory_2[2766] = 79;
memory_2[2767] = 88;
memory_2[2768] = 82;
memory_2[2769] = 113;
memory_2[2770] = 79;
memory_2[2771] = 89;
memory_2[2772] = 105;
memory_2[2773] = 82;
memory_2[2774] = 101;
memory_2[2775] = 104;
memory_2[2776] = 104;
memory_2[2777] = 97;
memory_2[2778] = 115;
memory_2[2779] = 109;
memory_2[2780] = 77;
memory_2[2781] = 119;
memory_2[2782] = 74;
memory_2[2783] = 48;
memory_2[2784] = 76;
memory_2[2785] = 67;
memory_2[2786] = 87;
memory_2[2787] = 68;
memory_2[2788] = 70;
memory_2[2789] = 86;
memory_2[2790] = 50;
memory_2[2791] = 120;
memory_2[2792] = 65;
memory_2[2793] = 53;
memory_2[2794] = 97;
memory_2[2795] = 48;
memory_2[2796] = 74;
memory_2[2797] = 120;
memory_2[2798] = 85;
memory_2[2799] = 67;
memory_2[2800] = 67;
memory_2[2801] = 81;
memory_2[2802] = 65;
memory_2[2803] = 55;
memory_2[2804] = 34;
memory_2[2805] = 32;
memory_2[2806] = 97;
memory_2[2807] = 108;
memory_2[2808] = 116;
memory_2[2809] = 61;
memory_2[2810] = 34;
memory_2[2811] = 65;
memory_2[2812] = 77;
memory_2[2813] = 57;
memory_2[2814] = 46;
memory_2[2815] = 103;
memory_2[2816] = 105;
memory_2[2817] = 102;
memory_2[2818] = 34;
memory_2[2819] = 32;
memory_2[2820] = 87;
memory_2[2821] = 73;
memory_2[2822] = 68;
memory_2[2823] = 84;
memory_2[2824] = 72;
memory_2[2825] = 61;
memory_2[2826] = 54;
memory_2[2827] = 48;
memory_2[2828] = 32;
memory_2[2829] = 72;
memory_2[2830] = 69;
memory_2[2831] = 73;
memory_2[2832] = 71;
memory_2[2833] = 72;
memory_2[2834] = 84;
memory_2[2835] = 61;
memory_2[2836] = 57;
memory_2[2837] = 48;
memory_2[2838] = 47;
memory_2[2839] = 62;
memory_2[2840] = 60;
memory_2[2841] = 47;
memory_2[2842] = 112;
memory_2[2843] = 62;
memory_2[2844] = 60;
memory_2[2845] = 47;
memory_2[2846] = 98;
memory_2[2847] = 111;
memory_2[2848] = 100;
memory_2[2849] = 121;
memory_2[2850] = 62;
memory_2[2851] = 60;
memory_2[2852] = 47;
memory_2[2853] = 104;
memory_2[2854] = 116;
memory_2[2855] = 109;
memory_2[2856] = 108;
memory_2[2857] = 62;
memory_2[2858] = 0;
memory_2[2859] = 87;
memory_2[2860] = 101;
memory_2[2861] = 108;
memory_2[2862] = 99;
memory_2[2863] = 111;
memory_2[2864] = 109;
memory_2[2865] = 101;
memory_2[2866] = 32;
memory_2[2867] = 116;
memory_2[2868] = 111;
memory_2[2869] = 32;
memory_2[2870] = 116;
memory_2[2871] = 104;
memory_2[2872] = 101;
memory_2[2873] = 32;
memory_2[2874] = 78;
memory_2[2875] = 101;
memory_2[2876] = 120;
memory_2[2877] = 121;
memory_2[2878] = 115;
memory_2[2879] = 51;
memory_2[2880] = 32;
memory_2[2881] = 67;
memory_2[2882] = 104;
memory_2[2883] = 105;
memory_2[2884] = 112;
memory_2[2885] = 115;
memory_2[2886] = 45;
memory_2[2887] = 50;
memory_2[2888] = 46;
memory_2[2889] = 48;
memory_2[2890] = 32;
memory_2[2891] = 100;
memory_2[2892] = 101;
memory_2[2893] = 109;
memory_2[2894] = 111;
memory_2[2895] = 33;
memory_2[2896] = 10;
memory_2[2897] = 0;
memory_2[2898] = 67;
memory_2[2899] = 111;
memory_2[2900] = 110;
memory_2[2901] = 110;
memory_2[2902] = 101;
memory_2[2903] = 99;
memory_2[2904] = 116;
memory_2[2905] = 32;
memory_2[2906] = 121;
memory_2[2907] = 111;
memory_2[2908] = 117;
memory_2[2909] = 114;
memory_2[2910] = 32;
memory_2[2911] = 87;
memory_2[2912] = 101;
memory_2[2913] = 98;
memory_2[2914] = 32;
memory_2[2915] = 98;
memory_2[2916] = 114;
memory_2[2917] = 111;
memory_2[2918] = 119;
memory_2[2919] = 115;
memory_2[2920] = 101;
memory_2[2921] = 114;
memory_2[2922] = 32;
memory_2[2923] = 116;
memory_2[2924] = 111;
memory_2[2925] = 32;
memory_2[2926] = 49;
memory_2[2927] = 57;
memory_2[2928] = 50;
memory_2[2929] = 46;
memory_2[2930] = 49;
memory_2[2931] = 54;
memory_2[2932] = 56;
memory_2[2933] = 46;
memory_2[2934] = 48;
memory_2[2935] = 46;
memory_2[2936] = 49;
memory_2[2937] = 49;
memory_2[2938] = 57;
memory_2[2939] = 10;
memory_2[2940] = 0;
end
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'literal'}
// 1 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_and_link'}
// 2 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'stop'}
// 3 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'move'}
// 4 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'nop'}
// 5 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'socket', 'op': 'write'}
// 6 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'jmp_to_reg'}
// 7 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'rs232_tx', 'op': 'write'}
// 8 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '+'}
// 9 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_request'}
// 10 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_wait'}
// 11 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read'}
// 12 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_false'}
// 13 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '+'}
// 14 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'goto'}
// 15 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>='}
// 16 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '-'}
// 17 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '|'}
// 18 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '|'}
// 19 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '>='}
// 20 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': '-'}
// 21 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '<<'}
// 22 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '&'}
// 23 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '=='}
// 24 {'float': False, 'literal': True, 'right': False, 'unsigned': True, 'op': '|'}
// 25 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>'}
// 26 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<'}
// 27 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<'}
// 28 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '=='}
// 29 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '+'}
// 30 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'read'}
// 31 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>>'}
// 32 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '&'}
// 33 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_write'}
// 34 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_true'}
// 35 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '!='}
// 36 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'leds', 'op': 'write'}
// 37 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'switches', 'op': 'read'}
// 38 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '~'}
// 39 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '+'}
// 40 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'buttons', 'op': 'read'}
// 41 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'rs232_rx', 'op': 'read'}
// Intructions
// ===========
initial
begin
instructions[0] = {6'd0, 7'd63, 7'd0, 32'd1};//{'dest': 63, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1] = {6'd0, 7'd64, 7'd0, 32'd0};//{'dest': 64, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2] = {6'd1, 7'd23, 7'd0, 32'd930};//{'dest': 23, 'label': 930, 'op': 'jmp_and_link'}
instructions[3] = {6'd2, 7'd0, 7'd0, 32'd0};//{'op': 'stop'}
instructions[4] = {6'd3, 7'd37, 7'd51, 32'd0};//{'dest': 37, 'src': 51, 'op': 'move'}
instructions[5] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[6] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[7] = {6'd5, 7'd0, 7'd37, 32'd0};//{'src': 37, 'output': 'socket', 'op': 'write'}
instructions[8] = {6'd6, 7'd0, 7'd50, 32'd0};//{'src': 50, 'op': 'jmp_to_reg'}
instructions[9] = {6'd3, 7'd37, 7'd53, 32'd0};//{'dest': 37, 'src': 53, 'op': 'move'}
instructions[10] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[11] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[12] = {6'd7, 7'd0, 7'd37, 32'd0};//{'src': 37, 'output': 'rs232_tx', 'op': 'write'}
instructions[13] = {6'd6, 7'd0, 7'd52, 32'd0};//{'src': 52, 'op': 'jmp_to_reg'}
instructions[14] = {6'd0, 7'd56, 7'd0, 32'd0};//{'dest': 56, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[15] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[16] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[17] = {6'd3, 7'd38, 7'd56, 32'd0};//{'dest': 38, 'src': 56, 'op': 'move'}
instructions[18] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[19] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[20] = {6'd8, 7'd39, 7'd38, 32'd55};//{'dest': 39, 'src': 38, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[21] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[22] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[23] = {6'd9, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208806720, 'op': 'memory_read_request'}
instructions[24] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[25] = {6'd10, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208806720, 'op': 'memory_read_wait'}
instructions[26] = {6'd11, 7'd37, 7'd39, 32'd0};//{'dest': 37, 'src': 39, 'sequence': 140361208806720, 'element_size': 2, 'op': 'memory_read'}
instructions[27] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[28] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[29] = {6'd12, 7'd0, 7'd37, 32'd47};//{'src': 37, 'label': 47, 'op': 'jmp_if_false'}
instructions[30] = {6'd3, 7'd39, 7'd56, 32'd0};//{'dest': 39, 'src': 56, 'op': 'move'}
instructions[31] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[32] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[33] = {6'd8, 7'd41, 7'd39, 32'd55};//{'dest': 41, 'src': 39, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[34] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[35] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[36] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208827776, 'op': 'memory_read_request'}
instructions[37] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[38] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208827776, 'op': 'memory_read_wait'}
instructions[39] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361208827776, 'element_size': 2, 'op': 'memory_read'}
instructions[40] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[41] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[42] = {6'd3, 7'd53, 7'd38, 32'd0};//{'dest': 53, 'src': 38, 'op': 'move'}
instructions[43] = {6'd1, 7'd52, 7'd0, 32'd9};//{'dest': 52, 'label': 9, 'op': 'jmp_and_link'}
instructions[44] = {6'd3, 7'd37, 7'd56, 32'd0};//{'dest': 37, 'src': 56, 'op': 'move'}
instructions[45] = {6'd13, 7'd56, 7'd56, 32'd1};//{'src': 56, 'right': 1, 'dest': 56, 'signed': False, 'op': '+', 'size': 2}
instructions[46] = {6'd14, 7'd0, 7'd0, 32'd48};//{'label': 48, 'op': 'goto'}
instructions[47] = {6'd14, 7'd0, 7'd0, 32'd49};//{'label': 49, 'op': 'goto'}
instructions[48] = {6'd14, 7'd0, 7'd0, 32'd15};//{'label': 15, 'op': 'goto'}
instructions[49] = {6'd6, 7'd0, 7'd54, 32'd0};//{'src': 54, 'op': 'jmp_to_reg'}
instructions[50] = {6'd0, 7'd59, 7'd0, 32'd0};//{'dest': 59, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[51] = {6'd0, 7'd60, 7'd0, 32'd0};//{'dest': 60, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[52] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[53] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[54] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[55] = {6'd3, 7'd59, 7'd37, 32'd0};//{'dest': 59, 'src': 37, 'op': 'move'}
instructions[56] = {6'd3, 7'd38, 7'd58, 32'd0};//{'dest': 38, 'src': 58, 'op': 'move'}
instructions[57] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[58] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[59] = {6'd15, 7'd37, 7'd38, 32'd10000};//{'src': 38, 'right': 10000, 'dest': 37, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[60] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[61] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[62] = {6'd12, 7'd0, 7'd37, 32'd78};//{'src': 37, 'label': 78, 'op': 'jmp_if_false'}
instructions[63] = {6'd3, 7'd38, 7'd58, 32'd0};//{'dest': 38, 'src': 58, 'op': 'move'}
instructions[64] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[65] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[66] = {6'd16, 7'd37, 7'd38, 32'd10000};//{'src': 38, 'right': 10000, 'dest': 37, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[67] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[68] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[69] = {6'd3, 7'd58, 7'd37, 32'd0};//{'dest': 58, 'src': 37, 'op': 'move'}
instructions[70] = {6'd3, 7'd38, 7'd59, 32'd0};//{'dest': 38, 'src': 59, 'op': 'move'}
instructions[71] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[72] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[73] = {6'd13, 7'd37, 7'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 37, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[74] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[75] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[76] = {6'd3, 7'd59, 7'd37, 32'd0};//{'dest': 59, 'src': 37, 'op': 'move'}
instructions[77] = {6'd14, 7'd0, 7'd0, 32'd79};//{'label': 79, 'op': 'goto'}
instructions[78] = {6'd14, 7'd0, 7'd0, 32'd80};//{'label': 80, 'op': 'goto'}
instructions[79] = {6'd14, 7'd0, 7'd0, 32'd56};//{'label': 56, 'op': 'goto'}
instructions[80] = {6'd3, 7'd38, 7'd59, 32'd0};//{'dest': 38, 'src': 59, 'op': 'move'}
instructions[81] = {6'd3, 7'd39, 7'd60, 32'd0};//{'dest': 39, 'src': 60, 'op': 'move'}
instructions[82] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[83] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[84] = {6'd17, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[85] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[86] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[87] = {6'd12, 7'd0, 7'd37, 32'd101};//{'src': 37, 'label': 101, 'op': 'jmp_if_false'}
instructions[88] = {6'd3, 7'd39, 7'd59, 32'd0};//{'dest': 39, 'src': 59, 'op': 'move'}
instructions[89] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[90] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[91] = {6'd18, 7'd38, 7'd39, 32'd48};//{'src': 39, 'right': 48, 'dest': 38, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[92] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[93] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[94] = {6'd3, 7'd53, 7'd38, 32'd0};//{'dest': 53, 'src': 38, 'op': 'move'}
instructions[95] = {6'd1, 7'd52, 7'd0, 32'd9};//{'dest': 52, 'label': 9, 'op': 'jmp_and_link'}
instructions[96] = {6'd0, 7'd37, 7'd0, 32'd1};//{'dest': 37, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[97] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[98] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[99] = {6'd3, 7'd60, 7'd37, 32'd0};//{'dest': 60, 'src': 37, 'op': 'move'}
instructions[100] = {6'd14, 7'd0, 7'd0, 32'd101};//{'label': 101, 'op': 'goto'}
instructions[101] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[102] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[103] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[104] = {6'd3, 7'd59, 7'd37, 32'd0};//{'dest': 59, 'src': 37, 'op': 'move'}
instructions[105] = {6'd3, 7'd38, 7'd58, 32'd0};//{'dest': 38, 'src': 58, 'op': 'move'}
instructions[106] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[107] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[108] = {6'd15, 7'd37, 7'd38, 32'd1000};//{'src': 38, 'right': 1000, 'dest': 37, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[109] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[110] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[111] = {6'd12, 7'd0, 7'd37, 32'd127};//{'src': 37, 'label': 127, 'op': 'jmp_if_false'}
instructions[112] = {6'd3, 7'd38, 7'd58, 32'd0};//{'dest': 38, 'src': 58, 'op': 'move'}
instructions[113] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[114] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[115] = {6'd16, 7'd37, 7'd38, 32'd1000};//{'src': 38, 'right': 1000, 'dest': 37, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[116] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[117] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[118] = {6'd3, 7'd58, 7'd37, 32'd0};//{'dest': 58, 'src': 37, 'op': 'move'}
instructions[119] = {6'd3, 7'd38, 7'd59, 32'd0};//{'dest': 38, 'src': 59, 'op': 'move'}
instructions[120] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[121] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[122] = {6'd13, 7'd37, 7'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 37, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[123] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[124] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[125] = {6'd3, 7'd59, 7'd37, 32'd0};//{'dest': 59, 'src': 37, 'op': 'move'}
instructions[126] = {6'd14, 7'd0, 7'd0, 32'd128};//{'label': 128, 'op': 'goto'}
instructions[127] = {6'd14, 7'd0, 7'd0, 32'd129};//{'label': 129, 'op': 'goto'}
instructions[128] = {6'd14, 7'd0, 7'd0, 32'd105};//{'label': 105, 'op': 'goto'}
instructions[129] = {6'd3, 7'd38, 7'd59, 32'd0};//{'dest': 38, 'src': 59, 'op': 'move'}
instructions[130] = {6'd3, 7'd39, 7'd60, 32'd0};//{'dest': 39, 'src': 60, 'op': 'move'}
instructions[131] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[132] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[133] = {6'd17, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[134] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[135] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[136] = {6'd12, 7'd0, 7'd37, 32'd150};//{'src': 37, 'label': 150, 'op': 'jmp_if_false'}
instructions[137] = {6'd3, 7'd39, 7'd59, 32'd0};//{'dest': 39, 'src': 59, 'op': 'move'}
instructions[138] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[139] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[140] = {6'd18, 7'd38, 7'd39, 32'd48};//{'src': 39, 'right': 48, 'dest': 38, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[141] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[142] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[143] = {6'd3, 7'd53, 7'd38, 32'd0};//{'dest': 53, 'src': 38, 'op': 'move'}
instructions[144] = {6'd1, 7'd52, 7'd0, 32'd9};//{'dest': 52, 'label': 9, 'op': 'jmp_and_link'}
instructions[145] = {6'd0, 7'd37, 7'd0, 32'd1};//{'dest': 37, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[146] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[147] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[148] = {6'd3, 7'd60, 7'd37, 32'd0};//{'dest': 60, 'src': 37, 'op': 'move'}
instructions[149] = {6'd14, 7'd0, 7'd0, 32'd150};//{'label': 150, 'op': 'goto'}
instructions[150] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[151] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[152] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[153] = {6'd3, 7'd59, 7'd37, 32'd0};//{'dest': 59, 'src': 37, 'op': 'move'}
instructions[154] = {6'd3, 7'd38, 7'd58, 32'd0};//{'dest': 38, 'src': 58, 'op': 'move'}
instructions[155] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[156] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[157] = {6'd15, 7'd37, 7'd38, 32'd100};//{'src': 38, 'right': 100, 'dest': 37, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[158] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[159] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[160] = {6'd12, 7'd0, 7'd37, 32'd176};//{'src': 37, 'label': 176, 'op': 'jmp_if_false'}
instructions[161] = {6'd3, 7'd38, 7'd58, 32'd0};//{'dest': 38, 'src': 58, 'op': 'move'}
instructions[162] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[163] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[164] = {6'd16, 7'd37, 7'd38, 32'd100};//{'src': 38, 'right': 100, 'dest': 37, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[165] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[166] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[167] = {6'd3, 7'd58, 7'd37, 32'd0};//{'dest': 58, 'src': 37, 'op': 'move'}
instructions[168] = {6'd3, 7'd38, 7'd59, 32'd0};//{'dest': 38, 'src': 59, 'op': 'move'}
instructions[169] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[170] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[171] = {6'd13, 7'd37, 7'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 37, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[172] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[173] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[174] = {6'd3, 7'd59, 7'd37, 32'd0};//{'dest': 59, 'src': 37, 'op': 'move'}
instructions[175] = {6'd14, 7'd0, 7'd0, 32'd177};//{'label': 177, 'op': 'goto'}
instructions[176] = {6'd14, 7'd0, 7'd0, 32'd178};//{'label': 178, 'op': 'goto'}
instructions[177] = {6'd14, 7'd0, 7'd0, 32'd154};//{'label': 154, 'op': 'goto'}
instructions[178] = {6'd3, 7'd38, 7'd59, 32'd0};//{'dest': 38, 'src': 59, 'op': 'move'}
instructions[179] = {6'd3, 7'd39, 7'd60, 32'd0};//{'dest': 39, 'src': 60, 'op': 'move'}
instructions[180] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[181] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[182] = {6'd17, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[183] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[184] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[185] = {6'd12, 7'd0, 7'd37, 32'd199};//{'src': 37, 'label': 199, 'op': 'jmp_if_false'}
instructions[186] = {6'd3, 7'd39, 7'd59, 32'd0};//{'dest': 39, 'src': 59, 'op': 'move'}
instructions[187] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[188] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[189] = {6'd18, 7'd38, 7'd39, 32'd48};//{'src': 39, 'right': 48, 'dest': 38, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[190] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[191] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[192] = {6'd3, 7'd53, 7'd38, 32'd0};//{'dest': 53, 'src': 38, 'op': 'move'}
instructions[193] = {6'd1, 7'd52, 7'd0, 32'd9};//{'dest': 52, 'label': 9, 'op': 'jmp_and_link'}
instructions[194] = {6'd0, 7'd37, 7'd0, 32'd1};//{'dest': 37, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[195] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[196] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[197] = {6'd3, 7'd60, 7'd37, 32'd0};//{'dest': 60, 'src': 37, 'op': 'move'}
instructions[198] = {6'd14, 7'd0, 7'd0, 32'd199};//{'label': 199, 'op': 'goto'}
instructions[199] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[200] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[201] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[202] = {6'd3, 7'd59, 7'd37, 32'd0};//{'dest': 59, 'src': 37, 'op': 'move'}
instructions[203] = {6'd3, 7'd38, 7'd58, 32'd0};//{'dest': 38, 'src': 58, 'op': 'move'}
instructions[204] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[205] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[206] = {6'd15, 7'd37, 7'd38, 32'd10};//{'src': 38, 'right': 10, 'dest': 37, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[207] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[208] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[209] = {6'd12, 7'd0, 7'd37, 32'd225};//{'src': 37, 'label': 225, 'op': 'jmp_if_false'}
instructions[210] = {6'd3, 7'd38, 7'd58, 32'd0};//{'dest': 38, 'src': 58, 'op': 'move'}
instructions[211] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[212] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[213] = {6'd16, 7'd37, 7'd38, 32'd10};//{'src': 38, 'right': 10, 'dest': 37, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[214] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[215] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[216] = {6'd3, 7'd58, 7'd37, 32'd0};//{'dest': 58, 'src': 37, 'op': 'move'}
instructions[217] = {6'd3, 7'd38, 7'd59, 32'd0};//{'dest': 38, 'src': 59, 'op': 'move'}
instructions[218] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[219] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[220] = {6'd13, 7'd37, 7'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 37, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[221] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[222] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[223] = {6'd3, 7'd59, 7'd37, 32'd0};//{'dest': 59, 'src': 37, 'op': 'move'}
instructions[224] = {6'd14, 7'd0, 7'd0, 32'd226};//{'label': 226, 'op': 'goto'}
instructions[225] = {6'd14, 7'd0, 7'd0, 32'd227};//{'label': 227, 'op': 'goto'}
instructions[226] = {6'd14, 7'd0, 7'd0, 32'd203};//{'label': 203, 'op': 'goto'}
instructions[227] = {6'd3, 7'd38, 7'd59, 32'd0};//{'dest': 38, 'src': 59, 'op': 'move'}
instructions[228] = {6'd3, 7'd39, 7'd60, 32'd0};//{'dest': 39, 'src': 60, 'op': 'move'}
instructions[229] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[230] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[231] = {6'd17, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[232] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[233] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[234] = {6'd12, 7'd0, 7'd37, 32'd248};//{'src': 37, 'label': 248, 'op': 'jmp_if_false'}
instructions[235] = {6'd3, 7'd39, 7'd59, 32'd0};//{'dest': 39, 'src': 59, 'op': 'move'}
instructions[236] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[237] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[238] = {6'd18, 7'd38, 7'd39, 32'd48};//{'src': 39, 'right': 48, 'dest': 38, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[239] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[240] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[241] = {6'd3, 7'd53, 7'd38, 32'd0};//{'dest': 53, 'src': 38, 'op': 'move'}
instructions[242] = {6'd1, 7'd52, 7'd0, 32'd9};//{'dest': 52, 'label': 9, 'op': 'jmp_and_link'}
instructions[243] = {6'd0, 7'd37, 7'd0, 32'd1};//{'dest': 37, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[244] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[245] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[246] = {6'd3, 7'd60, 7'd37, 32'd0};//{'dest': 60, 'src': 37, 'op': 'move'}
instructions[247] = {6'd14, 7'd0, 7'd0, 32'd248};//{'label': 248, 'op': 'goto'}
instructions[248] = {6'd3, 7'd39, 7'd58, 32'd0};//{'dest': 39, 'src': 58, 'op': 'move'}
instructions[249] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[250] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[251] = {6'd18, 7'd38, 7'd39, 32'd48};//{'src': 39, 'right': 48, 'dest': 38, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[252] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[253] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[254] = {6'd3, 7'd53, 7'd38, 32'd0};//{'dest': 53, 'src': 38, 'op': 'move'}
instructions[255] = {6'd1, 7'd52, 7'd0, 32'd9};//{'dest': 52, 'label': 9, 'op': 'jmp_and_link'}
instructions[256] = {6'd6, 7'd0, 7'd57, 32'd0};//{'src': 57, 'op': 'jmp_to_reg'}
instructions[257] = {6'd3, 7'd38, 7'd62, 32'd0};//{'dest': 38, 'src': 62, 'op': 'move'}
instructions[258] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[259] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[260] = {6'd19, 7'd37, 7'd38, 32'd0};//{'src': 38, 'right': 0, 'dest': 37, 'signed': True, 'op': '>=', 'type': 'int', 'size': 2}
instructions[261] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[262] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[263] = {6'd12, 7'd0, 7'd37, 32'd270};//{'src': 37, 'label': 270, 'op': 'jmp_if_false'}
instructions[264] = {6'd3, 7'd38, 7'd62, 32'd0};//{'dest': 38, 'src': 62, 'op': 'move'}
instructions[265] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[266] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[267] = {6'd3, 7'd58, 7'd38, 32'd0};//{'dest': 58, 'src': 38, 'op': 'move'}
instructions[268] = {6'd1, 7'd57, 7'd0, 32'd50};//{'dest': 57, 'label': 50, 'op': 'jmp_and_link'}
instructions[269] = {6'd14, 7'd0, 7'd0, 32'd283};//{'label': 283, 'op': 'goto'}
instructions[270] = {6'd0, 7'd38, 7'd0, 32'd45};//{'dest': 38, 'literal': 45, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[271] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[272] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[273] = {6'd3, 7'd53, 7'd38, 32'd0};//{'dest': 53, 'src': 38, 'op': 'move'}
instructions[274] = {6'd1, 7'd52, 7'd0, 32'd9};//{'dest': 52, 'label': 9, 'op': 'jmp_and_link'}
instructions[275] = {6'd3, 7'd39, 7'd62, 32'd0};//{'dest': 39, 'src': 62, 'op': 'move'}
instructions[276] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[277] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[278] = {6'd20, 7'd38, 7'd39, 32'd0};//{'src': 39, 'dest': 38, 'signed': True, 'op': '-', 'size': 2, 'type': 'int', 'left': 0}
instructions[279] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[280] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[281] = {6'd3, 7'd58, 7'd38, 32'd0};//{'dest': 58, 'src': 38, 'op': 'move'}
instructions[282] = {6'd1, 7'd57, 7'd0, 32'd50};//{'dest': 57, 'label': 50, 'op': 'jmp_and_link'}
instructions[283] = {6'd6, 7'd0, 7'd61, 32'd0};//{'src': 61, 'op': 'jmp_to_reg'}
instructions[284] = {6'd3, 7'd37, 7'd63, 32'd0};//{'dest': 37, 'src': 63, 'op': 'move'}
instructions[285] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[286] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[287] = {6'd12, 7'd0, 7'd37, 32'd300};//{'src': 37, 'label': 300, 'op': 'jmp_if_false'}
instructions[288] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[289] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[290] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[291] = {6'd3, 7'd63, 7'd37, 32'd0};//{'dest': 63, 'src': 37, 'op': 'move'}
instructions[292] = {6'd3, 7'd38, 7'd66, 32'd0};//{'dest': 38, 'src': 66, 'op': 'move'}
instructions[293] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[294] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[295] = {6'd21, 7'd37, 7'd38, 32'd8};//{'src': 38, 'right': 8, 'dest': 37, 'signed': True, 'op': '<<', 'type': 'int', 'size': 2}
instructions[296] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[297] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[298] = {6'd3, 7'd64, 7'd37, 32'd0};//{'dest': 64, 'src': 37, 'op': 'move'}
instructions[299] = {6'd14, 7'd0, 7'd0, 32'd322};//{'label': 322, 'op': 'goto'}
instructions[300] = {6'd0, 7'd37, 7'd0, 32'd1};//{'dest': 37, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[301] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[302] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[303] = {6'd3, 7'd63, 7'd37, 32'd0};//{'dest': 63, 'src': 37, 'op': 'move'}
instructions[304] = {6'd3, 7'd38, 7'd64, 32'd0};//{'dest': 38, 'src': 64, 'op': 'move'}
instructions[305] = {6'd3, 7'd41, 7'd66, 32'd0};//{'dest': 41, 'src': 66, 'op': 'move'}
instructions[306] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[307] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[308] = {6'd22, 7'd39, 7'd41, 32'd255};//{'src': 41, 'right': 255, 'dest': 39, 'signed': True, 'op': '&', 'type': 'int', 'size': 2}
instructions[309] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[310] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[311] = {6'd17, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[312] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[313] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[314] = {6'd3, 7'd64, 7'd37, 32'd0};//{'dest': 64, 'src': 37, 'op': 'move'}
instructions[315] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[316] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[317] = {6'd3, 7'd38, 7'd64, 32'd0};//{'dest': 38, 'src': 64, 'op': 'move'}
instructions[318] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[319] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[320] = {6'd3, 7'd51, 7'd38, 32'd0};//{'dest': 51, 'src': 38, 'op': 'move'}
instructions[321] = {6'd1, 7'd50, 7'd0, 32'd4};//{'dest': 50, 'label': 4, 'op': 'jmp_and_link'}
instructions[322] = {6'd6, 7'd0, 7'd65, 32'd0};//{'src': 65, 'op': 'jmp_to_reg'}
instructions[323] = {6'd3, 7'd38, 7'd63, 32'd0};//{'dest': 38, 'src': 63, 'op': 'move'}
instructions[324] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[325] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[326] = {6'd23, 7'd37, 7'd38, 32'd0};//{'src': 38, 'right': 0, 'dest': 37, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[327] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[328] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[329] = {6'd12, 7'd0, 7'd37, 32'd336};//{'src': 37, 'label': 336, 'op': 'jmp_if_false'}
instructions[330] = {6'd3, 7'd38, 7'd64, 32'd0};//{'dest': 38, 'src': 64, 'op': 'move'}
instructions[331] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[332] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[333] = {6'd3, 7'd51, 7'd38, 32'd0};//{'dest': 51, 'src': 38, 'op': 'move'}
instructions[334] = {6'd1, 7'd50, 7'd0, 32'd4};//{'dest': 50, 'label': 4, 'op': 'jmp_and_link'}
instructions[335] = {6'd14, 7'd0, 7'd0, 32'd336};//{'label': 336, 'op': 'goto'}
instructions[336] = {6'd0, 7'd37, 7'd0, 32'd1};//{'dest': 37, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[337] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[338] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[339] = {6'd3, 7'd63, 7'd37, 32'd0};//{'dest': 63, 'src': 37, 'op': 'move'}
instructions[340] = {6'd6, 7'd0, 7'd67, 32'd0};//{'src': 67, 'op': 'jmp_to_reg'}
instructions[341] = {6'd0, 7'd70, 7'd0, 32'd0};//{'dest': 70, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[342] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[343] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[344] = {6'd3, 7'd38, 7'd70, 32'd0};//{'dest': 38, 'src': 70, 'op': 'move'}
instructions[345] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[346] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[347] = {6'd8, 7'd39, 7'd38, 32'd69};//{'dest': 39, 'src': 38, 'srcb': 69, 'signed': False, 'op': '+'}
instructions[348] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[349] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[350] = {6'd9, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208960208, 'op': 'memory_read_request'}
instructions[351] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[352] = {6'd10, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208960208, 'op': 'memory_read_wait'}
instructions[353] = {6'd11, 7'd37, 7'd39, 32'd0};//{'dest': 37, 'src': 39, 'sequence': 140361208960208, 'element_size': 2, 'op': 'memory_read'}
instructions[354] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[355] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[356] = {6'd12, 7'd0, 7'd37, 32'd374};//{'src': 37, 'label': 374, 'op': 'jmp_if_false'}
instructions[357] = {6'd3, 7'd39, 7'd70, 32'd0};//{'dest': 39, 'src': 70, 'op': 'move'}
instructions[358] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[359] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[360] = {6'd8, 7'd41, 7'd39, 32'd69};//{'dest': 41, 'src': 39, 'srcb': 69, 'signed': False, 'op': '+'}
instructions[361] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[362] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[363] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208968976, 'op': 'memory_read_request'}
instructions[364] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[365] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208968976, 'op': 'memory_read_wait'}
instructions[366] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361208968976, 'element_size': 2, 'op': 'memory_read'}
instructions[367] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[368] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[369] = {6'd3, 7'd66, 7'd38, 32'd0};//{'dest': 66, 'src': 38, 'op': 'move'}
instructions[370] = {6'd1, 7'd65, 7'd0, 32'd284};//{'dest': 65, 'label': 284, 'op': 'jmp_and_link'}
instructions[371] = {6'd3, 7'd37, 7'd70, 32'd0};//{'dest': 37, 'src': 70, 'op': 'move'}
instructions[372] = {6'd13, 7'd70, 7'd70, 32'd1};//{'src': 70, 'right': 1, 'dest': 70, 'signed': False, 'op': '+', 'size': 2}
instructions[373] = {6'd14, 7'd0, 7'd0, 32'd375};//{'label': 375, 'op': 'goto'}
instructions[374] = {6'd14, 7'd0, 7'd0, 32'd376};//{'label': 376, 'op': 'goto'}
instructions[375] = {6'd14, 7'd0, 7'd0, 32'd342};//{'label': 342, 'op': 'goto'}
instructions[376] = {6'd6, 7'd0, 7'd68, 32'd0};//{'src': 68, 'op': 'jmp_to_reg'}
instructions[377] = {6'd0, 7'd73, 7'd0, 32'd0};//{'dest': 73, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[378] = {6'd0, 7'd74, 7'd0, 32'd0};//{'dest': 74, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[379] = {6'd0, 7'd75, 7'd0, 32'd0};//{'dest': 75, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[380] = {6'd0, 7'd76, 7'd0, 32'd0};//{'dest': 76, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[381] = {6'd0, 7'd0, 7'd0, 32'd0};//{'dest': 0, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[382] = {6'd0, 7'd1, 7'd0, 32'd0};//{'dest': 1, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[383] = {6'd3, 7'd38, 7'd72, 32'd0};//{'dest': 38, 'src': 72, 'op': 'move'}
instructions[384] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[385] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[386] = {6'd15, 7'd37, 7'd38, 32'd10000};//{'src': 38, 'right': 10000, 'dest': 37, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[387] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[388] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[389] = {6'd12, 7'd0, 7'd37, 32'd400};//{'src': 37, 'label': 400, 'op': 'jmp_if_false'}
instructions[390] = {6'd3, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'src': 0, 'op': 'move'}
instructions[391] = {6'd13, 7'd0, 7'd0, 32'd1};//{'src': 0, 'right': 1, 'dest': 0, 'signed': False, 'op': '+', 'size': 2}
instructions[392] = {6'd3, 7'd38, 7'd72, 32'd0};//{'dest': 38, 'src': 72, 'op': 'move'}
instructions[393] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[394] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[395] = {6'd16, 7'd37, 7'd38, 32'd10000};//{'src': 38, 'right': 10000, 'dest': 37, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[396] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[397] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[398] = {6'd3, 7'd72, 7'd37, 32'd0};//{'dest': 72, 'src': 37, 'op': 'move'}
instructions[399] = {6'd14, 7'd0, 7'd0, 32'd401};//{'label': 401, 'op': 'goto'}
instructions[400] = {6'd14, 7'd0, 7'd0, 32'd402};//{'label': 402, 'op': 'goto'}
instructions[401] = {6'd14, 7'd0, 7'd0, 32'd383};//{'label': 383, 'op': 'goto'}
instructions[402] = {6'd3, 7'd38, 7'd0, 32'd0};//{'dest': 38, 'src': 0, 'op': 'move'}
instructions[403] = {6'd3, 7'd39, 7'd1, 32'd0};//{'dest': 39, 'src': 1, 'op': 'move'}
instructions[404] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[405] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[406] = {6'd17, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[407] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[408] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[409] = {6'd12, 7'd0, 7'd37, 32'd423};//{'src': 37, 'label': 423, 'op': 'jmp_if_false'}
instructions[410] = {6'd3, 7'd39, 7'd0, 32'd0};//{'dest': 39, 'src': 0, 'op': 'move'}
instructions[411] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[412] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[413] = {6'd24, 7'd38, 7'd39, 32'd48};//{'src': 39, 'dest': 38, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 48}
instructions[414] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[415] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[416] = {6'd3, 7'd66, 7'd38, 32'd0};//{'dest': 66, 'src': 38, 'op': 'move'}
instructions[417] = {6'd1, 7'd65, 7'd0, 32'd284};//{'dest': 65, 'label': 284, 'op': 'jmp_and_link'}
instructions[418] = {6'd0, 7'd37, 7'd0, 32'd1};//{'dest': 37, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[419] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[420] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[421] = {6'd3, 7'd1, 7'd37, 32'd0};//{'dest': 1, 'src': 37, 'op': 'move'}
instructions[422] = {6'd14, 7'd0, 7'd0, 32'd423};//{'label': 423, 'op': 'goto'}
instructions[423] = {6'd3, 7'd38, 7'd72, 32'd0};//{'dest': 38, 'src': 72, 'op': 'move'}
instructions[424] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[425] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[426] = {6'd15, 7'd37, 7'd38, 32'd1000};//{'src': 38, 'right': 1000, 'dest': 37, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[427] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[428] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[429] = {6'd12, 7'd0, 7'd37, 32'd440};//{'src': 37, 'label': 440, 'op': 'jmp_if_false'}
instructions[430] = {6'd3, 7'd37, 7'd76, 32'd0};//{'dest': 37, 'src': 76, 'op': 'move'}
instructions[431] = {6'd13, 7'd76, 7'd76, 32'd1};//{'src': 76, 'right': 1, 'dest': 76, 'signed': False, 'op': '+', 'size': 2}
instructions[432] = {6'd3, 7'd38, 7'd72, 32'd0};//{'dest': 38, 'src': 72, 'op': 'move'}
instructions[433] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[434] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[435] = {6'd16, 7'd37, 7'd38, 32'd1000};//{'src': 38, 'right': 1000, 'dest': 37, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[436] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[437] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[438] = {6'd3, 7'd72, 7'd37, 32'd0};//{'dest': 72, 'src': 37, 'op': 'move'}
instructions[439] = {6'd14, 7'd0, 7'd0, 32'd441};//{'label': 441, 'op': 'goto'}
instructions[440] = {6'd14, 7'd0, 7'd0, 32'd442};//{'label': 442, 'op': 'goto'}
instructions[441] = {6'd14, 7'd0, 7'd0, 32'd423};//{'label': 423, 'op': 'goto'}
instructions[442] = {6'd3, 7'd38, 7'd76, 32'd0};//{'dest': 38, 'src': 76, 'op': 'move'}
instructions[443] = {6'd3, 7'd39, 7'd1, 32'd0};//{'dest': 39, 'src': 1, 'op': 'move'}
instructions[444] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[445] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[446] = {6'd17, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[447] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[448] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[449] = {6'd12, 7'd0, 7'd37, 32'd463};//{'src': 37, 'label': 463, 'op': 'jmp_if_false'}
instructions[450] = {6'd3, 7'd39, 7'd76, 32'd0};//{'dest': 39, 'src': 76, 'op': 'move'}
instructions[451] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[452] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[453] = {6'd24, 7'd38, 7'd39, 32'd48};//{'src': 39, 'dest': 38, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 48}
instructions[454] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[455] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[456] = {6'd3, 7'd66, 7'd38, 32'd0};//{'dest': 66, 'src': 38, 'op': 'move'}
instructions[457] = {6'd1, 7'd65, 7'd0, 32'd284};//{'dest': 65, 'label': 284, 'op': 'jmp_and_link'}
instructions[458] = {6'd0, 7'd37, 7'd0, 32'd1};//{'dest': 37, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[459] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[460] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[461] = {6'd3, 7'd1, 7'd37, 32'd0};//{'dest': 1, 'src': 37, 'op': 'move'}
instructions[462] = {6'd14, 7'd0, 7'd0, 32'd463};//{'label': 463, 'op': 'goto'}
instructions[463] = {6'd3, 7'd38, 7'd72, 32'd0};//{'dest': 38, 'src': 72, 'op': 'move'}
instructions[464] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[465] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[466] = {6'd15, 7'd37, 7'd38, 32'd100};//{'src': 38, 'right': 100, 'dest': 37, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[467] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[468] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[469] = {6'd12, 7'd0, 7'd37, 32'd480};//{'src': 37, 'label': 480, 'op': 'jmp_if_false'}
instructions[470] = {6'd3, 7'd37, 7'd75, 32'd0};//{'dest': 37, 'src': 75, 'op': 'move'}
instructions[471] = {6'd13, 7'd75, 7'd75, 32'd1};//{'src': 75, 'right': 1, 'dest': 75, 'signed': False, 'op': '+', 'size': 2}
instructions[472] = {6'd3, 7'd38, 7'd72, 32'd0};//{'dest': 38, 'src': 72, 'op': 'move'}
instructions[473] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[474] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[475] = {6'd16, 7'd37, 7'd38, 32'd100};//{'src': 38, 'right': 100, 'dest': 37, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[476] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[477] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[478] = {6'd3, 7'd72, 7'd37, 32'd0};//{'dest': 72, 'src': 37, 'op': 'move'}
instructions[479] = {6'd14, 7'd0, 7'd0, 32'd481};//{'label': 481, 'op': 'goto'}
instructions[480] = {6'd14, 7'd0, 7'd0, 32'd482};//{'label': 482, 'op': 'goto'}
instructions[481] = {6'd14, 7'd0, 7'd0, 32'd463};//{'label': 463, 'op': 'goto'}
instructions[482] = {6'd3, 7'd38, 7'd75, 32'd0};//{'dest': 38, 'src': 75, 'op': 'move'}
instructions[483] = {6'd3, 7'd39, 7'd1, 32'd0};//{'dest': 39, 'src': 1, 'op': 'move'}
instructions[484] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[485] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[486] = {6'd17, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[487] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[488] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[489] = {6'd12, 7'd0, 7'd37, 32'd503};//{'src': 37, 'label': 503, 'op': 'jmp_if_false'}
instructions[490] = {6'd3, 7'd39, 7'd75, 32'd0};//{'dest': 39, 'src': 75, 'op': 'move'}
instructions[491] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[492] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[493] = {6'd24, 7'd38, 7'd39, 32'd48};//{'src': 39, 'dest': 38, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 48}
instructions[494] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[495] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[496] = {6'd3, 7'd66, 7'd38, 32'd0};//{'dest': 66, 'src': 38, 'op': 'move'}
instructions[497] = {6'd1, 7'd65, 7'd0, 32'd284};//{'dest': 65, 'label': 284, 'op': 'jmp_and_link'}
instructions[498] = {6'd0, 7'd37, 7'd0, 32'd1};//{'dest': 37, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[499] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[500] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[501] = {6'd3, 7'd1, 7'd37, 32'd0};//{'dest': 1, 'src': 37, 'op': 'move'}
instructions[502] = {6'd14, 7'd0, 7'd0, 32'd503};//{'label': 503, 'op': 'goto'}
instructions[503] = {6'd3, 7'd38, 7'd72, 32'd0};//{'dest': 38, 'src': 72, 'op': 'move'}
instructions[504] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[505] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[506] = {6'd15, 7'd37, 7'd38, 32'd10};//{'src': 38, 'right': 10, 'dest': 37, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[507] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[508] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[509] = {6'd12, 7'd0, 7'd37, 32'd520};//{'src': 37, 'label': 520, 'op': 'jmp_if_false'}
instructions[510] = {6'd3, 7'd37, 7'd74, 32'd0};//{'dest': 37, 'src': 74, 'op': 'move'}
instructions[511] = {6'd13, 7'd74, 7'd74, 32'd1};//{'src': 74, 'right': 1, 'dest': 74, 'signed': False, 'op': '+', 'size': 2}
instructions[512] = {6'd3, 7'd38, 7'd72, 32'd0};//{'dest': 38, 'src': 72, 'op': 'move'}
instructions[513] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[514] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[515] = {6'd16, 7'd37, 7'd38, 32'd10};//{'src': 38, 'right': 10, 'dest': 37, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[516] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[517] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[518] = {6'd3, 7'd72, 7'd37, 32'd0};//{'dest': 72, 'src': 37, 'op': 'move'}
instructions[519] = {6'd14, 7'd0, 7'd0, 32'd521};//{'label': 521, 'op': 'goto'}
instructions[520] = {6'd14, 7'd0, 7'd0, 32'd522};//{'label': 522, 'op': 'goto'}
instructions[521] = {6'd14, 7'd0, 7'd0, 32'd503};//{'label': 503, 'op': 'goto'}
instructions[522] = {6'd3, 7'd38, 7'd74, 32'd0};//{'dest': 38, 'src': 74, 'op': 'move'}
instructions[523] = {6'd3, 7'd39, 7'd1, 32'd0};//{'dest': 39, 'src': 1, 'op': 'move'}
instructions[524] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[525] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[526] = {6'd17, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[527] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[528] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[529] = {6'd12, 7'd0, 7'd37, 32'd543};//{'src': 37, 'label': 543, 'op': 'jmp_if_false'}
instructions[530] = {6'd3, 7'd39, 7'd74, 32'd0};//{'dest': 39, 'src': 74, 'op': 'move'}
instructions[531] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[532] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[533] = {6'd24, 7'd38, 7'd39, 32'd48};//{'src': 39, 'dest': 38, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 48}
instructions[534] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[535] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[536] = {6'd3, 7'd66, 7'd38, 32'd0};//{'dest': 66, 'src': 38, 'op': 'move'}
instructions[537] = {6'd1, 7'd65, 7'd0, 32'd284};//{'dest': 65, 'label': 284, 'op': 'jmp_and_link'}
instructions[538] = {6'd0, 7'd37, 7'd0, 32'd1};//{'dest': 37, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[539] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[540] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[541] = {6'd3, 7'd1, 7'd37, 32'd0};//{'dest': 1, 'src': 37, 'op': 'move'}
instructions[542] = {6'd14, 7'd0, 7'd0, 32'd543};//{'label': 543, 'op': 'goto'}
instructions[543] = {6'd3, 7'd38, 7'd72, 32'd0};//{'dest': 38, 'src': 72, 'op': 'move'}
instructions[544] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[545] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[546] = {6'd15, 7'd37, 7'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 37, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[547] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[548] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[549] = {6'd12, 7'd0, 7'd37, 32'd560};//{'src': 37, 'label': 560, 'op': 'jmp_if_false'}
instructions[550] = {6'd3, 7'd37, 7'd73, 32'd0};//{'dest': 37, 'src': 73, 'op': 'move'}
instructions[551] = {6'd13, 7'd73, 7'd73, 32'd1};//{'src': 73, 'right': 1, 'dest': 73, 'signed': False, 'op': '+', 'size': 2}
instructions[552] = {6'd3, 7'd38, 7'd72, 32'd0};//{'dest': 38, 'src': 72, 'op': 'move'}
instructions[553] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[554] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[555] = {6'd16, 7'd37, 7'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 37, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[556] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[557] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[558] = {6'd3, 7'd72, 7'd37, 32'd0};//{'dest': 72, 'src': 37, 'op': 'move'}
instructions[559] = {6'd14, 7'd0, 7'd0, 32'd561};//{'label': 561, 'op': 'goto'}
instructions[560] = {6'd14, 7'd0, 7'd0, 32'd562};//{'label': 562, 'op': 'goto'}
instructions[561] = {6'd14, 7'd0, 7'd0, 32'd543};//{'label': 543, 'op': 'goto'}
instructions[562] = {6'd3, 7'd39, 7'd73, 32'd0};//{'dest': 39, 'src': 73, 'op': 'move'}
instructions[563] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[564] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[565] = {6'd24, 7'd38, 7'd39, 32'd48};//{'src': 39, 'dest': 38, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 48}
instructions[566] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[567] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[568] = {6'd3, 7'd66, 7'd38, 32'd0};//{'dest': 66, 'src': 38, 'op': 'move'}
instructions[569] = {6'd1, 7'd65, 7'd0, 32'd284};//{'dest': 65, 'label': 284, 'op': 'jmp_and_link'}
instructions[570] = {6'd6, 7'd0, 7'd71, 32'd0};//{'src': 71, 'op': 'jmp_to_reg'}
instructions[571] = {6'd0, 7'd3, 7'd0, 32'd0};//{'dest': 3, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[572] = {6'd0, 7'd4, 7'd0, 32'd4};//{'dest': 4, 'literal': 4, 'op': 'literal'}
instructions[573] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[574] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[575] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[576] = {6'd3, 7'd3, 7'd37, 32'd0};//{'dest': 3, 'src': 37, 'op': 'move'}
instructions[577] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[578] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[579] = {6'd3, 7'd38, 7'd3, 32'd0};//{'dest': 38, 'src': 3, 'op': 'move'}
instructions[580] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[581] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[582] = {6'd8, 7'd39, 7'd38, 32'd4};//{'dest': 39, 'src': 38, 'srcb': 4, 'signed': False, 'op': '+'}
instructions[583] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[584] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[585] = {6'd9, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208526320, 'op': 'memory_read_request'}
instructions[586] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[587] = {6'd10, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208526320, 'op': 'memory_read_wait'}
instructions[588] = {6'd11, 7'd37, 7'd39, 32'd0};//{'dest': 37, 'src': 39, 'sequence': 140361208526320, 'element_size': 2, 'op': 'memory_read'}
instructions[589] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[590] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[591] = {6'd12, 7'd0, 7'd37, 32'd595};//{'src': 37, 'label': 595, 'op': 'jmp_if_false'}
instructions[592] = {6'd3, 7'd37, 7'd3, 32'd0};//{'dest': 37, 'src': 3, 'op': 'move'}
instructions[593] = {6'd13, 7'd3, 7'd3, 32'd1};//{'src': 3, 'right': 1, 'dest': 3, 'signed': False, 'op': '+', 'size': 2}
instructions[594] = {6'd14, 7'd0, 7'd0, 32'd596};//{'label': 596, 'op': 'goto'}
instructions[595] = {6'd14, 7'd0, 7'd0, 32'd597};//{'label': 597, 'op': 'goto'}
instructions[596] = {6'd14, 7'd0, 7'd0, 32'd577};//{'label': 577, 'op': 'goto'}
instructions[597] = {6'd3, 7'd38, 7'd3, 32'd0};//{'dest': 38, 'src': 3, 'op': 'move'}
instructions[598] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[599] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[600] = {6'd3, 7'd51, 7'd38, 32'd0};//{'dest': 51, 'src': 38, 'op': 'move'}
instructions[601] = {6'd1, 7'd50, 7'd0, 32'd4};//{'dest': 50, 'label': 4, 'op': 'jmp_and_link'}
instructions[602] = {6'd3, 7'd42, 7'd4, 32'd0};//{'dest': 42, 'src': 4, 'op': 'move'}
instructions[603] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[604] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[605] = {6'd3, 7'd69, 7'd42, 32'd0};//{'dest': 69, 'src': 42, 'op': 'move'}
instructions[606] = {6'd1, 7'd68, 7'd0, 32'd341};//{'dest': 68, 'label': 341, 'op': 'jmp_and_link'}
instructions[607] = {6'd1, 7'd67, 7'd0, 32'd323};//{'dest': 67, 'label': 323, 'op': 'jmp_and_link'}
instructions[608] = {6'd6, 7'd0, 7'd2, 32'd0};//{'src': 2, 'op': 'jmp_to_reg'}
instructions[609] = {6'd0, 7'd7, 7'd0, 32'd0};//{'dest': 7, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[610] = {6'd0, 7'd8, 7'd0, 32'd0};//{'dest': 8, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[611] = {6'd0, 7'd9, 7'd0, 32'd0};//{'dest': 9, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[612] = {6'd0, 7'd10, 7'd0, 32'd0};//{'dest': 10, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[613] = {6'd0, 7'd11, 7'd0, 32'd0};//{'dest': 11, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[614] = {6'd0, 7'd12, 7'd0, 32'd132};//{'dest': 12, 'literal': 132, 'op': 'literal'}
instructions[615] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[616] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[617] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[618] = {6'd3, 7'd8, 7'd37, 32'd0};//{'dest': 8, 'src': 37, 'op': 'move'}
instructions[619] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[620] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[621] = {6'd3, 7'd38, 7'd8, 32'd0};//{'dest': 38, 'src': 8, 'op': 'move'}
instructions[622] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[623] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[624] = {6'd8, 7'd39, 7'd38, 32'd6};//{'dest': 39, 'src': 38, 'srcb': 6, 'signed': False, 'op': '+'}
instructions[625] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[626] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[627] = {6'd9, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208550392, 'op': 'memory_read_request'}
instructions[628] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[629] = {6'd10, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208550392, 'op': 'memory_read_wait'}
instructions[630] = {6'd11, 7'd37, 7'd39, 32'd0};//{'dest': 37, 'src': 39, 'sequence': 140361208550392, 'element_size': 2, 'op': 'memory_read'}
instructions[631] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[632] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[633] = {6'd12, 7'd0, 7'd37, 32'd637};//{'src': 37, 'label': 637, 'op': 'jmp_if_false'}
instructions[634] = {6'd3, 7'd37, 7'd8, 32'd0};//{'dest': 37, 'src': 8, 'op': 'move'}
instructions[635] = {6'd13, 7'd8, 7'd8, 32'd1};//{'src': 8, 'right': 1, 'dest': 8, 'signed': False, 'op': '+', 'size': 2}
instructions[636] = {6'd14, 7'd0, 7'd0, 32'd638};//{'label': 638, 'op': 'goto'}
instructions[637] = {6'd14, 7'd0, 7'd0, 32'd639};//{'label': 639, 'op': 'goto'}
instructions[638] = {6'd14, 7'd0, 7'd0, 32'd619};//{'label': 619, 'op': 'goto'}
instructions[639] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[640] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[641] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[642] = {6'd3, 7'd7, 7'd37, 32'd0};//{'dest': 7, 'src': 37, 'op': 'move'}
instructions[643] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[644] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[645] = {6'd3, 7'd38, 7'd7, 32'd0};//{'dest': 38, 'src': 7, 'op': 'move'}
instructions[646] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[647] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[648] = {6'd8, 7'd39, 7'd38, 32'd12};//{'dest': 39, 'src': 38, 'srcb': 12, 'signed': False, 'op': '+'}
instructions[649] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[650] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[651] = {6'd9, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208551256, 'op': 'memory_read_request'}
instructions[652] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[653] = {6'd10, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208551256, 'op': 'memory_read_wait'}
instructions[654] = {6'd11, 7'd37, 7'd39, 32'd0};//{'dest': 37, 'src': 39, 'sequence': 140361208551256, 'element_size': 2, 'op': 'memory_read'}
instructions[655] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[656] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[657] = {6'd12, 7'd0, 7'd37, 32'd661};//{'src': 37, 'label': 661, 'op': 'jmp_if_false'}
instructions[658] = {6'd3, 7'd37, 7'd7, 32'd0};//{'dest': 37, 'src': 7, 'op': 'move'}
instructions[659] = {6'd13, 7'd7, 7'd7, 32'd1};//{'src': 7, 'right': 1, 'dest': 7, 'signed': False, 'op': '+', 'size': 2}
instructions[660] = {6'd14, 7'd0, 7'd0, 32'd662};//{'label': 662, 'op': 'goto'}
instructions[661] = {6'd14, 7'd0, 7'd0, 32'd663};//{'label': 663, 'op': 'goto'}
instructions[662] = {6'd14, 7'd0, 7'd0, 32'd643};//{'label': 643, 'op': 'goto'}
instructions[663] = {6'd3, 7'd38, 7'd7, 32'd0};//{'dest': 38, 'src': 7, 'op': 'move'}
instructions[664] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[665] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[666] = {6'd13, 7'd37, 7'd38, 32'd5};//{'src': 38, 'right': 5, 'dest': 37, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[667] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[668] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[669] = {6'd3, 7'd9, 7'd37, 32'd0};//{'dest': 9, 'src': 37, 'op': 'move'}
instructions[670] = {6'd3, 7'd38, 7'd8, 32'd0};//{'dest': 38, 'src': 8, 'op': 'move'}
instructions[671] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[672] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[673] = {6'd25, 7'd37, 7'd38, 32'd9};//{'src': 38, 'right': 9, 'dest': 37, 'signed': False, 'op': '>', 'type': 'int', 'size': 2}
instructions[674] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[675] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[676] = {6'd12, 7'd0, 7'd37, 32'd680};//{'src': 37, 'label': 680, 'op': 'jmp_if_false'}
instructions[677] = {6'd3, 7'd37, 7'd9, 32'd0};//{'dest': 37, 'src': 9, 'op': 'move'}
instructions[678] = {6'd13, 7'd9, 7'd9, 32'd1};//{'src': 9, 'right': 1, 'dest': 9, 'signed': False, 'op': '+', 'size': 2}
instructions[679] = {6'd14, 7'd0, 7'd0, 32'd680};//{'label': 680, 'op': 'goto'}
instructions[680] = {6'd3, 7'd38, 7'd8, 32'd0};//{'dest': 38, 'src': 8, 'op': 'move'}
instructions[681] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[682] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[683] = {6'd25, 7'd37, 7'd38, 32'd99};//{'src': 38, 'right': 99, 'dest': 37, 'signed': False, 'op': '>', 'type': 'int', 'size': 2}
instructions[684] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[685] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[686] = {6'd12, 7'd0, 7'd37, 32'd690};//{'src': 37, 'label': 690, 'op': 'jmp_if_false'}
instructions[687] = {6'd3, 7'd37, 7'd9, 32'd0};//{'dest': 37, 'src': 9, 'op': 'move'}
instructions[688] = {6'd13, 7'd9, 7'd9, 32'd1};//{'src': 9, 'right': 1, 'dest': 9, 'signed': False, 'op': '+', 'size': 2}
instructions[689] = {6'd14, 7'd0, 7'd0, 32'd690};//{'label': 690, 'op': 'goto'}
instructions[690] = {6'd3, 7'd38, 7'd8, 32'd0};//{'dest': 38, 'src': 8, 'op': 'move'}
instructions[691] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[692] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[693] = {6'd25, 7'd37, 7'd38, 32'd999};//{'src': 38, 'right': 999, 'dest': 37, 'signed': False, 'op': '>', 'type': 'int', 'size': 2}
instructions[694] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[695] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[696] = {6'd12, 7'd0, 7'd37, 32'd700};//{'src': 37, 'label': 700, 'op': 'jmp_if_false'}
instructions[697] = {6'd3, 7'd37, 7'd9, 32'd0};//{'dest': 37, 'src': 9, 'op': 'move'}
instructions[698] = {6'd13, 7'd9, 7'd9, 32'd1};//{'src': 9, 'right': 1, 'dest': 9, 'signed': False, 'op': '+', 'size': 2}
instructions[699] = {6'd14, 7'd0, 7'd0, 32'd700};//{'label': 700, 'op': 'goto'}
instructions[700] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[701] = {6'd3, 7'd38, 7'd9, 32'd0};//{'dest': 38, 'src': 9, 'op': 'move'}
instructions[702] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[703] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[704] = {6'd3, 7'd51, 7'd38, 32'd0};//{'dest': 51, 'src': 38, 'op': 'move'}
instructions[705] = {6'd1, 7'd50, 7'd0, 32'd4};//{'dest': 50, 'label': 4, 'op': 'jmp_and_link'}
instructions[706] = {6'd3, 7'd43, 7'd12, 32'd0};//{'dest': 43, 'src': 12, 'op': 'move'}
instructions[707] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[708] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[709] = {6'd3, 7'd69, 7'd43, 32'd0};//{'dest': 69, 'src': 43, 'op': 'move'}
instructions[710] = {6'd1, 7'd68, 7'd0, 32'd341};//{'dest': 68, 'label': 341, 'op': 'jmp_and_link'}
instructions[711] = {6'd3, 7'd38, 7'd8, 32'd0};//{'dest': 38, 'src': 8, 'op': 'move'}
instructions[712] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[713] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[714] = {6'd3, 7'd72, 7'd38, 32'd0};//{'dest': 72, 'src': 38, 'op': 'move'}
instructions[715] = {6'd1, 7'd71, 7'd0, 32'd377};//{'dest': 71, 'label': 377, 'op': 'jmp_and_link'}
instructions[716] = {6'd0, 7'd13, 7'd0, 32'd246};//{'dest': 13, 'literal': 246, 'op': 'literal'}
instructions[717] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[718] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[719] = {6'd3, 7'd44, 7'd13, 32'd0};//{'dest': 44, 'src': 13, 'op': 'move'}
instructions[720] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[721] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[722] = {6'd3, 7'd69, 7'd44, 32'd0};//{'dest': 69, 'src': 44, 'op': 'move'}
instructions[723] = {6'd1, 7'd68, 7'd0, 32'd341};//{'dest': 68, 'label': 341, 'op': 'jmp_and_link'}
instructions[724] = {6'd1, 7'd67, 7'd0, 32'd323};//{'dest': 67, 'label': 323, 'op': 'jmp_and_link'}
instructions[725] = {6'd3, 7'd37, 7'd8, 32'd0};//{'dest': 37, 'src': 8, 'op': 'move'}
instructions[726] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[727] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[728] = {6'd3, 7'd9, 7'd37, 32'd0};//{'dest': 9, 'src': 37, 'op': 'move'}
instructions[729] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[730] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[731] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[732] = {6'd3, 7'd10, 7'd37, 32'd0};//{'dest': 10, 'src': 37, 'op': 'move'}
instructions[733] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[734] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[735] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[736] = {6'd3, 7'd11, 7'd37, 32'd0};//{'dest': 11, 'src': 37, 'op': 'move'}
instructions[737] = {6'd3, 7'd38, 7'd9, 32'd0};//{'dest': 38, 'src': 9, 'op': 'move'}
instructions[738] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[739] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[740] = {6'd15, 7'd37, 7'd38, 32'd1046};//{'src': 38, 'right': 1046, 'dest': 37, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[741] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[742] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[743] = {6'd12, 7'd0, 7'd37, 32'd790};//{'src': 37, 'label': 790, 'op': 'jmp_if_false'}
instructions[744] = {6'd3, 7'd38, 7'd9, 32'd0};//{'dest': 38, 'src': 9, 'op': 'move'}
instructions[745] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[746] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[747] = {6'd16, 7'd37, 7'd38, 32'd1046};//{'src': 38, 'right': 1046, 'dest': 37, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[748] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[749] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[750] = {6'd3, 7'd9, 7'd37, 32'd0};//{'dest': 9, 'src': 37, 'op': 'move'}
instructions[751] = {6'd0, 7'd38, 7'd0, 32'd1046};//{'dest': 38, 'literal': 1046, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[752] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[753] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[754] = {6'd3, 7'd51, 7'd38, 32'd0};//{'dest': 51, 'src': 38, 'op': 'move'}
instructions[755] = {6'd1, 7'd50, 7'd0, 32'd4};//{'dest': 50, 'label': 4, 'op': 'jmp_and_link'}
instructions[756] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[757] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[758] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[759] = {6'd3, 7'd11, 7'd37, 32'd0};//{'dest': 11, 'src': 37, 'op': 'move'}
instructions[760] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[761] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[762] = {6'd3, 7'd38, 7'd11, 32'd0};//{'dest': 38, 'src': 11, 'op': 'move'}
instructions[763] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[764] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[765] = {6'd26, 7'd37, 7'd38, 32'd1046};//{'src': 38, 'right': 1046, 'dest': 37, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[766] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[767] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[768] = {6'd12, 7'd0, 7'd37, 32'd788};//{'src': 37, 'label': 788, 'op': 'jmp_if_false'}
instructions[769] = {6'd3, 7'd39, 7'd10, 32'd0};//{'dest': 39, 'src': 10, 'op': 'move'}
instructions[770] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[771] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[772] = {6'd8, 7'd41, 7'd39, 32'd6};//{'dest': 41, 'src': 39, 'srcb': 6, 'signed': False, 'op': '+'}
instructions[773] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[774] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[775] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208599544, 'op': 'memory_read_request'}
instructions[776] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[777] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208599544, 'op': 'memory_read_wait'}
instructions[778] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361208599544, 'element_size': 2, 'op': 'memory_read'}
instructions[779] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[780] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[781] = {6'd3, 7'd66, 7'd38, 32'd0};//{'dest': 66, 'src': 38, 'op': 'move'}
instructions[782] = {6'd1, 7'd65, 7'd0, 32'd284};//{'dest': 65, 'label': 284, 'op': 'jmp_and_link'}
instructions[783] = {6'd3, 7'd37, 7'd10, 32'd0};//{'dest': 37, 'src': 10, 'op': 'move'}
instructions[784] = {6'd13, 7'd10, 7'd10, 32'd1};//{'src': 10, 'right': 1, 'dest': 10, 'signed': False, 'op': '+', 'size': 2}
instructions[785] = {6'd3, 7'd37, 7'd11, 32'd0};//{'dest': 37, 'src': 11, 'op': 'move'}
instructions[786] = {6'd13, 7'd11, 7'd11, 32'd1};//{'src': 11, 'right': 1, 'dest': 11, 'signed': False, 'op': '+', 'size': 2}
instructions[787] = {6'd14, 7'd0, 7'd0, 32'd760};//{'label': 760, 'op': 'goto'}
instructions[788] = {6'd1, 7'd67, 7'd0, 32'd323};//{'dest': 67, 'label': 323, 'op': 'jmp_and_link'}
instructions[789] = {6'd14, 7'd0, 7'd0, 32'd791};//{'label': 791, 'op': 'goto'}
instructions[790] = {6'd14, 7'd0, 7'd0, 32'd792};//{'label': 792, 'op': 'goto'}
instructions[791] = {6'd14, 7'd0, 7'd0, 32'd737};//{'label': 737, 'op': 'goto'}
instructions[792] = {6'd3, 7'd38, 7'd9, 32'd0};//{'dest': 38, 'src': 9, 'op': 'move'}
instructions[793] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[794] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[795] = {6'd3, 7'd51, 7'd38, 32'd0};//{'dest': 51, 'src': 38, 'op': 'move'}
instructions[796] = {6'd1, 7'd50, 7'd0, 32'd4};//{'dest': 50, 'label': 4, 'op': 'jmp_and_link'}
instructions[797] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[798] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[799] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[800] = {6'd3, 7'd11, 7'd37, 32'd0};//{'dest': 11, 'src': 37, 'op': 'move'}
instructions[801] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[802] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[803] = {6'd3, 7'd38, 7'd11, 32'd0};//{'dest': 38, 'src': 11, 'op': 'move'}
instructions[804] = {6'd3, 7'd39, 7'd9, 32'd0};//{'dest': 39, 'src': 9, 'op': 'move'}
instructions[805] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[806] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[807] = {6'd27, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[808] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[809] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[810] = {6'd12, 7'd0, 7'd37, 32'd830};//{'src': 37, 'label': 830, 'op': 'jmp_if_false'}
instructions[811] = {6'd3, 7'd39, 7'd10, 32'd0};//{'dest': 39, 'src': 10, 'op': 'move'}
instructions[812] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[813] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[814] = {6'd8, 7'd41, 7'd39, 32'd6};//{'dest': 41, 'src': 39, 'srcb': 6, 'signed': False, 'op': '+'}
instructions[815] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[816] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[817] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208601704, 'op': 'memory_read_request'}
instructions[818] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[819] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208601704, 'op': 'memory_read_wait'}
instructions[820] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361208601704, 'element_size': 2, 'op': 'memory_read'}
instructions[821] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[822] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[823] = {6'd3, 7'd66, 7'd38, 32'd0};//{'dest': 66, 'src': 38, 'op': 'move'}
instructions[824] = {6'd1, 7'd65, 7'd0, 32'd284};//{'dest': 65, 'label': 284, 'op': 'jmp_and_link'}
instructions[825] = {6'd3, 7'd37, 7'd10, 32'd0};//{'dest': 37, 'src': 10, 'op': 'move'}
instructions[826] = {6'd13, 7'd10, 7'd10, 32'd1};//{'src': 10, 'right': 1, 'dest': 10, 'signed': False, 'op': '+', 'size': 2}
instructions[827] = {6'd3, 7'd37, 7'd11, 32'd0};//{'dest': 37, 'src': 11, 'op': 'move'}
instructions[828] = {6'd13, 7'd11, 7'd11, 32'd1};//{'src': 11, 'right': 1, 'dest': 11, 'signed': False, 'op': '+', 'size': 2}
instructions[829] = {6'd14, 7'd0, 7'd0, 32'd801};//{'label': 801, 'op': 'goto'}
instructions[830] = {6'd1, 7'd67, 7'd0, 32'd323};//{'dest': 67, 'label': 323, 'op': 'jmp_and_link'}
instructions[831] = {6'd6, 7'd0, 7'd5, 32'd0};//{'src': 5, 'op': 'jmp_to_reg'}
instructions[832] = {6'd3, 7'd20, 7'd18, 32'd0};//{'dest': 20, 'src': 18, 'op': 'move'}
instructions[833] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[834] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[835] = {6'd3, 7'd38, 7'd20, 32'd0};//{'dest': 38, 'src': 20, 'op': 'move'}
instructions[836] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[837] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[838] = {6'd8, 7'd39, 7'd38, 32'd16};//{'dest': 39, 'src': 38, 'srcb': 16, 'signed': False, 'op': '+'}
instructions[839] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[840] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[841] = {6'd9, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208568576, 'op': 'memory_read_request'}
instructions[842] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[843] = {6'd10, 7'd0, 7'd39, 32'd0};//{'element_size': 2, 'src': 39, 'sequence': 140361208568576, 'op': 'memory_read_wait'}
instructions[844] = {6'd11, 7'd37, 7'd39, 32'd0};//{'dest': 37, 'src': 39, 'sequence': 140361208568576, 'element_size': 2, 'op': 'memory_read'}
instructions[845] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[846] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[847] = {6'd12, 7'd0, 7'd37, 32'd923};//{'src': 37, 'label': 923, 'op': 'jmp_if_false'}
instructions[848] = {6'd3, 7'd39, 7'd20, 32'd0};//{'dest': 39, 'src': 20, 'op': 'move'}
instructions[849] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[850] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[851] = {6'd8, 7'd41, 7'd39, 32'd16};//{'dest': 41, 'src': 39, 'srcb': 16, 'signed': False, 'op': '+'}
instructions[852] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[853] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[854] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208628864, 'op': 'memory_read_request'}
instructions[855] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[856] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208628864, 'op': 'memory_read_wait'}
instructions[857] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361208628864, 'element_size': 2, 'op': 'memory_read'}
instructions[858] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[859] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[860] = {6'd3, 7'd62, 7'd38, 32'd0};//{'dest': 62, 'src': 38, 'op': 'move'}
instructions[861] = {6'd1, 7'd61, 7'd0, 32'd257};//{'dest': 61, 'label': 257, 'op': 'jmp_and_link'}
instructions[862] = {6'd0, 7'd21, 7'd0, 32'd253};//{'dest': 21, 'literal': 253, 'op': 'literal'}
instructions[863] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[864] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[865] = {6'd3, 7'd40, 7'd21, 32'd0};//{'dest': 40, 'src': 21, 'op': 'move'}
instructions[866] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[867] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[868] = {6'd3, 7'd55, 7'd40, 32'd0};//{'dest': 55, 'src': 40, 'op': 'move'}
instructions[869] = {6'd1, 7'd54, 7'd0, 32'd14};//{'dest': 54, 'label': 14, 'op': 'jmp_and_link'}
instructions[870] = {6'd3, 7'd38, 7'd20, 32'd0};//{'dest': 38, 'src': 20, 'op': 'move'}
instructions[871] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[872] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[873] = {6'd3, 7'd62, 7'd38, 32'd0};//{'dest': 62, 'src': 38, 'op': 'move'}
instructions[874] = {6'd1, 7'd61, 7'd0, 32'd257};//{'dest': 61, 'label': 257, 'op': 'jmp_and_link'}
instructions[875] = {6'd0, 7'd22, 7'd0, 32'd255};//{'dest': 22, 'literal': 255, 'op': 'literal'}
instructions[876] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[877] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[878] = {6'd3, 7'd40, 7'd22, 32'd0};//{'dest': 40, 'src': 22, 'op': 'move'}
instructions[879] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[880] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[881] = {6'd3, 7'd55, 7'd40, 32'd0};//{'dest': 55, 'src': 40, 'op': 'move'}
instructions[882] = {6'd1, 7'd54, 7'd0, 32'd14};//{'dest': 54, 'label': 14, 'op': 'jmp_and_link'}
instructions[883] = {6'd3, 7'd38, 7'd20, 32'd0};//{'dest': 38, 'src': 20, 'op': 'move'}
instructions[884] = {6'd3, 7'd39, 7'd19, 32'd0};//{'dest': 39, 'src': 19, 'op': 'move'}
instructions[885] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[886] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[887] = {6'd28, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[888] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[889] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[890] = {6'd12, 7'd0, 7'd37, 32'd897};//{'src': 37, 'label': 897, 'op': 'jmp_if_false'}
instructions[891] = {6'd0, 7'd37, 7'd0, -32'd1};//{'dest': 37, 'literal': -1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[892] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[893] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[894] = {6'd3, 7'd15, 7'd37, 32'd0};//{'dest': 15, 'src': 37, 'op': 'move'}
instructions[895] = {6'd6, 7'd0, 7'd14, 32'd0};//{'src': 14, 'op': 'jmp_to_reg'}
instructions[896] = {6'd14, 7'd0, 7'd0, 32'd897};//{'label': 897, 'op': 'goto'}
instructions[897] = {6'd3, 7'd39, 7'd20, 32'd0};//{'dest': 39, 'src': 20, 'op': 'move'}
instructions[898] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[899] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[900] = {6'd8, 7'd41, 7'd39, 32'd16};//{'dest': 41, 'src': 39, 'srcb': 16, 'signed': False, 'op': '+'}
instructions[901] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[902] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[903] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208550464, 'op': 'memory_read_request'}
instructions[904] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[905] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361208550464, 'op': 'memory_read_wait'}
instructions[906] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361208550464, 'element_size': 2, 'op': 'memory_read'}
instructions[907] = {6'd3, 7'd39, 7'd17, 32'd0};//{'dest': 39, 'src': 17, 'op': 'move'}
instructions[908] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[909] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[910] = {6'd28, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[911] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[912] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[913] = {6'd12, 7'd0, 7'd37, 32'd920};//{'src': 37, 'label': 920, 'op': 'jmp_if_false'}
instructions[914] = {6'd3, 7'd37, 7'd20, 32'd0};//{'dest': 37, 'src': 20, 'op': 'move'}
instructions[915] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[916] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[917] = {6'd3, 7'd15, 7'd37, 32'd0};//{'dest': 15, 'src': 37, 'op': 'move'}
instructions[918] = {6'd6, 7'd0, 7'd14, 32'd0};//{'src': 14, 'op': 'jmp_to_reg'}
instructions[919] = {6'd14, 7'd0, 7'd0, 32'd920};//{'label': 920, 'op': 'goto'}
instructions[920] = {6'd3, 7'd37, 7'd20, 32'd0};//{'dest': 37, 'src': 20, 'op': 'move'}
instructions[921] = {6'd29, 7'd20, 7'd20, 32'd1};//{'src': 20, 'right': 1, 'dest': 20, 'signed': True, 'op': '+', 'size': 2}
instructions[922] = {6'd14, 7'd0, 7'd0, 32'd924};//{'label': 924, 'op': 'goto'}
instructions[923] = {6'd14, 7'd0, 7'd0, 32'd925};//{'label': 925, 'op': 'goto'}
instructions[924] = {6'd14, 7'd0, 7'd0, 32'd833};//{'label': 833, 'op': 'goto'}
instructions[925] = {6'd0, 7'd37, 7'd0, -32'd1};//{'dest': 37, 'literal': -1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[926] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[927] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[928] = {6'd3, 7'd15, 7'd37, 32'd0};//{'dest': 15, 'src': 37, 'op': 'move'}
instructions[929] = {6'd6, 7'd0, 7'd14, 32'd0};//{'src': 14, 'op': 'jmp_to_reg'}
instructions[930] = {6'd0, 7'd24, 7'd0, 32'd0};//{'dest': 24, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[931] = {6'd0, 7'd25, 7'd0, 32'd0};//{'dest': 25, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[932] = {6'd0, 7'd26, 7'd0, 32'd0};//{'dest': 26, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[933] = {6'd0, 7'd27, 7'd0, 32'd257};//{'dest': 27, 'literal': 257, 'op': 'literal'}
instructions[934] = {6'd0, 7'd28, 7'd0, 32'd0};//{'dest': 28, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[935] = {6'd0, 7'd29, 7'd0, 32'd0};//{'dest': 29, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[936] = {6'd0, 7'd30, 7'd0, 32'd0};//{'dest': 30, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[937] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[938] = {6'd0, 7'd32, 7'd0, 32'd0};//{'dest': 32, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[939] = {6'd0, 7'd33, 7'd0, 32'd0};//{'dest': 33, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[940] = {6'd0, 7'd34, 7'd0, 32'd1717};//{'dest': 34, 'literal': 1717, 'op': 'literal'}
instructions[941] = {6'd0, 7'd35, 7'd0, 32'd2859};//{'dest': 35, 'literal': 2859, 'op': 'literal'}
instructions[942] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[943] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[944] = {6'd3, 7'd45, 7'd35, 32'd0};//{'dest': 45, 'src': 35, 'op': 'move'}
instructions[945] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[946] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[947] = {6'd3, 7'd55, 7'd45, 32'd0};//{'dest': 55, 'src': 45, 'op': 'move'}
instructions[948] = {6'd1, 7'd54, 7'd0, 32'd14};//{'dest': 54, 'label': 14, 'op': 'jmp_and_link'}
instructions[949] = {6'd0, 7'd36, 7'd0, 32'd2898};//{'dest': 36, 'literal': 2898, 'op': 'literal'}
instructions[950] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[951] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[952] = {6'd3, 7'd46, 7'd36, 32'd0};//{'dest': 46, 'src': 36, 'op': 'move'}
instructions[953] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[954] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[955] = {6'd3, 7'd55, 7'd46, 32'd0};//{'dest': 55, 'src': 46, 'op': 'move'}
instructions[956] = {6'd1, 7'd54, 7'd0, 32'd14};//{'dest': 54, 'label': 14, 'op': 'jmp_and_link'}
instructions[957] = {6'd30, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'input': 'socket', 'op': 'read'}
instructions[958] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[959] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[960] = {6'd3, 7'd24, 7'd37, 32'd0};//{'dest': 24, 'src': 37, 'op': 'move'}
instructions[961] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[962] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[963] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[964] = {6'd3, 7'd26, 7'd37, 32'd0};//{'dest': 26, 'src': 37, 'op': 'move'}
instructions[965] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[966] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[967] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[968] = {6'd3, 7'd25, 7'd37, 32'd0};//{'dest': 25, 'src': 37, 'op': 'move'}
instructions[969] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[970] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[971] = {6'd3, 7'd38, 7'd25, 32'd0};//{'dest': 38, 'src': 25, 'op': 'move'}
instructions[972] = {6'd3, 7'd39, 7'd24, 32'd0};//{'dest': 39, 'src': 24, 'op': 'move'}
instructions[973] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[974] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[975] = {6'd27, 7'd37, 7'd38, 32'd39};//{'srcb': 39, 'src': 38, 'dest': 37, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[976] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[977] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[978] = {6'd12, 7'd0, 7'd37, 32'd1022};//{'src': 37, 'label': 1022, 'op': 'jmp_if_false'}
instructions[979] = {6'd30, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'input': 'socket', 'op': 'read'}
instructions[980] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[981] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[982] = {6'd3, 7'd28, 7'd37, 32'd0};//{'dest': 28, 'src': 37, 'op': 'move'}
instructions[983] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[984] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[985] = {6'd3, 7'd47, 7'd28, 32'd0};//{'dest': 47, 'src': 28, 'op': 'move'}
instructions[986] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[987] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[988] = {6'd31, 7'd41, 7'd47, 32'd8};//{'src': 47, 'right': 8, 'dest': 41, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[989] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[990] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[991] = {6'd32, 7'd37, 7'd41, 32'd255};//{'src': 41, 'right': 255, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[992] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[993] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[994] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[995] = {6'd8, 7'd39, 7'd38, 32'd27};//{'dest': 39, 'src': 38, 'srcb': 27, 'signed': False, 'op': '+'}
instructions[996] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[997] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[998] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[999] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1000] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1001] = {6'd3, 7'd41, 7'd28, 32'd0};//{'dest': 41, 'src': 28, 'op': 'move'}
instructions[1002] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1003] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1004] = {6'd32, 7'd37, 7'd41, 32'd255};//{'src': 41, 'right': 255, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1005] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1006] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1007] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1008] = {6'd8, 7'd39, 7'd38, 32'd27};//{'dest': 39, 'src': 38, 'srcb': 27, 'signed': False, 'op': '+'}
instructions[1009] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1010] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1011] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1012] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1013] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1014] = {6'd3, 7'd38, 7'd25, 32'd0};//{'dest': 38, 'src': 25, 'op': 'move'}
instructions[1015] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1016] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1017] = {6'd13, 7'd37, 7'd38, 32'd2};//{'src': 38, 'right': 2, 'dest': 37, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1018] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1019] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1020] = {6'd3, 7'd25, 7'd37, 32'd0};//{'dest': 25, 'src': 37, 'op': 'move'}
instructions[1021] = {6'd14, 7'd0, 7'd0, 32'd969};//{'label': 969, 'op': 'goto'}
instructions[1022] = {6'd0, 7'd39, 7'd0, 32'd0};//{'dest': 39, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1023] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1024] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1025] = {6'd8, 7'd41, 7'd39, 32'd27};//{'dest': 41, 'src': 39, 'srcb': 27, 'signed': False, 'op': '+'}
instructions[1026] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1027] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1028] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209467464, 'op': 'memory_read_request'}
instructions[1029] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1030] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209467464, 'op': 'memory_read_wait'}
instructions[1031] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361209467464, 'element_size': 2, 'op': 'memory_read'}
instructions[1032] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1033] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1034] = {6'd23, 7'd37, 7'd38, 32'd71};//{'src': 38, 'right': 71, 'dest': 37, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1035] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1036] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1037] = {6'd12, 7'd0, 7'd37, 32'd1051};//{'src': 37, 'label': 1051, 'op': 'jmp_if_false'}
instructions[1038] = {6'd0, 7'd39, 7'd0, 32'd1};//{'dest': 39, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1039] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1040] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1041] = {6'd8, 7'd41, 7'd39, 32'd27};//{'dest': 41, 'src': 39, 'srcb': 27, 'signed': False, 'op': '+'}
instructions[1042] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1043] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1044] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209467752, 'op': 'memory_read_request'}
instructions[1045] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1046] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209467752, 'op': 'memory_read_wait'}
instructions[1047] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361209467752, 'element_size': 2, 'op': 'memory_read'}
instructions[1048] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1049] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1050] = {6'd23, 7'd37, 7'd38, 32'd69};//{'src': 38, 'right': 69, 'dest': 37, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1051] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1052] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1053] = {6'd12, 7'd0, 7'd37, 32'd1067};//{'src': 37, 'label': 1067, 'op': 'jmp_if_false'}
instructions[1054] = {6'd0, 7'd39, 7'd0, 32'd2};//{'dest': 39, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1055] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1056] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1057] = {6'd8, 7'd41, 7'd39, 32'd27};//{'dest': 41, 'src': 39, 'srcb': 27, 'signed': False, 'op': '+'}
instructions[1058] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1059] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1060] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209468112, 'op': 'memory_read_request'}
instructions[1061] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1062] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209468112, 'op': 'memory_read_wait'}
instructions[1063] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361209468112, 'element_size': 2, 'op': 'memory_read'}
instructions[1064] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1065] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1066] = {6'd23, 7'd37, 7'd38, 32'd84};//{'src': 38, 'right': 84, 'dest': 37, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1067] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1068] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1069] = {6'd12, 7'd0, 7'd37, 32'd1083};//{'src': 37, 'label': 1083, 'op': 'jmp_if_false'}
instructions[1070] = {6'd0, 7'd39, 7'd0, 32'd3};//{'dest': 39, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1071] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1072] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1073] = {6'd8, 7'd41, 7'd39, 32'd27};//{'dest': 41, 'src': 39, 'srcb': 27, 'signed': False, 'op': '+'}
instructions[1074] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1075] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1076] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209468472, 'op': 'memory_read_request'}
instructions[1077] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1078] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209468472, 'op': 'memory_read_wait'}
instructions[1079] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361209468472, 'element_size': 2, 'op': 'memory_read'}
instructions[1080] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1081] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1082] = {6'd23, 7'd37, 7'd38, 32'd32};//{'src': 38, 'right': 32, 'dest': 37, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1083] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1084] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1085] = {6'd12, 7'd0, 7'd37, 32'd1099};//{'src': 37, 'label': 1099, 'op': 'jmp_if_false'}
instructions[1086] = {6'd0, 7'd39, 7'd0, 32'd4};//{'dest': 39, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1087] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1088] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1089] = {6'd8, 7'd41, 7'd39, 32'd27};//{'dest': 41, 'src': 39, 'srcb': 27, 'signed': False, 'op': '+'}
instructions[1090] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1091] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1092] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209468832, 'op': 'memory_read_request'}
instructions[1093] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1094] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209468832, 'op': 'memory_read_wait'}
instructions[1095] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361209468832, 'element_size': 2, 'op': 'memory_read'}
instructions[1096] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1097] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1098] = {6'd23, 7'd37, 7'd38, 32'd47};//{'src': 38, 'right': 47, 'dest': 37, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1099] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1100] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1101] = {6'd12, 7'd0, 7'd37, 32'd1131};//{'src': 37, 'label': 1131, 'op': 'jmp_if_false'}
instructions[1102] = {6'd0, 7'd39, 7'd0, 32'd5};//{'dest': 39, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1103] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1104] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1105] = {6'd8, 7'd41, 7'd39, 32'd27};//{'dest': 41, 'src': 39, 'srcb': 27, 'signed': False, 'op': '+'}
instructions[1106] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1107] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1108] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209473432, 'op': 'memory_read_request'}
instructions[1109] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1110] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209473432, 'op': 'memory_read_wait'}
instructions[1111] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361209473432, 'element_size': 2, 'op': 'memory_read'}
instructions[1112] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1113] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1114] = {6'd23, 7'd37, 7'd38, 32'd63};//{'src': 38, 'right': 63, 'dest': 37, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1115] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1116] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1117] = {6'd34, 7'd0, 7'd37, 32'd1131};//{'src': 37, 'label': 1131, 'op': 'jmp_if_true'}
instructions[1118] = {6'd0, 7'd39, 7'd0, 32'd5};//{'dest': 39, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1119] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1120] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1121] = {6'd8, 7'd41, 7'd39, 32'd27};//{'dest': 41, 'src': 39, 'srcb': 27, 'signed': False, 'op': '+'}
instructions[1122] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1123] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1124] = {6'd9, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209473720, 'op': 'memory_read_request'}
instructions[1125] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1126] = {6'd10, 7'd0, 7'd41, 32'd0};//{'element_size': 2, 'src': 41, 'sequence': 140361209473720, 'op': 'memory_read_wait'}
instructions[1127] = {6'd11, 7'd38, 7'd41, 32'd0};//{'dest': 38, 'src': 41, 'sequence': 140361209473720, 'element_size': 2, 'op': 'memory_read'}
instructions[1128] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1129] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1130] = {6'd23, 7'd37, 7'd38, 32'd32};//{'src': 38, 'right': 32, 'dest': 37, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1131] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1132] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1133] = {6'd12, 7'd0, 7'd37, 32'd1711};//{'src': 37, 'label': 1711, 'op': 'jmp_if_false'}
instructions[1134] = {6'd0, 7'd37, 7'd0, 32'd5};//{'dest': 37, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1135] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1136] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1137] = {6'd3, 7'd32, 7'd37, 32'd0};//{'dest': 32, 'src': 37, 'op': 'move'}
instructions[1138] = {6'd3, 7'd48, 7'd27, 32'd0};//{'dest': 48, 'src': 27, 'op': 'move'}
instructions[1139] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1140] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1141] = {6'd3, 7'd16, 7'd48, 32'd0};//{'dest': 16, 'src': 48, 'op': 'move'}
instructions[1142] = {6'd0, 7'd38, 7'd0, 32'd32};//{'dest': 38, 'literal': 32, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1143] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1144] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1145] = {6'd3, 7'd17, 7'd38, 32'd0};//{'dest': 17, 'src': 38, 'op': 'move'}
instructions[1146] = {6'd3, 7'd38, 7'd32, 32'd0};//{'dest': 38, 'src': 32, 'op': 'move'}
instructions[1147] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1148] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1149] = {6'd3, 7'd18, 7'd38, 32'd0};//{'dest': 18, 'src': 38, 'op': 'move'}
instructions[1150] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1151] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1152] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1153] = {6'd3, 7'd19, 7'd38, 32'd0};//{'dest': 19, 'src': 38, 'op': 'move'}
instructions[1154] = {6'd1, 7'd14, 7'd0, 32'd832};//{'dest': 14, 'label': 832, 'op': 'jmp_and_link'}
instructions[1155] = {6'd3, 7'd37, 7'd15, 32'd0};//{'dest': 37, 'src': 15, 'op': 'move'}
instructions[1156] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1157] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1158] = {6'd3, 7'd33, 7'd37, 32'd0};//{'dest': 33, 'src': 37, 'op': 'move'}
instructions[1159] = {6'd0, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1160] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1161] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1162] = {6'd3, 7'd31, 7'd37, 32'd0};//{'dest': 31, 'src': 37, 'op': 'move'}
instructions[1163] = {6'd3, 7'd48, 7'd27, 32'd0};//{'dest': 48, 'src': 27, 'op': 'move'}
instructions[1164] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1165] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1166] = {6'd3, 7'd16, 7'd48, 32'd0};//{'dest': 16, 'src': 48, 'op': 'move'}
instructions[1167] = {6'd0, 7'd39, 7'd0, 32'd65};//{'dest': 39, 'literal': 65, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1168] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1169] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1170] = {6'd3, 7'd17, 7'd39, 32'd0};//{'dest': 17, 'src': 39, 'op': 'move'}
instructions[1171] = {6'd3, 7'd39, 7'd32, 32'd0};//{'dest': 39, 'src': 32, 'op': 'move'}
instructions[1172] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1173] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1174] = {6'd3, 7'd18, 7'd39, 32'd0};//{'dest': 18, 'src': 39, 'op': 'move'}
instructions[1175] = {6'd3, 7'd39, 7'd33, 32'd0};//{'dest': 39, 'src': 33, 'op': 'move'}
instructions[1176] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1177] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1178] = {6'd3, 7'd19, 7'd39, 32'd0};//{'dest': 19, 'src': 39, 'op': 'move'}
instructions[1179] = {6'd1, 7'd14, 7'd0, 32'd832};//{'dest': 14, 'label': 832, 'op': 'jmp_and_link'}
instructions[1180] = {6'd3, 7'd38, 7'd15, 32'd0};//{'dest': 38, 'src': 15, 'op': 'move'}
instructions[1181] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1182] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1183] = {6'd35, 7'd37, 7'd38, -32'd1};//{'src': 38, 'right': -1, 'dest': 37, 'signed': True, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1184] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1185] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1186] = {6'd12, 7'd0, 7'd37, 32'd1195};//{'src': 37, 'label': 1195, 'op': 'jmp_if_false'}
instructions[1187] = {6'd3, 7'd38, 7'd31, 32'd0};//{'dest': 38, 'src': 31, 'op': 'move'}
instructions[1188] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1189] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1190] = {6'd18, 7'd37, 7'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1191] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1192] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1193] = {6'd3, 7'd31, 7'd37, 32'd0};//{'dest': 31, 'src': 37, 'op': 'move'}
instructions[1194] = {6'd14, 7'd0, 7'd0, 32'd1195};//{'label': 1195, 'op': 'goto'}
instructions[1195] = {6'd3, 7'd48, 7'd27, 32'd0};//{'dest': 48, 'src': 27, 'op': 'move'}
instructions[1196] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1197] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1198] = {6'd3, 7'd16, 7'd48, 32'd0};//{'dest': 16, 'src': 48, 'op': 'move'}
instructions[1199] = {6'd0, 7'd39, 7'd0, 32'd66};//{'dest': 39, 'literal': 66, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1200] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1201] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1202] = {6'd3, 7'd17, 7'd39, 32'd0};//{'dest': 17, 'src': 39, 'op': 'move'}
instructions[1203] = {6'd3, 7'd39, 7'd32, 32'd0};//{'dest': 39, 'src': 32, 'op': 'move'}
instructions[1204] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1205] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1206] = {6'd3, 7'd18, 7'd39, 32'd0};//{'dest': 18, 'src': 39, 'op': 'move'}
instructions[1207] = {6'd3, 7'd39, 7'd33, 32'd0};//{'dest': 39, 'src': 33, 'op': 'move'}
instructions[1208] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1209] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1210] = {6'd3, 7'd19, 7'd39, 32'd0};//{'dest': 19, 'src': 39, 'op': 'move'}
instructions[1211] = {6'd1, 7'd14, 7'd0, 32'd832};//{'dest': 14, 'label': 832, 'op': 'jmp_and_link'}
instructions[1212] = {6'd3, 7'd38, 7'd15, 32'd0};//{'dest': 38, 'src': 15, 'op': 'move'}
instructions[1213] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1214] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1215] = {6'd35, 7'd37, 7'd38, -32'd1};//{'src': 38, 'right': -1, 'dest': 37, 'signed': True, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1216] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1217] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1218] = {6'd12, 7'd0, 7'd37, 32'd1227};//{'src': 37, 'label': 1227, 'op': 'jmp_if_false'}
instructions[1219] = {6'd3, 7'd38, 7'd31, 32'd0};//{'dest': 38, 'src': 31, 'op': 'move'}
instructions[1220] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1221] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1222] = {6'd18, 7'd37, 7'd38, 32'd2};//{'src': 38, 'right': 2, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1223] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1224] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1225] = {6'd3, 7'd31, 7'd37, 32'd0};//{'dest': 31, 'src': 37, 'op': 'move'}
instructions[1226] = {6'd14, 7'd0, 7'd0, 32'd1227};//{'label': 1227, 'op': 'goto'}
instructions[1227] = {6'd3, 7'd48, 7'd27, 32'd0};//{'dest': 48, 'src': 27, 'op': 'move'}
instructions[1228] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1229] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1230] = {6'd3, 7'd16, 7'd48, 32'd0};//{'dest': 16, 'src': 48, 'op': 'move'}
instructions[1231] = {6'd0, 7'd39, 7'd0, 32'd67};//{'dest': 39, 'literal': 67, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1232] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1233] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1234] = {6'd3, 7'd17, 7'd39, 32'd0};//{'dest': 17, 'src': 39, 'op': 'move'}
instructions[1235] = {6'd3, 7'd39, 7'd32, 32'd0};//{'dest': 39, 'src': 32, 'op': 'move'}
instructions[1236] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1237] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1238] = {6'd3, 7'd18, 7'd39, 32'd0};//{'dest': 18, 'src': 39, 'op': 'move'}
instructions[1239] = {6'd3, 7'd39, 7'd33, 32'd0};//{'dest': 39, 'src': 33, 'op': 'move'}
instructions[1240] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1241] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1242] = {6'd3, 7'd19, 7'd39, 32'd0};//{'dest': 19, 'src': 39, 'op': 'move'}
instructions[1243] = {6'd1, 7'd14, 7'd0, 32'd832};//{'dest': 14, 'label': 832, 'op': 'jmp_and_link'}
instructions[1244] = {6'd3, 7'd38, 7'd15, 32'd0};//{'dest': 38, 'src': 15, 'op': 'move'}
instructions[1245] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1246] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1247] = {6'd35, 7'd37, 7'd38, -32'd1};//{'src': 38, 'right': -1, 'dest': 37, 'signed': True, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1248] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1249] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1250] = {6'd12, 7'd0, 7'd37, 32'd1259};//{'src': 37, 'label': 1259, 'op': 'jmp_if_false'}
instructions[1251] = {6'd3, 7'd38, 7'd31, 32'd0};//{'dest': 38, 'src': 31, 'op': 'move'}
instructions[1252] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1253] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1254] = {6'd18, 7'd37, 7'd38, 32'd4};//{'src': 38, 'right': 4, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1255] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1256] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1257] = {6'd3, 7'd31, 7'd37, 32'd0};//{'dest': 31, 'src': 37, 'op': 'move'}
instructions[1258] = {6'd14, 7'd0, 7'd0, 32'd1259};//{'label': 1259, 'op': 'goto'}
instructions[1259] = {6'd3, 7'd48, 7'd27, 32'd0};//{'dest': 48, 'src': 27, 'op': 'move'}
instructions[1260] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1261] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1262] = {6'd3, 7'd16, 7'd48, 32'd0};//{'dest': 16, 'src': 48, 'op': 'move'}
instructions[1263] = {6'd0, 7'd39, 7'd0, 32'd68};//{'dest': 39, 'literal': 68, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1264] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1265] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1266] = {6'd3, 7'd17, 7'd39, 32'd0};//{'dest': 17, 'src': 39, 'op': 'move'}
instructions[1267] = {6'd3, 7'd39, 7'd32, 32'd0};//{'dest': 39, 'src': 32, 'op': 'move'}
instructions[1268] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1269] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1270] = {6'd3, 7'd18, 7'd39, 32'd0};//{'dest': 18, 'src': 39, 'op': 'move'}
instructions[1271] = {6'd3, 7'd39, 7'd33, 32'd0};//{'dest': 39, 'src': 33, 'op': 'move'}
instructions[1272] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1273] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1274] = {6'd3, 7'd19, 7'd39, 32'd0};//{'dest': 19, 'src': 39, 'op': 'move'}
instructions[1275] = {6'd1, 7'd14, 7'd0, 32'd832};//{'dest': 14, 'label': 832, 'op': 'jmp_and_link'}
instructions[1276] = {6'd3, 7'd38, 7'd15, 32'd0};//{'dest': 38, 'src': 15, 'op': 'move'}
instructions[1277] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1278] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1279] = {6'd35, 7'd37, 7'd38, -32'd1};//{'src': 38, 'right': -1, 'dest': 37, 'signed': True, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1280] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1281] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1282] = {6'd12, 7'd0, 7'd37, 32'd1291};//{'src': 37, 'label': 1291, 'op': 'jmp_if_false'}
instructions[1283] = {6'd3, 7'd38, 7'd31, 32'd0};//{'dest': 38, 'src': 31, 'op': 'move'}
instructions[1284] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1285] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1286] = {6'd18, 7'd37, 7'd38, 32'd8};//{'src': 38, 'right': 8, 'dest': 37, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1287] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1288] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1289] = {6'd3, 7'd31, 7'd37, 32'd0};//{'dest': 31, 'src': 37, 'op': 'move'}
instructions[1290] = {6'd14, 7'd0, 7'd0, 32'd1291};//{'label': 1291, 'op': 'goto'}
instructions[1291] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1292] = {6'd3, 7'd37, 7'd31, 32'd0};//{'dest': 37, 'src': 31, 'op': 'move'}
instructions[1293] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1294] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1295] = {6'd36, 7'd0, 7'd37, 32'd0};//{'src': 37, 'output': 'leds', 'op': 'write'}
instructions[1296] = {6'd37, 7'd38, 7'd0, 32'd0};//{'dest': 38, 'input': 'switches', 'op': 'read'}
instructions[1297] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1298] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1299] = {6'd38, 7'd37, 7'd38, 32'd0};//{'dest': 37, 'src': 38, 'op': '~'}
instructions[1300] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1301] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1302] = {6'd3, 7'd29, 7'd37, 32'd0};//{'dest': 29, 'src': 37, 'op': 'move'}
instructions[1303] = {6'd3, 7'd49, 7'd34, 32'd0};//{'dest': 49, 'src': 34, 'op': 'move'}
instructions[1304] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1305] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1306] = {6'd3, 7'd16, 7'd49, 32'd0};//{'dest': 16, 'src': 49, 'op': 'move'}
instructions[1307] = {6'd0, 7'd38, 7'd0, 32'd59};//{'dest': 38, 'literal': 59, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1308] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1309] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1310] = {6'd3, 7'd17, 7'd38, 32'd0};//{'dest': 17, 'src': 38, 'op': 'move'}
instructions[1311] = {6'd0, 7'd38, 7'd0, 32'd0};//{'dest': 38, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1312] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1313] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1314] = {6'd3, 7'd18, 7'd38, 32'd0};//{'dest': 18, 'src': 38, 'op': 'move'}
instructions[1315] = {6'd0, 7'd38, 7'd0, 32'd1460};//{'dest': 38, 'literal': 1460, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1316] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1317] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1318] = {6'd3, 7'd19, 7'd38, 32'd0};//{'dest': 19, 'src': 38, 'op': 'move'}
instructions[1319] = {6'd1, 7'd14, 7'd0, 32'd832};//{'dest': 14, 'label': 832, 'op': 'jmp_and_link'}
instructions[1320] = {6'd3, 7'd37, 7'd15, 32'd0};//{'dest': 37, 'src': 15, 'op': 'move'}
instructions[1321] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1322] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1323] = {6'd3, 7'd26, 7'd37, 32'd0};//{'dest': 26, 'src': 37, 'op': 'move'}
instructions[1324] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1325] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1326] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1327] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1328] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1329] = {6'd13, 7'd37, 7'd38, 32'd2};//{'src': 38, 'right': 2, 'dest': 37, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1330] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1331] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1332] = {6'd3, 7'd26, 7'd37, 32'd0};//{'dest': 26, 'src': 37, 'op': 'move'}
instructions[1333] = {6'd3, 7'd38, 7'd29, 32'd0};//{'dest': 38, 'src': 29, 'op': 'move'}
instructions[1334] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1335] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1336] = {6'd32, 7'd37, 7'd38, 32'd128};//{'src': 38, 'right': 128, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1337] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1338] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1339] = {6'd12, 7'd0, 7'd37, 32'd1349};//{'src': 37, 'label': 1349, 'op': 'jmp_if_false'}
instructions[1340] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1341] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1342] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1343] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1344] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1345] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1346] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1347] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1348] = {6'd14, 7'd0, 7'd0, 32'd1357};//{'label': 1357, 'op': 'goto'}
instructions[1349] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1350] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1351] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1352] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1353] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1354] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1355] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1356] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1357] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1358] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1359] = {6'd3, 7'd38, 7'd29, 32'd0};//{'dest': 38, 'src': 29, 'op': 'move'}
instructions[1360] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1361] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1362] = {6'd32, 7'd37, 7'd38, 32'd64};//{'src': 38, 'right': 64, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1363] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1364] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1365] = {6'd12, 7'd0, 7'd37, 32'd1375};//{'src': 37, 'label': 1375, 'op': 'jmp_if_false'}
instructions[1366] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1367] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1368] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1369] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1370] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1371] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1372] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1373] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1374] = {6'd14, 7'd0, 7'd0, 32'd1383};//{'label': 1383, 'op': 'goto'}
instructions[1375] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1376] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1377] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1378] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1379] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1380] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1381] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1382] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1383] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1384] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1385] = {6'd3, 7'd38, 7'd29, 32'd0};//{'dest': 38, 'src': 29, 'op': 'move'}
instructions[1386] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1387] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1388] = {6'd32, 7'd37, 7'd38, 32'd32};//{'src': 38, 'right': 32, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1389] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1390] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1391] = {6'd12, 7'd0, 7'd37, 32'd1401};//{'src': 37, 'label': 1401, 'op': 'jmp_if_false'}
instructions[1392] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1393] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1394] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1395] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1396] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1397] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1398] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1399] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1400] = {6'd14, 7'd0, 7'd0, 32'd1409};//{'label': 1409, 'op': 'goto'}
instructions[1401] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1402] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1403] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1404] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1405] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1406] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1407] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1408] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1409] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1410] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1411] = {6'd3, 7'd38, 7'd29, 32'd0};//{'dest': 38, 'src': 29, 'op': 'move'}
instructions[1412] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1413] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1414] = {6'd32, 7'd37, 7'd38, 32'd16};//{'src': 38, 'right': 16, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1415] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1416] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1417] = {6'd12, 7'd0, 7'd37, 32'd1427};//{'src': 37, 'label': 1427, 'op': 'jmp_if_false'}
instructions[1418] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1419] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1420] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1421] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1422] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1423] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1424] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1425] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1426] = {6'd14, 7'd0, 7'd0, 32'd1435};//{'label': 1435, 'op': 'goto'}
instructions[1427] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1428] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1429] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1430] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1431] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1432] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1433] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1434] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1435] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1436] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1437] = {6'd3, 7'd38, 7'd29, 32'd0};//{'dest': 38, 'src': 29, 'op': 'move'}
instructions[1438] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1439] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1440] = {6'd32, 7'd37, 7'd38, 32'd8};//{'src': 38, 'right': 8, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1441] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1442] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1443] = {6'd12, 7'd0, 7'd37, 32'd1453};//{'src': 37, 'label': 1453, 'op': 'jmp_if_false'}
instructions[1444] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1445] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1446] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1447] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1448] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1449] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1450] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1451] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1452] = {6'd14, 7'd0, 7'd0, 32'd1461};//{'label': 1461, 'op': 'goto'}
instructions[1453] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1454] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1455] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1456] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1457] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1458] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1459] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1460] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1461] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1462] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1463] = {6'd3, 7'd38, 7'd29, 32'd0};//{'dest': 38, 'src': 29, 'op': 'move'}
instructions[1464] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1465] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1466] = {6'd32, 7'd37, 7'd38, 32'd4};//{'src': 38, 'right': 4, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1467] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1468] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1469] = {6'd12, 7'd0, 7'd37, 32'd1479};//{'src': 37, 'label': 1479, 'op': 'jmp_if_false'}
instructions[1470] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1471] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1472] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1473] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1474] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1475] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1476] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1477] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1478] = {6'd14, 7'd0, 7'd0, 32'd1487};//{'label': 1487, 'op': 'goto'}
instructions[1479] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1480] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1481] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1482] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1483] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1484] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1485] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1486] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1487] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1488] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1489] = {6'd3, 7'd38, 7'd29, 32'd0};//{'dest': 38, 'src': 29, 'op': 'move'}
instructions[1490] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1491] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1492] = {6'd32, 7'd37, 7'd38, 32'd2};//{'src': 38, 'right': 2, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1493] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1494] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1495] = {6'd12, 7'd0, 7'd37, 32'd1505};//{'src': 37, 'label': 1505, 'op': 'jmp_if_false'}
instructions[1496] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1497] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1498] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1499] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1500] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1501] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1502] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1503] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1504] = {6'd14, 7'd0, 7'd0, 32'd1513};//{'label': 1513, 'op': 'goto'}
instructions[1505] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1506] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1507] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1508] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1509] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1510] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1511] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1512] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1513] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1514] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1515] = {6'd3, 7'd38, 7'd29, 32'd0};//{'dest': 38, 'src': 29, 'op': 'move'}
instructions[1516] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1517] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1518] = {6'd32, 7'd37, 7'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1519] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1520] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1521] = {6'd12, 7'd0, 7'd37, 32'd1531};//{'src': 37, 'label': 1531, 'op': 'jmp_if_false'}
instructions[1522] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1523] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1524] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1525] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1526] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1527] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1528] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1529] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1530] = {6'd14, 7'd0, 7'd0, 32'd1539};//{'label': 1539, 'op': 'goto'}
instructions[1531] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1532] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1533] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1534] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1535] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1536] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1537] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1538] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1539] = {6'd40, 7'd38, 7'd0, 32'd0};//{'dest': 38, 'input': 'buttons', 'op': 'read'}
instructions[1540] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1541] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1542] = {6'd38, 7'd37, 7'd38, 32'd0};//{'dest': 37, 'src': 38, 'op': '~'}
instructions[1543] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1544] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1545] = {6'd3, 7'd30, 7'd37, 32'd0};//{'dest': 30, 'src': 37, 'op': 'move'}
instructions[1546] = {6'd3, 7'd49, 7'd34, 32'd0};//{'dest': 49, 'src': 34, 'op': 'move'}
instructions[1547] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1548] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1549] = {6'd3, 7'd16, 7'd49, 32'd0};//{'dest': 16, 'src': 49, 'op': 'move'}
instructions[1550] = {6'd0, 7'd38, 7'd0, 32'd59};//{'dest': 38, 'literal': 59, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1551] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1552] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1553] = {6'd3, 7'd17, 7'd38, 32'd0};//{'dest': 17, 'src': 38, 'op': 'move'}
instructions[1554] = {6'd3, 7'd39, 7'd26, 32'd0};//{'dest': 39, 'src': 26, 'op': 'move'}
instructions[1555] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1556] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1557] = {6'd13, 7'd38, 7'd39, 32'd1};//{'src': 39, 'right': 1, 'dest': 38, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1558] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1559] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1560] = {6'd3, 7'd18, 7'd38, 32'd0};//{'dest': 18, 'src': 38, 'op': 'move'}
instructions[1561] = {6'd0, 7'd38, 7'd0, 32'd1460};//{'dest': 38, 'literal': 1460, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1562] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1563] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1564] = {6'd3, 7'd19, 7'd38, 32'd0};//{'dest': 19, 'src': 38, 'op': 'move'}
instructions[1565] = {6'd1, 7'd14, 7'd0, 32'd832};//{'dest': 14, 'label': 832, 'op': 'jmp_and_link'}
instructions[1566] = {6'd3, 7'd37, 7'd15, 32'd0};//{'dest': 37, 'src': 15, 'op': 'move'}
instructions[1567] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1568] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1569] = {6'd3, 7'd26, 7'd37, 32'd0};//{'dest': 26, 'src': 37, 'op': 'move'}
instructions[1570] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1571] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1572] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1573] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1574] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1575] = {6'd13, 7'd37, 7'd38, 32'd2};//{'src': 38, 'right': 2, 'dest': 37, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1576] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1577] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1578] = {6'd3, 7'd26, 7'd37, 32'd0};//{'dest': 26, 'src': 37, 'op': 'move'}
instructions[1579] = {6'd3, 7'd38, 7'd30, 32'd0};//{'dest': 38, 'src': 30, 'op': 'move'}
instructions[1580] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1581] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1582] = {6'd32, 7'd37, 7'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1583] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1584] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1585] = {6'd12, 7'd0, 7'd37, 32'd1595};//{'src': 37, 'label': 1595, 'op': 'jmp_if_false'}
instructions[1586] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1587] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1588] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1589] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1590] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1591] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1592] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1593] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1594] = {6'd14, 7'd0, 7'd0, 32'd1603};//{'label': 1603, 'op': 'goto'}
instructions[1595] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1596] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1597] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1598] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1599] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1600] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1601] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1602] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1603] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1604] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1605] = {6'd3, 7'd38, 7'd30, 32'd0};//{'dest': 38, 'src': 30, 'op': 'move'}
instructions[1606] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1607] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1608] = {6'd32, 7'd37, 7'd38, 32'd2};//{'src': 38, 'right': 2, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1609] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1610] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1611] = {6'd12, 7'd0, 7'd37, 32'd1621};//{'src': 37, 'label': 1621, 'op': 'jmp_if_false'}
instructions[1612] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1613] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1614] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1615] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1616] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1617] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1618] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1619] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1620] = {6'd14, 7'd0, 7'd0, 32'd1629};//{'label': 1629, 'op': 'goto'}
instructions[1621] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1622] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1623] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1624] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1625] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1626] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1627] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1628] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1629] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1630] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1631] = {6'd3, 7'd38, 7'd30, 32'd0};//{'dest': 38, 'src': 30, 'op': 'move'}
instructions[1632] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1633] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1634] = {6'd32, 7'd37, 7'd38, 32'd4};//{'src': 38, 'right': 4, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1635] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1636] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1637] = {6'd12, 7'd0, 7'd37, 32'd1647};//{'src': 37, 'label': 1647, 'op': 'jmp_if_false'}
instructions[1638] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1639] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1640] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1641] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1642] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1643] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1644] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1645] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1646] = {6'd14, 7'd0, 7'd0, 32'd1655};//{'label': 1655, 'op': 'goto'}
instructions[1647] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1648] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1649] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1650] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1651] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1652] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1653] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1654] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1655] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1656] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1657] = {6'd3, 7'd38, 7'd30, 32'd0};//{'dest': 38, 'src': 30, 'op': 'move'}
instructions[1658] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1659] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1660] = {6'd32, 7'd37, 7'd38, 32'd8};//{'src': 38, 'right': 8, 'dest': 37, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1661] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1662] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1663] = {6'd12, 7'd0, 7'd37, 32'd1673};//{'src': 37, 'label': 1673, 'op': 'jmp_if_false'}
instructions[1664] = {6'd0, 7'd37, 7'd0, 32'd48};//{'dest': 37, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1665] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1666] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1667] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1668] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1669] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1670] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1671] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1672] = {6'd14, 7'd0, 7'd0, 32'd1681};//{'label': 1681, 'op': 'goto'}
instructions[1673] = {6'd0, 7'd37, 7'd0, 32'd49};//{'dest': 37, 'literal': 49, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1674] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1675] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1676] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1677] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1678] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1679] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1680] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1681] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1682] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1683] = {6'd0, 7'd37, 7'd0, 32'd32};//{'dest': 37, 'literal': 32, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1684] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1685] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1686] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1687] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1688] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1689] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1690] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1691] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1692] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1693] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1694] = {6'd0, 7'd37, 7'd0, 32'd32};//{'dest': 37, 'literal': 32, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1695] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1696] = {6'd3, 7'd38, 7'd26, 32'd0};//{'dest': 38, 'src': 26, 'op': 'move'}
instructions[1697] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1698] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1699] = {6'd39, 7'd39, 7'd38, 32'd34};//{'dest': 39, 'src': 38, 'srcb': 34, 'signed': True, 'op': '+'}
instructions[1700] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1701] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1702] = {6'd33, 7'd0, 7'd39, 32'd37};//{'srcb': 37, 'src': 39, 'element_size': 2, 'op': 'memory_write'}
instructions[1703] = {6'd3, 7'd37, 7'd26, 32'd0};//{'dest': 37, 'src': 26, 'op': 'move'}
instructions[1704] = {6'd13, 7'd26, 7'd26, 32'd1};//{'src': 26, 'right': 1, 'dest': 26, 'signed': False, 'op': '+', 'size': 2}
instructions[1705] = {6'd3, 7'd49, 7'd34, 32'd0};//{'dest': 49, 'src': 34, 'op': 'move'}
instructions[1706] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1707] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1708] = {6'd3, 7'd6, 7'd49, 32'd0};//{'dest': 6, 'src': 49, 'op': 'move'}
instructions[1709] = {6'd1, 7'd5, 7'd0, 32'd609};//{'dest': 5, 'label': 609, 'op': 'jmp_and_link'}
instructions[1710] = {6'd14, 7'd0, 7'd0, 32'd1712};//{'label': 1712, 'op': 'goto'}
instructions[1711] = {6'd1, 7'd2, 7'd0, 32'd571};//{'dest': 2, 'label': 571, 'op': 'jmp_and_link'}
instructions[1712] = {6'd14, 7'd0, 7'd0, 32'd957};//{'label': 957, 'op': 'goto'}
instructions[1713] = {6'd41, 7'd37, 7'd0, 32'd0};//{'dest': 37, 'input': 'rs232_rx', 'op': 'read'}
instructions[1714] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1715] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1716] = {6'd3, 7'd26, 7'd37, 32'd0};//{'dest': 26, 'src': 37, 'op': 'move'}
instructions[1717] = {6'd6, 7'd0, 7'd23, 32'd0};//{'src': 23, 'op': 'jmp_to_reg'}
end
//////////////////////////////////////////////////////////////////////////////
// CPU IMPLEMENTAION OF C PROCESS
//
// This section of the file contains a CPU implementing the C process.
always @(posedge clk)
begin
//implement memory for 2 byte x n arrays
if (memory_enable_2 == 1'b1) begin
memory_2[address_2] <= data_in_2;
end
data_out_2 <= memory_2[address_2];
memory_enable_2 <= 1'b0;
write_enable_2 <= 0;
//stage 0 instruction fetch
if (stage_0_enable) begin
stage_1_enable <= 1;
instruction_0 <= instructions[program_counter];
opcode_0 = instruction_0[51:46];
dest_0 = instruction_0[45:39];
src_0 = instruction_0[38:32];
srcb_0 = instruction_0[6:0];
literal_0 = instruction_0[31:0];
if(write_enable_2) begin
registers[dest_2] <= result_2;
end
program_counter_0 <= program_counter;
program_counter <= program_counter + 1;
end
//stage 1 opcode fetch
if (stage_1_enable) begin
stage_2_enable <= 1;
register_1 <= registers[src_0];
registerb_1 <= registers[srcb_0];
dest_1 <= dest_0;
literal_1 <= literal_0;
opcode_1 <= opcode_0;
program_counter_1 <= program_counter_0;
end
//stage 2 opcode fetch
if (stage_2_enable) begin
dest_2 <= dest_1;
case(opcode_1)
16'd0:
begin
result_2 <= literal_1;
write_enable_2 <= 1;
end
16'd1:
begin
program_counter <= literal_1;
result_2 <= program_counter_1 + 1;
write_enable_2 <= 1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd2:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd3:
begin
result_2 <= register_1;
write_enable_2 <= 1;
end
16'd5:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_socket_stb <= 1'b1;
s_output_socket <= register_1;
end
16'd6:
begin
program_counter <= register_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd7:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_rs232_tx_stb <= 1'b1;
s_output_rs232_tx <= register_1;
end
16'd8:
begin
result_2 <= $unsigned(register_1) + $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd9:
begin
address_2 <= register_1;
end
16'd11:
begin
result_2 <= data_out_2;
write_enable_2 <= 1;
end
16'd12:
begin
if (register_1 == 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd13:
begin
result_2 <= $unsigned(register_1) + $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd14:
begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd15:
begin
result_2 <= $unsigned(register_1) >= $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd16:
begin
result_2 <= $unsigned(register_1) - $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd17:
begin
result_2 <= $unsigned(register_1) | $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd18:
begin
result_2 <= $unsigned(register_1) | $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd19:
begin
result_2 <= $signed(register_1) >= $signed(literal_1);
write_enable_2 <= 1;
end
16'd20:
begin
result_2 <= $signed(literal_1) - $signed(register_1);
write_enable_2 <= 1;
end
16'd21:
begin
result_2 <= $signed(register_1) << $signed(literal_1);
write_enable_2 <= 1;
end
16'd22:
begin
result_2 <= $signed(register_1) & $signed(literal_1);
write_enable_2 <= 1;
end
16'd23:
begin
result_2 <= $unsigned(register_1) == $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd24:
begin
result_2 <= $unsigned(literal_1) | $unsigned(register_1);
write_enable_2 <= 1;
end
16'd25:
begin
result_2 <= $unsigned(register_1) > $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd26:
begin
result_2 <= $unsigned(register_1) < $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd27:
begin
result_2 <= $unsigned(register_1) < $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd28:
begin
result_2 <= $unsigned(register_1) == $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd29:
begin
result_2 <= $signed(register_1) + $signed(literal_1);
write_enable_2 <= 1;
end
16'd30:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_socket_ack <= 1'b1;
end
16'd31:
begin
result_2 <= $unsigned(register_1) >> $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd32:
begin
result_2 <= $unsigned(register_1) & $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd33:
begin
address_2 <= register_1;
data_in_2 <= registerb_1;
memory_enable_2 <= 1'b1;
end
16'd34:
begin
if (register_1 != 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd35:
begin
result_2 <= $signed(register_1) != $signed(literal_1);
write_enable_2 <= 1;
end
16'd36:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_leds_stb <= 1'b1;
s_output_leds <= register_1;
end
16'd37:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_switches_ack <= 1'b1;
end
16'd38:
begin
result_2 <= ~register_1;
write_enable_2 <= 1;
end
16'd39:
begin
result_2 <= $signed(register_1) + $signed(registerb_1);
write_enable_2 <= 1;
end
16'd40:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_buttons_ack <= 1'b1;
end
16'd41:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_rs232_rx_ack <= 1'b1;
end
endcase
end
if (s_output_socket_stb == 1'b1 && output_socket_ack == 1'b1) begin
s_output_socket_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_rs232_tx_stb == 1'b1 && output_rs232_tx_ack == 1'b1) begin
s_output_rs232_tx_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_socket_ack == 1'b1 && input_socket_stb == 1'b1) begin
result_2 <= input_socket;
write_enable_2 <= 1;
s_input_socket_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_leds_stb == 1'b1 && output_leds_ack == 1'b1) begin
s_output_leds_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_switches_ack == 1'b1 && input_switches_stb == 1'b1) begin
result_2 <= input_switches;
write_enable_2 <= 1;
s_input_switches_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_buttons_ack == 1'b1 && input_buttons_stb == 1'b1) begin
result_2 <= input_buttons;
write_enable_2 <= 1;
s_input_buttons_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_rs232_rx_ack == 1'b1 && input_rs232_rx_stb == 1'b1) begin
result_2 <= input_rs232_rx;
write_enable_2 <= 1;
s_input_rs232_rx_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (timer == 0) begin
if (timer_enable) begin
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
timer_enable <= 0;
end
end else begin
timer <= timer - 1;
end
if (rst == 1'b1) begin
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
timer <= 0;
timer_enable <= 0;
program_counter <= 0;
s_input_switches_ack <= 0;
s_input_buttons_ack <= 0;
s_input_socket_ack <= 0;
s_input_rs232_rx_ack <= 0;
s_output_rs232_tx_stb <= 0;
s_output_leds_stb <= 0;
s_output_socket_stb <= 0;
end
end
assign input_switches_ack = s_input_switches_ack;
assign input_buttons_ack = s_input_buttons_ack;
assign input_socket_ack = s_input_socket_ack;
assign input_rs232_rx_ack = s_input_rs232_rx_ack;
assign output_rs232_tx_stb = s_output_rs232_tx_stb;
assign output_rs232_tx = s_output_rs232_tx;
assign output_leds_stb = s_output_leds_stb;
assign output_leds = s_output_leds;
assign output_socket_stb = s_output_socket_stb;
assign output_socket = s_output_socket;
endmodule
|
//----------------------------------------------------------------------------
module machine( inc_pc, load_acc, load_pc, rd,wr, load_ir,
datactl_ena, halt, clk1, zero, ena, opcode );
output inc_pc, load_acc, load_pc, rd, wr, load_ir;
output datactl_ena, halt;
input clk1, zero, ena;
input [2:0] opcode;
reg inc_pc, load_acc, load_pc, rd, wr, load_ir;
reg datactl_ena, halt;
reg [2:0] state;
parameter HLT = 3 'b000,
SKZ = 3 'b001,
ADD = 3 'b010,
ANDD = 3 'b011,
XORR = 3 'b100,
LDA = 3 'b101,
STO = 3 'b110,
JMP = 3 'b111;
always @( negedge clk1 )
begin
if ( !ena ) //???????RST???????
begin
state<=3'b000;
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
ctl_cycle;
end
//-----------------begin of task ctl_cycle---------
task ctl_cycle;
begin
casex(state)
3'b000: //load high 8bits in struction
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0001;
{wr,load_ir,datactl_ena,halt}<=4'b0100;
state<=3'b001;
end
3'b001: //pc increased by one then load low 8bits instruction
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1001;
{wr,load_ir,datactl_ena,halt}<=4'b0100;
state<=3'b010;
end
3'b010: //idle
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
state<=3'b011;
end
3'b011: //next instruction address setup ?????????
begin
if(opcode==HLT) //?????HLT
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1000;
{wr,load_ir,datactl_ena,halt}<=4'b0001;
end
else
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
state<=3'b100;
end
3'b100: //fetch oprand
begin
if(opcode==JMP)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0010;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
if( opcode==ADD || opcode==ANDD ||
opcode==XORR || opcode==LDA)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0001;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
if(opcode==STO)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0010;
end
else
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
state<=3'b101;
end
3'b101: //operation
begin
if ( opcode==ADD||opcode==ANDD||
opcode==XORR||opcode==LDA )
begin //?????????????????
{inc_pc,load_acc,load_pc,rd}<=4'b0101;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
if( opcode==SKZ && zero==1)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
if(opcode==JMP)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1010;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
if(opcode==STO)
begin
//???????wr?1????RAM?
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b1010;
end
else
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
state<=3'b110;
end
3'b110: //idle
begin
if ( opcode==STO )
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0010;
end
else
if ( opcode==ADD||opcode==ANDD||
opcode==XORR||opcode==LDA)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0001;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
state<=3'b111;
end
3'b111: //
begin
if( opcode==SKZ && zero==1 )
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
state<=3'b000;
end
default:
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
state<=3'b000;
end
endcase
end
endtask
//-----------------end of task ctl_cycle---------
endmodule
//------------------------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311AI_TB_V
`define SKY130_FD_SC_HD__O311AI_TB_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o311ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__o311ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311AI_TB_V
|
module in_order_cpu(
input clk, rst,
input switch_program,
input [31:0] SPART_pc,
output spart_wrt_en,
output [31:0] spart_wrt_add,
output [31:0] spart_wrt_data
);
wire changeFlow; //from EX stage, when branch or jump or branch mis_prediction
wire [31:0] jb_addr; //from EX stage, provide address for jump or branch
wire [31:0] instr_IF; //instruction coming from I-mem
wire [31:0] pc_1_IF; //pc+1 from IF stage
wire flush_ID, flush_EX, stall_PC_ID;
wire taken, not_taken; //from EX stage, change the state of predictor
wire pred_taken;
wire halt;
IF_stage i_IF_stage(.instr(instr_IF), .pc_1(pc_1_IF), .jb_addr(jb_addr), .changeFlow(changeFlow),
.clk(clk), .rst(rst), .stall_PC(stall_PC_ID), .taken(taken), .not_taken(not_taken),
.pred_taken(pred_taken), .switch_program(switch_program), .SPART_pc(SPART_pc),
.halt(halt));
reg [31:0] instr_IF_ID; //the IF_ID pipe reg for instr
reg [31:0] pc_1_IF_ID; //the IF_ID pipe reg for pc_1
reg pred_taken_IF_ID;
//IF/ID pipeline register
always @(posedge clk or negedge rst) begin
if (!rst)
{instr_IF_ID, pc_1_IF_ID, pred_taken_IF_ID} <= 0;
else if (flush_ID || (halt && !switch_program && !stall_PC_ID))
{instr_IF_ID, pc_1_IF_ID, pred_taken_IF_ID} <= 0;
else if (!stall_PC_ID)
{instr_IF_ID, pc_1_IF_ID, pred_taken_IF_ID} <= {instr_IF, pc_1_IF, pred_taken};
end
//register data
wire [31:0] rs_data, rt_data;
//signals from WB
wire [31:0] wdata_WB;
wire [4:0] waddr_WB;
reg reg_wen_WB;
//control signals
//control signals for EX stage
wire writeRd, ldic, isSignEx, immed;
wire alu_ctrl0, alu_ctrl1, alu_ctrl2, alu_ctrl3;
wire isJump, isJR;
wire rs_read, rt_read;
//control signals for MEM stage
wire mem_ren, mem_wen;
//contorl signals for WB stage
wire lw, link, reg_wen;
//special control signals
wire str_ccnt, str_icnt, stp_cnt;
wire inc_instr;
//ID_stage
ID_stage i_ID_stage(
.instr(instr_IF_ID),
.clk(clk),
.rst(rst),
.wdata(wdata_WB),
.waddr(waddr_WB),
.reg_wen_WB(reg_wen_WB),
.rs_data(rs_data),
.rt_data(rt_data),
.rs_read(rs_read),
.rt_read(rt_read),
.writeRd(writeRd),
.ldic(ldic),
.isSignEx(isSignEx),
.immed(immed),
.alu_ctrl0(alu_ctrl0),
.alu_ctrl1(alu_ctrl1),
.alu_ctrl2(alu_ctrl2),
.alu_ctrl3(alu_ctrl3),
.isJump(isJump),
.isJR(isJR),
.mem_ren(mem_ren),
.mem_wen(mem_wen),
.lw(lw),
.link(link),
.reg_wen(reg_wen),
.str_ccnt(str_ccnt),
.str_icnt(str_icnt),
.stp_cnt(stp_cnt),
.inc_instr(inc_instr));
//from IF/ID pipeline
reg [31:0] instr_ID_EX; //the IF_ID pipe reg for instr
reg [31:0] pc_1_ID_EX; //the IF_ID pipe reg for pc_1
//control signals for EX stage
reg writeRd_ID_EX, ldic_ID_EX, isSignEx_ID_EX, immed_ID_EX;
reg alu_ctrl0_ID_EX, alu_ctrl1_ID_EX, alu_ctrl2_ID_EX, alu_ctrl3_ID_EX;
reg isJump_ID_EX, isJR_ID_EX;
//control signals for MEM stage
reg mem_ren_ID_EX, mem_wen_ID_EX;
//contorl signals for WB stage
reg lw_ID_EX, link_ID_EX, reg_wen_ID_EX;
reg str_icnt_ID_EX, stp_cnt_ID_EX; //counter control signal
reg inc_instr_ID_EX;
reg pred_taken_ID_EX;
reg [31:0] rs_data_ID_EX, rt_data_ID_EX;
//ID/EX pipeline for register data
always @(posedge clk or negedge rst) begin
if (!rst) begin
{rs_data_ID_EX, rt_data_ID_EX} <= 0;
end
else begin
{rs_data_ID_EX, rt_data_ID_EX} <= {rs_data, rt_data};
end
end
//ID/EX pipeline for control signals
always @(posedge clk or negedge rst) begin
if (!rst) begin
{writeRd_ID_EX, ldic_ID_EX, isSignEx_ID_EX, immed_ID_EX} <= 0;
{alu_ctrl0_ID_EX, alu_ctrl1_ID_EX, alu_ctrl2_ID_EX, alu_ctrl3_ID_EX} <= 0;
{isJump_ID_EX, isJR_ID_EX} <= 0;
{mem_ren_ID_EX, mem_wen_ID_EX} <= 0;
{lw_ID_EX, link_ID_EX, reg_wen_ID_EX} <= 0;
{instr_ID_EX, pc_1_ID_EX} <= 0;
{str_icnt_ID_EX, stp_cnt_ID_EX, inc_instr_ID_EX} <= 0;
pred_taken_ID_EX <= 0;
end
else if (flush_EX) begin
{writeRd_ID_EX, ldic_ID_EX, isSignEx_ID_EX, immed_ID_EX} <= 0;
{alu_ctrl0_ID_EX, alu_ctrl1_ID_EX, alu_ctrl2_ID_EX, alu_ctrl3_ID_EX} <= 0;
{isJump_ID_EX, isJR_ID_EX} <= 0;
{mem_ren_ID_EX, mem_wen_ID_EX} <= 0;
{lw_ID_EX, link_ID_EX, reg_wen_ID_EX} <= 0;
{instr_ID_EX, pc_1_ID_EX} <= 0;
{str_icnt_ID_EX, stp_cnt_ID_EX, inc_instr_ID_EX} <= 0;
pred_taken_ID_EX <= 0;
end
else begin
{writeRd_ID_EX, ldic_ID_EX, isSignEx_ID_EX, immed_ID_EX} <= {writeRd, ldic, isSignEx, immed};
{alu_ctrl0_ID_EX, alu_ctrl1_ID_EX, alu_ctrl2_ID_EX, alu_ctrl3_ID_EX} <= {alu_ctrl0, alu_ctrl1, alu_ctrl2, alu_ctrl3};
{isJump_ID_EX, isJR_ID_EX} <= {isJump, isJR};
{mem_ren_ID_EX, mem_wen_ID_EX} <= {mem_ren, mem_wen};
{lw_ID_EX, link_ID_EX, reg_wen_ID_EX} <= {lw, link, reg_wen};
{instr_ID_EX, pc_1_ID_EX} <= {instr_IF_ID, pc_1_IF_ID};
{str_icnt_ID_EX, stp_cnt_ID_EX, inc_instr_ID_EX} <= {str_icnt, stp_cnt, inc_instr};
pred_taken_ID_EX <= pred_taken_IF_ID;
end
end
//EX stage outputs
wire [31:0] alu_result;
wire [31:0] mem_addr;
wire [4:0] dst_reg;
wire [15:0] instr_cnt, cycle_cnt;
//EX_stage
EX_stage i_EX_stage(
.rs_data(rs_data_ID_EX),
.rt_data(rt_data_ID_EX),
.instr(instr_ID_EX),
.instr_cnt(instr_cnt),
.cycle_cnt(cycle_cnt),
.pc_1(pc_1_ID_EX),
.writeRd(writeRd_ID_EX),
.ldic(ldic_ID_EX),
.isSignEx(isSignEx_ID_EX),
.immed(immed_ID_EX),
.alu_ctrl0(alu_ctrl0_ID_EX),
.alu_ctrl1(alu_ctrl1_ID_EX),
.alu_ctrl2(alu_ctrl2_ID_EX),
.alu_ctrl3(alu_ctrl3_ID_EX),
.isJump(isJump_ID_EX),
.isJR(isJR_ID_EX),
.pred_taken(pred_taken_ID_EX),
.alu_result(alu_result),
.mem_addr(mem_addr),
.jb_addr(jb_addr),
.dst_reg(dst_reg),
.changeFlow(changeFlow),
.taken(taken),
.not_taken(not_taken));
reg [31:0] store_data;
reg [31:0] pc_1_EX_MEM;
reg [31:0] alu_result_EX_MEM;
reg [31:0] mem_addr_EX_MEM;
reg [4:0] dst_reg_EX_MEM;
//control signals for MEM stage
reg mem_ren_EX_MEM, mem_wen_EX_MEM;
//contorl signals for WB stage
reg lw_EX_MEM, link_EX_MEM, reg_wen_EX_MEM;
reg str_icnt_EX_MEM, stp_cnt_EX_MEM;
reg inc_instr_EX_MEM;
//EX_MEM pipeline
always @(posedge clk or negedge rst) begin
if (!rst) begin
{store_data, pc_1_EX_MEM, alu_result_EX_MEM, mem_addr_EX_MEM, dst_reg_EX_MEM} <= 0; //data
{mem_ren_EX_MEM, mem_wen_EX_MEM} <= 0; //control for MEM stage
{lw_EX_MEM, link_EX_MEM, reg_wen_EX_MEM} <= 0; //control for WB stage
{str_icnt_EX_MEM, stp_cnt_EX_MEM, inc_instr_EX_MEM} <= 0;
end
else begin
{store_data, pc_1_EX_MEM, alu_result_EX_MEM} <= {rt_data_ID_EX, pc_1_ID_EX, alu_result}; //data
{mem_addr_EX_MEM, dst_reg_EX_MEM} <= {mem_addr, dst_reg}; //data
{mem_ren_EX_MEM, mem_wen_EX_MEM} <= {mem_ren_ID_EX, mem_wen_ID_EX}; //control for MEM stage
{lw_EX_MEM, link_EX_MEM, reg_wen_EX_MEM} <= {lw_ID_EX, link_ID_EX, reg_wen_ID_EX}; //control for WB stage
{str_icnt_EX_MEM, stp_cnt_EX_MEM, inc_instr_EX_MEM} <= {str_icnt_ID_EX, stp_cnt_ID_EX, inc_instr_ID_EX};
end
end
//stall and hazard detection control
hazard_detect i_hazard_detect(
.changeFlow(changeFlow),
.ID_rs(instr_IF_ID[25:21]),
.ID_rt(instr_IF_ID[20:16]),
.rs_read(rs_read),
.rt_read(rt_read),
.EX_dst_reg(dst_reg),
.MEM_dst_reg(dst_reg_EX_MEM),
.EX_reg_wen(reg_wen_ID_EX),
.MEM_reg_wen(reg_wen_EX_MEM),
.flush_ID(flush_ID),
.flush_EX(flush_EX),
.stall_PC_ID(stall_PC_ID));
wire [31:0] mem_rdata_MEM_WB;
//MEM stage
MEM_stage i_MEM_stage(
.clk(clk),
.mem_addr(mem_addr_EX_MEM),
.mem_wdata(store_data),
.mem_ren(mem_ren_EX_MEM),
.mem_wen(mem_wen_EX_MEM),
.mem_rdata(mem_rdata_MEM_WB));
assign spart_wrt_en = mem_wen_EX_MEM;
assign spart_wrt_add = mem_addr_EX_MEM;
assign spart_wrt_data = store_data;
reg [31:0] pc_1_MEM_WB;
reg [31:0] alu_result_MEM_WB;
reg [4:0] dst_reg_MEM_WB;
reg lw_MEM_WB, link_MEM_WB; //reg_wen_WB is defined in ID stage
reg str_icnt_MEM_WB, stp_cnt_MEM_WB;
reg inc_instr_MEM_WB;
//MEM_WB pipeline
always @(posedge clk or negedge rst) begin
if (!rst) begin
{pc_1_MEM_WB, alu_result_MEM_WB, dst_reg_MEM_WB} <= 0;
{lw_MEM_WB, link_MEM_WB, reg_wen_WB} <= 0;
{str_icnt_MEM_WB, stp_cnt_MEM_WB} <= 0;
end
else begin
{pc_1_MEM_WB, alu_result_MEM_WB, dst_reg_MEM_WB} <= {pc_1_EX_MEM, alu_result_EX_MEM, dst_reg_EX_MEM};
{lw_MEM_WB, link_MEM_WB, reg_wen_WB} <= {lw_EX_MEM, link_EX_MEM, reg_wen_EX_MEM};
{str_icnt_MEM_WB, stp_cnt_MEM_WB, inc_instr_MEM_WB} <= {str_icnt_EX_MEM, stp_cnt_EX_MEM, inc_instr_EX_MEM};
end
end
WB_stage i_WB_stage(
.pc_1(pc_1_MEM_WB),
.alu_result(alu_result_MEM_WB),
.mem_rdata(mem_rdata_MEM_WB),
.dst_reg(dst_reg_MEM_WB),
.lw(lw_MEM_WB),
.link(link_MEM_WB),
.wb_data(wdata_WB),
.wb_addr(waddr_WB));
//perf_cnt i_perf_cnt(.str_ccnt(str_ccnt), .str_icnt(str_icnt_MEM_WB), .stp_cnt(stp_cnt_MEM_WB), .clk(clk), .rst(rst), .inc_instr(inc_instr_MEM_WB),
// .instr_cnt(instr_cnt), .cycle_cnt(cycle_cnt));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_1_V
`define SKY130_FD_SC_HS__A2111O_1_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2111o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2111o_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_1_V
|
/*
* The MIT License (MIT)
*
* Copyright (c) 2015 Stefan Wendler
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module top
(
input clk
/* synthesis loc="27" pullmode="none" */,
input rx
/* synthesis loc="73" */,
input [7:0] pin
/* synthesis loc="10, 9, 6, 5, 4, 3, 2, 1" */,
output tx
/* synthesis loc="74" */,
output [7:0] led
/* synthesis loc="107, 106, 105, 104, 100, 99, 98, 97" */,
output x2en
/* synthesis loc="32" */,
output [7:0] pout
/* synthesis loc="96, 95, 94, 93, 92, 91, 86, 85" */,
output clk_sample
/* synthesis loc="14" */
);
parameter ENABLE = 1'b1;
parameter DISABLE = 1'b0;
parameter STATE_RCV_REG = 2'b0;
parameter STATE_RCV_VAL = 2'b1;
parameter REG_LED = 7'h0;
parameter REG_MEMADR_RD_LO = 7'h1;
parameter REG_MEMADR_RD_HI = 7'h2;
parameter REG_MEMADR_WR_LO = 7'h3;
parameter REG_MEMADR_WR_HI = 7'h4;
parameter REG_MEM = 7'h5;
parameter REG_STATUS = 7'h6;
parameter REG_TRIG_EN = 7'h7;
parameter REG_TRIG_VAL = 7'h8;
parameter REG_CLKDIV_LO = 7'h9;
parameter REG_CLKDIV_HI = 7'hA;
reg rst = ENABLE;
reg transmit = DISABLE;
reg [7:0] tx_byte;
reg [6:0] register;
reg [7:0] value;
reg [2:0] state = 2'b0;
reg [7:0] r_led = 8'b0;
reg [13:0] memadr_rd = 13'h0;
reg [13:0] memadr_wr = 13'h0;
reg memwe = DISABLE;
reg [7:0] memdata_in;
wire [7:0] memdata_out;
reg [7:0] memcnt_rd = 10'h0;
reg [7:0] trig_en = 8'h0;
reg [7:0] trig_val = 8'h0;
reg [15:0] clkdiv = 16'h1;
/**
* Status register bits:
*
* Bit Direction Function
* 0 WR Write 1 to start sampling, is set to 0 after sampling started
* 1 R 1 if sampling is in progress, 0 no sampling in progress
* 2 WR Trigger enable
* 3
* 4
* 5
* 6
* 7
*/
reg [7:0] status = 8'b0;
wire received;
wire [7:0] rx_byte;
wire is_receiving;
wire is_transmitting;
wire rcv_error;
wire clk_96M;
wire clk_48M;
wire clk_24M;
wire clk_1M;
// pll
pll pll1 (
clk,
clk_96M,
clk_48M,
clk_24M,
clk_1M
);
reg clk_sample_rst = DISABLE;
// wire clk_sample;
clkdiv div1 (
clk_sample_rst,
clk_96M,
clkdiv,
clk_sample
);
// DP ram
ram ram1 (
memadr_wr[13:0] - 1'b1,
memadr_rd[13:0],
memdata_in[7:0],
memwe,
clk_96M,
ENABLE,
rst,
clk_96M,
ENABLE,
memdata_out[7:0]
);
// uart 115200 baud (12 MHz * 1000 * 1000 / (115200 * 4))
// uart #(26) uart1 (
uart #(26) uart1 (
clk_96M, // The master clock for this module
rst, // Synchronous reset.
rx, // Incoming serial line
tx, // Outgoing serial line
transmit, // Signal to transmit
tx_byte, // Byte to transmit
received, // Indicated that a byte has been received.
rx_byte, // Byte received
is_receiving, // Low when receive line is idle.
is_transmitting, // Low when transmit line is idle.
recv_error // Indicates error in receiving packet.
);
////
// communication loop
////
always @(posedge clk_96M) begin
if(rst) begin
rst <= DISABLE;
end
else if(received) begin
case(state)
STATE_RCV_REG:
begin
register[6:0] = rx_byte[6:0];
// check if bit 7 is 0, this means read access
if(rx_byte[7] == 0) begin
////
// handle register command
////
case(register)
REG_STATUS : tx_byte[7:0] = status[7:0];
REG_LED : tx_byte[7:0] = r_led[7:0];
REG_MEMADR_RD_LO : tx_byte[7:0] = memadr_rd[7:0];
REG_MEMADR_RD_HI : tx_byte[7:0] = memadr_rd[13:8];
REG_MEMADR_WR_LO : tx_byte[7:0] = memadr_wr[7:0];
REG_MEMADR_WR_HI : tx_byte[7:0] = memadr_wr[13:8];
REG_MEM : state <= STATE_RCV_VAL; // this takes the number of bytes as a parameter
REG_TRIG_EN : tx_byte[7:0] = trig_en[7:0];
REG_TRIG_VAL : tx_byte[7:0] = trig_val[7:0];
REG_CLKDIV_LO : tx_byte[7:0] = clkdiv[7:0];
REG_CLKDIV_HI : tx_byte[7:0] = clkdiv[15:8];
default : tx_byte[7:0] = 8'hff;
endcase
// for single read access, begin data transfer
if(register != REG_MEM) begin
transmit <= ENABLE;
end
end
else begin
// write access always takes a parameter
state <= STATE_RCV_VAL;
end
end
STATE_RCV_VAL:
begin
value[7:0] = rx_byte[7:0];
////
// handle parameter
////
case(register)
REG_STATUS :
begin
status[0] = value[0]; // start sampling
status[2] = value[2]; // enable trigger
end
REG_LED : r_led[7:0] = value[7:0];
REG_MEMADR_RD_LO : memadr_rd[7:0] = value[7:0];
REG_MEMADR_RD_HI : memadr_rd[13:8] = value[5:0];
REG_MEM : memcnt_rd[7:0] = value[7:0];
REG_TRIG_EN : trig_en[7:0] = value[7:0];
REG_TRIG_VAL : trig_val[7:0] = value[7:0];
REG_CLKDIV_LO : clkdiv[7:0] = value[7:0];
REG_CLKDIV_HI : clkdiv[15:8] = value[7:0];
endcase
// reset sample clk
if(register == REG_CLKDIV_LO || register == REG_CLKDIV_HI) begin
clk_sample_rst = ENABLE;
end
// ready to receive next command
state <= STATE_RCV_REG;
end
endcase
end
else if(is_transmitting) begin
transmit <= DISABLE;
end
else if(!transmit && memcnt_rd) begin
// send the requested bytes from memory until count is zero
tx_byte[7:0] = memdata_out[7:0];
memadr_rd = memadr_rd + 1;
memcnt_rd = memcnt_rd - 1;
transmit <= ENABLE;
end
else if(status[1] && status[0]) begin
status[0] = 1'b0;
end
else begin
// enable sample clk in case it was disabled
clk_sample_rst = DISABLE;
end
end
////
// sampling loop
////
always @(posedge clk_sample) begin
// stop writing to memory
memwe = DISABLE;
// start sampling is requesetd but sampling not started
if(status[0] && !status[1] &&
// check trigger if enabled
(!status[2] || (status[2] && (pin[7:0] & trig_en[7:0]) == trig_val[7:0])))
begin
memadr_wr = 14'h00; // start writing samples to address 0
status[1] = ENABLE; // sampling started
end
// sampling already in progress
else if(status[1]) begin
memdata_in[7:0] = pin[7:0]; // put sample to memory
memadr_wr = memadr_wr + 1; // auto advance to next address
memwe = ENABLE; // write to memory
// when address is 0 again, whole sample memory is written - done sampling
if(!memadr_wr) begin
status[1] = DISABLE;
end
end
end
reg [7:0] r_pout = 8'h0;
// create some test data on the output
always @(posedge clk_24M) begin
r_pout <= r_pout + 1;
end
assign x2en = 1'b1;
assign led[7:0] = ~r_led[7:0];
assign pout = r_pout;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_BLACKBOX_V
`define SKY130_FD_SC_LP__OR3_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_BLACKBOX_V
|
module prometheus_fx3_stream_in(
input rst_n,
input clk_100,
input stream_in_mode_selected,
input i_gpif_in_ch0_rdy_d,
input i_gpif_out_ch0_rdy_d,
output o_gpif_we_n_stream_in_,
output [31:0] data_out_stream_in
);
reg [2:0]current_stream_in_state;
reg [2:0]next_stream_in_state;
reg [31:0]data_gen_stream_in;
//parameters for StreamIN mode state machine
parameter [2:0] stream_in_idle = 3'd0;
parameter [2:0] stream_in_wait_flagb = 3'd1;
parameter [2:0] stream_in_write = 3'd2;
parameter [2:0] stream_in_write_wr_delay = 3'd3;
assign o_gpif_we_n_stream_in_ = ((current_stream_in_state == stream_in_write) && (i_gpif_out_ch0_rdy_d == 1'b1)) ? 1'b0 : 1'b1;
//stream_in mode state machine
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
current_stream_in_state <= stream_in_idle;
end else begin
current_stream_in_state <= next_stream_in_state;
end
end
//StreamIN mode state machine combo
always @(*)begin
next_stream_in_state = current_stream_in_state;
case(current_stream_in_state)
stream_in_idle:begin
if((stream_in_mode_selected) & (i_gpif_in_ch0_rdy_d == 1'b1))begin
next_stream_in_state = stream_in_wait_flagb;
end else begin
next_stream_in_state = stream_in_idle;
end
end
stream_in_wait_flagb :begin
if (i_gpif_out_ch0_rdy_d == 1'b1)begin
next_stream_in_state = stream_in_write;
end else begin
next_stream_in_state = stream_in_wait_flagb;
end
end
stream_in_write:begin
if(i_gpif_out_ch0_rdy_d == 1'b0)begin
next_stream_in_state = stream_in_write_wr_delay;
end else begin
next_stream_in_state = stream_in_write;
end
end
stream_in_write_wr_delay:begin
next_stream_in_state = stream_in_idle;
end
endcase
end
//data generator counter for Partial, ZLP, StreamIN modes
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
data_gen_stream_in <= 32'd0;
end else if((o_gpif_we_n_stream_in_ == 1'b0) & (stream_in_mode_selected)) begin
data_gen_stream_in <= data_gen_stream_in + 1;
end else if (!stream_in_mode_selected) begin
data_gen_stream_in <= 32'd0;
end
end
assign data_out_stream_in = data_gen_stream_in;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninja_life.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ninja_life (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites/ninja_life.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/ninja_life.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/ninja_life.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
////////////////////////////////////////////////////////////////////////////////////////////
// File: measure.v
// Author: B. Brown, T. Dotsikas
// About: Same as new_pipeline_2 but with new modules from this experiment added.
////////////////////////////////////////////////////////////////////////////////////////////
//=======================================================
// Ports generated by Terasic System Builder
//=======================================================
module measure(
//////////// CLOCK //////////
input CLOCK_50,
input CLOCK2_50,
input CLOCK3_50,
//////////// LED //////////
output [8:0] LEDG,
output [17:0] LEDR,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [17:0] SW,
//////////// VGA //////////
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS,
//////////// I2C for Tv-Decoder //////////
output I2C_SCLK,
inout I2C_SDAT,
//////////// TV Decoder //////////
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
//////////// SDRAM //////////
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [31:0] DRAM_DQ,
output [3:0] DRAM_DQM,
output DRAM_RAS_N,
output DRAM_WE_N,
//////////// SRAM //////////
output [19:0] SRAM_ADDR,
output SRAM_CE_N,
inout [15:0] SRAM_DQ,
output SRAM_LB_N,
output SRAM_OE_N,
output SRAM_UB_N,
output SRAM_WE_N
);
// VGA Display Width
localparam DISP_WIDTH = 11;
// Color Width
localparam COLOR_WIDTH = 10;
// SDRAM and SRAM Data Width
localparam RAM_WIDTH = 16;
// Moving Average Filter
localparam FILTER_LENGTH = 20;
localparam CLOG2_FILTER_LENGTH = 5;
// Minimum number of pixels an object must have to be tracked
localparam COUNT_THRESHOLD = 40;
// Number of pixels to draw in each direction from the target
localparam TARGET_SIZE = 10;
// Output Resolution Parameters for a 27MHz clock (units: pixels)
localparam VGA_RES_POLAR = 1'b0; // HS and VS are active-low for these settings
localparam VGA_RES_H_FRONT = 16; // Horizontal Front Porch
localparam VGA_RES_H_SYNC = 98; // Horizontal Sync Length
localparam VGA_RES_H_BACK = 46; // Horizontal Back Porch
localparam VGA_RES_H_ACT = 640; // Horizontal Actual (Visible)
localparam VGA_RES_V_FRONT = 11; // Vertical Front Porch
localparam VGA_RES_V_SYNC = 2; // Vertical Sync Length
localparam VGA_RES_V_BACK = 31; // Vertical Back Porch
localparam VGA_RES_V_ACT = 480; // Vertical Actual (Visible)
localparam VGA_RES_V_ACT_2 = 240; // Just divide the above number by 2
// Pad bits needed for memory
localparam PAD_BITS = RAM_WIDTH - COLOR_WIDTH;
// SDRAM Parameters (units: pixels)
localparam LINES_ODD_START = VGA_RES_V_FRONT + VGA_RES_V_SYNC;
localparam LINES_ODD_END = LINES_ODD_START + VGA_RES_V_ACT_2;
localparam LINES_EVEN_START = LINES_ODD_END + LINES_ODD_START + 1;
localparam LINES_EVEN_END = LINES_EVEN_START + VGA_RES_V_ACT_2;
// Global Reset
wire aresetn;
// User Control
wire grab_base;
wire track_object;
wire disp_delta;
wire [(COLOR_WIDTH-1):0] sat_thresh;
// TV Decode Pipeline Output
wire [(COLOR_WIDTH-1):0] Red; // RGB data after YCbCr conversion
wire [(COLOR_WIDTH-1):0] Green; // RGB data after YCbCr conversion
wire [(COLOR_WIDTH-1):0] Blue; // RGB data after YCbCr conversion
wire RGB_valid; // Valid RGB data after YCbCr conversion, unused
// RGB to Grayscale Converter
wire [(COLOR_WIDTH-1):0] grayscale;
wire grayscale_valid;
// Curr Frame SDRAM
wire [(RAM_WIDTH-1):0] sdram_output; // SDRAM read data muxed for odd or even field
wire [(RAM_WIDTH-1):0] grayscale_odd; // SDRAM data odd field
wire [(RAM_WIDTH-1):0] grayscale_even; // SDRAM data even field
wire vga_odd_ready; // VGA data request odd field
wire vga_even_ready; // VGA data request even field
// Base Frame SRAM
wire [(RAM_WIDTH-1):0] sram_output;
// Delta Frame Generator
wire filter_delta;
wire [(COLOR_WIDTH-1):0] delta_frame;
// Measure
wire [(DISP_WIDTH-1):0] x_object;
wire [(DISP_WIDTH-1):0] y_object;
// Color Position
wire [(COLOR_WIDTH-1):0] red_out;
wire [(COLOR_WIDTH-1):0] green_out;
wire [(COLOR_WIDTH-1):0] blue_out;
// VGA Controller Output
wire [(DISP_WIDTH-1):0] vga_x; // VGA horizontal position
wire [(DISP_WIDTH-1):0] vga_y; // VGA vertical position
wire vga_ready; // VGA data request
// Map user control to peripherals
assign aresetn = KEY[0];
assign grab_base = ~KEY[1];
assign filter_delta = SW[15];
assign track_object = SW[16];
assign disp_delta = SW[17];
assign sat_thresh = SW[(COLOR_WIDTH-1):0];
// Video Input Decode Pipeline
video_input video_input_inst
(
.aresetn (aresetn),
// TV Decoder
.TD_CLK27 (TD_CLK27),
.TD_DATA (TD_DATA),
.TD_HS (TD_HS),
.TD_RESET_N (TD_RESET_N),
.TD_VS (TD_VS),
// RGB
.R_out (Red),
.B_out (Blue),
.G_out (Green),
.RGB_valid (RGB_valid)
);
// RGB 30-bit convertered to 10-bit grayscale
rgb_to_grayscale #(
.rgb_width (COLOR_WIDTH)
) conv_rgb_to_gray (
.clk (TD_CLK27),
.aresetn (aresetn),
// Input Data Bus
.RED (Red),
.GREEN (Green),
.BLUE (Blue),
.valid_in (RGB_valid),
// Output Data Bus
.GRAYSCALE (grayscale),
.valid_out (grayscale_valid)
);
// SDRAM Frame Buffer
Sdram_Control_4Port sdram_control_inst
(
.REF_CLK (TD_CLK27),
.RESET_N (aresetn),
// FIFO Write Side 1
.WR1_DATA ({{PAD_BITS{1'b0}}, grayscale}),
.WR1 (grayscale_valid), // Write Enable
.WR1_ADDR (0), // Base address
.WR1_MAX_ADDR (VGA_RES_H_ACT*LINES_EVEN_END), // Store every pixel of every line. Blanking lines, odd lines, blanking lines, and even lines.
.WR1_LENGTH (9'h80), // The valid signal drops low every 8 samples, 16*8 = 128 bits per burst?
.WR1_LOAD (~aresetn), // Clears FIFO
.WR1_CLK (TD_CLK27),
// FIFO Read Side 1 (Odd Field, Bypass Blanking)
.RD1_DATA (grayscale_odd),
.RD1 (vga_odd_ready), // Read Enable
.RD1_ADDR (VGA_RES_H_ACT*LINES_ODD_START), // Bypass the blanking lines
.RD1_MAX_ADDR (VGA_RES_H_ACT*LINES_ODD_END ), // Read out of the valid odd lines
.RD1_LENGTH (9'h80), // Just being consistent with write length?
.RD1_LOAD (~aresetn), // Clears FIFO
.RD1_CLK (TD_CLK27),
// FIFO Read Side 2 (Even Field, Bypass Blanking)
.RD2_DATA (grayscale_even),
.RD2 (vga_even_ready), // Read Enable
.RD2_ADDR (VGA_RES_H_ACT*LINES_EVEN_START), // Bypass the blanking lines
.RD2_MAX_ADDR (VGA_RES_H_ACT*LINES_EVEN_END ), // Read out of the valid even lines
.RD2_LENGTH (9'h80), // Just being consistent with write length?
.RD2_LOAD (~aresetn), // Clears FIFO
.RD2_CLK (TD_CLK27),
// SDRAM
.SA (DRAM_ADDR),
.BA (DRAM_BA),
.CS_N (DRAM_CS_N),
.CKE (DRAM_CKE),
.RAS_N (DRAM_RAS_N),
.CAS_N (DRAM_CAS_N),
.WE_N (DRAM_WE_N),
.DQ (DRAM_DQ),
.DQM ({DRAM_DQM[1], DRAM_DQM[0]}),
.SDR_CLK (DRAM_CLK)
);
// Field Select Logic (Odd/Even)
assign vga_odd_ready = vga_y[0] ? 1'b0 : vga_ready;
assign vga_even_ready = vga_y[0] ? vga_ready : 1'b0;
assign sdram_output = ~vga_y[0] ? grayscale_odd : grayscale_even;
// SRAM Controller
sram_wrapper sram_wrapper_inst
(
// Clock and Reset
.clk (TD_CLK27),
.aresetn (aresetn),
// Wrapper Signals
.wen (grab_base),
.addr ({vga_x[9:0], vga_y[9:0]}),
.din (sdram_output),
.dout (sram_output),
// SRAM Signals
.SRAM_ADDR (SRAM_ADDR),
.SRAM_CE_N (SRAM_CE_N),
.SRAM_DQ (SRAM_DQ),
.SRAM_LB_N (SRAM_LB_N),
.SRAM_OE_N (SRAM_OE_N),
.SRAM_UB_N (SRAM_UB_N),
.SRAM_WE_N (SRAM_WE_N)
);
delta_frame #(
.COLOR_WIDTH (COLOR_WIDTH),
.FILTER_LENGTH (FILTER_LENGTH),
.CLOG2_FILTER_LENGTH (CLOG2_FILTER_LENGTH)
) delta_frame_inst (
// Control
.clk (TD_CLK27),
.aresetn (aresetn),
// For Moving Average Filter
.is_filter (filter_delta),
.is_not_blank (vga_ready),
// For Saturation Filter
.threshold (sat_thresh),
// Input Data
.base_frame (sram_output [(COLOR_WIDTH-1):0]),
.curr_frame (sdram_output[(COLOR_WIDTH-1):0]),
// Output Data
.delta_frame (delta_frame)
);
measure_position #(
.INPUT_WIDTH (DISP_WIDTH),
.COLOR_WIDTH (COLOR_WIDTH),
.FRAME_X_MAX (VGA_RES_H_ACT),
.FRAME_Y_MAX (VGA_RES_V_ACT),
.COUNT_THRESH (COUNT_THRESHOLD)
) measure_position_inst (
// Control
.clk (TD_CLK27),
.aresetn (aresetn),
.enable (track_object),
// Input Data
.vga_x (vga_x),
.vga_y (vga_y),
.delta_frame (delta_frame),
// Output Data
.x_position (x_object),
.y_position (y_object)
);
color_position #(
.THRESHOLD (TARGET_SIZE),
.COLOR_WIDTH (COLOR_WIDTH),
.DISP_WIDTH (DISP_WIDTH)
) color_position_inst (
// Control
.clk (TD_CLK27),
.aresetn (aresetn),
.enable (track_object),
// Input Data: From VGA
.x_pos (vga_x),
.y_pos (vga_y),
// Input Data: From Measure
.x_obj (x_object),
.y_obj (y_object),
// Input Data: Output Video
.curr (disp_delta ? delta_frame : sdram_output[(COLOR_WIDTH-1):0]),
// Output Data: To VGA
.r_out (red_out),
.g_out (green_out),
.b_out (blue_out)
);
// VGA Controller
vga_sync #(
.H_TOTAL_WIDTH (DISP_WIDTH),
.V_TOTAL_WIDTH (DISP_WIDTH),
.POLARITY (VGA_RES_POLAR),
.H_FRONT (VGA_RES_H_FRONT),
.H_SYNC (VGA_RES_H_SYNC),
.H_BACK (VGA_RES_H_BACK),
.H_ACT (VGA_RES_H_ACT),
.V_FRONT (VGA_RES_V_FRONT),
.V_SYNC (VGA_RES_V_SYNC),
.V_BACK (VGA_RES_V_BACK),
.V_ACT (VGA_RES_V_ACT)
) vga_sync_inst (
.clock (TD_CLK27),
.aresetn (aresetn),
// Input Data
.R_in (red_out),
.G_in (green_out),
.B_in (blue_out),
// Output Control Logic
.current_x (vga_x),
.current_y (vga_y),
.ready (vga_ready),
// Output VGA Signals
.vga_clk (VGA_CLK),
.R_out (VGA_R),
.G_out (VGA_G),
.B_out (VGA_B),
.h_sync (VGA_HS),
.v_sync (VGA_VS),
.blank_n (VGA_BLANK_N),
.sync_n (VGA_SYNC_N)
);
endmodule |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_2_cols_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_2_cols_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_2_cols_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_2_cols_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
//==================================================================================================
// Filename : CORDIC_Arch3.v
// Created On : 2016-09-28 14:58:46
// Last Modified : 2016-10-04 21:14:36
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
`timescale 1ns / 1ps
module CORDIC_Arch3 #(parameter W = 32, parameter EW = 8, parameter SW = 23, parameter SWR=26, parameter EWR = 5)//*/
/*#(parameter W = 64, parameter EW = 11, parameter SW = 52, parameter SWR = 55, parameter EWR = 6) //-- Double Precision */
(
//Input Signals
input wire clk, // Reloj del sistema.
input wire rst, // Señal de reset del sistema.
input wire beg_fsm_cordic, // Señal de inicio de la maquina de estados del módulo CORDIC.
input wire ack_cordic, // Señal de acknowledge proveniente de otro módulo que indica que ha recibido el resultado del modulo CORDIC.
input wire operation, // Señal que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
input wire [W-1:0] data_in, // Dato de entrada, contiene el angulo que se desea calcular en radianes.
input wire [1:0] shift_region_flag, // Señal que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//input wire [1:0] r_mode,
//Output Signals
output wire ready_cordic, // Señal de salida que indica que se ha completado el calculo del seno/coseno.
output wire overflow_flag, // Bandera de overflow de la operacion.
output wire underflow_flag,
output wire zero_flag,
output wire busy,
output wire [W-1:0] data_output // Bus de datos con el valor final del angulo calculado.
);
//localparam d_var = 0; // Valor por defecto que se le carga al contador de variables.
//localparam d_iter = 0; // Valor por defecto que se le carga al contador de iteraciones.
localparam mode = 1'b0;
localparam iter_bits = 4; //Modificar valor para obtener diferente cantidad de iteraciones; ejem= 3=8iter, 4=16iter. etc
wire [W-1:0] x0,y0;
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
generate
case(W)
32:
begin
assign x0 = 32'h3f1b74ee; // x0 = 0.607252935008881, valor inicial de la variable X.
assign y0 = 32'h00000000; // y0 = 0, valor inicial de la variable Y.
end
64:
begin
assign x0 = 64'h3fe36e9db5086bc9; // x0 = 0.607252935008881, valor inicial de la variable X.
assign y0 = 64'h0000000000000000; // y0 = 0, valor inicial de la variable Y.
end
default:
begin
assign x0 = 32'h3f1b74ee; // x0 = 0.607252935008881, valor inicial de la variable X.
assign y0 = 32'h00000000; // y0 = 0, valor inicial de la variable Y.
end
endcase
endgenerate
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
//Signal declaration
wire reset_reg_cordic;
//ENABLE
wire enab_d_ff_RB1; // Enable de la primera linea de registros.
wire enab_d_ff2_RB2; // Enable de la segunda linea de registros.
wire enab_RB3; // Enable del registro que guarda el valor del signo, dependiendo del modo del algoritmo.
wire enab_d_ff4_Xn, enab_d_ff4_Yn, enab_d_ff4_Zn; // Enable de los registros que guardan los datos provenientes del modulo de suma/resta.
wire enab_d_ff5_data_out; // Enable del registo que guarda el valor de salida final, listo para enviarse al procesador.
wire enab_cont_iter, enab_cont_var; // Enable de los contadores de variable e iteracion
//wire load_cont_iter, load_cont_var; // Señal de carga de un valor en los contadores de variable e iteraciones.
wire enab_dff_5;
//SELECTION
wire sel_mux_3; // Señales de seleccion provenientes de la maquina de estados.
wire [1:0] sel_mux_2; // Señal de seleccion que se activa dependiendo de la variable que se este calculando.
wire sel_mux_1_reg, sel_mux_3_reg; // Señales de seleccion provenientes de la maquina de estados.
wire [1:0] sel_mux_2_reg; // Señal de seleccion que se activa dependiendo de la variable que se este calculando.
//DATA WIRES
wire d_ff1_operation_out; // Salida del registro que guarda el dato de entrada de la operacion a realizar, coseno(1'b0) o seno(1'b1)
wire [1:0] d_ff1_shift_region_flag_out; // Salida del registro que guarda el dato de entrada que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
wire [W-1:0] d_ff1_Z; // Salidas de los registros que guardan los valores iniciales de las variables X, Y y Z.
wire [W-1:0] d_ff_Xn, d_ff_Yn, d_ff_Zn; // Salidas de los registros que guardan los valores de las variables X, Y y Z despues de cada iteracion.
wire [W-1:0] first_mux_X, first_mux_Y, first_mux_Z; // Salidas de los mux que escogen entre un valor inicial y el valor obtenido en una iteracion.
wire [W-1:0] d_ff2_X, d_ff2_Y, d_ff2_Z; // Salidas de los registros que guardan los valores provenientes de la primera linea de mux.
wire sign; // Salida del mux que escoge entre el signo de Y o Z, dependiendo del modo, ya sea rotacion o vectorizacion.
wire [W-1:0] data_out_LUT; // Salida del modulo generate que genera la LUT necesaria dependiendo del ancho de palabra.
wire [iter_bits-1:0] cont_iter_out; // Salida del contador que cuenta las iteraciones realizadas.
wire [EW-1:0] sh_exp_x, sh_exp_y; // Salidas de los sumadores de punto fijo que realizan los desplazamientos.
wire [W-1:0] d_ff3_sh_x_out, d_ff3_sh_y_out; // Salida del registro que guarda el valor de X y Y luego de realizar los desplazamientos.
wire [W-1:0] d_ff3_LUT_out; // Salida del registro que guarda el valor de la LUT.
wire d_ff3_sign_out; // Salida del registro que guarda el valor del signo.
wire [1:0] cont_var_out; // Salida del contador que cuenta las variables calculadas.
wire [W-1:0] mux_sal; // Salida del mux final para colocar en la salida el valor deseado.
wire [W-1:0] data_output2; // Salida del registro antes del cambio de signo.
wire [W-1:0] fmtted_Result; // Salida del modulo de inversion de signo, dependiendo de si se el angulo de entrada estaba fuera del rango de calculo del algoritmo CORDIC.
wire min_tick_iter,max_tick_iter; // Señales que indican cuando se ha alcanzado el valor mas bajo y masalto de cuenta, correspondientemente en el contador de iteraciones.
wire min_tick_var,max_tick_var; // Señales que indican cuando se ha alcanzado el valor mas bajo y masalto de cuenta, correspondientemente en el contador de variables.
//wire enab_reg_sel_mux1,enab_reg_sel_mux2,enab_reg_sel_mux3;
wire ready_add_subt; // Señal que indica que se ha realizado la operacion de suma/resta en punto flotante.
wire [W-1:0] result_add_subt; // Dato de entrada, contiene el resultado del módulo de suma/resta.
wire beg_add_subt; // Señal de salida que indica que se debe de iniciar el modulo de suma/resta.
wire ack_add_subt; // Señal que le indica al modulo de suma/resta que se recibio el resultado de este modulo correctamente.
wire op_add_subt; // Señal hacia el módulo de suma/resta que indica si se va a realizar una suma(1'b0) o una resta(1'b1).
wire [W-1:0] add_subt_dataA; // Bus de datos hacia el modulo de suma/resta con el valor al que se le desea aplicar dicha operacion.
wire [W-1:0] add_subt_dataB; // Bus de datos hacia el modulo de suma/resta con el valor al que se le desea aplicar dicha operacion.
//Instanciación
//------------------------------------------------------------------------------------------------------------------------
//FSM
CORDIC_FSM_v3 inst_CORDIC_FSM_v3
(
.clk (clk),
.reset (rst),
.beg_FSM_CORDIC (beg_fsm_cordic),
.ACK_FSM_CORDIC (ack_cordic),
.exception (1'b0),
.max_tick_iter (max_tick_iter),
.max_tick_var (max_tick_var),
.enab_dff_z (enab_d_ff4_Zn),
.reset_reg_cordic (reset_reg_cordic),
.ready_CORDIC (ready_cordic),
.beg_add_subt (beg_add_subt),
.enab_cont_iter (enab_cont_iter),
.enab_cont_var (enab_cont_var),
.enab_RB1 (enab_d_ff_RB1),
.enab_RB2 (enab_d_ff2_RB2),
.enab_RB3 (enab_RB3),
.enab_d_ff5_data_out (enab_d_ff5_data_out)
);
Up_counter #(.COUNTER_WIDTH(iter_bits)
) ITER_CONT (
.clk (clk),
.rst (reset_reg_cordic),
.enable (enab_cont_iter),
.c_output_W (cont_iter_out)
);
assign max_tick_iter = (cont_iter_out == ((2**iter_bits)-1)) ? 1'b1 : 1'b0;
assign min_tick_iter = (cont_iter_out == 0) ? 1'b1 : 1'b0;
//Son dos, ya que son 3 variables a ser operadas por el FPADD
Up_counter #(.COUNTER_WIDTH(2)
) VAR_CONT (
.clk (clk),
.rst (rst),
.enable (ready_add_subt|enab_cont_var),
.c_output_W (cont_var_out)
);
assign max_tick_var = (cont_var_out == 2**2-1) ? 1'b1 : 1'b0;
//--------------------------------------------------------------------------------------------------------------------------------------------------------
//Primera Etapa: Registros que guardan los valores iniciales.
d_ff_en # (.W(1)) reg_operation
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_d_ff_RB1), //load signal
.D(operation), //input signal
.Q(d_ff1_operation_out) //output signal
);
d_ff_en # (.W(2)) reg_region_flag
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_d_ff_RB1), //load signal
.D(shift_region_flag), //input signal
.Q(d_ff1_shift_region_flag_out) //output signal
);
d_ff_en # (.W(W)) reg_Z0
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_d_ff_RB1), //load signal
.D(data_in), //input signal
.Q(d_ff1_Z) //output signal
);
//--------------------------------------------------------------------------------------------------------------------------------------------------------
//Segunda Etapa : Registros que guardan el canal elegido para el mux, asi como los mux.
Mux_2x1 #(.W(W)) mux1_x0
(
.select(~min_tick_iter),
.ch_0(x0),
.ch_1(d_ff_Xn),
.data_out(first_mux_X)
);
Mux_2x1 #(.W(W)) mux1_y0
(
.select(~min_tick_iter),
.ch_0(y0),
.ch_1(d_ff_Yn),
.data_out(first_mux_Y)
);
Mux_2x1 #(.W(W)) mux1_z0
(
.select(~min_tick_iter),
.ch_0(d_ff1_Z),
.ch_1(d_ff_Zn),
.data_out(first_mux_Z)
);
//----------------------------------------------------------------------------------------------------------------------
//Tercera Etapa: Registros que guardan los datos provenientes de los mux.
d_ff_en # (.W(W)) reg_val_muxX_2stage
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_d_ff2_RB2), //load signal
.D(first_mux_X), //input signal
.Q(d_ff2_X) //output signal
);
d_ff_en # (.W(W)) reg_val_muxY_2stage
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_d_ff2_RB2), //load signal
.D(first_mux_Y), //input signal
.Q(d_ff2_Y) //output signal
);
d_ff_en # (.W(W)) reg_val_muxZ_2stage
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_d_ff2_RB2), //load signal
.D(first_mux_Z), //input signal
.Q(d_ff2_Z) //output signal
);
//----------------------------------------------------------------------------------------------------------------------
//Cuarta Etapa : Restadores para el corrimiento del exponente de X y Y, Lookup-Table y mux de signo dependiendo del modo.
Simple_Subt #(.W(EW),.N(iter_bits)) shift_x
(
.A(d_ff2_X[W-2:SW]),
.B(cont_iter_out),
.Y(sh_exp_x)
);
Simple_Subt #(.W(EW),.N(iter_bits)) shift_y
(
.A(d_ff2_Y[W-2:SW]),
.B(cont_iter_out),
.Y(sh_exp_y)
);
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
generate
case(W)
32:
begin
LUT_ROM_32bits #(.W(W),.N(iter_bits)) LUT32
(
.address(cont_iter_out),
.data_out(data_out_LUT)
);
end
64:
begin
LUT_ROM_64bits #(.W(W),.N(iter_bits)) LUT64
(
.address(cont_iter_out),
.data_out(data_out_LUT)
);
end
default:
begin
LUT_ROM_32bits #(.W(W),.N(iter_bits)) LUT32
(
.address(cont_iter_out),
.data_out(data_out_LUT)
);
end
endcase
endgenerate
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Mux_2x1 #(.W(1)) mux_sign
(
.select(mode),
.ch_0(d_ff2_Z[W-1]),
.ch_1(d_ff2_Y[W-1]),
.data_out(sign)
);
//-------------------------------------------------------------------------------------------------------------------------
//Quinta Etapa : Registros que guardan los datos provenientes de la etapa anterior.
d_ff_en # (.W(W)) reg_shift_x
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_RB3), //load signal
.D({d_ff2_X[W-1],sh_exp_x,d_ff2_X[SW-1:0]}), //input signal
.Q(d_ff3_sh_x_out) //output signal
);
d_ff_en # (.W(W)) reg_shift_y
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_RB3), //load signal
.D({d_ff2_Y[W-1],sh_exp_y,d_ff2_Y[SW-1:0]}), //input signal
.Q(d_ff3_sh_y_out) //output signal
);
d_ff_en # (.W(W)) reg_LUT
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_RB3), //load signal
.D(data_out_LUT), //input signal
.Q(d_ff3_LUT_out) //output signal
);
d_ff_en # (.W(1)) reg_sign
(
.clk(clk),//system clock
.rst(reset_reg_cordic), //system reset
.enable(enab_RB3), //load signal
.D(sign), //input signal
.Q(d_ff3_sign_out) //output signal
);
//-------------------------------------------------------------------------------------------------------------------------------------------------------
//Sexta Etapa : Mux de 3 canales que se activan dependiendo de la variable a calcular.
Mux_3x1_bv2 #(.W(W)) mux_3x1_var1
(
.select(cont_var_out),
.ch_0(d_ff2_X),
.ch_1(d_ff2_Y),
.ch_2(d_ff2_Z),
.data_out(add_subt_dataA)
);
Mux_3x1_bv2 #(.W(W)) mux_3x1_var2
(
.select(cont_var_out),
.ch_0(d_ff3_sh_y_out),
.ch_1(d_ff3_sh_x_out),
.ch_2(d_ff3_LUT_out),
.data_out(add_subt_dataB)
);
PriorityEncoder_CORDIC inst_PriorityEncoder_CORDIC (
.enable(ready_add_subt),
.Data_i(cont_var_out),
.Data_o({enab_d_ff4_Zn,enab_d_ff4_Yn,enab_d_ff4_Xn})
);
Op_Select op_select_mod
(
.variable(~cont_var_out[0]),
.sign(d_ff3_sign_out),
.operation(op_add_subt)
);
//--------------------------------------------------------------------------------------------------------------------------------
//Septima Etapa : Instanciamiento del módulo de suma y resta.
FPU_PIPELINED_FPADDSUB #(
.W(W),
.EW(EW),
.SW(SW),
.SWR(SWR),
.EWR(EWR)
) inst_FPU_PIPELINED_FPADDSUB (
.clk (clk),
.rst (rst|enab_cont_iter),
// .beg_OP (enab_cont_var),
.beg_OP (beg_add_subt),
.Data_X (add_subt_dataA),
.Data_Y (add_subt_dataB),
.add_subt (op_add_subt),
.busy (busy),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.ready (ready_add_subt),
.final_result_ieee (result_add_subt)
);
//-------------------------------------------------------------------------------------------------------------------------------
//Octava Etapa: Registros que guardan los valores de calculo del modulo de suma y resta.
d_ff_en #(.W(W)) d_ff4_Xn
(
.clk(clk),
.rst(reset_reg_cordic),
.enable(enab_d_ff4_Xn),
.D(result_add_subt),
.Q(d_ff_Xn)
);
d_ff_en #(.W(W)) d_ff4_Yn
(
.clk(clk),
.rst(reset_reg_cordic),
.enable(enab_d_ff4_Yn),
.D(result_add_subt),
.Q(d_ff_Yn)
);
d_ff_en #(.W(W)) d_ff4_Zn
(
.clk(clk),
.rst(reset_reg_cordic),
.enable(enab_d_ff4_Zn),
.D(result_add_subt),
.Q(d_ff_Zn)
);
//--------------------------------------------------------------------------------------------------------------------------------
//Novena Etapa: Mux de selección del valor de salida, así como el modulo de correccion de signo y los registros intermedios que
//guardan los datos de salida.
//Aca se decodifica el signo del resultado final
//y ademas se decodifica cual resultado vamos a escoger.
Mux_2x1 #(
.W(W)
) mux_2x1_sal (
.select (sel_mux_3),
.ch_0 (d_ff_Xn),
.ch_1 (d_ff_Yn),
.data_out (mux_sal)
);
DECO_CORDIC_EXT #(
.W(W)
) inst_DECO_CORDIC_EXT (
.data_i (mux_sal),
.operation (d_ff1_operation_out),
.shift_region_flag (d_ff1_shift_region_flag_out),
.sel_mux_3 (sel_mux_3),
.data_out (fmtted_Result)
);
d_ff_en #(.W(W)) d_ff5_data_out
(
.clk(clk),
.rst(reset_reg_cordic),
.enable(enab_d_ff5_data_out),
.D(fmtted_Result),
.Q(data_output)
);
endmodule
|
// A pipelined non-restoring integer division,
// output is valid in WIDTH/2 + 1 clock cycles.
// E.g., 9 cycles for 16-bit, 17 cycles for 32-bit
//
// If timing is shitty, use div1.v for a twice as long pipeline.
//
// WIDTH: input width
module div_pipelined2(clk, rst, z, d,
quot, rem);
parameter WIDTH = 32;
localparam ZBITS = WIDTH*2;
localparam DBITS = ZBITS/2;
localparam STAGES = DBITS/2;
input clk;
input rst;
input [WIDTH -1:0] z;
input [DBITS -1:0] d;
output [DBITS -1:0] quot;
output [DBITS -1:0] rem;
reg [DBITS-1:0] quot;
reg [DBITS-1:0] rem;
function [ZBITS:0] remainder;
input [ZBITS:0] rem_i; input [ZBITS:0] d_i;
begin
remainder = (rem_i[ZBITS])?({rem_i[ZBITS-1:0], 1'b0} + d_i):
({rem_i[ZBITS-1:0], 1'b0} - d_i);
end
endfunction // remainder
function [ZBITS-1:0] remainder_final;
input [ZBITS:0] rem_i; input [ZBITS:0] d_i;
begin
remainder_final = (rem_i[ZBITS]?(rem_i + d_i):rem_i);
end
endfunction // remainder_final
function [DBITS-1:0] quotient;
input [DBITS-1:0] quot_i; input [ZBITS:0] rem_i;
begin
quotient = {quot_i[DBITS-2:0], ~rem_i[ZBITS]};
end
endfunction
reg [ZBITS:0] d_stage [STAGES:0];
reg [DBITS-1:0] quot_stage [STAGES:0];
reg [ZBITS:0] rem_stage [STAGES:0];
wire [ZBITS-1:0] quot_stage_wire [STAGES:0];
wire [ZBITS:0] rem_stage_wire [STAGES:0];
wire [ZBITS:0] rem_next;
assign rem_next = remainder_final(rem_stage_wire[STAGES], d_stage[STAGES]);
integer stage, stage0;
generate genvar stage1;
for(stage1=0; stage1 <= STAGES; stage1=stage1+1) begin
assign rem_stage_wire[stage1] = remainder(rem_stage[stage1], d_stage[stage1]);
if (stage1>0)
assign quot_stage_wire[stage1] = quotient(quot_stage[stage1], rem_stage[stage1]);
else assign quot_stage_wire[stage1] = 0;
end
endgenerate
always @(posedge clk)
if (!rst) begin
quot <= 0;
rem <= 0;
for (stage=0; stage <=STAGES; stage=stage+1) begin
rem_stage[stage] <= 0;
quot_stage[stage] <= 0;
d_stage[stage] <= 0;
end
end else begin
d_stage[0] <= { 1'b0, d, { (ZBITS-DBITS){1'b0} } };
rem_stage[0] <= z;
quot_stage[0] <= 0;
for(stage0=1; stage0 <= STAGES; stage0=stage0+1) begin
d_stage[stage0] <= d_stage[stage0-1];
rem_stage[stage0] <= remainder(rem_stage_wire[stage0-1], d_stage[stage0-1]);
quot_stage[stage0] <= quotient(quot_stage_wire[stage0-1], rem_stage_wire[stage0-1]);
end
quot <= quot_stage_wire[STAGES];
rem <= rem_next[ZBITS-1:ZBITS-DBITS];
end // else: !if(!rst)
endmodule
|
(* * ProofObjects: The Curry-Howard Correspondence *)
(** * 証明オブジェクト: カーリー-ハワード対応 *)
(** "_Algorithms are the computational content of proofs_." --Robert Harper *)
Require Export IndProp.
(* We have seen that Coq has mechanisms both for _programming_,
using inductive data types like [nat] or [list] and functions over
these types, and for _proving_ properties of these programs, using
inductive propositions (like [ev]), implication, universal
quantification, and the like. So far, we have mostly treated
these mechanisms as if they were quite separate, and for many
purposes this is a good way to think. But we have also seen hints
that Coq's programming and proving facilities are closely related.
For example, the keyword [Inductive] is used to declare both data
types and propositions, and [->] is used both to describe the type
of functions on data and logical implication. This is not just a
syntactic accident! In fact, programs and proofs in Coq are
almost the same thing. In this chapter we will study how this
works.
We have already seen the fundamental idea: provability in Coq is
represented by concrete _evidence_. When we construct the proof
of a basic proposition, we are actually building a tree of
evidence, which can be thought of as a data structure.
If the proposition is an implication like [A -> B], then its proof
will be an evidence _transformer_: a recipe for converting
evidence for A into evidence for B. So at a fundamental level,
proofs are simply programs that manipulate evidence. *)
(** これまでに、Coqが、帰納的に定義された([list]や[nat]などの)データ型とそれら型上の関数を使用したプログラミング(_programming_)の側面と、これらのプログラムの性質を帰納的に定義された([ev]や[eq]などの)命題や含意、全称記号を使用して証明すること(_proving_)の両方のメカニズムを持つことを見て来ました。 いままでのところ、これらのメカニズムを全然別のものであるかのように取り扱ってきました。このことは多くの目的に適います。しかし、Coqのプログラミングと証明のための機能は密接に関係しています。例えば、[Inductive]というキーワードは、データ型と命題の両方の宣言に用いられますし、[->]は、関数の型と論理的な含意の記述の両方に使用されます。これは単なる偶然ではありません。実際、Coqにおいて、プログラムと証明はほとんど同じものです。この章において、Coqがどのように動くのかを学びましょう。
我々はすでに根本的なアイデアを見て来ています。Coqにおける証明可能性は具体的な根拠[_evidence_]において表現されており、我々は実際に根拠の木を構築し、その木はデータ構造と同じものであると考えることが出来ます。もし命題が、[A -> B]のような含意を持っていれば、その証明はBの根拠のためにAの根拠を変換するためのレシピになるでしょう。そのため根本的なレベルにおいては、証明は単純なことに根拠を操作するプログラムなのです。 *)
(* Question: If evidence is data, what are propositions themselves?
Answer: They are types!
Look again at the formal definition of the [ev] property. *)
(**
Q. もし根拠がデータなら、命題自身はなんなのでしょう？
A. 型なんです!
[ev]属性の形式的定義をもう一度見直してみましょう。
*)
Print ev.
(* ==>
Inductive ev : nat -> Prop :=
| ev_0 : ev 0
| ev_SS : forall n, ev n -> ev (S (S n)).
*)
(** Suppose we introduce an alternative pronunciation of "[:]".
Instead of "has type," we can say "is a proof of." For example,
the second line in the definition of [ev] declares that [ev_0 : ev
0]. Instead of "[ev_0] has type [ev 0]," we can say that "[ev_0]
is a proof of [ev 0]." *)
(** [:]を「--の型を持っている」の代わりに、「--の証明である」と読むものであると仮定してみましょう。
例えば、[ev]の定義の二行目で[ev_0 : ev 0]と宣言しているところで、 [ev 0]は型[ev 0]を持つ。の代わりに、[ev_0は、ev 0]の証明である。と読みます。
*)
(* This pun between types and propositions -- between [:] as "has type"
and [:] as "is a proof of" or "is evidence for" -- is called the
_Curry-Howard correspondence_. It proposes a deep connection
between the world of logic and the world of computation:
propositions ~ types
proofs ~ data values
See [Wadler 2015] for a brief history and an up-to-date exposition.
Many useful insights follow from this connection. To begin with,
it gives us a natural interpretation of the type of the [ev_SS]
constructor: *)
(** この型と命題の間の類似性([:]の"型である"と"その証明または根拠である"ということ)はカーリーハワード対応と呼ばれます。この対応は、計算機の世界と論理の世界の間に深い関係があることを示唆します。
命題 ~ 型
証明 ~ データ値
[Wadler 2015]において、簡単な歴史と、今までの変遷を見ることが出来ます。
この関係から多くの有用な洞察が導かれます。まず、[ev_SS]コンストラクタの型の自然な解釈を得られます: *)
Check ev_SS.
(* ===> ev_SS : forall n,
ev n ->
ev (S (S n)) *)
(** This can be read "[ev_SS] is a constructor that takes two
arguments -- a number [n] and evidence for the proposition [ev
n] -- and yields evidence for the proposition [ev (S (S n))]." *)
(** これは次のように読むことが出来ます。"[ev_SS]は、二つの引数、--数[n]と[ev n]という命題の根拠と--を取るコンストラクタであり、
[ev (S (S n))]という命題の根拠を生成します。"*)
(** Now let's look again at a previous proof involving [ev]. *)
Theorem ev_4 : ev 4.
Proof.
apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** As with ordinary data values and functions, we can use the [Print]
command to see the _proof object_ that results from this proof
script. *)
Print ev_4.
(* ===> ev_4 = ev_SS 2 (ev_SS 0 ev_0)
: ev 4 *)
(** As a matter of fact, we can also write down this proof object
_directly_, without the need for a separate proof script: *)
Check (ev_SS 2 (ev_SS 0 ev_0)).
(* ===> ev 4 *)
(* The expression [ev_SS 2 (ev_SS 0 ev_0)] can be thought of as
instantiating the parameterized constructor [ev_SS] with the
specific arguments [2] and [0] plus the corresponding proof
objects for its premises [ev 2] and [ev 0]. Alternatively, we can
think of [ev_SS] as a primitive "evidence constructor" that, when
applied to a particular number, wants to be further applied to
evidence that that number is even; its type,
forall n, ev n -> ev (S (S n)),
expresses this functionality, in the same way that the polymorphic
type [forall X, list X] expresses the fact that the constructor
[nil] can be thought of as a function from types to empty lists
with elements of that type. *)
(** [ev_SS 2 (ev_SS 0 ev_0)]という式は、パラメータ付きコンストラクタ[ev_SS]を特定の引数[2]と[0]および、前提である[beautiful 3]と[beautiful 5]に対応する証明オブジェクトを指定して呼び出して、実体化させていると考えることが出来ます。あるいは、[b_sum]は二つの特定の数が適用されたときに、さらに、二つの数がbeautifulである根拠が適用されることを求めるプリミティブな根拠構築器であると考えることも出来ます。
その型は、forall n m, beautiful n -> beautiful m -> beautiful (n+m),です。
前の章において、多相的な型[forall X, list X]がコンストラクタ [nil]がその型の要素の空リストを生成する関数であるのと同じことです。
*)
(* We saw in the [Logic] chapter that we can use function
application syntax to instantiate universally quantified variables
in lemmas, as well as to supply evidence for assumptions that
these lemmas impose. For instance: *)
(** [Logic]の章で見たように補題の中の全称化された変数を裏付けるために、また、これらの補題が導入した仮定に根拠を与えるために。関数適用の構文が使用することが出来たこを覚えているかもしれません。例えば:*)
Theorem ev_4': ev 4.
Proof.
apply (ev_SS 2 (ev_SS 0 ev_0)).
Qed.
(** We can now see that this feature is a trivial consequence of the
status the Coq grants to proofs and propositions: Lemmas and
hypotheses can be combined in expressions (i.e., proof objects)
according to the same basic rules used for programs in the
language. *)
(** この特質が Coqが証明や命題を扱うことを可能にする状態の小さな並びであることが分かると思います:
補題や仮説は式と結合し(たとえば、証明オブジェクト) 同じ基本的な、言語内のプログラムのための規則に従います。*)
(* ################################################################# *)
(* * Proof Scripts *)
(** * 証明スクリプト *)
(** The _proof objects_ we've been discussing lie at the core of how
Coq operates. When Coq is following a proof script, what is
happening internally is that it is gradually constructing a proof
object -- a term whose type is the proposition being proved. The
tactics between [Proof] and [Qed] tell it how to build up a term
of the required type. To see this process in action, let's use
the [Show Proof] command to display the current state of the proof
tree at various points in the following tactic proof. *)
(** これまで議論してきた_証明オブジェクト_は、Coqの動作の中心です。Coqが証明スクリプトを動かすとき、内部的に起こっていることは、証明オブジェクトを徐々に作りあげていることです。ある項の、その型が証明済みの命題であるような。です。
[Proof]と[Qed]の間にあるタクティックは要求された型の項をどのように構築すればよいのか教えてくれます。[Show Proof]コマンドを使って証明木の現在の状態をタクティックの証明中のいろいろな時点で表示してみましょう。*)
Theorem ev_4'' : ev 4.
Proof.
Show Proof.
apply ev_SS.
Show Proof.
apply ev_SS.
Show Proof.
apply ev_0.
Show Proof.
Qed.
(* At any given moment, Coq has constructed a term with a
"hole" (indicated by [?Goal] here, and so on), and it knows what
type of evidence is needed to fill this hole. *)
(** どの瞬間もCoqは穴を持った項([?Goal]などで示される)を構築していて、それぞれの穴にどんな型の根拠が必要になるかを知っています。 *)
(** Each hole corresponds to a subgoal, and the proof is
finished when there are no more subgoals. At this point, the
evidence we've built stored in the global context under the name
given in the [Theorem] command. *)
(** それぞれの穴にはサブゴールが対応しており、証明は、サブゴールがすべて無くなったときに終了します。この時において、[Theorem]コマンドは我々が構築した根拠に名前を与え、グローバルなコンテキストにそれを追加します。 *)
(* Tactic proofs are useful and convenient, but they are not
essential: in principle, we can always construct the required
evidence by hand, as shown above. Then we can use [Definition]
(rather than [Theorem]) to give a global name directly to a
piece of evidence. *)
(** タクティックにようる証明は、使いやすいのですが、本質的ではありません。原理的に、われわれは上で見たように、必要とされる根拠を手でいつでも構築することが出来ます。それから、[Definition]コマンドを(むしろ[Theorem]コマンドより)根拠の断片にグローバルな名前を与えるために使っています。*)
Definition ev_4''' : ev 4 :=
ev_SS 2 (ev_SS 0 ev_0).
(* All these different ways of building the proof lead to exactly the
same evidence being saved in the global environment. *)
(** 証明を構築する方法のいろいろありますが、全て皆同じ根拠がグローバル環境にセーブされます。*)
Print ev_4.
(* ===> ev_4 = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4'.
(* ===> ev_4' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4''.
(* ===> ev_4'' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4'''.
(* ===> ev_4''' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
(** **** Exercise: 1 star (eight_is_even) *)
(** **** 練習問題: ★ (eight_is_even) *)
(** Give a tactic proof and a proof object showing that [ev 8]. *)
(** [ev 8]であるということを示すタクティックによる証明と証明オブジェクトを書きなさい。*)
Theorem ev_8 : ev 8.
Proof.
(* FILL IN HERE *) Admitted.
Definition ev_8' : ev 8 :=
(* FILL IN HERE *) admit.
(** [] *)
(* ##################################################### *)
(* * Quantifiers, Implications, Functions *)
(** 全称量化、含意、関数 *)
(* In Coq's computational universe (where data structures and
programs live), there are two sorts of values with arrows in their
types: _constructors_ introduced by [Inductive]-ly defined data
types, and _functions_.
Similarly, in Coq's logical universe (where we carry out proofs),
there are two ways of giving evidence for an implication:
constructors introduced by [Inductive]-ly defined propositions,
and... functions!
For example, consider this statement: *)
(** Coqにおける計算機の世界(この章までは我々はほとんどそこに住んでいました)において、二つの種類の、型の中に矢印を持つ値があります。
再帰的[Inductive]に定義されることによって導入されるコンスラクタ(_constructors_)と関数(_function_) です
同様に、Coqの論理の世界において、含意のための根拠を与える二つの方法があります。再帰的[Inductive]に定義される命題と...そう。関数です!
例として次の文を考えましょう。 *)
Theorem ev_plus4 : forall n, ev n -> ev (4 + n).
Proof.
intros n H. simpl.
apply ev_SS.
apply ev_SS.
apply H.
Qed.
(* What is the proof object corresponding to [ev_plus4]?
We're looking for an expression whose _type_ is [forall n, ev n ->
ev (4 + n)] -- that is, a _function_ that takes two arguments (one
number and a piece of evidence) and returns a piece of evidence!
Here it is: *)
(** [ev_plus4]に対応する証明オブジェクトはどのようなものでしょうか？
われわれは、型(_type_)が[forall n, ev n -> ev (4 + n)]である式を探します。すなわち、二つの引数(一つの数値と根拠の断片)を取って、根拠の断片を返す関数(_function_)です! *)
Definition ev_plus4' : forall n, ev n -> ev (4 + n) :=
fun (n : nat) => fun (H : ev n) =>
ev_SS (S (S n)) (ev_SS n H).
Check ev_plus4'.
(* ===> ev_plus4' : forall n : nat, ev n -> ev (4 + n) *)
(** Recall that [fun n => blah] means "the function that, given [n],
yields [blah]," and that Coq treats [4 + n] and [S (S (S (S n)))]
as synonyms. Another equivalent way to write this definition is: *)
(** [fun n => blah]は、関数を意味し、その関数は[n]が与えられたら、[blah]を返すものであり、Coqは、[4+n]と[S (S (S (S n)))]
を同義として扱うことを意味することを思いだしましょう。
この定義を書くもう一つの等価な方法は、以下の通りです。 *)
Definition ev_plus4'' (n : nat) (H : ev n) : ev (4 + n) :=
ev_SS (S (S n)) (ev_SS n H).
Check ev_plus4''.
(* ===> ev_plus4'' : forall n : nat, ev n -> ev (4 + n) *)
(** When we view the proposition being proved by [ev_plus4] as a
function type, one aspect of it may seem a little unusual. The
second argument's type, [ev n], mentions the _value_ of the first
argument, [n]. While such _dependent types_ are not found in
conventional programming languages, they can be useful in
programming too, as the recent flurry of activity in the
functional programming community demonstrates.
Notice that both implication ([->]) and quantification ([forall])
correspond to functions on evidence. In fact, they are really the
same thing: [->] is just a shorthand for a degenerate use of
[forall] where there is no dependency, i.e., no need to give a
name to the type on the left-hand side of the arrow. *)
(** [ev_plus4]によって証明される命題を関数型として見るときに、その一つの局面はあまり役に立たないように見えるかもしれません。
二つめの引数の型、[ev n]は最初の引数である[n]の値に言及します。一方そのような依存型(_dependent types_)は通常のプログラミング言語ではあまり見られませんが、それらはとても有用なものなのです。 最近の関数型言語界隈では実装する動きが見られます。
含意[->]と全称量化([forall])は根拠上の関数に対応しています。実際に、それらは本当に同じものです。[->]は、依存性が存在しない場合の[forall]の短縮記法にすぎません。つまり、矢印の左側の型に名前を与える必要がないような場合です。 *)
(* For example, consider this proposition: *)
(** 例としてこの命題について考えてみましょう *)
Definition ev_plus2 : Prop :=
forall n, forall (E : ev n), ev (n + 2).
(* A proof term inhabiting this proposition would be a function
with two arguments: a number [n] and some evidence [E] that [n] is
even. But the name [E] for this evidence is not used in the rest
of the statement of [ev_plus2], so it's a bit silly to bother
making up a name for it. We could write it like this instead,
using the dummy identifier [_] in place of a real name: *)
(* この命題を継承する項は数 [n]と [n]が偶数であるという根拠[E]の二つの引数を取る関数になるでしょう。
しかしこの根拠のための名前[E]は[ev_plus2]の残りの文の中で使われません。そのための名前を考えだすために手間をかけることは少しばかばかしいように思われます。以上の代わりにダミーの識別子[_]を用いて以下のように書くことが出来ます。*)
Definition ev_plus2' : Prop :=
forall n, forall (_ : ev n), ev (n + 2).
(* Or, equivalently, we can write it in more familiar notation: *)
(** あるいは、もっと書き慣れた方法で書くことも出来ます。 *)
Definition ev_plus2'' : Prop :=
forall n, ev n -> ev (n + 2).
(* In general, "[P -> Q]" is just syntactic sugar for
"[forall (_:P), Q]". *)
(** 一般的に、"[P -> Q]"というのは、"[forall (_:P), Q]"の糖衣構文です *)
(* ################################################################# *)
(* * Programming with Tactics *)
(** * タクティックによるプログラミング *)
(* If we can build proofs by giving explicit terms rather than
executing tactic scripts, you may be wondering whether we can
build _programs_ using _tactics_ rather than explicit terms.
Naturally, the answer is yes! *)
(** 明示的な項を使用して証明を構築できるならば、明示的な項ではなく、タクティックを使用してプログラムを構築することが出来るのでしょうか？
もちろん出来ます ! *)
Definition add1 : nat -> nat.
intro n.
Show Proof.
apply S.
Show Proof.
apply n. Defined.
Print add1.
(* ==>
add1 = fun n : nat => S n
: nat -> nat
*)
Compute add1 2.
(* ==> 3 : nat *)
(** Notice that we terminate the [Definition] with a [.] rather than
with [:=] followed by a term. This tells Coq to enter _proof
scripting mode_ to build an object of type [nat -> nat]. Also, we
terminate the proof with [Defined] rather than [Qed]; this makes
the definition _transparent_ so that it can be used in computation
like a normally-defined function. ([Qed]-defined objects are
opaque during computation.)
This feature is mainly useful for writing functions with dependent
types, which we won't explore much further in this book. But it
does illustrate the uniformity and orthogonality of the basic
ideas in Coq. *)
(** ここで[Definition]を[:=]とそれに続く項ではなく、[.]で終了させたことに気を付けましょう。
このことはCoqに対して、[nat->nat]型を持つオブジェクトを生成するために、証明スクリプトモードに入ることを告げるものです。
それから、[Qed]ではなく、[Defined]で証明を終わらせたことにも気を付けましょう。これは、定義を普通に定義された関数のように
_透過的_に使用出来るようにしてくれます。([Qed]で定義されたオブジェクトは、計算の上では、不透過です。)
この特徴は、依存型を使って関数を書くのに主に使われますが、この本では深入りしません。しかしこれはCoqの基本的な
概念の統一性と直交性を示すものです。*)
(* ################################################################# *)
(* * Logical Connectives as Inductive Types *)
(** * 帰納的な型としての論理結合子 *)
(** Inductive definitions are powerful enough to express most of the
connectives and quantifiers we have seen so far. Indeed, only
universal quantification (and thus implication) is built into Coq;
all the others are defined inductively. We'll see these
definitions in this section. *)
(** 帰納的な定義は、これまで見てきたように、結合子と量化子の殆どを表現するのに十分な力を備えています。確かに全称記号(と、含意)はCoqに組込まれています;
すべての他のものは、帰納的に定義されています。このセクションでこれらの定義を見てみましょう *)
Module Props.
(* ** Conjunction
To prove that [P /\ Q] holds, we must present evidence for both
[P] and [Q]. Thus, it makes sense to define a proof object for [P
/\ Q] as consisting of a pair of two proofs: one for [P] and
another one for [Q]. This leads to the following definition. *)
(** ** 連言
[P /\ Q]を証明するために、[P]と[Q]の両方の根拠を提示しなければなりません。それゆえ、
[P /\ Q]の証明オブジェクトを二つの証明のペア([P]のために一つと、[Q]のために一つです)を構成するように定義することは必然です。
このことは次の定義を導きます。*)
*)
Module And.
Inductive and (P Q : Prop) : Prop :=
| conj : P -> Q -> and P Q.
End And.
(* Notice the similarity with the definition of the [prod] type,
given in chapter [Poly]; the only difference is that [prod] takes
[Type] arguments, whereas [and] takes [Prop] arguments. *)
(** [Poly」の章の[prod]型の定義との類似性に注目してください。違いは[prod]が、[Type]を引数にとり、[and]が[Prop]を引数に取るという点だけです。*)
Print prod.
(* ===>
Inductive prod (X Y : Type) : Type :=
| pair : X -> Y -> X * Y. *)
(* This should clarify why [destruct] and [intros] patterns can be
used on a conjunctive hypothesis. Case analysis allows us to
consider all possible ways in which [P /\ Q] was proved -- here
just one (the [conj] constructor). Similarly, the [split] tactic
actually works for any inductively defined proposition with only
one constructor. In particular, it works for [and]: *)
(** このことは、なぜ[destruct]と[intros]が連言の仮説に使用されるかについて明確にしてくれます。
ケース分析によって、[P/\Q]が証明される有り得るすべてのルートについて考えることが可能になります。
-- この場合は、[conj]コンストラクタ一つしかありませんが...
同様に、[split]タクティックは帰納的に定義された一つしかコンスラクタを持たないような命題についても実際に動作します。
とりわけ、[and]については特に。*)
Lemma and_comm : forall P Q : Prop, P /\ Q <-> Q /\ P.
Proof.
intros P Q. split.
- intros [HP HQ]. split.
+ apply HQ.
+ apply HP.
- intros [HP HQ]. split.
+ apply HQ.
+ apply HP.
Qed.
(* This shows why the inductive definition of [and] can be
manipulated by tactics as we've been doing. We can also use it to
build proofs directly, using pattern-matching. For instance: *)
(** このことは、[and]の帰納的定義がなぜ、タクティックによってこれまで行なわれてきたように操作されうるかを示しています。
パターンマッチを用いて直接に証明を組み立てるためにandを使うことが出来ます。例えば *)
Definition and_comm'_aux P Q (H : P /\ Q) :=
match H with
| conj HP HQ => conj HQ HP
end.
Definition and_comm' P Q : P /\ Q <-> Q /\ P :=
conj (and_comm'_aux P Q) (and_comm'_aux Q P).
(* **** Exercise: 2 stars, optional (conj_fact) *)
(** **** 練習問題: ★★, optional (conj_fact) *)
(* Construct a proof object demonstrating the following proposition. *)
(** 次の命題を立証する証明オブジェクトを構築しなさい *)
Definition conj_fact : forall P Q R, P /\ Q -> Q /\ R -> P /\ R
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(* ** Disjunction
The inductive definition of disjunction uses two constructors, one
for each side of the disjunct: *)
(** ** 選言
選言の帰納的定義は二つのコンストラクタを使います。それぞれが選言の枝になります。*)
Module Or.
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
End Or.
(* This declaration explains the behavior of the [destruct] tactic on
a disjunctive hypothesis, since the generated subgoals match the
shape of the [or_introl] and [or_intror] constructors.
Once again, we can also directly write proof objects for theorems
involving [or], without resorting to tactics. *)
(** この宣言は、選言的仮説上での[destruct]タクティックのふるまいを説明します。
生成されたサブゴールは[or_introl]と[or_intror]コンストラクタの形にマッチします。
ここでも、[or]を含む定理のための証明オブジェクトをタクティックに頼ることなく、直接書くことが出来ます。*)
(* **** Exercise: 2 stars, optional (or_commut'') *)
(** **** 練習問題: ★★, optional (or_commut'') *)
(* Try to write down an explicit proof object for [or_commut] (without
using [Print] to peek at the ones we already defined!). *)
(** 明示的な証明オブジェクトをすでに定義したそれを[Print]を使って覗くことなく、書下してみましょう *)
Definition or_comm : forall P Q, P \/ Q -> Q \/ P
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(** ** Existential Quantification
To give evidence for an existential quantifier, we package a
witness [x] together with a proof that [x] satisfies the property
[P]: *)
Module Ex.
Inductive ex {A : Type} (P : A -> Prop) : Prop :=
| ex_intro : forall x : A, P x -> ex P.
End Ex.
(** This may benefit from a little unpacking. The core definition is
for a type former [ex] that can be used to build propositions of
the form [ex P], where [P] itself is a _function_ from witness
values in the type [A] to propositions. The [ex_intro]
constructor then offers a way of constructing evidence for [ex P],
given a witness [x] and a proof of [P x].
The more familiar form [exists x, P x] desugars to an expression
involving [ex]: *)
Check ex (fun n => ev n).
(* ===> exists n : nat, ev n
: Prop *)
(** Here's how to define an explicit proof object involving [ex]: *)
Definition some_nat_is_even : exists n, ev n :=
ex_intro ev 4 (ev_SS 2 (ev_SS 0 ev_0)).
(** **** 練習問題: ★ ★s, optional (ex_ev_Sn) *)
(** Complete the definition of the following proof object: *)
Definition ex_ev_Sn : ex (fun n => ev (S n)) :=
(* FILL IN HERE *) admit.
(** [] *)
(** ** [True] and [False] *)
(** The inductive definition of the [True] proposition is simple: *)
Inductive True : Prop :=
I : True.
(** It has one constructor (so every proof of [True] is the same, so
being given a proof of [True] is not informative.) *)
(** [False] is equally simple -- indeed, so simple it may look
syntactically wrong at first glance! *)
Inductive False : Prop :=.
(** That is, [False] is an inductive type with _no_ constructors --
i.e., no way to build evidence for it. *)
End Props.
(* ################################################################# *)
(* ###################################################### *)
(** * Equality *)
(** Even Coq's equality relation is not built in. It has the
following inductive definition. (Actually, the definition in the
standard library is a small variant of this, which gives an
induction principle that is slightly easier to use.) *)
(** Coqには、等価という関係すら組み込まれていませんから、次のように帰納的に定義
してやります。(実際にはcoqの標準ライブラリでは、これのちょっと違う版が定義されています。帰納の原理がちょっぴり使いやすくなっています。
Module MyEquality.
Inductive eq {X:Type} : X -> X -> Prop :=
| eq_refl : forall x, eq x x.
Notation "x = y" := (eq x y)
(at level 70, no associativity)
: type_scope.
(* The way to think about this definition is that, given a set [X],
it defines a _family_ of propositions "[x] is equal to [y],"
indexed by pairs of values ([x] and [y]) from [X]. There is just
one way of constructing evidence for each member of this family:
applying the constructor [eq_refl] to a type [X] and a value [x :
X] yields evidence that [x] is equal to [x]. *)
(** この定義の考え方は次のようなものです。集合 [X] が与えられると、「集合 [X] に属する値 ([x] and [y]) にインデックスされた、[x] は [y] に等しい」というような命題の _集団_ を定義してくれるということです。
この集団に属する命題に根拠を与えるためには、一つの方法しかありません。それは、コンストラクタ [refl_equal] に型 [X] とその値[x : X] を適用し、[x] が [x] と等しいという根拠を生成することです。*)
(** **** 練習問題: ★ ★s (leibniz_equality) *)
(** **** 練習問題: ★ ★s (leibniz_equality) *)
(* The inductive definition of equality corresponds to _Leibniz
equality_: what we mean when we say "[x] and [y] are equal" is
that every property on [P] that is true of [x] is also true of
[y]. *)
(** 同値性の帰納的定義は、ライプニッツの同値性と対応しています。ライプニッツの同値性とは、[x] と [y] が等しいということは、 任意の命題 [P] が[x] でtrueとなるならば [y] でもtrueとなる」ということです。
Lemma leibniz_equality : forall (X : Type) (x y: X),
x = y -> forall P:X->Prop, P x -> P y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* We can use [eq_refl] to construct evidence that, for example, [2 =
2]. Can we also use it to construct evidence that [1 + 1 = 2]?
Yes, we can. Indeed, it is the very same piece of evidence! The
reason is that Coq treats as "the same" any two terms that are
_convertible_ according to a simple set of computation rules.
These rules, which are similar to those used by [Compute], include
evaluation of function application, inlining of definitions, and
simplification of [match]es. *)
(** たとえば、[2 = 2]の根拠を構築するために、[eq_refl]を使うことが出来ます。[1 + 1 = 2]の根拠を構築するために、[eq_refl]を使用することは出来るでしょうか？
はい。実際に出来ます。それらは全く同じ根拠なのです！ その理由は、Coqがシンプルな計算ルールに従うどんな二つの項も"同じもの"として扱うからです。
これらのルールは、[Compute]を使って行なわれるものと似たルールで、関数の適用の評価、定義のインライン展開や[match]節の簡約が含まれます。*)
Lemma four: 2 + 2 = 1 + 3.
Proof.
apply eq_refl.
Qed.
(* The [reflexivity] tactic that we have used to prove equalities up
to now is essentially just short-hand for [apply refl_equal].
In tactic-based proofs of equality, the conversion rules are
normally hidden in uses of [simpl] (either explicit or implicit in
other tactics such as [reflexivity]). But you can see them
directly at work in the following explicit proof objects: *)
(** これまでに同値性を証明するために使用してきた[relexivity]タクティックは、本質的には、[apply refl_equal]の略記法であることが分かりました。
タクティックをベースとした同値性の証明において、変換規則は[simpl]の使用に隠されています(暗黙的に、明示的に、[reflexivity]
と他のタクティックも似たようなものです) しかし、証明オブジェクトで明示的に直接動作するのを次の例で見ることが出来ます。*)
Definition four' : 2 + 2 = 1 + 3 :=
eq_refl 4.
Definition singleton : forall (X:Set) (x:X), []++[x] = x::[] :=
fun (X:Set) (x:X) => eq_refl [x].
End MyEquality.
Definition quiz6 : exists x, x + 3 = 4
:= ex_intro (fun z => (z + 3 = 4)) 1 (refl_equal 4).
(* ================================================================= *)
(* ** Inversion, Again *)
(** ** Inversion 再び *)
(* We've seen [inversion] used with both equality hypotheses and
hypotheses about inductively defined propositions. Now that we've
seen that these are actually the same thing, we're in a position
to take a closer look at how [inversion] behaves.
In general, the [inversion] tactic...
- takes a hypothesis [H] whose type [P] is inductively defined,
and
- for each constructor [C] in [P]'s definition,
- generates a new subgoal in which we assume [H] was
built with [C],
- adds the arguments (premises) of [C] to the context of
the subgoal as extra hypotheses,
- matches the conclusion (result type) of [C] against the
current goal and calculates a set of equalities that must
hold in order for [C] to be applicable,
- adds these equalities to the context (and, for convenience,
rewrites them in the goal), and
- if the equalities are not satisfiable (e.g., they involve
things like [S n = O]), immediately solves the subgoal. *)
(** これまでにも inversion が等値性にからむ仮定や帰納的に定義された命題に対して 使われるところを見てきました。今度もやることは変わりませんが、もう少し近くまで 寄って inversion の振る舞いを観察してみましょう。
一般的に inversion タクティックは、
- 帰納的に定義された型 P の命題 H をとる。
- その型 P の定義にある各コンストラクタ C が、
- H が C から成っていると仮定するような新しいサブゴールを作る。
- C の引数（前提）を、追加の仮定としてサブゴールのコンテキストに加える。
- C の結論（戻り値の型）を現在のゴールとmatchして、 C を適用できるような一連の等式算出する。
- そしてこれらの等式をサブゴールのコンテキストに加えてから、
- もしこの等式が充足可能でない場合（S n = O というような式を含むなど）は、 即座にサブゴールを解決する。*)
(** _Example_: If we invert a hypothesis built with [or], there are two
constructors, so two subgoals get generated. The
conclusion (result type) of the constructor ([P \/ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal.
_Example_: If we invert a hypothesis built with [and], there is
only one constructor, so only one subgoal gets generated. Again,
the conclusion (result type) of the constructor ([P /\ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal. The
constructor does have two arguments, though, and these can be seen
in the context in the subgoal.
_Example_: If we invert a hypothesis built with [eq], there is
again only one constructor, so only one subgoal gets generated.
Now, though, the form of the [refl_equal] constructor does give us
some extra information: it tells us that the two arguments to [eq]
must be the same! The [inversion] tactic adds this fact to the
context. *)
(** TODO *)
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 20:12:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_stub.v
// Design : system_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module system_processing_system7_0_0(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP,
S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk,
DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM,
DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[63:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[63:0],S_AXI_HP0_WSTRB[7:0],IRQ_F2P[1:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
input [1:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
//-----------------------------------------------------------------------------
// system_processing_system7_0_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "processing_system7_v4_03_a" *)
(* CORE_GENERATION_INFO = "processing_system7_0,processing_system7,{C_ENET0_PERIPHERAL_ENABLE = 1,C_USB0_PERIPHERAL_ENABLE = 1,C_QSPI_PERIPHERAL_ENABLE = 1,C_DDR_V4.00.A_C_S_AXI_HP3_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP2_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP1_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP0_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP3_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP2_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP1_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP0_HIGHADDR = 0x3FFFFFFF,C_GPIO_PERIPHERAL_ENABLE = 1,C_GPIO_V2.00.A_C_EN_EMIO_GPIO = 0,C:GPIO_EMIO_GPIO_WIDTH = 64,C_CAN_PERIPHERAL_FREQMHZ = 100,C_FPGA3_PERIPHERAL_FREQMHZ = 25.000000,C_FPGA0_PERIPHERAL_FREQMHZ = 100.000000,C_PRESET_GLOBAL_DEFAULT = powerup,C_FPGA1_PERIPHERAL_FREQMHZ = 150.000000,C_PRESET_GLOBAL_CONFIG = Default,C_PRESET_FPGA_SPEED = -1,C_PRESET_FPGA_PARTNUMBER = xc7z020clg484-1,C_SD0_PERIPHERAL_ENABLE = 1,C_UART1_PERIPHERAL_ENABLE = 1}" *)
module system_processing_system7_0_wrapper
(
CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_EXT_INTIN,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_EXT_INTIN,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TD_I,
PJTAG_TD_T,
PJTAG_TD_O,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
USB0_PORT_INDCTL,
USB1_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB1_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_AWREADY,
S_AXI_ACP_ARREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA0_DRTYPE,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA1_DRTYPE,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_DRVALID,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA2_DRTYPE,
DMA3_DRTYPE,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG,
FTMT_F2P_TRIGACK,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK,
FTMT_P2F_TRIG,
FTMT_P2F_DEBUG,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FPGA_IDLE_N,
DDR_ARB,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
MIO,
DDR_Clk,
DDR_Clk_n,
DDR_CKE,
DDR_CS_n,
DDR_RAS_n,
DDR_CAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_ODT,
DDR_DRSTB,
DDR_DQ,
DDR_DM,
DDR_DQS,
DDR_DQS_n,
DDR_VRN,
DDR_VRP,
PS_SRSTB,
PS_CLK,
PS_PORB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1
);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0] ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_EXT_INTIN;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input [7:0] ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0] ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_EXT_INTIN;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input [7:0] ENET1_GMII_RXD;
input [63:0] GPIO_I;
output [63:0] GPIO_O;
output [63:0] GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TD_I;
output PJTAG_TD_T;
output PJTAG_TD_O;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0] SDIO0_DATA_I;
output [3:0] SDIO0_DATA_O;
output [3:0] SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0] SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0] SDIO1_DATA_I;
output [3:0] SDIO1_DATA_O;
output [3:0] SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0] SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [31:0] TRACE_DATA;
output [1:0] USB0_PORT_INDCTL;
output [1:0] USB1_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
output USB1_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0] M_AXI_GP0_ARID;
output [11:0] M_AXI_GP0_AWID;
output [11:0] M_AXI_GP0_WID;
output [1:0] M_AXI_GP0_ARBURST;
output [1:0] M_AXI_GP0_ARLOCK;
output [2:0] M_AXI_GP0_ARSIZE;
output [1:0] M_AXI_GP0_AWBURST;
output [1:0] M_AXI_GP0_AWLOCK;
output [2:0] M_AXI_GP0_AWSIZE;
output [2:0] M_AXI_GP0_ARPROT;
output [2:0] M_AXI_GP0_AWPROT;
output [31:0] M_AXI_GP0_ARADDR;
output [31:0] M_AXI_GP0_AWADDR;
output [31:0] M_AXI_GP0_WDATA;
output [3:0] M_AXI_GP0_ARCACHE;
output [3:0] M_AXI_GP0_ARLEN;
output [3:0] M_AXI_GP0_ARQOS;
output [3:0] M_AXI_GP0_AWCACHE;
output [3:0] M_AXI_GP0_AWLEN;
output [3:0] M_AXI_GP0_AWQOS;
output [3:0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0] M_AXI_GP0_BID;
input [11:0] M_AXI_GP0_RID;
input [1:0] M_AXI_GP0_BRESP;
input [1:0] M_AXI_GP0_RRESP;
input [31:0] M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0] M_AXI_GP1_ARID;
output [11:0] M_AXI_GP1_AWID;
output [11:0] M_AXI_GP1_WID;
output [1:0] M_AXI_GP1_ARBURST;
output [1:0] M_AXI_GP1_ARLOCK;
output [2:0] M_AXI_GP1_ARSIZE;
output [1:0] M_AXI_GP1_AWBURST;
output [1:0] M_AXI_GP1_AWLOCK;
output [2:0] M_AXI_GP1_AWSIZE;
output [2:0] M_AXI_GP1_ARPROT;
output [2:0] M_AXI_GP1_AWPROT;
output [31:0] M_AXI_GP1_ARADDR;
output [31:0] M_AXI_GP1_AWADDR;
output [31:0] M_AXI_GP1_WDATA;
output [3:0] M_AXI_GP1_ARCACHE;
output [3:0] M_AXI_GP1_ARLEN;
output [3:0] M_AXI_GP1_ARQOS;
output [3:0] M_AXI_GP1_AWCACHE;
output [3:0] M_AXI_GP1_AWLEN;
output [3:0] M_AXI_GP1_AWQOS;
output [3:0] M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0] M_AXI_GP1_BID;
input [11:0] M_AXI_GP1_RID;
input [1:0] M_AXI_GP1_BRESP;
input [1:0] M_AXI_GP1_RRESP;
input [31:0] M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0] S_AXI_GP0_BRESP;
output [1:0] S_AXI_GP0_RRESP;
output [31:0] S_AXI_GP0_RDATA;
output [5:0] S_AXI_GP0_BID;
output [5:0] S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0] S_AXI_GP0_ARBURST;
input [1:0] S_AXI_GP0_ARLOCK;
input [2:0] S_AXI_GP0_ARSIZE;
input [1:0] S_AXI_GP0_AWBURST;
input [1:0] S_AXI_GP0_AWLOCK;
input [2:0] S_AXI_GP0_AWSIZE;
input [2:0] S_AXI_GP0_ARPROT;
input [2:0] S_AXI_GP0_AWPROT;
input [31:0] S_AXI_GP0_ARADDR;
input [31:0] S_AXI_GP0_AWADDR;
input [31:0] S_AXI_GP0_WDATA;
input [3:0] S_AXI_GP0_ARCACHE;
input [3:0] S_AXI_GP0_ARLEN;
input [3:0] S_AXI_GP0_ARQOS;
input [3:0] S_AXI_GP0_AWCACHE;
input [3:0] S_AXI_GP0_AWLEN;
input [3:0] S_AXI_GP0_AWQOS;
input [3:0] S_AXI_GP0_WSTRB;
input [5:0] S_AXI_GP0_ARID;
input [5:0] S_AXI_GP0_AWID;
input [5:0] S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0] S_AXI_GP1_BRESP;
output [1:0] S_AXI_GP1_RRESP;
output [31:0] S_AXI_GP1_RDATA;
output [5:0] S_AXI_GP1_BID;
output [5:0] S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0] S_AXI_GP1_ARBURST;
input [1:0] S_AXI_GP1_ARLOCK;
input [2:0] S_AXI_GP1_ARSIZE;
input [1:0] S_AXI_GP1_AWBURST;
input [1:0] S_AXI_GP1_AWLOCK;
input [2:0] S_AXI_GP1_AWSIZE;
input [2:0] S_AXI_GP1_ARPROT;
input [2:0] S_AXI_GP1_AWPROT;
input [31:0] S_AXI_GP1_ARADDR;
input [31:0] S_AXI_GP1_AWADDR;
input [31:0] S_AXI_GP1_WDATA;
input [3:0] S_AXI_GP1_ARCACHE;
input [3:0] S_AXI_GP1_ARLEN;
input [3:0] S_AXI_GP1_ARQOS;
input [3:0] S_AXI_GP1_AWCACHE;
input [3:0] S_AXI_GP1_AWLEN;
input [3:0] S_AXI_GP1_AWQOS;
input [3:0] S_AXI_GP1_WSTRB;
input [5:0] S_AXI_GP1_ARID;
input [5:0] S_AXI_GP1_AWID;
input [5:0] S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0] S_AXI_ACP_BRESP;
output [1:0] S_AXI_ACP_RRESP;
output [2:0] S_AXI_ACP_BID;
output [2:0] S_AXI_ACP_RID;
output [63:0] S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0] S_AXI_ACP_ARID;
input [2:0] S_AXI_ACP_ARPROT;
input [2:0] S_AXI_ACP_AWID;
input [2:0] S_AXI_ACP_AWPROT;
input [2:0] S_AXI_ACP_WID;
input [31:0] S_AXI_ACP_ARADDR;
input [31:0] S_AXI_ACP_AWADDR;
input [3:0] S_AXI_ACP_ARCACHE;
input [3:0] S_AXI_ACP_ARLEN;
input [3:0] S_AXI_ACP_ARQOS;
input [3:0] S_AXI_ACP_AWCACHE;
input [3:0] S_AXI_ACP_AWLEN;
input [3:0] S_AXI_ACP_AWQOS;
input [1:0] S_AXI_ACP_ARBURST;
input [1:0] S_AXI_ACP_ARLOCK;
input [2:0] S_AXI_ACP_ARSIZE;
input [1:0] S_AXI_ACP_AWBURST;
input [1:0] S_AXI_ACP_AWLOCK;
input [2:0] S_AXI_ACP_AWSIZE;
input [4:0] S_AXI_ACP_ARUSER;
input [4:0] S_AXI_ACP_AWUSER;
input [63:0] S_AXI_ACP_WDATA;
input [7:0] S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0] S_AXI_HP0_BRESP;
output [1:0] S_AXI_HP0_RRESP;
output [1:0] S_AXI_HP0_BID;
output [1:0] S_AXI_HP0_RID;
output [63:0] S_AXI_HP0_RDATA;
output [7:0] S_AXI_HP0_RCOUNT;
output [7:0] S_AXI_HP0_WCOUNT;
output [2:0] S_AXI_HP0_RACOUNT;
output [5:0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0] S_AXI_HP0_ARBURST;
input [1:0] S_AXI_HP0_ARLOCK;
input [2:0] S_AXI_HP0_ARSIZE;
input [1:0] S_AXI_HP0_AWBURST;
input [1:0] S_AXI_HP0_AWLOCK;
input [2:0] S_AXI_HP0_AWSIZE;
input [2:0] S_AXI_HP0_ARPROT;
input [2:0] S_AXI_HP0_AWPROT;
input [31:0] S_AXI_HP0_ARADDR;
input [31:0] S_AXI_HP0_AWADDR;
input [3:0] S_AXI_HP0_ARCACHE;
input [3:0] S_AXI_HP0_ARLEN;
input [3:0] S_AXI_HP0_ARQOS;
input [3:0] S_AXI_HP0_AWCACHE;
input [3:0] S_AXI_HP0_AWLEN;
input [3:0] S_AXI_HP0_AWQOS;
input [1:0] S_AXI_HP0_ARID;
input [1:0] S_AXI_HP0_AWID;
input [1:0] S_AXI_HP0_WID;
input [63:0] S_AXI_HP0_WDATA;
input [7:0] S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0] S_AXI_HP1_BRESP;
output [1:0] S_AXI_HP1_RRESP;
output [5:0] S_AXI_HP1_BID;
output [5:0] S_AXI_HP1_RID;
output [63:0] S_AXI_HP1_RDATA;
output [7:0] S_AXI_HP1_RCOUNT;
output [7:0] S_AXI_HP1_WCOUNT;
output [2:0] S_AXI_HP1_RACOUNT;
output [5:0] S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0] S_AXI_HP1_ARBURST;
input [1:0] S_AXI_HP1_ARLOCK;
input [2:0] S_AXI_HP1_ARSIZE;
input [1:0] S_AXI_HP1_AWBURST;
input [1:0] S_AXI_HP1_AWLOCK;
input [2:0] S_AXI_HP1_AWSIZE;
input [2:0] S_AXI_HP1_ARPROT;
input [2:0] S_AXI_HP1_AWPROT;
input [31:0] S_AXI_HP1_ARADDR;
input [31:0] S_AXI_HP1_AWADDR;
input [3:0] S_AXI_HP1_ARCACHE;
input [3:0] S_AXI_HP1_ARLEN;
input [3:0] S_AXI_HP1_ARQOS;
input [3:0] S_AXI_HP1_AWCACHE;
input [3:0] S_AXI_HP1_AWLEN;
input [3:0] S_AXI_HP1_AWQOS;
input [5:0] S_AXI_HP1_ARID;
input [5:0] S_AXI_HP1_AWID;
input [5:0] S_AXI_HP1_WID;
input [63:0] S_AXI_HP1_WDATA;
input [7:0] S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0] S_AXI_HP2_BRESP;
output [1:0] S_AXI_HP2_RRESP;
output [5:0] S_AXI_HP2_BID;
output [5:0] S_AXI_HP2_RID;
output [63:0] S_AXI_HP2_RDATA;
output [7:0] S_AXI_HP2_RCOUNT;
output [7:0] S_AXI_HP2_WCOUNT;
output [2:0] S_AXI_HP2_RACOUNT;
output [5:0] S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0] S_AXI_HP2_ARBURST;
input [1:0] S_AXI_HP2_ARLOCK;
input [2:0] S_AXI_HP2_ARSIZE;
input [1:0] S_AXI_HP2_AWBURST;
input [1:0] S_AXI_HP2_AWLOCK;
input [2:0] S_AXI_HP2_AWSIZE;
input [2:0] S_AXI_HP2_ARPROT;
input [2:0] S_AXI_HP2_AWPROT;
input [31:0] S_AXI_HP2_ARADDR;
input [31:0] S_AXI_HP2_AWADDR;
input [3:0] S_AXI_HP2_ARCACHE;
input [3:0] S_AXI_HP2_ARLEN;
input [3:0] S_AXI_HP2_ARQOS;
input [3:0] S_AXI_HP2_AWCACHE;
input [3:0] S_AXI_HP2_AWLEN;
input [3:0] S_AXI_HP2_AWQOS;
input [5:0] S_AXI_HP2_ARID;
input [5:0] S_AXI_HP2_AWID;
input [5:0] S_AXI_HP2_WID;
input [63:0] S_AXI_HP2_WDATA;
input [7:0] S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0] S_AXI_HP3_BRESP;
output [1:0] S_AXI_HP3_RRESP;
output [5:0] S_AXI_HP3_BID;
output [5:0] S_AXI_HP3_RID;
output [63:0] S_AXI_HP3_RDATA;
output [7:0] S_AXI_HP3_RCOUNT;
output [7:0] S_AXI_HP3_WCOUNT;
output [2:0] S_AXI_HP3_RACOUNT;
output [5:0] S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0] S_AXI_HP3_ARBURST;
input [1:0] S_AXI_HP3_ARLOCK;
input [2:0] S_AXI_HP3_ARSIZE;
input [1:0] S_AXI_HP3_AWBURST;
input [1:0] S_AXI_HP3_AWLOCK;
input [2:0] S_AXI_HP3_AWSIZE;
input [2:0] S_AXI_HP3_ARPROT;
input [2:0] S_AXI_HP3_AWPROT;
input [31:0] S_AXI_HP3_ARADDR;
input [31:0] S_AXI_HP3_AWADDR;
input [3:0] S_AXI_HP3_ARCACHE;
input [3:0] S_AXI_HP3_ARLEN;
input [3:0] S_AXI_HP3_ARQOS;
input [3:0] S_AXI_HP3_AWCACHE;
input [3:0] S_AXI_HP3_AWLEN;
input [3:0] S_AXI_HP3_AWQOS;
input [5:0] S_AXI_HP3_ARID;
input [5:0] S_AXI_HP3_AWID;
input [5:0] S_AXI_HP3_WID;
input [63:0] S_AXI_HP3_WDATA;
input [7:0] S_AXI_HP3_WSTRB;
output [1:0] DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input [1:0] DMA0_DRTYPE;
output [1:0] DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input [1:0] DMA1_DRTYPE;
output [1:0] DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_DRVALID;
output [1:0] DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input [1:0] DMA2_DRTYPE;
input [1:0] DMA3_DRTYPE;
input [31:0] FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0] FTMD_TRACEIN_ATID;
input [3:0] FTMT_F2P_TRIG;
output [3:0] FTMT_F2P_TRIGACK;
input [31:0] FTMT_F2P_DEBUG;
input [3:0] FTMT_P2F_TRIGACK;
output [3:0] FTMT_P2F_TRIG;
output [31:0] FTMT_P2F_DEBUG;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input FPGA_IDLE_N;
input [3:0] DDR_ARB;
input [0:0] IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output EVENT_EVENTO;
output [1:0] EVENT_STANDBYWFE;
output [1:0] EVENT_STANDBYWFI;
input EVENT_EVENTI;
inout [53:0] MIO;
inout DDR_Clk;
inout DDR_Clk_n;
inout DDR_CKE;
inout DDR_CS_n;
inout DDR_RAS_n;
inout DDR_CAS_n;
output DDR_WEB;
inout [2:0] DDR_BankAddr;
inout [14:0] DDR_Addr;
inout DDR_ODT;
inout DDR_DRSTB;
inout [31:0] DDR_DQ;
inout [3:0] DDR_DM;
inout [3:0] DDR_DQS;
inout [3:0] DDR_DQS_n;
inout DDR_VRN;
inout DDR_VRP;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
(* CORE_GENERATION_INFO = "processing_system7_0,processing_system7,{C_ENET0_PERIPHERAL_ENABLE = 1,C_USB0_PERIPHERAL_ENABLE = 1,C_QSPI_PERIPHERAL_ENABLE = 1,C_DDR_V4.00.A_C_S_AXI_HP3_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP2_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP1_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP0_BASEADDR = 0x00000000,C_DDR_V4.00.A_C_S_AXI_HP3_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP2_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP1_HIGHADDR = 0x3FFFFFFF,C_DDR_V4.00.A_C_S_AXI_HP0_HIGHADDR = 0x3FFFFFFF,C_GPIO_PERIPHERAL_ENABLE = 1,C_GPIO_V2.00.A_C_EN_EMIO_GPIO = 0,C:GPIO_EMIO_GPIO_WIDTH = 64,C_CAN_PERIPHERAL_FREQMHZ = 100,C_FPGA3_PERIPHERAL_FREQMHZ = 25.000000,C_FPGA0_PERIPHERAL_FREQMHZ = 100.000000,C_PRESET_GLOBAL_DEFAULT = powerup,C_FPGA1_PERIPHERAL_FREQMHZ = 150.000000,C_PRESET_GLOBAL_CONFIG = Default,C_PRESET_FPGA_SPEED = -1,C_PRESET_FPGA_PARTNUMBER = xc7z020clg484-1,C_SD0_PERIPHERAL_ENABLE = 1,C_UART1_PERIPHERAL_ENABLE = 1}" *)
processing_system7
#(
.C_EN_EMIO_ENET0 ( 1 ),
.C_EN_EMIO_ENET1 ( 0 ),
.C_EN_EMIO_TRACE ( 0 ),
.C_INCLUDE_TRACE_BUFFER ( 0 ),
.C_TRACE_BUFFER_FIFO_SIZE ( 128 ),
.USE_TRACE_DATA_EDGE_DETECTOR ( 0 ),
.C_TRACE_BUFFER_CLOCK_DELAY ( 12 ),
.C_EMIO_GPIO_WIDTH ( 64 ),
.C_INCLUDE_ACP_TRANS_CHECK ( 0 ),
.C_USE_DEFAULT_ACP_USER_VAL ( 0 ),
.C_S_AXI_ACP_ARUSER_VAL ( 31 ),
.C_S_AXI_ACP_AWUSER_VAL ( 31 ),
.C_DQ_WIDTH ( 32 ),
.C_DQS_WIDTH ( 4 ),
.C_DM_WIDTH ( 4 ),
.C_MIO_PRIMITIVE ( 54 ),
.C_PACKAGE_NAME ( "clg484" ),
.C_PS7_SI_REV ( "PRODUCTION" ),
.C_M_AXI_GP0_ID_WIDTH ( 12 ),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP ( 0 ),
.C_M_AXI_GP1_ID_WIDTH ( 12 ),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP ( 0 ),
.C_S_AXI_GP0_ID_WIDTH ( 6 ),
.C_S_AXI_GP1_ID_WIDTH ( 6 ),
.C_S_AXI_ACP_ID_WIDTH ( 3 ),
.C_S_AXI_HP0_ID_WIDTH ( 2 ),
.C_S_AXI_HP0_DATA_WIDTH ( 64 ),
.C_S_AXI_HP1_ID_WIDTH ( 6 ),
.C_S_AXI_HP1_DATA_WIDTH ( 64 ),
.C_S_AXI_HP2_ID_WIDTH ( 6 ),
.C_S_AXI_HP2_DATA_WIDTH ( 64 ),
.C_S_AXI_HP3_ID_WIDTH ( 6 ),
.C_S_AXI_HP3_DATA_WIDTH ( 64 ),
.C_M_AXI_GP0_THREAD_ID_WIDTH ( 12 ),
.C_M_AXI_GP1_THREAD_ID_WIDTH ( 12 ),
.C_NUM_F2P_INTR_INPUTS ( 1 ),
.C_FCLK_CLK0_BUF ( "TRUE" ),
.C_FCLK_CLK1_BUF ( "FALSE" ),
.C_FCLK_CLK2_BUF ( "FALSE" ),
.C_FCLK_CLK3_BUF ( "TRUE" )
)
processing_system7_0 (
.CAN0_PHY_TX ( CAN0_PHY_TX ),
.CAN0_PHY_RX ( CAN0_PHY_RX ),
.CAN1_PHY_TX ( CAN1_PHY_TX ),
.CAN1_PHY_RX ( CAN1_PHY_RX ),
.ENET0_GMII_TX_EN ( ENET0_GMII_TX_EN ),
.ENET0_GMII_TX_ER ( ENET0_GMII_TX_ER ),
.ENET0_MDIO_MDC ( ENET0_MDIO_MDC ),
.ENET0_MDIO_O ( ENET0_MDIO_O ),
.ENET0_MDIO_T ( ENET0_MDIO_T ),
.ENET0_PTP_DELAY_REQ_RX ( ENET0_PTP_DELAY_REQ_RX ),
.ENET0_PTP_DELAY_REQ_TX ( ENET0_PTP_DELAY_REQ_TX ),
.ENET0_PTP_PDELAY_REQ_RX ( ENET0_PTP_PDELAY_REQ_RX ),
.ENET0_PTP_PDELAY_REQ_TX ( ENET0_PTP_PDELAY_REQ_TX ),
.ENET0_PTP_PDELAY_RESP_RX ( ENET0_PTP_PDELAY_RESP_RX ),
.ENET0_PTP_PDELAY_RESP_TX ( ENET0_PTP_PDELAY_RESP_TX ),
.ENET0_PTP_SYNC_FRAME_RX ( ENET0_PTP_SYNC_FRAME_RX ),
.ENET0_PTP_SYNC_FRAME_TX ( ENET0_PTP_SYNC_FRAME_TX ),
.ENET0_SOF_RX ( ENET0_SOF_RX ),
.ENET0_SOF_TX ( ENET0_SOF_TX ),
.ENET0_GMII_TXD ( ENET0_GMII_TXD ),
.ENET0_GMII_COL ( ENET0_GMII_COL ),
.ENET0_GMII_CRS ( ENET0_GMII_CRS ),
.ENET0_EXT_INTIN ( ENET0_EXT_INTIN ),
.ENET0_GMII_RX_CLK ( ENET0_GMII_RX_CLK ),
.ENET0_GMII_RX_DV ( ENET0_GMII_RX_DV ),
.ENET0_GMII_RX_ER ( ENET0_GMII_RX_ER ),
.ENET0_GMII_TX_CLK ( ENET0_GMII_TX_CLK ),
.ENET0_MDIO_I ( ENET0_MDIO_I ),
.ENET0_GMII_RXD ( ENET0_GMII_RXD ),
.ENET1_GMII_TX_EN ( ENET1_GMII_TX_EN ),
.ENET1_GMII_TX_ER ( ENET1_GMII_TX_ER ),
.ENET1_MDIO_MDC ( ENET1_MDIO_MDC ),
.ENET1_MDIO_O ( ENET1_MDIO_O ),
.ENET1_MDIO_T ( ENET1_MDIO_T ),
.ENET1_PTP_DELAY_REQ_RX ( ENET1_PTP_DELAY_REQ_RX ),
.ENET1_PTP_DELAY_REQ_TX ( ENET1_PTP_DELAY_REQ_TX ),
.ENET1_PTP_PDELAY_REQ_RX ( ENET1_PTP_PDELAY_REQ_RX ),
.ENET1_PTP_PDELAY_REQ_TX ( ENET1_PTP_PDELAY_REQ_TX ),
.ENET1_PTP_PDELAY_RESP_RX ( ENET1_PTP_PDELAY_RESP_RX ),
.ENET1_PTP_PDELAY_RESP_TX ( ENET1_PTP_PDELAY_RESP_TX ),
.ENET1_PTP_SYNC_FRAME_RX ( ENET1_PTP_SYNC_FRAME_RX ),
.ENET1_PTP_SYNC_FRAME_TX ( ENET1_PTP_SYNC_FRAME_TX ),
.ENET1_SOF_RX ( ENET1_SOF_RX ),
.ENET1_SOF_TX ( ENET1_SOF_TX ),
.ENET1_GMII_TXD ( ENET1_GMII_TXD ),
.ENET1_GMII_COL ( ENET1_GMII_COL ),
.ENET1_GMII_CRS ( ENET1_GMII_CRS ),
.ENET1_EXT_INTIN ( ENET1_EXT_INTIN ),
.ENET1_GMII_RX_CLK ( ENET1_GMII_RX_CLK ),
.ENET1_GMII_RX_DV ( ENET1_GMII_RX_DV ),
.ENET1_GMII_RX_ER ( ENET1_GMII_RX_ER ),
.ENET1_GMII_TX_CLK ( ENET1_GMII_TX_CLK ),
.ENET1_MDIO_I ( ENET1_MDIO_I ),
.ENET1_GMII_RXD ( ENET1_GMII_RXD ),
.GPIO_I ( GPIO_I ),
.GPIO_O ( GPIO_O ),
.GPIO_T ( GPIO_T ),
.I2C0_SDA_I ( I2C0_SDA_I ),
.I2C0_SDA_O ( I2C0_SDA_O ),
.I2C0_SDA_T ( I2C0_SDA_T ),
.I2C0_SCL_I ( I2C0_SCL_I ),
.I2C0_SCL_O ( I2C0_SCL_O ),
.I2C0_SCL_T ( I2C0_SCL_T ),
.I2C1_SDA_I ( I2C1_SDA_I ),
.I2C1_SDA_O ( I2C1_SDA_O ),
.I2C1_SDA_T ( I2C1_SDA_T ),
.I2C1_SCL_I ( I2C1_SCL_I ),
.I2C1_SCL_O ( I2C1_SCL_O ),
.I2C1_SCL_T ( I2C1_SCL_T ),
.PJTAG_TCK ( PJTAG_TCK ),
.PJTAG_TMS ( PJTAG_TMS ),
.PJTAG_TD_I ( PJTAG_TD_I ),
.PJTAG_TD_T ( PJTAG_TD_T ),
.PJTAG_TD_O ( PJTAG_TD_O ),
.SDIO0_CLK ( SDIO0_CLK ),
.SDIO0_CLK_FB ( SDIO0_CLK_FB ),
.SDIO0_CMD_O ( SDIO0_CMD_O ),
.SDIO0_CMD_I ( SDIO0_CMD_I ),
.SDIO0_CMD_T ( SDIO0_CMD_T ),
.SDIO0_DATA_I ( SDIO0_DATA_I ),
.SDIO0_DATA_O ( SDIO0_DATA_O ),
.SDIO0_DATA_T ( SDIO0_DATA_T ),
.SDIO0_LED ( SDIO0_LED ),
.SDIO0_CDN ( SDIO0_CDN ),
.SDIO0_WP ( SDIO0_WP ),
.SDIO0_BUSPOW ( SDIO0_BUSPOW ),
.SDIO0_BUSVOLT ( SDIO0_BUSVOLT ),
.SDIO1_CLK ( SDIO1_CLK ),
.SDIO1_CLK_FB ( SDIO1_CLK_FB ),
.SDIO1_CMD_O ( SDIO1_CMD_O ),
.SDIO1_CMD_I ( SDIO1_CMD_I ),
.SDIO1_CMD_T ( SDIO1_CMD_T ),
.SDIO1_DATA_I ( SDIO1_DATA_I ),
.SDIO1_DATA_O ( SDIO1_DATA_O ),
.SDIO1_DATA_T ( SDIO1_DATA_T ),
.SDIO1_LED ( SDIO1_LED ),
.SDIO1_CDN ( SDIO1_CDN ),
.SDIO1_WP ( SDIO1_WP ),
.SDIO1_BUSPOW ( SDIO1_BUSPOW ),
.SDIO1_BUSVOLT ( SDIO1_BUSVOLT ),
.SPI0_SCLK_I ( SPI0_SCLK_I ),
.SPI0_SCLK_O ( SPI0_SCLK_O ),
.SPI0_SCLK_T ( SPI0_SCLK_T ),
.SPI0_MOSI_I ( SPI0_MOSI_I ),
.SPI0_MOSI_O ( SPI0_MOSI_O ),
.SPI0_MOSI_T ( SPI0_MOSI_T ),
.SPI0_MISO_I ( SPI0_MISO_I ),
.SPI0_MISO_O ( SPI0_MISO_O ),
.SPI0_MISO_T ( SPI0_MISO_T ),
.SPI0_SS_I ( SPI0_SS_I ),
.SPI0_SS_O ( SPI0_SS_O ),
.SPI0_SS1_O ( SPI0_SS1_O ),
.SPI0_SS2_O ( SPI0_SS2_O ),
.SPI0_SS_T ( SPI0_SS_T ),
.SPI1_SCLK_I ( SPI1_SCLK_I ),
.SPI1_SCLK_O ( SPI1_SCLK_O ),
.SPI1_SCLK_T ( SPI1_SCLK_T ),
.SPI1_MOSI_I ( SPI1_MOSI_I ),
.SPI1_MOSI_O ( SPI1_MOSI_O ),
.SPI1_MOSI_T ( SPI1_MOSI_T ),
.SPI1_MISO_I ( SPI1_MISO_I ),
.SPI1_MISO_O ( SPI1_MISO_O ),
.SPI1_MISO_T ( SPI1_MISO_T ),
.SPI1_SS_I ( SPI1_SS_I ),
.SPI1_SS_O ( SPI1_SS_O ),
.SPI1_SS1_O ( SPI1_SS1_O ),
.SPI1_SS2_O ( SPI1_SS2_O ),
.SPI1_SS_T ( SPI1_SS_T ),
.UART0_DTRN ( UART0_DTRN ),
.UART0_RTSN ( UART0_RTSN ),
.UART0_TX ( UART0_TX ),
.UART0_CTSN ( UART0_CTSN ),
.UART0_DCDN ( UART0_DCDN ),
.UART0_DSRN ( UART0_DSRN ),
.UART0_RIN ( UART0_RIN ),
.UART0_RX ( UART0_RX ),
.UART1_DTRN ( UART1_DTRN ),
.UART1_RTSN ( UART1_RTSN ),
.UART1_TX ( UART1_TX ),
.UART1_CTSN ( UART1_CTSN ),
.UART1_DCDN ( UART1_DCDN ),
.UART1_DSRN ( UART1_DSRN ),
.UART1_RIN ( UART1_RIN ),
.UART1_RX ( UART1_RX ),
.TTC0_WAVE0_OUT ( TTC0_WAVE0_OUT ),
.TTC0_WAVE1_OUT ( TTC0_WAVE1_OUT ),
.TTC0_WAVE2_OUT ( TTC0_WAVE2_OUT ),
.TTC0_CLK0_IN ( TTC0_CLK0_IN ),
.TTC0_CLK1_IN ( TTC0_CLK1_IN ),
.TTC0_CLK2_IN ( TTC0_CLK2_IN ),
.TTC1_WAVE0_OUT ( TTC1_WAVE0_OUT ),
.TTC1_WAVE1_OUT ( TTC1_WAVE1_OUT ),
.TTC1_WAVE2_OUT ( TTC1_WAVE2_OUT ),
.TTC1_CLK0_IN ( TTC1_CLK0_IN ),
.TTC1_CLK1_IN ( TTC1_CLK1_IN ),
.TTC1_CLK2_IN ( TTC1_CLK2_IN ),
.WDT_CLK_IN ( WDT_CLK_IN ),
.WDT_RST_OUT ( WDT_RST_OUT ),
.TRACE_CLK ( TRACE_CLK ),
.TRACE_CTL ( TRACE_CTL ),
.TRACE_DATA ( TRACE_DATA ),
.USB0_PORT_INDCTL ( USB0_PORT_INDCTL ),
.USB1_PORT_INDCTL ( USB1_PORT_INDCTL ),
.USB0_VBUS_PWRSELECT ( USB0_VBUS_PWRSELECT ),
.USB1_VBUS_PWRSELECT ( USB1_VBUS_PWRSELECT ),
.USB0_VBUS_PWRFAULT ( USB0_VBUS_PWRFAULT ),
.USB1_VBUS_PWRFAULT ( USB1_VBUS_PWRFAULT ),
.SRAM_INTIN ( SRAM_INTIN ),
.M_AXI_GP0_ARESETN ( M_AXI_GP0_ARESETN ),
.M_AXI_GP0_ARVALID ( M_AXI_GP0_ARVALID ),
.M_AXI_GP0_AWVALID ( M_AXI_GP0_AWVALID ),
.M_AXI_GP0_BREADY ( M_AXI_GP0_BREADY ),
.M_AXI_GP0_RREADY ( M_AXI_GP0_RREADY ),
.M_AXI_GP0_WLAST ( M_AXI_GP0_WLAST ),
.M_AXI_GP0_WVALID ( M_AXI_GP0_WVALID ),
.M_AXI_GP0_ARID ( M_AXI_GP0_ARID ),
.M_AXI_GP0_AWID ( M_AXI_GP0_AWID ),
.M_AXI_GP0_WID ( M_AXI_GP0_WID ),
.M_AXI_GP0_ARBURST ( M_AXI_GP0_ARBURST ),
.M_AXI_GP0_ARLOCK ( M_AXI_GP0_ARLOCK ),
.M_AXI_GP0_ARSIZE ( M_AXI_GP0_ARSIZE ),
.M_AXI_GP0_AWBURST ( M_AXI_GP0_AWBURST ),
.M_AXI_GP0_AWLOCK ( M_AXI_GP0_AWLOCK ),
.M_AXI_GP0_AWSIZE ( M_AXI_GP0_AWSIZE ),
.M_AXI_GP0_ARPROT ( M_AXI_GP0_ARPROT ),
.M_AXI_GP0_AWPROT ( M_AXI_GP0_AWPROT ),
.M_AXI_GP0_ARADDR ( M_AXI_GP0_ARADDR ),
.M_AXI_GP0_AWADDR ( M_AXI_GP0_AWADDR ),
.M_AXI_GP0_WDATA ( M_AXI_GP0_WDATA ),
.M_AXI_GP0_ARCACHE ( M_AXI_GP0_ARCACHE ),
.M_AXI_GP0_ARLEN ( M_AXI_GP0_ARLEN ),
.M_AXI_GP0_ARQOS ( M_AXI_GP0_ARQOS ),
.M_AXI_GP0_AWCACHE ( M_AXI_GP0_AWCACHE ),
.M_AXI_GP0_AWLEN ( M_AXI_GP0_AWLEN ),
.M_AXI_GP0_AWQOS ( M_AXI_GP0_AWQOS ),
.M_AXI_GP0_WSTRB ( M_AXI_GP0_WSTRB ),
.M_AXI_GP0_ACLK ( M_AXI_GP0_ACLK ),
.M_AXI_GP0_ARREADY ( M_AXI_GP0_ARREADY ),
.M_AXI_GP0_AWREADY ( M_AXI_GP0_AWREADY ),
.M_AXI_GP0_BVALID ( M_AXI_GP0_BVALID ),
.M_AXI_GP0_RLAST ( M_AXI_GP0_RLAST ),
.M_AXI_GP0_RVALID ( M_AXI_GP0_RVALID ),
.M_AXI_GP0_WREADY ( M_AXI_GP0_WREADY ),
.M_AXI_GP0_BID ( M_AXI_GP0_BID ),
.M_AXI_GP0_RID ( M_AXI_GP0_RID ),
.M_AXI_GP0_BRESP ( M_AXI_GP0_BRESP ),
.M_AXI_GP0_RRESP ( M_AXI_GP0_RRESP ),
.M_AXI_GP0_RDATA ( M_AXI_GP0_RDATA ),
.M_AXI_GP1_ARESETN ( M_AXI_GP1_ARESETN ),
.M_AXI_GP1_ARVALID ( M_AXI_GP1_ARVALID ),
.M_AXI_GP1_AWVALID ( M_AXI_GP1_AWVALID ),
.M_AXI_GP1_BREADY ( M_AXI_GP1_BREADY ),
.M_AXI_GP1_RREADY ( M_AXI_GP1_RREADY ),
.M_AXI_GP1_WLAST ( M_AXI_GP1_WLAST ),
.M_AXI_GP1_WVALID ( M_AXI_GP1_WVALID ),
.M_AXI_GP1_ARID ( M_AXI_GP1_ARID ),
.M_AXI_GP1_AWID ( M_AXI_GP1_AWID ),
.M_AXI_GP1_WID ( M_AXI_GP1_WID ),
.M_AXI_GP1_ARBURST ( M_AXI_GP1_ARBURST ),
.M_AXI_GP1_ARLOCK ( M_AXI_GP1_ARLOCK ),
.M_AXI_GP1_ARSIZE ( M_AXI_GP1_ARSIZE ),
.M_AXI_GP1_AWBURST ( M_AXI_GP1_AWBURST ),
.M_AXI_GP1_AWLOCK ( M_AXI_GP1_AWLOCK ),
.M_AXI_GP1_AWSIZE ( M_AXI_GP1_AWSIZE ),
.M_AXI_GP1_ARPROT ( M_AXI_GP1_ARPROT ),
.M_AXI_GP1_AWPROT ( M_AXI_GP1_AWPROT ),
.M_AXI_GP1_ARADDR ( M_AXI_GP1_ARADDR ),
.M_AXI_GP1_AWADDR ( M_AXI_GP1_AWADDR ),
.M_AXI_GP1_WDATA ( M_AXI_GP1_WDATA ),
.M_AXI_GP1_ARCACHE ( M_AXI_GP1_ARCACHE ),
.M_AXI_GP1_ARLEN ( M_AXI_GP1_ARLEN ),
.M_AXI_GP1_ARQOS ( M_AXI_GP1_ARQOS ),
.M_AXI_GP1_AWCACHE ( M_AXI_GP1_AWCACHE ),
.M_AXI_GP1_AWLEN ( M_AXI_GP1_AWLEN ),
.M_AXI_GP1_AWQOS ( M_AXI_GP1_AWQOS ),
.M_AXI_GP1_WSTRB ( M_AXI_GP1_WSTRB ),
.M_AXI_GP1_ACLK ( M_AXI_GP1_ACLK ),
.M_AXI_GP1_ARREADY ( M_AXI_GP1_ARREADY ),
.M_AXI_GP1_AWREADY ( M_AXI_GP1_AWREADY ),
.M_AXI_GP1_BVALID ( M_AXI_GP1_BVALID ),
.M_AXI_GP1_RLAST ( M_AXI_GP1_RLAST ),
.M_AXI_GP1_RVALID ( M_AXI_GP1_RVALID ),
.M_AXI_GP1_WREADY ( M_AXI_GP1_WREADY ),
.M_AXI_GP1_BID ( M_AXI_GP1_BID ),
.M_AXI_GP1_RID ( M_AXI_GP1_RID ),
.M_AXI_GP1_BRESP ( M_AXI_GP1_BRESP ),
.M_AXI_GP1_RRESP ( M_AXI_GP1_RRESP ),
.M_AXI_GP1_RDATA ( M_AXI_GP1_RDATA ),
.S_AXI_GP0_ARESETN ( S_AXI_GP0_ARESETN ),
.S_AXI_GP0_ARREADY ( S_AXI_GP0_ARREADY ),
.S_AXI_GP0_AWREADY ( S_AXI_GP0_AWREADY ),
.S_AXI_GP0_BVALID ( S_AXI_GP0_BVALID ),
.S_AXI_GP0_RLAST ( S_AXI_GP0_RLAST ),
.S_AXI_GP0_RVALID ( S_AXI_GP0_RVALID ),
.S_AXI_GP0_WREADY ( S_AXI_GP0_WREADY ),
.S_AXI_GP0_BRESP ( S_AXI_GP0_BRESP ),
.S_AXI_GP0_RRESP ( S_AXI_GP0_RRESP ),
.S_AXI_GP0_RDATA ( S_AXI_GP0_RDATA ),
.S_AXI_GP0_BID ( S_AXI_GP0_BID ),
.S_AXI_GP0_RID ( S_AXI_GP0_RID ),
.S_AXI_GP0_ACLK ( S_AXI_GP0_ACLK ),
.S_AXI_GP0_ARVALID ( S_AXI_GP0_ARVALID ),
.S_AXI_GP0_AWVALID ( S_AXI_GP0_AWVALID ),
.S_AXI_GP0_BREADY ( S_AXI_GP0_BREADY ),
.S_AXI_GP0_RREADY ( S_AXI_GP0_RREADY ),
.S_AXI_GP0_WLAST ( S_AXI_GP0_WLAST ),
.S_AXI_GP0_WVALID ( S_AXI_GP0_WVALID ),
.S_AXI_GP0_ARBURST ( S_AXI_GP0_ARBURST ),
.S_AXI_GP0_ARLOCK ( S_AXI_GP0_ARLOCK ),
.S_AXI_GP0_ARSIZE ( S_AXI_GP0_ARSIZE ),
.S_AXI_GP0_AWBURST ( S_AXI_GP0_AWBURST ),
.S_AXI_GP0_AWLOCK ( S_AXI_GP0_AWLOCK ),
.S_AXI_GP0_AWSIZE ( S_AXI_GP0_AWSIZE ),
.S_AXI_GP0_ARPROT ( S_AXI_GP0_ARPROT ),
.S_AXI_GP0_AWPROT ( S_AXI_GP0_AWPROT ),
.S_AXI_GP0_ARADDR ( S_AXI_GP0_ARADDR ),
.S_AXI_GP0_AWADDR ( S_AXI_GP0_AWADDR ),
.S_AXI_GP0_WDATA ( S_AXI_GP0_WDATA ),
.S_AXI_GP0_ARCACHE ( S_AXI_GP0_ARCACHE ),
.S_AXI_GP0_ARLEN ( S_AXI_GP0_ARLEN ),
.S_AXI_GP0_ARQOS ( S_AXI_GP0_ARQOS ),
.S_AXI_GP0_AWCACHE ( S_AXI_GP0_AWCACHE ),
.S_AXI_GP0_AWLEN ( S_AXI_GP0_AWLEN ),
.S_AXI_GP0_AWQOS ( S_AXI_GP0_AWQOS ),
.S_AXI_GP0_WSTRB ( S_AXI_GP0_WSTRB ),
.S_AXI_GP0_ARID ( S_AXI_GP0_ARID ),
.S_AXI_GP0_AWID ( S_AXI_GP0_AWID ),
.S_AXI_GP0_WID ( S_AXI_GP0_WID ),
.S_AXI_GP1_ARESETN ( S_AXI_GP1_ARESETN ),
.S_AXI_GP1_ARREADY ( S_AXI_GP1_ARREADY ),
.S_AXI_GP1_AWREADY ( S_AXI_GP1_AWREADY ),
.S_AXI_GP1_BVALID ( S_AXI_GP1_BVALID ),
.S_AXI_GP1_RLAST ( S_AXI_GP1_RLAST ),
.S_AXI_GP1_RVALID ( S_AXI_GP1_RVALID ),
.S_AXI_GP1_WREADY ( S_AXI_GP1_WREADY ),
.S_AXI_GP1_BRESP ( S_AXI_GP1_BRESP ),
.S_AXI_GP1_RRESP ( S_AXI_GP1_RRESP ),
.S_AXI_GP1_RDATA ( S_AXI_GP1_RDATA ),
.S_AXI_GP1_BID ( S_AXI_GP1_BID ),
.S_AXI_GP1_RID ( S_AXI_GP1_RID ),
.S_AXI_GP1_ACLK ( S_AXI_GP1_ACLK ),
.S_AXI_GP1_ARVALID ( S_AXI_GP1_ARVALID ),
.S_AXI_GP1_AWVALID ( S_AXI_GP1_AWVALID ),
.S_AXI_GP1_BREADY ( S_AXI_GP1_BREADY ),
.S_AXI_GP1_RREADY ( S_AXI_GP1_RREADY ),
.S_AXI_GP1_WLAST ( S_AXI_GP1_WLAST ),
.S_AXI_GP1_WVALID ( S_AXI_GP1_WVALID ),
.S_AXI_GP1_ARBURST ( S_AXI_GP1_ARBURST ),
.S_AXI_GP1_ARLOCK ( S_AXI_GP1_ARLOCK ),
.S_AXI_GP1_ARSIZE ( S_AXI_GP1_ARSIZE ),
.S_AXI_GP1_AWBURST ( S_AXI_GP1_AWBURST ),
.S_AXI_GP1_AWLOCK ( S_AXI_GP1_AWLOCK ),
.S_AXI_GP1_AWSIZE ( S_AXI_GP1_AWSIZE ),
.S_AXI_GP1_ARPROT ( S_AXI_GP1_ARPROT ),
.S_AXI_GP1_AWPROT ( S_AXI_GP1_AWPROT ),
.S_AXI_GP1_ARADDR ( S_AXI_GP1_ARADDR ),
.S_AXI_GP1_AWADDR ( S_AXI_GP1_AWADDR ),
.S_AXI_GP1_WDATA ( S_AXI_GP1_WDATA ),
.S_AXI_GP1_ARCACHE ( S_AXI_GP1_ARCACHE ),
.S_AXI_GP1_ARLEN ( S_AXI_GP1_ARLEN ),
.S_AXI_GP1_ARQOS ( S_AXI_GP1_ARQOS ),
.S_AXI_GP1_AWCACHE ( S_AXI_GP1_AWCACHE ),
.S_AXI_GP1_AWLEN ( S_AXI_GP1_AWLEN ),
.S_AXI_GP1_AWQOS ( S_AXI_GP1_AWQOS ),
.S_AXI_GP1_WSTRB ( S_AXI_GP1_WSTRB ),
.S_AXI_GP1_ARID ( S_AXI_GP1_ARID ),
.S_AXI_GP1_AWID ( S_AXI_GP1_AWID ),
.S_AXI_GP1_WID ( S_AXI_GP1_WID ),
.S_AXI_ACP_ARESETN ( S_AXI_ACP_ARESETN ),
.S_AXI_ACP_AWREADY ( S_AXI_ACP_AWREADY ),
.S_AXI_ACP_ARREADY ( S_AXI_ACP_ARREADY ),
.S_AXI_ACP_BVALID ( S_AXI_ACP_BVALID ),
.S_AXI_ACP_RLAST ( S_AXI_ACP_RLAST ),
.S_AXI_ACP_RVALID ( S_AXI_ACP_RVALID ),
.S_AXI_ACP_WREADY ( S_AXI_ACP_WREADY ),
.S_AXI_ACP_BRESP ( S_AXI_ACP_BRESP ),
.S_AXI_ACP_RRESP ( S_AXI_ACP_RRESP ),
.S_AXI_ACP_BID ( S_AXI_ACP_BID ),
.S_AXI_ACP_RID ( S_AXI_ACP_RID ),
.S_AXI_ACP_RDATA ( S_AXI_ACP_RDATA ),
.S_AXI_ACP_ACLK ( S_AXI_ACP_ACLK ),
.S_AXI_ACP_ARVALID ( S_AXI_ACP_ARVALID ),
.S_AXI_ACP_AWVALID ( S_AXI_ACP_AWVALID ),
.S_AXI_ACP_BREADY ( S_AXI_ACP_BREADY ),
.S_AXI_ACP_RREADY ( S_AXI_ACP_RREADY ),
.S_AXI_ACP_WLAST ( S_AXI_ACP_WLAST ),
.S_AXI_ACP_WVALID ( S_AXI_ACP_WVALID ),
.S_AXI_ACP_ARID ( S_AXI_ACP_ARID ),
.S_AXI_ACP_ARPROT ( S_AXI_ACP_ARPROT ),
.S_AXI_ACP_AWID ( S_AXI_ACP_AWID ),
.S_AXI_ACP_AWPROT ( S_AXI_ACP_AWPROT ),
.S_AXI_ACP_WID ( S_AXI_ACP_WID ),
.S_AXI_ACP_ARADDR ( S_AXI_ACP_ARADDR ),
.S_AXI_ACP_AWADDR ( S_AXI_ACP_AWADDR ),
.S_AXI_ACP_ARCACHE ( S_AXI_ACP_ARCACHE ),
.S_AXI_ACP_ARLEN ( S_AXI_ACP_ARLEN ),
.S_AXI_ACP_ARQOS ( S_AXI_ACP_ARQOS ),
.S_AXI_ACP_AWCACHE ( S_AXI_ACP_AWCACHE ),
.S_AXI_ACP_AWLEN ( S_AXI_ACP_AWLEN ),
.S_AXI_ACP_AWQOS ( S_AXI_ACP_AWQOS ),
.S_AXI_ACP_ARBURST ( S_AXI_ACP_ARBURST ),
.S_AXI_ACP_ARLOCK ( S_AXI_ACP_ARLOCK ),
.S_AXI_ACP_ARSIZE ( S_AXI_ACP_ARSIZE ),
.S_AXI_ACP_AWBURST ( S_AXI_ACP_AWBURST ),
.S_AXI_ACP_AWLOCK ( S_AXI_ACP_AWLOCK ),
.S_AXI_ACP_AWSIZE ( S_AXI_ACP_AWSIZE ),
.S_AXI_ACP_ARUSER ( S_AXI_ACP_ARUSER ),
.S_AXI_ACP_AWUSER ( S_AXI_ACP_AWUSER ),
.S_AXI_ACP_WDATA ( S_AXI_ACP_WDATA ),
.S_AXI_ACP_WSTRB ( S_AXI_ACP_WSTRB ),
.S_AXI_HP0_ARESETN ( S_AXI_HP0_ARESETN ),
.S_AXI_HP0_ARREADY ( S_AXI_HP0_ARREADY ),
.S_AXI_HP0_AWREADY ( S_AXI_HP0_AWREADY ),
.S_AXI_HP0_BVALID ( S_AXI_HP0_BVALID ),
.S_AXI_HP0_RLAST ( S_AXI_HP0_RLAST ),
.S_AXI_HP0_RVALID ( S_AXI_HP0_RVALID ),
.S_AXI_HP0_WREADY ( S_AXI_HP0_WREADY ),
.S_AXI_HP0_BRESP ( S_AXI_HP0_BRESP ),
.S_AXI_HP0_RRESP ( S_AXI_HP0_RRESP ),
.S_AXI_HP0_BID ( S_AXI_HP0_BID ),
.S_AXI_HP0_RID ( S_AXI_HP0_RID ),
.S_AXI_HP0_RDATA ( S_AXI_HP0_RDATA ),
.S_AXI_HP0_RCOUNT ( S_AXI_HP0_RCOUNT ),
.S_AXI_HP0_WCOUNT ( S_AXI_HP0_WCOUNT ),
.S_AXI_HP0_RACOUNT ( S_AXI_HP0_RACOUNT ),
.S_AXI_HP0_WACOUNT ( S_AXI_HP0_WACOUNT ),
.S_AXI_HP0_ACLK ( S_AXI_HP0_ACLK ),
.S_AXI_HP0_ARVALID ( S_AXI_HP0_ARVALID ),
.S_AXI_HP0_AWVALID ( S_AXI_HP0_AWVALID ),
.S_AXI_HP0_BREADY ( S_AXI_HP0_BREADY ),
.S_AXI_HP0_RDISSUECAP1_EN ( S_AXI_HP0_RDISSUECAP1_EN ),
.S_AXI_HP0_RREADY ( S_AXI_HP0_RREADY ),
.S_AXI_HP0_WLAST ( S_AXI_HP0_WLAST ),
.S_AXI_HP0_WRISSUECAP1_EN ( S_AXI_HP0_WRISSUECAP1_EN ),
.S_AXI_HP0_WVALID ( S_AXI_HP0_WVALID ),
.S_AXI_HP0_ARBURST ( S_AXI_HP0_ARBURST ),
.S_AXI_HP0_ARLOCK ( S_AXI_HP0_ARLOCK ),
.S_AXI_HP0_ARSIZE ( S_AXI_HP0_ARSIZE ),
.S_AXI_HP0_AWBURST ( S_AXI_HP0_AWBURST ),
.S_AXI_HP0_AWLOCK ( S_AXI_HP0_AWLOCK ),
.S_AXI_HP0_AWSIZE ( S_AXI_HP0_AWSIZE ),
.S_AXI_HP0_ARPROT ( S_AXI_HP0_ARPROT ),
.S_AXI_HP0_AWPROT ( S_AXI_HP0_AWPROT ),
.S_AXI_HP0_ARADDR ( S_AXI_HP0_ARADDR ),
.S_AXI_HP0_AWADDR ( S_AXI_HP0_AWADDR ),
.S_AXI_HP0_ARCACHE ( S_AXI_HP0_ARCACHE ),
.S_AXI_HP0_ARLEN ( S_AXI_HP0_ARLEN ),
.S_AXI_HP0_ARQOS ( S_AXI_HP0_ARQOS ),
.S_AXI_HP0_AWCACHE ( S_AXI_HP0_AWCACHE ),
.S_AXI_HP0_AWLEN ( S_AXI_HP0_AWLEN ),
.S_AXI_HP0_AWQOS ( S_AXI_HP0_AWQOS ),
.S_AXI_HP0_ARID ( S_AXI_HP0_ARID ),
.S_AXI_HP0_AWID ( S_AXI_HP0_AWID ),
.S_AXI_HP0_WID ( S_AXI_HP0_WID ),
.S_AXI_HP0_WDATA ( S_AXI_HP0_WDATA ),
.S_AXI_HP0_WSTRB ( S_AXI_HP0_WSTRB ),
.S_AXI_HP1_ARESETN ( S_AXI_HP1_ARESETN ),
.S_AXI_HP1_ARREADY ( S_AXI_HP1_ARREADY ),
.S_AXI_HP1_AWREADY ( S_AXI_HP1_AWREADY ),
.S_AXI_HP1_BVALID ( S_AXI_HP1_BVALID ),
.S_AXI_HP1_RLAST ( S_AXI_HP1_RLAST ),
.S_AXI_HP1_RVALID ( S_AXI_HP1_RVALID ),
.S_AXI_HP1_WREADY ( S_AXI_HP1_WREADY ),
.S_AXI_HP1_BRESP ( S_AXI_HP1_BRESP ),
.S_AXI_HP1_RRESP ( S_AXI_HP1_RRESP ),
.S_AXI_HP1_BID ( S_AXI_HP1_BID ),
.S_AXI_HP1_RID ( S_AXI_HP1_RID ),
.S_AXI_HP1_RDATA ( S_AXI_HP1_RDATA ),
.S_AXI_HP1_RCOUNT ( S_AXI_HP1_RCOUNT ),
.S_AXI_HP1_WCOUNT ( S_AXI_HP1_WCOUNT ),
.S_AXI_HP1_RACOUNT ( S_AXI_HP1_RACOUNT ),
.S_AXI_HP1_WACOUNT ( S_AXI_HP1_WACOUNT ),
.S_AXI_HP1_ACLK ( S_AXI_HP1_ACLK ),
.S_AXI_HP1_ARVALID ( S_AXI_HP1_ARVALID ),
.S_AXI_HP1_AWVALID ( S_AXI_HP1_AWVALID ),
.S_AXI_HP1_BREADY ( S_AXI_HP1_BREADY ),
.S_AXI_HP1_RDISSUECAP1_EN ( S_AXI_HP1_RDISSUECAP1_EN ),
.S_AXI_HP1_RREADY ( S_AXI_HP1_RREADY ),
.S_AXI_HP1_WLAST ( S_AXI_HP1_WLAST ),
.S_AXI_HP1_WRISSUECAP1_EN ( S_AXI_HP1_WRISSUECAP1_EN ),
.S_AXI_HP1_WVALID ( S_AXI_HP1_WVALID ),
.S_AXI_HP1_ARBURST ( S_AXI_HP1_ARBURST ),
.S_AXI_HP1_ARLOCK ( S_AXI_HP1_ARLOCK ),
.S_AXI_HP1_ARSIZE ( S_AXI_HP1_ARSIZE ),
.S_AXI_HP1_AWBURST ( S_AXI_HP1_AWBURST ),
.S_AXI_HP1_AWLOCK ( S_AXI_HP1_AWLOCK ),
.S_AXI_HP1_AWSIZE ( S_AXI_HP1_AWSIZE ),
.S_AXI_HP1_ARPROT ( S_AXI_HP1_ARPROT ),
.S_AXI_HP1_AWPROT ( S_AXI_HP1_AWPROT ),
.S_AXI_HP1_ARADDR ( S_AXI_HP1_ARADDR ),
.S_AXI_HP1_AWADDR ( S_AXI_HP1_AWADDR ),
.S_AXI_HP1_ARCACHE ( S_AXI_HP1_ARCACHE ),
.S_AXI_HP1_ARLEN ( S_AXI_HP1_ARLEN ),
.S_AXI_HP1_ARQOS ( S_AXI_HP1_ARQOS ),
.S_AXI_HP1_AWCACHE ( S_AXI_HP1_AWCACHE ),
.S_AXI_HP1_AWLEN ( S_AXI_HP1_AWLEN ),
.S_AXI_HP1_AWQOS ( S_AXI_HP1_AWQOS ),
.S_AXI_HP1_ARID ( S_AXI_HP1_ARID ),
.S_AXI_HP1_AWID ( S_AXI_HP1_AWID ),
.S_AXI_HP1_WID ( S_AXI_HP1_WID ),
.S_AXI_HP1_WDATA ( S_AXI_HP1_WDATA ),
.S_AXI_HP1_WSTRB ( S_AXI_HP1_WSTRB ),
.S_AXI_HP2_ARESETN ( S_AXI_HP2_ARESETN ),
.S_AXI_HP2_ARREADY ( S_AXI_HP2_ARREADY ),
.S_AXI_HP2_AWREADY ( S_AXI_HP2_AWREADY ),
.S_AXI_HP2_BVALID ( S_AXI_HP2_BVALID ),
.S_AXI_HP2_RLAST ( S_AXI_HP2_RLAST ),
.S_AXI_HP2_RVALID ( S_AXI_HP2_RVALID ),
.S_AXI_HP2_WREADY ( S_AXI_HP2_WREADY ),
.S_AXI_HP2_BRESP ( S_AXI_HP2_BRESP ),
.S_AXI_HP2_RRESP ( S_AXI_HP2_RRESP ),
.S_AXI_HP2_BID ( S_AXI_HP2_BID ),
.S_AXI_HP2_RID ( S_AXI_HP2_RID ),
.S_AXI_HP2_RDATA ( S_AXI_HP2_RDATA ),
.S_AXI_HP2_RCOUNT ( S_AXI_HP2_RCOUNT ),
.S_AXI_HP2_WCOUNT ( S_AXI_HP2_WCOUNT ),
.S_AXI_HP2_RACOUNT ( S_AXI_HP2_RACOUNT ),
.S_AXI_HP2_WACOUNT ( S_AXI_HP2_WACOUNT ),
.S_AXI_HP2_ACLK ( S_AXI_HP2_ACLK ),
.S_AXI_HP2_ARVALID ( S_AXI_HP2_ARVALID ),
.S_AXI_HP2_AWVALID ( S_AXI_HP2_AWVALID ),
.S_AXI_HP2_BREADY ( S_AXI_HP2_BREADY ),
.S_AXI_HP2_RDISSUECAP1_EN ( S_AXI_HP2_RDISSUECAP1_EN ),
.S_AXI_HP2_RREADY ( S_AXI_HP2_RREADY ),
.S_AXI_HP2_WLAST ( S_AXI_HP2_WLAST ),
.S_AXI_HP2_WRISSUECAP1_EN ( S_AXI_HP2_WRISSUECAP1_EN ),
.S_AXI_HP2_WVALID ( S_AXI_HP2_WVALID ),
.S_AXI_HP2_ARBURST ( S_AXI_HP2_ARBURST ),
.S_AXI_HP2_ARLOCK ( S_AXI_HP2_ARLOCK ),
.S_AXI_HP2_ARSIZE ( S_AXI_HP2_ARSIZE ),
.S_AXI_HP2_AWBURST ( S_AXI_HP2_AWBURST ),
.S_AXI_HP2_AWLOCK ( S_AXI_HP2_AWLOCK ),
.S_AXI_HP2_AWSIZE ( S_AXI_HP2_AWSIZE ),
.S_AXI_HP2_ARPROT ( S_AXI_HP2_ARPROT ),
.S_AXI_HP2_AWPROT ( S_AXI_HP2_AWPROT ),
.S_AXI_HP2_ARADDR ( S_AXI_HP2_ARADDR ),
.S_AXI_HP2_AWADDR ( S_AXI_HP2_AWADDR ),
.S_AXI_HP2_ARCACHE ( S_AXI_HP2_ARCACHE ),
.S_AXI_HP2_ARLEN ( S_AXI_HP2_ARLEN ),
.S_AXI_HP2_ARQOS ( S_AXI_HP2_ARQOS ),
.S_AXI_HP2_AWCACHE ( S_AXI_HP2_AWCACHE ),
.S_AXI_HP2_AWLEN ( S_AXI_HP2_AWLEN ),
.S_AXI_HP2_AWQOS ( S_AXI_HP2_AWQOS ),
.S_AXI_HP2_ARID ( S_AXI_HP2_ARID ),
.S_AXI_HP2_AWID ( S_AXI_HP2_AWID ),
.S_AXI_HP2_WID ( S_AXI_HP2_WID ),
.S_AXI_HP2_WDATA ( S_AXI_HP2_WDATA ),
.S_AXI_HP2_WSTRB ( S_AXI_HP2_WSTRB ),
.S_AXI_HP3_ARESETN ( S_AXI_HP3_ARESETN ),
.S_AXI_HP3_ARREADY ( S_AXI_HP3_ARREADY ),
.S_AXI_HP3_AWREADY ( S_AXI_HP3_AWREADY ),
.S_AXI_HP3_BVALID ( S_AXI_HP3_BVALID ),
.S_AXI_HP3_RLAST ( S_AXI_HP3_RLAST ),
.S_AXI_HP3_RVALID ( S_AXI_HP3_RVALID ),
.S_AXI_HP3_WREADY ( S_AXI_HP3_WREADY ),
.S_AXI_HP3_BRESP ( S_AXI_HP3_BRESP ),
.S_AXI_HP3_RRESP ( S_AXI_HP3_RRESP ),
.S_AXI_HP3_BID ( S_AXI_HP3_BID ),
.S_AXI_HP3_RID ( S_AXI_HP3_RID ),
.S_AXI_HP3_RDATA ( S_AXI_HP3_RDATA ),
.S_AXI_HP3_RCOUNT ( S_AXI_HP3_RCOUNT ),
.S_AXI_HP3_WCOUNT ( S_AXI_HP3_WCOUNT ),
.S_AXI_HP3_RACOUNT ( S_AXI_HP3_RACOUNT ),
.S_AXI_HP3_WACOUNT ( S_AXI_HP3_WACOUNT ),
.S_AXI_HP3_ACLK ( S_AXI_HP3_ACLK ),
.S_AXI_HP3_ARVALID ( S_AXI_HP3_ARVALID ),
.S_AXI_HP3_AWVALID ( S_AXI_HP3_AWVALID ),
.S_AXI_HP3_BREADY ( S_AXI_HP3_BREADY ),
.S_AXI_HP3_RDISSUECAP1_EN ( S_AXI_HP3_RDISSUECAP1_EN ),
.S_AXI_HP3_RREADY ( S_AXI_HP3_RREADY ),
.S_AXI_HP3_WLAST ( S_AXI_HP3_WLAST ),
.S_AXI_HP3_WRISSUECAP1_EN ( S_AXI_HP3_WRISSUECAP1_EN ),
.S_AXI_HP3_WVALID ( S_AXI_HP3_WVALID ),
.S_AXI_HP3_ARBURST ( S_AXI_HP3_ARBURST ),
.S_AXI_HP3_ARLOCK ( S_AXI_HP3_ARLOCK ),
.S_AXI_HP3_ARSIZE ( S_AXI_HP3_ARSIZE ),
.S_AXI_HP3_AWBURST ( S_AXI_HP3_AWBURST ),
.S_AXI_HP3_AWLOCK ( S_AXI_HP3_AWLOCK ),
.S_AXI_HP3_AWSIZE ( S_AXI_HP3_AWSIZE ),
.S_AXI_HP3_ARPROT ( S_AXI_HP3_ARPROT ),
.S_AXI_HP3_AWPROT ( S_AXI_HP3_AWPROT ),
.S_AXI_HP3_ARADDR ( S_AXI_HP3_ARADDR ),
.S_AXI_HP3_AWADDR ( S_AXI_HP3_AWADDR ),
.S_AXI_HP3_ARCACHE ( S_AXI_HP3_ARCACHE ),
.S_AXI_HP3_ARLEN ( S_AXI_HP3_ARLEN ),
.S_AXI_HP3_ARQOS ( S_AXI_HP3_ARQOS ),
.S_AXI_HP3_AWCACHE ( S_AXI_HP3_AWCACHE ),
.S_AXI_HP3_AWLEN ( S_AXI_HP3_AWLEN ),
.S_AXI_HP3_AWQOS ( S_AXI_HP3_AWQOS ),
.S_AXI_HP3_ARID ( S_AXI_HP3_ARID ),
.S_AXI_HP3_AWID ( S_AXI_HP3_AWID ),
.S_AXI_HP3_WID ( S_AXI_HP3_WID ),
.S_AXI_HP3_WDATA ( S_AXI_HP3_WDATA ),
.S_AXI_HP3_WSTRB ( S_AXI_HP3_WSTRB ),
.DMA0_DATYPE ( DMA0_DATYPE ),
.DMA0_DAVALID ( DMA0_DAVALID ),
.DMA0_DRREADY ( DMA0_DRREADY ),
.DMA0_RSTN ( DMA0_RSTN ),
.DMA0_ACLK ( DMA0_ACLK ),
.DMA0_DAREADY ( DMA0_DAREADY ),
.DMA0_DRLAST ( DMA0_DRLAST ),
.DMA0_DRVALID ( DMA0_DRVALID ),
.DMA0_DRTYPE ( DMA0_DRTYPE ),
.DMA1_DATYPE ( DMA1_DATYPE ),
.DMA1_DAVALID ( DMA1_DAVALID ),
.DMA1_DRREADY ( DMA1_DRREADY ),
.DMA1_RSTN ( DMA1_RSTN ),
.DMA1_ACLK ( DMA1_ACLK ),
.DMA1_DAREADY ( DMA1_DAREADY ),
.DMA1_DRLAST ( DMA1_DRLAST ),
.DMA1_DRVALID ( DMA1_DRVALID ),
.DMA1_DRTYPE ( DMA1_DRTYPE ),
.DMA2_DATYPE ( DMA2_DATYPE ),
.DMA2_DAVALID ( DMA2_DAVALID ),
.DMA2_DRREADY ( DMA2_DRREADY ),
.DMA2_RSTN ( DMA2_RSTN ),
.DMA2_ACLK ( DMA2_ACLK ),
.DMA2_DAREADY ( DMA2_DAREADY ),
.DMA2_DRLAST ( DMA2_DRLAST ),
.DMA2_DRVALID ( DMA2_DRVALID ),
.DMA3_DRVALID ( DMA3_DRVALID ),
.DMA3_DATYPE ( DMA3_DATYPE ),
.DMA3_DAVALID ( DMA3_DAVALID ),
.DMA3_DRREADY ( DMA3_DRREADY ),
.DMA3_RSTN ( DMA3_RSTN ),
.DMA3_ACLK ( DMA3_ACLK ),
.DMA3_DAREADY ( DMA3_DAREADY ),
.DMA3_DRLAST ( DMA3_DRLAST ),
.DMA2_DRTYPE ( DMA2_DRTYPE ),
.DMA3_DRTYPE ( DMA3_DRTYPE ),
.FTMD_TRACEIN_DATA ( FTMD_TRACEIN_DATA ),
.FTMD_TRACEIN_VALID ( FTMD_TRACEIN_VALID ),
.FTMD_TRACEIN_CLK ( FTMD_TRACEIN_CLK ),
.FTMD_TRACEIN_ATID ( FTMD_TRACEIN_ATID ),
.FTMT_F2P_TRIG ( FTMT_F2P_TRIG ),
.FTMT_F2P_TRIGACK ( FTMT_F2P_TRIGACK ),
.FTMT_F2P_DEBUG ( FTMT_F2P_DEBUG ),
.FTMT_P2F_TRIGACK ( FTMT_P2F_TRIGACK ),
.FTMT_P2F_TRIG ( FTMT_P2F_TRIG ),
.FTMT_P2F_DEBUG ( FTMT_P2F_DEBUG ),
.FCLK_CLK3 ( FCLK_CLK3 ),
.FCLK_CLK2 ( FCLK_CLK2 ),
.FCLK_CLK1 ( FCLK_CLK1 ),
.FCLK_CLK0 ( FCLK_CLK0 ),
.FCLK_CLKTRIG3_N ( FCLK_CLKTRIG3_N ),
.FCLK_CLKTRIG2_N ( FCLK_CLKTRIG2_N ),
.FCLK_CLKTRIG1_N ( FCLK_CLKTRIG1_N ),
.FCLK_CLKTRIG0_N ( FCLK_CLKTRIG0_N ),
.FCLK_RESET3_N ( FCLK_RESET3_N ),
.FCLK_RESET2_N ( FCLK_RESET2_N ),
.FCLK_RESET1_N ( FCLK_RESET1_N ),
.FCLK_RESET0_N ( FCLK_RESET0_N ),
.FPGA_IDLE_N ( FPGA_IDLE_N ),
.DDR_ARB ( DDR_ARB ),
.IRQ_F2P ( IRQ_F2P ),
.Core0_nFIQ ( Core0_nFIQ ),
.Core0_nIRQ ( Core0_nIRQ ),
.Core1_nFIQ ( Core1_nFIQ ),
.Core1_nIRQ ( Core1_nIRQ ),
.EVENT_EVENTO ( EVENT_EVENTO ),
.EVENT_STANDBYWFE ( EVENT_STANDBYWFE ),
.EVENT_STANDBYWFI ( EVENT_STANDBYWFI ),
.EVENT_EVENTI ( EVENT_EVENTI ),
.MIO ( MIO ),
.DDR_Clk ( DDR_Clk ),
.DDR_Clk_n ( DDR_Clk_n ),
.DDR_CKE ( DDR_CKE ),
.DDR_CS_n ( DDR_CS_n ),
.DDR_RAS_n ( DDR_RAS_n ),
.DDR_CAS_n ( DDR_CAS_n ),
.DDR_WEB ( DDR_WEB ),
.DDR_BankAddr ( DDR_BankAddr ),
.DDR_Addr ( DDR_Addr ),
.DDR_ODT ( DDR_ODT ),
.DDR_DRSTB ( DDR_DRSTB ),
.DDR_DQ ( DDR_DQ ),
.DDR_DM ( DDR_DM ),
.DDR_DQS ( DDR_DQS ),
.DDR_DQS_n ( DDR_DQS_n ),
.DDR_VRN ( DDR_VRN ),
.DDR_VRP ( DDR_VRP ),
.PS_SRSTB ( PS_SRSTB ),
.PS_CLK ( PS_CLK ),
.PS_PORB ( PS_PORB ),
.IRQ_P2F_DMAC_ABORT ( IRQ_P2F_DMAC_ABORT ),
.IRQ_P2F_DMAC0 ( IRQ_P2F_DMAC0 ),
.IRQ_P2F_DMAC1 ( IRQ_P2F_DMAC1 ),
.IRQ_P2F_DMAC2 ( IRQ_P2F_DMAC2 ),
.IRQ_P2F_DMAC3 ( IRQ_P2F_DMAC3 ),
.IRQ_P2F_DMAC4 ( IRQ_P2F_DMAC4 ),
.IRQ_P2F_DMAC5 ( IRQ_P2F_DMAC5 ),
.IRQ_P2F_DMAC6 ( IRQ_P2F_DMAC6 ),
.IRQ_P2F_DMAC7 ( IRQ_P2F_DMAC7 ),
.IRQ_P2F_SMC ( IRQ_P2F_SMC ),
.IRQ_P2F_QSPI ( IRQ_P2F_QSPI ),
.IRQ_P2F_CTI ( IRQ_P2F_CTI ),
.IRQ_P2F_GPIO ( IRQ_P2F_GPIO ),
.IRQ_P2F_USB0 ( IRQ_P2F_USB0 ),
.IRQ_P2F_ENET0 ( IRQ_P2F_ENET0 ),
.IRQ_P2F_ENET_WAKE0 ( IRQ_P2F_ENET_WAKE0 ),
.IRQ_P2F_SDIO0 ( IRQ_P2F_SDIO0 ),
.IRQ_P2F_I2C0 ( IRQ_P2F_I2C0 ),
.IRQ_P2F_SPI0 ( IRQ_P2F_SPI0 ),
.IRQ_P2F_UART0 ( IRQ_P2F_UART0 ),
.IRQ_P2F_CAN0 ( IRQ_P2F_CAN0 ),
.IRQ_P2F_USB1 ( IRQ_P2F_USB1 ),
.IRQ_P2F_ENET1 ( IRQ_P2F_ENET1 ),
.IRQ_P2F_ENET_WAKE1 ( IRQ_P2F_ENET_WAKE1 ),
.IRQ_P2F_SDIO1 ( IRQ_P2F_SDIO1 ),
.IRQ_P2F_I2C1 ( IRQ_P2F_I2C1 ),
.IRQ_P2F_SPI1 ( IRQ_P2F_SPI1 ),
.IRQ_P2F_UART1 ( IRQ_P2F_UART1 ),
.IRQ_P2F_CAN1 ( IRQ_P2F_CAN1 )
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_108x128.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_108x128 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [107:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [107:0] q;
output [6:0] usedw;
wire [6:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [107:0] sub_wire3;
wire [6:0] usedw = sub_wire0[6:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [107:0] q = sub_wire3[107:0];
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 108,
scfifo_component.lpm_widthu = 7,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "108"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "108"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "108"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 108 0 INPUT NODEFVAL "data[107..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 108 0 OUTPUT NODEFVAL "q[107..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL "usedw[6..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 108 0 data 0 0 108 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 108 0 @q 0 0 108 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_108x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_108x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_108x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_108x128.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_108x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_108x128_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Module: altera_tse_xcvr_resync
//
// Description:
// A general purpose resynchronization module.
//
// Parameters:
// SYNC_CHAIN_LENGTH
// - Specifies the length of the synchronizer chain for metastability
// retiming.
// WIDTH
// - Specifies the number of bits you want to synchronize. Controls the width of the
// d and q ports.
// SLOW_CLOCK - USE WITH CAUTION.
// - Leaving this setting at its default will create a standard resynch circuit that
// merely passes the input data through a chain of flip-flops. This setting assumes
// that the input data has a pulse width longer than one clock cycle sufficient to
// satisfy setup and hold requirements on at least one clock edge.
// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
// circuit that will capture the input data regardless of the pulse width and
// its relationship to the clock. However it is more difficult to apply static
// timing constraints as it ties the data input to the clock input of the flop.
// This implementation assumes the data rate is slow enough
//
`timescale 1ns/1ns
module altera_tse_xcvr_resync #(
parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
parameter WIDTH = 1, // Number of bits to resync
parameter SLOW_CLOCK = 0 // See description above
) (
input wire clk,
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q
);
localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
genvar ig;
// Generate a synchronizer chain for each bit
generate begin
for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
wire d_in; // Input to sychronization chain.
reg [INT_LEN-1:0] r = {INT_LEN{1'b0}};
wire [INT_LEN :0] next_r; // One larger real chain
assign q[ig] = r[INT_LEN-1]; // Output signal
assign next_r = {r,d_in};
always @(posedge clk)
r <= next_r[INT_LEN-1:0];
// Generate asynchronous capture circuit if specified.
if(SLOW_CLOCK == 0) begin
assign d_in = d[ig];
end else begin
wire d_clk;
reg d_r;
wire clr_n;
assign d_clk = d[ig];
assign d_in = d_r;
assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
// Asynchronously latch the input signal.
always @(posedge d_clk or negedge clr_n)
if(!clr_n) d_r <= 1'b0;
else if(d_clk) d_r <= 1'b1;
end // SLOW_CLOCK
end // for loop
end // generate
endgenerate
endmodule
|
`ifndef _REGFILE
`define _REGFILE
module register_file(clk, out1, out2, readAdd1, readAdd2, write, writeAdd, in, reset);
output [15:0] out1, out2;
input [15:0] in;
input [2:0] readAdd1, readAdd2, writeAdd;
input write, clk, reset;
wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
wire [7:0] writeLinesInit, writeLines;
demux8 dem(writeAdd, writeLinesInit);
mux16x8 mux1(data0, data1, data2, data3, data4, data5, data6, data7, readAdd1, out1);
mux16x8 mux2(data0, data1, data2, data3, data4, data5, data6, data7, readAdd2, out2);
or a0(writeLines[0], write, ~writeLinesInit[0]);
or a1(writeLines[1], write, ~writeLinesInit[1]);
or a2(writeLines[2], write, ~writeLinesInit[2]);
or a3(writeLines[3], write, ~writeLinesInit[3]);
or a4(writeLines[4], write, ~writeLinesInit[4]);
or a5(writeLines[5], write, ~writeLinesInit[5]);
or a6(writeLines[6], write, ~writeLinesInit[6]);
or a7(writeLines[7], write, ~writeLinesInit[7]);
register16 r0(clk, data0, in, writeLines[0], reset);
register16 r1(clk, data1, in, writeLines[1], reset);
register16 r2(clk, data2, in, writeLines[2], reset);
register16 r3(clk, data3, in, writeLines[3], reset);
register16 r4(clk, data4, in, writeLines[4], reset);
register16 r5(clk, data5, in, writeLines[5], reset);
register16 r6(clk, data6, in, writeLines[6], reset);
register16 r7(clk, data7, in, writeLines[7], reset);
endmodule
`endif
|
(** * ImpCEvalFun: Evaluation Function for Imp *)
(* $Date: 2013-07-01 18:48:47 -0400 (Mon, 01 Jul 2013) $ *)
(* #################################### *)
(** ** Evaluation Function *)
Require Import Imp.
(** Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_step1 st (c1;; WHILE b1 DO c1 END)
else st
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the changed
[ceval_step1] function applied to the [loop] program from [Imp.v] would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_step1] cannot be written in Coq -- at least not
without one additional trick... *)
(** Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(** _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
Module ifTest.
Inductive ab : Set :=
a : ab
| b : ab.
Check if (a) then 0 else 1.
Eval compute in if (a) then 0 else 1.
Eval compute in if (b) then 0 else 1.
(* Check if (b) then 0 else a. *)
(* QQQQQQQQQQQQQQQQQQQQ type check error, why? *)
Inductive abc : Set :=
a_ : abc
| b_ : abc
| c_ : abc.
(* Eval compute in if (a_) then 0 else 1. *)
(* Toplevel input, characters 16-37: *)
(* > Eval compute in if (a_) then 0 else 1. *)
(* > ^^^^^^^^^^^^^^^^^^^^^ *)
(* Error: If is only for inductive types with two constructors. *)
End ifTest.
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(** We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
Eval compute in
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
(* Eval compute in
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4) *)
(** **** Exercise: 2 stars (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
Definition pup_to_n : com :=
(* Z ::= ANum 1;; *)
(* WHILE BLe (AId Z) (AId X) *)
(* DO *)
(* Y ::= APlus (AId Z) (AId Y);; *)
(* Z ::= APlus (AId Z) (ANum 1) *)
(* END ;; *)
(* X ::= ANum 0;; *)
(* Z ::= ANum 0 *)
WHILE BNot (BEq (AId X) (ANum 0))
DO
Y ::= APlus (AId X) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
.
Eval compute in test_ceval (update empty_state X 5) pup_to_n.
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (peven) *)
(** Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
Definition peven_fail : com :=
WHILE (BLe (ANum 0) (AId X)) DO
X ::= AMinus (AId X) (ANum 2)
END ;;
IFB (BEq (ANum 0) (AId X))
THEN Z ::= (ANum 0)
ELSE Z ::= (ANum 1)
FI
.
(* X cannot go lower than 0 !!! inf loop -> None ! *)
Definition peven : com :=
WHILE (BAnd (BNot (BEq (ANum 0) (AId X))) (BNot (BEq (ANum 1) (AId X)))) DO
X ::= AMinus (AId X) (ANum 2)
END ;;
IFB (BEq (ANum 0) (AId X))
THEN Z ::= (ANum 0)
ELSE Z ::= (ANum 1)
FI
.
(** [] *)
Check ex_intro.
Print ex.
(* Theorem tmpp : 1 + 1 = 2. *)
(* Definition tmp := test_ceval (update empty_state X 77) peven. *)
(* Definition tmp_ := test_ceval (update empty_state X 77) peven = Some (0, 0, 1). *)
(* Definition tmp__ : test_ceval (update empty_state X 77) peven = Some (0, 0, 1). *)
(* QQQQQQQQQQQQQQQQQQQQ *)
(* Compute just few steps? *)
(* normalize, normalize1 tactic in SF final exam 08? *)
(* cannot find tactic and cannot use it here *)
(* also, in 08 file, normalize tactic can be used inside theorem proof but not in the form of "eval compute in blah *)
Eval compute in test_ceval (update empty_state X 77) peven.
Lemma peven_test1 :
exists x, test_ceval (update empty_state X 77) peven = Some (x, 0, 1).
Proof. exists 1. reflexivity. Qed.
(* ################################################################ *)
(** ** Equivalence of Relational and Step-Indexed Evaluation *)
(** As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
Lemma some_implies_non_zero : forall i c st st2, ceval_step st c i = Some st2 -> i <> O.
Proof.
intros. destruct i. inversion H. auto.
Qed.
Lemma lem : forall i c st st2, ceval_step st c i = Some st2 -> ceval_step st c (S i) = Some st2.
intros i c.
generalize dependent i.
induction c; intros; auto; assert(G := H); apply some_implies_non_zero in G.
- destruct i.
destruct G; auto.
simpl in H; auto.
- destruct i0.
destruct G; auto.
simpl in H; auto.
- destruct i.
destruct G; auto.
simpl in H; auto. destruct (ceval_step st c1 i) eqn:T.
apply IHc1 in T.
apply IHc2 in H.
rewrite <- H.
remember (S i) as j.
simpl. rewrite T. auto.
inversion H.
- destruct i.
destruct G; auto.
simpl in H; auto.
remember (S i) as j.
simpl.
destruct (beval st b) eqn:T.
apply IHc1 in H. rewrite <- H. auto.
apply IHc2 in H. rewrite <- H. auto.
-
generalize dependent st2.
generalize dependent st.
generalize dependent c.
generalize dependent b.
induction i.
destruct G; auto. clear G.
(* destruct i. *)
(* destruct G; auto. clear G. *)
(* ---------------------------------------------------- *)
intros.
(* Heqx : ceval_step st c i = Some s *)
(* H : ceval_step s (WHILE b DO c END) i = Some st2 *)
(* H0 : beval st b = true *)
(* TT : ceval_step st c (S i) = Some s *)
(* ============================ *)
(* ceval_step s (WHILE b DO c END) (S i) = ceval_step s (WHILE b DO c END) i *)
(* ---------------------------------------------------------- *)
remember (S i) as j.
destruct (beval st b) eqn:H0.
(* assert(beval st b = true) by admit. *)
simpl. rewrite H0.
rewrite Heqj in H. simpl in H. rewrite H0 in H.
remember (ceval_step st c i) as x.
destruct x.
symmetry in Heqx.
assert(TT:=Heqx).
apply IHc in TT.
rewrite <- Heqj in TT.
rewrite TT.
(* rewrite <- H. *)
subst.
apply IHi.
apply some_implies_non_zero in Heqx. auto.
intros; auto. apply H.
inversion H.
(* ----------------------------------------------------- *)
simpl. rewrite H0. subst. simpl in H. rewrite H0 in H. auto.
Qed.
(* inversion H. *)
(* remember (S i) as j. simpl. destruct (beval st b) eqn:T. *)
(* remember (ceval_step st c i) as x. *)
(* symmetry in Heqx. *)
(* assert(K := Heqx). *)
(* destruct x. *)
(* apply IHc in K. *)
(* rewrite <- Heqj in K. *)
(* rewrite K. rewrite <- H. *)
(* assert(L := K). *)
(* apply IHc in L. *)
(* rewrite <- K in L. *)
(* subst. simpl. *)
(* rewrite T. *)
(* rewrite Heqx. *)
(* destruct (beval s b) eqn:TT. *)
(* simpl in H; auto. *)
(* rewrite <- H. *)
(* destruct (beval st b) eqn:T. *)
(* * destruct i. simpl in H. inversion H. *)
(* remember (ceval_step st c (S i)) as M. *)
(* destruct M. *)
(* simpl in H. destruct (beval s b); auto. *)
(* symmetry in HeqM. apply IHc in HeqM. apply IHc in HeqM. *)
(* * simpl; rewrite T; subst; auto. *)
(* * destruct (ceval_step st c i) eqn:T2. *)
(* simpl. rewrite T. *)
(* Lemma lem_ : forall i c st st2, ceval_step st c i = Some st2 -> ceval_step st c (S i) = Some st2. *)
(* induction i. *)
(* intros. inversion H. *)
(* intros. *)
(* remember (ceval_step st c i) as v. *)
(* destruct v. *)
(* * *)
(* symmetry in Heqv. *)
(* assert(Heqv2 := Heqv). *)
(* apply IHi in Heqv. *)
(* rewrite H in Heqv. *)
(* inversion Heqv. subst. clear Heqv. *)
(* assert(H2 := H). *)
(* rename H into js. *)
(* rename Heqv2 into is. *)
(* simpl in js. *)
(* remember (S i) as j. *)
(* simpl. *)
(* rewrite <- js. *)
(* rewrite <- is in H2. *)
(* destruct c; try rewrite <- H2; auto. *)
(* - admit. *)
(* (* destruct (ceval_step st c1 i) eqn:iT. destruct (ceval_step st c1 j) eqn:jT. *) *)
(* (* subst. *) *)
(* (* rewrite js. *) *)
(* (* rewrite <- is. *) *)
(* - assert(G: i <> 0). apply some_implies_non_zero in is. auto. *)
(* destruct i. destruct G; auto. *)
(* clear G. *)
(* destruct (beval st b) eqn:T; auto. *)
(* simpl in is. rewrite T in is. *)
(* simpl in H2. rewrite T in H2. *)
(* reflexivity. *)
(* rewrite H2. *)
(* Lemma lem2 : forall i c st st2, ceval_step st c i = Some st2 -> ceval_step st c (S i) = Some st2 -> ceval_step st c (S (S i)) = Some st2. *)
(* Lemma lem3 : forall i c st, ceval_step st c i = ceval_step st c (S i) -> ceval_step st c (S i) = ceval_step st c (S (S i)). *)
Theorem ceval_step__ceval1: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros.
destruct H.
generalize dependent st'.
generalize dependent st. (* third case ! st -> st', st -> st' *)
generalize dependent c.
induction x; intros; simpl.
- inversion H.
- simpl in H.
induction c. (* try (inversion H; constructor; auto). *)
+ inversion H; constructor.
+ inversion H.
constructor. auto.
+ remember (ceval_step st c1 x) as a.
symmetry in Heqa.
destruct a.
* apply IHx in Heqa.
eapply E_Seq. apply Heqa. apply IHx in H. apply H.
* inversion H.
+ destruct (beval st b) eqn:T.
* constructor; auto.
* apply E_IfFalse; auto.
+
remember (ceval_step st c x) as a.
destruct (beval st b) eqn:T.
{
destruct a.
* eapply E_WhileLoop; auto.
symmetry in Heqa.
assert(G:=Heqa).
apply IHx in G.
apply G.
apply IHx in H.
apply H.
* inversion H.
}
{
inversion H; subst; clear H.
apply E_WhileEnd; auto.
}
Qed.
Theorem ceval_step__ceval2: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros.
destruct H.
generalize dependent st'.
generalize dependent st. (* third case ! st -> st', st -> st' *)
generalize dependent x.
induction c; intros; simpl.
-
destruct x; simpl in H; inversion H.
constructor.
-
destruct x; simpl in H; inversion H.
constructor; auto.
-
destruct x; simpl in H; inversion H.
remember (ceval_step st c1 x) as t.
destruct t.
(* QQQQQQQQQQQQQQQQQQQQQQ inversion here does not work! *)
apply E_Seq with (st':=s).
eapply IHc1; eauto.
eapply IHc2; eauto.
inversion H.
-
destruct x; simpl in H; inversion H.
destruct (beval st b) eqn:T.
apply E_IfTrue; auto. eapply IHc1; eauto.
apply E_IfFalse; auto. eapply IHc2. eauto.
-
(* destruct x; simpl in H; inversion H. *)
(* destruct (beval st b) eqn:T. *)
(* Abort All. *)
(* generalize dependent st. *)
(* generalize dependent st'. *)
(* generalize dependent x. *)
(* induction (WHILE b DO c END). admit. admit. admit. admit. *)
(* intros. *)
(* destruct (beval st b0) eqn:T. *)
(* eapply E_WhileLoop; auto. *)
(* Abort All. *)
(* generalize dependent st. *)
(* generalize dependent st'. *)
(* generalize dependent b. *)
(* generalize dependent c. *)
(* induction x; intros. + simpl in H; inversion H. *)
(* + apply IHx. *)
(* * intros. simpl in H. *)
(* apply lem in H0. *)
(* apply IHc in H0. auto. *)
(* * rewrite <- H. simpl. *)
(* destruct (beval st b) eqn:Tb. *)
(* simpl in H. rewrite Tb in H. *)
(* remember (ceval_step st c x) as m. *)
(* destruct m. symmetry in Heqm. *)
(* destruct (ceval_step st c x) eqn:Tc. *)
(* ceval_step = *)
(* fix ceval_step (st : state) (c : com) (i : nat) {struct i} : *)
(* option state := *)
(* match i with *)
(* | 0 => None *)
(* | S i' => *)
(* match c with *)
(* | SKIP => Some st *)
(* | l ::= a1 => Some (update st l (aeval st a1)) *)
(* | c1;; c2 => LETOPT st' <== ceval_step st c1 i' IN ceval_step st' c2 i' *)
(* | IFB b THEN c1 ELSE c2 FI => *)
(* if beval st b then ceval_step st c1 i' else ceval_step st c2 i' *)
(* | WHILE b1 DO c1 END => *)
(* if beval st b1 *)
(* then LETOPT st' <== ceval_step st c1 i' IN ceval_step st' c i' *)
(* else Some st *)
(* end *)
(* end *)
(* : state -> com -> nat -> option state *)
(* | WHILE b1 DO c1 END => *)
(* then LETOPT st' <== ceval_step st c1 i' IN ceval_step st' c i' *)
remember (ceval_step st c x).
symmetry in Heqo.
destruct o eqn:To; subst.
{
destruct (beval st b) eqn:T.
*
(* eapply E_WhileLoop; auto. *)
(* apply lem in H. *)
(* simpl in H. *)
(* rewrite T in H. *)
(* eapply IHc. *)
(* rewrite Heqo in H. *)
(* apply Heqo. *)
Admitted.
(* symmetry. *)
(* apply Heqo. *)
(* induction x. *)
(* * inversion H. *)
(* * *)
(* apply IHx. *)
(* Lemma wrong: exists *)
(* (b: bexp) *)
(* (c: com) *)
(* (IHc: forall(x:nat)(st st':state), ceval_step st c x = Some st' -> c / st || st') *)
(* (x: nat) *)
(* (st: state) *)
(* (st': state) *)
(* (H: ceval_step st (WHILE b DO c END) (S x) = Some st') *)
(* (IHx: ceval_step st (WHILE b DO c END) x = Some st' -> (WHILE b DO c END) / st || st'), *)
(* ~(ceval_step st (WHILE b DO c END) x = Some st'). *)
(* Proof. *)
(* exists BFalse. *)
(* exists SKIP. *)
(* eexists. intros. { destruct x. inversion H. simpl in H. inversion H; subst. constructor. } *)
(* exists 0. *)
(* exists empty_state. *)
(* exists empty_state. *)
(* eexists. simpl. auto. *)
(* exists. simpl. intros. inversion H. *)
(* unfold not. *)
(* intros. *)
(* simpl in H. *)
(* inversion H. *)
(* Qed. *)
(* clear IHx. *)
(* destruct (ceval_step st (WHILE b DO c END) x) eqn:T. *)
(* { *)
(* apply lem in T. *)
(* rewrite H in T. *)
(* auto. *)
(* } *)
(* { *)
(* destruct x. *)
(* { *)
(* simpl in T. clear T. *)
(* simpl in H. destruct (beval st b) eqn:T; auto. *)
(* } *)
(* { *)
(* simpl in T. *)
(* destruct (beval st b) eqn:TT; auto. *)
(* } *)
(* simpl in H. *)
(* destruct (beval st b) eqn:TT. *)
(* } *)
(* assert(H2 := H). *)
(* simpl in H. destruct (beval st b) eqn:T. *)
(* { *)
(* apply E_WhileLoop with (st':=st'); auto. *)
(* destruct (ceval_step st c x) eqn:TT. *)
(* { *)
(* apply IHc in TT. *)
(* apply IHc; auto. *)
(* eapply IHc; eauto. *)
(* destruct (ceval_step st c x). *)
(* apply IHx. intros. *)
(* simpl in H. rewrite T in *; subst. apply *)
(* apply IHx. *)
(* intros. *)
(* apply E_WhileLoop with (st':=st'); auto. apply IHc. apply lem. *)
(* constructor; auto. *)
(* unfold ceval_step in H. *)
(* simpl in H. *)
(* compute in H. *)
(* QQQQQQQQQQQQQQQQQQQQQQQQ Why Seq i-1, i-1? not i-1, i-2 ? *)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
Case "i = 0 -- contradictory".
intros c st st' H. inversion H.
Case "i = S i'".
intros c st st' H.
com_cases (destruct c) SCase;
simpl in H; inversion H; subst; clear H.
SCase "SKIP". apply E_Skip.
SCase "::=". apply E_Ass. reflexivity.
SCase ";;".
destruct (ceval_step st c1 i') eqn:Heqr1.
SSCase "Evaluation of r1 terminates normally".
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSCase "Otherwise -- contradiction".
inversion H1.
SCase "IFB".
destruct (beval st b) eqn:Heqr.
SSCase "r = true".
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SSCase "r = false".
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SCase "WHILE". destruct (beval st b) eqn :Heqr.
SSCase "r = true".
destruct (ceval_step st c i') eqn:Heqr1.
SSSCase "r1 = Some s".
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSSCase "r1 = None".
inversion H1.
SSCase "r = false".
inversion H1.
apply E_WhileEnd.
rewrite <- Heqr. subst. reflexivity. Qed.
(** **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more1: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
intros.
induction H.
auto.
apply lem in IHle.
apply IHle.
Qed.
(* AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA *)
(* Proving this seems much more easier than proving lem... *)
Theorem ceval_step_more2: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1; intros.
* inversion H0.
*
(***************)(* simpl in H0. *)
(* rewrite <- H0 *)
destruct i2. inversion H.
(*******************)(* simpl. *)
induction c; intros; auto. (* eqn:T. *)
+ simpl in H0.
simpl.
destruct (ceval_step st c1 i1) eqn:T.
- assert(G := T).
apply (IHi1 i2) in G; try omega.
rewrite G.
eapply IHi1; auto; try omega.
- inversion H0.
(* destruct (ceval_step st c2 i1) eqn:T2. *)
(* assert(G:=T2). *)
(* apply IHi1 with (i2:=i2) in G; try omega. *)
(* assert(K: Some(st') = Some(s0)). *)
(* rewrite <- H0. *)
(* rewrite <- T2. *)
(* apply IHi1. omega. *)
(* destruct (ceval_step st c1 i1) eqn:T2. *)
(* inversion H0; subst. auto. *)
+ simpl.
destruct (beval st b) eqn:T; simpl in H0; rewrite T in H0.
- apply IHi1; auto; try omega.
- apply IHi1; auto; try omega.
+ simpl.
destruct (beval st b) eqn:T; simpl in H0; rewrite T in H0.
- destruct (ceval_step st c i1) eqn:T2.
apply (IHi1 i2) in T2; try omega.
rewrite T2.
apply (IHi1 i2) in H0; try omega.
auto.
inversion H0.
- auto.
Qed.
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
Case "i1 = 0".
simpl in Hceval. inversion Hceval.
Case "i1 = S i1'".
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
com_cases (destruct c) SCase.
SCase "SKIP".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase "::=".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase ";;".
simpl in Hceval. simpl.
destruct (ceval_step st c1 i1') eqn:Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "st1'o = None".
inversion Hceval.
SCase "IFB".
simpl in Hceval. simpl.
destruct (beval st b); apply (IHi1' i2') in Hceval; assumption.
SCase "WHILE".
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
destruct (ceval_step st c i1') eqn: Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "i1'o = None".
simpl in Hceval. inversion Hceval. Qed.
(** **** Exercise: 3 stars (ceval__ceval_step) *)
(** Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
(* ceval_cases (induction Hce) Case. *)
induction Hce.
* exists 1. auto.
* exists 1. simpl. rewrite H. auto.
* destruct IHHce1. destruct IHHce2.
exists (1 + x + x0). (******** not x + x0 + 1 ************)
assert(G:= (ceval_step__ceval c1 st st' )).
Check (ex_intro ((fun i => (ceval_step st c1 i = Some st')))).
Check (ex_intro ((fun i => (ceval_step st c1 i = Some st'))) x H).
assert(GG:= (ceval_step__ceval c1 st st' (ex_intro ((fun i => (ceval_step st c1 i = Some st'))) x H))).
(* Check (ex_intro (forall i: nat, (ceval_step st c1 i = Some st'))). *)
(* (fun i => ceval_step st c1 i = Some st') *)
simpl.
eapply ceval_step_more in H. rewrite H.
eapply ceval_step_more in H0.rewrite H0.
auto.
omega. omega.
*
destruct IHHce.
exists (1+x).
simpl.
rewrite H.
auto.
*
destruct IHHce.
exists (1+x).
simpl.
rewrite H.
auto.
*
exists 1. simpl. rewrite H. auto.
*
destruct IHHce1.
destruct IHHce2.
exists (1+x+x0).
simpl.
rewrite H.
eapply ceval_step_more in H0.
rewrite H0.
eapply ceval_step_more in H1.
rewrite H1.
auto.
omega.
omega.
Qed.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(** ** Determinism of Evaluation (Simpler Proof) *)
(** Here's a slicker proof showing that the evaluation relation is
deterministic, using the fact that the relational and step-indexed
definition of evaluation are the same. *)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.68d
// \ \ Application: netgen
// / / Filename: uart_rx_timesim.v
// /___/ /\ Timestamp: Sun Oct 26 02:31:38 2014
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -s 5 -pcf uart_rx.pcf -sdf_anno true -sdf_path netgen/par -insert_glbl true -insert_pp_buffers true -w -dir netgen/par -ofmt verilog -sim uart_rx.ncd uart_rx_timesim.v
// Device : 3s100ecp132-5 (PRODUCTION 1.27 2013-06-08)
// Input file : uart_rx.ncd
// Output file : C:\Users\James\Desktop\iDriveSync\IDrive-Sync\DSD LAB\lab9_uart_rx\netgen\par\uart_rx_timesim.v
// # of Modules : 1
// Design Name : uart_rx
// Xilinx : C:\Xilinx\14.6\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module uart_rx (
clk, rden, wren, reset, rxin, dout, addr, din
);
input clk;
input rden;
input wren;
input reset;
input rxin;
output [8 : 0] dout;
input [2 : 0] addr;
input [7 : 0] din;
wire ld_shift_0;
wire clk_BUFGP;
wire reset_IBUF_963;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ;
wire din_0_IBUF_978;
wire \fifo1/N23_0 ;
wire \fifo1/N9_0 ;
wire in_two_983;
wire \baud1/Madd_timer_addsub0000_cy[3] ;
wire N30;
wire \baud1/baud_cmp_eq0000_0 ;
wire \baud1/baud_cmp_eq0000893_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_995 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_996 ;
wire rd_fifo;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_998 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 ;
wire rxin_IBUF_1000;
wire N26_0;
wire N28_0;
wire bitcounter_not0001_0;
wire N10;
wire finish_0;
wire loaded_mux0000_0;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1019 ;
wire \fifo1/N5_0 ;
wire bittime_0;
wire \baud1/baud_1023 ;
wire full;
wire N20;
wire loaded_1030;
wire load_1032;
wire \pstate_mux0000<2>4_1033 ;
wire \pstate_mux0000<2>10_0 ;
wire \pstate_mux0000<3>15_0 ;
wire \pstate_mux0000<3>2_1036 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_0 ;
wire empty;
wire N14;
wire N16;
wire addr_2_IBUF_1045;
wire wren_IBUF_1047;
wire rden_IBUF_1051;
wire addr_0_IBUF_1064;
wire addr_1_IBUF_1065;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en_0 ;
wire \dout<0>30 ;
wire \dout<1>30 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_1102 ;
wire N41;
wire N47;
wire \baud1/timer_mux0000<0>11_SW5/O ;
wire \fifo1/N17_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000100_SW0_SW0_SW0/O ;
wire \fifo1/N8_0 ;
wire \pstate_mux0000<4>_SW0/O ;
wire \pstate_mux0000<2>18_SW0/O ;
wire \baud1/baud_cmp_eq0000853/O ;
wire \baud1/baud_cmp_eq0000826_0 ;
wire \baud1/baud_cmp_eq00008120_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000079/O ;
wire \fifo1/N7_0 ;
wire \fifo1/N21_0 ;
wire \baud1/Madd_timer_addsub0000_cy<5>_0 ;
wire \baud1/timer_mux0000<4>_SW0/O ;
wire \bitcounter_not00011_SW0/O ;
wire frame_ready_1129;
wire \baud1/timer_mux0000<0>11_SW7/O ;
wire \baud1/timer_mux0000<0>11_SW6/O ;
wire \fifo1/N3 ;
wire wr_baud_0;
wire N22;
wire N24;
wire \dout<2>10_1140 ;
wire \din<4>/INBUF ;
wire \din<2>/INBUF ;
wire \dout<7>/O ;
wire \dout<3>/O ;
wire \wren/INBUF ;
wire \dout<5>/O ;
wire \clk/INBUF ;
wire \dout<0>/O ;
wire \dout<8>/O ;
wire \reset/INBUF ;
wire \din<3>/INBUF ;
wire \rden/INBUF ;
wire \din<5>/INBUF ;
wire \rxin/INBUF ;
wire \dout<4>/O ;
wire \dout<6>/O ;
wire \din<6>/INBUF ;
wire \din<7>/INBUF ;
wire \dout<2>/O ;
wire \dout<1>/O ;
wire \addr<0>/INBUF ;
wire \bitcounter<0>/DXMUX_1802 ;
wire Mcount_bitcounter;
wire bittime;
wire \bitcounter<0>/CLKINV_1785 ;
wire \bitcounter<0>/CEINV_1784 ;
wire \addr<2>/INBUF ;
wire \dout<1>30/F5MUX_2226 ;
wire N78;
wire \dout<1>30/BXINV_2219 ;
wire N77;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DXMUX_2306 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FXMUX_2305 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/F5MUX_2304 ;
wire \fifo1/N26 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/BXINV_2297 ;
wire \fifo1/N25 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV_2289 ;
wire \dout_3_OBUF/F5MUX_2251 ;
wire \dout<3>1_2249 ;
wire \dout_3_OBUF/BXINV_2243 ;
wire \dout<3>2_2241 ;
wire \dout_5_OBUF/F5MUX_2333 ;
wire \dout<5>1_2331 ;
wire \dout_5_OBUF/BXINV_2325 ;
wire \dout<5>2_2323 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB31 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB30 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB29 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB28 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB27 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB26 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB23 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB22 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB21 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB20 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB19 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB18 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB15 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB14 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB13 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB12 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB11 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB10 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB7 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB6 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB5 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB4 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA31 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA30 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA29 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA28 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA27 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA26 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA25 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA24 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA23 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA22 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA21 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA20 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA19 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA18 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA17 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA16 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA15 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA14 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA13 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA12 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA11 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA10 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA9 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA8 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA7 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA6 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA5 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA4 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB31 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB30 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB29 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB28 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB27 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB26 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB25 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB24 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB23 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB22 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB21 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB20 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB19 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB18 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB17 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB16 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB15 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB14 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB13 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB12 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB11 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB10 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB9 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB8 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB7 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB6 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB5 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB4 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB0 ;
wire \baud1/timer<2>/DXMUX_2438 ;
wire \baud1/timer_mux0000<0>11_SW5/O_pack_2 ;
wire \baud1/timer<2>/CLKINV_2422 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_2471 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000100_SW0_SW0_SW0/O_pack_2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_2456 ;
wire \dout_7_OBUF/F5MUX_2176 ;
wire \dout<7>1_2174 ;
wire \dout_7_OBUF/BXINV_2168 ;
wire \dout<7>2_2166 ;
wire \dout_4_OBUF/F5MUX_2276 ;
wire \dout<4>1_2274 ;
wire \dout_4_OBUF/BXINV_2268 ;
wire \dout<4>2_2266 ;
wire \pstate<1>/DXMUX_2503 ;
wire \pstate_mux0000<4>_SW0/O_pack_2 ;
wire \pstate<1>/CLKINV_2486 ;
wire \clk_BUFGP/BUFG/S_INVNOT ;
wire \clk_BUFGP/BUFG/I0_INV ;
wire \dout<0>30/F5MUX_2201 ;
wire N80;
wire \dout<0>30/BXINV_2194 ;
wire N79;
wire \N47/F5MUX_2408 ;
wire \dout<2>41_SW0 ;
wire \N47/BXINV_2401 ;
wire \N47/G ;
wire \dout_6_OBUF/F5MUX_2383 ;
wire \dout<6>1_2381 ;
wire \dout_6_OBUF/BXINV_2375 ;
wire \dout<6>2_2373 ;
wire \N41/F5MUX_2358 ;
wire N46;
wire \N41/BXINV_2351 ;
wire N45;
wire \din<0>/INBUF ;
wire \addr<1>/INBUF ;
wire \din<1>/INBUF ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX_2944 ;
wire \fifo1/Result<3>1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX_2931 ;
wire \fifo1/Result<2>1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_2922 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_2921 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_2920 ;
wire \baud1/Madd_timer_addsub0000_cy[5] ;
wire \baud1/Madd_timer_addsub0000_cy<3>_pack_1 ;
wire \baud1/timer<1>/DXMUX_2872 ;
wire \baud1/timer<1>/DYMUX_2858 ;
wire \baud1/timer<1>/SRINV_2850 ;
wire \baud1/timer<1>/CLKINV_2849 ;
wire \frame_ready/DXMUX_2701 ;
wire \frame_ready/FXMUX_2700 ;
wire finish;
wire \bitcounter_not00011_SW0/O_pack_1 ;
wire \frame_ready/CLKINV_2683 ;
wire \in_two/DYMUX_2904 ;
wire Mshreg_in_two;
wire \in_two/DIG_MUX_2893 ;
wire \in_two/CLKINV_2891 ;
wire \in_two/WSG ;
wire \in_two/SRINV_2887 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX_2620 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX_2619 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000079/O_pack_2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV_2605 ;
wire \pstate<3>/DXMUX_2538 ;
wire \pstate_mux0000<2>18_SW0/O_pack_1 ;
wire \pstate<3>/CLKINV_2521 ;
wire N26;
wire \baud1/timer_mux0000<4>_SW0/O_pack_1 ;
wire \baud1/baud_cmp_eq0000 ;
wire \baud1/baud_cmp_eq0000853/O_pack_1 ;
wire \baud1/timer<6>/DXMUX_2771 ;
wire N30_pack_2;
wire \baud1/timer<6>/CLKINV_2754 ;
wire \baud1/timer<5>/DXMUX_2806 ;
wire \baud1/timer_mux0000<0>11_SW6/O_pack_2 ;
wire \baud1/timer<5>/CLKINV_2790 ;
wire \fifo1/N8 ;
wire \fifo1/N3_pack_1 ;
wire \baud1/timer<7>/DXMUX_2736 ;
wire \baud1/timer_mux0000<0>11_SW7/O_pack_2 ;
wire \baud1/timer<7>/CLKINV_2720 ;
wire \pstate_mux0000<3>15_2590 ;
wire N16_pack_1;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_2986 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_2973 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_2964 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_2963 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_2962 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/DXMUX_1719 ;
wire \fifo1/Result<1>1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/DYMUX_1704 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_1701 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/SRINV_1695 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/CLKINV_1694 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/CEINV_1693 ;
wire \load/DXMUX_1614 ;
wire \load/FXMUX_1613 ;
wire ld_shift_1611;
wire N20_pack_1;
wire \load/CLKINV_1597 ;
wire \pstate_mux0000<2>10_1642 ;
wire \pstate_mux0000<2>4_pack_1 ;
wire \full/DYMUX_1581 ;
wire \full/CLKINV_1579 ;
wire \pstate<2>/DXMUX_1673 ;
wire \pstate_mux0000<3>2_pack_1 ;
wire \pstate<2>/CLKINV_1655 ;
wire \bittimer<0>/DXMUX_1568 ;
wire \bittimer<0>/DYMUX_1559 ;
wire \bittimer<0>/SRINV_1549 ;
wire \bittimer<0>/CLKINV_1548 ;
wire \bittimer<0>/CEINV_1547 ;
wire \bitcounter<3>/DXMUX_1764 ;
wire Mcount_bitcounter3;
wire N14_pack_3;
wire \bitcounter<3>/CLKINV_1747 ;
wire \bitcounter<3>/CEINV_1746 ;
wire \empty/DYMUX_1730 ;
wire \empty/CLKINV_1728 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX_3689 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/BXINV_3688 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/REVUSED_3687 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV_3685 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV_3684 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CEINV_3683 ;
wire dout_1_OBUF_3674;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DXMUX_3893 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DYMUX_3886 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV_3884 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV_3883 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV_3882 ;
wire \frame_error<7>/DXMUX_3740 ;
wire \frame_error<7>/DYMUX_3731 ;
wire \frame_error<7>/SRINV_3729 ;
wire \frame_error<7>/CLKINV_3728 ;
wire \frame_error<7>/CEINV_3727 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DXMUX_3869 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DYMUX_3862 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/SRINV_3860 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CLKINV_3859 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CEINV_3858 ;
wire \dout_fifo<5>/DXMUX_3714 ;
wire \dout_fifo<5>/DYMUX_3707 ;
wire \dout_fifo<5>/SRINV_3705 ;
wire \dout_fifo<5>/CLKINV_3704 ;
wire \dout_fifo<5>/CEINV_3703 ;
wire \dout_fifo<1>/DXMUX_3579 ;
wire \dout_fifo<1>/DYMUX_3572 ;
wire \dout_fifo<1>/SRINV_3570 ;
wire \dout_fifo<1>/CLKINV_3569 ;
wire \dout_fifo<1>/CEINV_3568 ;
wire \frame_error<3>/FFX/RST ;
wire \frame_error<3>/FFY/RST ;
wire \frame_error<3>/DXMUX_3605 ;
wire \frame_error<3>/DYMUX_3596 ;
wire \frame_error<3>/SRINV_3594 ;
wire \frame_error<3>/CLKINV_3593 ;
wire \frame_error<3>/CEINV_3592 ;
wire \frame_error<5>/FFX/RST ;
wire \frame_error<5>/FFY/RST ;
wire \frame_error<5>/DXMUX_3657 ;
wire \frame_error<5>/DYMUX_3648 ;
wire \frame_error<5>/SRINV_3646 ;
wire \frame_error<5>/CLKINV_3645 ;
wire \frame_error<5>/CEINV_3644 ;
wire \dout_fifo<8>/DYMUX_3819 ;
wire \dout_fifo<8>/SRINV_3817 ;
wire \dout_fifo<8>/CLKINV_3816 ;
wire \dout_fifo<8>/CEINV_3815 ;
wire \shift<3>/DXMUX_3844 ;
wire \shift<3>/DYMUX_3836 ;
wire \shift<3>/SRINV_3834 ;
wire \shift<3>/CLKINV_3833 ;
wire \shift<3>/CEINV_3832 ;
wire \dout_fifo<3>/DXMUX_3631 ;
wire \dout_fifo<3>/DYMUX_3624 ;
wire \dout_fifo<3>/SRINV_3622 ;
wire \dout_fifo<3>/CLKINV_3621 ;
wire \dout_fifo<3>/CEINV_3620 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_3558 ;
wire \baud1/baud_cmp_eq0000826_3757 ;
wire \dout_fifo<7>/DXMUX_3778 ;
wire \dout_fifo<7>/DYMUX_3771 ;
wire \dout_fifo<7>/SRINV_3769 ;
wire \dout_fifo<7>/CLKINV_3768 ;
wire \dout_fifo<7>/CEINV_3767 ;
wire \shift<1>/DXMUX_3803 ;
wire \shift<1>/DYMUX_3795 ;
wire \shift<1>/SRINV_3793 ;
wire \shift<1>/CLKINV_3792 ;
wire \shift<1>/CEINV_3791 ;
wire \shift<5>/DXMUX_1164 ;
wire \shift<5>/DYMUX_1156 ;
wire \shift<5>/SRINV_1154 ;
wire \shift<5>/CLKINV_1153 ;
wire \shift<5>/CEINV_1152 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DXMUX_1189 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DYMUX_1182 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/SRINV_1180 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CLKINV_1179 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CEINV_1178 ;
wire \shift<7>/DXMUX_1238 ;
wire \shift<7>/DYMUX_1230 ;
wire \shift<7>/SRINV_1228 ;
wire \shift<7>/CLKINV_1227 ;
wire \shift<7>/CEINV_1226 ;
wire \control<0>/DYMUX_1254 ;
wire \control<0>/CLKINV_1251 ;
wire \control<0>/CEINV_1250 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX_1213 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX_1206 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_1204 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_1203 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_1202 ;
wire \shift<9>/DXMUX_1305 ;
wire \shift<9>/DYMUX_1297 ;
wire \shift<9>/SRINV_1295 ;
wire \shift<9>/CLKINV_1294 ;
wire \shift<9>/CEINV_1293 ;
wire \bitcounter<0>/FFX/RSTAND_1808 ;
wire \baud1/timer<4>/DXMUX_1357 ;
wire \baud1/baud_cmp_eq0000893_1347 ;
wire \baud1/timer<4>/CLKINV_1341 ;
wire \baud1/timer<3>/DXMUX_1425 ;
wire N28;
wire \baud1/timer<3>/CLKINV_1407 ;
wire \fifo1/N23 ;
wire \fifo1/N9 ;
wire \fifo1/N5 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_pack_1 ;
wire \bitcounter<1>/DXMUX_1462 ;
wire Mcount_bitcounter1;
wire N10_pack_2;
wire \bitcounter<1>/CLKINV_1444 ;
wire \bitcounter<1>/CEINV_1443 ;
wire \pstate<4>/DXMUX_1508 ;
wire \pstate<4>/DYMUX_1492 ;
wire bitcounter_not0001;
wire \pstate<4>/SRINV_1481 ;
wire \pstate<4>/CLKINV_1480 ;
wire \bitcounter<3>/FFX/RSTAND_1770 ;
wire \control<2>/DYMUX_1321 ;
wire \control<2>/CLKINV_1318 ;
wire \control<2>/CEINV_1317 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/DXMUX_1392 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/SRINV_1376 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/CLKINV_1375 ;
wire dout_0_OBUF_3482;
wire wr_control;
wire \baud1/baud/DYMUX_3360 ;
wire \baud1/baud/CLKINV_3357 ;
wire \baud1/baud/CEINV_3356 ;
wire \baud1/period<5>/DXMUX_3252 ;
wire \baud1/period<5>/DYMUX_3244 ;
wire \baud1/period<5>/SRINV_3242 ;
wire \baud1/period<5>/CLKINV_3241 ;
wire \baud1/period<5>/CEINV_3240 ;
wire \bittimer<3>/DXMUX_3123 ;
wire \bittimer<3>/DYMUX_3108 ;
wire \bittimer<3>/SRINV_3099 ;
wire \bittimer<3>/CLKINV_3098 ;
wire \bittimer<3>/CEINV_3097 ;
wire control_2_not0001;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ;
wire \fifo1/N7 ;
wire \baud1/period<1>/DXMUX_3199 ;
wire \baud1/period<1>/DYMUX_3190 ;
wire \baud1/period<1>/SRINV_3188 ;
wire \baud1/period<1>/CLKINV_3187 ;
wire \baud1/period<1>/CEINV_3186 ;
wire \baud1/period<3>/DXMUX_3226 ;
wire \baud1/period<3>/DYMUX_3217 ;
wire \baud1/period<3>/SRINV_3215 ;
wire \baud1/period<3>/CLKINV_3214 ;
wire \baud1/period<3>/CEINV_3213 ;
wire \loaded/DXMUX_3343 ;
wire \loaded/FXMUX_3342 ;
wire loaded_mux0000_3340;
wire N22_pack_1;
wire \loaded/CLKINVNOT ;
wire \loaded/CEINV_3325 ;
wire \control<1>/DXMUX_3026 ;
wire control_1_mux0000;
wire \control<1>/DYMUX_3011 ;
wire \control<1>/SRINV_3003 ;
wire \control<1>/CLKINV_3002 ;
wire \bitcounter<2>/DYMUX_3077 ;
wire Mcount_bitcounter2;
wire \bitcounter<2>/CLKINV_3067 ;
wire \bitcounter<2>/CEINV_3066 ;
wire \fifo1/N21 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ;
wire rd_fifo_pack_1;
wire \frame_error<8>/DYMUX_3051 ;
wire frame_error_8_or0000;
wire \frame_error<8>/CLKINV_3040 ;
wire \frame_error<8>/CEINV_3039 ;
wire \baud1/period<7>/DXMUX_3304 ;
wire \baud1/period<7>/DYMUX_3295 ;
wire \baud1/period<7>/SRINV_3293 ;
wire \baud1/period<7>/CLKINV_3292 ;
wire \baud1/period<7>/CEINV_3291 ;
wire loaded_not0001;
wire N24_pack_1;
wire wr_baud;
wire dout_8_OBUF_3451;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/DXMUX_3407 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/DYMUX_3392 ;
wire \fifo1/N17 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/SRINV_3381 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/CLKINV_3380 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/CEINV_3379 ;
wire \frame_error<1>/FFX/RST ;
wire \frame_error<1>/FFY/RST ;
wire \frame_error<1>/DXMUX_3541 ;
wire \frame_error<1>/DYMUX_3532 ;
wire \frame_error<1>/SRINV_3530 ;
wire \frame_error<1>/CLKINV_3529 ;
wire \frame_error<1>/CEINV_3528 ;
wire dout_2_OBUF_3518;
wire \dout<2>10_pack_1 ;
wire \baud1/baud_cmp_eq00008120_3494 ;
wire \control<0>/FFY/RSTAND_1260 ;
wire \control<2>/FFY/RSTAND_1327 ;
wire \baud1/timer<3>/FFX/RSTAND_1430 ;
wire \baud1/timer<4>/FFX/RSTAND_1362 ;
wire \bitcounter<1>/FFX/RSTAND_1468 ;
wire \load/FFX/RSTAND_1619 ;
wire \pstate<2>/FFX/RSTAND_1678 ;
wire \baud1/baud/FFY/RSTAND_3366 ;
wire \loaded/FFX/RSTAND_3349 ;
wire \pstate<1>/FFX/RSTAND_2508 ;
wire \baud1/timer<2>/FFX/RSTAND_2443 ;
wire \pstate<3>/FFX/RSTAND_2543 ;
wire \baud1/timer<6>/FFX/RSTAND_2776 ;
wire \baud1/timer<5>/FFX/RSTAND_2811 ;
wire \baud1/timer<7>/FFX/RSTAND_2741 ;
wire \frame_ready/FFX/RSTAND_2706 ;
wire \bitcounter<2>/FFY/RSTAND_3083 ;
wire \frame_error<8>/FFY/RSTAND_3057 ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<2> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<17> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<24> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25> ;
wire GND;
wire VCC;
wire \NLW_Mshreg_in_two/SRL16E_Q15_UNCONNECTED ;
wire [9 : 0] shift;
wire [3 : 0] \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count ;
wire [5 : 0] pstate;
wire [3 : 0] \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 ;
wire [3 : 0] \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count ;
wire [3 : 0] \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 ;
wire [2 : 0] control;
wire [7 : 0] \baud1/timer ;
wire [7 : 0] \baud1/period ;
wire [3 : 0] bitcounter;
wire [3 : 0] bittimer;
wire [8 : 0] frame_error;
wire [8 : 0] \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem ;
wire [8 : 0] dout_fifo;
wire [7 : 0] \baud1/timer_mux0000 ;
wire [5 : 1] pstate_mux0000;
wire [3 : 1] \fifo1/Result ;
wire [3 : 1] Result;
initial $sdf_annotate("netgen/par/uart_rx_timesim.sdf");
X_IPAD #(
.LOC ( "PAD31" ))
\din<4>/PAD (
.PAD(din[4])
);
X_BUF #(
.LOC ( "PAD31" ))
din_4_IBUF (
.I(din[4]),
.O(\din<4>/INBUF )
);
X_IPAD #(
.LOC ( "PAD34" ))
\din<2>/PAD (
.PAD(din[2])
);
X_BUF #(
.LOC ( "PAD34" ))
din_2_IBUF (
.I(din[2]),
.O(\din<2>/INBUF )
);
X_OPAD #(
.LOC ( "PAD38" ))
\dout<7>/PAD (
.PAD(dout[7])
);
X_OBUF #(
.LOC ( "PAD38" ))
dout_7_OBUF (
.I(\dout<7>/O ),
.O(dout[7])
);
X_OPAD #(
.LOC ( "PAD45" ))
\dout<3>/PAD (
.PAD(dout[3])
);
X_OBUF #(
.LOC ( "PAD45" ))
dout_3_OBUF (
.I(\dout<3>/O ),
.O(dout[3])
);
X_IPAD #(
.LOC ( "PAD39" ))
\wren/PAD (
.PAD(wren)
);
X_BUF #(
.LOC ( "PAD39" ))
wren_IBUF (
.I(wren),
.O(\wren/INBUF )
);
X_OPAD #(
.LOC ( "PAD40" ))
\dout<5>/PAD (
.PAD(dout[5])
);
X_OBUF #(
.LOC ( "PAD40" ))
dout_5_OBUF (
.I(\dout<5>/O ),
.O(dout[5])
);
X_IPAD #(
.LOC ( "IPAD12" ))
\clk/PAD (
.PAD(clk)
);
X_BUF #(
.LOC ( "IPAD12" ))
\clk_BUFGP/IBUFG (
.I(clk),
.O(\clk/INBUF )
);
X_OPAD #(
.LOC ( "PAD47" ))
\dout<0>/PAD (
.PAD(dout[0])
);
X_OBUF #(
.LOC ( "PAD47" ))
dout_0_OBUF (
.I(\dout<0>/O ),
.O(dout[0])
);
X_OPAD #(
.LOC ( "PAD44" ))
\dout<8>/PAD (
.PAD(dout[8])
);
X_OBUF #(
.LOC ( "PAD44" ))
dout_8_OBUF (
.I(\dout<8>/O ),
.O(dout[8])
);
X_IPAD #(
.LOC ( "PAD51" ))
\reset/PAD (
.PAD(reset)
);
X_BUF #(
.LOC ( "PAD51" ))
reset_IBUF (
.I(reset),
.O(\reset/INBUF )
);
X_IPAD #(
.LOC ( "PAD33" ))
\din<3>/PAD (
.PAD(din[3])
);
X_BUF #(
.LOC ( "PAD33" ))
din_3_IBUF (
.I(din[3]),
.O(\din<3>/INBUF )
);
X_IPAD #(
.LOC ( "PAD54" ))
\rden/PAD (
.PAD(rden)
);
X_BUF #(
.LOC ( "PAD54" ))
rden_IBUF (
.I(rden),
.O(\rden/INBUF )
);
X_IPAD #(
.LOC ( "PAD30" ))
\din<5>/PAD (
.PAD(din[5])
);
X_BUF #(
.LOC ( "PAD30" ))
din_5_IBUF (
.I(din[5]),
.O(\din<5>/INBUF )
);
X_IPAD #(
.LOC ( "PAD25" ))
\rxin/PAD (
.PAD(rxin)
);
X_BUF #(
.LOC ( "PAD25" ))
rxin_IBUF (
.I(rxin),
.O(\rxin/INBUF )
);
X_OPAD #(
.LOC ( "PAD43" ))
\dout<4>/PAD (
.PAD(dout[4])
);
X_OBUF #(
.LOC ( "PAD43" ))
dout_4_OBUF (
.I(\dout<4>/O ),
.O(dout[4])
);
X_OPAD #(
.LOC ( "PAD42" ))
\dout<6>/PAD (
.PAD(dout[6])
);
X_OBUF #(
.LOC ( "PAD42" ))
dout_6_OBUF (
.I(\dout<6>/O ),
.O(dout[6])
);
X_IPAD #(
.LOC ( "PAD29" ))
\din<6>/PAD (
.PAD(din[6])
);
X_BUF #(
.LOC ( "PAD29" ))
din_6_IBUF (
.I(din[6]),
.O(\din<6>/INBUF )
);
X_IPAD #(
.LOC ( "PAD28" ))
\din<7>/PAD (
.PAD(din[7])
);
X_BUF #(
.LOC ( "PAD28" ))
din_7_IBUF (
.I(din[7]),
.O(\din<7>/INBUF )
);
X_OPAD #(
.LOC ( "PAD37" ))
\dout<2>/PAD (
.PAD(dout[2])
);
X_OBUF #(
.LOC ( "PAD37" ))
dout_2_OBUF (
.I(\dout<2>/O ),
.O(dout[2])
);
X_OPAD #(
.LOC ( "PAD49" ))
\dout<1>/PAD (
.PAD(dout[1])
);
X_OBUF #(
.LOC ( "PAD49" ))
dout_1_OBUF (
.I(\dout<1>/O ),
.O(dout[1])
);
X_BUF #(
.LOC ( "PAD54" ))
\rden/IFF/IMUX (
.I(\rden/INBUF ),
.O(rden_IBUF_1051)
);
X_IPAD #(
.LOC ( "PAD52" ))
\addr<0>/PAD (
.PAD(addr[0])
);
X_BUF #(
.LOC ( "PAD52" ))
addr_0_IBUF (
.I(addr[0]),
.O(\addr<0>/INBUF )
);
X_BUF #(
.LOC ( "SLICE_X19Y29" ))
\bitcounter<0>/DXMUX (
.I(Mcount_bitcounter),
.O(\bitcounter<0>/DXMUX_1802 )
);
X_BUF #(
.LOC ( "SLICE_X19Y29" ))
\bitcounter<0>/YUSED (
.I(bittime),
.O(bittime_0)
);
X_BUF #(
.LOC ( "SLICE_X19Y29" ))
\bitcounter<0>/CLKINV (
.I(clk_BUFGP),
.O(\bitcounter<0>/CLKINV_1785 )
);
X_BUF #(
.LOC ( "SLICE_X19Y29" ))
\bitcounter<0>/CEINV (
.I(bitcounter_not0001_0),
.O(\bitcounter<0>/CEINV_1784 )
);
X_IPAD #(
.LOC ( "PAD53" ))
\addr<2>/PAD (
.PAD(addr[2])
);
X_BUF #(
.LOC ( "PAD53" ))
addr_2_IBUF (
.I(addr[2]),
.O(\addr<2>/INBUF )
);
X_BUF #(
.LOC ( "SLICE_X25Y25" ))
\dout<1>30/XUSED (
.I(\dout<1>30/F5MUX_2226 ),
.O(\dout<1>30 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y25" ))
\dout<1>30/F5MUX (
.IA(N77),
.IB(N78),
.SEL(\dout<1>30/BXINV_2219 ),
.O(\dout<1>30/F5MUX_2226 )
);
X_BUF #(
.LOC ( "SLICE_X25Y25" ))
\dout<1>30/BXINV (
.I(addr_0_IBUF_1064),
.O(\dout<1>30/BXINV_2219 )
);
X_BUF #(
.LOC ( "SLICE_X17Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FXMUX_2305 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DXMUX_2306 )
);
X_BUF #(
.LOC ( "SLICE_X17Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/F5MUX_2304 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FXMUX_2305 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/F5MUX (
.IA(\fifo1/N25 ),
.IB(\fifo1/N26 ),
.SEL(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/BXINV_2297 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/F5MUX_2304 )
);
X_BUF #(
.LOC ( "SLICE_X17Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/BXINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_998 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/BXINV_2297 )
);
X_BUF #(
.LOC ( "SLICE_X17Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV_2289 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y27" ))
\dout_3_OBUF/F5MUX (
.IA(\dout<3>2_2241 ),
.IB(\dout<3>1_2249 ),
.SEL(\dout_3_OBUF/BXINV_2243 ),
.O(\dout_3_OBUF/F5MUX_2251 )
);
X_BUF #(
.LOC ( "SLICE_X29Y27" ))
\dout_3_OBUF/BXINV (
.I(addr_0_IBUF_1064),
.O(\dout_3_OBUF/BXINV_2243 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y24" ))
\dout_5_OBUF/F5MUX (
.IA(\dout<5>2_2323 ),
.IB(\dout<5>1_2331 ),
.SEL(\dout_5_OBUF/BXINV_2325 ),
.O(\dout_5_OBUF/F5MUX_2333 )
);
X_BUF #(
.LOC ( "SLICE_X29Y24" ))
\dout_5_OBUF/BXINV (
.I(addr_0_IBUF_1064),
.O(\dout_5_OBUF/BXINV_2325 )
);
X_RAMB16_S36_S36 #(
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.WRITE_MODE_A ( "NO_CHANGE" ),
.WRITE_MODE_B ( "NO_CHANGE" ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.LOC ( "RAMB16_X0Y3" ),
.SETUP_ALL ( 227 ),
.SETUP_READ_FIRST ( 227 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram (
.CLKA(clk_BUFGP),
.CLKB(clk_BUFGP),
.ENA(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.ENB(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en_0 ),
.SSRA(1'b0),
.SSRB(pstate[0]),
.WEA(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.WEB(1'b0),
.ADDRA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0>
}),
.ADDRB({1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0>
}),
.DIA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<24>
, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<17>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16>
, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8>
, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<2>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0>
}),
.DIPA({1'b0, 1'b0, 1'b0, 1'b0}),
.DIB({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB31
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB30
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB29
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB28
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB27
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB26
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB25
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB24
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB23
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB22
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB21
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB20
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB19
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB18
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB17
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB16
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB15
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB14
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB13
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB12
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB11
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB10
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB9
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB8
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB7
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB6
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB5
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB4
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB3
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB2
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB1
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB0
}),
.DIPB({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB3
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB2
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB1
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB0
}),
.DOA({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA31
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA30
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA29
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA28
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA27
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA26
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA25
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA24
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA23
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA22
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA21
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA20
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA19
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA18
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA17
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA16
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA15
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA14
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA13
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA12
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA11
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA10
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA9
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA8
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA7
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA6
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA5
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA4
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA3
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA2
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA1
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA0
}),
.DOPA({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA3
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA2
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA1
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA0
}),
.DOB({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB31
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB30
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB29
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB28
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB27
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB26
, \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [8],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [7],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB23
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB22
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB21
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB20
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB19
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB18
, \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [6],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [5],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB15
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB14
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB13
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB12
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB11
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB10
, \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [4],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [3],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB7
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB6
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB5
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB4
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB3
, \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [2],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [1],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [0]}),
.DOPB({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB3
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB2
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB1
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB0
})
);
X_BUF #(
.LOC ( "SLICE_X27Y28" ))
\baud1/timer<2>/DXMUX (
.I(\baud1/timer_mux0000 [5]),
.O(\baud1/timer<2>/DXMUX_2438 )
);
X_BUF #(
.LOC ( "SLICE_X27Y28" ))
\baud1/timer<2>/YUSED (
.I(\baud1/timer_mux0000<0>11_SW5/O_pack_2 ),
.O(\baud1/timer_mux0000<0>11_SW5/O )
);
X_BUF #(
.LOC ( "SLICE_X27Y28" ))
\baud1/timer<2>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<2>/CLKINV_2422 )
);
X_BUF #(
.LOC ( "SLICE_X13Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_2471 )
);
X_BUF #(
.LOC ( "SLICE_X13Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/YUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000100_SW0_SW0_SW0/O_pack_2 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000100_SW0_SW0_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X13Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_2456 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y26" ))
\dout_7_OBUF/F5MUX (
.IA(\dout<7>2_2166 ),
.IB(\dout<7>1_2174 ),
.SEL(\dout_7_OBUF/BXINV_2168 ),
.O(\dout_7_OBUF/F5MUX_2176 )
);
X_BUF #(
.LOC ( "SLICE_X28Y26" ))
\dout_7_OBUF/BXINV (
.I(addr_0_IBUF_1064),
.O(\dout_7_OBUF/BXINV_2168 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y27" ))
\dout_4_OBUF/F5MUX (
.IA(\dout<4>2_2266 ),
.IB(\dout<4>1_2274 ),
.SEL(\dout_4_OBUF/BXINV_2268 ),
.O(\dout_4_OBUF/F5MUX_2276 )
);
X_BUF #(
.LOC ( "SLICE_X26Y27" ))
\dout_4_OBUF/BXINV (
.I(addr_0_IBUF_1064),
.O(\dout_4_OBUF/BXINV_2268 )
);
X_BUF #(
.LOC ( "SLICE_X23Y25" ))
\pstate<1>/DXMUX (
.I(pstate_mux0000[4]),
.O(\pstate<1>/DXMUX_2503 )
);
X_BUF #(
.LOC ( "SLICE_X23Y25" ))
\pstate<1>/YUSED (
.I(\pstate_mux0000<4>_SW0/O_pack_2 ),
.O(\pstate_mux0000<4>_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X23Y25" ))
\pstate<1>/CLKINV (
.I(clk_BUFGP),
.O(\pstate<1>/CLKINV_2486 )
);
X_BUFGMUX #(
.LOC ( "BUFGMUX_X2Y10" ))
\clk_BUFGP/BUFG (
.I0(\clk_BUFGP/BUFG/I0_INV ),
.I1(GND),
.S(\clk_BUFGP/BUFG/S_INVNOT ),
.O(clk_BUFGP)
);
X_INV #(
.LOC ( "BUFGMUX_X2Y10" ))
\clk_BUFGP/BUFG/SINV (
.I(1'b1),
.O(\clk_BUFGP/BUFG/S_INVNOT )
);
X_BUF #(
.LOC ( "BUFGMUX_X2Y10" ))
\clk_BUFGP/BUFG/I0_USED (
.I(\clk/INBUF ),
.O(\clk_BUFGP/BUFG/I0_INV )
);
X_BUF #(
.LOC ( "SLICE_X27Y27" ))
\dout<0>30/XUSED (
.I(\dout<0>30/F5MUX_2201 ),
.O(\dout<0>30 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y27" ))
\dout<0>30/F5MUX (
.IA(N79),
.IB(N80),
.SEL(\dout<0>30/BXINV_2194 ),
.O(\dout<0>30/F5MUX_2201 )
);
X_BUF #(
.LOC ( "SLICE_X27Y27" ))
\dout<0>30/BXINV (
.I(addr_0_IBUF_1064),
.O(\dout<0>30/BXINV_2194 )
);
X_BUF #(
.LOC ( "SLICE_X29Y26" ))
\N47/XUSED (
.I(\N47/F5MUX_2408 ),
.O(N47)
);
X_MUX2 #(
.LOC ( "SLICE_X29Y26" ))
\N47/F5MUX (
.IA(\N47/G ),
.IB(\dout<2>41_SW0 ),
.SEL(\N47/BXINV_2401 ),
.O(\N47/F5MUX_2408 )
);
X_BUF #(
.LOC ( "SLICE_X29Y26" ))
\N47/BXINV (
.I(rden_IBUF_1051),
.O(\N47/BXINV_2401 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y27" ))
\dout_6_OBUF/F5MUX (
.IA(\dout<6>2_2373 ),
.IB(\dout<6>1_2381 ),
.SEL(\dout_6_OBUF/BXINV_2375 ),
.O(\dout_6_OBUF/F5MUX_2383 )
);
X_BUF #(
.LOC ( "SLICE_X28Y27" ))
\dout_6_OBUF/BXINV (
.I(addr_0_IBUF_1064),
.O(\dout_6_OBUF/BXINV_2375 )
);
X_BUF #(
.LOC ( "SLICE_X25Y33" ))
\N41/XUSED (
.I(\N41/F5MUX_2358 ),
.O(N41)
);
X_MUX2 #(
.LOC ( "SLICE_X25Y33" ))
\N41/F5MUX (
.IA(N45),
.IB(N46),
.SEL(\N41/BXINV_2351 ),
.O(\N41/F5MUX_2358 )
);
X_BUF #(
.LOC ( "SLICE_X25Y33" ))
\N41/BXINV (
.I(pstate[1]),
.O(\N41/BXINV_2351 )
);
X_IPAD #(
.LOC ( "IPAD36" ))
\din<0>/PAD (
.PAD(din[0])
);
X_BUF #(
.LOC ( "IPAD36" ))
din_0_IBUF (
.I(din[0]),
.O(\din<0>/INBUF )
);
X_IPAD #(
.LOC ( "PAD48" ))
\addr<1>/PAD (
.PAD(addr[1])
);
X_BUF #(
.LOC ( "PAD48" ))
addr_1_IBUF (
.I(addr[1]),
.O(\addr<1>/INBUF )
);
X_IPAD #(
.LOC ( "PAD35" ))
\din<1>/PAD (
.PAD(din[1])
);
X_BUF #(
.LOC ( "PAD35" ))
din_1_IBUF (
.I(din[1]),
.O(\din<1>/INBUF )
);
X_BUF #(
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX (
.I(\fifo1/Result<3>1 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX_2944 )
);
X_BUF #(
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX (
.I(\fifo1/Result<2>1 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX_2931 )
);
X_BUF #(
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV (
.I(pstate[0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_2922 )
);
X_BUF #(
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_2921 )
);
X_BUF #(
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_2920 )
);
X_BUF #(
.LOC ( "SLICE_X26Y30" ))
\baud1/Madd_timer_addsub0000_cy<5>/XUSED (
.I(\baud1/Madd_timer_addsub0000_cy[5] ),
.O(\baud1/Madd_timer_addsub0000_cy<5>_0 )
);
X_BUF #(
.LOC ( "SLICE_X26Y30" ))
\baud1/Madd_timer_addsub0000_cy<5>/YUSED (
.I(\baud1/Madd_timer_addsub0000_cy<3>_pack_1 ),
.O(\baud1/Madd_timer_addsub0000_cy[3] )
);
X_BUF #(
.LOC ( "SLICE_X27Y33" ))
\baud1/timer<1>/DXMUX (
.I(\baud1/timer_mux0000 [6]),
.O(\baud1/timer<1>/DXMUX_2872 )
);
X_BUF #(
.LOC ( "SLICE_X27Y33" ))
\baud1/timer<1>/DYMUX (
.I(\baud1/timer_mux0000 [7]),
.O(\baud1/timer<1>/DYMUX_2858 )
);
X_BUF #(
.LOC ( "SLICE_X27Y33" ))
\baud1/timer<1>/SRINV (
.I(reset_IBUF_963),
.O(\baud1/timer<1>/SRINV_2850 )
);
X_BUF #(
.LOC ( "SLICE_X27Y33" ))
\baud1/timer<1>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<1>/CLKINV_2849 )
);
X_BUF #(
.LOC ( "SLICE_X19Y24" ))
\frame_ready/DXMUX (
.I(\frame_ready/FXMUX_2700 ),
.O(\frame_ready/DXMUX_2701 )
);
X_BUF #(
.LOC ( "SLICE_X19Y24" ))
\frame_ready/XUSED (
.I(\frame_ready/FXMUX_2700 ),
.O(finish_0)
);
X_BUF #(
.LOC ( "SLICE_X19Y24" ))
\frame_ready/FXMUX (
.I(finish),
.O(\frame_ready/FXMUX_2700 )
);
X_BUF #(
.LOC ( "SLICE_X19Y24" ))
\frame_ready/YUSED (
.I(\bitcounter_not00011_SW0/O_pack_1 ),
.O(\bitcounter_not00011_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X19Y24" ))
\frame_ready/CLKINV (
.I(clk_BUFGP),
.O(\frame_ready/CLKINV_2683 )
);
X_BUF #(
.LOC ( "SLICE_X18Y23" ))
\in_two/DYMUX (
.I(Mshreg_in_two),
.O(\in_two/DYMUX_2904 )
);
X_BUF #(
.LOC ( "SLICE_X18Y23" ))
\in_two/DIG_MUX (
.I(rxin_IBUF_1000),
.O(\in_two/DIG_MUX_2893 )
);
X_BUF #(
.LOC ( "SLICE_X18Y23" ))
\in_two/SRINV (
.I(1'b1),
.O(\in_two/SRINV_2887 )
);
X_BUF #(
.LOC ( "SLICE_X18Y23" ))
\in_two/CLKINV (
.I(clk_BUFGP),
.O(\in_two/CLKINV_2891 )
);
X_BUF #(
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX_2619 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX_2620 )
);
X_BUF #(
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX_2619 )
);
X_BUF #(
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/YUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000079/O_pack_2 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000079/O )
);
X_BUF #(
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV_2605 )
);
X_BUF #(
.LOC ( "SLICE_X19Y28" ))
\pstate<3>/DXMUX (
.I(pstate_mux0000[2]),
.O(\pstate<3>/DXMUX_2538 )
);
X_BUF #(
.LOC ( "SLICE_X19Y28" ))
\pstate<3>/YUSED (
.I(\pstate_mux0000<2>18_SW0/O_pack_1 ),
.O(\pstate_mux0000<2>18_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X19Y28" ))
\pstate<3>/CLKINV (
.I(clk_BUFGP),
.O(\pstate<3>/CLKINV_2521 )
);
X_BUF #(
.LOC ( "SLICE_X26Y31" ))
\N26/XUSED (
.I(N26),
.O(N26_0)
);
X_BUF #(
.LOC ( "SLICE_X26Y31" ))
\N26/YUSED (
.I(\baud1/timer_mux0000<4>_SW0/O_pack_1 ),
.O(\baud1/timer_mux0000<4>_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X26Y29" ))
\baud1/baud_cmp_eq0000/XUSED (
.I(\baud1/baud_cmp_eq0000 ),
.O(\baud1/baud_cmp_eq0000_0 )
);
X_BUF #(
.LOC ( "SLICE_X26Y29" ))
\baud1/baud_cmp_eq0000/YUSED (
.I(\baud1/baud_cmp_eq0000853/O_pack_1 ),
.O(\baud1/baud_cmp_eq0000853/O )
);
X_BUF #(
.LOC ( "SLICE_X26Y33" ))
\baud1/timer<6>/DXMUX (
.I(\baud1/timer_mux0000 [1]),
.O(\baud1/timer<6>/DXMUX_2771 )
);
X_BUF #(
.LOC ( "SLICE_X26Y33" ))
\baud1/timer<6>/YUSED (
.I(N30_pack_2),
.O(N30)
);
X_BUF #(
.LOC ( "SLICE_X26Y33" ))
\baud1/timer<6>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<6>/CLKINV_2754 )
);
X_BUF #(
.LOC ( "SLICE_X27Y31" ))
\baud1/timer<5>/DXMUX (
.I(\baud1/timer_mux0000 [2]),
.O(\baud1/timer<5>/DXMUX_2806 )
);
X_BUF #(
.LOC ( "SLICE_X27Y31" ))
\baud1/timer<5>/YUSED (
.I(\baud1/timer_mux0000<0>11_SW6/O_pack_2 ),
.O(\baud1/timer_mux0000<0>11_SW6/O )
);
X_BUF #(
.LOC ( "SLICE_X27Y31" ))
\baud1/timer<5>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<5>/CLKINV_2790 )
);
X_BUF #(
.LOC ( "SLICE_X12Y22" ))
\fifo1/N8/XUSED (
.I(\fifo1/N8 ),
.O(\fifo1/N8_0 )
);
X_BUF #(
.LOC ( "SLICE_X12Y22" ))
\fifo1/N8/YUSED (
.I(\fifo1/N3_pack_1 ),
.O(\fifo1/N3 )
);
X_BUF #(
.LOC ( "SLICE_X26Y32" ))
\baud1/timer<7>/DXMUX (
.I(\baud1/timer_mux0000 [0]),
.O(\baud1/timer<7>/DXMUX_2736 )
);
X_BUF #(
.LOC ( "SLICE_X26Y32" ))
\baud1/timer<7>/YUSED (
.I(\baud1/timer_mux0000<0>11_SW7/O_pack_2 ),
.O(\baud1/timer_mux0000<0>11_SW7/O )
);
X_BUF #(
.LOC ( "SLICE_X26Y32" ))
\baud1/timer<7>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<7>/CLKINV_2720 )
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\pstate_mux0000<3>15/XUSED (
.I(\pstate_mux0000<3>15_2590 ),
.O(\pstate_mux0000<3>15_0 )
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\pstate_mux0000<3>15/YUSED (
.I(N16_pack_1),
.O(N16)
);
X_BUF #(
.LOC ( "SLICE_X12Y28" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX (
.I(\fifo1/Result [3]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_2986 )
);
X_BUF #(
.LOC ( "SLICE_X12Y28" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX (
.I(\fifo1/Result [2]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_2973 )
);
X_BUF #(
.LOC ( "SLICE_X12Y28" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV (
.I(pstate[0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_2964 )
);
X_BUF #(
.LOC ( "SLICE_X12Y28" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_2963 )
);
X_BUF #(
.LOC ( "SLICE_X12Y28" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_2962 )
);
X_BUF #(
.LOC ( "SLICE_X13Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/DXMUX (
.I(\fifo1/Result<1>1 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/DXMUX_1719 )
);
X_INV #(
.LOC ( "SLICE_X13Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/DYMUX_1704 )
);
X_BUF #(
.LOC ( "SLICE_X13Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/YUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_1701 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_0 )
);
X_BUF #(
.LOC ( "SLICE_X13Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/SRINV (
.I(pstate[0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/SRINV_1695 )
);
X_BUF #(
.LOC ( "SLICE_X13Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/CLKINV_1694 )
);
X_BUF #(
.LOC ( "SLICE_X13Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/CEINV_1693 )
);
X_BUF #(
.LOC ( "SLICE_X16Y27" ))
\load/DXMUX (
.I(\load/FXMUX_1613 ),
.O(\load/DXMUX_1614 )
);
X_BUF #(
.LOC ( "SLICE_X16Y27" ))
\load/XUSED (
.I(\load/FXMUX_1613 ),
.O(ld_shift_0)
);
X_BUF #(
.LOC ( "SLICE_X16Y27" ))
\load/FXMUX (
.I(ld_shift_1611),
.O(\load/FXMUX_1613 )
);
X_BUF #(
.LOC ( "SLICE_X16Y27" ))
\load/YUSED (
.I(N20_pack_1),
.O(N20)
);
X_BUF #(
.LOC ( "SLICE_X16Y27" ))
\load/CLKINV (
.I(clk_BUFGP),
.O(\load/CLKINV_1597 )
);
X_BUF #(
.LOC ( "PAD39" ))
\wren/IFF/IMUX (
.I(\wren/INBUF ),
.O(wren_IBUF_1047)
);
X_BUF #(
.LOC ( "SLICE_X17Y26" ))
\pstate_mux0000<2>10/XUSED (
.I(\pstate_mux0000<2>10_1642 ),
.O(\pstate_mux0000<2>10_0 )
);
X_BUF #(
.LOC ( "SLICE_X17Y26" ))
\pstate_mux0000<2>10/YUSED (
.I(\pstate_mux0000<2>4_pack_1 ),
.O(\pstate_mux0000<2>4_1033 )
);
X_BUF #(
.LOC ( "SLICE_X16Y24" ))
\full/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX_2619 ),
.O(\full/DYMUX_1581 )
);
X_BUF #(
.LOC ( "SLICE_X16Y24" ))
\full/CLKINV (
.I(clk_BUFGP),
.O(\full/CLKINV_1579 )
);
X_BUF #(
.LOC ( "SLICE_X18Y28" ))
\pstate<2>/DXMUX (
.I(pstate_mux0000[3]),
.O(\pstate<2>/DXMUX_1673 )
);
X_BUF #(
.LOC ( "SLICE_X18Y28" ))
\pstate<2>/YUSED (
.I(\pstate_mux0000<3>2_pack_1 ),
.O(\pstate_mux0000<3>2_1036 )
);
X_BUF #(
.LOC ( "SLICE_X18Y28" ))
\pstate<2>/CLKINV (
.I(clk_BUFGP),
.O(\pstate<2>/CLKINV_1655 )
);
X_INV #(
.LOC ( "SLICE_X21Y26" ))
\bittimer<0>/DXMUX (
.I(bittimer[0]),
.O(\bittimer<0>/DXMUX_1568 )
);
X_BUF #(
.LOC ( "SLICE_X21Y26" ))
\bittimer<0>/DYMUX (
.I(Result[1]),
.O(\bittimer<0>/DYMUX_1559 )
);
X_BUF #(
.LOC ( "SLICE_X21Y26" ))
\bittimer<0>/SRINV (
.I(reset_IBUF_963),
.O(\bittimer<0>/SRINV_1549 )
);
X_BUF #(
.LOC ( "SLICE_X21Y26" ))
\bittimer<0>/CLKINV (
.I(\baud1/baud_1023 ),
.O(\bittimer<0>/CLKINV_1548 )
);
X_BUF #(
.LOC ( "SLICE_X21Y26" ))
\bittimer<0>/CEINV (
.I(bittime_0),
.O(\bittimer<0>/CEINV_1547 )
);
X_BUF #(
.LOC ( "SLICE_X18Y26" ))
\bitcounter<3>/DXMUX (
.I(Mcount_bitcounter3),
.O(\bitcounter<3>/DXMUX_1764 )
);
X_BUF #(
.LOC ( "SLICE_X18Y26" ))
\bitcounter<3>/YUSED (
.I(N14_pack_3),
.O(N14)
);
X_BUF #(
.LOC ( "SLICE_X18Y26" ))
\bitcounter<3>/CLKINV (
.I(clk_BUFGP),
.O(\bitcounter<3>/CLKINV_1747 )
);
X_BUF #(
.LOC ( "SLICE_X18Y26" ))
\bitcounter<3>/CEINV (
.I(bitcounter_not0001_0),
.O(\bitcounter<3>/CEINV_1746 )
);
X_BUF #(
.LOC ( "SLICE_X18Y22" ))
\empty/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FXMUX_2305 ),
.O(\empty/DYMUX_1730 )
);
X_BUF #(
.LOC ( "SLICE_X18Y22" ))
\empty/CLKINV (
.I(clk_BUFGP),
.O(\empty/CLKINV_1728 )
);
X_SFF #(
.LOC ( "SLICE_X16Y25" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX_3689 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CEINV_3683 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV_3684 ),
.SET(GND),
.RST(GND),
.SSET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/REVUSED_3687 ),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV_3685 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_998 )
);
X_BUF #(
.LOC ( "SLICE_X16Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/BXINV_3688 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX_3689 )
);
X_BUF #(
.LOC ( "SLICE_X16Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/BXINV (
.I(1'b0),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/BXINV_3688 )
);
X_BUF #(
.LOC ( "SLICE_X16Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/REVUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_996 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/REVUSED_3687 )
);
X_BUF #(
.LOC ( "SLICE_X16Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV (
.I(pstate[0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV_3685 )
);
X_BUF #(
.LOC ( "SLICE_X16Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV (
.I(clk_BUFGP),
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X_LUT4 #(
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X_BUF #(
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\frame_error<7>/DYMUX (
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X_BUF #(
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X_BUF #(
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\frame_error<7>/CLKINV (
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X_BUF #(
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\frame_error<7>/CEINV (
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X_SFF #(
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X_SFF #(
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X_SFF #(
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.RST(GND),
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X_SFF #(
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\dout_fifo<5>/DXMUX (
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X_BUF #(
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\dout_fifo<5>/DYMUX (
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X_BUF #(
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\dout_fifo<5>/SRINV (
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X_BUF #(
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\dout_fifo<5>/CLKINV (
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X_BUF #(
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\dout_fifo<5>/CEINV (
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X_SFF #(
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X_SFF #(
.LOC ( "SLICE_X14Y26" ),
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X_BUF #(
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\dout_fifo<1>/DXMUX (
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X_BUF #(
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\dout_fifo<1>/DYMUX (
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X_BUF #(
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\dout_fifo<1>/SRINV (
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X_BUF #(
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\dout_fifo<1>/CLKINV (
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X_BUF #(
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\dout_fifo<1>/CEINV (
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X_BUF #(
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\frame_error<3>/FFX/RSTOR (
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X_FF #(
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frame_error_3 (
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X_BUF #(
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\frame_error<3>/FFY/RSTOR (
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X_FF #(
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frame_error_2 (
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X_BUF #(
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\frame_error<3>/DXMUX (
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X_BUF #(
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\frame_error<3>/DYMUX (
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X_BUF #(
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\frame_error<3>/SRINV (
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X_BUF #(
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\frame_error<3>/CLKINV (
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X_BUF #(
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\frame_error<3>/CEINV (
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X_BUF #(
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\frame_error<5>/FFX/RSTOR (
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X_FF #(
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frame_error_5 (
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X_BUF #(
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\frame_error<5>/FFY/RSTOR (
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X_FF #(
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frame_error_4 (
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X_BUF #(
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\frame_error<5>/DXMUX (
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X_BUF #(
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\frame_error<5>/DYMUX (
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.O(\frame_error<5>/DYMUX_3648 )
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X_BUF #(
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\frame_error<5>/SRINV (
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X_BUF #(
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\frame_error<5>/CLKINV (
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X_BUF #(
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\frame_error<5>/CEINV (
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X_SFF #(
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\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 (
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X_BUF #(
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\dout_fifo<8>/DYMUX (
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X_BUF #(
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\dout_fifo<8>/SRINV (
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.O(\dout_fifo<8>/SRINV_3817 )
);
X_BUF #(
.LOC ( "SLICE_X14Y27" ))
\dout_fifo<8>/CLKINV (
.I(clk_BUFGP),
.O(\dout_fifo<8>/CLKINV_3816 )
);
X_BUF #(
.LOC ( "SLICE_X14Y27" ))
\dout_fifo<8>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 ),
.O(\dout_fifo<8>/CEINV_3815 )
);
X_FF #(
.LOC ( "SLICE_X15Y24" ),
.INIT ( 1'b1 ))
shift_3 (
.I(\shift<3>/DXMUX_3844 ),
.CE(\shift<3>/CEINV_3832 ),
.CLK(\shift<3>/CLKINV_3833 ),
.SET(\shift<3>/SRINV_3834 ),
.RST(GND),
.O(shift[3])
);
X_FF #(
.LOC ( "SLICE_X15Y24" ),
.INIT ( 1'b1 ))
shift_2 (
.I(\shift<3>/DYMUX_3836 ),
.CE(\shift<3>/CEINV_3832 ),
.CLK(\shift<3>/CLKINV_3833 ),
.SET(\shift<3>/SRINV_3834 ),
.RST(GND),
.O(shift[2])
);
X_BUF #(
.LOC ( "SLICE_X15Y24" ))
\shift<3>/DXMUX (
.I(shift[4]),
.O(\shift<3>/DXMUX_3844 )
);
X_BUF #(
.LOC ( "SLICE_X15Y24" ))
\shift<3>/DYMUX (
.I(shift[3]),
.O(\shift<3>/DYMUX_3836 )
);
X_BUF #(
.LOC ( "SLICE_X15Y24" ))
\shift<3>/SRINV (
.I(reset_IBUF_963),
.O(\shift<3>/SRINV_3834 )
);
X_BUF #(
.LOC ( "SLICE_X15Y24" ))
\shift<3>/CLKINV (
.I(clk_BUFGP),
.O(\shift<3>/CLKINV_3833 )
);
X_BUF #(
.LOC ( "SLICE_X15Y24" ))
\shift<3>/CEINV (
.I(ld_shift_0),
.O(\shift<3>/CEINV_3832 )
);
X_SFF #(
.LOC ( "SLICE_X15Y27" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 (
.I(\dout_fifo<3>/DXMUX_3631 ),
.CE(\dout_fifo<3>/CEINV_3620 ),
.CLK(\dout_fifo<3>/CLKINV_3621 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\dout_fifo<3>/SRINV_3622 ),
.O(dout_fifo[3])
);
X_SFF #(
.LOC ( "SLICE_X15Y27" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 (
.I(\dout_fifo<3>/DYMUX_3624 ),
.CE(\dout_fifo<3>/CEINV_3620 ),
.CLK(\dout_fifo<3>/CLKINV_3621 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\dout_fifo<3>/SRINV_3622 ),
.O(dout_fifo[2])
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\dout_fifo<3>/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [3]),
.O(\dout_fifo<3>/DXMUX_3631 )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\dout_fifo<3>/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [2]),
.O(\dout_fifo<3>/DYMUX_3624 )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\dout_fifo<3>/SRINV (
.I(pstate[0]),
.O(\dout_fifo<3>/SRINV_3622 )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\dout_fifo<3>/CLKINV (
.I(clk_BUFGP),
.O(\dout_fifo<3>/CLKINV_3621 )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\dout_fifo<3>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 ),
.O(\dout_fifo<3>/CEINV_3620 )
);
X_LUT4 #(
.INIT ( 16'h8241 ),
.LOC ( "SLICE_X12Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_3558 )
);
X_BUF #(
.LOC ( "SLICE_X12Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056/XUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_3558 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_0 )
);
X_BUF #(
.LOC ( "SLICE_X26Y28" ))
\baud1/baud_cmp_eq0000826/XUSED (
.I(\baud1/baud_cmp_eq0000826_3757 ),
.O(\baud1/baud_cmp_eq0000826_0 )
);
X_BUF #(
.LOC ( "SLICE_X15Y26" ))
\dout_fifo<7>/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [7]),
.O(\dout_fifo<7>/DXMUX_3778 )
);
X_BUF #(
.LOC ( "SLICE_X15Y26" ))
\dout_fifo<7>/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [6]),
.O(\dout_fifo<7>/DYMUX_3771 )
);
X_BUF #(
.LOC ( "SLICE_X15Y26" ))
\dout_fifo<7>/SRINV (
.I(pstate[0]),
.O(\dout_fifo<7>/SRINV_3769 )
);
X_BUF #(
.LOC ( "SLICE_X15Y26" ))
\dout_fifo<7>/CLKINV (
.I(clk_BUFGP),
.O(\dout_fifo<7>/CLKINV_3768 )
);
X_BUF #(
.LOC ( "SLICE_X15Y26" ))
\dout_fifo<7>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 ),
.O(\dout_fifo<7>/CEINV_3767 )
);
X_BUF #(
.LOC ( "SLICE_X17Y22" ))
\shift<1>/DXMUX (
.I(shift[2]),
.O(\shift<1>/DXMUX_3803 )
);
X_BUF #(
.LOC ( "SLICE_X17Y22" ))
\shift<1>/DYMUX (
.I(shift[1]),
.O(\shift<1>/DYMUX_3795 )
);
X_BUF #(
.LOC ( "SLICE_X17Y22" ))
\shift<1>/SRINV (
.I(reset_IBUF_963),
.O(\shift<1>/SRINV_3793 )
);
X_BUF #(
.LOC ( "SLICE_X17Y22" ))
\shift<1>/CLKINV (
.I(clk_BUFGP),
.O(\shift<1>/CLKINV_3792 )
);
X_BUF #(
.LOC ( "SLICE_X17Y22" ))
\shift<1>/CEINV (
.I(ld_shift_0),
.O(\shift<1>/CEINV_3791 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\shift<5>/DXMUX (
.I(shift[6]),
.O(\shift<5>/DXMUX_1164 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\shift<5>/DYMUX (
.I(shift[5]),
.O(\shift<5>/DYMUX_1156 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\shift<5>/SRINV (
.I(reset_IBUF_963),
.O(\shift<5>/SRINV_1154 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\shift<5>/CLKINV (
.I(clk_BUFGP),
.O(\shift<5>/CLKINV_1153 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\shift<5>/CEINV (
.I(ld_shift_0),
.O(\shift<5>/CEINV_1152 )
);
X_BUF #(
.LOC ( "SLICE_X13Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DXMUX_1189 )
);
X_BUF #(
.LOC ( "SLICE_X13Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DYMUX_1182 )
);
X_BUF #(
.LOC ( "SLICE_X13Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/SRINV (
.I(pstate[0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/SRINV_1180 )
);
X_BUF #(
.LOC ( "SLICE_X13Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CLKINV_1179 )
);
X_BUF #(
.LOC ( "SLICE_X13Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CEINV_1178 )
);
X_BUF #(
.LOC ( "SLICE_X16Y23" ))
\shift<7>/DXMUX (
.I(shift[8]),
.O(\shift<7>/DXMUX_1238 )
);
X_BUF #(
.LOC ( "SLICE_X16Y23" ))
\shift<7>/DYMUX (
.I(shift[7]),
.O(\shift<7>/DYMUX_1230 )
);
X_BUF #(
.LOC ( "SLICE_X16Y23" ))
\shift<7>/SRINV (
.I(reset_IBUF_963),
.O(\shift<7>/SRINV_1228 )
);
X_BUF #(
.LOC ( "SLICE_X16Y23" ))
\shift<7>/CLKINV (
.I(clk_BUFGP),
.O(\shift<7>/CLKINV_1227 )
);
X_BUF #(
.LOC ( "SLICE_X16Y23" ))
\shift<7>/CEINV (
.I(ld_shift_0),
.O(\shift<7>/CEINV_1226 )
);
X_BUF #(
.LOC ( "SLICE_X26Y24" ))
\control<0>/DYMUX (
.I(din_0_IBUF_978),
.O(\control<0>/DYMUX_1254 )
);
X_BUF #(
.LOC ( "SLICE_X26Y24" ))
\control<0>/CLKINV (
.I(clk_BUFGP),
.O(\control<0>/CLKINV_1251 )
);
X_BUF #(
.LOC ( "SLICE_X26Y24" ))
\control<0>/CEINV (
.I(wr_control),
.O(\control<0>/CEINV_1250 )
);
X_BUF #(
.LOC ( "SLICE_X12Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX_1213 )
);
X_BUF #(
.LOC ( "SLICE_X12Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX_1206 )
);
X_BUF #(
.LOC ( "SLICE_X12Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV (
.I(pstate[0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_1204 )
);
X_BUF #(
.LOC ( "SLICE_X12Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_1203 )
);
X_BUF #(
.LOC ( "SLICE_X12Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_1202 )
);
X_BUF #(
.LOC ( "SLICE_X16Y22" ))
\shift<9>/DXMUX (
.I(in_two_983),
.O(\shift<9>/DXMUX_1305 )
);
X_BUF #(
.LOC ( "SLICE_X16Y22" ))
\shift<9>/DYMUX (
.I(shift[9]),
.O(\shift<9>/DYMUX_1297 )
);
X_BUF #(
.LOC ( "SLICE_X16Y22" ))
\shift<9>/SRINV (
.I(reset_IBUF_963),
.O(\shift<9>/SRINV_1295 )
);
X_BUF #(
.LOC ( "SLICE_X16Y22" ))
\shift<9>/CLKINV (
.I(clk_BUFGP),
.O(\shift<9>/CLKINV_1294 )
);
X_BUF #(
.LOC ( "SLICE_X16Y22" ))
\shift<9>/CEINV (
.I(ld_shift_0),
.O(\shift<9>/CEINV_1293 )
);
X_LUT4 #(
.INIT ( 16'hFFC8 ),
.LOC ( "SLICE_X19Y29" ))
bittime1 (
.ADR0(N16),
.ADR1(pstate[2]),
.ADR2(bitcounter[0]),
.ADR3(pstate[3]),
.O(bittime)
);
X_FF #(
.LOC ( "SLICE_X19Y29" ),
.INIT ( 1'b0 ))
bitcounter_0 (
.I(\bitcounter<0>/DXMUX_1802 ),
.CE(\bitcounter<0>/CEINV_1784 ),
.CLK(\bitcounter<0>/CLKINV_1785 ),
.SET(GND),
.RST(\bitcounter<0>/FFX/RSTAND_1808 ),
.O(bitcounter[0])
);
X_BUF #(
.LOC ( "SLICE_X19Y29" ))
\bitcounter<0>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\bitcounter<0>/FFX/RSTAND_1808 )
);
X_BUF #(
.LOC ( "SLICE_X27Y30" ))
\baud1/timer<4>/DXMUX (
.I(\baud1/timer_mux0000 [3]),
.O(\baud1/timer<4>/DXMUX_1357 )
);
X_BUF #(
.LOC ( "SLICE_X27Y30" ))
\baud1/timer<4>/YUSED (
.I(\baud1/baud_cmp_eq0000893_1347 ),
.O(\baud1/baud_cmp_eq0000893_0 )
);
X_BUF #(
.LOC ( "SLICE_X27Y30" ))
\baud1/timer<4>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<4>/CLKINV_1341 )
);
X_BUF #(
.LOC ( "SLICE_X27Y32" ))
\baud1/timer<3>/DXMUX (
.I(\baud1/timer_mux0000 [4]),
.O(\baud1/timer<3>/DXMUX_1425 )
);
X_BUF #(
.LOC ( "SLICE_X27Y32" ))
\baud1/timer<3>/YUSED (
.I(N28),
.O(N28_0)
);
X_BUF #(
.LOC ( "SLICE_X27Y32" ))
\baud1/timer<3>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<3>/CLKINV_1407 )
);
X_BUF #(
.LOC ( "SLICE_X13Y23" ))
\fifo1/N23/XUSED (
.I(\fifo1/N23 ),
.O(\fifo1/N23_0 )
);
X_BUF #(
.LOC ( "SLICE_X13Y23" ))
\fifo1/N23/YUSED (
.I(\fifo1/N9 ),
.O(\fifo1/N9_0 )
);
X_LUT4 #(
.INIT ( 16'h5151 ),
.LOC ( "SLICE_X19Y29" ))
\Mcount_bitcounter_xor<0>11 (
.ADR0(bitcounter[0]),
.ADR1(pstate[2]),
.ADR2(N16),
.ADR3(VCC),
.O(Mcount_bitcounter)
);
X_BUF #(
.LOC ( "SLICE_X12Y25" ))
\fifo1/N5/XUSED (
.I(\fifo1/N5 ),
.O(\fifo1/N5_0 )
);
X_BUF #(
.LOC ( "SLICE_X12Y25" ))
\fifo1/N5/YUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_pack_1 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\bitcounter<1>/DXMUX (
.I(Mcount_bitcounter1),
.O(\bitcounter<1>/DXMUX_1462 )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\bitcounter<1>/YUSED (
.I(N10_pack_2),
.O(N10)
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\bitcounter<1>/CLKINV (
.I(clk_BUFGP),
.O(\bitcounter<1>/CLKINV_1444 )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\bitcounter<1>/CEINV (
.I(bitcounter_not0001_0),
.O(\bitcounter<1>/CEINV_1443 )
);
X_BUF #(
.LOC ( "PAD53" ))
\addr<2>/IFF/IMUX (
.I(\addr<2>/INBUF ),
.O(addr_2_IBUF_1045)
);
X_BUF #(
.LOC ( "SLICE_X18Y25" ))
\pstate<4>/DXMUX (
.I(pstate_mux0000[1]),
.O(\pstate<4>/DXMUX_1508 )
);
X_BUF #(
.LOC ( "SLICE_X18Y25" ))
\pstate<4>/DYMUX (
.I(control[2]),
.O(\pstate<4>/DYMUX_1492 )
);
X_BUF #(
.LOC ( "SLICE_X18Y25" ))
\pstate<4>/YUSED (
.I(bitcounter_not0001),
.O(bitcounter_not0001_0)
);
X_BUF #(
.LOC ( "SLICE_X18Y25" ))
\pstate<4>/SRINV (
.I(reset_IBUF_963),
.O(\pstate<4>/SRINV_1481 )
);
X_BUF #(
.LOC ( "SLICE_X18Y25" ))
\pstate<4>/CLKINV (
.I(clk_BUFGP),
.O(\pstate<4>/CLKINV_1480 )
);
X_FF #(
.LOC ( "SLICE_X18Y26" ),
.INIT ( 1'b0 ))
bitcounter_3 (
.I(\bitcounter<3>/DXMUX_1764 ),
.CE(\bitcounter<3>/CEINV_1746 ),
.CLK(\bitcounter<3>/CLKINV_1747 ),
.SET(GND),
.RST(\bitcounter<3>/FFX/RSTAND_1770 ),
.O(bitcounter[3])
);
X_BUF #(
.LOC ( "SLICE_X18Y26" ))
\bitcounter<3>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\bitcounter<3>/FFX/RSTAND_1770 )
);
X_BUF #(
.LOC ( "SLICE_X20Y25" ))
\control<2>/DYMUX (
.I(control[0]),
.O(\control<2>/DYMUX_1321 )
);
X_BUF #(
.LOC ( "SLICE_X20Y25" ))
\control<2>/CLKINV (
.I(clk_BUFGP),
.O(\control<2>/CLKINV_1318 )
);
X_BUF #(
.LOC ( "SLICE_X20Y25" ))
\control<2>/CEINV (
.I(control_2_not0001),
.O(\control<2>/CEINV_1317 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/DXMUX_1392 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/YUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/SRINV (
.I(pstate[0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/SRINV_1376 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/CLKINV_1375 )
);
X_FF #(
.LOC ( "SLICE_X19Y22" ),
.INIT ( 1'b0 ))
frame_error_6 (
.I(\frame_error<7>/DYMUX_3731 ),
.CE(\frame_error<7>/CEINV_3727 ),
.CLK(\frame_error<7>/CLKINV_3728 ),
.SET(GND),
.RST(\frame_error<7>/SRINV_3729 ),
.O(frame_error[6])
);
X_FF #(
.LOC ( "SLICE_X17Y22" ),
.INIT ( 1'b1 ))
shift_0 (
.I(\shift<1>/DYMUX_3795 ),
.CE(\shift<1>/CEINV_3791 ),
.CLK(\shift<1>/CLKINV_3792 ),
.SET(\shift<1>/SRINV_3793 ),
.RST(GND),
.O(shift[0])
);
X_INV #(
.LOC ( "SLICE_X19Y31" ))
\baud1/baud/DYMUX (
.I(\baud1/baud_1023 ),
.O(\baud1/baud/DYMUX_3360 )
);
X_BUF #(
.LOC ( "SLICE_X19Y31" ))
\baud1/baud/CLKINV (
.I(clk_BUFGP),
.O(\baud1/baud/CLKINV_3357 )
);
X_BUF #(
.LOC ( "SLICE_X19Y31" ))
\baud1/baud/CEINV (
.I(\baud1/baud_cmp_eq0000_0 ),
.O(\baud1/baud/CEINV_3356 )
);
X_BUF #(
.LOC ( "SLICE_X28Y30" ))
\baud1/period<5>/DXMUX (
.I(\din<5>/INBUF ),
.O(\baud1/period<5>/DXMUX_3252 )
);
X_BUF #(
.LOC ( "SLICE_X28Y30" ))
\baud1/period<5>/DYMUX (
.I(\din<4>/INBUF ),
.O(\baud1/period<5>/DYMUX_3244 )
);
X_BUF #(
.LOC ( "SLICE_X28Y30" ))
\baud1/period<5>/SRINV (
.I(reset_IBUF_963),
.O(\baud1/period<5>/SRINV_3242 )
);
X_BUF #(
.LOC ( "SLICE_X28Y30" ))
\baud1/period<5>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/period<5>/CLKINV_3241 )
);
X_BUF #(
.LOC ( "SLICE_X28Y30" ))
\baud1/period<5>/CEINV (
.I(wr_baud_0),
.O(\baud1/period<5>/CEINV_3240 )
);
X_BUF #(
.LOC ( "SLICE_X20Y26" ))
\bittimer<3>/DXMUX (
.I(Result[3]),
.O(\bittimer<3>/DXMUX_3123 )
);
X_BUF #(
.LOC ( "SLICE_X20Y26" ))
\bittimer<3>/DYMUX (
.I(Result[2]),
.O(\bittimer<3>/DYMUX_3108 )
);
X_BUF #(
.LOC ( "SLICE_X20Y26" ))
\bittimer<3>/SRINV (
.I(reset_IBUF_963),
.O(\bittimer<3>/SRINV_3099 )
);
X_BUF #(
.LOC ( "SLICE_X20Y26" ))
\bittimer<3>/CLKINV (
.I(\baud1/baud_1023 ),
.O(\bittimer<3>/CLKINV_3098 )
);
X_BUF #(
.LOC ( "SLICE_X20Y26" ))
\bittimer<3>/CEINV (
.I(bittime_0),
.O(\bittimer<3>/CEINV_3097 )
);
X_BUF #(
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en/XUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en_0 )
);
X_BUF #(
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en/YUSED (
.I(\fifo1/N7 ),
.O(\fifo1/N7_0 )
);
X_SFF #(
.LOC ( "SLICE_X15Y26" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 (
.I(\dout_fifo<7>/DXMUX_3778 ),
.CE(\dout_fifo<7>/CEINV_3767 ),
.CLK(\dout_fifo<7>/CLKINV_3768 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\dout_fifo<7>/SRINV_3769 ),
.O(dout_fifo[7])
);
X_LUT4 #(
.INIT ( 16'h9009 ),
.LOC ( "SLICE_X26Y28" ))
\baud1/baud_cmp_eq0000826 (
.ADR0(\baud1/period [0]),
.ADR1(\baud1/timer [0]),
.ADR2(\baud1/period [1]),
.ADR3(\baud1/timer [1]),
.O(\baud1/baud_cmp_eq0000826_3757 )
);
X_BUF #(
.LOC ( "SLICE_X28Y29" ))
\baud1/period<1>/DXMUX (
.I(\din<1>/INBUF ),
.O(\baud1/period<1>/DXMUX_3199 )
);
X_BUF #(
.LOC ( "SLICE_X28Y29" ))
\baud1/period<1>/DYMUX (
.I(din_0_IBUF_978),
.O(\baud1/period<1>/DYMUX_3190 )
);
X_BUF #(
.LOC ( "SLICE_X28Y29" ))
\baud1/period<1>/SRINV (
.I(reset_IBUF_963),
.O(\baud1/period<1>/SRINV_3188 )
);
X_BUF #(
.LOC ( "SLICE_X28Y29" ))
\baud1/period<1>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/period<1>/CLKINV_3187 )
);
X_BUF #(
.LOC ( "SLICE_X28Y29" ))
\baud1/period<1>/CEINV (
.I(wr_baud_0),
.O(\baud1/period<1>/CEINV_3186 )
);
X_BUF #(
.LOC ( "SLICE_X29Y28" ))
\baud1/period<3>/DXMUX (
.I(\din<3>/INBUF ),
.O(\baud1/period<3>/DXMUX_3226 )
);
X_BUF #(
.LOC ( "SLICE_X29Y28" ))
\baud1/period<3>/DYMUX (
.I(\din<2>/INBUF ),
.O(\baud1/period<3>/DYMUX_3217 )
);
X_BUF #(
.LOC ( "SLICE_X29Y28" ))
\baud1/period<3>/SRINV (
.I(reset_IBUF_963),
.O(\baud1/period<3>/SRINV_3215 )
);
X_BUF #(
.LOC ( "SLICE_X29Y28" ))
\baud1/period<3>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/period<3>/CLKINV_3214 )
);
X_BUF #(
.LOC ( "SLICE_X29Y28" ))
\baud1/period<3>/CEINV (
.I(wr_baud_0),
.O(\baud1/period<3>/CEINV_3213 )
);
X_BUF #(
.LOC ( "SLICE_X16Y29" ))
\loaded/DXMUX (
.I(\loaded/FXMUX_3342 ),
.O(\loaded/DXMUX_3343 )
);
X_BUF #(
.LOC ( "SLICE_X16Y29" ))
\loaded/XUSED (
.I(\loaded/FXMUX_3342 ),
.O(loaded_mux0000_0)
);
X_BUF #(
.LOC ( "SLICE_X16Y29" ))
\loaded/FXMUX (
.I(loaded_mux0000_3340),
.O(\loaded/FXMUX_3342 )
);
X_BUF #(
.LOC ( "SLICE_X16Y29" ))
\loaded/YUSED (
.I(N22_pack_1),
.O(N22)
);
X_INV #(
.LOC ( "SLICE_X16Y29" ))
\loaded/CLKINV (
.I(clk_BUFGP),
.O(\loaded/CLKINVNOT )
);
X_BUF #(
.LOC ( "SLICE_X16Y29" ))
\loaded/CEINV (
.I(loaded_not0001),
.O(\loaded/CEINV_3325 )
);
X_BUF #(
.LOC ( "SLICE_X20Y24" ))
\control<1>/DXMUX (
.I(control_1_mux0000),
.O(\control<1>/DXMUX_3026 )
);
X_BUF #(
.LOC ( "SLICE_X20Y24" ))
\control<1>/DYMUX (
.I(pstate_mux0000[5]),
.O(\control<1>/DYMUX_3011 )
);
X_BUF #(
.LOC ( "SLICE_X20Y24" ))
\control<1>/SRINV (
.I(reset_IBUF_963),
.O(\control<1>/SRINV_3003 )
);
X_BUF #(
.LOC ( "SLICE_X20Y24" ))
\control<1>/CLKINV (
.I(clk_BUFGP),
.O(\control<1>/CLKINV_3002 )
);
X_BUF #(
.LOC ( "SLICE_X18Y24" ))
\bitcounter<2>/DYMUX (
.I(Mcount_bitcounter2),
.O(\bitcounter<2>/DYMUX_3077 )
);
X_BUF #(
.LOC ( "SLICE_X18Y24" ))
\bitcounter<2>/CLKINV (
.I(clk_BUFGP),
.O(\bitcounter<2>/CLKINV_3067 )
);
X_BUF #(
.LOC ( "SLICE_X18Y24" ))
\bitcounter<2>/CEINV (
.I(bitcounter_not0001_0),
.O(\bitcounter<2>/CEINV_3066 )
);
X_BUF #(
.LOC ( "SLICE_X13Y24" ))
\fifo1/N21/XUSED (
.I(\fifo1/N21 ),
.O(\fifo1/N21_0 )
);
X_BUF #(
.LOC ( "SLICE_X15Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en/XUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 )
);
X_BUF #(
.LOC ( "SLICE_X15Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en/YUSED (
.I(rd_fifo_pack_1),
.O(rd_fifo)
);
X_BUF #(
.LOC ( "SLICE_X17Y23" ))
\frame_error<8>/DYMUX (
.I(frame_error_8_or0000),
.O(\frame_error<8>/DYMUX_3051 )
);
X_BUF #(
.LOC ( "SLICE_X17Y23" ))
\frame_error<8>/CLKINV (
.I(clk_BUFGP),
.O(\frame_error<8>/CLKINV_3040 )
);
X_BUF #(
.LOC ( "SLICE_X17Y23" ))
\frame_error<8>/CEINV (
.I(finish_0),
.O(\frame_error<8>/CEINV_3039 )
);
X_FF #(
.LOC ( "SLICE_X19Y22" ),
.INIT ( 1'b0 ))
frame_error_7 (
.I(\frame_error<7>/DXMUX_3740 ),
.CE(\frame_error<7>/CEINV_3727 ),
.CLK(\frame_error<7>/CLKINV_3728 ),
.SET(GND),
.RST(\frame_error<7>/SRINV_3729 ),
.O(frame_error[7])
);
X_BUF #(
.LOC ( "SLICE_X29Y31" ))
\baud1/period<7>/DXMUX (
.I(\din<7>/INBUF ),
.O(\baud1/period<7>/DXMUX_3304 )
);
X_BUF #(
.LOC ( "SLICE_X29Y31" ))
\baud1/period<7>/DYMUX (
.I(\din<6>/INBUF ),
.O(\baud1/period<7>/DYMUX_3295 )
);
X_BUF #(
.LOC ( "SLICE_X29Y31" ))
\baud1/period<7>/SRINV (
.I(reset_IBUF_963),
.O(\baud1/period<7>/SRINV_3293 )
);
X_BUF #(
.LOC ( "SLICE_X29Y31" ))
\baud1/period<7>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/period<7>/CLKINV_3292 )
);
X_BUF #(
.LOC ( "SLICE_X29Y31" ))
\baud1/period<7>/CEINV (
.I(wr_baud_0),
.O(\baud1/period<7>/CEINV_3291 )
);
X_FF #(
.LOC ( "SLICE_X17Y22" ),
.INIT ( 1'b1 ))
shift_1 (
.I(\shift<1>/DXMUX_3803 ),
.CE(\shift<1>/CEINV_3791 ),
.CLK(\shift<1>/CLKINV_3792 ),
.SET(\shift<1>/SRINV_3793 ),
.RST(GND),
.O(shift[1])
);
X_SFF #(
.LOC ( "SLICE_X15Y26" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 (
.I(\dout_fifo<7>/DYMUX_3771 ),
.CE(\dout_fifo<7>/CEINV_3767 ),
.CLK(\dout_fifo<7>/CLKINV_3768 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\dout_fifo<7>/SRINV_3769 ),
.O(dout_fifo[6])
);
X_BUF #(
.LOC ( "SLICE_X16Y28" ))
\loaded_not0001/YUSED (
.I(N24_pack_1),
.O(N24)
);
X_BUF #(
.LOC ( "SLICE_X28Y23" ))
\wr_baud/XUSED (
.I(wr_baud),
.O(wr_baud_0)
);
X_BUF #(
.LOC ( "SLICE_X12Y20" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/DXMUX (
.I(\fifo1/Result [1]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/DXMUX_3407 )
);
X_INV #(
.LOC ( "SLICE_X12Y20" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/DYMUX_3392 )
);
X_BUF #(
.LOC ( "SLICE_X12Y20" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/YUSED (
.I(\fifo1/N17 ),
.O(\fifo1/N17_0 )
);
X_BUF #(
.LOC ( "SLICE_X12Y20" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/SRINV (
.I(pstate[0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/SRINV_3381 )
);
X_BUF #(
.LOC ( "SLICE_X12Y20" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/CLKINV_3380 )
);
X_BUF #(
.LOC ( "SLICE_X12Y20" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/CEINV_3379 )
);
X_BUF #(
.LOC ( "SLICE_X14Y23" ))
\frame_error<1>/FFX/RSTOR (
.I(\frame_error<1>/SRINV_3530 ),
.O(\frame_error<1>/FFX/RST )
);
X_FF #(
.LOC ( "SLICE_X14Y23" ),
.INIT ( 1'b0 ))
frame_error_1 (
.I(\frame_error<1>/DXMUX_3541 ),
.CE(\frame_error<1>/CEINV_3528 ),
.CLK(\frame_error<1>/CLKINV_3529 ),
.SET(GND),
.RST(\frame_error<1>/FFX/RST ),
.O(frame_error[1])
);
X_BUF #(
.LOC ( "SLICE_X14Y23" ))
\frame_error<1>/FFY/RSTOR (
.I(\frame_error<1>/SRINV_3530 ),
.O(\frame_error<1>/FFY/RST )
);
X_FF #(
.LOC ( "SLICE_X14Y23" ),
.INIT ( 1'b0 ))
frame_error_0 (
.I(\frame_error<1>/DYMUX_3532 ),
.CE(\frame_error<1>/CEINV_3528 ),
.CLK(\frame_error<1>/CLKINV_3529 ),
.SET(GND),
.RST(\frame_error<1>/FFY/RST ),
.O(frame_error[0])
);
X_BUF #(
.LOC ( "SLICE_X14Y23" ))
\frame_error<1>/DXMUX (
.I(shift[2]),
.O(\frame_error<1>/DXMUX_3541 )
);
X_BUF #(
.LOC ( "SLICE_X14Y23" ))
\frame_error<1>/DYMUX (
.I(shift[1]),
.O(\frame_error<1>/DYMUX_3532 )
);
X_BUF #(
.LOC ( "SLICE_X14Y23" ))
\frame_error<1>/SRINV (
.I(reset_IBUF_963),
.O(\frame_error<1>/SRINV_3530 )
);
X_BUF #(
.LOC ( "SLICE_X14Y23" ))
\frame_error<1>/CLKINV (
.I(clk_BUFGP),
.O(\frame_error<1>/CLKINV_3529 )
);
X_BUF #(
.LOC ( "SLICE_X14Y23" ))
\frame_error<1>/CEINV (
.I(finish_0),
.O(\frame_error<1>/CEINV_3528 )
);
X_LUT4 #(
.INIT ( 16'h80C4 ),
.LOC ( "SLICE_X24Y27" ))
\dout<2>41 (
.ADR0(addr_0_IBUF_1064),
.ADR1(addr_2_IBUF_1045),
.ADR2(\dout<2>10_1140 ),
.ADR3(N47),
.O(dout_2_OBUF_3518)
);
X_BUF #(
.LOC ( "SLICE_X24Y27" ))
\dout_2_OBUF/YUSED (
.I(\dout<2>10_pack_1 ),
.O(\dout<2>10_1140 )
);
X_BUF #(
.LOC ( "SLICE_X28Y31" ))
\baud1/baud_cmp_eq00008120/XUSED (
.I(\baud1/baud_cmp_eq00008120_3494 ),
.O(\baud1/baud_cmp_eq00008120_0 )
);
X_SFF #(
.LOC ( "SLICE_X12Y26" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_3 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX_1213 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_1202 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_1203 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_1204 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3])
);
X_FF #(
.LOC ( "SLICE_X26Y24" ),
.INIT ( 1'b0 ))
control_0 (
.I(\control<0>/DYMUX_1254 ),
.CE(\control<0>/CEINV_1250 ),
.CLK(\control<0>/CLKINV_1251 ),
.SET(GND),
.RST(\control<0>/FFY/RSTAND_1260 ),
.O(control[0])
);
X_BUF #(
.LOC ( "SLICE_X26Y24" ))
\control<0>/FFY/RSTAND (
.I(reset_IBUF_963),
.O(\control<0>/FFY/RSTAND_1260 )
);
X_LUT4 #(
.INIT ( 16'h8241 ),
.LOC ( "SLICE_X13Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00005_SW0_SW0 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.O(\fifo1/N23 )
);
X_SFF #(
.LOC ( "SLICE_X13Y25" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_3 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DXMUX_1189 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CEINV_1178 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CLKINV_1179 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/SRINV_1180 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3])
);
X_FF #(
.LOC ( "SLICE_X17Y29" ),
.INIT ( 1'b1 ))
shift_5 (
.I(\shift<5>/DXMUX_1164 ),
.CE(\shift<5>/CEINV_1152 ),
.CLK(\shift<5>/CLKINV_1153 ),
.SET(\shift<5>/SRINV_1154 ),
.RST(GND),
.O(shift[5])
);
X_SFF #(
.LOC ( "SLICE_X13Y25" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DYMUX_1182 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CEINV_1178 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CLKINV_1179 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/SRINV_1180 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2])
);
X_FF #(
.LOC ( "SLICE_X17Y29" ),
.INIT ( 1'b1 ))
shift_4 (
.I(\shift<5>/DYMUX_1156 ),
.CE(\shift<5>/CEINV_1152 ),
.CLK(\shift<5>/CLKINV_1153 ),
.SET(\shift<5>/SRINV_1154 ),
.RST(GND),
.O(shift[4])
);
X_SFF #(
.LOC ( "SLICE_X12Y26" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX_1206 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_1202 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_1203 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_1204 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2])
);
X_FF #(
.LOC ( "SLICE_X16Y23" ),
.INIT ( 1'b1 ))
shift_7 (
.I(\shift<7>/DXMUX_1238 ),
.CE(\shift<7>/CEINV_1226 ),
.CLK(\shift<7>/CLKINV_1227 ),
.SET(\shift<7>/SRINV_1228 ),
.RST(GND),
.O(shift[7])
);
X_FF #(
.LOC ( "SLICE_X16Y23" ),
.INIT ( 1'b1 ))
shift_6 (
.I(\shift<7>/DYMUX_1230 ),
.CE(\shift<7>/CEINV_1226 ),
.CLK(\shift<7>/CLKINV_1227 ),
.SET(\shift<7>/SRINV_1228 ),
.RST(GND),
.O(shift[6])
);
X_LUT4 #(
.INIT ( 16'h0CFC ),
.LOC ( "SLICE_X18Y26" ))
\Mcount_bitcounter_xor<3>1 (
.ADR0(VCC),
.ADR1(bitcounter[3]),
.ADR2(bitcounter[1]),
.ADR3(N14),
.O(Mcount_bitcounter3)
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X13Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168_SW1 (
.ADR0(VCC),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.ADR3(VCC),
.O(\fifo1/N9 )
);
X_LUT4 #(
.INIT ( 16'h0012 ),
.LOC ( "SLICE_X27Y30" ))
\baud1/timer_mux0000<3>1 (
.ADR0(\baud1/Madd_timer_addsub0000_cy[3] ),
.ADR1(\baud1/baud_cmp_eq0000_0 ),
.ADR2(\baud1/timer [4]),
.ADR3(N30),
.O(\baud1/timer_mux0000 [3])
);
X_LUT4 #(
.INIT ( 16'h88AA ),
.LOC ( "SLICE_X17Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/RAM_REGOUT_EN1 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_996 ),
.ADR1(rd_fifo),
.ADR2(VCC),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_998 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en )
);
X_FF #(
.LOC ( "SLICE_X16Y22" ),
.INIT ( 1'b1 ))
shift_9 (
.I(\shift<9>/DXMUX_1305 ),
.CE(\shift<9>/CEINV_1293 ),
.CLK(\shift<9>/CLKINV_1294 ),
.SET(\shift<9>/SRINV_1295 ),
.RST(GND),
.O(shift[9])
);
X_LUT4 #(
.INIT ( 16'h2F0F ),
.LOC ( "SLICE_X17Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_996 ),
.ADR1(rd_fifo),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_995 ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_998 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In )
);
X_LUT4 #(
.INIT ( 16'hA0A0 ),
.LOC ( "SLICE_X27Y32" ))
\baud1/timer_mux0000<0>11_SW1 (
.ADR0(rxin_IBUF_1000),
.ADR1(VCC),
.ADR2(pstate[1]),
.ADR3(VCC),
.O(N28)
);
X_FF #(
.LOC ( "SLICE_X20Y25" ),
.INIT ( 1'b0 ))
control_2 (
.I(\control<2>/DYMUX_1321 ),
.CE(\control<2>/CEINV_1317 ),
.CLK(\control<2>/CLKINV_1318 ),
.SET(GND),
.RST(\control<2>/FFY/RSTAND_1327 ),
.O(control[2])
);
X_BUF #(
.LOC ( "SLICE_X20Y25" ))
\control<2>/FFY/RSTAND (
.I(reset_IBUF_963),
.O(\control<2>/FFY/RSTAND_1327 )
);
X_SFF #(
.LOC ( "SLICE_X17Y25" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/DXMUX_1392 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/CLKINV_1375 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1/SRINV_1376 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_996 )
);
X_FF #(
.LOC ( "SLICE_X27Y32" ),
.INIT ( 1'b0 ))
\baud1/timer_3 (
.I(\baud1/timer<3>/DXMUX_1425 ),
.CE(VCC),
.CLK(\baud1/timer<3>/CLKINV_1407 ),
.SET(GND),
.RST(\baud1/timer<3>/FFX/RSTAND_1430 ),
.O(\baud1/timer [3])
);
X_BUF #(
.LOC ( "SLICE_X27Y32" ))
\baud1/timer<3>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\baud1/timer<3>/FFX/RSTAND_1430 )
);
X_LUT4 #(
.INIT ( 16'h0013 ),
.LOC ( "SLICE_X27Y32" ))
\baud1/timer_mux0000<4> (
.ADR0(rxin_IBUF_1000),
.ADR1(\baud1/baud_cmp_eq0000_0 ),
.ADR2(pstate[1]),
.ADR3(N26_0),
.O(\baud1/timer_mux0000 [4])
);
X_FF #(
.LOC ( "SLICE_X27Y30" ),
.INIT ( 1'b0 ))
\baud1/timer_4 (
.I(\baud1/timer<4>/DXMUX_1357 ),
.CE(VCC),
.CLK(\baud1/timer<4>/CLKINV_1341 ),
.SET(GND),
.RST(\baud1/timer<4>/FFX/RSTAND_1362 ),
.O(\baud1/timer [4])
);
X_BUF #(
.LOC ( "SLICE_X27Y30" ))
\baud1/timer<4>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\baud1/timer<4>/FFX/RSTAND_1362 )
);
X_LUT4 #(
.INIT ( 16'h9009 ),
.LOC ( "SLICE_X27Y30" ))
\baud1/baud_cmp_eq0000893 (
.ADR0(\baud1/timer [5]),
.ADR1(\baud1/period [5]),
.ADR2(\baud1/period [4]),
.ADR3(\baud1/timer [4]),
.O(\baud1/baud_cmp_eq0000893_1347 )
);
X_FF #(
.LOC ( "SLICE_X16Y22" ),
.INIT ( 1'b1 ))
shift_8 (
.I(\shift<9>/DYMUX_1297 ),
.CE(\shift<9>/CEINV_1293 ),
.CLK(\shift<9>/CLKINV_1294 ),
.SET(\shift<9>/SRINV_1295 ),
.RST(GND),
.O(shift[8])
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X21Y26" ))
\Mcount_bittimer_xor<1>11 (
.ADR0(VCC),
.ADR1(bittimer[1]),
.ADR2(VCC),
.ADR3(bittimer[0]),
.O(Result[1])
);
X_LUT4 #(
.INIT ( 16'h00F0 ),
.LOC ( "SLICE_X18Y25" ))
\pstate_mux0000<1>1 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(finish_0),
.ADR3(control[2]),
.O(pstate_mux0000[1])
);
X_LUT4 #(
.INIT ( 16'h00CC ),
.LOC ( "SLICE_X12Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 (
.ADR0(VCC),
.ADR1(pstate[4]),
.ADR2(VCC),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1019 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h0804 ),
.LOC ( "SLICE_X12Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000073_SW0 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_0 ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\fifo1/N5 )
);
X_LUT4 #(
.INIT ( 16'h525A ),
.LOC ( "SLICE_X19Y25" ))
\Mcount_bitcounter_xor<1>1 (
.ADR0(bitcounter[1]),
.ADR1(bitcounter[3]),
.ADR2(bitcounter[0]),
.ADR3(N10),
.O(Mcount_bitcounter1)
);
X_FF #(
.LOC ( "SLICE_X18Y25" ),
.INIT ( 1'b0 ))
pstate_4 (
.I(\pstate<4>/DXMUX_1508 ),
.CE(VCC),
.CLK(\pstate<4>/CLKINV_1480 ),
.SET(GND),
.RST(\pstate<4>/SRINV_1481 ),
.O(pstate[4])
);
X_LUT4 #(
.INIT ( 16'hF5F5 ),
.LOC ( "SLICE_X18Y25" ))
bitcounter_not00012 (
.ADR0(loaded_mux0000_0),
.ADR1(VCC),
.ADR2(finish_0),
.ADR3(VCC),
.O(bitcounter_not0001)
);
X_FF #(
.LOC ( "SLICE_X18Y25" ),
.INIT ( 1'b0 ))
pstate_5 (
.I(\pstate<4>/DYMUX_1492 ),
.CE(VCC),
.CLK(\pstate<4>/CLKINV_1480 ),
.SET(GND),
.RST(\pstate<4>/SRINV_1481 ),
.O(pstate[5])
);
X_FF #(
.LOC ( "SLICE_X21Y26" ),
.INIT ( 1'b0 ))
bittimer_1 (
.I(\bittimer<0>/DYMUX_1559 ),
.CE(\bittimer<0>/CEINV_1547 ),
.CLK(\bittimer<0>/CLKINV_1548 ),
.SET(GND),
.RST(\bittimer<0>/SRINV_1549 ),
.O(bittimer[1])
);
X_FF #(
.LOC ( "SLICE_X21Y26" ),
.INIT ( 1'b0 ))
bittimer_0 (
.I(\bittimer<0>/DXMUX_1568 ),
.CE(\bittimer<0>/CEINV_1547 ),
.CLK(\bittimer<0>/CLKINV_1548 ),
.SET(GND),
.RST(\bittimer<0>/SRINV_1549 ),
.O(bittimer[0])
);
X_LUT4 #(
.INIT ( 16'h00F0 ),
.LOC ( "SLICE_X19Y25" ))
\Mcount_bitcounter_xor<1>1_SW0 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(pstate[2]),
.ADR3(bitcounter[2]),
.O(N10_pack_2)
);
X_FF #(
.LOC ( "SLICE_X19Y25" ),
.INIT ( 1'b0 ))
bitcounter_1 (
.I(\bitcounter<1>/DXMUX_1462 ),
.CE(\bitcounter<1>/CEINV_1443 ),
.CLK(\bitcounter<1>/CLKINV_1444 ),
.SET(GND),
.RST(\bitcounter<1>/FFX/RSTAND_1468 ),
.O(bitcounter[1])
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\bitcounter<1>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\bitcounter<1>/FFX/RSTAND_1468 )
);
X_FF #(
.LOC ( "SLICE_X16Y24" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i (
.I(\full/DYMUX_1581 ),
.CE(VCC),
.CLK(\full/CLKINV_1579 ),
.SET(GND),
.RST(GND),
.O(full)
);
X_LUT4 #(
.INIT ( 16'hFFFE ),
.LOC ( "SLICE_X17Y26" ))
\pstate_mux0000<2>4 (
.ADR0(bittimer[1]),
.ADR1(bittimer[3]),
.ADR2(bittimer[2]),
.ADR3(bittimer[0]),
.O(\pstate_mux0000<2>4_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h8421 ),
.LOC ( "SLICE_X13Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_1701 )
);
X_FF #(
.LOC ( "SLICE_X16Y27" ),
.INIT ( 1'b0 ))
load (
.I(\load/DXMUX_1614 ),
.CE(VCC),
.CLK(\load/CLKINV_1597 ),
.SET(GND),
.RST(\load/FFX/RSTAND_1619 ),
.O(load_1032)
);
X_BUF #(
.LOC ( "SLICE_X16Y27" ))
\load/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\load/FFX/RSTAND_1619 )
);
X_LUT4 #(
.INIT ( 16'hFC00 ),
.LOC ( "SLICE_X17Y26" ))
\pstate_mux0000<2>10 (
.ADR0(VCC),
.ADR1(\baud1/baud_1023 ),
.ADR2(\pstate_mux0000<2>4_1033 ),
.ADR3(pstate[3]),
.O(\pstate_mux0000<2>10_1642 )
);
X_LUT4 #(
.INIT ( 16'h3323 ),
.LOC ( "SLICE_X18Y28" ))
\pstate_mux0000<3>30 (
.ADR0(\pstate_mux0000<3>15_0 ),
.ADR1(control[2]),
.ADR2(loaded_mux0000_0),
.ADR3(\pstate_mux0000<3>2_1036 ),
.O(pstate_mux0000[3])
);
X_FF #(
.LOC ( "SLICE_X18Y22" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i (
.I(\empty/DYMUX_1730 ),
.CE(VCC),
.CLK(\empty/CLKINV_1728 ),
.SET(GND),
.RST(GND),
.O(empty)
);
X_LUT4 #(
.INIT ( 16'h3030 ),
.LOC ( "SLICE_X18Y28" ))
\pstate_mux0000<3>2 (
.ADR0(VCC),
.ADR1(rxin_IBUF_1000),
.ADR2(pstate[1]),
.ADR3(VCC),
.O(\pstate_mux0000<3>2_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h9787 ),
.LOC ( "SLICE_X18Y26" ))
\Mcount_bitcounter_xor<3>1_SW0 (
.ADR0(bitcounter[2]),
.ADR1(bitcounter[0]),
.ADR2(bitcounter[3]),
.ADR3(pstate[2]),
.O(N14_pack_3)
);
X_LUT4 #(
.INIT ( 16'h0002 ),
.LOC ( "SLICE_X16Y27" ))
ld_shift (
.ADR0(pstate[3]),
.ADR1(bittimer[2]),
.ADR2(N20),
.ADR3(loaded_1030),
.O(ld_shift_1611)
);
X_FF #(
.LOC ( "SLICE_X18Y28" ),
.INIT ( 1'b0 ))
pstate_2 (
.I(\pstate<2>/DXMUX_1673 ),
.CE(VCC),
.CLK(\pstate<2>/CLKINV_1655 ),
.SET(GND),
.RST(\pstate<2>/FFX/RSTAND_1678 ),
.O(pstate[2])
);
X_BUF #(
.LOC ( "SLICE_X18Y28" ))
\pstate<2>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\pstate<2>/FFX/RSTAND_1678 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<1>11 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.ADR2(VCC),
.ADR3(VCC),
.O(\fifo1/Result<1>1 )
);
X_SFF #(
.LOC ( "SLICE_X13Y26" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_1 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/DXMUX_1719 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/CEINV_1693 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/CLKINV_1694 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/SRINV_1695 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1])
);
X_LUT4 #(
.INIT ( 16'hFFF3 ),
.LOC ( "SLICE_X16Y27" ))
ld_shift_SW0 (
.ADR0(VCC),
.ADR1(bittimer[3]),
.ADR2(bittimer[0]),
.ADR3(bittimer[1]),
.O(N20_pack_1)
);
X_SFF #(
.LOC ( "SLICE_X13Y26" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_0 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/DYMUX_1704 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/CEINV_1693 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/CLKINV_1694 ),
.SET(GND),
.RST(GND),
.SSET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<1>/SRINV_1695 ),
.SRST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0])
);
X_SFF #(
.LOC ( "SLICE_X12Y20" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_1 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/DXMUX_3407 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/CEINV_3379 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/CLKINV_3380 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/SRINV_3381 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1])
);
X_FF #(
.LOC ( "SLICE_X19Y31" ),
.INIT ( 1'b0 ))
\baud1/baud (
.I(\baud1/baud/DYMUX_3360 ),
.CE(\baud1/baud/CEINV_3356 ),
.CLK(\baud1/baud/CLKINV_3357 ),
.SET(GND),
.RST(\baud1/baud/FFY/RSTAND_3366 ),
.O(\baud1/baud_1023 )
);
X_BUF #(
.LOC ( "SLICE_X19Y31" ))
\baud1/baud/FFY/RSTAND (
.I(reset_IBUF_963),
.O(\baud1/baud/FFY/RSTAND_3366 )
);
X_LUT4 #(
.INIT ( 16'hFFFD ),
.LOC ( "SLICE_X16Y29" ))
loaded_mux0000 (
.ADR0(pstate[3]),
.ADR1(N22),
.ADR2(\baud1/baud_1023 ),
.ADR3(bittimer[2]),
.O(loaded_mux0000_3340)
);
X_LUT4 #(
.INIT ( 16'h8421 ),
.LOC ( "SLICE_X28Y31" ))
\baud1/baud_cmp_eq00008120 (
.ADR0(\baud1/timer [6]),
.ADR1(\baud1/period [7]),
.ADR2(\baud1/period [6]),
.ADR3(\baud1/timer [7]),
.O(\baud1/baud_cmp_eq00008120_3494 )
);
X_LUT4 #(
.INIT ( 16'h8000 ),
.LOC ( "SLICE_X28Y22" ))
wr_control1 (
.ADR0(addr_1_IBUF_1065),
.ADR1(addr_0_IBUF_1064),
.ADR2(wren_IBUF_1047),
.ADR3(addr_2_IBUF_1045),
.O(wr_control)
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X12Y20" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<1>11 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\fifo1/Result [1])
);
X_LUT4 #(
.INIT ( 16'hCC33 ),
.LOC ( "SLICE_X12Y20" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000029_SW0 (
.ADR0(VCC),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR2(VCC),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.O(\fifo1/N17 )
);
X_LUT4 #(
.INIT ( 16'hFFFC ),
.LOC ( "SLICE_X16Y29" ))
loaded_mux0000_SW0 (
.ADR0(VCC),
.ADR1(bittimer[0]),
.ADR2(bittimer[1]),
.ADR3(bittimer[3]),
.O(N22_pack_1)
);
X_LUT4 #(
.INIT ( 16'h1000 ),
.LOC ( "SLICE_X28Y23" ))
wr_baud1 (
.ADR0(addr_1_IBUF_1065),
.ADR1(addr_0_IBUF_1064),
.ADR2(wren_IBUF_1047),
.ADR3(addr_2_IBUF_1045),
.O(wr_baud)
);
X_SFF #(
.LOC ( "SLICE_X12Y20" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_0 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/DYMUX_3392 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/CEINV_3379 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/CLKINV_3380 ),
.SET(GND),
.RST(GND),
.SSET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<1>/SRINV_3381 ),
.SRST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0])
);
X_LUT4 #(
.INIT ( 16'hC0C0 ),
.LOC ( "SLICE_X28Y22" ))
\dout<0>39 (
.ADR0(VCC),
.ADR1(addr_2_IBUF_1045),
.ADR2(\dout<0>30 ),
.ADR3(VCC),
.O(dout_0_OBUF_3482)
);
X_LUT4 #(
.INIT ( 16'h0001 ),
.LOC ( "SLICE_X16Y28" ))
loaded_mux0000_SW1 (
.ADR0(bittimer[1]),
.ADR1(bittimer[0]),
.ADR2(bittimer[2]),
.ADR3(bittimer[3]),
.O(N24_pack_1)
);
X_FF #(
.LOC ( "SLICE_X16Y29" ),
.INIT ( 1'b0 ))
loaded (
.I(\loaded/DXMUX_3343 ),
.CE(\loaded/CEINV_3325 ),
.CLK(\loaded/CLKINVNOT ),
.SET(GND),
.RST(\loaded/FFX/RSTAND_3349 ),
.O(loaded_1030)
);
X_BUF #(
.LOC ( "SLICE_X16Y29" ))
\loaded/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\loaded/FFX/RSTAND_3349 )
);
X_LUT4 #(
.INIT ( 16'hCECC ),
.LOC ( "SLICE_X16Y28" ))
loaded_not00011 (
.ADR0(pstate[3]),
.ADR1(load_1032),
.ADR2(\baud1/baud_1023 ),
.ADR3(N24),
.O(loaded_not0001)
);
X_LUT4 #(
.INIT ( 16'h4000 ),
.LOC ( "SLICE_X28Y23" ))
\dout<8>1 (
.ADR0(addr_1_IBUF_1065),
.ADR1(addr_2_IBUF_1045),
.ADR2(addr_0_IBUF_1064),
.ADR3(dout_fifo[8]),
.O(dout_8_OBUF_3451)
);
X_BUF #(
.LOC ( "PAD25" ))
\rxin/IFF/IMUX (
.I(\rxin/INBUF ),
.O(rxin_IBUF_1000)
);
X_BUF #(
.LOC ( "IPAD36" ))
\din<0>/IFF/IMUX (
.I(\din<0>/INBUF ),
.O(din_0_IBUF_978)
);
X_BUF #(
.LOC ( "PAD51" ))
\reset/IFF/IMUX (
.I(\reset/INBUF ),
.O(reset_IBUF_963)
);
X_BUF #(
.LOC ( "PAD52" ))
\addr<0>/IFF/IMUX (
.I(\addr<0>/INBUF ),
.O(addr_0_IBUF_1064)
);
X_BUF #(
.LOC ( "PAD48" ))
\addr<1>/IFF/IMUX (
.I(\addr<1>/INBUF ),
.O(addr_1_IBUF_1065)
);
X_FF #(
.LOC ( "SLICE_X17Y24" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DXMUX_2306 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV_2289 ),
.SET(GND),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_1102 )
);
X_LUT4 #(
.INIT ( 16'h0080 ),
.LOC ( "SLICE_X29Y24" ))
\dout<5>2 (
.ADR0(\baud1/period [5]),
.ADR1(rden_IBUF_1051),
.ADR2(addr_2_IBUF_1045),
.ADR3(addr_1_IBUF_1065),
.O(\dout<5>2_2323 )
);
X_LUT4 #(
.INIT ( 16'h4000 ),
.LOC ( "SLICE_X25Y25" ))
\dout<1>30_F (
.ADR0(addr_1_IBUF_1065),
.ADR1(rden_IBUF_1051),
.ADR2(addr_2_IBUF_1045),
.ADR3(\baud1/period [1]),
.O(N77)
);
X_LUT4 #(
.INIT ( 16'hBABA ),
.LOC ( "SLICE_X17Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_mux0000_F (
.ADR0(pstate[0]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_996 ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_1102 ),
.ADR3(VCC),
.O(\fifo1/N25 )
);
X_LUT4 #(
.INIT ( 16'h4040 ),
.LOC ( "SLICE_X26Y27" ))
\dout<4>1 (
.ADR0(addr_1_IBUF_1065),
.ADR1(addr_2_IBUF_1045),
.ADR2(dout_fifo[4]),
.ADR3(VCC),
.O(\dout<4>1_2274 )
);
X_LUT4 #(
.INIT ( 16'hFBFA ),
.LOC ( "SLICE_X17Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_mux0000_G (
.ADR0(pstate[0]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_996 ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_1102 ),
.ADR3(rd_fifo),
.O(\fifo1/N26 )
);
X_LUT4 #(
.INIT ( 16'h2000 ),
.LOC ( "SLICE_X29Y27" ))
\dout<3>2 (
.ADR0(\baud1/period [3]),
.ADR1(addr_1_IBUF_1065),
.ADR2(rden_IBUF_1051),
.ADR3(addr_2_IBUF_1045),
.O(\dout<3>2_2241 )
);
X_LUT4 #(
.INIT ( 16'h4400 ),
.LOC ( "SLICE_X29Y27" ))
\dout<3>1 (
.ADR0(addr_1_IBUF_1065),
.ADR1(dout_fifo[3]),
.ADR2(VCC),
.ADR3(addr_2_IBUF_1045),
.O(\dout<3>1_2249 )
);
X_LUT4 #(
.INIT ( 16'hE222 ),
.LOC ( "SLICE_X27Y27" ))
\dout<0>30_G (
.ADR0(dout_fifo[0]),
.ADR1(addr_1_IBUF_1065),
.ADR2(rden_IBUF_1051),
.ADR3(control[0]),
.O(N80)
);
X_LUT4 #(
.INIT ( 16'h0080 ),
.LOC ( "SLICE_X26Y27" ))
\dout<4>2 (
.ADR0(\baud1/period [4]),
.ADR1(rden_IBUF_1051),
.ADR2(addr_2_IBUF_1045),
.ADR3(addr_1_IBUF_1065),
.O(\dout<4>2_2266 )
);
X_LUT4 #(
.INIT ( 16'h5000 ),
.LOC ( "SLICE_X29Y24" ))
\dout<5>1 (
.ADR0(addr_1_IBUF_1065),
.ADR1(VCC),
.ADR2(addr_2_IBUF_1045),
.ADR3(dout_fifo[5]),
.O(\dout<5>1_2331 )
);
X_LUT4 #(
.INIT ( 16'h0080 ),
.LOC ( "SLICE_X28Y26" ))
\dout<7>2 (
.ADR0(rden_IBUF_1051),
.ADR1(\baud1/period [7]),
.ADR2(addr_2_IBUF_1045),
.ADR3(addr_1_IBUF_1065),
.O(\dout<7>2_2166 )
);
X_LUT4 #(
.INIT ( 16'h4000 ),
.LOC ( "SLICE_X27Y27" ))
\dout<0>30_F (
.ADR0(addr_1_IBUF_1065),
.ADR1(addr_2_IBUF_1045),
.ADR2(rden_IBUF_1051),
.ADR3(\baud1/period [0]),
.O(N79)
);
X_LUT4 #(
.INIT ( 16'h88F0 ),
.LOC ( "SLICE_X25Y25" ))
\dout<1>30_G (
.ADR0(control[1]),
.ADR1(rden_IBUF_1051),
.ADR2(dout_fifo[1]),
.ADR3(addr_1_IBUF_1065),
.O(N78)
);
X_LUT4 #(
.INIT ( 16'h00A0 ),
.LOC ( "SLICE_X28Y26" ))
\dout<7>1 (
.ADR0(dout_fifo[7]),
.ADR1(VCC),
.ADR2(addr_2_IBUF_1045),
.ADR3(addr_1_IBUF_1065),
.O(\dout<7>1_2174 )
);
X_LUT4 #(
.INIT ( 16'h0777 ),
.LOC ( "SLICE_X23Y25" ))
\pstate_mux0000<4>_SW0 (
.ADR0(pstate[1]),
.ADR1(rxin_IBUF_1000),
.ADR2(pstate[0]),
.ADR3(control[0]),
.O(\pstate_mux0000<4>_SW0/O_pack_2 )
);
X_LUT4 #(
.INIT ( 16'h0A00 ),
.LOC ( "SLICE_X28Y27" ))
\dout<6>1 (
.ADR0(addr_2_IBUF_1045),
.ADR1(VCC),
.ADR2(addr_1_IBUF_1065),
.ADR3(dout_fifo[6]),
.O(\dout<6>1_2381 )
);
X_FF #(
.LOC ( "SLICE_X13Y22" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_2471 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_2456 ),
.SET(GND),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_995 )
);
X_LUT4 #(
.INIT ( 16'h0080 ),
.LOC ( "SLICE_X28Y27" ))
\dout<6>2 (
.ADR0(addr_2_IBUF_1045),
.ADR1(rden_IBUF_1051),
.ADR2(\baud1/period [6]),
.ADR3(addr_1_IBUF_1065),
.O(\dout<6>2_2373 )
);
X_LUT4 #(
.INIT ( 16'hFCF4 ),
.LOC ( "SLICE_X13Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000100_SW0_SW0_SW0 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_995 ),
.ADR2(pstate[0]),
.ADR3(\fifo1/N8_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000100_SW0_SW0_SW0/O_pack_2 )
);
X_LUT4 #(
.INIT ( 16'hFEFB ),
.LOC ( "SLICE_X25Y33" ))
\baud1/timer_mux0000<0>11_SW8_G (
.ADR0(rxin_IBUF_1000),
.ADR1(\baud1/timer [6]),
.ADR2(pstate[0]),
.ADR3(\baud1/timer [7]),
.O(N46)
);
X_LUT4 #(
.INIT ( 16'h0007 ),
.LOC ( "SLICE_X27Y28" ))
\baud1/timer_mux0000<5>1 (
.ADR0(rxin_IBUF_1000),
.ADR1(pstate[1]),
.ADR2(\baud1/baud_cmp_eq0000_0 ),
.ADR3(\baud1/timer_mux0000<0>11_SW5/O ),
.O(\baud1/timer_mux0000 [5])
);
X_LUT4 #(
.INIT ( 16'h3033 ),
.LOC ( "SLICE_X23Y25" ))
\pstate_mux0000<4> (
.ADR0(VCC),
.ADR1(control[2]),
.ADR2(pstate[4]),
.ADR3(\pstate_mux0000<4>_SW0/O ),
.O(pstate_mux0000[4])
);
X_FF #(
.LOC ( "SLICE_X23Y25" ),
.INIT ( 1'b0 ))
pstate_1 (
.I(\pstate<1>/DXMUX_2503 ),
.CE(VCC),
.CLK(\pstate<1>/CLKINV_2486 ),
.SET(GND),
.RST(\pstate<1>/FFX/RSTAND_2508 ),
.O(pstate[1])
);
X_BUF #(
.LOC ( "SLICE_X23Y25" ))
\pstate<1>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\pstate<1>/FFX/RSTAND_2508 )
);
X_LUT4 #(
.INIT ( 16'hEFFF ),
.LOC ( "SLICE_X29Y26" ))
\dout<2>41_SW01 (
.ADR0(addr_1_IBUF_1065),
.ADR1(addr_0_IBUF_1064),
.ADR2(\baud1/period [2]),
.ADR3(addr_2_IBUF_1045),
.O(\dout<2>41_SW0 )
);
X_LUT4 #(
.INIT ( 16'hFCF3 ),
.LOC ( "SLICE_X25Y33" ))
\baud1/timer_mux0000<0>11_SW8_F (
.ADR0(VCC),
.ADR1(\baud1/timer [6]),
.ADR2(pstate[0]),
.ADR3(\baud1/timer [7]),
.O(N45)
);
X_FF #(
.LOC ( "SLICE_X27Y28" ),
.INIT ( 1'b0 ))
\baud1/timer_2 (
.I(\baud1/timer<2>/DXMUX_2438 ),
.CE(VCC),
.CLK(\baud1/timer<2>/CLKINV_2422 ),
.SET(GND),
.RST(\baud1/timer<2>/FFX/RSTAND_2443 ),
.O(\baud1/timer [2])
);
X_BUF #(
.LOC ( "SLICE_X27Y28" ))
\baud1/timer<2>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\baud1/timer<2>/FFX/RSTAND_2443 )
);
X_LUT4 #(
.INIT ( 16'hECDF ),
.LOC ( "SLICE_X27Y28" ))
\baud1/timer_mux0000<0>11_SW5 (
.ADR0(\baud1/timer [1]),
.ADR1(pstate[0]),
.ADR2(\baud1/timer [0]),
.ADR3(\baud1/timer [2]),
.O(\baud1/timer_mux0000<0>11_SW5/O_pack_2 )
);
X_LUT4 #(
.INIT ( 16'hF8F0 ),
.LOC ( "SLICE_X13Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000102 (
.ADR0(\fifo1/N17_0 ),
.ADR1(\fifo1/N5_0 ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000100_SW0_SW0_SW0/O ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 )
);
X_LUT4 #(
.INIT ( 16'h8000 ),
.LOC ( "SLICE_X26Y30" ))
\baud1/Madd_timer_addsub0000_cy<3>11 (
.ADR0(\baud1/timer [2]),
.ADR1(\baud1/timer [0]),
.ADR2(\baud1/timer [3]),
.ADR3(\baud1/timer [1]),
.O(\baud1/Madd_timer_addsub0000_cy<3>_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h9009 ),
.LOC ( "SLICE_X26Y29" ))
\baud1/baud_cmp_eq0000853 (
.ADR0(\baud1/timer [2]),
.ADR1(\baud1/period [2]),
.ADR2(\baud1/timer [3]),
.ADR3(\baud1/period [3]),
.O(\baud1/baud_cmp_eq0000853/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h8800 ),
.LOC ( "SLICE_X26Y30" ))
\baud1/Madd_timer_addsub0000_cy<5>11 (
.ADR0(\baud1/timer [4]),
.ADR1(\baud1/timer [5]),
.ADR2(VCC),
.ADR3(\baud1/Madd_timer_addsub0000_cy[3] ),
.O(\baud1/Madd_timer_addsub0000_cy[5] )
);
X_LUT4 #(
.INIT ( 16'h0080 ),
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000079 (
.ADR0(pstate[4]),
.ADR1(\fifo1/N21_0 ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_0 ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000079/O_pack_2 )
);
X_LUT4 #(
.INIT ( 16'h3737 ),
.LOC ( "SLICE_X19Y28" ))
\pstate_mux0000<2>18_SW0 (
.ADR0(bitcounter[0]),
.ADR1(pstate[2]),
.ADR2(N16),
.ADR3(VCC),
.O(\pstate_mux0000<2>18_SW0/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h00AE ),
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000105 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000079/O ),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1019 ),
.ADR2(\fifo1/N7_0 ),
.ADR3(pstate[0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 )
);
X_FF #(
.LOC ( "SLICE_X14Y25" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX_2620 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV_2605 ),
.SET(GND),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1019 )
);
X_LUT4 #(
.INIT ( 16'h5400 ),
.LOC ( "SLICE_X19Y26" ))
\pstate_mux0000<3>15 (
.ADR0(\baud1/baud_1023 ),
.ADR1(N16),
.ADR2(bitcounter[0]),
.ADR3(pstate[2]),
.O(\pstate_mux0000<3>15_2590 )
);
X_LUT4 #(
.INIT ( 16'h8000 ),
.LOC ( "SLICE_X26Y29" ))
\baud1/baud_cmp_eq00008136 (
.ADR0(\baud1/baud_cmp_eq00008120_0 ),
.ADR1(\baud1/baud_cmp_eq0000826_0 ),
.ADR2(\baud1/baud_cmp_eq0000853/O ),
.ADR3(\baud1/baud_cmp_eq0000893_0 ),
.O(\baud1/baud_cmp_eq0000 )
);
X_LUT4 #(
.INIT ( 16'h2322 ),
.LOC ( "SLICE_X19Y28" ))
\pstate_mux0000<2>31 (
.ADR0(\pstate_mux0000<2>10_0 ),
.ADR1(control[2]),
.ADR2(\pstate_mux0000<2>18_SW0/O ),
.ADR3(\baud1/baud_1023 ),
.O(pstate_mux0000[2])
);
X_LUT4 #(
.INIT ( 16'hEBAF ),
.LOC ( "SLICE_X26Y31" ))
\baud1/timer_mux0000<0>11_SW0 (
.ADR0(pstate[0]),
.ADR1(\baud1/timer_mux0000<4>_SW0/O ),
.ADR2(\baud1/timer [3]),
.ADR3(\baud1/timer [2]),
.O(N26)
);
X_LUT4 #(
.INIT ( 16'hFF3F ),
.LOC ( "SLICE_X19Y26" ))
\Mcount_bitcounter_xor<0>1111 (
.ADR0(VCC),
.ADR1(bitcounter[1]),
.ADR2(bitcounter[3]),
.ADR3(bitcounter[2]),
.O(N16_pack_1)
);
X_LUT4 #(
.INIT ( 16'hAFAF ),
.LOC ( "SLICE_X19Y24" ))
bitcounter_not00011_SW0 (
.ADR0(bitcounter[0]),
.ADR1(VCC),
.ADR2(pstate[2]),
.ADR3(VCC),
.O(\bitcounter_not00011_SW0/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hCC00 ),
.LOC ( "SLICE_X26Y31" ))
\baud1/timer_mux0000<4>_SW0 (
.ADR0(VCC),
.ADR1(\baud1/timer [0]),
.ADR2(VCC),
.ADR3(\baud1/timer [1]),
.O(\baud1/timer_mux0000<4>_SW0/O_pack_1 )
);
X_FF #(
.LOC ( "SLICE_X19Y28" ),
.INIT ( 1'b0 ))
pstate_3 (
.I(\pstate<3>/DXMUX_2538 ),
.CE(VCC),
.CLK(\pstate<3>/CLKINV_2521 ),
.SET(GND),
.RST(\pstate<3>/FFX/RSTAND_2543 ),
.O(pstate[3])
);
X_BUF #(
.LOC ( "SLICE_X19Y28" ))
\pstate<3>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\pstate<3>/FFX/RSTAND_2543 )
);
X_LUT4 #(
.INIT ( 16'h0001 ),
.LOC ( "SLICE_X27Y33" ))
\baud1/timer_mux0000<7>1 (
.ADR0(\baud1/timer [0]),
.ADR1(\baud1/baud_cmp_eq0000_0 ),
.ADR2(N28_0),
.ADR3(pstate[0]),
.O(\baud1/timer_mux0000 [7])
);
X_FF #(
.LOC ( "SLICE_X26Y33" ),
.INIT ( 1'b0 ))
\baud1/timer_6 (
.I(\baud1/timer<6>/DXMUX_2771 ),
.CE(VCC),
.CLK(\baud1/timer<6>/CLKINV_2754 ),
.SET(GND),
.RST(\baud1/timer<6>/FFX/RSTAND_2776 ),
.O(\baud1/timer [6])
);
X_BUF #(
.LOC ( "SLICE_X26Y33" ))
\baud1/timer<6>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\baud1/timer<6>/FFX/RSTAND_2776 )
);
X_LUT4 #(
.INIT ( 16'h0013 ),
.LOC ( "SLICE_X27Y31" ))
\baud1/timer_mux0000<2>1 (
.ADR0(rxin_IBUF_1000),
.ADR1(\baud1/baud_cmp_eq0000_0 ),
.ADR2(pstate[1]),
.ADR3(\baud1/timer_mux0000<0>11_SW6/O ),
.O(\baud1/timer_mux0000 [2])
);
X_LUT4 #(
.INIT ( 16'hFFBE ),
.LOC ( "SLICE_X12Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168 (
.ADR0(\fifo1/N9_0 ),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.ADR3(\fifo1/N3 ),
.O(\fifo1/N8 )
);
X_LUT4 #(
.INIT ( 16'h6FF6 ),
.LOC ( "SLICE_X12Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168_SW0 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.O(\fifo1/N3_pack_1 )
);
X_FF #(
.LOC ( "SLICE_X27Y31" ),
.INIT ( 1'b0 ))
\baud1/timer_5 (
.I(\baud1/timer<5>/DXMUX_2806 ),
.CE(VCC),
.CLK(\baud1/timer<5>/CLKINV_2790 ),
.SET(GND),
.RST(\baud1/timer<5>/FFX/RSTAND_2811 ),
.O(\baud1/timer [5])
);
X_BUF #(
.LOC ( "SLICE_X27Y31" ))
\baud1/timer<5>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\baud1/timer<5>/FFX/RSTAND_2811 )
);
X_LUT4 #(
.INIT ( 16'h0035 ),
.LOC ( "SLICE_X26Y32" ))
\baud1/timer_mux0000<0>1 (
.ADR0(\baud1/timer_mux0000<0>11_SW7/O ),
.ADR1(N41),
.ADR2(\baud1/Madd_timer_addsub0000_cy<5>_0 ),
.ADR3(\baud1/baud_cmp_eq0000_0 ),
.O(\baud1/timer_mux0000 [0])
);
X_LUT4 #(
.INIT ( 16'hEEAA ),
.LOC ( "SLICE_X26Y33" ))
\baud1/timer_mux0000<0>11_SW2 (
.ADR0(pstate[0]),
.ADR1(pstate[1]),
.ADR2(VCC),
.ADR3(rxin_IBUF_1000),
.O(N30_pack_2)
);
X_LUT4 #(
.INIT ( 16'hFF93 ),
.LOC ( "SLICE_X27Y31" ))
\baud1/timer_mux0000<0>11_SW6 (
.ADR0(\baud1/Madd_timer_addsub0000_cy[3] ),
.ADR1(\baud1/timer [5]),
.ADR2(\baud1/timer [4]),
.ADR3(pstate[0]),
.O(\baud1/timer_mux0000<0>11_SW6/O_pack_2 )
);
X_LUT4 #(
.INIT ( 16'h0008 ),
.LOC ( "SLICE_X19Y24" ))
bitcounter_not00011 (
.ADR0(bitcounter[1]),
.ADR1(bitcounter[3]),
.ADR2(\bitcounter_not00011_SW0/O ),
.ADR3(bitcounter[2]),
.O(finish)
);
X_FF #(
.LOC ( "SLICE_X26Y32" ),
.INIT ( 1'b0 ))
\baud1/timer_7 (
.I(\baud1/timer<7>/DXMUX_2736 ),
.CE(VCC),
.CLK(\baud1/timer<7>/CLKINV_2720 ),
.SET(GND),
.RST(\baud1/timer<7>/FFX/RSTAND_2741 ),
.O(\baud1/timer [7])
);
X_BUF #(
.LOC ( "SLICE_X26Y32" ))
\baud1/timer<7>/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\baud1/timer<7>/FFX/RSTAND_2741 )
);
X_FF #(
.LOC ( "SLICE_X19Y24" ),
.INIT ( 1'b0 ))
frame_ready (
.I(\frame_ready/DXMUX_2701 ),
.CE(VCC),
.CLK(\frame_ready/CLKINV_2683 ),
.SET(GND),
.RST(\frame_ready/FFX/RSTAND_2706 ),
.O(frame_ready_1129)
);
X_BUF #(
.LOC ( "SLICE_X19Y24" ))
\frame_ready/FFX/RSTAND (
.I(reset_IBUF_963),
.O(\frame_ready/FFX/RSTAND_2706 )
);
X_LUT4 #(
.INIT ( 16'h0006 ),
.LOC ( "SLICE_X26Y33" ))
\baud1/timer_mux0000<1>1 (
.ADR0(\baud1/timer [6]),
.ADR1(\baud1/Madd_timer_addsub0000_cy<5>_0 ),
.ADR2(N30),
.ADR3(\baud1/baud_cmp_eq0000_0 ),
.O(\baud1/timer_mux0000 [1])
);
X_LUT4 #(
.INIT ( 16'hEAFF ),
.LOC ( "SLICE_X26Y32" ))
\baud1/timer_mux0000<0>11_SW7 (
.ADR0(pstate[0]),
.ADR1(pstate[1]),
.ADR2(rxin_IBUF_1000),
.ADR3(\baud1/timer [7]),
.O(\baud1/timer_mux0000<0>11_SW7/O_pack_2 )
);
X_LUT4 #(
.INIT ( 16'h0110 ),
.LOC ( "SLICE_X27Y33" ))
\baud1/timer_mux0000<6>1 (
.ADR0(N30),
.ADR1(\baud1/baud_cmp_eq0000_0 ),
.ADR2(\baud1/timer [0]),
.ADR3(\baud1/timer [1]),
.O(\baud1/timer_mux0000 [6])
);
X_LUT4 #(
.INIT ( 16'h0D0C ),
.LOC ( "SLICE_X20Y24" ))
\pstate_mux0000<5>1 (
.ADR0(control[0]),
.ADR1(pstate[5]),
.ADR2(control[2]),
.ADR3(pstate[0]),
.O(pstate_mux0000[5])
);
X_FF #(
.LOC ( "SLICE_X18Y23" ),
.INIT ( 1'b0 ))
in_two (
.I(\in_two/DYMUX_2904 ),
.CE(VCC),
.CLK(\in_two/CLKINV_2891 ),
.SET(GND),
.RST(GND),
.O(in_two_983)
);
X_LUT4 #(
.INIT ( 16'h6CCC ),
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<3>11 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\fifo1/Result<3>1 )
);
X_LUT4 #(
.INIT ( 16'h66AA ),
.LOC ( "SLICE_X12Y28" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<2>11 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR2(VCC),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\fifo1/Result [2])
);
X_SFF #(
.LOC ( "SLICE_X12Y28" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_2973 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_2962 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_2963 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_2964 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2])
);
X_SFF #(
.LOC ( "SLICE_X13Y27" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX_2931 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_2920 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_2921 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_2922 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2])
);
X_SFF #(
.LOC ( "SLICE_X13Y27" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_3 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX_2944 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_2920 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_2921 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_2922 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3])
);
X_LUT4 #(
.INIT ( 16'h7F80 ),
.LOC ( "SLICE_X12Y28" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<3>11 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.O(\fifo1/Result [3])
);
X_SRLC16E #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X18Y23" ))
\Mshreg_in_two/SRL16E (
.A0(GND),
.A1(GND),
.A2(GND),
.A3(GND),
.D(\in_two/DIG_MUX_2893 ),
.CE(\in_two/WSG ),
.CLK(\in_two/CLKINV_2891 ),
.Q(Mshreg_in_two),
.Q15(\NLW_Mshreg_in_two/SRL16E_Q15_UNCONNECTED )
);
X_SFF #(
.LOC ( "SLICE_X12Y28" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_3 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_2986 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_2962 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_2963 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_2964 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3])
);
X_LUT4 #(
.INIT ( 16'h7878 ),
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<2>11 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.ADR3(VCC),
.O(\fifo1/Result<2>1 )
);
X_FF #(
.LOC ( "SLICE_X27Y33" ),
.INIT ( 1'b0 ))
\baud1/timer_0 (
.I(\baud1/timer<1>/DYMUX_2858 ),
.CE(VCC),
.CLK(\baud1/timer<1>/CLKINV_2849 ),
.SET(GND),
.RST(\baud1/timer<1>/SRINV_2850 ),
.O(\baud1/timer [0])
);
X_FF #(
.LOC ( "SLICE_X27Y33" ),
.INIT ( 1'b0 ))
\baud1/timer_1 (
.I(\baud1/timer<1>/DXMUX_2872 ),
.CE(VCC),
.CLK(\baud1/timer<1>/CLKINV_2849 ),
.SET(GND),
.RST(\baud1/timer<1>/SRINV_2850 ),
.O(\baud1/timer [1])
);
X_LUT4 #(
.INIT ( 16'hAFAA ),
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en1 (
.ADR0(pstate[0]),
.ADR1(VCC),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_995 ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en )
);
X_FF #(
.LOC ( "SLICE_X20Y24" ),
.INIT ( 1'b0 ))
control_1 (
.I(\control<1>/DXMUX_3026 ),
.CE(VCC),
.CLK(\control<1>/CLKINV_3002 ),
.SET(GND),
.RST(\control<1>/SRINV_3003 ),
.O(control[1])
);
X_FF #(
.LOC ( "SLICE_X20Y24" ),
.INIT ( 1'b1 ))
pstate_0 (
.I(\control<1>/DYMUX_3011 ),
.CE(VCC),
.CLK(\control<1>/CLKINV_3002 ),
.SET(\control<1>/SRINV_3003 ),
.RST(GND),
.O(pstate[0])
);
X_FF #(
.LOC ( "SLICE_X18Y24" ),
.INIT ( 1'b0 ))
bitcounter_2 (
.I(\bitcounter<2>/DYMUX_3077 ),
.CE(\bitcounter<2>/CEINV_3066 ),
.CLK(\bitcounter<2>/CLKINV_3067 ),
.SET(GND),
.RST(\bitcounter<2>/FFY/RSTAND_3083 ),
.O(bitcounter[2])
);
X_BUF #(
.LOC ( "SLICE_X18Y24" ))
\bitcounter<2>/FFY/RSTAND (
.I(reset_IBUF_963),
.O(\bitcounter<2>/FFY/RSTAND_3083 )
);
X_LUT4 #(
.INIT ( 16'h3CCC ),
.LOC ( "SLICE_X20Y26" ))
\Mcount_bittimer_xor<2>11 (
.ADR0(VCC),
.ADR1(bittimer[2]),
.ADR2(bittimer[1]),
.ADR3(bittimer[0]),
.O(Result[2])
);
X_LUT4 #(
.INIT ( 16'h66AA ),
.LOC ( "SLICE_X18Y24" ))
\Mcount_bitcounter_xor<2>11 (
.ADR0(bitcounter[2]),
.ADR1(bitcounter[0]),
.ADR2(VCC),
.ADR3(bitcounter[1]),
.O(Mcount_bitcounter2)
);
X_FF #(
.LOC ( "SLICE_X20Y26" ),
.INIT ( 1'b0 ))
bittimer_3 (
.I(\bittimer<3>/DXMUX_3123 ),
.CE(\bittimer<3>/CEINV_3097 ),
.CLK(\bittimer<3>/CLKINV_3098 ),
.SET(GND),
.RST(\bittimer<3>/SRINV_3099 ),
.O(bittimer[3])
);
X_LUT4 #(
.INIT ( 16'h88FF ),
.LOC ( "SLICE_X21Y24" ))
control_2_not00011 (
.ADR0(frame_ready_1129),
.ADR1(full),
.ADR2(VCC),
.ADR3(control[0]),
.O(control_2_not0001)
);
X_FF #(
.LOC ( "SLICE_X17Y23" ),
.INIT ( 1'b0 ))
frame_error_8 (
.I(\frame_error<8>/DYMUX_3051 ),
.CE(\frame_error<8>/CEINV_3039 ),
.CLK(\frame_error<8>/CLKINV_3040 ),
.SET(GND),
.RST(\frame_error<8>/FFY/RSTAND_3057 ),
.O(frame_error[8])
);
X_BUF #(
.LOC ( "SLICE_X17Y23" ))
\frame_error<8>/FFY/RSTAND (
.I(reset_IBUF_963),
.O(\frame_error<8>/FFY/RSTAND_3057 )
);
X_LUT4 #(
.INIT ( 16'hFF55 ),
.LOC ( "SLICE_X17Y23" ))
frame_error_8_or00001 (
.ADR0(shift[9]),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(shift[0]),
.O(frame_error_8_or0000)
);
X_FF #(
.LOC ( "SLICE_X20Y26" ),
.INIT ( 1'b0 ))
bittimer_2 (
.I(\bittimer<3>/DYMUX_3108 ),
.CE(\bittimer<3>/CEINV_3097 ),
.CLK(\bittimer<3>/CLKINV_3098 ),
.SET(GND),
.RST(\bittimer<3>/SRINV_3099 ),
.O(bittimer[2])
);
X_LUT4 #(
.INIT ( 16'h6AAA ),
.LOC ( "SLICE_X20Y26" ))
\Mcount_bittimer_xor<3>11 (
.ADR0(bittimer[3]),
.ADR1(bittimer[2]),
.ADR2(bittimer[1]),
.ADR3(bittimer[0]),
.O(Result[3])
);
X_LUT4 #(
.INIT ( 16'h3000 ),
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00005_SW0 (
.ADR0(VCC),
.ADR1(\fifo1/N3 ),
.ADR2(\fifo1/N23_0 ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\fifo1/N7 )
);
X_LUT4 #(
.INIT ( 16'h2222 ),
.LOC ( "SLICE_X20Y24" ))
control_1_mux00001 (
.ADR0(control[0]),
.ADR1(empty),
.ADR2(VCC),
.ADR3(VCC),
.O(control_1_mux0000)
);
X_LUT4 #(
.INIT ( 16'h8F80 ),
.LOC ( "SLICE_X24Y27" ))
\dout<2>10 (
.ADR0(rden_IBUF_1051),
.ADR1(control[2]),
.ADR2(addr_1_IBUF_1065),
.ADR3(dout_fifo[2]),
.O(\dout<2>10_pack_1 )
);
X_FF #(
.LOC ( "SLICE_X28Y30" ),
.INIT ( 1'b0 ))
\baud1/period_5 (
.I(\baud1/period<5>/DXMUX_3252 ),
.CE(\baud1/period<5>/CEINV_3240 ),
.CLK(\baud1/period<5>/CLKINV_3241 ),
.SET(GND),
.RST(\baud1/period<5>/SRINV_3242 ),
.O(\baud1/period [5])
);
X_FF #(
.LOC ( "SLICE_X28Y29" ),
.INIT ( 1'b1 ))
\baud1/period_1 (
.I(\baud1/period<1>/DXMUX_3199 ),
.CE(\baud1/period<1>/CEINV_3186 ),
.CLK(\baud1/period<1>/CLKINV_3187 ),
.SET(\baud1/period<1>/SRINV_3188 ),
.RST(GND),
.O(\baud1/period [1])
);
X_FF #(
.LOC ( "SLICE_X28Y30" ),
.INIT ( 1'b1 ))
\baud1/period_4 (
.I(\baud1/period<5>/DYMUX_3244 ),
.CE(\baud1/period<5>/CEINV_3240 ),
.CLK(\baud1/period<5>/CLKINV_3241 ),
.SET(\baud1/period<5>/SRINV_3242 ),
.RST(GND),
.O(\baud1/period [4])
);
X_FF #(
.LOC ( "SLICE_X28Y29" ),
.INIT ( 1'b0 ))
\baud1/period_0 (
.I(\baud1/period<1>/DYMUX_3190 ),
.CE(\baud1/period<1>/CEINV_3186 ),
.CLK(\baud1/period<1>/CLKINV_3187 ),
.SET(GND),
.RST(\baud1/period<1>/SRINV_3188 ),
.O(\baud1/period [0])
);
X_FF #(
.LOC ( "SLICE_X29Y28" ),
.INIT ( 1'b1 ))
\baud1/period_3 (
.I(\baud1/period<3>/DXMUX_3226 ),
.CE(\baud1/period<3>/CEINV_3213 ),
.CLK(\baud1/period<3>/CLKINV_3214 ),
.SET(\baud1/period<3>/SRINV_3215 ),
.RST(GND),
.O(\baud1/period [3])
);
X_FF #(
.LOC ( "SLICE_X29Y31" ),
.INIT ( 1'b0 ))
\baud1/period_6 (
.I(\baud1/period<7>/DYMUX_3295 ),
.CE(\baud1/period<7>/CEINV_3291 ),
.CLK(\baud1/period<7>/CLKINV_3292 ),
.SET(GND),
.RST(\baud1/period<7>/SRINV_3293 ),
.O(\baud1/period [6])
);
X_LUT4 #(
.INIT ( 16'h2000 ),
.LOC ( "SLICE_X15Y25" ))
rd_fifo1 (
.ADR0(rden_IBUF_1051),
.ADR1(addr_1_IBUF_1065),
.ADR2(addr_0_IBUF_1064),
.ADR3(addr_2_IBUF_1045),
.O(rd_fifo_pack_1)
);
X_LUT4 #(
.INIT ( 16'h8241 ),
.LOC ( "SLICE_X13Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000079_SW0 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.O(\fifo1/N21 )
);
X_FF #(
.LOC ( "SLICE_X29Y28" ),
.INIT ( 1'b0 ))
\baud1/period_2 (
.I(\baud1/period<3>/DYMUX_3217 ),
.CE(\baud1/period<3>/CEINV_3213 ),
.CLK(\baud1/period<3>/CLKINV_3214 ),
.SET(GND),
.RST(\baud1/period<3>/SRINV_3215 ),
.O(\baud1/period [2])
);
X_LUT4 #(
.INIT ( 16'h0F07 ),
.LOC ( "SLICE_X15Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/RAM_RD_EN_FWFT1 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_998 ),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_996 ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_995 ),
.ADR3(rd_fifo),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en )
);
X_FF #(
.LOC ( "SLICE_X29Y31" ),
.INIT ( 1'b0 ))
\baud1/period_7 (
.I(\baud1/period<7>/DXMUX_3304 ),
.CE(\baud1/period<7>/CEINV_3291 ),
.CLK(\baud1/period<7>/CLKINV_3292 ),
.SET(GND),
.RST(\baud1/period<7>/SRINV_3293 ),
.O(\baud1/period [7])
);
X_BUF #(
.LOC ( "PAD38" ))
\dout<7>/OUTPUT/OFF/OMUX (
.I(\dout_7_OBUF/F5MUX_2176 ),
.O(\dout<7>/O )
);
X_BUF #(
.LOC ( "PAD45" ))
\dout<3>/OUTPUT/OFF/OMUX (
.I(\dout_3_OBUF/F5MUX_2251 ),
.O(\dout<3>/O )
);
X_BUF #(
.LOC ( "PAD40" ))
\dout<5>/OUTPUT/OFF/OMUX (
.I(\dout_5_OBUF/F5MUX_2333 ),
.O(\dout<5>/O )
);
X_BUF #(
.LOC ( "PAD47" ))
\dout<0>/OUTPUT/OFF/OMUX (
.I(dout_0_OBUF_3482),
.O(\dout<0>/O )
);
X_BUF #(
.LOC ( "PAD44" ))
\dout<8>/OUTPUT/OFF/OMUX (
.I(dout_8_OBUF_3451),
.O(\dout<8>/O )
);
X_BUF #(
.LOC ( "PAD43" ))
\dout<4>/OUTPUT/OFF/OMUX (
.I(\dout_4_OBUF/F5MUX_2276 ),
.O(\dout<4>/O )
);
X_BUF #(
.LOC ( "PAD42" ))
\dout<6>/OUTPUT/OFF/OMUX (
.I(\dout_6_OBUF/F5MUX_2383 ),
.O(\dout<6>/O )
);
X_BUF #(
.LOC ( "PAD37" ))
\dout<2>/OUTPUT/OFF/OMUX (
.I(dout_2_OBUF_3518),
.O(\dout<2>/O )
);
X_BUF #(
.LOC ( "PAD49" ))
\dout<1>/OUTPUT/OFF/OMUX (
.I(dout_1_OBUF_3674),
.O(\dout<1>/O )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X29Y26" ))
\N47/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\N47/G )
);
X_BUF #(
.LOC ( "SLICE_X18Y23" ))
\Mshreg_in_two/SRL16E.CE/WSGAND (
.I(\in_two/SRINV_2887 ),
.O(\in_two/WSG )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0> (
.I(frame_error[0]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1> (
.I(frame_error[1]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<2> (
.I(frame_error[2]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<2> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8> (
.I(frame_error[3]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9> (
.I(frame_error[4]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16> (
.I(frame_error[5]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<17> (
.I(frame_error[6]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<17> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<24> (
.I(frame_error[7]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<24> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25> (
.I(frame_error[8]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25> )
);
X_ZERO NlwBlock_uart_rx_GND (
.O(GND)
);
X_ONE NlwBlock_uart_rx_VCC (
.O(VCC)
);
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module helloworld (clk, led, dipswitch, key0, key1);
// declare inputs
// pins are in pin planner/DE0-Nano User Guide
input clk;
input key0;
input key1;
input [3:0] dipswitch;
output reg [7:0] led;
reg [31:0] counter = 0;
integer i = 0;
reg [3:0] toggle = 0;
always @ (posedge clk)
begin
// 50MHz internal clock
// 25M clock cycles = 0.5s
if (counter <= 25000000)
begin
counter <= counter + 1;
end
else
begin
counter <= 0;
// increment or decrement on buttonpress depending on button pressed
if (~key0)
begin
led[i] = 0;
if (dipswitch[0] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[1] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[2] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[3] == 1)
begin
toggle = toggle + 1'b1;
end
// increment i by the number of switches activated
i = i + toggle;
// wraparound to 0
if (i > 7)
begin
i = i - 8;
end
led[i] = 1;
end
else if (~key1)
begin
led[i] = 0;
if (dipswitch[0] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[1] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[2] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[3] == 1)
begin
toggle = toggle + 1'b1;
end
// decrement i by the number of switches activated
i = i - toggle;
// wraparound to 7
if (i < 0)
begin
i = i + 8;
end
// activate selected LED
led[i] = 1;
end
else
begin
end
// flash LED
led[i] = ~led[i];
// reset toggle value
toggle = 0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD3_BEHAVIORAL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD3_BEHAVIORAL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd3 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD3_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: SILAB , Physics Institute of Bonn University
// Engineer: Viacheslav Filimonov
//
// Create Date: 10:40:28 12/16/2013
// Design Name:
// Module Name: KX7_IF_Test_Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mmc3_top(
// FX 3 interface
input wire fx3_pclk_100MHz,
(* IOB = "FORCE" *) input wire fx3_wr, // force IOB register
(* IOB = "FORCE" *) input wire fx3_cs, // async. signal
(* IOB = "FORCE" *) input wire fx3_oe, // async. signal
input wire fx3_rst,// async. signal from FX3, active high
(* IOB = "FORCE" *) output wire fx3_ack,// force IOB register
(* IOB = "FORCE" *) output wire fx3_rdy,// force IOB register
output wire reset_fx3,
inout wire [31:0] fx3_bus, // 32 bit databus
// 200 MHz oscillator
input wire sys_clk_p,
input wire sys_clk_n,
// 100 Mhz oscillator
input wire Clk100,
// GPIO
output wire [8:1] led,
output wire [3:0] PWR_EN,
(* IOB = "FORCE" *) output wire fx3_rd_finish,
input wire Reset_button2,// async. signal
input wire FLAG1, // was DMA Flag; currently connected to TEST signal from FX3
(* IOB = "FORCE" *) input wire FLAG2, // DMA watermark flag for thread 2 of FX3
// Power supply regulators EN signals
output wire EN_VD1,
output wire EN_VD2,
output wire EN_VA1,
output wire EN_VA2,
// Command sequencer signals
output wire CMD_CLK_OUT,
(* IOB = "FORCE" *) output wire CMD_DATA,
// FE-I4_rx signals
(* IOB = "FORCE" *) input wire DOBOUT
);
assign reset_fx3 = 1; // not to reset fx3 while loading fpga
assign EN_VD1 = 1;
assign EN_VD2 = 1;
assign EN_VA1 = 1;
assign EN_VA2 = 1;
wire [31:0] BUS_ADD;
wire [31:0] BUS_DATA;
wire BUS_RD, BUS_WR, BUS_RST, BUS_CLK;
//assign BUS_RST = (BUS_RST | (!LOCKED));
wire BUS_BYTE_ACCESS;
assign BUS_BYTE_ACCESS = (BUS_ADD < 32'h8000_0000) ? 1'b1 : 1'b0;
wire PLL_RST;
assign PLL_RST = ((fx3_rst)|(!LOCKED));
FX3_IF FX3_IF_inst (
.fx3_bus(fx3_bus),
.fx3_wr(fx3_wr),
.fx3_oe(fx3_oe),
.fx3_cs(fx3_cs),
.fx3_clk(fx3_pclk_100MHz),
.fx3_rdy(fx3_rdy),
.fx3_ack(fx3_ack),
.fx3_rd_finish(fx3_rd_finish),
.fx3_rst(PLL_RST), // PLL is reset first
// .fx3_rst(fx3_rst), // Comment before synthesis and uncomment previous line
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_BYTE_ACCESS(BUS_BYTE_ACCESS),
.FLAG1(FLAG1),
.FLAG2(FLAG2)
);
wire clk40mhz_pll, clk320mhz_pll, clk160mhz_pll, clk16mhz_pll;
wire pll_feedback, LOCKED;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(64), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(10.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(32), // Divide amount for CLKOUT0 (1-128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT1_DIVIDE(4), // Divide amount for CLKOUT0 (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT2_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT3_DIVIDE(80), // Divide amount for CLKOUT0 (1-128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT3_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.DIVCLK_DIVIDE(5), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
PLLE2_BASE_inst (
// Generated 40 MHz clock
.CLKOUT0(clk40mhz_pll),
.CLKOUT1(clk320mhz_pll),
.CLKOUT2(clk160mhz_pll),
.CLKOUT3(clk16mhz_pll),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(pll_feedback),
.LOCKED(LOCKED), // 1-bit output: LOCK
// Input 100 MHz clock
.CLKIN1(BUS_CLK),
// Control Ports
.PWRDWN(0),
.RST(fx3_rst), // Button is active low
// Feedback
.CLKFBIN(pll_feedback)
);
wire clk40mhz, clk320mhz, clk160mhz, clk16mhz;
BUFG BUFG_inst_40 (
.O(clk40mhz), // Clock buffer output
.I(clk40mhz_pll) // Clock buffer input
);
BUFG BUFG_inst_320 (
.O(clk320mhz), // Clock buffer output
.I(clk320mhz_pll) // Clock buffer input
);
BUFG BUFG_inst_160 (
.O(clk160mhz), // Clock buffer output
.I(clk160mhz_pll) // Clock buffer input
);
BUFG BUFG_inst_16 (
.O(clk16mhz), // Clock buffer output
.I(clk16mhz_pll) // Clock buffer input
);
// ------- MODULE ADREESSES ------- //
localparam CMD_BASEADDR = 32'h0000;
localparam CMD_HIGHADDR = 32'h1000-1;
localparam GPIO1_BASEADDR = 32'h1000;
localparam GPIO1_HIGHADDR = 32'h1003;
localparam GPIO2_BASEADDR = 32'h1004;
localparam GPIO2_HIGHADDR = 32'h1007;
localparam FIFO_BASEADDR = 32'h8100;
localparam FIFO_HIGHADDR = 32'h8200-1;
localparam RX4_BASEADDR = 32'h8300;
localparam RX4_HIGHADDR = 32'h8400-1;
localparam RX3_BASEADDR = 32'h8400;
localparam RX3_HIGHADDR = 32'h8500-1;
localparam RX2_BASEADDR = 32'h8500;
localparam RX2_HIGHADDR = 32'h8600-1;
localparam RX1_BASEADDR = 32'h8600;
localparam RX1_HIGHADDR = 32'h8700-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
wire CMD_EXT_START_FLAG;
assign CMD_EXT_START_FLAG = 0;
gpio
#(
.BASEADDR(GPIO1_BASEADDR),
.HIGHADDR(GPIO1_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff),
.IO_TRI(0)
)gpio1(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(led)
);
gpio
#(
.BASEADDR(GPIO2_BASEADDR),
.HIGHADDR(GPIO2_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff),
.IO_TRI(0)
)gpio2(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(PWR_EN[3:0])
);
cmd_seq
#(
.BASEADDR(CMD_BASEADDR),
.HIGHADDR(CMD_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) icmd (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CMD_CLK_OUT(CMD_CLK_OUT),
.CMD_CLK_IN(clk40mhz),
.CMD_EXT_START_FLAG(CMD_EXT_START_FLAG),
.CMD_EXT_START_ENABLE(),
.CMD_DATA(CMD_DATA),
.CMD_READY(),
.CMD_START_FLAG()
);
parameter DSIZE = 10;
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
//assign FIFO_READ = 0;
genvar i;
generate
for (i = 3; i < 4; i = i + 1) begin: rx_gen
fei4_rx
#(
.BASEADDR(RX1_BASEADDR-32'h0100*i),
.HIGHADDR(RX1_HIGHADDR-32'h0100*i),
.DSIZE(DSIZE),
.DATA_IDENTIFIER(i+1),
.ABUSWIDTH(ABUSWIDTH)
) i_fei4_rx (
.RX_CLK(clk160mhz),
.RX_CLK2X(clk320mhz),
.DATA_CLK(clk16mhz),
.RX_DATA(DOBOUT),
.RX_READY(),
.RX_8B10B_DECODER_ERR(),
.RX_FIFO_OVERFLOW_ERR(),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.RX_FIFO_FULL(),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR)
);
end
endgenerate
wire FIFO_NOT_EMPTY, FIFO_FULL, FIFO_NEAR_FULL, FIFO_READ_ERROR;
bram_fifo
#(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(FIFO_NOT_EMPTY),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(FIFO_NEAR_FULL),
.FIFO_READ_ERROR(FIFO_READ_ERROR)
);
//assign led[5] = FIFO_NOT_EMPTY;
//assign led[6] = FIFO_FULL;
//assign led[7] = FIFO_NEAR_FULL;
//assign led[8] = FIFO_READ_ERROR;
/*always @ (posedge BUS_CLK)
begin
if (BUS_RST)
begin
led[5] <= 0;
led[6] <= 0;
led[7] <= 0;
led[8] <= 0;
end
else
begin
if (FIFO_NOT_EMPTY)
led[5] <= 1;
else if (FIFO_FULL)
led[6] <= 1;
else if (FIFO_NEAR_FULL)
led[7] <= 1;
else if (FIFO_READ_ERROR)
led[8] <= 1;
end
end*/
/*
gpio
#(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(32),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(led[8:1])
);
*/
/*Register #(
.REG_SIZE(32),
.ADDRESS(1))
Reg1_inst (
.D(DataIn),
.WR(WR),
.RD(RD),
.Addr(Addr),
.CLK(CLK_100MHz),
.Q(Reg1),
.RB(DataOut),
.RDYB(RDYB),
.RD_VALID_N(ACKB),
.RST(RST)
);
Register #(
.REG_SIZE(32),
.ADDRESS(2))
Reg2_inst (
.D(DataIn),
.WR(WR),
.RD(RD),
.Addr(Addr),
.CLK(CLK_100MHz),
.Q(Reg2),
.RB(DataOut),
.RDYB(RDYB),
.RD_VALID_N(ACKB),
.RST(RST)
);
BRAM_Test #(
.ADDRESS( 32'h10_00_00_00),
.MEM_SIZE(32'h00_00_40_00))
BRAM_Test_inst (
.DataIn(DataIn),
.WR(WR),
.RD(RD),
.CLK(CLK_100MHz),
.DataOut(DataOut),
.Addr(Addr[31:0]),
.RDYB(RDYB),
.RD_VALID_N(ACKB),
// .DMA_RDY(DMA_RDY),
.RST(RST)
);
DDR3_256_8 #(
.ADDRESS( 32'h20_00_00_00),
.MEM_SIZE(32'h10_00_00_00))
DDR3_256_8_inst (
.DataIn(DataIn[31:0]),
.WR(WR),
.RD(RD),
.Addr(Addr[31:0]),
.DataOut(DataOut[31:0]),
.RDY_N(RDYB),
.RD_VALID_N(ACKB),
.CLK_OUT(CLK_100MHz),
.RST(RST),
.Reset_button2(Reset_button2),
.INIT_COMPLETE(INIT_COMPLETE),
.ddr3_dq(ddr3_dq),
.ddr3_addr(ddr3_addr),
// .ddr3_dm(ddr3_dm),
.ddr3_dqs_p(ddr3_dqs_p),
.ddr3_dqs_n(ddr3_dqs_n),
.ddr3_ba(ddr3_ba),
.ddr3_ck_p(ddr3_ck_p),
.ddr3_ck_n(ddr3_ck_n),
.ddr3_ras_n(ddr3_ras_n),
.ddr3_cas_n(ddr3_cas_n),
.ddr3_we_n(ddr3_we_n),
.ddr3_reset_n(ddr3_reset_n),
.ddr3_cke(ddr3_cke),
.ddr3_odt(ddr3_odt),
// .ddr3_cs_n(ddr3_cs_n),
.sys_clk_p(sys_clk_p),
.sys_clk_n(sys_clk_n),
.Clk100(Clk100),
.full_fifo(full_fifo),
// .DMA_RDY(DMA_RDY),
.CS_FX3(CS_FX3),
.FLAG2_reg(FLAG2_reg)
); */
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NAND4_BEHAVIORAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4_BEHAVIORAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "block" *) module Loop_loop_height_eOg_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_eOg_rom.dat", ram0);
$readmemh("./Loop_loop_height_eOg_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_eOg(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_eOg_rom Loop_loop_height_eOg_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
// /___/ /\ Filename : RAMB18E1.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 02/26/08 - Initial version.
// 07/25/08 - Fixed ECC in register mode. (IR 477257)
// 07/30/08 - Updated to support SDP mode with smaller port width <= 18. (IR 477258)
// 11/04/08 - Fixed incorrect output during first clock cycle. (CR 470964)
// 03/11/09 - X's the unused bits of outputs (CR 511363).
// 03/12/09 - Removed parameter from specify block (CR 503821).
// 03/23/09 - Fixed unusual behavior of X's in the unused bits of outputs (CR 513167).
// 04/10/09 - Implemented workaround for NCSim event triggering during initial time (CR 517450).
// 08/03/09 - Updated collision behavior when both clocks are in phase/within 100 ps (CR 522327).
// 08/12/09 - Updated collision address check for none in phase clocks (CR 527010).
// 11/18/09 - Define tasks and functions before calling (CR 532610).
// 12/16/09 - Enhanced memory initialization (CR 540764).
// 03/15/10 - Updated address collision for asynchronous clocks and read first mode (CR 527010).
// 04/01/10 - Fixed clocks detection for collision (CR 552123).
// 05/11/10 - Updated clocks detection for collision (CR 557624).
// - Added attribute RDADDR_COLLISION_HWCONFIG. (CR 557971).
// 05/25/10 - Added WRITE_FIRST support in SDP mode (CR 561807).
// 06/03/10 - Added functionality for attribute RDADDR_COLLISION_HWCONFIG (CR 557971).
// 07/08/10 - Added SIM_DEVICE attribute (CR 567633).
// 07/09/10 - Initialized memory to zero for INIT_FILE (CR 560672).
// 08/09/10 - Updated the model according to new address collision/overlap tables (CR 566507).
// 09/16/10 - Updated from bit to bus timing (CR 575523).
// 10/14/10 - Removed NO_CHANGE support in SDP mode (CR 575924).
// 10/15/10 - Updated 7SERIES address overlap and address collision (CR 575953).
// 12/10/10 - Converted parameter to wire in specify block (CR 574534).
// 03/16/11 - Changed synchronous clock skew to 50ps for 7 series(CR 588053).
// 08/04/11 - Fixed address overlap when clocks are within 100ps (CR 611004).
// 09/12/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap (CR 621942).
// 09/28/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap, part 2 (CR 621942).
// 10/11/11 - Fixed collision with clocks rise at the same time (CR 628129).
// 10/17/11 - Fixed collision with clocks within 100ps in SDP mode (CR 620844).
// 10/28/11 - Removed all mention of internal block ram from messaging (CR 569190).
// 11/04/11 - Fixed collision with clock within 100ps in TDP mode (CR 627670).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 02/05/12 - Fixed read width function when READ_WIDTH_A/B = 0 (CR 643482).
// 02/22/12 - Fixed mem/memp out of bounds warning messages (CR 584399).
// 03/06/12 - Fixed hierarchical error from CR 584399 (CR 648454).
// 03/15/12 - Reverted CR 584399 (CR 651279).
// 02/15/13 - Updated collision check to use clock period or 3ns (CR 694934).
// 07/25/13 - Added invertible pins support (CR 715417).
// 09/04/13 - Removed warning for memp (CR 728988).
// 03/24/14 - Balanced all iniputs with xor (CR778933).
// 08/29/14 - Added negative timing check (CR 821138).
// 09/05/14 - Fixed timing check (CR 822107)
// 10/01/14 - Updated conditional timing check for IS_INVERTED parameter.
// 10/22/14 - Added #1 to $finish (CR 808642).
// 01/21/15 - SIM_DEVICE defaulted to 7SERIES (PR 841966).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module RAMB18E1 (DOADO, DOBDO, DOPADOP, DOPBDOP,
ADDRARDADDR, ADDRBWRADDR, CLKARDCLK, CLKBWRCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENARDEN, ENBWREN, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, WEA, WEBWE);
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [17:0] INIT_A = 18'h0;
parameter [17:0] INIT_B = 18'h0;
parameter INIT_FILE = "NONE";
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter RAM_MODE = "TDP";
parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_DEVICE = "7SERIES";
parameter [17:0] SRVAL_A = 18'h0;
parameter [17:0] SRVAL_B = 18'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
localparam SETUP_ALL = 1000;
localparam SETUP_READ_FIRST = 3000;
output [15:0] DOADO;
output [15:0] DOBDO;
output [1:0] DOPADOP;
output [1:0] DOPBDOP;
input CLKARDCLK;
input CLKBWRCLK;
input ENARDEN;
input ENBWREN;
input REGCEAREGCE;
input REGCEB;
input RSTRAMARSTRAM;
input RSTRAMB;
input RSTREGARSTREG;
input RSTREGB;
input [13:0] ADDRARDADDR;
input [13:0] ADDRBWRADDR;
input [15:0] DIADI;
input [15:0] DIBDI;
input [1:0] DIPADIP;
input [1:0] DIPBDIP;
input [1:0] WEA;
input [3:0] WEBWE;
tri0 GSR = glbl.GSR;
wire [7:0] dangle_out8;
wire dangle_out;
wire [1:0] dangle_out2;
wire [3:0] dangle_out4;
wire [5:0] dangle_out6;
wire [8:0] dangle_out9;
wire [15:0] dangle_out16;
wire [31:0] dangle_out32;
wire [47:0] dangle_out48;
wire [15:0] doado_wire, dobdo_wire;
wire [1:0] dopadop_wire, dopbdop_wire;
reg [15:0] doado_out, dobdo_out;
reg [1:0] dopadop_out, dopbdop_out;
reg notifier, notifier_a, notifier_b;
reg notifier_addra0, notifier_addra1, notifier_addra2, notifier_addra3, notifier_addra4;
reg notifier_addra5, notifier_addra6, notifier_addra7, notifier_addra8, notifier_addra9;
reg notifier_addra10, notifier_addra11, notifier_addra12, notifier_addra13;
reg notifier_addrb0, notifier_addrb1, notifier_addrb2, notifier_addrb3, notifier_addrb4;
reg notifier_addrb5, notifier_addrb6, notifier_addrb7, notifier_addrb8, notifier_addrb9;
reg notifier_addrb10, notifier_addrb11, notifier_addrb12, notifier_addrb13;
reg attr_err = 1'b0;
wire regcearegce_in;
wire regceb_in;
wire [13:0] addrardaddr_in;
wire [13:0] addrbwraddr_in;
wire [15:0] diadi_in;
wire [15:0] dibdi_in;
wire [1:0] dipadip_in;
wire [1:0] dipbdip_in;
wire [1:0] wea_in;
wire [3:0] webwe_in;
wire clkardclk_in;
wire clkbwrclk_in;
wire enarden_in;
wire enbwren_in;
wire rstramarstram_in;
wire rstramb_in;
wire rstregarstreg_in;
wire rstregb_in;
`ifdef XIL_TIMING
wire CLKARDCLK_delay;
wire CLKBWRCLK_delay;
wire ENARDEN_delay;
wire ENBWREN_delay;
wire REGCEAREGCE_delay;
wire REGCEB_delay;
wire RSTRAMARSTRAM_delay;
wire RSTRAMB_delay;
wire RSTREGARSTREG_delay;
wire RSTREGB_delay;
wire [13:0] ADDRARDADDR_delay;
wire [13:0] ADDRBWRADDR_delay;
wire [15:0] DIADI_delay;
wire [15:0] DIBDI_delay;
wire [1:0] DIPADIP_delay;
wire [1:0] DIPBDIP_delay;
wire [1:0] WEA_delay;
wire [3:0] WEBWE_delay;
`endif
`ifdef XIL_TIMING
assign regcearegce_in = REGCEAREGCE_delay;
assign regceb_in = REGCEB_delay;
assign addrardaddr_in = ADDRARDADDR_delay;
assign addrbwraddr_in = ADDRBWRADDR_delay;
assign diadi_in = DIADI_delay;
assign dibdi_in = DIBDI_delay;
assign dipadip_in = DIPADIP_delay;
assign dipbdip_in = DIPBDIP_delay;
assign wea_in = WEA_delay;
assign webwe_in = WEBWE_delay;
assign clkardclk_in = CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED;
assign clkbwrclk_in = CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED;
assign enarden_in = ENARDEN_delay ^ IS_ENARDEN_INVERTED;
assign enbwren_in = ENBWREN_delay ^ IS_ENBWREN_INVERTED;
assign rstramarstram_in = RSTRAMARSTRAM_delay ^ IS_RSTRAMARSTRAM_INVERTED;
assign rstramb_in = RSTRAMB_delay ^ IS_RSTRAMB_INVERTED;
assign rstregarstreg_in = RSTREGARSTREG_delay ^ IS_RSTREGARSTREG_INVERTED;
assign rstregb_in = RSTREGB_delay ^ IS_RSTREGB_INVERTED;
`else
assign regcearegce_in = REGCEAREGCE;
assign regceb_in = REGCEB;
assign addrardaddr_in = ADDRARDADDR;
assign addrbwraddr_in = ADDRBWRADDR;
assign diadi_in = DIADI;
assign dibdi_in = DIBDI;
assign dipadip_in = DIPADIP;
assign dipbdip_in = DIPBDIP;
assign wea_in = WEA;
assign webwe_in = WEBWE;
assign clkardclk_in = CLKARDCLK ^ IS_CLKARDCLK_INVERTED;
assign clkbwrclk_in = CLKBWRCLK ^ IS_CLKBWRCLK_INVERTED;
assign enarden_in = ENARDEN ^ IS_ENARDEN_INVERTED;
assign enbwren_in = ENBWREN ^ IS_ENBWREN_INVERTED;
assign rstramarstram_in = RSTRAMARSTRAM ^ IS_RSTRAMARSTRAM_INVERTED;
assign rstramb_in = RSTRAMB ^ IS_RSTRAMB_INVERTED;
assign rstregarstreg_in = RSTREGARSTREG ^ IS_RSTREGARSTREG_INVERTED;
assign rstregb_in = RSTREGB ^ IS_RSTREGB_INVERTED;
`endif
initial begin
if (!((IS_CLKARDCLK_INVERTED >= 1'b0) && (IS_CLKARDCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_CLKARDCLK_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKARDCLK_INVERTED);
attr_err = 1'b1;
end
if (!((IS_CLKBWRCLK_INVERTED >= 1'b0) && (IS_CLKBWRCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_CLKBWRCLK_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKBWRCLK_INVERTED);
attr_err = 1'b1;
end
if (!((IS_ENARDEN_INVERTED >= 1'b0) && (IS_ENARDEN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_ENARDEN_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENARDEN_INVERTED);
attr_err = 1'b1;
end
if (!((IS_ENBWREN_INVERTED >= 1'b0) && (IS_ENBWREN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_ENBWREN_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENBWREN_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTRAMARSTRAM_INVERTED >= 1'b0) && (IS_RSTRAMARSTRAM_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTRAMARSTRAM_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMARSTRAM_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTRAMB_INVERTED >= 1'b0) && (IS_RSTRAMB_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTRAMB_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMB_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTREGARSTREG_INVERTED >= 1'b0) && (IS_RSTREGARSTREG_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTREGARSTREG_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGARSTREG_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTREGB_INVERTED >= 1'b0) && (IS_RSTREGB_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTREGB_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGB_INVERTED);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end // initial begin
// special handle for sdp width = 36
localparam [35:0] init_sdp = (READ_WIDTH_A == 36) ? {INIT_B[17:16],INIT_A[17:16],INIT_B[15:0],INIT_A[15:0]} : {INIT_B, INIT_A};
localparam [35:0] srval_sdp = (READ_WIDTH_A == 36) ? {SRVAL_B[17:16],SRVAL_A[17:16],SRVAL_B[15:0],SRVAL_A[15:0]} : {SRVAL_B, SRVAL_A};
generate
case (RAM_MODE)
"TDP" : begin : gen_tdp
RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_FILE(INIT_FILE),
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.SETUP_ALL(SETUP_ALL),
.SETUP_READ_FIRST(SETUP_READ_FIRST),
.SIM_COLLISION_CHECK(SIM_COLLISION_CHECK),
.SIM_DEVICE(SIM_DEVICE),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.BRAM_SIZE(18),
.INIT_00(INIT_00),
.INIT_01(INIT_01),
.INIT_02(INIT_02),
.INIT_03(INIT_03),
.INIT_04(INIT_04),
.INIT_05(INIT_05),
.INIT_06(INIT_06),
.INIT_07(INIT_07),
.INIT_08(INIT_08),
.INIT_09(INIT_09),
.INIT_0A(INIT_0A),
.INIT_0B(INIT_0B),
.INIT_0C(INIT_0C),
.INIT_0D(INIT_0D),
.INIT_0E(INIT_0E),
.INIT_0F(INIT_0F),
.INIT_10(INIT_10),
.INIT_11(INIT_11),
.INIT_12(INIT_12),
.INIT_13(INIT_13),
.INIT_14(INIT_14),
.INIT_15(INIT_15),
.INIT_16(INIT_16),
.INIT_17(INIT_17),
.INIT_18(INIT_18),
.INIT_19(INIT_19),
.INIT_1A(INIT_1A),
.INIT_1B(INIT_1B),
.INIT_1C(INIT_1C),
.INIT_1D(INIT_1D),
.INIT_1E(INIT_1E),
.INIT_1F(INIT_1F),
.INIT_20(INIT_20),
.INIT_21(INIT_21),
.INIT_22(INIT_22),
.INIT_23(INIT_23),
.INIT_24(INIT_24),
.INIT_25(INIT_25),
.INIT_26(INIT_26),
.INIT_27(INIT_27),
.INIT_28(INIT_28),
.INIT_29(INIT_29),
.INIT_2A(INIT_2A),
.INIT_2B(INIT_2B),
.INIT_2C(INIT_2C),
.INIT_2D(INIT_2D),
.INIT_2E(INIT_2E),
.INIT_2F(INIT_2F),
.INIT_30(INIT_30),
.INIT_31(INIT_31),
.INIT_32(INIT_32),
.INIT_33(INIT_33),
.INIT_34(INIT_34),
.INIT_35(INIT_35),
.INIT_36(INIT_36),
.INIT_37(INIT_37),
.INIT_38(INIT_38),
.INIT_39(INIT_39),
.INIT_3A(INIT_3A),
.INIT_3B(INIT_3B),
.INIT_3C(INIT_3C),
.INIT_3D(INIT_3D),
.INIT_3E(INIT_3E),
.INIT_3F(INIT_3F),
.INITP_00(INITP_00),
.INITP_01(INITP_01),
.INITP_02(INITP_02),
.INITP_03(INITP_03),
.INITP_04(INITP_04),
.INITP_05(INITP_05),
.INITP_06(INITP_06),
.INITP_07(INITP_07))
INT_RAMB_TDP (.ADDRA({2'b0,addrardaddr_in}),
.ADDRB({2'b0,addrbwraddr_in}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(dangle_out),
.CASCADEOUTB(dangle_out),
.CLKA(clkardclk_in),
.CLKB(clkbwrclk_in),
.DBITERR(dangle_out),
.DIA({48'b0,diadi_in}),
.DIB({48'b0,dibdi_in}),
.DIPA({2'b0,dipadip_in}),
.DIPB({6'b0,dipbdip_in}),
.DOA({dangle_out48,doado_wire}),
.DOB({dangle_out16,dobdo_wire}),
.DOPA({dangle_out6,dopadop_wire}),
.DOPB({dangle_out2,dopbdop_wire}),
.ECCPARITY(dangle_out8),
.ENA(enarden_in),
.ENB(enbwren_in),
.GSR(GSR),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(dangle_out9),
.REGCEA(regcearegce_in),
.REGCEB(regceb_in),
.RSTRAMA(rstramarstram_in),
.RSTRAMB(rstramb_in),
.RSTREGA(rstregarstreg_in),
.RSTREGB(rstregb_in),
.SBITERR(dangle_out),
.WEA({4{wea_in}}),
.WEB({2{webwe_in}}));
end // case: "TDP"
"SDP" : begin : gen_sdp
if (WRITE_WIDTH_B == 36) begin : gen_wide
RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE),
.INIT_A({36'b0,init_sdp}),
.INIT_B({36'b0,init_sdp}),
.INIT_FILE(INIT_FILE),
.SRVAL_A({36'b0,{srval_sdp}}),
.SRVAL_B({36'b0,{srval_sdp}}),
.RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_A),
.WRITE_WIDTH_A(WRITE_WIDTH_B),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.SETUP_ALL(SETUP_ALL),
.SETUP_READ_FIRST(SETUP_READ_FIRST),
.SIM_COLLISION_CHECK(SIM_COLLISION_CHECK),
.SIM_DEVICE(SIM_DEVICE),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.BRAM_SIZE(18),
.INIT_00(INIT_00),
.INIT_01(INIT_01),
.INIT_02(INIT_02),
.INIT_03(INIT_03),
.INIT_04(INIT_04),
.INIT_05(INIT_05),
.INIT_06(INIT_06),
.INIT_07(INIT_07),
.INIT_08(INIT_08),
.INIT_09(INIT_09),
.INIT_0A(INIT_0A),
.INIT_0B(INIT_0B),
.INIT_0C(INIT_0C),
.INIT_0D(INIT_0D),
.INIT_0E(INIT_0E),
.INIT_0F(INIT_0F),
.INIT_10(INIT_10),
.INIT_11(INIT_11),
.INIT_12(INIT_12),
.INIT_13(INIT_13),
.INIT_14(INIT_14),
.INIT_15(INIT_15),
.INIT_16(INIT_16),
.INIT_17(INIT_17),
.INIT_18(INIT_18),
.INIT_19(INIT_19),
.INIT_1A(INIT_1A),
.INIT_1B(INIT_1B),
.INIT_1C(INIT_1C),
.INIT_1D(INIT_1D),
.INIT_1E(INIT_1E),
.INIT_1F(INIT_1F),
.INIT_20(INIT_20),
.INIT_21(INIT_21),
.INIT_22(INIT_22),
.INIT_23(INIT_23),
.INIT_24(INIT_24),
.INIT_25(INIT_25),
.INIT_26(INIT_26),
.INIT_27(INIT_27),
.INIT_28(INIT_28),
.INIT_29(INIT_29),
.INIT_2A(INIT_2A),
.INIT_2B(INIT_2B),
.INIT_2C(INIT_2C),
.INIT_2D(INIT_2D),
.INIT_2E(INIT_2E),
.INIT_2F(INIT_2F),
.INIT_30(INIT_30),
.INIT_31(INIT_31),
.INIT_32(INIT_32),
.INIT_33(INIT_33),
.INIT_34(INIT_34),
.INIT_35(INIT_35),
.INIT_36(INIT_36),
.INIT_37(INIT_37),
.INIT_38(INIT_38),
.INIT_39(INIT_39),
.INIT_3A(INIT_3A),
.INIT_3B(INIT_3B),
.INIT_3C(INIT_3C),
.INIT_3D(INIT_3D),
.INIT_3E(INIT_3E),
.INIT_3F(INIT_3F),
.INITP_00(INITP_00),
.INITP_01(INITP_01),
.INITP_02(INITP_02),
.INITP_03(INITP_03),
.INITP_04(INITP_04),
.INITP_05(INITP_05),
.INITP_06(INITP_06),
.INITP_07(INITP_07))
INT_RAMB_SDP (.ADDRA({2'b0,addrardaddr_in}),
.ADDRB({2'b0,addrbwraddr_in}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(dangle_out),
.CASCADEOUTB(dangle_out),
.CLKA(clkardclk_in),
.CLKB(clkbwrclk_in),
.DBITERR(dangle_out),
.DIA(64'b0),
.DIB({32'b0,dibdi_in,diadi_in}),
.DIPA(4'b0),
.DIPB({4'b0,dipbdip_in,dipadip_in}),
.DOA({dangle_out32,dobdo_wire,doado_wire}),
.DOB(dangle_out32),
.DOPA({dangle_out4,dopbdop_wire,dopadop_wire}),
.DOPB(dangle_out4),
.ECCPARITY(dangle_out8),
.ENA(enarden_in),
.ENB(enbwren_in),
.GSR(GSR),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(dangle_out9),
.REGCEA(regcearegce_in),
.REGCEB(regceb_in),
.RSTRAMA(rstramarstram_in),
.RSTRAMB(rstramb_in),
.RSTREGA(rstregarstreg_in),
.RSTREGB(rstregb_in),
.SBITERR(dangle_out),
.WEA(8'b0),
.WEB({2{webwe_in}}));
end // if (WRITE_WIDTH_B == 36)
else begin : gen_narrow
RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE),
.INIT_A({36'b0,init_sdp}),
.INIT_B({36'b0,init_sdp}),
.INIT_FILE(INIT_FILE),
.SRVAL_A({36'b0,{srval_sdp}}),
.SRVAL_B({36'b0,{srval_sdp}}),
.RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_A),
.WRITE_WIDTH_A(WRITE_WIDTH_B),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.SETUP_ALL(SETUP_ALL),
.SETUP_READ_FIRST(SETUP_READ_FIRST),
.SIM_COLLISION_CHECK(SIM_COLLISION_CHECK),
.SIM_DEVICE(SIM_DEVICE),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.BRAM_SIZE(18),
.INIT_00(INIT_00),
.INIT_01(INIT_01),
.INIT_02(INIT_02),
.INIT_03(INIT_03),
.INIT_04(INIT_04),
.INIT_05(INIT_05),
.INIT_06(INIT_06),
.INIT_07(INIT_07),
.INIT_08(INIT_08),
.INIT_09(INIT_09),
.INIT_0A(INIT_0A),
.INIT_0B(INIT_0B),
.INIT_0C(INIT_0C),
.INIT_0D(INIT_0D),
.INIT_0E(INIT_0E),
.INIT_0F(INIT_0F),
.INIT_10(INIT_10),
.INIT_11(INIT_11),
.INIT_12(INIT_12),
.INIT_13(INIT_13),
.INIT_14(INIT_14),
.INIT_15(INIT_15),
.INIT_16(INIT_16),
.INIT_17(INIT_17),
.INIT_18(INIT_18),
.INIT_19(INIT_19),
.INIT_1A(INIT_1A),
.INIT_1B(INIT_1B),
.INIT_1C(INIT_1C),
.INIT_1D(INIT_1D),
.INIT_1E(INIT_1E),
.INIT_1F(INIT_1F),
.INIT_20(INIT_20),
.INIT_21(INIT_21),
.INIT_22(INIT_22),
.INIT_23(INIT_23),
.INIT_24(INIT_24),
.INIT_25(INIT_25),
.INIT_26(INIT_26),
.INIT_27(INIT_27),
.INIT_28(INIT_28),
.INIT_29(INIT_29),
.INIT_2A(INIT_2A),
.INIT_2B(INIT_2B),
.INIT_2C(INIT_2C),
.INIT_2D(INIT_2D),
.INIT_2E(INIT_2E),
.INIT_2F(INIT_2F),
.INIT_30(INIT_30),
.INIT_31(INIT_31),
.INIT_32(INIT_32),
.INIT_33(INIT_33),
.INIT_34(INIT_34),
.INIT_35(INIT_35),
.INIT_36(INIT_36),
.INIT_37(INIT_37),
.INIT_38(INIT_38),
.INIT_39(INIT_39),
.INIT_3A(INIT_3A),
.INIT_3B(INIT_3B),
.INIT_3C(INIT_3C),
.INIT_3D(INIT_3D),
.INIT_3E(INIT_3E),
.INIT_3F(INIT_3F),
.INITP_00(INITP_00),
.INITP_01(INITP_01),
.INITP_02(INITP_02),
.INITP_03(INITP_03),
.INITP_04(INITP_04),
.INITP_05(INITP_05),
.INITP_06(INITP_06),
.INITP_07(INITP_07))
INT_RAMB_SDP (.ADDRA({2'b0,addrardaddr_in}),
.ADDRB({2'b0,addrbwraddr_in}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(dangle_out),
.CASCADEOUTB(dangle_out),
.CLKA(clkardclk_in),
.CLKB(clkbwrclk_in),
.DBITERR(dangle_out),
.DIA(64'b0),
.DIB({48'b0,dibdi_in}),
.DIPA(4'b0),
.DIPB({6'b0,dipbdip_in}),
.DOA({dangle_out32,dobdo_wire,doado_wire}),
.DOB(dangle_out32),
.DOPA({dangle_out4,dopbdop_wire,dopadop_wire}),
.DOPB(dangle_out4),
.ECCPARITY(dangle_out8),
.ENA(enarden_in),
.ENB(enbwren_in),
.GSR(GSR),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(dangle_out9),
.REGCEA(regcearegce_in),
.REGCEB(regceb_in),
.RSTRAMA(rstramarstram_in),
.RSTRAMB(rstramb_in),
.RSTREGA(rstregarstreg_in),
.RSTREGB(rstregb_in),
.SBITERR(dangle_out),
.WEA(8'b0),
.WEB({2{webwe_in}}));
end // else: !if(WRITE_WIDTH_B == 36)
end // case: "SDP"
endcase // case(RAM_MODE)
endgenerate
//*** Timing Checks Start here
reg [15:0] DOADO_out;
reg [15:0] DOBDO_out;
reg [1:0] DOPADOP_out;
reg [1:0] DOPBDOP_out;
assign DOADO = DOADO_out;
assign DOBDO = DOBDO_out;
assign DOPADOP = DOPADOP_out;
assign DOPBDOP = DOPBDOP_out;
always @(doado_wire or rstramb_in or GSR) DOADO_out = doado_wire;
always @(dobdo_wire or rstramb_in or GSR) DOBDO_out = dobdo_wire;
always @(dopadop_wire or rstramb_in or GSR) DOPADOP_out = dopadop_wire;
always @(dopbdop_wire or rstramb_in or GSR) DOPBDOP_out = dopbdop_wire;
`ifdef XIL_TIMING
wire clkardclk_en_n;
wire clkardclk_en_p;
wire clkbwrclk_en_n;
wire clkbwrclk_en_p;
assign clkardclk_en_n = IS_CLKARDCLK_INVERTED;
assign clkardclk_en_p = ~IS_CLKARDCLK_INVERTED;
assign clkbwrclk_en_n = IS_CLKBWRCLK_INVERTED;
assign clkbwrclk_en_p = ~IS_CLKBWRCLK_INVERTED;
wire enarden_clka_n = enarden_in && clkardclk_en_n;
wire enarden_clka_p = enarden_in && clkardclk_en_p;
wire enbwren_clkb_n = enbwren_in && clkbwrclk_en_n;
wire enbwren_clkb_p = enbwren_in && clkbwrclk_en_p;
wire diadi0_enable_n = (RAM_MODE == "TDP") && enarden_in && wea_in[0] && clkardclk_en_n;
wire diadi0_enable_p = (RAM_MODE == "TDP") && enarden_in && wea_in[0] && clkardclk_en_p;
wire dibdi0_enable_n = (RAM_MODE == "TDP") ? (enbwren_in && webwe_in[0] && clkbwrclk_en_n) : (enbwren_in && webwe_in[2] && clkbwrclk_en_n) ;
wire dibdi0_enable_p = (RAM_MODE == "TDP") ? (enbwren_in && webwe_in[0] && clkbwrclk_en_p) : (enbwren_in && webwe_in[2] && clkbwrclk_en_p) ;
wire sdp_dia0_clkwr_n = (RAM_MODE == "SDP") && enbwren_in && webwe_in[0] && clkbwrclk_en_n;
wire sdp_dia0_clkwr_p = (RAM_MODE == "SDP") && enbwren_in && webwe_in[0] && clkbwrclk_en_p;
always @(notifier or notifier_a or notifier_addra0 or notifier_addra1 or notifier_addra2 or notifier_addra3 or notifier_addra4 or
notifier_addra5 or notifier_addra6 or notifier_addra7 or notifier_addra8 or notifier_addra9 or notifier_addra10 or
notifier_addra11 or notifier_addra12 or notifier_addra13) begin
doado_out <= 16'hxxxx;
dopadop_out <= 2'bxx;
end
always @(notifier or notifier_b or notifier_addrb0 or notifier_addrb1 or notifier_addrb2 or notifier_addrb3 or notifier_addrb4 or
notifier_addrb5 or notifier_addrb6 or notifier_addrb7 or notifier_addrb8 or notifier_addrb9 or notifier_addrb10 or
notifier_addrb11 or notifier_addrb12 or notifier_addrb13) begin
dobdo_out <= 16'hxxxx;
dopbdop_out <= 2'bxx;
if (RAM_MODE == "SDP") begin
doado_out <= 16'hxxxx;
dopadop_out <= 2'bxx;
end
end
always @(notifier_addra0) begin
task_warn_msg ("ADDRARDADDR[0]", "CLKARDCLK");
end
always @(notifier_addra1) begin
task_warn_msg ("ADDRARDADDR[1]", "CLKARDCLK");
end
always @(notifier_addra2) begin
task_warn_msg ("ADDRARDADDR[2]", "CLKARDCLK");
end
always @(notifier_addra3) begin
task_warn_msg ("ADDRARDADDR[3]", "CLKARDCLK");
end
always @(notifier_addra4) begin
task_warn_msg ("ADDRARDADDR[4]", "CLKARDCLK");
end
always @(notifier_addra5) begin
task_warn_msg ("ADDRARDADDR[5]", "CLKARDCLK");
end
always @(notifier_addra6) begin
task_warn_msg ("ADDRARDADDR[6]", "CLKARDCLK");
end
always @(notifier_addra7) begin
task_warn_msg ("ADDRARDADDR[7]", "CLKARDCLK");
end
always @(notifier_addra8) begin
task_warn_msg ("ADDRARDADDR[8]", "CLKARDCLK");
end
always @(notifier_addra9) begin
task_warn_msg ("ADDRARDADDR[9]", "CLKARDCLK");
end
always @(notifier_addra10) begin
task_warn_msg ("ADDRARDADDR[10]", "CLKARDCLK");
end
always @(notifier_addra11) begin
task_warn_msg ("ADDRARDADDR[11]", "CLKARDCLK");
end
always @(notifier_addra12) begin
task_warn_msg ("ADDRARDADDR[12]", "CLKARDCLK");
end
always @(notifier_addra13) begin
task_warn_msg ("ADDRARDADDR[13]", "CLKARDCLK");
end
always @(notifier_addrb0) begin
task_warn_msg ("ADDRBWRADDR[0]", "CLKBWRCLK");
end
always @(notifier_addrb1) begin
task_warn_msg ("ADDRBWRADDR[1]", "CLKBWRCLK");
end
always @(notifier_addrb2) begin
task_warn_msg ("ADDRBWRADDR[2]", "CLKBWRCLK");
end
always @(notifier_addrb3) begin
task_warn_msg ("ADDRBWRADDR[3]", "CLKBWRCLK");
end
always @(notifier_addrb4) begin
task_warn_msg ("ADDRBWRADDR[4]", "CLKBWRCLK");
end
always @(notifier_addrb5) begin
task_warn_msg ("ADDRBWRADDR[5]", "CLKBWRCLK");
end
always @(notifier_addrb6) begin
task_warn_msg ("ADDRBWRADDR[6]", "CLKBWRCLK");
end
always @(notifier_addrb7) begin
task_warn_msg ("ADDRBWRADDR[7]", "CLKBWRCLK");
end
always @(notifier_addrb8) begin
task_warn_msg ("ADDRBWRADDR[8]", "CLKBWRCLK");
end
always @(notifier_addrb9) begin
task_warn_msg ("ADDRBWRADDR[9]", "CLKBWRCLK");
end
always @(notifier_addrb10) begin
task_warn_msg ("ADDRBWRADDR[10]", "CLKBWRCLK");
end
always @(notifier_addrb11) begin
task_warn_msg ("ADDRBWRADDR[11]", "CLKBWRCLK");
end
always @(notifier_addrb12) begin
task_warn_msg ("ADDRBWRADDR[12]", "CLKBWRCLK");
end
always @(notifier_addrb13) begin
task_warn_msg ("ADDRBWRADDR[13]", "CLKBWRCLK");
end
task task_warn_msg;
input [8*15:1] addr_str;
input [8*9:1] clk_str;
begin
$display("Error: Setup/Hold Violation on %s with respect to %s when memory has been enabled. The memory contents at %s of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.", addr_str, clk_str, addr_str);
end
endtask // task_warn_msg
`endif // `ifdef XIL_TIMING
wire ram_mode_wire = (RAM_MODE == "TDP") ? 1 : 0;
specify
(CLKARDCLK *> DOADO) = (100:100:100, 100:100:100);
(CLKARDCLK *> DOPADOP) = (100:100:100, 100:100:100);
if (ram_mode_wire == 0) (CLKARDCLK *> DOBDO) = (100:100:100, 100:100:100);
if (ram_mode_wire == 0) (CLKARDCLK *> DOPBDOP) = (100:100:100, 100:100:100);
if (ram_mode_wire == 1) (CLKBWRCLK *> DOBDO) = (100:100:100, 100:100:100);
if (ram_mode_wire == 1) (CLKBWRCLK *> DOPBDOP) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$setuphold (posedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKARDCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIADI_delay);
$setuphold (posedge CLKARDCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIADI_delay);
$setuphold (posedge CLKARDCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIPADIP_delay);
$setuphold (posedge CLKARDCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIPADIP_delay);
$setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, WEA_delay);
$setuphold (posedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, WEA_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKBWRCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIADI_delay);
$setuphold (posedge CLKBWRCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIADI_delay);
$setuphold (posedge CLKBWRCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIPADIP_delay);
$setuphold (posedge CLKBWRCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIPADIP_delay);
$setuphold (posedge CLKBWRCLK, posedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIBDI_delay);
$setuphold (posedge CLKBWRCLK, negedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIBDI_delay);
$setuphold (posedge CLKBWRCLK, posedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIPBDIP_delay);
$setuphold (posedge CLKBWRCLK, negedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIPBDIP_delay);
$setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (posedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKARDCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIADI_delay);
$setuphold (negedge CLKARDCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIADI_delay);
$setuphold (negedge CLKARDCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIPADIP_delay);
$setuphold (negedge CLKARDCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIPADIP_delay);
$setuphold (negedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, WEA_delay);
$setuphold (negedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, WEA_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKBWRCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIADI_delay);
$setuphold (negedge CLKBWRCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIADI_delay);
$setuphold (negedge CLKBWRCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIPADIP_delay);
$setuphold (negedge CLKBWRCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIPADIP_delay);
$setuphold (negedge CLKBWRCLK, posedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIBDI_delay);
$setuphold (negedge CLKBWRCLK, negedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIBDI_delay);
$setuphold (negedge CLKBWRCLK, posedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIPBDIP_delay);
$setuphold (negedge CLKBWRCLK, negedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIPBDIP_delay);
$setuphold (negedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (negedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (negedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, WEBWE_delay);
$period (negedge CLKARDCLK, 0:0:0, notifier_a);
$period (negedge CLKBWRCLK, 0:0:0, notifier_b);
$period (posedge CLKARDCLK, 0:0:0, notifier_a);
$period (posedge CLKBWRCLK, 0:0:0, notifier_b);
$width (posedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a);
$width (negedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a);
$width (posedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b);
$width (negedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // RAMB18E1
// WARNING !!!: The following model is not an user primitive.
// Please do not modify any part of it. RAMB18E1 may not work properly if do so.
//
`timescale 1 ps/1 ps
module RB18_INTERNAL_VLOG (CASCADEOUTA, CASCADEOUTB, DBITERR, DOA, DOB, DOPA, DOPB, ECCPARITY, RDADDRECC, SBITERR,
ADDRA, ADDRB, CASCADEINA, CASCADEINB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, GSR, INJECTDBITERR, INJECTSBITERR, REGCEA, REGCEB, RSTRAMA, RSTRAMB, RSTREGA, RSTREGB, WEA, WEB);
output CASCADEOUTA;
output CASCADEOUTB;
output DBITERR;
output SBITERR;
output [8:0] RDADDRECC;
output reg [63:0] DOA;
output reg [31:0] DOB;
output reg [7:0] DOPA;
output reg [3:0] DOPB;
output [7:0] ECCPARITY;
input ENA, CLKA, CASCADEINA, REGCEA;
input ENB, CLKB, CASCADEINB, REGCEB;
input GSR;
input RSTRAMA, RSTRAMB;
input RSTREGA, RSTREGB;
input INJECTDBITERR, INJECTSBITERR;
input [15:0] ADDRA;
input [15:0] ADDRB;
input [63:0] DIA;
input [63:0] DIB;
input [3:0] DIPA;
input [7:0] DIPB;
input [7:0] WEA;
input [7:0] WEB;
parameter DOA_REG = 0;
parameter DOB_REG = 0;
parameter EN_ECC_READ = "FALSE";
parameter EN_ECC_WRITE = "FALSE";
parameter [71:0] INIT_A = 72'h0;
parameter [71:0] INIT_B = 72'h0;
parameter RAM_EXTENSION_A = "NONE";
parameter RAM_EXTENSION_B = "NONE";
parameter RAM_MODE = "TDP";
parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter SETUP_ALL = 1000;
parameter SETUP_READ_FIRST = 3000;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_DEVICE = "7SERIES";
parameter [71:0] SRVAL_A = 72'h0;
parameter [71:0] SRVAL_B = 72'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
parameter INIT_FILE = "NONE";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
// xilinx_internal_parameter on
// WARNING !!!: This model may not work properly if the following parameters are changed.
parameter BRAM_SIZE = 36;
// xilinx_internal_parameter off
integer count, countp, init_mult, initp_mult, large_width;
integer count1, countp1, i, i1, j, j1, i_p, i_mem, init_offset, initp_offset;
integer viol_time = 0;
integer rdaddr_collision_hwconfig_int, rstreg_priority_a_int, rstreg_priority_b_int;
integer ram_mode_int, en_ecc_write_int, en_ecc_read_int;
integer chk_ox_same_clk = 0, chk_ox_msg = 0, chk_col_same_clk = 0;
reg addra_in_15_reg_bram, addrb_in_15_reg_bram;
reg addra_in_15_reg, addrb_in_15_reg;
reg addra_in_15_reg1, addrb_in_15_reg1;
reg junk1;
reg [1:0] wr_mode_a, wr_mode_b, cascade_a, cascade_b;
reg [63:0] doa_out = 64'b0, doa_buf = 64'b0, doa_outreg = 64'b0;
reg [31:0] dob_out = 32'b0, dob_buf = 32'b0, dob_outreg = 32'b0;
reg [3:0] dopb_out = 4'b0, dopb_buf = 4'b0, dopb_outreg = 4'b0;
reg [7:0] dopa_out = 8'b0, dopa_buf = 8'b0, dopa_outreg = 8'b0;
reg [63:0] doa_out_mux = 64'b0, doa_outreg_mux = 64'b0;
reg [7:0] dopa_out_mux = 8'b0, dopa_outreg_mux = 8'b0;
reg [63:0] dob_out_mux = 64'b0, dob_outreg_mux = 64'b0;
reg [7:0] dopb_out_mux = 8'b0, dopb_outreg_mux = 8'b0;
reg [7:0] eccparity_out = 8'b0;
reg [7:0] dopr_ecc, syndrome = 8'b0;
reg [7:0] dipb_in_ecc;
reg [71:0] ecc_bit_position;
reg [7:0] dip_ecc, dip_ecc_col, dipa_in_ecc_corrected;
reg [63:0] dib_in_ecc, dib_ecc_col, dia_in_ecc_corrected, di_x = 64'bx;
reg dbiterr_out = 0, sbiterr_out = 0;
reg dbiterr_outreg = 0, sbiterr_outreg = 0;
reg dbiterr_out_out = 0, sbiterr_out_out = 0;
reg [7:0] wea_reg;
reg enb_reg;
reg [7:0] out_a = 8'b0, out_b = 8'b0, junk, web_reg;
reg outp_a = 1'b0, outp_b = 1'b0, junkp;
reg rising_clka = 1'b0, rising_clkb = 1'b0;
reg [15:0] addra_reg, addrb_reg;
reg [63:0] dia_reg, dib_reg;
reg [3:0] dipa_reg;
reg [7:0] dipb_reg;
reg [1:0] viol_type = 2'b00;
reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1;
reg [8:0] rdaddrecc_out = 9'b0, rdaddrecc_outreg = 9'b0;
reg [8:0] rdaddrecc_out_out = 9'b0;
reg finish_error = 0;
time time_port_a, time_port_b;
wire ena_in, enb_in, gsr_in, regcea_in, regceb_in, rstrama_in, rstramb_in;
wire [7:0] wea_in;
wire [7:0] web_in;
wire cascadeina_in, cascadeinb_in;
wire injectdbiterr_in, injectsbiterr_in;
wire rstrega_in, rstregb_in;
reg [15:0] ox_addra_reconstruct, ox_addrb_reconstruct;
reg [15:0] ox_addra_reconstruct_reg, ox_addrb_reconstruct_reg;
wire temp_wire; // trigger NCsim at initial time
assign temp_wire = 1;
time time_clka_period, time_clkb_period, time_period;
reg time_skew_a_flag = 0;
reg time_skew_b_flag = 0;
assign CASCADEOUTA = DOA[0];
assign CASCADEOUTB = DOB[0];
assign SBITERR = sbiterr_out_out;
assign DBITERR = dbiterr_out_out;
assign ECCPARITY = eccparity_out;
assign RDADDRECC = rdaddrecc_out_out;
assign injectdbiterr_in = INJECTDBITERR;
assign injectsbiterr_in = INJECTSBITERR;
assign rstrega_in = RSTREGA;
assign rstregb_in = RSTREGB;
localparam sync_clk_skew = (SIM_DEVICE == "7SERIES") ? 50 : 100;
// Determine memory size
localparam widest_width = (WRITE_WIDTH_A >= WRITE_WIDTH_B && WRITE_WIDTH_A >= READ_WIDTH_A &&
WRITE_WIDTH_A >= READ_WIDTH_B) ? WRITE_WIDTH_A :
(WRITE_WIDTH_B >= WRITE_WIDTH_A && WRITE_WIDTH_B >= READ_WIDTH_A &&
WRITE_WIDTH_B >= READ_WIDTH_B) ? WRITE_WIDTH_B :
(READ_WIDTH_A >= WRITE_WIDTH_A && READ_WIDTH_A >= WRITE_WIDTH_B &&
READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A :
(READ_WIDTH_B >= WRITE_WIDTH_A && READ_WIDTH_B >= WRITE_WIDTH_B &&
READ_WIDTH_B >= READ_WIDTH_A) ? READ_WIDTH_B : 72;
localparam wa_width = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 :
(WRITE_WIDTH_A == 4) ? 4 : (WRITE_WIDTH_A == 9) ? 8 :
(WRITE_WIDTH_A == 18) ? 16 : (WRITE_WIDTH_A == 36) ? 32 :
(WRITE_WIDTH_A == 72) ? 64 : 64;
localparam wa_width_0 = 0;
localparam wa_width_1 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 :
(WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 :
(WRITE_WIDTH_A == 18) ? 8 : (WRITE_WIDTH_A == 36) ? 8 :
(WRITE_WIDTH_A == 72) ? 8 : 0;
localparam wa_width_2 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 :
(WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 :
(WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 16 :
(WRITE_WIDTH_A == 72) ? 16 : 0;
localparam wa_width_3 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 :
(WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 :
(WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 24 :
(WRITE_WIDTH_A == 72) ? 24 : 0;
localparam wa_width_4 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 :
(WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 :
(WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 :
(WRITE_WIDTH_A == 72) ? 32 : 0;
localparam wa_width_5 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 :
(WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 :
(WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 :
(WRITE_WIDTH_A == 72) ? 40 : 0;
localparam wa_width_6 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 :
(WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 :
(WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 :
(WRITE_WIDTH_A == 72) ? 48 : 0;
localparam wa_width_7 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 :
(WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 :
(WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 :
(WRITE_WIDTH_A == 72) ? 56 : 0;
localparam wa_width_n = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 :
(WRITE_WIDTH_A == 4) ? 4 : (WRITE_WIDTH_A == 9) ? 8 :
(WRITE_WIDTH_A == 18) ? 8 : (WRITE_WIDTH_A == 36) ? 8 :
(WRITE_WIDTH_A == 72) ? 8 : 8;
localparam wb_width = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 :
(WRITE_WIDTH_B == 4) ? 4 : (WRITE_WIDTH_B == 9) ? 8 :
(WRITE_WIDTH_B == 18) ? 16 : (WRITE_WIDTH_B == 36) ? 32 :
(WRITE_WIDTH_B == 72) ? 64 : 64;
localparam wb_width_0 = 0;
localparam wb_width_1 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 :
(WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 :
(WRITE_WIDTH_B == 18) ? 8 : (WRITE_WIDTH_B == 36) ? 8 :
(WRITE_WIDTH_B == 72) ? 8 : 0;
localparam wb_width_2 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 :
(WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 :
(WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 16 :
(WRITE_WIDTH_B == 72) ? 16 : 0;
localparam wb_width_3 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 :
(WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 :
(WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 24 :
(WRITE_WIDTH_B == 72) ? 24 : 0;
localparam wb_width_4 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 :
(WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 :
(WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 :
(WRITE_WIDTH_B == 72) ? 32 : 0;
localparam wb_width_5 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 :
(WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 :
(WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 :
(WRITE_WIDTH_B == 72) ? 40 : 0;
localparam wb_width_6 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 :
(WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 :
(WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 :
(WRITE_WIDTH_B == 72) ? 48 : 0;
localparam wb_width_7 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 :
(WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 :
(WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 :
(WRITE_WIDTH_B == 72) ? 56 : 0;
localparam wb_width_n = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 :
(WRITE_WIDTH_B == 4) ? 4 : (WRITE_WIDTH_B == 9) ? 8 :
(WRITE_WIDTH_B == 18) ? 8 : (WRITE_WIDTH_B == 36) ? 8 :
(WRITE_WIDTH_B == 72) ? 8 : 8;
localparam wa_widthp = (WRITE_WIDTH_A == 9) ? 1 : (WRITE_WIDTH_A == 18) ? 2 :
(WRITE_WIDTH_A == 36) ? 4 : (WRITE_WIDTH_A == 72) ? 8 : 8;
localparam wb_widthp = (WRITE_WIDTH_B == 9) ? 1 : (WRITE_WIDTH_B == 18) ? 2 :
(WRITE_WIDTH_B == 36) ? 4 : (WRITE_WIDTH_B == 72) ? 8 : 8;
localparam ra_width = (READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 :
(READ_WIDTH_A == 4) ? 4 : (READ_WIDTH_A == 9) ? 8 :
(READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 :
(READ_WIDTH_A == 72) ? 64 : (READ_WIDTH_A == 0) ?
((READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 :
(READ_WIDTH_B == 4) ? 4 : (READ_WIDTH_B == 9) ? 8 :
(READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 :
(READ_WIDTH_B == 72) ? 64 : 64) : 64;
localparam ra_width_n = (ra_width == 1) ? 1 : (ra_width == 2) ? 2 :
(ra_width == 4) ? 4 : (ra_width == 8) ? 8 :
(ra_width == 16) ? 8 : (ra_width == 32) ? 8 :
(ra_width == 64) ? 8 : 8;
localparam rb_width = (READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 :
(READ_WIDTH_B == 4) ? 4 : (READ_WIDTH_B == 9) ? 8 :
(READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 :
(READ_WIDTH_B == 72) ? 32 : (READ_WIDTH_B == 0) ?
((READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 :
(READ_WIDTH_A == 4) ? 4 : (READ_WIDTH_A == 9) ? 8 :
(READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 :
(READ_WIDTH_A == 72) ? 32 : 32) : 32;
localparam rb_width_0 = 0;
localparam rb_width_1 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 :
(rb_width == 4) ? 0 : (rb_width == 8) ? 0 :
(rb_width == 16) ? 8 : (rb_width == 32) ? 8 :
(rb_width == 64) ? 8 : 8;
localparam rb_width_2 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 :
(rb_width == 4) ? 0 : (rb_width == 8) ? 0 :
(rb_width == 16) ? 0 : (rb_width == 32) ? 16 :
(rb_width == 64) ? 16 : 16;
localparam rb_width_3 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 :
(rb_width == 4) ? 0 : (rb_width == 8) ? 0 :
(rb_width == 16) ? 0 : (rb_width == 32) ? 24 :
(rb_width == 64) ? 24 : 24;
localparam rb_width_4 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 :
(rb_width == 4) ? 0 : (rb_width == 8) ? 0 :
(rb_width == 16) ? 0 : (rb_width == 32) ? 0 :
(rb_width == 64) ? 32 : 32;
localparam rb_width_5 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 :
(rb_width == 4) ? 0 : (rb_width == 8) ? 0 :
(rb_width == 16) ? 0 : (rb_width == 32) ? 0 :
(rb_width == 64) ? 40 : 40;
localparam rb_width_6 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 :
(rb_width == 4) ? 0 : (rb_width == 8) ? 0 :
(rb_width == 16) ? 0 : (rb_width == 32) ? 0 :
(rb_width == 64) ? 48 : 48;
localparam rb_width_7 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 :
(rb_width == 4) ? 0 : (rb_width == 8) ? 0 :
(rb_width == 16) ? 0 : (rb_width == 32) ? 0 :
(rb_width == 64) ? 56 : 56;
localparam rb_width_n = (rb_width == 1) ? 1 : (rb_width == 2) ? 2 :
(rb_width == 4) ? 4 : (rb_width == 8) ? 8 :
(rb_width == 16) ? 8 : (rb_width == 32) ? 8 :
(rb_width == 64) ? 8 : 8;
localparam ra_widthp = (READ_WIDTH_A == 9) ? 1 : (READ_WIDTH_A == 18) ? 2 :
(READ_WIDTH_A == 36) ? 4 : (READ_WIDTH_A == 72) ? 8 : 1;
localparam rb_widthp = (READ_WIDTH_B == 9) ? 1 : (READ_WIDTH_B == 18) ? 2 :
(READ_WIDTH_B == 36) ? 4 : (READ_WIDTH_B == 72) ? 4 : 1;
localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 :
(widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 :
(widest_width == 72) ? 6 : 0;
always @(*) begin
if (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") begin
if (BRAM_SIZE == 36) ox_addra_reconstruct[15:0] = {1'b0,ADDRA[14:8],8'b0};
else if (BRAM_SIZE == 18) ox_addra_reconstruct[15:0] = {2'b0,ADDRA[13:7],7'b0};
else ox_addra_reconstruct[15:0] = ADDRA;
end else ox_addra_reconstruct[15:0] = ADDRA;
end
always @(*) begin
if (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") begin
if (BRAM_SIZE == 36) ox_addrb_reconstruct[15:0] = {1'b0,ADDRB[14:8],8'b0};
else if (BRAM_SIZE == 18) ox_addrb_reconstruct[15:0] = {2'b0,ADDRB[13:7],7'b0};
else ox_addrb_reconstruct[15:0] = ADDRB;
end else ox_addrb_reconstruct[15:0] = ADDRB;
end
localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 :
(widest_width == 4) ? 4 : (widest_width == 9) ? 8 :
(widest_width == 18) ? 16 : (widest_width == 36) ? 32 :
(widest_width == 72) ? 64 : 64;
localparam width_0 = 0;
localparam width_1 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 :
(widest_width == 4) ? 0 : (widest_width == 9) ? 0 :
(widest_width == 18) ? 8 : (widest_width == 36) ? 8 :
(widest_width == 72) ? 8 : 0;
localparam width_2 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 :
(widest_width == 4) ? 0 : (widest_width == 9) ? 0 :
(widest_width == 18) ? 0 : (widest_width == 36) ? 16 :
(widest_width == 72) ? 16 : 0;
localparam width_3 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 :
(widest_width == 4) ? 0 : (widest_width == 9) ? 0 :
(widest_width == 18) ? 0 : (widest_width == 36) ? 24 :
(widest_width == 72) ? 24 : 0;
localparam width_4 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 :
(widest_width == 4) ? 0 : (widest_width == 9) ? 0 :
(widest_width == 18) ? 0 : (widest_width == 36) ? 0 :
(widest_width == 72) ? 32 : 0;
localparam width_5 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 :
(widest_width == 4) ? 0 : (widest_width == 9) ? 0 :
(widest_width == 18) ? 0 : (widest_width == 36) ? 0 :
(widest_width == 72) ? 40 : 0;
localparam width_6 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 :
(widest_width == 4) ? 0 : (widest_width == 9) ? 0 :
(widest_width == 18) ? 0 : (widest_width == 36) ? 0 :
(widest_width == 72) ? 48 : 0;
localparam width_7 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 :
(widest_width == 4) ? 0 : (widest_width == 9) ? 0 :
(widest_width == 18) ? 0 : (widest_width == 36) ? 0 :
(widest_width == 72) ? 56 : 0;
localparam width_n = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 :
(widest_width == 4) ? 4 : (widest_width == 9) ? 8 :
(widest_width == 18) ? 8 : (widest_width == 36) ? 8 :
(widest_width == 72) ? 8 : 8;
localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 :
(widest_width == 36) ? 4 :
(widest_width == 72) ? 8 : 1;
localparam r_addra_lbit_124 = (READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 :
(READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 :
(READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 :
(READ_WIDTH_A == 72) ? 6 : (READ_WIDTH_A == 0) ?
((READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 :
(READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 :
(READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 :
(READ_WIDTH_B == 72) ? 6 : 10) : 10;
localparam r_addrb_lbit_124 = (READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 :
(READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 :
(READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 :
(READ_WIDTH_B == 72) ? 6 : (READ_WIDTH_B == 0) ?
((READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 :
(READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 :
(READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 :
(READ_WIDTH_A == 72) ? 6 : 10) : 10;
localparam addra_lbit_124 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 1 :
(WRITE_WIDTH_A == 4) ? 2 : (WRITE_WIDTH_A == 9) ? 3 :
(WRITE_WIDTH_A == 18) ? 4 : (WRITE_WIDTH_A == 36) ? 5 :
(WRITE_WIDTH_A == 72) ? 6 : 10;
localparam addrb_lbit_124 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 1 :
(WRITE_WIDTH_B == 4) ? 2 : (WRITE_WIDTH_B == 9) ? 3 :
(WRITE_WIDTH_B == 18) ? 4 : (WRITE_WIDTH_B == 36) ? 5 :
(WRITE_WIDTH_B == 72) ? 6 : 10;
localparam addra_bit_124 = (WRITE_WIDTH_A == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_A == 1 && widest_width == 4) ? 1 :
(WRITE_WIDTH_A == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_A == 1 && widest_width == 18) ? 3 :
(WRITE_WIDTH_A == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 1 && widest_width == 72) ? 5 :
(WRITE_WIDTH_A == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_A == 2 && widest_width == 9) ? 2 :
(WRITE_WIDTH_A == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 2 && widest_width == 36) ? 4 :
(WRITE_WIDTH_A == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_A == 4 && widest_width == 9) ? 2 :
(WRITE_WIDTH_A == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 4 && widest_width == 36) ? 4 :
(WRITE_WIDTH_A == 4 && widest_width == 72) ? 5 : 10;
localparam r_addra_bit_124 = (READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 4 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ?
((READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 4 && widest_width == 72) ? 5 : 10) : 10;
localparam addrb_bit_124 = (WRITE_WIDTH_B == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_B == 1 && widest_width == 4) ? 1 :
(WRITE_WIDTH_B == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_B == 1 && widest_width == 18) ? 3 :
(WRITE_WIDTH_B == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 1 && widest_width == 72) ? 5 :
(WRITE_WIDTH_B == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_B == 2 && widest_width == 9) ? 2 :
(WRITE_WIDTH_B == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 2 && widest_width == 36) ? 4 :
(WRITE_WIDTH_B == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_B == 4 && widest_width == 9) ? 2 :
(WRITE_WIDTH_B == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 4 && widest_width == 36) ? 4 :
(WRITE_WIDTH_B == 4 && widest_width == 72) ? 5 : 10;
localparam r_addrb_bit_124 = (READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 4 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ?
((READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 4 && widest_width == 72) ? 5 : 10) : 10;
localparam addra_bit_8 = (WRITE_WIDTH_A == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 9 && widest_width == 36) ? 4 :
(WRITE_WIDTH_A == 9 && widest_width == 72) ? 5 : 10;
localparam addra_bit_16 = (WRITE_WIDTH_A == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 18 && widest_width == 72) ? 5 : 10;
localparam r_addra_bit_8 = (READ_WIDTH_A == 9 && widest_width == 18) ? 3 : (READ_WIDTH_A == 9 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 9 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 9 && widest_width == 18) ? 3 :
(READ_WIDTH_B == 9 && widest_width == 36) ? 4 : (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addra_bit_16 = (READ_WIDTH_A == 18 && widest_width == 36) ? 4 : (READ_WIDTH_A == 18 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 18 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 18 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addra_bit_32 = (READ_WIDTH_A == 36 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 36 && widest_width == 72) ? 5 : 10) : 10;
localparam addrb_bit_8 = (WRITE_WIDTH_B == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 9 && widest_width == 36) ? 4 :
(WRITE_WIDTH_B == 9 && widest_width == 72) ? 5 : 10;
localparam addrb_bit_16 = (WRITE_WIDTH_B == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 18 && widest_width == 72) ? 5 : 10;
localparam addrb_bit_32 = (WRITE_WIDTH_B == 36 && widest_width == 72) ? 5 : 10;
localparam r_addrb_bit_8 = (READ_WIDTH_B == 9 && widest_width == 18) ? 3 : (READ_WIDTH_B == 9 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 9 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 9 && widest_width == 18) ? 3 :
(READ_WIDTH_A == 9 && widest_width == 36) ? 4 : (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addrb_bit_16 = (READ_WIDTH_B == 18 && widest_width == 36) ? 4 : (READ_WIDTH_B == 18 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 18 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 18 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addrb_bit_32 = (READ_WIDTH_B == 36 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 36 && widest_width == 72) ? 5 : 10) : 10;
localparam mem_size1 = (BRAM_SIZE == 18) ? 16384 : (BRAM_SIZE == 36) ? 32768 : 32768;
localparam mem_size2 = (BRAM_SIZE == 18) ? 8192 : (BRAM_SIZE == 36) ? 16384 : 16384;
localparam mem_size4 = (BRAM_SIZE == 18) ? 4096 : (BRAM_SIZE == 36) ? 8192 : 8192;
localparam mem_size9 = (BRAM_SIZE == 18) ? 2048 : (BRAM_SIZE == 36) ? 4096 : 4096;
localparam mem_size18 = (BRAM_SIZE == 18) ? 1024 : (BRAM_SIZE == 36) ? 2048 : 2048;
localparam mem_size36 = (BRAM_SIZE == 18) ? 512 : (BRAM_SIZE == 36) ? 1024 : 1024;
localparam mem_size72 = (BRAM_SIZE == 18) ? 0 : (BRAM_SIZE == 36) ? 512 : 512;
localparam mem_depth = (widest_width == 1) ? mem_size1 : (widest_width == 2) ? mem_size2 : (widest_width == 4) ? mem_size4 :
(widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 :
(widest_width == 72) ? mem_size72 : 32768;
localparam memp_depth = (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 :
(widest_width == 72) ? mem_size72 : 4096;
reg [width+widthp-1:0] tmp_mem [0 : mem_depth-1];
reg [width-1:0] mem [mem_depth-1:0];
reg [widthp-1:0] memp [memp_depth-1:0];
integer index = 0;
/******************************************** task and function **************************************/
task task_ram;
input ram_we;
input [7:0] ram_di;
input ram_dip;
inout [7:0] mem_task;
inout memp_task;
begin
if (ram_we == 1'b1) begin
mem_task = ram_di;
if (width >= 8)
memp_task = ram_dip;
end
end
endtask // task_ram
task task_ram_col;
input ram_col_we_o;
input ram_col_we;
input [7:0] ram_col_di;
input ram_col_dip;
inout [7:0] ram_col_mem_task;
inout ram_col_memp_task;
integer ram_col_i;
begin
if (ram_col_we == 1'b1) begin
for (ram_col_i = 0; ram_col_i < 8; ram_col_i = ram_col_i + 1)
if (ram_col_mem_task[ram_col_i] !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1))
ram_col_mem_task[ram_col_i] = ram_col_di[ram_col_i];
if (width >= 8 && (ram_col_memp_task !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1)))
ram_col_memp_task = ram_col_dip;
end
end
endtask // task_ram_col
task task_ram_ox;
input ram_ox_we_o;
input ram_ox_we;
input [7:0] ram_ox_di;
input ram_ox_dip;
inout [7:0] ram_ox_mem_task;
inout ram_ox_memp_task;
integer ram_ox_i;
begin
if (ram_ox_we == 1'b1) begin
for (ram_ox_i = 0; ram_ox_i < 8; ram_ox_i = ram_ox_i + 1)
ram_ox_mem_task[ram_ox_i] = ram_ox_di[ram_ox_i];
if (width >= 8)
ram_ox_memp_task = ram_ox_dip;
end
end
endtask // task_ram_ox
task task_x_buf;
input [1:0] wr_rd_mode;
input integer do_uindex;
input integer do_lindex;
input integer dop_index;
input [63:0] do_ltmp;
inout [63:0] x_buf_do_tmp;
input [7:0] dop_ltmp;
inout [7:0] x_buf_dop_tmp;
integer i;
begin
if (wr_rd_mode == 2'b01) begin
for (i = do_lindex; i <= do_uindex; i = i + 1) begin
if (do_ltmp[i] === 1'bx)
x_buf_do_tmp[i] = 1'bx;
end
if (dop_ltmp[dop_index] === 1'bx)
x_buf_dop_tmp[dop_index] = 1'bx;
end // if (wr_rd_mode == 2'b01)
else begin
x_buf_do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8];
x_buf_dop_tmp[dop_index] = dop_ltmp[dop_index];
end // else: !if(wr_rd_mode == 2'b01)
end
endtask // task_x_buf
task task_col_wr_ram_a;
input [1:0] col_wr_ram_a_seq;
input [7:0] col_wr_ram_a_web_tmp;
input [7:0] col_wr_ram_a_wea_tmp;
input [63:0] col_wr_ram_a_dia_tmp;
input [7:0] col_wr_ram_a_dipa_tmp;
input [15:0] col_wr_ram_a_addrb_tmp;
input [15:0] col_wr_ram_a_addra_tmp;
begin
case (wa_width)
1, 2, 4 : begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1);
else
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(col_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10)
end // case: 1, 2, 4
8 : if (width >= 8) begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:3]], memp[col_wr_ram_a_addra_tmp[14:3]]);
else
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * wa_width) +: wa_width], memp[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 8
16 : if (width >= 16) begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:4]][(index)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) + wa_width_1) +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 16
32 : if (width >= 32) begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:5]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index)+:1]);
else if (wa_width < width) begin
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index)+:1]);
end
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:5]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]);
else if (wa_width < width)
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:5]][width_2 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]);
else if (wa_width < width)
task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:5]][width_3 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]);
else if (wa_width < width)
task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 32
64 : if (width >= 64) begin
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:6]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_0 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:6]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_1 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:6]][width_2 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_2 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:6]][width_3 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_3 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[4], col_wr_ram_a_wea_tmp[4], col_wr_ram_a_dia_tmp[39:32], col_wr_ram_a_dipa_tmp[4], mem[col_wr_ram_a_addra_tmp[14:6]][width_4 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[4], col_wr_ram_a_wea_tmp[4], col_wr_ram_a_dia_tmp[39:32], col_wr_ram_a_dipa_tmp[4], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_4 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[4], col_wr_ram_a_web_tmp[4], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[5], col_wr_ram_a_wea_tmp[5], col_wr_ram_a_dia_tmp[47:40], col_wr_ram_a_dipa_tmp[5], mem[col_wr_ram_a_addra_tmp[14:6]][width_5 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[5], col_wr_ram_a_wea_tmp[5], col_wr_ram_a_dia_tmp[47:40], col_wr_ram_a_dipa_tmp[5], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_5 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[5], col_wr_ram_a_web_tmp[5], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[6], col_wr_ram_a_wea_tmp[6], col_wr_ram_a_dia_tmp[55:48], col_wr_ram_a_dipa_tmp[6], mem[col_wr_ram_a_addra_tmp[14:6]][width_6 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[6], col_wr_ram_a_wea_tmp[6], col_wr_ram_a_dia_tmp[55:48], col_wr_ram_a_dipa_tmp[6], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_6 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[6], col_wr_ram_a_web_tmp[6], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[7], col_wr_ram_a_wea_tmp[7], col_wr_ram_a_dia_tmp[63:56], col_wr_ram_a_dipa_tmp[7], mem[col_wr_ram_a_addra_tmp[14:6]][width_7 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[7], col_wr_ram_a_wea_tmp[7], col_wr_ram_a_dia_tmp[63:56], col_wr_ram_a_dipa_tmp[7], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_7 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[7], col_wr_ram_a_web_tmp[7], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // case: 64
endcase // case(wa_width)
end
endtask // task_col_wr_ram_a
task task_ox_wr_ram_a;
input [1:0] ox_wr_ram_a_seq;
input [7:0] ox_wr_ram_a_web_tmp;
input [7:0] ox_wr_ram_a_wea_tmp;
input [63:0] ox_wr_ram_a_dia_tmp;
input [7:0] ox_wr_ram_a_dipa_tmp;
input [15:0] ox_wr_ram_a_addrb_tmp;
input [15:0] ox_wr_ram_a_addra_tmp;
begin
case (wa_width)
1, 2, 4 : begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1);
else
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(ox_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10)
end // case: 1, 2, 4
8 : if (width >= 8) begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:3]], memp[ox_wr_ram_a_addra_tmp[14:3]]);
else
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 8) +: 8], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 8
16 : if (width >= 16) begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[ox_wr_ram_a_addra_tmp[14:4]][(index)+:1]);
else
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[ox_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]);
else
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) + wa_width_1) +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 16
32 : if ( width >= 32) begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 32
64 : if (width >= 64) begin
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_0 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_1 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_2 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_3 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_dia_tmp[39:32], ox_wr_ram_a_dipa_tmp[4], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_4 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_dia_tmp[47:40], ox_wr_ram_a_dipa_tmp[5], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_5 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_dia_tmp[55:48], ox_wr_ram_a_dipa_tmp[6], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_6 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_dia_tmp[63:56], ox_wr_ram_a_dipa_tmp[7], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_7 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // case: 64
endcase // case(wa_width)
end
endtask // task_ox_wr_ram_a
task task_col_wr_ram_b;
input [1:0] col_wr_ram_b_seq;
input [7:0] col_wr_ram_b_wea_tmp;
input [7:0] col_wr_ram_b_web_tmp;
input [63:0] col_wr_ram_b_dib_tmp;
input [7:0] col_wr_ram_b_dipb_tmp;
input [15:0] col_wr_ram_b_addra_tmp;
input [15:0] col_wr_ram_b_addrb_tmp;
begin
case (wb_width)
1, 2, 4 : begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width_n], junk1);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 1, 2, 4
8 : if (width >= 8) begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:3]], memp[col_wr_ram_b_addrb_tmp[14:3]]);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 8
16 : if (width >= 16) begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:4]][(index)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_n) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10)
end // case: 16
32 : if (width >= 32) begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10)
end // case: 32
64 : if (width >= 64) begin
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_dib_tmp[39:32], col_wr_ram_b_dipb_tmp[4], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_dib_tmp[47:40], col_wr_ram_b_dipb_tmp[5], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_dib_tmp[55:48], col_wr_ram_b_dipb_tmp[6], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_dib_tmp[63:56], col_wr_ram_b_dipb_tmp[7], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // case: 64
endcase // case(wb_width)
end
endtask // task_col_wr_ram_b
task task_ox_wr_ram_b;
input [1:0] ox_wr_ram_b_seq;
input [7:0] ox_wr_ram_b_wea_tmp;
input [7:0] ox_wr_ram_b_web_tmp;
input [63:0] ox_wr_ram_b_dib_tmp;
input [7:0] ox_wr_ram_b_dipb_tmp;
input [15:0] ox_wr_ram_b_addra_tmp;
input [15:0] ox_wr_ram_b_addrb_tmp;
begin
case (wb_width)
1, 2, 4 : begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 1, 2, 4
8 : if (width >= 8) begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:3]], memp[ox_wr_ram_b_addrb_tmp[14:3]]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 8
16 : if (width >= 16) begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_1) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10)
end // case: 16
32 : if (width >= 32) begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10)
end // case: 32
64 : if (width >= 64) begin
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_dib_tmp[39:32], ox_wr_ram_b_dipb_tmp[4], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_dib_tmp[47:40], ox_wr_ram_b_dipb_tmp[5], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_dib_tmp[55:48], ox_wr_ram_b_dipb_tmp[6], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_dib_tmp[63:56], ox_wr_ram_b_dipb_tmp[7], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // case: 64
endcase // case(wb_width)
end
endtask // task_ox_wr_ram_b
task task_wr_ram_a;
input [7:0] wr_ram_a_wea_tmp;
input [63:0] dia_tmp;
input [7:0] dipa_tmp;
input [15:0] wr_ram_a_addra_tmp;
begin
case (wa_width)
1, 2, 4 : begin
if (wa_width >= width)
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1);
else
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_bit_124+1]][(wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width_n], junk1);
end
8 : if (width >= 8) begin
if (wa_width >= width)
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:3]], memp[wr_ram_a_addra_tmp[14:3]]);
else
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * wa_width) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]);
end
16 : if (width >= 16) begin
if (wa_width >= width) begin
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[wr_ram_a_addra_tmp[14:4]][(index)+:1]);
task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[wr_ram_a_addra_tmp[14:4]][(index+1)+:1]);
end else begin
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]);
task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) + wa_width_1) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]);
end // else: !if(wa_width >= wb_width)
end // case: 16
32 : if (width >= 32) begin
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index)+:1]);
task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+1)+:1]);
task_ram (wr_ram_a_wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+2)+:1]);
task_ram (wr_ram_a_wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+3)+:1]);
end // case: 32
endcase // case(wa_width)
end
endtask // task_wr_ram_a
task task_wr_ram_b;
input [7:0] wr_ram_b_web_tmp;
input [63:0] dib_tmp;
input [7:0] dipb_tmp;
input [15:0] wr_ram_b_addrb_tmp;
begin
case (wb_width)
1, 2, 4 : begin
if (wb_width >= width)
task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1);
else
task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width_n], junk1);
end
8 : if (width >= 8) begin
if (wb_width >= width)
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:3]], memp[wr_ram_b_addrb_tmp[14:3]]);
else
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]);
end
16 : if (width >= 16) begin
if (wb_width >= width) begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[wr_ram_b_addrb_tmp[14:4]][(index)+:1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]);
end else begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_1) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]);
end
end // case: 16
32 : if (width >= 32) begin
if (wb_width >= width) begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index)+:1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]);
task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]);
task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]);
end else begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]);
task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]);
task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]);
end // else: !if(wb_width >= width)
end // case: 32
64 : if (width >= 64) begin // only valid with ECC single bit correction for 64 bits
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index)+:1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]);
task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]);
task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]);
task_ram (wr_ram_b_web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]);
task_ram (wr_ram_b_web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]);
task_ram (wr_ram_b_web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]);
task_ram (wr_ram_b_web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]);
end // case: 64
endcase // case(wb_width)
end
endtask // task_wr_ram_b
task task_col_rd_ram_a;
input [1:0] col_rd_ram_a_seq; // 1 is bypass
input [7:0] col_rd_ram_a_web_tmp;
input [7:0] col_rd_ram_a_wea_tmp;
input [15:0] col_rd_ram_a_addra_tmp;
inout [63:0] col_rd_ram_a_doa_tmp;
inout [7:0] col_rd_ram_a_dopa_tmp;
reg [63:0] doa_ltmp;
reg [7:0] dopa_ltmp;
begin
doa_ltmp= 64'b0;
dopa_ltmp= 8'b0;
case (ra_width)
1, 2, 4 : begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
if (ra_width >= width)
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_lbit_124]];
else
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width];
task_x_buf (wr_mode_a, 3, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end // case: 1, 2, 4
8 : if (width >= 8) begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
if (ra_width >= width) begin
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:3]];
dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:3]];
end else begin
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_width) +: ra_width_n];
dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * 1) +: 1];
end
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end // case: 8
16 : if (width >= 16) begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
if (ra_width >= width) begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:4]][width_0 +: width_n];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:4]][(index)+:1];
end else begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) +: ra_width_n];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) +: 1];
end
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin
if (ra_width >= width) begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:4]][width_1 +: width_n];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:4]][(index+1)+:1];
end else begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) + ra_width_n) +: ra_width_n];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) + 1) +: 1];
end
task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end
32 : if (width >= 32) begin
if (ra_width >= width) begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:5]][width_0 +: width_n];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:5]][(index)+:1];
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:5]][width_1 +: width_n];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+1)+:1];
task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin
doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:5]][width_2 +: width_n];
dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+2)+:1];
task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin
doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:5]][width_3 +: width_n];
dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+3)+:1];
task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end // if (ra_width >= width)
end
64 : if (width >= 64) begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:6]][width_0 +: width_n];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:6]][(index)+:1];
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:6]][width_1 +: width_n];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+1)+:1];
task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin
doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:6]][width_2 +: width_n];
dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+2)+:1];
task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin
doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:6]][width_3 +: width_n];
dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+3)+:1];
task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[4] !== 1'b1)) begin
doa_ltmp[39:32] = mem[col_rd_ram_a_addra_tmp[14:6]][width_4 +: width_n];
dopa_ltmp[4:4] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+4)+:1];
task_x_buf (wr_mode_a, 39, 32, 4, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[5] !== 1'b1)) begin
doa_ltmp[47:40] = mem[col_rd_ram_a_addra_tmp[14:6]][width_5 +: width_n];
dopa_ltmp[5:5] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+5)+:1];
task_x_buf (wr_mode_a, 47, 40, 5, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[6] !== 1'b1)) begin
doa_ltmp[55:48] = mem[col_rd_ram_a_addra_tmp[14:6]][width_6 +: width_n];
dopa_ltmp[6:6] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+6)+:1];
task_x_buf (wr_mode_a, 55, 48, 6, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[7] !== 1'b1)) begin
doa_ltmp[63:56] = mem[col_rd_ram_a_addra_tmp[14:6]][width_7 +: width_n];
dopa_ltmp[7:7] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+7)+:1];
task_x_buf (wr_mode_a, 63, 56, 7, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end
endcase // case(ra_width)
end
endtask // task_col_rd_ram_a
task task_col_rd_ram_b;
input [1:0] col_rd_ram_b_seq; // 1 is bypass
input [7:0] col_rd_ram_b_wea_tmp;
input [7:0] col_rd_ram_b_web_tmp;
input [15:0] col_rd_ram_b_addrb_tmp;
inout [63:0] col_rd_ram_b_dob_tmp;
inout [7:0] col_rd_ram_b_dopb_tmp;
reg [63:0] col_rd_ram_b_dob_ltmp;
reg [7:0] col_rd_ram_b_dopb_ltmp;
begin
col_rd_ram_b_dob_ltmp= 64'b0;
col_rd_ram_b_dopb_ltmp= 8'b0;
case (rb_width)
1, 2, 4 : begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width)
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]];
else
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width_n];
task_x_buf (wr_mode_b, 3, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end // case: 1, 2, 4
8 : if (width >= 8) begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:3]];
col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:3]];
end else begin
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * rb_width) +: rb_width_n];
col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1];
end
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end // case: 8
16 : if (width >= 16) begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:4]][width_0 +: width_n];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index)+:1];
end else begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * rb_width) +: rb_width_n];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 1];
end
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:4]][width_1 +: width_n];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index+1)+:1];
end else begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * rb_width) + rb_width_n) +: rb_width_n];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) + 1) +: 1];
end
task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end
32 : if (width >= 32) begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_0 +: width_n];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index)+:1];
end else begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) +: rb_width_n];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) +: 1];
end
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_1 +: width_n];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+1)+:1];
end else begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_1) +: rb_width_n];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 1) +: 1];
end
task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_2 +: width_n];
col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+2)+:1];
end else begin
col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_2) +: rb_width_n];
col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 2) +: 1];
end
task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_3 +: width_n];
col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+3)+:1];
end else begin
col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_3) +: rb_width_n];
col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 3) +: 1];
end
task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end
64 : if (width >= 64) begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_0 +: width_n];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index)+:1];
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_1 +: width_n];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+1)+:1];
task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_2 +: width_n];
col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+2)+:1];
task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_3 +: width_n];
col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+3)+:1];
task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[4] === 1'b1 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1 && col_rd_ram_b_web_tmp[4] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[4] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[39:32] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_4 +: width_n];
col_rd_ram_b_dopb_ltmp[4:4] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+4)+:1];
task_x_buf (wr_mode_b, 39, 32, 4, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[5] === 1'b1 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1 && col_rd_ram_b_web_tmp[5] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[5] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[47:40] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_5 +: width_n];
col_rd_ram_b_dopb_ltmp[5:5] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+5)+:1];
task_x_buf (wr_mode_b, 47, 40, 5, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[6] === 1'b1 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1 && col_rd_ram_b_web_tmp[6] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[6] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[55:48] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_6 +: width_n];
col_rd_ram_b_dopb_ltmp[6:6] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+6)+:1];
task_x_buf (wr_mode_b, 55, 48, 6, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[7] === 1'b1 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1 && col_rd_ram_b_web_tmp[7] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[7] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[63:56] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_7 +: width_n];
col_rd_ram_b_dopb_ltmp[7:7] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+7)+:1];
task_x_buf (wr_mode_b, 63, 56, 7, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end
endcase // case(rb_width)
end
endtask // task_col_rd_ram_b
task task_rd_ram_a;
input [15:0] rd_ram_a_addra_tmp;
inout [63:0] doa_tmp;
inout [7:0] dopa_tmp;
begin
case (ra_width)
1, 2, 4 : begin
if (ra_width >= width)
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_lbit_124]];
else
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width];
end
8 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:3]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:3]];
end
else begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_width) +: ra_width];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_widthp) +: ra_widthp];
end
end
16 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:4]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:4]];
end
else begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) +: ra_width];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_widthp) +: ra_widthp];
end
end
32 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:5]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:5]];
end
else begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * ra_width) +: ra_width];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * ra_widthp) +: ra_widthp];
end
end
64 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:6]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:6]];
end
end
endcase // case(ra_width)
end
endtask // task_rd_ram_a
task task_rd_ram_b;
input [15:0] rd_ram_b_addrb_tmp;
inout [31:0] dob_tmp;
inout [3:0] dopb_tmp;
begin
case (rb_width)
1, 2, 4 : begin
if (rb_width >= width)
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]];
else
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width];
end
8 : begin
if (rb_width >= width) begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:3]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:3]];
end
else begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 8) +: 8];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1];
end
end
16 : begin
if (rb_width >= width) begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:4]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:4]];
end
else begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 16) +: 16];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 2];
end
end
32 : begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:5]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:5]];
end
64 : begin
if (rb_width >= width) begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:6]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:6]];
end
end
endcase
end
endtask // task_rd_ram_b
task chk_for_col_msg;
input wea_tmp;
input web_tmp;
input [15:0] addra_tmp;
input [15:0] addrb_tmp;
begin
if (SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY")
if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) begin
if (chk_ox_msg == 1) begin
if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1))
$display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA write was requested to the overlapped address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp);
end
else
$display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp);
col_wr_wr_msg = 0;
end // if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1)
else if (wea_tmp === 1'b1 && web_tmp === 1'b0 && col_wra_rdb_msg == 1) begin
if (chk_ox_msg == 1) begin
if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1))
$display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the overlapped address %h (hex) of port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp, addra_tmp);
end
else begin
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6"))
$display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp);
else if (wr_mode_a != 2'b01 || (viol_type == 2'b11 && wr_mode_a == 2'b01))
$display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_tmp);
end // else: !if(chk_ox_msg == 1)
col_wra_rdb_msg = 0;
end
else if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) begin
if (chk_ox_msg == 1) begin
if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1))
$display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the overlapped address %h (hex) of port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addra_tmp, addrb_tmp);
end
else begin
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6"))
$display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp);
else if (wr_mode_b != 2'b01 || (viol_type == 2'b10 && wr_mode_b == 2'b01))
$display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKA cycle.", $time/1000.0, addra_tmp);
end // else: !if(chk_ox_msg == 1)
col_wrb_rda_msg = 0;
end // if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1)
end
endtask // chk_for_col_msg
task task_col_ecc_read;
inout [63:0] do_tmp;
inout [7:0] dop_tmp;
input [15:0] addr_tmp;
reg [71:0] task_ecc_bit_position;
reg [7:0] task_dopr_ecc, task_syndrome;
reg [63:0] task_di_in_ecc_corrected;
reg [7:0] task_dip_in_ecc_corrected;
begin
if (|do_tmp === 1'bx) begin // if there is collision
dbiterr_out <= 1'bx;
sbiterr_out <= 1'bx;
end
else begin
task_dopr_ecc = fn_dip_ecc(1'b0, do_tmp, dop_tmp);
task_syndrome = task_dopr_ecc ^ dop_tmp;
if (task_syndrome !== 0) begin
if (task_syndrome[7]) begin // dectect single bit error
task_ecc_bit_position = {do_tmp[63:57], dop_tmp[6], do_tmp[56:26], dop_tmp[5], do_tmp[25:11], dop_tmp[4], do_tmp[10:4], dop_tmp[3], do_tmp[3:1], dop_tmp[2], do_tmp[0], dop_tmp[1:0], dop_tmp[7]};
if (task_syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
task_ecc_bit_position[task_syndrome[6:0]] = ~task_ecc_bit_position[task_syndrome[6:0]]; // correct single bit error in the output
task_di_in_ecc_corrected = {task_ecc_bit_position[71:65], task_ecc_bit_position[63:33], task_ecc_bit_position[31:17], task_ecc_bit_position[15:9], task_ecc_bit_position[7:5], task_ecc_bit_position[3]}; // correct single bit error in the memory
do_tmp = task_di_in_ecc_corrected;
task_dip_in_ecc_corrected = {task_ecc_bit_position[0], task_ecc_bit_position[64], task_ecc_bit_position[32], task_ecc_bit_position[16], task_ecc_bit_position[8], task_ecc_bit_position[4], task_ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_tmp = task_dip_in_ecc_corrected;
dbiterr_out <= 0;
sbiterr_out <= 1;
end
else if (!task_syndrome[7]) begin // double bit error
sbiterr_out <= 0;
dbiterr_out <= 1;
end
end // if (task_syndrome !== 0)
else begin
dbiterr_out <= 0;
sbiterr_out <= 0;
end // else: !if(task_syndrome !== 0)
end
end
endtask // task_col_ecc_read
function [7:0] fn_dip_ecc;
input encode;
input [63:0] di_in;
input [7:0] dip_in;
begin
fn_dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
fn_dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
fn_dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
fn_dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
fn_dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
fn_dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
fn_dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
if (encode == 1'b1)
fn_dip_ecc[7] = fn_dip_ecc[0]^fn_dip_ecc[1]^fn_dip_ecc[2]^fn_dip_ecc[3]^fn_dip_ecc[4]^fn_dip_ecc[5]^fn_dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
else
fn_dip_ecc[7] = dip_in[0]^dip_in[1]^dip_in[2]^dip_in[3]^dip_in[4]^dip_in[5]^dip_in[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
end
endfunction // fn_dip_ecc
/******************************************** END task and function **************************************/
initial begin
if (INIT_FILE == "NONE") begin // memory initialization from attributes
init_mult = 256/width;
for (count = 0; count < init_mult; count = count + 1) begin
init_offset = count * width;
mem[count] = INIT_00[init_offset +:width];
mem[count + (init_mult * 1)] = INIT_01[init_offset +:width];
mem[count + (init_mult * 2)] = INIT_02[init_offset +:width];
mem[count + (init_mult * 3)] = INIT_03[init_offset +:width];
mem[count + (init_mult * 4)] = INIT_04[init_offset +:width];
mem[count + (init_mult * 5)] = INIT_05[init_offset +:width];
mem[count + (init_mult * 6)] = INIT_06[init_offset +:width];
mem[count + (init_mult * 7)] = INIT_07[init_offset +:width];
mem[count + (init_mult * 8)] = INIT_08[init_offset +:width];
mem[count + (init_mult * 9)] = INIT_09[init_offset +:width];
mem[count + (init_mult * 10)] = INIT_0A[init_offset +:width];
mem[count + (init_mult * 11)] = INIT_0B[init_offset +:width];
mem[count + (init_mult * 12)] = INIT_0C[init_offset +:width];
mem[count + (init_mult * 13)] = INIT_0D[init_offset +:width];
mem[count + (init_mult * 14)] = INIT_0E[init_offset +:width];
mem[count + (init_mult * 15)] = INIT_0F[init_offset +:width];
mem[count + (init_mult * 16)] = INIT_10[init_offset +:width];
mem[count + (init_mult * 17)] = INIT_11[init_offset +:width];
mem[count + (init_mult * 18)] = INIT_12[init_offset +:width];
mem[count + (init_mult * 19)] = INIT_13[init_offset +:width];
mem[count + (init_mult * 20)] = INIT_14[init_offset +:width];
mem[count + (init_mult * 21)] = INIT_15[init_offset +:width];
mem[count + (init_mult * 22)] = INIT_16[init_offset +:width];
mem[count + (init_mult * 23)] = INIT_17[init_offset +:width];
mem[count + (init_mult * 24)] = INIT_18[init_offset +:width];
mem[count + (init_mult * 25)] = INIT_19[init_offset +:width];
mem[count + (init_mult * 26)] = INIT_1A[init_offset +:width];
mem[count + (init_mult * 27)] = INIT_1B[init_offset +:width];
mem[count + (init_mult * 28)] = INIT_1C[init_offset +:width];
mem[count + (init_mult * 29)] = INIT_1D[init_offset +:width];
mem[count + (init_mult * 30)] = INIT_1E[init_offset +:width];
mem[count + (init_mult * 31)] = INIT_1F[init_offset +:width];
mem[count + (init_mult * 32)] = INIT_20[init_offset +:width];
mem[count + (init_mult * 33)] = INIT_21[init_offset +:width];
mem[count + (init_mult * 34)] = INIT_22[init_offset +:width];
mem[count + (init_mult * 35)] = INIT_23[init_offset +:width];
mem[count + (init_mult * 36)] = INIT_24[init_offset +:width];
mem[count + (init_mult * 37)] = INIT_25[init_offset +:width];
mem[count + (init_mult * 38)] = INIT_26[init_offset +:width];
mem[count + (init_mult * 39)] = INIT_27[init_offset +:width];
mem[count + (init_mult * 40)] = INIT_28[init_offset +:width];
mem[count + (init_mult * 41)] = INIT_29[init_offset +:width];
mem[count + (init_mult * 42)] = INIT_2A[init_offset +:width];
mem[count + (init_mult * 43)] = INIT_2B[init_offset +:width];
mem[count + (init_mult * 44)] = INIT_2C[init_offset +:width];
mem[count + (init_mult * 45)] = INIT_2D[init_offset +:width];
mem[count + (init_mult * 46)] = INIT_2E[init_offset +:width];
mem[count + (init_mult * 47)] = INIT_2F[init_offset +:width];
mem[count + (init_mult * 48)] = INIT_30[init_offset +:width];
mem[count + (init_mult * 49)] = INIT_31[init_offset +:width];
mem[count + (init_mult * 50)] = INIT_32[init_offset +:width];
mem[count + (init_mult * 51)] = INIT_33[init_offset +:width];
mem[count + (init_mult * 52)] = INIT_34[init_offset +:width];
mem[count + (init_mult * 53)] = INIT_35[init_offset +:width];
mem[count + (init_mult * 54)] = INIT_36[init_offset +:width];
mem[count + (init_mult * 55)] = INIT_37[init_offset +:width];
mem[count + (init_mult * 56)] = INIT_38[init_offset +:width];
mem[count + (init_mult * 57)] = INIT_39[init_offset +:width];
mem[count + (init_mult * 58)] = INIT_3A[init_offset +:width];
mem[count + (init_mult * 59)] = INIT_3B[init_offset +:width];
mem[count + (init_mult * 60)] = INIT_3C[init_offset +:width];
mem[count + (init_mult * 61)] = INIT_3D[init_offset +:width];
mem[count + (init_mult * 62)] = INIT_3E[init_offset +:width];
mem[count + (init_mult * 63)] = INIT_3F[init_offset +:width];
if (BRAM_SIZE == 36) begin
mem[count + (init_mult * 64)] = INIT_40[init_offset +:width];
mem[count + (init_mult * 65)] = INIT_41[init_offset +:width];
mem[count + (init_mult * 66)] = INIT_42[init_offset +:width];
mem[count + (init_mult * 67)] = INIT_43[init_offset +:width];
mem[count + (init_mult * 68)] = INIT_44[init_offset +:width];
mem[count + (init_mult * 69)] = INIT_45[init_offset +:width];
mem[count + (init_mult * 70)] = INIT_46[init_offset +:width];
mem[count + (init_mult * 71)] = INIT_47[init_offset +:width];
mem[count + (init_mult * 72)] = INIT_48[init_offset +:width];
mem[count + (init_mult * 73)] = INIT_49[init_offset +:width];
mem[count + (init_mult * 74)] = INIT_4A[init_offset +:width];
mem[count + (init_mult * 75)] = INIT_4B[init_offset +:width];
mem[count + (init_mult * 76)] = INIT_4C[init_offset +:width];
mem[count + (init_mult * 77)] = INIT_4D[init_offset +:width];
mem[count + (init_mult * 78)] = INIT_4E[init_offset +:width];
mem[count + (init_mult * 79)] = INIT_4F[init_offset +:width];
mem[count + (init_mult * 80)] = INIT_50[init_offset +:width];
mem[count + (init_mult * 81)] = INIT_51[init_offset +:width];
mem[count + (init_mult * 82)] = INIT_52[init_offset +:width];
mem[count + (init_mult * 83)] = INIT_53[init_offset +:width];
mem[count + (init_mult * 84)] = INIT_54[init_offset +:width];
mem[count + (init_mult * 85)] = INIT_55[init_offset +:width];
mem[count + (init_mult * 86)] = INIT_56[init_offset +:width];
mem[count + (init_mult * 87)] = INIT_57[init_offset +:width];
mem[count + (init_mult * 88)] = INIT_58[init_offset +:width];
mem[count + (init_mult * 89)] = INIT_59[init_offset +:width];
mem[count + (init_mult * 90)] = INIT_5A[init_offset +:width];
mem[count + (init_mult * 91)] = INIT_5B[init_offset +:width];
mem[count + (init_mult * 92)] = INIT_5C[init_offset +:width];
mem[count + (init_mult * 93)] = INIT_5D[init_offset +:width];
mem[count + (init_mult * 94)] = INIT_5E[init_offset +:width];
mem[count + (init_mult * 95)] = INIT_5F[init_offset +:width];
mem[count + (init_mult * 96)] = INIT_60[init_offset +:width];
mem[count + (init_mult * 97)] = INIT_61[init_offset +:width];
mem[count + (init_mult * 98)] = INIT_62[init_offset +:width];
mem[count + (init_mult * 99)] = INIT_63[init_offset +:width];
mem[count + (init_mult * 100)] = INIT_64[init_offset +:width];
mem[count + (init_mult * 101)] = INIT_65[init_offset +:width];
mem[count + (init_mult * 102)] = INIT_66[init_offset +:width];
mem[count + (init_mult * 103)] = INIT_67[init_offset +:width];
mem[count + (init_mult * 104)] = INIT_68[init_offset +:width];
mem[count + (init_mult * 105)] = INIT_69[init_offset +:width];
mem[count + (init_mult * 106)] = INIT_6A[init_offset +:width];
mem[count + (init_mult * 107)] = INIT_6B[init_offset +:width];
mem[count + (init_mult * 108)] = INIT_6C[init_offset +:width];
mem[count + (init_mult * 109)] = INIT_6D[init_offset +:width];
mem[count + (init_mult * 110)] = INIT_6E[init_offset +:width];
mem[count + (init_mult * 111)] = INIT_6F[init_offset +:width];
mem[count + (init_mult * 112)] = INIT_70[init_offset +:width];
mem[count + (init_mult * 113)] = INIT_71[init_offset +:width];
mem[count + (init_mult * 114)] = INIT_72[init_offset +:width];
mem[count + (init_mult * 115)] = INIT_73[init_offset +:width];
mem[count + (init_mult * 116)] = INIT_74[init_offset +:width];
mem[count + (init_mult * 117)] = INIT_75[init_offset +:width];
mem[count + (init_mult * 118)] = INIT_76[init_offset +:width];
mem[count + (init_mult * 119)] = INIT_77[init_offset +:width];
mem[count + (init_mult * 120)] = INIT_78[init_offset +:width];
mem[count + (init_mult * 121)] = INIT_79[init_offset +:width];
mem[count + (init_mult * 122)] = INIT_7A[init_offset +:width];
mem[count + (init_mult * 123)] = INIT_7B[init_offset +:width];
mem[count + (init_mult * 124)] = INIT_7C[init_offset +:width];
mem[count + (init_mult * 125)] = INIT_7D[init_offset +:width];
mem[count + (init_mult * 126)] = INIT_7E[init_offset +:width];
mem[count + (init_mult * 127)] = INIT_7F[init_offset +:width];
end // if (BRAM_SIZE == 36)
end // for (count = 0; count < init_mult; count = count + 1)
if (width >= 8) begin
initp_mult = 256/widthp;
for (countp = 0; countp < initp_mult; countp = countp + 1) begin
initp_offset = countp * widthp;
memp[countp] = INITP_00[initp_offset +:widthp];
memp[countp + (initp_mult * 1)] = INITP_01[initp_offset +:widthp];
memp[countp + (initp_mult * 2)] = INITP_02[initp_offset +:widthp];
memp[countp + (initp_mult * 3)] = INITP_03[initp_offset +:widthp];
memp[countp + (initp_mult * 4)] = INITP_04[initp_offset +:widthp];
memp[countp + (initp_mult * 5)] = INITP_05[initp_offset +:widthp];
memp[countp + (initp_mult * 6)] = INITP_06[initp_offset +:widthp];
memp[countp + (initp_mult * 7)] = INITP_07[initp_offset +:widthp];
if (BRAM_SIZE == 36) begin
memp[countp + (initp_mult * 8)] = INITP_08[initp_offset +:widthp];
memp[countp + (initp_mult * 9)] = INITP_09[initp_offset +:widthp];
memp[countp + (initp_mult * 10)] = INITP_0A[initp_offset +:widthp];
memp[countp + (initp_mult * 11)] = INITP_0B[initp_offset +:widthp];
memp[countp + (initp_mult * 12)] = INITP_0C[initp_offset +:widthp];
memp[countp + (initp_mult * 13)] = INITP_0D[initp_offset +:widthp];
memp[countp + (initp_mult * 14)] = INITP_0E[initp_offset +:widthp];
memp[countp + (initp_mult * 15)] = INITP_0F[initp_offset +:widthp];
end
end // for (countp = 0; countp < initp_mult; countp = countp + 1)
end // if (width >= 8)
end // if (INIT_FILE == "NONE")
else begin // memory initialization from memory file
for (j = 0; j < mem_depth; j = j + 1) begin
for (j1 = 0; j1 < widest_width; j1 = j1 + 1) begin
tmp_mem[j][j1] = 1'b0;
end
end
$readmemh (INIT_FILE, tmp_mem);
case (widest_width)
1, 2, 4 : begin
for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1)
mem[i_mem] = tmp_mem [i_mem];
end
9 : if ((width == 8) && (widthp == 1)) begin
for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: width];
memp[i_mem] = tmp_mem[i_mem][width +: widthp];
end
end
18 : if ((width == 16) && (widthp == 2)) begin
for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: width];
memp[i_mem] = tmp_mem[i_mem][width +: widthp];
end
end
36 : if ((width == 32) && (widthp == 4)) begin
for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: width];
memp[i_mem] = tmp_mem[i_mem][width +: widthp];
end
end
72 : if ((width == 64) && (widthp == 8)) begin
for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: width];
memp[i_mem] = tmp_mem[i_mem][width +: widthp];
end
end
endcase // case(widest_width)
end // else: !if(INIT_FILE == "NONE")
case (EN_ECC_WRITE)
"TRUE" : en_ecc_write_int = 1;
"FALSE" : en_ecc_write_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_WRITE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE);
finish_error = 1;
end
endcase
case (EN_ECC_READ)
"TRUE" : en_ecc_read_int = 1;
"FALSE" : en_ecc_read_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_READ on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ);
finish_error = 1;
end
endcase
case (RAM_MODE)
"TDP" : begin
ram_mode_int = 1;
if (en_ecc_write_int == 1) begin
$display("DRC Error : The attribute EN_ECC_WRITE on RAMB18E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_WRITE);
finish_error = 1;
end
if (en_ecc_read_int == 1) begin
$display("DRC Error : The attribute EN_ECC_READ on RAMB18E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_READ);
finish_error = 1;
end
end // case: "TDP"
"SDP" : begin
ram_mode_int = 0;
if ((WRITE_MODE_A != WRITE_MODE_B) || WRITE_MODE_A == "NO_CHANGE" || WRITE_MODE_B == "NO_CHANGE") begin
$display("DRC Error : Both attributes WRITE_MODE_A and WRITE_MODE_B must be set to READ_FIRST or both attributes must be set to WRITE_FIRST when RAM_MODE = SDP on RAMB18E1 instance %m.");
finish_error = 1;
end
if (BRAM_SIZE == 18) begin
if (!(WRITE_WIDTH_B == 36 || READ_WIDTH_A == 36)) begin
$display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 36 when RAM_MODE = SDP.");
finish_error = 1;
end
end
else begin
if (!(WRITE_WIDTH_B == 72 || READ_WIDTH_A == 72)) begin
$display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 72 when RAM_MODE = SDP.");
finish_error = 1;
end
end // else: !if(BRAM_SIZE == 18)
end // case: "SDP"
default : begin
$display("Attribute Syntax Error : The attribute RAM_MODE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TDP or SDP.", RAM_MODE);
finish_error = 1;
end
endcase
case (WRITE_WIDTH_A)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A);
finish_error = 1;
end
end
endcase // case(WRITE_WIDTH_A)
case (WRITE_WIDTH_B)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B);
finish_error = 1;
end
end
endcase // case(WRITE_WIDTH_B)
case (READ_WIDTH_A)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A);
finish_error = 1;
end
end
endcase // case(READ_WIDTH_A)
case (READ_WIDTH_B)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B);
finish_error = 1;
end
end
endcase // case(READ_WIDTH_B)
if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && READ_WIDTH_A != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1.");
finish_error = 1;
end
if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && WRITE_WIDTH_A != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1.");
finish_error = 1;
end
if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && READ_WIDTH_B != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1.");
finish_error = 1;
end
if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && WRITE_WIDTH_B != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1.");
finish_error = 1;
end
if (READ_WIDTH_A == 0 && READ_WIDTH_B == 0) begin
$display("Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on RAMB18E1 instance %m, both can not be 0.");
finish_error = 1;
end
case (WRITE_MODE_A)
"WRITE_FIRST" : wr_mode_a = 2'b00;
"READ_FIRST" : wr_mode_a = 2'b01;
"NO_CHANGE" : wr_mode_a = 2'b10;
default : begin
$display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
finish_error = 1;
end
endcase
case (WRITE_MODE_B)
"WRITE_FIRST" : wr_mode_b = 2'b00;
"READ_FIRST" : wr_mode_b = 2'b01;
"NO_CHANGE" : wr_mode_b = 2'b10;
default : begin
$display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
finish_error = 1;
end
endcase
case (RAM_EXTENSION_A)
"UPPER" : cascade_a = 2'b11;
"LOWER" : cascade_a = 2'b01;
"NONE" : cascade_a = 2'b00;
default : begin
$display("Attribute Syntax Error : The attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_A);
finish_error = 1;
end
endcase
case (RAM_EXTENSION_B)
"UPPER" : cascade_b = 2'b11;
"LOWER" : cascade_b = 2'b01;
"NONE" : cascade_b = 2'b00;
default : begin
$display("Attribute Syntax Error : The attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_B);
finish_error = 1;
end
endcase
if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin
$display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RAMB18E1 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
finish_error = 1;
end
case (RSTREG_PRIORITY_A)
"RSTREG" : rstreg_priority_a_int = 1;
"REGCE" : rstreg_priority_a_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_A);
finish_error = 1;
end
endcase
case (RSTREG_PRIORITY_B)
"RSTREG" : rstreg_priority_b_int = 1;
"REGCE" : rstreg_priority_b_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_B);
finish_error = 1;
end
endcase
if ((en_ecc_write_int == 1 || en_ecc_read_int == 1) && (WRITE_WIDTH_B != 72 || READ_WIDTH_A != 72)) begin
$display("DRC Error : Attributes WRITE_WIDTH_B and READ_WIDTH_A have to be set to 72 on RAMB18E1 instance %m when either attribute EN_ECC_WRITE or EN_ECC_READ is set to TRUE.");
finish_error = 1;
end
case (RDADDR_COLLISION_HWCONFIG)
"DELAYED_WRITE" : rdaddr_collision_hwconfig_int = 0;
"PERFORMANCE" : rdaddr_collision_hwconfig_int = 1;
default : begin
$display("Attribute Syntax Error : The attribute RDADDR_COLLISION_HWCONFIG on RAMB18E1 instance %m is set to %s. Legal values for this attribute are DELAYED_WRITE or PERFORMANCE.", RDADDR_COLLISION_HWCONFIG);
finish_error = 1;
end
endcase
if (!(SIM_DEVICE == "VIRTEX6" || SIM_DEVICE == "7SERIES")) begin
$display("Attribute Syntax Error : The Attribute SIM_DEVICE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are VIRTEX6, or 7SERIES.", SIM_DEVICE);
finish_error = 1;
end
if (finish_error == 1)
#1 $finish;
end // initial begin
// GSR
always @(GSR)
if (GSR) begin
assign doa_out = INIT_A[0 +: ra_width];
if (ra_width >= 8) begin
assign dopa_out = INIT_A[ra_width +: ra_widthp];
end
assign dob_out = INIT_B[0 +: rb_width];
if (rb_width >= 8) begin
assign dopb_out = INIT_B[rb_width +: rb_widthp];
end
assign dbiterr_out = 0;
assign sbiterr_out = 0;
assign rdaddrecc_out = 9'b0;
end
else begin
deassign doa_out;
deassign dopa_out;
deassign dob_out;
deassign dopb_out;
deassign dbiterr_out;
deassign sbiterr_out;
deassign rdaddrecc_out;
end
always @(time_clka_period or time_clkb_period) begin
if (time_clka_period != 0 && time_clkb_period != 0) begin
if (time_clka_period <= time_clkb_period) begin
if (time_clka_period <= SETUP_READ_FIRST) begin
time_period = time_clka_period;
end
else begin
time_period = SETUP_READ_FIRST;
end
end
else if (time_clkb_period <= SETUP_READ_FIRST)
time_period = time_clkb_period;
else
time_period = SETUP_READ_FIRST;
end
end
// registering signals
always @(posedge CLKA) begin
`ifdef MODEL_TECH
#0 rising_clka = 1; // mentor race condition check
`else
rising_clka = 1;
`endif
if (time_skew_a_flag == 0) begin
if ($time > 110000) begin
time_clka_period = $time - time_port_a;
time_skew_a_flag = 1;
end
end
if (ENA === 1'b1) begin
time_port_a = $time;
addra_reg = ADDRA;
wea_reg = WEA;
dia_reg = DIA;
dipa_reg = DIPA;
ox_addra_reconstruct_reg = ox_addra_reconstruct;
end
end
always @(posedge CLKB) begin
`ifdef MODEL_TECH
#0 rising_clkb = 1; // mentor race condition check
`else
rising_clkb = 1;
`endif
if (time_skew_b_flag == 0) begin
if ($time > 110000) begin
time_clkb_period = $time - time_port_b;
time_skew_b_flag = 1;
end
end
if (ENB === 1'b1) begin
time_port_b = $time;
addrb_reg = ADDRB;
web_reg = WEB;
enb_reg = ENB;
dib_reg = DIB;
dipb_reg = DIPB;
ox_addrb_reconstruct_reg = ox_addrb_reconstruct;
end
end // always @ (posedge CLKB)
// CLKA and CLKB
always @(posedge rising_clka or posedge rising_clkb) begin
// Registering addr[15] for cascade mode
if (rising_clka)
if (cascade_a[1])
addra_in_15_reg_bram = ~ADDRA[15];
else
addra_in_15_reg_bram = ADDRA[15];
if (rising_clkb)
if (cascade_b[1])
addrb_in_15_reg_bram = ~ADDRB[15];
else
addrb_in_15_reg_bram = ADDRB[15];
if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin
/************************************* Collision starts *****************************************/
if (SIM_COLLISION_CHECK != "NONE") begin
if (GSR === 1'b0) begin
if (time_port_a > time_port_b) begin
if (time_port_a - time_port_b <= sync_clk_skew) begin
viol_time = 1;
end
else if (time_port_a - time_port_b <= time_period) begin
viol_time = 2;
end
end
else begin
if (time_port_b - time_port_a <= sync_clk_skew) begin
viol_time = 1;
end
else if (time_port_b - time_port_a <= time_period) begin
viol_time = 2;
end
end // else: !if(time_port_a > time_port_b)
if (ENA === 1'b0 || ENB === 1'b0)
viol_time = 0;
if ((WRITE_WIDTH_A <= 9 && WEA[0] === 1'b0) || (WRITE_WIDTH_A == 18 && WEA[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && WEA[3:0] === 4'b0000))
if ((WRITE_WIDTH_B <= 9 && WEB[0] === 1'b0) || (WRITE_WIDTH_B == 18 && WEB[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && WEB[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && WEB[7:0] === 8'h00))
viol_time = 0;
if (viol_time != 0) begin
if (SIM_DEVICE == "VIRTEX6") begin
// Clka and clkb rise at the same time
if ((rising_clka && rising_clkb) || viol_time == 1) begin
if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin
viol_type = 2'b01;
chk_col_same_clk = 1;
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin
doa_buf = dob_buf;
dopa_buf = dopb_buf;
end
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin
dob_buf = doa_buf;
dopb_buf = dopa_buf;
end
else begin
task_rd_ram_a (ADDRA, doa_buf, dopa_buf);
task_rd_ram_b (ADDRB, dob_buf, dopb_buf);
end
task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA);
task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB);
chk_col_same_clk = 0;
task_col_rd_ram_a (2'b01, WEB, WEA, ADDRA, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, WEA, WEB, ADDRB, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA);
dib_ecc_col = DIB;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB);
end
else
task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf);
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && rdaddr_collision_hwconfig_int == 1) begin
task_col_wr_ram_a (2'b10, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA);
task_col_wr_ram_b (2'b10, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB);
end
if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb)))
task_col_ecc_read (doa_buf, dopa_buf, ADDRA);
end // if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin
viol_type = 2'b01;
chk_ox_msg = 1;
chk_ox_same_clk = 1;
if (time_port_a > time_port_b)
task_rd_ram_a (ADDRA, doa_buf, dopa_buf);
else if (time_port_b > time_port_a)
task_rd_ram_b (ADDRB, dob_buf, dopb_buf);
else begin
task_rd_ram_a (ADDRA, doa_buf, dopa_buf);
task_rd_ram_b (ADDRB, dob_buf, dopb_buf);
end
task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA);
task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB);
chk_ox_msg = 0;
chk_ox_same_clk = 0;
task_ox_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA);
dib_ecc_col = DIB;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB);
eccparity_out = dip_ecc_col;
task_ox_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB);
end
else
task_ox_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf);
if (rdaddr_collision_hwconfig_int == 1) begin
task_col_wr_ram_a (2'b10, WEB, 8'hff, di_x, di_x[7:0], ADDRB, ADDRA);
task_col_wr_ram_b (2'b10, WEA, 8'hff, di_x, di_x[7:0], ADDRA, ADDRB);
end
if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb)))
task_col_ecc_read (doa_buf, dopa_buf, ADDRA);
end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]))
else
viol_time = 0;
end // if (rising_clka && rising_clkb)
// Clkb before clka
else if (rising_clka && !rising_clkb) begin
if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin
viol_type = 2'b10;
task_rd_ram_a (ADDRA, doa_buf, dopa_buf);
task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA);
task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg);
task_col_rd_ram_a (2'b01, web_reg, WEA, ADDRA, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, WEA, web_reg, addrb_reg, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA);
dib_ecc_col = dib_reg;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg);
end
else
task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf);
if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin
task_col_wr_ram_a (2'b10, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA);
task_col_wr_ram_b (2'b10, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg);
end
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, ADDRA);
end // if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb])) begin
viol_type = 2'b10;
chk_ox_msg = 1;
task_rd_ram_a (ADDRA, doa_buf, dopa_buf);
// get msg
task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA);
task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg);
chk_ox_msg = 0;
task_ox_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA);
dib_ecc_col = dib_reg;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg);
eccparity_out = dip_ecc_col;
task_ox_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg);
end
else
task_ox_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_reg, 8'hff, di_x, di_x[7:0], addrb_reg, ADDRA);
task_col_wr_ram_b (2'b10, WEA, 8'hff, di_x, di_x[7:0], ADDRA, addrb_reg);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, ADDRA);
end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb]))
else
viol_time = 0;
end // if (rising_clka && !rising_clkb)
// Clka before clkb
else if (!rising_clka && rising_clkb) begin
if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin
viol_type = 2'b11;
task_rd_ram_b (ADDRB, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg);
task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB);
task_col_rd_ram_a (2'b01, WEB, wea_reg, addra_reg, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_reg, WEB, ADDRB, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg);
dib_ecc_col = DIB;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB);
end
else
task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf);
if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin
task_col_wr_ram_a (2'b10, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg);
task_col_wr_ram_b (2'b10, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB);
end
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_reg);
end // if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin
viol_type = 2'b11;
chk_ox_msg = 1;
task_rd_ram_b (ADDRB, dob_buf, dopb_buf);
// get msg
task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg);
task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB);
chk_ox_msg = 0;
task_ox_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg);
dib_ecc_col = DIB;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB);
eccparity_out = dip_ecc_col;
task_ox_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB);
end
else
task_ox_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, WEB, 8'hff, di_x, di_x[7:0], ADDRB, addra_reg);
task_col_wr_ram_b (2'b10, wea_reg, 8'hff, di_x, di_x[7:0], addra_reg, ADDRB);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_reg);
end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]))
else
viol_time = 0;
end // if (!rising_clka && rising_clkb)
end // if (SIM_DEVICE == "VIRTEX6")
else begin // 7series
// Clka and clkb rise at the same time
if ((rising_clka && rising_clkb) || viol_time == 1) begin
if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin
viol_type = 2'b01;
chk_col_same_clk = 1;
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin
doa_buf = dob_buf;
dopa_buf = dopb_buf;
end
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin
dob_buf = doa_buf;
dopb_buf = dopa_buf;
end
else begin
task_rd_ram_a (ADDRA, doa_buf, dopa_buf);
task_rd_ram_b (ADDRB, dob_buf, dopb_buf);
end
task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA);
task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB);
chk_col_same_clk = 0;
task_col_rd_ram_a (2'b01, WEB, WEA, ADDRA, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, WEA, WEB, ADDRB, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA);
dib_ecc_col = DIB;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB);
end
else
task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf);
if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb)))
task_col_ecc_read (doa_buf, dopa_buf, ADDRA);
end // if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin
$display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, ADDRA, ADDRB, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B );
$finish;
end
else
viol_time = 0;
end // if ((rising_clka && rising_clkb) || viol_time == 1)
// Clkb before clka
else if (rising_clka && !rising_clkb) begin
if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin
viol_type = 2'b10;
task_rd_ram_a (ADDRA, doa_buf, dopa_buf);
task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA);
task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg);
task_col_rd_ram_a (2'b01, web_reg, WEA, ADDRA, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, WEA, web_reg, addrb_reg, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA);
dib_ecc_col = dib_reg;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg);
end
else
task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, ADDRA);
end // if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin
$display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, ADDRA, addrb_reg, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B );
$finish;
end
else
viol_time = 0;
end // if (rising_clka && !rising_clkb)
// Clka before clkb
else if (!rising_clka && rising_clkb) begin
if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin
viol_type = 2'b11;
task_rd_ram_b (ADDRB, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg);
task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB);
task_col_rd_ram_a (2'b01, WEB, wea_reg, addra_reg, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_reg, WEB, ADDRB, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg);
dib_ecc_col = DIB;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB);
end
else
task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_reg);
end // if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin
$display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, addra_reg, ADDRB, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B );
$finish;
end
else
viol_time = 0;
end // if (!rising_clka && rising_clkb)
end // else: !if(SIM_DEVICE == "VIRTEX6")
end // if (viol_time != 0)
end // if (GSR === 1'b0)
if (SIM_COLLISION_CHECK == "WARNING_ONLY")
viol_time = 0;
end // if (SIM_COLLISION_CHECK != "NONE")
/*************************************** end collision ********************************/
end // if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00)))
/**************************** Port A ****************************************/
if (rising_clka) begin
// DRC
if (RSTRAMA === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB18E1 instance %m.");
// end DRC
// registering ADDRA[15] the second time
if (REGCEA)
addra_in_15_reg1 = addra_in_15_reg;
if (ENA && (wr_mode_a != 2'b10 || WEA[0] == 0 || RSTRAMA == 1'b1))
if (cascade_a[1])
addra_in_15_reg = ~ADDRA[15];
else
addra_in_15_reg = ADDRA[15];
if (GSR == 1'b0 && ENA == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) begin
// SRVAL
if (RSTRAMA === 1'b1) begin
doa_buf = SRVAL_A[0 +: ra_width];
doa_out = SRVAL_A[0 +: ra_width];
if (ra_width >= 8) begin
dopa_buf = SRVAL_A[ra_width +: ra_widthp];
dopa_out = SRVAL_A[ra_width +: ra_widthp];
end
end
if (viol_time == 0) begin
// Read first
if (wr_mode_a == 2'b01 || (ram_mode_int == 0 && en_ecc_read_int == 1)) begin
task_rd_ram_a (ADDRA, doa_buf, dopa_buf);
// ECC decode
if (ram_mode_int == 0 && en_ecc_read_int == 1) begin
dopr_ecc = fn_dip_ecc(1'b0, doa_buf, dopa_buf);
syndrome = dopr_ecc ^ dopa_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {doa_buf[63:57], dopa_buf[6], doa_buf[56:26], dopa_buf[5], doa_buf[25:11], dopa_buf[4], doa_buf[10:4], dopa_buf[3], doa_buf[3:1], dopa_buf[2], doa_buf[0], dopa_buf[1:0], dopa_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
dia_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
doa_buf = dia_in_ecc_corrected;
dipa_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dopa_buf = dipa_in_ecc_corrected;
dbiterr_out <= 0;
sbiterr_out <= 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out <= 0;
dbiterr_out <= 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out <= 0;
sbiterr_out <= 0;
end // else: !if(syndrome !== 0)
// output of rdaddrecc
rdaddrecc_out[8:0] <= ADDRA[14:6];
end // if (ram_mode_int == 0 && en_ecc_read_int == 1)
end // if (wr_mode_a == 2'b01)
// Write
task_wr_ram_a (WEA, DIA, DIPA, ADDRA);
// Read if not read first
if (wr_mode_a != 2'b01 && !(ram_mode_int == 0 && en_ecc_read_int == 1))
task_rd_ram_a (ADDRA, doa_buf, dopa_buf);
end // if (viol_time == 0)
end // if (GSR == 1'b0 && ENA == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)))
end // if (rising_clka)
// end of port A
/************************************** port B ***************************************************************/
if (rising_clkb) begin
// DRC
if (RSTRAMB === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB18E1 instance %m.");
if (!(en_ecc_write_int == 1 || en_ecc_read_int == 1)) begin
if (injectsbiterr_in === 1)
$display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB18E1 instance %m.");
if (injectdbiterr_in === 1)
$display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB18E1 instance %m.");
end
// End DRC
if (REGCEB)
addrb_in_15_reg1 = addrb_in_15_reg;
if (ENB && (wr_mode_b != 2'b10 || WEB[0] == 0 || RSTRAMB == 1'b1))
if (cascade_b[1])
addrb_in_15_reg = ~ADDRB[15];
else
addrb_in_15_reg = ADDRB[15];
if (GSR == 1'b0 && ENB == 1'b1 && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin
// SRVAL
if (RSTRAMB === 1'b1) begin
dob_buf = SRVAL_B[0 +: rb_width];
dob_out = SRVAL_B[0 +: rb_width];
if (rb_width >= 8) begin
dopb_buf = SRVAL_B[rb_width +: rb_widthp];
dopb_out = SRVAL_B[rb_width +: rb_widthp];
end
end
if (viol_time == 0) begin
// ECC encode
if (ram_mode_int == 0 && en_ecc_write_int == 1) begin
dip_ecc = fn_dip_ecc(1'b1, DIB, DIPB);
eccparity_out = dip_ecc;
dipb_in_ecc = dip_ecc;
end
else
dipb_in_ecc = DIPB;
dib_in_ecc = DIB;
// injecting error
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin // double bit
dib_in_ecc[30] = ~dib_in_ecc[30];
dib_in_ecc[62] = ~dib_in_ecc[62];
end
else if (injectsbiterr_in === 1) begin // single bit
dib_in_ecc[30] = ~dib_in_ecc[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
// Read first
if (wr_mode_b == 2'b01 && RSTRAMB === 1'b0)
task_rd_ram_b (ADDRB, dob_buf, dopb_buf);
// Write
task_wr_ram_b (WEB, dib_in_ecc, dipb_in_ecc, ADDRB);
// Read if not read first
if (wr_mode_b != 2'b01 && RSTRAMB === 1'b0)
task_rd_ram_b (ADDRB, dob_buf, dopb_buf);
end // if (viol_time == 0)
end // if (GSR == 1'b0 && ENB == 1'b1 && (cascade_b == 2'b00 || addrb_in_15_reg_bram == 1'b0))
end // if (rising_clkb)
// end of port B
if (GSR == 1'b0) begin
// writing outputs of port A
if (ENA && (rising_clka || viol_time != 0)) begin
if (RSTRAMA === 1'b0 && (wr_mode_a != 2'b10 || (WRITE_WIDTH_A <= 9 && WEA[0] === 1'b0) || (WRITE_WIDTH_A == 18 && WEA[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && WEA[3:0] === 4'b0000))) begin
doa_out <= doa_buf;
if (ra_width >= 8)
dopa_out <= dopa_buf;
end
end
// writing outputs of port B
if (ENB && (rising_clkb || viol_time != 0)) begin
if (RSTRAMB === 1'b0 && (wr_mode_b != 2'b10 || (WRITE_WIDTH_B <= 9 && WEB[0] === 1'b0) || (WRITE_WIDTH_B == 18 && WEB[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && WEB[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && WEB[7:0] === 8'h00))) begin
dob_out <= dob_buf;
if (rb_width >= 8)
dopb_out <= dopb_buf;
end
end
end // if (GSR == 1'b0)
viol_time = 0;
`ifdef MODEL_TECH
#0 rising_clka = 0; // mentor race condition check
#0 rising_clkb = 0; // mentor race condition check
`else
rising_clka = 0;
rising_clkb = 0;
`endif
viol_type = 2'b00;
col_wr_wr_msg = 1;
col_wra_rdb_msg = 1;
col_wrb_rda_msg = 1;
end // always @ (posedge rising_clka or posedge rising_clkb)
// ********* Cascade Port A ********
always @(posedge CLKA or CASCADEINA or addra_in_15_reg or doa_out or dopa_out) begin
if (cascade_a[1] == 1'b1 && addra_in_15_reg == 1'b1) begin
doa_out_mux[0] = CASCADEINA;
end
else begin
doa_out_mux = doa_out;
if (ra_width >= 8)
dopa_out_mux = dopa_out;
end
end
// output register mode
always @(posedge CLKA or CASCADEINA or addra_in_15_reg1 or doa_outreg or dopa_outreg) begin
if (cascade_a[1] == 1'b1 && addra_in_15_reg1 == 1'b1) begin
doa_outreg_mux[0] = CASCADEINA;
end
else begin
doa_outreg_mux = doa_outreg;
if (ra_width >= 8)
dopa_outreg_mux = dopa_outreg;
end
end
// ********* Cascade Port B ********
always @(posedge CLKB or CASCADEINB or addrb_in_15_reg or dob_out or dopb_out) begin
if (cascade_b[1] == 1'b1 && addrb_in_15_reg == 1'b1) begin
dob_out_mux[0] = CASCADEINB;
end
else begin
dob_out_mux = dob_out;
if (rb_width >= 8)
dopb_out_mux = dopb_out;
end
end
// output register mode
always @(posedge CLKB or CASCADEINB or addrb_in_15_reg1 or dob_outreg or dopb_outreg) begin
if (cascade_b[1] == 1'b1 && addrb_in_15_reg1 == 1'b1) begin
dob_outreg_mux[0] = CASCADEINB;
end
else begin
dob_outreg_mux = dob_outreg;
if (rb_width >= 8)
dopb_outreg_mux = dopb_outreg;
end
end // always @ (posedge REGCLKB or CASCADEINREGB or addrb_in_15_reg1 or dob_outreg or dopb_outreg)
// ***** Output Registers **** Port A *****
always @(posedge CLKA or posedge GSR) begin
if (DOA_REG == 1) begin
if (GSR == 1'b1) begin
rdaddrecc_outreg <= 9'b0;
dbiterr_outreg <= 0;
sbiterr_outreg <= 0;
doa_outreg <= INIT_A[0 +: ra_width];
if (ra_width >= 8)
dopa_outreg <= INIT_A[ra_width +: ra_widthp];
end
else if (GSR == 1'b0) begin
if (REGCEA === 1'b1) begin
dbiterr_outreg <= dbiterr_out;
sbiterr_outreg <= sbiterr_out;
rdaddrecc_outreg <= rdaddrecc_out;
end
if (rstreg_priority_a_int == 0) begin // Virtex5 behavior
if (REGCEA == 1'b1) begin
if (RSTREGA == 1'b1) begin
doa_outreg <= SRVAL_A[0 +: ra_width];
if (ra_width >= 8)
dopa_outreg <= SRVAL_A[ra_width +: ra_widthp];
end
else if (RSTREGA == 1'b0) begin
doa_outreg <= doa_out;
if (ra_width >= 8)
dopa_outreg <= dopa_out;
end
end // if (REGCEA == 1'b1)
end // if (rstreg_priority_a_int == 1'b0)
else begin
if (RSTREGA == 1'b1) begin
doa_outreg <= SRVAL_A[0 +: ra_width];
if (ra_width >= 8)
dopa_outreg <= SRVAL_A[ra_width +: ra_widthp];
end
else if (RSTREGA == 1'b0) begin
if (REGCEA == 1'b1) begin
doa_outreg <= doa_out;
if (ra_width >= 8)
dopa_outreg <= dopa_out;
end
end
end // else: !if(rstreg_priority_a_int == 1'b0)
end // if (GSR == 1'b0)
end // if (DOA_REG == 1)
end // always @ (posedge CLKA or posedge GSR)
always @(temp_wire or doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg or rdaddrecc_out or rdaddrecc_outreg) begin
case (DOA_REG)
0 : begin
dbiterr_out_out = dbiterr_out;
sbiterr_out_out = sbiterr_out;
rdaddrecc_out_out = rdaddrecc_out;
DOA[0 +: ra_width] = doa_out_mux[0 +: ra_width];
if (ra_width >= 8)
DOPA[0 +: ra_widthp] = dopa_out_mux[0 +: ra_widthp];
end
1 : begin
dbiterr_out_out = dbiterr_outreg;
sbiterr_out_out = sbiterr_outreg;
DOA[0 +: ra_width] = doa_outreg_mux[0 +: ra_width];
rdaddrecc_out_out = rdaddrecc_outreg;
if (ra_width >= 8)
DOPA[0 +: ra_widthp] = dopa_outreg_mux[0 +: ra_widthp];
end
default : begin
$display("Attribute Syntax Error : The attribute DOA_REG on RAMB18E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOA_REG);
$finish;
end
endcase
end // always @ (doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg)
// ***** Output Registers **** Port B *****
always @(posedge CLKB or posedge GSR) begin
if (DOB_REG == 1) begin
if (GSR == 1'b1) begin
dob_outreg <= INIT_B[0 +: rb_width];
if (rb_width >= 8)
dopb_outreg <= INIT_B[rb_width +: rb_widthp];
end
else if (GSR == 1'b0) begin
if (rstreg_priority_b_int == 0) begin // Virtex5 behavior
if (REGCEB == 1'b1) begin
if (RSTREGB == 1'b1) begin
dob_outreg <= SRVAL_B[0 +: rb_width];
if (rb_width >= 8)
dopb_outreg <= SRVAL_B[rb_width +: rb_widthp];
end
else if (RSTREGB == 1'b0) begin
dob_outreg <= dob_out;
if (rb_width >= 8)
dopb_outreg <= dopb_out;
end
end // if (REGCEB == 1'b1)
end // if (rstreg_priority_b_int == 1'b0)
else begin
if (RSTREGB == 1'b1) begin
dob_outreg <= SRVAL_B[0 +: rb_width];
if (rb_width >= 8)
dopb_outreg <= SRVAL_B[rb_width +: rb_widthp];
end
else if (RSTREGB == 1'b0) begin
if (REGCEB == 1'b1) begin
dob_outreg <= dob_out;
if (rb_width >= 8)
dopb_outreg <= dopb_out;
end
end
end // else: !if(rstreg_priority_b_int == 1'b0)
end // if (GSR == 1'b0)
end // if (DOB_REG == 1)
end // always @ (posedge CLKB or posedge GSR)
always @(temp_wire or dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) begin
case (DOB_REG)
0 : begin
DOB[0 +: rb_width] = dob_out_mux[0 +: rb_width];
if (rb_width >= 8)
DOPB[0 +: rb_widthp] = dopb_out_mux[0 +: rb_widthp];
end
1 : begin
DOB[0 +: rb_width] = dob_outreg_mux[0 +: rb_width];
if (rb_width >= 8)
DOPB[0 +: rb_widthp] = dopb_outreg_mux[0 +: rb_widthp];
end
default : begin
$display("Attribute Syntax Error : The attribute DOB_REG on RAMB18E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOB_REG);
$finish;
end
endcase
end // always @ (dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux)
endmodule // RB18_INTERNAL_VLOG
`endcelldefine
// end of RB18_INTERNAL_VLOG - Note: Not an user primitive
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:28:21 04/13/2016
// Design Name: MAIN
// Module Name: Y:/TEOCOA/EXPR5/TESTSTORAGE.v
// Project Name: EXPR5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: TESTSTORAGE
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TEST;
// Inputs
reg [5:0] Mem_Addr;
reg [1:0] CS;
reg Mem_Write;
reg Clk;
// Outputs
wire [7:0] LED;
// Instantiate the Unit Under Test (UUT)
TESTSTORAGE uut (
.Mem_Addr(Mem_Addr),
.CS(CS),
.Mem_Write(Mem_Write),
.Clk(Clk),
.LED(LED)
);
initial begin
// Initialize Inputs
Clk = 0;
Mem_Addr = 0;
CS = 0;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 0;
CS = 1;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 0;
CS = 2;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 0;
CS = 3;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 1;
CS = 0;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 1;
CS = 1;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 1;
CS = 2;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 1;
CS = 3;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
end
always #1 Clk = ~Clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_TB_V
`define SKY130_FD_SC_HS__A222O_TB_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a222o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 C1 = 1'b1;
#280 C2 = 1'b1;
#300 VGND = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 C1 = 1'b0;
#440 C2 = 1'b0;
#460 VGND = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VGND = 1'b1;
#540 C2 = 1'b1;
#560 C1 = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VGND = 1'bx;
#700 C2 = 1'bx;
#720 C1 = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hs__a222o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_TB_V
|
module top
(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
parameter SRL_COUNT = 4;
parameter PRESCALER = 4;
// UART loopback
assign tx = rx;
// ============================================================================
// Reset
reg [3:0] rst_sr;
wire rst;
initial rst_sr <= 4'hF;
always @(posedge clk)
if (sw[0]) rst_sr <= 4'hF;
else rst_sr <= rst_sr >> 1;
assign rst = rst_sr[0];
// ============================================================================
// Clock prescaler
reg [32:0] ps_cnt = 0;
wire ps_tick = ps_cnt[32];
always @(posedge clk)
if (rst || ps_tick)
ps_cnt <= PRESCALER - 2;
else
ps_cnt <= ps_cnt - 1;
// ============================================================================
// SRL32 testers
wire sim_error = sw[2];
wire [SRL_COUNT-1:0] srl_q31;
wire [SRL_COUNT-1:0] error;
genvar i;
generate for(i=0; i<SRL_COUNT; i=i+1) begin
wire srl_d;
wire srl_sh;
srl_shift_tester #
(
.FIXED_DELAY (32)
)
tester
(
.clk (clk),
.rst (rst),
.ce (ps_tick),
.srl_sh (srl_sh),
.srl_d (srl_d),
.srl_q (srl_q31[i] ^ sim_error),
.srl_a (),
.error (error[i])
);
SRLC32E srl
(
.CLK (clk),
.CE (srl_sh),
.A (5'd0),
.D (srl_d),
.Q31 (srl_q31[i])
);
end endgenerate
// ============================================================================
// Error latch
reg [SRL_COUNT-1:0] error_lat = 0;
always @(posedge clk)
if (rst)
error_lat <= 0;
else
error_lat <= error_lat | error;
// ============================================================================
// Create a non-GND/VCC source for additional LED outputs.
// This is a side affect of the ROI disallowing GND/VCC connections to synth
// IO pads.
wire net_0;
LUT2 #(.INIT(4'hC)) lut_0 (.I0(|sw), .I1(&sw), .O(net_0));
// LEDs
genvar j;
generate for(j=0; j<8; j=j+1) begin
if (j < SRL_COUNT) begin
assign led[j ] = (sw[1]) ? error_lat[j] : error[j];
assign led[j+8] = srl_q31[j];
end else begin
assign led[j ] = net_0;
assign led[j+8] = net_0;
end
end endgenerate
endmodule
|
/*************************************************************************
* This file is part of Stierlitz: *
* https://github.com/asciilifeform/Stierlitz *
*************************************************************************/
/*************************************************************************
* (c) Copyright 2012 Stanislav Datskovskiy *
* http://www.loper-os.org *
**************************************************************************
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
* *
*************************************************************************/
`timescale 1ns/100ps
`include "stierlitz.v"
module stierlitz_testbench;
/* The basics */
// input wire sys_clk;
reg hpi_clock = 0;
// input wire sys_rst_pin;
reg sys_rst_pin;
input wire CBUTTON; /* These buttons are active-high */
input wire EBUTTON;
output wire [7:0] led_byte;
/* CY7C67300 */
output wire sace_usb_oen;
output wire sace_usb_wen;
output wire usb_csn;
wire usb_hpi_int;
output wire [1:0] sace_usb_a;
wire [15:0] sace_usb_d;
output wire usb_hpi_reset_n;
// reg usb_hpi_int;
// reg [15:0] sace_usb_d;
reg hpi_int = 0;
reg [15:0] usb_d = 0;
assign usb_hpi_int = hpi_int;
assign sace_usb_d = ~sace_usb_oen ? usb_d : 'bz;
wire usbreset = ~sys_rst_pin;
wire sbus_ready;
wire sbus_rw;
wire sbus_start_op;
wire [40:0] sbus_address;
wire [7:0] sbus_data;
reg sb_data = 0;
assign sbus_data = sbus_rw ? sb_data : 'bz;
assign sbus_ready = 1;
stierlitz s(.clk(hpi_clock),
.reset(usbreset),
.enable(1),
/* Control wiring */
.bus_ready(sbus_ready),
.bus_address(sbus_address),
.bus_data(sbus_data),
.bus_rw(sbus_rw),
.bus_start_op(sbus_start_op),
/* CY7C67300 connections */
.cy_hpi_address(sace_usb_a),
.cy_hpi_data(sace_usb_d),
.cy_hpi_oen(sace_usb_oen),
.cy_hpi_wen(sace_usb_wen),
.cy_hpi_csn(usb_csn),
.cy_hpi_irq(usb_hpi_int),
.cy_hpi_resetn(usb_hpi_reset_n)
);
/* 16 MHz (x2) clock for HPI interface */
// wire hpi_clock;
// reg [2:0] clkdiv;
// always @(posedge sys_clk, posedge usbreset)
// if (usbreset)
// begin
// clkdiv <= 0;
// end
// else
// begin
// clkdiv <= clkdiv + 1;
// end
// assign hpi_clock = clkdiv[2];
// 100MHz
always
begin
hpi_clock <= 1'b1;
#5;
hpi_clock <= 1'b0;
#5;
end
parameter T = 1;
parameter P = 160;
always @(posedge hpi_clock)
if (~sace_usb_oen)
begin
#T;
hpi_int <= 0;
end
initial
begin: Init
#0 $display ("Init!\n");
#0 sys_rst_pin = 1;
// system reset active
sys_rst_pin = 0;
#P;
#P;
sys_rst_pin = 1;
#P;
#P;
// end of system reset
end
always
begin
// start of test
#P;
#P;
#P;
#P;
#P;
// Set up LBA address:
// LBA-0
usb_d = 'h00AA;
hpi_int = 1;
#P;
// LBA-1
usb_d = 'h01BB;
hpi_int = 1;
#P;
// LBA-2
usb_d = 'h02CC;
hpi_int = 1;
#P;
// LBA-3
usb_d = 'h03DD;
hpi_int = 1;
#P;
// Write '0x01'
usb_d = 'h8001;
hpi_int = 1;
#P;
// Write '0x02'
usb_d = 'h8002;
hpi_int = 1;
#P;
// Write '0x03'
usb_d = 'h8003;
hpi_int = 1;
#P;
// Write '0x04'
usb_d = 'h8004;
hpi_int = 1;
#P;
// Write '0x05'
usb_d = 'h8005;
hpi_int = 1;
#P;
// // Read
// sb_data = 'h01;
// usb_d = 'h4000;
// hpi_int = 1;
// #P;
// // Read
// sb_data = 'h02;
// usb_d = 'h4000;
// hpi_int = 1;
// #P;
// // Read
// sb_data = 'h03;
// usb_d = 'h4000;
// hpi_int = 1;
// #P;
// // Read
// sb_data = 'h04;
// usb_d = 'h4000;
// hpi_int = 1;
// #P;
// // Read
// sb_data = 'h05;
// usb_d = 'h4000;
// hpi_int = 1;
// #P;
// end of test
#P;
#P;
#P;
#P;
#P;
$finish;
end
initial
begin
$dumpfile("wave.vcd");
$dumpvars(0,
hpi_clock,
usbreset,
usb_csn,
sace_usb_oen,
sace_usb_wen,
usb_hpi_int,
sace_usb_a,
sace_usb_d,
sbus_ready,
sbus_rw,
sbus_start_op,
sbus_address,
sbus_data
);
end
endmodule |
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI Slave
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// mem_sim_axi_slave
//
//--------------------------------------------------------------------------
//
// アクセスのデータ幅は、定義されたデータ幅だけに対応する
`default_nettype none
module mem_sim_axi_slave # (
parameter integer C_S_AXI_ID_WIDTH = 1,
parameter integer C_S_AXI_ADDR_WIDTH = 32,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_AWUSER_WIDTH = 1,
parameter integer C_S_AXI_ARUSER_WIDTH = 1,
parameter integer C_S_AXI_WUSER_WIDTH = 1,
parameter integer C_S_AXI_RUSER_WIDTH = 1,
parameter integer C_S_AXI_BUSER_WIDTH = 1,
parameter integer C_MEMORY_SIZE = 512 // Word (not byte)
) (
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_S_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [8-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [4-1:0] S_AXI_AWREGION,
input wire [4-1:0] S_AXI_AWQOS,
input wire [C_S_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_S_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_S_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_S_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_S_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_S_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [8-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [4-1:0] S_AXI_ARREGION,
input wire [4-1:0] S_AXI_ARQOS,
input wire [C_S_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_S_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_S_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
// Value of S_AXI_BRESP
localparam RESP_OKAY = 2'b00,
RESP_EXOKAY = 2'b01,
RESP_SLVERR = 2'b10,
RESP_DECERR = 2'b11;
// Value of S_AXI_ARBURST
localparam AxBURST_FIXED = 2'b00,
AxBURST_INCR = 2'b01,
AxBURST_WRAP = 2'b10;
localparam IDLE_WADDR = 1'b0,
AWREADY_HOLD_OFF = 1'b1;
reg waddr_sm_cs;
reg awready;
reg awid;
reg [C_S_AXI_ADDR_WIDTH-1:0] waddr;
reg [C_S_AXI_ID_WIDTH-1:0] wid;
reg [2-1:0] awburst;
localparam IDLE_WDATA = 1'b0,
WREADY_ASSERT = 1'b1;
reg wdata_sm_cs;
reg wready;
localparam IDLE_WRES = 1'b0,
BVALID_ASSERT = 1'b1;
reg wres_sm_cs;
reg [2-1:0] bresp;
reg bvalid;
localparam IDLE_RADDR = 1'b0,
ARREADY_HOLD_OFF = 1'b1;
reg raddr_sm_cs;
reg arready;
reg [C_S_AXI_ID_WIDTH-1:0] arid;
reg [C_S_AXI_ADDR_WIDTH-1:0] raddr;
localparam IDLE_RDATA = 1'b0,
RVALID_ASSERT = 1'b1;
reg rdata_sm_cs;
reg rvalid;
reg [C_S_AXI_ID_WIDTH-1:0] rid;
reg [1:0] rresp;
reg [8:0] rdata_count;
localparam IDLE_RLAST = 1'b0,
RLAST_ASSERT = 1'b1;
reg rlast_sm_cs;
reg rlast;
// instance memory_8bit
generate
genvar i;
for (i=(C_S_AXI_DATA_WIDTH/8-1); i>=0; i=i-1) begin : MEMORY_GEN
memory_8bit #(
.C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
.C_MEMORY_SIZE(C_MEMORY_SIZE)
) memory_8bit_i (
.clk(ACLK),
.waddr(waddr),
.write_data(S_AXI_WDATA[i*8+7:i*8]),
.write_enable(wready & S_AXI_WVALID),
.byte_enable(S_AXI_WSTRB[i]),
.raddr(raddr),
.read_data(S_AXI_RDATA[i*8+7:i*8])
);
end
endgenerate
// Write Transaction
assign S_AXI_BUSER = 1'd0;
// waddr State Machine
// awready is normally 1. if S_AXI_AWVALID is 1 then awready is 0.
always @(posedge ACLK) begin
if (ARESETN == 1'b0) begin
waddr_sm_cs <= IDLE_WADDR;
awready <= 1'b1;
awid <= {C_S_AXI_ID_WIDTH{1'b0}};
awburst <= 2'd0;
end else begin
case (waddr_sm_cs)
IDLE_WADDR :
if (S_AXI_AWVALID) begin
waddr_sm_cs <= AWREADY_HOLD_OFF;
awready <= 1'b0;
awid <= S_AXI_AWID;
awburst <= S_AXI_AWBURST;
end
AWREADY_HOLD_OFF :
if (bvalid) begin
waddr_sm_cs <= IDLE_WADDR;
awready <= 1'b1;
end
endcase
end
end
assign S_AXI_AWREADY = awready;
// waddr
always @(posedge ACLK) begin
if (ARESETN == 1'b0) begin
waddr <= {C_S_AXI_ADDR_WIDTH{1'b0}};
end else begin
if (waddr_sm_cs == IDLE_WADDR & S_AXI_AWVALID)
waddr <= S_AXI_AWADDR;
else if (wready & S_AXI_WVALID)
waddr <= waddr + C_S_AXI_DATA_WIDTH/8;
end
end
// wdata State Machine
always @(posedge ACLK) begin
if (ARESETN == 1'b0) begin
wdata_sm_cs <= IDLE_WDATA;
wready <= 1'b0;
end else begin
case (wdata_sm_cs)
IDLE_WDATA :
if (waddr_sm_cs == IDLE_WADDR && S_AXI_AWVALID) begin // Write transaction start
wdata_sm_cs <= WREADY_ASSERT;
wready <= 1'b1;
end
WREADY_ASSERT :
if (S_AXI_WLAST & S_AXI_WVALID) begin // Write transaction end
wdata_sm_cs <= IDLE_WDATA;
wready <= 1'b0;
end
endcase
end
end
assign S_AXI_WREADY = wready;
assign S_AXI_BID = awid;
// Write Response State Machine
always @(posedge ACLK) begin
if (ARESETN == 1'b0) begin
wres_sm_cs <= IDLE_WRES;
bvalid <= 1'b0;
end else begin
case (wres_sm_cs)
IDLE_WRES :
if (wdata_sm_cs == WREADY_ASSERT & S_AXI_WLAST & S_AXI_WVALID) begin // Write transaction end
wres_sm_cs <= BVALID_ASSERT;
bvalid <= 1'b1;
end
BVALID_ASSERT :
if (S_AXI_BREADY) begin
wres_sm_cs <= IDLE_WRES;
bvalid <= 1'b0;
end
endcase
end
end
assign S_AXI_BVALID = bvalid;
// bresp
// if S_AXI_AWBURST is INCR then return OKAY else return SLVERR
always @(posedge ACLK) begin
if (ARESETN == 1'b0)
bresp <= 2'b0;
else begin
if (waddr_sm_cs == AWREADY_HOLD_OFF) begin
if (awburst == AxBURST_INCR) // The burst type is Addres Increment Type
bresp <= RESP_OKAY; // The Write Transaction is success
else
bresp <= RESP_SLVERR; // Error
end
end
end
assign S_AXI_BRESP = bresp;
// Read Transaction
assign S_AXI_RUSER = 0;
// raddr State Machine
// arready is normally 1. if S_AXI_ARVALID is 1 then arready is 0.
always @(posedge ACLK) begin
if (ARESETN == 1'b0) begin
raddr_sm_cs <= IDLE_RADDR;
arready <= 1'b1;
arid <= {C_S_AXI_ID_WIDTH{1'b0}};
end else begin
case (raddr_sm_cs)
IDLE_RADDR :
if (S_AXI_ARVALID) begin
raddr_sm_cs <= ARREADY_HOLD_OFF;
arready <= 1'b0;
arid <= S_AXI_ARID;
end
ARREADY_HOLD_OFF :
if (rvalid & S_AXI_RREADY & S_AXI_RLAST) begin // Read Transaction End
raddr_sm_cs <= IDLE_RADDR;
arready <= 1'b1;
end
endcase
end
end
assign S_AXI_ARREADY = arready;
// raddr
always @(posedge ACLK) begin
if (ARESETN == 1'b0) begin
raddr <= {C_S_AXI_ADDR_WIDTH{1'b0}};
end else begin
if (raddr_sm_cs == IDLE_RADDR & S_AXI_ARVALID)
raddr <= S_AXI_ARADDR;
else if (rvalid & S_AXI_RREADY)
raddr <= raddr + C_S_AXI_ADDR_WIDTH/8;
end
end
// rdata State Machine
always @(posedge ACLK) begin
if (ARESETN == 1'b0) begin
rdata_sm_cs <= IDLE_RDATA;
rvalid <= 1'b0;
rid <= {C_S_AXI_ID_WIDTH{1'b0}};
end else begin
case (rdata_sm_cs)
IDLE_RDATA :
if (raddr_sm_cs == IDLE_RADDR & S_AXI_ARVALID) begin
rdata_sm_cs <= RVALID_ASSERT;
rvalid <= 1'b1;
end
RVALID_ASSERT :
if (rlast & S_AXI_RREADY) begin
rdata_sm_cs <= IDLE_RDATA;
rvalid <= 1'b0;
end
endcase
end
end
assign S_AXI_RVALID = rvalid;
assign S_AXI_RID = arid;
// assign S_AXI_RRESP = RESP_OKAY;
always @(posedge ACLK) begin
if (ARESETN == 1'b0) begin
rresp <= RESP_OKAY;
end else if (rdata_sm_cs == RVALID_ASSERT && rid != arid) begin
rresp <= RESP_SLVERR;
end
end
assign S_AXI_RRESP = rresp;
// rdata_count
always @(posedge ACLK) begin
if (ARESETN == 1'b0) begin
rdata_count <= 9'd0;
end else begin
if (raddr_sm_cs == IDLE_RADDR & S_AXI_ARVALID)
rdata_count <= {1'b0, S_AXI_ARLEN} + 9'd1;
else if (rvalid & S_AXI_RREADY)
rdata_count <= rdata_count - 9'd1;
end
end
// rlast
always @(posedge ACLK) begin
if (ARESETN == 1'b0) begin
rlast_sm_cs <= IDLE_RLAST;
rlast <= 1'b0;
end else begin
case (rlast_sm_cs)
IDLE_RLAST :
if (rdata_count == 9'd2 && (rvalid & S_AXI_RREADY)) begin
rlast_sm_cs <= RLAST_ASSERT;
rlast <= 1'b1;
end else if (raddr_sm_cs==IDLE_RADDR && S_AXI_ARVALID==1'b1 && S_AXI_ARLEN==8'd0) begin
// 転送数が1の時はデータ転送の最初からrlast を1にする
rlast_sm_cs <= RLAST_ASSERT;
rlast <= 1'b1;
end
RLAST_ASSERT :
if (rvalid & S_AXI_RREADY) begin
rlast_sm_cs <= IDLE_RLAST;
rlast <= 1'b0;
end
endcase
end
end
assign S_AXI_RLAST = rlast;
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : fme_ip_quarter_ver.v
// Author : Yufeng Bai
// Email : [email protected]
//
// $Id$
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fme_ip_quarter_ver (
clk ,
rstn ,
blk_start_i ,
refpel_valid_i ,
hor_start_i ,
horbuf_valid_i ,
frac_x_i ,
frac_y_i ,
q1_buf0_i ,
q1_buf1_i ,
q1_buf2_i ,
q1_buf3_i ,
q1_buf4_i ,
q1_buf5_i ,
q1_buf6_i ,
q1_buf7_i ,
q3_buf0_i ,
q3_buf1_i ,
q3_buf2_i ,
q3_buf3_i ,
q3_buf4_i ,
q3_buf5_i ,
q3_buf6_i ,
q3_buf7_i ,
h_buf0_i ,
h_buf1_i ,
h_buf2_i ,
h_buf3_i ,
h_buf4_i ,
h_buf5_i ,
h_buf6_i ,
h_buf7_i ,
ref_pel0_i ,
ref_pel1_i ,
ref_pel2_i ,
ref_pel3_i ,
ref_pel4_i ,
ref_pel5_i ,
ref_pel6_i ,
ref_pel7_i ,
//vquarter_1_valid_o , // [1][1]. [3][1]
//vquarter_3_valid_o , // [1][3], [3][3]
//vquarter_2_valid_o , // [1][2], [3][2]
//vquarter_0_valid_o , // [1][0], [3][0]
//vhalf_valid_o , // [2][1], [2][3]
//vpel_valid_o , // [0][1], [0][3]
vquarter_1_1_pel0_o ,
vquarter_1_1_pel1_o ,
vquarter_1_1_pel2_o ,
vquarter_1_1_pel3_o ,
vquarter_1_1_pel4_o ,
vquarter_1_1_pel5_o ,
vquarter_1_1_pel6_o ,
vquarter_1_1_pel7_o ,
vquarter_1_3_pel0_o ,
vquarter_1_3_pel1_o ,
vquarter_1_3_pel2_o ,
vquarter_1_3_pel3_o ,
vquarter_1_3_pel4_o ,
vquarter_1_3_pel5_o ,
vquarter_1_3_pel6_o ,
vquarter_1_3_pel7_o ,
vquarter_1_2_pel0_o ,
vquarter_1_2_pel1_o ,
vquarter_1_2_pel2_o ,
vquarter_1_2_pel3_o ,
vquarter_1_2_pel4_o ,
vquarter_1_2_pel5_o ,
vquarter_1_2_pel6_o ,
vquarter_1_2_pel7_o ,
vquarter_1_0_pel0_o ,
vquarter_1_0_pel1_o ,
vquarter_1_0_pel2_o ,
vquarter_1_0_pel3_o ,
vquarter_1_0_pel4_o ,
vquarter_1_0_pel5_o ,
vquarter_1_0_pel6_o ,
vquarter_1_0_pel7_o ,
vquarter_3_1_pel0_o ,
vquarter_3_1_pel1_o ,
vquarter_3_1_pel2_o ,
vquarter_3_1_pel3_o ,
vquarter_3_1_pel4_o ,
vquarter_3_1_pel5_o ,
vquarter_3_1_pel6_o ,
vquarter_3_1_pel7_o ,
vquarter_3_3_pel0_o ,
vquarter_3_3_pel1_o ,
vquarter_3_3_pel2_o ,
vquarter_3_3_pel3_o ,
vquarter_3_3_pel4_o ,
vquarter_3_3_pel5_o ,
vquarter_3_3_pel6_o ,
vquarter_3_3_pel7_o ,
vquarter_3_2_pel0_o ,
vquarter_3_2_pel1_o ,
vquarter_3_2_pel2_o ,
vquarter_3_2_pel3_o ,
vquarter_3_2_pel4_o ,
vquarter_3_2_pel5_o ,
vquarter_3_2_pel6_o ,
vquarter_3_2_pel7_o ,
vquarter_3_0_pel0_o ,
vquarter_3_0_pel1_o ,
vquarter_3_0_pel2_o ,
vquarter_3_0_pel3_o ,
vquarter_3_0_pel4_o ,
vquarter_3_0_pel5_o ,
vquarter_3_0_pel6_o ,
vquarter_3_0_pel7_o ,
vpel_0_1_pel0_o ,
vpel_0_1_pel1_o ,
vpel_0_1_pel2_o ,
vpel_0_1_pel3_o ,
vpel_0_1_pel4_o ,
vpel_0_1_pel5_o ,
vpel_0_1_pel6_o ,
vpel_0_1_pel7_o ,
vpel_0_3_pel0_o ,
vpel_0_3_pel1_o ,
vpel_0_3_pel2_o ,
vpel_0_3_pel3_o ,
vpel_0_3_pel4_o ,
vpel_0_3_pel5_o ,
vpel_0_3_pel6_o ,
vpel_0_3_pel7_o ,
vhalf_2_1_pel0_o ,
vhalf_2_1_pel1_o ,
vhalf_2_1_pel2_o ,
vhalf_2_1_pel3_o ,
vhalf_2_1_pel4_o ,
vhalf_2_1_pel5_o ,
vhalf_2_1_pel6_o ,
vhalf_2_1_pel7_o ,
vhalf_2_3_pel0_o ,
vhalf_2_3_pel1_o ,
vhalf_2_3_pel2_o ,
vhalf_2_3_pel3_o ,
vhalf_2_3_pel4_o ,
vhalf_2_3_pel5_o ,
vhalf_2_3_pel6_o ,
vhalf_2_3_pel7_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] blk_start_i ; // 8x8 block interpolation start signal
input [1-1:0] refpel_valid_i ; // referenced pixel valid
input [1-1:0] hor_start_i ; // 8x8 block horizontal interpolation start signal
input [1-1:0] horbuf_valid_i ; // horizontal buf pixel valid
input [2-1:0] frac_x_i ; // frac_x: 00: ==0, 01: <0, 10:>0
input [2-1:0] frac_y_i ; // frac_y: 00: ==0, 01: <0, 10:>0
input [2*`PIXEL_WIDTH-1:0] q1_buf0_i ; // horizontal quarter 1 interpolation results 0
input [2*`PIXEL_WIDTH-1:0] q1_buf1_i ; // horizontal quarter 1 interpolation results 1
input [2*`PIXEL_WIDTH-1:0] q1_buf2_i ; // horizontal quarter 1 interpolation results 2
input [2*`PIXEL_WIDTH-1:0] q1_buf3_i ; // horizontal quarter 1 interpolation results 3
input [2*`PIXEL_WIDTH-1:0] q1_buf4_i ; // horizontal quarter 1 interpolation results 4
input [2*`PIXEL_WIDTH-1:0] q1_buf5_i ; // horizontal quarter 1 interpolation results 5
input [2*`PIXEL_WIDTH-1:0] q1_buf6_i ; // horizontal quarter 1 interpolation results 6
input [2*`PIXEL_WIDTH-1:0] q1_buf7_i ; // horizontal quarter 1 interpolation results 7
input [2*`PIXEL_WIDTH-1:0] q3_buf0_i ; // horizontal quarter 3 interpolation results 0
input [2*`PIXEL_WIDTH-1:0] q3_buf1_i ; // horizontal quarter 3 interpolation results 1
input [2*`PIXEL_WIDTH-1:0] q3_buf2_i ; // horizontal quarter 3 interpolation results 2
input [2*`PIXEL_WIDTH-1:0] q3_buf3_i ; // horizontal quarter 3 interpolation results 3
input [2*`PIXEL_WIDTH-1:0] q3_buf4_i ; // horizontal quarter 3 interpolation results 4
input [2*`PIXEL_WIDTH-1:0] q3_buf5_i ; // horizontal quarter 3 interpolation results 5
input [2*`PIXEL_WIDTH-1:0] q3_buf6_i ; // horizontal quarter 3 interpolation results 6
input [2*`PIXEL_WIDTH-1:0] q3_buf7_i ; // horizontal quarter 3 interpolation results 7
input [2*`PIXEL_WIDTH-1:0] h_buf0_i ; // horizontal half interpolation results 0
input [2*`PIXEL_WIDTH-1:0] h_buf1_i ; // horizontal half interpolation results 1
input [2*`PIXEL_WIDTH-1:0] h_buf2_i ; // horizontal half interpolation results 2
input [2*`PIXEL_WIDTH-1:0] h_buf3_i ; // horizontal half interpolation results 3
input [2*`PIXEL_WIDTH-1:0] h_buf4_i ; // horizontal half interpolation results 4
input [2*`PIXEL_WIDTH-1:0] h_buf5_i ; // horizontal half interpolation results 5
input [2*`PIXEL_WIDTH-1:0] h_buf6_i ; // horizontal half interpolation results 6
input [2*`PIXEL_WIDTH-1:0] h_buf7_i ; // horizontal half interpolation results 7
input [`PIXEL_WIDTH-1:0] ref_pel0_i ; // referenced pixel 0
input [`PIXEL_WIDTH-1:0] ref_pel1_i ; // referenced pixel 1
input [`PIXEL_WIDTH-1:0] ref_pel2_i ; // referenced pixel 2
input [`PIXEL_WIDTH-1:0] ref_pel3_i ; // referenced pixel 3
input [`PIXEL_WIDTH-1:0] ref_pel4_i ; // referenced pixel 4
input [`PIXEL_WIDTH-1:0] ref_pel5_i ; // referenced pixel 5
input [`PIXEL_WIDTH-1:0] ref_pel6_i ; // referenced pixel 6
input [`PIXEL_WIDTH-1:0] ref_pel7_i ; // referenced pixel 7
//output [1-1:0] vquarter_1_valid_o ; // vertical quarter 1 predicted pixels output valid
//output [1-1:0] vquarter_3_valid_o ; // vertical quarter 3 predicted pixels output valid
//output [1-1:0] vquarter_2_valid_o ; // vertical quarter 2 predicted pixels output valid
//output [1-1:0] vquarter_0_valid_o ; // vertical quarter 0 predicted pixels output valid
//output [1-1:0] vhalf_valid_o ; // vertical half predicted pixels output valid
//output [1-1:0] vpel_valid_o ; // cliped half predicted pixels output valid
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel0_o ; // from q1 vertical quarter 1 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel1_o ; // from q1 vertical quarter 1 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel2_o ; // from q1 vertical quarter 1 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel3_o ; // from q1 vertical quarter 1 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel4_o ; // from q1 vertical quarter 1 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel5_o ; // from q1 vertical quarter 1 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel6_o ; // from q1 vertical quarter 1 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel7_o ; // from q1 vertical quarter 1 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel0_o ; // from q3 vertical quarter 1 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel1_o ; // from q3 vertical quarter 1 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel2_o ; // from q3 vertical quarter 1 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel3_o ; // from q3 vertical quarter 1 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel4_o ; // from q3 vertical quarter 1 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel5_o ; // from q3 vertical quarter 1 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel6_o ; // from q3 vertical quarter 1 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel7_o ; // from q3 vertical quarter 1 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel0_o ; // from half vertical quarter 1 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel1_o ; // from half vertical quarter 1 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel2_o ; // from half vertical quarter 1 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel3_o ; // from half vertical quarter 1 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel4_o ; // from half vertical quarter 1 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel5_o ; // from half vertical quarter 1 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel6_o ; // from half vertical quarter 1 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel7_o ; // from half vertical quarter 1 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel0_o ; // from ref vertical quarter 1 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel1_o ; // from ref vertical quarter 1 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel2_o ; // from ref vertical quarter 1 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel3_o ; // from ref vertical quarter 1 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel4_o ; // from ref vertical quarter 1 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel5_o ; // from ref vertical quarter 1 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel6_o ; // from ref vertical quarter 1 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel7_o ; // from ref vertical quarter 1 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel0_o ; // from q1 vertical quarter 3 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel1_o ; // from q1 vertical quarter 3 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel2_o ; // from q1 vertical quarter 3 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel3_o ; // from q1 vertical quarter 3 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel4_o ; // from q1 vertical quarter 3 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel5_o ; // from q1 vertical quarter 3 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel6_o ; // from q1 vertical quarter 3 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel7_o ; // from q1 vertical quarter 3 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel0_o ; // from q3 vertical quarter 3 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel1_o ; // from q3 vertical quarter 3 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel2_o ; // from q3 vertical quarter 3 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel3_o ; // from q3 vertical quarter 3 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel4_o ; // from q3 vertical quarter 3 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel5_o ; // from q3 vertical quarter 3 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel6_o ; // from q3 vertical quarter 3 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel7_o ; // from q3 vertical quarter 3 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel0_o ; // from ref vertical quarter 3 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel1_o ; // from ref vertical quarter 3 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel2_o ; // from ref vertical quarter 3 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel3_o ; // from ref vertical quarter 3 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel4_o ; // from ref vertical quarter 3 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel5_o ; // from ref vertical quarter 3 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel6_o ; // from ref vertical quarter 3 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel7_o ; // from ref vertical quarter 3 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel0_o ; // from half vertical quarter 3 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel1_o ; // from half vertical quarter 3 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel2_o ; // from half vertical quarter 3 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel3_o ; // from half vertical quarter 3 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel4_o ; // from half vertical quarter 3 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel5_o ; // from half vertical quarter 3 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel6_o ; // from half vertical quarter 3 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel7_o ; // from half vertical quarter 3 pixel 7
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel0_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel1_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel2_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel3_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel4_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel5_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel6_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel7_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel0_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel1_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel2_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel3_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel4_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel5_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel6_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel7_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel0_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel1_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel2_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel3_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel4_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel5_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel6_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel7_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel0_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel1_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel2_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel3_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel4_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel5_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel6_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel7_o ;
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg [3 :0] cnt_ref;
reg [3 :0] cnt_hor;
reg [2*`PIXEL_WIDTH-1:0] q1_buf0_d1, q1_buf0_d2, q1_buf0_d3, q1_buf0_d4, q1_buf0_d5, q1_buf0_d6, q1_buf0_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf1_d1, q1_buf1_d2, q1_buf1_d3, q1_buf1_d4, q1_buf1_d5, q1_buf1_d6, q1_buf1_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf2_d1, q1_buf2_d2, q1_buf2_d3, q1_buf2_d4, q1_buf2_d5, q1_buf2_d6, q1_buf2_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf3_d1, q1_buf3_d2, q1_buf3_d3, q1_buf3_d4, q1_buf3_d5, q1_buf3_d6, q1_buf3_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf4_d1, q1_buf4_d2, q1_buf4_d3, q1_buf4_d4, q1_buf4_d5, q1_buf4_d6, q1_buf4_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf5_d1, q1_buf5_d2, q1_buf5_d3, q1_buf5_d4, q1_buf5_d5, q1_buf5_d6, q1_buf5_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf6_d1, q1_buf6_d2, q1_buf6_d3, q1_buf6_d4, q1_buf6_d5, q1_buf6_d6, q1_buf6_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf7_d1, q1_buf7_d2, q1_buf7_d3, q1_buf7_d4, q1_buf7_d5, q1_buf7_d6, q1_buf7_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf0_d1, q3_buf0_d2, q3_buf0_d3, q3_buf0_d4, q3_buf0_d5, q3_buf0_d6, q3_buf0_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf1_d1, q3_buf1_d2, q3_buf1_d3, q3_buf1_d4, q3_buf1_d5, q3_buf1_d6, q3_buf1_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf2_d1, q3_buf2_d2, q3_buf2_d3, q3_buf2_d4, q3_buf2_d5, q3_buf2_d6, q3_buf2_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf3_d1, q3_buf3_d2, q3_buf3_d3, q3_buf3_d4, q3_buf3_d5, q3_buf3_d6, q3_buf3_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf4_d1, q3_buf4_d2, q3_buf4_d3, q3_buf4_d4, q3_buf4_d5, q3_buf4_d6, q3_buf4_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf5_d1, q3_buf5_d2, q3_buf5_d3, q3_buf5_d4, q3_buf5_d5, q3_buf5_d6, q3_buf5_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf6_d1, q3_buf6_d2, q3_buf6_d3, q3_buf6_d4, q3_buf6_d5, q3_buf6_d6, q3_buf6_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf7_d1, q3_buf7_d2, q3_buf7_d3, q3_buf7_d4, q3_buf7_d5, q3_buf7_d6, q3_buf7_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf0_d1, h_buf0_d2, h_buf0_d3, h_buf0_d4, h_buf0_d5, h_buf0_d6, h_buf0_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf1_d1, h_buf1_d2, h_buf1_d3, h_buf1_d4, h_buf1_d5, h_buf1_d6, h_buf1_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf2_d1, h_buf2_d2, h_buf2_d3, h_buf2_d4, h_buf2_d5, h_buf2_d6, h_buf2_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf3_d1, h_buf3_d2, h_buf3_d3, h_buf3_d4, h_buf3_d5, h_buf3_d6, h_buf3_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf4_d1, h_buf4_d2, h_buf4_d3, h_buf4_d4, h_buf4_d5, h_buf4_d6, h_buf4_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf5_d1, h_buf5_d2, h_buf5_d3, h_buf5_d4, h_buf5_d5, h_buf5_d6, h_buf5_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf6_d1, h_buf6_d2, h_buf6_d3, h_buf6_d4, h_buf6_d5, h_buf6_d6, h_buf6_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf7_d1, h_buf7_d2, h_buf7_d3, h_buf7_d4, h_buf7_d5, h_buf7_d6, h_buf7_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel0_d1, ref_pel0_d2, ref_pel0_d3, ref_pel0_d4, ref_pel0_d5, ref_pel0_d6, ref_pel0_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel1_d1, ref_pel1_d2, ref_pel1_d3, ref_pel1_d4, ref_pel1_d5, ref_pel1_d6, ref_pel1_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel2_d1, ref_pel2_d2, ref_pel2_d3, ref_pel2_d4, ref_pel2_d5, ref_pel2_d6, ref_pel2_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel3_d1, ref_pel3_d2, ref_pel3_d3, ref_pel3_d4, ref_pel3_d5, ref_pel3_d6, ref_pel3_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel4_d1, ref_pel4_d2, ref_pel4_d3, ref_pel4_d4, ref_pel4_d5, ref_pel4_d6, ref_pel4_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel5_d1, ref_pel5_d2, ref_pel5_d3, ref_pel5_d4, ref_pel5_d5, ref_pel5_d6, ref_pel5_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel6_d1, ref_pel6_d2, ref_pel6_d3, ref_pel6_d4, ref_pel6_d5, ref_pel6_d6, ref_pel6_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel7_d1, ref_pel7_d2, ref_pel7_d3, ref_pel7_d4, ref_pel7_d5, ref_pel7_d6, ref_pel7_d7;
//wire cnthorLargerThan3;
//wire cnthorLargerThan4;
//
//wire cntrefLargerThan7;
//wire cntrefLargerThan8;
//
//wire cnthorLargerThan7;
//wire cnthorLargerThan8;
// ********************************************
//
// Combinational Logic
//
// ********************************************
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
q1_buf0_d1 <= 'd0; q1_buf0_d2 <= 'd0; q1_buf0_d3 <= 'd0; q1_buf0_d4 <= 'd0; q1_buf0_d5 <= 'd0; q1_buf0_d6 <= 'd0; q1_buf0_d7 <= 'd0;
q1_buf1_d1 <= 'd0; q1_buf1_d2 <= 'd0; q1_buf1_d3 <= 'd0; q1_buf1_d4 <= 'd0; q1_buf1_d5 <= 'd0; q1_buf1_d6 <= 'd0; q1_buf1_d7 <= 'd0;
q1_buf2_d1 <= 'd0; q1_buf2_d2 <= 'd0; q1_buf2_d3 <= 'd0; q1_buf2_d4 <= 'd0; q1_buf2_d5 <= 'd0; q1_buf2_d6 <= 'd0; q1_buf2_d7 <= 'd0;
q1_buf3_d1 <= 'd0; q1_buf3_d2 <= 'd0; q1_buf3_d3 <= 'd0; q1_buf3_d4 <= 'd0; q1_buf3_d5 <= 'd0; q1_buf3_d6 <= 'd0; q1_buf3_d7 <= 'd0;
q1_buf4_d1 <= 'd0; q1_buf4_d2 <= 'd0; q1_buf4_d3 <= 'd0; q1_buf4_d4 <= 'd0; q1_buf4_d5 <= 'd0; q1_buf4_d6 <= 'd0; q1_buf4_d7 <= 'd0;
q1_buf5_d1 <= 'd0; q1_buf5_d2 <= 'd0; q1_buf5_d3 <= 'd0; q1_buf5_d4 <= 'd0; q1_buf5_d5 <= 'd0; q1_buf5_d6 <= 'd0; q1_buf5_d7 <= 'd0;
q1_buf6_d1 <= 'd0; q1_buf6_d2 <= 'd0; q1_buf6_d3 <= 'd0; q1_buf6_d4 <= 'd0; q1_buf6_d5 <= 'd0; q1_buf6_d6 <= 'd0; q1_buf6_d7 <= 'd0;
q1_buf7_d1 <= 'd0; q1_buf7_d2 <= 'd0; q1_buf7_d3 <= 'd0; q1_buf7_d4 <= 'd0; q1_buf7_d5 <= 'd0; q1_buf7_d6 <= 'd0; q1_buf7_d7 <= 'd0;
q3_buf0_d1 <= 'd0; q3_buf0_d2 <= 'd0; q3_buf0_d3 <= 'd0; q3_buf0_d4 <= 'd0; q3_buf0_d5 <= 'd0; q3_buf0_d6 <= 'd0; q3_buf0_d7 <= 'd0;
q3_buf1_d1 <= 'd0; q3_buf1_d2 <= 'd0; q3_buf1_d3 <= 'd0; q3_buf1_d4 <= 'd0; q3_buf1_d5 <= 'd0; q3_buf1_d6 <= 'd0; q3_buf1_d7 <= 'd0;
q3_buf2_d1 <= 'd0; q3_buf2_d2 <= 'd0; q3_buf2_d3 <= 'd0; q3_buf2_d4 <= 'd0; q3_buf2_d5 <= 'd0; q3_buf2_d6 <= 'd0; q3_buf2_d7 <= 'd0;
q3_buf3_d1 <= 'd0; q3_buf3_d2 <= 'd0; q3_buf3_d3 <= 'd0; q3_buf3_d4 <= 'd0; q3_buf3_d5 <= 'd0; q3_buf3_d6 <= 'd0; q3_buf3_d7 <= 'd0;
q3_buf4_d1 <= 'd0; q3_buf4_d2 <= 'd0; q3_buf4_d3 <= 'd0; q3_buf4_d4 <= 'd0; q3_buf4_d5 <= 'd0; q3_buf4_d6 <= 'd0; q3_buf4_d7 <= 'd0;
q3_buf5_d1 <= 'd0; q3_buf5_d2 <= 'd0; q3_buf5_d3 <= 'd0; q3_buf5_d4 <= 'd0; q3_buf5_d5 <= 'd0; q3_buf5_d6 <= 'd0; q3_buf5_d7 <= 'd0;
q3_buf6_d1 <= 'd0; q3_buf6_d2 <= 'd0; q3_buf6_d3 <= 'd0; q3_buf6_d4 <= 'd0; q3_buf6_d5 <= 'd0; q3_buf6_d6 <= 'd0; q3_buf6_d7 <= 'd0;
q3_buf7_d1 <= 'd0; q3_buf7_d2 <= 'd0; q3_buf7_d3 <= 'd0; q3_buf7_d4 <= 'd0; q3_buf7_d5 <= 'd0; q3_buf7_d6 <= 'd0; q3_buf7_d7 <= 'd0;
h_buf0_d1 <= 'd0; h_buf0_d2 <= 'd0; h_buf0_d3 <= 'd0; h_buf0_d4 <= 'd0; h_buf0_d5 <= 'd0; h_buf0_d6 <= 'd0; h_buf0_d7 <= 'd0;
h_buf1_d1 <= 'd0; h_buf1_d2 <= 'd0; h_buf1_d3 <= 'd0; h_buf1_d4 <= 'd0; h_buf1_d5 <= 'd0; h_buf1_d6 <= 'd0; h_buf1_d7 <= 'd0;
h_buf2_d1 <= 'd0; h_buf2_d2 <= 'd0; h_buf2_d3 <= 'd0; h_buf2_d4 <= 'd0; h_buf2_d5 <= 'd0; h_buf2_d6 <= 'd0; h_buf2_d7 <= 'd0;
h_buf3_d1 <= 'd0; h_buf3_d2 <= 'd0; h_buf3_d3 <= 'd0; h_buf3_d4 <= 'd0; h_buf3_d5 <= 'd0; h_buf3_d6 <= 'd0; h_buf3_d7 <= 'd0;
h_buf4_d1 <= 'd0; h_buf4_d2 <= 'd0; h_buf4_d3 <= 'd0; h_buf4_d4 <= 'd0; h_buf4_d5 <= 'd0; h_buf4_d6 <= 'd0; h_buf4_d7 <= 'd0;
h_buf5_d1 <= 'd0; h_buf5_d2 <= 'd0; h_buf5_d3 <= 'd0; h_buf5_d4 <= 'd0; h_buf5_d5 <= 'd0; h_buf5_d6 <= 'd0; h_buf5_d7 <= 'd0;
h_buf6_d1 <= 'd0; h_buf6_d2 <= 'd0; h_buf6_d3 <= 'd0; h_buf6_d4 <= 'd0; h_buf6_d5 <= 'd0; h_buf6_d6 <= 'd0; h_buf6_d7 <= 'd0;
h_buf7_d1 <= 'd0; h_buf7_d2 <= 'd0; h_buf7_d3 <= 'd0; h_buf7_d4 <= 'd0; h_buf7_d5 <= 'd0; h_buf7_d6 <= 'd0; h_buf7_d7 <= 'd0;
end
else if (horbuf_valid_i) begin
q1_buf0_d1 <= q1_buf0_i; q1_buf0_d2 <= q1_buf0_d1; q1_buf0_d3 <= q1_buf0_d2; q1_buf0_d4 <= q1_buf0_d3; q1_buf0_d5 <= q1_buf0_d4; q1_buf0_d6 <= q1_buf0_d5; q1_buf0_d7 <= q1_buf0_d6;
q1_buf1_d1 <= q1_buf1_i; q1_buf1_d2 <= q1_buf1_d1; q1_buf1_d3 <= q1_buf1_d2; q1_buf1_d4 <= q1_buf1_d3; q1_buf1_d5 <= q1_buf1_d4; q1_buf1_d6 <= q1_buf1_d5; q1_buf1_d7 <= q1_buf1_d6;
q1_buf2_d1 <= q1_buf2_i; q1_buf2_d2 <= q1_buf2_d1; q1_buf2_d3 <= q1_buf2_d2; q1_buf2_d4 <= q1_buf2_d3; q1_buf2_d5 <= q1_buf2_d4; q1_buf2_d6 <= q1_buf2_d5; q1_buf2_d7 <= q1_buf2_d6;
q1_buf3_d1 <= q1_buf3_i; q1_buf3_d2 <= q1_buf3_d1; q1_buf3_d3 <= q1_buf3_d2; q1_buf3_d4 <= q1_buf3_d3; q1_buf3_d5 <= q1_buf3_d4; q1_buf3_d6 <= q1_buf3_d5; q1_buf3_d7 <= q1_buf3_d6;
q1_buf4_d1 <= q1_buf4_i; q1_buf4_d2 <= q1_buf4_d1; q1_buf4_d3 <= q1_buf4_d2; q1_buf4_d4 <= q1_buf4_d3; q1_buf4_d5 <= q1_buf4_d4; q1_buf4_d6 <= q1_buf4_d5; q1_buf4_d7 <= q1_buf4_d6;
q1_buf5_d1 <= q1_buf5_i; q1_buf5_d2 <= q1_buf5_d1; q1_buf5_d3 <= q1_buf5_d2; q1_buf5_d4 <= q1_buf5_d3; q1_buf5_d5 <= q1_buf5_d4; q1_buf5_d6 <= q1_buf5_d5; q1_buf5_d7 <= q1_buf5_d6;
q1_buf6_d1 <= q1_buf6_i; q1_buf6_d2 <= q1_buf6_d1; q1_buf6_d3 <= q1_buf6_d2; q1_buf6_d4 <= q1_buf6_d3; q1_buf6_d5 <= q1_buf6_d4; q1_buf6_d6 <= q1_buf6_d5; q1_buf6_d7 <= q1_buf6_d6;
q1_buf7_d1 <= q1_buf7_i; q1_buf7_d2 <= q1_buf7_d1; q1_buf7_d3 <= q1_buf7_d2; q1_buf7_d4 <= q1_buf7_d3; q1_buf7_d5 <= q1_buf7_d4; q1_buf7_d6 <= q1_buf7_d5; q1_buf7_d7 <= q1_buf7_d6;
q3_buf0_d1 <= q3_buf0_i; q3_buf0_d2 <= q3_buf0_d1; q3_buf0_d3 <= q3_buf0_d2; q3_buf0_d4 <= q3_buf0_d3; q3_buf0_d5 <= q3_buf0_d4; q3_buf0_d6 <= q3_buf0_d5; q3_buf0_d7 <= q3_buf0_d6;
q3_buf1_d1 <= q3_buf1_i; q3_buf1_d2 <= q3_buf1_d1; q3_buf1_d3 <= q3_buf1_d2; q3_buf1_d4 <= q3_buf1_d3; q3_buf1_d5 <= q3_buf1_d4; q3_buf1_d6 <= q3_buf1_d5; q3_buf1_d7 <= q3_buf1_d6;
q3_buf2_d1 <= q3_buf2_i; q3_buf2_d2 <= q3_buf2_d1; q3_buf2_d3 <= q3_buf2_d2; q3_buf2_d4 <= q3_buf2_d3; q3_buf2_d5 <= q3_buf2_d4; q3_buf2_d6 <= q3_buf2_d5; q3_buf2_d7 <= q3_buf2_d6;
q3_buf3_d1 <= q3_buf3_i; q3_buf3_d2 <= q3_buf3_d1; q3_buf3_d3 <= q3_buf3_d2; q3_buf3_d4 <= q3_buf3_d3; q3_buf3_d5 <= q3_buf3_d4; q3_buf3_d6 <= q3_buf3_d5; q3_buf3_d7 <= q3_buf3_d6;
q3_buf4_d1 <= q3_buf4_i; q3_buf4_d2 <= q3_buf4_d1; q3_buf4_d3 <= q3_buf4_d2; q3_buf4_d4 <= q3_buf4_d3; q3_buf4_d5 <= q3_buf4_d4; q3_buf4_d6 <= q3_buf4_d5; q3_buf4_d7 <= q3_buf4_d6;
q3_buf5_d1 <= q3_buf5_i; q3_buf5_d2 <= q3_buf5_d1; q3_buf5_d3 <= q3_buf5_d2; q3_buf5_d4 <= q3_buf5_d3; q3_buf5_d5 <= q3_buf5_d4; q3_buf5_d6 <= q3_buf5_d5; q3_buf5_d7 <= q3_buf5_d6;
q3_buf6_d1 <= q3_buf6_i; q3_buf6_d2 <= q3_buf6_d1; q3_buf6_d3 <= q3_buf6_d2; q3_buf6_d4 <= q3_buf6_d3; q3_buf6_d5 <= q3_buf6_d4; q3_buf6_d6 <= q3_buf6_d5; q3_buf6_d7 <= q3_buf6_d6;
q3_buf7_d1 <= q3_buf7_i; q3_buf7_d2 <= q3_buf7_d1; q3_buf7_d3 <= q3_buf7_d2; q3_buf7_d4 <= q3_buf7_d3; q3_buf7_d5 <= q3_buf7_d4; q3_buf7_d6 <= q3_buf7_d5; q3_buf7_d7 <= q3_buf7_d6;
h_buf0_d1 <= h_buf0_i; h_buf0_d2 <= h_buf0_d1; h_buf0_d3 <= h_buf0_d2; h_buf0_d4 <= h_buf0_d3; h_buf0_d5 <= h_buf0_d4; h_buf0_d6 <= h_buf0_d5; h_buf0_d7 <= h_buf0_d6;
h_buf1_d1 <= h_buf1_i; h_buf1_d2 <= h_buf1_d1; h_buf1_d3 <= h_buf1_d2; h_buf1_d4 <= h_buf1_d3; h_buf1_d5 <= h_buf1_d4; h_buf1_d6 <= h_buf1_d5; h_buf1_d7 <= h_buf1_d6;
h_buf2_d1 <= h_buf2_i; h_buf2_d2 <= h_buf2_d1; h_buf2_d3 <= h_buf2_d2; h_buf2_d4 <= h_buf2_d3; h_buf2_d5 <= h_buf2_d4; h_buf2_d6 <= h_buf2_d5; h_buf2_d7 <= h_buf2_d6;
h_buf3_d1 <= h_buf3_i; h_buf3_d2 <= h_buf3_d1; h_buf3_d3 <= h_buf3_d2; h_buf3_d4 <= h_buf3_d3; h_buf3_d5 <= h_buf3_d4; h_buf3_d6 <= h_buf3_d5; h_buf3_d7 <= h_buf3_d6;
h_buf4_d1 <= h_buf4_i; h_buf4_d2 <= h_buf4_d1; h_buf4_d3 <= h_buf4_d2; h_buf4_d4 <= h_buf4_d3; h_buf4_d5 <= h_buf4_d4; h_buf4_d6 <= h_buf4_d5; h_buf4_d7 <= h_buf4_d6;
h_buf5_d1 <= h_buf5_i; h_buf5_d2 <= h_buf5_d1; h_buf5_d3 <= h_buf5_d2; h_buf5_d4 <= h_buf5_d3; h_buf5_d5 <= h_buf5_d4; h_buf5_d6 <= h_buf5_d5; h_buf5_d7 <= h_buf5_d6;
h_buf6_d1 <= h_buf6_i; h_buf6_d2 <= h_buf6_d1; h_buf6_d3 <= h_buf6_d2; h_buf6_d4 <= h_buf6_d3; h_buf6_d5 <= h_buf6_d4; h_buf6_d6 <= h_buf6_d5; h_buf6_d7 <= h_buf6_d6;
h_buf7_d1 <= h_buf7_i; h_buf7_d2 <= h_buf7_d1; h_buf7_d3 <= h_buf7_d2; h_buf7_d4 <= h_buf7_d3; h_buf7_d5 <= h_buf7_d4; h_buf7_d6 <= h_buf7_d5; h_buf7_d7 <= h_buf7_d6;
end
end
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
cnt_hor <= 'd0;
end
else if(horbuf_valid_i) begin
cnt_hor <= cnt_hor + 'd1;
end
end
always @ (posedge clk or negedge rstn ) begin
if (~rstn) begin
ref_pel0_d1 <= 'd0; ref_pel0_d2 <= 'd0; ref_pel0_d3 <= 'd0; ref_pel0_d4 <= 'd0; ref_pel0_d5 <= 'd0; ref_pel0_d6 <= 'd0; ref_pel0_d7 <= 'd0;
ref_pel1_d1 <= 'd0; ref_pel1_d2 <= 'd0; ref_pel1_d3 <= 'd0; ref_pel1_d4 <= 'd0; ref_pel1_d5 <= 'd0; ref_pel1_d6 <= 'd0; ref_pel1_d7 <= 'd0;
ref_pel2_d1 <= 'd0; ref_pel2_d2 <= 'd0; ref_pel2_d3 <= 'd0; ref_pel2_d4 <= 'd0; ref_pel2_d5 <= 'd0; ref_pel2_d6 <= 'd0; ref_pel2_d7 <= 'd0;
ref_pel3_d1 <= 'd0; ref_pel3_d2 <= 'd0; ref_pel3_d3 <= 'd0; ref_pel3_d4 <= 'd0; ref_pel3_d5 <= 'd0; ref_pel3_d6 <= 'd0; ref_pel3_d7 <= 'd0;
ref_pel4_d1 <= 'd0; ref_pel4_d2 <= 'd0; ref_pel4_d3 <= 'd0; ref_pel4_d4 <= 'd0; ref_pel4_d5 <= 'd0; ref_pel4_d6 <= 'd0; ref_pel4_d7 <= 'd0;
ref_pel5_d1 <= 'd0; ref_pel5_d2 <= 'd0; ref_pel5_d3 <= 'd0; ref_pel5_d4 <= 'd0; ref_pel5_d5 <= 'd0; ref_pel5_d6 <= 'd0; ref_pel5_d7 <= 'd0;
ref_pel6_d1 <= 'd0; ref_pel6_d2 <= 'd0; ref_pel6_d3 <= 'd0; ref_pel6_d4 <= 'd0; ref_pel6_d5 <= 'd0; ref_pel6_d6 <= 'd0; ref_pel6_d7 <= 'd0;
ref_pel7_d1 <= 'd0; ref_pel7_d2 <= 'd0; ref_pel7_d3 <= 'd0; ref_pel7_d4 <= 'd0; ref_pel7_d5 <= 'd0; ref_pel7_d6 <= 'd0; ref_pel7_d7 <= 'd0;
end
else if (refpel_valid_i) begin
ref_pel0_d1 <= ref_pel0_i; ref_pel0_d2 <= ref_pel0_d1; ref_pel0_d3 <= ref_pel0_d2; ref_pel0_d4 <= ref_pel0_d3; ref_pel0_d5 <= ref_pel0_d4; ref_pel0_d6 <= ref_pel0_d5; ref_pel0_d7 <= ref_pel0_d6;
ref_pel1_d1 <= ref_pel1_i; ref_pel1_d2 <= ref_pel1_d1; ref_pel1_d3 <= ref_pel1_d2; ref_pel1_d4 <= ref_pel1_d3; ref_pel1_d5 <= ref_pel1_d4; ref_pel1_d6 <= ref_pel1_d5; ref_pel1_d7 <= ref_pel1_d6;
ref_pel2_d1 <= ref_pel2_i; ref_pel2_d2 <= ref_pel2_d1; ref_pel2_d3 <= ref_pel2_d2; ref_pel2_d4 <= ref_pel2_d3; ref_pel2_d5 <= ref_pel2_d4; ref_pel2_d6 <= ref_pel2_d5; ref_pel2_d7 <= ref_pel2_d6;
ref_pel3_d1 <= ref_pel3_i; ref_pel3_d2 <= ref_pel3_d1; ref_pel3_d3 <= ref_pel3_d2; ref_pel3_d4 <= ref_pel3_d3; ref_pel3_d5 <= ref_pel3_d4; ref_pel3_d6 <= ref_pel3_d5; ref_pel3_d7 <= ref_pel3_d6;
ref_pel4_d1 <= ref_pel4_i; ref_pel4_d2 <= ref_pel4_d1; ref_pel4_d3 <= ref_pel4_d2; ref_pel4_d4 <= ref_pel4_d3; ref_pel4_d5 <= ref_pel4_d4; ref_pel4_d6 <= ref_pel4_d5; ref_pel4_d7 <= ref_pel4_d6;
ref_pel5_d1 <= ref_pel5_i; ref_pel5_d2 <= ref_pel5_d1; ref_pel5_d3 <= ref_pel5_d2; ref_pel5_d4 <= ref_pel5_d3; ref_pel5_d5 <= ref_pel5_d4; ref_pel5_d6 <= ref_pel5_d5; ref_pel5_d7 <= ref_pel5_d6;
ref_pel6_d1 <= ref_pel6_i; ref_pel6_d2 <= ref_pel6_d1; ref_pel6_d3 <= ref_pel6_d2; ref_pel6_d4 <= ref_pel6_d3; ref_pel6_d5 <= ref_pel6_d4; ref_pel6_d6 <= ref_pel6_d5; ref_pel6_d7 <= ref_pel6_d6;
ref_pel7_d1 <= ref_pel7_i; ref_pel7_d2 <= ref_pel7_d1; ref_pel7_d3 <= ref_pel7_d2; ref_pel7_d4 <= ref_pel7_d3; ref_pel7_d5 <= ref_pel7_d4; ref_pel7_d6 <= ref_pel7_d5; ref_pel7_d7 <= ref_pel7_d6;
end
end
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
cnt_ref <= 'd0;
end
else if(refpel_valid_i) begin
cnt_ref <= cnt_ref + 'd1;
end
end
// ********************************************
//
// Sub Module
//
// ********************************************
// vertical quarter 1 interpolator
// from q1
//
//
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_0 (
.tap_0_i( q1_buf0_d7 ) ,
.tap_1_i( q1_buf0_d6 ) ,
.tap_2_i( q1_buf0_d5 ) ,
.tap_3_i( q1_buf0_d4 ) ,
.tap_4_i( q1_buf0_d3 ) ,
.tap_5_i( q1_buf0_d2 ) ,
.tap_6_i( q1_buf0_d1 ) ,
.tap_7_i( q1_buf0_i ) ,
.val_o ( vquarter_1_1_pel0_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_1 (
.tap_0_i( q1_buf1_d7 ) ,
.tap_1_i( q1_buf1_d6 ) ,
.tap_2_i( q1_buf1_d5 ) ,
.tap_3_i( q1_buf1_d4 ) ,
.tap_4_i( q1_buf1_d3 ) ,
.tap_5_i( q1_buf1_d2 ) ,
.tap_6_i( q1_buf1_d1 ) ,
.tap_7_i( q1_buf1_i ) ,
.val_o ( vquarter_1_1_pel1_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_2 (
.tap_0_i( q1_buf2_d7 ) ,
.tap_1_i( q1_buf2_d6 ) ,
.tap_2_i( q1_buf2_d5 ) ,
.tap_3_i( q1_buf2_d4 ) ,
.tap_4_i( q1_buf2_d3 ) ,
.tap_5_i( q1_buf2_d2 ) ,
.tap_6_i( q1_buf2_d1 ) ,
.tap_7_i( q1_buf2_i ) ,
.val_o ( vquarter_1_1_pel2_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_3 (
.tap_0_i( q1_buf3_d7 ) ,
.tap_1_i( q1_buf3_d6 ) ,
.tap_2_i( q1_buf3_d5 ) ,
.tap_3_i( q1_buf3_d4 ) ,
.tap_4_i( q1_buf3_d3 ) ,
.tap_5_i( q1_buf3_d2 ) ,
.tap_6_i( q1_buf3_d1 ) ,
.tap_7_i( q1_buf3_i ) ,
.val_o ( vquarter_1_1_pel3_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_4 (
.tap_0_i( q1_buf4_d7 ) ,
.tap_1_i( q1_buf4_d6 ) ,
.tap_2_i( q1_buf4_d5 ) ,
.tap_3_i( q1_buf4_d4 ) ,
.tap_4_i( q1_buf4_d3 ) ,
.tap_5_i( q1_buf4_d2 ) ,
.tap_6_i( q1_buf4_d1 ) ,
.tap_7_i( q1_buf4_i ) ,
.val_o ( vquarter_1_1_pel4_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_5 (
.tap_0_i( q1_buf5_d7 ) ,
.tap_1_i( q1_buf5_d6 ) ,
.tap_2_i( q1_buf5_d5 ) ,
.tap_3_i( q1_buf5_d4 ) ,
.tap_4_i( q1_buf5_d3 ) ,
.tap_5_i( q1_buf5_d2 ) ,
.tap_6_i( q1_buf5_d1 ) ,
.tap_7_i( q1_buf5_i ) ,
.val_o ( vquarter_1_1_pel5_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_6 (
.tap_0_i( q1_buf6_d7 ) ,
.tap_1_i( q1_buf6_d6 ) ,
.tap_2_i( q1_buf6_d5 ) ,
.tap_3_i( q1_buf6_d4 ) ,
.tap_4_i( q1_buf6_d3 ) ,
.tap_5_i( q1_buf6_d2 ) ,
.tap_6_i( q1_buf6_d1 ) ,
.tap_7_i( q1_buf6_i ) ,
.val_o ( vquarter_1_1_pel6_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_7 (
.tap_0_i( q1_buf7_d7 ) ,
.tap_1_i( q1_buf7_d6 ) ,
.tap_2_i( q1_buf7_d5 ) ,
.tap_3_i( q1_buf7_d4 ) ,
.tap_4_i( q1_buf7_d3 ) ,
.tap_5_i( q1_buf7_d2 ) ,
.tap_6_i( q1_buf7_d1 ) ,
.tap_7_i( q1_buf7_i ) ,
.val_o ( vquarter_1_1_pel7_o)
);
// from q3
// q3_buf0_d7
// q3_buf0_d6
// q3_buf0_d5
// q3_buf0_d4
// q3_buf0_d3
// q3_buf0_d2
// q3_buf0_d1
// q3_buf0_i
//
//
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_0 (
.tap_0_i( q3_buf0_d7 ) ,
.tap_1_i( q3_buf0_d6 ) ,
.tap_2_i( q3_buf0_d5 ) ,
.tap_3_i( q3_buf0_d4 ) ,
.tap_4_i( q3_buf0_d3 ) ,
.tap_5_i( q3_buf0_d2 ) ,
.tap_6_i( q3_buf0_d1 ) ,
.tap_7_i( q3_buf0_i ) ,
.val_o ( vquarter_1_3_pel0_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_1 (
.tap_0_i( q3_buf1_d7 ) ,
.tap_1_i( q3_buf1_d6 ) ,
.tap_2_i( q3_buf1_d5 ) ,
.tap_3_i( q3_buf1_d4 ) ,
.tap_4_i( q3_buf1_d3 ) ,
.tap_5_i( q3_buf1_d2 ) ,
.tap_6_i( q3_buf1_d1 ) ,
.tap_7_i( q3_buf1_i ) ,
.val_o ( vquarter_1_3_pel1_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_2 (
.tap_0_i( q3_buf2_d7 ) ,
.tap_1_i( q3_buf2_d6 ) ,
.tap_2_i( q3_buf2_d5 ) ,
.tap_3_i( q3_buf2_d4 ) ,
.tap_4_i( q3_buf2_d3 ) ,
.tap_5_i( q3_buf2_d2 ) ,
.tap_6_i( q3_buf2_d1 ) ,
.tap_7_i( q3_buf2_i ) ,
.val_o ( vquarter_1_3_pel2_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_3 (
.tap_0_i( q3_buf3_d7 ) ,
.tap_1_i( q3_buf3_d6 ) ,
.tap_2_i( q3_buf3_d5 ) ,
.tap_3_i( q3_buf3_d4 ) ,
.tap_4_i( q3_buf3_d3 ) ,
.tap_5_i( q3_buf3_d2 ) ,
.tap_6_i( q3_buf3_d1 ) ,
.tap_7_i( q3_buf3_i ) ,
.val_o ( vquarter_1_3_pel3_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_4 (
.tap_0_i( q3_buf4_d7 ) ,
.tap_1_i( q3_buf4_d6 ) ,
.tap_2_i( q3_buf4_d5 ) ,
.tap_3_i( q3_buf4_d4 ) ,
.tap_4_i( q3_buf4_d3 ) ,
.tap_5_i( q3_buf4_d2 ) ,
.tap_6_i( q3_buf4_d1 ) ,
.tap_7_i( q3_buf4_i ) ,
.val_o ( vquarter_1_3_pel4_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_5 (
.tap_0_i( q3_buf5_d7 ) ,
.tap_1_i( q3_buf5_d6 ) ,
.tap_2_i( q3_buf5_d5 ) ,
.tap_3_i( q3_buf5_d4 ) ,
.tap_4_i( q3_buf5_d3 ) ,
.tap_5_i( q3_buf5_d2 ) ,
.tap_6_i( q3_buf5_d1 ) ,
.tap_7_i( q3_buf5_i ) ,
.val_o ( vquarter_1_3_pel5_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_6 (
.tap_0_i( q3_buf6_d7 ) ,
.tap_1_i( q3_buf6_d6 ) ,
.tap_2_i( q3_buf6_d5 ) ,
.tap_3_i( q3_buf6_d4 ) ,
.tap_4_i( q3_buf6_d3 ) ,
.tap_5_i( q3_buf6_d2 ) ,
.tap_6_i( q3_buf6_d1 ) ,
.tap_7_i( q3_buf6_i ) ,
.val_o ( vquarter_1_3_pel6_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_7 (
.tap_0_i( q3_buf7_d7 ) ,
.tap_1_i( q3_buf7_d6 ) ,
.tap_2_i( q3_buf7_d5 ) ,
.tap_3_i( q3_buf7_d4 ) ,
.tap_4_i( q3_buf7_d3 ) ,
.tap_5_i( q3_buf7_d2 ) ,
.tap_6_i( q3_buf7_d1 ) ,
.tap_7_i( q3_buf7_i ) ,
.val_o ( vquarter_1_3_pel7_o)
);
//from half buf
// h_buf0_d7
// h_buf0_d6
// h_buf0_d5
// h_buf0_d4
// h_buf0_d3
// h_buf0_d2
// h_buf0_d1
// h_buf0_i
//
//
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_0 (
.tap_0_i( h_buf0_d7 ) ,
.tap_1_i( h_buf0_d6 ) ,
.tap_2_i( h_buf0_d5 ) ,
.tap_3_i( h_buf0_d4 ) ,
.tap_4_i( h_buf0_d3 ) ,
.tap_5_i( h_buf0_d2 ) ,
.tap_6_i( h_buf0_d1 ) ,
.tap_7_i( h_buf0_i ) ,
.val_o ( vquarter_1_2_pel0_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_1 (
.tap_0_i( h_buf1_d7 ) ,
.tap_1_i( h_buf1_d6 ) ,
.tap_2_i( h_buf1_d5 ) ,
.tap_3_i( h_buf1_d4 ) ,
.tap_4_i( h_buf1_d3 ) ,
.tap_5_i( h_buf1_d2 ) ,
.tap_6_i( h_buf1_d1 ) ,
.tap_7_i( h_buf1_i ) ,
.val_o ( vquarter_1_2_pel1_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_2 (
.tap_0_i( h_buf2_d7 ) ,
.tap_1_i( h_buf2_d6 ) ,
.tap_2_i( h_buf2_d5 ) ,
.tap_3_i( h_buf2_d4 ) ,
.tap_4_i( h_buf2_d3 ) ,
.tap_5_i( h_buf2_d2 ) ,
.tap_6_i( h_buf2_d1 ) ,
.tap_7_i( h_buf2_i ) ,
.val_o ( vquarter_1_2_pel2_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_3 (
.tap_0_i( h_buf3_d7 ) ,
.tap_1_i( h_buf3_d6 ) ,
.tap_2_i( h_buf3_d5 ) ,
.tap_3_i( h_buf3_d4 ) ,
.tap_4_i( h_buf3_d3 ) ,
.tap_5_i( h_buf3_d2 ) ,
.tap_6_i( h_buf3_d1 ) ,
.tap_7_i( h_buf3_i ) ,
.val_o ( vquarter_1_2_pel3_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_4 (
.tap_0_i( h_buf4_d7 ) ,
.tap_1_i( h_buf4_d6 ) ,
.tap_2_i( h_buf4_d5 ) ,
.tap_3_i( h_buf4_d4 ) ,
.tap_4_i( h_buf4_d3 ) ,
.tap_5_i( h_buf4_d2 ) ,
.tap_6_i( h_buf4_d1 ) ,
.tap_7_i( h_buf4_i ) ,
.val_o ( vquarter_1_2_pel4_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_5 (
.tap_0_i( h_buf5_d7 ) ,
.tap_1_i( h_buf5_d6 ) ,
.tap_2_i( h_buf5_d5 ) ,
.tap_3_i( h_buf5_d4 ) ,
.tap_4_i( h_buf5_d3 ) ,
.tap_5_i( h_buf5_d2 ) ,
.tap_6_i( h_buf5_d1 ) ,
.tap_7_i( h_buf5_i ) ,
.val_o ( vquarter_1_2_pel5_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_6 (
.tap_0_i( h_buf6_d7 ) ,
.tap_1_i( h_buf6_d6 ) ,
.tap_2_i( h_buf6_d5 ) ,
.tap_3_i( h_buf6_d4 ) ,
.tap_4_i( h_buf6_d3 ) ,
.tap_5_i( h_buf6_d2 ) ,
.tap_6_i( h_buf6_d1 ) ,
.tap_7_i( h_buf6_i ) ,
.val_o ( vquarter_1_2_pel6_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_7 (
.tap_0_i( h_buf7_d7 ) ,
.tap_1_i( h_buf7_d6 ) ,
.tap_2_i( h_buf7_d5 ) ,
.tap_3_i( h_buf7_d4 ) ,
.tap_4_i( h_buf7_d3 ) ,
.tap_5_i( h_buf7_d2 ) ,
.tap_6_i( h_buf7_d1 ) ,
.tap_7_i( h_buf7_i ) ,
.val_o ( vquarter_1_2_pel7_o)
);
// from ref
// ref_pel0_d7
// ref_pel0_d6
// ref_pel0_d5
// ref_pel0_d4
// ref_pel0_d3
// ref_pel0_d2
// ref_pel0_d1
// ref_pel0_i
//
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_0 (
.tap_0_i( ref_pel0_d7 ) ,
.tap_1_i( ref_pel0_d6 ) ,
.tap_2_i( ref_pel0_d5 ) ,
.tap_3_i( ref_pel0_d4 ) ,
.tap_4_i( ref_pel0_d3 ) ,
.tap_5_i( ref_pel0_d2 ) ,
.tap_6_i( ref_pel0_d1 ) ,
.tap_7_i( ref_pel0_i ) ,
.val_o ( vquarter_1_0_pel0_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_1 (
.tap_0_i( ref_pel1_d7 ) ,
.tap_1_i( ref_pel1_d6 ) ,
.tap_2_i( ref_pel1_d5 ) ,
.tap_3_i( ref_pel1_d4 ) ,
.tap_4_i( ref_pel1_d3 ) ,
.tap_5_i( ref_pel1_d2 ) ,
.tap_6_i( ref_pel1_d1 ) ,
.tap_7_i( ref_pel1_i ) ,
.val_o ( vquarter_1_0_pel1_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_2 (
.tap_0_i( ref_pel2_d7 ) ,
.tap_1_i( ref_pel2_d6 ) ,
.tap_2_i( ref_pel2_d5 ) ,
.tap_3_i( ref_pel2_d4 ) ,
.tap_4_i( ref_pel2_d3 ) ,
.tap_5_i( ref_pel2_d2 ) ,
.tap_6_i( ref_pel2_d1 ) ,
.tap_7_i( ref_pel2_i ) ,
.val_o ( vquarter_1_0_pel2_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_3 (
.tap_0_i( ref_pel3_d7 ) ,
.tap_1_i( ref_pel3_d6 ) ,
.tap_2_i( ref_pel3_d5 ) ,
.tap_3_i( ref_pel3_d4 ) ,
.tap_4_i( ref_pel3_d3 ) ,
.tap_5_i( ref_pel3_d2 ) ,
.tap_6_i( ref_pel3_d1 ) ,
.tap_7_i( ref_pel3_i ) ,
.val_o ( vquarter_1_0_pel3_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_4 (
.tap_0_i( ref_pel4_d7 ) ,
.tap_1_i( ref_pel4_d6 ) ,
.tap_2_i( ref_pel4_d5 ) ,
.tap_3_i( ref_pel4_d4 ) ,
.tap_4_i( ref_pel4_d3 ) ,
.tap_5_i( ref_pel4_d2 ) ,
.tap_6_i( ref_pel4_d1 ) ,
.tap_7_i( ref_pel4_i ) ,
.val_o ( vquarter_1_0_pel4_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_5 (
.tap_0_i( ref_pel5_d7 ) ,
.tap_1_i( ref_pel5_d6 ) ,
.tap_2_i( ref_pel5_d5 ) ,
.tap_3_i( ref_pel5_d4 ) ,
.tap_4_i( ref_pel5_d3 ) ,
.tap_5_i( ref_pel5_d2 ) ,
.tap_6_i( ref_pel5_d1 ) ,
.tap_7_i( ref_pel5_i ) ,
.val_o ( vquarter_1_0_pel5_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_6 (
.tap_0_i( ref_pel6_d7 ) ,
.tap_1_i( ref_pel6_d6 ) ,
.tap_2_i( ref_pel6_d5 ) ,
.tap_3_i( ref_pel6_d4 ) ,
.tap_4_i( ref_pel6_d3 ) ,
.tap_5_i( ref_pel6_d2 ) ,
.tap_6_i( ref_pel6_d1 ) ,
.tap_7_i( ref_pel6_i ) ,
.val_o ( vquarter_1_0_pel6_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_7 (
.tap_0_i( ref_pel7_d7 ) ,
.tap_1_i( ref_pel7_d6 ) ,
.tap_2_i( ref_pel7_d5 ) ,
.tap_3_i( ref_pel7_d4 ) ,
.tap_4_i( ref_pel7_d3 ) ,
.tap_5_i( ref_pel7_d2 ) ,
.tap_6_i( ref_pel7_d1 ) ,
.tap_7_i( ref_pel7_i ) ,
.val_o ( vquarter_1_0_pel7_o)
);
// vertical quarter 3 interpolator
// from 1
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_0 (
.tap_0_i( q1_buf0_d7 ) ,
.tap_1_i( q1_buf0_d6 ) ,
.tap_2_i( q1_buf0_d5 ) ,
.tap_3_i( q1_buf0_d4 ) ,
.tap_4_i( q1_buf0_d3 ) ,
.tap_5_i( q1_buf0_d2 ) ,
.tap_6_i( q1_buf0_d1 ) ,
.tap_7_i( q1_buf0_i ) ,
.val_o ( vquarter_3_1_pel0_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_1 (
.tap_0_i( q1_buf1_d7 ) ,
.tap_1_i( q1_buf1_d6 ) ,
.tap_2_i( q1_buf1_d5 ) ,
.tap_3_i( q1_buf1_d4 ) ,
.tap_4_i( q1_buf1_d3 ) ,
.tap_5_i( q1_buf1_d2 ) ,
.tap_6_i( q1_buf1_d1 ) ,
.tap_7_i( q1_buf1_i ) ,
.val_o ( vquarter_3_1_pel1_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_2 (
.tap_0_i( q1_buf2_d7 ) ,
.tap_1_i( q1_buf2_d6 ) ,
.tap_2_i( q1_buf2_d5 ) ,
.tap_3_i( q1_buf2_d4 ) ,
.tap_4_i( q1_buf2_d3 ) ,
.tap_5_i( q1_buf2_d2 ) ,
.tap_6_i( q1_buf2_d1 ) ,
.tap_7_i( q1_buf2_i ) ,
.val_o ( vquarter_3_1_pel2_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_3 (
.tap_0_i( q1_buf3_d7 ) ,
.tap_1_i( q1_buf3_d6 ) ,
.tap_2_i( q1_buf3_d5 ) ,
.tap_3_i( q1_buf3_d4 ) ,
.tap_4_i( q1_buf3_d3 ) ,
.tap_5_i( q1_buf3_d2 ) ,
.tap_6_i( q1_buf3_d1 ) ,
.tap_7_i( q1_buf3_i ) ,
.val_o ( vquarter_3_1_pel3_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_4 (
.tap_0_i( q1_buf4_d7 ) ,
.tap_1_i( q1_buf4_d6 ) ,
.tap_2_i( q1_buf4_d5 ) ,
.tap_3_i( q1_buf4_d4 ) ,
.tap_4_i( q1_buf4_d3 ) ,
.tap_5_i( q1_buf4_d2 ) ,
.tap_6_i( q1_buf4_d1 ) ,
.tap_7_i( q1_buf4_i ) ,
.val_o ( vquarter_3_1_pel4_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_5 (
.tap_0_i( q1_buf5_d7 ) ,
.tap_1_i( q1_buf5_d6 ) ,
.tap_2_i( q1_buf5_d5 ) ,
.tap_3_i( q1_buf5_d4 ) ,
.tap_4_i( q1_buf5_d3 ) ,
.tap_5_i( q1_buf5_d2 ) ,
.tap_6_i( q1_buf5_d1 ) ,
.tap_7_i( q1_buf5_i ) ,
.val_o ( vquarter_3_1_pel5_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_6 (
.tap_0_i( q1_buf6_d7 ) ,
.tap_1_i( q1_buf6_d6 ) ,
.tap_2_i( q1_buf6_d5 ) ,
.tap_3_i( q1_buf6_d4 ) ,
.tap_4_i( q1_buf6_d3 ) ,
.tap_5_i( q1_buf6_d2 ) ,
.tap_6_i( q1_buf6_d1 ) ,
.tap_7_i( q1_buf6_i ) ,
.val_o ( vquarter_3_1_pel6_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_7 (
.tap_0_i( q1_buf7_d7 ) ,
.tap_1_i( q1_buf7_d6 ) ,
.tap_2_i( q1_buf7_d5 ) ,
.tap_3_i( q1_buf7_d4 ) ,
.tap_4_i( q1_buf7_d3 ) ,
.tap_5_i( q1_buf7_d2 ) ,
.tap_6_i( q1_buf7_d1 ) ,
.tap_7_i( q1_buf7_i ) ,
.val_o ( vquarter_3_1_pel7_o)
);
// from 3
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_0 (
.tap_0_i( q3_buf0_d7 ) ,
.tap_1_i( q3_buf0_d6 ) ,
.tap_2_i( q3_buf0_d5 ) ,
.tap_3_i( q3_buf0_d4 ) ,
.tap_4_i( q3_buf0_d3 ) ,
.tap_5_i( q3_buf0_d2 ) ,
.tap_6_i( q3_buf0_d1 ) ,
.tap_7_i( q3_buf0_i ) ,
.val_o ( vquarter_3_3_pel0_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_1 (
.tap_0_i( q3_buf1_d7 ) ,
.tap_1_i( q3_buf1_d6 ) ,
.tap_2_i( q3_buf1_d5 ) ,
.tap_3_i( q3_buf1_d4 ) ,
.tap_4_i( q3_buf1_d3 ) ,
.tap_5_i( q3_buf1_d2 ) ,
.tap_6_i( q3_buf1_d1 ) ,
.tap_7_i( q3_buf1_i ) ,
.val_o ( vquarter_3_3_pel1_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_2 (
.tap_0_i( q3_buf2_d7 ) ,
.tap_1_i( q3_buf2_d6 ) ,
.tap_2_i( q3_buf2_d5 ) ,
.tap_3_i( q3_buf2_d4 ) ,
.tap_4_i( q3_buf2_d3 ) ,
.tap_5_i( q3_buf2_d2 ) ,
.tap_6_i( q3_buf2_d1 ) ,
.tap_7_i( q3_buf2_i ) ,
.val_o ( vquarter_3_3_pel2_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_3 (
.tap_0_i( q3_buf3_d7 ) ,
.tap_1_i( q3_buf3_d6 ) ,
.tap_2_i( q3_buf3_d5 ) ,
.tap_3_i( q3_buf3_d4 ) ,
.tap_4_i( q3_buf3_d3 ) ,
.tap_5_i( q3_buf3_d2 ) ,
.tap_6_i( q3_buf3_d1 ) ,
.tap_7_i( q3_buf3_i ) ,
.val_o ( vquarter_3_3_pel3_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_4 (
.tap_0_i( q3_buf4_d7 ) ,
.tap_1_i( q3_buf4_d6 ) ,
.tap_2_i( q3_buf4_d5 ) ,
.tap_3_i( q3_buf4_d4 ) ,
.tap_4_i( q3_buf4_d3 ) ,
.tap_5_i( q3_buf4_d2 ) ,
.tap_6_i( q3_buf4_d1 ) ,
.tap_7_i( q3_buf4_i ) ,
.val_o ( vquarter_3_3_pel4_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_5 (
.tap_0_i( q3_buf5_d7 ) ,
.tap_1_i( q3_buf5_d6 ) ,
.tap_2_i( q3_buf5_d5 ) ,
.tap_3_i( q3_buf5_d4 ) ,
.tap_4_i( q3_buf5_d3 ) ,
.tap_5_i( q3_buf5_d2 ) ,
.tap_6_i( q3_buf5_d1 ) ,
.tap_7_i( q3_buf5_i ) ,
.val_o ( vquarter_3_3_pel5_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_6 (
.tap_0_i( q3_buf6_d7 ) ,
.tap_1_i( q3_buf6_d6 ) ,
.tap_2_i( q3_buf6_d5 ) ,
.tap_3_i( q3_buf6_d4 ) ,
.tap_4_i( q3_buf6_d3 ) ,
.tap_5_i( q3_buf6_d2 ) ,
.tap_6_i( q3_buf6_d1 ) ,
.tap_7_i( q3_buf6_i ) ,
.val_o ( vquarter_3_3_pel6_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_7 (
.tap_0_i( q3_buf7_d7 ) ,
.tap_1_i( q3_buf7_d6 ) ,
.tap_2_i( q3_buf7_d5 ) ,
.tap_3_i( q3_buf7_d4 ) ,
.tap_4_i( q3_buf7_d3 ) ,
.tap_5_i( q3_buf7_d2 ) ,
.tap_6_i( q3_buf7_d1 ) ,
.tap_7_i( q3_buf7_i ) ,
.val_o ( vquarter_3_3_pel7_o)
);
// from half
// h_buf0_d7
// h_buf0_d6
// h_buf0_d5
// h_buf0_d4
// h_buf0_d3
// h_buf0_d2
// h_buf0_d1
// h_buf0_i
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_0 (
.tap_0_i( h_buf0_d7 ) ,
.tap_1_i( h_buf0_d6 ) ,
.tap_2_i( h_buf0_d5 ) ,
.tap_3_i( h_buf0_d4 ) ,
.tap_4_i( h_buf0_d3 ) ,
.tap_5_i( h_buf0_d2 ) ,
.tap_6_i( h_buf0_d1 ) ,
.tap_7_i( h_buf0_i ) ,
.val_o ( vquarter_3_2_pel0_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_1 (
.tap_0_i( h_buf1_d7 ) ,
.tap_1_i( h_buf1_d6 ) ,
.tap_2_i( h_buf1_d5 ) ,
.tap_3_i( h_buf1_d4 ) ,
.tap_4_i( h_buf1_d3 ) ,
.tap_5_i( h_buf1_d2 ) ,
.tap_6_i( h_buf1_d1 ) ,
.tap_7_i( h_buf1_i ) ,
.val_o ( vquarter_3_2_pel1_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_2 (
.tap_0_i( h_buf2_d7 ) ,
.tap_1_i( h_buf2_d6 ) ,
.tap_2_i( h_buf2_d5 ) ,
.tap_3_i( h_buf2_d4 ) ,
.tap_4_i( h_buf2_d3 ) ,
.tap_5_i( h_buf2_d2 ) ,
.tap_6_i( h_buf2_d1 ) ,
.tap_7_i( h_buf2_i ) ,
.val_o ( vquarter_3_2_pel2_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_3 (
.tap_0_i( h_buf3_d7 ) ,
.tap_1_i( h_buf3_d6 ) ,
.tap_2_i( h_buf3_d5 ) ,
.tap_3_i( h_buf3_d4 ) ,
.tap_4_i( h_buf3_d3 ) ,
.tap_5_i( h_buf3_d2 ) ,
.tap_6_i( h_buf3_d1 ) ,
.tap_7_i( h_buf3_i ) ,
.val_o ( vquarter_3_2_pel3_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_4 (
.tap_0_i( h_buf4_d7 ) ,
.tap_1_i( h_buf4_d6 ) ,
.tap_2_i( h_buf4_d5 ) ,
.tap_3_i( h_buf4_d4 ) ,
.tap_4_i( h_buf4_d3 ) ,
.tap_5_i( h_buf4_d2 ) ,
.tap_6_i( h_buf4_d1 ) ,
.tap_7_i( h_buf4_i ) ,
.val_o ( vquarter_3_2_pel4_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_5 (
.tap_0_i( h_buf5_d7 ) ,
.tap_1_i( h_buf5_d6 ) ,
.tap_2_i( h_buf5_d5 ) ,
.tap_3_i( h_buf5_d4 ) ,
.tap_4_i( h_buf5_d3 ) ,
.tap_5_i( h_buf5_d2 ) ,
.tap_6_i( h_buf5_d1 ) ,
.tap_7_i( h_buf5_i ) ,
.val_o ( vquarter_3_2_pel5_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_6 (
.tap_0_i( h_buf6_d7 ) ,
.tap_1_i( h_buf6_d6 ) ,
.tap_2_i( h_buf6_d5 ) ,
.tap_3_i( h_buf6_d4 ) ,
.tap_4_i( h_buf6_d3 ) ,
.tap_5_i( h_buf6_d2 ) ,
.tap_6_i( h_buf6_d1 ) ,
.tap_7_i( h_buf6_i ) ,
.val_o ( vquarter_3_2_pel6_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_7 (
.tap_0_i( h_buf7_d7 ) ,
.tap_1_i( h_buf7_d6 ) ,
.tap_2_i( h_buf7_d5 ) ,
.tap_3_i( h_buf7_d4 ) ,
.tap_4_i( h_buf7_d3 ) ,
.tap_5_i( h_buf7_d2 ) ,
.tap_6_i( h_buf7_d1 ) ,
.tap_7_i( h_buf7_i ) ,
.val_o ( vquarter_3_2_pel7_o)
);
// from ref
// ref_pel0_d7
// ref_pel0_d6
// ref_pel0_d5
// ref_pel0_d4
// ref_pel0_d3
// ref_pel0_d2
// ref_pel0_d1
// ref_pel0_i
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_0 (
.tap_0_i( ref_pel0_d7 ) ,
.tap_1_i( ref_pel0_d6 ) ,
.tap_2_i( ref_pel0_d5 ) ,
.tap_3_i( ref_pel0_d4 ) ,
.tap_4_i( ref_pel0_d3 ) ,
.tap_5_i( ref_pel0_d2 ) ,
.tap_6_i( ref_pel0_d1 ) ,
.tap_7_i( ref_pel0_i ) ,
.val_o ( vquarter_3_0_pel0_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_1 (
.tap_0_i( ref_pel1_d7 ) ,
.tap_1_i( ref_pel1_d6 ) ,
.tap_2_i( ref_pel1_d5 ) ,
.tap_3_i( ref_pel1_d4 ) ,
.tap_4_i( ref_pel1_d3 ) ,
.tap_5_i( ref_pel1_d2 ) ,
.tap_6_i( ref_pel1_d1 ) ,
.tap_7_i( ref_pel1_i ) ,
.val_o ( vquarter_3_0_pel1_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_2 (
.tap_0_i( ref_pel2_d7 ) ,
.tap_1_i( ref_pel2_d6 ) ,
.tap_2_i( ref_pel2_d5 ) ,
.tap_3_i( ref_pel2_d4 ) ,
.tap_4_i( ref_pel2_d3 ) ,
.tap_5_i( ref_pel2_d2 ) ,
.tap_6_i( ref_pel2_d1 ) ,
.tap_7_i( ref_pel2_i ) ,
.val_o ( vquarter_3_0_pel2_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_3 (
.tap_0_i( ref_pel3_d7 ) ,
.tap_1_i( ref_pel3_d6 ) ,
.tap_2_i( ref_pel3_d5 ) ,
.tap_3_i( ref_pel3_d4 ) ,
.tap_4_i( ref_pel3_d3 ) ,
.tap_5_i( ref_pel3_d2 ) ,
.tap_6_i( ref_pel3_d1 ) ,
.tap_7_i( ref_pel3_i ) ,
.val_o ( vquarter_3_0_pel3_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_4 (
.tap_0_i( ref_pel4_d7 ) ,
.tap_1_i( ref_pel4_d6 ) ,
.tap_2_i( ref_pel4_d5 ) ,
.tap_3_i( ref_pel4_d4 ) ,
.tap_4_i( ref_pel4_d3 ) ,
.tap_5_i( ref_pel4_d2 ) ,
.tap_6_i( ref_pel4_d1 ) ,
.tap_7_i( ref_pel4_i ) ,
.val_o ( vquarter_3_0_pel4_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_5 (
.tap_0_i( ref_pel5_d7 ) ,
.tap_1_i( ref_pel5_d6 ) ,
.tap_2_i( ref_pel5_d5 ) ,
.tap_3_i( ref_pel5_d4 ) ,
.tap_4_i( ref_pel5_d3 ) ,
.tap_5_i( ref_pel5_d2 ) ,
.tap_6_i( ref_pel5_d1 ) ,
.tap_7_i( ref_pel5_i ) ,
.val_o ( vquarter_3_0_pel5_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_6 (
.tap_0_i( ref_pel6_d7 ) ,
.tap_1_i( ref_pel6_d6 ) ,
.tap_2_i( ref_pel6_d5 ) ,
.tap_3_i( ref_pel6_d4 ) ,
.tap_4_i( ref_pel6_d3 ) ,
.tap_5_i( ref_pel6_d2 ) ,
.tap_6_i( ref_pel6_d1 ) ,
.tap_7_i( ref_pel6_i ) ,
.val_o ( vquarter_3_0_pel6_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_7 (
.tap_0_i( ref_pel7_d7 ) ,
.tap_1_i( ref_pel7_d6 ) ,
.tap_2_i( ref_pel7_d5 ) ,
.tap_3_i( ref_pel7_d4 ) ,
.tap_4_i( ref_pel7_d3 ) ,
.tap_5_i( ref_pel7_d2 ) ,
.tap_6_i( ref_pel7_d1 ) ,
.tap_7_i( ref_pel7_i ) ,
.val_o ( vquarter_3_0_pel7_o)
);
// vertical half interpolator
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_0 (
.tap_0_i( q1_buf0_i ) ,
.tap_1_i( q1_buf0_d1 ) ,
.tap_2_i( q1_buf0_d2 ) ,
.tap_3_i( q1_buf0_d3 ) ,
.tap_4_i( q1_buf0_d4 ) ,
.tap_5_i( q1_buf0_d5 ) ,
.tap_6_i( q1_buf0_d6 ) ,
.tap_7_i( q1_buf0_d7 ) ,
.val_o ( vhalf_2_1_pel0_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_1 (
.tap_0_i( q1_buf1_i ) ,
.tap_1_i( q1_buf1_d1 ) ,
.tap_2_i( q1_buf1_d2 ) ,
.tap_3_i( q1_buf1_d3 ) ,
.tap_4_i( q1_buf1_d4 ) ,
.tap_5_i( q1_buf1_d5 ) ,
.tap_6_i( q1_buf1_d6 ) ,
.tap_7_i( q1_buf1_d7 ) ,
.val_o ( vhalf_2_1_pel1_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_2 (
.tap_0_i( q1_buf2_i ) ,
.tap_1_i( q1_buf2_d1 ) ,
.tap_2_i( q1_buf2_d2 ) ,
.tap_3_i( q1_buf2_d3 ) ,
.tap_4_i( q1_buf2_d4 ) ,
.tap_5_i( q1_buf2_d5 ) ,
.tap_6_i( q1_buf2_d6 ) ,
.tap_7_i( q1_buf2_d7 ) ,
.val_o ( vhalf_2_1_pel2_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_3 (
.tap_0_i( q1_buf3_i ) ,
.tap_1_i( q1_buf3_d1 ) ,
.tap_2_i( q1_buf3_d2 ) ,
.tap_3_i( q1_buf3_d3 ) ,
.tap_4_i( q1_buf3_d4 ) ,
.tap_5_i( q1_buf3_d5 ) ,
.tap_6_i( q1_buf3_d6 ) ,
.tap_7_i( q1_buf3_d7 ) ,
.val_o ( vhalf_2_1_pel3_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_4 (
.tap_0_i( q1_buf4_i ) ,
.tap_1_i( q1_buf4_d1 ) ,
.tap_2_i( q1_buf4_d2 ) ,
.tap_3_i( q1_buf4_d3 ) ,
.tap_4_i( q1_buf4_d4 ) ,
.tap_5_i( q1_buf4_d5 ) ,
.tap_6_i( q1_buf4_d6 ) ,
.tap_7_i( q1_buf4_d7 ) ,
.val_o ( vhalf_2_1_pel4_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_5 (
.tap_0_i( q1_buf5_i ) ,
.tap_1_i( q1_buf5_d1 ) ,
.tap_2_i( q1_buf5_d2 ) ,
.tap_3_i( q1_buf5_d3 ) ,
.tap_4_i( q1_buf5_d4 ) ,
.tap_5_i( q1_buf5_d5 ) ,
.tap_6_i( q1_buf5_d6 ) ,
.tap_7_i( q1_buf5_d7 ) ,
.val_o ( vhalf_2_1_pel5_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_6 (
.tap_0_i( q1_buf6_i ) ,
.tap_1_i( q1_buf6_d1 ) ,
.tap_2_i( q1_buf6_d2 ) ,
.tap_3_i( q1_buf6_d3 ) ,
.tap_4_i( q1_buf6_d4 ) ,
.tap_5_i( q1_buf6_d5 ) ,
.tap_6_i( q1_buf6_d6 ) ,
.tap_7_i( q1_buf6_d7 ) ,
.val_o ( vhalf_2_1_pel6_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_7 (
.tap_0_i( q1_buf7_i ) ,
.tap_1_i( q1_buf7_d1 ) ,
.tap_2_i( q1_buf7_d2 ) ,
.tap_3_i( q1_buf7_d3 ) ,
.tap_4_i( q1_buf7_d4 ) ,
.tap_5_i( q1_buf7_d5 ) ,
.tap_6_i( q1_buf7_d6 ) ,
.tap_7_i( q1_buf7_d7 ) ,
.val_o ( vhalf_2_1_pel7_o)
);
//from q3
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_0 (
.tap_0_i( q3_buf0_i ) ,
.tap_1_i( q3_buf0_d1 ) ,
.tap_2_i( q3_buf0_d2 ) ,
.tap_3_i( q3_buf0_d3 ) ,
.tap_4_i( q3_buf0_d4 ) ,
.tap_5_i( q3_buf0_d5 ) ,
.tap_6_i( q3_buf0_d6 ) ,
.tap_7_i( q3_buf0_d7 ) ,
.val_o ( vhalf_2_3_pel0_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_1 (
.tap_0_i( q3_buf1_i ) ,
.tap_1_i( q3_buf1_d1 ) ,
.tap_2_i( q3_buf1_d2 ) ,
.tap_3_i( q3_buf1_d3 ) ,
.tap_4_i( q3_buf1_d4 ) ,
.tap_5_i( q3_buf1_d5 ) ,
.tap_6_i( q3_buf1_d6 ) ,
.tap_7_i( q3_buf1_d7 ) ,
.val_o ( vhalf_2_3_pel1_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_2 (
.tap_0_i( q3_buf2_i ) ,
.tap_1_i( q3_buf2_d1 ) ,
.tap_2_i( q3_buf2_d2 ) ,
.tap_3_i( q3_buf2_d3 ) ,
.tap_4_i( q3_buf2_d4 ) ,
.tap_5_i( q3_buf2_d5 ) ,
.tap_6_i( q3_buf2_d6 ) ,
.tap_7_i( q3_buf2_d7 ) ,
.val_o ( vhalf_2_3_pel2_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_3 (
.tap_0_i( q3_buf3_i ) ,
.tap_1_i( q3_buf3_d1 ) ,
.tap_2_i( q3_buf3_d2 ) ,
.tap_3_i( q3_buf3_d3 ) ,
.tap_4_i( q3_buf3_d4 ) ,
.tap_5_i( q3_buf3_d5 ) ,
.tap_6_i( q3_buf3_d6 ) ,
.tap_7_i( q3_buf3_d7 ) ,
.val_o ( vhalf_2_3_pel3_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_4 (
.tap_0_i( q3_buf4_i ) ,
.tap_1_i( q3_buf4_d1 ) ,
.tap_2_i( q3_buf4_d2 ) ,
.tap_3_i( q3_buf4_d3 ) ,
.tap_4_i( q3_buf4_d4 ) ,
.tap_5_i( q3_buf4_d5 ) ,
.tap_6_i( q3_buf4_d6 ) ,
.tap_7_i( q3_buf4_d7 ) ,
.val_o ( vhalf_2_3_pel4_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_5 (
.tap_0_i( q3_buf5_i ) ,
.tap_1_i( q3_buf5_d1 ) ,
.tap_2_i( q3_buf5_d2 ) ,
.tap_3_i( q3_buf5_d3 ) ,
.tap_4_i( q3_buf5_d4 ) ,
.tap_5_i( q3_buf5_d5 ) ,
.tap_6_i( q3_buf5_d6 ) ,
.tap_7_i( q3_buf5_d7 ) ,
.val_o ( vhalf_2_3_pel5_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_6 (
.tap_0_i( q3_buf6_i ) ,
.tap_1_i( q3_buf6_d1 ) ,
.tap_2_i( q3_buf6_d2 ) ,
.tap_3_i( q3_buf6_d3 ) ,
.tap_4_i( q3_buf6_d4 ) ,
.tap_5_i( q3_buf6_d5 ) ,
.tap_6_i( q3_buf6_d6 ) ,
.tap_7_i( q3_buf6_d7 ) ,
.val_o ( vhalf_2_3_pel6_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_7 (
.tap_0_i( q3_buf7_i ) ,
.tap_1_i( q3_buf7_d1 ) ,
.tap_2_i( q3_buf7_d2 ) ,
.tap_3_i( q3_buf7_d3 ) ,
.tap_4_i( q3_buf7_d4 ) ,
.tap_5_i( q3_buf7_d5 ) ,
.tap_6_i( q3_buf7_d6 ) ,
.tap_7_i( q3_buf7_d7 ) ,
.val_o ( vhalf_2_3_pel7_o)
);
// clip
clip2 clip_0_1_0 (
.val_in(q1_buf0_i),
.val_out(vpel_0_1_pel0_o)
);
clip2 clip_0_1_1 (
.val_in(q1_buf1_i),
.val_out(vpel_0_1_pel1_o)
);
clip2 clip_0_1_2 (
.val_in(q1_buf2_i),
.val_out(vpel_0_1_pel2_o)
);
clip2 clip_0_1_3 (
.val_in(q1_buf3_i),
.val_out(vpel_0_1_pel3_o)
);
clip2 clip_0_1_4 (
.val_in(q1_buf4_i),
.val_out(vpel_0_1_pel4_o)
);
clip2 clip_0_1_5 (
.val_in(q1_buf5_i),
.val_out(vpel_0_1_pel5_o)
);
clip2 clip_0_1_6 (
.val_in(q1_buf6_i),
.val_out(vpel_0_1_pel6_o)
);
clip2 clip_0_1_7 (
.val_in(q1_buf7_i),
.val_out(vpel_0_1_pel7_o)
);
//
clip2 clip_0_3_0 (
.val_in(q3_buf0_i),
.val_out(vpel_0_3_pel0_o)
);
clip2 clip_0_3_1 (
.val_in(q3_buf1_i),
.val_out(vpel_0_3_pel1_o)
);
clip2 clip_0_3_2 (
.val_in(q3_buf2_i),
.val_out(vpel_0_3_pel2_o)
);
clip2 clip_0_3_3 (
.val_in(q3_buf3_i),
.val_out(vpel_0_3_pel3_o)
);
clip2 clip_0_3_4 (
.val_in(q3_buf4_i),
.val_out(vpel_0_3_pel4_o)
);
clip2 clip_0_3_5 (
.val_in(q3_buf5_i),
.val_out(vpel_0_3_pel5_o)
);
clip2 clip_0_3_6 (
.val_in(q3_buf6_i),
.val_out(vpel_0_3_pel6_o)
);
clip2 clip_0_3_7 (
.val_in(q3_buf7_i),
.val_out(vpel_0_3_pel7_o)
);
/*
assign cnthorLargerThan3 = (cnt_hor >='d3 && cnt_hor <='d10);
assign cnthorLargerThan4 = (cnt_hor >='d4 && cnt_hor <='d11);
assign cntrefLargerThan7 = (cnt_ref >='d7 && cnt_ref <='d14);
assign cntrefLargerThan8 = (cnt_ref [3]);
assign cnthorLargerThan7 = (cnt_hor >='d7 && cnt_hor <='d14);
assign cnthorLargerThan8 = (cnt_hor [3]);
assign vquarter_1_valid_o = (frac_y_i == 2'b00 || frac_y_i == 2'b01) ? (cnthorLargerThan8) : (cnthorLargerThan7);
assign vquarter_3_valid_o = (frac_y_i == 2'b00 ) ? (cnthorLargerThan8) : (cnthorLargerThan7);
assign vquarter_2_valid_o = (frac_y_i == 2'b00 || frac_y_i == 2'b01) ? (cnthorLargerThan8) : (cnthorLargerThan7);
assign vquarter_0_valid_o = (frac_y_i == 2'b00 || frac_y_i == 2'b01) ? (cntrefLargerThan8) : (cntrefLargerThan7);
assign vhalf_valid_o = (frac_y_i == 2'b00 || frac_y_i == 2'b01) ? (cnthorLargerThan4) : (cnthorLargerThan3);
assign vpel_valid_o = (frac_y_i == 2'b00 || frac_y_i == 2'b01) ? (cnthorLargerThan4) : (cnthorLargerThan3);
*/
endmodule
|
// Computer_System_mm_interconnect_4.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Computer_System_mm_interconnect_4 (
input wire System_PLL_sys_clk_clk, // System_PLL_sys_clk.clk
input wire Expansion_JP1_reset_reset_bridge_in_reset_reset, // Expansion_JP1_reset_reset_bridge_in_reset.reset
input wire Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset, // Video_In_Subsystem_sys_reset_reset_bridge_in_reset.reset
input wire [3:0] Video_In_Subsystem_top_io_gpi1_streamin_address, // Video_In_Subsystem_top_io_gpi1_streamin.address
input wire Video_In_Subsystem_top_io_gpi1_streamin_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpi1_streamin_read, // .read
output wire [31:0] Video_In_Subsystem_top_io_gpi1_streamin_readdata, // .readdata
input wire [3:0] Video_In_Subsystem_top_io_gpo1_streamout_address, // Video_In_Subsystem_top_io_gpo1_streamout.address
input wire Video_In_Subsystem_top_io_gpo1_streamout_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpo1_streamout_write, // .write
input wire [31:0] Video_In_Subsystem_top_io_gpo1_streamout_writedata, // .writedata
output wire [1:0] Expansion_JP1_s1_address, // Expansion_JP1_s1.address
output wire Expansion_JP1_s1_write, // .write
input wire [31:0] Expansion_JP1_s1_readdata, // .readdata
output wire [31:0] Expansion_JP1_s1_writedata, // .writedata
output wire Expansion_JP1_s1_chipselect // .chipselect
);
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpi1_streamin_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpi1_streamin_agent:av_readdata -> Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_readdata
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_address -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_address
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_read -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_byteenable
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpi1_streamin_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_lock -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_lock
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_write -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_writedata -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_valid
wire [73:0] rsp_mux_src_data; // rsp_mux:src_data -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_data
wire rsp_mux_src_ready; // Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_endofpacket
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpo1_streamout_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpo1_streamout_agent:av_readdata -> Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_readdata
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_address -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_address
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_read -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_byteenable
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpo1_streamout_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_lock -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_lock
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_write -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_writedata -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_valid
wire [73:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_data
wire rsp_mux_001_src_ready; // Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_ready -> rsp_mux_001:src_ready
wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_endofpacket
wire [31:0] expansion_jp1_s1_agent_m0_readdata; // Expansion_JP1_s1_translator:uav_readdata -> Expansion_JP1_s1_agent:m0_readdata
wire expansion_jp1_s1_agent_m0_waitrequest; // Expansion_JP1_s1_translator:uav_waitrequest -> Expansion_JP1_s1_agent:m0_waitrequest
wire expansion_jp1_s1_agent_m0_debugaccess; // Expansion_JP1_s1_agent:m0_debugaccess -> Expansion_JP1_s1_translator:uav_debugaccess
wire [3:0] expansion_jp1_s1_agent_m0_address; // Expansion_JP1_s1_agent:m0_address -> Expansion_JP1_s1_translator:uav_address
wire [3:0] expansion_jp1_s1_agent_m0_byteenable; // Expansion_JP1_s1_agent:m0_byteenable -> Expansion_JP1_s1_translator:uav_byteenable
wire expansion_jp1_s1_agent_m0_read; // Expansion_JP1_s1_agent:m0_read -> Expansion_JP1_s1_translator:uav_read
wire expansion_jp1_s1_agent_m0_readdatavalid; // Expansion_JP1_s1_translator:uav_readdatavalid -> Expansion_JP1_s1_agent:m0_readdatavalid
wire expansion_jp1_s1_agent_m0_lock; // Expansion_JP1_s1_agent:m0_lock -> Expansion_JP1_s1_translator:uav_lock
wire [31:0] expansion_jp1_s1_agent_m0_writedata; // Expansion_JP1_s1_agent:m0_writedata -> Expansion_JP1_s1_translator:uav_writedata
wire expansion_jp1_s1_agent_m0_write; // Expansion_JP1_s1_agent:m0_write -> Expansion_JP1_s1_translator:uav_write
wire [2:0] expansion_jp1_s1_agent_m0_burstcount; // Expansion_JP1_s1_agent:m0_burstcount -> Expansion_JP1_s1_translator:uav_burstcount
wire expansion_jp1_s1_agent_rf_source_valid; // Expansion_JP1_s1_agent:rf_source_valid -> Expansion_JP1_s1_agent_rsp_fifo:in_valid
wire [74:0] expansion_jp1_s1_agent_rf_source_data; // Expansion_JP1_s1_agent:rf_source_data -> Expansion_JP1_s1_agent_rsp_fifo:in_data
wire expansion_jp1_s1_agent_rf_source_ready; // Expansion_JP1_s1_agent_rsp_fifo:in_ready -> Expansion_JP1_s1_agent:rf_source_ready
wire expansion_jp1_s1_agent_rf_source_startofpacket; // Expansion_JP1_s1_agent:rf_source_startofpacket -> Expansion_JP1_s1_agent_rsp_fifo:in_startofpacket
wire expansion_jp1_s1_agent_rf_source_endofpacket; // Expansion_JP1_s1_agent:rf_source_endofpacket -> Expansion_JP1_s1_agent_rsp_fifo:in_endofpacket
wire expansion_jp1_s1_agent_rsp_fifo_out_valid; // Expansion_JP1_s1_agent_rsp_fifo:out_valid -> Expansion_JP1_s1_agent:rf_sink_valid
wire [74:0] expansion_jp1_s1_agent_rsp_fifo_out_data; // Expansion_JP1_s1_agent_rsp_fifo:out_data -> Expansion_JP1_s1_agent:rf_sink_data
wire expansion_jp1_s1_agent_rsp_fifo_out_ready; // Expansion_JP1_s1_agent:rf_sink_ready -> Expansion_JP1_s1_agent_rsp_fifo:out_ready
wire expansion_jp1_s1_agent_rsp_fifo_out_startofpacket; // Expansion_JP1_s1_agent_rsp_fifo:out_startofpacket -> Expansion_JP1_s1_agent:rf_sink_startofpacket
wire expansion_jp1_s1_agent_rsp_fifo_out_endofpacket; // Expansion_JP1_s1_agent_rsp_fifo:out_endofpacket -> Expansion_JP1_s1_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> Expansion_JP1_s1_agent:cp_valid
wire [73:0] cmd_mux_src_data; // cmd_mux:src_data -> Expansion_JP1_s1_agent:cp_data
wire cmd_mux_src_ready; // Expansion_JP1_s1_agent:cp_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> Expansion_JP1_s1_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> Expansion_JP1_s1_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> Expansion_JP1_s1_agent:cp_endofpacket
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_valid; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_valid -> router:sink_valid
wire [73:0] video_in_subsystem_top_io_gpi1_streamin_agent_cp_data; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_data -> router:sink_data
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_ready; // router:sink_ready -> Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_ready
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_startofpacket -> router:sink_startofpacket
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [73:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_valid; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_valid -> router_001:sink_valid
wire [73:0] video_in_subsystem_top_io_gpo1_streamout_agent_cp_data; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_data -> router_001:sink_data
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_ready; // router_001:sink_ready -> Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_ready
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_startofpacket -> router_001:sink_startofpacket
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [73:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire expansion_jp1_s1_agent_rp_valid; // Expansion_JP1_s1_agent:rp_valid -> router_002:sink_valid
wire [73:0] expansion_jp1_s1_agent_rp_data; // Expansion_JP1_s1_agent:rp_data -> router_002:sink_data
wire expansion_jp1_s1_agent_rp_ready; // router_002:sink_ready -> Expansion_JP1_s1_agent:rp_ready
wire expansion_jp1_s1_agent_rp_startofpacket; // Expansion_JP1_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire expansion_jp1_s1_agent_rp_endofpacket; // Expansion_JP1_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [73:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [73:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [73:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [73:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [73:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire expansion_jp1_s1_agent_rdata_fifo_src_valid; // Expansion_JP1_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] expansion_jp1_s1_agent_rdata_fifo_src_data; // Expansion_JP1_s1_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire expansion_jp1_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> Expansion_JP1_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> Expansion_JP1_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> Expansion_JP1_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // Expansion_JP1_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> Expansion_JP1_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpi1_streamin_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpi1_streamin_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpi1_streamin_chipselect), // .chipselect
.av_read (Video_In_Subsystem_top_io_gpi1_streamin_read), // .read
.av_readdata (Video_In_Subsystem_top_io_gpi1_streamin_readdata), // .readdata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (0),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpo1_streamout_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpo1_streamout_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpo1_streamout_chipselect), // .chipselect
.av_write (Video_In_Subsystem_top_io_gpo1_streamout_write), // .write
.av_writedata (Video_In_Subsystem_top_io_gpo1_streamout_writedata), // .writedata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_read (1'b0), // (terminated)
.av_readdata (), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) expansion_jp1_s1_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (expansion_jp1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (expansion_jp1_s1_agent_m0_burstcount), // .burstcount
.uav_read (expansion_jp1_s1_agent_m0_read), // .read
.uav_write (expansion_jp1_s1_agent_m0_write), // .write
.uav_waitrequest (expansion_jp1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (expansion_jp1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (expansion_jp1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (expansion_jp1_s1_agent_m0_readdata), // .readdata
.uav_writedata (expansion_jp1_s1_agent_m0_writedata), // .writedata
.uav_lock (expansion_jp1_s1_agent_m0_lock), // .lock
.uav_debugaccess (expansion_jp1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (Expansion_JP1_s1_address), // avalon_anti_slave_0.address
.av_write (Expansion_JP1_s1_write), // .write
.av_readdata (Expansion_JP1_s1_readdata), // .readdata
.av_writedata (Expansion_JP1_s1_writedata), // .writedata
.av_chipselect (Expansion_JP1_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpi1_streamin_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpi1_streamin_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpi1_streamin_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpi1_streamin_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpo1_streamout_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpo1_streamout_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpo1_streamout_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpo1_streamout_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (74),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) expansion_jp1_s1_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (expansion_jp1_s1_agent_m0_address), // m0.address
.m0_burstcount (expansion_jp1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (expansion_jp1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (expansion_jp1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (expansion_jp1_s1_agent_m0_lock), // .lock
.m0_readdata (expansion_jp1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (expansion_jp1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (expansion_jp1_s1_agent_m0_read), // .read
.m0_waitrequest (expansion_jp1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (expansion_jp1_s1_agent_m0_writedata), // .writedata
.m0_write (expansion_jp1_s1_agent_m0_write), // .write
.rp_endofpacket (expansion_jp1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (expansion_jp1_s1_agent_rp_ready), // .ready
.rp_valid (expansion_jp1_s1_agent_rp_valid), // .valid
.rp_data (expansion_jp1_s1_agent_rp_data), // .data
.rp_startofpacket (expansion_jp1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (expansion_jp1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (expansion_jp1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (expansion_jp1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (expansion_jp1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (expansion_jp1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (expansion_jp1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (expansion_jp1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (expansion_jp1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (expansion_jp1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (expansion_jp1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (expansion_jp1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (expansion_jp1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (expansion_jp1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (75),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) expansion_jp1_s1_agent_rsp_fifo (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (expansion_jp1_s1_agent_rf_source_data), // in.data
.in_valid (expansion_jp1_s1_agent_rf_source_valid), // .valid
.in_ready (expansion_jp1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (expansion_jp1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (expansion_jp1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (expansion_jp1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (expansion_jp1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (expansion_jp1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (expansion_jp1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (expansion_jp1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
Computer_System_mm_interconnect_4_router router (
.sink_ready (video_in_subsystem_top_io_gpi1_streamin_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpi1_streamin_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpi1_streamin_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router router_001 (
.sink_ready (video_in_subsystem_top_io_gpo1_streamout_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpo1_streamout_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpo1_streamout_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router_002 router_002 (
.sink_ready (expansion_jp1_s1_agent_rp_ready), // sink.ready
.sink_valid (expansion_jp1_s1_agent_rp_valid), // .valid
.sink_data (expansion_jp1_s1_agent_rp_data), // .data
.sink_startofpacket (expansion_jp1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (expansion_jp1_s1_agent_rp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_mux cmd_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_demux rsp_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (System_PLL_sys_clk_clk), // in_clk_0.clk
.in_rst_0_reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (expansion_jp1_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (expansion_jp1_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (expansion_jp1_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule
|
// DE0_Nano_SOPC.v
// Generated using ACDS version 13.1 162 at 2015.06.30.18:35:36
`timescale 1 ps / 1 ps
module DE0_Nano_SOPC (
input wire reset_n, // clk_50_clk_in_reset.reset_n
input wire clk_50, // clk_50_clk_in.clk
input wire [1:0] in_port_to_the_key, // key_external_connection.export
input wire [3:0] in_port_to_the_sw, // sw_external_connection.export
output wire [7:0] out_port_from_the_led, // led_external_connection.export
output wire out_port_from_the_i2c_scl, // i2c_scl_external_connection.export
inout wire bidir_port_to_and_from_the_i2c_sda, // i2c_sda_external_connection.export
output wire [12:0] zs_addr_from_the_sdram, // sdram_wire.addr
output wire [1:0] zs_ba_from_the_sdram, // .ba
output wire zs_cas_n_from_the_sdram, // .cas_n
output wire zs_cke_from_the_sdram, // .cke
output wire zs_cs_n_from_the_sdram, // .cs_n
inout wire [15:0] zs_dq_to_and_from_the_sdram, // .dq
output wire [1:0] zs_dqm_from_the_sdram, // .dqm
output wire zs_ras_n_from_the_sdram, // .ras_n
output wire zs_we_n_from_the_sdram, // .we_n
output wire altpll_sys, // c0_out_clk.clk
output wire altpll_sdram, // altpll_sys_c1.clk
output wire altpll_io, // c2_out_clk.clk
output wire altpll_sys_c3_out, // altpll_sys_c3.clk
output wire altpll_adc, // c4_out_clk.clk
output wire locked_from_the_altpll_sys, // altpll_sys_locked_conduit.export
output wire phasedone_from_the_altpll_sys, // altpll_sys_phasedone_conduit.export
input wire in_port_to_the_g_sensor_int, // g_sensor_int_external_connection.export
output wire dclk_from_the_epcs, // epcs_external.dclk
output wire sce_from_the_epcs, // .sce
output wire sdo_from_the_epcs, // .sdo
input wire data0_to_the_epcs, // .data0
inout wire SPI_SDIO_to_and_from_the_gsensor_spi, // gsensor_spi_conduit_end.SDIO
output wire SPI_SCLK_from_the_gsensor_spi, // .SCLK
output wire SPI_CS_n_from_the_gsensor_spi, // .CS_n
output wire out_port_from_the_select_i2c_clk, // select_i2c_clk_external_connection.export
output wire [23:0] GPIO_out_from_the_motor_controller_0, // motor_controller_0_conduit_end.export
output wire kill_sw_from_the_power_management_slave_0, // power_management_slave_0_conduit_end.kill_sw
output wire [2:0] mux_from_the_power_management_slave_0, // .mux
input wire data_to_the_power_management_slave_0, // .data
input wire sys_clk_to_the_imu_controller_0, // imu_controller_0_conduit_end.sys_clk
input wire ADC_SDAT_to_the_imu_controller_0, // .ADC_SDAT
output wire ADC_CS_N_from_the_imu_controller_0, // .ADC_CS_N
output wire ADC_SADDR_from_the_imu_controller_0, // .ADC_SADDR
output wire ADC_SCLK_from_the_imu_controller_0, // .ADC_SCLK
input wire UART_RXD_to_the_RS232_0, // RS232_0_conduit_end.export
output wire UART_TXD_from_the_RS232_0 // RS232_0_conduit_end_1.export
);
wire [31:0] mm_interconnect_0_altpll_sys_pll_slave_writedata; // mm_interconnect_0:altpll_sys_pll_slave_writedata -> altpll_sys:writedata
wire [1:0] mm_interconnect_0_altpll_sys_pll_slave_address; // mm_interconnect_0:altpll_sys_pll_slave_address -> altpll_sys:address
wire mm_interconnect_0_altpll_sys_pll_slave_write; // mm_interconnect_0:altpll_sys_pll_slave_write -> altpll_sys:write
wire mm_interconnect_0_altpll_sys_pll_slave_read; // mm_interconnect_0:altpll_sys_pll_slave_read -> altpll_sys:read
wire [31:0] mm_interconnect_0_altpll_sys_pll_slave_readdata; // altpll_sys:readdata -> mm_interconnect_0:altpll_sys_pll_slave_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire [31:0] mm_interconnect_0_rs232_0_avalon_slave_0_writedata; // mm_interconnect_0:RS232_0_avalon_slave_0_writedata -> RS232_0:writedata
wire [0:0] mm_interconnect_0_rs232_0_avalon_slave_0_address; // mm_interconnect_0:RS232_0_avalon_slave_0_address -> RS232_0:address
wire mm_interconnect_0_rs232_0_avalon_slave_0_chipselect; // mm_interconnect_0:RS232_0_avalon_slave_0_chipselect -> RS232_0:chipselect
wire mm_interconnect_0_rs232_0_avalon_slave_0_write; // mm_interconnect_0:RS232_0_avalon_slave_0_write -> RS232_0:write
wire mm_interconnect_0_rs232_0_avalon_slave_0_read; // mm_interconnect_0:RS232_0_avalon_slave_0_read -> RS232_0:read
wire [31:0] mm_interconnect_0_rs232_0_avalon_slave_0_readdata; // RS232_0:readdata -> mm_interconnect_0:RS232_0_avalon_slave_0_readdata
wire [3:0] mm_interconnect_0_rs232_0_avalon_slave_0_byteenable; // mm_interconnect_0:RS232_0_avalon_slave_0_byteenable -> RS232_0:byteenable
wire mm_interconnect_0_clock_crossing_io_s0_waitrequest; // clock_crossing_io:s0_waitrequest -> mm_interconnect_0:clock_crossing_io_s0_waitrequest
wire [0:0] mm_interconnect_0_clock_crossing_io_s0_burstcount; // mm_interconnect_0:clock_crossing_io_s0_burstcount -> clock_crossing_io:s0_burstcount
wire [31:0] mm_interconnect_0_clock_crossing_io_s0_writedata; // mm_interconnect_0:clock_crossing_io_s0_writedata -> clock_crossing_io:s0_writedata
wire [6:0] mm_interconnect_0_clock_crossing_io_s0_address; // mm_interconnect_0:clock_crossing_io_s0_address -> clock_crossing_io:s0_address
wire mm_interconnect_0_clock_crossing_io_s0_write; // mm_interconnect_0:clock_crossing_io_s0_write -> clock_crossing_io:s0_write
wire mm_interconnect_0_clock_crossing_io_s0_read; // mm_interconnect_0:clock_crossing_io_s0_read -> clock_crossing_io:s0_read
wire [31:0] mm_interconnect_0_clock_crossing_io_s0_readdata; // clock_crossing_io:s0_readdata -> mm_interconnect_0:clock_crossing_io_s0_readdata
wire mm_interconnect_0_clock_crossing_io_s0_debugaccess; // mm_interconnect_0:clock_crossing_io_s0_debugaccess -> clock_crossing_io:s0_debugaccess
wire mm_interconnect_0_clock_crossing_io_s0_readdatavalid; // clock_crossing_io:s0_readdatavalid -> mm_interconnect_0:clock_crossing_io_s0_readdatavalid
wire [3:0] mm_interconnect_0_clock_crossing_io_s0_byteenable; // mm_interconnect_0:clock_crossing_io_s0_byteenable -> clock_crossing_io:s0_byteenable
wire mm_interconnect_0_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_0:sdram_s1_waitrequest
wire [15:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:sdram_s1_writedata -> sdram:az_data
wire [23:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:sdram_s1_address -> sdram:az_addr
wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:sdram_s1_chipselect -> sdram:az_cs
wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:sdram_s1_write -> sdram:az_wr_n
wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:sdram_s1_read -> sdram:az_rd_n
wire [15:0] mm_interconnect_0_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_0:sdram_s1_readdata
wire mm_interconnect_0_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_0:sdram_s1_readdatavalid
wire [1:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:sdram_s1_byteenable -> sdram:az_be_n
wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
wire [26:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
wire mm_interconnect_0_clock_crossing_io2_s0_waitrequest; // clock_crossing_io2:s0_waitrequest -> mm_interconnect_0:clock_crossing_io2_s0_waitrequest
wire [0:0] mm_interconnect_0_clock_crossing_io2_s0_burstcount; // mm_interconnect_0:clock_crossing_io2_s0_burstcount -> clock_crossing_io2:s0_burstcount
wire [31:0] mm_interconnect_0_clock_crossing_io2_s0_writedata; // mm_interconnect_0:clock_crossing_io2_s0_writedata -> clock_crossing_io2:s0_writedata
wire [11:0] mm_interconnect_0_clock_crossing_io2_s0_address; // mm_interconnect_0:clock_crossing_io2_s0_address -> clock_crossing_io2:s0_address
wire mm_interconnect_0_clock_crossing_io2_s0_write; // mm_interconnect_0:clock_crossing_io2_s0_write -> clock_crossing_io2:s0_write
wire mm_interconnect_0_clock_crossing_io2_s0_read; // mm_interconnect_0:clock_crossing_io2_s0_read -> clock_crossing_io2:s0_read
wire [31:0] mm_interconnect_0_clock_crossing_io2_s0_readdata; // clock_crossing_io2:s0_readdata -> mm_interconnect_0:clock_crossing_io2_s0_readdata
wire mm_interconnect_0_clock_crossing_io2_s0_debugaccess; // mm_interconnect_0:clock_crossing_io2_s0_debugaccess -> clock_crossing_io2:s0_debugaccess
wire mm_interconnect_0_clock_crossing_io2_s0_readdatavalid; // clock_crossing_io2:s0_readdatavalid -> mm_interconnect_0:clock_crossing_io2_s0_readdatavalid
wire [3:0] mm_interconnect_0_clock_crossing_io2_s0_byteenable; // mm_interconnect_0:clock_crossing_io2_s0_byteenable -> clock_crossing_io2:s0_byteenable
wire [3:0] mm_interconnect_0_imu_controller_0_avalon_slave_0_address; // mm_interconnect_0:imu_controller_0_avalon_slave_0_address -> imu_controller_0:addr
wire mm_interconnect_0_imu_controller_0_avalon_slave_0_chipselect; // mm_interconnect_0:imu_controller_0_avalon_slave_0_chipselect -> imu_controller_0:chipselect
wire mm_interconnect_0_imu_controller_0_avalon_slave_0_read; // mm_interconnect_0:imu_controller_0_avalon_slave_0_read -> imu_controller_0:read
wire [31:0] mm_interconnect_0_imu_controller_0_avalon_slave_0_readdata; // imu_controller_0:readdata -> mm_interconnect_0:imu_controller_0_avalon_slave_0_readdata
wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
wire [26:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
wire cpu_data_master_debugaccess; // cpu:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
wire [15:0] mm_interconnect_0_controller_interrupt_counter_s1_writedata; // mm_interconnect_0:controller_interrupt_counter_s1_writedata -> controller_interrupt_counter:writedata
wire [2:0] mm_interconnect_0_controller_interrupt_counter_s1_address; // mm_interconnect_0:controller_interrupt_counter_s1_address -> controller_interrupt_counter:address
wire mm_interconnect_0_controller_interrupt_counter_s1_chipselect; // mm_interconnect_0:controller_interrupt_counter_s1_chipselect -> controller_interrupt_counter:chipselect
wire mm_interconnect_0_controller_interrupt_counter_s1_write; // mm_interconnect_0:controller_interrupt_counter_s1_write -> controller_interrupt_counter:write_n
wire [15:0] mm_interconnect_0_controller_interrupt_counter_s1_readdata; // controller_interrupt_counter:readdata -> mm_interconnect_0:controller_interrupt_counter_s1_readdata
wire mm_interconnect_0_cpu_jtag_debug_module_waitrequest; // cpu:jtag_debug_module_waitrequest -> mm_interconnect_0:cpu_jtag_debug_module_waitrequest
wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_writedata; // mm_interconnect_0:cpu_jtag_debug_module_writedata -> cpu:jtag_debug_module_writedata
wire [8:0] mm_interconnect_0_cpu_jtag_debug_module_address; // mm_interconnect_0:cpu_jtag_debug_module_address -> cpu:jtag_debug_module_address
wire mm_interconnect_0_cpu_jtag_debug_module_write; // mm_interconnect_0:cpu_jtag_debug_module_write -> cpu:jtag_debug_module_write
wire mm_interconnect_0_cpu_jtag_debug_module_read; // mm_interconnect_0:cpu_jtag_debug_module_read -> cpu:jtag_debug_module_read
wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_readdata; // cpu:jtag_debug_module_readdata -> mm_interconnect_0:cpu_jtag_debug_module_readdata
wire mm_interconnect_0_cpu_jtag_debug_module_debugaccess; // mm_interconnect_0:cpu_jtag_debug_module_debugaccess -> cpu:jtag_debug_module_debugaccess
wire [3:0] mm_interconnect_0_cpu_jtag_debug_module_byteenable; // mm_interconnect_0:cpu_jtag_debug_module_byteenable -> cpu:jtag_debug_module_byteenable
wire [31:0] mm_interconnect_0_motor_controller_0_avalon_slave_0_writedata; // mm_interconnect_0:motor_controller_0_avalon_slave_0_writedata -> motor_controller_0:writedata
wire [3:0] mm_interconnect_0_motor_controller_0_avalon_slave_0_address; // mm_interconnect_0:motor_controller_0_avalon_slave_0_address -> motor_controller_0:addr
wire mm_interconnect_0_motor_controller_0_avalon_slave_0_chipselect; // mm_interconnect_0:motor_controller_0_avalon_slave_0_chipselect -> motor_controller_0:chipselect
wire mm_interconnect_0_motor_controller_0_avalon_slave_0_write; // mm_interconnect_0:motor_controller_0_avalon_slave_0_write -> motor_controller_0:write
wire [31:0] mm_interconnect_0_power_management_slave_0_avalon_slave_0_writedata; // mm_interconnect_0:power_management_slave_0_avalon_slave_0_writedata -> power_management_slave_0:writedata
wire mm_interconnect_0_power_management_slave_0_avalon_slave_0_chipselect; // mm_interconnect_0:power_management_slave_0_avalon_slave_0_chipselect -> power_management_slave_0:chipselect
wire mm_interconnect_0_power_management_slave_0_avalon_slave_0_write; // mm_interconnect_0:power_management_slave_0_avalon_slave_0_write -> power_management_slave_0:write
wire mm_interconnect_0_power_management_slave_0_avalon_slave_0_read; // mm_interconnect_0:power_management_slave_0_avalon_slave_0_read -> power_management_slave_0:read
wire [31:0] mm_interconnect_0_power_management_slave_0_avalon_slave_0_readdata; // power_management_slave_0:readdata -> mm_interconnect_0:power_management_slave_0_avalon_slave_0_readdata
wire [0:0] clock_crossing_io_m0_burstcount; // clock_crossing_io:m0_burstcount -> mm_interconnect_1:clock_crossing_io_m0_burstcount
wire clock_crossing_io_m0_waitrequest; // mm_interconnect_1:clock_crossing_io_m0_waitrequest -> clock_crossing_io:m0_waitrequest
wire [6:0] clock_crossing_io_m0_address; // clock_crossing_io:m0_address -> mm_interconnect_1:clock_crossing_io_m0_address
wire [31:0] clock_crossing_io_m0_writedata; // clock_crossing_io:m0_writedata -> mm_interconnect_1:clock_crossing_io_m0_writedata
wire clock_crossing_io_m0_write; // clock_crossing_io:m0_write -> mm_interconnect_1:clock_crossing_io_m0_write
wire clock_crossing_io_m0_read; // clock_crossing_io:m0_read -> mm_interconnect_1:clock_crossing_io_m0_read
wire [31:0] clock_crossing_io_m0_readdata; // mm_interconnect_1:clock_crossing_io_m0_readdata -> clock_crossing_io:m0_readdata
wire clock_crossing_io_m0_debugaccess; // clock_crossing_io:m0_debugaccess -> mm_interconnect_1:clock_crossing_io_m0_debugaccess
wire [3:0] clock_crossing_io_m0_byteenable; // clock_crossing_io:m0_byteenable -> mm_interconnect_1:clock_crossing_io_m0_byteenable
wire clock_crossing_io_m0_readdatavalid; // mm_interconnect_1:clock_crossing_io_m0_readdatavalid -> clock_crossing_io:m0_readdatavalid
wire [0:0] mm_interconnect_1_sysid_control_slave_address; // mm_interconnect_1:sysid_control_slave_address -> sysid:address
wire [31:0] mm_interconnect_1_sysid_control_slave_readdata; // sysid:readdata -> mm_interconnect_1:sysid_control_slave_readdata
wire [31:0] mm_interconnect_1_select_i2c_clk_s1_writedata; // mm_interconnect_1:select_i2c_clk_s1_writedata -> select_i2c_clk:writedata
wire [1:0] mm_interconnect_1_select_i2c_clk_s1_address; // mm_interconnect_1:select_i2c_clk_s1_address -> select_i2c_clk:address
wire mm_interconnect_1_select_i2c_clk_s1_chipselect; // mm_interconnect_1:select_i2c_clk_s1_chipselect -> select_i2c_clk:chipselect
wire mm_interconnect_1_select_i2c_clk_s1_write; // mm_interconnect_1:select_i2c_clk_s1_write -> select_i2c_clk:write_n
wire [31:0] mm_interconnect_1_select_i2c_clk_s1_readdata; // select_i2c_clk:readdata -> mm_interconnect_1:select_i2c_clk_s1_readdata
wire [31:0] mm_interconnect_1_led_s1_writedata; // mm_interconnect_1:led_s1_writedata -> led:writedata
wire [1:0] mm_interconnect_1_led_s1_address; // mm_interconnect_1:led_s1_address -> led:address
wire mm_interconnect_1_led_s1_chipselect; // mm_interconnect_1:led_s1_chipselect -> led:chipselect
wire mm_interconnect_1_led_s1_write; // mm_interconnect_1:led_s1_write -> led:write_n
wire [31:0] mm_interconnect_1_led_s1_readdata; // led:readdata -> mm_interconnect_1:led_s1_readdata
wire [31:0] mm_interconnect_1_key_s1_writedata; // mm_interconnect_1:key_s1_writedata -> key:writedata
wire [1:0] mm_interconnect_1_key_s1_address; // mm_interconnect_1:key_s1_address -> key:address
wire mm_interconnect_1_key_s1_chipselect; // mm_interconnect_1:key_s1_chipselect -> key:chipselect
wire mm_interconnect_1_key_s1_write; // mm_interconnect_1:key_s1_write -> key:write_n
wire [31:0] mm_interconnect_1_key_s1_readdata; // key:readdata -> mm_interconnect_1:key_s1_readdata
wire [31:0] mm_interconnect_1_g_sensor_int_s1_writedata; // mm_interconnect_1:g_sensor_int_s1_writedata -> g_sensor_int:writedata
wire [1:0] mm_interconnect_1_g_sensor_int_s1_address; // mm_interconnect_1:g_sensor_int_s1_address -> g_sensor_int:address
wire mm_interconnect_1_g_sensor_int_s1_chipselect; // mm_interconnect_1:g_sensor_int_s1_chipselect -> g_sensor_int:chipselect
wire mm_interconnect_1_g_sensor_int_s1_write; // mm_interconnect_1:g_sensor_int_s1_write -> g_sensor_int:write_n
wire [31:0] mm_interconnect_1_g_sensor_int_s1_readdata; // g_sensor_int:readdata -> mm_interconnect_1:g_sensor_int_s1_readdata
wire [31:0] mm_interconnect_1_sw_s1_writedata; // mm_interconnect_1:sw_s1_writedata -> sw:writedata
wire [1:0] mm_interconnect_1_sw_s1_address; // mm_interconnect_1:sw_s1_address -> sw:address
wire mm_interconnect_1_sw_s1_chipselect; // mm_interconnect_1:sw_s1_chipselect -> sw:chipselect
wire mm_interconnect_1_sw_s1_write; // mm_interconnect_1:sw_s1_write -> sw:write_n
wire [31:0] mm_interconnect_1_sw_s1_readdata; // sw:readdata -> mm_interconnect_1:sw_s1_readdata
wire [31:0] mm_interconnect_2_i2c_sda_s1_writedata; // mm_interconnect_2:i2c_sda_s1_writedata -> i2c_sda:writedata
wire [1:0] mm_interconnect_2_i2c_sda_s1_address; // mm_interconnect_2:i2c_sda_s1_address -> i2c_sda:address
wire mm_interconnect_2_i2c_sda_s1_chipselect; // mm_interconnect_2:i2c_sda_s1_chipselect -> i2c_sda:chipselect
wire mm_interconnect_2_i2c_sda_s1_write; // mm_interconnect_2:i2c_sda_s1_write -> i2c_sda:write_n
wire [31:0] mm_interconnect_2_i2c_sda_s1_readdata; // i2c_sda:readdata -> mm_interconnect_2:i2c_sda_s1_readdata
wire [31:0] mm_interconnect_2_epcs_epcs_control_port_writedata; // mm_interconnect_2:epcs_epcs_control_port_writedata -> epcs:writedata
wire [8:0] mm_interconnect_2_epcs_epcs_control_port_address; // mm_interconnect_2:epcs_epcs_control_port_address -> epcs:address
wire mm_interconnect_2_epcs_epcs_control_port_chipselect; // mm_interconnect_2:epcs_epcs_control_port_chipselect -> epcs:chipselect
wire mm_interconnect_2_epcs_epcs_control_port_write; // mm_interconnect_2:epcs_epcs_control_port_write -> epcs:write_n
wire mm_interconnect_2_epcs_epcs_control_port_read; // mm_interconnect_2:epcs_epcs_control_port_read -> epcs:read_n
wire [31:0] mm_interconnect_2_epcs_epcs_control_port_readdata; // epcs:readdata -> mm_interconnect_2:epcs_epcs_control_port_readdata
wire [31:0] mm_interconnect_2_i2c_scl_s1_writedata; // mm_interconnect_2:i2c_scl_s1_writedata -> i2c_scl:writedata
wire [1:0] mm_interconnect_2_i2c_scl_s1_address; // mm_interconnect_2:i2c_scl_s1_address -> i2c_scl:address
wire mm_interconnect_2_i2c_scl_s1_chipselect; // mm_interconnect_2:i2c_scl_s1_chipselect -> i2c_scl:chipselect
wire mm_interconnect_2_i2c_scl_s1_write; // mm_interconnect_2:i2c_scl_s1_write -> i2c_scl:write_n
wire [31:0] mm_interconnect_2_i2c_scl_s1_readdata; // i2c_scl:readdata -> mm_interconnect_2:i2c_scl_s1_readdata
wire [0:0] clock_crossing_io2_m0_burstcount; // clock_crossing_io2:m0_burstcount -> mm_interconnect_2:clock_crossing_io2_m0_burstcount
wire clock_crossing_io2_m0_waitrequest; // mm_interconnect_2:clock_crossing_io2_m0_waitrequest -> clock_crossing_io2:m0_waitrequest
wire [11:0] clock_crossing_io2_m0_address; // clock_crossing_io2:m0_address -> mm_interconnect_2:clock_crossing_io2_m0_address
wire [31:0] clock_crossing_io2_m0_writedata; // clock_crossing_io2:m0_writedata -> mm_interconnect_2:clock_crossing_io2_m0_writedata
wire clock_crossing_io2_m0_write; // clock_crossing_io2:m0_write -> mm_interconnect_2:clock_crossing_io2_m0_write
wire clock_crossing_io2_m0_read; // clock_crossing_io2:m0_read -> mm_interconnect_2:clock_crossing_io2_m0_read
wire [31:0] clock_crossing_io2_m0_readdata; // mm_interconnect_2:clock_crossing_io2_m0_readdata -> clock_crossing_io2:m0_readdata
wire clock_crossing_io2_m0_debugaccess; // clock_crossing_io2:m0_debugaccess -> mm_interconnect_2:clock_crossing_io2_m0_debugaccess
wire [3:0] clock_crossing_io2_m0_byteenable; // clock_crossing_io2:m0_byteenable -> mm_interconnect_2:clock_crossing_io2_m0_byteenable
wire clock_crossing_io2_m0_readdatavalid; // mm_interconnect_2:clock_crossing_io2_m0_readdatavalid -> clock_crossing_io2:m0_readdatavalid
wire [7:0] mm_interconnect_2_gsensor_spi_slave_writedata; // mm_interconnect_2:gsensor_spi_slave_writedata -> gsensor_spi:s_writedata
wire [3:0] mm_interconnect_2_gsensor_spi_slave_address; // mm_interconnect_2:gsensor_spi_slave_address -> gsensor_spi:s_address
wire mm_interconnect_2_gsensor_spi_slave_chipselect; // mm_interconnect_2:gsensor_spi_slave_chipselect -> gsensor_spi:s_chipselect
wire mm_interconnect_2_gsensor_spi_slave_write; // mm_interconnect_2:gsensor_spi_slave_write -> gsensor_spi:s_write
wire mm_interconnect_2_gsensor_spi_slave_read; // mm_interconnect_2:gsensor_spi_slave_read -> gsensor_spi:s_read
wire [7:0] mm_interconnect_2_gsensor_spi_slave_readdata; // gsensor_spi:s_readdata -> mm_interconnect_2:gsensor_spi_slave_readdata
wire irq_mapper_receiver4_irq; // jtag_uart:av_irq -> irq_mapper:receiver4_irq
wire [31:0] cpu_d_irq_irq; // irq_mapper:sender_irq -> cpu:d_irq
wire irq_mapper_receiver0_irq; // irq_synchronizer:sender_irq -> irq_mapper:receiver0_irq
wire [0:0] irq_synchronizer_receiver_irq; // key:irq -> irq_synchronizer:receiver_irq
wire irq_mapper_receiver1_irq; // irq_synchronizer_001:sender_irq -> irq_mapper:receiver1_irq
wire [0:0] irq_synchronizer_001_receiver_irq; // sw:irq -> irq_synchronizer_001:receiver_irq
wire irq_mapper_receiver2_irq; // irq_synchronizer_002:sender_irq -> irq_mapper:receiver2_irq
wire [0:0] irq_synchronizer_002_receiver_irq; // g_sensor_int:irq -> irq_synchronizer_002:receiver_irq
wire irq_mapper_receiver3_irq; // irq_synchronizer_003:sender_irq -> irq_mapper:receiver3_irq
wire [0:0] irq_synchronizer_003_receiver_irq; // epcs:irq -> irq_synchronizer_003:receiver_irq
wire irq_mapper_receiver5_irq; // irq_synchronizer_004:sender_irq -> irq_mapper:receiver5_irq
wire [0:0] irq_synchronizer_004_receiver_irq; // controller_interrupt_counter:irq -> irq_synchronizer_004:receiver_irq
wire irq_mapper_receiver6_irq; // irq_synchronizer_005:sender_irq -> irq_mapper:receiver6_irq
wire [0:0] irq_synchronizer_005_receiver_irq; // power_management_slave_0:error -> irq_synchronizer_005:receiver_irq
wire irq_mapper_receiver7_irq; // irq_synchronizer_006:sender_irq -> irq_mapper:receiver7_irq
wire [0:0] irq_synchronizer_006_receiver_irq; // RS232_0:irq -> irq_synchronizer_006:receiver_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [clock_crossing_io:m0_reset, g_sensor_int:reset_n, irq_synchronizer:receiver_reset, irq_synchronizer_001:receiver_reset, irq_synchronizer_002:receiver_reset, key:reset_n, led:reset_n, mm_interconnect_1:clock_crossing_io_m0_reset_reset_bridge_in_reset_reset, select_i2c_clk:reset_n, sw:reset_n, sysid:reset_n]
wire cpu_jtag_debug_module_reset_reset; // cpu:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1, rst_controller_003:reset_in1]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [RS232_0:reset, altpll_sys:reset, clock_crossing_io2:m0_reset, controller_interrupt_counter:reset_n, epcs:reset_n, gsensor_spi:reset_n, i2c_scl:reset_n, i2c_sda:reset_n, irq_synchronizer_003:receiver_reset, irq_synchronizer_004:receiver_reset, irq_synchronizer_005:receiver_reset, irq_synchronizer_006:receiver_reset, mm_interconnect_0:altpll_sys_inclk_interface_reset_reset_bridge_in_reset_reset, mm_interconnect_2:clock_crossing_io2_m0_reset_reset_bridge_in_reset_reset, motor_controller_0:reset, power_management_slave_0:reset, rst_translator:in_reset]
wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [epcs:reset_req, rst_translator:reset_req_in]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [clock_crossing_io2:s0_reset, clock_crossing_io:s0_reset, cpu:reset_n, irq_mapper:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, irq_synchronizer_002:sender_reset, irq_synchronizer_003:sender_reset, irq_synchronizer_004:sender_reset, irq_synchronizer_005:sender_reset, irq_synchronizer_006:sender_reset, jtag_uart:rst_n, mm_interconnect_0:cpu_reset_n_reset_bridge_in_reset_reset, rst_translator_001:in_reset, sdram:reset_n]
wire rst_controller_002_reset_out_reset_req; // rst_controller_002:reset_req -> [cpu:reset_req, rst_translator_001:reset_req_in]
wire rst_controller_003_reset_out_reset; // rst_controller_003:reset_out -> [imu_controller_0:spi_reset, mm_interconnect_0:imu_controller_0_reset_sink_reset_bridge_in_reset_reset]
DE0_Nano_SOPC_key key (
.clk (altpll_io), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_key_s1_address), // s1.address
.write_n (~mm_interconnect_1_key_s1_write), // .write_n
.writedata (mm_interconnect_1_key_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_key_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_key_s1_readdata), // .readdata
.in_port (in_port_to_the_key), // external_connection.export
.irq (irq_synchronizer_receiver_irq) // irq.irq
);
DE0_Nano_SOPC_sw sw (
.clk (altpll_io), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_sw_s1_address), // s1.address
.write_n (~mm_interconnect_1_sw_s1_write), // .write_n
.writedata (mm_interconnect_1_sw_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_sw_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_sw_s1_readdata), // .readdata
.in_port (in_port_to_the_sw), // external_connection.export
.irq (irq_synchronizer_001_receiver_irq) // irq.irq
);
DE0_Nano_SOPC_led led (
.clk (altpll_io), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_led_s1_address), // s1.address
.write_n (~mm_interconnect_1_led_s1_write), // .write_n
.writedata (mm_interconnect_1_led_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_led_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_led_s1_readdata), // .readdata
.out_port (out_port_from_the_led) // external_connection.export
);
DE0_Nano_SOPC_i2c_scl i2c_scl (
.clk (clk_50), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_2_i2c_scl_s1_address), // s1.address
.write_n (~mm_interconnect_2_i2c_scl_s1_write), // .write_n
.writedata (mm_interconnect_2_i2c_scl_s1_writedata), // .writedata
.chipselect (mm_interconnect_2_i2c_scl_s1_chipselect), // .chipselect
.readdata (mm_interconnect_2_i2c_scl_s1_readdata), // .readdata
.out_port (out_port_from_the_i2c_scl) // external_connection.export
);
DE0_Nano_SOPC_i2c_sda i2c_sda (
.clk (clk_50), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_2_i2c_sda_s1_address), // s1.address
.write_n (~mm_interconnect_2_i2c_sda_s1_write), // .write_n
.writedata (mm_interconnect_2_i2c_sda_s1_writedata), // .writedata
.chipselect (mm_interconnect_2_i2c_sda_s1_chipselect), // .chipselect
.readdata (mm_interconnect_2_i2c_sda_s1_readdata), // .readdata
.bidir_port (bidir_port_to_and_from_the_i2c_sda) // external_connection.export
);
DE0_Nano_SOPC_sdram sdram (
.clk (altpll_sys), // clk.clk
.reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.zs_addr (zs_addr_from_the_sdram), // wire.export
.zs_ba (zs_ba_from_the_sdram), // .export
.zs_cas_n (zs_cas_n_from_the_sdram), // .export
.zs_cke (zs_cke_from_the_sdram), // .export
.zs_cs_n (zs_cs_n_from_the_sdram), // .export
.zs_dq (zs_dq_to_and_from_the_sdram), // .export
.zs_dqm (zs_dqm_from_the_sdram), // .export
.zs_ras_n (zs_ras_n_from_the_sdram), // .export
.zs_we_n (zs_we_n_from_the_sdram) // .export
);
DE0_Nano_SOPC_altpll_sys altpll_sys_inst (
.clk (clk_50), // inclk_interface.clk
.reset (rst_controller_001_reset_out_reset), // inclk_interface_reset.reset
.read (mm_interconnect_0_altpll_sys_pll_slave_read), // pll_slave.read
.write (mm_interconnect_0_altpll_sys_pll_slave_write), // .write
.address (mm_interconnect_0_altpll_sys_pll_slave_address), // .address
.readdata (mm_interconnect_0_altpll_sys_pll_slave_readdata), // .readdata
.writedata (mm_interconnect_0_altpll_sys_pll_slave_writedata), // .writedata
.c0 (altpll_sys), // c0.clk
.c1 (altpll_sdram), // c1.clk
.c2 (altpll_io), // c2.clk
.c3 (altpll_sys_c3_out), // c3.clk
.c4 (altpll_adc), // c4.clk
.locked (locked_from_the_altpll_sys), // locked_conduit.export
.phasedone (phasedone_from_the_altpll_sys) // phasedone_conduit.export
);
DE0_Nano_SOPC_g_sensor_int g_sensor_int (
.clk (altpll_io), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_g_sensor_int_s1_address), // s1.address
.write_n (~mm_interconnect_1_g_sensor_int_s1_write), // .write_n
.writedata (mm_interconnect_1_g_sensor_int_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_g_sensor_int_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_g_sensor_int_s1_readdata), // .readdata
.in_port (in_port_to_the_g_sensor_int), // external_connection.export
.irq (irq_synchronizer_002_receiver_irq) // irq.irq
);
DE0_Nano_SOPC_epcs epcs (
.clk (clk_50), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.address (mm_interconnect_2_epcs_epcs_control_port_address), // epcs_control_port.address
.chipselect (mm_interconnect_2_epcs_epcs_control_port_chipselect), // .chipselect
.dataavailable (), // .dataavailable
.endofpacket (), // .endofpacket
.read_n (~mm_interconnect_2_epcs_epcs_control_port_read), // .read_n
.readdata (mm_interconnect_2_epcs_epcs_control_port_readdata), // .readdata
.readyfordata (), // .readyfordata
.write_n (~mm_interconnect_2_epcs_epcs_control_port_write), // .write_n
.writedata (mm_interconnect_2_epcs_epcs_control_port_writedata), // .writedata
.irq (irq_synchronizer_003_receiver_irq), // irq.irq
.dclk (dclk_from_the_epcs), // external.export
.sce (sce_from_the_epcs), // .export
.sdo (sdo_from_the_epcs), // .export
.data0 (data0_to_the_epcs) // .export
);
DE0_Nano_SOPC_jtag_uart jtag_uart (
.clk (altpll_sys), // clk.clk
.rst_n (~rst_controller_002_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver4_irq) // irq.irq
);
TERASIC_SPI_3WIRE gsensor_spi (
.clk (clk_50), // clock_reset.clk
.reset_n (~rst_controller_001_reset_out_reset), // clock_reset_reset.reset_n
.s_chipselect (mm_interconnect_2_gsensor_spi_slave_chipselect), // slave.chipselect
.s_address (mm_interconnect_2_gsensor_spi_slave_address), // .address
.s_write (mm_interconnect_2_gsensor_spi_slave_write), // .write
.s_writedata (mm_interconnect_2_gsensor_spi_slave_writedata), // .writedata
.s_read (mm_interconnect_2_gsensor_spi_slave_read), // .read
.s_readdata (mm_interconnect_2_gsensor_spi_slave_readdata), // .readdata
.SPI_SDIO (SPI_SDIO_to_and_from_the_gsensor_spi), // conduit_end.export
.SPI_SCLK (SPI_SCLK_from_the_gsensor_spi), // .export
.SPI_CS_n (SPI_CS_n_from_the_gsensor_spi) // .export
);
DE0_Nano_SOPC_select_i2c_clk select_i2c_clk (
.clk (altpll_io), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_select_i2c_clk_s1_address), // s1.address
.write_n (~mm_interconnect_1_select_i2c_clk_s1_write), // .write_n
.writedata (mm_interconnect_1_select_i2c_clk_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_select_i2c_clk_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_select_i2c_clk_s1_readdata), // .readdata
.out_port (out_port_from_the_select_i2c_clk) // external_connection.export
);
slave_controller motor_controller_0 (
.clk (clk_50), // clock.clk
.chipselect (mm_interconnect_0_motor_controller_0_avalon_slave_0_chipselect), // avalon_slave_0.chipselect
.write (mm_interconnect_0_motor_controller_0_avalon_slave_0_write), // .write
.addr (mm_interconnect_0_motor_controller_0_avalon_slave_0_address), // .address
.writedata (mm_interconnect_0_motor_controller_0_avalon_slave_0_writedata), // .writedata
.GPIO_out (GPIO_out_from_the_motor_controller_0), // conduit_end.export
.reset (rst_controller_001_reset_out_reset) // reset.reset
);
DE0_Nano_SOPC_controller_interrupt_counter controller_interrupt_counter (
.clk (clk_50), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_controller_interrupt_counter_s1_address), // s1.address
.writedata (mm_interconnect_0_controller_interrupt_counter_s1_writedata), // .writedata
.readdata (mm_interconnect_0_controller_interrupt_counter_s1_readdata), // .readdata
.chipselect (mm_interconnect_0_controller_interrupt_counter_s1_chipselect), // .chipselect
.write_n (~mm_interconnect_0_controller_interrupt_counter_s1_write), // .write_n
.irq (irq_synchronizer_004_receiver_irq) // irq.irq
);
power_management_slave power_management_slave_0 (
.chipselect (mm_interconnect_0_power_management_slave_0_avalon_slave_0_chipselect), // avalon_slave_0.chipselect
.write (mm_interconnect_0_power_management_slave_0_avalon_slave_0_write), // .write
.read (mm_interconnect_0_power_management_slave_0_avalon_slave_0_read), // .read
.writedata (mm_interconnect_0_power_management_slave_0_avalon_slave_0_writedata), // .writedata
.readdata (mm_interconnect_0_power_management_slave_0_avalon_slave_0_readdata), // .readdata
.clk (clk_50), // clock.clk
.kill_sw (kill_sw_from_the_power_management_slave_0), // conduit_end.export
.mux (mux_from_the_power_management_slave_0), // .export
.data (data_to_the_power_management_slave_0), // .export
.error (irq_synchronizer_005_receiver_irq), // interrupt_sender.irq
.reset (rst_controller_001_reset_out_reset) // reset.reset
);
imu_controller imu_controller_0 (
.spi_clk (altpll_adc), // clock.clk
.chipselect (mm_interconnect_0_imu_controller_0_avalon_slave_0_chipselect), // avalon_slave_0.chipselect
.addr (mm_interconnect_0_imu_controller_0_avalon_slave_0_address), // .address
.read (mm_interconnect_0_imu_controller_0_avalon_slave_0_read), // .read
.readdata (mm_interconnect_0_imu_controller_0_avalon_slave_0_readdata), // .readdata
.sys_clk (sys_clk_to_the_imu_controller_0), // conduit_end.export
.ADC_SDAT (ADC_SDAT_to_the_imu_controller_0), // .export
.ADC_CS_N (ADC_CS_N_from_the_imu_controller_0), // .export
.ADC_SADDR (ADC_SADDR_from_the_imu_controller_0), // .export
.ADC_SCLK (ADC_SCLK_from_the_imu_controller_0), // .export
.spi_reset (rst_controller_003_reset_out_reset) // reset_sink.reset
);
Altera_UP_Avalon_RS232 rs232_0 (
.clk (clk_50), // clock.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.address (mm_interconnect_0_rs232_0_avalon_slave_0_address), // avalon_slave_0.address
.chipselect (mm_interconnect_0_rs232_0_avalon_slave_0_chipselect), // .chipselect
.byteenable (mm_interconnect_0_rs232_0_avalon_slave_0_byteenable), // .byteenable
.read (mm_interconnect_0_rs232_0_avalon_slave_0_read), // .read
.write (mm_interconnect_0_rs232_0_avalon_slave_0_write), // .write
.writedata (mm_interconnect_0_rs232_0_avalon_slave_0_writedata), // .writedata
.readdata (mm_interconnect_0_rs232_0_avalon_slave_0_readdata), // .readdata
.UART_RXD (UART_RXD_to_the_RS232_0), // conduit_end.export
.UART_TXD (UART_TXD_from_the_RS232_0), // conduit_end_1.export
.irq (irq_synchronizer_006_receiver_irq) // interrupt_sender.irq
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.ADDRESS_WIDTH (7),
.BURSTCOUNT_WIDTH (1),
.COMMAND_FIFO_DEPTH (16),
.RESPONSE_FIFO_DEPTH (32),
.MASTER_SYNC_DEPTH (3),
.SLAVE_SYNC_DEPTH (3)
) clock_crossing_io (
.m0_clk (altpll_io), // m0_clk.clk
.m0_reset (rst_controller_reset_out_reset), // m0_reset.reset
.s0_clk (altpll_sys), // s0_clk.clk
.s0_reset (rst_controller_002_reset_out_reset), // s0_reset.reset
.s0_waitrequest (mm_interconnect_0_clock_crossing_io_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_clock_crossing_io_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_clock_crossing_io_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_clock_crossing_io_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_clock_crossing_io_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_clock_crossing_io_s0_address), // .address
.s0_write (mm_interconnect_0_clock_crossing_io_s0_write), // .write
.s0_read (mm_interconnect_0_clock_crossing_io_s0_read), // .read
.s0_byteenable (mm_interconnect_0_clock_crossing_io_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_clock_crossing_io_s0_debugaccess), // .debugaccess
.m0_waitrequest (clock_crossing_io_m0_waitrequest), // m0.waitrequest
.m0_readdata (clock_crossing_io_m0_readdata), // .readdata
.m0_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid
.m0_burstcount (clock_crossing_io_m0_burstcount), // .burstcount
.m0_writedata (clock_crossing_io_m0_writedata), // .writedata
.m0_address (clock_crossing_io_m0_address), // .address
.m0_write (clock_crossing_io_m0_write), // .write
.m0_read (clock_crossing_io_m0_read), // .read
.m0_byteenable (clock_crossing_io_m0_byteenable), // .byteenable
.m0_debugaccess (clock_crossing_io_m0_debugaccess) // .debugaccess
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.ADDRESS_WIDTH (12),
.BURSTCOUNT_WIDTH (1),
.COMMAND_FIFO_DEPTH (16),
.RESPONSE_FIFO_DEPTH (64),
.MASTER_SYNC_DEPTH (3),
.SLAVE_SYNC_DEPTH (3)
) clock_crossing_io2 (
.m0_clk (clk_50), // m0_clk.clk
.m0_reset (rst_controller_001_reset_out_reset), // m0_reset.reset
.s0_clk (altpll_sys), // s0_clk.clk
.s0_reset (rst_controller_002_reset_out_reset), // s0_reset.reset
.s0_waitrequest (mm_interconnect_0_clock_crossing_io2_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_clock_crossing_io2_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_clock_crossing_io2_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_clock_crossing_io2_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_clock_crossing_io2_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_clock_crossing_io2_s0_address), // .address
.s0_write (mm_interconnect_0_clock_crossing_io2_s0_write), // .write
.s0_read (mm_interconnect_0_clock_crossing_io2_s0_read), // .read
.s0_byteenable (mm_interconnect_0_clock_crossing_io2_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_clock_crossing_io2_s0_debugaccess), // .debugaccess
.m0_waitrequest (clock_crossing_io2_m0_waitrequest), // m0.waitrequest
.m0_readdata (clock_crossing_io2_m0_readdata), // .readdata
.m0_readdatavalid (clock_crossing_io2_m0_readdatavalid), // .readdatavalid
.m0_burstcount (clock_crossing_io2_m0_burstcount), // .burstcount
.m0_writedata (clock_crossing_io2_m0_writedata), // .writedata
.m0_address (clock_crossing_io2_m0_address), // .address
.m0_write (clock_crossing_io2_m0_write), // .write
.m0_read (clock_crossing_io2_m0_read), // .read
.m0_byteenable (clock_crossing_io2_m0_byteenable), // .byteenable
.m0_debugaccess (clock_crossing_io2_m0_debugaccess) // .debugaccess
);
DE0_Nano_SOPC_cpu cpu (
.clk (altpll_sys), // clk.clk
.reset_n (~rst_controller_002_reset_out_reset), // reset_n.reset_n
.reset_req (rst_controller_002_reset_out_reset_req), // .reset_req
.d_address (cpu_data_master_address), // data_master.address
.d_byteenable (cpu_data_master_byteenable), // .byteenable
.d_read (cpu_data_master_read), // .read
.d_readdata (cpu_data_master_readdata), // .readdata
.d_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.d_write (cpu_data_master_write), // .write
.d_writedata (cpu_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess
.i_address (cpu_instruction_master_address), // instruction_master.address
.i_read (cpu_instruction_master_read), // .read
.i_readdata (cpu_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (cpu_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
.jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable
.jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess
.jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read
.jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata
.jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest
.jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write
.jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
DE0_Nano_SOPC_sysid sysid (
.clock (altpll_io), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_1_sysid_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_1_sysid_control_slave_address) // .address
);
DE0_Nano_SOPC_mm_interconnect_0 mm_interconnect_0 (
.altpll_sys_c0_clk (altpll_sys), // altpll_sys_c0.clk
.altpll_sys_c4_clk (altpll_adc), // altpll_sys_c4.clk
.clk_50_clk_clk (clk_50), // clk_50_clk.clk
.altpll_sys_inclk_interface_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // altpll_sys_inclk_interface_reset_reset_bridge_in_reset.reset
.cpu_reset_n_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // cpu_reset_n_reset_bridge_in_reset.reset
.imu_controller_0_reset_sink_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset), // imu_controller_0_reset_sink_reset_bridge_in_reset.reset
.cpu_data_master_address (cpu_data_master_address), // cpu_data_master.address
.cpu_data_master_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.cpu_data_master_byteenable (cpu_data_master_byteenable), // .byteenable
.cpu_data_master_read (cpu_data_master_read), // .read
.cpu_data_master_readdata (cpu_data_master_readdata), // .readdata
.cpu_data_master_write (cpu_data_master_write), // .write
.cpu_data_master_writedata (cpu_data_master_writedata), // .writedata
.cpu_data_master_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.cpu_instruction_master_address (cpu_instruction_master_address), // cpu_instruction_master.address
.cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.cpu_instruction_master_read (cpu_instruction_master_read), // .read
.cpu_instruction_master_readdata (cpu_instruction_master_readdata), // .readdata
.altpll_sys_pll_slave_address (mm_interconnect_0_altpll_sys_pll_slave_address), // altpll_sys_pll_slave.address
.altpll_sys_pll_slave_write (mm_interconnect_0_altpll_sys_pll_slave_write), // .write
.altpll_sys_pll_slave_read (mm_interconnect_0_altpll_sys_pll_slave_read), // .read
.altpll_sys_pll_slave_readdata (mm_interconnect_0_altpll_sys_pll_slave_readdata), // .readdata
.altpll_sys_pll_slave_writedata (mm_interconnect_0_altpll_sys_pll_slave_writedata), // .writedata
.clock_crossing_io_s0_address (mm_interconnect_0_clock_crossing_io_s0_address), // clock_crossing_io_s0.address
.clock_crossing_io_s0_write (mm_interconnect_0_clock_crossing_io_s0_write), // .write
.clock_crossing_io_s0_read (mm_interconnect_0_clock_crossing_io_s0_read), // .read
.clock_crossing_io_s0_readdata (mm_interconnect_0_clock_crossing_io_s0_readdata), // .readdata
.clock_crossing_io_s0_writedata (mm_interconnect_0_clock_crossing_io_s0_writedata), // .writedata
.clock_crossing_io_s0_burstcount (mm_interconnect_0_clock_crossing_io_s0_burstcount), // .burstcount
.clock_crossing_io_s0_byteenable (mm_interconnect_0_clock_crossing_io_s0_byteenable), // .byteenable
.clock_crossing_io_s0_readdatavalid (mm_interconnect_0_clock_crossing_io_s0_readdatavalid), // .readdatavalid
.clock_crossing_io_s0_waitrequest (mm_interconnect_0_clock_crossing_io_s0_waitrequest), // .waitrequest
.clock_crossing_io_s0_debugaccess (mm_interconnect_0_clock_crossing_io_s0_debugaccess), // .debugaccess
.clock_crossing_io2_s0_address (mm_interconnect_0_clock_crossing_io2_s0_address), // clock_crossing_io2_s0.address
.clock_crossing_io2_s0_write (mm_interconnect_0_clock_crossing_io2_s0_write), // .write
.clock_crossing_io2_s0_read (mm_interconnect_0_clock_crossing_io2_s0_read), // .read
.clock_crossing_io2_s0_readdata (mm_interconnect_0_clock_crossing_io2_s0_readdata), // .readdata
.clock_crossing_io2_s0_writedata (mm_interconnect_0_clock_crossing_io2_s0_writedata), // .writedata
.clock_crossing_io2_s0_burstcount (mm_interconnect_0_clock_crossing_io2_s0_burstcount), // .burstcount
.clock_crossing_io2_s0_byteenable (mm_interconnect_0_clock_crossing_io2_s0_byteenable), // .byteenable
.clock_crossing_io2_s0_readdatavalid (mm_interconnect_0_clock_crossing_io2_s0_readdatavalid), // .readdatavalid
.clock_crossing_io2_s0_waitrequest (mm_interconnect_0_clock_crossing_io2_s0_waitrequest), // .waitrequest
.clock_crossing_io2_s0_debugaccess (mm_interconnect_0_clock_crossing_io2_s0_debugaccess), // .debugaccess
.controller_interrupt_counter_s1_address (mm_interconnect_0_controller_interrupt_counter_s1_address), // controller_interrupt_counter_s1.address
.controller_interrupt_counter_s1_write (mm_interconnect_0_controller_interrupt_counter_s1_write), // .write
.controller_interrupt_counter_s1_readdata (mm_interconnect_0_controller_interrupt_counter_s1_readdata), // .readdata
.controller_interrupt_counter_s1_writedata (mm_interconnect_0_controller_interrupt_counter_s1_writedata), // .writedata
.controller_interrupt_counter_s1_chipselect (mm_interconnect_0_controller_interrupt_counter_s1_chipselect), // .chipselect
.cpu_jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // cpu_jtag_debug_module.address
.cpu_jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write
.cpu_jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read
.cpu_jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata
.cpu_jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata
.cpu_jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable
.cpu_jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest
.cpu_jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess
.imu_controller_0_avalon_slave_0_address (mm_interconnect_0_imu_controller_0_avalon_slave_0_address), // imu_controller_0_avalon_slave_0.address
.imu_controller_0_avalon_slave_0_read (mm_interconnect_0_imu_controller_0_avalon_slave_0_read), // .read
.imu_controller_0_avalon_slave_0_readdata (mm_interconnect_0_imu_controller_0_avalon_slave_0_readdata), // .readdata
.imu_controller_0_avalon_slave_0_chipselect (mm_interconnect_0_imu_controller_0_avalon_slave_0_chipselect), // .chipselect
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.motor_controller_0_avalon_slave_0_address (mm_interconnect_0_motor_controller_0_avalon_slave_0_address), // motor_controller_0_avalon_slave_0.address
.motor_controller_0_avalon_slave_0_write (mm_interconnect_0_motor_controller_0_avalon_slave_0_write), // .write
.motor_controller_0_avalon_slave_0_writedata (mm_interconnect_0_motor_controller_0_avalon_slave_0_writedata), // .writedata
.motor_controller_0_avalon_slave_0_chipselect (mm_interconnect_0_motor_controller_0_avalon_slave_0_chipselect), // .chipselect
.power_management_slave_0_avalon_slave_0_write (mm_interconnect_0_power_management_slave_0_avalon_slave_0_write), // power_management_slave_0_avalon_slave_0.write
.power_management_slave_0_avalon_slave_0_read (mm_interconnect_0_power_management_slave_0_avalon_slave_0_read), // .read
.power_management_slave_0_avalon_slave_0_readdata (mm_interconnect_0_power_management_slave_0_avalon_slave_0_readdata), // .readdata
.power_management_slave_0_avalon_slave_0_writedata (mm_interconnect_0_power_management_slave_0_avalon_slave_0_writedata), // .writedata
.power_management_slave_0_avalon_slave_0_chipselect (mm_interconnect_0_power_management_slave_0_avalon_slave_0_chipselect), // .chipselect
.RS232_0_avalon_slave_0_address (mm_interconnect_0_rs232_0_avalon_slave_0_address), // RS232_0_avalon_slave_0.address
.RS232_0_avalon_slave_0_write (mm_interconnect_0_rs232_0_avalon_slave_0_write), // .write
.RS232_0_avalon_slave_0_read (mm_interconnect_0_rs232_0_avalon_slave_0_read), // .read
.RS232_0_avalon_slave_0_readdata (mm_interconnect_0_rs232_0_avalon_slave_0_readdata), // .readdata
.RS232_0_avalon_slave_0_writedata (mm_interconnect_0_rs232_0_avalon_slave_0_writedata), // .writedata
.RS232_0_avalon_slave_0_byteenable (mm_interconnect_0_rs232_0_avalon_slave_0_byteenable), // .byteenable
.RS232_0_avalon_slave_0_chipselect (mm_interconnect_0_rs232_0_avalon_slave_0_chipselect), // .chipselect
.sdram_s1_address (mm_interconnect_0_sdram_s1_address), // sdram_s1.address
.sdram_s1_write (mm_interconnect_0_sdram_s1_write), // .write
.sdram_s1_read (mm_interconnect_0_sdram_s1_read), // .read
.sdram_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata
.sdram_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata
.sdram_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable
.sdram_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.sdram_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.sdram_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect) // .chipselect
);
DE0_Nano_SOPC_mm_interconnect_1 mm_interconnect_1 (
.altpll_sys_c2_clk (altpll_io), // altpll_sys_c2.clk
.clock_crossing_io_m0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // clock_crossing_io_m0_reset_reset_bridge_in_reset.reset
.clock_crossing_io_m0_address (clock_crossing_io_m0_address), // clock_crossing_io_m0.address
.clock_crossing_io_m0_waitrequest (clock_crossing_io_m0_waitrequest), // .waitrequest
.clock_crossing_io_m0_burstcount (clock_crossing_io_m0_burstcount), // .burstcount
.clock_crossing_io_m0_byteenable (clock_crossing_io_m0_byteenable), // .byteenable
.clock_crossing_io_m0_read (clock_crossing_io_m0_read), // .read
.clock_crossing_io_m0_readdata (clock_crossing_io_m0_readdata), // .readdata
.clock_crossing_io_m0_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid
.clock_crossing_io_m0_write (clock_crossing_io_m0_write), // .write
.clock_crossing_io_m0_writedata (clock_crossing_io_m0_writedata), // .writedata
.clock_crossing_io_m0_debugaccess (clock_crossing_io_m0_debugaccess), // .debugaccess
.g_sensor_int_s1_address (mm_interconnect_1_g_sensor_int_s1_address), // g_sensor_int_s1.address
.g_sensor_int_s1_write (mm_interconnect_1_g_sensor_int_s1_write), // .write
.g_sensor_int_s1_readdata (mm_interconnect_1_g_sensor_int_s1_readdata), // .readdata
.g_sensor_int_s1_writedata (mm_interconnect_1_g_sensor_int_s1_writedata), // .writedata
.g_sensor_int_s1_chipselect (mm_interconnect_1_g_sensor_int_s1_chipselect), // .chipselect
.key_s1_address (mm_interconnect_1_key_s1_address), // key_s1.address
.key_s1_write (mm_interconnect_1_key_s1_write), // .write
.key_s1_readdata (mm_interconnect_1_key_s1_readdata), // .readdata
.key_s1_writedata (mm_interconnect_1_key_s1_writedata), // .writedata
.key_s1_chipselect (mm_interconnect_1_key_s1_chipselect), // .chipselect
.led_s1_address (mm_interconnect_1_led_s1_address), // led_s1.address
.led_s1_write (mm_interconnect_1_led_s1_write), // .write
.led_s1_readdata (mm_interconnect_1_led_s1_readdata), // .readdata
.led_s1_writedata (mm_interconnect_1_led_s1_writedata), // .writedata
.led_s1_chipselect (mm_interconnect_1_led_s1_chipselect), // .chipselect
.select_i2c_clk_s1_address (mm_interconnect_1_select_i2c_clk_s1_address), // select_i2c_clk_s1.address
.select_i2c_clk_s1_write (mm_interconnect_1_select_i2c_clk_s1_write), // .write
.select_i2c_clk_s1_readdata (mm_interconnect_1_select_i2c_clk_s1_readdata), // .readdata
.select_i2c_clk_s1_writedata (mm_interconnect_1_select_i2c_clk_s1_writedata), // .writedata
.select_i2c_clk_s1_chipselect (mm_interconnect_1_select_i2c_clk_s1_chipselect), // .chipselect
.sw_s1_address (mm_interconnect_1_sw_s1_address), // sw_s1.address
.sw_s1_write (mm_interconnect_1_sw_s1_write), // .write
.sw_s1_readdata (mm_interconnect_1_sw_s1_readdata), // .readdata
.sw_s1_writedata (mm_interconnect_1_sw_s1_writedata), // .writedata
.sw_s1_chipselect (mm_interconnect_1_sw_s1_chipselect), // .chipselect
.sysid_control_slave_address (mm_interconnect_1_sysid_control_slave_address), // sysid_control_slave.address
.sysid_control_slave_readdata (mm_interconnect_1_sysid_control_slave_readdata) // .readdata
);
DE0_Nano_SOPC_mm_interconnect_2 mm_interconnect_2 (
.clk_50_clk_clk (clk_50), // clk_50_clk.clk
.clock_crossing_io2_m0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // clock_crossing_io2_m0_reset_reset_bridge_in_reset.reset
.clock_crossing_io2_m0_address (clock_crossing_io2_m0_address), // clock_crossing_io2_m0.address
.clock_crossing_io2_m0_waitrequest (clock_crossing_io2_m0_waitrequest), // .waitrequest
.clock_crossing_io2_m0_burstcount (clock_crossing_io2_m0_burstcount), // .burstcount
.clock_crossing_io2_m0_byteenable (clock_crossing_io2_m0_byteenable), // .byteenable
.clock_crossing_io2_m0_read (clock_crossing_io2_m0_read), // .read
.clock_crossing_io2_m0_readdata (clock_crossing_io2_m0_readdata), // .readdata
.clock_crossing_io2_m0_readdatavalid (clock_crossing_io2_m0_readdatavalid), // .readdatavalid
.clock_crossing_io2_m0_write (clock_crossing_io2_m0_write), // .write
.clock_crossing_io2_m0_writedata (clock_crossing_io2_m0_writedata), // .writedata
.clock_crossing_io2_m0_debugaccess (clock_crossing_io2_m0_debugaccess), // .debugaccess
.epcs_epcs_control_port_address (mm_interconnect_2_epcs_epcs_control_port_address), // epcs_epcs_control_port.address
.epcs_epcs_control_port_write (mm_interconnect_2_epcs_epcs_control_port_write), // .write
.epcs_epcs_control_port_read (mm_interconnect_2_epcs_epcs_control_port_read), // .read
.epcs_epcs_control_port_readdata (mm_interconnect_2_epcs_epcs_control_port_readdata), // .readdata
.epcs_epcs_control_port_writedata (mm_interconnect_2_epcs_epcs_control_port_writedata), // .writedata
.epcs_epcs_control_port_chipselect (mm_interconnect_2_epcs_epcs_control_port_chipselect), // .chipselect
.gsensor_spi_slave_address (mm_interconnect_2_gsensor_spi_slave_address), // gsensor_spi_slave.address
.gsensor_spi_slave_write (mm_interconnect_2_gsensor_spi_slave_write), // .write
.gsensor_spi_slave_read (mm_interconnect_2_gsensor_spi_slave_read), // .read
.gsensor_spi_slave_readdata (mm_interconnect_2_gsensor_spi_slave_readdata), // .readdata
.gsensor_spi_slave_writedata (mm_interconnect_2_gsensor_spi_slave_writedata), // .writedata
.gsensor_spi_slave_chipselect (mm_interconnect_2_gsensor_spi_slave_chipselect), // .chipselect
.i2c_scl_s1_address (mm_interconnect_2_i2c_scl_s1_address), // i2c_scl_s1.address
.i2c_scl_s1_write (mm_interconnect_2_i2c_scl_s1_write), // .write
.i2c_scl_s1_readdata (mm_interconnect_2_i2c_scl_s1_readdata), // .readdata
.i2c_scl_s1_writedata (mm_interconnect_2_i2c_scl_s1_writedata), // .writedata
.i2c_scl_s1_chipselect (mm_interconnect_2_i2c_scl_s1_chipselect), // .chipselect
.i2c_sda_s1_address (mm_interconnect_2_i2c_sda_s1_address), // i2c_sda_s1.address
.i2c_sda_s1_write (mm_interconnect_2_i2c_sda_s1_write), // .write
.i2c_sda_s1_readdata (mm_interconnect_2_i2c_sda_s1_readdata), // .readdata
.i2c_sda_s1_writedata (mm_interconnect_2_i2c_sda_s1_writedata), // .writedata
.i2c_sda_s1_chipselect (mm_interconnect_2_i2c_sda_s1_chipselect) // .chipselect
);
DE0_Nano_SOPC_irq_mapper irq_mapper (
.clk (altpll_sys), // clk.clk
.reset (rst_controller_002_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.receiver3_irq (irq_mapper_receiver3_irq), // receiver3.irq
.receiver4_irq (irq_mapper_receiver4_irq), // receiver4.irq
.receiver5_irq (irq_mapper_receiver5_irq), // receiver5.irq
.receiver6_irq (irq_mapper_receiver6_irq), // receiver6.irq
.receiver7_irq (irq_mapper_receiver7_irq), // receiver7.irq
.sender_irq (cpu_d_irq_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer (
.receiver_clk (altpll_io), // receiver_clk.clk
.sender_clk (altpll_sys), // sender_clk.clk
.receiver_reset (rst_controller_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_002_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver0_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_001 (
.receiver_clk (altpll_io), // receiver_clk.clk
.sender_clk (altpll_sys), // sender_clk.clk
.receiver_reset (rst_controller_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_002_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_001_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver1_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_002 (
.receiver_clk (altpll_io), // receiver_clk.clk
.sender_clk (altpll_sys), // sender_clk.clk
.receiver_reset (rst_controller_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_002_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_002_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver2_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_003 (
.receiver_clk (clk_50), // receiver_clk.clk
.sender_clk (altpll_sys), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_002_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_003_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver3_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_004 (
.receiver_clk (clk_50), // receiver_clk.clk
.sender_clk (altpll_sys), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_002_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_004_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver5_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_005 (
.receiver_clk (clk_50), // receiver_clk.clk
.sender_clk (altpll_sys), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_002_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_005_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver6_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer_006 (
.receiver_clk (clk_50), // receiver_clk.clk
.sender_clk (altpll_sys), // sender_clk.clk
.receiver_reset (rst_controller_001_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_002_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_006_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver7_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (altpll_io), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clk_50), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (altpll_sys), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_002_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_003 (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (altpll_adc), // clk.clk
.reset_out (rst_controller_003_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
`ifndef INCLUDE_PARAMS
`include "params.v"
`endif
`ifndef INCLUDE_MEM_MOD
`include "DMem.v"
`endif
`ifndef INCLUDE_ISA
`include "ISA.v"
`endif
module MEM (
input wire clk, // Clock
input wire rst_n, // reset
// pipeline inputs
input wire [`WIDTH - 1:0] IR_in,
input wire [`WIDTH - 3:0] PC_in,
input wire [`WIDTH - 1:0] Z_in,
input wire [`WIDTH - 1:0] Addr,
// pipeline outputs
output wire [`WIDTH - 1:0] IR_out,
output wire [`WIDTH - 3:0] PC_out,
output wire [`WIDTH - 1:0] Z_out
// mem trace
`ifdef TRACE_MEM
,input wire Print
`endif
);
wire [5:0] OpCode;
assign OpCode = IR_in[31:26];
reg [`WIDTH - 1:0] addr;
wire [`WIDTH - 1:0] data;
reg [`WIDTH - 1:0] data_reg;
reg data_v;
reg wr;
reg rd;
wire rd_st;
reg [1:0] mode;
reg [`WIDTH - 1:0] Z_reg;
assign data = (data_v == 1)? data_reg : 32'hZ;
assign PC_out = PC_in;
assign IR_out = IR_in;
assign Z_out = (rd_st == 1)? data : Z_in;
DMem DMem(.rst_n(rst_n), .add(addr), .data(data), .wr(wr), .rd(rd), .rd_st(rd_st), .mode(mode)
`ifdef TRACE_MEM
, .Print(Print)
`endif
);
always @(IR_in or PC_in) begin
rd = 0;
wr = 0;
data_v = 0;
case(OpCode)
`LW: begin
mode = 0;
ReadMem();
end
`LH: begin
mode = 1;
ReadMem();
end
`LD: begin
mode = 2;
ReadMem();
end
`SW:begin
mode = 0;
WriteMem();
end
`SH: begin
mode = 1;
WriteMem();
end
`SD: begin
mode = 2;
WriteMem();
end
endcase
end
// always @(posedge rd_st) begin
// Z_reg = data;
// end
task ReadMem();
begin
addr = Addr;
rd = 1;
end
endtask
task WriteMem();
begin
data_reg = Z_in;
data_v = 1;
addr = Addr;
wr = 1;
end
endtask
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__NOR2_PP_SYMBOL_V
/**
* nor2: 2-input NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_PP_SYMBOL_V
|
//******************************************************************************
// *
// Copyright (C) 2010 Regents of the University of California. *
// *
// The information contained herein is the exclusive property of the VCL *
// group but may be used and/or modified for non-comercial purposes if the *
// author is acknowledged. For all other uses, permission must be attained *
// by the VLSI Computation Lab. *
// *
// This work has been developed by members of the VLSI Computation Lab *
// (VCL) in the Department of Electrical and Computer Engineering at *
// the University of California at Davis. Contact: [email protected] *
//******************************************************************************
//
// tb.vt
//
// Testbench for FIFO
//
// This module will rigorously test the FIFO module.
//
// Written by Aaron Stillmaker
// 8/13/10
// Define FIFO Address width minus 1 and Data word width minus 1
`define ADDR_WIDTH_M1 6
`define DATA_WIDTH_M1 15
`timescale 10ps/1ps
`define IN_COUNT 200
module tb();
reg clkP, // write clock
clkC, // read clock
reset, // reset
wr_valid,
nap,
rd_request,
last_request,
request,
emp,
last_empty,
wr_en;
reg [`DATA_WIDTH_M1:0] data_in,
last_data;
reg [1:0] delay_sel; // delay select
reg [2:0] wr_sync_cntrl, // write sysch control
rd_sync_cntrl; // read sync control
reg [`ADDR_WIDTH_M1:0] reserve; // reserve
wire wr_request,
empty;
wire [`DATA_WIDTH_M1:0] data_out;
integer fh_output, // output file handle
r, // random seed
iterationP, // count of itteration for clock for producer
iterationC, // count of itteration for clock for consumer
speedP, // count of speed for clock for producer
speedC, // count of speed for clock for consumer
symcount, // count of how many runs are done
iterationRD,
rd_interval,
iterationWR,
wr_interval;
// Initialization for data capture
initial begin
//$recordfile("tb");
//$recordvars(tb);
fh_output = $fopen("output.m");
r = 123; // initialize random seed
end
// Initialize testbench
initial begin
clkP=0;
clkC=0;
reset = 1;
rd_request = 0;
data_in=7'b0000000;
symcount = 1;
wr_valid = 0;
iterationRD = 0;
rd_interval = 10;
iterationWR = 0;
wr_interval = 10;
wr_en = 0;
// Delay Select, set how much delay you want in the FIFO
delay_sel = 2'b00;
// Write and Read number of registers in the asynchronous communication beween the two frequencies
wr_sync_cntrl = 3'b000;
rd_sync_cntrl = 3'b000;
// Reserve space constant
reserve = 7'b0000000;
// No Increment Read pointer signal
nap = 0;
// Initialize the speed and interation numbers
speedP = 500;
speedC = 400;
iterationP = 0;
iterationC = 0;
#50;
clkP=1;
clkC=1;
#50;
reset = 0;
end
// Producer Clock
always begin
if (iterationP == speedP/2) begin
#1
clkP = ~clkP; // alternate the clock
iterationP = iterationP + 1;
end
else if (iterationP == speedP) begin
#1
clkP = ~clkP; // alternate the clock
iterationP = 0; // reset the counter
speedP = 2 * (500 - ($random(r) % 250)); // make a new random number from 500-1500
end else begin
#1
iterationP = iterationP + 1;
end
end
// Consumer Clock
always begin
if (iterationC == speedC/2) begin
#1
clkC = ~clkC; // alternate the clock
iterationC = iterationC + 1;
end
else if (iterationC == speedC) begin
#1
clkC = ~clkC; // alternate the clock
iterationC = 0; // reset the counter
speedC = 2 * (500 - ($random(r) % 250)); // make a new random number from 500-1500
if (speedC == (speedP - iterationP)) begin
speedC = speedC +4; //make sure the clock pulses do not line up to stop a verilog error
end
end else begin
#1
iterationC = iterationC + 1;
end
end
// Create WR and RD enable signals
always @(posedge clkC) begin
if (iterationRD == rd_interval) begin
#1
rd_request = ~rd_request; // alternate the rd_request
iterationRD = 0; // reset the counter
rd_interval = (1001 - ($random(r) % 1000)); // make a new random number from 1-2001
end else begin
#1
iterationRD = iterationRD + 1;
end
end
always @(posedge clkP) begin
if (iterationWR == wr_interval) begin
#1
wr_en = ~wr_en; // alternate the wr_en
iterationWR = 0; // reset the counter
wr_interval = (1001 - ($random(r) % 1000)); // make a new random number from 1-2001
end else begin
#1
iterationWR = iterationWR + 1;
end
end
// Generate Producer Input
always @(posedge clkP) begin
if (wr_request == 1 & wr_en == 1) begin
// Inc when the FIFO is ready for a write and the pos edge of the clock
wr_valid = 1;
data_in = data_in + 1; // The data
//$fwrite(fh_output,"In = %h;\n", data_in);
#2
wr_valid = 0; // Data is no longer valid
end
end
// Save Output from Consumer
always @(posedge clkC) begin
// Save output whenever the FIFO is ready to output and the
//positive edge of the clock
if (last_request == 1 & last_empty != 1) begin
last_request = rd_request;
last_empty = empty;
#1
//$fwrite(fh_output, "Out = %h;\n", data_out);
if (last_data + 1 != data_out) begin
$display("ERROR last_data = %h while data_out= %h!!!!!!rd_request = %b, last_request = %b, and request = %b\n", last_data, data_out, rd_request, last_request, request);
$fwrite(fh_output, "ERROR last_data = %h while data_out= %h!!!!!!rd_request = %b, last_request = %b, and request = %b\n", last_data, data_out, rd_request, last_request, request);
end
last_data = data_out;
end
//symcount = symcount + 1;
if (symcount == 0 ) begin
$display("FINISHED!!!!");
$finish;
$fclose(fh_output);
end
end
// Submodule
FIFO FIFO (
.reserve (reserve),
.wr_sync_cntrl (wr_sync_cntrl),
.clk_wr (clkP),
.data_in (data_in),
.wr_valid (wr_valid),
.delay_sel (delay_sel),
.wr_request (wr_request),
.async_empty (async_empty),
.reset (reset),
.clk_rd (clkC),
.data_out (data_out),
.empty (empty),
.rd_request (rd_request),
.async_full (async_full),
.rd_sync_cntrl (rd_sync_cntrl),
.nap (nap),
.fifo_util (fifo_util)
);
endmodule
|
// file: relojes.v
//
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1 12.000 0.000 50.0 360.161 213.839
// CLK_OUT2 6.000 0.000 50.0 411.982 213.839
// CLK_OUT3 8.000 0.000 50.0 389.784 213.839
//
//----------------------------------------------------------------------------
// Input Clock Input Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// primary 50 0.010
`timescale 1ps/1ps
`default_nettype none
(* CORE_GENERATION_INFO = "relojes,clk_wiz_v1_8,{component_name=relojes,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module relojes
(// Clock in ports
input wire CLK_IN1,
// Clock out ports
output wire CLK_OUT1,
output wire CLK_OUT2,
output wire CLK_OUT3,
output wire CLK_OUT4
);
wire clkin1, clkout0, clkout1, clkout2, clkout3;
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire locked_unused;
wire clkfbout;
wire clkout4_unused;
wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (12),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (25),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (50),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (100),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DIVIDE (75),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (20.0),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2),
.CLKOUT3 (clkout3),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.LOCKED (locked_unused),
.RST (1'b0),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN (clkin1));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkout2));
BUFG clkout4_buf
(.O (CLK_OUT4),
.I (clkout3));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: Sam Skalicky
//
// Create Date: 07/16/2015 10:05:03 AM
// Design Name: Accelerator Trace Monitor
// Module Name: Event_Pulse
// Project Name: SDSoC Trace Framework
// Target Devices: Zynq
// Tool Versions: 2015.2
// Description: This module produces various pulses for different events of the
// input signal: rising or falling edge or both edges.
//
// Dependencies: None
//
// Revision: 1.0
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Event_Pulse(
input in, //Input signal to monitor
input clk, //clock to sample the input signal at
output rising_edge, //Output pulse if a rising edge is found
output falling_edge, //Output pulse if a falling edge is found
output both_edges //Output pulse if any edge is found
);
reg [1:0] reg_i = 2'b0; //two bit register for identifying edges
assign rising_edge = (~reg_i[1]) & reg_i[0]; //rising edge
assign falling_edge = reg_i[1] &(~reg_i[0]); //falling edge
assign both_edges = ((~reg_i[1]) & reg_i[0]) | (reg_i[1] & (~reg_i[0])); //both edges
//Shift in the signal every clock cycle
always @(posedge clk)
begin
reg_i[0] <= in;
reg_i[1] <= reg_i[0];
end
endmodule
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [15:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output srtc_enable,
output use_bsx,
output bsx_tristate,
input [14:0] bsx_regs,
output dspx_enable,
output dspx_dp_enable,
output dspx_a0,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output branch3_enable
);
/* feature bits. see src/fpga_spi.c for mapping */
parameter [2:0]
FEAT_DSPX = 0,
FEAT_ST0010 = 1,
FEAT_SRTC = 2,
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_2100 = 6
;
wire [23:0] SRAM_SNES_ADDR;
/* currently supported mappers:
Index Mapper
000 HiROM
001 LoROM
010 ExHiROM (48-64Mbit)
011 BS-X
100 ExLoROM (StarOCean and SFA2)
110 brainfuck interleaved 96MBit Star Ocean =)
111 menu (ROM in upper SRAM)
*/
// active high to select ROM in banks 00-3f,80-bf:8000-ffff and 40-7d,c0-ff:0000-ffff
// (decoded by SNES)
assign IS_ROM = ~SNES_ROMSEL;
// select backup RAM when
// ST0010 chip is present, SRAM is mapped to
assign IS_SAVERAM = SAVERAM_MASK[0]&(featurebits[FEAT_ST0010]?((SNES_ADDR[22:19] == 4'b1101) & &(~SNES_ADDR[15:12]) & SNES_ADDR[11])
// for HiROM, ExtHIROM or interleaved StarOcean -> $3X:[$6000-$7FFF] or $BX:[$6000-$7FFF]
:((MAPPER == 3'b000 || MAPPER == 3'b010 || MAPPER == 3'b110) ? (!SNES_ADDR[22] & SNES_ADDR[21] & &SNES_ADDR[14:13] & !SNES_ADDR[15])
// for ExtLoROM -> $7X:[$6000-$7FFF]
:(MAPPER == 3'b100) ? ((SNES_ADDR[23:19] == 5'b01110) && (SNES_ADDR[15:13] == 3'b011))
// LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xff
// Offset 0000-7fff for ROM >= 32 MBit, otherwise 0000-ffff
:(MAPPER == 3'b001)? (&SNES_ADDR[22:20] & (~SNES_ROMSEL) & (~SNES_ADDR[15] | ~ROM_MASK[21]))
// BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff
:(MAPPER == 3'b011) ? ((SNES_ADDR[23:19] == 5'b00010) & (SNES_ADDR[15:12] == 4'b0101) )
// Menu mapper: 8Mbit "SRAM" @ Bank 0xf0-0xff (entire banks!)
:(MAPPER == 3'b111) ? (&SNES_ADDR[23:20])
: 1'b0));
// '1' to signal access to cartrigde writable range (Backup RAM or BS-X RAM)
assign IS_WRITABLE = IS_SAVERAM;
/* BSX regs:
Index Function
1 0=map flash to ROM area; 1=map PRAM to ROM area
2 1=HiROM; 0=LoROM
3 1=Mirror PRAM @60-6f:0000-ffff
5 1=DO NOT mirror PRAM @40-4f:0000-ffff
6 1=DO NOT mirror PRAM @50-5f:0000-ffff
7 1=map BSX cartridge ROM @00-1f:8000-ffff
8 1=map BSX cartridge ROM @80-9f:8000-ffff
*/
// HiROM
assign SRAM_SNES_ADDR = ((MAPPER == 3'b000) ? (IS_SAVERAM ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]} & SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
// LoROM
:(MAPPER == 3'b001) ? (IS_SAVERAM ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[14:0]} & SAVERAM_MASK)
: ({1'b0, ~SNES_ADDR[23], SNES_ADDR[22:16], SNES_ADDR[14:0]} & ROM_MASK))
// ExtHiROM
:(MAPPER == 3'b010) ? (IS_SAVERAM ? 24'hE00000 + ({7'b0000000, SNES_ADDR[19:16], SNES_ADDR[12:0]} & SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK))
// ExtLoROM
:(MAPPER == 3'b100) ? (IS_SAVERAM ? 24'hE00000 + ({7'b0000000, SNES_ADDR[19:16], SNES_ADDR[12:0]} & SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK))
// interleaved StarOcean
:(MAPPER == 3'b110) ? (IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
:(SNES_ADDR[15] ? ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
:({2'b10, SNES_ADDR[23], SNES_ADDR[21:16], SNES_ADDR[14:0]}) ) )
// menu
:(MAPPER == 3'b111) ? (IS_SAVERAM ? SNES_ADDR
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK) + 24'hC00000) )
: 24'b0);
assign ROM_ADDR = SRAM_SNES_ADDR;
// '1' when accesing PSRAM for ROM, Backup RAM, BS-X RAM
assign ROM_HIT = IS_ROM | IS_WRITABLE;
// '1' when accessing to MSU register map $2000:$2007
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
// MAGNO -> disabled for S-DD1 core
//assign use_bsx = (MAPPER == 3'b011);
assign use_bsx = 1'b0;
// MAGNO -> disabled for S-DD1 core
//assign srtc_enable = featurebits[FEAT_SRTC] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
assign srtc_enable = 1'b0;
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A6C);
assign branch1_enable = (SNES_ADDR == 24'h002A1F);
assign branch2_enable = (SNES_ADDR == 24'h002A59);
assign branch3_enable = (SNES_ADDR == 24'h002A5E);
endmodule
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